| 1 | Couple of last-minute things for rc3... | 1 | Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code. |
|---|---|---|---|
| 2 | 2 | ||
| 3 | -- PMM | 3 | -- PMM |
| 4 | 4 | ||
| 5 | The following changes since commit d15532d91be177e7528310e0110e39f915779a99: | 5 | The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236: |
| 6 | 6 | ||
| 7 | Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20200804' into staging (2020-08-04 11:53:20 +0100) | 7 | Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700) |
| 8 | 8 | ||
| 9 | are available in the Git repository at: | 9 | are available in the Git repository at: |
| 10 | 10 | ||
| 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200804 | 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801 |
| 12 | 12 | ||
| 13 | for you to fetch changes up to d250bb19ced3b702c7c37731855f6876d0cc7995: | 13 | for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc: |
| 14 | 14 | ||
| 15 | target/arm: Fix decode of LDRA[AB] instructions (2020-08-04 16:40:19 +0100) | 15 | target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100) |
| 16 | 16 | ||
| 17 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
| 18 | target-arm queue: | 18 | target-arm queue: |
| 19 | * Fix decode of LDRA[AB] instructions | 19 | * Fix KVM SVE ID register probe code |
| 20 | * docs/devel: Document decodetree no-overlap groups | ||
| 21 | 20 | ||
| 22 | ---------------------------------------------------------------- | 21 | ---------------------------------------------------------------- |
| 23 | Peter Collingbourne (1): | 22 | Richard Henderson (3): |
| 24 | target/arm: Fix decode of LDRA[AB] instructions | 23 | target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features |
| 24 | target/arm: Set KVM_ARM_VCPU_SVE while probing the host | ||
| 25 | target/arm: Move sve probe inside kvm >= 4.15 branch | ||
| 25 | 26 | ||
| 26 | Richard Henderson (1): | 27 | target/arm/kvm64.c | 45 ++++++++++++++++++++++----------------------- |
| 27 | docs/devel: Document decodetree no-overlap groups | 28 | 1 file changed, 22 insertions(+), 23 deletions(-) |
| 28 | |||
| 29 | docs/devel/decodetree.rst | 29 ++++++++++++++++++----------- | ||
| 30 | target/arm/translate-a64.c | 6 ++++-- | ||
| 31 | 2 files changed, 22 insertions(+), 13 deletions(-) | ||
| 32 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 1 | 2 | ||
| 3 | Indication for support for SVE will not depend on whether we | ||
| 4 | perform the query on the main kvm_state or the temp vcpu. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-2-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 2 +- | ||
| 12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | } | ||
| 20 | } | ||
| 21 | |||
| 22 | - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; | ||
| 23 | + sve_supported = kvm_arm_sve_supported(); | ||
| 24 | |||
| 25 | /* Add feature bits that can't appear until after VCPU init. */ | ||
| 26 | if (sve_supported) { | ||
| 27 | -- | ||
| 28 | 2.25.1 | diff view generated by jsdifflib |
| 1 | From: Peter Collingbourne <pcc@google.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | These instructions use zero as the discriminator, not SP. | 3 | Because we weren't setting this flag, our probe of ID_AA64ZFR0 |
| 4 | was always returning zero. This also obviates the adjustment | ||
| 5 | of ID_AA64PFR0, which had sanitized the SVE field. | ||
| 4 | 6 | ||
| 5 | Signed-off-by: Peter Collingbourne <pcc@google.com> | 7 | The effects of the bug are not visible, because the only thing that |
| 6 | Message-id: 20200804002849.30268-1-pcc@google.com | 8 | ID_AA64ZFR0 is used for within qemu at present is tcg translation. |
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | The other tests for SVE within KVM are via ID_AA64PFR0.SVE. |
| 10 | |||
| 11 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
| 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | Message-id: 20220726045828.53697-3-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | --- | 16 | --- |
| 11 | target/arm/translate-a64.c | 6 ++++-- | 17 | target/arm/kvm64.c | 27 +++++++++++++-------------- |
| 12 | 1 file changed, 4 insertions(+), 2 deletions(-) | 18 | 1 file changed, 13 insertions(+), 14 deletions(-) |
| 13 | 19 | ||
| 14 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 20 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c |
| 15 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/target/arm/translate-a64.c | 22 | --- a/target/arm/kvm64.c |
| 17 | +++ b/target/arm/translate-a64.c | 23 | +++ b/target/arm/kvm64.c |
| 18 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, | 24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
| 19 | 25 | bool sve_supported; | |
| 20 | if (s->pauth_active) { | 26 | bool pmu_supported = false; |
| 21 | if (use_key_a) { | 27 | uint64_t features = 0; |
| 22 | - gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); | 28 | - uint64_t t; |
| 23 | + gen_helper_autda(dirty_addr, cpu_env, dirty_addr, | 29 | int err; |
| 24 | + new_tmp_a64_zero(s)); | 30 | |
| 25 | } else { | 31 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however |
| 26 | - gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); | 32 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
| 27 | + gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, | 33 | struct kvm_vcpu_init init = { .target = -1, }; |
| 28 | + new_tmp_a64_zero(s)); | 34 | |
| 35 | /* | ||
| 36 | - * Ask for Pointer Authentication if supported. We can't play the | ||
| 37 | - * SVE trick of synthesising the ID reg as KVM won't tell us | ||
| 38 | - * whether we have the architected or IMPDEF version of PAuth, so | ||
| 39 | - * we have to use the actual ID regs. | ||
| 40 | + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, | ||
| 41 | + * which is otherwise RAZ. | ||
| 42 | + */ | ||
| 43 | + sve_supported = kvm_arm_sve_supported(); | ||
| 44 | + if (sve_supported) { | ||
| 45 | + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; | ||
| 46 | + } | ||
| 47 | + | ||
| 48 | + /* | ||
| 49 | + * Ask for Pointer Authentication if supported, so that we get | ||
| 50 | + * the unsanitized field values for AA64ISAR1_EL1. | ||
| 51 | */ | ||
| 52 | if (kvm_arm_pauth_supported()) { | ||
| 53 | init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | | ||
| 54 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 29 | } | 55 | } |
| 30 | } | 56 | } |
| 31 | 57 | ||
| 58 | - sve_supported = kvm_arm_sve_supported(); | ||
| 59 | - | ||
| 60 | - /* Add feature bits that can't appear until after VCPU init. */ | ||
| 61 | if (sve_supported) { | ||
| 62 | - t = ahcf->isar.id_aa64pfr0; | ||
| 63 | - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
| 64 | - ahcf->isar.id_aa64pfr0 = t; | ||
| 65 | - | ||
| 66 | /* | ||
| 67 | * There is a range of kernels between kernel commit 73433762fcae | ||
| 68 | * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 69 | * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 70 | - * SVE support, so we only read it here, rather than together with all | ||
| 71 | - * the other ID registers earlier. | ||
| 72 | + * SVE support, which resulted in an error rather than RAZ. | ||
| 73 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 74 | */ | ||
| 75 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 76 | ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 32 | -- | 77 | -- |
| 33 | 2.20.1 | 78 | 2.25.1 |
| 34 | |||
| 35 | diff view generated by jsdifflib |
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | When support for this feature went in, the update to the | 3 | The test for the IF block indicates no ID registers are exposed, much |
| 4 | documentation was forgotten. | 4 | less host support for SVE. Move the SVE probe into the ELSE block. |
| 5 | 5 | ||
| 6 | Fixes: 067e8b0f45d6 | ||
| 7 | Reported-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 7 | Message-id: 20220726045828.53697-4-richard.henderson@linaro.org | ||
| 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | Message-id: 20200803205708.315829-1-richard.henderson@linaro.org | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 12 | --- | 10 | --- |
| 13 | docs/devel/decodetree.rst | 29 ++++++++++++++++++----------- | 11 | target/arm/kvm64.c | 22 +++++++++++----------- |
| 14 | 1 file changed, 18 insertions(+), 11 deletions(-) | 12 | 1 file changed, 11 insertions(+), 11 deletions(-) |
| 15 | 13 | ||
| 16 | diff --git a/docs/devel/decodetree.rst b/docs/devel/decodetree.rst | 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c |
| 17 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/docs/devel/decodetree.rst | 16 | --- a/target/arm/kvm64.c |
| 19 | +++ b/docs/devel/decodetree.rst | 17 | +++ b/target/arm/kvm64.c |
| 20 | @@ -XXX,XX +XXX,XX @@ Pattern Groups | 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
| 21 | 19 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, | |
| 22 | Syntax:: | 20 | ARM64_SYS_REG(3, 3, 9, 12, 0)); |
| 23 | 21 | } | |
| 24 | - group := '{' ( pat_def | group )+ '}' | 22 | - } |
| 25 | + group := overlap_group | no_overlap_group | 23 | |
| 26 | + overlap_group := '{' ( pat_def | group )+ '}' | 24 | - if (sve_supported) { |
| 27 | + no_overlap_group := '[' ( pat_def | group )+ ']' | 25 | - /* |
| 28 | 26 | - * There is a range of kernels between kernel commit 73433762fcae | |
| 29 | -A *group* begins with a lone open-brace, with all subsequent lines | 27 | - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose |
| 30 | -indented two spaces, and ending with a lone close-brace. Groups | 28 | - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled |
| 31 | -may be nested, increasing the required indentation of the lines | 29 | - * SVE support, which resulted in an error rather than RAZ. |
| 32 | -within the nested group to two spaces per nesting level. | 30 | - * So only read the register if we set KVM_ARM_VCPU_SVE above. |
| 33 | +A *group* begins with a lone open-brace or open-bracket, with all | 31 | - */ |
| 34 | +subsequent lines indented two spaces, and ending with a lone | 32 | - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, |
| 35 | +close-brace or close-bracket. Groups may be nested, increasing the | 33 | - ARM64_SYS_REG(3, 0, 0, 4, 4)); |
| 36 | +required indentation of the lines within the nested group to two | 34 | + if (sve_supported) { |
| 37 | +spaces per nesting level. | 35 | + /* |
| 38 | 36 | + * There is a range of kernels between kernel commit 73433762fcae | |
| 39 | -Unlike ungrouped patterns, grouped patterns are allowed to overlap. | 37 | + * and f81cb2c3ad41 which have a bug where the kernel doesn't |
| 40 | -Conflicts are resolved by selecting the patterns in order. If all | 38 | + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has |
| 41 | -of the fixedbits for a pattern match, its translate function will | 39 | + * enabled SVE support, which resulted in an error rather than RAZ. |
| 42 | -be called. If the translate function returns false, then subsequent | 40 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. |
| 43 | -patterns within the group will be matched. | 41 | + */ |
| 44 | +Patterns within overlap groups are allowed to overlap. Conflicts are | 42 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, |
| 45 | +resolved by selecting the patterns in order. If all of the fixedbits | 43 | + ARM64_SYS_REG(3, 0, 0, 4, 4)); |
| 46 | +for a pattern match, its translate function will be called. If the | 44 | + } |
| 47 | +translate function returns false, then subsequent patterns within the | 45 | } |
| 48 | +group will be matched. | 46 | |
| 49 | + | 47 | kvm_arm_destroy_scratch_host_vcpu(fdarray); |
| 50 | +Patterns within no-overlap groups are not allowed to overlap, just | ||
| 51 | +the same as ungrouped patterns. Thus no-overlap groups are intended | ||
| 52 | +to be nested inside overlap groups. | ||
| 53 | |||
| 54 | The following example from PA-RISC shows specialization of the *or* | ||
| 55 | instruction:: | ||
| 56 | @@ -XXX,XX +XXX,XX @@ instruction:: | ||
| 57 | When the *cf* field is zero, the instruction has no side effects, | ||
| 58 | and may be specialized. When the *rt* field is zero, the output | ||
| 59 | is discarded and so the instruction has no effect. When the *rt2* | ||
| 60 | -field is zero, the operation is ``reg[rt] | 0`` and so encodes | ||
| 61 | +field is zero, the operation is ``reg[r1] | 0`` and so encodes | ||
| 62 | the canonical register copy operation. | ||
| 63 | |||
| 64 | The output from the generator might look like:: | ||
| 65 | -- | 48 | -- |
| 66 | 2.20.1 | 49 | 2.25.1 |
| 67 | |||
| 68 | diff view generated by jsdifflib |