[PULL 0/2] target-arm queue
[PULL v2 00/57] target-arm queue
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Couple of last-minute things for rc3...
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Squashed in a trivial fix for 32-bit hosts:
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--- a/target/arm/mve_helper.c
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+++ b/target/arm/mve_helper.c
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@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
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acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
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m[H##ESIZE(e)])); \
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} \
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- acc = int128_add(acc, 1 << 7); \
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+ acc = int128_add(acc, int128_make64(1 << 7)); \
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} \
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} \
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mve_advance_vpt(env); \
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-- PMM
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-- PMM
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The following changes since commit d15532d91be177e7528310e0110e39f915779a99:
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The following changes since commit 53f306f316549d20c76886903181413d20842423:
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Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20200804' into staging (2020-08-04 11:53:20 +0100)
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Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200804
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
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for you to fetch changes up to d250bb19ced3b702c7c37731855f6876d0cc7995:
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for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
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target/arm: Fix decode of LDRA[AB] instructions (2020-08-04 16:40:19 +0100)
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docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* Fix decode of LDRA[AB] instructions
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* Don't require 'virt' board to be compiled in for ACPI GHES code
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* docs/devel: Document decodetree no-overlap groups
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* docs: Document which architecture extensions we emulate
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* Fix bugs in M-profile FPCXT_NS accesses
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* First slice of MVE patches
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* Implement MTE3
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* docs/system: arm: Add nRF boards description
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----------------------------------------------------------------
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----------------------------------------------------------------
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Alexandre Iooss (1):
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docs/system: arm: Add nRF boards description
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Peter Collingbourne (1):
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Peter Collingbourne (1):
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target/arm: Fix decode of LDRA[AB] instructions
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target/arm: Implement MTE3
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Richard Henderson (1):
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Peter Maydell (55):
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docs/devel: Document decodetree no-overlap groups
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hw/acpi: Provide stub version of acpi_ghes_record_errors()
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hw/acpi: Provide function acpi_ghes_present()
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target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
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docs/system/arm: Document which architecture extensions we emulate
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target/arm/translate-vfp.c: Whitespace fixes
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target/arm: Handle FPU being disabled in FPCXT_NS accesses
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target/arm: Don't NOCP fault for FPCXT_NS accesses
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target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
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target/arm: Factor FP context update code out into helper function
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target/arm: Split vfp_access_check() into A and M versions
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target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
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target/arm: Implement MVE VLDR/VSTR (non-widening forms)
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target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
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target/arm: Implement MVE VCLZ
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target/arm: Implement MVE VCLS
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target/arm: Implement MVE VREV16, VREV32, VREV64
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target/arm: Implement MVE VMVN (register)
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target/arm: Implement MVE VABS
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target/arm: Implement MVE VNEG
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tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
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target/arm: Implement MVE VDUP
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target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
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target/arm: Implement MVE VADD, VSUB, VMUL
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target/arm: Implement MVE VMULH
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target/arm: Implement MVE VRMULH
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target/arm: Implement MVE VMAX, VMIN
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target/arm: Implement MVE VABD
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target/arm: Implement MVE VHADD, VHSUB
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target/arm: Implement MVE VMULL
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target/arm: Implement MVE VMLALDAV
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target/arm: Implement MVE VMLSLDAV
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target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
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target/arm: Implement MVE VADD (scalar)
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target/arm: Implement MVE VSUB, VMUL (scalar)
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target/arm: Implement MVE VHADD, VHSUB (scalar)
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target/arm: Implement MVE VBRSR
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target/arm: Implement MVE VPST
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target/arm: Implement MVE VQADD and VQSUB
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target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
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target/arm: Implement MVE VQDMULL scalar
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target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
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target/arm: Implement MVE VQADD, VQSUB (vector)
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target/arm: Implement MVE VQSHL (vector)
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target/arm: Implement MVE VQRSHL
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target/arm: Implement MVE VSHL insn
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target/arm: Implement MVE VRSHL
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target/arm: Implement MVE VQDMLADH and VQRDMLADH
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target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
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target/arm: Implement MVE VQDMULL (vector)
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target/arm: Implement MVE VRHADD
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target/arm: Implement MVE VADC, VSBC
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target/arm: Implement MVE VCADD
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target/arm: Implement MVE VHCADD
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target/arm: Implement MVE VADDV
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target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
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docs/devel/decodetree.rst | 29 ++++++++++++++++++-----------
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docs/system/arm/emulation.rst | 103 ++++
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target/arm/translate-a64.c | 6 ++++--
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docs/system/arm/nrf.rst | 51 ++
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2 files changed, 22 insertions(+), 13 deletions(-)
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docs/system/target-arm.rst | 7 +
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include/hw/acpi/ghes.h | 9 +
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include/tcg/tcg-op.h | 8 +
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include/tcg/tcg.h | 1 -
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target/arm/helper-mve.h | 357 +++++++++++++
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target/arm/helper.h | 2 +
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target/arm/internals.h | 11 +
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target/arm/translate-a32.h | 3 +
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target/arm/translate.h | 10 +
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target/arm/m-nocp.decode | 24 +
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target/arm/mve.decode | 240 +++++++++
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target/arm/vfp.decode | 14 -
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hw/acpi/ghes-stub.c | 22 +
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hw/acpi/ghes.c | 17 +
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target/arm/cpu64.c | 2 +-
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target/arm/kvm64.c | 6 +-
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target/arm/mte_helper.c | 82 +--
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target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
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target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
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target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
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target/arm/translate-vfp.c | 741 +++++++-------------------
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tcg/tcg-op-gvec.c | 20 +-
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MAINTAINERS | 1 +
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hw/acpi/meson.build | 6 +-
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target/arm/meson.build | 1 +
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27 files changed, 3578 insertions(+), 629 deletions(-)
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create mode 100644 docs/system/arm/emulation.rst
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create mode 100644 docs/system/arm/nrf.rst
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create mode 100644 target/arm/helper-mve.h
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create mode 100644 hw/acpi/ghes-stub.c
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create mode 100644 target/arm/mve_helper.c
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diff view generated by jsdifflib
[PULL 1/2] docs/devel: Document decodetree no-overlap groups
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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1
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When support for this feature went in, the update to the
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documentation was forgotten.
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Fixes: 067e8b0f45d6
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20200803205708.315829-1-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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docs/devel/decodetree.rst | 29 ++++++++++++++++++-----------
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1 file changed, 18 insertions(+), 11 deletions(-)
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diff --git a/docs/devel/decodetree.rst b/docs/devel/decodetree.rst
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index XXXXXXX..XXXXXXX 100644
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--- a/docs/devel/decodetree.rst
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+++ b/docs/devel/decodetree.rst
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@@ -XXX,XX +XXX,XX @@ Pattern Groups
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Syntax::
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- group := '{' ( pat_def | group )+ '}'
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+ group := overlap_group | no_overlap_group
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+ overlap_group := '{' ( pat_def | group )+ '}'
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+ no_overlap_group := '[' ( pat_def | group )+ ']'
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-A *group* begins with a lone open-brace, with all subsequent lines
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-indented two spaces, and ending with a lone close-brace. Groups
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-may be nested, increasing the required indentation of the lines
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-within the nested group to two spaces per nesting level.
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+A *group* begins with a lone open-brace or open-bracket, with all
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+subsequent lines indented two spaces, and ending with a lone
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+close-brace or close-bracket. Groups may be nested, increasing the
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+required indentation of the lines within the nested group to two
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+spaces per nesting level.
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-Unlike ungrouped patterns, grouped patterns are allowed to overlap.
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-Conflicts are resolved by selecting the patterns in order. If all
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-of the fixedbits for a pattern match, its translate function will
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-be called. If the translate function returns false, then subsequent
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-patterns within the group will be matched.
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+Patterns within overlap groups are allowed to overlap. Conflicts are
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+resolved by selecting the patterns in order. If all of the fixedbits
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+for a pattern match, its translate function will be called. If the
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+translate function returns false, then subsequent patterns within the
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+group will be matched.
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+
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+Patterns within no-overlap groups are not allowed to overlap, just
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+the same as ungrouped patterns. Thus no-overlap groups are intended
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+to be nested inside overlap groups.
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The following example from PA-RISC shows specialization of the *or*
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instruction::
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@@ -XXX,XX +XXX,XX @@ instruction::
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When the *cf* field is zero, the instruction has no side effects,
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and may be specialized. When the *rt* field is zero, the output
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is discarded and so the instruction has no effect. When the *rt2*
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-field is zero, the operation is ``reg[rt] | 0`` and so encodes
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+field is zero, the operation is ``reg[r1] | 0`` and so encodes
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the canonical register copy operation.
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The output from the generator might look like::
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--
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2.20.1
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diff view generated by jsdifflib
[PULL 2/2] target/arm: Fix decode of LDRA[AB] instructions
Deleted patch
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From: Peter Collingbourne <pcc@google.com>
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1
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These instructions use zero as the discriminator, not SP.
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Signed-off-by: Peter Collingbourne <pcc@google.com>
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Message-id: 20200804002849.30268-1-pcc@google.com
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/translate-a64.c | 6 ++++--
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1 file changed, 4 insertions(+), 2 deletions(-)
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diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/translate-a64.c
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+++ b/target/arm/translate-a64.c
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@@ -XXX,XX +XXX,XX @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn,
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if (s->pauth_active) {
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if (use_key_a) {
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- gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]);
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+ gen_helper_autda(dirty_addr, cpu_env, dirty_addr,
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+ new_tmp_a64_zero(s));
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} else {
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- gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]);
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+ gen_helper_autdb(dirty_addr, cpu_env, dirty_addr,
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+ new_tmp_a64_zero(s));
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}
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}
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--
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2.20.1
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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