| 1 | Couple of last-minute things for rc3... | 1 | Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx |
|---|---|---|---|
| 2 | ethernet device failed 'make check' on big-endian hosts. | ||
| 2 | 3 | ||
| 3 | -- PMM | 4 | -- PMM |
| 4 | 5 | ||
| 5 | The following changes since commit d15532d91be177e7528310e0110e39f915779a99: | 6 | The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf: |
| 6 | 7 | ||
| 7 | Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20200804' into staging (2020-08-04 11:53:20 +0100) | 8 | Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000) |
| 8 | 9 | ||
| 9 | are available in the Git repository at: | 10 | are available in the Git repository at: |
| 10 | 11 | ||
| 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200804 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1 |
| 12 | 13 | ||
| 13 | for you to fetch changes up to d250bb19ced3b702c7c37731855f6876d0cc7995: | 14 | for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621: |
| 14 | 15 | ||
| 15 | target/arm: Fix decode of LDRA[AB] instructions (2020-08-04 16:40:19 +0100) | 16 | target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000) |
| 16 | 17 | ||
| 17 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
| 18 | target-arm queue: | 19 | target-arm queue: |
| 19 | * Fix decode of LDRA[AB] instructions | 20 | * Correctly initialize MDCR_EL2.HPMN |
| 20 | * docs/devel: Document decodetree no-overlap groups | 21 | * versal: Use nr_apu_cpus in favor of hard coding 2 |
| 22 | * accel/tcg: Add URL of clang bug to comment about our workaround | ||
| 23 | * Add support for FEAT_DIT, Data Independent Timing | ||
| 24 | * Remove GPIO from unimplemented NPCM7XX | ||
| 25 | * Fix SCR RES1 handling | ||
| 26 | * Don't migrate CPUARMState.features | ||
| 21 | 27 | ||
| 22 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
| 23 | Peter Collingbourne (1): | 29 | Aaron Lindsay (1): |
| 24 | target/arm: Fix decode of LDRA[AB] instructions | 30 | target/arm: Don't migrate CPUARMState.features |
| 25 | 31 | ||
| 26 | Richard Henderson (1): | 32 | Daniel Müller (1): |
| 27 | docs/devel: Document decodetree no-overlap groups | 33 | target/arm: Correctly initialize MDCR_EL2.HPMN |
| 28 | 34 | ||
| 29 | docs/devel/decodetree.rst | 29 ++++++++++++++++++----------- | 35 | Edgar E. Iglesias (1): |
| 30 | target/arm/translate-a64.c | 6 ++++-- | 36 | hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2 |
| 31 | 2 files changed, 22 insertions(+), 13 deletions(-) | ||
| 32 | 37 | ||
| 38 | Hao Wu (1): | ||
| 39 | hw/arm: Remove GPIO from unimplemented NPCM7XX | ||
| 40 | |||
| 41 | Mike Nawrocki (1): | ||
| 42 | target/arm: Fix SCR RES1 handling | ||
| 43 | |||
| 44 | Peter Maydell (2): | ||
| 45 | arm: Update infocenter.arm.com URLs | ||
| 46 | accel/tcg: Add URL of clang bug to comment about our workaround | ||
| 47 | |||
| 48 | Rebecca Cran (4): | ||
| 49 | target/arm: Add support for FEAT_DIT, Data Independent Timing | ||
| 50 | target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate | ||
| 51 | target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU | ||
| 52 | target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU | ||
| 53 | |||
| 54 | include/hw/dma/pl080.h | 7 ++-- | ||
| 55 | include/hw/misc/arm_integrator_debug.h | 2 +- | ||
| 56 | include/hw/ssi/pl022.h | 5 ++- | ||
| 57 | target/arm/cpu.h | 17 ++++++++ | ||
| 58 | target/arm/internals.h | 6 +++ | ||
| 59 | accel/tcg/cpu-exec.c | 25 +++++++++--- | ||
| 60 | hw/arm/aspeed_ast2600.c | 2 +- | ||
| 61 | hw/arm/musca.c | 4 +- | ||
| 62 | hw/arm/npcm7xx.c | 8 ---- | ||
| 63 | hw/arm/xlnx-versal.c | 4 +- | ||
| 64 | hw/misc/arm_integrator_debug.c | 2 +- | ||
| 65 | hw/timer/arm_timer.c | 7 ++-- | ||
| 66 | target/arm/cpu.c | 4 ++ | ||
| 67 | target/arm/cpu64.c | 5 +++ | ||
| 68 | target/arm/helper-a64.c | 27 +++++++++++-- | ||
| 69 | target/arm/helper.c | 71 +++++++++++++++++++++++++++------- | ||
| 70 | target/arm/machine.c | 2 +- | ||
| 71 | target/arm/op_helper.c | 9 +---- | ||
| 72 | target/arm/translate-a64.c | 12 ++++++ | ||
| 73 | 19 files changed, 164 insertions(+), 55 deletions(-) | ||
| 74 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | When support for this feature went in, the update to the | ||
| 4 | documentation was forgotten. | ||
| 5 | |||
| 6 | Fixes: 067e8b0f45d6 | ||
| 7 | Reported-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | Message-id: 20200803205708.315829-1-richard.henderson@linaro.org | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 12 | --- | ||
| 13 | docs/devel/decodetree.rst | 29 ++++++++++++++++++----------- | ||
| 14 | 1 file changed, 18 insertions(+), 11 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/docs/devel/decodetree.rst b/docs/devel/decodetree.rst | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/docs/devel/decodetree.rst | ||
| 19 | +++ b/docs/devel/decodetree.rst | ||
| 20 | @@ -XXX,XX +XXX,XX @@ Pattern Groups | ||
| 21 | |||
| 22 | Syntax:: | ||
| 23 | |||
| 24 | - group := '{' ( pat_def | group )+ '}' | ||
| 25 | + group := overlap_group | no_overlap_group | ||
| 26 | + overlap_group := '{' ( pat_def | group )+ '}' | ||
| 27 | + no_overlap_group := '[' ( pat_def | group )+ ']' | ||
| 28 | |||
| 29 | -A *group* begins with a lone open-brace, with all subsequent lines | ||
| 30 | -indented two spaces, and ending with a lone close-brace. Groups | ||
| 31 | -may be nested, increasing the required indentation of the lines | ||
| 32 | -within the nested group to two spaces per nesting level. | ||
| 33 | +A *group* begins with a lone open-brace or open-bracket, with all | ||
| 34 | +subsequent lines indented two spaces, and ending with a lone | ||
| 35 | +close-brace or close-bracket. Groups may be nested, increasing the | ||
| 36 | +required indentation of the lines within the nested group to two | ||
| 37 | +spaces per nesting level. | ||
| 38 | |||
| 39 | -Unlike ungrouped patterns, grouped patterns are allowed to overlap. | ||
| 40 | -Conflicts are resolved by selecting the patterns in order. If all | ||
| 41 | -of the fixedbits for a pattern match, its translate function will | ||
| 42 | -be called. If the translate function returns false, then subsequent | ||
| 43 | -patterns within the group will be matched. | ||
| 44 | +Patterns within overlap groups are allowed to overlap. Conflicts are | ||
| 45 | +resolved by selecting the patterns in order. If all of the fixedbits | ||
| 46 | +for a pattern match, its translate function will be called. If the | ||
| 47 | +translate function returns false, then subsequent patterns within the | ||
| 48 | +group will be matched. | ||
| 49 | + | ||
| 50 | +Patterns within no-overlap groups are not allowed to overlap, just | ||
| 51 | +the same as ungrouped patterns. Thus no-overlap groups are intended | ||
| 52 | +to be nested inside overlap groups. | ||
| 53 | |||
| 54 | The following example from PA-RISC shows specialization of the *or* | ||
| 55 | instruction:: | ||
| 56 | @@ -XXX,XX +XXX,XX @@ instruction:: | ||
| 57 | When the *cf* field is zero, the instruction has no side effects, | ||
| 58 | and may be specialized. When the *rt* field is zero, the output | ||
| 59 | is discarded and so the instruction has no effect. When the *rt2* | ||
| 60 | -field is zero, the operation is ``reg[rt] | 0`` and so encodes | ||
| 61 | +field is zero, the operation is ``reg[r1] | 0`` and so encodes | ||
| 62 | the canonical register copy operation. | ||
| 63 | |||
| 64 | The output from the generator might look like:: | ||
| 65 | -- | ||
| 66 | 2.20.1 | ||
| 67 | |||
| 68 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Peter Collingbourne <pcc@google.com> | ||
| 2 | 1 | ||
| 3 | These instructions use zero as the discriminator, not SP. | ||
| 4 | |||
| 5 | Signed-off-by: Peter Collingbourne <pcc@google.com> | ||
| 6 | Message-id: 20200804002849.30268-1-pcc@google.com | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/translate-a64.c | 6 ++++-- | ||
| 12 | 1 file changed, 4 insertions(+), 2 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/translate-a64.c | ||
| 17 | +++ b/target/arm/translate-a64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, | ||
| 19 | |||
| 20 | if (s->pauth_active) { | ||
| 21 | if (use_key_a) { | ||
| 22 | - gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); | ||
| 23 | + gen_helper_autda(dirty_addr, cpu_env, dirty_addr, | ||
| 24 | + new_tmp_a64_zero(s)); | ||
| 25 | } else { | ||
| 26 | - gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); | ||
| 27 | + gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, | ||
| 28 | + new_tmp_a64_zero(s)); | ||
| 29 | } | ||
| 30 | } | ||
| 31 | |||
| 32 | -- | ||
| 33 | 2.20.1 | ||
| 34 | |||
| 35 | diff view generated by jsdifflib |