| 1 | Handful of bugfixes for rc2. None of these are particularly critical | 1 | This one's almost all docs fixes. |
|---|---|---|---|
| 2 | or exciting. | ||
| 3 | 2 | ||
| 3 | thanks | ||
| 4 | -- PMM | 4 | -- PMM |
| 5 | 5 | ||
| 6 | The following changes since commit 45a150aa2b3492acf6691c7bdbeb25a8545d8345: | 6 | The following changes since commit ba54a7e6b86884e43bed2d2f5a79c719059652a8: |
| 7 | 7 | ||
| 8 | Merge remote-tracking branch 'remotes/ericb/tags/pull-bitmaps-2020-08-03' into staging (2020-08-03 15:13:49 +0100) | 8 | Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2024-11-26 14:06:40 +0000) |
| 9 | 9 | ||
| 10 | are available in the Git repository at: | 10 | are available in the Git repository at: |
| 11 | 11 | ||
| 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200803 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241126 |
| 13 | 13 | ||
| 14 | for you to fetch changes up to 13557fd392890cbd985bceba7f717e01efd674b8: | 14 | for you to fetch changes up to d8790ead55a2ef1e65332ebec63ae3c5db598942: |
| 15 | 15 | ||
| 16 | hw/timer/imx_epit: Avoid assertion when CR.SWR is written (2020-08-03 17:56:11 +0100) | 16 | docs/system/arm/aspeed: add missing model supermicrox11spi-bmc (2024-11-26 16:22:38 +0000) |
| 17 | 17 | ||
| 18 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
| 19 | target-arm queue: | 19 | target-arm queue: |
| 20 | * hw/timer/imx_epit: Avoid assertion when CR.SWR is written | 20 | * target/arm/tcg/cpu32.c: swap ATCM and BTCM register names |
| 21 | * netduino2, netduinoplus2, microbit: set system_clock_scale so that | 21 | * docs/system/arm: Fix broken links and missing feature names |
| 22 | SysTick running on the CPU clock works | ||
| 23 | * target/arm: Avoid maybe-uninitialized warning with gcc 4.9 | ||
| 24 | * target/arm: Fix AddPAC error indication | ||
| 25 | * Make AIRCR.SYSRESETREQ actually reset the system for the | ||
| 26 | microbit, mps2-*, musca-*, netduino* boards | ||
| 27 | 22 | ||
| 28 | ---------------------------------------------------------------- | 23 | ---------------------------------------------------------------- |
| 29 | Kaige Li (1): | 24 | Michael Tokarev (1): |
| 30 | target/arm: Avoid maybe-uninitialized warning with gcc 4.9 | 25 | target/arm/tcg/cpu32.c: swap ATCM and BTCM register names |
| 31 | 26 | ||
| 32 | Peter Maydell (6): | 27 | Pierrick Bouvier (8): |
| 33 | hw/arm/netduino2, netduinoplus2: Set system_clock_scale | 28 | docs/system/arm/emulation: mention armv9 |
| 34 | include/hw/irq.h: New function qemu_irq_is_connected() | 29 | docs/system/arm/emulation: fix typo in feature name |
| 35 | hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for SYSRESETREQ | 30 | docs/system/arm/emulation: add FEAT_SSBS2 |
| 36 | msf2-soc, stellaris: Don't wire up SYSRESETREQ | 31 | target/arm/tcg/: fix typo in FEAT name |
| 37 | hw/arm/nrf51_soc: Set system_clock_scale | 32 | docs/system/arm/: add FEAT_MTE_ASYNC |
| 38 | hw/timer/imx_epit: Avoid assertion when CR.SWR is written | 33 | docs/system/arm/: add FEAT_DoubleLock |
| 34 | docs/system/arm/fby35: update link to product page | ||
| 35 | docs/system/arm/aspeed: add missing model supermicrox11spi-bmc | ||
| 39 | 36 | ||
| 40 | Richard Henderson (1): | 37 | docs/system/arm/aspeed.rst | 7 ++++--- |
| 41 | target/arm: Fix AddPAC error indication | 38 | docs/system/arm/emulation.rst | 11 +++++++---- |
| 42 | 39 | docs/system/arm/fby35.rst | 2 +- | |
| 43 | include/hw/arm/armv7m.h | 4 +++- | 40 | target/arm/tcg/cpu32.c | 6 +++--- |
| 44 | include/hw/irq.h | 18 ++++++++++++++++++ | 41 | 4 files changed, 15 insertions(+), 11 deletions(-) |
| 45 | hw/arm/msf2-soc.c | 11 ----------- | ||
| 46 | hw/arm/netduino2.c | 10 ++++++++++ | ||
| 47 | hw/arm/netduinoplus2.c | 10 ++++++++++ | ||
| 48 | hw/arm/nrf51_soc.c | 5 +++++ | ||
| 49 | hw/arm/stellaris.c | 12 ------------ | ||
| 50 | hw/intc/armv7m_nvic.c | 17 ++++++++++++++++- | ||
| 51 | hw/timer/imx_epit.c | 13 ++++++++++--- | ||
| 52 | target/arm/pauth_helper.c | 6 +++++- | ||
| 53 | target/arm/translate-a64.c | 2 +- | ||
| 54 | tests/tcg/aarch64/pauth-5.c | 33 +++++++++++++++++++++++++++++++++ | ||
| 55 | tests/tcg/aarch64/Makefile.target | 2 +- | ||
| 56 | 13 files changed, 112 insertions(+), 31 deletions(-) | ||
| 57 | create mode 100644 tests/tcg/aarch64/pauth-5.c | ||
| 58 | diff view generated by jsdifflib |
| 1 | The nrf51 SoC model wasn't setting the system_clock_scale | 1 | From: Michael Tokarev <mjt@tls.msk.ru> |
|---|---|---|---|
| 2 | global.which meant that if guest code used the systick timer in "use | ||
| 3 | the processor clock" mode it would hang because time never advances. | ||
| 4 | 2 | ||
| 5 | Set the global to match the documented CPU clock speed for this SoC. | 3 | According to Cortex-R5 r1p2 manual, register with opcode2=0 is |
| 4 | BTCM and with opcode2=1 is ATCM, - exactly the opposite from how | ||
| 5 | qemu labels them. Just swap the labels to avoid confusion, - | ||
| 6 | both registers are implemented as always-zero. | ||
| 6 | 7 | ||
| 7 | This SoC in fact doesn't have a SysTick timer (which is the only thing | 8 | Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> |
| 8 | currently that cares about the system_clock_scale), because it's | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 9 | a configurable option in the Cortex-M0. However our Cortex-M0 and | 10 | Message-id: 20241121171602.3273252-1-mjt@tls.msk.ru |
| 10 | thus our nrf51 and our micro:bit board do provide a SysTick, so | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | we ought to provide a functional one rather than a broken one. | 12 | --- |
| 13 | target/arm/tcg/cpu32.c | 4 ++-- | ||
| 14 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
| 12 | 15 | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c |
| 14 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 15 | Message-id: 20200727193458.31250-1-peter.maydell@linaro.org | ||
| 16 | --- | ||
| 17 | hw/arm/nrf51_soc.c | 5 +++++ | ||
| 18 | 1 file changed, 5 insertions(+) | ||
| 19 | |||
| 20 | diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 22 | --- a/hw/arm/nrf51_soc.c | 18 | --- a/target/arm/tcg/cpu32.c |
| 23 | +++ b/hw/arm/nrf51_soc.c | 19 | +++ b/target/arm/tcg/cpu32.c |
| 24 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj) |
| 25 | 21 | ||
| 26 | #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) | 22 | static const ARMCPRegInfo cortexr5_cp_reginfo[] = { |
| 27 | 23 | /* Dummy the TCM region regs for the moment */ | |
| 28 | +/* HCLK (the main CPU clock) on this SoC is always 16MHz */ | 24 | - { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, |
| 29 | +#define HCLK_FRQ 16000000 | 25 | + { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, |
| 30 | + | 26 | .access = PL1_RW, .type = ARM_CP_CONST }, |
| 31 | static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) | 27 | - { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, |
| 32 | { | 28 | + { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, |
| 33 | qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", | 29 | .access = PL1_RW, .type = ARM_CP_CONST }, |
| 34 | @@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) | 30 | { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, |
| 35 | return; | 31 | .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, |
| 36 | } | ||
| 37 | |||
| 38 | + system_clock_scale = NANOSECONDS_PER_SECOND / HCLK_FRQ; | ||
| 39 | + | ||
| 40 | object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container), | ||
| 41 | &error_abort); | ||
| 42 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) { | ||
| 43 | -- | 32 | -- |
| 44 | 2.20.1 | 33 | 2.34.1 |
| 45 | |||
| 46 | diff view generated by jsdifflib |
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The definition of top_bit used in this function is one higher | 3 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
| 4 | than that used in the Arm ARM psuedo-code, which put the error | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 5 | indication at top_bit - 1 at the wrong place, which meant that | 5 | Message-id: 20241122225049.1617774-2-pierrick.bouvier@linaro.org |
| 6 | it wasn't visible to Auth. | ||
| 7 | |||
| 8 | Fixing the definition of top_bit requires more changes, because | ||
| 9 | its most common use is for the count of bits in top_bit:bot_bit, | ||
| 10 | which would then need to be computed as top_bit - bot_bit + 1. | ||
| 11 | |||
| 12 | For now, prefer the minimal fix to the error indication alone. | ||
| 13 | |||
| 14 | Fixes: 63ff0ca94cb | ||
| 15 | Reported-by: Derrick McKee <derrick.mckee@gmail.com> | ||
| 16 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 17 | Message-id: 20200728195706.11087-1-richard.henderson@linaro.org | ||
| 18 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 19 | [PMM: added comment about the divergence from the pseudocode] | ||
| 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 21 | --- | 7 | --- |
| 22 | target/arm/pauth_helper.c | 6 +++++- | 8 | docs/system/arm/emulation.rst | 6 +++--- |
| 23 | tests/tcg/aarch64/pauth-5.c | 33 +++++++++++++++++++++++++++++++ | 9 | 1 file changed, 3 insertions(+), 3 deletions(-) |
| 24 | tests/tcg/aarch64/Makefile.target | 2 +- | ||
| 25 | 3 files changed, 39 insertions(+), 2 deletions(-) | ||
| 26 | create mode 100644 tests/tcg/aarch64/pauth-5.c | ||
| 27 | 10 | ||
| 28 | diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c | 11 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
| 29 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
| 30 | --- a/target/arm/pauth_helper.c | 13 | --- a/docs/system/arm/emulation.rst |
| 31 | +++ b/target/arm/pauth_helper.c | 14 | +++ b/docs/system/arm/emulation.rst |
| 32 | @@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, | ||
| 33 | */ | ||
| 34 | test = sextract64(ptr, bot_bit, top_bit - bot_bit); | ||
| 35 | if (test != 0 && test != -1) { | ||
| 36 | - pac ^= MAKE_64BIT_MASK(top_bit - 1, 1); | ||
| 37 | + /* | ||
| 38 | + * Note that our top_bit is one greater than the pseudocode's | ||
| 39 | + * version, hence "- 2" here. | ||
| 40 | + */ | ||
| 41 | + pac ^= MAKE_64BIT_MASK(top_bit - 2, 1); | ||
| 42 | } | ||
| 43 | |||
| 44 | /* | ||
| 45 | diff --git a/tests/tcg/aarch64/pauth-5.c b/tests/tcg/aarch64/pauth-5.c | ||
| 46 | new file mode 100644 | ||
| 47 | index XXXXXXX..XXXXXXX | ||
| 48 | --- /dev/null | ||
| 49 | +++ b/tests/tcg/aarch64/pauth-5.c | ||
| 50 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ |
| 51 | +#include <assert.h> | 16 | A-profile CPU architecture support |
| 52 | + | 17 | ================================== |
| 53 | +static int x; | 18 | |
| 54 | + | 19 | -QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7 and |
| 55 | +int main() | 20 | -Armv8 versions of the A-profile architecture. It also has support for |
| 56 | +{ | 21 | +QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7, |
| 57 | + int *p0 = &x, *p1, *p2, *p3; | 22 | +Armv8 and Armv9 versions of the A-profile architecture. It also has support for |
| 58 | + unsigned long salt = 0; | 23 | the following architecture extensions: |
| 59 | + | 24 | |
| 60 | + /* | 25 | - FEAT_AA32BF16 (AArch32 BFloat16 instructions) |
| 61 | + * With TBI enabled and a 48-bit VA, there are 7 bits of auth, and so | 26 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
| 62 | + * a 1/128 chance of auth = pac(ptr,key,salt) producing zero. | 27 | - FEAT_XNX (Translation table stage 2 Unprivileged Execute-never) |
| 63 | + * Find a salt that creates auth != 0. | 28 | |
| 64 | + */ | 29 | For information on the specifics of these extensions, please refer |
| 65 | + do { | 30 | -to the `Armv8-A Arm Architecture Reference Manual |
| 66 | + salt++; | 31 | +to the `Arm Architecture Reference Manual for A-profile architecture |
| 67 | + asm("pacda %0, %1" : "=r"(p1) : "r"(salt), "0"(p0)); | 32 | <https://developer.arm.com/documentation/ddi0487/latest>`_. |
| 68 | + } while (p0 == p1); | 33 | |
| 69 | + | 34 | When a specific named CPU is being emulated, only those features which |
| 70 | + /* | ||
| 71 | + * This pac must fail, because the input pointer bears an encryption, | ||
| 72 | + * and so is not properly extended within bits [55:47]. This will | ||
| 73 | + * toggle bit 54 in the output... | ||
| 74 | + */ | ||
| 75 | + asm("pacda %0, %1" : "=r"(p2) : "r"(salt), "0"(p1)); | ||
| 76 | + | ||
| 77 | + /* ... so that the aut must fail, setting bit 53 in the output ... */ | ||
| 78 | + asm("autda %0, %1" : "=r"(p3) : "r"(salt), "0"(p2)); | ||
| 79 | + | ||
| 80 | + /* ... which means this equality must not hold. */ | ||
| 81 | + assert(p3 != p0); | ||
| 82 | + return 0; | ||
| 83 | +} | ||
| 84 | diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target | ||
| 85 | index XXXXXXX..XXXXXXX 100644 | ||
| 86 | --- a/tests/tcg/aarch64/Makefile.target | ||
| 87 | +++ b/tests/tcg/aarch64/Makefile.target | ||
| 88 | @@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt | ||
| 89 | |||
| 90 | # Pauth Tests | ||
| 91 | ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_3),) | ||
| 92 | -AARCH64_TESTS += pauth-1 pauth-2 pauth-4 | ||
| 93 | +AARCH64_TESTS += pauth-1 pauth-2 pauth-4 pauth-5 | ||
| 94 | pauth-%: CFLAGS += -march=armv8.3-a | ||
| 95 | run-pauth-%: QEMU_OPTS += -cpu max | ||
| 96 | run-plugin-pauth-%: QEMU_OPTS += -cpu max | ||
| 97 | -- | 35 | -- |
| 98 | 2.20.1 | 36 | 2.34.1 |
| 99 | |||
| 100 | diff view generated by jsdifflib |
| 1 | From: Kaige Li <likaige@loongson.cn> | 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | GCC version 4.9.4 isn't clever enough to figure out that all | 3 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
| 4 | execution paths in disas_ldst() that use 'fn' will have initialized | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 5 | it first, and so it warns: | 5 | Message-id: 20241122225049.1617774-3-pierrick.bouvier@linaro.org |
| 6 | |||
| 7 | /home/LiKaige/qemu/target/arm/translate-a64.c: In function ‘disas_ldst’: | ||
| 8 | /home/LiKaige/qemu/target/arm/translate-a64.c:3392:5: error: ‘fn’ may be used uninitialized in this function [-Werror=maybe-uninitialized] | ||
| 9 | fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s), | ||
| 10 | ^ | ||
| 11 | /home/LiKaige/qemu/target/arm/translate-a64.c:3318:22: note: ‘fn’ was declared here | ||
| 12 | AtomicThreeOpFn *fn; | ||
| 13 | ^ | ||
| 14 | |||
| 15 | Make it happy by initializing the variable to NULL. | ||
| 16 | |||
| 17 | Signed-off-by: Kaige Li <likaige@loongson.cn> | ||
| 18 | Message-id: 1596110248-7366-2-git-send-email-likaige@loongson.cn | ||
| 19 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 20 | [PMM: Clean up commit message and note which gcc version this was] | ||
| 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 22 | --- | 7 | --- |
| 23 | target/arm/translate-a64.c | 2 +- | 8 | docs/system/arm/emulation.rst | 2 +- |
| 24 | 1 file changed, 1 insertion(+), 1 deletion(-) | 9 | 1 file changed, 1 insertion(+), 1 deletion(-) |
| 25 | 10 | ||
| 26 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 11 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
| 27 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
| 28 | --- a/target/arm/translate-a64.c | 13 | --- a/docs/system/arm/emulation.rst |
| 29 | +++ b/target/arm/translate-a64.c | 14 | +++ b/docs/system/arm/emulation.rst |
| 30 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | 15 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
| 31 | bool r = extract32(insn, 22, 1); | 16 | - FEAT_LSE2 (Large System Extensions v2) |
| 32 | bool a = extract32(insn, 23, 1); | 17 | - FEAT_LVA (Large Virtual Address space) |
| 33 | TCGv_i64 tcg_rs, clean_addr; | 18 | - FEAT_MixedEnd (Mixed-endian support) |
| 34 | - AtomicThreeOpFn *fn; | 19 | -- FEAT_MixdEndEL0 (Mixed-endian support at EL0) |
| 35 | + AtomicThreeOpFn *fn = NULL; | 20 | +- FEAT_MixedEndEL0 (Mixed-endian support at EL0) |
| 36 | 21 | - FEAT_MOPS (Standardization of memory operations) | |
| 37 | if (is_vector || !dc_isar_feature(aa64_atomics, s)) { | 22 | - FEAT_MTE (Memory Tagging Extension) |
| 38 | unallocated_encoding(s); | 23 | - FEAT_MTE2 (Memory Tagging Extension) |
| 39 | -- | 24 | -- |
| 40 | 2.20.1 | 25 | 2.34.1 |
| 41 | |||
| 42 | diff view generated by jsdifflib |
| 1 | The MSF2 SoC model and the Stellaris board code both wire | 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
|---|---|---|---|
| 2 | SYSRESETREQ up to a function that just invokes | ||
| 3 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | ||
| 4 | This is now the default action that the NVIC does if the line is | ||
| 5 | not connected, so we can delete the handling code. | ||
| 6 | 2 | ||
| 3 | We implemented this at the same times as FEAT_SSBS, but forgot | ||
| 4 | to list it in the documentation. | ||
| 5 | |||
| 6 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20241122225049.1617774-4-pierrick.bouvier@linaro.org | ||
| 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | [PMM: improve commit message] | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | Message-id: 20200728103744.6909-4-peter.maydell@linaro.org | ||
| 11 | --- | 12 | --- |
| 12 | hw/arm/msf2-soc.c | 11 ----------- | 13 | docs/system/arm/emulation.rst | 1 + |
| 13 | hw/arm/stellaris.c | 12 ------------ | 14 | 1 file changed, 1 insertion(+) |
| 14 | 2 files changed, 23 deletions(-) | ||
| 15 | 15 | ||
| 16 | diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c | 16 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
| 17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/hw/arm/msf2-soc.c | 18 | --- a/docs/system/arm/emulation.rst |
| 19 | +++ b/hw/arm/msf2-soc.c | 19 | +++ b/docs/system/arm/emulation.rst |
| 20 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
| 21 | #include "hw/irq.h" | 21 | - FEAT_SVE2 (Scalable Vector Extension version 2) |
| 22 | #include "hw/arm/msf2-soc.h" | 22 | - FEAT_SPECRES (Speculation restriction instructions) |
| 23 | #include "hw/misc/unimp.h" | 23 | - FEAT_SSBS (Speculative Store Bypass Safe) |
| 24 | -#include "sysemu/runstate.h" | 24 | +- FEAT_SSBS2 (MRS and MSR instructions for SSBS version 2) |
| 25 | #include "sysemu/sysemu.h" | 25 | - FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1) |
| 26 | 26 | - FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1) | |
| 27 | #define MSF2_TIMER_BASE 0x40004000 | 27 | - FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1) |
| 28 | @@ -XXX,XX +XXX,XX @@ static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 }; | ||
| 29 | static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 }; | ||
| 30 | static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 }; | ||
| 31 | |||
| 32 | -static void do_sys_reset(void *opaque, int n, int level) | ||
| 33 | -{ | ||
| 34 | - if (level) { | ||
| 35 | - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | ||
| 36 | - } | ||
| 37 | -} | ||
| 38 | - | ||
| 39 | static void m2sxxx_soc_initfn(Object *obj) | ||
| 40 | { | ||
| 41 | MSF2State *s = MSF2_SOC(obj); | ||
| 42 | @@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) | ||
| 43 | return; | ||
| 44 | } | ||
| 45 | |||
| 46 | - qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0, | ||
| 47 | - qemu_allocate_irq(&do_sys_reset, NULL, 0)); | ||
| 48 | - | ||
| 49 | system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk; | ||
| 50 | |||
| 51 | for (i = 0; i < MSF2_NUM_UARTS; i++) { | ||
| 52 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c | ||
| 53 | index XXXXXXX..XXXXXXX 100644 | ||
| 54 | --- a/hw/arm/stellaris.c | ||
| 55 | +++ b/hw/arm/stellaris.c | ||
| 56 | @@ -XXX,XX +XXX,XX @@ | ||
| 57 | #include "hw/boards.h" | ||
| 58 | #include "qemu/log.h" | ||
| 59 | #include "exec/address-spaces.h" | ||
| 60 | -#include "sysemu/runstate.h" | ||
| 61 | #include "sysemu/sysemu.h" | ||
| 62 | #include "hw/arm/armv7m.h" | ||
| 63 | #include "hw/char/pl011.h" | ||
| 64 | @@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj) | ||
| 65 | qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); | ||
| 66 | } | ||
| 67 | |||
| 68 | -static | ||
| 69 | -void do_sys_reset(void *opaque, int n, int level) | ||
| 70 | -{ | ||
| 71 | - if (level) { | ||
| 72 | - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | ||
| 73 | - } | ||
| 74 | -} | ||
| 75 | - | ||
| 76 | /* Board init. */ | ||
| 77 | static stellaris_board_info stellaris_boards[] = { | ||
| 78 | { "LM3S811EVB", | ||
| 79 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | ||
| 80 | /* This will exit with an error if the user passed us a bad cpu_type */ | ||
| 81 | sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); | ||
| 82 | |||
| 83 | - qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, | ||
| 84 | - qemu_allocate_irq(&do_sys_reset, NULL, 0)); | ||
| 85 | - | ||
| 86 | if (board->dc1 & (1 << 16)) { | ||
| 87 | dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, | ||
| 88 | qdev_get_gpio_in(nvic, 14), | ||
| 89 | -- | 28 | -- |
| 90 | 2.20.1 | 29 | 2.34.1 |
| 91 | |||
| 92 | diff view generated by jsdifflib |
| 1 | The NVIC provides an outbound qemu_irq "SYSRESETREQ" which it signals | 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
|---|---|---|---|
| 2 | when the guest sets the SYSRESETREQ bit in the AIRCR register. This | ||
| 3 | matches the hardware design (where the CPU has a signal of this name | ||
| 4 | and it is up to the SoC to connect that up to an actual reset | ||
| 5 | mechanism), but in QEMU it mostly results in duplicated code in SoC | ||
| 6 | objects and bugs where SoC model implementors forget to wire up the | ||
| 7 | SYSRESETREQ line. | ||
| 8 | 2 | ||
| 9 | Provide a default behaviour for the case where SYSRESETREQ is not | 3 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
| 10 | actually connected to anything: use qemu_system_reset_request() to | 4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 11 | perform a system reset. This will allow us to remove the | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 12 | implementations of SYSRESETREQ handling from the boards where that's | 6 | Message-id: 20241122225049.1617774-5-pierrick.bouvier@linaro.org |
| 13 | exactly what it does, and also fixes the bugs in the board models | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 14 | which forgot to wire up the signal: | 8 | --- |
| 9 | target/arm/tcg/cpu32.c | 2 +- | ||
| 10 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 15 | 11 | ||
| 16 | * microbit | 12 | diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c |
| 17 | * mps2-an385 | ||
| 18 | * mps2-an505 | ||
| 19 | * mps2-an511 | ||
| 20 | * mps2-an521 | ||
| 21 | * musca-a | ||
| 22 | * musca-b1 | ||
| 23 | * netduino | ||
| 24 | * netduinoplus2 | ||
| 25 | |||
| 26 | We still allow the board to wire up the signal if it needs to, in case | ||
| 27 | we need to model more complicated reset controller logic or to model | ||
| 28 | buggy SoC hardware which forgot to wire up the line itself. But | ||
| 29 | defaulting to "reset the system" is more often going to be correct | ||
| 30 | than defaulting to "do nothing". | ||
| 31 | |||
| 32 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 33 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 34 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 35 | Message-id: 20200728103744.6909-3-peter.maydell@linaro.org | ||
| 36 | --- | ||
| 37 | include/hw/arm/armv7m.h | 4 +++- | ||
| 38 | hw/intc/armv7m_nvic.c | 17 ++++++++++++++++- | ||
| 39 | 2 files changed, 19 insertions(+), 2 deletions(-) | ||
| 40 | |||
| 41 | diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h | ||
| 42 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 43 | --- a/include/hw/arm/armv7m.h | 14 | --- a/target/arm/tcg/cpu32.c |
| 44 | +++ b/include/hw/arm/armv7m.h | 15 | +++ b/target/arm/tcg/cpu32.c |
| 45 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 16 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) |
| 46 | 17 | cpu->isar.id_mmfr5 = t; | |
| 47 | /* ARMv7M container object. | 18 | |
| 48 | * + Unnamed GPIO input lines: external IRQ lines for the NVIC | 19 | t = cpu->isar.id_pfr0; |
| 49 | - * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ | 20 | - t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ |
| 50 | + * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ. | 21 | + t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ |
| 51 | + * If this GPIO is not wired up then the NVIC will default to performing | 22 | t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ |
| 52 | + * a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET). | 23 | t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ |
| 53 | * + Property "cpu-type": CPU type to instantiate | 24 | cpu->isar.id_pfr0 = t; |
| 54 | * + Property "num-irq": number of external IRQ lines | ||
| 55 | * + Property "memory": MemoryRegion defining the physical address space | ||
| 56 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
| 57 | index XXXXXXX..XXXXXXX 100644 | ||
| 58 | --- a/hw/intc/armv7m_nvic.c | ||
| 59 | +++ b/hw/intc/armv7m_nvic.c | ||
| 60 | @@ -XXX,XX +XXX,XX @@ | ||
| 61 | #include "hw/intc/armv7m_nvic.h" | ||
| 62 | #include "hw/irq.h" | ||
| 63 | #include "hw/qdev-properties.h" | ||
| 64 | +#include "sysemu/runstate.h" | ||
| 65 | #include "target/arm/cpu.h" | ||
| 66 | #include "exec/exec-all.h" | ||
| 67 | #include "exec/memop.h" | ||
| 68 | @@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = { | ||
| 69 | 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 | ||
| 70 | }; | ||
| 71 | |||
| 72 | +static void signal_sysresetreq(NVICState *s) | ||
| 73 | +{ | ||
| 74 | + if (qemu_irq_is_connected(s->sysresetreq)) { | ||
| 75 | + qemu_irq_pulse(s->sysresetreq); | ||
| 76 | + } else { | ||
| 77 | + /* | ||
| 78 | + * Default behaviour if the SoC doesn't need to wire up | ||
| 79 | + * SYSRESETREQ (eg to a system reset controller of some kind): | ||
| 80 | + * perform a system reset via the usual QEMU API. | ||
| 81 | + */ | ||
| 82 | + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | ||
| 83 | + } | ||
| 84 | +} | ||
| 85 | + | ||
| 86 | static int nvic_pending_prio(NVICState *s) | ||
| 87 | { | ||
| 88 | /* return the group priority of the current pending interrupt, | ||
| 89 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
| 90 | if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) { | ||
| 91 | if (attrs.secure || | ||
| 92 | !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) { | ||
| 93 | - qemu_irq_pulse(s->sysresetreq); | ||
| 94 | + signal_sysresetreq(s); | ||
| 95 | } | ||
| 96 | } | ||
| 97 | if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) { | ||
| 98 | -- | 25 | -- |
| 99 | 2.20.1 | 26 | 2.34.1 |
| 100 | 27 | ||
| 101 | 28 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
| 1 | 2 | ||
| 3 | We already implement FEAT_MTE_ASYNC; we just forgot to list it | ||
| 4 | in the documentation. | ||
| 5 | |||
| 6 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20241122225049.1617774-6-pierrick.bouvier@linaro.org | ||
| 9 | [PMM: expand commit message] | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | docs/system/arm/emulation.rst | 1 + | ||
| 13 | 1 file changed, 1 insertion(+) | ||
| 14 | |||
| 15 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/docs/system/arm/emulation.rst | ||
| 18 | +++ b/docs/system/arm/emulation.rst | ||
| 19 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
| 20 | - FEAT_MTE2 (Memory Tagging Extension) | ||
| 21 | - FEAT_MTE3 (MTE Asymmetric Fault Handling) | ||
| 22 | - FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults) | ||
| 23 | +- FEAT_MTE_ASYNC (Asynchronous reporting of Tag Check Fault) | ||
| 24 | - FEAT_NMI (Non-maskable Interrupt) | ||
| 25 | - FEAT_NV (Nested Virtualization) | ||
| 26 | - FEAT_NV2 (Enhanced nested virtualization support) | ||
| 27 | -- | ||
| 28 | 2.34.1 | diff view generated by jsdifflib |
| 1 | Mostly devices don't need to care whether one of their output | 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
|---|---|---|---|
| 2 | qemu_irq lines is connected, because functions like qemu_set_irq() | ||
| 3 | silently do nothing if there is nothing on the other end. However | ||
| 4 | sometimes a device might want to implement default behaviour for the | ||
| 5 | case where the machine hasn't wired the line up to anywhere. | ||
| 6 | 2 | ||
| 7 | Provide a function qemu_irq_is_connected() that devices can use for | 3 | We already implement FEAT_DoubleLock (see commit f94a6df5dd6a7) when |
| 8 | this purpose. (The test is trivial but encapsulating it in a | 4 | the ID registers call for it. This feature is actually one that must |
| 9 | function makes it easier to see where we're doing it in case we need | 5 | *not* be implemented in v9.0, but since our documentation lists |
| 10 | to change the implementation later.) | 6 | everything we can emulate, we should include FEAT_DoubleLock in the |
| 7 | list. | ||
| 11 | 8 | ||
| 9 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
| 10 | Message-id: 20241122225049.1617774-7-pierrick.bouvier@linaro.org | ||
| 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 12 | [PMM: expand commit message] | ||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 14 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 15 | Message-id: 20200728103744.6909-2-peter.maydell@linaro.org | ||
| 16 | --- | 14 | --- |
| 17 | include/hw/irq.h | 18 ++++++++++++++++++ | 15 | docs/system/arm/emulation.rst | 1 + |
| 18 | 1 file changed, 18 insertions(+) | 16 | 1 file changed, 1 insertion(+) |
| 19 | 17 | ||
| 20 | diff --git a/include/hw/irq.h b/include/hw/irq.h | 18 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
| 21 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
| 22 | --- a/include/hw/irq.h | 20 | --- a/docs/system/arm/emulation.rst |
| 23 | +++ b/include/hw/irq.h | 21 | +++ b/docs/system/arm/emulation.rst |
| 24 | @@ -XXX,XX +XXX,XX @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2); | 22 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
| 25 | on an existing vector of qemu_irq. */ | 23 | - FEAT_CSV3 (Cache speculation variant 3) |
| 26 | void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n); | 24 | - FEAT_DGH (Data gathering hint) |
| 27 | 25 | - FEAT_DIT (Data Independent Timing instructions) | |
| 28 | +/** | 26 | +- FEAT_DoubleLock (Double Lock) |
| 29 | + * qemu_irq_is_connected: Return true if IRQ line is wired up | 27 | - FEAT_DPB (DC CVAP instruction) |
| 30 | + * | 28 | - FEAT_DPB2 (DC CVADP instruction) |
| 31 | + * If a qemu_irq has a device on the other (receiving) end of it, | 29 | - FEAT_Debugv8p1 (Debug with VHE) |
| 32 | + * return true; otherwise return false. | ||
| 33 | + * | ||
| 34 | + * Usually device models don't need to care whether the machine model | ||
| 35 | + * has wired up their outbound qemu_irq lines, because functions like | ||
| 36 | + * qemu_set_irq() silently do nothing if there is nothing on the other | ||
| 37 | + * end of the line. However occasionally a device model will want to | ||
| 38 | + * provide default behaviour if its output is left floating, and | ||
| 39 | + * it can use this function to identify when that is the case. | ||
| 40 | + */ | ||
| 41 | +static inline bool qemu_irq_is_connected(qemu_irq irq) | ||
| 42 | +{ | ||
| 43 | + return irq != NULL; | ||
| 44 | +} | ||
| 45 | + | ||
| 46 | #endif | ||
| 47 | -- | 30 | -- |
| 48 | 2.20.1 | 31 | 2.34.1 |
| 49 | |||
| 50 | diff view generated by jsdifflib |
| 1 | The netduino2 and netduinoplus2 boards forgot to set the system_clock_scale | 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
|---|---|---|---|
| 2 | global, which meant that if guest code used the systick timer in "use | ||
| 3 | the processor clock" mode it would hang because time never advances. | ||
| 4 | 2 | ||
| 5 | Set the global to match the documented CPU clock speed of these boards. | 3 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
| 6 | Judging by the data sheet this is slightly simplistic because the | 4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 7 | SoC allows configuration of the SYSCLK source and frequency via the | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | RCC (reset and clock control) module, but we don't model that. | 6 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 7 | Message-id: 20241122225049.1617774-8-pierrick.bouvier@linaro.org | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | --- | ||
| 10 | docs/system/arm/fby35.rst | 2 +- | ||
| 11 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 9 | 12 | ||
| 10 | Fixes: https://bugs.launchpad.net/qemu/+bug/1876187 | 13 | diff --git a/docs/system/arm/fby35.rst b/docs/system/arm/fby35.rst |
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 13 | Message-id: 20200727162617.26227-1-peter.maydell@linaro.org | ||
| 14 | --- | ||
| 15 | hw/arm/netduino2.c | 10 ++++++++++ | ||
| 16 | hw/arm/netduinoplus2.c | 10 ++++++++++ | ||
| 17 | 2 files changed, 20 insertions(+) | ||
| 18 | |||
| 19 | diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c | ||
| 20 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
| 21 | --- a/hw/arm/netduino2.c | 15 | --- a/docs/system/arm/fby35.rst |
| 22 | +++ b/hw/arm/netduino2.c | 16 | +++ b/docs/system/arm/fby35.rst |
| 23 | @@ -XXX,XX +XXX,XX @@ | 17 | @@ -XXX,XX +XXX,XX @@ include various compute accelerators (video, inferencing, etc). At the moment, |
| 24 | #include "hw/arm/stm32f205_soc.h" | 18 | only the first server slot's BIC is included. |
| 25 | #include "hw/arm/boot.h" | 19 | |
| 26 | 20 | Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds | |
| 27 | +/* Main SYSCLK frequency in Hz (120MHz) */ | 21 | -can be fit into a chassis. See `here <https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server>`__ |
| 28 | +#define SYSCLK_FRQ 120000000ULL | 22 | +can be fit into a chassis. See `here <https://www.opencompute.org/products-chiplets/237/wiwynn-yosemite-v3-server>`__ |
| 29 | + | 23 | for an example. |
| 30 | static void netduino2_init(MachineState *machine) | 24 | |
| 31 | { | 25 | In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC |
| 32 | DeviceState *dev; | ||
| 33 | |||
| 34 | + /* | ||
| 35 | + * TODO: ideally we would model the SoC RCC and let it handle | ||
| 36 | + * system_clock_scale, including its ability to define different | ||
| 37 | + * possible SYSCLK sources. | ||
| 38 | + */ | ||
| 39 | + system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; | ||
| 40 | + | ||
| 41 | dev = qdev_new(TYPE_STM32F205_SOC); | ||
| 42 | qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); | ||
| 43 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
| 44 | diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c | ||
| 45 | index XXXXXXX..XXXXXXX 100644 | ||
| 46 | --- a/hw/arm/netduinoplus2.c | ||
| 47 | +++ b/hw/arm/netduinoplus2.c | ||
| 48 | @@ -XXX,XX +XXX,XX @@ | ||
| 49 | #include "hw/arm/stm32f405_soc.h" | ||
| 50 | #include "hw/arm/boot.h" | ||
| 51 | |||
| 52 | +/* Main SYSCLK frequency in Hz (168MHz) */ | ||
| 53 | +#define SYSCLK_FRQ 168000000ULL | ||
| 54 | + | ||
| 55 | static void netduinoplus2_init(MachineState *machine) | ||
| 56 | { | ||
| 57 | DeviceState *dev; | ||
| 58 | |||
| 59 | + /* | ||
| 60 | + * TODO: ideally we would model the SoC RCC and let it handle | ||
| 61 | + * system_clock_scale, including its ability to define different | ||
| 62 | + * possible SYSCLK sources. | ||
| 63 | + */ | ||
| 64 | + system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; | ||
| 65 | + | ||
| 66 | dev = qdev_new(TYPE_STM32F405_SOC); | ||
| 67 | qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); | ||
| 68 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
| 69 | -- | 26 | -- |
| 70 | 2.20.1 | 27 | 2.34.1 |
| 71 | 28 | ||
| 72 | 29 | diff view generated by jsdifflib |
| 1 | The imx_epit device has a software-controllable reset triggered by | 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
|---|---|---|---|
| 2 | setting the SWR bit in the CR register. An error in commit cc2722ec83ad9 | ||
| 3 | means that we will end up assert()ing if the guest does this, because | ||
| 4 | the code in imx_epit_write() starts ptimer transactions, and then | ||
| 5 | imx_epit_reset() also starts ptimer transactions, triggering | ||
| 6 | "ptimer_transaction_begin: Assertion `!s->in_transaction' failed". | ||
| 7 | 2 | ||
| 8 | The cleanest way to avoid this double-transaction is to move the | 3 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
| 9 | start-transaction for the CR write handling down below the check of | 4 | Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> |
| 10 | the SWR bit. | 5 | Message-id: 20241122225049.1617774-13-pierrick.bouvier@linaro.org |
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | --- | ||
| 8 | docs/system/arm/aspeed.rst | 7 ++++--- | ||
| 9 | 1 file changed, 4 insertions(+), 3 deletions(-) | ||
| 11 | 10 | ||
| 12 | Fixes: https://bugs.launchpad.net/qemu/+bug/1880424 | 11 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst |
| 13 | Fixes: cc2722ec83ad944505fe | ||
| 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 15 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 16 | Message-id: 20200727154550.3409-1-peter.maydell@linaro.org | ||
| 17 | --- | ||
| 18 | hw/timer/imx_epit.c | 13 ++++++++++--- | ||
| 19 | 1 file changed, 10 insertions(+), 3 deletions(-) | ||
| 20 | |||
| 21 | diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c | ||
| 22 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
| 23 | --- a/hw/timer/imx_epit.c | 13 | --- a/docs/system/arm/aspeed.rst |
| 24 | +++ b/hw/timer/imx_epit.c | 14 | +++ b/docs/system/arm/aspeed.rst |
| 25 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, | 15 | @@ -XXX,XX +XXX,XX @@ |
| 26 | 16 | -Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``) | |
| 27 | switch (offset >> 2) { | 17 | -======================================================================================================================================================================================================================================================================================================================================================================================================== |
| 28 | case 0: /* CR */ | 18 | +Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``) |
| 29 | - ptimer_transaction_begin(s->timer_cmp); | 19 | +================================================================================================================================================================================================================================================================================================================================================================================================================================== |
| 30 | - ptimer_transaction_begin(s->timer_reload); | 20 | |
| 31 | 21 | The QEMU Aspeed machines model BMCs of various OpenPOWER systems and | |
| 32 | oldcr = s->cr; | 22 | Aspeed evaluation boards. They are based on different releases of the |
| 33 | s->cr = value & 0x03ffffff; | 23 | @@ -XXX,XX +XXX,XX @@ AST2400 SoC based machines : |
| 34 | if (s->cr & CR_SWR) { | 24 | |
| 35 | /* handle the reset */ | 25 | - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC |
| 36 | imx_epit_reset(DEVICE(s)); | 26 | - ``quanta-q71l-bmc`` OpenBMC Quanta BMC |
| 37 | - } else { | 27 | -- ``supermicrox11-bmc`` Supermicro X11 BMC |
| 38 | + /* | 28 | +- ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S) |
| 39 | + * TODO: could we 'break' here? following operations appear | 29 | +- ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176) |
| 40 | + * to duplicate the work imx_epit_reset() already did. | 30 | |
| 41 | + */ | 31 | AST2500 SoC based machines : |
| 42 | + } | ||
| 43 | + | ||
| 44 | + ptimer_transaction_begin(s->timer_cmp); | ||
| 45 | + ptimer_transaction_begin(s->timer_reload); | ||
| 46 | + | ||
| 47 | + if (!(s->cr & CR_SWR)) { | ||
| 48 | imx_epit_set_freq(s); | ||
| 49 | } | ||
| 50 | 32 | ||
| 51 | -- | 33 | -- |
| 52 | 2.20.1 | 34 | 2.34.1 |
| 53 | |||
| 54 | diff view generated by jsdifflib |