1
Handful of bugfixes for rc2. None of these are particularly critical
1
A last lot of bug fixes before rc0...
2
or exciting.
3
2
3
thanks
4
-- PMM
4
-- PMM
5
5
6
The following changes since commit 45a150aa2b3492acf6691c7bdbeb25a8545d8345:
6
The following changes since commit 0d0275c31f00b71b49eb80bbdca2cfe244cf80fb:
7
7
8
Merge remote-tracking branch 'remotes/ericb/tags/pull-bitmaps-2020-08-03' into staging (2020-08-03 15:13:49 +0100)
8
Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2022-07-26 10:31:02 +0100)
9
9
10
are available in the Git repository at:
10
are available in the Git repository at:
11
11
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200803
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220726
13
13
14
for you to fetch changes up to 13557fd392890cbd985bceba7f717e01efd674b8:
14
for you to fetch changes up to 5865d99fe88d8c8fa437c18c6b63fb2a8165634f:
15
15
16
hw/timer/imx_epit: Avoid assertion when CR.SWR is written (2020-08-03 17:56:11 +0100)
16
hw/display/bcm2835_fb: Fix framebuffer allocation address (2022-07-26 14:09:44 +0100)
17
17
18
----------------------------------------------------------------
18
----------------------------------------------------------------
19
target-arm queue:
19
target-arm queue:
20
* hw/timer/imx_epit: Avoid assertion when CR.SWR is written
20
* Update Coverity component definitions
21
* netduino2, netduinoplus2, microbit: set system_clock_scale so that
21
* target/arm: Add MO_128 entry to pred_esz_masks[]
22
SysTick running on the CPU clock works
22
* configure: Fix portability issues
23
* target/arm: Avoid maybe-uninitialized warning with gcc 4.9
23
* hw/display/bcm2835_fb: Fix framebuffer allocation address
24
* target/arm: Fix AddPAC error indication
25
* Make AIRCR.SYSRESETREQ actually reset the system for the
26
microbit, mps2-*, musca-*, netduino* boards
27
24
28
----------------------------------------------------------------
25
----------------------------------------------------------------
29
Kaige Li (1):
26
Alan Jian (1):
30
target/arm: Avoid maybe-uninitialized warning with gcc 4.9
27
hw/display/bcm2835_fb: Fix framebuffer allocation address
31
28
32
Peter Maydell (6):
29
Peter Maydell (8):
33
hw/arm/netduino2, netduinoplus2: Set system_clock_scale
30
scripts/coverity-scan/COMPONENTS.md: Add loongarch component
34
include/hw/irq.h: New function qemu_irq_is_connected()
31
scripts/coverity-scan/COMPONENTS.md: Update slirp component info
35
hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for SYSRESETREQ
32
target/arm: Add MO_128 entry to pred_esz_masks[]
36
msf2-soc, stellaris: Don't wire up SYSRESETREQ
33
configure: Add missing POSIX-required space
37
hw/arm/nrf51_soc: Set system_clock_scale
34
configure: Add braces to clarify intent of $emu[[:space:]]
38
hw/timer/imx_epit: Avoid assertion when CR.SWR is written
35
configure: Don't use bash-specific string-replacement syntax
36
configure: Drop dead code attempting to use -msmall-data on alpha hosts
37
configure: Avoid '==' bashism
39
38
40
Richard Henderson (1):
39
configure | 20 +++++++-------------
41
target/arm: Fix AddPAC error indication
40
target/arm/cpu.h | 2 +-
42
41
hw/display/bcm2835_fb.c | 3 +--
43
include/hw/arm/armv7m.h | 4 +++-
42
target/arm/translate-sve.c | 5 +++--
44
include/hw/irq.h | 18 ++++++++++++++++++
43
scripts/coverity-scan/COMPONENTS.md | 7 +++++--
45
hw/arm/msf2-soc.c | 11 -----------
44
5 files changed, 17 insertions(+), 20 deletions(-)
46
hw/arm/netduino2.c | 10 ++++++++++
47
hw/arm/netduinoplus2.c | 10 ++++++++++
48
hw/arm/nrf51_soc.c | 5 +++++
49
hw/arm/stellaris.c | 12 ------------
50
hw/intc/armv7m_nvic.c | 17 ++++++++++++++++-
51
hw/timer/imx_epit.c | 13 ++++++++++---
52
target/arm/pauth_helper.c | 6 +++++-
53
target/arm/translate-a64.c | 2 +-
54
tests/tcg/aarch64/pauth-5.c | 33 +++++++++++++++++++++++++++++++++
55
tests/tcg/aarch64/Makefile.target | 2 +-
56
13 files changed, 112 insertions(+), 31 deletions(-)
57
create mode 100644 tests/tcg/aarch64/pauth-5.c
58
diff view generated by jsdifflib
New patch
1
Add the component regex for the new loongarch target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
5
Message-id: 20220718142310.16013-2-peter.maydell@linaro.org
6
---
7
scripts/coverity-scan/COMPONENTS.md | 3 +++
8
1 file changed, 3 insertions(+)
9
10
diff --git a/scripts/coverity-scan/COMPONENTS.md b/scripts/coverity-scan/COMPONENTS.md
11
index XXXXXXX..XXXXXXX 100644
12
--- a/scripts/coverity-scan/COMPONENTS.md
13
+++ b/scripts/coverity-scan/COMPONENTS.md
14
@@ -XXX,XX +XXX,XX @@ testlibs
15
16
tests
17
~ (/qemu)?(/tests/.*)
18
+
19
+loongarch
20
+ ~ (/qemu)?((/include)?/hw/(loongarch/.*|.*/loongarch.*)|/target/loongarch/.*)
21
--
22
2.25.1
diff view generated by jsdifflib
1
The nrf51 SoC model wasn't setting the system_clock_scale
1
Update the regex for the slirp component now that it lives
2
global.which meant that if guest code used the systick timer in "use
2
solely inside /slirp/, and note that it should be ignored in
3
the processor clock" mode it would hang because time never advances.
3
Coverity analysis (because it's a separate upstream project
4
4
now, and they run Coverity on it themselves).
5
Set the global to match the documented CPU clock speed for this SoC.
6
7
This SoC in fact doesn't have a SysTick timer (which is the only thing
8
currently that cares about the system_clock_scale), because it's
9
a configurable option in the Cortex-M0. However our Cortex-M0 and
10
thus our nrf51 and our micro:bit board do provide a SysTick, so
11
we ought to provide a functional one rather than a broken one.
12
5
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
15
Message-id: 20200727193458.31250-1-peter.maydell@linaro.org
8
Message-id: 20220718142310.16013-3-peter.maydell@linaro.org
16
---
9
---
17
hw/arm/nrf51_soc.c | 5 +++++
10
scripts/coverity-scan/COMPONENTS.md | 4 ++--
18
1 file changed, 5 insertions(+)
11
1 file changed, 2 insertions(+), 2 deletions(-)
19
12
20
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
13
diff --git a/scripts/coverity-scan/COMPONENTS.md b/scripts/coverity-scan/COMPONENTS.md
21
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/nrf51_soc.c
15
--- a/scripts/coverity-scan/COMPONENTS.md
23
+++ b/hw/arm/nrf51_soc.c
16
+++ b/scripts/coverity-scan/COMPONENTS.md
24
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ qemu-ga
25
18
scsi
26
#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
19
~ (/qemu)?(/scsi/.*|/hw/scsi/.*|/include/hw/scsi/.*)
27
20
28
+/* HCLK (the main CPU clock) on this SoC is always 16MHz */
21
-slirp
29
+#define HCLK_FRQ 16000000
22
- ~ (/qemu)?(/.*slirp.*)
30
+
23
+slirp (component should be ignored in analysis)
31
static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
24
+ ~ (/qemu)?(/slirp/.*)
32
{
25
33
qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
26
tcg
34
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
27
~ (/qemu)?(/accel/tcg/.*|/replay/.*|/(.*/)?softmmu.*)
35
return;
36
}
37
38
+ system_clock_scale = NANOSECONDS_PER_SECOND / HCLK_FRQ;
39
+
40
object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
41
&error_abort);
42
if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {
43
--
28
--
44
2.20.1
29
2.25.1
45
46
diff view generated by jsdifflib
1
The MSF2 SoC model and the Stellaris board code both wire
1
In commit 7390e0e9ab8475, we added support for SME loads and stores.
2
SYSRESETREQ up to a function that just invokes
2
Unlike SVE loads and stores, these include handling of 128-bit
3
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
3
elements. The SME load/store functions call down into the existing
4
This is now the default action that the NVIC does if the line is
4
sve_cont_ldst_elements() function, which uses the element size MO_*
5
not connected, so we can delete the handling code.
5
value as an index into the pred_esz_masks[] array. Because this code
6
path now has to handle MO_128, we need to add an extra element to the
7
array.
6
8
9
This bug was spotted by Coverity because it meant we were reading off
10
the end of the array.
11
12
Resolves: Coverity CID 1490539, 1490541, 1490543, 1490544, 1490545,
13
1490546, 1490548, 1490549, 1490550, 1490551, 1490555, 1490557,
14
1490558, 1490560, 1490561, 1490563
15
Fixes: 7390e0e9ab8475 ("target/arm: Implement SME LD1, ST1")
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
18
Message-id: 20220718100144.3248052-1-peter.maydell@linaro.org
10
Message-id: 20200728103744.6909-4-peter.maydell@linaro.org
11
---
19
---
12
hw/arm/msf2-soc.c | 11 -----------
20
target/arm/cpu.h | 2 +-
13
hw/arm/stellaris.c | 12 ------------
21
target/arm/translate-sve.c | 5 +++--
14
2 files changed, 23 deletions(-)
22
2 files changed, 4 insertions(+), 3 deletions(-)
15
23
16
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
24
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/msf2-soc.c
26
--- a/target/arm/cpu.h
19
+++ b/hw/arm/msf2-soc.c
27
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
21
#include "hw/irq.h"
29
}
22
#include "hw/arm/msf2-soc.h"
30
23
#include "hw/misc/unimp.h"
31
/* Shared between translate-sve.c and sve_helper.c. */
24
-#include "sysemu/runstate.h"
32
-extern const uint64_t pred_esz_masks[4];
25
#include "sysemu/sysemu.h"
33
+extern const uint64_t pred_esz_masks[5];
26
34
27
#define MSF2_TIMER_BASE 0x40004000
35
/* Helper for the macros below, validating the argument type. */
28
@@ -XXX,XX +XXX,XX @@ static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
36
static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
29
static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
37
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
30
static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
31
32
-static void do_sys_reset(void *opaque, int n, int level)
33
-{
34
- if (level) {
35
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
36
- }
37
-}
38
-
39
static void m2sxxx_soc_initfn(Object *obj)
40
{
41
MSF2State *s = MSF2_SOC(obj);
42
@@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
43
return;
44
}
45
46
- qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0,
47
- qemu_allocate_irq(&do_sys_reset, NULL, 0));
48
-
49
system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
50
51
for (i = 0; i < MSF2_NUM_UARTS; i++) {
52
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
53
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/arm/stellaris.c
39
--- a/target/arm/translate-sve.c
55
+++ b/hw/arm/stellaris.c
40
+++ b/target/arm/translate-sve.c
56
@@ -XXX,XX +XXX,XX @@
41
@@ -XXX,XX +XXX,XX @@ static void do_predtest(DisasContext *s, int dofs, int gofs, int words)
57
#include "hw/boards.h"
58
#include "qemu/log.h"
59
#include "exec/address-spaces.h"
60
-#include "sysemu/runstate.h"
61
#include "sysemu/sysemu.h"
62
#include "hw/arm/armv7m.h"
63
#include "hw/char/pl011.h"
64
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj)
65
qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
66
}
42
}
67
43
68
-static
44
/* For each element size, the bits within a predicate word that are active. */
69
-void do_sys_reset(void *opaque, int n, int level)
45
-const uint64_t pred_esz_masks[4] = {
70
-{
46
+const uint64_t pred_esz_masks[5] = {
71
- if (level) {
47
0xffffffffffffffffull, 0x5555555555555555ull,
72
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
48
- 0x1111111111111111ull, 0x0101010101010101ull
73
- }
49
+ 0x1111111111111111ull, 0x0101010101010101ull,
74
-}
50
+ 0x0001000100010001ull,
75
-
51
};
76
/* Board init. */
52
77
static stellaris_board_info stellaris_boards[] = {
53
static bool trans_INVALID(DisasContext *s, arg_INVALID *a)
78
{ "LM3S811EVB",
79
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
80
/* This will exit with an error if the user passed us a bad cpu_type */
81
sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
82
83
- qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0,
84
- qemu_allocate_irq(&do_sys_reset, NULL, 0));
85
-
86
if (board->dc1 & (1 << 16)) {
87
dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
88
qdev_get_gpio_in(nvic, 14),
89
--
54
--
90
2.20.1
55
2.25.1
91
92
diff view generated by jsdifflib
1
The imx_epit device has a software-controllable reset triggered by
1
In commit 7d7dbf9dc15be6e1 we added a line to the configure script
2
setting the SWR bit in the CR register. An error in commit cc2722ec83ad9
2
which is not valid POSIX shell syntax, because it is missing a space
3
means that we will end up assert()ing if the guest does this, because
3
after a '!' character. shellcheck diagnoses this:
4
the code in imx_epit_write() starts ptimer transactions, and then
5
imx_epit_reset() also starts ptimer transactions, triggering
6
"ptimer_transaction_begin: Assertion `!s->in_transaction' failed".
7
4
8
The cleanest way to avoid this double-transaction is to move the
5
if !(GIT="$git" "$source_path/scripts/git-submodule.sh" "$git_submodules_action" "$git_submodules"); then
9
start-transaction for the CR write handling down below the check of
6
^-- SC1035: You are missing a required space after the !.
10
the SWR bit.
11
7
12
Fixes: https://bugs.launchpad.net/qemu/+bug/1880424
8
and the OpenBSD shell will not correctly handle this without the space.
13
Fixes: cc2722ec83ad944505fe
9
10
Fixes: 7d7dbf9dc15be6e1 ("configure: replace --enable/disable-git-update with --with-git-submodules")
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Thomas Huth <thuth@redhat.com>
16
Message-id: 20200727154550.3409-1-peter.maydell@linaro.org
13
Tested-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
14
Message-id: 20220720152631.450903-2-peter.maydell@linaro.org
17
---
15
---
18
hw/timer/imx_epit.c | 13 ++++++++++---
16
configure | 2 +-
19
1 file changed, 10 insertions(+), 3 deletions(-)
17
1 file changed, 1 insertion(+), 1 deletion(-)
20
18
21
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
19
diff --git a/configure b/configure
22
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100755
23
--- a/hw/timer/imx_epit.c
21
--- a/configure
24
+++ b/hw/timer/imx_epit.c
22
+++ b/configure
25
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
23
@@ -XXX,XX +XXX,XX @@ else
26
24
cxx=
27
switch (offset >> 2) {
25
fi
28
case 0: /* CR */
26
29
- ptimer_transaction_begin(s->timer_cmp);
27
-if !(GIT="$git" "$source_path/scripts/git-submodule.sh" "$git_submodules_action" "$git_submodules"); then
30
- ptimer_transaction_begin(s->timer_reload);
28
+if ! (GIT="$git" "$source_path/scripts/git-submodule.sh" "$git_submodules_action" "$git_submodules"); then
31
29
exit 1
32
oldcr = s->cr;
30
fi
33
s->cr = value & 0x03ffffff;
34
if (s->cr & CR_SWR) {
35
/* handle the reset */
36
imx_epit_reset(DEVICE(s));
37
- } else {
38
+ /*
39
+ * TODO: could we 'break' here? following operations appear
40
+ * to duplicate the work imx_epit_reset() already did.
41
+ */
42
+ }
43
+
44
+ ptimer_transaction_begin(s->timer_cmp);
45
+ ptimer_transaction_begin(s->timer_reload);
46
+
47
+ if (!(s->cr & CR_SWR)) {
48
imx_epit_set_freq(s);
49
}
50
31
51
--
32
--
52
2.20.1
33
2.25.1
53
54
diff view generated by jsdifflib
1
The NVIC provides an outbound qemu_irq "SYSRESETREQ" which it signals
1
In shell script syntax, $var[something] is not special for variable
2
when the guest sets the SYSRESETREQ bit in the AIRCR register. This
2
expansion: $var is expanded. However, as it can look as if it were
3
matches the hardware design (where the CPU has a signal of this name
3
intended to be an array element access (the correct syntax for which
4
and it is up to the SoC to connect that up to an actual reset
4
is ${var[something]}), shellcheck recommends using explicit braces
5
mechanism), but in QEMU it mostly results in duplicated code in SoC
5
around ${var} to clarify the intended expansion.
6
objects and bugs where SoC model implementors forget to wire up the
7
SYSRESETREQ line.
8
6
9
Provide a default behaviour for the case where SYSRESETREQ is not
7
This fixes the warning:
10
actually connected to anything: use qemu_system_reset_request() to
11
perform a system reset. This will allow us to remove the
12
implementations of SYSRESETREQ handling from the boards where that's
13
exactly what it does, and also fixes the bugs in the board models
14
which forgot to wire up the signal:
15
8
16
* microbit
9
In ./configure line 2346:
17
* mps2-an385
10
if "$target_ld" -verbose 2>&1 | grep -q "^[[:space:]]*$emu[[:space:]]*$"; then
18
* mps2-an505
11
^-- SC1087: Use braces when expanding arrays, e.g. ${array[idx]} (or ${var}[.. to quiet).
19
* mps2-an511
20
* mps2-an521
21
* musca-a
22
* musca-b1
23
* netduino
24
* netduinoplus2
25
26
We still allow the board to wire up the signal if it needs to, in case
27
we need to model more complicated reset controller logic or to model
28
buggy SoC hardware which forgot to wire up the line itself. But
29
defaulting to "reset the system" is more often going to be correct
30
than defaulting to "do nothing".
31
12
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Thomas Huth <thuth@redhat.com>
34
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Message-id: 20220720152631.450903-3-peter.maydell@linaro.org
35
Message-id: 20200728103744.6909-3-peter.maydell@linaro.org
36
---
16
---
37
include/hw/arm/armv7m.h | 4 +++-
17
configure | 2 +-
38
hw/intc/armv7m_nvic.c | 17 ++++++++++++++++-
18
1 file changed, 1 insertion(+), 1 deletion(-)
39
2 files changed, 19 insertions(+), 2 deletions(-)
40
19
41
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
20
diff --git a/configure b/configure
42
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100755
43
--- a/include/hw/arm/armv7m.h
22
--- a/configure
44
+++ b/include/hw/arm/armv7m.h
23
+++ b/configure
45
@@ -XXX,XX +XXX,XX @@ typedef struct {
24
@@ -XXX,XX +XXX,XX @@ if test -n "$target_cc" &&
46
25
# emulation. Linux and OpenBSD/amd64 use 'elf_i386'; FreeBSD uses the _fbsd
47
/* ARMv7M container object.
26
# variant; OpenBSD/i386 uses the _obsd variant; and Windows uses i386pe.
48
* + Unnamed GPIO input lines: external IRQ lines for the NVIC
27
for emu in elf_i386 elf_i386_fbsd elf_i386_obsd i386pe; do
49
- * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
28
- if "$target_ld" -verbose 2>&1 | grep -q "^[[:space:]]*$emu[[:space:]]*$"; then
50
+ * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ.
29
+ if "$target_ld" -verbose 2>&1 | grep -q "^[[:space:]]*${emu}[[:space:]]*$"; then
51
+ * If this GPIO is not wired up then the NVIC will default to performing
30
ld_i386_emulation="$emu"
52
+ * a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET).
31
break
53
* + Property "cpu-type": CPU type to instantiate
32
fi
54
* + Property "num-irq": number of external IRQ lines
55
* + Property "memory": MemoryRegion defining the physical address space
56
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/intc/armv7m_nvic.c
59
+++ b/hw/intc/armv7m_nvic.c
60
@@ -XXX,XX +XXX,XX @@
61
#include "hw/intc/armv7m_nvic.h"
62
#include "hw/irq.h"
63
#include "hw/qdev-properties.h"
64
+#include "sysemu/runstate.h"
65
#include "target/arm/cpu.h"
66
#include "exec/exec-all.h"
67
#include "exec/memop.h"
68
@@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = {
69
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
70
};
71
72
+static void signal_sysresetreq(NVICState *s)
73
+{
74
+ if (qemu_irq_is_connected(s->sysresetreq)) {
75
+ qemu_irq_pulse(s->sysresetreq);
76
+ } else {
77
+ /*
78
+ * Default behaviour if the SoC doesn't need to wire up
79
+ * SYSRESETREQ (eg to a system reset controller of some kind):
80
+ * perform a system reset via the usual QEMU API.
81
+ */
82
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
83
+ }
84
+}
85
+
86
static int nvic_pending_prio(NVICState *s)
87
{
88
/* return the group priority of the current pending interrupt,
89
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
90
if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) {
91
if (attrs.secure ||
92
!(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) {
93
- qemu_irq_pulse(s->sysresetreq);
94
+ signal_sysresetreq(s);
95
}
96
}
97
if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) {
98
--
33
--
99
2.20.1
34
2.25.1
100
101
diff view generated by jsdifflib
1
The netduino2 and netduinoplus2 boards forgot to set the system_clock_scale
1
The variable string-replacement syntax ${var/old/new} is a bashism
2
global, which meant that if guest code used the systick timer in "use
2
(though it is also supported by some other shells), and for instance
3
the processor clock" mode it would hang because time never advances.
3
does not work with the NetBSD /bin/sh, which complains:
4
../src/configure: 687: Syntax error: Bad substitution
4
5
5
Set the global to match the documented CPU clock speed of these boards.
6
Replace it with a more portable sed-based approach, similar to
6
Judging by the data sheet this is slightly simplistic because the
7
what we already do in quote_sh().
7
SoC allows configuration of the SYSCLK source and frequency via the
8
RCC (reset and clock control) module, but we don't model that.
9
8
10
Fixes: https://bugs.launchpad.net/qemu/+bug/1876187
9
Note that shellcheck also diagnoses this:
10
11
In ./configure line 687:
12
e=${e/'\'/'\\'}
13
^-----------^ SC2039: In POSIX sh, string replacement is undefined.
14
^-- SC1003: Want to escape a single quote? echo 'This is how it'\''s done'.
15
^-- SC1003: Want to escape a single quote? echo 'This is how it'\''s done'.
16
17
In ./configure line 688:
18
e=${e/\"/'\"'}
19
^----------^ SC2039: In POSIX sh, string replacement is undefined.
20
21
Fixes: 8154f5e64b0cf ("meson: Prefix each element of firmware path")
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
23
Tested-by: Thomas Huth <thuth@redhat.com>
13
Message-id: 20200727162617.26227-1-peter.maydell@linaro.org
24
Message-id: 20220720152631.450903-4-peter.maydell@linaro.org
14
---
25
---
15
hw/arm/netduino2.c | 10 ++++++++++
26
configure | 7 ++++---
16
hw/arm/netduinoplus2.c | 10 ++++++++++
27
1 file changed, 4 insertions(+), 3 deletions(-)
17
2 files changed, 20 insertions(+)
18
28
19
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
29
diff --git a/configure b/configure
20
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100755
21
--- a/hw/arm/netduino2.c
31
--- a/configure
22
+++ b/hw/arm/netduino2.c
32
+++ b/configure
23
@@ -XXX,XX +XXX,XX @@
33
@@ -XXX,XX +XXX,XX @@ meson_option_build_array() {
24
#include "hw/arm/stm32f205_soc.h"
34
IFS=:
25
#include "hw/arm/boot.h"
35
fi
26
36
for e in $1; do
27
+/* Main SYSCLK frequency in Hz (120MHz) */
37
- e=${e/'\'/'\\'}
28
+#define SYSCLK_FRQ 120000000ULL
38
- e=${e/\"/'\"'}
29
+
39
- printf '"""%s""",' "$e"
30
static void netduino2_init(MachineState *machine)
40
+ printf '"""'
31
{
41
+ # backslash escape any '\' and '"' characters
32
DeviceState *dev;
42
+ printf "%s" "$e" | sed -e 's/\([\"]\)/\\\1/g'
33
43
+ printf '""",'
34
+ /*
44
done)
35
+ * TODO: ideally we would model the SoC RCC and let it handle
45
printf ']\n'
36
+ * system_clock_scale, including its ability to define different
46
}
37
+ * possible SYSCLK sources.
38
+ */
39
+ system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
40
+
41
dev = qdev_new(TYPE_STM32F205_SOC);
42
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
43
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
44
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/arm/netduinoplus2.c
47
+++ b/hw/arm/netduinoplus2.c
48
@@ -XXX,XX +XXX,XX @@
49
#include "hw/arm/stm32f405_soc.h"
50
#include "hw/arm/boot.h"
51
52
+/* Main SYSCLK frequency in Hz (168MHz) */
53
+#define SYSCLK_FRQ 168000000ULL
54
+
55
static void netduinoplus2_init(MachineState *machine)
56
{
57
DeviceState *dev;
58
59
+ /*
60
+ * TODO: ideally we would model the SoC RCC and let it handle
61
+ * system_clock_scale, including its ability to define different
62
+ * possible SYSCLK sources.
63
+ */
64
+ system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
65
+
66
dev = qdev_new(TYPE_STM32F405_SOC);
67
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
68
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
69
--
47
--
70
2.20.1
48
2.25.1
71
72
diff view generated by jsdifflib
1
Mostly devices don't need to care whether one of their output
1
In commit 823eb013452e93d we moved the setting of ARCH from configure
2
qemu_irq lines is connected, because functions like qemu_set_irq()
2
to meson.build, but we accidentally left behind one attempt to use
3
silently do nothing if there is nothing on the other end. However
3
$ARCH in configure, which was trying to add -msmall-data to the
4
sometimes a device might want to implement default behaviour for the
4
compiler flags on Alpha hosts. Since ARCH is now never set, the test
5
case where the machine hasn't wired the line up to anywhere.
5
always fails and we never add the flag.
6
6
7
Provide a function qemu_irq_is_connected() that devices can use for
7
There isn't actually any need to use this compiler flag on Alpha:
8
this purpose. (The test is trivial but encapsulating it in a
8
the original intent was that it would allow us to simplify our TCG
9
function makes it easier to see where we're doing it in case we need
9
codegen on that platform, but we never actually made the TCG changes
10
to change the implementation later.)
10
that would rely on -msmall-data.
11
12
Drop the effectively-dead code from configure, as we don't need it.
13
14
This was spotted by shellcheck:
15
16
In ./configure line 2254:
17
case "$ARCH" in
18
^---^ SC2153: Possible misspelling: ARCH may not be assigned, but arch is.
11
19
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
Reviewed-by: Thomas Huth <thuth@redhat.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
22
Message-id: 20220720152631.450903-5-peter.maydell@linaro.org
15
Message-id: 20200728103744.6909-2-peter.maydell@linaro.org
16
---
23
---
17
include/hw/irq.h | 18 ++++++++++++++++++
24
configure | 7 -------
18
1 file changed, 18 insertions(+)
25
1 file changed, 7 deletions(-)
19
26
20
diff --git a/include/hw/irq.h b/include/hw/irq.h
27
diff --git a/configure b/configure
21
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100755
22
--- a/include/hw/irq.h
29
--- a/configure
23
+++ b/include/hw/irq.h
30
+++ b/configure
24
@@ -XXX,XX +XXX,XX @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
31
@@ -XXX,XX +XXX,XX @@ if test "$fortify_source" = "yes" ; then
25
on an existing vector of qemu_irq. */
32
QEMU_CFLAGS="-U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 $QEMU_CFLAGS"
26
void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
33
fi
27
34
28
+/**
35
-case "$ARCH" in
29
+ * qemu_irq_is_connected: Return true if IRQ line is wired up
36
-alpha)
30
+ *
37
- # Ensure there's only a single GP
31
+ * If a qemu_irq has a device on the other (receiving) end of it,
38
- QEMU_CFLAGS="-msmall-data $QEMU_CFLAGS"
32
+ * return true; otherwise return false.
39
-;;
33
+ *
40
-esac
34
+ * Usually device models don't need to care whether the machine model
41
-
35
+ * has wired up their outbound qemu_irq lines, because functions like
42
if test "$have_asan" = "yes"; then
36
+ * qemu_set_irq() silently do nothing if there is nothing on the other
43
QEMU_CFLAGS="-fsanitize=address $QEMU_CFLAGS"
37
+ * end of the line. However occasionally a device model will want to
44
QEMU_LDFLAGS="-fsanitize=address $QEMU_LDFLAGS"
38
+ * provide default behaviour if its output is left floating, and
39
+ * it can use this function to identify when that is the case.
40
+ */
41
+static inline bool qemu_irq_is_connected(qemu_irq irq)
42
+{
43
+ return irq != NULL;
44
+}
45
+
46
#endif
47
--
45
--
48
2.20.1
46
2.25.1
49
50
diff view generated by jsdifflib
1
From: Kaige Li <likaige@loongson.cn>
1
The '==' operator to test is a bashism; the standard way to copmare
2
strings is '='. This causes dash to complain:
2
3
3
GCC version 4.9.4 isn't clever enough to figure out that all
4
../../configure: 681: test: linux: unexpected operator
4
execution paths in disas_ldst() that use 'fn' will have initialized
5
it first, and so it warns:
6
5
7
/home/LiKaige/qemu/target/arm/translate-a64.c: In function ‘disas_ldst’:
8
/home/LiKaige/qemu/target/arm/translate-a64.c:3392:5: error: ‘fn’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
9
fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s),
10
^
11
/home/LiKaige/qemu/target/arm/translate-a64.c:3318:22: note: ‘fn’ was declared here
12
AtomicThreeOpFn *fn;
13
^
14
15
Make it happy by initializing the variable to NULL.
16
17
Signed-off-by: Kaige Li <likaige@loongson.cn>
18
Message-id: 1596110248-7366-2-git-send-email-likaige@loongson.cn
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
[PMM: Clean up commit message and note which gcc version this was]
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Thomas Huth <thuth@redhat.com>
8
Message-id: 20220720152631.450903-6-peter.maydell@linaro.org
22
---
9
---
23
target/arm/translate-a64.c | 2 +-
10
configure | 2 +-
24
1 file changed, 1 insertion(+), 1 deletion(-)
11
1 file changed, 1 insertion(+), 1 deletion(-)
25
12
26
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
13
diff --git a/configure b/configure
27
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100755
28
--- a/target/arm/translate-a64.c
15
--- a/configure
29
+++ b/target/arm/translate-a64.c
16
+++ b/configure
30
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
17
@@ -XXX,XX +XXX,XX @@ werror=""
31
bool r = extract32(insn, 22, 1);
18
32
bool a = extract32(insn, 23, 1);
19
meson_option_build_array() {
33
TCGv_i64 tcg_rs, clean_addr;
20
printf '['
34
- AtomicThreeOpFn *fn;
21
- (if test "$targetos" == windows; then
35
+ AtomicThreeOpFn *fn = NULL;
22
+ (if test "$targetos" = windows; then
36
23
IFS=\;
37
if (is_vector || !dc_isar_feature(aa64_atomics, s)) {
24
else
38
unallocated_encoding(s);
25
IFS=:
39
--
26
--
40
2.20.1
27
2.25.1
41
42
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Alan Jian <alanjian85@gmail.com>
2
2
3
The definition of top_bit used in this function is one higher
3
This patch fixes the dedicated framebuffer mailbox interface by
4
than that used in the Arm ARM psuedo-code, which put the error
4
removing an unneeded offset. This means that we pick the framebuffer
5
indication at top_bit - 1 at the wrong place, which meant that
5
address in the same way that we do if the guest code uses the buffer
6
it wasn't visible to Auth.
6
allocate mechanism of the bcm2835_property interface (case
7
0x00040001: /* Allocate buffer */ in bcm2835_property.c).
7
8
8
Fixing the definition of top_bit requires more changes, because
9
The documentation of this mailbox interface doesn't say anything
9
its most common use is for the count of bits in top_bit:bot_bit,
10
about using parts of the request buffer address to affect the
10
which would then need to be computed as top_bit - bot_bit + 1.
11
chosen framebuffer address:
12
https://github.com/raspberrypi/firmware/wiki/Mailbox-framebuffer-interface
11
13
12
For now, prefer the minimal fix to the error indication alone.
14
Some baremetal applications like the Screen01/Screen02 examples from
15
Baking Pi tutorial[1] didn't work before this patch.
13
16
14
Fixes: 63ff0ca94cb
17
[1] https://www.cl.cam.ac.uk/projects/raspberrypi/tutorials/os/screen01.html
15
Reported-by: Derrick McKee <derrick.mckee@gmail.com>
18
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
19
Signed-off-by: Alan Jian <alanjian85@outlook.com>
17
Message-id: 20200728195706.11087-1-richard.henderson@linaro.org
20
Message-id: 20220725145838.8412-1-alanjian85@outlook.com
21
[PMM: tweaked commit message]
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
22
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
[PMM: added comment about the divergence from the pseudocode]
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
24
---
22
target/arm/pauth_helper.c | 6 +++++-
25
hw/display/bcm2835_fb.c | 3 +--
23
tests/tcg/aarch64/pauth-5.c | 33 +++++++++++++++++++++++++++++++
26
1 file changed, 1 insertion(+), 2 deletions(-)
24
tests/tcg/aarch64/Makefile.target | 2 +-
25
3 files changed, 39 insertions(+), 2 deletions(-)
26
create mode 100644 tests/tcg/aarch64/pauth-5.c
27
27
28
diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
28
diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c
29
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/pauth_helper.c
30
--- a/hw/display/bcm2835_fb.c
31
+++ b/target/arm/pauth_helper.c
31
+++ b/hw/display/bcm2835_fb.c
32
@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
32
@@ -XXX,XX +XXX,XX @@ static void bcm2835_fb_mbox_push(BCM2835FBState *s, uint32_t value)
33
*/
33
newconf.xoffset = ldl_le_phys(&s->dma_as, value + 24);
34
test = sextract64(ptr, bot_bit, top_bit - bot_bit);
34
newconf.yoffset = ldl_le_phys(&s->dma_as, value + 28);
35
if (test != 0 && test != -1) {
35
36
- pac ^= MAKE_64BIT_MASK(top_bit - 1, 1);
36
- newconf.base = s->vcram_base | (value & 0xc0000000);
37
+ /*
37
- newconf.base += BCM2835_FB_OFFSET;
38
+ * Note that our top_bit is one greater than the pseudocode's
38
+ newconf.base = s->vcram_base + BCM2835_FB_OFFSET;
39
+ * version, hence "- 2" here.
39
40
+ */
40
/* Copy fields which we don't want to change from the existing config */
41
+ pac ^= MAKE_64BIT_MASK(top_bit - 2, 1);
41
newconf.pixo = s->config.pixo;
42
}
43
44
/*
45
diff --git a/tests/tcg/aarch64/pauth-5.c b/tests/tcg/aarch64/pauth-5.c
46
new file mode 100644
47
index XXXXXXX..XXXXXXX
48
--- /dev/null
49
+++ b/tests/tcg/aarch64/pauth-5.c
50
@@ -XXX,XX +XXX,XX @@
51
+#include <assert.h>
52
+
53
+static int x;
54
+
55
+int main()
56
+{
57
+ int *p0 = &x, *p1, *p2, *p3;
58
+ unsigned long salt = 0;
59
+
60
+ /*
61
+ * With TBI enabled and a 48-bit VA, there are 7 bits of auth, and so
62
+ * a 1/128 chance of auth = pac(ptr,key,salt) producing zero.
63
+ * Find a salt that creates auth != 0.
64
+ */
65
+ do {
66
+ salt++;
67
+ asm("pacda %0, %1" : "=r"(p1) : "r"(salt), "0"(p0));
68
+ } while (p0 == p1);
69
+
70
+ /*
71
+ * This pac must fail, because the input pointer bears an encryption,
72
+ * and so is not properly extended within bits [55:47]. This will
73
+ * toggle bit 54 in the output...
74
+ */
75
+ asm("pacda %0, %1" : "=r"(p2) : "r"(salt), "0"(p1));
76
+
77
+ /* ... so that the aut must fail, setting bit 53 in the output ... */
78
+ asm("autda %0, %1" : "=r"(p3) : "r"(salt), "0"(p2));
79
+
80
+ /* ... which means this equality must not hold. */
81
+ assert(p3 != p0);
82
+ return 0;
83
+}
84
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
85
index XXXXXXX..XXXXXXX 100644
86
--- a/tests/tcg/aarch64/Makefile.target
87
+++ b/tests/tcg/aarch64/Makefile.target
88
@@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt
89
90
# Pauth Tests
91
ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_3),)
92
-AARCH64_TESTS += pauth-1 pauth-2 pauth-4
93
+AARCH64_TESTS += pauth-1 pauth-2 pauth-4 pauth-5
94
pauth-%: CFLAGS += -march=armv8.3-a
95
run-pauth-%: QEMU_OPTS += -cpu max
96
run-plugin-pauth-%: QEMU_OPTS += -cpu max
97
--
42
--
98
2.20.1
43
2.25.1
99
100
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