1 | Handful of bugfixes for rc2. None of these are particularly critical | 1 | The following changes since commit 6eeea6725a70e6fcb5abba0764496bdab07ddfb3: |
---|---|---|---|
2 | or exciting. | ||
3 | 2 | ||
4 | -- PMM | 3 | Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-10-06' into staging (2020-10-06 21:13:34 +0100) |
5 | |||
6 | The following changes since commit 45a150aa2b3492acf6691c7bdbeb25a8545d8345: | ||
7 | |||
8 | Merge remote-tracking branch 'remotes/ericb/tags/pull-bitmaps-2020-08-03' into staging (2020-08-03 15:13:49 +0100) | ||
9 | 4 | ||
10 | are available in the Git repository at: | 5 | are available in the Git repository at: |
11 | 6 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200803 | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201008 |
13 | 8 | ||
14 | for you to fetch changes up to 13557fd392890cbd985bceba7f717e01efd674b8: | 9 | for you to fetch changes up to ba118c26e16a97e6ff6de8184057d3420ce16a23: |
15 | 10 | ||
16 | hw/timer/imx_epit: Avoid assertion when CR.SWR is written (2020-08-03 17:56:11 +0100) | 11 | target/arm: Make '-cpu max' have a 48-bit PA (2020-10-08 15:24:32 +0100) |
17 | 12 | ||
18 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
19 | target-arm queue: | 14 | target-arm queue: |
20 | * hw/timer/imx_epit: Avoid assertion when CR.SWR is written | 15 | * hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer |
21 | * netduino2, netduinoplus2, microbit: set system_clock_scale so that | 16 | * hw/arm/fsl-imx25: Fix a typo |
22 | SysTick running on the CPU clock works | 17 | * hw/arm/sbsa-ref : Fix SMMUv3 Initialisation |
23 | * target/arm: Avoid maybe-uninitialized warning with gcc 4.9 | 18 | * hw/arm/sbsa-ref : allocate IRQs for SMMUv3 |
24 | * target/arm: Fix AddPAC error indication | 19 | * hw/char/bcm2835_aux: Allow less than 32-bit accesses |
25 | * Make AIRCR.SYSRESETREQ actually reset the system for the | 20 | * hw/arm/virt: Implement kvm-steal-time |
26 | microbit, mps2-*, musca-*, netduino* boards | 21 | * target/arm: Make '-cpu max' have a 48-bit PA |
27 | 22 | ||
28 | ---------------------------------------------------------------- | 23 | ---------------------------------------------------------------- |
29 | Kaige Li (1): | 24 | Andrew Jones (6): |
30 | target/arm: Avoid maybe-uninitialized warning with gcc 4.9 | 25 | linux headers: sync to 5.9-rc7 |
26 | target/arm/kvm: Make uncalled stubs explicitly unreachable | ||
27 | hw/arm/virt: Move post cpu realize check into its own function | ||
28 | hw/arm/virt: Move kvm pmu setup to virt_cpu_post_init | ||
29 | tests/qtest: Restore aarch64 arm-cpu-features test | ||
30 | hw/arm/virt: Implement kvm-steal-time | ||
31 | 31 | ||
32 | Peter Maydell (6): | 32 | Graeme Gregory (2): |
33 | hw/arm/netduino2, netduinoplus2: Set system_clock_scale | 33 | hw/arm/sbsa-ref : Fix SMMUv3 Initialisation |
34 | include/hw/irq.h: New function qemu_irq_is_connected() | 34 | hw/arm/sbsa-ref : allocate IRQs for SMMUv3 |
35 | hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for SYSRESETREQ | ||
36 | msf2-soc, stellaris: Don't wire up SYSRESETREQ | ||
37 | hw/arm/nrf51_soc: Set system_clock_scale | ||
38 | hw/timer/imx_epit: Avoid assertion when CR.SWR is written | ||
39 | 35 | ||
40 | Richard Henderson (1): | 36 | Peter Maydell (1): |
41 | target/arm: Fix AddPAC error indication | 37 | target/arm: Make '-cpu max' have a 48-bit PA |
42 | 38 | ||
43 | include/hw/arm/armv7m.h | 4 +++- | 39 | Philippe Mathieu-Daudé (3): |
44 | include/hw/irq.h | 18 ++++++++++++++++++ | 40 | hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer |
45 | hw/arm/msf2-soc.c | 11 ----------- | 41 | hw/arm/fsl-imx25: Fix a typo |
46 | hw/arm/netduino2.c | 10 ++++++++++ | 42 | hw/char/bcm2835_aux: Allow less than 32-bit accesses |
47 | hw/arm/netduinoplus2.c | 10 ++++++++++ | ||
48 | hw/arm/nrf51_soc.c | 5 +++++ | ||
49 | hw/arm/stellaris.c | 12 ------------ | ||
50 | hw/intc/armv7m_nvic.c | 17 ++++++++++++++++- | ||
51 | hw/timer/imx_epit.c | 13 ++++++++++--- | ||
52 | target/arm/pauth_helper.c | 6 +++++- | ||
53 | target/arm/translate-a64.c | 2 +- | ||
54 | tests/tcg/aarch64/pauth-5.c | 33 +++++++++++++++++++++++++++++++++ | ||
55 | tests/tcg/aarch64/Makefile.target | 2 +- | ||
56 | 13 files changed, 112 insertions(+), 31 deletions(-) | ||
57 | create mode 100644 tests/tcg/aarch64/pauth-5.c | ||
58 | 43 | ||
44 | docs/system/arm/cpu-features.rst | 11 ++++ | ||
45 | include/hw/arm/fsl-imx25.h | 2 +- | ||
46 | include/hw/arm/virt.h | 5 ++ | ||
47 | linux-headers/linux/kvm.h | 6 ++- | ||
48 | target/arm/cpu.h | 4 ++ | ||
49 | target/arm/kvm_arm.h | 94 ++++++++++++++++++++++++++------- | ||
50 | hw/arm/sbsa-ref.c | 3 +- | ||
51 | hw/arm/virt.c | 110 ++++++++++++++++++++++++++++----------- | ||
52 | hw/char/bcm2835_aux.c | 4 +- | ||
53 | hw/ssi/npcm7xx_fiu.c | 12 ++--- | ||
54 | target/arm/cpu.c | 8 +++ | ||
55 | target/arm/cpu64.c | 4 ++ | ||
56 | target/arm/kvm.c | 16 ++++++ | ||
57 | target/arm/kvm64.c | 64 +++++++++++++++++++++-- | ||
58 | target/arm/monitor.c | 2 +- | ||
59 | tests/qtest/arm-cpu-features.c | 25 +++++++-- | ||
60 | hw/ssi/trace-events | 2 +- | ||
61 | tests/qtest/meson.build | 3 +- | ||
62 | 18 files changed, 303 insertions(+), 72 deletions(-) | ||
63 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
1 | 2 | ||
3 | Fix integer handling issues handling issue reported by Coverity: | ||
4 | |||
5 | hw/ssi/npcm7xx_fiu.c: 162 in npcm7xx_fiu_flash_read() | ||
6 | >>> CID 1432730: Integer handling issues (NEGATIVE_RETURNS) | ||
7 | >>> "npcm7xx_fiu_cs_index(fiu, f)" is passed to a parameter that cannot be negative. | ||
8 | 162 npcm7xx_fiu_select(fiu, npcm7xx_fiu_cs_index(fiu, f)); | ||
9 | |||
10 | hw/ssi/npcm7xx_fiu.c: 221 in npcm7xx_fiu_flash_write() | ||
11 | 218 cs_id = npcm7xx_fiu_cs_index(fiu, f); | ||
12 | 219 trace_npcm7xx_fiu_flash_write(DEVICE(fiu)->canonical_path, cs_id, addr, | ||
13 | 220 size, v); | ||
14 | >>> CID 1432729: Integer handling issues (NEGATIVE_RETURNS) | ||
15 | >>> "cs_id" is passed to a parameter that cannot be negative. | ||
16 | 221 npcm7xx_fiu_select(fiu, cs_id); | ||
17 | |||
18 | Since the index of the flash can not be negative, return an | ||
19 | unsigned type. | ||
20 | |||
21 | Reported-by: Coverity (CID 1432729 & 1432730: NEGATIVE_RETURNS) | ||
22 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
23 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
24 | Message-id: 20200919132435.310527-1-f4bug@amsat.org | ||
25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
26 | --- | ||
27 | hw/ssi/npcm7xx_fiu.c | 12 ++++++------ | ||
28 | hw/ssi/trace-events | 2 +- | ||
29 | 2 files changed, 7 insertions(+), 7 deletions(-) | ||
30 | |||
31 | diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/hw/ssi/npcm7xx_fiu.c | ||
34 | +++ b/hw/ssi/npcm7xx_fiu.c | ||
35 | @@ -XXX,XX +XXX,XX @@ enum NPCM7xxFIURegister { | ||
36 | * Returns the index of flash in the fiu->flash array. This corresponds to the | ||
37 | * chip select ID of the flash. | ||
38 | */ | ||
39 | -static int npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, NPCM7xxFIUFlash *flash) | ||
40 | +static unsigned npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, | ||
41 | + NPCM7xxFIUFlash *flash) | ||
42 | { | ||
43 | int index = flash - fiu->flash; | ||
44 | |||
45 | @@ -XXX,XX +XXX,XX @@ static int npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, NPCM7xxFIUFlash *flash) | ||
46 | } | ||
47 | |||
48 | /* Assert the chip select specified in the UMA Control/Status Register. */ | ||
49 | -static void npcm7xx_fiu_select(NPCM7xxFIUState *s, int cs_id) | ||
50 | +static void npcm7xx_fiu_select(NPCM7xxFIUState *s, unsigned cs_id) | ||
51 | { | ||
52 | trace_npcm7xx_fiu_select(DEVICE(s)->canonical_path, cs_id); | ||
53 | |||
54 | if (cs_id < s->cs_count) { | ||
55 | qemu_irq_lower(s->cs_lines[cs_id]); | ||
56 | + s->active_cs = cs_id; | ||
57 | } else { | ||
58 | qemu_log_mask(LOG_GUEST_ERROR, | ||
59 | "%s: UMA to CS%d; this module has only %d chip selects", | ||
60 | DEVICE(s)->canonical_path, cs_id, s->cs_count); | ||
61 | - cs_id = -1; | ||
62 | + s->active_cs = -1; | ||
63 | } | ||
64 | - | ||
65 | - s->active_cs = cs_id; | ||
66 | } | ||
67 | |||
68 | /* Deassert the currently active chip select. */ | ||
69 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_flash_write(void *opaque, hwaddr addr, uint64_t v, | ||
70 | NPCM7xxFIUFlash *f = opaque; | ||
71 | NPCM7xxFIUState *fiu = f->fiu; | ||
72 | uint32_t dwr_cfg; | ||
73 | - int cs_id; | ||
74 | + unsigned cs_id; | ||
75 | int i; | ||
76 | |||
77 | if (fiu->active_cs != -1) { | ||
78 | diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events | ||
79 | index XXXXXXX..XXXXXXX 100644 | ||
80 | --- a/hw/ssi/trace-events | ||
81 | +++ b/hw/ssi/trace-events | ||
82 | @@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_deselect(const char *id, int cs) "%s deselect CS%d" | ||
83 | npcm7xx_fiu_ctrl_read(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 | ||
84 | npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 | ||
85 | npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64 | ||
86 | -npcm7xx_fiu_flash_write(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64 | ||
87 | +npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64 | ||
88 | -- | ||
89 | 2.20.1 | ||
90 | |||
91 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
1 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
4 | Message-id: 20201002080935.1660005-1-f4bug@amsat.org | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | include/hw/arm/fsl-imx25.h | 2 +- | ||
9 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
10 | |||
11 | diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/include/hw/arm/fsl-imx25.h | ||
14 | +++ b/include/hw/arm/fsl-imx25.h | ||
15 | @@ -XXX,XX +XXX,XX @@ struct FslIMX25State { | ||
16 | * 0xBB00_0000 0xBB00_0FFF 4 Kbytes NAND flash main area buffer | ||
17 | * 0xBB00_1000 0xBB00_11FF 512 B NAND flash spare area buffer | ||
18 | * 0xBB00_1200 0xBB00_1DFF 3 Kbytes Reserved | ||
19 | - * 0xBB00_1E00 0xBB00_1FFF 512 B NAND flash control regisers | ||
20 | + * 0xBB00_1E00 0xBB00_1FFF 512 B NAND flash control registers | ||
21 | * 0xBB01_2000 0xBFFF_FFFF 96 Mbytes (minus 8 Kbytes) Reserved | ||
22 | * 0xC000_0000 0xFFFF_FFFF 1024 Mbytes Reserved | ||
23 | */ | ||
24 | -- | ||
25 | 2.20.1 | ||
26 | |||
27 | diff view generated by jsdifflib |
1 | From: Kaige Li <likaige@loongson.cn> | 1 | From: Graeme Gregory <graeme@nuviainc.com> |
---|---|---|---|
2 | 2 | ||
3 | GCC version 4.9.4 isn't clever enough to figure out that all | 3 | SMMUv3 has an error in a previous patch where an i was transposed to a 1 |
4 | execution paths in disas_ldst() that use 'fn' will have initialized | 4 | meaning interrupts would not have been correctly assigned to the SMMUv3 |
5 | it first, and so it warns: | 5 | instance. |
6 | 6 | ||
7 | /home/LiKaige/qemu/target/arm/translate-a64.c: In function ‘disas_ldst’: | 7 | Fixes: 48ba18e6d3f3 ("hw/arm/sbsa-ref: Simplify by moving the gic in the machine state") |
8 | /home/LiKaige/qemu/target/arm/translate-a64.c:3392:5: error: ‘fn’ may be used uninitialized in this function [-Werror=maybe-uninitialized] | 8 | Signed-off-by: Graeme Gregory <graeme@nuviainc.com> |
9 | fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s), | 9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
10 | ^ | 10 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
11 | /home/LiKaige/qemu/target/arm/translate-a64.c:3318:22: note: ‘fn’ was declared here | 11 | Message-id: 20201007100732.4103790-2-graeme@nuviainc.com |
12 | AtomicThreeOpFn *fn; | ||
13 | ^ | ||
14 | |||
15 | Make it happy by initializing the variable to NULL. | ||
16 | |||
17 | Signed-off-by: Kaige Li <likaige@loongson.cn> | ||
18 | Message-id: 1596110248-7366-2-git-send-email-likaige@loongson.cn | ||
19 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
20 | [PMM: Clean up commit message and note which gcc version this was] | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
22 | --- | 13 | --- |
23 | target/arm/translate-a64.c | 2 +- | 14 | hw/arm/sbsa-ref.c | 2 +- |
24 | 1 file changed, 1 insertion(+), 1 deletion(-) | 15 | 1 file changed, 1 insertion(+), 1 deletion(-) |
25 | 16 | ||
26 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 17 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c |
27 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/target/arm/translate-a64.c | 19 | --- a/hw/arm/sbsa-ref.c |
29 | +++ b/target/arm/translate-a64.c | 20 | +++ b/hw/arm/sbsa-ref.c |
30 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | 21 | @@ -XXX,XX +XXX,XX @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) |
31 | bool r = extract32(insn, 22, 1); | 22 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
32 | bool a = extract32(insn, 23, 1); | 23 | for (i = 0; i < NUM_SMMU_IRQS; i++) { |
33 | TCGv_i64 tcg_rs, clean_addr; | 24 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, |
34 | - AtomicThreeOpFn *fn; | 25 | - qdev_get_gpio_in(sms->gic, irq + 1)); |
35 | + AtomicThreeOpFn *fn = NULL; | 26 | + qdev_get_gpio_in(sms->gic, irq + i)); |
36 | 27 | } | |
37 | if (is_vector || !dc_isar_feature(aa64_atomics, s)) { | 28 | } |
38 | unallocated_encoding(s); | 29 | |
39 | -- | 30 | -- |
40 | 2.20.1 | 31 | 2.20.1 |
41 | 32 | ||
42 | 33 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Graeme Gregory <graeme@nuviainc.com> | ||
1 | 2 | ||
3 | Original commit did not allocate IRQs for the SMMUv3 in the irqmap | ||
4 | effectively using irq 0->3 (shared with other devices). Assuming | ||
5 | original intent was to allocate unique IRQs then add an allocation | ||
6 | to the irqmap. | ||
7 | |||
8 | Fixes: e9fdf453240 ("hw/arm: Add arm SBSA reference machine, devices part") | ||
9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
10 | Signed-off-by: Graeme Gregory <graeme@nuviainc.com> | ||
11 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
12 | Message-id: 20201007100732.4103790-3-graeme@nuviainc.com | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | hw/arm/sbsa-ref.c | 1 + | ||
16 | 1 file changed, 1 insertion(+) | ||
17 | |||
18 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/hw/arm/sbsa-ref.c | ||
21 | +++ b/hw/arm/sbsa-ref.c | ||
22 | @@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = { | ||
23 | [SBSA_SECURE_UART_MM] = 9, | ||
24 | [SBSA_AHCI] = 10, | ||
25 | [SBSA_EHCI] = 11, | ||
26 | + [SBSA_SMMU] = 12, /* ... to 15 */ | ||
27 | }; | ||
28 | |||
29 | static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) | ||
30 | -- | ||
31 | 2.20.1 | ||
32 | |||
33 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
1 | 2 | ||
3 | The "BCM2835 ARM Peripherals" datasheet [*] chapter 2 | ||
4 | ("Auxiliaries: UART1 & SPI1, SPI2"), list the register | ||
5 | sizes as 3/8/16/32 bits. We assume this means this | ||
6 | peripheral allows 8-bit accesses. | ||
7 | |||
8 | This was not an issue until commit 5d971f9e67 which reverted | ||
9 | ("memory: accept mismatching sizes in memory_region_access_valid"). | ||
10 | |||
11 | The model is implemented as 32-bit accesses (see commit 97398d900c, | ||
12 | all registers are 32-bit) so replace MemoryRegionOps.valid as | ||
13 | MemoryRegionOps.impl, and re-introduce MemoryRegionOps.valid | ||
14 | with a 8/32-bit range. | ||
15 | |||
16 | [*] https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf | ||
17 | |||
18 | Fixes: 97398d900c ("bcm2835_aux: add emulation of BCM2835 AUX (aka UART1) block") | ||
19 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
20 | Message-id: 20201002181032.1899463-1-f4bug@amsat.org | ||
21 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
23 | --- | ||
24 | hw/char/bcm2835_aux.c | 4 +++- | ||
25 | 1 file changed, 3 insertions(+), 1 deletion(-) | ||
26 | |||
27 | diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/hw/char/bcm2835_aux.c | ||
30 | +++ b/hw/char/bcm2835_aux.c | ||
31 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps bcm2835_aux_ops = { | ||
32 | .read = bcm2835_aux_read, | ||
33 | .write = bcm2835_aux_write, | ||
34 | .endianness = DEVICE_NATIVE_ENDIAN, | ||
35 | - .valid.min_access_size = 4, | ||
36 | + .impl.min_access_size = 4, | ||
37 | + .impl.max_access_size = 4, | ||
38 | + .valid.min_access_size = 1, | ||
39 | .valid.max_access_size = 4, | ||
40 | }; | ||
41 | |||
42 | -- | ||
43 | 2.20.1 | ||
44 | |||
45 | diff view generated by jsdifflib |
1 | The netduino2 and netduinoplus2 boards forgot to set the system_clock_scale | 1 | From: Andrew Jones <drjones@redhat.com> |
---|---|---|---|
2 | global, which meant that if guest code used the systick timer in "use | ||
3 | the processor clock" mode it would hang because time never advances. | ||
4 | 2 | ||
5 | Set the global to match the documented CPU clock speed of these boards. | 3 | Update against Linux 5.9-rc7. |
6 | Judging by the data sheet this is slightly simplistic because the | ||
7 | SoC allows configuration of the SYSCLK source and frequency via the | ||
8 | RCC (reset and clock control) module, but we don't model that. | ||
9 | 4 | ||
10 | Fixes: https://bugs.launchpad.net/qemu/+bug/1876187 | 5 | Cc: Paolo Bonzini <pbonzini@redhat.com> |
6 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
7 | Message-id: 20201001061718.101915-2-drjones@redhat.com | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
13 | Message-id: 20200727162617.26227-1-peter.maydell@linaro.org | ||
14 | --- | 9 | --- |
15 | hw/arm/netduino2.c | 10 ++++++++++ | 10 | linux-headers/linux/kvm.h | 6 ++++-- |
16 | hw/arm/netduinoplus2.c | 10 ++++++++++ | 11 | 1 file changed, 4 insertions(+), 2 deletions(-) |
17 | 2 files changed, 20 insertions(+) | ||
18 | 12 | ||
19 | diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c | 13 | diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h |
20 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/arm/netduino2.c | 15 | --- a/linux-headers/linux/kvm.h |
22 | +++ b/hw/arm/netduino2.c | 16 | +++ b/linux-headers/linux/kvm.h |
23 | @@ -XXX,XX +XXX,XX @@ | 17 | @@ -XXX,XX +XXX,XX @@ struct kvm_ppc_resize_hpt { |
24 | #include "hw/arm/stm32f205_soc.h" | 18 | #define KVM_VM_PPC_HV 1 |
25 | #include "hw/arm/boot.h" | 19 | #define KVM_VM_PPC_PR 2 |
26 | 20 | ||
27 | +/* Main SYSCLK frequency in Hz (120MHz) */ | 21 | -/* on MIPS, 0 forces trap & emulate, 1 forces VZ ASE */ |
28 | +#define SYSCLK_FRQ 120000000ULL | 22 | -#define KVM_VM_MIPS_TE 0 |
29 | + | 23 | +/* on MIPS, 0 indicates auto, 1 forces VZ ASE, 2 forces trap & emulate */ |
30 | static void netduino2_init(MachineState *machine) | 24 | +#define KVM_VM_MIPS_AUTO 0 |
31 | { | 25 | #define KVM_VM_MIPS_VZ 1 |
32 | DeviceState *dev; | 26 | +#define KVM_VM_MIPS_TE 2 |
33 | 27 | ||
34 | + /* | 28 | #define KVM_S390_SIE_PAGE_OFFSET 1 |
35 | + * TODO: ideally we would model the SoC RCC and let it handle | 29 | |
36 | + * system_clock_scale, including its ability to define different | 30 | @@ -XXX,XX +XXX,XX @@ struct kvm_ppc_resize_hpt { |
37 | + * possible SYSCLK sources. | 31 | #define KVM_CAP_LAST_CPU 184 |
38 | + */ | 32 | #define KVM_CAP_SMALLER_MAXPHYADDR 185 |
39 | + system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; | 33 | #define KVM_CAP_S390_DIAG318 186 |
40 | + | 34 | +#define KVM_CAP_STEAL_TIME 187 |
41 | dev = qdev_new(TYPE_STM32F205_SOC); | 35 | |
42 | qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); | 36 | #ifdef KVM_CAP_IRQ_ROUTING |
43 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | 37 | |
44 | diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/hw/arm/netduinoplus2.c | ||
47 | +++ b/hw/arm/netduinoplus2.c | ||
48 | @@ -XXX,XX +XXX,XX @@ | ||
49 | #include "hw/arm/stm32f405_soc.h" | ||
50 | #include "hw/arm/boot.h" | ||
51 | |||
52 | +/* Main SYSCLK frequency in Hz (168MHz) */ | ||
53 | +#define SYSCLK_FRQ 168000000ULL | ||
54 | + | ||
55 | static void netduinoplus2_init(MachineState *machine) | ||
56 | { | ||
57 | DeviceState *dev; | ||
58 | |||
59 | + /* | ||
60 | + * TODO: ideally we would model the SoC RCC and let it handle | ||
61 | + * system_clock_scale, including its ability to define different | ||
62 | + * possible SYSCLK sources. | ||
63 | + */ | ||
64 | + system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; | ||
65 | + | ||
66 | dev = qdev_new(TYPE_STM32F405_SOC); | ||
67 | qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); | ||
68 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
69 | -- | 38 | -- |
70 | 2.20.1 | 39 | 2.20.1 |
71 | 40 | ||
72 | 41 | diff view generated by jsdifflib |
1 | The MSF2 SoC model and the Stellaris board code both wire | 1 | From: Andrew Jones <drjones@redhat.com> |
---|---|---|---|
2 | SYSRESETREQ up to a function that just invokes | ||
3 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | ||
4 | This is now the default action that the NVIC does if the line is | ||
5 | not connected, so we can delete the handling code. | ||
6 | 2 | ||
3 | When we compile without KVM support !defined(CONFIG_KVM) we generate | ||
4 | stubs for functions that the linker will still encounter. Sometimes | ||
5 | these stubs can be executed safely and are placed in paths where they | ||
6 | get executed with or without KVM. Other functions should never be | ||
7 | called without KVM. Those functions should be guarded by kvm_enabled(), | ||
8 | but should also be robust to refactoring mistakes. Putting a | ||
9 | g_assert_not_reached() in the function should help. Additionally, | ||
10 | the g_assert_not_reached() calls may actually help the linker remove | ||
11 | some code. | ||
12 | |||
13 | We remove the stubs for kvm_arm_get/put_virtual_time(), as they aren't | ||
14 | necessary at all - the only caller is in kvm.c | ||
15 | |||
16 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
17 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
18 | Message-id: 20201001061718.101915-3-drjones@redhat.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
10 | Message-id: 20200728103744.6909-4-peter.maydell@linaro.org | ||
11 | --- | 20 | --- |
12 | hw/arm/msf2-soc.c | 11 ----------- | 21 | target/arm/kvm_arm.h | 51 +++++++++++++++++++++++++++----------------- |
13 | hw/arm/stellaris.c | 12 ------------ | 22 | 1 file changed, 32 insertions(+), 19 deletions(-) |
14 | 2 files changed, 23 deletions(-) | ||
15 | 23 | ||
16 | diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c | 24 | diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h |
17 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/arm/msf2-soc.c | 26 | --- a/target/arm/kvm_arm.h |
19 | +++ b/hw/arm/msf2-soc.c | 27 | +++ b/target/arm/kvm_arm.h |
20 | @@ -XXX,XX +XXX,XX @@ | 28 | @@ -XXX,XX +XXX,XX @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); |
21 | #include "hw/irq.h" | 29 | |
22 | #include "hw/arm/msf2-soc.h" | 30 | #else |
23 | #include "hw/misc/unimp.h" | 31 | |
24 | -#include "sysemu/runstate.h" | 32 | -static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) |
25 | #include "sysemu/sysemu.h" | ||
26 | |||
27 | #define MSF2_TIMER_BASE 0x40004000 | ||
28 | @@ -XXX,XX +XXX,XX @@ static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 }; | ||
29 | static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 }; | ||
30 | static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 }; | ||
31 | |||
32 | -static void do_sys_reset(void *opaque, int n, int level) | ||
33 | -{ | 33 | -{ |
34 | - if (level) { | 34 | - /* |
35 | - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | 35 | - * This should never actually be called in the "not KVM" case, |
36 | - } | 36 | - * but set up the fields to indicate an error anyway. |
37 | - */ | ||
38 | - cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; | ||
39 | - cpu->host_cpu_probe_failed = true; | ||
37 | -} | 40 | -} |
38 | - | 41 | - |
39 | static void m2sxxx_soc_initfn(Object *obj) | 42 | -static inline void kvm_arm_add_vcpu_properties(Object *obj) {} |
43 | - | ||
44 | +/* | ||
45 | + * It's safe to call these functions without KVM support. | ||
46 | + * They should either do nothing or return "not supported". | ||
47 | + */ | ||
48 | static inline bool kvm_arm_aarch32_supported(void) | ||
40 | { | 49 | { |
41 | MSF2State *s = MSF2_SOC(obj); | 50 | return false; |
42 | @@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) | 51 | @@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_sve_supported(void) |
43 | return; | 52 | return false; |
44 | } | ||
45 | |||
46 | - qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0, | ||
47 | - qemu_allocate_irq(&do_sys_reset, NULL, 0)); | ||
48 | - | ||
49 | system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk; | ||
50 | |||
51 | for (i = 0; i < MSF2_NUM_UARTS; i++) { | ||
52 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/hw/arm/stellaris.c | ||
55 | +++ b/hw/arm/stellaris.c | ||
56 | @@ -XXX,XX +XXX,XX @@ | ||
57 | #include "hw/boards.h" | ||
58 | #include "qemu/log.h" | ||
59 | #include "exec/address-spaces.h" | ||
60 | -#include "sysemu/runstate.h" | ||
61 | #include "sysemu/sysemu.h" | ||
62 | #include "hw/arm/armv7m.h" | ||
63 | #include "hw/char/pl011.h" | ||
64 | @@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj) | ||
65 | qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); | ||
66 | } | 53 | } |
67 | 54 | ||
68 | -static | 55 | +/* |
69 | -void do_sys_reset(void *opaque, int n, int level) | 56 | + * These functions should never actually be called without KVM support. |
70 | -{ | 57 | + */ |
71 | - if (level) { | 58 | +static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) |
72 | - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | 59 | +{ |
73 | - } | 60 | + g_assert_not_reached(); |
74 | -} | 61 | +} |
75 | - | 62 | + |
76 | /* Board init. */ | 63 | +static inline void kvm_arm_add_vcpu_properties(Object *obj) |
77 | static stellaris_board_info stellaris_boards[] = { | 64 | +{ |
78 | { "LM3S811EVB", | 65 | + g_assert_not_reached(); |
79 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | 66 | +} |
80 | /* This will exit with an error if the user passed us a bad cpu_type */ | 67 | + |
81 | sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); | 68 | static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms) |
82 | 69 | { | |
83 | - qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, | 70 | - return -ENOENT; |
84 | - qemu_allocate_irq(&do_sys_reset, NULL, 0)); | 71 | + g_assert_not_reached(); |
85 | - | 72 | } |
86 | if (board->dc1 & (1 << 16)) { | 73 | |
87 | dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, | 74 | static inline int kvm_arm_vgic_probe(void) |
88 | qdev_get_gpio_in(nvic, 14), | 75 | { |
76 | - return 0; | ||
77 | + g_assert_not_reached(); | ||
78 | } | ||
79 | |||
80 | -static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {} | ||
81 | -static inline void kvm_arm_pmu_init(CPUState *cs) {} | ||
82 | +static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) | ||
83 | +{ | ||
84 | + g_assert_not_reached(); | ||
85 | +} | ||
86 | |||
87 | -static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {} | ||
88 | +static inline void kvm_arm_pmu_init(CPUState *cs) | ||
89 | +{ | ||
90 | + g_assert_not_reached(); | ||
91 | +} | ||
92 | + | ||
93 | +static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) | ||
94 | +{ | ||
95 | + g_assert_not_reached(); | ||
96 | +} | ||
97 | |||
98 | -static inline void kvm_arm_get_virtual_time(CPUState *cs) {} | ||
99 | -static inline void kvm_arm_put_virtual_time(CPUState *cs) {} | ||
100 | #endif | ||
101 | |||
102 | static inline const char *gic_class_name(void) | ||
89 | -- | 103 | -- |
90 | 2.20.1 | 104 | 2.20.1 |
91 | 105 | ||
92 | 106 | diff view generated by jsdifflib |
1 | The NVIC provides an outbound qemu_irq "SYSRESETREQ" which it signals | 1 | From: Andrew Jones <drjones@redhat.com> |
---|---|---|---|
2 | when the guest sets the SYSRESETREQ bit in the AIRCR register. This | ||
3 | matches the hardware design (where the CPU has a signal of this name | ||
4 | and it is up to the SoC to connect that up to an actual reset | ||
5 | mechanism), but in QEMU it mostly results in duplicated code in SoC | ||
6 | objects and bugs where SoC model implementors forget to wire up the | ||
7 | SYSRESETREQ line. | ||
8 | 2 | ||
9 | Provide a default behaviour for the case where SYSRESETREQ is not | 3 | We'll add more to this new function in coming patches so we also |
10 | actually connected to anything: use qemu_system_reset_request() to | 4 | state the gic must be created and call it below create_gic(). |
11 | perform a system reset. This will allow us to remove the | ||
12 | implementations of SYSRESETREQ handling from the boards where that's | ||
13 | exactly what it does, and also fixes the bugs in the board models | ||
14 | which forgot to wire up the signal: | ||
15 | 5 | ||
16 | * microbit | 6 | No functional change intended. |
17 | * mps2-an385 | ||
18 | * mps2-an505 | ||
19 | * mps2-an511 | ||
20 | * mps2-an521 | ||
21 | * musca-a | ||
22 | * musca-b1 | ||
23 | * netduino | ||
24 | * netduinoplus2 | ||
25 | 7 | ||
26 | We still allow the board to wire up the signal if it needs to, in case | 8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
27 | we need to model more complicated reset controller logic or to model | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
28 | buggy SoC hardware which forgot to wire up the line itself. But | 10 | Signed-off-by: Andrew Jones <drjones@redhat.com> |
29 | defaulting to "reset the system" is more often going to be correct | 11 | Message-id: 20201001061718.101915-4-drjones@redhat.com |
30 | than defaulting to "do nothing". | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | ||
14 | hw/arm/virt.c | 43 +++++++++++++++++++++++++++---------------- | ||
15 | 1 file changed, 27 insertions(+), 16 deletions(-) | ||
31 | 16 | ||
32 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
33 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
34 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
35 | Message-id: 20200728103744.6909-3-peter.maydell@linaro.org | ||
36 | --- | ||
37 | include/hw/arm/armv7m.h | 4 +++- | ||
38 | hw/intc/armv7m_nvic.c | 17 ++++++++++++++++- | ||
39 | 2 files changed, 19 insertions(+), 2 deletions(-) | ||
40 | |||
41 | diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h | ||
42 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
43 | --- a/include/hw/arm/armv7m.h | 19 | --- a/hw/arm/virt.c |
44 | +++ b/include/hw/arm/armv7m.h | 20 | +++ b/hw/arm/virt.c |
45 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 21 | @@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms) |
46 | 22 | } | |
47 | /* ARMv7M container object. | 23 | } |
48 | * + Unnamed GPIO input lines: external IRQ lines for the NVIC | 24 | |
49 | - * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ | 25 | +/* |
50 | + * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ. | 26 | + * virt_cpu_post_init() must be called after the CPUs have |
51 | + * If this GPIO is not wired up then the NVIC will default to performing | 27 | + * been realized and the GIC has been created. |
52 | + * a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET). | 28 | + */ |
53 | * + Property "cpu-type": CPU type to instantiate | 29 | +static void virt_cpu_post_init(VirtMachineState *vms) |
54 | * + Property "num-irq": number of external IRQ lines | ||
55 | * + Property "memory": MemoryRegion defining the physical address space | ||
56 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/hw/intc/armv7m_nvic.c | ||
59 | +++ b/hw/intc/armv7m_nvic.c | ||
60 | @@ -XXX,XX +XXX,XX @@ | ||
61 | #include "hw/intc/armv7m_nvic.h" | ||
62 | #include "hw/irq.h" | ||
63 | #include "hw/qdev-properties.h" | ||
64 | +#include "sysemu/runstate.h" | ||
65 | #include "target/arm/cpu.h" | ||
66 | #include "exec/exec-all.h" | ||
67 | #include "exec/memop.h" | ||
68 | @@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = { | ||
69 | 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 | ||
70 | }; | ||
71 | |||
72 | +static void signal_sysresetreq(NVICState *s) | ||
73 | +{ | 30 | +{ |
74 | + if (qemu_irq_is_connected(s->sysresetreq)) { | 31 | + bool aarch64; |
75 | + qemu_irq_pulse(s->sysresetreq); | 32 | + |
76 | + } else { | 33 | + aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); |
77 | + /* | 34 | + |
78 | + * Default behaviour if the SoC doesn't need to wire up | 35 | + if (!kvm_enabled()) { |
79 | + * SYSRESETREQ (eg to a system reset controller of some kind): | 36 | + if (aarch64 && vms->highmem) { |
80 | + * perform a system reset via the usual QEMU API. | 37 | + int requested_pa_size = 64 - clz64(vms->highest_gpa); |
81 | + */ | 38 | + int pamax = arm_pamax(ARM_CPU(first_cpu)); |
82 | + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | 39 | + |
40 | + if (pamax < requested_pa_size) { | ||
41 | + error_report("VCPU supports less PA bits (%d) than " | ||
42 | + "requested by the memory map (%d)", | ||
43 | + pamax, requested_pa_size); | ||
44 | + exit(1); | ||
45 | + } | ||
46 | + } | ||
83 | + } | 47 | + } |
84 | +} | 48 | +} |
85 | + | 49 | + |
86 | static int nvic_pending_prio(NVICState *s) | 50 | static void machvirt_init(MachineState *machine) |
87 | { | 51 | { |
88 | /* return the group priority of the current pending interrupt, | 52 | VirtMachineState *vms = VIRT_MACHINE(machine); |
89 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | 53 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) |
90 | if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) { | 54 | fdt_add_timer_nodes(vms); |
91 | if (attrs.secure || | 55 | fdt_add_cpu_nodes(vms); |
92 | !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) { | 56 | |
93 | - qemu_irq_pulse(s->sysresetreq); | 57 | - if (!kvm_enabled()) { |
94 | + signal_sysresetreq(s); | 58 | - ARMCPU *cpu = ARM_CPU(first_cpu); |
95 | } | 59 | - bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL); |
96 | } | 60 | - |
97 | if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) { | 61 | - if (aarch64 && vms->highmem) { |
62 | - int requested_pa_size, pamax = arm_pamax(cpu); | ||
63 | - | ||
64 | - requested_pa_size = 64 - clz64(vms->highest_gpa); | ||
65 | - if (pamax < requested_pa_size) { | ||
66 | - error_report("VCPU supports less PA bits (%d) than requested " | ||
67 | - "by the memory map (%d)", pamax, requested_pa_size); | ||
68 | - exit(1); | ||
69 | - } | ||
70 | - } | ||
71 | - } | ||
72 | - | ||
73 | memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, | ||
74 | machine->ram); | ||
75 | if (machine->device_memory) { | ||
76 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
77 | |||
78 | create_gic(vms); | ||
79 | |||
80 | + virt_cpu_post_init(vms); | ||
81 | + | ||
82 | fdt_add_pmu_nodes(vms); | ||
83 | |||
84 | create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); | ||
98 | -- | 85 | -- |
99 | 2.20.1 | 86 | 2.20.1 |
100 | 87 | ||
101 | 88 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Andrew Jones <drjones@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | The definition of top_bit used in this function is one higher | 3 | Move the KVM PMU setup part of fdt_add_pmu_nodes() to |
4 | than that used in the Arm ARM psuedo-code, which put the error | 4 | virt_cpu_post_init(), which is a more appropriate location. Now |
5 | indication at top_bit - 1 at the wrong place, which meant that | 5 | fdt_add_pmu_nodes() is also named more appropriately, because it |
6 | it wasn't visible to Auth. | 6 | no longer does anything but fdt node creation. |
7 | 7 | ||
8 | Fixing the definition of top_bit requires more changes, because | 8 | No functional change intended. |
9 | its most common use is for the count of bits in top_bit:bot_bit, | ||
10 | which would then need to be computed as top_bit - bot_bit + 1. | ||
11 | 9 | ||
12 | For now, prefer the minimal fix to the error indication alone. | ||
13 | |||
14 | Fixes: 63ff0ca94cb | ||
15 | Reported-by: Derrick McKee <derrick.mckee@gmail.com> | ||
16 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
17 | Message-id: 20200728195706.11087-1-richard.henderson@linaro.org | ||
18 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
19 | [PMM: added comment about the divergence from the pseudocode] | 11 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
12 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
13 | Message-id: 20201001061718.101915-5-drjones@redhat.com | ||
20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
21 | --- | 15 | --- |
22 | target/arm/pauth_helper.c | 6 +++++- | 16 | hw/arm/virt.c | 34 ++++++++++++++++++---------------- |
23 | tests/tcg/aarch64/pauth-5.c | 33 +++++++++++++++++++++++++++++++ | 17 | 1 file changed, 18 insertions(+), 16 deletions(-) |
24 | tests/tcg/aarch64/Makefile.target | 2 +- | ||
25 | 3 files changed, 39 insertions(+), 2 deletions(-) | ||
26 | create mode 100644 tests/tcg/aarch64/pauth-5.c | ||
27 | 18 | ||
28 | diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c | 19 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
29 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/target/arm/pauth_helper.c | 21 | --- a/hw/arm/virt.c |
31 | +++ b/target/arm/pauth_helper.c | 22 | +++ b/hw/arm/virt.c |
32 | @@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, | 23 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_gic_node(VirtMachineState *vms) |
33 | */ | 24 | |
34 | test = sextract64(ptr, bot_bit, top_bit - bot_bit); | 25 | static void fdt_add_pmu_nodes(const VirtMachineState *vms) |
35 | if (test != 0 && test != -1) { | 26 | { |
36 | - pac ^= MAKE_64BIT_MASK(top_bit - 1, 1); | 27 | - CPUState *cpu; |
37 | + /* | 28 | - ARMCPU *armcpu; |
38 | + * Note that our top_bit is one greater than the pseudocode's | 29 | + ARMCPU *armcpu = ARM_CPU(first_cpu); |
39 | + * version, hence "- 2" here. | 30 | uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; |
40 | + */ | 31 | |
41 | + pac ^= MAKE_64BIT_MASK(top_bit - 2, 1); | 32 | - CPU_FOREACH(cpu) { |
33 | - armcpu = ARM_CPU(cpu); | ||
34 | - if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { | ||
35 | - return; | ||
36 | - } | ||
37 | - if (kvm_enabled()) { | ||
38 | - if (kvm_irqchip_in_kernel()) { | ||
39 | - kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); | ||
40 | - } | ||
41 | - kvm_arm_pmu_init(cpu); | ||
42 | - } | ||
43 | + if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { | ||
44 | + assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); | ||
45 | + return; | ||
42 | } | 46 | } |
43 | 47 | ||
44 | /* | 48 | if (vms->gic_version == VIRT_GIC_VERSION_2) { |
45 | diff --git a/tests/tcg/aarch64/pauth-5.c b/tests/tcg/aarch64/pauth-5.c | 49 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms) |
46 | new file mode 100644 | 50 | (1 << vms->smp_cpus) - 1); |
47 | index XXXXXXX..XXXXXXX | 51 | } |
48 | --- /dev/null | 52 | |
49 | +++ b/tests/tcg/aarch64/pauth-5.c | 53 | - armcpu = ARM_CPU(qemu_get_cpu(0)); |
50 | @@ -XXX,XX +XXX,XX @@ | 54 | qemu_fdt_add_subnode(vms->fdt, "/pmu"); |
51 | +#include <assert.h> | 55 | if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { |
52 | + | 56 | const char compat[] = "arm,armv8-pmuv3"; |
53 | +static int x; | 57 | @@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms) |
54 | + | 58 | */ |
55 | +int main() | 59 | static void virt_cpu_post_init(VirtMachineState *vms) |
56 | +{ | 60 | { |
57 | + int *p0 = &x, *p1, *p2, *p3; | 61 | - bool aarch64; |
58 | + unsigned long salt = 0; | 62 | + bool aarch64, pmu; |
59 | + | 63 | + CPUState *cpu; |
60 | + /* | 64 | |
61 | + * With TBI enabled and a 48-bit VA, there are 7 bits of auth, and so | 65 | aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); |
62 | + * a 1/128 chance of auth = pac(ptr,key,salt) producing zero. | 66 | + pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); |
63 | + * Find a salt that creates auth != 0. | 67 | |
64 | + */ | 68 | - if (!kvm_enabled()) { |
65 | + do { | 69 | + if (kvm_enabled()) { |
66 | + salt++; | 70 | + CPU_FOREACH(cpu) { |
67 | + asm("pacda %0, %1" : "=r"(p1) : "r"(salt), "0"(p0)); | 71 | + if (pmu) { |
68 | + } while (p0 == p1); | 72 | + assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); |
69 | + | 73 | + if (kvm_irqchip_in_kernel()) { |
70 | + /* | 74 | + kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); |
71 | + * This pac must fail, because the input pointer bears an encryption, | 75 | + } |
72 | + * and so is not properly extended within bits [55:47]. This will | 76 | + kvm_arm_pmu_init(cpu); |
73 | + * toggle bit 54 in the output... | 77 | + } |
74 | + */ | 78 | + } |
75 | + asm("pacda %0, %1" : "=r"(p2) : "r"(salt), "0"(p1)); | 79 | + } else { |
76 | + | 80 | if (aarch64 && vms->highmem) { |
77 | + /* ... so that the aut must fail, setting bit 53 in the output ... */ | 81 | int requested_pa_size = 64 - clz64(vms->highest_gpa); |
78 | + asm("autda %0, %1" : "=r"(p3) : "r"(salt), "0"(p2)); | 82 | int pamax = arm_pamax(ARM_CPU(first_cpu)); |
79 | + | ||
80 | + /* ... which means this equality must not hold. */ | ||
81 | + assert(p3 != p0); | ||
82 | + return 0; | ||
83 | +} | ||
84 | diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target | ||
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/tests/tcg/aarch64/Makefile.target | ||
87 | +++ b/tests/tcg/aarch64/Makefile.target | ||
88 | @@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt | ||
89 | |||
90 | # Pauth Tests | ||
91 | ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_3),) | ||
92 | -AARCH64_TESTS += pauth-1 pauth-2 pauth-4 | ||
93 | +AARCH64_TESTS += pauth-1 pauth-2 pauth-4 pauth-5 | ||
94 | pauth-%: CFLAGS += -march=armv8.3-a | ||
95 | run-pauth-%: QEMU_OPTS += -cpu max | ||
96 | run-plugin-pauth-%: QEMU_OPTS += -cpu max | ||
97 | -- | 83 | -- |
98 | 2.20.1 | 84 | 2.20.1 |
99 | 85 | ||
100 | 86 | diff view generated by jsdifflib |
1 | The imx_epit device has a software-controllable reset triggered by | 1 | From: Andrew Jones <drjones@redhat.com> |
---|---|---|---|
2 | setting the SWR bit in the CR register. An error in commit cc2722ec83ad9 | ||
3 | means that we will end up assert()ing if the guest does this, because | ||
4 | the code in imx_epit_write() starts ptimer transactions, and then | ||
5 | imx_epit_reset() also starts ptimer transactions, triggering | ||
6 | "ptimer_transaction_begin: Assertion `!s->in_transaction' failed". | ||
7 | 2 | ||
8 | The cleanest way to avoid this double-transaction is to move the | 3 | arm-cpu-features got dropped from the AArch64 tests during the meson |
9 | start-transaction for the CR write handling down below the check of | 4 | conversion shuffle. |
10 | the SWR bit. | ||
11 | 5 | ||
12 | Fixes: https://bugs.launchpad.net/qemu/+bug/1880424 | 6 | Signed-off-by: Andrew Jones <drjones@redhat.com> |
13 | Fixes: cc2722ec83ad944505fe | 7 | Message-id: 20201001061718.101915-6-drjones@redhat.com |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
16 | Message-id: 20200727154550.3409-1-peter.maydell@linaro.org | ||
17 | --- | 10 | --- |
18 | hw/timer/imx_epit.c | 13 ++++++++++--- | 11 | tests/qtest/meson.build | 3 ++- |
19 | 1 file changed, 10 insertions(+), 3 deletions(-) | 12 | 1 file changed, 2 insertions(+), 1 deletion(-) |
20 | 13 | ||
21 | diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c | 14 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build |
22 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/timer/imx_epit.c | 16 | --- a/tests/qtest/meson.build |
24 | +++ b/hw/timer/imx_epit.c | 17 | +++ b/tests/qtest/meson.build |
25 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, | 18 | @@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \ |
26 | 19 | (cpu != 'arm' ? ['bios-tables-test'] : []) + \ | |
27 | switch (offset >> 2) { | 20 | (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \ |
28 | case 0: /* CR */ | 21 | (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \ |
29 | - ptimer_transaction_begin(s->timer_cmp); | 22 | - ['numa-test', |
30 | - ptimer_transaction_begin(s->timer_reload); | 23 | + ['arm-cpu-features', |
31 | 24 | + 'numa-test', | |
32 | oldcr = s->cr; | 25 | 'boot-serial-test', |
33 | s->cr = value & 0x03ffffff; | 26 | 'migration-test'] |
34 | if (s->cr & CR_SWR) { | ||
35 | /* handle the reset */ | ||
36 | imx_epit_reset(DEVICE(s)); | ||
37 | - } else { | ||
38 | + /* | ||
39 | + * TODO: could we 'break' here? following operations appear | ||
40 | + * to duplicate the work imx_epit_reset() already did. | ||
41 | + */ | ||
42 | + } | ||
43 | + | ||
44 | + ptimer_transaction_begin(s->timer_cmp); | ||
45 | + ptimer_transaction_begin(s->timer_reload); | ||
46 | + | ||
47 | + if (!(s->cr & CR_SWR)) { | ||
48 | imx_epit_set_freq(s); | ||
49 | } | ||
50 | 27 | ||
51 | -- | 28 | -- |
52 | 2.20.1 | 29 | 2.20.1 |
53 | 30 | ||
54 | 31 | diff view generated by jsdifflib |
1 | The nrf51 SoC model wasn't setting the system_clock_scale | 1 | From: Andrew Jones <drjones@redhat.com> |
---|---|---|---|
2 | global.which meant that if guest code used the systick timer in "use | ||
3 | the processor clock" mode it would hang because time never advances. | ||
4 | 2 | ||
5 | Set the global to match the documented CPU clock speed for this SoC. | 3 | We add the kvm-steal-time CPU property and implement it for machvirt. |
4 | A tiny bit of refactoring was also done to allow pmu and pvtime to | ||
5 | use the same vcpu device helper functions. | ||
6 | 6 | ||
7 | This SoC in fact doesn't have a SysTick timer (which is the only thing | 7 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
8 | currently that cares about the system_clock_scale), because it's | 8 | Signed-off-by: Andrew Jones <drjones@redhat.com> |
9 | a configurable option in the Cortex-M0. However our Cortex-M0 and | 9 | Message-id: 20201001061718.101915-7-drjones@redhat.com |
10 | thus our nrf51 and our micro:bit board do provide a SysTick, so | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | we ought to provide a functional one rather than a broken one. | 11 | --- |
12 | docs/system/arm/cpu-features.rst | 11 ++++++ | ||
13 | include/hw/arm/virt.h | 5 +++ | ||
14 | target/arm/cpu.h | 4 ++ | ||
15 | target/arm/kvm_arm.h | 43 +++++++++++++++++++++ | ||
16 | hw/arm/virt.c | 43 +++++++++++++++++++-- | ||
17 | target/arm/cpu.c | 8 ++++ | ||
18 | target/arm/kvm.c | 16 ++++++++ | ||
19 | target/arm/kvm64.c | 64 +++++++++++++++++++++++++++++--- | ||
20 | target/arm/monitor.c | 2 +- | ||
21 | tests/qtest/arm-cpu-features.c | 25 +++++++++++-- | ||
22 | 10 files changed, 208 insertions(+), 13 deletions(-) | ||
12 | 23 | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst |
14 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 25 | index XXXXXXX..XXXXXXX 100644 |
15 | Message-id: 20200727193458.31250-1-peter.maydell@linaro.org | 26 | --- a/docs/system/arm/cpu-features.rst |
16 | --- | 27 | +++ b/docs/system/arm/cpu-features.rst |
17 | hw/arm/nrf51_soc.c | 5 +++++ | 28 | @@ -XXX,XX +XXX,XX @@ the list of KVM VCPU features and their descriptions. |
18 | 1 file changed, 5 insertions(+) | 29 | adjustment, also restoring the legacy (pre-5.0) |
19 | 30 | behavior. | |
20 | diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c | 31 | |
21 | index XXXXXXX..XXXXXXX 100644 | 32 | + kvm-steal-time Since v5.2, kvm-steal-time is enabled by |
22 | --- a/hw/arm/nrf51_soc.c | 33 | + default when KVM is enabled, the feature is |
23 | +++ b/hw/arm/nrf51_soc.c | 34 | + supported, and the guest is 64-bit. |
35 | + | ||
36 | + When kvm-steal-time is enabled a 64-bit guest | ||
37 | + can account for time its CPUs were not running | ||
38 | + due to the host not scheduling the corresponding | ||
39 | + VCPU threads. The accounting statistics may | ||
40 | + influence the guest scheduler behavior and/or be | ||
41 | + exposed to the guest userspace. | ||
42 | + | ||
43 | SVE CPU Properties | ||
44 | ================== | ||
45 | |||
46 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/include/hw/arm/virt.h | ||
49 | +++ b/include/hw/arm/virt.h | ||
24 | @@ -XXX,XX +XXX,XX @@ | 50 | @@ -XXX,XX +XXX,XX @@ |
25 | 51 | ||
26 | #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) | 52 | #define PPI(irq) ((irq) + 16) |
27 | 53 | ||
28 | +/* HCLK (the main CPU clock) on this SoC is always 16MHz */ | 54 | +/* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */ |
29 | +#define HCLK_FRQ 16000000 | 55 | +#define PVTIME_SIZE_PER_CPU 64 |
30 | + | 56 | + |
31 | static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) | 57 | enum { |
32 | { | 58 | VIRT_FLASH, |
33 | qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", | 59 | VIRT_MEM, |
34 | @@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) | 60 | @@ -XXX,XX +XXX,XX @@ enum { |
61 | VIRT_PCDIMM_ACPI, | ||
62 | VIRT_ACPI_GED, | ||
63 | VIRT_NVDIMM_ACPI, | ||
64 | + VIRT_PVTIME, | ||
65 | VIRT_LOWMEMMAP_LAST, | ||
66 | }; | ||
67 | |||
68 | @@ -XXX,XX +XXX,XX @@ struct VirtMachineClass { | ||
69 | bool no_highmem_ecam; | ||
70 | bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */ | ||
71 | bool kvm_no_adjvtime; | ||
72 | + bool no_kvm_steal_time; | ||
73 | bool acpi_expose_flash; | ||
74 | }; | ||
75 | |||
76 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
77 | index XXXXXXX..XXXXXXX 100644 | ||
78 | --- a/target/arm/cpu.h | ||
79 | +++ b/target/arm/cpu.h | ||
80 | @@ -XXX,XX +XXX,XX @@ | ||
81 | #include "hw/registerfields.h" | ||
82 | #include "cpu-qom.h" | ||
83 | #include "exec/cpu-defs.h" | ||
84 | +#include "qapi/qapi-types-common.h" | ||
85 | |||
86 | /* ARM processors have a weak memory model */ | ||
87 | #define TCG_GUEST_DEFAULT_MO (0) | ||
88 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | ||
89 | bool kvm_vtime_dirty; | ||
90 | uint64_t kvm_vtime; | ||
91 | |||
92 | + /* KVM steal time */ | ||
93 | + OnOffAuto kvm_steal_time; | ||
94 | + | ||
95 | /* Uniprocessor system with MP extensions */ | ||
96 | bool mp_is_up; | ||
97 | |||
98 | diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h | ||
99 | index XXXXXXX..XXXXXXX 100644 | ||
100 | --- a/target/arm/kvm_arm.h | ||
101 | +++ b/target/arm/kvm_arm.h | ||
102 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); | ||
103 | */ | ||
104 | void kvm_arm_add_vcpu_properties(Object *obj); | ||
105 | |||
106 | +/** | ||
107 | + * kvm_arm_steal_time_finalize: | ||
108 | + * @cpu: ARMCPU for which to finalize kvm-steal-time | ||
109 | + * @errp: Pointer to Error* for error propagation | ||
110 | + * | ||
111 | + * Validate the kvm-steal-time property selection and set its default | ||
112 | + * based on KVM support and guest configuration. | ||
113 | + */ | ||
114 | +void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp); | ||
115 | + | ||
116 | +/** | ||
117 | + * kvm_arm_steal_time_supported: | ||
118 | + * | ||
119 | + * Returns: true if KVM can enable steal time reporting | ||
120 | + * and false otherwise. | ||
121 | + */ | ||
122 | +bool kvm_arm_steal_time_supported(void); | ||
123 | + | ||
124 | /** | ||
125 | * kvm_arm_aarch32_supported: | ||
126 | * | ||
127 | @@ -XXX,XX +XXX,XX @@ int kvm_arm_vgic_probe(void); | ||
128 | |||
129 | void kvm_arm_pmu_set_irq(CPUState *cs, int irq); | ||
130 | void kvm_arm_pmu_init(CPUState *cs); | ||
131 | + | ||
132 | +/** | ||
133 | + * kvm_arm_pvtime_init: | ||
134 | + * @cs: CPUState | ||
135 | + * @ipa: Per-vcpu guest physical base address of the pvtime structures | ||
136 | + * | ||
137 | + * Initializes PVTIME for the VCPU, setting the PVTIME IPA to @ipa. | ||
138 | + */ | ||
139 | +void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa); | ||
140 | + | ||
141 | int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); | ||
142 | |||
143 | #else | ||
144 | @@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_sve_supported(void) | ||
145 | return false; | ||
146 | } | ||
147 | |||
148 | +static inline bool kvm_arm_steal_time_supported(void) | ||
149 | +{ | ||
150 | + return false; | ||
151 | +} | ||
152 | + | ||
153 | /* | ||
154 | * These functions should never actually be called without KVM support. | ||
155 | */ | ||
156 | @@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_pmu_init(CPUState *cs) | ||
157 | g_assert_not_reached(); | ||
158 | } | ||
159 | |||
160 | +static inline void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) | ||
161 | +{ | ||
162 | + g_assert_not_reached(); | ||
163 | +} | ||
164 | + | ||
165 | +static inline void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) | ||
166 | +{ | ||
167 | + g_assert_not_reached(); | ||
168 | +} | ||
169 | + | ||
170 | static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) | ||
171 | { | ||
172 | g_assert_not_reached(); | ||
173 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
174 | index XXXXXXX..XXXXXXX 100644 | ||
175 | --- a/hw/arm/virt.c | ||
176 | +++ b/hw/arm/virt.c | ||
177 | @@ -XXX,XX +XXX,XX @@ static const MemMapEntry base_memmap[] = { | ||
178 | [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, | ||
179 | [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, | ||
180 | [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, | ||
181 | + [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, | ||
182 | [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, | ||
183 | /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ | ||
184 | [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, | ||
185 | @@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms) | ||
186 | * virt_cpu_post_init() must be called after the CPUs have | ||
187 | * been realized and the GIC has been created. | ||
188 | */ | ||
189 | -static void virt_cpu_post_init(VirtMachineState *vms) | ||
190 | +static void virt_cpu_post_init(VirtMachineState *vms, int max_cpus, | ||
191 | + MemoryRegion *sysmem) | ||
192 | { | ||
193 | - bool aarch64, pmu; | ||
194 | + bool aarch64, pmu, steal_time; | ||
195 | CPUState *cpu; | ||
196 | |||
197 | aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); | ||
198 | pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); | ||
199 | + steal_time = object_property_get_bool(OBJECT(first_cpu), | ||
200 | + "kvm-steal-time", NULL); | ||
201 | |||
202 | if (kvm_enabled()) { | ||
203 | + hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; | ||
204 | + hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; | ||
205 | + | ||
206 | + if (steal_time) { | ||
207 | + MemoryRegion *pvtime = g_new(MemoryRegion, 1); | ||
208 | + hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; | ||
209 | + | ||
210 | + /* The memory region size must be a multiple of host page size. */ | ||
211 | + pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); | ||
212 | + | ||
213 | + if (pvtime_size > pvtime_reg_size) { | ||
214 | + error_report("pvtime requires a %ld byte memory region for " | ||
215 | + "%d CPUs, but only %ld has been reserved", | ||
216 | + pvtime_size, max_cpus, pvtime_reg_size); | ||
217 | + exit(1); | ||
218 | + } | ||
219 | + | ||
220 | + memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); | ||
221 | + memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); | ||
222 | + } | ||
223 | + | ||
224 | CPU_FOREACH(cpu) { | ||
225 | if (pmu) { | ||
226 | assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); | ||
227 | @@ -XXX,XX +XXX,XX @@ static void virt_cpu_post_init(VirtMachineState *vms) | ||
228 | } | ||
229 | kvm_arm_pmu_init(cpu); | ||
230 | } | ||
231 | + if (steal_time) { | ||
232 | + kvm_arm_pvtime_init(cpu, pvtime_reg_base + | ||
233 | + cpu->cpu_index * PVTIME_SIZE_PER_CPU); | ||
234 | + } | ||
235 | } | ||
236 | } else { | ||
237 | if (aarch64 && vms->highmem) { | ||
238 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
239 | object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); | ||
240 | } | ||
241 | |||
242 | + if (vmc->no_kvm_steal_time && | ||
243 | + object_property_find(cpuobj, "kvm-steal-time")) { | ||
244 | + object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); | ||
245 | + } | ||
246 | + | ||
247 | if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { | ||
248 | object_property_set_bool(cpuobj, "pmu", false, NULL); | ||
249 | } | ||
250 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
251 | |||
252 | create_gic(vms); | ||
253 | |||
254 | - virt_cpu_post_init(vms); | ||
255 | + virt_cpu_post_init(vms, possible_cpus->len, sysmem); | ||
256 | |||
257 | fdt_add_pmu_nodes(vms); | ||
258 | |||
259 | @@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 2) | ||
260 | |||
261 | static void virt_machine_5_1_options(MachineClass *mc) | ||
262 | { | ||
263 | + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); | ||
264 | + | ||
265 | virt_machine_5_2_options(mc); | ||
266 | compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); | ||
267 | + vmc->no_kvm_steal_time = true; | ||
268 | } | ||
269 | DEFINE_VIRT_MACHINE(5, 1) | ||
270 | |||
271 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
272 | index XXXXXXX..XXXXXXX 100644 | ||
273 | --- a/target/arm/cpu.c | ||
274 | +++ b/target/arm/cpu.c | ||
275 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) | ||
276 | return; | ||
277 | } | ||
278 | } | ||
279 | + | ||
280 | + if (kvm_enabled()) { | ||
281 | + kvm_arm_steal_time_finalize(cpu, &local_err); | ||
282 | + if (local_err != NULL) { | ||
283 | + error_propagate(errp, local_err); | ||
284 | + return; | ||
285 | + } | ||
286 | + } | ||
287 | } | ||
288 | |||
289 | static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
290 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | ||
291 | index XXXXXXX..XXXXXXX 100644 | ||
292 | --- a/target/arm/kvm.c | ||
293 | +++ b/target/arm/kvm.c | ||
294 | @@ -XXX,XX +XXX,XX @@ static void kvm_no_adjvtime_set(Object *obj, bool value, Error **errp) | ||
295 | ARM_CPU(obj)->kvm_adjvtime = !value; | ||
296 | } | ||
297 | |||
298 | +static bool kvm_steal_time_get(Object *obj, Error **errp) | ||
299 | +{ | ||
300 | + return ARM_CPU(obj)->kvm_steal_time != ON_OFF_AUTO_OFF; | ||
301 | +} | ||
302 | + | ||
303 | +static void kvm_steal_time_set(Object *obj, bool value, Error **errp) | ||
304 | +{ | ||
305 | + ARM_CPU(obj)->kvm_steal_time = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; | ||
306 | +} | ||
307 | + | ||
308 | /* KVM VCPU properties should be prefixed with "kvm-". */ | ||
309 | void kvm_arm_add_vcpu_properties(Object *obj) | ||
310 | { | ||
311 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_add_vcpu_properties(Object *obj) | ||
312 | "the virtual counter. VM stopped time " | ||
313 | "will be counted."); | ||
314 | } | ||
315 | + | ||
316 | + cpu->kvm_steal_time = ON_OFF_AUTO_AUTO; | ||
317 | + object_property_add_bool(obj, "kvm-steal-time", kvm_steal_time_get, | ||
318 | + kvm_steal_time_set); | ||
319 | + object_property_set_description(obj, "kvm-steal-time", | ||
320 | + "Set off to disable KVM steal time."); | ||
321 | } | ||
322 | |||
323 | bool kvm_arm_pmu_supported(void) | ||
324 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
325 | index XXXXXXX..XXXXXXX 100644 | ||
326 | --- a/target/arm/kvm64.c | ||
327 | +++ b/target/arm/kvm64.c | ||
328 | @@ -XXX,XX +XXX,XX @@ | ||
329 | #include <linux/kvm.h> | ||
330 | |||
331 | #include "qemu-common.h" | ||
332 | +#include "qapi/error.h" | ||
333 | #include "cpu.h" | ||
334 | #include "qemu/timer.h" | ||
335 | #include "qemu/error-report.h" | ||
336 | @@ -XXX,XX +XXX,XX @@ static CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr) | ||
337 | return NULL; | ||
338 | } | ||
339 | |||
340 | -static bool kvm_arm_pmu_set_attr(CPUState *cs, struct kvm_device_attr *attr) | ||
341 | +static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *attr, | ||
342 | + const char *name) | ||
343 | { | ||
344 | int err; | ||
345 | |||
346 | err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); | ||
347 | if (err != 0) { | ||
348 | - error_report("PMU: KVM_HAS_DEVICE_ATTR: %s", strerror(-err)); | ||
349 | + error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err)); | ||
350 | return false; | ||
351 | } | ||
352 | |||
353 | err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr); | ||
354 | if (err != 0) { | ||
355 | - error_report("PMU: KVM_SET_DEVICE_ATTR: %s", strerror(-err)); | ||
356 | + error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err)); | ||
357 | return false; | ||
358 | } | ||
359 | |||
360 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_init(CPUState *cs) | ||
361 | if (!ARM_CPU(cs)->has_pmu) { | ||
35 | return; | 362 | return; |
36 | } | 363 | } |
37 | 364 | - if (!kvm_arm_pmu_set_attr(cs, &attr)) { | |
38 | + system_clock_scale = NANOSECONDS_PER_SECOND / HCLK_FRQ; | 365 | + if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { |
39 | + | 366 | error_report("failed to init PMU"); |
40 | object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container), | 367 | abort(); |
41 | &error_abort); | 368 | } |
42 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) { | 369 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq) |
370 | if (!ARM_CPU(cs)->has_pmu) { | ||
371 | return; | ||
372 | } | ||
373 | - if (!kvm_arm_pmu_set_attr(cs, &attr)) { | ||
374 | + if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { | ||
375 | error_report("failed to set irq for PMU"); | ||
376 | abort(); | ||
377 | } | ||
378 | } | ||
379 | |||
380 | +void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) | ||
381 | +{ | ||
382 | + struct kvm_device_attr attr = { | ||
383 | + .group = KVM_ARM_VCPU_PVTIME_CTRL, | ||
384 | + .attr = KVM_ARM_VCPU_PVTIME_IPA, | ||
385 | + .addr = (uint64_t)&ipa, | ||
386 | + }; | ||
387 | + | ||
388 | + if (ARM_CPU(cs)->kvm_steal_time == ON_OFF_AUTO_OFF) { | ||
389 | + return; | ||
390 | + } | ||
391 | + if (!kvm_arm_set_device_attr(cs, &attr, "PVTIME IPA")) { | ||
392 | + error_report("failed to init PVTIME IPA"); | ||
393 | + abort(); | ||
394 | + } | ||
395 | +} | ||
396 | + | ||
397 | static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) | ||
398 | { | ||
399 | uint64_t ret; | ||
400 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
401 | return true; | ||
402 | } | ||
403 | |||
404 | +void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) | ||
405 | +{ | ||
406 | + bool has_steal_time = kvm_arm_steal_time_supported(); | ||
407 | + | ||
408 | + if (cpu->kvm_steal_time == ON_OFF_AUTO_AUTO) { | ||
409 | + if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | ||
410 | + cpu->kvm_steal_time = ON_OFF_AUTO_OFF; | ||
411 | + } else { | ||
412 | + cpu->kvm_steal_time = ON_OFF_AUTO_ON; | ||
413 | + } | ||
414 | + } else if (cpu->kvm_steal_time == ON_OFF_AUTO_ON) { | ||
415 | + if (!has_steal_time) { | ||
416 | + error_setg(errp, "'kvm-steal-time' cannot be enabled " | ||
417 | + "on this host"); | ||
418 | + return; | ||
419 | + } else if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | ||
420 | + /* | ||
421 | + * DEN0057A chapter 2 says "This specification only covers | ||
422 | + * systems in which the Execution state of the hypervisor | ||
423 | + * as well as EL1 of virtual machines is AArch64.". And, | ||
424 | + * to ensure that, the smc/hvc calls are only specified as | ||
425 | + * smc64/hvc64. | ||
426 | + */ | ||
427 | + error_setg(errp, "'kvm-steal-time' cannot be enabled " | ||
428 | + "for AArch32 guests"); | ||
429 | + return; | ||
430 | + } | ||
431 | + } | ||
432 | +} | ||
433 | + | ||
434 | bool kvm_arm_aarch32_supported(void) | ||
435 | { | ||
436 | return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT); | ||
437 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_sve_supported(void) | ||
438 | return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); | ||
439 | } | ||
440 | |||
441 | +bool kvm_arm_steal_time_supported(void) | ||
442 | +{ | ||
443 | + return kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME); | ||
444 | +} | ||
445 | + | ||
446 | QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1); | ||
447 | |||
448 | void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) | ||
449 | diff --git a/target/arm/monitor.c b/target/arm/monitor.c | ||
450 | index XXXXXXX..XXXXXXX 100644 | ||
451 | --- a/target/arm/monitor.c | ||
452 | +++ b/target/arm/monitor.c | ||
453 | @@ -XXX,XX +XXX,XX @@ static const char *cpu_model_advertised_features[] = { | ||
454 | "sve128", "sve256", "sve384", "sve512", | ||
455 | "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280", | ||
456 | "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048", | ||
457 | - "kvm-no-adjvtime", | ||
458 | + "kvm-no-adjvtime", "kvm-steal-time", | ||
459 | NULL | ||
460 | }; | ||
461 | |||
462 | diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c | ||
463 | index XXXXXXX..XXXXXXX 100644 | ||
464 | --- a/tests/qtest/arm-cpu-features.c | ||
465 | +++ b/tests/qtest/arm-cpu-features.c | ||
466 | @@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data) | ||
467 | assert_set_feature(qts, "max", "pmu", true); | ||
468 | |||
469 | assert_has_not_feature(qts, "max", "kvm-no-adjvtime"); | ||
470 | + assert_has_not_feature(qts, "max", "kvm-steal-time"); | ||
471 | |||
472 | if (g_str_equal(qtest_get_arch(), "aarch64")) { | ||
473 | assert_has_feature_enabled(qts, "max", "aarch64"); | ||
474 | @@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data) | ||
475 | assert_set_feature(qts, "host", "kvm-no-adjvtime", false); | ||
476 | |||
477 | if (g_str_equal(qtest_get_arch(), "aarch64")) { | ||
478 | + bool kvm_supports_steal_time; | ||
479 | bool kvm_supports_sve; | ||
480 | char max_name[8], name[8]; | ||
481 | uint32_t max_vq, vq; | ||
482 | @@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data) | ||
483 | QDict *resp; | ||
484 | char *error; | ||
485 | |||
486 | + assert_error(qts, "cortex-a15", | ||
487 | + "We cannot guarantee the CPU type 'cortex-a15' works " | ||
488 | + "with KVM on this host", NULL); | ||
489 | + | ||
490 | assert_has_feature_enabled(qts, "host", "aarch64"); | ||
491 | |||
492 | /* Enabling and disabling pmu should always work. */ | ||
493 | @@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data) | ||
494 | assert_set_feature(qts, "host", "pmu", false); | ||
495 | assert_set_feature(qts, "host", "pmu", true); | ||
496 | |||
497 | - assert_error(qts, "cortex-a15", | ||
498 | - "We cannot guarantee the CPU type 'cortex-a15' works " | ||
499 | - "with KVM on this host", NULL); | ||
500 | - | ||
501 | + /* | ||
502 | + * Some features would be enabled by default, but they're disabled | ||
503 | + * because this instance of KVM doesn't support them. Test that the | ||
504 | + * features are present, and, when enabled, issue further tests. | ||
505 | + */ | ||
506 | + assert_has_feature(qts, "host", "kvm-steal-time"); | ||
507 | assert_has_feature(qts, "host", "sve"); | ||
508 | + | ||
509 | resp = do_query_no_props(qts, "host"); | ||
510 | + kvm_supports_steal_time = resp_get_feature(resp, "kvm-steal-time"); | ||
511 | kvm_supports_sve = resp_get_feature(resp, "sve"); | ||
512 | vls = resp_get_sve_vls(resp); | ||
513 | qobject_unref(resp); | ||
514 | |||
515 | + if (kvm_supports_steal_time) { | ||
516 | + /* If we have steal-time then we should be able to toggle it. */ | ||
517 | + assert_set_feature(qts, "host", "kvm-steal-time", false); | ||
518 | + assert_set_feature(qts, "host", "kvm-steal-time", true); | ||
519 | + } | ||
520 | + | ||
521 | if (kvm_supports_sve) { | ||
522 | g_assert(vls != 0); | ||
523 | max_vq = 64 - __builtin_clzll(vls); | ||
524 | @@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data) | ||
525 | assert_has_not_feature(qts, "host", "aarch64"); | ||
526 | assert_has_not_feature(qts, "host", "pmu"); | ||
527 | assert_has_not_feature(qts, "host", "sve"); | ||
528 | + assert_has_not_feature(qts, "host", "kvm-steal-time"); | ||
529 | } | ||
530 | |||
531 | qtest_quit(qts); | ||
43 | -- | 532 | -- |
44 | 2.20.1 | 533 | 2.20.1 |
45 | 534 | ||
46 | 535 | diff view generated by jsdifflib |
1 | Mostly devices don't need to care whether one of their output | 1 | QEMU supports a 48-bit physical address range, but we don't currently |
---|---|---|---|
2 | qemu_irq lines is connected, because functions like qemu_set_irq() | 2 | expose it in the '-cpu max' ID registers (you get the same range as |
3 | silently do nothing if there is nothing on the other end. However | 3 | Cortex-A57, which is 44 bits). |
4 | sometimes a device might want to implement default behaviour for the | ||
5 | case where the machine hasn't wired the line up to anywhere. | ||
6 | 4 | ||
7 | Provide a function qemu_irq_is_connected() that devices can use for | 5 | Set the ID_AA64MMFR0.PARange field to indicate 48 bits. |
8 | this purpose. (The test is trivial but encapsulating it in a | ||
9 | function makes it easier to see where we're doing it in case we need | ||
10 | to change the implementation later.) | ||
11 | 6 | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
14 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 9 | Message-id: 20201001160116.18095-1-peter.maydell@linaro.org |
15 | Message-id: 20200728103744.6909-2-peter.maydell@linaro.org | ||
16 | --- | 10 | --- |
17 | include/hw/irq.h | 18 ++++++++++++++++++ | 11 | target/arm/cpu64.c | 4 ++++ |
18 | 1 file changed, 18 insertions(+) | 12 | 1 file changed, 4 insertions(+) |
19 | 13 | ||
20 | diff --git a/include/hw/irq.h b/include/hw/irq.h | 14 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
21 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/include/hw/irq.h | 16 | --- a/target/arm/cpu64.c |
23 | +++ b/include/hw/irq.h | 17 | +++ b/target/arm/cpu64.c |
24 | @@ -XXX,XX +XXX,XX @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2); | 18 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
25 | on an existing vector of qemu_irq. */ | 19 | t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); |
26 | void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n); | 20 | cpu->isar.id_aa64pfr1 = t; |
27 | 21 | ||
28 | +/** | 22 | + t = cpu->isar.id_aa64mmfr0; |
29 | + * qemu_irq_is_connected: Return true if IRQ line is wired up | 23 | + t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */ |
30 | + * | 24 | + cpu->isar.id_aa64mmfr0 = t; |
31 | + * If a qemu_irq has a device on the other (receiving) end of it, | ||
32 | + * return true; otherwise return false. | ||
33 | + * | ||
34 | + * Usually device models don't need to care whether the machine model | ||
35 | + * has wired up their outbound qemu_irq lines, because functions like | ||
36 | + * qemu_set_irq() silently do nothing if there is nothing on the other | ||
37 | + * end of the line. However occasionally a device model will want to | ||
38 | + * provide default behaviour if its output is left floating, and | ||
39 | + * it can use this function to identify when that is the case. | ||
40 | + */ | ||
41 | +static inline bool qemu_irq_is_connected(qemu_irq irq) | ||
42 | +{ | ||
43 | + return irq != NULL; | ||
44 | +} | ||
45 | + | 25 | + |
46 | #endif | 26 | t = cpu->isar.id_aa64mmfr1; |
27 | t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ | ||
28 | t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); | ||
47 | -- | 29 | -- |
48 | 2.20.1 | 30 | 2.20.1 |
49 | 31 | ||
50 | 32 | diff view generated by jsdifflib |