With RISC-V H-extension support, a RISC-V implementation can provide trapped
instruction encoding for almost all traps/exceptions.

For illegal/virtual instruction traps, the instruction encoding is available
in STVAL/MTVAL CSR.

For load/store faults, a transformed encoding of the trapped instruction is
available in MTINST/HTINST CSR.

This series implements optional RISC-V HART feature to provide trapped
instruction encoding in appropriate CSR.

These patches can be found in riscv_trap_insn_v1, branch at:
https://github.com/avpatel/qemu.git

Anup Patel (3):
  target/riscv: Optional feature to provide trapped instruction in CSRs
  target/riscv: Fix write_htinst() implementation
  target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt()

 target/riscv/cpu.c        |   7 ++
 target/riscv/cpu.h        |  11 ++-
 target/riscv/cpu_helper.c | 172 +++++++++++++++++++++++++++++++++++++-
 target/riscv/csr.c        |   1 +
 target/riscv/instmap.h    |  41 +++++++++
 target/riscv/translate.c  |  14 +++-
 6 files changed, 241 insertions(+), 5 deletions(-)

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2.25.1