1
Just some bugfixes this time around.
1
Patches for rc1: nothing major, just some minor bugfixes and
2
code cleanups.
2
3
3
-- PMM
4
-- PMM
4
5
5
The following changes since commit 4215d3413272ad6d1c6c9d0234450b602e46a74c:
6
The following changes since commit f7e1914adad8885a5d4c70239ab90d901ed97e9f:
6
7
7
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.1-20200727' into staging (2020-07-27 09:33:04 +0100)
8
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging (2020-11-10 09:24:56 +0000)
8
9
9
are available in the Git repository at:
10
are available in the Git repository at:
10
11
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200727
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201110
12
13
13
for you to fetch changes up to d4f6dda182e19afa75706936805e18397cb95f07:
14
for you to fetch changes up to b6c56c8a9a4064ea783f352f43c5df6231a110fa:
14
15
15
target/arm: Improve IMPDEF algorithm for IRG (2020-07-27 16:12:11 +0100)
16
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check (2020-11-10 11:03:48 +0000)
16
17
17
----------------------------------------------------------------
18
----------------------------------------------------------------
18
target-arm queue:
19
target-arm queue:
19
* ACPI: Assert that we don't run out of the preallocated memory
20
* hw/arm/Kconfig: ARM_V7M depends on PTIMER
20
* hw/misc/aspeed_sdmc: Fix incorrect memory size
21
* Minor coding style fixes
21
* target/arm: Always pass cacheattr in S1_ptw_translate
22
* docs: add some notes on the sbsa-ref machine
22
* docs/system/arm/virt: Document 'mte' machine option
23
* hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
23
* hw/arm/boot: Fix PAUTH, MTE for EL3 direct kernel boot
24
* target/arm: Fix neon VTBL/VTBX for len > 1
24
* target/arm: Improve IMPDEF algorithm for IRG
25
* hw/arm/armsse: Correct expansion MPC interrupt lines
26
* hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
27
* hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
28
* hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
29
* hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
30
* hw/arm/nseries: Check return value from load_image_targphys()
31
* tests/qtest/npcm7xx_rng-test: count runs properly
32
* target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
25
33
26
----------------------------------------------------------------
34
----------------------------------------------------------------
27
Dongjiu Geng (1):
35
Alex Bennée (1):
28
ACPI: Assert that we don't run out of the preallocated memory
36
docs: add some notes on the sbsa-ref machine
29
37
30
Peter Maydell (1):
38
AlexChen (1):
31
docs/system/arm/virt: Document 'mte' machine option
39
ssi: Fix bad printf format specifiers
32
40
33
Philippe Mathieu-Daudé (1):
41
Andrew Jones (1):
34
hw/misc/aspeed_sdmc: Fix incorrect memory size
42
hw/arm/Kconfig: ARM_V7M depends on PTIMER
35
43
36
Richard Henderson (4):
44
Havard Skinnemoen (1):
37
target/arm: Always pass cacheattr in S1_ptw_translate
45
tests/qtest/npcm7xx_rng-test: count runs properly
38
hw/arm/boot: Fix PAUTH for EL3 direct kernel boot
39
hw/arm/boot: Fix MTE for EL3 direct kernel boot
40
target/arm: Improve IMPDEF algorithm for IRG
41
46
42
docs/system/arm/virt.rst | 4 ++++
47
Peter Maydell (2):
43
hw/acpi/ghes.c | 12 ++++--------
48
hw/arm/nseries: Check return value from load_image_targphys()
44
hw/arm/boot.c | 6 ++++++
49
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
45
hw/misc/aspeed_sdmc.c | 7 ++++---
46
target/arm/helper.c | 19 ++++++-------------
47
target/arm/mte_helper.c | 37 ++++++++++++++++++++++++++++++-------
48
6 files changed, 54 insertions(+), 31 deletions(-)
49
50
51
Philippe Mathieu-Daudé (6):
52
hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
53
hw/arm/armsse: Correct expansion MPC interrupt lines
54
hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
55
hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
56
hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
57
hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
58
59
Richard Henderson (1):
60
target/arm: Fix neon VTBL/VTBX for len > 1
61
62
Xinhao Zhang (3):
63
target/arm: add spaces around operator
64
target/arm: Don't use '#' flag of printf format
65
target/arm: add space before the open parenthesis '('
66
67
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++
68
docs/system/target-arm.rst | 1 +
69
include/hw/misc/stm32f2xx_syscfg.h | 2 --
70
target/arm/helper.h | 2 +-
71
hw/arm/armsse.c | 3 +-
72
hw/arm/musicpal.c | 40 +++++++++++++++++----------
73
hw/arm/nseries.c | 26 ++++++++----------
74
hw/arm/stm32f205_soc.c | 1 -
75
hw/misc/stm32f2xx_syscfg.c | 2 --
76
hw/ssi/imx_spi.c | 2 +-
77
hw/ssi/xilinx_spi.c | 2 +-
78
target/arm/arch_dump.c | 8 +++---
79
target/arm/arm-semi.c | 8 +++---
80
target/arm/helper.c | 2 +-
81
target/arm/op_helper.c | 23 +++++++++-------
82
target/arm/translate-a64.c | 4 +--
83
target/arm/translate.c | 2 +-
84
tests/qtest/npcm7xx_rng-test.c | 2 +-
85
hw/arm/Kconfig | 3 +-
86
target/arm/translate-neon.c.inc | 56 ++++++++++++++------------------------
87
20 files changed, 123 insertions(+), 98 deletions(-)
88
create mode 100644 docs/system/arm/sbsa.rst
89
diff view generated by jsdifflib
New patch
1
From: Andrew Jones <drjones@redhat.com>
1
2
3
commit 32bd322a0134 ("hw/timer/armv7m_systick: Rewrite to use ptimers")
4
changed armv7m_systick to build on ptimers. Make sure we have ptimers
5
in the build when building armv7m_systick.
6
7
Signed-off-by: Andrew Jones <drjones@redhat.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20201104103343.30392-1-drjones@redhat.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/Kconfig | 1 +
13
1 file changed, 1 insertion(+)
14
15
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/Kconfig
18
+++ b/hw/arm/Kconfig
19
@@ -XXX,XX +XXX,XX @@ config ZYNQ
20
21
config ARM_V7M
22
bool
23
+ select PTIMER
24
25
config ALLWINNER_A10
26
bool
27
--
28
2.20.1
29
30
diff view generated by jsdifflib
New patch
1
From: AlexChen <alex.chen@huawei.com>
1
2
3
We should use printf format specifier "%u" instead of "%d" for
4
argument of type "unsigned int".
5
6
Reported-by: Euler Robot <euler.robot@huawei.com>
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 5FA280F5.8060902@huawei.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/ssi/imx_spi.c | 2 +-
13
hw/ssi/xilinx_spi.c | 2 +-
14
2 files changed, 2 insertions(+), 2 deletions(-)
15
16
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/ssi/imx_spi.c
19
+++ b/hw/ssi/imx_spi.c
20
@@ -XXX,XX +XXX,XX @@ static const char *imx_spi_reg_name(uint32_t reg)
21
case ECSPI_MSGDATA:
22
return "ECSPI_MSGDATA";
23
default:
24
- sprintf(unknown, "%d ?", reg);
25
+ sprintf(unknown, "%u ?", reg);
26
return unknown;
27
}
28
}
29
diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/ssi/xilinx_spi.c
32
+++ b/hw/ssi/xilinx_spi.c
33
@@ -XXX,XX +XXX,XX @@ static void xlx_spi_update_irq(XilinxSPI *s)
34
irq chain unless things really changed. */
35
if (pending != s->irqline) {
36
s->irqline = pending;
37
- DB_PRINT("irq_change of state %d ISR:%x IER:%X\n",
38
+ DB_PRINT("irq_change of state %u ISR:%x IER:%X\n",
39
pending, s->regs[R_IPISR], s->regs[R_IPIER]);
40
qemu_set_irq(s->irq, pending);
41
}
42
--
43
2.20.1
44
45
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
2
2
3
When we changed the interface of get_phys_addr_lpae to require
3
Fix code style. Operator needs spaces both sides.
4
the cacheattr parameter, this spot was missed. The compiler is
5
unable to detect the use of NULL vs the nonnull attribute here.
6
4
7
Fixes: 7e98e21c098
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
8
Reported-by: Jan Kiszka <jan.kiszka@siemens.com>
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201103114529.638233-1-zhangxinhao1@huawei.com
10
Tested-by: Jan Kiszka <jan.kiskza@siemens.com>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
target/arm/helper.c | 19 ++++++-------------
11
target/arm/arch_dump.c | 8 ++++----
15
1 file changed, 6 insertions(+), 13 deletions(-)
12
target/arm/arm-semi.c | 8 ++++----
13
target/arm/helper.c | 2 +-
14
3 files changed, 9 insertions(+), 9 deletions(-)
16
15
16
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/arch_dump.c
19
+++ b/target/arm/arch_dump.c
20
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
21
22
for (i = 0; i < 32; ++i) {
23
uint64_t *q = aa64_vfp_qreg(env, i);
24
- note.vfp.vregs[2*i + 0] = cpu_to_dump64(s, q[0]);
25
- note.vfp.vregs[2*i + 1] = cpu_to_dump64(s, q[1]);
26
+ note.vfp.vregs[2 * i + 0] = cpu_to_dump64(s, q[0]);
27
+ note.vfp.vregs[2 * i + 1] = cpu_to_dump64(s, q[1]);
28
}
29
30
if (s->dump_info.d_endian == ELFDATA2MSB) {
31
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
32
*/
33
for (i = 0; i < 32; ++i) {
34
uint64_t tmp = note.vfp.vregs[2*i];
35
- note.vfp.vregs[2*i] = note.vfp.vregs[2*i+1];
36
- note.vfp.vregs[2*i+1] = tmp;
37
+ note.vfp.vregs[2 * i] = note.vfp.vregs[2 * i + 1];
38
+ note.vfp.vregs[2 * i + 1] = tmp;
39
}
40
}
41
42
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/arm-semi.c
45
+++ b/target/arm/arm-semi.c
46
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
47
if (use_gdb_syscalls()) {
48
arm_semi_open_guestfd = guestfd;
49
ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0,
50
- (int)arg2+1, gdb_open_modeflags[arg1]);
51
+ (int)arg2 + 1, gdb_open_modeflags[arg1]);
52
} else {
53
ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644));
54
if (ret == (uint32_t)-1) {
55
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
56
GET_ARG(1);
57
if (use_gdb_syscalls()) {
58
ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s",
59
- arg0, (int)arg1+1);
60
+ arg0, (int)arg1 + 1);
61
} else {
62
s = lock_user_string(arg0);
63
if (!s) {
64
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
65
GET_ARG(3);
66
if (use_gdb_syscalls()) {
67
return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s",
68
- arg0, (int)arg1+1, arg2, (int)arg3+1);
69
+ arg0, (int)arg1 + 1, arg2, (int)arg3 + 1);
70
} else {
71
char *s2;
72
s = lock_user_string(arg0);
73
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
74
GET_ARG(1);
75
if (use_gdb_syscalls()) {
76
return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s",
77
- arg0, (int)arg1+1);
78
+ arg0, (int)arg1 + 1);
79
} else {
80
s = lock_user_string(arg0);
81
if (!s) {
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
82
diff --git a/target/arm/helper.c b/target/arm/helper.c
18
index XXXXXXX..XXXXXXX 100644
83
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper.c
84
--- a/target/arm/helper.c
20
+++ b/target/arm/helper.c
85
+++ b/target/arm/helper.c
21
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
86
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
22
int s2prot;
87
uint32_t sum;
23
int ret;
88
sum = do_usad(a, b);
24
ARMCacheAttrs cacheattrs = {};
89
sum += do_usad(a >> 8, b >> 8);
25
- ARMCacheAttrs *pcacheattrs = NULL;
90
- sum += do_usad(a >> 16, b >>16);
26
-
91
+ sum += do_usad(a >> 16, b >> 16);
27
- if (env->cp15.hcr_el2 & HCR_PTW) {
92
sum += do_usad(a >> 24, b >> 24);
28
- /*
93
return sum;
29
- * PTW means we must fault if this S1 walk touches S2 Device
94
}
30
- * memory; otherwise we don't care about the attributes and can
31
- * save the S2 translation the effort of computing them.
32
- */
33
- pcacheattrs = &cacheattrs;
34
- }
35
36
ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,
37
false,
38
&s2pa, &txattrs, &s2prot, &s2size, fi,
39
- pcacheattrs);
40
+ &cacheattrs);
41
if (ret) {
42
assert(fi->type != ARMFault_None);
43
fi->s2addr = addr;
44
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
45
fi->s1ptw = true;
46
return ~0;
47
}
48
- if (pcacheattrs && (pcacheattrs->attrs & 0xf0) == 0) {
49
- /* Access was to Device memory: generate Permission fault */
50
+ if ((env->cp15.hcr_el2 & HCR_PTW) && (cacheattrs.attrs & 0xf0) == 0) {
51
+ /*
52
+ * PTW set and S1 walk touched S2 Device memory:
53
+ * generate Permission fault.
54
+ */
55
fi->type = ARMFault_Permission;
56
fi->s2addr = addr;
57
fi->stage2 = true;
58
--
95
--
59
2.20.1
96
2.20.1
60
97
61
98
diff view generated by jsdifflib
New patch
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
1
2
3
Fix code style. Don't use '#' flag of printf format ('%#') in
4
format strings, use '0x' prefix instead
5
6
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
7
Signed-off-by: Kai Deng <dengkai1@huawei.com>
8
Message-id: 20201103114529.638233-2-zhangxinhao1@huawei.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-a64.c | 4 ++--
13
1 file changed, 2 insertions(+), 2 deletions(-)
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
20
gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
21
break;
22
default:
23
- fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
24
+ fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n",
25
__func__, insn, fpopcode, s->pc_curr);
26
g_assert_not_reached();
27
}
28
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
29
case 0x7f: /* FSQRT (vector) */
30
break;
31
default:
32
- fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
33
+ fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop);
34
g_assert_not_reached();
35
}
36
37
--
38
2.20.1
39
40
diff view generated by jsdifflib
New patch
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
1
2
3
Fix code style. Space required before the open parenthesis '('.
4
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
7
Message-id: 20201103114529.638233-3-zhangxinhao1@huawei.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
17
+++ b/target/arm/translate.c
18
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
19
- Hardware watchpoints.
20
Hardware breakpoints have already been handled and skip this code.
21
*/
22
- switch(dc->base.is_jmp) {
23
+ switch (dc->base.is_jmp) {
24
case DISAS_NEXT:
25
case DISAS_TOO_MANY:
26
gen_goto_tb(dc, 1, dc->base.pc_next);
27
--
28
2.20.1
29
30
diff view generated by jsdifflib
New patch
1
From: Alex Bennée <alex.bennee@linaro.org>
1
2
3
We should at least document what this machine is about.
4
5
Reviewed-by: Graeme Gregory <graeme@nuviainc.com>
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20201104165254.24822-1-alex.bennee@linaro.org
8
Cc: Leif Lindholm <leif@nuviainc.com>
9
Cc: Shashi Mallela <shashi.mallela@linaro.org>
10
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
11
[PMM: fixed filename mismatch]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++++++++++++
15
docs/system/target-arm.rst | 1 +
16
2 files changed, 33 insertions(+)
17
create mode 100644 docs/system/arm/sbsa.rst
18
19
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
20
new file mode 100644
21
index XXXXXXX..XXXXXXX
22
--- /dev/null
23
+++ b/docs/system/arm/sbsa.rst
24
@@ -XXX,XX +XXX,XX @@
25
+Arm Server Base System Architecture Reference board (``sbsa-ref``)
26
+==================================================================
27
+
28
+While the `virt` board is a generic board platform that doesn't match
29
+any real hardware the `sbsa-ref` board intends to look like real
30
+hardware. The `Server Base System Architecture
31
+<https://developer.arm.com/documentation/den0029/latest>` defines a
32
+minimum base line of hardware support and importantly how the firmware
33
+reports that to any operating system. It is a static system that
34
+reports a very minimal DT to the firmware for non-discoverable
35
+information about components affected by the qemu command line (i.e.
36
+cpus and memory). As a result it must have a firmware specifically
37
+built to expect a certain hardware layout (as you would in a real
38
+machine).
39
+
40
+It is intended to be a machine for developing firmware and testing
41
+standards compliance with operating systems.
42
+
43
+Supported devices
44
+"""""""""""""""""
45
+
46
+The sbsa-ref board supports:
47
+
48
+ - A configurable number of AArch64 CPUs
49
+ - GIC version 3
50
+ - System bus AHCI controller
51
+ - System bus EHCI controller
52
+ - CDROM and hard disc on AHCI bus
53
+ - E1000E ethernet card on PCIe bus
54
+ - VGA display adaptor on PCIe bus
55
+ - A generic SBSA watchdog device
56
+
57
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
58
index XXXXXXX..XXXXXXX 100644
59
--- a/docs/system/target-arm.rst
60
+++ b/docs/system/target-arm.rst
61
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
62
arm/mps2
63
arm/musca
64
arm/realview
65
+ arm/sbsa
66
arm/versatile
67
arm/vexpress
68
arm/aspeed
69
--
70
2.20.1
71
72
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
When using a Cortex-A15, the Virt machine does not use any
4
MPCore peripherals. Remove the dependency.
5
6
Fixes: 7951c7b7c05 ("hw/arm: Express dependencies of the virt machine with Kconfig")
7
Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20201107114852.271922-1-philmd@redhat.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/Kconfig | 1 -
14
1 file changed, 1 deletion(-)
15
16
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/Kconfig
19
+++ b/hw/arm/Kconfig
20
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
21
imply VFIO_PLATFORM
22
imply VFIO_XGMAC
23
imply TPM_TIS_SYSBUS
24
- select A15MPCORE
25
select ACPI
26
select ARM_SMMUV3
27
select GPIO_KEY
28
--
29
2.20.1
30
31
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
When GCR_EL1.RRND==1, the choosing of the random value is IMPDEF,
3
The helper function did not get updated when we reorganized
4
and the kernel is not expected to have set RGSR_EL1. Force a
4
the vector register file for SVE. Since then, the neon dregs
5
non-zero value into SEED, so that we do not continually return
5
are non-sequential and cannot be simply indexed.
6
the same tag.
7
6
8
Reported-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
7
At the same time, make the helper function operate on 64-bit
8
quantities so that we do not have to call it twice.
9
10
Fixes: c39c2b9043e
11
Reported-by: Ard Biesheuvel <ardb@kernel.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200724163853.504655-4-richard.henderson@linaro.org
13
[PMM: use aa32_vfp_dreg() rather than opencoding]
14
Message-id: 20201105171126.88014-1-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
17
---
14
target/arm/mte_helper.c | 37 ++++++++++++++++++++++++++++++-------
18
target/arm/helper.h | 2 +-
15
1 file changed, 30 insertions(+), 7 deletions(-)
19
target/arm/op_helper.c | 23 +++++++++--------
20
target/arm/translate-neon.c.inc | 44 +++++++++++----------------------
21
3 files changed, 29 insertions(+), 40 deletions(-)
16
22
17
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
23
diff --git a/target/arm/helper.h b/target/arm/helper.h
18
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/mte_helper.c
25
--- a/target/arm/helper.h
20
+++ b/target/arm/mte_helper.c
26
+++ b/target/arm/helper.h
21
@@ -XXX,XX +XXX,XX @@
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
22
#include "exec/ram_addr.h"
28
DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
23
#include "exec/cpu_ldst.h"
29
DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32)
24
#include "exec/helper-proto.h"
30
DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32)
25
+#include "qapi/error.h"
31
-DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32)
26
+#include "qemu/guest-random.h"
32
+DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64)
27
33
28
34
DEF_HELPER_3(shl_cc, i32, env, i32, i32)
29
static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude)
35
DEF_HELPER_3(shr_cc, i32, env, i32, i32)
30
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
36
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
31
37
index XXXXXXX..XXXXXXX 100644
32
uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm)
38
--- a/target/arm/op_helper.c
39
+++ b/target/arm/op_helper.c
40
@@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
41
cpu_loop_exit_restore(cs, ra);
42
}
43
44
-uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,
45
- uint32_t maxindex)
46
+uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc,
47
+ uint64_t ireg, uint64_t def)
33
{
48
{
34
- int rtag;
49
- uint32_t val, shift;
35
-
50
- uint64_t *table = vn;
36
- /*
51
+ uint64_t tmp, val = 0;
37
- * Our IMPDEF choice for GCR_EL1.RRND==1 is to behave as if
52
+ uint32_t maxindex = ((desc & 3) + 1) * 8;
38
- * GCR_EL1.RRND==0, always producing deterministic results.
53
+ uint32_t base_reg = desc >> 2;
39
- */
54
+ uint32_t shift, index, reg;
40
uint16_t exclude = extract32(rm | env->cp15.gcr_el1, 0, 16);
55
41
+ int rrnd = extract32(env->cp15.gcr_el1, 16, 1);
56
- val = 0;
42
int start = extract32(env->cp15.rgsr_el1, 0, 4);
57
- for (shift = 0; shift < 32; shift += 8) {
43
int seed = extract32(env->cp15.rgsr_el1, 8, 16);
58
- uint32_t index = (ireg >> shift) & 0xff;
44
- int offset, i;
59
+ for (shift = 0; shift < 64; shift += 8) {
45
+ int offset, i, rtag;
60
+ index = (ireg >> shift) & 0xff;
61
if (index < maxindex) {
62
- uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
63
- val |= tmp << shift;
64
+ reg = base_reg + (index >> 3);
65
+ tmp = *aa32_vfp_dreg(env, reg);
66
+ tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift;
67
} else {
68
- val |= def & (0xff << shift);
69
+ tmp = def & (0xffull << shift);
70
}
71
+ val |= tmp;
72
}
73
return val;
74
}
75
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/translate-neon.c.inc
78
+++ b/target/arm/translate-neon.c.inc
79
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
80
81
static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
82
{
83
- int n;
84
- TCGv_i32 tmp, tmp2, tmp3, tmp4;
85
- TCGv_ptr ptr1;
86
+ TCGv_i64 val, def;
87
+ TCGv_i32 desc;
88
89
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
90
return false;
91
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
92
return true;
93
}
94
95
- n = a->len + 1;
96
- if ((a->vn + n) > 32) {
97
+ if ((a->vn + a->len + 1) > 32) {
98
/*
99
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
100
* helper function running off the end of the register file.
101
*/
102
return false;
103
}
104
- n <<= 3;
105
- tmp = tcg_temp_new_i32();
106
- if (a->op) {
107
- read_neon_element32(tmp, a->vd, 0, MO_32);
108
- } else {
109
- tcg_gen_movi_i32(tmp, 0);
110
- }
111
- tmp2 = tcg_temp_new_i32();
112
- read_neon_element32(tmp2, a->vm, 0, MO_32);
113
- ptr1 = vfp_reg_ptr(true, a->vn);
114
- tmp4 = tcg_const_i32(n);
115
- gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);
116
117
+ desc = tcg_const_i32((a->vn << 2) | a->len);
118
+ def = tcg_temp_new_i64();
119
if (a->op) {
120
- read_neon_element32(tmp, a->vd, 1, MO_32);
121
+ read_neon_element64(def, a->vd, 0, MO_64);
122
} else {
123
- tcg_gen_movi_i32(tmp, 0);
124
+ tcg_gen_movi_i64(def, 0);
125
}
126
- tmp3 = tcg_temp_new_i32();
127
- read_neon_element32(tmp3, a->vm, 1, MO_32);
128
- gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);
129
- tcg_temp_free_i32(tmp);
130
- tcg_temp_free_i32(tmp4);
131
- tcg_temp_free_ptr(ptr1);
132
+ val = tcg_temp_new_i64();
133
+ read_neon_element64(val, a->vm, 0, MO_64);
134
135
- write_neon_element32(tmp2, a->vd, 0, MO_32);
136
- write_neon_element32(tmp3, a->vd, 1, MO_32);
137
- tcg_temp_free_i32(tmp2);
138
- tcg_temp_free_i32(tmp3);
139
+ gen_helper_neon_tbl(val, cpu_env, desc, val, def);
140
+ write_neon_element64(val, a->vd, 0, MO_64);
46
+
141
+
47
+ /*
142
+ tcg_temp_free_i64(def);
48
+ * Our IMPDEF choice for GCR_EL1.RRND==1 is to continue to use the
143
+ tcg_temp_free_i64(val);
49
+ * deterministic algorithm. Except that with RRND==1 the kernel is
144
+ tcg_temp_free_i32(desc);
50
+ * not required to have set RGSR_EL1.SEED != 0, which is required for
145
return true;
51
+ * the deterministic algorithm to function. So we force a non-zero
146
}
52
+ * SEED for that case.
147
53
+ */
54
+ if (unlikely(seed == 0) && rrnd) {
55
+ do {
56
+ Error *err = NULL;
57
+ uint16_t two;
58
+
59
+ if (qemu_guest_getrandom(&two, sizeof(two), &err) < 0) {
60
+ /*
61
+ * Failed, for unknown reasons in the crypto subsystem.
62
+ * Best we can do is log the reason and use a constant seed.
63
+ */
64
+ qemu_log_mask(LOG_UNIMP, "IRG: Crypto failure: %s\n",
65
+ error_get_pretty(err));
66
+ error_free(err);
67
+ two = 1;
68
+ }
69
+ seed = two;
70
+ } while (seed == 0);
71
+ }
72
73
/* RandomTag */
74
for (i = offset = 0; i < 4; ++i) {
75
--
148
--
76
2.20.1
149
2.20.1
77
150
78
151
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
We can use one MPC per SRAM bank, but we currently only wire the
4
IRQ from the first expansion MPC to the IRQ splitter. Fix that.
5
6
Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines")
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20201107193403.436146-2-f4bug@amsat.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/armsse.c | 3 ++-
13
1 file changed, 2 insertions(+), 1 deletion(-)
14
15
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/armsse.c
18
+++ b/hw/arm/armsse.c
19
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
20
qdev_get_gpio_in(dev_splitter, 0));
21
qdev_connect_gpio_out(dev_splitter, 0,
22
qdev_get_gpio_in_named(dev_secctl,
23
- "mpc_status", 0));
24
+ "mpc_status",
25
+ i - IOTS_NUM_EXP_MPC));
26
}
27
28
qdev_connect_gpio_out(dev_splitter, 1,
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
The system configuration controller (SYSCFG) doesn't have
4
any output IRQ (and the INTC input #71 belongs to the UART6).
5
Remove the invalid code.
6
7
Fixes: db635521a02 ("stm32f205: Add the stm32f205 SoC")
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20201107193403.436146-3-f4bug@amsat.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/misc/stm32f2xx_syscfg.h | 2 --
14
hw/arm/stm32f205_soc.c | 1 -
15
hw/misc/stm32f2xx_syscfg.c | 2 --
16
3 files changed, 5 deletions(-)
17
18
diff --git a/include/hw/misc/stm32f2xx_syscfg.h b/include/hw/misc/stm32f2xx_syscfg.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/misc/stm32f2xx_syscfg.h
21
+++ b/include/hw/misc/stm32f2xx_syscfg.h
22
@@ -XXX,XX +XXX,XX @@ struct STM32F2XXSyscfgState {
23
uint32_t syscfg_exticr3;
24
uint32_t syscfg_exticr4;
25
uint32_t syscfg_cmpcr;
26
-
27
- qemu_irq irq;
28
};
29
30
#endif /* HW_STM32F2XX_SYSCFG_H */
31
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/stm32f205_soc.c
34
+++ b/hw/arm/stm32f205_soc.c
35
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
36
}
37
busdev = SYS_BUS_DEVICE(dev);
38
sysbus_mmio_map(busdev, 0, 0x40013800);
39
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
40
41
/* Attach UART (uses USART registers) and USART controllers */
42
for (i = 0; i < STM_NUM_USARTS; i++) {
43
diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/misc/stm32f2xx_syscfg.c
46
+++ b/hw/misc/stm32f2xx_syscfg.c
47
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_syscfg_init(Object *obj)
48
{
49
STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj);
50
51
- sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
52
-
53
memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s,
54
TYPE_STM32F2XX_SYSCFG, 0x400);
55
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
56
--
57
2.20.1
58
59
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
When booting an EL3 cpu with -kernel, we set up EL3 and then
3
omap2420_mpu_init() introduced in commit 827df9f3c5f ("Add basic
4
drop down to EL2. We need to enable access to v8.5-MemTag
4
OMAP2 chip support") takes care of creating the 3 UARTs.
5
tag allocation at EL3 before doing so.
6
5
7
Reported-by: Peter Maydell <peter.maydell@linaro.org>
6
Then commit 58a26b477e9 ("Emulate a serial bluetooth HCI with H4+
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
extensions and attach to n8x0's UART") added n8x0_uart_setup()
9
Message-id: 20200724163853.504655-3-richard.henderson@linaro.org
8
which create the UART and connects it to an IRQ output,
9
overwritting the existing peripheral and its IRQ connection.
10
This is incorrect.
11
12
Fortunately we don't need to fix this, because commit 6da68df7f9b
13
("hw/arm/nseries: Replace the bluetooth chardev with a "null"
14
chardev") removed the use of this peripheral. We can simply
15
remove the code.
16
17
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20201107193403.436146-4-f4bug@amsat.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
21
---
13
hw/arm/boot.c | 3 +++
22
hw/arm/nseries.c | 11 -----------
14
1 file changed, 3 insertions(+)
23
1 file changed, 11 deletions(-)
15
24
16
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
25
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
17
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/boot.c
27
--- a/hw/arm/nseries.c
19
+++ b/hw/arm/boot.c
28
+++ b/hw/arm/nseries.c
20
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
29
@@ -XXX,XX +XXX,XX @@ static void n8x0_cbus_setup(struct n800_s *s)
21
if (cpu_isar_feature(aa64_pauth, cpu)) {
30
cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
22
env->cp15.scr_el3 |= SCR_API | SCR_APK;
31
}
23
}
32
24
+ if (cpu_isar_feature(aa64_mte, cpu)) {
33
-static void n8x0_uart_setup(struct n800_s *s)
25
+ env->cp15.scr_el3 |= SCR_ATA;
34
-{
26
+ }
35
- Chardev *radio = qemu_chr_new("bt-dummy-uart", "null", NULL);
27
/* AArch64 kernels never boot in secure mode */
36
- /*
28
assert(!info->secure_boot);
37
- * Note: We used to connect N8X0_BT_RESET_GPIO and N8X0_BT_WKUP_GPIO
29
/* This hook is only supported for AArch32 currently:
38
- * here, but this code has been removed with the bluetooth backend.
39
- */
40
- omap_uart_attach(s->mpu->uart[BT_UART], radio);
41
-}
42
-
43
static void n8x0_usb_setup(struct n800_s *s)
44
{
45
SysBusDevice *dev;
46
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
47
n8x0_spi_setup(s);
48
n8x0_dss_setup(s);
49
n8x0_cbus_setup(s);
50
- n8x0_uart_setup(s);
51
if (machine_usb(machine)) {
52
n8x0_usb_setup(s);
53
}
30
--
54
--
31
2.20.1
55
2.20.1
32
56
33
57
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
When booting an EL3 cpu with -kernel, we set up EL3 and then
3
The MusicPal board code connects both of the IRQ outputs of the UART
4
drop down to EL2. We need to enable access to v8.3-PAuth
4
to the same INTC qemu_irq. Connecting two qemu_irqs outputs directly
5
keys and instructions at EL3 before doing so.
5
to the same input is not valid as it produces subtly wrong behaviour
6
(for instance if both the IRQ lines are high, and then one goes
7
low, the INTC input will see this as a high-to-low transition
8
even though the second IRQ line should still be holding it high).
6
9
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
This kind of wiring needs an explicitly created OR gate; add one.
8
Message-id: 20200724163853.504655-2-richard.henderson@linaro.org
11
12
Inspired-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20201107193403.436146-5-f4bug@amsat.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
17
---
12
hw/arm/boot.c | 3 +++
18
hw/arm/musicpal.c | 17 +++++++++++++----
13
1 file changed, 3 insertions(+)
19
hw/arm/Kconfig | 1 +
20
2 files changed, 14 insertions(+), 4 deletions(-)
14
21
15
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
22
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
16
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/boot.c
24
--- a/hw/arm/musicpal.c
18
+++ b/hw/arm/boot.c
25
+++ b/hw/arm/musicpal.c
19
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
26
@@ -XXX,XX +XXX,XX @@
20
} else {
27
#include "ui/console.h"
21
env->pstate = PSTATE_MODE_EL1h;
28
#include "hw/i2c/i2c.h"
22
}
29
#include "hw/irq.h"
23
+ if (cpu_isar_feature(aa64_pauth, cpu)) {
30
+#include "hw/or-irq.h"
24
+ env->cp15.scr_el3 |= SCR_API | SCR_APK;
31
#include "hw/audio/wm8750.h"
25
+ }
32
#include "sysemu/block-backend.h"
26
/* AArch64 kernels never boot in secure mode */
33
#include "sysemu/runstate.h"
27
assert(!info->secure_boot);
34
@@ -XXX,XX +XXX,XX @@
28
/* This hook is only supported for AArch32 currently:
35
#define MP_TIMER4_IRQ 7
36
#define MP_EHCI_IRQ 8
37
#define MP_ETH_IRQ 9
38
-#define MP_UART1_IRQ 11
39
-#define MP_UART2_IRQ 11
40
+#define MP_UART_SHARED_IRQ 11
41
#define MP_GPIO_IRQ 12
42
#define MP_RTC_IRQ 28
43
#define MP_AUDIO_IRQ 30
44
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
45
ARMCPU *cpu;
46
qemu_irq pic[32];
47
DeviceState *dev;
48
+ DeviceState *uart_orgate;
49
DeviceState *i2c_dev;
50
DeviceState *lcd_dev;
51
DeviceState *key_dev;
52
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
53
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
54
pic[MP_TIMER4_IRQ], NULL);
55
56
- serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
57
+ /* Logically OR both UART IRQs together */
58
+ uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
59
+ object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
60
+ qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
61
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
62
+
63
+ serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
64
+ qdev_get_gpio_in(uart_orgate, 0),
65
1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
66
- serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
67
+ serial_mm_init(address_space_mem, MP_UART2_BASE, 2,
68
+ qdev_get_gpio_in(uart_orgate, 1),
69
1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
70
71
/* Register flash */
72
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
73
index XXXXXXX..XXXXXXX 100644
74
--- a/hw/arm/Kconfig
75
+++ b/hw/arm/Kconfig
76
@@ -XXX,XX +XXX,XX @@ config MUSCA
77
78
config MUSICPAL
79
bool
80
+ select OR_IRQ
81
select BITBANG_I2C
82
select MARVELL_88W8618
83
select PTIMER
29
--
84
--
30
2.20.1
85
2.20.1
31
86
32
87
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
The SDRAM Memory Controller has a 32-bit address bus, thus
3
We don't need to fill the full pic[] array if we only use
4
supports up to 4 GiB of DRAM. There is a signed to unsigned
4
few of the interrupt lines. Directly call qdev_get_gpio_in()
5
conversion error with the AST2600 maximum memory size:
5
when necessary.
6
6
7
(uint64_t)(2048 << 20) = (uint64_t)(-2147483648)
8
= 0xffffffff40000000
9
= 16 EiB - 2 GiB
10
11
Fix by using the IEC suffixes which are usually safer, and add
12
an assertion check to verify the memory is valid. This would have
13
caught this bug:
14
15
$ qemu-system-arm -M ast2600-evb
16
qemu-system-arm: hw/misc/aspeed_sdmc.c:258: aspeed_sdmc_realize: Assertion `asc->max_ram_size < 4 * GiB' failed.
17
Aborted (core dumped)
18
19
Fixes: 1550d72679 ("aspeed/sdmc: Add AST2600 support")
20
Reviewed-by: Cédric Le Goater <clg@kaod.org>
21
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20201107193403.436146-6-f4bug@amsat.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
---
11
---
24
hw/misc/aspeed_sdmc.c | 7 ++++---
12
hw/arm/musicpal.c | 25 +++++++++++++------------
25
1 file changed, 4 insertions(+), 3 deletions(-)
13
1 file changed, 13 insertions(+), 12 deletions(-)
26
14
27
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
15
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
28
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/misc/aspeed_sdmc.c
17
--- a/hw/arm/musicpal.c
30
+++ b/hw/misc/aspeed_sdmc.c
18
+++ b/hw/arm/musicpal.c
31
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
19
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info musicpal_binfo = {
32
AspeedSDMCState *s = ASPEED_SDMC(dev);
20
static void musicpal_init(MachineState *machine)
33
AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
21
{
34
22
ARMCPU *cpu;
35
+ assert(asc->max_ram_size < 4 * GiB); /* 32-bit address bus */
23
- qemu_irq pic[32];
36
s->max_ram_size = asc->max_ram_size;
24
DeviceState *dev;
37
25
+ DeviceState *pic;
38
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,
26
DeviceState *uart_orgate;
39
@@ -XXX,XX +XXX,XX @@ static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data)
27
DeviceState *i2c_dev;
40
AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
28
DeviceState *lcd_dev;
41
29
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
42
dc->desc = "ASPEED 2400 SDRAM Memory Controller";
30
&error_fatal);
43
- asc->max_ram_size = 512 << 20;
31
memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
44
+ asc->max_ram_size = 512 * MiB;
32
45
asc->compute_conf = aspeed_2400_sdmc_compute_conf;
33
- dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
46
asc->write = aspeed_2400_sdmc_write;
34
+ pic = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
47
asc->valid_ram_sizes = aspeed_2400_ram_sizes;
35
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
48
@@ -XXX,XX +XXX,XX @@ static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data)
36
- for (i = 0; i < 32; i++) {
49
AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
37
- pic[i] = qdev_get_gpio_in(dev, i);
50
38
- }
51
dc->desc = "ASPEED 2500 SDRAM Memory Controller";
39
- sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ],
52
- asc->max_ram_size = 1024 << 20;
40
- pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
53
+ asc->max_ram_size = 1 * GiB;
41
- pic[MP_TIMER4_IRQ], NULL);
54
asc->compute_conf = aspeed_2500_sdmc_compute_conf;
42
+ sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE,
55
asc->write = aspeed_2500_sdmc_write;
43
+ qdev_get_gpio_in(pic, MP_TIMER1_IRQ),
56
asc->valid_ram_sizes = aspeed_2500_ram_sizes;
44
+ qdev_get_gpio_in(pic, MP_TIMER2_IRQ),
57
@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data)
45
+ qdev_get_gpio_in(pic, MP_TIMER3_IRQ),
58
AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
46
+ qdev_get_gpio_in(pic, MP_TIMER4_IRQ), NULL);
59
47
60
dc->desc = "ASPEED 2600 SDRAM Memory Controller";
48
/* Logically OR both UART IRQs together */
61
- asc->max_ram_size = 2048 << 20;
49
uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
62
+ asc->max_ram_size = 2 * GiB;
50
object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
63
asc->compute_conf = aspeed_2600_sdmc_compute_conf;
51
qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
64
asc->write = aspeed_2600_sdmc_write;
52
- qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
65
asc->valid_ram_sizes = aspeed_2600_ram_sizes;
53
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0,
54
+ qdev_get_gpio_in(pic, MP_UART_SHARED_IRQ));
55
56
serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
57
qdev_get_gpio_in(uart_orgate, 0),
58
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
59
OBJECT(get_system_memory()), &error_fatal);
60
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
61
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
62
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
63
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
64
+ qdev_get_gpio_in(pic, MP_ETH_IRQ));
65
66
sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
67
68
sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL);
69
70
dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE,
71
- pic[MP_GPIO_IRQ]);
72
+ qdev_get_gpio_in(pic, MP_GPIO_IRQ));
73
i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
74
i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c");
75
76
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
77
NULL);
78
sysbus_realize_and_unref(s, &error_fatal);
79
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
80
- sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
81
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ));
82
83
musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
84
arm_load_kernel(cpu, machine, &musicpal_binfo);
66
--
85
--
67
2.20.1
86
2.20.1
68
87
69
88
diff view generated by jsdifflib
New patch
1
The nseries machines have a codepath that allows them to load a
2
secondary bootloader. This code wasn't checking that the
3
load_image_targphys() succeeded. Check the return value and report
4
the error to the user.
1
5
6
While we're in the vicinity, fix the comment style of the
7
comment documenting what this image load is doing.
8
9
Fixes: Coverity CID 1192904
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20201103114918.11807-1-peter.maydell@linaro.org
13
---
14
hw/arm/nseries.c | 15 +++++++++++----
15
1 file changed, 11 insertions(+), 4 deletions(-)
16
17
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/nseries.c
20
+++ b/hw/arm/nseries.c
21
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
22
/* No, wait, better start at the ROM. */
23
s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
24
25
- /* This is intended for loading the `secondary.bin' program from
26
+ /*
27
+ * This is intended for loading the `secondary.bin' program from
28
* Nokia images (the NOLO bootloader). The entry point seems
29
* to be at OMAP2_Q2_BASE + 0x400000.
30
*
31
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
32
* for them the entry point needs to be set to OMAP2_SRAM_BASE.
33
*
34
* The code above is for loading the `zImage' file from Nokia
35
- * images. */
36
- load_image_targphys(option_rom[0].name, OMAP2_Q2_BASE + 0x400000,
37
- machine->ram_size - 0x400000);
38
+ * images.
39
+ */
40
+ if (load_image_targphys(option_rom[0].name,
41
+ OMAP2_Q2_BASE + 0x400000,
42
+ machine->ram_size - 0x400000) < 0) {
43
+ error_report("Failed to load secondary bootloader %s",
44
+ option_rom[0].name);
45
+ exit(EXIT_FAILURE);
46
+ }
47
48
n800_setup_nolo_tags(nolo_tags);
49
cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
50
--
51
2.20.1
52
53
diff view generated by jsdifflib
1
From: Dongjiu Geng <gengdongjiu@huawei.com>
1
From: Havard Skinnemoen <hskinnemoen@google.com>
2
2
3
data_length is a constant value, so we use assert instead of
3
The number of runs is equal to the number of 0-1 and 1-0 transitions,
4
condition check.
4
plus one. Currently, it's counting the number of times these transitions
5
do _not_ happen, plus one.
5
6
6
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
7
Source:
7
Message-id: 20200622113146.33421-1-gengdongjiu@huawei.com
8
https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-22r1a.pdf
8
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
9
section 2.3.4 point (3).
10
11
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
12
Message-id: 20201103011457.2959989-2-hskinnemoen@google.com
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
15
---
11
hw/acpi/ghes.c | 12 ++++--------
16
tests/qtest/npcm7xx_rng-test.c | 2 +-
12
1 file changed, 4 insertions(+), 8 deletions(-)
17
1 file changed, 1 insertion(+), 1 deletion(-)
13
18
14
diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c
19
diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
15
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/acpi/ghes.c
21
--- a/tests/qtest/npcm7xx_rng-test.c
17
+++ b/hw/acpi/ghes.c
22
+++ b/tests/qtest/npcm7xx_rng-test.c
18
@@ -XXX,XX +XXX,XX @@ static int acpi_ghes_record_mem_error(uint64_t error_block_address,
23
@@ -XXX,XX +XXX,XX @@ static double calc_runs_p(const unsigned long *buf, unsigned int nr_bits)
19
24
pi = (double)nr_ones / nr_bits;
20
/* This is the length if adding a new generic error data entry*/
25
21
data_length = ACPI_GHES_DATA_LENGTH + ACPI_GHES_MEM_CPER_LENGTH;
26
for (k = 0; k < nr_bits - 1; k++) {
22
-
27
- vn_obs += !(test_bit(k, buf) ^ test_bit(k + 1, buf));
23
/*
28
+ vn_obs += (test_bit(k, buf) ^ test_bit(k + 1, buf));
24
- * Check whether it will run out of the preallocated memory if adding a new
29
}
25
- * generic error data entry
30
vn_obs += 1;
26
+ * It should not run out of the preallocated memory if adding a new generic
31
27
+ * error data entry
28
*/
29
- if ((data_length + ACPI_GHES_GESB_SIZE) > ACPI_GHES_MAX_RAW_DATA_LENGTH) {
30
- error_report("Not enough memory to record new CPER!!!");
31
- g_array_free(block, true);
32
- return -1;
33
- }
34
+ assert((data_length + ACPI_GHES_GESB_SIZE) <=
35
+ ACPI_GHES_MAX_RAW_DATA_LENGTH);
36
37
/* Build the new generic error status block header */
38
acpi_ghes_generic_error_status(block, ACPI_GEBS_UNCORRECTABLE,
39
--
32
--
40
2.20.1
33
2.20.1
41
34
42
35
diff view generated by jsdifflib
1
Commit 6a0b7505f1fd6769c which added documentation of the virt board
1
Checks for UNDEF cases should go before the "is VFP enabled?" access
2
crossed in the post with commit 6f4e1405b91da0d0 which added a new
2
check, except in special cases. Move a stray UNDEF check in the VTBL
3
'mte' machine option. Update the docs to include the new option.
3
trans function up above the access check.
4
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201109145324.2859-1-peter.maydell@linaro.org
8
---
8
---
9
docs/system/arm/virt.rst | 4 ++++
9
target/arm/translate-neon.c.inc | 8 ++++----
10
1 file changed, 4 insertions(+)
10
1 file changed, 4 insertions(+), 4 deletions(-)
11
11
12
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
12
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
13
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
14
--- a/docs/system/arm/virt.rst
14
--- a/target/arm/translate-neon.c.inc
15
+++ b/docs/system/arm/virt.rst
15
+++ b/target/arm/translate-neon.c.inc
16
@@ -XXX,XX +XXX,XX @@ virtualization
16
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
17
Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
17
return false;
18
Arm Virtualization Extensions. The default is ``off``.
18
}
19
19
20
+mte
20
- if (!vfp_access_check(s)) {
21
+ Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
21
- return true;
22
+ Arm Memory Tagging Extensions. The default is ``off``.
22
- }
23
-
24
if ((a->vn + a->len + 1) > 32) {
25
/*
26
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
27
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
28
return false;
29
}
30
31
+ if (!vfp_access_check(s)) {
32
+ return true;
33
+ }
23
+
34
+
24
highmem
35
desc = tcg_const_i32((a->vn << 2) | a->len);
25
Set ``on``/``off`` to enable/disable placing devices and RAM in physical
36
def = tcg_temp_new_i64();
26
address space above 32 bits. The default is ``on`` for machine types
37
if (a->op) {
27
--
38
--
28
2.20.1
39
2.20.1
29
40
30
41
diff view generated by jsdifflib