[PULL 0/5] riscv-to-apply queue
[PULL 0/2] riscv-to-apply queue
1
The following changes since commit 3cbc8970f55c87cb58699b6dc8fe42998bc79dc0:
1
From: Alistair Francis <alistair.francis@wdc.com>
2
2
3
Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2020-07-21' into staging (2020-07-22 09:13:46 +0100)
3
The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1:
4
5
Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100)
4
6
5
are available in the Git repository at:
7
are available in the Git repository at:
6
8
7
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200722-1
9
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122
8
10
9
for you to fetch changes up to 8ba26b0b2b00dd5849a6c0981e358dc7a7cc315d:
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for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3:
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12
11
target/riscv: Fix the range of pmpcfg of CSR funcion table (2020-07-22 09:41:36 -0700)
13
hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000)
12
14
13
----------------------------------------------------------------
15
----------------------------------------------------------------
14
This PR contains a few RISC-V fixes.
16
Seventh RISC-V PR for QEMU 6.2
15
17
16
The main fix is the correction of the goldfish RTC time. On top of that
18
- Deprecate IF_NONE for SiFive OTP
17
some small fixes to the recently added vector extensions have been added
19
- Don't reset SiFive OTP content
18
(including an assert that fixed a coverity report). There is a change in
19
the SiFive E debug memory size to match hardware. Finally there is a fix
20
for PMP accesses.
21
20
22
----------------------------------------------------------------
21
----------------------------------------------------------------
23
Bin Meng (1):
22
Philippe Mathieu-Daudé (1):
24
hw/riscv: sifive_e: Correct debug block size
23
hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
25
24
26
Jessica Clarke (1):
25
Thomas Huth (1):
27
goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH
26
hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
28
27
29
LIU Zhiwei (2):
28
docs/about/deprecated.rst | 6 ++++++
30
target/riscv: Quiet Coverity complains about vamo*
29
hw/misc/sifive_u_otp.c | 22 +++++++++++++---------
31
target/riscv: fix vector index load/store constraints
30
2 files changed, 19 insertions(+), 9 deletions(-)
32
31
33
Zong Li (1):
34
target/riscv: Fix the range of pmpcfg of CSR funcion table
35
36
include/hw/rtc/goldfish_rtc.h | 1 +
37
hw/riscv/sifive_e.c | 2 +-
38
hw/rtc/goldfish_rtc.c | 17 ++++++++++++++---
39
target/riscv/csr.c | 2 +-
40
target/riscv/insn_trans/trans_rvv.inc.c | 11 ++++++++++-
41
5 files changed, 27 insertions(+), 6 deletions(-)
42
diff view generated by jsdifflib
[PULL 1/5] goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH
Deleted patch
1
From: Jessica Clarke <jrtc27@jrtc27.com>
2
1
3
The specification says:
4
5
0x00 TIME_LOW R: Get current time, then return low-order 32-bits.
6
0x04 TIME_HIGH R: Return high 32-bits from previous TIME_LOW read.
7
8
...
9
10
To read the value, the kernel must perform an IO_READ(TIME_LOW),
11
which returns an unsigned 32-bit value, before an IO_READ(TIME_HIGH),
12
which returns a signed 32-bit value, corresponding to the higher half
13
of the full value.
14
15
However, we were just returning the current time for both. If the guest
16
is unlucky enough to read TIME_LOW and TIME_HIGH either side of an
17
overflow of the lower half, it will see time be in the future, before
18
jumping backwards on the next read, and Linux currently relies on the
19
atomicity guaranteed by the spec so is affected by this. Fix this
20
violation of the spec by caching the correct value for TIME_HIGH
21
whenever TIME_LOW is read, and returning that value for any TIME_HIGH
22
read.
23
24
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
25
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
26
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
27
Message-Id: <20200718004934.83174-1-jrtc27@jrtc27.com>
28
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
29
---
30
include/hw/rtc/goldfish_rtc.h | 1 +
31
hw/rtc/goldfish_rtc.c | 17 ++++++++++++++---
32
2 files changed, 15 insertions(+), 3 deletions(-)
33
34
diff --git a/include/hw/rtc/goldfish_rtc.h b/include/hw/rtc/goldfish_rtc.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/include/hw/rtc/goldfish_rtc.h
37
+++ b/include/hw/rtc/goldfish_rtc.h
38
@@ -XXX,XX +XXX,XX @@ typedef struct GoldfishRTCState {
39
uint32_t alarm_running;
40
uint32_t irq_pending;
41
uint32_t irq_enabled;
42
+ uint32_t time_high;
43
} GoldfishRTCState;
44
45
#endif
46
diff --git a/hw/rtc/goldfish_rtc.c b/hw/rtc/goldfish_rtc.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/rtc/goldfish_rtc.c
49
+++ b/hw/rtc/goldfish_rtc.c
50
@@ -XXX,XX +XXX,XX @@ static uint64_t goldfish_rtc_read(void *opaque, hwaddr offset,
51
GoldfishRTCState *s = opaque;
52
uint64_t r = 0;
53
54
+ /*
55
+ * From the documentation linked at the top of the file:
56
+ *
57
+ * To read the value, the kernel must perform an IO_READ(TIME_LOW), which
58
+ * returns an unsigned 32-bit value, before an IO_READ(TIME_HIGH), which
59
+ * returns a signed 32-bit value, corresponding to the higher half of the
60
+ * full value.
61
+ */
62
switch (offset) {
63
case RTC_TIME_LOW:
64
- r = goldfish_rtc_get_count(s) & 0xffffffff;
65
+ r = goldfish_rtc_get_count(s);
66
+ s->time_high = r >> 32;
67
+ r &= 0xffffffff;
68
break;
69
case RTC_TIME_HIGH:
70
- r = goldfish_rtc_get_count(s) >> 32;
71
+ r = s->time_high;
72
break;
73
case RTC_ALARM_LOW:
74
r = s->alarm_next & 0xffffffff;
75
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps goldfish_rtc_ops = {
76
77
static const VMStateDescription goldfish_rtc_vmstate = {
78
.name = TYPE_GOLDFISH_RTC,
79
- .version_id = 1,
80
+ .version_id = 2,
81
.pre_save = goldfish_rtc_pre_save,
82
.post_load = goldfish_rtc_post_load,
83
.fields = (VMStateField[]) {
84
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription goldfish_rtc_vmstate = {
85
VMSTATE_UINT32(alarm_running, GoldfishRTCState),
86
VMSTATE_UINT32(irq_pending, GoldfishRTCState),
87
VMSTATE_UINT32(irq_enabled, GoldfishRTCState),
88
+ VMSTATE_UINT32(time_high, GoldfishRTCState),
89
VMSTATE_END_OF_LIST()
90
}
91
};
92
--
93
2.27.0
94
95
diff view generated by jsdifflib
[PULL 5/5] target/riscv: Fix the range of pmpcfg of CSR funcion table
[PULL 1/2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
1
From: Zong Li <zong.li@sifive.com>
1
From: Thomas Huth <thuth@redhat.com>
2
2
3
The range of Physical Memory Protection should be from CSR_PMPCFG0
3
Configuring a drive with "if=none" is meant for creation of a backend
4
to CSR_PMPCFG3, not to CSR_PMPADDR9.
4
only, it should not get automatically assigned to a device frontend.
5
Use "if=pflash" for the One-Time-Programmable device instead (like
6
it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c).
5
7
6
Signed-off-by: Zong Li <zong.li@sifive.com>
8
Since the old way of configuring the device has already been published
9
with the previous QEMU versions, we cannot remove this immediately, but
10
have to deprecate it and support it for at least two more releases.
11
12
Signed-off-by: Thomas Huth <thuth@redhat.com>
13
Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Reviewed-by: Markus Armbruster <armbru@redhat.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Bin Meng <bin.meng@windriver.com>
16
Message-id: 20211119102549.217755-1-thuth@redhat.com
9
Message-Id: <eae49e9252c9596e4f3bdb471772f79235141a87.1595335112.git.zong.li@sifive.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
18
---
12
target/riscv/csr.c | 2 +-
19
docs/about/deprecated.rst | 6 ++++++
13
1 file changed, 1 insertion(+), 1 deletion(-)
20
hw/misc/sifive_u_otp.c | 9 ++++++++-
21
2 files changed, 14 insertions(+), 1 deletion(-)
14
22
15
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
23
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
16
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/csr.c
25
--- a/docs/about/deprecated.rst
18
+++ b/target/riscv/csr.c
26
+++ b/docs/about/deprecated.rst
19
@@ -XXX,XX +XXX,XX @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
27
@@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``.
20
[CSR_MTINST] = { hmode, read_mtinst, write_mtinst },
28
However, short-form booleans are deprecated and full explicit ``arg_name=on``
21
29
form is preferred.
22
/* Physical Memory Protection */
30
23
- [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
31
+``-drive if=none`` for the sifive_u OTP device (since 6.2)
24
+ [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg },
32
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
25
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
33
+
26
34
+Using ``-drive if=none`` to configure the OTP device of the sifive_u
27
/* Performance Counters */
35
+RISC-V machine is deprecated. Use ``-drive if=pflash`` instead.
36
+
37
38
QEMU Machine Protocol (QMP) commands
39
------------------------------------
40
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/misc/sifive_u_otp.c
43
+++ b/hw/misc/sifive_u_otp.c
44
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
45
TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
46
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
47
48
- dinfo = drive_get_next(IF_NONE);
49
+ dinfo = drive_get_next(IF_PFLASH);
50
+ if (!dinfo) {
51
+ dinfo = drive_get_next(IF_NONE);
52
+ if (dinfo) {
53
+ warn_report("using \"-drive if=none\" for the OTP is deprecated, "
54
+ "use \"-drive if=pflash\" instead.");
55
+ }
56
+ }
57
if (dinfo) {
58
int ret;
59
uint64_t perm;
28
--
60
--
29
2.27.0
61
2.31.1
30
62
31
63
diff view generated by jsdifflib
[PULL 2/5] target/riscv: Quiet Coverity complains about vamo*
[PULL 2/2] hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
1
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
3
Once a "One Time Programmable" is programmed, it shouldn't be reset.
4
5
Do not re-initialize the OTP content in the DeviceReset handler,
6
initialize it once in the DeviceRealize one.
7
8
Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP")
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-Id: <20200721133742.2298-1-zhiwei_liu@c-sky.com>
11
Message-Id: <20211119104757.331579-1-f4bug@amsat.org>
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
---
13
---
8
target/riscv/insn_trans/trans_rvv.inc.c | 1 +
14
hw/misc/sifive_u_otp.c | 13 +++++--------
9
1 file changed, 1 insertion(+)
15
1 file changed, 5 insertions(+), 8 deletions(-)
10
16
11
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
17
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/target/riscv/insn_trans/trans_rvv.inc.c
19
--- a/hw/misc/sifive_u_otp.c
14
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
20
+++ b/hw/misc/sifive_u_otp.c
15
@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
21
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
16
g_assert_not_reached();
22
17
#endif
23
if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
18
} else {
24
error_setg(errp, "failed to read the initial flash content");
19
+ assert(seq < ARRAY_SIZE(fnsw));
25
+ return;
20
fn = fnsw[seq];
26
}
21
}
27
}
22
}
28
}
29
-}
30
-
31
-static void sifive_u_otp_reset(DeviceState *dev)
32
-{
33
- SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
34
35
/* Initialize all fuses' initial value to 0xFFs */
36
memset(s->fuse, 0xff, sizeof(s->fuse));
37
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
38
serial_data = s->serial;
39
if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
40
&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
41
- error_report("write error index<%d>", index);
42
+ error_setg(errp, "failed to write index<%d>", index);
43
+ return;
44
}
45
46
serial_data = ~(s->serial);
47
if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
48
&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
49
- error_report("write error index<%d>", index + 1);
50
+ error_setg(errp, "failed to write index<%d>", index + 1);
51
+ return;
52
}
53
}
54
55
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
56
57
device_class_set_props(dc, sifive_u_otp_properties);
58
dc->realize = sifive_u_otp_realize;
59
- dc->reset = sifive_u_otp_reset;
60
}
61
62
static const TypeInfo sifive_u_otp_info = {
23
--
63
--
24
2.27.0
64
2.31.1
25
65
26
66
diff view generated by jsdifflib
[PULL 3/5] target/riscv: fix vector index load/store constraints
Deleted patch
1
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
2
1
3
Although not explicitly specified that the the destination
4
vector register groups cannot overlap the source vector register group,
5
it is still necessary.
6
7
And this constraint has been added to the v0.8 spec.
8
9
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-Id: <20200721133742.2298-2-zhiwei_liu@c-sky.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/insn_trans/trans_rvv.inc.c | 10 +++++++++-
15
1 file changed, 9 insertions(+), 1 deletion(-)
16
17
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/insn_trans/trans_rvv.inc.c
20
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
21
@@ -XXX,XX +XXX,XX @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
22
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
23
}
24
25
+/*
26
+ * For vector indexed segment loads, the destination vector register
27
+ * groups cannot overlap the source vector register group (specified by
28
+ * `vs2`), else an illegal instruction exception is raised.
29
+ */
30
static bool ld_index_check(DisasContext *s, arg_rnfvm* a)
31
{
32
return (vext_check_isa_ill(s) &&
33
vext_check_overlap_mask(s, a->rd, a->vm, false) &&
34
vext_check_reg(s, a->rd, false) &&
35
vext_check_reg(s, a->rs2, false) &&
36
- vext_check_nf(s, a->nf));
37
+ vext_check_nf(s, a->nf) &&
38
+ ((a->nf == 1) ||
39
+ vext_check_overlap_group(a->rd, a->nf << s->lmul,
40
+ a->rs2, 1 << s->lmul)));
41
}
42
43
GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check)
44
--
45
2.27.0
46
47
diff view generated by jsdifflib
[PULL 4/5] hw/riscv: sifive_e: Correct debug block size
Deleted patch
1
From: Bin Meng <bmeng.cn@gmail.com>
2
1
3
Currently the debug region size is set to 0x100, but according to
4
FE310-G000 and FE310-G002 manuals:
5
6
FE310-G000: 0x100 - 0xFFF
7
FE310-G002: 0x0 - 0xFFF
8
9
Change the size to 0x1000 that applies to both.
10
11
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-Id: <1594891856-15474-1-git-send-email-bmeng.cn@gmail.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
16
hw/riscv/sifive_e.c | 2 +-
17
1 file changed, 1 insertion(+), 1 deletion(-)
18
19
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/riscv/sifive_e.c
22
+++ b/hw/riscv/sifive_e.c
23
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
24
hwaddr base;
25
hwaddr size;
26
} sifive_e_memmap[] = {
27
- [SIFIVE_E_DEBUG] = { 0x0, 0x100 },
28
+ [SIFIVE_E_DEBUG] = { 0x0, 0x1000 },
29
[SIFIVE_E_MROM] = { 0x1000, 0x2000 },
30
[SIFIVE_E_OTP] = { 0x20000, 0x2000 },
31
[SIFIVE_E_CLINT] = { 0x2000000, 0x10000 },
32
--
33
2.27.0
34
35
diff view generated by jsdifflib

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