[RFC v2 06/76] target/riscv: fix vill bit index in vtype register

From: Frank Chang <frank.chang@sifive.com>

vill bit is at vtype[XLEN-1].

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 378f6e82bf..27ce075e50 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -98,7 +98,7 @@ FIELD(VTYPE, VLMUL, 0, 2)
 FIELD(VTYPE, VSEW, 2, 3)
 FIELD(VTYPE, VEDIV, 5, 2)
 FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
-FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 2, 1)
+FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
 
 struct CPURISCVState {
     target_ulong gpr[32];
-- 
2.17.1

• [RFC v2 01/76] target/riscv: drop vector 0.7.1 support
• [RFC v2 02/76] target/riscv: rvv-0.9: support vector 0.9
• [RFC v2 03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
• [RFC v2 04/76] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
• [RFC v2 05/76] target/riscv: fix return value of do_opivx_widen()
• [RFC v2 06/76] target/riscv: fix vill bit index in vtype register
• [RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field
• [RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field
• [RFC v2 09/76] target/riscv: rvv-0.9: add sstatus VS field
• [RFC v2 10/76] target/riscv: rvv-0.9: add translation-time vector context status
• [RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register
• [RFC v2 12/76] target/riscv: rvv-0.9: add vcsr register
• [RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register
• [RFC v2 14/76] target/riscv: rvv-0.9: remove MLEN calculations
• [RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL
• [RFC v2 16/76] target/riscv: rvv-0.9: add VMA and VTA
• [RFC v2 17/76] target/riscv: rvv-0.9: update check functions
• [RFC v2 18/76] target/riscv: introduce more imm value modes in translator functions
• [RFC v2 19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper
• [RFC v2 20/76] target/riscv: rvv-0.9: apply narrower nanbox helper in opfvf_trans
• [RFC v2 21/76] target/riscv: rvv-0.9: configure instructions
• [RFC v2 22/76] target/riscv: rvv-0.9: stride load and store instructions
• [RFC v2 23/76] target/riscv: rvv-0.9: index load and store instructions
• [RFC v2 24/76] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns
• [RFC v2 25/76] target/riscv: rvv-0.9: fault-only-first unit stride load
• [RFC v2 26/76] target/riscv: rvv-0.9: amo operations
• [RFC v2 27/76] target/riscv: rvv-0.9: load/store whole register instructions
• [RFC v2 28/76] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns
• [RFC v2 29/76] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation
• [RFC v2 30/76] target/riscv: rvv-0.9: floating-point square-root instruction
• [RFC v2 31/76] target/riscv: rvv-0.9: floating-point classify instructions
• [RFC v2 32/76] target/riscv: rvv-0.9: mask population count instruction
• [RFC v2 33/76] target/riscv: rvv-0.9: find-first-set mask bit instruction
• [RFC v2 34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions
• [RFC v2 35/76] target/riscv: rvv-0.9: iota instruction
• [RFC v2 36/76] target/riscv: rvv-0.9: element index instruction
• [RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended
• [RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions
• [RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions
• [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction
• [RFC v2 41/76] target/riscv: rvv-0.9: floating-point scalar move instructions
• [RFC v2 42/76] target/riscv: rvv-0.9: whole register move instructions
• [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions
• [RFC v2 44/76] target/riscv: rvv-0.9: single-width averaging add and subtract instructions
• [RFC v2 45/76] target/riscv: rvv-0.9: single-width bit shift instructions
• [RFC v2 46/76] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow
• [RFC v2 47/76] target/riscv: rvv-0.9: narrowing integer right shift instructions
• [RFC v2 48/76] target/riscv: rvv-0.9: widening integer multiply-add instructions
• [RFC v2 49/76] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions
• [RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions
• [RFC v2 51/76] target/riscv: rvv-0.9: integer comparison instructions
• [RFC v2 52/76] fpu: implement full set compare for fp16
• [RFC v2 53/76] target/riscv: use softfloat lib float16 comparison functions
• [RFC v2 54/76] target/riscv: rvv-0.9: floating-point compare instructions
• [RFC v2 55/76] target/riscv: rvv-0.9: single-width integer reduction instructions
• [RFC v2 56/76] target/riscv: rvv-0.9: widening integer reduction instructions
• [RFC v2 57/76] target/riscv: rvv-0.9: mask-register logical instructions
• [RFC v2 58/76] target/riscv: rvv-0.9: slide instructions
• [RFC v2 59/76] target/riscv: rvv-0.9: floating-point slide instructions
• [RFC v2 60/76] target/riscv: rvv-0.9: narrowing fixed-point clip instructions
• [RFC v2 61/76] target/riscv: rvv-0.9: floating-point/integer type-convert instructions
• [RFC v2 62/76] target/riscv: rvv-0.9: single-width floating-point reduction
• [RFC v2 63/76] target/riscv: rvv-0.9: widening floating-point reduction instructions
• [RFC v2 64/76] target/riscv: rvv-0.9: single-width scaling shift instructions
• [RFC v2 65/76] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add
• [RFC v2 66/76] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf
• [RFC v2 67/76] target/riscv: rvv-0.9: remove integer extract instruction
• [RFC v2 68/76] fpu: add api to handle alternative sNaN propagation
• [RFC v2 69/76] target/riscv: rvv-0.9: floating-point min/max instructions
• [RFC v2 70/76] softfloat: add fp16 and uint8/int8 interconvert functions
• [RFC v2 71/76] target/riscv: rvv-0.9: widening floating-point/integer type-convert
• [RFC v2 72/76] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert
• [RFC v2 73/76] fpu: fix float16 nan check
• [RFC v2 74/76] target/riscv: gdb: modify gdb csr xml file to align with csr register map
• [RFC v2 75/76] target/riscv: gdb: support vector registers for rv64
• [RFC v2 76/76] target/riscv: gdb: support vector registers for rv32