[v2] target/riscv: support vector extension v0.9

[RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions

Posted by frank.chang@sifive.com 5 years, 6 months ago

From: Frank Chang <frank.chang@sifive.com>

Sign-extend vsaddu.vi immediate value.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 956ee90745..3018489536 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2374,7 +2374,7 @@ GEN_OPIVX_TRANS(vsaddu_vx,  opivx_check)
 GEN_OPIVX_TRANS(vsadd_vx,  opivx_check)
 GEN_OPIVX_TRANS(vssubu_vx,  opivx_check)
 GEN_OPIVX_TRANS(vssub_vx,  opivx_check)
-GEN_OPIVI_TRANS(vsaddu_vi, IMM_ZX, vsaddu_vx, opivx_check)
+GEN_OPIVI_TRANS(vsaddu_vi, IMM_SX, vsaddu_vx, opivx_check)
 GEN_OPIVI_TRANS(vsadd_vi, IMM_SX, vsadd_vx, opivx_check)
 
 /* Vector Single-Width Averaging Add and Subtract */
-- 
2.17.1

Re: [RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions

Posted by Richard Henderson 5 years, 6 months ago

On 7/22/20 2:16 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
> 
> Sign-extend vsaddu.vi immediate value.
> 
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
>  target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
> index 956ee90745..3018489536 100644
> --- a/target/riscv/insn_trans/trans_rvv.inc.c
> +++ b/target/riscv/insn_trans/trans_rvv.inc.c
> @@ -2374,7 +2374,7 @@ GEN_OPIVX_TRANS(vsaddu_vx,  opivx_check)
>  GEN_OPIVX_TRANS(vsadd_vx,  opivx_check)
>  GEN_OPIVX_TRANS(vssubu_vx,  opivx_check)
>  GEN_OPIVX_TRANS(vssub_vx,  opivx_check)
> -GEN_OPIVI_TRANS(vsaddu_vi, IMM_ZX, vsaddu_vx, opivx_check)
> +GEN_OPIVI_TRANS(vsaddu_vi, IMM_SX, vsaddu_vx, opivx_check)
>  GEN_OPIVI_TRANS(vsadd_vi, IMM_SX, vsadd_vx, opivx_check)
>  
>  /* Vector Single-Width Averaging Add and Subtract */
> 

This isn't what spike does.

The manual could really stand to be more specific here...


r~

Re: [RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions

Posted by Frank Chang 5 years, 6 months ago

On Fri, Jul 31, 2020 at 5:24 AM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 7/22/20 2:16 AM, frank.chang@sifive.com wrote:
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > Sign-extend vsaddu.vi immediate value.
> >
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> > ---
> >  target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
> b/target/riscv/insn_trans/trans_rvv.inc.c
> > index 956ee90745..3018489536 100644
> > --- a/target/riscv/insn_trans/trans_rvv.inc.c
> > +++ b/target/riscv/insn_trans/trans_rvv.inc.c
> > @@ -2374,7 +2374,7 @@ GEN_OPIVX_TRANS(vsaddu_vx,  opivx_check)
> >  GEN_OPIVX_TRANS(vsadd_vx,  opivx_check)
> >  GEN_OPIVX_TRANS(vssubu_vx,  opivx_check)
> >  GEN_OPIVX_TRANS(vssub_vx,  opivx_check)
> > -GEN_OPIVI_TRANS(vsaddu_vi, IMM_ZX, vsaddu_vx, opivx_check)
> > +GEN_OPIVI_TRANS(vsaddu_vi, IMM_SX, vsaddu_vx, opivx_check)
> >  GEN_OPIVI_TRANS(vsadd_vi, IMM_SX, vsadd_vx, opivx_check)
> >
> >  /* Vector Single-Width Averaging Add and Subtract */
> >
>
> This isn't what spike does.
>
> The manual could really stand to be more specific here...
>
>
> r~
>

Isn't Spike's vsaddu.vi immediate value also signed-extended?
*riscv/insns/vsaddu_vi.h:*
*vd = vs2 + (insn.v_simm5() & (UINT64_MAX >> (64 - P.VU.vsew))); *

From RVV 0.9 spec.:
*vsaddu.vi <http://vsaddu.vi> vd, vs2, imm, vm # vector-immediate*
It also mentions *imm* is sign-extended.
In contrast, *uimm* represents the immediate value to be zero-extended.

Frank Chang

Re: [RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions

Posted by Richard Henderson 5 years, 6 months ago

On 8/3/20 7:40 PM, Frank Chang wrote:
>     This isn't what spike does.
> 
>     The manual could really stand to be more specific here...
> 
> Isn't Spike's vsaddu.vi <http://vsaddu.vi> immediate value also signed-extended? 
> /riscv/insns/vsaddu_vi.h:/
> /vd = vs2 + (insn.v_simm5() & (UINT64_MAX >> (64 - P.VU.vsew))); /

Whoops, quite right.  Masking to SEW, not (u)imm5.


r~