[v2] target/riscv: support vector extension v0.9

[RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction

Posted by frank.chang@sifive.com 5 years, 6 months ago

From: Frank Chang <frank.chang@sifive.com>

NaN-boxed the scalar floating-point register based on RVV 0.9's rules.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.inc.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 780f8660bf..54c08ea1f8 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2722,6 +2722,7 @@ GEN_OPFVF_TRANS(vfmerge_vfm,  opfvf_check)
 static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
 {
     if (require_rvv(s) &&
+        has_ext(s, RVF) &&
         vext_check_isa_ill(s) &&
         require_align(a->rd, s->flmul) &&
         (s->sew != 0)) {
@@ -2744,7 +2745,20 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
             dest = tcg_temp_new_ptr();
             desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
             tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
-            fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
+
+            if ((s->sew < MO_64 && has_ext(s, RVD)) ||
+                (s->sew < MO_32)) {
+                /* SEW < FLEN */
+                TCGv_i64 t1 = tcg_temp_new_i64();
+                TCGv_i32 sew = tcg_const_i32(1 << (s->sew + 3));
+                gen_helper_narrower_nanbox_fpr(t1, cpu_fpr[a->rs1],
+                                               sew, cpu_env);
+                fns[s->sew - 1](dest, t1, cpu_env, desc);
+                tcg_temp_free_i64(t1);
+                tcg_temp_free_i32(sew);
+            } else {
+                fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
+            }
 
             tcg_temp_free_ptr(dest);
             tcg_temp_free_i32(desc);
-- 
2.17.1

Re: [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction

Posted by Richard Henderson 5 years, 6 months ago

On 7/22/20 2:16 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
> 
> NaN-boxed the scalar floating-point register based on RVV 0.9's rules.
> 
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
>  target/riscv/insn_trans/trans_rvv.inc.c | 16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
> index 780f8660bf..54c08ea1f8 100644
> --- a/target/riscv/insn_trans/trans_rvv.inc.c
> +++ b/target/riscv/insn_trans/trans_rvv.inc.c
> @@ -2722,6 +2722,7 @@ GEN_OPFVF_TRANS(vfmerge_vfm,  opfvf_check)
>  static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
>  {
>      if (require_rvv(s) &&
> +        has_ext(s, RVF) &&
>          vext_check_isa_ill(s) &&
>          require_align(a->rd, s->flmul) &&
>          (s->sew != 0)) {
> @@ -2744,7 +2745,20 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
>              dest = tcg_temp_new_ptr();
>              desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
>              tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
> -            fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
> +
> +            if ((s->sew < MO_64 && has_ext(s, RVD)) ||

Bearing in mind my nanboxing patch set that Alistair picked up (for 5.2, I
assume), wherein you would not check RVD, but allow the nanboxing to 64-bits to
happen always.

But this also isn't the correct place to do this.  You need to move it up above

        if (s->vl_eq_vlmax) {
            tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
                                 MAXSZ(s), MAXSZ(s),
                                 cpu_fpr[a->rs1]);


> +                (s->sew < MO_32)) {
> +                /* SEW < FLEN */
> +                TCGv_i64 t1 = tcg_temp_new_i64();
> +                TCGv_i32 sew = tcg_const_i32(1 << (s->sew + 3));
> +                gen_helper_narrower_nanbox_fpr(t1, cpu_fpr[a->rs1],
> +                                               sew, cpu_env);

Also, while there is currently one function, gen_nanbox_s, you'll want to add
gen_nanbox_h to match.


r~


> +                fns[s->sew - 1](dest, t1, cpu_env, desc);
> +                tcg_temp_free_i64(t1);
> +                tcg_temp_free_i32(sew);
> +            } else {
> +                fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
> +            }
>  
>              tcg_temp_free_ptr(dest);
>              tcg_temp_free_i32(desc);
>

Re: [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction

Posted by Richard Henderson 5 years, 6 months ago

On 7/30/20 12:57 PM, Richard Henderson wrote:
> On 7/22/20 2:16 AM, frank.chang@sifive.com wrote:
>> +                (s->sew < MO_32)) {
>> +                /* SEW < FLEN */
>> +                TCGv_i64 t1 = tcg_temp_new_i64();
>> +                TCGv_i32 sew = tcg_const_i32(1 << (s->sew + 3));
>> +                gen_helper_narrower_nanbox_fpr(t1, cpu_fpr[a->rs1],
>> +                                               sew, cpu_env);
> 
> Also, while there is currently one function, gen_nanbox_s, you'll want to add
> gen_nanbox_h to match.

Oops, I forgot which way your helper worked.
The correct function is gen_check_nanbox_s.


r~