1 | Not much here, mostly documentation, but a few bug fixes. | 1 | arm pullreq for rc1. All minor bugfixes, except for the sve-default-vector-length |
---|---|---|---|
2 | patches, which are somewhere between a bugfix and a new feature. | ||
2 | 3 | ||
3 | thanks | 4 | thanks |
4 | -- PMM | 5 | -- PMM |
5 | 6 | ||
6 | The following changes since commit 873ec69aeb12e24eec7fb317fd0cd8494e8489dd: | 7 | The following changes since commit c08ccd1b53f488ac86c1f65cf7623dc91acc249a: |
7 | 8 | ||
8 | Merge remote-tracking branch 'remotes/cminyard/tags/for-qemu-i2c-5' into staging (2020-07-20 11:03:09 +0100) | 9 | Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210726' into staging (2021-07-27 08:35:01 +0100) |
9 | 10 | ||
10 | are available in the Git repository at: | 11 | are available in the Git repository at: |
11 | 12 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200720 | 13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210727 |
13 | 14 | ||
14 | for you to fetch changes up to 6a0b7505f1fd6769c3f1558fda76464d51e4118a: | 15 | for you to fetch changes up to e229a179a503f2aee43a76888cf12fbdfe8a3749: |
15 | 16 | ||
16 | docs/system: Document the arm virt board (2020-07-20 11:35:17 +0100) | 17 | hw: aspeed_gpio: Fix memory size (2021-07-27 11:00:00 +0100) |
17 | 18 | ||
18 | ---------------------------------------------------------------- | 19 | ---------------------------------------------------------------- |
19 | target-arm queue: | 20 | target-arm queue: |
20 | * virt: Don't enable MTE emulation by default | 21 | * hw/arm/smmuv3: Check 31st bit to see if CD is valid |
21 | * virt: Diagnose attempts to use MTE with memory-hotplug or KVM | 22 | * qemu-options.hx: Fix formatting of -machine memory-backend option |
22 | (rather than silently not working correctly) | 23 | * hw: aspeed_gpio: Fix memory size |
23 | * util: Implement qemu_get_thread_id() for OpenBSD | 24 | * hw/arm/nseries: Display hexadecimal value with '0x' prefix |
24 | * qdev: Add doc comments for qdev_unrealize and GPIO functions, | 25 | * Add sve-default-vector-length cpu property |
25 | and standardize on doc-comments-in-header-file | 26 | * docs: Update path that mentions deprecated.rst |
26 | * hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize() | 27 | * hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS |
27 | * docs/system: Document canon-a1100, collie, gumstix, virt boards | 28 | * hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING |
29 | * hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts | ||
30 | * target/arm: Report M-profile alignment faults correctly to the guest | ||
31 | * target/arm: Add missing 'return's after calling v7m_exception_taken() | ||
32 | * target/arm: Enforce that M-profile SP low 2 bits are always zero | ||
28 | 33 | ||
29 | ---------------------------------------------------------------- | 34 | ---------------------------------------------------------------- |
30 | David CARLIER (1): | 35 | Joe Komlodi (1): |
31 | util: Implement qemu_get_thread_id() for OpenBSD | 36 | hw/arm/smmuv3: Check 31st bit to see if CD is valid |
32 | 37 | ||
33 | Peter Maydell (8): | 38 | Joel Stanley (1): |
34 | qdev: Move doc comments from qdev.c to qdev-core.h | 39 | hw: aspeed_gpio: Fix memory size |
35 | qdev: Document qdev_unrealize() | 40 | |
36 | qdev: Document GPIO related functions | 41 | Mao Zhongyi (1): |
37 | hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize() | 42 | docs: Update path that mentions deprecated.rst |
38 | docs/system: Briefly document canon-a1100 board | 43 | |
39 | docs/system: Briefly document collie board | 44 | Peter Maydell (7): |
40 | docs/system: Briefly document gumstix boards | 45 | qemu-options.hx: Fix formatting of -machine memory-backend option |
41 | docs/system: Document the arm virt board | 46 | target/arm: Enforce that M-profile SP low 2 bits are always zero |
47 | target/arm: Add missing 'return's after calling v7m_exception_taken() | ||
48 | target/arm: Report M-profile alignment faults correctly to the guest | ||
49 | hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts | ||
50 | hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING | ||
51 | hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS | ||
52 | |||
53 | Philippe Mathieu-Daudé (1): | ||
54 | hw/arm/nseries: Display hexadecimal value with '0x' prefix | ||
42 | 55 | ||
43 | Richard Henderson (3): | 56 | Richard Henderson (3): |
44 | hw/arm/virt: Enable MTE via a machine property | 57 | target/arm: Correctly bound length in sve_zcr_get_valid_len |
45 | hw/arm/virt: Error for MTE enabled with KVM | 58 | target/arm: Export aarch64_sve_zcr_get_valid_len |
46 | hw/arm/virt: Disable memory hotplug when MTE is enabled | 59 | target/arm: Add sve-default-vector-length cpu property |
47 | 60 | ||
48 | docs/system/arm/collie.rst | 16 +++ | 61 | docs/system/arm/cpu-features.rst | 15 ++++++++++ |
49 | docs/system/arm/digic.rst | 11 ++ | 62 | configure | 2 +- |
50 | docs/system/arm/gumstix.rst | 21 ++++ | 63 | hw/arm/smmuv3-internal.h | 2 +- |
51 | docs/system/arm/virt.rst | 161 ++++++++++++++++++++++++++ | 64 | target/arm/cpu.h | 5 ++++ |
52 | docs/system/target-arm.rst | 4 + | 65 | target/arm/internals.h | 10 +++++++ |
53 | include/hw/arm/virt.h | 1 + | 66 | hw/arm/nseries.c | 2 +- |
54 | include/hw/qdev-core.h | 267 ++++++++++++++++++++++++++++++++++++++++++- | 67 | hw/gpio/aspeed_gpio.c | 3 +- |
55 | include/hw/qdev-properties.h | 13 +++ | 68 | hw/intc/armv7m_nvic.c | 40 +++++++++++++++++++-------- |
56 | hw/arm/armsse.c | 2 + | 69 | target/arm/cpu.c | 14 ++++++++-- |
57 | hw/arm/virt.c | 50 +++++++- | 70 | target/arm/cpu64.c | 60 ++++++++++++++++++++++++++++++++++++++++ |
58 | hw/core/qdev.c | 33 ------ | 71 | target/arm/gdbstub.c | 4 +++ |
59 | target/arm/cpu.c | 19 +-- | 72 | target/arm/helper.c | 8 ++++-- |
60 | target/arm/cpu64.c | 5 +- | 73 | target/arm/m_helper.c | 24 ++++++++++++---- |
61 | util/oslib-posix.c | 2 + | 74 | target/arm/translate.c | 3 ++ |
62 | MAINTAINERS | 4 + | 75 | target/i386/cpu.c | 2 +- |
63 | 15 files changed, 559 insertions(+), 50 deletions(-) | 76 | MAINTAINERS | 2 +- |
64 | create mode 100644 docs/system/arm/collie.rst | 77 | qemu-options.hx | 30 +++++++++++--------- |
65 | create mode 100644 docs/system/arm/digic.rst | 78 | 17 files changed, 183 insertions(+), 43 deletions(-) |
66 | create mode 100644 docs/system/arm/gumstix.rst | ||
67 | create mode 100644 docs/system/arm/virt.rst | ||
68 | 79 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Joe Komlodi <joe.komlodi@xilinx.com> | ||
1 | 2 | ||
3 | The bit to see if a CD is valid is the last bit of the first word of the CD. | ||
4 | |||
5 | Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com> | ||
6 | Message-id: 1626728232-134665-2-git-send-email-joe.komlodi@xilinx.com | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | hw/arm/smmuv3-internal.h | 2 +- | ||
11 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/hw/arm/smmuv3-internal.h | ||
16 | +++ b/hw/arm/smmuv3-internal.h | ||
17 | @@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste) | ||
18 | |||
19 | /* CD fields */ | ||
20 | |||
21 | -#define CD_VALID(x) extract32((x)->word[0], 30, 1) | ||
22 | +#define CD_VALID(x) extract32((x)->word[0], 31, 1) | ||
23 | #define CD_ASID(x) extract32((x)->word[1], 16, 16) | ||
24 | #define CD_TTB(x, sel) \ | ||
25 | ({ \ | ||
26 | -- | ||
27 | 2.20.1 | ||
28 | |||
29 | diff view generated by jsdifflib |
1 | Document the arm 'virt' board, which has been undocumented | 1 | The documentation of the -machine memory-backend has some minor |
---|---|---|---|
2 | for far too long given that it is the main recommended board | 2 | formatting errors: |
3 | type for arm guests. | 3 | * Misindentation of the initial line meant that the whole option |
4 | section is incorrectly indented in the HTML output compared to | ||
5 | the other -machine options | ||
6 | * The examples weren't indented, which meant that they were formatted | ||
7 | as plain run-on text including outputting the "::" as text. | ||
8 | * The a) b) list has no rst-format markup so it is rendered as | ||
9 | a single run-on paragraph | ||
10 | |||
11 | Fix the formatting. | ||
4 | 12 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 14 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> |
7 | Message-id: 20200713175746.5936-5-peter.maydell@linaro.org | 15 | Message-id: 20210719105257.3599-1-peter.maydell@linaro.org |
8 | --- | 16 | --- |
9 | docs/system/arm/virt.rst | 161 +++++++++++++++++++++++++++++++++++++ | 17 | qemu-options.hx | 30 +++++++++++++++++------------- |
10 | docs/system/target-arm.rst | 1 + | 18 | 1 file changed, 17 insertions(+), 13 deletions(-) |
11 | MAINTAINERS | 1 + | ||
12 | 3 files changed, 163 insertions(+) | ||
13 | create mode 100644 docs/system/arm/virt.rst | ||
14 | 19 | ||
15 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst | 20 | diff --git a/qemu-options.hx b/qemu-options.hx |
16 | new file mode 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
17 | index XXXXXXX..XXXXXXX | 22 | --- a/qemu-options.hx |
18 | --- /dev/null | 23 | +++ b/qemu-options.hx |
19 | +++ b/docs/system/arm/virt.rst | 24 | @@ -XXX,XX +XXX,XX @@ SRST |
20 | @@ -XXX,XX +XXX,XX @@ | 25 | Enables or disables ACPI Heterogeneous Memory Attribute Table |
21 | +'virt' generic virtual platform (``virt``) | 26 | (HMAT) support. The default is off. |
22 | +========================================== | 27 | |
28 | - ``memory-backend='id'`` | ||
29 | + ``memory-backend='id'`` | ||
30 | An alternative to legacy ``-mem-path`` and ``mem-prealloc`` options. | ||
31 | Allows to use a memory backend as main RAM. | ||
32 | |||
33 | For example: | ||
34 | :: | ||
35 | - -object memory-backend-file,id=pc.ram,size=512M,mem-path=/hugetlbfs,prealloc=on,share=on | ||
36 | - -machine memory-backend=pc.ram | ||
37 | - -m 512M | ||
23 | + | 38 | + |
24 | +The `virt` board is a platform which does not correspond to any | 39 | + -object memory-backend-file,id=pc.ram,size=512M,mem-path=/hugetlbfs,prealloc=on,share=on |
25 | +real hardware; it is designed for use in virtual machines. | 40 | + -machine memory-backend=pc.ram |
26 | +It is the recommended board type if you simply want to run | 41 | + -m 512M |
27 | +a guest such as Linux and do not care about reproducing the | 42 | |
28 | +idiosyncrasies and limitations of a particular bit of real-world | 43 | Migration compatibility note: |
29 | +hardware. | 44 | - a) as backend id one shall use value of 'default-ram-id', advertised by |
45 | - machine type (available via ``query-machines`` QMP command), if migration | ||
46 | - to/from old QEMU (<5.0) is expected. | ||
47 | - b) for machine types 4.0 and older, user shall | ||
48 | - use ``x-use-canonical-path-for-ramblock-id=off`` backend option | ||
49 | - if migration to/from old QEMU (<5.0) is expected. | ||
30 | + | 50 | + |
31 | +This is a "versioned" board model, so as well as the ``virt`` machine | 51 | + * as backend id one shall use value of 'default-ram-id', advertised by |
32 | +type itself (which may have improvements, bugfixes and other minor | 52 | + machine type (available via ``query-machines`` QMP command), if migration |
33 | +changes between QEMU versions) a version is provided that guarantees | 53 | + to/from old QEMU (<5.0) is expected. |
34 | +to have the same behaviour as that of previous QEMU releases, so | 54 | + * for machine types 4.0 and older, user shall |
35 | +that VM migration will work between QEMU versions. For instance the | 55 | + use ``x-use-canonical-path-for-ramblock-id=off`` backend option |
36 | +``virt-5.0`` machine type will behave like the ``virt`` machine from | 56 | + if migration to/from old QEMU (<5.0) is expected. |
37 | +the QEMU 5.0 release, and migration should work between ``virt-5.0`` | ||
38 | +of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration | ||
39 | +is not guaranteed to work between different QEMU releases for | ||
40 | +the non-versioned ``virt`` machine type. | ||
41 | + | 57 | + |
42 | +Supported devices | 58 | For example: |
43 | +""""""""""""""""" | 59 | :: |
60 | - -object memory-backend-ram,id=pc.ram,size=512M,x-use-canonical-path-for-ramblock-id=off | ||
61 | - -machine memory-backend=pc.ram | ||
62 | - -m 512M | ||
44 | + | 63 | + |
45 | +The virt board supports: | 64 | + -object memory-backend-ram,id=pc.ram,size=512M,x-use-canonical-path-for-ramblock-id=off |
46 | + | 65 | + -machine memory-backend=pc.ram |
47 | +- PCI/PCIe devices | 66 | + -m 512M |
48 | +- Flash memory | 67 | ERST |
49 | +- One PL011 UART | 68 | |
50 | +- An RTC | 69 | HXCOMM Deprecated by -machine |
51 | +- The fw_cfg device that allows a guest to obtain data from QEMU | ||
52 | +- A PL061 GPIO controller | ||
53 | +- An optional SMMUv3 IOMMU | ||
54 | +- hotpluggable DIMMs | ||
55 | +- hotpluggable NVDIMMs | ||
56 | +- An MSI controller (GICv2M or ITS). GICv2M is selected by default along | ||
57 | + with GICv2. ITS is selected by default with GICv3 (>= virt-2.7). Note | ||
58 | + that ITS is not modeled in TCG mode. | ||
59 | +- 32 virtio-mmio transport devices | ||
60 | +- running guests using the KVM accelerator on aarch64 hardware | ||
61 | +- large amounts of RAM (at least 255GB, and more if using highmem) | ||
62 | +- many CPUs (up to 512 if using a GICv3 and highmem) | ||
63 | +- Secure-World-only devices if the CPU has TrustZone: | ||
64 | + | ||
65 | + - A second PL011 UART | ||
66 | + - A secure flash memory | ||
67 | + - 16MB of secure RAM | ||
68 | + | ||
69 | +Supported guest CPU types: | ||
70 | + | ||
71 | +- ``cortex-a7`` (32-bit) | ||
72 | +- ``cortex-a15`` (32-bit; the default) | ||
73 | +- ``cortex-a53`` (64-bit) | ||
74 | +- ``cortex-a57`` (64-bit) | ||
75 | +- ``cortex-a72`` (64-bit) | ||
76 | +- ``host`` (with KVM only) | ||
77 | +- ``max`` (same as ``host`` for KVM; best possible emulation with TCG) | ||
78 | + | ||
79 | +Note that the default is ``cortex-a15``, so for an AArch64 guest you must | ||
80 | +specify a CPU type. | ||
81 | + | ||
82 | +Graphics output is available, but unlike the x86 PC machine types | ||
83 | +there is no default display device enabled: you should select one from | ||
84 | +the Display devices section of "-device help". The recommended option | ||
85 | +is ``virtio-gpu-pci``; this is the only one which will work correctly | ||
86 | +with KVM. You may also need to ensure your guest kernel is configured | ||
87 | +with support for this; see below. | ||
88 | + | ||
89 | +Machine-specific options | ||
90 | +"""""""""""""""""""""""" | ||
91 | + | ||
92 | +The following machine-specific options are supported: | ||
93 | + | ||
94 | +secure | ||
95 | + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the | ||
96 | + Arm Security Extensions (TrustZone). The default is ``off``. | ||
97 | + | ||
98 | +virtualization | ||
99 | + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the | ||
100 | + Arm Virtualization Extensions. The default is ``off``. | ||
101 | + | ||
102 | +highmem | ||
103 | + Set ``on``/``off`` to enable/disable placing devices and RAM in physical | ||
104 | + address space above 32 bits. The default is ``on`` for machine types | ||
105 | + later than ``virt-2.12``. | ||
106 | + | ||
107 | +gic-version | ||
108 | + Specify the version of the Generic Interrupt Controller (GIC) to provide. | ||
109 | + Valid values are: | ||
110 | + | ||
111 | + ``2`` | ||
112 | + GICv2 | ||
113 | + ``3`` | ||
114 | + GICv3 | ||
115 | + ``host`` | ||
116 | + Use the same GIC version the host provides, when using KVM | ||
117 | + ``max`` | ||
118 | + Use the best GIC version possible (same as host when using KVM; | ||
119 | + currently same as ``3``` for TCG, but this may change in future) | ||
120 | + | ||
121 | +its | ||
122 | + Set ``on``/``off`` to enable/disable ITS instantiation. The default is ``on`` | ||
123 | + for machine types later than ``virt-2.7``. | ||
124 | + | ||
125 | +iommu | ||
126 | + Set the IOMMU type to create for the guest. Valid values are: | ||
127 | + | ||
128 | + ``none`` | ||
129 | + Don't create an IOMMU (the default) | ||
130 | + ``smmuv3`` | ||
131 | + Create an SMMUv3 | ||
132 | + | ||
133 | +ras | ||
134 | + Set ``on``/``off`` to enable/disable reporting host memory errors to a guest | ||
135 | + using ACPI and guest external abort exceptions. The default is off. | ||
136 | + | ||
137 | +Linux guest kernel configuration | ||
138 | +"""""""""""""""""""""""""""""""" | ||
139 | + | ||
140 | +The 'defconfig' for Linux arm and arm64 kernels should include the | ||
141 | +right device drivers for virtio and the PCI controller; however some older | ||
142 | +kernel versions, especially for 32-bit Arm, did not have everything | ||
143 | +enabled by default. If you're not seeing PCI devices that you expect, | ||
144 | +then check that your guest config has:: | ||
145 | + | ||
146 | + CONFIG_PCI=y | ||
147 | + CONFIG_VIRTIO_PCI=y | ||
148 | + CONFIG_PCI_HOST_GENERIC=y | ||
149 | + | ||
150 | +If you want to use the ``virtio-gpu-pci`` graphics device you will also | ||
151 | +need:: | ||
152 | + | ||
153 | + CONFIG_DRM=y | ||
154 | + CONFIG_DRM_VIRTIO_GPU=y | ||
155 | + | ||
156 | +Hardware configuration information for bare-metal programming | ||
157 | +""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" | ||
158 | + | ||
159 | +The ``virt`` board automatically generates a device tree blob ("dtb") | ||
160 | +which it passes to the guest. This provides information about the | ||
161 | +addresses, interrupt lines and other configuration of the various devices | ||
162 | +in the system. Guest code can rely on and hard-code the following | ||
163 | +addresses: | ||
164 | + | ||
165 | +- Flash memory starts at address 0x0000_0000 | ||
166 | + | ||
167 | +- RAM starts at 0x4000_0000 | ||
168 | + | ||
169 | +All other information about device locations may change between | ||
170 | +QEMU versions, so guest code must look in the DTB. | ||
171 | + | ||
172 | +QEMU supports two types of guest image boot for ``virt``, and | ||
173 | +the way for the guest code to locate the dtb binary differs: | ||
174 | + | ||
175 | +- For guests using the Linux kernel boot protocol (this means any | ||
176 | + non-ELF file passed to the QEMU ``-kernel`` option) the address | ||
177 | + of the DTB is passed in a register (``r2`` for 32-bit guests, | ||
178 | + or ``x0`` for 64-bit guests) | ||
179 | + | ||
180 | +- For guests booting as "bare-metal" (any other kind of boot), | ||
181 | + the DTB is at the start of RAM (0x4000_0000) | ||
182 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
183 | index XXXXXXX..XXXXXXX 100644 | ||
184 | --- a/docs/system/target-arm.rst | ||
185 | +++ b/docs/system/target-arm.rst | ||
186 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | ||
187 | arm/collie | ||
188 | arm/sx1 | ||
189 | arm/stellaris | ||
190 | + arm/virt | ||
191 | |||
192 | Arm CPU features | ||
193 | ================ | ||
194 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
195 | index XXXXXXX..XXXXXXX 100644 | ||
196 | --- a/MAINTAINERS | ||
197 | +++ b/MAINTAINERS | ||
198 | @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org | ||
199 | S: Maintained | ||
200 | F: hw/arm/virt* | ||
201 | F: include/hw/arm/virt.h | ||
202 | +F: docs/system/arm/virt.rst | ||
203 | |||
204 | Xilinx Zynq | ||
205 | M: Edgar E. Iglesias <edgar.iglesias@gmail.com> | ||
206 | -- | 70 | -- |
207 | 2.20.1 | 71 | 2.20.1 |
208 | 72 | ||
209 | 73 | diff view generated by jsdifflib |
1 | Add skeletal documentation of the gumstix boards | 1 | For M-profile, unlike A-profile, the low 2 bits of SP are defined to be |
---|---|---|---|
2 | ('connex' and 'verdex'). | 2 | RES0H, which is to say that they must be hardwired to zero so that |
3 | guest attempts to write non-zero values to them are ignored. | ||
4 | |||
5 | Implement this behaviour by masking out the low bits: | ||
6 | * for writes to r13 by the gdbstub | ||
7 | * for writes to any of the various flavours of SP via MSR | ||
8 | * for writes to r13 via store_reg() in generated code | ||
9 | |||
10 | Note that all the direct uses of cpu_R[] in translate.c are in places | ||
11 | where the register is definitely not r13 (usually because that has | ||
12 | been checked for as an UNDEFINED or UNPREDICTABLE case and handled as | ||
13 | UNDEF). | ||
14 | |||
15 | All the other writes to regs[13] in C code are either: | ||
16 | * A-profile only code | ||
17 | * writes of values we can guarantee to be aligned, such as | ||
18 | - writes of previous-SP-value plus or minus a 4-aligned constant | ||
19 | - writes of the value in an SP limit register (which we already | ||
20 | enforce to be aligned) | ||
3 | 21 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 23 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 24 | Message-id: 20210723162146.5167-2-peter.maydell@linaro.org |
7 | Message-id: 20200713175746.5936-4-peter.maydell@linaro.org | ||
8 | --- | 25 | --- |
9 | docs/system/arm/gumstix.rst | 21 +++++++++++++++++++++ | 26 | target/arm/gdbstub.c | 4 ++++ |
10 | docs/system/target-arm.rst | 1 + | 27 | target/arm/m_helper.c | 14 ++++++++------ |
11 | MAINTAINERS | 1 + | 28 | target/arm/translate.c | 3 +++ |
12 | 3 files changed, 23 insertions(+) | 29 | 3 files changed, 15 insertions(+), 6 deletions(-) |
13 | create mode 100644 docs/system/arm/gumstix.rst | ||
14 | 30 | ||
15 | diff --git a/docs/system/arm/gumstix.rst b/docs/system/arm/gumstix.rst | 31 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c |
16 | new file mode 100644 | 32 | index XXXXXXX..XXXXXXX 100644 |
17 | index XXXXXXX..XXXXXXX | 33 | --- a/target/arm/gdbstub.c |
18 | --- /dev/null | 34 | +++ b/target/arm/gdbstub.c |
19 | +++ b/docs/system/arm/gumstix.rst | 35 | @@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) |
20 | @@ -XXX,XX +XXX,XX @@ | 36 | |
21 | +Gumstix Connex and Verdex (``connex``, ``verdex``) | 37 | if (n < 16) { |
22 | +================================================== | 38 | /* Core integer register. */ |
39 | + if (n == 13 && arm_feature(env, ARM_FEATURE_M)) { | ||
40 | + /* M profile SP low bits are always 0 */ | ||
41 | + tmp &= ~3; | ||
42 | + } | ||
43 | env->regs[n] = tmp; | ||
44 | return 4; | ||
45 | } | ||
46 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/m_helper.c | ||
49 | +++ b/target/arm/m_helper.c | ||
50 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | ||
51 | if (!env->v7m.secure) { | ||
52 | return; | ||
53 | } | ||
54 | - env->v7m.other_ss_msp = val; | ||
55 | + env->v7m.other_ss_msp = val & ~3; | ||
56 | return; | ||
57 | case 0x89: /* PSP_NS */ | ||
58 | if (!env->v7m.secure) { | ||
59 | return; | ||
60 | } | ||
61 | - env->v7m.other_ss_psp = val; | ||
62 | + env->v7m.other_ss_psp = val & ~3; | ||
63 | return; | ||
64 | case 0x8a: /* MSPLIM_NS */ | ||
65 | if (!env->v7m.secure) { | ||
66 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | ||
67 | |||
68 | limit = is_psp ? env->v7m.psplim[false] : env->v7m.msplim[false]; | ||
69 | |||
70 | + val &= ~0x3; | ||
23 | + | 71 | + |
24 | +These machines model the Gumstix Connex and Verdex boards. | 72 | if (val < limit) { |
25 | +The Connex has a PXA255 CPU and the Verdex has a PXA270. | 73 | raise_exception_ra(env, EXCP_STKOF, 0, 1, GETPC()); |
26 | + | 74 | } |
27 | +Implemented devices: | 75 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) |
28 | + | 76 | break; |
29 | + * NOR flash | 77 | case 8: /* MSP */ |
30 | + * SMC91C111 ethernet | 78 | if (v7m_using_psp(env)) { |
31 | + * Interrupt controller | 79 | - env->v7m.other_sp = val; |
32 | + * DMA | 80 | + env->v7m.other_sp = val & ~3; |
33 | + * Timer | 81 | } else { |
34 | + * GPIO | 82 | - env->regs[13] = val; |
35 | + * MMC/SD card | 83 | + env->regs[13] = val & ~3; |
36 | + * Fast infra-red communications port (FIR) | 84 | } |
37 | + * LCD controller | 85 | break; |
38 | + * Synchronous serial ports (SPI) | 86 | case 9: /* PSP */ |
39 | + * PCMCIA interface | 87 | if (v7m_using_psp(env)) { |
40 | + * I2C | 88 | - env->regs[13] = val; |
41 | + * I2S | 89 | + env->regs[13] = val & ~3; |
42 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | 90 | } else { |
91 | - env->v7m.other_sp = val; | ||
92 | + env->v7m.other_sp = val & ~3; | ||
93 | } | ||
94 | break; | ||
95 | case 10: /* MSPLIM */ | ||
96 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | 97 | index XXXXXXX..XXXXXXX 100644 |
44 | --- a/docs/system/target-arm.rst | 98 | --- a/target/arm/translate.c |
45 | +++ b/docs/system/target-arm.rst | 99 | +++ b/target/arm/translate.c |
46 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | 100 | @@ -XXX,XX +XXX,XX @@ void store_reg(DisasContext *s, int reg, TCGv_i32 var) |
47 | arm/aspeed | 101 | */ |
48 | arm/digic | 102 | tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3); |
49 | arm/musicpal | 103 | s->base.is_jmp = DISAS_JUMP; |
50 | + arm/gumstix | 104 | + } else if (reg == 13 && arm_dc_feature(s, ARM_FEATURE_M)) { |
51 | arm/nseries | 105 | + /* For M-profile SP bits [1:0] are always zero */ |
52 | arm/orangepi | 106 | + tcg_gen_andi_i32(var, var, ~3); |
53 | arm/palm | 107 | } |
54 | diff --git a/MAINTAINERS b/MAINTAINERS | 108 | tcg_gen_mov_i32(cpu_R[reg], var); |
55 | index XXXXXXX..XXXXXXX 100644 | 109 | tcg_temp_free_i32(var); |
56 | --- a/MAINTAINERS | ||
57 | +++ b/MAINTAINERS | ||
58 | @@ -XXX,XX +XXX,XX @@ R: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
59 | L: qemu-arm@nongnu.org | ||
60 | S: Odd Fixes | ||
61 | F: hw/arm/gumstix.c | ||
62 | +F: docs/system/arm/gumstix.rst | ||
63 | |||
64 | i.MX25 PDK | ||
65 | M: Peter Maydell <peter.maydell@linaro.org> | ||
66 | -- | 110 | -- |
67 | 2.20.1 | 111 | 2.20.1 |
68 | 112 | ||
69 | 113 | diff view generated by jsdifflib |
1 | In armsse_realize() we have a loop over [0, info->num_cpus), which | 1 | In do_v7m_exception_exit(), we perform various checks as part of |
---|---|---|---|
2 | indexes into various fixed-size arrays in the ARMSSE struct. This | 2 | performing the exception return. If one of these checks fails, the |
3 | confuses Coverity, which warns that we might overrun those arrays | 3 | architecture requires that we take an appropriate exception on the |
4 | (CID 1430326, 1430337, 1430371, 1430414, 1430430). This can't | 4 | existing stackframe. We implement this by calling |
5 | actually happen, because the info struct is always one of the entries | 5 | v7m_exception_taken() to set up to take the new exception, and then |
6 | in the armsse_variants[] array and num_cpus is either 1 or 2; we also | 6 | immediately returning from do_v7m_exception_exit() without proceeding |
7 | already assert in armsse_init() that num_cpus is not too large. | 7 | any further with the unstack-and-exception-return process. |
8 | However, adding an assert to armsse_realize() like the one in | 8 | |
9 | armsse_init() should help Coverity figure out that these code paths | 9 | In a couple of checks that are new in v8.1M, we forgot the "return" |
10 | aren't possible. | 10 | statement, with the effect that if bad code in the guest tripped over |
11 | these checks we would set up to take a UsageFault exception but then | ||
12 | blunder on trying to also unstack and return from the original | ||
13 | exception, with the probable result that the guest would crash. | ||
14 | |||
15 | Add the missing return statements. | ||
11 | 16 | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
14 | Message-id: 20200713143716.9881-1-peter.maydell@linaro.org | 19 | Message-id: 20210723162146.5167-3-peter.maydell@linaro.org |
15 | --- | 20 | --- |
16 | hw/arm/armsse.c | 2 ++ | 21 | target/arm/m_helper.c | 2 ++ |
17 | 1 file changed, 2 insertions(+) | 22 | 1 file changed, 2 insertions(+) |
18 | 23 | ||
19 | diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c | 24 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c |
20 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/arm/armsse.c | 26 | --- a/target/arm/m_helper.c |
22 | +++ b/hw/arm/armsse.c | 27 | +++ b/target/arm/m_helper.c |
23 | @@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp) | 28 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) |
24 | return; | 29 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " |
25 | } | 30 | "stackframe: NSACR prevents clearing FPU registers\n"); |
26 | 31 | v7m_exception_taken(cpu, excret, true, false); | |
27 | + assert(info->num_cpus <= SSE_MAX_CPUS); | 32 | + return; |
28 | + | 33 | } else if (!cpacr_pass) { |
29 | /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ | 34 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, |
30 | assert(is_power_of_2(info->sram_banks)); | 35 | exc_secure); |
31 | addr_width_max = 24 - ctz32(info->sram_banks); | 36 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) |
37 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " | ||
38 | "stackframe: CPACR prevents clearing FPU registers\n"); | ||
39 | v7m_exception_taken(cpu, excret, true, false); | ||
40 | + return; | ||
41 | } | ||
42 | } | ||
43 | /* Clear s0..s15, FPSCR and VPR */ | ||
32 | -- | 44 | -- |
33 | 2.20.1 | 45 | 2.20.1 |
34 | 46 | ||
35 | 47 | diff view generated by jsdifflib |
1 | Add skeletal documentation of the canon-a1100 board. | 1 | For M-profile, we weren't reporting alignment faults triggered by the |
---|---|---|---|
2 | generic TCG code correctly to the guest. These get passed into | ||
3 | arm_v7m_cpu_do_interrupt() as an EXCP_DATA_ABORT with an A-profile | ||
4 | style exception.fsr value of 1. We didn't check for this, and so | ||
5 | they fell through into the default of "assume this is an MPU fault" | ||
6 | and were reported to the guest as a data access violation MPU fault. | ||
7 | |||
8 | Report these alignment faults as UsageFaults which set the UNALIGNED | ||
9 | bit in the UFSR. | ||
2 | 10 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 13 | Message-id: 20210723162146.5167-4-peter.maydell@linaro.org |
6 | Message-id: 20200713175746.5936-2-peter.maydell@linaro.org | ||
7 | --- | 14 | --- |
8 | docs/system/arm/digic.rst | 11 +++++++++++ | 15 | target/arm/m_helper.c | 8 ++++++++ |
9 | docs/system/target-arm.rst | 1 + | 16 | 1 file changed, 8 insertions(+) |
10 | MAINTAINERS | 1 + | ||
11 | 3 files changed, 13 insertions(+) | ||
12 | create mode 100644 docs/system/arm/digic.rst | ||
13 | 17 | ||
14 | diff --git a/docs/system/arm/digic.rst b/docs/system/arm/digic.rst | 18 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c |
15 | new file mode 100644 | ||
16 | index XXXXXXX..XXXXXXX | ||
17 | --- /dev/null | ||
18 | +++ b/docs/system/arm/digic.rst | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | +Canon A1100 (``canon-a1100``) | ||
21 | +============================= | ||
22 | + | ||
23 | +This machine is a model of the Canon PowerShot A1100 camera, which | ||
24 | +uses the DIGIC SoC. This model is based on reverse engineering efforts | ||
25 | +by the contributors to the `CHDK <http://chdk.wikia.com/>`_ and | ||
26 | +`Magic Lantern <http://www.magiclantern.fm/>`_ projects. | ||
27 | + | ||
28 | +The emulation is incomplete. In particular it can't be used | ||
29 | +to run the original camera firmware, but it can successfully run | ||
30 | +an experimental version of the `barebox bootloader <http://www.barebox.org/>`_. | ||
31 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
32 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
33 | --- a/docs/system/target-arm.rst | 20 | --- a/target/arm/m_helper.c |
34 | +++ b/docs/system/target-arm.rst | 21 | +++ b/target/arm/m_helper.c |
35 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | 22 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) |
36 | arm/versatile | 23 | env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK; |
37 | arm/vexpress | 24 | break; |
38 | arm/aspeed | 25 | case EXCP_UNALIGNED: |
39 | + arm/digic | 26 | + /* Unaligned faults reported by M-profile aware code */ |
40 | arm/musicpal | 27 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); |
41 | arm/nseries | 28 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK; |
42 | arm/orangepi | 29 | break; |
43 | diff --git a/MAINTAINERS b/MAINTAINERS | 30 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) |
44 | index XXXXXXX..XXXXXXX 100644 | 31 | } |
45 | --- a/MAINTAINERS | 32 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); |
46 | +++ b/MAINTAINERS | 33 | break; |
47 | @@ -XXX,XX +XXX,XX @@ F: include/hw/arm/digic.h | 34 | + case 0x1: /* Alignment fault reported by generic code */ |
48 | F: hw/*/digic* | 35 | + qemu_log_mask(CPU_LOG_INT, |
49 | F: include/hw/*/digic* | 36 | + "...really UsageFault with UFSR.UNALIGNED\n"); |
50 | F: tests/acceptance/machine_arm_canona1100.py | 37 | + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK; |
51 | +F: docs/system/arm/digic.rst | 38 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, |
52 | 39 | + env->v7m.secure); | |
53 | Goldfish RTC | 40 | + break; |
54 | M: Anup Patel <anup.patel@wdc.com> | 41 | default: |
42 | /* | ||
43 | * All other FSR values are either MPU faults or "can't happen | ||
55 | -- | 44 | -- |
56 | 2.20.1 | 45 | 2.20.1 |
57 | 46 | ||
58 | 47 | diff view generated by jsdifflib |
1 | Add documentation comments for the various qdev functions | 1 | The ISCR.ISRPENDING bit is set when an external interrupt is pending. |
---|---|---|---|
2 | related to creating and connecting GPIO lines. | 2 | This is true whether that external interrupt is enabled or not. |
3 | This means that we can't use 's->vectpending == 0' as a shortcut to | ||
4 | "ISRPENDING is zero", because s->vectpending indicates only the | ||
5 | highest priority pending enabled interrupt. | ||
6 | |||
7 | Remove the incorrect optimization so that if there is no pending | ||
8 | enabled interrupt we fall through to scanning through the whole | ||
9 | interrupt array. | ||
3 | 10 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 20200711142425.16283-4-peter.maydell@linaro.org | 13 | Message-id: 20210723162146.5167-5-peter.maydell@linaro.org |
7 | --- | 14 | --- |
8 | include/hw/qdev-core.h | 191 ++++++++++++++++++++++++++++++++++++++++- | 15 | hw/intc/armv7m_nvic.c | 9 ++++----- |
9 | 1 file changed, 189 insertions(+), 2 deletions(-) | 16 | 1 file changed, 4 insertions(+), 5 deletions(-) |
10 | 17 | ||
11 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | 18 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c |
12 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/include/hw/qdev-core.h | 20 | --- a/hw/intc/armv7m_nvic.c |
14 | +++ b/include/hw/qdev-core.h | 21 | +++ b/hw/intc/armv7m_nvic.c |
15 | @@ -XXX,XX +XXX,XX @@ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev, | 22 | @@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s) |
16 | void qdev_machine_creation_done(void); | 23 | { |
17 | bool qdev_machine_modified(void); | 24 | int irq; |
18 | 25 | ||
19 | +/** | 26 | - /* We can shortcut if the highest priority pending interrupt |
20 | + * qdev_get_gpio_in: Get one of a device's anonymous input GPIO lines | 27 | - * happens to be external or if there is nothing pending. |
21 | + * @dev: Device whose GPIO we want | 28 | + /* |
22 | + * @n: Number of the anonymous GPIO line (which must be in range) | 29 | + * We can shortcut if the highest priority pending interrupt |
23 | + * | 30 | + * happens to be external; if not we need to check the whole |
24 | + * Returns the qemu_irq corresponding to an anonymous input GPIO line | 31 | + * vectors[] array. |
25 | + * (which the device has set up with qdev_init_gpio_in()). The index | 32 | */ |
26 | + * @n of the GPIO line must be valid (i.e. be at least 0 and less than | 33 | if (s->vectpending > NVIC_FIRST_IRQ) { |
27 | + * the total number of anonymous input GPIOs the device has); this | 34 | return true; |
28 | + * function will assert() if passed an invalid index. | 35 | } |
29 | + * | 36 | - if (s->vectpending == 0) { |
30 | + * This function is intended to be used by board code or SoC "container" | 37 | - return false; |
31 | + * device models to wire up the GPIO lines; usually the return value | 38 | - } |
32 | + * will be passed to qdev_connect_gpio_out() or a similar function to | 39 | |
33 | + * connect another device's output GPIO line to this input. | 40 | for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) { |
34 | + * | 41 | if (s->vectors[irq].pending) { |
35 | + * For named input GPIO lines, use qdev_get_gpio_in_named(). | ||
36 | + */ | ||
37 | qemu_irq qdev_get_gpio_in(DeviceState *dev, int n); | ||
38 | +/** | ||
39 | + * qdev_get_gpio_in_named: Get one of a device's named input GPIO lines | ||
40 | + * @dev: Device whose GPIO we want | ||
41 | + * @name: Name of the input GPIO array | ||
42 | + * @n: Number of the GPIO line in that array (which must be in range) | ||
43 | + * | ||
44 | + * Returns the qemu_irq corresponding to a named input GPIO line | ||
45 | + * (which the device has set up with qdev_init_gpio_in_named()). | ||
46 | + * The @name string must correspond to an input GPIO array which exists on | ||
47 | + * the device, and the index @n of the GPIO line must be valid (i.e. | ||
48 | + * be at least 0 and less than the total number of input GPIOs in that | ||
49 | + * array); this function will assert() if passed an invalid name or index. | ||
50 | + * | ||
51 | + * For anonymous input GPIO lines, use qdev_get_gpio_in(). | ||
52 | + */ | ||
53 | qemu_irq qdev_get_gpio_in_named(DeviceState *dev, const char *name, int n); | ||
54 | |||
55 | +/** | ||
56 | + * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines | ||
57 | + * @dev: Device whose GPIO to connect | ||
58 | + * @n: Number of the anonymous output GPIO line (which must be in range) | ||
59 | + * @pin: qemu_irq to connect the output line to | ||
60 | + * | ||
61 | + * This function connects an anonymous output GPIO line on a device | ||
62 | + * up to an arbitrary qemu_irq, so that when the device asserts that | ||
63 | + * output GPIO line, the qemu_irq's callback is invoked. | ||
64 | + * The index @n of the GPIO line must be valid (i.e. be at least 0 and | ||
65 | + * less than the total number of anonymous output GPIOs the device has | ||
66 | + * created with qdev_init_gpio_out()); otherwise this function will assert(). | ||
67 | + * | ||
68 | + * Outbound GPIO lines can be connected to any qemu_irq, but the common | ||
69 | + * case is connecting them to another device's inbound GPIO line, using | ||
70 | + * the qemu_irq returned by qdev_get_gpio_in() or qdev_get_gpio_in_named(). | ||
71 | + * | ||
72 | + * It is not valid to try to connect one outbound GPIO to multiple | ||
73 | + * qemu_irqs at once, or to connect multiple outbound GPIOs to the | ||
74 | + * same qemu_irq. (Warning: there is no assertion or other guard to | ||
75 | + * catch this error: the model will just not do the right thing.) | ||
76 | + * Instead, for fan-out you can use the TYPE_IRQ_SPLIT device: connect | ||
77 | + * a device's outbound GPIO to the splitter's input, and connect each | ||
78 | + * of the splitter's outputs to a different device. For fan-in you | ||
79 | + * can use the TYPE_OR_IRQ device, which is a model of a logical OR | ||
80 | + * gate with multiple inputs and one output. | ||
81 | + * | ||
82 | + * For named output GPIO lines, use qdev_connect_gpio_out_named(). | ||
83 | + */ | ||
84 | void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin); | ||
85 | +/** | ||
86 | + * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines | ||
87 | + * @dev: Device whose GPIO to connect | ||
88 | + * @name: Name of the output GPIO array | ||
89 | + * @n: Number of the anonymous output GPIO line (which must be in range) | ||
90 | + * @pin: qemu_irq to connect the output line to | ||
91 | + * | ||
92 | + * This function connects an anonymous output GPIO line on a device | ||
93 | + * up to an arbitrary qemu_irq, so that when the device asserts that | ||
94 | + * output GPIO line, the qemu_irq's callback is invoked. | ||
95 | + * The @name string must correspond to an output GPIO array which exists on | ||
96 | + * the device, and the index @n of the GPIO line must be valid (i.e. | ||
97 | + * be at least 0 and less than the total number of input GPIOs in that | ||
98 | + * array); this function will assert() if passed an invalid name or index. | ||
99 | + * | ||
100 | + * Outbound GPIO lines can be connected to any qemu_irq, but the common | ||
101 | + * case is connecting them to another device's inbound GPIO line, using | ||
102 | + * the qemu_irq returned by qdev_get_gpio_in() or qdev_get_gpio_in_named(). | ||
103 | + * | ||
104 | + * It is not valid to try to connect one outbound GPIO to multiple | ||
105 | + * qemu_irqs at once, or to connect multiple outbound GPIOs to the | ||
106 | + * same qemu_irq; see qdev_connect_gpio_out() for details. | ||
107 | + * | ||
108 | + * For named output GPIO lines, use qdev_connect_gpio_out_named(). | ||
109 | + */ | ||
110 | void qdev_connect_gpio_out_named(DeviceState *dev, const char *name, int n, | ||
111 | qemu_irq pin); | ||
112 | +/** | ||
113 | + * qdev_get_gpio_out_connector: Get the qemu_irq connected to an output GPIO | ||
114 | + * @dev: Device whose output GPIO we are interested in | ||
115 | + * @name: Name of the output GPIO array | ||
116 | + * @n: Number of the output GPIO line within that array | ||
117 | + * | ||
118 | + * Returns whatever qemu_irq is currently connected to the specified | ||
119 | + * output GPIO line of @dev. This will be NULL if the output GPIO line | ||
120 | + * has never been wired up to the anything. Note that the qemu_irq | ||
121 | + * returned does not belong to @dev -- it will be the input GPIO or | ||
122 | + * IRQ of whichever device the board code has connected up to @dev's | ||
123 | + * output GPIO. | ||
124 | + * | ||
125 | + * You probably don't need to use this function -- it is used only | ||
126 | + * by the platform-bus subsystem. | ||
127 | + */ | ||
128 | qemu_irq qdev_get_gpio_out_connector(DeviceState *dev, const char *name, int n); | ||
129 | +/** | ||
130 | + * qdev_intercept_gpio_out: Intercept an existing GPIO connection | ||
131 | + * @dev: Device to intercept the outbound GPIO line from | ||
132 | + * @icpt: New qemu_irq to connect instead | ||
133 | + * @name: Name of the output GPIO array | ||
134 | + * @n: Number of the GPIO line in the array | ||
135 | + * | ||
136 | + * This function is provided only for use by the qtest testing framework | ||
137 | + * and is not suitable for use in non-testing parts of QEMU. | ||
138 | + * | ||
139 | + * This function breaks an existing connection of an outbound GPIO | ||
140 | + * line from @dev, and replaces it with the new qemu_irq @icpt, as if | ||
141 | + * ``qdev_connect_gpio_out_named(dev, icpt, name, n)`` had been called. | ||
142 | + * The previously connected qemu_irq is returned, so it can be restored | ||
143 | + * by a second call to qdev_intercept_gpio_out() if desired. | ||
144 | + */ | ||
145 | qemu_irq qdev_intercept_gpio_out(DeviceState *dev, qemu_irq icpt, | ||
146 | const char *name, int n); | ||
147 | |||
148 | @@ -XXX,XX +XXX,XX @@ BusState *qdev_get_child_bus(DeviceState *dev, const char *name); | ||
149 | |||
150 | /*** Device API. ***/ | ||
151 | |||
152 | -/* Register device properties. */ | ||
153 | -/* GPIO inputs also double as IRQ sinks. */ | ||
154 | +/** | ||
155 | + * qdev_init_gpio_in: create an array of anonymous input GPIO lines | ||
156 | + * @dev: Device to create input GPIOs for | ||
157 | + * @handler: Function to call when GPIO line value is set | ||
158 | + * @n: Number of GPIO lines to create | ||
159 | + * | ||
160 | + * Devices should use functions in the qdev_init_gpio_in* family in | ||
161 | + * their instance_init or realize methods to create any input GPIO | ||
162 | + * lines they need. There is no functional difference between | ||
163 | + * anonymous and named GPIO lines. Stylistically, named GPIOs are | ||
164 | + * preferable (easier to understand at callsites) unless a device | ||
165 | + * has exactly one uniform kind of GPIO input whose purpose is obvious. | ||
166 | + * Note that input GPIO lines can serve as 'sinks' for IRQ lines. | ||
167 | + * | ||
168 | + * See qdev_get_gpio_in() for how code that uses such a device can get | ||
169 | + * hold of an input GPIO line to manipulate it. | ||
170 | + */ | ||
171 | void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n); | ||
172 | +/** | ||
173 | + * qdev_init_gpio_out: create an array of anonymous output GPIO lines | ||
174 | + * @dev: Device to create output GPIOs for | ||
175 | + * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines | ||
176 | + * @n: Number of GPIO lines to create | ||
177 | + * | ||
178 | + * Devices should use functions in the qdev_init_gpio_out* family | ||
179 | + * in their instance_init or realize methods to create any output | ||
180 | + * GPIO lines they need. There is no functional difference between | ||
181 | + * anonymous and named GPIO lines. Stylistically, named GPIOs are | ||
182 | + * preferable (easier to understand at callsites) unless a device | ||
183 | + * has exactly one uniform kind of GPIO output whose purpose is obvious. | ||
184 | + * | ||
185 | + * The @pins argument should be a pointer to either a "qemu_irq" | ||
186 | + * (if @n == 1) or a "qemu_irq []" array (if @n > 1) in the device's | ||
187 | + * state structure. The device implementation can then raise and | ||
188 | + * lower the GPIO line by calling qemu_set_irq(). (If anything is | ||
189 | + * connected to the other end of the GPIO this will cause the handler | ||
190 | + * function for that input GPIO to be called.) | ||
191 | + * | ||
192 | + * See qdev_connect_gpio_out() for how code that uses such a device | ||
193 | + * can connect to one of its output GPIO lines. | ||
194 | + */ | ||
195 | void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n); | ||
196 | +/** | ||
197 | + * qdev_init_gpio_out: create an array of named output GPIO lines | ||
198 | + * @dev: Device to create output GPIOs for | ||
199 | + * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines | ||
200 | + * @name: Name to give this array of GPIO lines | ||
201 | + * @n: Number of GPIO lines to create | ||
202 | + * | ||
203 | + * Like qdev_init_gpio_out(), but creates an array of GPIO output lines | ||
204 | + * with a name. Code using the device can then connect these GPIO lines | ||
205 | + * using qdev_connect_gpio_out_named(). | ||
206 | + */ | ||
207 | void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins, | ||
208 | const char *name, int n); | ||
209 | /** | ||
210 | @@ -XXX,XX +XXX,XX @@ static inline void qdev_init_gpio_in_named(DeviceState *dev, | ||
211 | qdev_init_gpio_in_named_with_opaque(dev, handler, dev, name, n); | ||
212 | } | ||
213 | |||
214 | +/** | ||
215 | + * qdev_pass_gpios: create GPIO lines on container which pass through to device | ||
216 | + * @dev: Device which has GPIO lines | ||
217 | + * @container: Container device which needs to expose them | ||
218 | + * @name: Name of GPIO array to pass through (NULL for the anonymous GPIO array) | ||
219 | + * | ||
220 | + * In QEMU, complicated devices like SoCs are often modelled with a | ||
221 | + * "container" QOM device which itself contains other QOM devices and | ||
222 | + * which wires them up appropriately. This function allows the container | ||
223 | + * to create GPIO arrays on itself which simply pass through to a GPIO | ||
224 | + * array of one of its internal devices. | ||
225 | + * | ||
226 | + * If @dev has both input and output GPIOs named @name then both will | ||
227 | + * be passed through. It is not possible to pass a subset of the array | ||
228 | + * with this function. | ||
229 | + * | ||
230 | + * To users of the container device, the GPIO array created on @container | ||
231 | + * behaves exactly like any other. | ||
232 | + */ | ||
233 | void qdev_pass_gpios(DeviceState *dev, DeviceState *container, | ||
234 | const char *name); | ||
235 | |||
236 | -- | 42 | -- |
237 | 2.20.1 | 43 | 2.20.1 |
238 | 44 | ||
239 | 45 | diff view generated by jsdifflib |
1 | Add a doc comment for qdev_unrealize(), to go with the new | 1 | The VECTPENDING field in the ICSR is 9 bits wide, in bits [20:12] of |
---|---|---|---|
2 | documentation for the realize part of the qdev lifecycle. | 2 | the register. We were incorrectly masking it to 8 bits, so it would |
3 | report the wrong value if the pending exception was greater than 256. | ||
4 | Fix the bug. | ||
3 | 5 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 20200711142425.16283-3-peter.maydell@linaro.org | 8 | Message-id: 20210723162146.5167-6-peter.maydell@linaro.org |
7 | --- | 9 | --- |
8 | include/hw/qdev-core.h | 19 +++++++++++++++++++ | 10 | hw/intc/armv7m_nvic.c | 2 +- |
9 | 1 file changed, 19 insertions(+) | 11 | 1 file changed, 1 insertion(+), 1 deletion(-) |
10 | 12 | ||
11 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | 13 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c |
12 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/include/hw/qdev-core.h | 15 | --- a/hw/intc/armv7m_nvic.c |
14 | +++ b/include/hw/qdev-core.h | 16 | +++ b/hw/intc/armv7m_nvic.c |
15 | @@ -XXX,XX +XXX,XX @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp); | 17 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) |
16 | * would be incorrect. For that use case you want qdev_realize(). | 18 | /* VECTACTIVE */ |
17 | */ | 19 | val = cpu->env.v7m.exception; |
18 | bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp); | 20 | /* VECTPENDING */ |
19 | +/** | 21 | - val |= (s->vectpending & 0xff) << 12; |
20 | + * qdev_unrealize: Unrealize a device | 22 | + val |= (s->vectpending & 0x1ff) << 12; |
21 | + * @dev: device to unrealize | 23 | /* ISRPENDING - set if any external IRQ is pending */ |
22 | + * | 24 | if (nvic_isrpending(s)) { |
23 | + * This function will "unrealize" a device, which is the first phase | 25 | val |= (1 << 22); |
24 | + * of correctly destroying a device that has been realized. It will: | ||
25 | + * | ||
26 | + * - unrealize any child buses by calling qbus_unrealize() | ||
27 | + * (this will recursively unrealize any devices on those buses) | ||
28 | + * - call the the unrealize method of @dev | ||
29 | + * | ||
30 | + * The device can then be freed by causing its reference count to go | ||
31 | + * to zero. | ||
32 | + * | ||
33 | + * Warning: most devices in QEMU do not expect to be unrealized. Only | ||
34 | + * devices which are hot-unpluggable should be unrealized (as part of | ||
35 | + * the unplugging process); all other devices are expected to last for | ||
36 | + * the life of the simulation and should not be unrealized and freed. | ||
37 | + */ | ||
38 | void qdev_unrealize(DeviceState *dev); | ||
39 | void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id, | ||
40 | int required_for_version); | ||
41 | -- | 26 | -- |
42 | 2.20.1 | 27 | 2.20.1 |
43 | 28 | ||
44 | 29 | diff view generated by jsdifflib |
1 | The doc-comments which document the qdev API are split between the | 1 | In Arm v8.1M the VECTPENDING field in the ICSR has new behaviour: if |
---|---|---|---|
2 | header file and the C source files, because as a project we haven't | 2 | the register is accessed NonSecure and the highest priority pending |
3 | been consistent about where we put them. | 3 | enabled exception (that would be returned in the VECTPENDING field) |
4 | 4 | targets Secure, then the VECTPENDING field must read 1 rather than | |
5 | Move all the doc-comments in qdev.c to the header files, so that | 5 | the exception number of the pending exception. Implement this. |
6 | users of the APIs don't have to look at the implementation files for | ||
7 | this information. | ||
8 | |||
9 | In the process, unify them into our doc-comment format and expand on | ||
10 | them in some cases to clarify expected use cases. | ||
11 | 6 | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
14 | Message-id: 20200711142425.16283-2-peter.maydell@linaro.org | 9 | Message-id: 20210723162146.5167-7-peter.maydell@linaro.org |
15 | --- | 10 | --- |
16 | include/hw/qdev-core.h | 57 ++++++++++++++++++++++++++++++++++++ | 11 | hw/intc/armv7m_nvic.c | 31 ++++++++++++++++++++++++------- |
17 | include/hw/qdev-properties.h | 13 ++++++++ | 12 | 1 file changed, 24 insertions(+), 7 deletions(-) |
18 | hw/core/qdev.c | 33 --------------------- | ||
19 | 3 files changed, 70 insertions(+), 33 deletions(-) | ||
20 | 13 | ||
21 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | 14 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c |
22 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/include/hw/qdev-core.h | 16 | --- a/hw/intc/armv7m_nvic.c |
24 | +++ b/include/hw/qdev-core.h | 17 | +++ b/hw/intc/armv7m_nvic.c |
25 | @@ -XXX,XX +XXX,XX @@ compat_props_add(GPtrArray *arr, | 18 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque) |
26 | 19 | nvic_irq_update(s); | |
27 | /*** Board API. This should go away once we have a machine config file. ***/ | ||
28 | |||
29 | +/** | ||
30 | + * qdev_new: Create a device on the heap | ||
31 | + * @name: device type to create (we assert() that this type exists) | ||
32 | + * | ||
33 | + * This only allocates the memory and initializes the device state | ||
34 | + * structure, ready for the caller to set properties if they wish. | ||
35 | + * The device still needs to be realized. | ||
36 | + * The returned object has a reference count of 1. | ||
37 | + */ | ||
38 | DeviceState *qdev_new(const char *name); | ||
39 | +/** | ||
40 | + * qdev_try_new: Try to create a device on the heap | ||
41 | + * @name: device type to create | ||
42 | + * | ||
43 | + * This is like qdev_new(), except it returns %NULL when type @name | ||
44 | + * does not exist, rather than asserting. | ||
45 | + */ | ||
46 | DeviceState *qdev_try_new(const char *name); | ||
47 | +/** | ||
48 | + * qdev_realize: Realize @dev. | ||
49 | + * @dev: device to realize | ||
50 | + * @bus: bus to plug it into (may be NULL) | ||
51 | + * @errp: pointer to error object | ||
52 | + * | ||
53 | + * "Realize" the device, i.e. perform the second phase of device | ||
54 | + * initialization. | ||
55 | + * @dev must not be plugged into a bus already. | ||
56 | + * If @bus, plug @dev into @bus. This takes a reference to @dev. | ||
57 | + * If @dev has no QOM parent, make one up, taking another reference. | ||
58 | + * On success, return true. | ||
59 | + * On failure, store an error through @errp and return false. | ||
60 | + * | ||
61 | + * If you created @dev using qdev_new(), you probably want to use | ||
62 | + * qdev_realize_and_unref() instead. | ||
63 | + */ | ||
64 | bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp); | ||
65 | +/** | ||
66 | + * qdev_realize_and_unref: Realize @dev and drop a reference | ||
67 | + * @dev: device to realize | ||
68 | + * @bus: bus to plug it into (may be NULL) | ||
69 | + * @errp: pointer to error object | ||
70 | + * | ||
71 | + * Realize @dev and drop a reference. | ||
72 | + * This is like qdev_realize(), except the caller must hold a | ||
73 | + * (private) reference, which is dropped on return regardless of | ||
74 | + * success or failure. Intended use:: | ||
75 | + * | ||
76 | + * dev = qdev_new(); | ||
77 | + * [...] | ||
78 | + * qdev_realize_and_unref(dev, bus, errp); | ||
79 | + * | ||
80 | + * Now @dev can go away without further ado. | ||
81 | + * | ||
82 | + * If you are embedding the device into some other QOM device and | ||
83 | + * initialized it via some variant on object_initialize_child() then | ||
84 | + * do not use this function, because that family of functions arrange | ||
85 | + * for the only reference to the child device to be held by the parent | ||
86 | + * via the child<> property, and so the reference-count-drop done here | ||
87 | + * would be incorrect. For that use case you want qdev_realize(). | ||
88 | + */ | ||
89 | bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp); | ||
90 | void qdev_unrealize(DeviceState *dev); | ||
91 | void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id, | ||
92 | diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h | ||
93 | index XXXXXXX..XXXXXXX 100644 | ||
94 | --- a/include/hw/qdev-properties.h | ||
95 | +++ b/include/hw/qdev-properties.h | ||
96 | @@ -XXX,XX +XXX,XX @@ void error_set_from_qdev_prop_error(Error **errp, int ret, DeviceState *dev, | ||
97 | */ | ||
98 | void qdev_property_add_static(DeviceState *dev, Property *prop); | ||
99 | |||
100 | +/** | ||
101 | + * qdev_alias_all_properties: Create aliases on source for all target properties | ||
102 | + * @target: Device which has properties to be aliased | ||
103 | + * @source: Object to add alias properties to | ||
104 | + * | ||
105 | + * Add alias properties to the @source object for all qdev properties on | ||
106 | + * the @target DeviceState. | ||
107 | + * | ||
108 | + * This is useful when @target is an internal implementation object | ||
109 | + * owned by @source, and you want to expose all the properties of that | ||
110 | + * implementation object as properties on the @source object so that users | ||
111 | + * of @source can set them. | ||
112 | + */ | ||
113 | void qdev_alias_all_properties(DeviceState *target, Object *source); | ||
114 | |||
115 | /** | ||
116 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | ||
117 | index XXXXXXX..XXXXXXX 100644 | ||
118 | --- a/hw/core/qdev.c | ||
119 | +++ b/hw/core/qdev.c | ||
120 | @@ -XXX,XX +XXX,XX @@ void qdev_set_parent_bus(DeviceState *dev, BusState *bus) | ||
121 | } | ||
122 | } | 20 | } |
123 | 21 | ||
124 | -/* | 22 | +static bool vectpending_targets_secure(NVICState *s) |
125 | - * Create a device on the heap. | 23 | +{ |
126 | - * A type @name must exist. | 24 | + /* Return true if s->vectpending targets Secure state */ |
127 | - * This only initializes the device state structure and allows | 25 | + if (s->vectpending_is_s_banked) { |
128 | - * properties to be set. The device still needs to be realized. See | 26 | + return true; |
129 | - * qdev-core.h. | 27 | + } |
130 | - */ | 28 | + return !exc_is_banked(s->vectpending) && |
131 | DeviceState *qdev_new(const char *name) | 29 | + exc_targets_secure(s, s->vectpending); |
30 | +} | ||
31 | + | ||
32 | void armv7m_nvic_get_pending_irq_info(void *opaque, | ||
33 | int *pirq, bool *ptargets_secure) | ||
132 | { | 34 | { |
133 | if (!object_class_by_name(name)) { | 35 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque, |
134 | @@ -XXX,XX +XXX,XX @@ DeviceState *qdev_new(const char *name) | 36 | |
135 | return DEVICE(object_new(name)); | 37 | assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); |
136 | } | 38 | |
137 | 39 | - if (s->vectpending_is_s_banked) { | |
138 | -/* | 40 | - targets_secure = true; |
139 | - * Try to create a device on the heap. | 41 | - } else { |
140 | - * This is like qdev_new(), except it returns %NULL when type @name | 42 | - targets_secure = !exc_is_banked(pending) && |
141 | - * does not exist. | 43 | - exc_targets_secure(s, pending); |
142 | - */ | 44 | - } |
143 | DeviceState *qdev_try_new(const char *name) | 45 | + targets_secure = vectpending_targets_secure(s); |
144 | { | 46 | |
145 | if (!module_object_class_by_name(name)) { | 47 | trace_nvic_get_pending_irq_info(pending, targets_secure); |
146 | @@ -XXX,XX +XXX,XX @@ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev, | 48 | |
147 | qdev_unrealize(dev); | 49 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) |
148 | } | 50 | /* VECTACTIVE */ |
149 | 51 | val = cpu->env.v7m.exception; | |
150 | -/* | 52 | /* VECTPENDING */ |
151 | - * Realize @dev. | 53 | - val |= (s->vectpending & 0x1ff) << 12; |
152 | - * @dev must not be plugged into a bus. | 54 | + if (s->vectpending) { |
153 | - * If @bus, plug @dev into @bus. This takes a reference to @dev. | 55 | + /* |
154 | - * If @dev has no QOM parent, make one up, taking another reference. | 56 | + * From v8.1M VECTPENDING must read as 1 if accessed as |
155 | - * On success, return true. | 57 | + * NonSecure and the highest priority pending and enabled |
156 | - * On failure, store an error through @errp and return false. | 58 | + * exception targets Secure. |
157 | - */ | 59 | + */ |
158 | bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp) | 60 | + int vp = s->vectpending; |
159 | { | 61 | + if (!attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && |
160 | assert(!dev->realized && !dev->parent_bus); | 62 | + vectpending_targets_secure(s)) { |
161 | @@ -XXX,XX +XXX,XX @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp) | 63 | + vp = 1; |
162 | return object_property_set_bool(OBJECT(dev), "realized", true, errp); | 64 | + } |
163 | } | 65 | + val |= (vp & 0x1ff) << 12; |
164 | 66 | + } | |
165 | -/* | 67 | /* ISRPENDING - set if any external IRQ is pending */ |
166 | - * Realize @dev and drop a reference. | 68 | if (nvic_isrpending(s)) { |
167 | - * This is like qdev_realize(), except the caller must hold a | 69 | val |= (1 << 22); |
168 | - * (private) reference, which is dropped on return regardless of | ||
169 | - * success or failure. Intended use: | ||
170 | - * dev = qdev_new(); | ||
171 | - * [...] | ||
172 | - * qdev_realize_and_unref(dev, bus, errp); | ||
173 | - * Now @dev can go away without further ado. | ||
174 | - */ | ||
175 | bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp) | ||
176 | { | ||
177 | bool ret; | ||
178 | @@ -XXX,XX +XXX,XX @@ static void qdev_class_add_property(DeviceClass *klass, Property *prop) | ||
179 | prop->info->description); | ||
180 | } | ||
181 | |||
182 | -/* @qdev_alias_all_properties - Add alias properties to the source object for | ||
183 | - * all qdev properties on the target DeviceState. | ||
184 | - */ | ||
185 | void qdev_alias_all_properties(DeviceState *target, Object *source) | ||
186 | { | ||
187 | ObjectClass *class; | ||
188 | -- | 70 | -- |
189 | 2.20.1 | 71 | 2.20.1 |
190 | 72 | ||
191 | 73 | diff view generated by jsdifflib |
1 | Add skeletal documentation of the collie board. | 1 | From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com> |
---|---|---|---|
2 | 2 | ||
3 | Missed in commit f3478392 "docs: Move deprecation, build | ||
4 | and license info out of system/" | ||
5 | |||
6 | Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20210723065828.1336760-1-maozhongyi@cmss.chinamobile.com | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
6 | Message-id: 20200713175746.5936-3-peter.maydell@linaro.org | ||
7 | --- | 10 | --- |
8 | docs/system/arm/collie.rst | 16 ++++++++++++++++ | 11 | configure | 2 +- |
9 | docs/system/target-arm.rst | 1 + | 12 | target/i386/cpu.c | 2 +- |
10 | MAINTAINERS | 1 + | 13 | MAINTAINERS | 2 +- |
11 | 3 files changed, 18 insertions(+) | 14 | 3 files changed, 3 insertions(+), 3 deletions(-) |
12 | create mode 100644 docs/system/arm/collie.rst | ||
13 | 15 | ||
14 | diff --git a/docs/system/arm/collie.rst b/docs/system/arm/collie.rst | 16 | diff --git a/configure b/configure |
15 | new file mode 100644 | 17 | index XXXXXXX..XXXXXXX 100755 |
16 | index XXXXXXX..XXXXXXX | 18 | --- a/configure |
17 | --- /dev/null | 19 | +++ b/configure |
18 | +++ b/docs/system/arm/collie.rst | 20 | @@ -XXX,XX +XXX,XX @@ fi |
19 | @@ -XXX,XX +XXX,XX @@ | 21 | |
20 | +Sharp Zaurus SL-5500 (``collie``) | 22 | if test -n "${deprecated_features}"; then |
21 | +================================= | 23 | echo "Warning, deprecated features enabled." |
22 | + | 24 | - echo "Please see docs/system/deprecated.rst" |
23 | +This machine is a model of the Sharp Zaurus SL-5500, which was | 25 | + echo "Please see docs/about/deprecated.rst" |
24 | +a 1990s PDA based on the StrongARM SA1110. | 26 | echo " features: ${deprecated_features}" |
25 | + | 27 | fi |
26 | +Implemented devices: | 28 | |
27 | + | 29 | diff --git a/target/i386/cpu.c b/target/i386/cpu.c |
28 | + * NOR flash | ||
29 | + * Interrupt controller | ||
30 | + * Timer | ||
31 | + * RTC | ||
32 | + * GPIO | ||
33 | + * Peripheral Pin Controller (PPC) | ||
34 | + * UARTs | ||
35 | + * Synchronous Serial Ports (SSP) | ||
36 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
37 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/docs/system/target-arm.rst | 31 | --- a/target/i386/cpu.c |
39 | +++ b/docs/system/target-arm.rst | 32 | +++ b/target/i386/cpu.c |
40 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | 33 | @@ -XXX,XX +XXX,XX @@ static const X86CPUDefinition builtin_x86_defs[] = { |
41 | arm/orangepi | 34 | * none", but this is just for compatibility while libvirt isn't |
42 | arm/palm | 35 | * adapted to resolve CPU model versions before creating VMs. |
43 | arm/xscale | 36 | * See "Runnability guarantee of CPU models" at |
44 | + arm/collie | 37 | - * docs/system/deprecated.rst. |
45 | arm/sx1 | 38 | + * docs/about/deprecated.rst. |
46 | arm/stellaris | 39 | */ |
40 | X86CPUVersion default_cpu_version = 1; | ||
47 | 41 | ||
48 | diff --git a/MAINTAINERS b/MAINTAINERS | 42 | diff --git a/MAINTAINERS b/MAINTAINERS |
49 | index XXXXXXX..XXXXXXX 100644 | 43 | index XXXXXXX..XXXXXXX 100644 |
50 | --- a/MAINTAINERS | 44 | --- a/MAINTAINERS |
51 | +++ b/MAINTAINERS | 45 | +++ b/MAINTAINERS |
52 | @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org | 46 | @@ -XXX,XX +XXX,XX @@ F: contrib/gitdm/* |
53 | S: Odd Fixes | 47 | |
54 | F: hw/arm/collie.c | 48 | Incompatible changes |
55 | F: hw/arm/strongarm* | 49 | R: libvir-list@redhat.com |
56 | +F: docs/system/arm/collie.rst | 50 | -F: docs/system/deprecated.rst |
57 | 51 | +F: docs/about/deprecated.rst | |
58 | Stellaris | 52 | |
59 | M: Peter Maydell <peter.maydell@linaro.org> | 53 | Build System |
54 | ------------ | ||
60 | -- | 55 | -- |
61 | 2.20.1 | 56 | 2.20.1 |
62 | 57 | ||
63 | 58 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | When MTE is enabled, tag memory must exist for all RAM. | 3 | Currently, our only caller is sve_zcr_len_for_el, which has |
4 | already masked the length extracted from ZCR_ELx, so the | ||
5 | masking done here is a nop. But we will shortly have uses | ||
6 | from other locations, where the length will be unmasked. | ||
4 | 7 | ||
5 | It might be possible to simultaneously hot plug tag memory | 8 | Saturate the length to ARM_MAX_VQ instead of truncating to |
6 | alongside the corresponding normal memory, but for now just | 9 | the low 4 bits. |
7 | disable hotplug. | ||
8 | 10 | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20200713213341.590275-4-richard.henderson@linaro.org | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Message-id: 20210723203344.968563-2-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 15 | --- |
14 | hw/arm/virt.c | 5 +++++ | 16 | target/arm/helper.c | 4 +++- |
15 | 1 file changed, 5 insertions(+) | 17 | 1 file changed, 3 insertions(+), 1 deletion(-) |
16 | 18 | ||
17 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 19 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
18 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/arm/virt.c | 21 | --- a/target/arm/helper.c |
20 | +++ b/hw/arm/virt.c | 22 | +++ b/target/arm/helper.c |
21 | @@ -XXX,XX +XXX,XX @@ static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | 23 | @@ -XXX,XX +XXX,XX @@ static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) |
22 | return; | 24 | { |
23 | } | 25 | uint32_t end_len; |
24 | 26 | ||
25 | + if (vms->mte) { | 27 | - end_len = start_len &= 0xf; |
26 | + error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); | 28 | + start_len = MIN(start_len, ARM_MAX_VQ - 1); |
27 | + return; | 29 | + end_len = start_len; |
28 | + } | ||
29 | + | 30 | + |
30 | if (is_nvdimm && !ms->nvdimms_state->is_enabled) { | 31 | if (!test_bit(start_len, cpu->sve_vq_map)) { |
31 | error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); | 32 | end_len = find_last_bit(cpu->sve_vq_map, start_len); |
32 | return; | 33 | assert(end_len < start_len); |
33 | -- | 34 | -- |
34 | 2.20.1 | 35 | 2.20.1 |
35 | 36 | ||
36 | 37 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | While we expect KVM to support MTE at some future point, | 3 | Rename from sve_zcr_get_valid_len and make accessible |
4 | it certainly won't be ready in time for qemu 5.1. | 4 | from outside of helper.c. |
5 | 5 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20200713213341.590275-3-richard.henderson@linaro.org | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Message-id: 20210723203344.968563-3-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | hw/arm/virt.c | 6 ++++++ | 11 | target/arm/internals.h | 10 ++++++++++ |
12 | 1 file changed, 6 insertions(+) | 12 | target/arm/helper.c | 4 ++-- |
13 | 2 files changed, 12 insertions(+), 2 deletions(-) | ||
13 | 14 | ||
14 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 15 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/arm/virt.c | 17 | --- a/target/arm/internals.h |
17 | +++ b/hw/arm/virt.c | 18 | +++ b/target/arm/internals.h |
18 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | 19 | @@ -XXX,XX +XXX,XX @@ void arm_translate_init(void); |
19 | exit(1); | 20 | void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); |
21 | #endif /* CONFIG_TCG */ | ||
22 | |||
23 | +/** | ||
24 | + * aarch64_sve_zcr_get_valid_len: | ||
25 | + * @cpu: cpu context | ||
26 | + * @start_len: maximum len to consider | ||
27 | + * | ||
28 | + * Return the maximum supported sve vector length <= @start_len. | ||
29 | + * Note that both @start_len and the return value are in units | ||
30 | + * of ZCR_ELx.LEN, so the vector bit length is (x + 1) * 128. | ||
31 | + */ | ||
32 | +uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len); | ||
33 | |||
34 | enum arm_fprounding { | ||
35 | FPROUNDING_TIEEVEN, | ||
36 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/helper.c | ||
39 | +++ b/target/arm/helper.c | ||
40 | @@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el) | ||
41 | return 0; | ||
42 | } | ||
43 | |||
44 | -static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) | ||
45 | +uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) | ||
46 | { | ||
47 | uint32_t end_len; | ||
48 | |||
49 | @@ -XXX,XX +XXX,XX @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) | ||
50 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); | ||
20 | } | 51 | } |
21 | 52 | ||
22 | + if (vms->mte && kvm_enabled()) { | 53 | - return sve_zcr_get_valid_len(cpu, zcr_len); |
23 | + error_report("mach-virt: KVM does not support providing " | 54 | + return aarch64_sve_zcr_get_valid_len(cpu, zcr_len); |
24 | + "MTE to the guest CPU"); | 55 | } |
25 | + exit(1); | 56 | |
26 | + } | 57 | static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
27 | + | ||
28 | create_fdt(vms); | ||
29 | |||
30 | possible_cpus = mc->possible_cpu_arch_ids(machine); | ||
31 | -- | 58 | -- |
32 | 2.20.1 | 59 | 2.20.1 |
33 | 60 | ||
34 | 61 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Control this cpu feature via a machine property, much as we do | 3 | Mirror the behavour of /proc/sys/abi/sve_default_vector_length |
4 | with secure=on, since both require specialized support in the | 4 | under the real linux kernel. We have no way of passing along |
5 | machine setup to be functional. | 5 | a real default across exec like the kernel can, but this is a |
6 | decent way of adjusting the startup vector length of a process. | ||
6 | 7 | ||
7 | Default MTE to off, since this feature implies extra overhead. | 8 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/482 |
8 | |||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20200713213341.590275-2-richard.henderson@linaro.org | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Message-id: 20210723203344.968563-4-richard.henderson@linaro.org | ||
12 | [PMM: tweaked docs formatting, document -1 special-case, | ||
13 | added fixup patch from RTH mentioning QEMU's maximum veclen.] | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 15 | --- |
14 | include/hw/arm/virt.h | 1 + | 16 | docs/system/arm/cpu-features.rst | 15 ++++++++ |
15 | hw/arm/virt.c | 39 ++++++++++++++++++++++++++++++++++----- | 17 | target/arm/cpu.h | 5 +++ |
16 | target/arm/cpu.c | 19 +++++++++++-------- | 18 | target/arm/cpu.c | 14 ++++++-- |
17 | target/arm/cpu64.c | 5 +++-- | 19 | target/arm/cpu64.c | 60 ++++++++++++++++++++++++++++++++ |
18 | 4 files changed, 49 insertions(+), 15 deletions(-) | 20 | 4 files changed, 92 insertions(+), 2 deletions(-) |
19 | 21 | ||
20 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h | 22 | diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst |
21 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/include/hw/arm/virt.h | 24 | --- a/docs/system/arm/cpu-features.rst |
23 | +++ b/include/hw/arm/virt.h | 25 | +++ b/docs/system/arm/cpu-features.rst |
24 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 26 | @@ -XXX,XX +XXX,XX @@ verbose command lines. However, the recommended way to select vector |
25 | bool its; | 27 | lengths is to explicitly enable each desired length. Therefore only |
26 | bool virt; | 28 | example's (1), (4), and (6) exhibit recommended uses of the properties. |
27 | bool ras; | 29 | |
28 | + bool mte; | 30 | +SVE User-mode Default Vector Length Property |
29 | OnOffAuto acpi; | 31 | +-------------------------------------------- |
30 | VirtGICType gic_version; | 32 | + |
31 | VirtIOMMUType iommu; | 33 | +For qemu-aarch64, the cpu property ``sve-default-vector-length=N`` is |
32 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 34 | +defined to mirror the Linux kernel parameter file |
35 | +``/proc/sys/abi/sve_default_vector_length``. The default length, ``N``, | ||
36 | +is in units of bytes and must be between 16 and 8192. | ||
37 | +If not specified, the default vector length is 64. | ||
38 | + | ||
39 | +If the default length is larger than the maximum vector length enabled, | ||
40 | +the actual vector length will be reduced. Note that the maximum vector | ||
41 | +length supported by QEMU is 256. | ||
42 | + | ||
43 | +If this property is set to ``-1`` then the default vector length | ||
44 | +is set to the maximum possible length. | ||
45 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
33 | index XXXXXXX..XXXXXXX 100644 | 46 | index XXXXXXX..XXXXXXX 100644 |
34 | --- a/hw/arm/virt.c | 47 | --- a/target/arm/cpu.h |
35 | +++ b/hw/arm/virt.c | 48 | +++ b/target/arm/cpu.h |
36 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | 49 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { |
37 | OBJECT(secure_sysmem), &error_abort); | 50 | /* Used to set the maximum vector length the cpu will support. */ |
38 | } | 51 | uint32_t sve_max_vq; |
39 | 52 | ||
40 | - /* | 53 | +#ifdef CONFIG_USER_ONLY |
41 | - * The cpu adds the property if and only if MemTag is supported. | 54 | + /* Used to set the default vector length at process start. */ |
42 | - * If it is, we must allocate the ram to back that up. | 55 | + uint32_t sve_default_vq; |
43 | - */ | 56 | +#endif |
44 | - if (object_property_find(cpuobj, "tag-memory", NULL)) { | ||
45 | + if (vms->mte) { | ||
46 | + /* Create the memory region only once, but link to all cpus. */ | ||
47 | if (!tag_sysmem) { | ||
48 | + /* | ||
49 | + * The property exists only if MemTag is supported. | ||
50 | + * If it is, we must allocate the ram to back that up. | ||
51 | + */ | ||
52 | + if (!object_property_find(cpuobj, "tag-memory", NULL)) { | ||
53 | + error_report("MTE requested, but not supported " | ||
54 | + "by the guest CPU"); | ||
55 | + exit(1); | ||
56 | + } | ||
57 | + | 57 | + |
58 | tag_sysmem = g_new(MemoryRegion, 1); | 58 | /* |
59 | memory_region_init(tag_sysmem, OBJECT(machine), | 59 | * In sve_vq_map each set bit is a supported vector length of |
60 | "tag-memory", UINT64_MAX / 32); | 60 | * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector |
61 | @@ -XXX,XX +XXX,XX @@ static void virt_set_ras(Object *obj, bool value, Error **errp) | ||
62 | vms->ras = value; | ||
63 | } | ||
64 | |||
65 | +static bool virt_get_mte(Object *obj, Error **errp) | ||
66 | +{ | ||
67 | + VirtMachineState *vms = VIRT_MACHINE(obj); | ||
68 | + | ||
69 | + return vms->mte; | ||
70 | +} | ||
71 | + | ||
72 | +static void virt_set_mte(Object *obj, bool value, Error **errp) | ||
73 | +{ | ||
74 | + VirtMachineState *vms = VIRT_MACHINE(obj); | ||
75 | + | ||
76 | + vms->mte = value; | ||
77 | +} | ||
78 | + | ||
79 | static char *virt_get_gic_version(Object *obj, Error **errp) | ||
80 | { | ||
81 | VirtMachineState *vms = VIRT_MACHINE(obj); | ||
82 | @@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj) | ||
83 | "Set on/off to enable/disable reporting host memory errors " | ||
84 | "to a KVM guest using ACPI and guest external abort exceptions"); | ||
85 | |||
86 | + /* MTE is disabled by default. */ | ||
87 | + vms->mte = false; | ||
88 | + object_property_add_bool(obj, "mte", virt_get_mte, virt_set_mte); | ||
89 | + object_property_set_description(obj, "mte", | ||
90 | + "Set on/off to enable/disable emulating a " | ||
91 | + "guest CPU which implements the ARM " | ||
92 | + "Memory Tagging Extension"); | ||
93 | + | ||
94 | vms->irqmap = a15irqmap; | ||
95 | |||
96 | virt_flash_create(vms); | ||
97 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 61 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
98 | index XXXXXXX..XXXXXXX 100644 | 62 | index XXXXXXX..XXXXXXX 100644 |
99 | --- a/target/arm/cpu.c | 63 | --- a/target/arm/cpu.c |
100 | +++ b/target/arm/cpu.c | 64 | +++ b/target/arm/cpu.c |
101 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 65 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) |
102 | cpu->id_pfr1 &= ~0xf000; | 66 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); |
103 | } | 67 | /* with reasonable vector length */ |
104 | 68 | if (cpu_isar_feature(aa64_sve, cpu)) { | |
105 | +#ifndef CONFIG_USER_ONLY | 69 | - env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3); |
106 | + if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { | 70 | + env->vfp.zcr_el[1] = |
107 | + /* | 71 | + aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); |
108 | + * Disable the MTE feature bits if we do not have tag-memory | ||
109 | + * provided by the machine. | ||
110 | + */ | ||
111 | + cpu->isar.id_aa64pfr1 = | ||
112 | + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); | ||
113 | + } | ||
114 | +#endif | ||
115 | + | ||
116 | /* MPU can be configured out of a PMSA CPU either by setting has-mpu | ||
117 | * to false or by setting pmsav7-dregion to 0. | ||
118 | */ | ||
119 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
120 | cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", | ||
121 | cpu->secure_tag_memory); | ||
122 | } | 72 | } |
123 | - } else if (cpu_isar_feature(aa64_mte, cpu)) { | 73 | /* |
124 | - /* | 74 | * Enable TBI0 but not TBI1. |
125 | - * Since there is no tag memory, we can't meaningfully support MTE | 75 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj) |
126 | - * to its fullest. To avoid problems later, when we would come to | 76 | QLIST_INIT(&cpu->pre_el_change_hooks); |
127 | - * use the tag memory, downgrade support to insns only. | 77 | QLIST_INIT(&cpu->el_change_hooks); |
128 | - */ | 78 | |
129 | - cpu->isar.id_aa64pfr1 = | 79 | -#ifndef CONFIG_USER_ONLY |
130 | - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); | 80 | +#ifdef CONFIG_USER_ONLY |
131 | } | 81 | +# ifdef TARGET_AARCH64 |
132 | 82 | + /* | |
133 | cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); | 83 | + * The linux kernel defaults to 512-bit vectors, when sve is supported. |
84 | + * See documentation for /proc/sys/abi/sve_default_vector_length, and | ||
85 | + * our corresponding sve-default-vector-length cpu property. | ||
86 | + */ | ||
87 | + cpu->sve_default_vq = 4; | ||
88 | +# endif | ||
89 | +#else | ||
90 | /* Our inbound IRQ and FIQ lines */ | ||
91 | if (kvm_enabled()) { | ||
92 | /* VIRQ and VFIQ are unused with KVM but we add them to maintain | ||
134 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 93 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
135 | index XXXXXXX..XXXXXXX 100644 | 94 | index XXXXXXX..XXXXXXX 100644 |
136 | --- a/target/arm/cpu64.c | 95 | --- a/target/arm/cpu64.c |
137 | +++ b/target/arm/cpu64.c | 96 | +++ b/target/arm/cpu64.c |
138 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 97 | @@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) |
139 | t = cpu->isar.id_aa64pfr1; | 98 | cpu->isar.id_aa64pfr0 = t; |
140 | t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); | 99 | } |
141 | /* | 100 | |
142 | - * Begin with full support for MTE; will be downgraded to MTE=1 | 101 | +#ifdef CONFIG_USER_ONLY |
143 | - * during realize if the board provides no tag memory. | 102 | +/* Mirror linux /proc/sys/abi/sve_default_vector_length. */ |
144 | + * Begin with full support for MTE. This will be downgraded to MTE=0 | 103 | +static void cpu_arm_set_sve_default_vec_len(Object *obj, Visitor *v, |
145 | + * during realize if the board provides no tag memory, much like | 104 | + const char *name, void *opaque, |
146 | + * we do for EL2 with the virtualization=on property. | 105 | + Error **errp) |
147 | */ | 106 | +{ |
148 | t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); | 107 | + ARMCPU *cpu = ARM_CPU(obj); |
149 | cpu->isar.id_aa64pfr1 = t; | 108 | + int32_t default_len, default_vq, remainder; |
109 | + | ||
110 | + if (!visit_type_int32(v, name, &default_len, errp)) { | ||
111 | + return; | ||
112 | + } | ||
113 | + | ||
114 | + /* Undocumented, but the kernel allows -1 to indicate "maximum". */ | ||
115 | + if (default_len == -1) { | ||
116 | + cpu->sve_default_vq = ARM_MAX_VQ; | ||
117 | + return; | ||
118 | + } | ||
119 | + | ||
120 | + default_vq = default_len / 16; | ||
121 | + remainder = default_len % 16; | ||
122 | + | ||
123 | + /* | ||
124 | + * Note that the 512 max comes from include/uapi/asm/sve_context.h | ||
125 | + * and is the maximum architectural width of ZCR_ELx.LEN. | ||
126 | + */ | ||
127 | + if (remainder || default_vq < 1 || default_vq > 512) { | ||
128 | + error_setg(errp, "cannot set sve-default-vector-length"); | ||
129 | + if (remainder) { | ||
130 | + error_append_hint(errp, "Vector length not a multiple of 16\n"); | ||
131 | + } else if (default_vq < 1) { | ||
132 | + error_append_hint(errp, "Vector length smaller than 16\n"); | ||
133 | + } else { | ||
134 | + error_append_hint(errp, "Vector length larger than %d\n", | ||
135 | + 512 * 16); | ||
136 | + } | ||
137 | + return; | ||
138 | + } | ||
139 | + | ||
140 | + cpu->sve_default_vq = default_vq; | ||
141 | +} | ||
142 | + | ||
143 | +static void cpu_arm_get_sve_default_vec_len(Object *obj, Visitor *v, | ||
144 | + const char *name, void *opaque, | ||
145 | + Error **errp) | ||
146 | +{ | ||
147 | + ARMCPU *cpu = ARM_CPU(obj); | ||
148 | + int32_t value = cpu->sve_default_vq * 16; | ||
149 | + | ||
150 | + visit_type_int32(v, name, &value, errp); | ||
151 | +} | ||
152 | +#endif | ||
153 | + | ||
154 | void aarch64_add_sve_properties(Object *obj) | ||
155 | { | ||
156 | uint32_t vq; | ||
157 | @@ -XXX,XX +XXX,XX @@ void aarch64_add_sve_properties(Object *obj) | ||
158 | object_property_add(obj, name, "bool", cpu_arm_get_sve_vq, | ||
159 | cpu_arm_set_sve_vq, NULL, NULL); | ||
160 | } | ||
161 | + | ||
162 | +#ifdef CONFIG_USER_ONLY | ||
163 | + /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ | ||
164 | + object_property_add(obj, "sve-default-vector-length", "int32", | ||
165 | + cpu_arm_get_sve_default_vec_len, | ||
166 | + cpu_arm_set_sve_default_vec_len, NULL, NULL); | ||
167 | +#endif | ||
168 | } | ||
169 | |||
170 | void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) | ||
150 | -- | 171 | -- |
151 | 2.20.1 | 172 | 2.20.1 |
152 | 173 | ||
153 | 174 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
1 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20210726150953.1218690-1-f4bug@amsat.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | hw/arm/nseries.c | 2 +- | ||
9 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
10 | |||
11 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/hw/arm/nseries.c | ||
14 | +++ b/hw/arm/nseries.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len) | ||
16 | default: | ||
17 | bad_cmd: | ||
18 | qemu_log_mask(LOG_GUEST_ERROR, | ||
19 | - "%s: unknown command %02x\n", __func__, s->cmd); | ||
20 | + "%s: unknown command 0x%02x\n", __func__, s->cmd); | ||
21 | break; | ||
22 | } | ||
23 | |||
24 | -- | ||
25 | 2.20.1 | ||
26 | |||
27 | diff view generated by jsdifflib |
1 | From: David CARLIER <devnexen@gmail.com> | 1 | From: Joel Stanley <joel@jms.id.au> |
---|---|---|---|
2 | 2 | ||
3 | Implement qemu_get_thread_id() for OpenBSD hosts, using | 3 | The macro used to calculate the maximum memory size of the MMIO region |
4 | getthrid(). | 4 | had a mistake, causing all GPIO models to create a mapping of 0x9D8. |
5 | The intent was to have it be 0x9D8 - 0x800. | ||
5 | 6 | ||
6 | Signed-off-by: David Carlier <devnexen@gmail.com> | 7 | This extra size doesn't matter on ast2400 and ast2500, which have a 4KB |
7 | Reviewed-by: Brad Smith <brad@comstyle.com> | 8 | region set aside for the GPIO controller. |
8 | Message-id: CA+XhMqxD6gQDBaj8tX0CMEj3si7qYKsM8u1km47e_-U7MC37Pg@mail.gmail.com | 9 | |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | On the ast2600 the 3.3V and 1.8V GPIO controllers are 2KB apart, so the |
10 | [PMM: tidied up commit message] | 11 | regions would overlap. Worse was the 1.8V controller would map over the |
12 | top of the following peripheral, which happens to be the RTC. | ||
13 | |||
14 | The mmio region used by each device is a maximum of 2KB, so avoid the | ||
15 | calculations and hard code this as the maximum. | ||
16 | |||
17 | Fixes: 36d737ee82b2 ("hw/gpio: Add in AST2600 specific implementation") | ||
18 | Signed-off-by: Joel Stanley <joel@jms.id.au> | ||
19 | Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com> | ||
20 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
21 | Message-id: 20210713065854.134634-2-joel@jms.id.au | ||
22 | [PMM: fix autocorrect error in commit message] | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 24 | --- |
13 | util/oslib-posix.c | 2 ++ | 25 | hw/gpio/aspeed_gpio.c | 3 +-- |
14 | 1 file changed, 2 insertions(+) | 26 | 1 file changed, 1 insertion(+), 2 deletions(-) |
15 | 27 | ||
16 | diff --git a/util/oslib-posix.c b/util/oslib-posix.c | 28 | diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c |
17 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/util/oslib-posix.c | 30 | --- a/hw/gpio/aspeed_gpio.c |
19 | +++ b/util/oslib-posix.c | 31 | +++ b/hw/gpio/aspeed_gpio.c |
20 | @@ -XXX,XX +XXX,XX @@ int qemu_get_thread_id(void) | 32 | @@ -XXX,XX +XXX,XX @@ |
21 | return (int)tid; | 33 | #define GPIO_1_8V_MEM_SIZE 0x9D8 |
22 | #elif defined(__NetBSD__) | 34 | #define GPIO_1_8V_REG_ARRAY_SIZE ((GPIO_1_8V_MEM_SIZE - \ |
23 | return _lwp_self(); | 35 | GPIO_1_8V_REG_OFFSET) >> 2) |
24 | +#elif defined(__OpenBSD__) | 36 | -#define GPIO_MAX_MEM_SIZE MAX(GPIO_3_6V_MEM_SIZE, GPIO_1_8V_MEM_SIZE) |
25 | + return getthrid(); | 37 | |
26 | #else | 38 | static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio) |
27 | return getpid(); | 39 | { |
28 | #endif | 40 | @@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_realize(DeviceState *dev, Error **errp) |
41 | } | ||
42 | |||
43 | memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s, | ||
44 | - TYPE_ASPEED_GPIO, GPIO_MAX_MEM_SIZE); | ||
45 | + TYPE_ASPEED_GPIO, 0x800); | ||
46 | |||
47 | sysbus_init_mmio(sbd, &s->iomem); | ||
48 | } | ||
29 | -- | 49 | -- |
30 | 2.20.1 | 50 | 2.20.1 |
31 | 51 | ||
32 | 52 | diff view generated by jsdifflib |