Nothing too exciting, but does include the last bits of v8.1M support work.

The following changes since commit e79de63ab1bd1f6550e7b915e433bec1ad1a870a:

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210107' into staging (2021-01-07 20:34:05 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210108

for you to fetch changes up to c9f8511ea8d2b80723af0fea1f716d752c1b5208:

docs/system: arm: Add sabrelite board description (2021-01-08 15:13:39 +0000)

* intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs

* target/arm: Fix MTE0_ACTIVE

* target/arm: Implement v8.1M and Cortex-M55 model

* hw/arm/highbank: Drop dead KVM support code

* util/qemu-timer: Make timer_free() imply timer_del()

* various devices: Use ptimer_free() in finalize function

* docs/system: arm: Add sabrelite board description

* sabrelite: Minor fixes to allow booting U-Boot

Andrew Jones (1):

hw/arm/virt: Remove virt machine state 'smp_cpus'

Bin Meng (4):

hw/misc: imx6_ccm: Update PMU_MISC0 reset value

hw/msic: imx6_ccm: Correct register value for silicon type

hw/arm: sabrelite: Connect the Ethernet PHY at address 6

docs/system: arm: Add sabrelite board description

Edgar E. Iglesias (1):

intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs

Gan Qixin (7):

digic-timer: Use ptimer_free() in the finalize function to avoid memleaks

allwinner-a10-pit: Use ptimer_free() in the finalize function to avoid memleaks

exynos4210_rtc: Use ptimer_free() in the finalize function to avoid memleaks

exynos4210_pwm: Use ptimer_free() in the finalize function to avoid memleaks

mss-timer: Use ptimer_free() in the finalize function to avoid memleaks

musicpal: Use ptimer_free() in the finalize function to avoid memleaks

exynos4210_mct: Use ptimer_free() in the finalize function to avoid memleaks

From: Andrew Jones <drjones@redhat.com>

virt machine's 'smp_cpus' and machine->smp.cpus must always have the

same value. And, anywhere we have virt machine state we have machine

state. So let's remove the redundancy. Also, to make it easier to see

that machine->smp is the true source for "smp_cpus" and "max_cpus",

avoid passing them in function parameters, preferring instead to get

them from the state.

No functional change intended.

Signed-off-by: Andrew Jones <drjones@redhat.com>

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

Reviewed-by: Ying Fang <fangying1@huawei.com>

Message-id: 20201215174815.51520-1-drjones@redhat.com

[PMM: minor formatting tweak to smp_cpus variable declaration]

include/hw/arm/virt.h | 3 +--

hw/arm/virt-acpi-build.c | 9 +++++----

hw/arm/virt.c | 21 ++++++++++-----------

3 files changed, 16 insertions(+), 17 deletions(-)

- vms->smp_cpus = smp_cpus;

-

if (vms->virt && kvm_enabled()) {

error_report("mach-virt: KVM does not support providing "

"Virtualization extensions to the guest CPU");

@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)

In 50244cc76abc we updated mte_check_fail to match the ARM

pseudocode, using the correct EL to select the TCF field.

But we failed to update MTE0_ACTIVE the same way, which led

to g_assert_not_reached().

Cc: qemu-stable@nongnu.org

Buglink: https://bugs.launchpad.net/bugs/1907137

Message-id: 20201221204426.88514-1-richard.henderson@linaro.org

target/arm/helper.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,

if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV)

&& tbid

&& !(env->pstate & PSTATE_TCO)

- && (sctlr & SCTLR_TCF0)

+ && (sctlr & SCTLR_TCF)

&& allocation_tag_access_enabled(env, 0, sctlr)) {

flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1);

}

Implement the v8.1M FPCXT_NS floating-point system register. This is

a little more complicated than FPCXT_S, because it has specific

handling for "current FP state is inactive", and it only wants to do

PreserveFPState(), not the full set of actions done by

ExecuteFPCheck() which vfp_access_check() implements.

Message-id: 20201210201433.26262-4-peter.maydell@linaro.org

target/arm/translate-vfp.c.inc | 102 ++++++++++++++++++++++++++++++++-

1 file changed, 99 insertions(+), 3 deletions(-)

diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc

--- a/target/arm/translate-vfp.c.inc

+++ b/target/arm/translate-vfp.c.inc

@@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)

}

break;

case ARM_VFP_FPCXT_S:

+ case ARM_VFP_FPCXT_NS:

if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)

return FPSysRegCheckFailed;

+static void gen_branch_fpInactive(DisasContext *s, TCGCond cond,

+ TCGLabel *label)

+{

+ /*

+ * FPCXT_NS is a special case: it has specific handling for

+ * "current FP state is inactive", and must do the PreserveFPState()

+ * but not the usual full set of actions done by ExecuteFPCheck().

+ * We don't have a TB flag that matches the fpInactive check, so we

+ * do it at runtime as we don't expect FPCXT_NS accesses to be frequent.

+ *

+ * Emit code that checks fpInactive and does a conditional

+ * branch to label based on it:

+ * if cond is TCG_COND_NE then branch if fpInactive != 0 (ie if inactive)

+ * if cond is TCG_COND_EQ then branch if fpInactive == 0 (ie if active)

+ */

+ assert(cond == TCG_COND_EQ || cond == TCG_COND_NE);

+

+ /* fpInactive = FPCCR_NS.ASPEN == 1 && CONTROL.FPCA == 0 */

+ TCGv_i32 aspen, fpca;

+ aspen = load_cpu_field(v7m.fpccr[M_REG_NS]);

+ fpca = load_cpu_field(v7m.control[M_REG_S]);

+ tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);

+ tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);

+ tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK);

+ tcg_gen_or_i32(fpca, fpca, aspen);

+ tcg_gen_brcondi_i32(tcg_invert_cond(cond), fpca, 0, label);

+ tcg_temp_free_i32(aspen);

+ tcg_temp_free_i32(fpca);

+}

+

static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,

fp_sysreg_loadfn *loadfn,

@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,

/* Do a write to an M-profile floating point system register */

TCGv_i32 tmp;

+ TCGLabel *lab_end = NULL;

switch (fp_sysreg_checks(s, regno)) {

case FPSysRegCheckFailed:

@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,

tcg_temp_free_i32(tmp);

break;

}

+ case ARM_VFP_FPCXT_NS:

+ lab_end = gen_new_label();

+ /* fpInactive case: write is a NOP, so branch to end */

+ gen_branch_fpInactive(s, TCG_COND_NE, lab_end);

+ /* !fpInactive: PreserveFPState(), and reads same as FPCXT_S */

+ gen_preserve_fp_state(s);

+ /* fall through */

case ARM_VFP_FPCXT_S:

{

TCGv_i32 sfpa, control;

@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,

default:

g_assert_not_reached();

}

+ if (lab_end) {

+ gen_set_label(lab_end);

+ }

return true;

@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,

/* Do a read from an M-profile floating point system register */

TCGv_i32 tmp;

+ TCGLabel *lab_end = NULL;

+ bool lookup_tb = false;

switch (fp_sysreg_checks(s, regno)) {

case FPSysRegCheckFailed:

@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,

fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);

gen_helper_vfp_set_fpscr(cpu_env, fpscr);

tcg_temp_free_i32(fpscr);

- gen_lookup_tb(s);

+ lookup_tb = true;

+ break;

+ }

+ case ARM_VFP_FPCXT_NS:

+ {

+ TCGv_i32 control, sfpa, fpscr, fpdscr, zero;

+ TCGLabel *lab_active = gen_new_label();

+

+ lookup_tb = true;

+

+ gen_branch_fpInactive(s, TCG_COND_EQ, lab_active);

+ /* fpInactive case: reads as FPDSCR_NS */

+ TCGv_i32 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]);

+ storefn(s, opaque, tmp);

+ lab_end = gen_new_label();

+ tcg_gen_br(lab_end);

+

+ gen_set_label(lab_active);

+ /* !fpInactive: Reads the same as FPCXT_S, but side effects differ */

+ gen_preserve_fp_state(s);

+ tmp = tcg_temp_new_i32();

+ sfpa = tcg_temp_new_i32();

+ fpscr = tcg_temp_new_i32();

+ gen_helper_vfp_get_fpscr(fpscr, cpu_env);

+ tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK);

+ control = load_cpu_field(v7m.control[M_REG_S]);

+ tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);

+ tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);

+ tcg_gen_or_i32(tmp, tmp, sfpa);

+ tcg_temp_free_i32(control);

+ /* Store result before updating FPSCR, in case it faults */

+ storefn(s, opaque, tmp);

+ /* If SFPA is zero then set FPSCR from FPDSCR_NS */

+ fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);

+ zero = tcg_const_i32(0);

+ tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, zero, fpdscr, fpscr);

+ gen_helper_vfp_set_fpscr(cpu_env, fpscr);

+ tcg_temp_free_i32(zero);

+ tcg_temp_free_i32(sfpa);

+ tcg_temp_free_i32(fpdscr);

+ tcg_temp_free_i32(fpscr);

break;

}

default:

g_assert_not_reached();

}

+

+ if (lab_end) {

+ gen_set_label(lab_end);

+ }

+ if (lookup_tb) {

+ gen_lookup_tb(s);

+ }

return true;

Now that we have implemented all the features needed by the v8.1M

architecture, we can add the model of the Cortex-M55. This is the

configuration without MVE support; we'll add MVE later.

Message-id: 20201210201433.26262-5-peter.maydell@linaro.org

target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++

1 file changed, 42 insertions(+)

diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c

--- a/target/arm/cpu_tcg.c

+++ b/target/arm/cpu_tcg.c

@@ -XXX,XX +XXX,XX @@ static void cortex_m33_initfn(Object *obj)

cpu->ctr = 0x8000c000;

+static void cortex_m55_initfn(Object *obj)

+{

+ ARMCPU *cpu = ARM_CPU(obj);

+

+ set_feature(&cpu->env, ARM_FEATURE_V8);

+ set_feature(&cpu->env, ARM_FEATURE_V8_1M);

+ set_feature(&cpu->env, ARM_FEATURE_M);

+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);

+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);

+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);

+ cpu->midr = 0x410fd221; /* r0p1 */

+ cpu->revidr = 0;

+ cpu->pmsav7_dregion = 16;

+ cpu->sau_sregion = 8;

+ /*

+ * These are the MVFR* values for the FPU, no MVE configuration;

+ * we will update them later when we implement MVE

+ */

+ cpu->isar.mvfr0 = 0x10110221;

+ cpu->isar.mvfr1 = 0x12100011;

+ cpu->isar.mvfr2 = 0x00000040;

+ cpu->isar.id_pfr0 = 0x20000030;

+ cpu->isar.id_pfr1 = 0x00000230;

+ cpu->isar.id_dfr0 = 0x10200000;

+ cpu->id_afr0 = 0x00000000;

+ cpu->isar.id_mmfr0 = 0x00111040;

+ cpu->isar.id_mmfr1 = 0x00000000;

+ cpu->isar.id_mmfr2 = 0x01000000;

+ cpu->isar.id_mmfr3 = 0x00000011;

+ cpu->isar.id_isar0 = 0x01103110;

+ cpu->isar.id_isar1 = 0x02212000;

+ cpu->isar.id_isar2 = 0x20232232;

+ cpu->isar.id_isar3 = 0x01111131;

+ cpu->isar.id_isar4 = 0x01310132;

+ cpu->isar.id_isar5 = 0x00000000;

+ cpu->isar.id_isar6 = 0x00000000;

+ cpu->clidr = 0x00000000; /* caches not implemented */

+ cpu->ctr = 0x8303c003;

+}

+

static const ARMCPRegInfo cortexr5_cp_reginfo[] = {

/* Dummy the TCM region regs for the moment */

{ .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,

@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = {

.class_init = arm_v7m_class_init },

{ .name = "cortex-m33", .initfn = cortex_m33_initfn,

.class_init = arm_v7m_class_init },

+ { .name = "cortex-m55", .initfn = cortex_m55_initfn,

+ .class_init = arm_v7m_class_init },

{ .name = "cortex-r5", .initfn = cortex_r5_initfn },

{ .name = "cortex-r5f", .initfn = cortex_r5f_initfn },

{ .name = "ti925t", .initfn = ti925t_initfn },

Support for running KVM on 32-bit Arm hosts was removed in commit

82bf7ae84ce739e. You can still run a 32-bit guest on a 64-bit Arm

host CPU, but because Arm KVM requires the host and guest CPU types

to match, it is not possible to run a guest that requires a Cortex-A9

or Cortex-A15 CPU there. That means that the code in the

highbank/midway board models to support KVM is no longer used, and we

can delete it.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20201215144215.28482-1-peter.maydell@linaro.org

hw/arm/highbank.c | 14 ++++----------

1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c

--- a/hw/arm/highbank.c

+++ b/hw/arm/highbank.c

@@ -XXX,XX +XXX,XX @@

#include "hw/arm/boot.h"

#include "hw/loader.h"

#include "net/net.h"

-#include "sysemu/kvm.h"

#include "sysemu/runstate.h"

#include "sysemu/sysemu.h"

#include "hw/boards.h"

@@ -XXX,XX +XXX,XX @@

#include "hw/cpu/a15mpcore.h"

#include "qemu/log.h"

#include "qom/object.h"

+#include "cpu.h"

#define SMP_BOOT_ADDR 0x100

#define SMP_BOOT_REG 0x40

@@ -XXX,XX +XXX,XX @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)

highbank_binfo.loader_start = 0;

highbank_binfo.write_secondary_boot = hb_write_secondary;

highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;

- if (!kvm_enabled()) {

- highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;

- highbank_binfo.write_board_setup = hb_write_board_setup;

- highbank_binfo.secure_board_setup = true;

- } else {

- warn_report("cannot load built-in Monitor support "

- "if KVM is enabled. Some guests (such as Linux) "

- "may not boot.");

- }

+ highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;

+ highbank_binfo.write_board_setup = hb_write_board_setup;

+ highbank_binfo.secure_board_setup = true;

arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo);

}

Currently timer_free() is a simple wrapper for g_free(). This means

that the timer being freed must not be currently active, as otherwise

QEMU might crash later when the active list is processed and still

has a pointer to freed memory on it. As a result almost all calls to

timer_free() are preceded by a timer_del() call, as can be seen in

the output of

git grep -B1 '\<timer_free\>'

This is unfortunate API design as it makes it easy to accidentally

misuse (by forgetting the timer_del()), and the correct use is

annoyingly verbose.

Make timer_free() imply a timer_del().

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20201215154107.3255-2-peter.maydell@linaro.org

include/qemu/timer.h | 24 +++++++++++++-----------

1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/include/qemu/timer.h b/include/qemu/timer.h

index XXXXXXX..XXXXXXX 100644

--- a/include/qemu/timer.h

+++ b/include/qemu/timer.h

@@ -XXX,XX +XXX,XX @@ static inline QEMUTimer *timer_new_ms(QEMUClockType type, QEMUTimerCB *cb,

*/

void timer_deinit(QEMUTimer *ts);

-/**

- * timer_free:

- * @ts: the timer

- *

- * Free a timer (it must not be on the active list)

- */

-static inline void timer_free(QEMUTimer *ts)

-{

- g_free(ts);

-}

-

/**

* timer_del:

* @ts: the timer

@@ -XXX,XX +XXX,XX @@ static inline void timer_free(QEMUTimer *ts)

*/

void timer_del(QEMUTimer *ts);

+/**

+ * timer_free:

+ * @ts: the timer

+ *

+ * Free a timer. This will call timer_del() for you to remove

+ * the timer from the active list if it was still active.

+ */

+static inline void timer_free(QEMUTimer *ts)

+{

+ timer_del(ts);

+ g_free(ts);

+}

/**

* timer_mod_ns:

* @ts: the timer