1
Not much here, mostly documentation, but a few bug fixes.
1
Arm queue; bugfixes only.
2
2
3
thanks
3
thanks
4
-- PMM
4
-- PMM
5
5
6
The following changes since commit 873ec69aeb12e24eec7fb317fd0cd8494e8489dd:
6
The following changes since commit 48aa8f0ac536db3550a35c295ff7de94e4c33739:
7
7
8
Merge remote-tracking branch 'remotes/cminyard/tags/for-qemu-i2c-5' into staging (2020-07-20 11:03:09 +0100)
8
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2020-11-16' into staging (2020-11-17 11:07:00 +0000)
9
9
10
are available in the Git repository at:
10
are available in the Git repository at:
11
11
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200720
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201117
13
13
14
for you to fetch changes up to 6a0b7505f1fd6769c3f1558fda76464d51e4118a:
14
for you to fetch changes up to ab135622cf478585bdfcb68b85e4a817d74a0c42:
15
15
16
docs/system: Document the arm virt board (2020-07-20 11:35:17 +0100)
16
tmp105: Correct handling of temperature limit checks (2020-11-17 12:56:33 +0000)
17
17
18
----------------------------------------------------------------
18
----------------------------------------------------------------
19
target-arm queue:
19
target-arm queue:
20
* virt: Don't enable MTE emulation by default
20
* hw/arm/virt: ARM_VIRT must select ARM_GIC
21
* virt: Diagnose attempts to use MTE with memory-hotplug or KVM
21
* exynos: Fix bad printf format specifiers
22
(rather than silently not working correctly)
22
* hw/input/ps2.c: Remove remnants of printf debug
23
* util: Implement qemu_get_thread_id() for OpenBSD
23
* target/openrisc: Remove dead code attempting to check "is timer disabled"
24
* qdev: Add doc comments for qdev_unrealize and GPIO functions,
24
* register: Remove unnecessary NULL check
25
and standardize on doc-comments-in-header-file
25
* util/cutils: Fix Coverity array overrun in freq_to_str()
26
* hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize()
26
* configure: Make "does libgio work" test pull in some actual functions
27
* docs/system: Document canon-a1100, collie, gumstix, virt boards
27
* tmp105: reset the T_low and T_High registers
28
* tmp105: Correct handling of temperature limit checks
28
29
29
----------------------------------------------------------------
30
----------------------------------------------------------------
30
David CARLIER (1):
31
Alex Chen (1):
31
util: Implement qemu_get_thread_id() for OpenBSD
32
exynos: Fix bad printf format specifiers
32
33
33
Peter Maydell (8):
34
Alistair Francis (1):
34
qdev: Move doc comments from qdev.c to qdev-core.h
35
register: Remove unnecessary NULL check
35
qdev: Document qdev_unrealize()
36
qdev: Document GPIO related functions
37
hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize()
38
docs/system: Briefly document canon-a1100 board
39
docs/system: Briefly document collie board
40
docs/system: Briefly document gumstix boards
41
docs/system: Document the arm virt board
42
36
43
Richard Henderson (3):
37
Andrew Jones (1):
44
hw/arm/virt: Enable MTE via a machine property
38
hw/arm/virt: ARM_VIRT must select ARM_GIC
45
hw/arm/virt: Error for MTE enabled with KVM
46
hw/arm/virt: Disable memory hotplug when MTE is enabled
47
39
48
docs/system/arm/collie.rst | 16 +++
40
Peter Maydell (5):
49
docs/system/arm/digic.rst | 11 ++
41
hw/input/ps2.c: Remove remnants of printf debug
50
docs/system/arm/gumstix.rst | 21 ++++
42
target/openrisc: Remove dead code attempting to check "is timer disabled"
51
docs/system/arm/virt.rst | 161 ++++++++++++++++++++++++++
43
configure: Make "does libgio work" test pull in some actual functions
52
docs/system/target-arm.rst | 4 +
44
hw/misc/tmp105: reset the T_low and T_High registers
53
include/hw/arm/virt.h | 1 +
45
tmp105: Correct handling of temperature limit checks
54
include/hw/qdev-core.h | 267 ++++++++++++++++++++++++++++++++++++++++++-
55
include/hw/qdev-properties.h | 13 +++
56
hw/arm/armsse.c | 2 +
57
hw/arm/virt.c | 50 +++++++-
58
hw/core/qdev.c | 33 ------
59
target/arm/cpu.c | 19 +--
60
target/arm/cpu64.c | 5 +-
61
util/oslib-posix.c | 2 +
62
MAINTAINERS | 4 +
63
15 files changed, 559 insertions(+), 50 deletions(-)
64
create mode 100644 docs/system/arm/collie.rst
65
create mode 100644 docs/system/arm/digic.rst
66
create mode 100644 docs/system/arm/gumstix.rst
67
create mode 100644 docs/system/arm/virt.rst
68
46
47
Philippe Mathieu-Daudé (1):
48
util/cutils: Fix Coverity array overrun in freq_to_str()
49
50
configure | 11 +++++--
51
hw/misc/tmp105.h | 7 +++++
52
hw/core/register.c | 4 ---
53
hw/input/ps2.c | 9 ------
54
hw/misc/tmp105.c | 73 ++++++++++++++++++++++++++++++++++++++------
55
hw/timer/exynos4210_mct.c | 4 +--
56
hw/timer/exynos4210_pwm.c | 8 ++---
57
target/openrisc/sys_helper.c | 3 --
58
util/cutils.c | 3 +-
59
hw/arm/Kconfig | 1 +
60
10 files changed, 89 insertions(+), 34 deletions(-)
61
diff view generated by jsdifflib
1
Document the arm 'virt' board, which has been undocumented
1
From: Andrew Jones <drjones@redhat.com>
2
for far too long given that it is the main recommended board
3
type for arm guests.
4
2
3
The removal of the selection of A15MPCORE from ARM_VIRT also
4
removed what A15MPCORE selects, ARM_GIC. We still need ARM_GIC.
5
6
Fixes: bec3c97e0cf9 ("hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals")
7
Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
8
Signed-off-by: Andrew Jones <drjones@redhat.com>
9
Reviewed-by: Miroslav Rezanina <mrezanin@redhat.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20201111143440.112763-1-drjones@redhat.com
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20200713175746.5936-5-peter.maydell@linaro.org
8
---
13
---
9
docs/system/arm/virt.rst | 161 +++++++++++++++++++++++++++++++++++++
14
hw/arm/Kconfig | 1 +
10
docs/system/target-arm.rst | 1 +
15
1 file changed, 1 insertion(+)
11
MAINTAINERS | 1 +
12
3 files changed, 163 insertions(+)
13
create mode 100644 docs/system/arm/virt.rst
14
16
15
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
17
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
16
new file mode 100644
17
index XXXXXXX..XXXXXXX
18
--- /dev/null
19
+++ b/docs/system/arm/virt.rst
20
@@ -XXX,XX +XXX,XX @@
21
+'virt' generic virtual platform (``virt``)
22
+==========================================
23
+
24
+The `virt` board is a platform which does not correspond to any
25
+real hardware; it is designed for use in virtual machines.
26
+It is the recommended board type if you simply want to run
27
+a guest such as Linux and do not care about reproducing the
28
+idiosyncrasies and limitations of a particular bit of real-world
29
+hardware.
30
+
31
+This is a "versioned" board model, so as well as the ``virt`` machine
32
+type itself (which may have improvements, bugfixes and other minor
33
+changes between QEMU versions) a version is provided that guarantees
34
+to have the same behaviour as that of previous QEMU releases, so
35
+that VM migration will work between QEMU versions. For instance the
36
+``virt-5.0`` machine type will behave like the ``virt`` machine from
37
+the QEMU 5.0 release, and migration should work between ``virt-5.0``
38
+of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
39
+is not guaranteed to work between different QEMU releases for
40
+the non-versioned ``virt`` machine type.
41
+
42
+Supported devices
43
+"""""""""""""""""
44
+
45
+The virt board supports:
46
+
47
+- PCI/PCIe devices
48
+- Flash memory
49
+- One PL011 UART
50
+- An RTC
51
+- The fw_cfg device that allows a guest to obtain data from QEMU
52
+- A PL061 GPIO controller
53
+- An optional SMMUv3 IOMMU
54
+- hotpluggable DIMMs
55
+- hotpluggable NVDIMMs
56
+- An MSI controller (GICv2M or ITS). GICv2M is selected by default along
57
+ with GICv2. ITS is selected by default with GICv3 (>= virt-2.7). Note
58
+ that ITS is not modeled in TCG mode.
59
+- 32 virtio-mmio transport devices
60
+- running guests using the KVM accelerator on aarch64 hardware
61
+- large amounts of RAM (at least 255GB, and more if using highmem)
62
+- many CPUs (up to 512 if using a GICv3 and highmem)
63
+- Secure-World-only devices if the CPU has TrustZone:
64
+
65
+ - A second PL011 UART
66
+ - A secure flash memory
67
+ - 16MB of secure RAM
68
+
69
+Supported guest CPU types:
70
+
71
+- ``cortex-a7`` (32-bit)
72
+- ``cortex-a15`` (32-bit; the default)
73
+- ``cortex-a53`` (64-bit)
74
+- ``cortex-a57`` (64-bit)
75
+- ``cortex-a72`` (64-bit)
76
+- ``host`` (with KVM only)
77
+- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
78
+
79
+Note that the default is ``cortex-a15``, so for an AArch64 guest you must
80
+specify a CPU type.
81
+
82
+Graphics output is available, but unlike the x86 PC machine types
83
+there is no default display device enabled: you should select one from
84
+the Display devices section of "-device help". The recommended option
85
+is ``virtio-gpu-pci``; this is the only one which will work correctly
86
+with KVM. You may also need to ensure your guest kernel is configured
87
+with support for this; see below.
88
+
89
+Machine-specific options
90
+""""""""""""""""""""""""
91
+
92
+The following machine-specific options are supported:
93
+
94
+secure
95
+ Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
96
+ Arm Security Extensions (TrustZone). The default is ``off``.
97
+
98
+virtualization
99
+ Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
100
+ Arm Virtualization Extensions. The default is ``off``.
101
+
102
+highmem
103
+ Set ``on``/``off`` to enable/disable placing devices and RAM in physical
104
+ address space above 32 bits. The default is ``on`` for machine types
105
+ later than ``virt-2.12``.
106
+
107
+gic-version
108
+ Specify the version of the Generic Interrupt Controller (GIC) to provide.
109
+ Valid values are:
110
+
111
+ ``2``
112
+ GICv2
113
+ ``3``
114
+ GICv3
115
+ ``host``
116
+ Use the same GIC version the host provides, when using KVM
117
+ ``max``
118
+ Use the best GIC version possible (same as host when using KVM;
119
+ currently same as ``3``` for TCG, but this may change in future)
120
+
121
+its
122
+ Set ``on``/``off`` to enable/disable ITS instantiation. The default is ``on``
123
+ for machine types later than ``virt-2.7``.
124
+
125
+iommu
126
+ Set the IOMMU type to create for the guest. Valid values are:
127
+
128
+ ``none``
129
+ Don't create an IOMMU (the default)
130
+ ``smmuv3``
131
+ Create an SMMUv3
132
+
133
+ras
134
+ Set ``on``/``off`` to enable/disable reporting host memory errors to a guest
135
+ using ACPI and guest external abort exceptions. The default is off.
136
+
137
+Linux guest kernel configuration
138
+""""""""""""""""""""""""""""""""
139
+
140
+The 'defconfig' for Linux arm and arm64 kernels should include the
141
+right device drivers for virtio and the PCI controller; however some older
142
+kernel versions, especially for 32-bit Arm, did not have everything
143
+enabled by default. If you're not seeing PCI devices that you expect,
144
+then check that your guest config has::
145
+
146
+ CONFIG_PCI=y
147
+ CONFIG_VIRTIO_PCI=y
148
+ CONFIG_PCI_HOST_GENERIC=y
149
+
150
+If you want to use the ``virtio-gpu-pci`` graphics device you will also
151
+need::
152
+
153
+ CONFIG_DRM=y
154
+ CONFIG_DRM_VIRTIO_GPU=y
155
+
156
+Hardware configuration information for bare-metal programming
157
+"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
158
+
159
+The ``virt`` board automatically generates a device tree blob ("dtb")
160
+which it passes to the guest. This provides information about the
161
+addresses, interrupt lines and other configuration of the various devices
162
+in the system. Guest code can rely on and hard-code the following
163
+addresses:
164
+
165
+- Flash memory starts at address 0x0000_0000
166
+
167
+- RAM starts at 0x4000_0000
168
+
169
+All other information about device locations may change between
170
+QEMU versions, so guest code must look in the DTB.
171
+
172
+QEMU supports two types of guest image boot for ``virt``, and
173
+the way for the guest code to locate the dtb binary differs:
174
+
175
+- For guests using the Linux kernel boot protocol (this means any
176
+ non-ELF file passed to the QEMU ``-kernel`` option) the address
177
+ of the DTB is passed in a register (``r2`` for 32-bit guests,
178
+ or ``x0`` for 64-bit guests)
179
+
180
+- For guests booting as "bare-metal" (any other kind of boot),
181
+ the DTB is at the start of RAM (0x4000_0000)
182
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
183
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
184
--- a/docs/system/target-arm.rst
19
--- a/hw/arm/Kconfig
185
+++ b/docs/system/target-arm.rst
20
+++ b/hw/arm/Kconfig
186
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
21
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
187
arm/collie
22
imply VFIO_PLATFORM
188
arm/sx1
23
imply VFIO_XGMAC
189
arm/stellaris
24
imply TPM_TIS_SYSBUS
190
+ arm/virt
25
+ select ARM_GIC
191
26
select ACPI
192
Arm CPU features
27
select ARM_SMMUV3
193
================
28
select GPIO_KEY
194
diff --git a/MAINTAINERS b/MAINTAINERS
195
index XXXXXXX..XXXXXXX 100644
196
--- a/MAINTAINERS
197
+++ b/MAINTAINERS
198
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
199
S: Maintained
200
F: hw/arm/virt*
201
F: include/hw/arm/virt.h
202
+F: docs/system/arm/virt.rst
203
204
Xilinx Zynq
205
M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
206
--
29
--
207
2.20.1
30
2.20.1
208
31
209
32
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Alex Chen <alex.chen@huawei.com>
2
2
3
Control this cpu feature via a machine property, much as we do
3
We should use printf format specifier "%u" instead of "%d" for
4
with secure=on, since both require specialized support in the
4
argument of type "unsigned int".
5
machine setup to be functional.
6
5
7
Default MTE to off, since this feature implies extra overhead.
6
Reported-by: Euler Robot <euler.robot@huawei.com>
8
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201111073651.72804-1-alex.chen@huawei.com
10
Message-id: 20200713213341.590275-2-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
11
---
14
include/hw/arm/virt.h | 1 +
12
hw/timer/exynos4210_mct.c | 4 ++--
15
hw/arm/virt.c | 39 ++++++++++++++++++++++++++++++++++-----
13
hw/timer/exynos4210_pwm.c | 8 ++++----
16
target/arm/cpu.c | 19 +++++++++++--------
14
2 files changed, 6 insertions(+), 6 deletions(-)
17
target/arm/cpu64.c | 5 +++--
18
4 files changed, 49 insertions(+), 15 deletions(-)
19
15
20
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
16
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
21
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/arm/virt.h
18
--- a/hw/timer/exynos4210_mct.c
23
+++ b/include/hw/arm/virt.h
19
+++ b/hw/timer/exynos4210_mct.c
24
@@ -XXX,XX +XXX,XX @@ typedef struct {
20
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gcomp_raise_irq(void *opaque, uint32_t id)
25
bool its;
21
/* If CSTAT is pending and IRQ is enabled */
26
bool virt;
22
if ((s->reg.int_cstat & G_INT_CSTAT_COMP(id)) &&
27
bool ras;
23
(s->reg.int_enb & G_INT_ENABLE(id))) {
28
+ bool mte;
24
- DPRINTF("gcmp timer[%d] IRQ\n", id);
29
OnOffAuto acpi;
25
+ DPRINTF("gcmp timer[%u] IRQ\n", id);
30
VirtGICType gic_version;
26
qemu_irq_raise(s->irq[id]);
31
VirtIOMMUType iommu;
27
}
32
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
28
}
29
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s)
30
MCT_CFG_GET_DIVIDER(s->reg_mct_cfg));
31
32
if (freq != s->freq) {
33
- DPRINTF("freq=%dHz\n", s->freq);
34
+ DPRINTF("freq=%uHz\n", s->freq);
35
36
/* global timer */
37
tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq);
38
diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c
33
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/virt.c
40
--- a/hw/timer/exynos4210_pwm.c
35
+++ b/hw/arm/virt.c
41
+++ b/hw/timer/exynos4210_pwm.c
36
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
42
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id)
37
OBJECT(secure_sysmem), &error_abort);
43
38
}
44
if (freq != s->timer[id].freq) {
39
45
ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq);
40
- /*
46
- DPRINTF("freq=%dHz\n", s->timer[id].freq);
41
- * The cpu adds the property if and only if MemTag is supported.
47
+ DPRINTF("freq=%uHz\n", s->timer[id].freq);
42
- * If it is, we must allocate the ram to back that up.
48
}
43
- */
44
- if (object_property_find(cpuobj, "tag-memory", NULL)) {
45
+ if (vms->mte) {
46
+ /* Create the memory region only once, but link to all cpus. */
47
if (!tag_sysmem) {
48
+ /*
49
+ * The property exists only if MemTag is supported.
50
+ * If it is, we must allocate the ram to back that up.
51
+ */
52
+ if (!object_property_find(cpuobj, "tag-memory", NULL)) {
53
+ error_report("MTE requested, but not supported "
54
+ "by the guest CPU");
55
+ exit(1);
56
+ }
57
+
58
tag_sysmem = g_new(MemoryRegion, 1);
59
memory_region_init(tag_sysmem, OBJECT(machine),
60
"tag-memory", UINT64_MAX / 32);
61
@@ -XXX,XX +XXX,XX @@ static void virt_set_ras(Object *obj, bool value, Error **errp)
62
vms->ras = value;
63
}
49
}
64
50
65
+static bool virt_get_mte(Object *obj, Error **errp)
51
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque)
66
+{
52
uint32_t id = s->id;
67
+ VirtMachineState *vms = VIRT_MACHINE(obj);
53
bool cmp;
68
+
54
69
+ return vms->mte;
55
- DPRINTF("timer %d tick\n", id);
70
+}
56
+ DPRINTF("timer %u tick\n", id);
71
+
57
72
+static void virt_set_mte(Object *obj, bool value, Error **errp)
58
/* set irq status */
73
+{
59
p->reg_tint_cstat |= TINT_CSTAT_STATUS(id);
74
+ VirtMachineState *vms = VIRT_MACHINE(obj);
60
75
+
61
/* raise IRQ */
76
+ vms->mte = value;
62
if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) {
77
+}
63
- DPRINTF("timer %d IRQ\n", id);
78
+
64
+ DPRINTF("timer %u IRQ\n", id);
79
static char *virt_get_gic_version(Object *obj, Error **errp)
65
qemu_irq_raise(p->timer[id].irq);
80
{
81
VirtMachineState *vms = VIRT_MACHINE(obj);
82
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
83
"Set on/off to enable/disable reporting host memory errors "
84
"to a KVM guest using ACPI and guest external abort exceptions");
85
86
+ /* MTE is disabled by default. */
87
+ vms->mte = false;
88
+ object_property_add_bool(obj, "mte", virt_get_mte, virt_set_mte);
89
+ object_property_set_description(obj, "mte",
90
+ "Set on/off to enable/disable emulating a "
91
+ "guest CPU which implements the ARM "
92
+ "Memory Tagging Extension");
93
+
94
vms->irqmap = a15irqmap;
95
96
virt_flash_create(vms);
97
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
98
index XXXXXXX..XXXXXXX 100644
99
--- a/target/arm/cpu.c
100
+++ b/target/arm/cpu.c
101
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
102
cpu->id_pfr1 &= ~0xf000;
103
}
66
}
104
67
105
+#ifndef CONFIG_USER_ONLY
68
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque)
106
+ if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
107
+ /*
108
+ * Disable the MTE feature bits if we do not have tag-memory
109
+ * provided by the machine.
110
+ */
111
+ cpu->isar.id_aa64pfr1 =
112
+ FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
113
+ }
114
+#endif
115
+
116
/* MPU can be configured out of a PMSA CPU either by setting has-mpu
117
* to false or by setting pmsav7-dregion to 0.
118
*/
119
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
120
cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory",
121
cpu->secure_tag_memory);
122
}
123
- } else if (cpu_isar_feature(aa64_mte, cpu)) {
124
- /*
125
- * Since there is no tag memory, we can't meaningfully support MTE
126
- * to its fullest. To avoid problems later, when we would come to
127
- * use the tag memory, downgrade support to insns only.
128
- */
129
- cpu->isar.id_aa64pfr1 =
130
- FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
131
}
69
}
132
70
133
cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
71
if (cmp) {
134
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
72
- DPRINTF("auto reload timer %d count to %x\n", id,
135
index XXXXXXX..XXXXXXX 100644
73
+ DPRINTF("auto reload timer %u count to %x\n", id,
136
--- a/target/arm/cpu64.c
74
p->timer[id].reg_tcntb);
137
+++ b/target/arm/cpu64.c
75
ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb);
138
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
76
ptimer_run(p->timer[id].ptimer, 1);
139
t = cpu->isar.id_aa64pfr1;
140
t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
141
/*
142
- * Begin with full support for MTE; will be downgraded to MTE=1
143
- * during realize if the board provides no tag memory.
144
+ * Begin with full support for MTE. This will be downgraded to MTE=0
145
+ * during realize if the board provides no tag memory, much like
146
+ * we do for EL2 with the virtualization=on property.
147
*/
148
t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);
149
cpu->isar.id_aa64pfr1 = t;
150
--
77
--
151
2.20.1
78
2.20.1
152
79
153
80
diff view generated by jsdifflib
1
Add skeletal documentation of the gumstix boards
1
In commit 5edab03d4040 we added tracepoints to the ps2 keyboard
2
('connex' and 'verdex').
2
and mouse emulation. However we didn't remove all the debug-by-printf
3
support. In fact there is only one printf() remaining, and it is
4
redundant with the trace_ps2_write_mouse() event next to it.
5
Remove the printf() and the now-unused DEBUG* macros.
3
6
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
7
Message-id: 20200713175746.5936-4-peter.maydell@linaro.org
10
Message-id: 20201101133258.4240-1-peter.maydell@linaro.org
8
---
11
---
9
docs/system/arm/gumstix.rst | 21 +++++++++++++++++++++
12
hw/input/ps2.c | 9 ---------
10
docs/system/target-arm.rst | 1 +
13
1 file changed, 9 deletions(-)
11
MAINTAINERS | 1 +
12
3 files changed, 23 insertions(+)
13
create mode 100644 docs/system/arm/gumstix.rst
14
14
15
diff --git a/docs/system/arm/gumstix.rst b/docs/system/arm/gumstix.rst
15
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
16
new file mode 100644
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX
17
--- a/hw/input/ps2.c
18
--- /dev/null
18
+++ b/hw/input/ps2.c
19
+++ b/docs/system/arm/gumstix.rst
20
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@
21
+Gumstix Connex and Verdex (``connex``, ``verdex``)
20
22
+==================================================
21
#include "trace.h"
23
+
22
24
+These machines model the Gumstix Connex and Verdex boards.
23
-/* debug PC keyboard */
25
+The Connex has a PXA255 CPU and the Verdex has a PXA270.
24
-//#define DEBUG_KBD
26
+
25
-
27
+Implemented devices:
26
-/* debug PC keyboard : only mouse */
28
+
27
-//#define DEBUG_MOUSE
29
+ * NOR flash
28
-
30
+ * SMC91C111 ethernet
29
/* Keyboard Commands */
31
+ * Interrupt controller
30
#define KBD_CMD_SET_LEDS    0xED    /* Set keyboard leds */
32
+ * DMA
31
#define KBD_CMD_ECHO     0xEE
33
+ * Timer
32
@@ -XXX,XX +XXX,XX @@ void ps2_write_mouse(void *opaque, int val)
34
+ * GPIO
33
PS2MouseState *s = (PS2MouseState *)opaque;
35
+ * MMC/SD card
34
36
+ * Fast infra-red communications port (FIR)
35
trace_ps2_write_mouse(opaque, val);
37
+ * LCD controller
36
-#ifdef DEBUG_MOUSE
38
+ * Synchronous serial ports (SPI)
37
- printf("kbd: write mouse 0x%02x\n", val);
39
+ * PCMCIA interface
38
-#endif
40
+ * I2C
39
switch(s->common.write_cmd) {
41
+ * I2S
40
default:
42
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
41
case -1:
43
index XXXXXXX..XXXXXXX 100644
44
--- a/docs/system/target-arm.rst
45
+++ b/docs/system/target-arm.rst
46
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
47
arm/aspeed
48
arm/digic
49
arm/musicpal
50
+ arm/gumstix
51
arm/nseries
52
arm/orangepi
53
arm/palm
54
diff --git a/MAINTAINERS b/MAINTAINERS
55
index XXXXXXX..XXXXXXX 100644
56
--- a/MAINTAINERS
57
+++ b/MAINTAINERS
58
@@ -XXX,XX +XXX,XX @@ R: Philippe Mathieu-Daudé <f4bug@amsat.org>
59
L: qemu-arm@nongnu.org
60
S: Odd Fixes
61
F: hw/arm/gumstix.c
62
+F: docs/system/arm/gumstix.rst
63
64
i.MX25 PDK
65
M: Peter Maydell <peter.maydell@linaro.org>
66
--
42
--
67
2.20.1
43
2.20.1
68
44
69
45
diff view generated by jsdifflib
1
From: David CARLIER <devnexen@gmail.com>
1
In the mtspr helper we attempt to check for "is the timer disabled"
2
with "if (env->ttmr & TIMER_NONE)". This is wrong because TIMER_NONE
3
is zero and the condition is always false (Coverity complains about
4
the dead code.)
2
5
3
Implement qemu_get_thread_id() for OpenBSD hosts, using
6
The correct check would be to test whether the TTMR_M field in the
4
getthrid().
7
register is equal to TIMER_NONE instead. However, the
8
cpu_openrisc_timer_update() function checks whether the timer is
9
enabled (it looks at cpu->env.is_counting, which is set to 0 via
10
cpu_openrisc_count_stop() when the TTMR_M field is set to
11
TIMER_NONE), so there's no need to check for "timer disabled" in the
12
target/openrisc code. Instead, simply remove the dead code.
5
13
6
Signed-off-by: David Carlier <devnexen@gmail.com>
14
Fixes: Coverity CID 1005812
7
Reviewed-by: Brad Smith <brad@comstyle.com>
8
Message-id: CA+XhMqxD6gQDBaj8tX0CMEj3si7qYKsM8u1km47e_-U7MC37Pg@mail.gmail.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
[PMM: tidied up commit message]
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Acked-by: Stafford Horne <shorne@gmail.com>
17
Message-id: 20201103114654.18540-1-peter.maydell@linaro.org
12
---
18
---
13
util/oslib-posix.c | 2 ++
19
target/openrisc/sys_helper.c | 3 ---
14
1 file changed, 2 insertions(+)
20
1 file changed, 3 deletions(-)
15
21
16
diff --git a/util/oslib-posix.c b/util/oslib-posix.c
22
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
17
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
18
--- a/util/oslib-posix.c
24
--- a/target/openrisc/sys_helper.c
19
+++ b/util/oslib-posix.c
25
+++ b/target/openrisc/sys_helper.c
20
@@ -XXX,XX +XXX,XX @@ int qemu_get_thread_id(void)
26
@@ -XXX,XX +XXX,XX @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
21
return (int)tid;
27
22
#elif defined(__NetBSD__)
28
case TO_SPR(10, 1): /* TTCR */
23
return _lwp_self();
29
cpu_openrisc_count_set(cpu, rb);
24
+#elif defined(__OpenBSD__)
30
- if (env->ttmr & TIMER_NONE) {
25
+ return getthrid();
31
- return;
26
#else
32
- }
27
return getpid();
33
cpu_openrisc_timer_update(cpu);
34
break;
28
#endif
35
#endif
29
--
36
--
30
2.20.1
37
2.20.1
31
38
32
39
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Alistair Francis <alistair.francis@wdc.com>
2
2
3
When MTE is enabled, tag memory must exist for all RAM.
3
This patch fixes CID 1432800 by removing an unnecessary check.
4
4
5
It might be possible to simultaneously hot plug tag memory
5
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6
alongside the corresponding normal memory, but for now just
7
disable hotplug.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200713213341.590275-4-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
8
---
14
hw/arm/virt.c | 5 +++++
9
hw/core/register.c | 4 ----
15
1 file changed, 5 insertions(+)
10
1 file changed, 4 deletions(-)
16
11
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
12
diff --git a/hw/core/register.c b/hw/core/register.c
18
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/virt.c
14
--- a/hw/core/register.c
20
+++ b/hw/arm/virt.c
15
+++ b/hw/core/register.c
21
@@ -XXX,XX +XXX,XX @@ static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
16
@@ -XXX,XX +XXX,XX @@ static RegisterInfoArray *register_init_block(DeviceState *owner,
22
return;
17
int index = rae[i].addr / data_size;
23
}
18
RegisterInfo *r = &ri[index];
24
19
25
+ if (vms->mte) {
20
- if (data + data_size * index == 0 || !&rae[i]) {
26
+ error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
21
- continue;
27
+ return;
22
- }
28
+ }
23
-
29
+
24
/* Init the register, this will zero it. */
30
if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
25
object_initialize((void *)r, sizeof(*r), TYPE_REGISTER);
31
error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
26
32
return;
33
--
27
--
34
2.20.1
28
2.20.1
35
29
36
30
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
While we expect KVM to support MTE at some future point,
3
Fix Coverity CID 1435957: Memory - illegal accesses (OVERRUN):
4
it certainly won't be ready in time for qemu 5.1.
5
4
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
>>> Overrunning array "suffixes" of 7 8-byte elements at element
7
Message-id: 20200713213341.590275-3-richard.henderson@linaro.org
6
index 7 (byte offset 63) using index "idx" (which evaluates to 7).
7
8
Note, the biggest input value freq_to_str() can accept is UINT64_MAX,
9
which is ~18.446 EHz, less than 1000 EHz.
10
11
Reported-by: Eduardo Habkost <ehabkost@redhat.com>
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
15
Reviewed-by: Luc Michel <luc@lmichel.fr>
16
Message-id: 20201101215755.2021421-1-f4bug@amsat.org
17
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
20
---
11
hw/arm/virt.c | 6 ++++++
21
util/cutils.c | 3 ++-
12
1 file changed, 6 insertions(+)
22
1 file changed, 2 insertions(+), 1 deletion(-)
13
23
14
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
24
diff --git a/util/cutils.c b/util/cutils.c
15
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/virt.c
26
--- a/util/cutils.c
17
+++ b/hw/arm/virt.c
27
+++ b/util/cutils.c
18
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
28
@@ -XXX,XX +XXX,XX @@ char *freq_to_str(uint64_t freq_hz)
19
exit(1);
29
double freq = freq_hz;
30
size_t idx = 0;
31
32
- while (freq >= 1000.0 && idx < ARRAY_SIZE(suffixes)) {
33
+ while (freq >= 1000.0) {
34
freq /= 1000.0;
35
idx++;
20
}
36
}
21
37
+ assert(idx < ARRAY_SIZE(suffixes));
22
+ if (vms->mte && kvm_enabled()) {
38
23
+ error_report("mach-virt: KVM does not support providing "
39
return g_strdup_printf("%0.3g %sHz", freq, suffixes[idx]);
24
+ "MTE to the guest CPU");
40
}
25
+ exit(1);
26
+ }
27
+
28
create_fdt(vms);
29
30
possible_cpus = mc->possible_cpu_arch_ids(machine);
31
--
41
--
32
2.20.1
42
2.20.1
33
43
34
44
diff view generated by jsdifflib
Deleted patch
1
The doc-comments which document the qdev API are split between the
2
header file and the C source files, because as a project we haven't
3
been consistent about where we put them.
4
1
5
Move all the doc-comments in qdev.c to the header files, so that
6
users of the APIs don't have to look at the implementation files for
7
this information.
8
9
In the process, unify them into our doc-comment format and expand on
10
them in some cases to clarify expected use cases.
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20200711142425.16283-2-peter.maydell@linaro.org
15
---
16
include/hw/qdev-core.h | 57 ++++++++++++++++++++++++++++++++++++
17
include/hw/qdev-properties.h | 13 ++++++++
18
hw/core/qdev.c | 33 ---------------------
19
3 files changed, 70 insertions(+), 33 deletions(-)
20
21
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/qdev-core.h
24
+++ b/include/hw/qdev-core.h
25
@@ -XXX,XX +XXX,XX @@ compat_props_add(GPtrArray *arr,
26
27
/*** Board API. This should go away once we have a machine config file. ***/
28
29
+/**
30
+ * qdev_new: Create a device on the heap
31
+ * @name: device type to create (we assert() that this type exists)
32
+ *
33
+ * This only allocates the memory and initializes the device state
34
+ * structure, ready for the caller to set properties if they wish.
35
+ * The device still needs to be realized.
36
+ * The returned object has a reference count of 1.
37
+ */
38
DeviceState *qdev_new(const char *name);
39
+/**
40
+ * qdev_try_new: Try to create a device on the heap
41
+ * @name: device type to create
42
+ *
43
+ * This is like qdev_new(), except it returns %NULL when type @name
44
+ * does not exist, rather than asserting.
45
+ */
46
DeviceState *qdev_try_new(const char *name);
47
+/**
48
+ * qdev_realize: Realize @dev.
49
+ * @dev: device to realize
50
+ * @bus: bus to plug it into (may be NULL)
51
+ * @errp: pointer to error object
52
+ *
53
+ * "Realize" the device, i.e. perform the second phase of device
54
+ * initialization.
55
+ * @dev must not be plugged into a bus already.
56
+ * If @bus, plug @dev into @bus. This takes a reference to @dev.
57
+ * If @dev has no QOM parent, make one up, taking another reference.
58
+ * On success, return true.
59
+ * On failure, store an error through @errp and return false.
60
+ *
61
+ * If you created @dev using qdev_new(), you probably want to use
62
+ * qdev_realize_and_unref() instead.
63
+ */
64
bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp);
65
+/**
66
+ * qdev_realize_and_unref: Realize @dev and drop a reference
67
+ * @dev: device to realize
68
+ * @bus: bus to plug it into (may be NULL)
69
+ * @errp: pointer to error object
70
+ *
71
+ * Realize @dev and drop a reference.
72
+ * This is like qdev_realize(), except the caller must hold a
73
+ * (private) reference, which is dropped on return regardless of
74
+ * success or failure. Intended use::
75
+ *
76
+ * dev = qdev_new();
77
+ * [...]
78
+ * qdev_realize_and_unref(dev, bus, errp);
79
+ *
80
+ * Now @dev can go away without further ado.
81
+ *
82
+ * If you are embedding the device into some other QOM device and
83
+ * initialized it via some variant on object_initialize_child() then
84
+ * do not use this function, because that family of functions arrange
85
+ * for the only reference to the child device to be held by the parent
86
+ * via the child<> property, and so the reference-count-drop done here
87
+ * would be incorrect. For that use case you want qdev_realize().
88
+ */
89
bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp);
90
void qdev_unrealize(DeviceState *dev);
91
void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id,
92
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
93
index XXXXXXX..XXXXXXX 100644
94
--- a/include/hw/qdev-properties.h
95
+++ b/include/hw/qdev-properties.h
96
@@ -XXX,XX +XXX,XX @@ void error_set_from_qdev_prop_error(Error **errp, int ret, DeviceState *dev,
97
*/
98
void qdev_property_add_static(DeviceState *dev, Property *prop);
99
100
+/**
101
+ * qdev_alias_all_properties: Create aliases on source for all target properties
102
+ * @target: Device which has properties to be aliased
103
+ * @source: Object to add alias properties to
104
+ *
105
+ * Add alias properties to the @source object for all qdev properties on
106
+ * the @target DeviceState.
107
+ *
108
+ * This is useful when @target is an internal implementation object
109
+ * owned by @source, and you want to expose all the properties of that
110
+ * implementation object as properties on the @source object so that users
111
+ * of @source can set them.
112
+ */
113
void qdev_alias_all_properties(DeviceState *target, Object *source);
114
115
/**
116
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
117
index XXXXXXX..XXXXXXX 100644
118
--- a/hw/core/qdev.c
119
+++ b/hw/core/qdev.c
120
@@ -XXX,XX +XXX,XX @@ void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
121
}
122
}
123
124
-/*
125
- * Create a device on the heap.
126
- * A type @name must exist.
127
- * This only initializes the device state structure and allows
128
- * properties to be set. The device still needs to be realized. See
129
- * qdev-core.h.
130
- */
131
DeviceState *qdev_new(const char *name)
132
{
133
if (!object_class_by_name(name)) {
134
@@ -XXX,XX +XXX,XX @@ DeviceState *qdev_new(const char *name)
135
return DEVICE(object_new(name));
136
}
137
138
-/*
139
- * Try to create a device on the heap.
140
- * This is like qdev_new(), except it returns %NULL when type @name
141
- * does not exist.
142
- */
143
DeviceState *qdev_try_new(const char *name)
144
{
145
if (!module_object_class_by_name(name)) {
146
@@ -XXX,XX +XXX,XX @@ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev,
147
qdev_unrealize(dev);
148
}
149
150
-/*
151
- * Realize @dev.
152
- * @dev must not be plugged into a bus.
153
- * If @bus, plug @dev into @bus. This takes a reference to @dev.
154
- * If @dev has no QOM parent, make one up, taking another reference.
155
- * On success, return true.
156
- * On failure, store an error through @errp and return false.
157
- */
158
bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp)
159
{
160
assert(!dev->realized && !dev->parent_bus);
161
@@ -XXX,XX +XXX,XX @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp)
162
return object_property_set_bool(OBJECT(dev), "realized", true, errp);
163
}
164
165
-/*
166
- * Realize @dev and drop a reference.
167
- * This is like qdev_realize(), except the caller must hold a
168
- * (private) reference, which is dropped on return regardless of
169
- * success or failure. Intended use:
170
- * dev = qdev_new();
171
- * [...]
172
- * qdev_realize_and_unref(dev, bus, errp);
173
- * Now @dev can go away without further ado.
174
- */
175
bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp)
176
{
177
bool ret;
178
@@ -XXX,XX +XXX,XX @@ static void qdev_class_add_property(DeviceClass *klass, Property *prop)
179
prop->info->description);
180
}
181
182
-/* @qdev_alias_all_properties - Add alias properties to the source object for
183
- * all qdev properties on the target DeviceState.
184
- */
185
void qdev_alias_all_properties(DeviceState *target, Object *source)
186
{
187
ObjectClass *class;
188
--
189
2.20.1
190
191
diff view generated by jsdifflib
Deleted patch
1
Add a doc comment for qdev_unrealize(), to go with the new
2
documentation for the realize part of the qdev lifecycle.
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200711142425.16283-3-peter.maydell@linaro.org
7
---
8
include/hw/qdev-core.h | 19 +++++++++++++++++++
9
1 file changed, 19 insertions(+)
10
11
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/qdev-core.h
14
+++ b/include/hw/qdev-core.h
15
@@ -XXX,XX +XXX,XX @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp);
16
* would be incorrect. For that use case you want qdev_realize().
17
*/
18
bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp);
19
+/**
20
+ * qdev_unrealize: Unrealize a device
21
+ * @dev: device to unrealize
22
+ *
23
+ * This function will "unrealize" a device, which is the first phase
24
+ * of correctly destroying a device that has been realized. It will:
25
+ *
26
+ * - unrealize any child buses by calling qbus_unrealize()
27
+ * (this will recursively unrealize any devices on those buses)
28
+ * - call the the unrealize method of @dev
29
+ *
30
+ * The device can then be freed by causing its reference count to go
31
+ * to zero.
32
+ *
33
+ * Warning: most devices in QEMU do not expect to be unrealized. Only
34
+ * devices which are hot-unpluggable should be unrealized (as part of
35
+ * the unplugging process); all other devices are expected to last for
36
+ * the life of the simulation and should not be unrealized and freed.
37
+ */
38
void qdev_unrealize(DeviceState *dev);
39
void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id,
40
int required_for_version);
41
--
42
2.20.1
43
44
diff view generated by jsdifflib
1
Add skeletal documentation of the collie board.
1
In commit 76346b6264a9b01979 we tried to add a configure check that
2
the libgio pkg-config data was correct, which builds an executable
3
linked against it. Unfortunately this doesn't catch the problem
4
(missing static library dependency info), because a "do nothing" test
5
source file doesn't have any symbol references that cause the linker
6
to pull in .o files from libgio.a, and so we don't see the "missing
7
symbols from libmount" error that a full QEMU link triggers.
8
9
(The ineffective test went unnoticed because of a typo that
10
effectively disabled libgio unconditionally, but after commit
11
3569a5dfc11f2 fixed that, a static link of the system emulator on
12
Ubuntu stopped working again.)
13
14
Improve the gio test by having the test source fragment reference a
15
g_dbus function (which is what is indirectly causing us to end up
16
wanting functions from libmount).
2
17
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
20
Message-id: 20201116104617.18333-1-peter.maydell@linaro.org
6
Message-id: 20200713175746.5936-3-peter.maydell@linaro.org
7
---
21
---
8
docs/system/arm/collie.rst | 16 ++++++++++++++++
22
configure | 11 +++++++++--
9
docs/system/target-arm.rst | 1 +
23
1 file changed, 9 insertions(+), 2 deletions(-)
10
MAINTAINERS | 1 +
11
3 files changed, 18 insertions(+)
12
create mode 100644 docs/system/arm/collie.rst
13
24
14
diff --git a/docs/system/arm/collie.rst b/docs/system/arm/collie.rst
25
diff --git a/configure b/configure
15
new file mode 100644
26
index XXXXXXX..XXXXXXX 100755
16
index XXXXXXX..XXXXXXX
27
--- a/configure
17
--- /dev/null
28
+++ b/configure
18
+++ b/docs/system/arm/collie.rst
29
@@ -XXX,XX +XXX,XX @@ if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then
19
@@ -XXX,XX +XXX,XX @@
30
# Check that the libraries actually work -- Ubuntu 18.04 ships
20
+Sharp Zaurus SL-5500 (``collie``)
31
# with pkg-config --static --libs data for gio-2.0 that is missing
21
+=================================
32
# -lblkid and will give a link error.
22
+
33
- write_c_skeleton
23
+This machine is a model of the Sharp Zaurus SL-5500, which was
34
- if compile_prog "" "$gio_libs" ; then
24
+a 1990s PDA based on the StrongARM SA1110.
35
+ cat > $TMPC <<EOF
25
+
36
+#include <gio/gio.h>
26
+Implemented devices:
37
+int main(void)
27
+
38
+{
28
+ * NOR flash
39
+ g_dbus_proxy_new_sync(0, 0, 0, 0, 0, 0, 0, 0);
29
+ * Interrupt controller
40
+ return 0;
30
+ * Timer
41
+}
31
+ * RTC
42
+EOF
32
+ * GPIO
43
+ if compile_prog "$gio_cflags" "$gio_libs" ; then
33
+ * Peripheral Pin Controller (PPC)
44
gio=yes
34
+ * UARTs
45
else
35
+ * Synchronous Serial Ports (SSP)
46
gio=no
36
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
37
index XXXXXXX..XXXXXXX 100644
38
--- a/docs/system/target-arm.rst
39
+++ b/docs/system/target-arm.rst
40
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
41
arm/orangepi
42
arm/palm
43
arm/xscale
44
+ arm/collie
45
arm/sx1
46
arm/stellaris
47
48
diff --git a/MAINTAINERS b/MAINTAINERS
49
index XXXXXXX..XXXXXXX 100644
50
--- a/MAINTAINERS
51
+++ b/MAINTAINERS
52
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
53
S: Odd Fixes
54
F: hw/arm/collie.c
55
F: hw/arm/strongarm*
56
+F: docs/system/arm/collie.rst
57
58
Stellaris
59
M: Peter Maydell <peter.maydell@linaro.org>
60
--
47
--
61
2.20.1
48
2.20.1
62
49
63
50
diff view generated by jsdifflib
1
Add documentation comments for the various qdev functions
1
The TMP105 datasheet (https://www.ti.com/lit/gpn/tmp105) says that the
2
related to creating and connecting GPIO lines.
2
power-up reset values for the T_low and T_high registers are 80 degrees C
3
and 75 degrees C, which are 0x500 and 0x4B0 hex according to table 5. These
4
values are then shifted right by four bits to give the register reset
5
values, since both registers store the 12 bits of temperature data in bits
6
[15..4] of a 16 bit register.
7
8
We were resetting these registers to zero, which is problematic for Linux
9
guests which enable the alert interrupt and then immediately take an
10
unexpected overtemperature alert because the current temperature is above
11
freezing...
3
12
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Cédric Le Goater <clg@kaod.org>
6
Message-id: 20200711142425.16283-4-peter.maydell@linaro.org
15
Message-id: 20201110150023.25533-2-peter.maydell@linaro.org
7
---
16
---
8
include/hw/qdev-core.h | 191 ++++++++++++++++++++++++++++++++++++++++-
17
hw/misc/tmp105.c | 3 +++
9
1 file changed, 189 insertions(+), 2 deletions(-)
18
1 file changed, 3 insertions(+)
10
19
11
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
20
diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c
12
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/qdev-core.h
22
--- a/hw/misc/tmp105.c
14
+++ b/include/hw/qdev-core.h
23
+++ b/hw/misc/tmp105.c
15
@@ -XXX,XX +XXX,XX @@ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev,
24
@@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c)
16
void qdev_machine_creation_done(void);
25
s->faults = tmp105_faultq[(s->config >> 3) & 3];
17
bool qdev_machine_modified(void);
26
s->alarm = 0;
18
27
19
+/**
28
+ s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */
20
+ * qdev_get_gpio_in: Get one of a device's anonymous input GPIO lines
29
+ s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */
21
+ * @dev: Device whose GPIO we want
30
+
22
+ * @n: Number of the anonymous GPIO line (which must be in range)
31
tmp105_interrupt_update(s);
23
+ *
24
+ * Returns the qemu_irq corresponding to an anonymous input GPIO line
25
+ * (which the device has set up with qdev_init_gpio_in()). The index
26
+ * @n of the GPIO line must be valid (i.e. be at least 0 and less than
27
+ * the total number of anonymous input GPIOs the device has); this
28
+ * function will assert() if passed an invalid index.
29
+ *
30
+ * This function is intended to be used by board code or SoC "container"
31
+ * device models to wire up the GPIO lines; usually the return value
32
+ * will be passed to qdev_connect_gpio_out() or a similar function to
33
+ * connect another device's output GPIO line to this input.
34
+ *
35
+ * For named input GPIO lines, use qdev_get_gpio_in_named().
36
+ */
37
qemu_irq qdev_get_gpio_in(DeviceState *dev, int n);
38
+/**
39
+ * qdev_get_gpio_in_named: Get one of a device's named input GPIO lines
40
+ * @dev: Device whose GPIO we want
41
+ * @name: Name of the input GPIO array
42
+ * @n: Number of the GPIO line in that array (which must be in range)
43
+ *
44
+ * Returns the qemu_irq corresponding to a named input GPIO line
45
+ * (which the device has set up with qdev_init_gpio_in_named()).
46
+ * The @name string must correspond to an input GPIO array which exists on
47
+ * the device, and the index @n of the GPIO line must be valid (i.e.
48
+ * be at least 0 and less than the total number of input GPIOs in that
49
+ * array); this function will assert() if passed an invalid name or index.
50
+ *
51
+ * For anonymous input GPIO lines, use qdev_get_gpio_in().
52
+ */
53
qemu_irq qdev_get_gpio_in_named(DeviceState *dev, const char *name, int n);
54
55
+/**
56
+ * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines
57
+ * @dev: Device whose GPIO to connect
58
+ * @n: Number of the anonymous output GPIO line (which must be in range)
59
+ * @pin: qemu_irq to connect the output line to
60
+ *
61
+ * This function connects an anonymous output GPIO line on a device
62
+ * up to an arbitrary qemu_irq, so that when the device asserts that
63
+ * output GPIO line, the qemu_irq's callback is invoked.
64
+ * The index @n of the GPIO line must be valid (i.e. be at least 0 and
65
+ * less than the total number of anonymous output GPIOs the device has
66
+ * created with qdev_init_gpio_out()); otherwise this function will assert().
67
+ *
68
+ * Outbound GPIO lines can be connected to any qemu_irq, but the common
69
+ * case is connecting them to another device's inbound GPIO line, using
70
+ * the qemu_irq returned by qdev_get_gpio_in() or qdev_get_gpio_in_named().
71
+ *
72
+ * It is not valid to try to connect one outbound GPIO to multiple
73
+ * qemu_irqs at once, or to connect multiple outbound GPIOs to the
74
+ * same qemu_irq. (Warning: there is no assertion or other guard to
75
+ * catch this error: the model will just not do the right thing.)
76
+ * Instead, for fan-out you can use the TYPE_IRQ_SPLIT device: connect
77
+ * a device's outbound GPIO to the splitter's input, and connect each
78
+ * of the splitter's outputs to a different device. For fan-in you
79
+ * can use the TYPE_OR_IRQ device, which is a model of a logical OR
80
+ * gate with multiple inputs and one output.
81
+ *
82
+ * For named output GPIO lines, use qdev_connect_gpio_out_named().
83
+ */
84
void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin);
85
+/**
86
+ * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines
87
+ * @dev: Device whose GPIO to connect
88
+ * @name: Name of the output GPIO array
89
+ * @n: Number of the anonymous output GPIO line (which must be in range)
90
+ * @pin: qemu_irq to connect the output line to
91
+ *
92
+ * This function connects an anonymous output GPIO line on a device
93
+ * up to an arbitrary qemu_irq, so that when the device asserts that
94
+ * output GPIO line, the qemu_irq's callback is invoked.
95
+ * The @name string must correspond to an output GPIO array which exists on
96
+ * the device, and the index @n of the GPIO line must be valid (i.e.
97
+ * be at least 0 and less than the total number of input GPIOs in that
98
+ * array); this function will assert() if passed an invalid name or index.
99
+ *
100
+ * Outbound GPIO lines can be connected to any qemu_irq, but the common
101
+ * case is connecting them to another device's inbound GPIO line, using
102
+ * the qemu_irq returned by qdev_get_gpio_in() or qdev_get_gpio_in_named().
103
+ *
104
+ * It is not valid to try to connect one outbound GPIO to multiple
105
+ * qemu_irqs at once, or to connect multiple outbound GPIOs to the
106
+ * same qemu_irq; see qdev_connect_gpio_out() for details.
107
+ *
108
+ * For named output GPIO lines, use qdev_connect_gpio_out_named().
109
+ */
110
void qdev_connect_gpio_out_named(DeviceState *dev, const char *name, int n,
111
qemu_irq pin);
112
+/**
113
+ * qdev_get_gpio_out_connector: Get the qemu_irq connected to an output GPIO
114
+ * @dev: Device whose output GPIO we are interested in
115
+ * @name: Name of the output GPIO array
116
+ * @n: Number of the output GPIO line within that array
117
+ *
118
+ * Returns whatever qemu_irq is currently connected to the specified
119
+ * output GPIO line of @dev. This will be NULL if the output GPIO line
120
+ * has never been wired up to the anything. Note that the qemu_irq
121
+ * returned does not belong to @dev -- it will be the input GPIO or
122
+ * IRQ of whichever device the board code has connected up to @dev's
123
+ * output GPIO.
124
+ *
125
+ * You probably don't need to use this function -- it is used only
126
+ * by the platform-bus subsystem.
127
+ */
128
qemu_irq qdev_get_gpio_out_connector(DeviceState *dev, const char *name, int n);
129
+/**
130
+ * qdev_intercept_gpio_out: Intercept an existing GPIO connection
131
+ * @dev: Device to intercept the outbound GPIO line from
132
+ * @icpt: New qemu_irq to connect instead
133
+ * @name: Name of the output GPIO array
134
+ * @n: Number of the GPIO line in the array
135
+ *
136
+ * This function is provided only for use by the qtest testing framework
137
+ * and is not suitable for use in non-testing parts of QEMU.
138
+ *
139
+ * This function breaks an existing connection of an outbound GPIO
140
+ * line from @dev, and replaces it with the new qemu_irq @icpt, as if
141
+ * ``qdev_connect_gpio_out_named(dev, icpt, name, n)`` had been called.
142
+ * The previously connected qemu_irq is returned, so it can be restored
143
+ * by a second call to qdev_intercept_gpio_out() if desired.
144
+ */
145
qemu_irq qdev_intercept_gpio_out(DeviceState *dev, qemu_irq icpt,
146
const char *name, int n);
147
148
@@ -XXX,XX +XXX,XX @@ BusState *qdev_get_child_bus(DeviceState *dev, const char *name);
149
150
/*** Device API. ***/
151
152
-/* Register device properties. */
153
-/* GPIO inputs also double as IRQ sinks. */
154
+/**
155
+ * qdev_init_gpio_in: create an array of anonymous input GPIO lines
156
+ * @dev: Device to create input GPIOs for
157
+ * @handler: Function to call when GPIO line value is set
158
+ * @n: Number of GPIO lines to create
159
+ *
160
+ * Devices should use functions in the qdev_init_gpio_in* family in
161
+ * their instance_init or realize methods to create any input GPIO
162
+ * lines they need. There is no functional difference between
163
+ * anonymous and named GPIO lines. Stylistically, named GPIOs are
164
+ * preferable (easier to understand at callsites) unless a device
165
+ * has exactly one uniform kind of GPIO input whose purpose is obvious.
166
+ * Note that input GPIO lines can serve as 'sinks' for IRQ lines.
167
+ *
168
+ * See qdev_get_gpio_in() for how code that uses such a device can get
169
+ * hold of an input GPIO line to manipulate it.
170
+ */
171
void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n);
172
+/**
173
+ * qdev_init_gpio_out: create an array of anonymous output GPIO lines
174
+ * @dev: Device to create output GPIOs for
175
+ * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines
176
+ * @n: Number of GPIO lines to create
177
+ *
178
+ * Devices should use functions in the qdev_init_gpio_out* family
179
+ * in their instance_init or realize methods to create any output
180
+ * GPIO lines they need. There is no functional difference between
181
+ * anonymous and named GPIO lines. Stylistically, named GPIOs are
182
+ * preferable (easier to understand at callsites) unless a device
183
+ * has exactly one uniform kind of GPIO output whose purpose is obvious.
184
+ *
185
+ * The @pins argument should be a pointer to either a "qemu_irq"
186
+ * (if @n == 1) or a "qemu_irq []" array (if @n > 1) in the device's
187
+ * state structure. The device implementation can then raise and
188
+ * lower the GPIO line by calling qemu_set_irq(). (If anything is
189
+ * connected to the other end of the GPIO this will cause the handler
190
+ * function for that input GPIO to be called.)
191
+ *
192
+ * See qdev_connect_gpio_out() for how code that uses such a device
193
+ * can connect to one of its output GPIO lines.
194
+ */
195
void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n);
196
+/**
197
+ * qdev_init_gpio_out: create an array of named output GPIO lines
198
+ * @dev: Device to create output GPIOs for
199
+ * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines
200
+ * @name: Name to give this array of GPIO lines
201
+ * @n: Number of GPIO lines to create
202
+ *
203
+ * Like qdev_init_gpio_out(), but creates an array of GPIO output lines
204
+ * with a name. Code using the device can then connect these GPIO lines
205
+ * using qdev_connect_gpio_out_named().
206
+ */
207
void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins,
208
const char *name, int n);
209
/**
210
@@ -XXX,XX +XXX,XX @@ static inline void qdev_init_gpio_in_named(DeviceState *dev,
211
qdev_init_gpio_in_named_with_opaque(dev, handler, dev, name, n);
212
}
32
}
213
214
+/**
215
+ * qdev_pass_gpios: create GPIO lines on container which pass through to device
216
+ * @dev: Device which has GPIO lines
217
+ * @container: Container device which needs to expose them
218
+ * @name: Name of GPIO array to pass through (NULL for the anonymous GPIO array)
219
+ *
220
+ * In QEMU, complicated devices like SoCs are often modelled with a
221
+ * "container" QOM device which itself contains other QOM devices and
222
+ * which wires them up appropriately. This function allows the container
223
+ * to create GPIO arrays on itself which simply pass through to a GPIO
224
+ * array of one of its internal devices.
225
+ *
226
+ * If @dev has both input and output GPIOs named @name then both will
227
+ * be passed through. It is not possible to pass a subset of the array
228
+ * with this function.
229
+ *
230
+ * To users of the container device, the GPIO array created on @container
231
+ * behaves exactly like any other.
232
+ */
233
void qdev_pass_gpios(DeviceState *dev, DeviceState *container,
234
const char *name);
235
33
236
--
34
--
237
2.20.1
35
2.20.1
238
36
239
37
diff view generated by jsdifflib
1
In armsse_realize() we have a loop over [0, info->num_cpus), which
1
The TMP105 datasheet says that in Interrupt Mode (when TM==1) the device
2
indexes into various fixed-size arrays in the ARMSSE struct. This
2
signals an alert when the temperature equals or exceeds the T_high value and
3
confuses Coverity, which warns that we might overrun those arrays
3
then remains high until a device register is read or the device responds to
4
(CID 1430326, 1430337, 1430371, 1430414, 1430430). This can't
4
the SMBUS Alert Response address, or the device is put into Shutdown Mode.
5
actually happen, because the info struct is always one of the entries
5
Thereafter the Alert pin will only be re-signalled when temperature falls
6
in the armsse_variants[] array and num_cpus is either 1 or 2; we also
6
below T_low; alert can then be cleared in the same set of ways, and the
7
already assert in armsse_init() that num_cpus is not too large.
7
device returns to its initial "alert when temperature goes above T_high"
8
However, adding an assert to armsse_realize() like the one in
8
mode. (If this textual description is confusing, see figure 3 in the
9
armsse_init() should help Coverity figure out that these code paths
9
TI datasheet at https://www.ti.com/lit/gpn/tmp105 .)
10
aren't possible.
10
11
We were misimplementing this as a simple "always alert if temperature is
12
above T_high or below T_low" condition, which gives a spurious alert on
13
startup if using the "T_high = 80 degrees C, T_low = 75 degrees C" reset
14
limit values.
15
16
Implement the correct (hysteresis) behaviour by tracking whether we
17
are currently looking for the temperature to rise over T_high or
18
for it to fall below T_low. Our implementation of the comparator
19
mode (TM==0) wasn't wrong, but rephrase it to match the way that
20
interrupt mode is now handled for clarity.
11
21
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
23
Reviewed-by: Cédric Le Goater <clg@kaod.org>
14
Message-id: 20200713143716.9881-1-peter.maydell@linaro.org
24
Message-id: 20201110150023.25533-3-peter.maydell@linaro.org
15
---
25
---
16
hw/arm/armsse.c | 2 ++
26
hw/misc/tmp105.h | 7 +++++
17
1 file changed, 2 insertions(+)
27
hw/misc/tmp105.c | 70 +++++++++++++++++++++++++++++++++++++++++-------
28
2 files changed, 68 insertions(+), 9 deletions(-)
18
29
19
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
30
diff --git a/hw/misc/tmp105.h b/hw/misc/tmp105.h
20
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/armsse.c
32
--- a/hw/misc/tmp105.h
22
+++ b/hw/arm/armsse.c
33
+++ b/hw/misc/tmp105.h
23
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
34
@@ -XXX,XX +XXX,XX @@ struct TMP105State {
24
return;
35
int16_t limit[2];
36
int faults;
37
uint8_t alarm;
38
+ /*
39
+ * The TMP105 initially looks for a temperature rising above T_high;
40
+ * once this is detected, the condition it looks for next is the
41
+ * temperature falling below T_low. This flag is false when initially
42
+ * looking for T_high, true when looking for T_low.
43
+ */
44
+ bool detect_falling;
45
};
46
47
#endif
48
diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/misc/tmp105.c
51
+++ b/hw/misc/tmp105.c
52
@@ -XXX,XX +XXX,XX @@ static void tmp105_alarm_update(TMP105State *s)
53
return;
25
}
54
}
26
55
27
+ assert(info->num_cpus <= SSE_MAX_CPUS);
56
- if ((s->config >> 1) & 1) {                    /* TM */
57
- if (s->temperature >= s->limit[1])
58
- s->alarm = 1;
59
- else if (s->temperature < s->limit[0])
60
- s->alarm = 1;
61
+ if (s->config >> 1 & 1) {
62
+ /*
63
+ * TM == 1 : Interrupt mode. We signal Alert when the
64
+ * temperature rises above T_high, and expect the guest to clear
65
+ * it (eg by reading a device register).
66
+ */
67
+ if (s->detect_falling) {
68
+ if (s->temperature < s->limit[0]) {
69
+ s->alarm = 1;
70
+ s->detect_falling = false;
71
+ }
72
+ } else {
73
+ if (s->temperature >= s->limit[1]) {
74
+ s->alarm = 1;
75
+ s->detect_falling = true;
76
+ }
77
+ }
78
} else {
79
- if (s->temperature >= s->limit[1])
80
- s->alarm = 1;
81
- else if (s->temperature < s->limit[0])
82
- s->alarm = 0;
83
+ /*
84
+ * TM == 0 : Comparator mode. We signal Alert when the temperature
85
+ * rises above T_high, and stop signalling it when the temperature
86
+ * falls below T_low.
87
+ */
88
+ if (s->detect_falling) {
89
+ if (s->temperature < s->limit[0]) {
90
+ s->alarm = 0;
91
+ s->detect_falling = false;
92
+ }
93
+ } else {
94
+ if (s->temperature >= s->limit[1]) {
95
+ s->alarm = 1;
96
+ s->detect_falling = true;
97
+ }
98
+ }
99
}
100
101
tmp105_interrupt_update(s);
102
@@ -XXX,XX +XXX,XX @@ static int tmp105_post_load(void *opaque, int version_id)
103
return 0;
104
}
105
106
+static bool detect_falling_needed(void *opaque)
107
+{
108
+ TMP105State *s = opaque;
28
+
109
+
29
/* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */
110
+ /*
30
assert(is_power_of_2(info->sram_banks));
111
+ * We only need to migrate the detect_falling bool if it's set;
31
addr_width_max = 24 - ctz32(info->sram_banks);
112
+ * for migration from older machines we assume that it is false
113
+ * (ie temperature is not out of range).
114
+ */
115
+ return s->detect_falling;
116
+}
117
+
118
+static const VMStateDescription vmstate_tmp105_detect_falling = {
119
+ .name = "TMP105/detect-falling",
120
+ .version_id = 1,
121
+ .minimum_version_id = 1,
122
+ .needed = detect_falling_needed,
123
+ .fields = (VMStateField[]) {
124
+ VMSTATE_BOOL(detect_falling, TMP105State),
125
+ VMSTATE_END_OF_LIST()
126
+ }
127
+};
128
+
129
static const VMStateDescription vmstate_tmp105 = {
130
.name = "TMP105",
131
.version_id = 0,
132
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_tmp105 = {
133
VMSTATE_UINT8(alarm, TMP105State),
134
VMSTATE_I2C_SLAVE(i2c, TMP105State),
135
VMSTATE_END_OF_LIST()
136
+ },
137
+ .subsections = (const VMStateDescription*[]) {
138
+ &vmstate_tmp105_detect_falling,
139
+ NULL
140
}
141
};
142
143
@@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c)
144
s->config = 0;
145
s->faults = tmp105_faultq[(s->config >> 3) & 3];
146
s->alarm = 0;
147
+ s->detect_falling = false;
148
149
s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */
150
s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */
32
--
151
--
33
2.20.1
152
2.20.1
34
153
35
154
diff view generated by jsdifflib
Deleted patch
1
Add skeletal documentation of the canon-a1100 board.
2
1
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Message-id: 20200713175746.5936-2-peter.maydell@linaro.org
7
---
8
docs/system/arm/digic.rst | 11 +++++++++++
9
docs/system/target-arm.rst | 1 +
10
MAINTAINERS | 1 +
11
3 files changed, 13 insertions(+)
12
create mode 100644 docs/system/arm/digic.rst
13
14
diff --git a/docs/system/arm/digic.rst b/docs/system/arm/digic.rst
15
new file mode 100644
16
index XXXXXXX..XXXXXXX
17
--- /dev/null
18
+++ b/docs/system/arm/digic.rst
19
@@ -XXX,XX +XXX,XX @@
20
+Canon A1100 (``canon-a1100``)
21
+=============================
22
+
23
+This machine is a model of the Canon PowerShot A1100 camera, which
24
+uses the DIGIC SoC. This model is based on reverse engineering efforts
25
+by the contributors to the `CHDK <http://chdk.wikia.com/>`_ and
26
+`Magic Lantern <http://www.magiclantern.fm/>`_ projects.
27
+
28
+The emulation is incomplete. In particular it can't be used
29
+to run the original camera firmware, but it can successfully run
30
+an experimental version of the `barebox bootloader <http://www.barebox.org/>`_.
31
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
32
index XXXXXXX..XXXXXXX 100644
33
--- a/docs/system/target-arm.rst
34
+++ b/docs/system/target-arm.rst
35
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
36
arm/versatile
37
arm/vexpress
38
arm/aspeed
39
+ arm/digic
40
arm/musicpal
41
arm/nseries
42
arm/orangepi
43
diff --git a/MAINTAINERS b/MAINTAINERS
44
index XXXXXXX..XXXXXXX 100644
45
--- a/MAINTAINERS
46
+++ b/MAINTAINERS
47
@@ -XXX,XX +XXX,XX @@ F: include/hw/arm/digic.h
48
F: hw/*/digic*
49
F: include/hw/*/digic*
50
F: tests/acceptance/machine_arm_canona1100.py
51
+F: docs/system/arm/digic.rst
52
53
Goldfish RTC
54
M: Anup Patel <anup.patel@wdc.com>
55
--
56
2.20.1
57
58
diff view generated by jsdifflib