1 | Not much here, mostly documentation, but a few bug fixes. | 1 | Patches for rc1: nothing major, just some minor bugfixes and |
---|---|---|---|
2 | code cleanups. | ||
2 | 3 | ||
3 | thanks | ||
4 | -- PMM | 4 | -- PMM |
5 | 5 | ||
6 | The following changes since commit 873ec69aeb12e24eec7fb317fd0cd8494e8489dd: | 6 | The following changes since commit f7e1914adad8885a5d4c70239ab90d901ed97e9f: |
7 | 7 | ||
8 | Merge remote-tracking branch 'remotes/cminyard/tags/for-qemu-i2c-5' into staging (2020-07-20 11:03:09 +0100) | 8 | Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging (2020-11-10 09:24:56 +0000) |
9 | 9 | ||
10 | are available in the Git repository at: | 10 | are available in the Git repository at: |
11 | 11 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200720 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201110 |
13 | 13 | ||
14 | for you to fetch changes up to 6a0b7505f1fd6769c3f1558fda76464d51e4118a: | 14 | for you to fetch changes up to b6c56c8a9a4064ea783f352f43c5df6231a110fa: |
15 | 15 | ||
16 | docs/system: Document the arm virt board (2020-07-20 11:35:17 +0100) | 16 | target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check (2020-11-10 11:03:48 +0000) |
17 | 17 | ||
18 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
19 | target-arm queue: | 19 | target-arm queue: |
20 | * virt: Don't enable MTE emulation by default | 20 | * hw/arm/Kconfig: ARM_V7M depends on PTIMER |
21 | * virt: Diagnose attempts to use MTE with memory-hotplug or KVM | 21 | * Minor coding style fixes |
22 | (rather than silently not working correctly) | 22 | * docs: add some notes on the sbsa-ref machine |
23 | * util: Implement qemu_get_thread_id() for OpenBSD | 23 | * hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals |
24 | * qdev: Add doc comments for qdev_unrealize and GPIO functions, | 24 | * target/arm: Fix neon VTBL/VTBX for len > 1 |
25 | and standardize on doc-comments-in-header-file | 25 | * hw/arm/armsse: Correct expansion MPC interrupt lines |
26 | * hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize() | 26 | * hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ |
27 | * docs/system: Document canon-a1100, collie, gumstix, virt boards | 27 | * hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup() |
28 | * hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input | ||
29 | * hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary | ||
30 | * hw/arm/nseries: Check return value from load_image_targphys() | ||
31 | * tests/qtest/npcm7xx_rng-test: count runs properly | ||
32 | * target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check | ||
28 | 33 | ||
29 | ---------------------------------------------------------------- | 34 | ---------------------------------------------------------------- |
30 | David CARLIER (1): | 35 | Alex Bennée (1): |
31 | util: Implement qemu_get_thread_id() for OpenBSD | 36 | docs: add some notes on the sbsa-ref machine |
32 | 37 | ||
33 | Peter Maydell (8): | 38 | AlexChen (1): |
34 | qdev: Move doc comments from qdev.c to qdev-core.h | 39 | ssi: Fix bad printf format specifiers |
35 | qdev: Document qdev_unrealize() | ||
36 | qdev: Document GPIO related functions | ||
37 | hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize() | ||
38 | docs/system: Briefly document canon-a1100 board | ||
39 | docs/system: Briefly document collie board | ||
40 | docs/system: Briefly document gumstix boards | ||
41 | docs/system: Document the arm virt board | ||
42 | 40 | ||
43 | Richard Henderson (3): | 41 | Andrew Jones (1): |
44 | hw/arm/virt: Enable MTE via a machine property | 42 | hw/arm/Kconfig: ARM_V7M depends on PTIMER |
45 | hw/arm/virt: Error for MTE enabled with KVM | ||
46 | hw/arm/virt: Disable memory hotplug when MTE is enabled | ||
47 | 43 | ||
48 | docs/system/arm/collie.rst | 16 +++ | 44 | Havard Skinnemoen (1): |
49 | docs/system/arm/digic.rst | 11 ++ | 45 | tests/qtest/npcm7xx_rng-test: count runs properly |
50 | docs/system/arm/gumstix.rst | 21 ++++ | ||
51 | docs/system/arm/virt.rst | 161 ++++++++++++++++++++++++++ | ||
52 | docs/system/target-arm.rst | 4 + | ||
53 | include/hw/arm/virt.h | 1 + | ||
54 | include/hw/qdev-core.h | 267 ++++++++++++++++++++++++++++++++++++++++++- | ||
55 | include/hw/qdev-properties.h | 13 +++ | ||
56 | hw/arm/armsse.c | 2 + | ||
57 | hw/arm/virt.c | 50 +++++++- | ||
58 | hw/core/qdev.c | 33 ------ | ||
59 | target/arm/cpu.c | 19 +-- | ||
60 | target/arm/cpu64.c | 5 +- | ||
61 | util/oslib-posix.c | 2 + | ||
62 | MAINTAINERS | 4 + | ||
63 | 15 files changed, 559 insertions(+), 50 deletions(-) | ||
64 | create mode 100644 docs/system/arm/collie.rst | ||
65 | create mode 100644 docs/system/arm/digic.rst | ||
66 | create mode 100644 docs/system/arm/gumstix.rst | ||
67 | create mode 100644 docs/system/arm/virt.rst | ||
68 | 46 | ||
47 | Peter Maydell (2): | ||
48 | hw/arm/nseries: Check return value from load_image_targphys() | ||
49 | target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check | ||
50 | |||
51 | Philippe Mathieu-Daudé (6): | ||
52 | hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals | ||
53 | hw/arm/armsse: Correct expansion MPC interrupt lines | ||
54 | hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ | ||
55 | hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup() | ||
56 | hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input | ||
57 | hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary | ||
58 | |||
59 | Richard Henderson (1): | ||
60 | target/arm: Fix neon VTBL/VTBX for len > 1 | ||
61 | |||
62 | Xinhao Zhang (3): | ||
63 | target/arm: add spaces around operator | ||
64 | target/arm: Don't use '#' flag of printf format | ||
65 | target/arm: add space before the open parenthesis '(' | ||
66 | |||
67 | docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++ | ||
68 | docs/system/target-arm.rst | 1 + | ||
69 | include/hw/misc/stm32f2xx_syscfg.h | 2 -- | ||
70 | target/arm/helper.h | 2 +- | ||
71 | hw/arm/armsse.c | 3 +- | ||
72 | hw/arm/musicpal.c | 40 +++++++++++++++++---------- | ||
73 | hw/arm/nseries.c | 26 ++++++++---------- | ||
74 | hw/arm/stm32f205_soc.c | 1 - | ||
75 | hw/misc/stm32f2xx_syscfg.c | 2 -- | ||
76 | hw/ssi/imx_spi.c | 2 +- | ||
77 | hw/ssi/xilinx_spi.c | 2 +- | ||
78 | target/arm/arch_dump.c | 8 +++--- | ||
79 | target/arm/arm-semi.c | 8 +++--- | ||
80 | target/arm/helper.c | 2 +- | ||
81 | target/arm/op_helper.c | 23 +++++++++------- | ||
82 | target/arm/translate-a64.c | 4 +-- | ||
83 | target/arm/translate.c | 2 +- | ||
84 | tests/qtest/npcm7xx_rng-test.c | 2 +- | ||
85 | hw/arm/Kconfig | 3 +- | ||
86 | target/arm/translate-neon.c.inc | 56 ++++++++++++++------------------------ | ||
87 | 20 files changed, 123 insertions(+), 98 deletions(-) | ||
88 | create mode 100644 docs/system/arm/sbsa.rst | ||
89 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Andrew Jones <drjones@redhat.com> | ||
1 | 2 | ||
3 | commit 32bd322a0134 ("hw/timer/armv7m_systick: Rewrite to use ptimers") | ||
4 | changed armv7m_systick to build on ptimers. Make sure we have ptimers | ||
5 | in the build when building armv7m_systick. | ||
6 | |||
7 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
9 | Message-id: 20201104103343.30392-1-drjones@redhat.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/arm/Kconfig | 1 + | ||
13 | 1 file changed, 1 insertion(+) | ||
14 | |||
15 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/arm/Kconfig | ||
18 | +++ b/hw/arm/Kconfig | ||
19 | @@ -XXX,XX +XXX,XX @@ config ZYNQ | ||
20 | |||
21 | config ARM_V7M | ||
22 | bool | ||
23 | + select PTIMER | ||
24 | |||
25 | config ALLWINNER_A10 | ||
26 | bool | ||
27 | -- | ||
28 | 2.20.1 | ||
29 | |||
30 | diff view generated by jsdifflib |
1 | The doc-comments which document the qdev API are split between the | 1 | From: AlexChen <alex.chen@huawei.com> |
---|---|---|---|
2 | header file and the C source files, because as a project we haven't | ||
3 | been consistent about where we put them. | ||
4 | 2 | ||
5 | Move all the doc-comments in qdev.c to the header files, so that | 3 | We should use printf format specifier "%u" instead of "%d" for |
6 | users of the APIs don't have to look at the implementation files for | 4 | argument of type "unsigned int". |
7 | this information. | ||
8 | 5 | ||
9 | In the process, unify them into our doc-comment format and expand on | 6 | Reported-by: Euler Robot <euler.robot@huawei.com> |
10 | them in some cases to clarify expected use cases. | 7 | Signed-off-by: Alex Chen <alex.chen@huawei.com> |
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
9 | Message-id: 5FA280F5.8060902@huawei.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/ssi/imx_spi.c | 2 +- | ||
13 | hw/ssi/xilinx_spi.c | 2 +- | ||
14 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
11 | 15 | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c |
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Message-id: 20200711142425.16283-2-peter.maydell@linaro.org | ||
15 | --- | ||
16 | include/hw/qdev-core.h | 57 ++++++++++++++++++++++++++++++++++++ | ||
17 | include/hw/qdev-properties.h | 13 ++++++++ | ||
18 | hw/core/qdev.c | 33 --------------------- | ||
19 | 3 files changed, 70 insertions(+), 33 deletions(-) | ||
20 | |||
21 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | ||
22 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/include/hw/qdev-core.h | 18 | --- a/hw/ssi/imx_spi.c |
24 | +++ b/include/hw/qdev-core.h | 19 | +++ b/hw/ssi/imx_spi.c |
25 | @@ -XXX,XX +XXX,XX @@ compat_props_add(GPtrArray *arr, | 20 | @@ -XXX,XX +XXX,XX @@ static const char *imx_spi_reg_name(uint32_t reg) |
26 | 21 | case ECSPI_MSGDATA: | |
27 | /*** Board API. This should go away once we have a machine config file. ***/ | 22 | return "ECSPI_MSGDATA"; |
28 | 23 | default: | |
29 | +/** | 24 | - sprintf(unknown, "%d ?", reg); |
30 | + * qdev_new: Create a device on the heap | 25 | + sprintf(unknown, "%u ?", reg); |
31 | + * @name: device type to create (we assert() that this type exists) | 26 | return unknown; |
32 | + * | ||
33 | + * This only allocates the memory and initializes the device state | ||
34 | + * structure, ready for the caller to set properties if they wish. | ||
35 | + * The device still needs to be realized. | ||
36 | + * The returned object has a reference count of 1. | ||
37 | + */ | ||
38 | DeviceState *qdev_new(const char *name); | ||
39 | +/** | ||
40 | + * qdev_try_new: Try to create a device on the heap | ||
41 | + * @name: device type to create | ||
42 | + * | ||
43 | + * This is like qdev_new(), except it returns %NULL when type @name | ||
44 | + * does not exist, rather than asserting. | ||
45 | + */ | ||
46 | DeviceState *qdev_try_new(const char *name); | ||
47 | +/** | ||
48 | + * qdev_realize: Realize @dev. | ||
49 | + * @dev: device to realize | ||
50 | + * @bus: bus to plug it into (may be NULL) | ||
51 | + * @errp: pointer to error object | ||
52 | + * | ||
53 | + * "Realize" the device, i.e. perform the second phase of device | ||
54 | + * initialization. | ||
55 | + * @dev must not be plugged into a bus already. | ||
56 | + * If @bus, plug @dev into @bus. This takes a reference to @dev. | ||
57 | + * If @dev has no QOM parent, make one up, taking another reference. | ||
58 | + * On success, return true. | ||
59 | + * On failure, store an error through @errp and return false. | ||
60 | + * | ||
61 | + * If you created @dev using qdev_new(), you probably want to use | ||
62 | + * qdev_realize_and_unref() instead. | ||
63 | + */ | ||
64 | bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp); | ||
65 | +/** | ||
66 | + * qdev_realize_and_unref: Realize @dev and drop a reference | ||
67 | + * @dev: device to realize | ||
68 | + * @bus: bus to plug it into (may be NULL) | ||
69 | + * @errp: pointer to error object | ||
70 | + * | ||
71 | + * Realize @dev and drop a reference. | ||
72 | + * This is like qdev_realize(), except the caller must hold a | ||
73 | + * (private) reference, which is dropped on return regardless of | ||
74 | + * success or failure. Intended use:: | ||
75 | + * | ||
76 | + * dev = qdev_new(); | ||
77 | + * [...] | ||
78 | + * qdev_realize_and_unref(dev, bus, errp); | ||
79 | + * | ||
80 | + * Now @dev can go away without further ado. | ||
81 | + * | ||
82 | + * If you are embedding the device into some other QOM device and | ||
83 | + * initialized it via some variant on object_initialize_child() then | ||
84 | + * do not use this function, because that family of functions arrange | ||
85 | + * for the only reference to the child device to be held by the parent | ||
86 | + * via the child<> property, and so the reference-count-drop done here | ||
87 | + * would be incorrect. For that use case you want qdev_realize(). | ||
88 | + */ | ||
89 | bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp); | ||
90 | void qdev_unrealize(DeviceState *dev); | ||
91 | void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id, | ||
92 | diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h | ||
93 | index XXXXXXX..XXXXXXX 100644 | ||
94 | --- a/include/hw/qdev-properties.h | ||
95 | +++ b/include/hw/qdev-properties.h | ||
96 | @@ -XXX,XX +XXX,XX @@ void error_set_from_qdev_prop_error(Error **errp, int ret, DeviceState *dev, | ||
97 | */ | ||
98 | void qdev_property_add_static(DeviceState *dev, Property *prop); | ||
99 | |||
100 | +/** | ||
101 | + * qdev_alias_all_properties: Create aliases on source for all target properties | ||
102 | + * @target: Device which has properties to be aliased | ||
103 | + * @source: Object to add alias properties to | ||
104 | + * | ||
105 | + * Add alias properties to the @source object for all qdev properties on | ||
106 | + * the @target DeviceState. | ||
107 | + * | ||
108 | + * This is useful when @target is an internal implementation object | ||
109 | + * owned by @source, and you want to expose all the properties of that | ||
110 | + * implementation object as properties on the @source object so that users | ||
111 | + * of @source can set them. | ||
112 | + */ | ||
113 | void qdev_alias_all_properties(DeviceState *target, Object *source); | ||
114 | |||
115 | /** | ||
116 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | ||
117 | index XXXXXXX..XXXXXXX 100644 | ||
118 | --- a/hw/core/qdev.c | ||
119 | +++ b/hw/core/qdev.c | ||
120 | @@ -XXX,XX +XXX,XX @@ void qdev_set_parent_bus(DeviceState *dev, BusState *bus) | ||
121 | } | 27 | } |
122 | } | 28 | } |
123 | 29 | diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c | |
124 | -/* | 30 | index XXXXXXX..XXXXXXX 100644 |
125 | - * Create a device on the heap. | 31 | --- a/hw/ssi/xilinx_spi.c |
126 | - * A type @name must exist. | 32 | +++ b/hw/ssi/xilinx_spi.c |
127 | - * This only initializes the device state structure and allows | 33 | @@ -XXX,XX +XXX,XX @@ static void xlx_spi_update_irq(XilinxSPI *s) |
128 | - * properties to be set. The device still needs to be realized. See | 34 | irq chain unless things really changed. */ |
129 | - * qdev-core.h. | 35 | if (pending != s->irqline) { |
130 | - */ | 36 | s->irqline = pending; |
131 | DeviceState *qdev_new(const char *name) | 37 | - DB_PRINT("irq_change of state %d ISR:%x IER:%X\n", |
132 | { | 38 | + DB_PRINT("irq_change of state %u ISR:%x IER:%X\n", |
133 | if (!object_class_by_name(name)) { | 39 | pending, s->regs[R_IPISR], s->regs[R_IPIER]); |
134 | @@ -XXX,XX +XXX,XX @@ DeviceState *qdev_new(const char *name) | 40 | qemu_set_irq(s->irq, pending); |
135 | return DEVICE(object_new(name)); | 41 | } |
136 | } | ||
137 | |||
138 | -/* | ||
139 | - * Try to create a device on the heap. | ||
140 | - * This is like qdev_new(), except it returns %NULL when type @name | ||
141 | - * does not exist. | ||
142 | - */ | ||
143 | DeviceState *qdev_try_new(const char *name) | ||
144 | { | ||
145 | if (!module_object_class_by_name(name)) { | ||
146 | @@ -XXX,XX +XXX,XX @@ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev, | ||
147 | qdev_unrealize(dev); | ||
148 | } | ||
149 | |||
150 | -/* | ||
151 | - * Realize @dev. | ||
152 | - * @dev must not be plugged into a bus. | ||
153 | - * If @bus, plug @dev into @bus. This takes a reference to @dev. | ||
154 | - * If @dev has no QOM parent, make one up, taking another reference. | ||
155 | - * On success, return true. | ||
156 | - * On failure, store an error through @errp and return false. | ||
157 | - */ | ||
158 | bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp) | ||
159 | { | ||
160 | assert(!dev->realized && !dev->parent_bus); | ||
161 | @@ -XXX,XX +XXX,XX @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp) | ||
162 | return object_property_set_bool(OBJECT(dev), "realized", true, errp); | ||
163 | } | ||
164 | |||
165 | -/* | ||
166 | - * Realize @dev and drop a reference. | ||
167 | - * This is like qdev_realize(), except the caller must hold a | ||
168 | - * (private) reference, which is dropped on return regardless of | ||
169 | - * success or failure. Intended use: | ||
170 | - * dev = qdev_new(); | ||
171 | - * [...] | ||
172 | - * qdev_realize_and_unref(dev, bus, errp); | ||
173 | - * Now @dev can go away without further ado. | ||
174 | - */ | ||
175 | bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp) | ||
176 | { | ||
177 | bool ret; | ||
178 | @@ -XXX,XX +XXX,XX @@ static void qdev_class_add_property(DeviceClass *klass, Property *prop) | ||
179 | prop->info->description); | ||
180 | } | ||
181 | |||
182 | -/* @qdev_alias_all_properties - Add alias properties to the source object for | ||
183 | - * all qdev properties on the target DeviceState. | ||
184 | - */ | ||
185 | void qdev_alias_all_properties(DeviceState *target, Object *source) | ||
186 | { | ||
187 | ObjectClass *class; | ||
188 | -- | 42 | -- |
189 | 2.20.1 | 43 | 2.20.1 |
190 | 44 | ||
191 | 45 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Xinhao Zhang <zhangxinhao1@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | While we expect KVM to support MTE at some future point, | 3 | Fix code style. Operator needs spaces both sides. |
4 | it certainly won't be ready in time for qemu 5.1. | ||
5 | 4 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com> |
7 | Message-id: 20200713213341.590275-3-richard.henderson@linaro.org | 6 | Signed-off-by: Kai Deng <dengkai1@huawei.com> |
7 | Message-id: 20201103114529.638233-1-zhangxinhao1@huawei.com | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | hw/arm/virt.c | 6 ++++++ | 11 | target/arm/arch_dump.c | 8 ++++---- |
12 | 1 file changed, 6 insertions(+) | 12 | target/arm/arm-semi.c | 8 ++++---- |
13 | target/arm/helper.c | 2 +- | ||
14 | 3 files changed, 9 insertions(+), 9 deletions(-) | ||
13 | 15 | ||
14 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 16 | diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c |
15 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/arm/virt.c | 18 | --- a/target/arm/arch_dump.c |
17 | +++ b/hw/arm/virt.c | 19 | +++ b/target/arm/arch_dump.c |
18 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | 20 | @@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f, |
19 | exit(1); | 21 | |
22 | for (i = 0; i < 32; ++i) { | ||
23 | uint64_t *q = aa64_vfp_qreg(env, i); | ||
24 | - note.vfp.vregs[2*i + 0] = cpu_to_dump64(s, q[0]); | ||
25 | - note.vfp.vregs[2*i + 1] = cpu_to_dump64(s, q[1]); | ||
26 | + note.vfp.vregs[2 * i + 0] = cpu_to_dump64(s, q[0]); | ||
27 | + note.vfp.vregs[2 * i + 1] = cpu_to_dump64(s, q[1]); | ||
20 | } | 28 | } |
21 | 29 | ||
22 | + if (vms->mte && kvm_enabled()) { | 30 | if (s->dump_info.d_endian == ELFDATA2MSB) { |
23 | + error_report("mach-virt: KVM does not support providing " | 31 | @@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f, |
24 | + "MTE to the guest CPU"); | 32 | */ |
25 | + exit(1); | 33 | for (i = 0; i < 32; ++i) { |
26 | + } | 34 | uint64_t tmp = note.vfp.vregs[2*i]; |
27 | + | 35 | - note.vfp.vregs[2*i] = note.vfp.vregs[2*i+1]; |
28 | create_fdt(vms); | 36 | - note.vfp.vregs[2*i+1] = tmp; |
29 | 37 | + note.vfp.vregs[2 * i] = note.vfp.vregs[2 * i + 1]; | |
30 | possible_cpus = mc->possible_cpu_arch_ids(machine); | 38 | + note.vfp.vregs[2 * i + 1] = tmp; |
39 | } | ||
40 | } | ||
41 | |||
42 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/target/arm/arm-semi.c | ||
45 | +++ b/target/arm/arm-semi.c | ||
46 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
47 | if (use_gdb_syscalls()) { | ||
48 | arm_semi_open_guestfd = guestfd; | ||
49 | ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0, | ||
50 | - (int)arg2+1, gdb_open_modeflags[arg1]); | ||
51 | + (int)arg2 + 1, gdb_open_modeflags[arg1]); | ||
52 | } else { | ||
53 | ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644)); | ||
54 | if (ret == (uint32_t)-1) { | ||
55 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
56 | GET_ARG(1); | ||
57 | if (use_gdb_syscalls()) { | ||
58 | ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s", | ||
59 | - arg0, (int)arg1+1); | ||
60 | + arg0, (int)arg1 + 1); | ||
61 | } else { | ||
62 | s = lock_user_string(arg0); | ||
63 | if (!s) { | ||
64 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
65 | GET_ARG(3); | ||
66 | if (use_gdb_syscalls()) { | ||
67 | return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s", | ||
68 | - arg0, (int)arg1+1, arg2, (int)arg3+1); | ||
69 | + arg0, (int)arg1 + 1, arg2, (int)arg3 + 1); | ||
70 | } else { | ||
71 | char *s2; | ||
72 | s = lock_user_string(arg0); | ||
73 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
74 | GET_ARG(1); | ||
75 | if (use_gdb_syscalls()) { | ||
76 | return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s", | ||
77 | - arg0, (int)arg1+1); | ||
78 | + arg0, (int)arg1 + 1); | ||
79 | } else { | ||
80 | s = lock_user_string(arg0); | ||
81 | if (!s) { | ||
82 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
83 | index XXXXXXX..XXXXXXX 100644 | ||
84 | --- a/target/arm/helper.c | ||
85 | +++ b/target/arm/helper.c | ||
86 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | ||
87 | uint32_t sum; | ||
88 | sum = do_usad(a, b); | ||
89 | sum += do_usad(a >> 8, b >> 8); | ||
90 | - sum += do_usad(a >> 16, b >>16); | ||
91 | + sum += do_usad(a >> 16, b >> 16); | ||
92 | sum += do_usad(a >> 24, b >> 24); | ||
93 | return sum; | ||
94 | } | ||
31 | -- | 95 | -- |
32 | 2.20.1 | 96 | 2.20.1 |
33 | 97 | ||
34 | 98 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Xinhao Zhang <zhangxinhao1@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | When MTE is enabled, tag memory must exist for all RAM. | 3 | Fix code style. Don't use '#' flag of printf format ('%#') in |
4 | format strings, use '0x' prefix instead | ||
4 | 5 | ||
5 | It might be possible to simultaneously hot plug tag memory | 6 | Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com> |
6 | alongside the corresponding normal memory, but for now just | 7 | Signed-off-by: Kai Deng <dengkai1@huawei.com> |
7 | disable hotplug. | 8 | Message-id: 20201103114529.638233-2-zhangxinhao1@huawei.com |
8 | |||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20200713213341.590275-4-richard.henderson@linaro.org | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 11 | --- |
14 | hw/arm/virt.c | 5 +++++ | 12 | target/arm/translate-a64.c | 4 ++-- |
15 | 1 file changed, 5 insertions(+) | 13 | 1 file changed, 2 insertions(+), 2 deletions(-) |
16 | 14 | ||
17 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
18 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/arm/virt.c | 17 | --- a/target/arm/translate-a64.c |
20 | +++ b/hw/arm/virt.c | 18 | +++ b/target/arm/translate-a64.c |
21 | @@ -XXX,XX +XXX,XX @@ static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | 19 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) |
22 | return; | 20 | gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); |
21 | break; | ||
22 | default: | ||
23 | - fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", | ||
24 | + fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n", | ||
25 | __func__, insn, fpopcode, s->pc_curr); | ||
26 | g_assert_not_reached(); | ||
27 | } | ||
28 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) | ||
29 | case 0x7f: /* FSQRT (vector) */ | ||
30 | break; | ||
31 | default: | ||
32 | - fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); | ||
33 | + fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop); | ||
34 | g_assert_not_reached(); | ||
23 | } | 35 | } |
24 | 36 | ||
25 | + if (vms->mte) { | ||
26 | + error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); | ||
27 | + return; | ||
28 | + } | ||
29 | + | ||
30 | if (is_nvdimm && !ms->nvdimms_state->is_enabled) { | ||
31 | error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); | ||
32 | return; | ||
33 | -- | 37 | -- |
34 | 2.20.1 | 38 | 2.20.1 |
35 | 39 | ||
36 | 40 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Xinhao Zhang <zhangxinhao1@huawei.com> | ||
1 | 2 | ||
3 | Fix code style. Space required before the open parenthesis '('. | ||
4 | |||
5 | Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com> | ||
6 | Signed-off-by: Kai Deng <dengkai1@huawei.com> | ||
7 | Message-id: 20201103114529.638233-3-zhangxinhao1@huawei.com | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/translate.c | 2 +- | ||
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/translate.c | ||
17 | +++ b/target/arm/translate.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
19 | - Hardware watchpoints. | ||
20 | Hardware breakpoints have already been handled and skip this code. | ||
21 | */ | ||
22 | - switch(dc->base.is_jmp) { | ||
23 | + switch (dc->base.is_jmp) { | ||
24 | case DISAS_NEXT: | ||
25 | case DISAS_TOO_MANY: | ||
26 | gen_goto_tb(dc, 1, dc->base.pc_next); | ||
27 | -- | ||
28 | 2.20.1 | ||
29 | |||
30 | diff view generated by jsdifflib |
1 | Document the arm 'virt' board, which has been undocumented | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | for far too long given that it is the main recommended board | ||
3 | type for arm guests. | ||
4 | 2 | ||
3 | We should at least document what this machine is about. | ||
4 | |||
5 | Reviewed-by: Graeme Gregory <graeme@nuviainc.com> | ||
6 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
7 | Message-id: 20201104165254.24822-1-alex.bennee@linaro.org | ||
8 | Cc: Leif Lindholm <leif@nuviainc.com> | ||
9 | Cc: Shashi Mallela <shashi.mallela@linaro.org> | ||
10 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
11 | [PMM: fixed filename mismatch] | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
7 | Message-id: 20200713175746.5936-5-peter.maydell@linaro.org | ||
8 | --- | 13 | --- |
9 | docs/system/arm/virt.rst | 161 +++++++++++++++++++++++++++++++++++++ | 14 | docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++++++++++++ |
10 | docs/system/target-arm.rst | 1 + | 15 | docs/system/target-arm.rst | 1 + |
11 | MAINTAINERS | 1 + | 16 | 2 files changed, 33 insertions(+) |
12 | 3 files changed, 163 insertions(+) | 17 | create mode 100644 docs/system/arm/sbsa.rst |
13 | create mode 100644 docs/system/arm/virt.rst | ||
14 | 18 | ||
15 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst | 19 | diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst |
16 | new file mode 100644 | 20 | new file mode 100644 |
17 | index XXXXXXX..XXXXXXX | 21 | index XXXXXXX..XXXXXXX |
18 | --- /dev/null | 22 | --- /dev/null |
19 | +++ b/docs/system/arm/virt.rst | 23 | +++ b/docs/system/arm/sbsa.rst |
20 | @@ -XXX,XX +XXX,XX @@ | 24 | @@ -XXX,XX +XXX,XX @@ |
21 | +'virt' generic virtual platform (``virt``) | 25 | +Arm Server Base System Architecture Reference board (``sbsa-ref``) |
22 | +========================================== | 26 | +================================================================== |
23 | + | 27 | + |
24 | +The `virt` board is a platform which does not correspond to any | 28 | +While the `virt` board is a generic board platform that doesn't match |
25 | +real hardware; it is designed for use in virtual machines. | 29 | +any real hardware the `sbsa-ref` board intends to look like real |
26 | +It is the recommended board type if you simply want to run | 30 | +hardware. The `Server Base System Architecture |
27 | +a guest such as Linux and do not care about reproducing the | 31 | +<https://developer.arm.com/documentation/den0029/latest>` defines a |
28 | +idiosyncrasies and limitations of a particular bit of real-world | 32 | +minimum base line of hardware support and importantly how the firmware |
29 | +hardware. | 33 | +reports that to any operating system. It is a static system that |
34 | +reports a very minimal DT to the firmware for non-discoverable | ||
35 | +information about components affected by the qemu command line (i.e. | ||
36 | +cpus and memory). As a result it must have a firmware specifically | ||
37 | +built to expect a certain hardware layout (as you would in a real | ||
38 | +machine). | ||
30 | + | 39 | + |
31 | +This is a "versioned" board model, so as well as the ``virt`` machine | 40 | +It is intended to be a machine for developing firmware and testing |
32 | +type itself (which may have improvements, bugfixes and other minor | 41 | +standards compliance with operating systems. |
33 | +changes between QEMU versions) a version is provided that guarantees | ||
34 | +to have the same behaviour as that of previous QEMU releases, so | ||
35 | +that VM migration will work between QEMU versions. For instance the | ||
36 | +``virt-5.0`` machine type will behave like the ``virt`` machine from | ||
37 | +the QEMU 5.0 release, and migration should work between ``virt-5.0`` | ||
38 | +of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration | ||
39 | +is not guaranteed to work between different QEMU releases for | ||
40 | +the non-versioned ``virt`` machine type. | ||
41 | + | 42 | + |
42 | +Supported devices | 43 | +Supported devices |
43 | +""""""""""""""""" | 44 | +""""""""""""""""" |
44 | + | 45 | + |
45 | +The virt board supports: | 46 | +The sbsa-ref board supports: |
46 | + | 47 | + |
47 | +- PCI/PCIe devices | 48 | + - A configurable number of AArch64 CPUs |
48 | +- Flash memory | 49 | + - GIC version 3 |
49 | +- One PL011 UART | 50 | + - System bus AHCI controller |
50 | +- An RTC | 51 | + - System bus EHCI controller |
51 | +- The fw_cfg device that allows a guest to obtain data from QEMU | 52 | + - CDROM and hard disc on AHCI bus |
52 | +- A PL061 GPIO controller | 53 | + - E1000E ethernet card on PCIe bus |
53 | +- An optional SMMUv3 IOMMU | 54 | + - VGA display adaptor on PCIe bus |
54 | +- hotpluggable DIMMs | 55 | + - A generic SBSA watchdog device |
55 | +- hotpluggable NVDIMMs | ||
56 | +- An MSI controller (GICv2M or ITS). GICv2M is selected by default along | ||
57 | + with GICv2. ITS is selected by default with GICv3 (>= virt-2.7). Note | ||
58 | + that ITS is not modeled in TCG mode. | ||
59 | +- 32 virtio-mmio transport devices | ||
60 | +- running guests using the KVM accelerator on aarch64 hardware | ||
61 | +- large amounts of RAM (at least 255GB, and more if using highmem) | ||
62 | +- many CPUs (up to 512 if using a GICv3 and highmem) | ||
63 | +- Secure-World-only devices if the CPU has TrustZone: | ||
64 | + | 56 | + |
65 | + - A second PL011 UART | ||
66 | + - A secure flash memory | ||
67 | + - 16MB of secure RAM | ||
68 | + | ||
69 | +Supported guest CPU types: | ||
70 | + | ||
71 | +- ``cortex-a7`` (32-bit) | ||
72 | +- ``cortex-a15`` (32-bit; the default) | ||
73 | +- ``cortex-a53`` (64-bit) | ||
74 | +- ``cortex-a57`` (64-bit) | ||
75 | +- ``cortex-a72`` (64-bit) | ||
76 | +- ``host`` (with KVM only) | ||
77 | +- ``max`` (same as ``host`` for KVM; best possible emulation with TCG) | ||
78 | + | ||
79 | +Note that the default is ``cortex-a15``, so for an AArch64 guest you must | ||
80 | +specify a CPU type. | ||
81 | + | ||
82 | +Graphics output is available, but unlike the x86 PC machine types | ||
83 | +there is no default display device enabled: you should select one from | ||
84 | +the Display devices section of "-device help". The recommended option | ||
85 | +is ``virtio-gpu-pci``; this is the only one which will work correctly | ||
86 | +with KVM. You may also need to ensure your guest kernel is configured | ||
87 | +with support for this; see below. | ||
88 | + | ||
89 | +Machine-specific options | ||
90 | +"""""""""""""""""""""""" | ||
91 | + | ||
92 | +The following machine-specific options are supported: | ||
93 | + | ||
94 | +secure | ||
95 | + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the | ||
96 | + Arm Security Extensions (TrustZone). The default is ``off``. | ||
97 | + | ||
98 | +virtualization | ||
99 | + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the | ||
100 | + Arm Virtualization Extensions. The default is ``off``. | ||
101 | + | ||
102 | +highmem | ||
103 | + Set ``on``/``off`` to enable/disable placing devices and RAM in physical | ||
104 | + address space above 32 bits. The default is ``on`` for machine types | ||
105 | + later than ``virt-2.12``. | ||
106 | + | ||
107 | +gic-version | ||
108 | + Specify the version of the Generic Interrupt Controller (GIC) to provide. | ||
109 | + Valid values are: | ||
110 | + | ||
111 | + ``2`` | ||
112 | + GICv2 | ||
113 | + ``3`` | ||
114 | + GICv3 | ||
115 | + ``host`` | ||
116 | + Use the same GIC version the host provides, when using KVM | ||
117 | + ``max`` | ||
118 | + Use the best GIC version possible (same as host when using KVM; | ||
119 | + currently same as ``3``` for TCG, but this may change in future) | ||
120 | + | ||
121 | +its | ||
122 | + Set ``on``/``off`` to enable/disable ITS instantiation. The default is ``on`` | ||
123 | + for machine types later than ``virt-2.7``. | ||
124 | + | ||
125 | +iommu | ||
126 | + Set the IOMMU type to create for the guest. Valid values are: | ||
127 | + | ||
128 | + ``none`` | ||
129 | + Don't create an IOMMU (the default) | ||
130 | + ``smmuv3`` | ||
131 | + Create an SMMUv3 | ||
132 | + | ||
133 | +ras | ||
134 | + Set ``on``/``off`` to enable/disable reporting host memory errors to a guest | ||
135 | + using ACPI and guest external abort exceptions. The default is off. | ||
136 | + | ||
137 | +Linux guest kernel configuration | ||
138 | +"""""""""""""""""""""""""""""""" | ||
139 | + | ||
140 | +The 'defconfig' for Linux arm and arm64 kernels should include the | ||
141 | +right device drivers for virtio and the PCI controller; however some older | ||
142 | +kernel versions, especially for 32-bit Arm, did not have everything | ||
143 | +enabled by default. If you're not seeing PCI devices that you expect, | ||
144 | +then check that your guest config has:: | ||
145 | + | ||
146 | + CONFIG_PCI=y | ||
147 | + CONFIG_VIRTIO_PCI=y | ||
148 | + CONFIG_PCI_HOST_GENERIC=y | ||
149 | + | ||
150 | +If you want to use the ``virtio-gpu-pci`` graphics device you will also | ||
151 | +need:: | ||
152 | + | ||
153 | + CONFIG_DRM=y | ||
154 | + CONFIG_DRM_VIRTIO_GPU=y | ||
155 | + | ||
156 | +Hardware configuration information for bare-metal programming | ||
157 | +""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" | ||
158 | + | ||
159 | +The ``virt`` board automatically generates a device tree blob ("dtb") | ||
160 | +which it passes to the guest. This provides information about the | ||
161 | +addresses, interrupt lines and other configuration of the various devices | ||
162 | +in the system. Guest code can rely on and hard-code the following | ||
163 | +addresses: | ||
164 | + | ||
165 | +- Flash memory starts at address 0x0000_0000 | ||
166 | + | ||
167 | +- RAM starts at 0x4000_0000 | ||
168 | + | ||
169 | +All other information about device locations may change between | ||
170 | +QEMU versions, so guest code must look in the DTB. | ||
171 | + | ||
172 | +QEMU supports two types of guest image boot for ``virt``, and | ||
173 | +the way for the guest code to locate the dtb binary differs: | ||
174 | + | ||
175 | +- For guests using the Linux kernel boot protocol (this means any | ||
176 | + non-ELF file passed to the QEMU ``-kernel`` option) the address | ||
177 | + of the DTB is passed in a register (``r2`` for 32-bit guests, | ||
178 | + or ``x0`` for 64-bit guests) | ||
179 | + | ||
180 | +- For guests booting as "bare-metal" (any other kind of boot), | ||
181 | + the DTB is at the start of RAM (0x4000_0000) | ||
182 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | 57 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst |
183 | index XXXXXXX..XXXXXXX 100644 | 58 | index XXXXXXX..XXXXXXX 100644 |
184 | --- a/docs/system/target-arm.rst | 59 | --- a/docs/system/target-arm.rst |
185 | +++ b/docs/system/target-arm.rst | 60 | +++ b/docs/system/target-arm.rst |
186 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | 61 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running |
187 | arm/collie | 62 | arm/mps2 |
188 | arm/sx1 | 63 | arm/musca |
189 | arm/stellaris | 64 | arm/realview |
190 | + arm/virt | 65 | + arm/sbsa |
191 | 66 | arm/versatile | |
192 | Arm CPU features | 67 | arm/vexpress |
193 | ================ | 68 | arm/aspeed |
194 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
195 | index XXXXXXX..XXXXXXX 100644 | ||
196 | --- a/MAINTAINERS | ||
197 | +++ b/MAINTAINERS | ||
198 | @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org | ||
199 | S: Maintained | ||
200 | F: hw/arm/virt* | ||
201 | F: include/hw/arm/virt.h | ||
202 | +F: docs/system/arm/virt.rst | ||
203 | |||
204 | Xilinx Zynq | ||
205 | M: Edgar E. Iglesias <edgar.iglesias@gmail.com> | ||
206 | -- | 69 | -- |
207 | 2.20.1 | 70 | 2.20.1 |
208 | 71 | ||
209 | 72 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
1 | 2 | ||
3 | When using a Cortex-A15, the Virt machine does not use any | ||
4 | MPCore peripherals. Remove the dependency. | ||
5 | |||
6 | Fixes: 7951c7b7c05 ("hw/arm: Express dependencies of the virt machine with Kconfig") | ||
7 | Reported-by: Miroslav Rezanina <mrezanin@redhat.com> | ||
8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
9 | Message-id: 20201107114852.271922-1-philmd@redhat.com | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | hw/arm/Kconfig | 1 - | ||
14 | 1 file changed, 1 deletion(-) | ||
15 | |||
16 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/hw/arm/Kconfig | ||
19 | +++ b/hw/arm/Kconfig | ||
20 | @@ -XXX,XX +XXX,XX @@ config ARM_VIRT | ||
21 | imply VFIO_PLATFORM | ||
22 | imply VFIO_XGMAC | ||
23 | imply TPM_TIS_SYSBUS | ||
24 | - select A15MPCORE | ||
25 | select ACPI | ||
26 | select ARM_SMMUV3 | ||
27 | select GPIO_KEY | ||
28 | -- | ||
29 | 2.20.1 | ||
30 | |||
31 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Control this cpu feature via a machine property, much as we do | 3 | The helper function did not get updated when we reorganized |
4 | with secure=on, since both require specialized support in the | 4 | the vector register file for SVE. Since then, the neon dregs |
5 | machine setup to be functional. | 5 | are non-sequential and cannot be simply indexed. |
6 | 6 | ||
7 | Default MTE to off, since this feature implies extra overhead. | 7 | At the same time, make the helper function operate on 64-bit |
8 | quantities so that we do not have to call it twice. | ||
8 | 9 | ||
10 | Fixes: c39c2b9043e | ||
11 | Reported-by: Ard Biesheuvel <ardb@kernel.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20200713213341.590275-2-richard.henderson@linaro.org | 13 | [PMM: use aa32_vfp_dreg() rather than opencoding] |
14 | Message-id: 20201105171126.88014-1-richard.henderson@linaro.org | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 17 | --- |
14 | include/hw/arm/virt.h | 1 + | 18 | target/arm/helper.h | 2 +- |
15 | hw/arm/virt.c | 39 ++++++++++++++++++++++++++++++++++----- | 19 | target/arm/op_helper.c | 23 +++++++++-------- |
16 | target/arm/cpu.c | 19 +++++++++++-------- | 20 | target/arm/translate-neon.c.inc | 44 +++++++++++---------------------- |
17 | target/arm/cpu64.c | 5 +++-- | 21 | 3 files changed, 29 insertions(+), 40 deletions(-) |
18 | 4 files changed, 49 insertions(+), 15 deletions(-) | ||
19 | 22 | ||
20 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h | 23 | diff --git a/target/arm/helper.h b/target/arm/helper.h |
21 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/include/hw/arm/virt.h | 25 | --- a/target/arm/helper.h |
23 | +++ b/include/hw/arm/virt.h | 26 | +++ b/target/arm/helper.h |
24 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 27 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr) |
25 | bool its; | 28 | DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr) |
26 | bool virt; | 29 | DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32) |
27 | bool ras; | 30 | DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32) |
28 | + bool mte; | 31 | -DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32) |
29 | OnOffAuto acpi; | 32 | +DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64) |
30 | VirtGICType gic_version; | 33 | |
31 | VirtIOMMUType iommu; | 34 | DEF_HELPER_3(shl_cc, i32, env, i32, i32) |
32 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 35 | DEF_HELPER_3(shr_cc, i32, env, i32, i32) |
36 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | 37 | index XXXXXXX..XXXXXXX 100644 |
34 | --- a/hw/arm/virt.c | 38 | --- a/target/arm/op_helper.c |
35 | +++ b/hw/arm/virt.c | 39 | +++ b/target/arm/op_helper.c |
36 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | 40 | @@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, |
37 | OBJECT(secure_sysmem), &error_abort); | 41 | cpu_loop_exit_restore(cs, ra); |
42 | } | ||
43 | |||
44 | -uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn, | ||
45 | - uint32_t maxindex) | ||
46 | +uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc, | ||
47 | + uint64_t ireg, uint64_t def) | ||
48 | { | ||
49 | - uint32_t val, shift; | ||
50 | - uint64_t *table = vn; | ||
51 | + uint64_t tmp, val = 0; | ||
52 | + uint32_t maxindex = ((desc & 3) + 1) * 8; | ||
53 | + uint32_t base_reg = desc >> 2; | ||
54 | + uint32_t shift, index, reg; | ||
55 | |||
56 | - val = 0; | ||
57 | - for (shift = 0; shift < 32; shift += 8) { | ||
58 | - uint32_t index = (ireg >> shift) & 0xff; | ||
59 | + for (shift = 0; shift < 64; shift += 8) { | ||
60 | + index = (ireg >> shift) & 0xff; | ||
61 | if (index < maxindex) { | ||
62 | - uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff; | ||
63 | - val |= tmp << shift; | ||
64 | + reg = base_reg + (index >> 3); | ||
65 | + tmp = *aa32_vfp_dreg(env, reg); | ||
66 | + tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift; | ||
67 | } else { | ||
68 | - val |= def & (0xff << shift); | ||
69 | + tmp = def & (0xffull << shift); | ||
38 | } | 70 | } |
39 | 71 | + val |= tmp; | |
40 | - /* | 72 | } |
41 | - * The cpu adds the property if and only if MemTag is supported. | 73 | return val; |
42 | - * If it is, we must allocate the ram to back that up. | 74 | } |
43 | - */ | 75 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc |
44 | - if (object_property_find(cpuobj, "tag-memory", NULL)) { | 76 | index XXXXXXX..XXXXXXX 100644 |
45 | + if (vms->mte) { | 77 | --- a/target/arm/translate-neon.c.inc |
46 | + /* Create the memory region only once, but link to all cpus. */ | 78 | +++ b/target/arm/translate-neon.c.inc |
47 | if (!tag_sysmem) { | 79 | @@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) |
48 | + /* | 80 | |
49 | + * The property exists only if MemTag is supported. | 81 | static bool trans_VTBL(DisasContext *s, arg_VTBL *a) |
50 | + * If it is, we must allocate the ram to back that up. | 82 | { |
51 | + */ | 83 | - int n; |
52 | + if (!object_property_find(cpuobj, "tag-memory", NULL)) { | 84 | - TCGv_i32 tmp, tmp2, tmp3, tmp4; |
53 | + error_report("MTE requested, but not supported " | 85 | - TCGv_ptr ptr1; |
54 | + "by the guest CPU"); | 86 | + TCGv_i64 val, def; |
55 | + exit(1); | 87 | + TCGv_i32 desc; |
56 | + } | 88 | |
89 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
90 | return false; | ||
91 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
92 | return true; | ||
93 | } | ||
94 | |||
95 | - n = a->len + 1; | ||
96 | - if ((a->vn + n) > 32) { | ||
97 | + if ((a->vn + a->len + 1) > 32) { | ||
98 | /* | ||
99 | * This is UNPREDICTABLE; we choose to UNDEF to avoid the | ||
100 | * helper function running off the end of the register file. | ||
101 | */ | ||
102 | return false; | ||
103 | } | ||
104 | - n <<= 3; | ||
105 | - tmp = tcg_temp_new_i32(); | ||
106 | - if (a->op) { | ||
107 | - read_neon_element32(tmp, a->vd, 0, MO_32); | ||
108 | - } else { | ||
109 | - tcg_gen_movi_i32(tmp, 0); | ||
110 | - } | ||
111 | - tmp2 = tcg_temp_new_i32(); | ||
112 | - read_neon_element32(tmp2, a->vm, 0, MO_32); | ||
113 | - ptr1 = vfp_reg_ptr(true, a->vn); | ||
114 | - tmp4 = tcg_const_i32(n); | ||
115 | - gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4); | ||
116 | |||
117 | + desc = tcg_const_i32((a->vn << 2) | a->len); | ||
118 | + def = tcg_temp_new_i64(); | ||
119 | if (a->op) { | ||
120 | - read_neon_element32(tmp, a->vd, 1, MO_32); | ||
121 | + read_neon_element64(def, a->vd, 0, MO_64); | ||
122 | } else { | ||
123 | - tcg_gen_movi_i32(tmp, 0); | ||
124 | + tcg_gen_movi_i64(def, 0); | ||
125 | } | ||
126 | - tmp3 = tcg_temp_new_i32(); | ||
127 | - read_neon_element32(tmp3, a->vm, 1, MO_32); | ||
128 | - gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4); | ||
129 | - tcg_temp_free_i32(tmp); | ||
130 | - tcg_temp_free_i32(tmp4); | ||
131 | - tcg_temp_free_ptr(ptr1); | ||
132 | + val = tcg_temp_new_i64(); | ||
133 | + read_neon_element64(val, a->vm, 0, MO_64); | ||
134 | |||
135 | - write_neon_element32(tmp2, a->vd, 0, MO_32); | ||
136 | - write_neon_element32(tmp3, a->vd, 1, MO_32); | ||
137 | - tcg_temp_free_i32(tmp2); | ||
138 | - tcg_temp_free_i32(tmp3); | ||
139 | + gen_helper_neon_tbl(val, cpu_env, desc, val, def); | ||
140 | + write_neon_element64(val, a->vd, 0, MO_64); | ||
57 | + | 141 | + |
58 | tag_sysmem = g_new(MemoryRegion, 1); | 142 | + tcg_temp_free_i64(def); |
59 | memory_region_init(tag_sysmem, OBJECT(machine), | 143 | + tcg_temp_free_i64(val); |
60 | "tag-memory", UINT64_MAX / 32); | 144 | + tcg_temp_free_i32(desc); |
61 | @@ -XXX,XX +XXX,XX @@ static void virt_set_ras(Object *obj, bool value, Error **errp) | 145 | return true; |
62 | vms->ras = value; | ||
63 | } | 146 | } |
64 | 147 | ||
65 | +static bool virt_get_mte(Object *obj, Error **errp) | ||
66 | +{ | ||
67 | + VirtMachineState *vms = VIRT_MACHINE(obj); | ||
68 | + | ||
69 | + return vms->mte; | ||
70 | +} | ||
71 | + | ||
72 | +static void virt_set_mte(Object *obj, bool value, Error **errp) | ||
73 | +{ | ||
74 | + VirtMachineState *vms = VIRT_MACHINE(obj); | ||
75 | + | ||
76 | + vms->mte = value; | ||
77 | +} | ||
78 | + | ||
79 | static char *virt_get_gic_version(Object *obj, Error **errp) | ||
80 | { | ||
81 | VirtMachineState *vms = VIRT_MACHINE(obj); | ||
82 | @@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj) | ||
83 | "Set on/off to enable/disable reporting host memory errors " | ||
84 | "to a KVM guest using ACPI and guest external abort exceptions"); | ||
85 | |||
86 | + /* MTE is disabled by default. */ | ||
87 | + vms->mte = false; | ||
88 | + object_property_add_bool(obj, "mte", virt_get_mte, virt_set_mte); | ||
89 | + object_property_set_description(obj, "mte", | ||
90 | + "Set on/off to enable/disable emulating a " | ||
91 | + "guest CPU which implements the ARM " | ||
92 | + "Memory Tagging Extension"); | ||
93 | + | ||
94 | vms->irqmap = a15irqmap; | ||
95 | |||
96 | virt_flash_create(vms); | ||
97 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
98 | index XXXXXXX..XXXXXXX 100644 | ||
99 | --- a/target/arm/cpu.c | ||
100 | +++ b/target/arm/cpu.c | ||
101 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
102 | cpu->id_pfr1 &= ~0xf000; | ||
103 | } | ||
104 | |||
105 | +#ifndef CONFIG_USER_ONLY | ||
106 | + if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { | ||
107 | + /* | ||
108 | + * Disable the MTE feature bits if we do not have tag-memory | ||
109 | + * provided by the machine. | ||
110 | + */ | ||
111 | + cpu->isar.id_aa64pfr1 = | ||
112 | + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); | ||
113 | + } | ||
114 | +#endif | ||
115 | + | ||
116 | /* MPU can be configured out of a PMSA CPU either by setting has-mpu | ||
117 | * to false or by setting pmsav7-dregion to 0. | ||
118 | */ | ||
119 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
120 | cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", | ||
121 | cpu->secure_tag_memory); | ||
122 | } | ||
123 | - } else if (cpu_isar_feature(aa64_mte, cpu)) { | ||
124 | - /* | ||
125 | - * Since there is no tag memory, we can't meaningfully support MTE | ||
126 | - * to its fullest. To avoid problems later, when we would come to | ||
127 | - * use the tag memory, downgrade support to insns only. | ||
128 | - */ | ||
129 | - cpu->isar.id_aa64pfr1 = | ||
130 | - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); | ||
131 | } | ||
132 | |||
133 | cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); | ||
134 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
135 | index XXXXXXX..XXXXXXX 100644 | ||
136 | --- a/target/arm/cpu64.c | ||
137 | +++ b/target/arm/cpu64.c | ||
138 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
139 | t = cpu->isar.id_aa64pfr1; | ||
140 | t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); | ||
141 | /* | ||
142 | - * Begin with full support for MTE; will be downgraded to MTE=1 | ||
143 | - * during realize if the board provides no tag memory. | ||
144 | + * Begin with full support for MTE. This will be downgraded to MTE=0 | ||
145 | + * during realize if the board provides no tag memory, much like | ||
146 | + * we do for EL2 with the virtualization=on property. | ||
147 | */ | ||
148 | t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); | ||
149 | cpu->isar.id_aa64pfr1 = t; | ||
150 | -- | 148 | -- |
151 | 2.20.1 | 149 | 2.20.1 |
152 | 150 | ||
153 | 151 | diff view generated by jsdifflib |
1 | In armsse_realize() we have a loop over [0, info->num_cpus), which | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | indexes into various fixed-size arrays in the ARMSSE struct. This | ||
3 | confuses Coverity, which warns that we might overrun those arrays | ||
4 | (CID 1430326, 1430337, 1430371, 1430414, 1430430). This can't | ||
5 | actually happen, because the info struct is always one of the entries | ||
6 | in the armsse_variants[] array and num_cpus is either 1 or 2; we also | ||
7 | already assert in armsse_init() that num_cpus is not too large. | ||
8 | However, adding an assert to armsse_realize() like the one in | ||
9 | armsse_init() should help Coverity figure out that these code paths | ||
10 | aren't possible. | ||
11 | 2 | ||
3 | We can use one MPC per SRAM bank, but we currently only wire the | ||
4 | IRQ from the first expansion MPC to the IRQ splitter. Fix that. | ||
5 | |||
6 | Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines") | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Message-id: 20201107193403.436146-2-f4bug@amsat.org | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
14 | Message-id: 20200713143716.9881-1-peter.maydell@linaro.org | ||
15 | --- | 11 | --- |
16 | hw/arm/armsse.c | 2 ++ | 12 | hw/arm/armsse.c | 3 ++- |
17 | 1 file changed, 2 insertions(+) | 13 | 1 file changed, 2 insertions(+), 1 deletion(-) |
18 | 14 | ||
19 | diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c | 15 | diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c |
20 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/arm/armsse.c | 17 | --- a/hw/arm/armsse.c |
22 | +++ b/hw/arm/armsse.c | 18 | +++ b/hw/arm/armsse.c |
23 | @@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp) | 19 | @@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp) |
24 | return; | 20 | qdev_get_gpio_in(dev_splitter, 0)); |
25 | } | 21 | qdev_connect_gpio_out(dev_splitter, 0, |
26 | 22 | qdev_get_gpio_in_named(dev_secctl, | |
27 | + assert(info->num_cpus <= SSE_MAX_CPUS); | 23 | - "mpc_status", 0)); |
28 | + | 24 | + "mpc_status", |
29 | /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ | 25 | + i - IOTS_NUM_EXP_MPC)); |
30 | assert(is_power_of_2(info->sram_banks)); | 26 | } |
31 | addr_width_max = 24 - ctz32(info->sram_banks); | 27 | |
28 | qdev_connect_gpio_out(dev_splitter, 1, | ||
32 | -- | 29 | -- |
33 | 2.20.1 | 30 | 2.20.1 |
34 | 31 | ||
35 | 32 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
1 | 2 | ||
3 | The system configuration controller (SYSCFG) doesn't have | ||
4 | any output IRQ (and the INTC input #71 belongs to the UART6). | ||
5 | Remove the invalid code. | ||
6 | |||
7 | Fixes: db635521a02 ("stm32f205: Add the stm32f205 SoC") | ||
8 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Message-id: 20201107193403.436146-3-f4bug@amsat.org | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | include/hw/misc/stm32f2xx_syscfg.h | 2 -- | ||
14 | hw/arm/stm32f205_soc.c | 1 - | ||
15 | hw/misc/stm32f2xx_syscfg.c | 2 -- | ||
16 | 3 files changed, 5 deletions(-) | ||
17 | |||
18 | diff --git a/include/hw/misc/stm32f2xx_syscfg.h b/include/hw/misc/stm32f2xx_syscfg.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/misc/stm32f2xx_syscfg.h | ||
21 | +++ b/include/hw/misc/stm32f2xx_syscfg.h | ||
22 | @@ -XXX,XX +XXX,XX @@ struct STM32F2XXSyscfgState { | ||
23 | uint32_t syscfg_exticr3; | ||
24 | uint32_t syscfg_exticr4; | ||
25 | uint32_t syscfg_cmpcr; | ||
26 | - | ||
27 | - qemu_irq irq; | ||
28 | }; | ||
29 | |||
30 | #endif /* HW_STM32F2XX_SYSCFG_H */ | ||
31 | diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/hw/arm/stm32f205_soc.c | ||
34 | +++ b/hw/arm/stm32f205_soc.c | ||
35 | @@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) | ||
36 | } | ||
37 | busdev = SYS_BUS_DEVICE(dev); | ||
38 | sysbus_mmio_map(busdev, 0, 0x40013800); | ||
39 | - sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71)); | ||
40 | |||
41 | /* Attach UART (uses USART registers) and USART controllers */ | ||
42 | for (i = 0; i < STM_NUM_USARTS; i++) { | ||
43 | diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/hw/misc/stm32f2xx_syscfg.c | ||
46 | +++ b/hw/misc/stm32f2xx_syscfg.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static void stm32f2xx_syscfg_init(Object *obj) | ||
48 | { | ||
49 | STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj); | ||
50 | |||
51 | - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); | ||
52 | - | ||
53 | memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s, | ||
54 | TYPE_STM32F2XX_SYSCFG, 0x400); | ||
55 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); | ||
56 | -- | ||
57 | 2.20.1 | ||
58 | |||
59 | diff view generated by jsdifflib |
1 | Add skeletal documentation of the gumstix boards | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | ('connex' and 'verdex'). | ||
3 | 2 | ||
3 | omap2420_mpu_init() introduced in commit 827df9f3c5f ("Add basic | ||
4 | OMAP2 chip support") takes care of creating the 3 UARTs. | ||
5 | |||
6 | Then commit 58a26b477e9 ("Emulate a serial bluetooth HCI with H4+ | ||
7 | extensions and attach to n8x0's UART") added n8x0_uart_setup() | ||
8 | which create the UART and connects it to an IRQ output, | ||
9 | overwritting the existing peripheral and its IRQ connection. | ||
10 | This is incorrect. | ||
11 | |||
12 | Fortunately we don't need to fix this, because commit 6da68df7f9b | ||
13 | ("hw/arm/nseries: Replace the bluetooth chardev with a "null" | ||
14 | chardev") removed the use of this peripheral. We can simply | ||
15 | remove the code. | ||
16 | |||
17 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
18 | Message-id: 20201107193403.436146-4-f4bug@amsat.org | ||
19 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
7 | Message-id: 20200713175746.5936-4-peter.maydell@linaro.org | ||
8 | --- | 21 | --- |
9 | docs/system/arm/gumstix.rst | 21 +++++++++++++++++++++ | 22 | hw/arm/nseries.c | 11 ----------- |
10 | docs/system/target-arm.rst | 1 + | 23 | 1 file changed, 11 deletions(-) |
11 | MAINTAINERS | 1 + | ||
12 | 3 files changed, 23 insertions(+) | ||
13 | create mode 100644 docs/system/arm/gumstix.rst | ||
14 | 24 | ||
15 | diff --git a/docs/system/arm/gumstix.rst b/docs/system/arm/gumstix.rst | 25 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c |
16 | new file mode 100644 | ||
17 | index XXXXXXX..XXXXXXX | ||
18 | --- /dev/null | ||
19 | +++ b/docs/system/arm/gumstix.rst | ||
20 | @@ -XXX,XX +XXX,XX @@ | ||
21 | +Gumstix Connex and Verdex (``connex``, ``verdex``) | ||
22 | +================================================== | ||
23 | + | ||
24 | +These machines model the Gumstix Connex and Verdex boards. | ||
25 | +The Connex has a PXA255 CPU and the Verdex has a PXA270. | ||
26 | + | ||
27 | +Implemented devices: | ||
28 | + | ||
29 | + * NOR flash | ||
30 | + * SMC91C111 ethernet | ||
31 | + * Interrupt controller | ||
32 | + * DMA | ||
33 | + * Timer | ||
34 | + * GPIO | ||
35 | + * MMC/SD card | ||
36 | + * Fast infra-red communications port (FIR) | ||
37 | + * LCD controller | ||
38 | + * Synchronous serial ports (SPI) | ||
39 | + * PCMCIA interface | ||
40 | + * I2C | ||
41 | + * I2S | ||
42 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
43 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
44 | --- a/docs/system/target-arm.rst | 27 | --- a/hw/arm/nseries.c |
45 | +++ b/docs/system/target-arm.rst | 28 | +++ b/hw/arm/nseries.c |
46 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | 29 | @@ -XXX,XX +XXX,XX @@ static void n8x0_cbus_setup(struct n800_s *s) |
47 | arm/aspeed | 30 | cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1)); |
48 | arm/digic | 31 | } |
49 | arm/musicpal | 32 | |
50 | + arm/gumstix | 33 | -static void n8x0_uart_setup(struct n800_s *s) |
51 | arm/nseries | 34 | -{ |
52 | arm/orangepi | 35 | - Chardev *radio = qemu_chr_new("bt-dummy-uart", "null", NULL); |
53 | arm/palm | 36 | - /* |
54 | diff --git a/MAINTAINERS b/MAINTAINERS | 37 | - * Note: We used to connect N8X0_BT_RESET_GPIO and N8X0_BT_WKUP_GPIO |
55 | index XXXXXXX..XXXXXXX 100644 | 38 | - * here, but this code has been removed with the bluetooth backend. |
56 | --- a/MAINTAINERS | 39 | - */ |
57 | +++ b/MAINTAINERS | 40 | - omap_uart_attach(s->mpu->uart[BT_UART], radio); |
58 | @@ -XXX,XX +XXX,XX @@ R: Philippe Mathieu-Daudé <f4bug@amsat.org> | 41 | -} |
59 | L: qemu-arm@nongnu.org | 42 | - |
60 | S: Odd Fixes | 43 | static void n8x0_usb_setup(struct n800_s *s) |
61 | F: hw/arm/gumstix.c | 44 | { |
62 | +F: docs/system/arm/gumstix.rst | 45 | SysBusDevice *dev; |
63 | 46 | @@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine, | |
64 | i.MX25 PDK | 47 | n8x0_spi_setup(s); |
65 | M: Peter Maydell <peter.maydell@linaro.org> | 48 | n8x0_dss_setup(s); |
49 | n8x0_cbus_setup(s); | ||
50 | - n8x0_uart_setup(s); | ||
51 | if (machine_usb(machine)) { | ||
52 | n8x0_usb_setup(s); | ||
53 | } | ||
66 | -- | 54 | -- |
67 | 2.20.1 | 55 | 2.20.1 |
68 | 56 | ||
69 | 57 | diff view generated by jsdifflib |
1 | Add skeletal documentation of the collie board. | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | The MusicPal board code connects both of the IRQ outputs of the UART | ||
4 | to the same INTC qemu_irq. Connecting two qemu_irqs outputs directly | ||
5 | to the same input is not valid as it produces subtly wrong behaviour | ||
6 | (for instance if both the IRQ lines are high, and then one goes | ||
7 | low, the INTC input will see this as a high-to-low transition | ||
8 | even though the second IRQ line should still be holding it high). | ||
9 | |||
10 | This kind of wiring needs an explicitly created OR gate; add one. | ||
11 | |||
12 | Inspired-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
14 | Message-id: 20201107193403.436146-5-f4bug@amsat.org | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
6 | Message-id: 20200713175746.5936-3-peter.maydell@linaro.org | ||
7 | --- | 17 | --- |
8 | docs/system/arm/collie.rst | 16 ++++++++++++++++ | 18 | hw/arm/musicpal.c | 17 +++++++++++++---- |
9 | docs/system/target-arm.rst | 1 + | 19 | hw/arm/Kconfig | 1 + |
10 | MAINTAINERS | 1 + | 20 | 2 files changed, 14 insertions(+), 4 deletions(-) |
11 | 3 files changed, 18 insertions(+) | ||
12 | create mode 100644 docs/system/arm/collie.rst | ||
13 | 21 | ||
14 | diff --git a/docs/system/arm/collie.rst b/docs/system/arm/collie.rst | 22 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c |
15 | new file mode 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
16 | index XXXXXXX..XXXXXXX | 24 | --- a/hw/arm/musicpal.c |
17 | --- /dev/null | 25 | +++ b/hw/arm/musicpal.c |
18 | +++ b/docs/system/arm/collie.rst | ||
19 | @@ -XXX,XX +XXX,XX @@ | 26 | @@ -XXX,XX +XXX,XX @@ |
20 | +Sharp Zaurus SL-5500 (``collie``) | 27 | #include "ui/console.h" |
21 | +================================= | 28 | #include "hw/i2c/i2c.h" |
29 | #include "hw/irq.h" | ||
30 | +#include "hw/or-irq.h" | ||
31 | #include "hw/audio/wm8750.h" | ||
32 | #include "sysemu/block-backend.h" | ||
33 | #include "sysemu/runstate.h" | ||
34 | @@ -XXX,XX +XXX,XX @@ | ||
35 | #define MP_TIMER4_IRQ 7 | ||
36 | #define MP_EHCI_IRQ 8 | ||
37 | #define MP_ETH_IRQ 9 | ||
38 | -#define MP_UART1_IRQ 11 | ||
39 | -#define MP_UART2_IRQ 11 | ||
40 | +#define MP_UART_SHARED_IRQ 11 | ||
41 | #define MP_GPIO_IRQ 12 | ||
42 | #define MP_RTC_IRQ 28 | ||
43 | #define MP_AUDIO_IRQ 30 | ||
44 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
45 | ARMCPU *cpu; | ||
46 | qemu_irq pic[32]; | ||
47 | DeviceState *dev; | ||
48 | + DeviceState *uart_orgate; | ||
49 | DeviceState *i2c_dev; | ||
50 | DeviceState *lcd_dev; | ||
51 | DeviceState *key_dev; | ||
52 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
53 | pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], | ||
54 | pic[MP_TIMER4_IRQ], NULL); | ||
55 | |||
56 | - serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ], | ||
57 | + /* Logically OR both UART IRQs together */ | ||
58 | + uart_orgate = DEVICE(object_new(TYPE_OR_IRQ)); | ||
59 | + object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal); | ||
60 | + qdev_realize_and_unref(uart_orgate, NULL, &error_fatal); | ||
61 | + qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]); | ||
22 | + | 62 | + |
23 | +This machine is a model of the Sharp Zaurus SL-5500, which was | 63 | + serial_mm_init(address_space_mem, MP_UART1_BASE, 2, |
24 | +a 1990s PDA based on the StrongARM SA1110. | 64 | + qdev_get_gpio_in(uart_orgate, 0), |
25 | + | 65 | 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN); |
26 | +Implemented devices: | 66 | - serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ], |
27 | + | 67 | + serial_mm_init(address_space_mem, MP_UART2_BASE, 2, |
28 | + * NOR flash | 68 | + qdev_get_gpio_in(uart_orgate, 1), |
29 | + * Interrupt controller | 69 | 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN); |
30 | + * Timer | 70 | |
31 | + * RTC | 71 | /* Register flash */ |
32 | + * GPIO | 72 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig |
33 | + * Peripheral Pin Controller (PPC) | ||
34 | + * UARTs | ||
35 | + * Synchronous Serial Ports (SSP) | ||
36 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
37 | index XXXXXXX..XXXXXXX 100644 | 73 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/docs/system/target-arm.rst | 74 | --- a/hw/arm/Kconfig |
39 | +++ b/docs/system/target-arm.rst | 75 | +++ b/hw/arm/Kconfig |
40 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | 76 | @@ -XXX,XX +XXX,XX @@ config MUSCA |
41 | arm/orangepi | 77 | |
42 | arm/palm | 78 | config MUSICPAL |
43 | arm/xscale | 79 | bool |
44 | + arm/collie | 80 | + select OR_IRQ |
45 | arm/sx1 | 81 | select BITBANG_I2C |
46 | arm/stellaris | 82 | select MARVELL_88W8618 |
47 | 83 | select PTIMER | |
48 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/MAINTAINERS | ||
51 | +++ b/MAINTAINERS | ||
52 | @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org | ||
53 | S: Odd Fixes | ||
54 | F: hw/arm/collie.c | ||
55 | F: hw/arm/strongarm* | ||
56 | +F: docs/system/arm/collie.rst | ||
57 | |||
58 | Stellaris | ||
59 | M: Peter Maydell <peter.maydell@linaro.org> | ||
60 | -- | 84 | -- |
61 | 2.20.1 | 85 | 2.20.1 |
62 | 86 | ||
63 | 87 | diff view generated by jsdifflib |
1 | From: David CARLIER <devnexen@gmail.com> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | Implement qemu_get_thread_id() for OpenBSD hosts, using | 3 | We don't need to fill the full pic[] array if we only use |
4 | getthrid(). | 4 | few of the interrupt lines. Directly call qdev_get_gpio_in() |
5 | when necessary. | ||
5 | 6 | ||
6 | Signed-off-by: David Carlier <devnexen@gmail.com> | 7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
7 | Reviewed-by: Brad Smith <brad@comstyle.com> | 8 | Message-id: 20201107193403.436146-6-f4bug@amsat.org |
8 | Message-id: CA+XhMqxD6gQDBaj8tX0CMEj3si7qYKsM8u1km47e_-U7MC37Pg@mail.gmail.com | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | [PMM: tidied up commit message] | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 11 | --- |
13 | util/oslib-posix.c | 2 ++ | 12 | hw/arm/musicpal.c | 25 +++++++++++++------------ |
14 | 1 file changed, 2 insertions(+) | 13 | 1 file changed, 13 insertions(+), 12 deletions(-) |
15 | 14 | ||
16 | diff --git a/util/oslib-posix.c b/util/oslib-posix.c | 15 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c |
17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/util/oslib-posix.c | 17 | --- a/hw/arm/musicpal.c |
19 | +++ b/util/oslib-posix.c | 18 | +++ b/hw/arm/musicpal.c |
20 | @@ -XXX,XX +XXX,XX @@ int qemu_get_thread_id(void) | 19 | @@ -XXX,XX +XXX,XX @@ static struct arm_boot_info musicpal_binfo = { |
21 | return (int)tid; | 20 | static void musicpal_init(MachineState *machine) |
22 | #elif defined(__NetBSD__) | 21 | { |
23 | return _lwp_self(); | 22 | ARMCPU *cpu; |
24 | +#elif defined(__OpenBSD__) | 23 | - qemu_irq pic[32]; |
25 | + return getthrid(); | 24 | DeviceState *dev; |
26 | #else | 25 | + DeviceState *pic; |
27 | return getpid(); | 26 | DeviceState *uart_orgate; |
28 | #endif | 27 | DeviceState *i2c_dev; |
28 | DeviceState *lcd_dev; | ||
29 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
30 | &error_fatal); | ||
31 | memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram); | ||
32 | |||
33 | - dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, | ||
34 | + pic = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, | ||
35 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); | ||
36 | - for (i = 0; i < 32; i++) { | ||
37 | - pic[i] = qdev_get_gpio_in(dev, i); | ||
38 | - } | ||
39 | - sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ], | ||
40 | - pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], | ||
41 | - pic[MP_TIMER4_IRQ], NULL); | ||
42 | + sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, | ||
43 | + qdev_get_gpio_in(pic, MP_TIMER1_IRQ), | ||
44 | + qdev_get_gpio_in(pic, MP_TIMER2_IRQ), | ||
45 | + qdev_get_gpio_in(pic, MP_TIMER3_IRQ), | ||
46 | + qdev_get_gpio_in(pic, MP_TIMER4_IRQ), NULL); | ||
47 | |||
48 | /* Logically OR both UART IRQs together */ | ||
49 | uart_orgate = DEVICE(object_new(TYPE_OR_IRQ)); | ||
50 | object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal); | ||
51 | qdev_realize_and_unref(uart_orgate, NULL, &error_fatal); | ||
52 | - qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]); | ||
53 | + qdev_connect_gpio_out(DEVICE(uart_orgate), 0, | ||
54 | + qdev_get_gpio_in(pic, MP_UART_SHARED_IRQ)); | ||
55 | |||
56 | serial_mm_init(address_space_mem, MP_UART1_BASE, 2, | ||
57 | qdev_get_gpio_in(uart_orgate, 0), | ||
58 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
59 | OBJECT(get_system_memory()), &error_fatal); | ||
60 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
61 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE); | ||
62 | - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]); | ||
63 | + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, | ||
64 | + qdev_get_gpio_in(pic, MP_ETH_IRQ)); | ||
65 | |||
66 | sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); | ||
67 | |||
68 | sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL); | ||
69 | |||
70 | dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE, | ||
71 | - pic[MP_GPIO_IRQ]); | ||
72 | + qdev_get_gpio_in(pic, MP_GPIO_IRQ)); | ||
73 | i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL); | ||
74 | i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c"); | ||
75 | |||
76 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
77 | NULL); | ||
78 | sysbus_realize_and_unref(s, &error_fatal); | ||
79 | sysbus_mmio_map(s, 0, MP_AUDIO_BASE); | ||
80 | - sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]); | ||
81 | + sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ)); | ||
82 | |||
83 | musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; | ||
84 | arm_load_kernel(cpu, machine, &musicpal_binfo); | ||
29 | -- | 85 | -- |
30 | 2.20.1 | 86 | 2.20.1 |
31 | 87 | ||
32 | 88 | diff view generated by jsdifflib |
1 | Add skeletal documentation of the canon-a1100 board. | 1 | The nseries machines have a codepath that allows them to load a |
---|---|---|---|
2 | secondary bootloader. This code wasn't checking that the | ||
3 | load_image_targphys() succeeded. Check the return value and report | ||
4 | the error to the user. | ||
2 | 5 | ||
6 | While we're in the vicinity, fix the comment style of the | ||
7 | comment documenting what this image load is doing. | ||
8 | |||
9 | Fixes: Coverity CID 1192904 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 11 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 12 | Message-id: 20201103114918.11807-1-peter.maydell@linaro.org |
6 | Message-id: 20200713175746.5936-2-peter.maydell@linaro.org | ||
7 | --- | 13 | --- |
8 | docs/system/arm/digic.rst | 11 +++++++++++ | 14 | hw/arm/nseries.c | 15 +++++++++++---- |
9 | docs/system/target-arm.rst | 1 + | 15 | 1 file changed, 11 insertions(+), 4 deletions(-) |
10 | MAINTAINERS | 1 + | ||
11 | 3 files changed, 13 insertions(+) | ||
12 | create mode 100644 docs/system/arm/digic.rst | ||
13 | 16 | ||
14 | diff --git a/docs/system/arm/digic.rst b/docs/system/arm/digic.rst | 17 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c |
15 | new file mode 100644 | ||
16 | index XXXXXXX..XXXXXXX | ||
17 | --- /dev/null | ||
18 | +++ b/docs/system/arm/digic.rst | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | +Canon A1100 (``canon-a1100``) | ||
21 | +============================= | ||
22 | + | ||
23 | +This machine is a model of the Canon PowerShot A1100 camera, which | ||
24 | +uses the DIGIC SoC. This model is based on reverse engineering efforts | ||
25 | +by the contributors to the `CHDK <http://chdk.wikia.com/>`_ and | ||
26 | +`Magic Lantern <http://www.magiclantern.fm/>`_ projects. | ||
27 | + | ||
28 | +The emulation is incomplete. In particular it can't be used | ||
29 | +to run the original camera firmware, but it can successfully run | ||
30 | +an experimental version of the `barebox bootloader <http://www.barebox.org/>`_. | ||
31 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
32 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
33 | --- a/docs/system/target-arm.rst | 19 | --- a/hw/arm/nseries.c |
34 | +++ b/docs/system/target-arm.rst | 20 | +++ b/hw/arm/nseries.c |
35 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | 21 | @@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine, |
36 | arm/versatile | 22 | /* No, wait, better start at the ROM. */ |
37 | arm/vexpress | 23 | s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000; |
38 | arm/aspeed | 24 | |
39 | + arm/digic | 25 | - /* This is intended for loading the `secondary.bin' program from |
40 | arm/musicpal | 26 | + /* |
41 | arm/nseries | 27 | + * This is intended for loading the `secondary.bin' program from |
42 | arm/orangepi | 28 | * Nokia images (the NOLO bootloader). The entry point seems |
43 | diff --git a/MAINTAINERS b/MAINTAINERS | 29 | * to be at OMAP2_Q2_BASE + 0x400000. |
44 | index XXXXXXX..XXXXXXX 100644 | 30 | * |
45 | --- a/MAINTAINERS | 31 | @@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine, |
46 | +++ b/MAINTAINERS | 32 | * for them the entry point needs to be set to OMAP2_SRAM_BASE. |
47 | @@ -XXX,XX +XXX,XX @@ F: include/hw/arm/digic.h | 33 | * |
48 | F: hw/*/digic* | 34 | * The code above is for loading the `zImage' file from Nokia |
49 | F: include/hw/*/digic* | 35 | - * images. */ |
50 | F: tests/acceptance/machine_arm_canona1100.py | 36 | - load_image_targphys(option_rom[0].name, OMAP2_Q2_BASE + 0x400000, |
51 | +F: docs/system/arm/digic.rst | 37 | - machine->ram_size - 0x400000); |
52 | 38 | + * images. | |
53 | Goldfish RTC | 39 | + */ |
54 | M: Anup Patel <anup.patel@wdc.com> | 40 | + if (load_image_targphys(option_rom[0].name, |
41 | + OMAP2_Q2_BASE + 0x400000, | ||
42 | + machine->ram_size - 0x400000) < 0) { | ||
43 | + error_report("Failed to load secondary bootloader %s", | ||
44 | + option_rom[0].name); | ||
45 | + exit(EXIT_FAILURE); | ||
46 | + } | ||
47 | |||
48 | n800_setup_nolo_tags(nolo_tags); | ||
49 | cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000); | ||
55 | -- | 50 | -- |
56 | 2.20.1 | 51 | 2.20.1 |
57 | 52 | ||
58 | 53 | diff view generated by jsdifflib |
1 | Add documentation comments for the various qdev functions | 1 | From: Havard Skinnemoen <hskinnemoen@google.com> |
---|---|---|---|
2 | related to creating and connecting GPIO lines. | ||
3 | 2 | ||
3 | The number of runs is equal to the number of 0-1 and 1-0 transitions, | ||
4 | plus one. Currently, it's counting the number of times these transitions | ||
5 | do _not_ happen, plus one. | ||
6 | |||
7 | Source: | ||
8 | https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-22r1a.pdf | ||
9 | section 2.3.4 point (3). | ||
10 | |||
11 | Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
12 | Message-id: 20201103011457.2959989-2-hskinnemoen@google.com | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20200711142425.16283-4-peter.maydell@linaro.org | ||
7 | --- | 15 | --- |
8 | include/hw/qdev-core.h | 191 ++++++++++++++++++++++++++++++++++++++++- | 16 | tests/qtest/npcm7xx_rng-test.c | 2 +- |
9 | 1 file changed, 189 insertions(+), 2 deletions(-) | 17 | 1 file changed, 1 insertion(+), 1 deletion(-) |
10 | 18 | ||
11 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | 19 | diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c |
12 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/include/hw/qdev-core.h | 21 | --- a/tests/qtest/npcm7xx_rng-test.c |
14 | +++ b/include/hw/qdev-core.h | 22 | +++ b/tests/qtest/npcm7xx_rng-test.c |
15 | @@ -XXX,XX +XXX,XX @@ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev, | 23 | @@ -XXX,XX +XXX,XX @@ static double calc_runs_p(const unsigned long *buf, unsigned int nr_bits) |
16 | void qdev_machine_creation_done(void); | 24 | pi = (double)nr_ones / nr_bits; |
17 | bool qdev_machine_modified(void); | 25 | |
18 | 26 | for (k = 0; k < nr_bits - 1; k++) { | |
19 | +/** | 27 | - vn_obs += !(test_bit(k, buf) ^ test_bit(k + 1, buf)); |
20 | + * qdev_get_gpio_in: Get one of a device's anonymous input GPIO lines | 28 | + vn_obs += (test_bit(k, buf) ^ test_bit(k + 1, buf)); |
21 | + * @dev: Device whose GPIO we want | 29 | } |
22 | + * @n: Number of the anonymous GPIO line (which must be in range) | 30 | vn_obs += 1; |
23 | + * | ||
24 | + * Returns the qemu_irq corresponding to an anonymous input GPIO line | ||
25 | + * (which the device has set up with qdev_init_gpio_in()). The index | ||
26 | + * @n of the GPIO line must be valid (i.e. be at least 0 and less than | ||
27 | + * the total number of anonymous input GPIOs the device has); this | ||
28 | + * function will assert() if passed an invalid index. | ||
29 | + * | ||
30 | + * This function is intended to be used by board code or SoC "container" | ||
31 | + * device models to wire up the GPIO lines; usually the return value | ||
32 | + * will be passed to qdev_connect_gpio_out() or a similar function to | ||
33 | + * connect another device's output GPIO line to this input. | ||
34 | + * | ||
35 | + * For named input GPIO lines, use qdev_get_gpio_in_named(). | ||
36 | + */ | ||
37 | qemu_irq qdev_get_gpio_in(DeviceState *dev, int n); | ||
38 | +/** | ||
39 | + * qdev_get_gpio_in_named: Get one of a device's named input GPIO lines | ||
40 | + * @dev: Device whose GPIO we want | ||
41 | + * @name: Name of the input GPIO array | ||
42 | + * @n: Number of the GPIO line in that array (which must be in range) | ||
43 | + * | ||
44 | + * Returns the qemu_irq corresponding to a named input GPIO line | ||
45 | + * (which the device has set up with qdev_init_gpio_in_named()). | ||
46 | + * The @name string must correspond to an input GPIO array which exists on | ||
47 | + * the device, and the index @n of the GPIO line must be valid (i.e. | ||
48 | + * be at least 0 and less than the total number of input GPIOs in that | ||
49 | + * array); this function will assert() if passed an invalid name or index. | ||
50 | + * | ||
51 | + * For anonymous input GPIO lines, use qdev_get_gpio_in(). | ||
52 | + */ | ||
53 | qemu_irq qdev_get_gpio_in_named(DeviceState *dev, const char *name, int n); | ||
54 | |||
55 | +/** | ||
56 | + * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines | ||
57 | + * @dev: Device whose GPIO to connect | ||
58 | + * @n: Number of the anonymous output GPIO line (which must be in range) | ||
59 | + * @pin: qemu_irq to connect the output line to | ||
60 | + * | ||
61 | + * This function connects an anonymous output GPIO line on a device | ||
62 | + * up to an arbitrary qemu_irq, so that when the device asserts that | ||
63 | + * output GPIO line, the qemu_irq's callback is invoked. | ||
64 | + * The index @n of the GPIO line must be valid (i.e. be at least 0 and | ||
65 | + * less than the total number of anonymous output GPIOs the device has | ||
66 | + * created with qdev_init_gpio_out()); otherwise this function will assert(). | ||
67 | + * | ||
68 | + * Outbound GPIO lines can be connected to any qemu_irq, but the common | ||
69 | + * case is connecting them to another device's inbound GPIO line, using | ||
70 | + * the qemu_irq returned by qdev_get_gpio_in() or qdev_get_gpio_in_named(). | ||
71 | + * | ||
72 | + * It is not valid to try to connect one outbound GPIO to multiple | ||
73 | + * qemu_irqs at once, or to connect multiple outbound GPIOs to the | ||
74 | + * same qemu_irq. (Warning: there is no assertion or other guard to | ||
75 | + * catch this error: the model will just not do the right thing.) | ||
76 | + * Instead, for fan-out you can use the TYPE_IRQ_SPLIT device: connect | ||
77 | + * a device's outbound GPIO to the splitter's input, and connect each | ||
78 | + * of the splitter's outputs to a different device. For fan-in you | ||
79 | + * can use the TYPE_OR_IRQ device, which is a model of a logical OR | ||
80 | + * gate with multiple inputs and one output. | ||
81 | + * | ||
82 | + * For named output GPIO lines, use qdev_connect_gpio_out_named(). | ||
83 | + */ | ||
84 | void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin); | ||
85 | +/** | ||
86 | + * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines | ||
87 | + * @dev: Device whose GPIO to connect | ||
88 | + * @name: Name of the output GPIO array | ||
89 | + * @n: Number of the anonymous output GPIO line (which must be in range) | ||
90 | + * @pin: qemu_irq to connect the output line to | ||
91 | + * | ||
92 | + * This function connects an anonymous output GPIO line on a device | ||
93 | + * up to an arbitrary qemu_irq, so that when the device asserts that | ||
94 | + * output GPIO line, the qemu_irq's callback is invoked. | ||
95 | + * The @name string must correspond to an output GPIO array which exists on | ||
96 | + * the device, and the index @n of the GPIO line must be valid (i.e. | ||
97 | + * be at least 0 and less than the total number of input GPIOs in that | ||
98 | + * array); this function will assert() if passed an invalid name or index. | ||
99 | + * | ||
100 | + * Outbound GPIO lines can be connected to any qemu_irq, but the common | ||
101 | + * case is connecting them to another device's inbound GPIO line, using | ||
102 | + * the qemu_irq returned by qdev_get_gpio_in() or qdev_get_gpio_in_named(). | ||
103 | + * | ||
104 | + * It is not valid to try to connect one outbound GPIO to multiple | ||
105 | + * qemu_irqs at once, or to connect multiple outbound GPIOs to the | ||
106 | + * same qemu_irq; see qdev_connect_gpio_out() for details. | ||
107 | + * | ||
108 | + * For named output GPIO lines, use qdev_connect_gpio_out_named(). | ||
109 | + */ | ||
110 | void qdev_connect_gpio_out_named(DeviceState *dev, const char *name, int n, | ||
111 | qemu_irq pin); | ||
112 | +/** | ||
113 | + * qdev_get_gpio_out_connector: Get the qemu_irq connected to an output GPIO | ||
114 | + * @dev: Device whose output GPIO we are interested in | ||
115 | + * @name: Name of the output GPIO array | ||
116 | + * @n: Number of the output GPIO line within that array | ||
117 | + * | ||
118 | + * Returns whatever qemu_irq is currently connected to the specified | ||
119 | + * output GPIO line of @dev. This will be NULL if the output GPIO line | ||
120 | + * has never been wired up to the anything. Note that the qemu_irq | ||
121 | + * returned does not belong to @dev -- it will be the input GPIO or | ||
122 | + * IRQ of whichever device the board code has connected up to @dev's | ||
123 | + * output GPIO. | ||
124 | + * | ||
125 | + * You probably don't need to use this function -- it is used only | ||
126 | + * by the platform-bus subsystem. | ||
127 | + */ | ||
128 | qemu_irq qdev_get_gpio_out_connector(DeviceState *dev, const char *name, int n); | ||
129 | +/** | ||
130 | + * qdev_intercept_gpio_out: Intercept an existing GPIO connection | ||
131 | + * @dev: Device to intercept the outbound GPIO line from | ||
132 | + * @icpt: New qemu_irq to connect instead | ||
133 | + * @name: Name of the output GPIO array | ||
134 | + * @n: Number of the GPIO line in the array | ||
135 | + * | ||
136 | + * This function is provided only for use by the qtest testing framework | ||
137 | + * and is not suitable for use in non-testing parts of QEMU. | ||
138 | + * | ||
139 | + * This function breaks an existing connection of an outbound GPIO | ||
140 | + * line from @dev, and replaces it with the new qemu_irq @icpt, as if | ||
141 | + * ``qdev_connect_gpio_out_named(dev, icpt, name, n)`` had been called. | ||
142 | + * The previously connected qemu_irq is returned, so it can be restored | ||
143 | + * by a second call to qdev_intercept_gpio_out() if desired. | ||
144 | + */ | ||
145 | qemu_irq qdev_intercept_gpio_out(DeviceState *dev, qemu_irq icpt, | ||
146 | const char *name, int n); | ||
147 | |||
148 | @@ -XXX,XX +XXX,XX @@ BusState *qdev_get_child_bus(DeviceState *dev, const char *name); | ||
149 | |||
150 | /*** Device API. ***/ | ||
151 | |||
152 | -/* Register device properties. */ | ||
153 | -/* GPIO inputs also double as IRQ sinks. */ | ||
154 | +/** | ||
155 | + * qdev_init_gpio_in: create an array of anonymous input GPIO lines | ||
156 | + * @dev: Device to create input GPIOs for | ||
157 | + * @handler: Function to call when GPIO line value is set | ||
158 | + * @n: Number of GPIO lines to create | ||
159 | + * | ||
160 | + * Devices should use functions in the qdev_init_gpio_in* family in | ||
161 | + * their instance_init or realize methods to create any input GPIO | ||
162 | + * lines they need. There is no functional difference between | ||
163 | + * anonymous and named GPIO lines. Stylistically, named GPIOs are | ||
164 | + * preferable (easier to understand at callsites) unless a device | ||
165 | + * has exactly one uniform kind of GPIO input whose purpose is obvious. | ||
166 | + * Note that input GPIO lines can serve as 'sinks' for IRQ lines. | ||
167 | + * | ||
168 | + * See qdev_get_gpio_in() for how code that uses such a device can get | ||
169 | + * hold of an input GPIO line to manipulate it. | ||
170 | + */ | ||
171 | void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n); | ||
172 | +/** | ||
173 | + * qdev_init_gpio_out: create an array of anonymous output GPIO lines | ||
174 | + * @dev: Device to create output GPIOs for | ||
175 | + * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines | ||
176 | + * @n: Number of GPIO lines to create | ||
177 | + * | ||
178 | + * Devices should use functions in the qdev_init_gpio_out* family | ||
179 | + * in their instance_init or realize methods to create any output | ||
180 | + * GPIO lines they need. There is no functional difference between | ||
181 | + * anonymous and named GPIO lines. Stylistically, named GPIOs are | ||
182 | + * preferable (easier to understand at callsites) unless a device | ||
183 | + * has exactly one uniform kind of GPIO output whose purpose is obvious. | ||
184 | + * | ||
185 | + * The @pins argument should be a pointer to either a "qemu_irq" | ||
186 | + * (if @n == 1) or a "qemu_irq []" array (if @n > 1) in the device's | ||
187 | + * state structure. The device implementation can then raise and | ||
188 | + * lower the GPIO line by calling qemu_set_irq(). (If anything is | ||
189 | + * connected to the other end of the GPIO this will cause the handler | ||
190 | + * function for that input GPIO to be called.) | ||
191 | + * | ||
192 | + * See qdev_connect_gpio_out() for how code that uses such a device | ||
193 | + * can connect to one of its output GPIO lines. | ||
194 | + */ | ||
195 | void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n); | ||
196 | +/** | ||
197 | + * qdev_init_gpio_out: create an array of named output GPIO lines | ||
198 | + * @dev: Device to create output GPIOs for | ||
199 | + * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines | ||
200 | + * @name: Name to give this array of GPIO lines | ||
201 | + * @n: Number of GPIO lines to create | ||
202 | + * | ||
203 | + * Like qdev_init_gpio_out(), but creates an array of GPIO output lines | ||
204 | + * with a name. Code using the device can then connect these GPIO lines | ||
205 | + * using qdev_connect_gpio_out_named(). | ||
206 | + */ | ||
207 | void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins, | ||
208 | const char *name, int n); | ||
209 | /** | ||
210 | @@ -XXX,XX +XXX,XX @@ static inline void qdev_init_gpio_in_named(DeviceState *dev, | ||
211 | qdev_init_gpio_in_named_with_opaque(dev, handler, dev, name, n); | ||
212 | } | ||
213 | |||
214 | +/** | ||
215 | + * qdev_pass_gpios: create GPIO lines on container which pass through to device | ||
216 | + * @dev: Device which has GPIO lines | ||
217 | + * @container: Container device which needs to expose them | ||
218 | + * @name: Name of GPIO array to pass through (NULL for the anonymous GPIO array) | ||
219 | + * | ||
220 | + * In QEMU, complicated devices like SoCs are often modelled with a | ||
221 | + * "container" QOM device which itself contains other QOM devices and | ||
222 | + * which wires them up appropriately. This function allows the container | ||
223 | + * to create GPIO arrays on itself which simply pass through to a GPIO | ||
224 | + * array of one of its internal devices. | ||
225 | + * | ||
226 | + * If @dev has both input and output GPIOs named @name then both will | ||
227 | + * be passed through. It is not possible to pass a subset of the array | ||
228 | + * with this function. | ||
229 | + * | ||
230 | + * To users of the container device, the GPIO array created on @container | ||
231 | + * behaves exactly like any other. | ||
232 | + */ | ||
233 | void qdev_pass_gpios(DeviceState *dev, DeviceState *container, | ||
234 | const char *name); | ||
235 | 31 | ||
236 | -- | 32 | -- |
237 | 2.20.1 | 33 | 2.20.1 |
238 | 34 | ||
239 | 35 | diff view generated by jsdifflib |
1 | Add a doc comment for qdev_unrealize(), to go with the new | 1 | Checks for UNDEF cases should go before the "is VFP enabled?" access |
---|---|---|---|
2 | documentation for the realize part of the qdev lifecycle. | 2 | check, except in special cases. Move a stray UNDEF check in the VTBL |
3 | trans function up above the access check. | ||
3 | 4 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 20200711142425.16283-3-peter.maydell@linaro.org | 7 | Message-id: 20201109145324.2859-1-peter.maydell@linaro.org |
7 | --- | 8 | --- |
8 | include/hw/qdev-core.h | 19 +++++++++++++++++++ | 9 | target/arm/translate-neon.c.inc | 8 ++++---- |
9 | 1 file changed, 19 insertions(+) | 10 | 1 file changed, 4 insertions(+), 4 deletions(-) |
10 | 11 | ||
11 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | 12 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc |
12 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/include/hw/qdev-core.h | 14 | --- a/target/arm/translate-neon.c.inc |
14 | +++ b/include/hw/qdev-core.h | 15 | +++ b/target/arm/translate-neon.c.inc |
15 | @@ -XXX,XX +XXX,XX @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp); | 16 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) |
16 | * would be incorrect. For that use case you want qdev_realize(). | 17 | return false; |
17 | */ | 18 | } |
18 | bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp); | 19 | |
19 | +/** | 20 | - if (!vfp_access_check(s)) { |
20 | + * qdev_unrealize: Unrealize a device | 21 | - return true; |
21 | + * @dev: device to unrealize | 22 | - } |
22 | + * | 23 | - |
23 | + * This function will "unrealize" a device, which is the first phase | 24 | if ((a->vn + a->len + 1) > 32) { |
24 | + * of correctly destroying a device that has been realized. It will: | 25 | /* |
25 | + * | 26 | * This is UNPREDICTABLE; we choose to UNDEF to avoid the |
26 | + * - unrealize any child buses by calling qbus_unrealize() | 27 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) |
27 | + * (this will recursively unrealize any devices on those buses) | 28 | return false; |
28 | + * - call the the unrealize method of @dev | 29 | } |
29 | + * | 30 | |
30 | + * The device can then be freed by causing its reference count to go | 31 | + if (!vfp_access_check(s)) { |
31 | + * to zero. | 32 | + return true; |
32 | + * | 33 | + } |
33 | + * Warning: most devices in QEMU do not expect to be unrealized. Only | 34 | + |
34 | + * devices which are hot-unpluggable should be unrealized (as part of | 35 | desc = tcg_const_i32((a->vn << 2) | a->len); |
35 | + * the unplugging process); all other devices are expected to last for | 36 | def = tcg_temp_new_i64(); |
36 | + * the life of the simulation and should not be unrealized and freed. | 37 | if (a->op) { |
37 | + */ | ||
38 | void qdev_unrealize(DeviceState *dev); | ||
39 | void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id, | ||
40 | int required_for_version); | ||
41 | -- | 38 | -- |
42 | 2.20.1 | 39 | 2.20.1 |
43 | 40 | ||
44 | 41 | diff view generated by jsdifflib |