[PULL for-5.1 0/3] tcg patch queue
[PULL v2 00/29] tcg patch queue
1
The following changes since commit 95d1fbabae0cd44156ac4b96d512d143ca7dfd5e:
1
v2: Fix FreeBSD build error in patch 18.
2
2
3
Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200716-pull-request' into staging (2020-07-16 18:50:51 +0100)
3
r~
4
5
6
The following changes since commit 0d239e513e0117e66fa739fb71a43b9383a108ff:
7
8
Merge tag 'pull-lu-20231018' of https://gitlab.com/rth7680/qemu into staging (2023-10-19 10:20:57 -0700)
4
9
5
are available in the Git repository at:
10
are available in the Git repository at:
6
11
7
https://github.com/rth7680/qemu.git tags/pull-tcg-20200717
12
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20231018-2
8
13
9
for you to fetch changes up to ba3c35d9c4026361fd380b269dc6def9510b7166:
14
for you to fetch changes up to a75f704d972b9408f5e2843784b3add48c724c52:
10
15
11
tcg/cpu-exec: precise single-stepping after an interrupt (2020-07-17 11:09:34 -0700)
16
target/i386: Use i128 for 128 and 256-bit loads and stores (2023-10-19 21:11:44 -0700)
12
17
13
----------------------------------------------------------------
18
----------------------------------------------------------------
14
Fix vector min/max fallback expansion
19
tcg: Drop unused tcg_temp_free define
15
Fix singlestep from exception and interrupt
20
tcg: Introduce tcg_use_softmmu
21
tcg: Optimize past conditional branches
22
tcg: Use constant zero when expanding with divu2
23
tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TB
24
tcg/ppc: Use ADDPCIS for power9
25
tcg/ppc: Use prefixed instructions for power10
26
tcg/ppc: Disable TCG_REG_TB for Power9/Power10
16
27
17
----------------------------------------------------------------
28
----------------------------------------------------------------
18
Luc Michel (1):
29
Jordan Niethe (1):
19
tcg/cpu-exec: precise single-stepping after an exception
30
tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TB
20
31
21
Richard Henderson (2):
32
Mike Frysinger (1):
22
tcg: Save/restore vecop_list around minmax fallback
33
tcg: drop unused tcg_temp_free define
23
tcg/cpu-exec: precise single-stepping after an interrupt
24
34
25
accel/tcg/cpu-exec.c | 19 ++++++++++++++++++-
35
Richard Henderson (27):
26
tcg/tcg-op-vec.c | 2 ++
36
tcg/ppc: Untabify tcg-target.c.inc
27
2 files changed, 20 insertions(+), 1 deletion(-)
37
tcg/ppc: Reinterpret tb-relative to TB+4
38
tcg/ppc: Use ADDPCIS in tcg_out_tb_start
39
tcg/ppc: Use ADDPCIS in tcg_out_movi_int
40
tcg/ppc: Use ADDPCIS for the constant pool
41
tcg/ppc: Use ADDPCIS in tcg_out_goto_tb
42
tcg/ppc: Use PADDI in tcg_out_movi
43
tcg/ppc: Use prefixed instructions in tcg_out_mem_long
44
tcg/ppc: Use PLD in tcg_out_movi for constant pool
45
tcg/ppc: Use prefixed instructions in tcg_out_dupi_vec
46
tcg/ppc: Use PLD in tcg_out_goto_tb
47
tcg/ppc: Disable TCG_REG_TB for Power9/Power10
48
tcg: Introduce tcg_use_softmmu
49
tcg: Provide guest_base fallback for system mode
50
tcg/arm: Use tcg_use_softmmu
51
tcg/aarch64: Use tcg_use_softmmu
52
tcg/i386: Use tcg_use_softmmu
53
tcg/loongarch64: Use tcg_use_softmmu
54
tcg/mips: Use tcg_use_softmmu
55
tcg/ppc: Use tcg_use_softmmu
56
tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zero
57
tcg/riscv: Use tcg_use_softmmu
58
tcg/s390x: Use tcg_use_softmmu
59
tcg: Use constant zero when expanding with divu2
60
tcg: Optimize past conditional branches
61
tcg: Add tcg_gen_{ld,st}_i128
62
target/i386: Use i128 for 128 and 256-bit loads and stores
28
63
64
include/tcg/tcg-op-common.h | 3 +
65
include/tcg/tcg-op.h | 2 -
66
include/tcg/tcg.h | 8 +-
67
target/i386/tcg/translate.c | 63 ++---
68
tcg/optimize.c | 8 +-
69
tcg/tcg-op-ldst.c | 14 +-
70
tcg/tcg-op.c | 38 ++-
71
tcg/tcg.c | 13 +-
72
tcg/aarch64/tcg-target.c.inc | 177 ++++++------
73
tcg/arm/tcg-target.c.inc | 203 +++++++-------
74
tcg/i386/tcg-target.c.inc | 198 +++++++-------
75
tcg/loongarch64/tcg-target.c.inc | 126 +++++----
76
tcg/mips/tcg-target.c.inc | 231 ++++++++--------
77
tcg/ppc/tcg-target.c.inc | 561 ++++++++++++++++++++++++++-------------
78
tcg/riscv/tcg-target.c.inc | 189 ++++++-------
79
tcg/s390x/tcg-target.c.inc | 161 ++++++-----
80
16 files changed, 1102 insertions(+), 893 deletions(-)
diff view generated by jsdifflib
[PULL for-5.1 1/3] tcg: Save/restore vecop_list around minmax fallback
Deleted patch
1
Forgetting this asserts when tcg_gen_cmp_vec is called from
2
within tcg_gen_cmpsel_vec.
3
1
4
Fixes: 72b4c792c7a
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/tcg-op-vec.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/tcg-op-vec.c
13
+++ b/tcg/tcg-op-vec.c
14
@@ -XXX,XX +XXX,XX @@ static void do_minmax(unsigned vece, TCGv_vec r, TCGv_vec a,
15
TCGv_vec b, TCGOpcode opc, TCGCond cond)
16
{
17
if (!do_op3(vece, r, a, b, opc)) {
18
+ const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
19
tcg_gen_cmpsel_vec(cond, vece, r, a, b, a, b);
20
+ tcg_swap_vecop_list(hold_list);
21
}
22
}
23
24
--
25
2.25.1
26
27
diff view generated by jsdifflib
[PULL for-5.1 2/3] tcg/cpu-exec: precise single-stepping after an exception
Deleted patch
1
From: Luc Michel <luc.michel@greensocs.com>
2
1
3
When single-stepping with a debugger attached to QEMU, and when an
4
exception is raised, the debugger misses the first instruction after the
5
exception:
6
7
$ qemu-system-aarch64 -M virt -display none -cpu cortex-a53 -s -S
8
9
$ aarch64-linux-gnu-gdb
10
GNU gdb (GDB) 9.2
11
[...]
12
(gdb) tar rem :1234
13
Remote debugging using :1234
14
warning: No executable has been specified and target does not support
15
determining executable automatically. Try using the "file" command.
16
0x0000000000000000 in ?? ()
17
(gdb) # writing nop insns to 0x200 and 0x204
18
(gdb) set *0x200 = 0xd503201f
19
(gdb) set *0x204 = 0xd503201f
20
(gdb) # 0x0 address contains 0 which is an invalid opcode.
21
(gdb) # The CPU should raise an exception and jump to 0x200
22
(gdb) si
23
0x0000000000000204 in ?? ()
24
25
With this commit, the same run steps correctly on the first instruction
26
of the exception vector:
27
28
(gdb) si
29
0x0000000000000200 in ?? ()
30
31
Buglink: https://bugs.launchpad.net/qemu/+bug/757702
32
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
33
Message-Id: <20200716193947.3058389-1-luc.michel@greensocs.com>
34
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
35
---
36
accel/tcg/cpu-exec.c | 11 +++++++++++
37
1 file changed, 11 insertions(+)
38
39
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/accel/tcg/cpu-exec.c
42
+++ b/accel/tcg/cpu-exec.c
43
@@ -XXX,XX +XXX,XX @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
44
cc->do_interrupt(cpu);
45
qemu_mutex_unlock_iothread();
46
cpu->exception_index = -1;
47
+
48
+ if (unlikely(cpu->singlestep_enabled)) {
49
+ /*
50
+ * After processing the exception, ensure an EXCP_DEBUG is
51
+ * raised when single-stepping so that GDB doesn't miss the
52
+ * next instruction.
53
+ */
54
+ *ret = EXCP_DEBUG;
55
+ cpu_handle_debug_exception(cpu);
56
+ return true;
57
+ }
58
} else if (!replay_has_interrupt()) {
59
/* give a chance to iothread in replay mode */
60
*ret = EXCP_INTERRUPT;
61
--
62
2.25.1
63
64
diff view generated by jsdifflib
[PULL for-5.1 3/3] tcg/cpu-exec: precise single-stepping after an interrupt
[PULL v2 18/29] tcg/i386: Use tcg_use_softmmu
1
When single-stepping with a debugger attached to QEMU, and when an
1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2
interrupt is raised, the debugger misses the first instruction after
3
the interrupt.
4
5
Tested-by: Luc Michel <luc.michel@greensocs.com>
6
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
7
Buglink: https://bugs.launchpad.net/qemu/+bug/757702
8
Message-Id: <20200717163029.2737546-1-richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
3
---
11
accel/tcg/cpu-exec.c | 8 +++++++-
4
tcg/i386/tcg-target.c.inc | 198 +++++++++++++++++++-------------------
12
1 file changed, 7 insertions(+), 1 deletion(-)
5
1 file changed, 98 insertions(+), 100 deletions(-)
13
6
14
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
7
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
15
index XXXXXXX..XXXXXXX 100644
8
index XXXXXXX..XXXXXXX 100644
16
--- a/accel/tcg/cpu-exec.c
9
--- a/tcg/i386/tcg-target.c.inc
17
+++ b/accel/tcg/cpu-exec.c
10
+++ b/tcg/i386/tcg-target.c.inc
18
@@ -XXX,XX +XXX,XX @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
11
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
19
else {
12
# define ALL_VECTOR_REGS 0x00ff0000u
20
if (cc->cpu_exec_interrupt(cpu, interrupt_request)) {
13
# define ALL_BYTEL_REGS 0x0000000fu
21
replay_interrupt();
14
#endif
22
- cpu->exception_index = -1;
15
-#ifdef CONFIG_SOFTMMU
23
+ /*
16
-# define SOFTMMU_RESERVE_REGS ((1 << TCG_REG_L0) | (1 << TCG_REG_L1))
24
+ * After processing the interrupt, ensure an EXCP_DEBUG is
17
-#else
25
+ * raised when single-stepping so that GDB doesn't miss the
18
-# define SOFTMMU_RESERVE_REGS 0
26
+ * next instruction.
19
-#endif
27
+ */
20
+#define SOFTMMU_RESERVE_REGS \
28
+ cpu->exception_index =
21
+ (tcg_use_softmmu ? (1 << TCG_REG_L0) | (1 << TCG_REG_L1) : 0)
29
+ (cpu->singlestep_enabled ? EXCP_DEBUG : -1);
22
30
*last_tb = NULL;
23
/* For 64-bit, we always know that CMOV is available. */
24
#if TCG_TARGET_REG_BITS == 64
25
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
26
return true;
27
}
28
29
-#ifndef CONFIG_SOFTMMU
30
+#ifdef CONFIG_USER_ONLY
31
static HostAddress x86_guest_base = {
32
.index = -1
33
};
34
@@ -XXX,XX +XXX,XX @@ static inline int setup_guest_base_seg(void)
35
}
36
return 0;
37
}
38
+#define setup_guest_base_seg setup_guest_base_seg
39
#elif defined(__x86_64__) && \
40
(defined (__FreeBSD__) || defined (__FreeBSD_kernel__))
41
# include <machine/sysarch.h>
42
@@ -XXX,XX +XXX,XX @@ static inline int setup_guest_base_seg(void)
43
}
44
return 0;
45
}
46
+#define setup_guest_base_seg setup_guest_base_seg
47
+#endif
48
#else
49
-static inline int setup_guest_base_seg(void)
50
-{
51
- return 0;
52
-}
53
-#endif /* setup_guest_base_seg */
54
-#endif /* !SOFTMMU */
55
+# define x86_guest_base (*(HostAddress *)({ qemu_build_not_reached(); NULL; }))
56
+#endif /* CONFIG_USER_ONLY */
57
+#ifndef setup_guest_base_seg
58
+# define setup_guest_base_seg() 0
59
+#endif
60
61
#define MIN_TLB_MASK_TABLE_OFS INT_MIN
62
63
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
64
MemOp s_bits = opc & MO_SIZE;
65
unsigned a_mask;
66
67
-#ifdef CONFIG_SOFTMMU
68
- h->index = TCG_REG_L0;
69
- h->ofs = 0;
70
- h->seg = 0;
71
-#else
72
- *h = x86_guest_base;
73
-#endif
74
+ if (tcg_use_softmmu) {
75
+ h->index = TCG_REG_L0;
76
+ h->ofs = 0;
77
+ h->seg = 0;
78
+ } else {
79
+ *h = x86_guest_base;
80
+ }
81
h->base = addrlo;
82
h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128);
83
a_mask = (1 << h->aa.align) - 1;
84
85
-#ifdef CONFIG_SOFTMMU
86
- int cmp_ofs = is_ld ? offsetof(CPUTLBEntry, addr_read)
87
- : offsetof(CPUTLBEntry, addr_write);
88
- TCGType ttype = TCG_TYPE_I32;
89
- TCGType tlbtype = TCG_TYPE_I32;
90
- int trexw = 0, hrexw = 0, tlbrexw = 0;
91
- unsigned mem_index = get_mmuidx(oi);
92
- unsigned s_mask = (1 << s_bits) - 1;
93
- int fast_ofs = tlb_mask_table_ofs(s, mem_index);
94
- int tlb_mask;
95
+ if (tcg_use_softmmu) {
96
+ int cmp_ofs = is_ld ? offsetof(CPUTLBEntry, addr_read)
97
+ : offsetof(CPUTLBEntry, addr_write);
98
+ TCGType ttype = TCG_TYPE_I32;
99
+ TCGType tlbtype = TCG_TYPE_I32;
100
+ int trexw = 0, hrexw = 0, tlbrexw = 0;
101
+ unsigned mem_index = get_mmuidx(oi);
102
+ unsigned s_mask = (1 << s_bits) - 1;
103
+ int fast_ofs = tlb_mask_table_ofs(s, mem_index);
104
+ int tlb_mask;
105
106
- ldst = new_ldst_label(s);
107
- ldst->is_ld = is_ld;
108
- ldst->oi = oi;
109
- ldst->addrlo_reg = addrlo;
110
- ldst->addrhi_reg = addrhi;
111
+ ldst = new_ldst_label(s);
112
+ ldst->is_ld = is_ld;
113
+ ldst->oi = oi;
114
+ ldst->addrlo_reg = addrlo;
115
+ ldst->addrhi_reg = addrhi;
116
117
- if (TCG_TARGET_REG_BITS == 64) {
118
- ttype = s->addr_type;
119
- trexw = (ttype == TCG_TYPE_I32 ? 0 : P_REXW);
120
- if (TCG_TYPE_PTR == TCG_TYPE_I64) {
121
- hrexw = P_REXW;
122
- if (s->page_bits + s->tlb_dyn_max_bits > 32) {
123
- tlbtype = TCG_TYPE_I64;
124
- tlbrexw = P_REXW;
125
+ if (TCG_TARGET_REG_BITS == 64) {
126
+ ttype = s->addr_type;
127
+ trexw = (ttype == TCG_TYPE_I32 ? 0 : P_REXW);
128
+ if (TCG_TYPE_PTR == TCG_TYPE_I64) {
129
+ hrexw = P_REXW;
130
+ if (s->page_bits + s->tlb_dyn_max_bits > 32) {
131
+ tlbtype = TCG_TYPE_I64;
132
+ tlbrexw = P_REXW;
133
+ }
31
}
134
}
32
/* The target hook may have updated the 'cpu->interrupt_request';
135
}
136
- }
137
138
- tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo);
139
- tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0,
140
- s->page_bits - CPU_TLB_ENTRY_BITS);
141
+ tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo);
142
+ tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0,
143
+ s->page_bits - CPU_TLB_ENTRY_BITS);
144
145
- tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0,
146
- fast_ofs + offsetof(CPUTLBDescFast, mask));
147
+ tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0,
148
+ fast_ofs + offsetof(CPUTLBDescFast, mask));
149
150
- tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0,
151
- fast_ofs + offsetof(CPUTLBDescFast, table));
152
+ tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0,
153
+ fast_ofs + offsetof(CPUTLBDescFast, table));
154
155
- /*
156
- * If the required alignment is at least as large as the access, simply
157
- * copy the address and mask. For lesser alignments, check that we don't
158
- * cross pages for the complete access.
159
- */
160
- if (a_mask >= s_mask) {
161
- tcg_out_mov(s, ttype, TCG_REG_L1, addrlo);
162
- } else {
163
- tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1,
164
- addrlo, s_mask - a_mask);
165
- }
166
- tlb_mask = s->page_mask | a_mask;
167
- tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0);
168
+ /*
169
+ * If the required alignment is at least as large as the access,
170
+ * simply copy the address and mask. For lesser alignments,
171
+ * check that we don't cross pages for the complete access.
172
+ */
173
+ if (a_mask >= s_mask) {
174
+ tcg_out_mov(s, ttype, TCG_REG_L1, addrlo);
175
+ } else {
176
+ tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1,
177
+ addrlo, s_mask - a_mask);
178
+ }
179
+ tlb_mask = s->page_mask | a_mask;
180
+ tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0);
181
182
- /* cmp 0(TCG_REG_L0), TCG_REG_L1 */
183
- tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw,
184
- TCG_REG_L1, TCG_REG_L0, cmp_ofs);
185
-
186
- /* jne slow_path */
187
- tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
188
- ldst->label_ptr[0] = s->code_ptr;
189
- s->code_ptr += 4;
190
-
191
- if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I64) {
192
- /* cmp 4(TCG_REG_L0), addrhi */
193
- tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, cmp_ofs + 4);
194
+ /* cmp 0(TCG_REG_L0), TCG_REG_L1 */
195
+ tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw,
196
+ TCG_REG_L1, TCG_REG_L0, cmp_ofs);
197
198
/* jne slow_path */
199
tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
200
- ldst->label_ptr[1] = s->code_ptr;
201
+ ldst->label_ptr[0] = s->code_ptr;
202
s->code_ptr += 4;
203
- }
204
205
- /* TLB Hit. */
206
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0,
207
- offsetof(CPUTLBEntry, addend));
208
-#else
209
- if (a_mask) {
210
+ if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I64) {
211
+ /* cmp 4(TCG_REG_L0), addrhi */
212
+ tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi,
213
+ TCG_REG_L0, cmp_ofs + 4);
214
+
215
+ /* jne slow_path */
216
+ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
217
+ ldst->label_ptr[1] = s->code_ptr;
218
+ s->code_ptr += 4;
219
+ }
220
+
221
+ /* TLB Hit. */
222
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0,
223
+ offsetof(CPUTLBEntry, addend));
224
+ } else if (a_mask) {
225
ldst = new_ldst_label(s);
226
227
ldst->is_ld = is_ld;
228
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
229
ldst->label_ptr[0] = s->code_ptr;
230
s->code_ptr += 4;
231
}
232
-#endif
233
234
return ldst;
235
}
236
@@ -XXX,XX +XXX,XX @@ static void tcg_target_qemu_prologue(TCGContext *s)
237
tcg_out_push(s, tcg_target_callee_save_regs[i]);
238
}
239
240
-#if TCG_TARGET_REG_BITS == 32
241
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP,
242
- (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4);
243
- tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
244
- /* jmp *tb. */
245
- tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP,
246
- (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
247
- + stack_addend);
248
-#else
249
-# if !defined(CONFIG_SOFTMMU)
250
- if (guest_base) {
251
+ if (!tcg_use_softmmu && guest_base) {
252
int seg = setup_guest_base_seg();
253
if (seg != 0) {
254
x86_guest_base.seg = seg;
255
} else if (guest_base == (int32_t)guest_base) {
256
x86_guest_base.ofs = guest_base;
257
} else {
258
+ assert(TCG_TARGET_REG_BITS == 64);
259
/* Choose R12 because, as a base, it requires a SIB byte. */
260
x86_guest_base.index = TCG_REG_R12;
261
tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base.index, guest_base);
262
tcg_regset_set_reg(s->reserved_regs, x86_guest_base.index);
263
}
264
}
265
-# endif
266
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
267
- tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
268
- /* jmp *tb. */
269
- tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]);
270
-#endif
271
+
272
+ if (TCG_TARGET_REG_BITS == 32) {
273
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP,
274
+ (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4);
275
+ tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
276
+ /* jmp *tb. */
277
+ tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP,
278
+ (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
279
+ + stack_addend);
280
+ } else {
281
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
282
+ tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
283
+ /* jmp *tb. */
284
+ tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]);
285
+ }
286
287
/*
288
* Return path for goto_ptr. Set return value to 0, a-la exit_tb,
33
--
289
--
34
2.25.1
290
2.34.1
35
291
36
292
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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