Series comparison

-[PULL 00/15] riscv-to-apply queue
+[PULL 0/2] riscv-to-apply queue
-The following changes since commit 20c1df5476e1e9b5d3f5b94f9f3ce01d21f14c46:
+From: Alistair Francis <alistair.francis@wdc.com>
-  Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200713-pull-request' into staging (2020-07-13 16:58:44 +0100)
+The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1:
   Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200713
+  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122
-for you to fetch changes up to cfad709bceb629a4ebeb5d8a3acd1871b9a6436b:
+for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3:
-  target/riscv: Fix pmp NA4 implementation (2020-07-13 17:25:37 -0700)
+  hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000)
 ----------------------------------------------------------------
-This is a colection of bug fixes and small imrprovements for RISC-V.
+Seventh RISC-V PR for QEMU 6.2
-This includes some vector extensions fixes, a PMP bug fix, OpenTitan
+ - Deprecate IF_NONE for SiFive OTP
-UART bug fix and support for OpenSBI dynamic firmware.
+ - Don't reset SiFive OTP content
 ----------------------------------------------------------------
-Alexandre Mergnat (1):
+Philippe Mathieu-Daudé (1):
-      target/riscv: Fix pmp NA4 implementation
+      hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
-Alistair Francis (2):
+Thomas Huth (1):
-      hw/char: Convert the Ibex UART to use the qdev Clock model
+      hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
       hw/char: Convert the Ibex UART to use the registerfields API
-Atish Patra (4):
+ docs/about/deprecated.rst |  6 ++++++
-      riscv: Unify Qemu's reset vector code path
+ hw/misc/sifive_u_otp.c    | 22 +++++++++++++---------
-      RISC-V: Copy the fdt in dram instead of ROM
+files changed, 19 insertions(+), 9 deletions(-)
       riscv: Add opensbi firmware dynamic support
       RISC-V: Support 64 bit start address
-Bin Meng (3):
-      MAINTAINERS: Add an entry for OpenSBI firmware
-      hw/riscv: virt: Sort the SoC memmap table entries
-      hw/riscv: Modify MROM size to end at 0x10000
-Frank Chang (4):
-      target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
-      target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
-      target/riscv: fix return value of do_opivx_widen()
-      target/riscv: fix vill bit index in vtype register
-Liao Pingfang (1):
-      tcg/riscv: Remove superfluous breaks
- include/hw/char/ibex_uart.h             |  79 ++++++++--------
- include/hw/riscv/boot.h                 |   7 ++
- include/hw/riscv/boot_opensbi.h         |  58 ++++++++++++
- target/riscv/cpu.h                      |   2 +-
- hw/char/ibex_uart.c                     | 158 ++++++++++++++++++--------------
- hw/riscv/boot.c                         | 107 +++++++++++++++++++++
- hw/riscv/sifive_u.c                     |  53 ++++++-----
- hw/riscv/spike.c                        |  59 ++++--------
- hw/riscv/virt.c                         |  63 ++++---------
- target/riscv/insn_trans/trans_rvv.inc.c |   9 +-
- target/riscv/pmp.c                      |   2 +-
- tcg/riscv/tcg-target.inc.c              |   2 -
- MAINTAINERS                             |   7 ++
-files changed, 387 insertions(+), 219 deletions(-)
- create mode 100644 include/hw/riscv/boot_opensbi.h

-[PULL 01/15] MAINTAINERS: Add an entry for OpenSBI firmware
+Deleted patch
-From: Bin Meng <bmeng.cn@gmail.com>
-List me as the maintainer for OpenSBI firmware related files.
-Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-Id: <1593177220-28143-1-git-send-email-bmeng.cn@gmail.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- MAINTAINERS | 7 +++++++
-file changed, 7 insertions(+)
-diff --git a/MAINTAINERS b/MAINTAINERS
-index XXXXXXX..XXXXXXX 100644
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ F: hw/i386/intel_iommu.c
- F: hw/i386/intel_iommu_internal.h
- F: include/hw/i386/intel_iommu.h
-+OpenSBI Firmware
-+M: Bin Meng <bmeng.cn@gmail.com>
-+S: Supported
-+F: pc-bios/opensbi-*
-+F: .gitlab-ci.d/opensbi.yml
-+F: .gitlab-ci.d/opensbi/
-+
- Usermode Emulation
- ------------------
- Overall usermode emulation
---
-.27.0

-[PULL 02/15] hw/riscv: virt: Sort the SoC memmap table entries
+Deleted patch
-From: Bin Meng <bin.meng@windriver.com>
-Adjust the PCIe memory maps to follow the order.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1593746511-19517-1-git-send-email-bmeng.cn@gmail.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/riscv/virt.c | 6 +++---
-file changed, 3 insertions(+), 3 deletions(-)
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
-     [VIRT_TEST] =        {   0x100000,        0x1000 },
-     [VIRT_RTC] =         {   0x101000,        0x1000 },
-     [VIRT_CLINT] =       {  0x2000000,       0x10000 },
-+    [VIRT_PCIE_PIO] =    {  0x3000000,       0x10000 },
-     [VIRT_PLIC] =        {  0xc000000,     0x4000000 },
-     [VIRT_UART0] =       { 0x10000000,         0x100 },
-     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
-     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
--    [VIRT_DRAM] =        { 0x80000000,           0x0 },
--    [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
--    [VIRT_PCIE_PIO] =    { 0x03000000,    0x00010000 },
-     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
-+    [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
-+    [VIRT_DRAM] =        { 0x80000000,           0x0 },
- };
- #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
---
-.27.0

-[PULL 03/15] riscv: Unify Qemu's reset vector code path
+Deleted patch
-From: Atish Patra <atish.patra@wdc.com>
-Currently, all riscv machines except sifive_u have identical reset vector
-code implementations with memory addresses being different for all machines.
-They can be easily combined into a single function in common code.
-Move it to common function and let all the machines use the common function.
-Signed-off-by: Atish Patra <atish.patra@wdc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bin.meng@windriver.com>
-Tested-by: Bin Meng <bin.meng@windriver.com>
-Message-Id: <20200701183949.398134-2-atish.patra@wdc.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/hw/riscv/boot.h |  2 ++
- hw/riscv/boot.c         | 46 +++++++++++++++++++++++++++++++++++++++++
- hw/riscv/sifive_u.c     |  1 -
- hw/riscv/spike.c        | 41 +++---------------------------------
- hw/riscv/virt.c         | 40 +++--------------------------------
-files changed, 54 insertions(+), 76 deletions(-)
-diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/boot.h
-+++ b/include/hw/riscv/boot.h
-@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
-                                symbol_fn_t sym_cb);
- hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
-                          uint64_t kernel_entry, hwaddr *start);
-+void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base,
-+                               hwaddr rom_size, void *fdt);
- #endif /* RISCV_BOOT_H */
-diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/boot.c
-+++ b/hw/riscv/boot.c
-@@ -XXX,XX +XXX,XX @@
- #include "hw/loader.h"
- #include "hw/riscv/boot.h"
- #include "elf.h"
-+#include "sysemu/device_tree.h"
- #include "sysemu/qtest.h"
-+#include <libfdt.h>
-+
- #if defined(TARGET_RISCV32)
- # define KERNEL_BOOT_ADDRESS 0x80400000
- #else
-@@ -XXX,XX +XXX,XX @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
-     return *start + size;
- }
-+
-+void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
-+                               hwaddr rom_size, void *fdt)
-+{
-+    int i;
-+
-+    /* reset vector */
-+    uint32_t reset_vec[8] = {
-+        0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
-+        0x02028593,                  /*     addi   a1, t0, %pcrel_lo(1b) */
-+        0xf1402573,                  /*     csrr   a0, mhartid  */
-+#if defined(TARGET_RISCV32)
-+        0x0182a283,                  /*     lw     t0, 24(t0) */
-+#elif defined(TARGET_RISCV64)
-+        0x0182b283,                  /*     ld     t0, 24(t0) */
-+#endif
-+        0x00028067,                  /*     jr     t0 */
-+        0x00000000,
-+        start_addr,                  /* start: .dword */
-+        0x00000000,
-+                                     /* dtb: */
-+    };
-+
-+    /* copy in the reset vector in little_endian byte order */
-+    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
-+        reset_vec[i] = cpu_to_le32(reset_vec[i]);
-+    }
-+    rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
-+                          rom_base, &address_space_memory);
-+
-+    /* copy in the device tree */
-+    if (fdt_pack(fdt) || fdt_totalsize(fdt) >
-+        rom_size - sizeof(reset_vec)) {
-+        error_report("not enough space to store device-tree");
-+        exit(1);
-+    }
-+    qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
-+    rom_add_blob_fixed_as("mrom.fdt", fdt, fdt_totalsize(fdt),
-+                           rom_base + sizeof(reset_vec),
-+                           &address_space_memory);
-+
-+    return;
-+}
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_u.c
-+++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@
- #include "sysemu/device_tree.h"
- #include "sysemu/runstate.h"
- #include "sysemu/sysemu.h"
--#include "exec/address-spaces.h"
- #include <libfdt.h>
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
-+++ b/hw/riscv/spike.c
-@@ -XXX,XX +XXX,XX @@
- #include "sysemu/device_tree.h"
- #include "sysemu/qtest.h"
- #include "sysemu/sysemu.h"
--#include "exec/address-spaces.h"
--
--#include <libfdt.h>
- #if defined(TARGET_RISCV32)
- # define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf"
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-     MemoryRegion *system_memory = get_system_memory();
-     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
-     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
--    int i;
-     unsigned int smp_cpus = machine->smp.cpus;
-     /* Initialize SOC */
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-         }
-     }
--    /* reset vector */
--    uint32_t reset_vec[8] = {
--        0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
--        0x02028593,                  /*     addi   a1, t0, %pcrel_lo(1b) */
--        0xf1402573,                  /*     csrr   a0, mhartid  */
--#if defined(TARGET_RISCV32)
--        0x0182a283,                  /*     lw     t0, 24(t0) */
--#elif defined(TARGET_RISCV64)
--        0x0182b283,                  /*     ld     t0, 24(t0) */
--#endif
--        0x00028067,                  /*     jr     t0 */
--        0x00000000,
--        memmap[SPIKE_DRAM].base,     /* start: .dword DRAM_BASE */
--        0x00000000,
--                                     /* dtb: */
--    };
--
--    /* copy in the reset vector in little_endian byte order */
--    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
--        reset_vec[i] = cpu_to_le32(reset_vec[i]);
--    }
--    rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
--                          memmap[SPIKE_MROM].base, &address_space_memory);
--
--    /* copy in the device tree */
--    if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
--            memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
--        error_report("not enough space to store device-tree");
--        exit(1);
--    }
--    qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
--    rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
--                          memmap[SPIKE_MROM].base + sizeof(reset_vec),
--                          &address_space_memory);
-+    /* load the reset vector */
-+    riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base,
-+                              memmap[SPIKE_MROM].size, s->fdt);
-     /* initialize HTIF using symbols found in load_kernel */
-     htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@
- #include "sysemu/arch_init.h"
- #include "sysemu/device_tree.h"
- #include "sysemu/sysemu.h"
--#include "exec/address-spaces.h"
- #include "hw/pci/pci.h"
- #include "hw/pci-host/gpex.h"
--#include <libfdt.h>
--
- #if defined(TARGET_RISCV32)
- # define BIOS_FILENAME "opensbi-riscv32-virt-fw_jump.bin"
- #else
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
-         start_addr = virt_memmap[VIRT_FLASH].base;
-     }
--    /* reset vector */
--    uint32_t reset_vec[8] = {
--        0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
--        0x02028593,                  /*     addi   a1, t0, %pcrel_lo(1b) */
--        0xf1402573,                  /*     csrr   a0, mhartid  */
--#if defined(TARGET_RISCV32)
--        0x0182a283,                  /*     lw     t0, 24(t0) */
--#elif defined(TARGET_RISCV64)
--        0x0182b283,                  /*     ld     t0, 24(t0) */
--#endif
--        0x00028067,                  /*     jr     t0 */
--        0x00000000,
--        start_addr,                  /* start: .dword */
--        0x00000000,
--                                     /* dtb: */
--    };
--
--    /* copy in the reset vector in little_endian byte order */
--    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
--        reset_vec[i] = cpu_to_le32(reset_vec[i]);
--    }
--    rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
--                          memmap[VIRT_MROM].base, &address_space_memory);
--
--    /* copy in the device tree */
--    if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
--            memmap[VIRT_MROM].size - sizeof(reset_vec)) {
--        error_report("not enough space to store device-tree");
--        exit(1);
--    }
--    qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
--    rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
--                          memmap[VIRT_MROM].base + sizeof(reset_vec),
--                          &address_space_memory);
-+    /* load the reset vector */
-+    riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base,
-+                              virt_memmap[VIRT_MROM].size, s->fdt);
-     /* create PLIC hart topology configuration string */
-     plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
---
-.27.0

-[PULL 15/15] target/riscv: Fix pmp NA4 implementation
+[PULL 1/2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
-From: Alexandre Mergnat <amergnat@baylibre.com>
+From: Thomas Huth <thuth@redhat.com>
-The end address calculation for NA4 mode is wrong because the address
+Configuring a drive with "if=none" is meant for creation of a backend
-used isn't shifted.
+only, it should not get automatically assigned to a device frontend.
 Use "if=pflash" for the One-Time-Programmable device instead (like
 it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c).
-It doesn't watch 4 bytes but a huge range because the end address
+Since the old way of configuring the device has already been published
-calculation is wrong.
+with the previous QEMU versions, we cannot remove this immediately, but
 have to deprecate it and support it for at least two more releases.
-The solution is to use the shifted address calculated for start address
+Signed-off-by: Thomas Huth <thuth@redhat.com>
-variable.
+Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Markus Armbruster <armbru@redhat.com>
 Modifications are tested on Zephyr OS userspace test suite which works
 for other RISC-V boards (E31 and E34 core).
 Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20200706084550.24117-1-amergnat@baylibre.com
+Message-id: 20211119102549.217755-1-thuth@redhat.com
 Message-Id: <20200706084550.24117-1-amergnat@baylibre.com>
 [ Changes by AF:
  - Improve the commit title and message
 ]
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/pmp.c | 2 +-
+ docs/about/deprecated.rst | 6 ++++++
-file changed, 1 insertion(+), 1 deletion(-)
+ hw/misc/sifive_u_otp.c    | 9 ++++++++-
 files changed, 14 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
+diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.c
+--- a/docs/about/deprecated.rst
-+++ b/target/riscv/pmp.c
++++ b/docs/about/deprecated.rst
-@@ -XXX,XX +XXX,XX @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
+@@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``.
+ However, short-form booleans are deprecated and full explicit ``arg_name=on``
-     case PMP_AMATCH_NA4:
+ form is preferred.
-         sa = this_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
--        ea = (this_addr + 4u) - 1u;
++``-drive if=none`` for the sifive_u OTP device (since 6.2)
-+        ea = (sa + 4u) - 1u;
++''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
-         break;
++
++Using ``-drive if=none`` to configure the OTP device of the sifive_u
-     case PMP_AMATCH_NAPOT:
++RISC-V machine is deprecated. Use ``-drive if=pflash`` instead.
 +
  QEMU Machine Protocol (QMP) commands
  ------------------------------------
 diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/sifive_u_otp.c
 +++ b/hw/misc/sifive_u_otp.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
                            TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
      sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
 -    dinfo = drive_get_next(IF_NONE);
 +    dinfo = drive_get_next(IF_PFLASH);
 +    if (!dinfo) {
 +        dinfo = drive_get_next(IF_NONE);
 +        if (dinfo) {
 +            warn_report("using \"-drive if=none\" for the OTP is deprecated, "
 +                        "use \"-drive if=pflash\" instead.");
 +        }
 +    }
      if (dinfo) {
          int ret;
          uint64_t perm;
 --
-.27.0
+.31.1

-[PULL 04/15] RISC-V: Copy the fdt in dram instead of ROM
+[PULL 2/2] hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
-From: Atish Patra <atish.patra@wdc.com>
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Currently, the fdt is copied to the ROM after the reset vector. The firmware
+Once a "One Time Programmable" is programmed, it shouldn't be reset.
 has to copy it to DRAM. Instead of this, directly copy the device tree to a
 pre-computed dram address. The device tree load address should be as far as
 possible from kernel and initrd images. That's why it is kept at the end of
 the DRAM or 4GB whichever is lesser.
-Signed-off-by: Atish Patra <atish.patra@wdc.com>
+Do not re-initialize the OTP content in the DeviceReset handler,
 initialize it once in the DeviceRealize one.
 Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP")
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bin.meng@windriver.com>
+Message-Id: <20211119104757.331579-1-f4bug@amsat.org>
 Tested-by: Bin Meng <bin.meng@windriver.com>
 Message-Id: <20200701183949.398134-3-atish.patra@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/boot.h |  4 +++-
+ hw/misc/sifive_u_otp.c | 13 +++++--------
- hw/riscv/boot.c         | 53 +++++++++++++++++++++++++++++------------
+file changed, 5 insertions(+), 8 deletions(-)
  hw/riscv/sifive_u.c     | 28 ++++++++++------------
  hw/riscv/spike.c        |  7 +++++-
  hw/riscv/virt.c         |  7 +++++-
 files changed, 66 insertions(+), 33 deletions(-)
-diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
+diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/boot.h
+--- a/hw/misc/sifive_u_otp.c
-+++ b/include/hw/riscv/boot.h
++++ b/hw/misc/sifive_u_otp.c
-@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
+@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
-                                symbol_fn_t sym_cb);
- hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
+             if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
-                          uint64_t kernel_entry, hwaddr *start);
+                 error_setg(errp, "failed to read the initial flash content");
-+uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
++                return;
- void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base,
+             }
 -                               hwaddr rom_size, void *fdt);
 +                               hwaddr rom_size,
 +                               uint32_t fdt_load_addr, void *fdt);
  #endif /* RISCV_BOOT_H */
 diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/boot.c
 +++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
      return *start + size;
  }
 +uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
 +{
 +    uint32_t temp, fdt_addr;
 +    hwaddr dram_end = dram_base + mem_size;
 +    int fdtsize = fdt_totalsize(fdt);
 +
 +    if (fdtsize <= 0) {
 +        error_report("invalid device-tree");
 +        exit(1);
 +    }
 +
 +    /*
 +     * We should put fdt as far as possible to avoid kernel/initrd overwriting
 +     * its content. But it should be addressable by 32 bit system as well.
 +     * Thus, put it at an aligned address that less than fdt size from end of
 +     * dram or 4GB whichever is lesser.
 +     */
 +    temp = MIN(dram_end, 4096 * MiB);
 +    fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
 +
 +    fdt_pack(fdt);
 +    /* copy in the device tree */
 +    qemu_fdt_dumpdtb(fdt, fdtsize);
 +
 +    rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
 +                          &address_space_memory);
 +
 +    return fdt_addr;
 +}
 +
  void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
 -                               hwaddr rom_size, void *fdt)
 +                               hwaddr rom_size,
 +                               uint32_t fdt_load_addr, void *fdt)
  {
      int i;
      /* reset vector */
 -    uint32_t reset_vec[8] = {
 +    uint32_t reset_vec[10] = {
 x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
 -        0x02028593,                  /*     addi   a1, t0, %pcrel_lo(1b) */
 xf1402573,                  /*     csrr   a0, mhartid  */
  #if defined(TARGET_RISCV32)
 +        0x0202a583,                  /*     lw     a1, 32(t0) */
 x0182a283,                  /*     lw     t0, 24(t0) */
  #elif defined(TARGET_RISCV64)
 +        0x0202b583,                  /*     ld     a1, 32(t0) */
 x0182b283,                  /*     ld     t0, 24(t0) */
  #endif
 x00028067,                  /*     jr     t0 */
 x00000000,
          start_addr,                  /* start: .dword */
 +        0x00000000,
 +        fdt_load_addr,               /* fdt_laddr: .dword */
 x00000000,
                                       /* dtb: */
      };
      /* copy in the reset vector in little_endian byte order */
 -    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
 +    for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
          reset_vec[i] = cpu_to_le32(reset_vec[i]);
      }
      rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
                            rom_base, &address_space_memory);
 -    /* copy in the device tree */
 -    if (fdt_pack(fdt) || fdt_totalsize(fdt) >
 -        rom_size - sizeof(reset_vec)) {
 -        error_report("not enough space to store device-tree");
 -        exit(1);
 -    }
 -    qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
 -    rom_add_blob_fixed_as("mrom.fdt", fdt, fdt_totalsize(fdt),
 -                           rom_base + sizeof(reset_vec),
 -                           &address_space_memory);
 -
      return;
  }
 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_u.c
 +++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
      MemoryRegion *flash0 = g_new(MemoryRegion, 1);
      target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
      int i;
 +    uint32_t fdt_load_addr;
      /* Initialize SoC */
      object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
          }
      }
+-}
 +    /* Compute the fdt load address in dram */
 +    fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
 +                                   machine->ram_size, s->fdt);
 +
      /* reset vector */
 -    uint32_t reset_vec[8] = {
 +    uint32_t reset_vec[11] = {
          s->msel,                       /* MSEL pin state */
 x00000297,                    /* 1:  auipc  t0, %pcrel_hi(dtb) */
 -        0x01c28593,                    /*     addi   a1, t0, %pcrel_lo(1b) */
 xf1402573,                    /*     csrr   a0, mhartid  */
  #if defined(TARGET_RISCV32)
 +        0x0202a583,                    /*     lw     a1, 32(t0) */
 x0182a283,                    /*     lw     t0, 24(t0) */
  #elif defined(TARGET_RISCV64)
 -        0x0182e283,                    /*     lwu    t0, 24(t0) */
 +        0x0202b583,                    /*     ld     a1, 32(t0) */
 +        0x0182b283,                    /*     ld     t0, 24(t0) */
  #endif
 x00028067,                    /*     jr     t0 */
 x00000000,
          start_addr,                    /* start: .dword */
 +        0x00000000,
 +        fdt_load_addr,                 /* fdt_laddr: .dword */
 +        0x00000000,
                                         /* dtb: */
      };
      /* copy in the reset vector in little_endian byte order */
 -    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
 +    for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
          reset_vec[i] = cpu_to_le32(reset_vec[i]);
      }
      rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
                            memmap[SIFIVE_U_MROM].base, &address_space_memory);
 -
--    /* copy in the device tree */
+-static void sifive_u_otp_reset(DeviceState *dev)
--    if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
+-{
--            memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) {
+-    SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
--        error_report("not enough space to store device-tree");
--        exit(1);
+     /* Initialize all fuses' initial value to 0xFFs */
--    }
+     memset(s->fuse, 0xff, sizeof(s->fuse));
--    qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
+@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
--    rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
+         serial_data = s->serial;
--                          memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
+         if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
--                          &address_space_memory);
+                        &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
- }
+-            error_report("write error index<%d>", index);
++            error_setg(errp, "failed to write index<%d>", index);
- static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
++            return;
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
+         }
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
+         serial_data = ~(s->serial);
-+++ b/hw/riscv/spike.c
+         if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
+                        &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
-     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+-            error_report("write error index<%d>", index + 1);
-     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
++            error_setg(errp, "failed to write index<%d>", index + 1);
-     unsigned int smp_cpus = machine->smp.cpus;
++            return;
 +    uint32_t fdt_load_addr;
      /* Initialize SOC */
      object_initialize_child(OBJECT(machine), "soc", &s->soc,
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
          }
      }
-+    /* Compute the fdt load address in dram */
+@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
-+    fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
-+                                   machine->ram_size, s->fdt);
+     device_class_set_props(dc, sifive_u_otp_properties);
-     /* load the reset vector */
+     dc->realize = sifive_u_otp_realize;
-     riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base,
+-    dc->reset = sifive_u_otp_reset;
--                              memmap[SPIKE_MROM].size, s->fdt);
+ }
-+                              memmap[SPIKE_MROM].size,
-+                              fdt_load_addr, s->fdt);
+ static const TypeInfo sifive_u_otp_info = {
      /* initialize HTIF using symbols found in load_kernel */
      htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
      char *plic_hart_config;
      size_t plic_hart_config_len;
      target_ulong start_addr = memmap[VIRT_DRAM].base;
 +    uint32_t fdt_load_addr;
      int i;
      unsigned int smp_cpus = machine->smp.cpus;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
          start_addr = virt_memmap[VIRT_FLASH].base;
      }
 +    /* Compute the fdt load address in dram */
 +    fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
 +                                   machine->ram_size, s->fdt);
      /* load the reset vector */
      riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base,
 -                              virt_memmap[VIRT_MROM].size, s->fdt);
 +                              virt_memmap[VIRT_MROM].size,
 +                              fdt_load_addr, s->fdt);
      /* create PLIC hart topology configuration string */
      plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
 --
-.27.0
+.31.1

-[PULL 05/15] riscv: Add opensbi firmware dynamic support
+Deleted patch
-From: Atish Patra <atish.patra@wdc.com>
-OpenSBI is the default firmware in Qemu and has various firmware loading
-options. Currently, qemu loader uses fw_jump which has a compile time
-pre-defined address where fdt & kernel image must reside. This puts a
-constraint on image size of the Linux kernel depending on the fdt location
-and available memory. However, fw_dynamic allows the loader to specify
-the next stage location (i.e. Linux kernel/U-Boot) in memory and other
-configurable boot options available in OpenSBI.
-Add support for OpenSBI dynamic firmware loading support. This doesn't
-break existing setup and fw_jump will continue to work as it is. Any
-other firmware will continue to work without any issues as long as it
-doesn't expect anything specific from loader in "a2" register.
-Signed-off-by: Atish Patra <atish.patra@wdc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bin.meng@windriver.com>
-Tested-by: Bin Meng <bin.meng@windriver.com>
-Message-Id: <20200701183949.398134-4-atish.patra@wdc.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/hw/riscv/boot.h         |  5 ++-
- include/hw/riscv/boot_opensbi.h | 58 +++++++++++++++++++++++++++++++++
- hw/riscv/boot.c                 | 42 +++++++++++++++++++++---
- hw/riscv/sifive_u.c             | 20 +++++++++---
- hw/riscv/spike.c                | 13 ++++++--
- hw/riscv/virt.c                 | 12 +++++--
-files changed, 134 insertions(+), 16 deletions(-)
- create mode 100644 include/hw/riscv/boot_opensbi.h
-diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/boot.h
-+++ b/include/hw/riscv/boot.h
-@@ -XXX,XX +XXX,XX @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
-                          uint64_t kernel_entry, hwaddr *start);
- uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
- void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base,
--                               hwaddr rom_size,
-+                               hwaddr rom_size, uint64_t kernel_entry,
-                                uint32_t fdt_load_addr, void *fdt);
-+void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size,
-+                                  uint32_t reset_vec_size,
-+                                  uint64_t kernel_entry);
- #endif /* RISCV_BOOT_H */
-diff --git a/include/hw/riscv/boot_opensbi.h b/include/hw/riscv/boot_opensbi.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/include/hw/riscv/boot_opensbi.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: BSD-2-Clause */
-+/*
-+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
-+ *
-+ * Based on include/sbi/{fw_dynamic.h,sbi_scratch.h} from the OpenSBI project.
-+ */
-+#ifndef OPENSBI_H
-+#define OPENSBI_H
-+
-+/** Expected value of info magic ('OSBI' ascii string in hex) */
-+#define FW_DYNAMIC_INFO_MAGIC_VALUE     0x4942534f
-+
-+/** Maximum supported info version */
-+#define FW_DYNAMIC_INFO_VERSION         0x2
-+
-+/** Possible next mode values */
-+#define FW_DYNAMIC_INFO_NEXT_MODE_U     0x0
-+#define FW_DYNAMIC_INFO_NEXT_MODE_S     0x1
-+#define FW_DYNAMIC_INFO_NEXT_MODE_M     0x3
-+
-+enum sbi_scratch_options {
-+    /** Disable prints during boot */
-+    SBI_SCRATCH_NO_BOOT_PRINTS = (1 << 0),
-+    /** Enable runtime debug prints */
-+    SBI_SCRATCH_DEBUG_PRINTS = (1 << 1),
-+};
-+
-+/** Representation dynamic info passed by previous booting stage */
-+struct fw_dynamic_info {
-+    /** Info magic */
-+    target_long magic;
-+    /** Info version */
-+    target_long version;
-+    /** Next booting stage address */
-+    target_long next_addr;
-+    /** Next booting stage mode */
-+    target_long next_mode;
-+    /** Options for OpenSBI library */
-+    target_long options;
-+    /**
-+     * Preferred boot HART id
-+     *
-+     * It is possible that the previous booting stage uses same link
-+     * address as the FW_DYNAMIC firmware. In this case, the relocation
-+     * lottery mechanism can potentially overwrite the previous booting
-+     * stage while other HARTs are still running in the previous booting
-+     * stage leading to boot-time crash. To avoid this boot-time crash,
-+     * the previous booting stage can specify last HART that will jump
-+     * to the FW_DYNAMIC firmware as the preferred boot HART.
-+     *
-+     * To avoid specifying a preferred boot HART, the previous booting
-+     * stage can set it to -1UL which will force the FW_DYNAMIC firmware
-+     * to use the relocation lottery mechanism.
-+     */
-+    target_long boot_hart;
-+};
-+
-+#endif
-diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/boot.c
-+++ b/hw/riscv/boot.c
-@@ -XXX,XX +XXX,XX @@
- #include "hw/boards.h"
- #include "hw/loader.h"
- #include "hw/riscv/boot.h"
-+#include "hw/riscv/boot_opensbi.h"
- #include "elf.h"
- #include "sysemu/device_tree.h"
- #include "sysemu/qtest.h"
-@@ -XXX,XX +XXX,XX @@
- #if defined(TARGET_RISCV32)
- # define KERNEL_BOOT_ADDRESS 0x80400000
-+#define fw_dynamic_info_data(__val)     cpu_to_le32(__val)
- #else
- # define KERNEL_BOOT_ADDRESS 0x80200000
-+#define fw_dynamic_info_data(__val)     cpu_to_le64(__val)
- #endif
- void riscv_find_and_load_firmware(MachineState *machine,
-@@ -XXX,XX +XXX,XX @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
-     return fdt_addr;
- }
-+void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size,
-+                              uint32_t reset_vec_size, uint64_t kernel_entry)
-+{
-+    struct fw_dynamic_info dinfo;
-+    size_t dinfo_len;
-+
-+    dinfo.magic = fw_dynamic_info_data(FW_DYNAMIC_INFO_MAGIC_VALUE);
-+    dinfo.version = fw_dynamic_info_data(FW_DYNAMIC_INFO_VERSION);
-+    dinfo.next_mode = fw_dynamic_info_data(FW_DYNAMIC_INFO_NEXT_MODE_S);
-+    dinfo.next_addr = fw_dynamic_info_data(kernel_entry);
-+    dinfo.options = 0;
-+    dinfo.boot_hart = 0;
-+    dinfo_len = sizeof(dinfo);
-+
-+    /**
-+     * copy the dynamic firmware info. This information is specific to
-+     * OpenSBI but doesn't break any other firmware as long as they don't
-+     * expect any certain value in "a2" register.
-+     */
-+    if (dinfo_len > (rom_size - reset_vec_size)) {
-+        error_report("not enough space to store dynamic firmware info");
-+        exit(1);
-+    }
-+
-+    rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len,
-+                           rom_base + reset_vec_size,
-+                           &address_space_memory);
-+}
-+
- void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
--                               hwaddr rom_size,
-+                               hwaddr rom_size, uint64_t kernel_entry,
-                                uint32_t fdt_load_addr, void *fdt)
- {
-     int i;
-     /* reset vector */
-     uint32_t reset_vec[10] = {
--        0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
-+        0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(fw_dyn) */
-+        0x02828613,                  /*     addi   a2, t0, %pcrel_lo(1b) */
-xf1402573,                  /*     csrr   a0, mhartid  */
- #if defined(TARGET_RISCV32)
-x0202a583,                  /*     lw     a1, 32(t0) */
-@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
-x0182b283,                  /*     ld     t0, 24(t0) */
- #endif
-x00028067,                  /*     jr     t0 */
--        0x00000000,
-         start_addr,                  /* start: .dword */
-x00000000,
-         fdt_load_addr,               /* fdt_laddr: .dword */
-x00000000,
--                                     /* dtb: */
-+                                     /* fw_dyn: */
-     };
-     /* copy in the reset vector in little_endian byte order */
-@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
-     }
-     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
-                           rom_base, &address_space_memory);
-+    riscv_rom_copy_firmware_info(rom_base, rom_size, sizeof(reset_vec),
-+                                 kernel_entry);
-     return;
- }
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_u.c
-+++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
-     target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
-     int i;
-     uint32_t fdt_load_addr;
-+    uint64_t kernel_entry;
-     /* Initialize SoC */
-     object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
-     riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr, NULL);
-     if (machine->kernel_filename) {
--        uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
--                                                  NULL);
-+        kernel_entry = riscv_load_kernel(machine->kernel_filename, NULL);
-         if (machine->initrd_filename) {
-             hwaddr start;
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
-             qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
-                                   end);
-         }
-+    } else {
-+       /*
-+        * If dynamic firmware is used, it doesn't know where is the next mode
-+        * if kernel argument is not set.
-+        */
-+        kernel_entry = 0;
-     }
-     /* Compute the fdt load address in dram */
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
-     /* reset vector */
-     uint32_t reset_vec[11] = {
-         s->msel,                       /* MSEL pin state */
--        0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(dtb) */
-+        0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(fw_dyn) */
-+        0x02828613,                    /*     addi   a2, t0, %pcrel_lo(1b) */
-xf1402573,                    /*     csrr   a0, mhartid  */
- #if defined(TARGET_RISCV32)
-x0202a583,                    /*     lw     a1, 32(t0) */
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
-x0182b283,                    /*     ld     t0, 24(t0) */
- #endif
-x00028067,                    /*     jr     t0 */
--        0x00000000,
-         start_addr,                    /* start: .dword */
-x00000000,
-         fdt_load_addr,                 /* fdt_laddr: .dword */
-x00000000,
--                                       /* dtb: */
-+                                       /* fw_dyn: */
-     };
-     /* copy in the reset vector in little_endian byte order */
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
-     }
-     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
-                           memmap[SIFIVE_U_MROM].base, &address_space_memory);
-+
-+    riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base,
-+                                 memmap[SIFIVE_U_MROM].size,
-+                                 sizeof(reset_vec), kernel_entry);
- }
- static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
-+++ b/hw/riscv/spike.c
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
-     unsigned int smp_cpus = machine->smp.cpus;
-     uint32_t fdt_load_addr;
-+    uint64_t kernel_entry;
-     /* Initialize SOC */
-     object_initialize_child(OBJECT(machine), "soc", &s->soc,
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-                                  htif_symbol_callback);
-     if (machine->kernel_filename) {
--        uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
--                                                  htif_symbol_callback);
-+        kernel_entry = riscv_load_kernel(machine->kernel_filename,
-+                                         htif_symbol_callback);
-         if (machine->initrd_filename) {
-             hwaddr start;
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-             qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
-                                   end);
-         }
-+    } else {
-+       /*
-+        * If dynamic firmware is used, it doesn't know where is the next mode
-+        * if kernel argument is not set.
-+        */
-+        kernel_entry = 0;
-     }
-     /* Compute the fdt load address in dram */
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-                                    machine->ram_size, s->fdt);
-     /* load the reset vector */
-     riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base,
--                              memmap[SPIKE_MROM].size,
-+                              memmap[SPIKE_MROM].size, kernel_entry,
-                               fdt_load_addr, s->fdt);
-     /* initialize HTIF using symbols found in load_kernel */
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
-     size_t plic_hart_config_len;
-     target_ulong start_addr = memmap[VIRT_DRAM].base;
-     uint32_t fdt_load_addr;
-+    uint64_t kernel_entry;
-     int i;
-     unsigned int smp_cpus = machine->smp.cpus;
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
-                                  memmap[VIRT_DRAM].base, NULL);
-     if (machine->kernel_filename) {
--        uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
--                                                  NULL);
-+        kernel_entry = riscv_load_kernel(machine->kernel_filename, NULL);
-         if (machine->initrd_filename) {
-             hwaddr start;
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
-             qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
-                                   end);
-         }
-+    } else {
-+       /*
-+        * If dynamic firmware is used, it doesn't know where is the next mode
-+        * if kernel argument is not set.
-+        */
-+        kernel_entry = 0;
-     }
-     if (drive_get(IF_PFLASH, 0, 0)) {
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
-                                    machine->ram_size, s->fdt);
-     /* load the reset vector */
-     riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base,
--                              virt_memmap[VIRT_MROM].size,
-+                              virt_memmap[VIRT_MROM].size, kernel_entry,
-                               fdt_load_addr, s->fdt);
-     /* create PLIC hart topology configuration string */
---
-.27.0

-[PULL 06/15] RISC-V: Support 64 bit start address
+Deleted patch
-From: Atish Patra <atish.patra@wdc.com>
-Even though the start address in ROM code is declared as a 64 bit address
-for RV64, it can't be used as upper bits are set to zero in ROM code.
-Update the ROM code correctly to reflect the 64bit value.
-Signed-off-by: Atish Patra <atish.patra@wdc.com>
-Reviewed-by: Bin Meng <bin.meng@windriver.com>
-Tested-by: Bin Meng <bin.meng@windriver.com>
-Message-Id: <20200701183949.398134-5-atish.patra@wdc.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/riscv/boot.c     | 6 +++++-
- hw/riscv/sifive_u.c | 6 +++++-
-files changed, 10 insertions(+), 2 deletions(-)
-diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/boot.c
-+++ b/hw/riscv/boot.c
-@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
-                                uint32_t fdt_load_addr, void *fdt)
- {
-     int i;
-+    uint32_t start_addr_hi32 = 0x00000000;
-+    #if defined(TARGET_RISCV64)
-+    start_addr_hi32 = start_addr >> 32;
-+    #endif
-     /* reset vector */
-     uint32_t reset_vec[10] = {
-x00000297,                  /* 1:  auipc  t0, %pcrel_hi(fw_dyn) */
-@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
- #endif
-x00028067,                  /*     jr     t0 */
-         start_addr,                  /* start: .dword */
--        0x00000000,
-+        start_addr_hi32,
-         fdt_load_addr,               /* fdt_laddr: .dword */
-x00000000,
-                                      /* fw_dyn: */
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_u.c
-+++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
-     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
-     MemoryRegion *flash0 = g_new(MemoryRegion, 1);
-     target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
-+    uint32_t start_addr_hi32 = 0x00000000;
-     int i;
-     uint32_t fdt_load_addr;
-     uint64_t kernel_entry;
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
-     /* Compute the fdt load address in dram */
-     fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
-                                    machine->ram_size, s->fdt);
-+    #if defined(TARGET_RISCV64)
-+    start_addr_hi32 = start_addr >> 32;
-+    #endif
-     /* reset vector */
-     uint32_t reset_vec[11] = {
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
- #endif
-x00028067,                    /*     jr     t0 */
-         start_addr,                    /* start: .dword */
--        0x00000000,
-+        start_addr_hi32,
-         fdt_load_addr,                 /* fdt_laddr: .dword */
-x00000000,
-                                        /* fw_dyn: */
---
-.27.0

-[PULL 07/15] hw/riscv: Modify MROM size to end at 0x10000
+Deleted patch
-From: Bin Meng <bin.meng@windriver.com>
-At present the size of Mask ROM for sifive_u / spike / virt machines
-is set to 0x11000, which ends at an unusual address. This changes the
-size to 0xf000 so that it ends at 0x10000.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-Id: <1594289144-24723-1-git-send-email-bmeng.cn@gmail.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/riscv/sifive_u.c | 2 +-
- hw/riscv/spike.c    | 2 +-
- hw/riscv/virt.c     | 2 +-
-files changed, 3 insertions(+), 3 deletions(-)
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_u.c
-+++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
-     hwaddr size;
- } sifive_u_memmap[] = {
-     [SIFIVE_U_DEBUG] =    {        0x0,      0x100 },
--    [SIFIVE_U_MROM] =     {     0x1000,    0x11000 },
-+    [SIFIVE_U_MROM] =     {     0x1000,     0xf000 },
-     [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },
-     [SIFIVE_U_L2LIM] =    {  0x8000000,  0x2000000 },
-     [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
-+++ b/hw/riscv/spike.c
-@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
-     hwaddr base;
-     hwaddr size;
- } spike_memmap[] = {
--    [SPIKE_MROM] =     {     0x1000,    0x11000 },
-+    [SPIKE_MROM] =     {     0x1000,     0xf000 },
-     [SPIKE_CLINT] =    {  0x2000000,    0x10000 },
-     [SPIKE_DRAM] =     { 0x80000000,        0x0 },
- };
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
-     hwaddr size;
- } virt_memmap[] = {
-     [VIRT_DEBUG] =       {        0x0,         0x100 },
--    [VIRT_MROM] =        {     0x1000,       0x11000 },
-+    [VIRT_MROM] =        {     0x1000,        0xf000 },
-     [VIRT_TEST] =        {   0x100000,        0x1000 },
-     [VIRT_RTC] =         {   0x101000,        0x1000 },
-     [VIRT_CLINT] =       {  0x2000000,       0x10000 },
---
-.27.0

-[PULL 08/15] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-gvec should provide vecop_list to avoid:
-"tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-Id: <20200710104920.13550-2-frank.chang@sifive.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn_trans/trans_rvv.inc.c | 5 +++++
-file changed, 5 insertions(+)
-diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.inc.c
-+++ b/target/riscv/insn_trans/trans_rvv.inc.c
-@@ -XXX,XX +XXX,XX @@ static void gen_rsub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
- static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs,
-                                TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
- {
-+    static const TCGOpcode vecop_list[] = { INDEX_op_sub_vec, 0 };
-     static const GVecGen2s rsub_op[4] = {
-         { .fni8 = gen_vec_rsub8_i64,
-           .fniv = gen_rsub_vec,
-           .fno = gen_helper_vec_rsubs8,
-+          .opt_opc = vecop_list,
-           .vece = MO_8 },
-         { .fni8 = gen_vec_rsub16_i64,
-           .fniv = gen_rsub_vec,
-           .fno = gen_helper_vec_rsubs16,
-+          .opt_opc = vecop_list,
-           .vece = MO_16 },
-         { .fni4 = gen_rsub_i32,
-           .fniv = gen_rsub_vec,
-           .fno = gen_helper_vec_rsubs32,
-+          .opt_opc = vecop_list,
-           .vece = MO_32 },
-         { .fni8 = gen_rsub_i64,
-           .fniv = gen_rsub_vec,
-           .fno = gen_helper_vec_rsubs64,
-+          .opt_opc = vecop_list,
-           .prefer_i64 = TCG_TARGET_REG_BITS == 64,
-           .vece = MO_64 },
-     };
---
-.27.0

-[PULL 09/15] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-Id: <20200710104920.13550-3-frank.chang@sifive.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.inc.c
-+++ b/target/riscv/insn_trans/trans_rvv.inc.c
-@@ -XXX,XX +XXX,XX @@ static void gen_vec_rsub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
- static void gen_vec_rsub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
- {
--    tcg_gen_vec_sub8_i64(d, b, a);
-+    tcg_gen_vec_sub16_i64(d, b, a);
- }
- static void gen_rsub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
---
-.27.0

-[PULL 10/15] target/riscv: fix return value of do_opivx_widen()
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-do_opivx_widen() should return false if check function returns false.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-Id: <20200710104920.13550-4-frank.chang@sifive.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.inc.c
-+++ b/target/riscv/insn_trans/trans_rvv.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
-     if (opivx_widen_check(s, a)) {
-         return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
-     }
--    return true;
-+    return false;
- }
- #define GEN_OPIVX_WIDEN_TRANS(NAME) \
---
-.27.0

-[PULL 11/15] target/riscv: fix vill bit index in vtype register
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-vill bit is at vtype[XLEN-1].
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-Id: <20200710104920.13550-5-frank.chang@sifive.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.h | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ FIELD(VTYPE, VLMUL, 0, 2)
- FIELD(VTYPE, VSEW, 2, 3)
- FIELD(VTYPE, VEDIV, 5, 2)
- FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
--FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 2, 1)
-+FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
- struct CPURISCVState {
-     target_ulong gpr[32];
---
-.27.0

-[PULL 12/15] hw/char: Convert the Ibex UART to use the qdev Clock model
+Deleted patch
-Conver the Ibex UART to use the recently added qdev-clock functions.
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: b0136fad870a29049959ec161c1217b967d7e19d.1594332223.git.alistair.francis@wdc.com
-Message-Id: <b0136fad870a29049959ec161c1217b967d7e19d.1594332223.git.alistair.francis@wdc.com>
----
- include/hw/char/ibex_uart.h |  3 +++
- hw/char/ibex_uart.c         | 30 +++++++++++++++++++++++++++---
-files changed, 30 insertions(+), 3 deletions(-)
-diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/ibex_uart.h
-+++ b/include/hw/char/ibex_uart.h
-@@ -XXX,XX +XXX,XX @@
- #define IBEX_UART_TIMEOUT_CTRL 0x2c
- #define IBEX_UART_TX_FIFO_SIZE 16
-+#define IBEX_UART_CLOCK 50000000 /* 50MHz clock */
- #define TYPE_IBEX_UART "ibex-uart"
- #define IBEX_UART(obj) \
-@@ -XXX,XX +XXX,XX @@ typedef struct {
-     uint32_t uart_val;
-     uint32_t uart_timeout_ctrl;
-+    Clock *f_clk;
-+
-     CharBackend chr;
-     qemu_irq tx_watermark;
-     qemu_irq rx_watermark;
-diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/char/ibex_uart.c
-+++ b/hw/char/ibex_uart.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/osdep.h"
- #include "hw/char/ibex_uart.h"
- #include "hw/irq.h"
-+#include "hw/qdev-clock.h"
- #include "hw/qdev-properties.h"
- #include "migration/vmstate.h"
- #include "qemu/log.h"
-@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
-     ibex_uart_update_irqs(s);
- }
-+static uint64_t ibex_uart_get_baud(IbexUartState *s)
-+{
-+    uint64_t baud;
-+
-+    baud = ((s->uart_ctrl & UART_CTRL_NCO) >> 16);
-+    baud *= clock_get_hz(s->f_clk);
-+    baud >>= 20;
-+
-+    return baud;
-+}
-+
- static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
-                                        unsigned int size)
- {
-@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
-                           "%s: UART_CTRL_RXBLVL is not supported\n", __func__);
-         }
-         if (value & UART_CTRL_NCO) {
--            uint64_t baud = ((value & UART_CTRL_NCO) >> 16);
--            baud *= 1000;
--            baud >>= 20;
-+            uint64_t baud = ibex_uart_get_baud(s);
-             s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;
-         }
-@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
-     }
- }
-+static void ibex_uart_clk_update(void *opaque)
-+{
-+    IbexUartState *s = opaque;
-+
-+    /* recompute uart's speed on clock change */
-+    uint64_t baud = ibex_uart_get_baud(s);
-+
-+    s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;
-+}
-+
- static void fifo_trigger_update(void *opaque)
- {
-     IbexUartState *s = opaque;
-@@ -XXX,XX +XXX,XX @@ static void ibex_uart_init(Object *obj)
- {
-     IbexUartState *s = IBEX_UART(obj);
-+    s->f_clk = qdev_init_clock_in(DEVICE(obj), "f_clock",
-+                                  ibex_uart_clk_update, s);
-+    clock_set_hz(s->f_clk, IBEX_UART_CLOCK);
-+
-     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_watermark);
-     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_watermark);
-     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_empty);
---
-.27.0

-[PULL 13/15] hw/char: Convert the Ibex UART to use the registerfields API
+Deleted patch
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 06372c9cdeec715077899e71c858d9f0a2a3395b.1594332223.git.alistair.francis@wdc.com
-Message-Id: <06372c9cdeec715077899e71c858d9f0a2a3395b.1594332223.git.alistair.francis@wdc.com>
----
- include/hw/char/ibex_uart.h |  76 ++++++++++-----------
- hw/char/ibex_uart.c         | 130 ++++++++++++++++++------------------
-files changed, 100 insertions(+), 106 deletions(-)
-diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/ibex_uart.h
-+++ b/include/hw/char/ibex_uart.h
-@@ -XXX,XX +XXX,XX @@
- #define HW_IBEX_UART_H
- #include "hw/sysbus.h"
-+#include "hw/registerfields.h"
- #include "chardev/char-fe.h"
- #include "qemu/timer.h"
--#define IBEX_UART_INTR_STATE   0x00
--    #define INTR_STATE_TX_WATERMARK (1 << 0)
--    #define INTR_STATE_RX_WATERMARK (1 << 1)
--    #define INTR_STATE_TX_EMPTY     (1 << 2)
--    #define INTR_STATE_RX_OVERFLOW  (1 << 3)
--#define IBEX_UART_INTR_ENABLE  0x04
--#define IBEX_UART_INTR_TEST    0x08
--
--#define IBEX_UART_CTRL         0x0c
--    #define UART_CTRL_TX_ENABLE     (1 << 0)
--    #define UART_CTRL_RX_ENABLE     (1 << 1)
--    #define UART_CTRL_NF            (1 << 2)
--    #define UART_CTRL_SLPBK         (1 << 4)
--    #define UART_CTRL_LLPBK         (1 << 5)
--    #define UART_CTRL_PARITY_EN     (1 << 6)
--    #define UART_CTRL_PARITY_ODD    (1 << 7)
--    #define UART_CTRL_RXBLVL        (3 << 8)
--    #define UART_CTRL_NCO           (0xFFFF << 16)
--
--#define IBEX_UART_STATUS       0x10
--    #define UART_STATUS_TXFULL  (1 << 0)
--    #define UART_STATUS_RXFULL  (1 << 1)
--    #define UART_STATUS_TXEMPTY (1 << 2)
--    #define UART_STATUS_RXIDLE  (1 << 4)
--    #define UART_STATUS_RXEMPTY (1 << 5)
--
--#define IBEX_UART_RDATA        0x14
--#define IBEX_UART_WDATA        0x18
--
--#define IBEX_UART_FIFO_CTRL    0x1c
--    #define FIFO_CTRL_RXRST          (1 << 0)
--    #define FIFO_CTRL_TXRST          (1 << 1)
--    #define FIFO_CTRL_RXILVL         (7 << 2)
--    #define FIFO_CTRL_RXILVL_SHIFT   (2)
--    #define FIFO_CTRL_TXILVL         (3 << 5)
--    #define FIFO_CTRL_TXILVL_SHIFT   (5)
--
--#define IBEX_UART_FIFO_STATUS  0x20
--#define IBEX_UART_OVRD         0x24
--#define IBEX_UART_VAL          0x28
--#define IBEX_UART_TIMEOUT_CTRL 0x2c
-+REG32(INTR_STATE, 0x00)
-+    FIELD(INTR_STATE, TX_WATERMARK, 0, 1)
-+    FIELD(INTR_STATE, RX_WATERMARK, 1, 1)
-+    FIELD(INTR_STATE, TX_EMPTY, 2, 1)
-+    FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
-+REG32(INTR_ENABLE, 0x04)
-+REG32(INTR_TEST, 0x08)
-+REG32(CTRL, 0x0C)
-+    FIELD(CTRL, TX_ENABLE, 0, 1)
-+    FIELD(CTRL, RX_ENABLE, 1, 1)
-+    FIELD(CTRL, NF, 2, 1)
-+    FIELD(CTRL, SLPBK, 4, 1)
-+    FIELD(CTRL, LLPBK, 5, 1)
-+    FIELD(CTRL, PARITY_EN, 6, 1)
-+    FIELD(CTRL, PARITY_ODD, 7, 1)
-+    FIELD(CTRL, RXBLVL, 8, 2)
-+    FIELD(CTRL, NCO, 16, 16)
-+REG32(STATUS, 0x10)
-+    FIELD(STATUS, TXFULL, 0, 1)
-+    FIELD(STATUS, RXFULL, 1, 1)
-+    FIELD(STATUS, TXEMPTY, 2, 1)
-+    FIELD(STATUS, RXIDLE, 4, 1)
-+    FIELD(STATUS, RXEMPTY, 5, 1)
-+REG32(RDATA, 0x14)
-+REG32(WDATA, 0x18)
-+REG32(FIFO_CTRL, 0x1c)
-+    FIELD(FIFO_CTRL, RXRST, 0, 1)
-+    FIELD(FIFO_CTRL, TXRST, 1, 1)
-+    FIELD(FIFO_CTRL, RXILVL, 2, 3)
-+    FIELD(FIFO_CTRL, TXILVL, 5, 2)
-+REG32(FIFO_STATUS, 0x20)
-+REG32(OVRD, 0x24)
-+REG32(VAL, 0x28)
-+REG32(TIMEOUT_CTRL, 0x2c)
- #define IBEX_UART_TX_FIFO_SIZE 16
- #define IBEX_UART_CLOCK 50000000 /* 50MHz clock */
-diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/char/ibex_uart.c
-+++ b/hw/char/ibex_uart.c
-@@ -XXX,XX +XXX,XX @@
- static void ibex_uart_update_irqs(IbexUartState *s)
- {
--    if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_TX_WATERMARK) {
-+    if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) {
-         qemu_set_irq(s->tx_watermark, 1);
-     } else {
-         qemu_set_irq(s->tx_watermark, 0);
-     }
--    if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_RX_WATERMARK) {
-+    if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_WATERMARK_MASK) {
-         qemu_set_irq(s->rx_watermark, 1);
-     } else {
-         qemu_set_irq(s->rx_watermark, 0);
-     }
--    if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_TX_EMPTY) {
-+    if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_EMPTY_MASK) {
-         qemu_set_irq(s->tx_empty, 1);
-     } else {
-         qemu_set_irq(s->tx_empty, 0);
-     }
--    if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_RX_OVERFLOW) {
-+    if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_OVERFLOW_MASK) {
-         qemu_set_irq(s->rx_overflow, 1);
-     } else {
-         qemu_set_irq(s->rx_overflow, 0);
-@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
- {
-     IbexUartState *s = opaque;
--    if (s->uart_ctrl & UART_CTRL_RX_ENABLE) {
-+    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
-         return 1;
-     }
-@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
- static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
- {
-     IbexUartState *s = opaque;
--    uint8_t rx_fifo_level = (s->uart_fifo_ctrl & FIFO_CTRL_RXILVL)
--                            >> FIFO_CTRL_RXILVL_SHIFT;
-+    uint8_t rx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_RXILVL_MASK)
-+                            >> R_FIFO_CTRL_RXILVL_SHIFT;
-     s->uart_rdata = *buf;
--    s->uart_status &= ~UART_STATUS_RXIDLE;
--    s->uart_status &= ~UART_STATUS_RXEMPTY;
-+    s->uart_status &= ~R_STATUS_RXIDLE_MASK;
-+    s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
-     if (size > rx_fifo_level) {
--        s->uart_intr_state |= INTR_STATE_RX_WATERMARK;
-+        s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
-     }
-     ibex_uart_update_irqs(s);
-@@ -XXX,XX +XXX,XX @@ static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond,
-                                void *opaque)
- {
-     IbexUartState *s = opaque;
--    uint8_t tx_fifo_level = (s->uart_fifo_ctrl & FIFO_CTRL_TXILVL)
--                            >> FIFO_CTRL_TXILVL_SHIFT;
-+    uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK)
-+                            >> R_FIFO_CTRL_TXILVL_SHIFT;
-     int ret;
-     /* instant drain the fifo when there's no back-end */
-@@ -XXX,XX +XXX,XX @@ static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond,
-     }
-     if (!s->tx_level) {
--        s->uart_status &= ~UART_STATUS_TXFULL;
--        s->uart_status |= UART_STATUS_TXEMPTY;
--        s->uart_intr_state |= INTR_STATE_TX_EMPTY;
--        s->uart_intr_state &= ~INTR_STATE_TX_WATERMARK;
-+        s->uart_status &= ~R_STATUS_TXFULL_MASK;
-+        s->uart_status |= R_STATUS_TXEMPTY_MASK;
-+        s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK;
-+        s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK;
-         ibex_uart_update_irqs(s);
-         return FALSE;
-     }
-@@ -XXX,XX +XXX,XX @@ static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond,
-     /* Clear the TX Full bit */
-     if (s->tx_level != IBEX_UART_TX_FIFO_SIZE) {
--        s->uart_status &= ~UART_STATUS_TXFULL;
-+        s->uart_status &= ~R_STATUS_TXFULL_MASK;
-     }
-     /* Disable the TX_WATERMARK IRQ */
-     if (s->tx_level < tx_fifo_level) {
--        s->uart_intr_state &= ~INTR_STATE_TX_WATERMARK;
-+        s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK;
-     }
-     /* Set TX empty */
-     if (s->tx_level == 0) {
--        s->uart_status |= UART_STATUS_TXEMPTY;
--        s->uart_intr_state |= INTR_STATE_TX_EMPTY;
-+        s->uart_status |= R_STATUS_TXEMPTY_MASK;
-+        s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK;
-     }
-     ibex_uart_update_irqs(s);
-@@ -XXX,XX +XXX,XX @@ static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf,
-                                int size)
- {
-     uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
--    uint8_t tx_fifo_level = (s->uart_fifo_ctrl & FIFO_CTRL_TXILVL)
--                            >> FIFO_CTRL_TXILVL_SHIFT;
-+    uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK)
-+                            >> R_FIFO_CTRL_TXILVL_SHIFT;
-     if (size > IBEX_UART_TX_FIFO_SIZE - s->tx_level) {
-         size = IBEX_UART_TX_FIFO_SIZE - s->tx_level;
-@@ -XXX,XX +XXX,XX @@ static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf,
-     s->tx_level += size;
-     if (s->tx_level > 0) {
--        s->uart_status &= ~UART_STATUS_TXEMPTY;
-+        s->uart_status &= ~R_STATUS_TXEMPTY_MASK;
-     }
-     if (s->tx_level >= tx_fifo_level) {
--        s->uart_intr_state |= INTR_STATE_TX_WATERMARK;
-+        s->uart_intr_state |= R_INTR_STATE_TX_WATERMARK_MASK;
-         ibex_uart_update_irqs(s);
-     }
-     if (s->tx_level == IBEX_UART_TX_FIFO_SIZE) {
--        s->uart_status |= UART_STATUS_TXFULL;
-+        s->uart_status |= R_STATUS_TXFULL_MASK;
-     }
-     timer_mod(s->fifo_trigger_handle, current_time +
-@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_get_baud(IbexUartState *s)
- {
-     uint64_t baud;
--    baud = ((s->uart_ctrl & UART_CTRL_NCO) >> 16);
-+    baud = ((s->uart_ctrl & R_CTRL_NCO_MASK) >> 16);
-     baud *= clock_get_hz(s->f_clk);
-     baud >>= 20;
-@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
-     IbexUartState *s = opaque;
-     uint64_t retvalue = 0;
--    switch (addr) {
--    case IBEX_UART_INTR_STATE:
-+    switch (addr >> 2) {
-+    case R_INTR_STATE:
-         retvalue = s->uart_intr_state;
-         break;
--    case IBEX_UART_INTR_ENABLE:
-+    case R_INTR_ENABLE:
-         retvalue = s->uart_intr_enable;
-         break;
--    case IBEX_UART_INTR_TEST:
-+    case R_INTR_TEST:
-         qemu_log_mask(LOG_GUEST_ERROR,
-                       "%s: wdata is write only\n", __func__);
-         break;
--    case IBEX_UART_CTRL:
-+    case R_CTRL:
-         retvalue = s->uart_ctrl;
-         break;
--    case IBEX_UART_STATUS:
-+    case R_STATUS:
-         retvalue = s->uart_status;
-         break;
--    case IBEX_UART_RDATA:
-+    case R_RDATA:
-         retvalue = s->uart_rdata;
--        if (s->uart_ctrl & UART_CTRL_RX_ENABLE) {
-+        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
-             qemu_chr_fe_accept_input(&s->chr);
--            s->uart_status |= UART_STATUS_RXIDLE;
--            s->uart_status |= UART_STATUS_RXEMPTY;
-+            s->uart_status |= R_STATUS_RXIDLE_MASK;
-+            s->uart_status |= R_STATUS_RXEMPTY_MASK;
-         }
-         break;
--    case IBEX_UART_WDATA:
-+    case R_WDATA:
-         qemu_log_mask(LOG_GUEST_ERROR,
-                       "%s: wdata is write only\n", __func__);
-         break;
--    case IBEX_UART_FIFO_CTRL:
-+    case R_FIFO_CTRL:
-         retvalue = s->uart_fifo_ctrl;
-         break;
--    case IBEX_UART_FIFO_STATUS:
-+    case R_FIFO_STATUS:
-         retvalue = s->uart_fifo_status;
-         retvalue |= s->tx_level & 0x1F;
-@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
-                       "%s: RX fifos are not supported\n", __func__);
-         break;
--    case IBEX_UART_OVRD:
-+    case R_OVRD:
-         retvalue = s->uart_ovrd;
-         qemu_log_mask(LOG_UNIMP,
-                       "%s: ovrd is not supported\n", __func__);
-         break;
--    case IBEX_UART_VAL:
-+    case R_VAL:
-         retvalue = s->uart_val;
-         qemu_log_mask(LOG_UNIMP,
-                       "%s: val is not supported\n", __func__);
-         break;
--    case IBEX_UART_TIMEOUT_CTRL:
-+    case R_TIMEOUT_CTRL:
-         retvalue = s->uart_timeout_ctrl;
-         qemu_log_mask(LOG_UNIMP,
-                       "%s: timeout_ctrl is not supported\n", __func__);
-@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
-     IbexUartState *s = opaque;
-     uint32_t value = val64;
--    switch (addr) {
--    case IBEX_UART_INTR_STATE:
-+    switch (addr >> 2) {
-+    case R_INTR_STATE:
-         /* Write 1 clear */
-         s->uart_intr_state &= ~value;
-         ibex_uart_update_irqs(s);
-         break;
--    case IBEX_UART_INTR_ENABLE:
-+    case R_INTR_ENABLE:
-         s->uart_intr_enable = value;
-         ibex_uart_update_irqs(s);
-         break;
--    case IBEX_UART_INTR_TEST:
-+    case R_INTR_TEST:
-         s->uart_intr_state |= value;
-         ibex_uart_update_irqs(s);
-         break;
--    case IBEX_UART_CTRL:
-+    case R_CTRL:
-         s->uart_ctrl = value;
--        if (value & UART_CTRL_NF) {
-+        if (value & R_CTRL_NF_MASK) {
-             qemu_log_mask(LOG_UNIMP,
-                           "%s: UART_CTRL_NF is not supported\n", __func__);
-         }
--        if (value & UART_CTRL_SLPBK) {
-+        if (value & R_CTRL_SLPBK_MASK) {
-             qemu_log_mask(LOG_UNIMP,
-                           "%s: UART_CTRL_SLPBK is not supported\n", __func__);
-         }
--        if (value & UART_CTRL_LLPBK) {
-+        if (value & R_CTRL_LLPBK_MASK) {
-             qemu_log_mask(LOG_UNIMP,
-                           "%s: UART_CTRL_LLPBK is not supported\n", __func__);
-         }
--        if (value & UART_CTRL_PARITY_EN) {
-+        if (value & R_CTRL_PARITY_EN_MASK) {
-             qemu_log_mask(LOG_UNIMP,
-                           "%s: UART_CTRL_PARITY_EN is not supported\n",
-                           __func__);
-         }
--        if (value & UART_CTRL_PARITY_ODD) {
-+        if (value & R_CTRL_PARITY_ODD_MASK) {
-             qemu_log_mask(LOG_UNIMP,
-                           "%s: UART_CTRL_PARITY_ODD is not supported\n",
-                           __func__);
-         }
--        if (value & UART_CTRL_RXBLVL) {
-+        if (value & R_CTRL_RXBLVL_MASK) {
-             qemu_log_mask(LOG_UNIMP,
-                           "%s: UART_CTRL_RXBLVL is not supported\n", __func__);
-         }
--        if (value & UART_CTRL_NCO) {
-+        if (value & R_CTRL_NCO_MASK) {
-             uint64_t baud = ibex_uart_get_baud(s);
-             s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;
-         }
-         break;
--    case IBEX_UART_STATUS:
-+    case R_STATUS:
-         qemu_log_mask(LOG_GUEST_ERROR,
-                       "%s: status is read only\n", __func__);
-         break;
--    case IBEX_UART_RDATA:
-+    case R_RDATA:
-         qemu_log_mask(LOG_GUEST_ERROR,
-                       "%s: rdata is read only\n", __func__);
-         break;
--    case IBEX_UART_WDATA:
-+    case R_WDATA:
-         uart_write_tx_fifo(s, (uint8_t *) &value, 1);
-         break;
--    case IBEX_UART_FIFO_CTRL:
-+    case R_FIFO_CTRL:
-         s->uart_fifo_ctrl = value;
--        if (value & FIFO_CTRL_RXRST) {
-+        if (value & R_FIFO_CTRL_RXRST_MASK) {
-             qemu_log_mask(LOG_UNIMP,
-                           "%s: RX fifos are not supported\n", __func__);
-         }
--        if (value & FIFO_CTRL_TXRST) {
-+        if (value & R_FIFO_CTRL_TXRST_MASK) {
-             s->tx_level = 0;
-         }
-         break;
--    case IBEX_UART_FIFO_STATUS:
-+    case R_FIFO_STATUS:
-         qemu_log_mask(LOG_GUEST_ERROR,
-                       "%s: fifo_status is read only\n", __func__);
-         break;
--    case IBEX_UART_OVRD:
-+    case R_OVRD:
-         s->uart_ovrd = value;
-         qemu_log_mask(LOG_UNIMP,
-                       "%s: ovrd is not supported\n", __func__);
-         break;
--    case IBEX_UART_VAL:
-+    case R_VAL:
-         qemu_log_mask(LOG_GUEST_ERROR,
-                       "%s: val is read only\n", __func__);
-         break;
--    case IBEX_UART_TIMEOUT_CTRL:
-+    case R_TIMEOUT_CTRL:
-         s->uart_timeout_ctrl = value;
-         qemu_log_mask(LOG_UNIMP,
-                       "%s: timeout_ctrl is not supported\n", __func__);
-@@ -XXX,XX +XXX,XX @@ static void fifo_trigger_update(void *opaque)
- {
-     IbexUartState *s = opaque;
--    if (s->uart_ctrl & UART_CTRL_TX_ENABLE) {
-+    if (s->uart_ctrl & R_CTRL_TX_ENABLE_MASK) {
-         ibex_uart_xmit(NULL, G_IO_OUT, s);
-     }
- }
---
-.27.0

-[PULL 14/15] tcg/riscv: Remove superfluous breaks
+Deleted patch
-From: Liao Pingfang <liao.pingfang@zte.com.cn>
-Remove superfluous breaks, as there is a "return" before them.
-Signed-off-by: Liao Pingfang <liao.pingfang@zte.com.cn>
-Signed-off-by: Yi Wang <wang.yi59@zte.com.cn>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Thomas Huth <thuth@redhat.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1594600421-22942-1-git-send-email-wang.yi59@zte.com.cn>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- tcg/riscv/tcg-target.inc.c | 2 --
-file changed, 2 deletions(-)
-diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/riscv/tcg-target.inc.c
-+++ b/tcg/riscv/tcg-target.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
-         break;
-     case R_RISCV_JAL:
-         return reloc_jimm20(code_ptr, (tcg_insn_unit *)value);
--        break;
-     case R_RISCV_CALL:
-         return reloc_call(code_ptr, (tcg_insn_unit *)value);
--        break;
-     default:
-         tcg_abort();
-     }
---
-.27.0

The following changes since commit 20c1df5476e1e9b5d3f5b94f9f3ce01d21f14c46:

Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200713-pull-request' into staging (2020-07-13 16:58:44 +0100)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200713

for you to fetch changes up to cfad709bceb629a4ebeb5d8a3acd1871b9a6436b:

target/riscv: Fix pmp NA4 implementation (2020-07-13 17:25:37 -0700)

----------------------------------------------------------------
This is a colection of bug fixes and small imrprovements for RISC-V.

This includes some vector extensions fixes, a PMP bug fix, OpenTitan
UART bug fix and support for OpenSBI dynamic firmware.

----------------------------------------------------------------
Alexandre Mergnat (1):
      target/riscv: Fix pmp NA4 implementation

Alistair Francis (2):
      hw/char: Convert the Ibex UART to use the qdev Clock model
      hw/char: Convert the Ibex UART to use the registerfields API

Atish Patra (4):
      riscv: Unify Qemu's reset vector code path
      RISC-V: Copy the fdt in dram instead of ROM
      riscv: Add opensbi firmware dynamic support
      RISC-V: Support 64 bit start address

Bin Meng (3):
      MAINTAINERS: Add an entry for OpenSBI firmware
      hw/riscv: virt: Sort the SoC memmap table entries
      hw/riscv: Modify MROM size to end at 0x10000

Frank Chang (4):
      target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
      target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
      target/riscv: fix return value of do_opivx_widen()
      target/riscv: fix vill bit index in vtype register

Liao Pingfang (1):
      tcg/riscv: Remove superfluous breaks

From: Bin Meng <bin.meng@windriver.com>

Adjust the PCIe memory maps to follow the order.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1593746511-19517-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
     [VIRT_TEST] =        {   0x100000,        0x1000 },
     [VIRT_RTC] =         {   0x101000,        0x1000 },
     [VIRT_CLINT] =       {  0x2000000,       0x10000 },
+    [VIRT_PCIE_PIO] =    {  0x3000000,       0x10000 },
     [VIRT_PLIC] =        {  0xc000000,     0x4000000 },
     [VIRT_UART0] =       { 0x10000000,         0x100 },
     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
-    [VIRT_DRAM] =        { 0x80000000,           0x0 },
-    [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
-    [VIRT_PCIE_PIO] =    { 0x03000000,    0x00010000 },
     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
+    [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
+    [VIRT_DRAM] =        { 0x80000000,           0x0 },
 };
 
 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
-- 
2.27.0

From: Atish Patra <atish.patra@wdc.com>

Currently, all riscv machines except sifive_u have identical reset vector
code implementations with memory addresses being different for all machines.
They can be easily combined into a single function in common code.

Move it to common function and let all the machines use the common function.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20200701183949.398134-2-atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h |  2 ++
 hw/riscv/boot.c         | 46 +++++++++++++++++++++++++++++++++++++++++
 hw/riscv/sifive_u.c     |  1 -
 hw/riscv/spike.c        | 41 +++---------------------------------
 hw/riscv/virt.c         | 40 +++--------------------------------
 5 files changed, 54 insertions(+), 76 deletions(-)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
                                symbol_fn_t sym_cb);
 hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
                          uint64_t kernel_entry, hwaddr *start);
+void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base,
+                               hwaddr rom_size, void *fdt);
 
 #endif /* RISCV_BOOT_H */
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/loader.h"
 #include "hw/riscv/boot.h"
 #include "elf.h"
+#include "sysemu/device_tree.h"
 #include "sysemu/qtest.h"
 
+#include <libfdt.h>
+
 #if defined(TARGET_RISCV32)
 # define KERNEL_BOOT_ADDRESS 0x80400000
 #else
@@ -XXX,XX +XXX,XX @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
 
     return *start + size;
 }
+
+void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
+                               hwaddr rom_size, void *fdt)
+{
+    int i;
+
+    /* reset vector */
+    uint32_t reset_vec[8] = {
+        0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
+        0x02028593,                  /*     addi   a1, t0, %pcrel_lo(1b) */
+        0xf1402573,                  /*     csrr   a0, mhartid  */
+#if defined(TARGET_RISCV32)
+        0x0182a283,                  /*     lw     t0, 24(t0) */
+#elif defined(TARGET_RISCV64)
+        0x0182b283,                  /*     ld     t0, 24(t0) */
+#endif
+        0x00028067,                  /*     jr     t0 */
+        0x00000000,
+        start_addr,                  /* start: .dword */
+        0x00000000,
+                                     /* dtb: */
+    };
+
+    /* copy in the reset vector in little_endian byte order */
+    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
+        reset_vec[i] = cpu_to_le32(reset_vec[i]);
+    }
+    rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
+                          rom_base, &address_space_memory);
+
+    /* copy in the device tree */
+    if (fdt_pack(fdt) || fdt_totalsize(fdt) >
+        rom_size - sizeof(reset_vec)) {
+        error_report("not enough space to store device-tree");
+        exit(1);
+    }
+    qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
+    rom_add_blob_fixed_as("mrom.fdt", fdt, fdt_totalsize(fdt),
+                           rom_base + sizeof(reset_vec),
+                           &address_space_memory);
+
+    return;
+}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/device_tree.h"
 #include "sysemu/runstate.h"
 #include "sysemu/sysemu.h"
-#include "exec/address-spaces.h"
 
 #include <libfdt.h>
 
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/device_tree.h"
 #include "sysemu/qtest.h"
 #include "sysemu/sysemu.h"
-#include "exec/address-spaces.h"
-
-#include <libfdt.h>
 
 #if defined(TARGET_RISCV32)
 # define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf"
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
     MemoryRegion *system_memory = get_system_memory();
     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
-    int i;
     unsigned int smp_cpus = machine->smp.cpus;
 
     /* Initialize SOC */
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
         }
     }
 
-    /* reset vector */
-    uint32_t reset_vec[8] = {
-        0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
-        0x02028593,                  /*     addi   a1, t0, %pcrel_lo(1b) */
-        0xf1402573,                  /*     csrr   a0, mhartid  */
-#if defined(TARGET_RISCV32)
-        0x0182a283,                  /*     lw     t0, 24(t0) */
-#elif defined(TARGET_RISCV64)
-        0x0182b283,                  /*     ld     t0, 24(t0) */
-#endif
-        0x00028067,                  /*     jr     t0 */
-        0x00000000,
-        memmap[SPIKE_DRAM].base,     /* start: .dword DRAM_BASE */
-        0x00000000,
-                                     /* dtb: */
-    };
-
-    /* copy in the reset vector in little_endian byte order */
-    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
-        reset_vec[i] = cpu_to_le32(reset_vec[i]);
-    }
-    rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
-                          memmap[SPIKE_MROM].base, &address_space_memory);
-
-    /* copy in the device tree */
-    if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
-            memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
-        error_report("not enough space to store device-tree");
-        exit(1);
-    }
-    qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
-    rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
-                          memmap[SPIKE_MROM].base + sizeof(reset_vec),
-                          &address_space_memory);
+    /* load the reset vector */
+    riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base,
+                              memmap[SPIKE_MROM].size, s->fdt);
 
     /* initialize HTIF using symbols found in load_kernel */
     htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
 #include "sysemu/sysemu.h"
-#include "exec/address-spaces.h"
 #include "hw/pci/pci.h"
 #include "hw/pci-host/gpex.h"
 
-#include <libfdt.h>
-
 #if defined(TARGET_RISCV32)
 # define BIOS_FILENAME "opensbi-riscv32-virt-fw_jump.bin"
 #else
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
         start_addr = virt_memmap[VIRT_FLASH].base;
     }
 
-    /* reset vector */
-    uint32_t reset_vec[8] = {
-        0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
-        0x02028593,                  /*     addi   a1, t0, %pcrel_lo(1b) */
-        0xf1402573,                  /*     csrr   a0, mhartid  */
-#if defined(TARGET_RISCV32)
-        0x0182a283,                  /*     lw     t0, 24(t0) */
-#elif defined(TARGET_RISCV64)
-        0x0182b283,                  /*     ld     t0, 24(t0) */
-#endif
-        0x00028067,                  /*     jr     t0 */
-        0x00000000,
-        start_addr,                  /* start: .dword */
-        0x00000000,
-                                     /* dtb: */
-    };
-
-    /* copy in the reset vector in little_endian byte order */
-    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
-        reset_vec[i] = cpu_to_le32(reset_vec[i]);
-    }
-    rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
-                          memmap[VIRT_MROM].base, &address_space_memory);
-
-    /* copy in the device tree */
-    if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
-            memmap[VIRT_MROM].size - sizeof(reset_vec)) {
-        error_report("not enough space to store device-tree");
-        exit(1);
-    }
-    qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
-    rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
-                          memmap[VIRT_MROM].base + sizeof(reset_vec),
-                          &address_space_memory);
+    /* load the reset vector */
+    riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base,
+                              virt_memmap[VIRT_MROM].size, s->fdt);
 
     /* create PLIC hart topology configuration string */
     plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
-- 
2.27.0

From: Atish Patra <atish.patra@wdc.com>

Currently, the fdt is copied to the ROM after the reset vector. The firmware
has to copy it to DRAM. Instead of this, directly copy the device tree to a
pre-computed dram address. The device tree load address should be as far as
possible from kernel and initrd images. That's why it is kept at the end of
the DRAM or 4GB whichever is lesser.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20200701183949.398134-3-atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h |  4 +++-
 hw/riscv/boot.c         | 53 +++++++++++++++++++++++++++++------------
 hw/riscv/sifive_u.c     | 28 ++++++++++------------
 hw/riscv/spike.c        |  7 +++++-
 hw/riscv/virt.c         |  7 +++++-
 5 files changed, 66 insertions(+), 33 deletions(-)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
                                symbol_fn_t sym_cb);
 hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
                          uint64_t kernel_entry, hwaddr *start);
+uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
 void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base,
-                               hwaddr rom_size, void *fdt);
+                               hwaddr rom_size,
+                               uint32_t fdt_load_addr, void *fdt);
 
 #endif /* RISCV_BOOT_H */
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
     return *start + size;
 }
 
+uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
+{
+    uint32_t temp, fdt_addr;
+    hwaddr dram_end = dram_base + mem_size;
+    int fdtsize = fdt_totalsize(fdt);
+
+    if (fdtsize <= 0) {
+        error_report("invalid device-tree");
+        exit(1);
+    }
+
+    /*
+     * We should put fdt as far as possible to avoid kernel/initrd overwriting
+     * its content. But it should be addressable by 32 bit system as well.
+     * Thus, put it at an aligned address that less than fdt size from end of
+     * dram or 4GB whichever is lesser.
+     */
+    temp = MIN(dram_end, 4096 * MiB);
+    fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
+
+    fdt_pack(fdt);
+    /* copy in the device tree */
+    qemu_fdt_dumpdtb(fdt, fdtsize);
+
+    rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
+                          &address_space_memory);
+
+    return fdt_addr;
+}
+
 void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
-                               hwaddr rom_size, void *fdt)
+                               hwaddr rom_size,
+                               uint32_t fdt_load_addr, void *fdt)
 {
     int i;
 
     /* reset vector */
-    uint32_t reset_vec[8] = {
+    uint32_t reset_vec[10] = {
         0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
-        0x02028593,                  /*     addi   a1, t0, %pcrel_lo(1b) */
         0xf1402573,                  /*     csrr   a0, mhartid  */
 #if defined(TARGET_RISCV32)
+        0x0202a583,                  /*     lw     a1, 32(t0) */
         0x0182a283,                  /*     lw     t0, 24(t0) */
 #elif defined(TARGET_RISCV64)
+        0x0202b583,                  /*     ld     a1, 32(t0) */
         0x0182b283,                  /*     ld     t0, 24(t0) */
 #endif
         0x00028067,                  /*     jr     t0 */
         0x00000000,
         start_addr,                  /* start: .dword */
+        0x00000000,
+        fdt_load_addr,               /* fdt_laddr: .dword */
         0x00000000,
                                      /* dtb: */
     };
 
     /* copy in the reset vector in little_endian byte order */
-    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
+    for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
         reset_vec[i] = cpu_to_le32(reset_vec[i]);
     }
     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
                           rom_base, &address_space_memory);
 
-    /* copy in the device tree */
-    if (fdt_pack(fdt) || fdt_totalsize(fdt) >
-        rom_size - sizeof(reset_vec)) {
-        error_report("not enough space to store device-tree");
-        exit(1);
-    }
-    qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
-    rom_add_blob_fixed_as("mrom.fdt", fdt, fdt_totalsize(fdt),
-                           rom_base + sizeof(reset_vec),
-                           &address_space_memory);
-
     return;
 }
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
     MemoryRegion *flash0 = g_new(MemoryRegion, 1);
     target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
     int i;
+    uint32_t fdt_load_addr;
 
     /* Initialize SoC */
     object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
         }
     }
 
+    /* Compute the fdt load address in dram */
+    fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
+                                   machine->ram_size, s->fdt);
+
     /* reset vector */
-    uint32_t reset_vec[8] = {
+    uint32_t reset_vec[11] = {
         s->msel,                       /* MSEL pin state */
         0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(dtb) */
-        0x01c28593,                    /*     addi   a1, t0, %pcrel_lo(1b) */
         0xf1402573,                    /*     csrr   a0, mhartid  */
 #if defined(TARGET_RISCV32)
+        0x0202a583,                    /*     lw     a1, 32(t0) */
         0x0182a283,                    /*     lw     t0, 24(t0) */
 #elif defined(TARGET_RISCV64)
-        0x0182e283,                    /*     lwu    t0, 24(t0) */
+        0x0202b583,                    /*     ld     a1, 32(t0) */
+        0x0182b283,                    /*     ld     t0, 24(t0) */
 #endif
         0x00028067,                    /*     jr     t0 */
         0x00000000,
         start_addr,                    /* start: .dword */
+        0x00000000,
+        fdt_load_addr,                 /* fdt_laddr: .dword */
+        0x00000000,
                                        /* dtb: */
     };
 
     /* copy in the reset vector in little_endian byte order */
-    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
+    for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
         reset_vec[i] = cpu_to_le32(reset_vec[i]);
     }
     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
                           memmap[SIFIVE_U_MROM].base, &address_space_memory);
-
-    /* copy in the device tree */
-    if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
-            memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) {
-        error_report("not enough space to store device-tree");
-        exit(1);
-    }
-    qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
-    rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
-                          memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
-                          &address_space_memory);
 }
 
 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
     unsigned int smp_cpus = machine->smp.cpus;
+    uint32_t fdt_load_addr;
 
     /* Initialize SOC */
     object_initialize_child(OBJECT(machine), "soc", &s->soc,
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
         }
     }
 
+    /* Compute the fdt load address in dram */
+    fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
+                                   machine->ram_size, s->fdt);
     /* load the reset vector */
     riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base,
-                              memmap[SPIKE_MROM].size, s->fdt);
+                              memmap[SPIKE_MROM].size,
+                              fdt_load_addr, s->fdt);
 
     /* initialize HTIF using symbols found in load_kernel */
     htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
     char *plic_hart_config;
     size_t plic_hart_config_len;
     target_ulong start_addr = memmap[VIRT_DRAM].base;
+    uint32_t fdt_load_addr;
     int i;
     unsigned int smp_cpus = machine->smp.cpus;
 
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
         start_addr = virt_memmap[VIRT_FLASH].base;
     }
 
+    /* Compute the fdt load address in dram */
+    fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
+                                   machine->ram_size, s->fdt);
     /* load the reset vector */
     riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base,
-                              virt_memmap[VIRT_MROM].size, s->fdt);
+                              virt_memmap[VIRT_MROM].size,
+                              fdt_load_addr, s->fdt);
 
     /* create PLIC hart topology configuration string */
     plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
-- 
2.27.0

From: Atish Patra <atish.patra@wdc.com>

OpenSBI is the default firmware in Qemu and has various firmware loading
options. Currently, qemu loader uses fw_jump which has a compile time
pre-defined address where fdt & kernel image must reside. This puts a
constraint on image size of the Linux kernel depending on the fdt location
and available memory. However, fw_dynamic allows the loader to specify
the next stage location (i.e. Linux kernel/U-Boot) in memory and other
configurable boot options available in OpenSBI.

Add support for OpenSBI dynamic firmware loading support. This doesn't
break existing setup and fw_jump will continue to work as it is. Any
other firmware will continue to work without any issues as long as it
doesn't expect anything specific from loader in "a2" register.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20200701183949.398134-4-atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h         |  5 ++-
 include/hw/riscv/boot_opensbi.h | 58 +++++++++++++++++++++++++++++++++
 hw/riscv/boot.c                 | 42 +++++++++++++++++++++---
 hw/riscv/sifive_u.c             | 20 +++++++++---
 hw/riscv/spike.c                | 13 ++++++--
 hw/riscv/virt.c                 | 12 +++++--
 6 files changed, 134 insertions(+), 16 deletions(-)
 create mode 100644 include/hw/riscv/boot_opensbi.h

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
                          uint64_t kernel_entry, hwaddr *start);
 uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
 void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base,
-                               hwaddr rom_size,
+                               hwaddr rom_size, uint64_t kernel_entry,
                                uint32_t fdt_load_addr, void *fdt);
+void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size,
+                                  uint32_t reset_vec_size,
+                                  uint64_t kernel_entry);
 
 #endif /* RISCV_BOOT_H */
diff --git a/include/hw/riscv/boot_opensbi.h b/include/hw/riscv/boot_opensbi.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/riscv/boot_opensbi.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Based on include/sbi/{fw_dynamic.h,sbi_scratch.h} from the OpenSBI project.
+ */
+#ifndef OPENSBI_H
+#define OPENSBI_H
+
+/** Expected value of info magic ('OSBI' ascii string in hex) */
+#define FW_DYNAMIC_INFO_MAGIC_VALUE     0x4942534f
+
+/** Maximum supported info version */
+#define FW_DYNAMIC_INFO_VERSION         0x2
+
+/** Possible next mode values */
+#define FW_DYNAMIC_INFO_NEXT_MODE_U     0x0
+#define FW_DYNAMIC_INFO_NEXT_MODE_S     0x1
+#define FW_DYNAMIC_INFO_NEXT_MODE_M     0x3
+
+enum sbi_scratch_options {
+    /** Disable prints during boot */
+    SBI_SCRATCH_NO_BOOT_PRINTS = (1 << 0),
+    /** Enable runtime debug prints */
+    SBI_SCRATCH_DEBUG_PRINTS = (1 << 1),
+};
+
+/** Representation dynamic info passed by previous booting stage */
+struct fw_dynamic_info {
+    /** Info magic */
+    target_long magic;
+    /** Info version */
+    target_long version;
+    /** Next booting stage address */
+    target_long next_addr;
+    /** Next booting stage mode */
+    target_long next_mode;
+    /** Options for OpenSBI library */
+    target_long options;
+    /**
+     * Preferred boot HART id
+     *
+     * It is possible that the previous booting stage uses same link
+     * address as the FW_DYNAMIC firmware. In this case, the relocation
+     * lottery mechanism can potentially overwrite the previous booting
+     * stage while other HARTs are still running in the previous booting
+     * stage leading to boot-time crash. To avoid this boot-time crash,
+     * the previous booting stage can specify last HART that will jump
+     * to the FW_DYNAMIC firmware as the preferred boot HART.
+     *
+     * To avoid specifying a preferred boot HART, the previous booting
+     * stage can set it to -1UL which will force the FW_DYNAMIC firmware
+     * to use the relocation lottery mechanism.
+     */
+    target_long boot_hart;
+};
+
+#endif
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #include "hw/loader.h"
 #include "hw/riscv/boot.h"
+#include "hw/riscv/boot_opensbi.h"
 #include "elf.h"
 #include "sysemu/device_tree.h"
 #include "sysemu/qtest.h"
@@ -XXX,XX +XXX,XX @@
 
 #if defined(TARGET_RISCV32)
 # define KERNEL_BOOT_ADDRESS 0x80400000
+#define fw_dynamic_info_data(__val)     cpu_to_le32(__val)
 #else
 # define KERNEL_BOOT_ADDRESS 0x80200000
+#define fw_dynamic_info_data(__val)     cpu_to_le64(__val)
 #endif
 
 void riscv_find_and_load_firmware(MachineState *machine,
@@ -XXX,XX +XXX,XX @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
     return fdt_addr;
 }
 
+void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size,
+                              uint32_t reset_vec_size, uint64_t kernel_entry)
+{
+    struct fw_dynamic_info dinfo;
+    size_t dinfo_len;
+
+    dinfo.magic = fw_dynamic_info_data(FW_DYNAMIC_INFO_MAGIC_VALUE);
+    dinfo.version = fw_dynamic_info_data(FW_DYNAMIC_INFO_VERSION);
+    dinfo.next_mode = fw_dynamic_info_data(FW_DYNAMIC_INFO_NEXT_MODE_S);
+    dinfo.next_addr = fw_dynamic_info_data(kernel_entry);
+    dinfo.options = 0;
+    dinfo.boot_hart = 0;
+    dinfo_len = sizeof(dinfo);
+
+    /**
+     * copy the dynamic firmware info. This information is specific to
+     * OpenSBI but doesn't break any other firmware as long as they don't
+     * expect any certain value in "a2" register.
+     */
+    if (dinfo_len > (rom_size - reset_vec_size)) {
+        error_report("not enough space to store dynamic firmware info");
+        exit(1);
+    }
+
+    rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len,
+                           rom_base + reset_vec_size,
+                           &address_space_memory);
+}
+
 void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
-                               hwaddr rom_size,
+                               hwaddr rom_size, uint64_t kernel_entry,
                                uint32_t fdt_load_addr, void *fdt)
 {
     int i;
 
     /* reset vector */
     uint32_t reset_vec[10] = {
-        0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
+        0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(fw_dyn) */
+        0x02828613,                  /*     addi   a2, t0, %pcrel_lo(1b) */
         0xf1402573,                  /*     csrr   a0, mhartid  */
 #if defined(TARGET_RISCV32)
         0x0202a583,                  /*     lw     a1, 32(t0) */
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
         0x0182b283,                  /*     ld     t0, 24(t0) */
 #endif
         0x00028067,                  /*     jr     t0 */
-        0x00000000,
         start_addr,                  /* start: .dword */
         0x00000000,
         fdt_load_addr,               /* fdt_laddr: .dword */
         0x00000000,
-                                     /* dtb: */
+                                     /* fw_dyn: */
     };
 
     /* copy in the reset vector in little_endian byte order */
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
     }
     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
                           rom_base, &address_space_memory);
+    riscv_rom_copy_firmware_info(rom_base, rom_size, sizeof(reset_vec),
+                                 kernel_entry);
 
     return;
 }
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
     target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
     int i;
     uint32_t fdt_load_addr;
+    uint64_t kernel_entry;
 
     /* Initialize SoC */
     object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
     riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr, NULL);
 
     if (machine->kernel_filename) {
-        uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
-                                                  NULL);
+        kernel_entry = riscv_load_kernel(machine->kernel_filename, NULL);
 
         if (machine->initrd_filename) {
             hwaddr start;
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
             qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
                                   end);
         }
+    } else {
+       /*
+        * If dynamic firmware is used, it doesn't know where is the next mode
+        * if kernel argument is not set.
+        */
+        kernel_entry = 0;
     }
 
     /* Compute the fdt load address in dram */
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
     /* reset vector */
     uint32_t reset_vec[11] = {
         s->msel,                       /* MSEL pin state */
-        0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(dtb) */
+        0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(fw_dyn) */
+        0x02828613,                    /*     addi   a2, t0, %pcrel_lo(1b) */
         0xf1402573,                    /*     csrr   a0, mhartid  */
 #if defined(TARGET_RISCV32)
         0x0202a583,                    /*     lw     a1, 32(t0) */
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
         0x0182b283,                    /*     ld     t0, 24(t0) */
 #endif
         0x00028067,                    /*     jr     t0 */
-        0x00000000,
         start_addr,                    /* start: .dword */
         0x00000000,
         fdt_load_addr,                 /* fdt_laddr: .dword */
         0x00000000,
-                                       /* dtb: */
+                                       /* fw_dyn: */
     };
 
     /* copy in the reset vector in little_endian byte order */
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
     }
     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
                           memmap[SIFIVE_U_MROM].base, &address_space_memory);
+
+    riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base,
+                                 memmap[SIFIVE_U_MROM].size,
+                                 sizeof(reset_vec), kernel_entry);
 }
 
 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
     unsigned int smp_cpus = machine->smp.cpus;
     uint32_t fdt_load_addr;
+    uint64_t kernel_entry;
 
     /* Initialize SOC */
     object_initialize_child(OBJECT(machine), "soc", &s->soc,
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
                                  htif_symbol_callback);
 
     if (machine->kernel_filename) {
-        uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
-                                                  htif_symbol_callback);
+        kernel_entry = riscv_load_kernel(machine->kernel_filename,
+                                         htif_symbol_callback);
 
         if (machine->initrd_filename) {
             hwaddr start;
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
             qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
                                   end);
         }
+    } else {
+       /*
+        * If dynamic firmware is used, it doesn't know where is the next mode
+        * if kernel argument is not set.
+        */
+        kernel_entry = 0;
     }
 
     /* Compute the fdt load address in dram */
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
                                    machine->ram_size, s->fdt);
     /* load the reset vector */
     riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base,
-                              memmap[SPIKE_MROM].size,
+                              memmap[SPIKE_MROM].size, kernel_entry,
                               fdt_load_addr, s->fdt);
 
     /* initialize HTIF using symbols found in load_kernel */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
     size_t plic_hart_config_len;
     target_ulong start_addr = memmap[VIRT_DRAM].base;
     uint32_t fdt_load_addr;
+    uint64_t kernel_entry;
     int i;
     unsigned int smp_cpus = machine->smp.cpus;
 
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                                  memmap[VIRT_DRAM].base, NULL);
 
     if (machine->kernel_filename) {
-        uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
-                                                  NULL);
+        kernel_entry = riscv_load_kernel(machine->kernel_filename, NULL);
 
         if (machine->initrd_filename) {
             hwaddr start;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
             qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
                                   end);
         }
+    } else {
+       /*
+        * If dynamic firmware is used, it doesn't know where is the next mode
+        * if kernel argument is not set.
+        */
+        kernel_entry = 0;
     }
 
     if (drive_get(IF_PFLASH, 0, 0)) {
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                                    machine->ram_size, s->fdt);
     /* load the reset vector */
     riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base,
-                              virt_memmap[VIRT_MROM].size,
+                              virt_memmap[VIRT_MROM].size, kernel_entry,
                               fdt_load_addr, s->fdt);
 
     /* create PLIC hart topology configuration string */
-- 
2.27.0

From: Atish Patra <atish.patra@wdc.com>

Even though the start address in ROM code is declared as a 64 bit address
for RV64, it can't be used as upper bits are set to zero in ROM code.

Update the ROM code correctly to reflect the 64bit value.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20200701183949.398134-5-atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/boot.c     | 6 +++++-
 hw/riscv/sifive_u.c | 6 +++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
                                uint32_t fdt_load_addr, void *fdt)
 {
     int i;
+    uint32_t start_addr_hi32 = 0x00000000;
 
+    #if defined(TARGET_RISCV64)
+    start_addr_hi32 = start_addr >> 32;
+    #endif
     /* reset vector */
     uint32_t reset_vec[10] = {
         0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(fw_dyn) */
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
 #endif
         0x00028067,                  /*     jr     t0 */
         start_addr,                  /* start: .dword */
-        0x00000000,
+        start_addr_hi32,
         fdt_load_addr,               /* fdt_laddr: .dword */
         0x00000000,
                                      /* fw_dyn: */
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *flash0 = g_new(MemoryRegion, 1);
     target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
+    uint32_t start_addr_hi32 = 0x00000000;
     int i;
     uint32_t fdt_load_addr;
     uint64_t kernel_entry;
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
                                    machine->ram_size, s->fdt);
+    #if defined(TARGET_RISCV64)
+    start_addr_hi32 = start_addr >> 32;
+    #endif
 
     /* reset vector */
     uint32_t reset_vec[11] = {
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
 #endif
         0x00028067,                    /*     jr     t0 */
         start_addr,                    /* start: .dword */
-        0x00000000,
+        start_addr_hi32,
         fdt_load_addr,                 /* fdt_laddr: .dword */
         0x00000000,
                                        /* fw_dyn: */
-- 
2.27.0

From: Bin Meng <bin.meng@windriver.com>

At present the size of Mask ROM for sifive_u / spike / virt machines
is set to 0x11000, which ends at an unusual address. This changes the
size to 0xf000 so that it ends at 0x10000.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1594289144-24723-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c | 2 +-
 hw/riscv/spike.c    | 2 +-
 hw/riscv/virt.c     | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
     hwaddr size;
 } sifive_u_memmap[] = {
     [SIFIVE_U_DEBUG] =    {        0x0,      0x100 },
-    [SIFIVE_U_MROM] =     {     0x1000,    0x11000 },
+    [SIFIVE_U_MROM] =     {     0x1000,     0xf000 },
     [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },
     [SIFIVE_U_L2LIM] =    {  0x8000000,  0x2000000 },
     [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
     hwaddr base;
     hwaddr size;
 } spike_memmap[] = {
-    [SPIKE_MROM] =     {     0x1000,    0x11000 },
+    [SPIKE_MROM] =     {     0x1000,     0xf000 },
     [SPIKE_CLINT] =    {  0x2000000,    0x10000 },
     [SPIKE_DRAM] =     { 0x80000000,        0x0 },
 };
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
     hwaddr size;
 } virt_memmap[] = {
     [VIRT_DEBUG] =       {        0x0,         0x100 },
-    [VIRT_MROM] =        {     0x1000,       0x11000 },
+    [VIRT_MROM] =        {     0x1000,        0xf000 },
     [VIRT_TEST] =        {   0x100000,        0x1000 },
     [VIRT_RTC] =         {   0x101000,        0x1000 },
     [VIRT_CLINT] =       {  0x2000000,       0x10000 },
-- 
2.27.0

From: Frank Chang <frank.chang@sifive.com>

gvec should provide vecop_list to avoid:
"tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200710104920.13550-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.inc.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -XXX,XX +XXX,XX @@ static void gen_rsub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
 static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs,
                                TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
 {
+    static const TCGOpcode vecop_list[] = { INDEX_op_sub_vec, 0 };
     static const GVecGen2s rsub_op[4] = {
         { .fni8 = gen_vec_rsub8_i64,
           .fniv = gen_rsub_vec,
           .fno = gen_helper_vec_rsubs8,
+          .opt_opc = vecop_list,
           .vece = MO_8 },
         { .fni8 = gen_vec_rsub16_i64,
           .fniv = gen_rsub_vec,
           .fno = gen_helper_vec_rsubs16,
+          .opt_opc = vecop_list,
           .vece = MO_16 },
         { .fni4 = gen_rsub_i32,
           .fniv = gen_rsub_vec,
           .fno = gen_helper_vec_rsubs32,
+          .opt_opc = vecop_list,
           .vece = MO_32 },
         { .fni8 = gen_rsub_i64,
           .fniv = gen_rsub_vec,
           .fno = gen_helper_vec_rsubs64,
+          .opt_opc = vecop_list,
           .prefer_i64 = TCG_TARGET_REG_BITS == 64,
           .vece = MO_64 },
     };
-- 
2.27.0

Conver the Ibex UART to use the recently added qdev-clock functions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: b0136fad870a29049959ec161c1217b967d7e19d.1594332223.git.alistair.francis@wdc.com
Message-Id: <b0136fad870a29049959ec161c1217b967d7e19d.1594332223.git.alistair.francis@wdc.com>
---
 include/hw/char/ibex_uart.h |  3 +++
 hw/char/ibex_uart.c         | 30 +++++++++++++++++++++++++++---
 2 files changed, 30 insertions(+), 3 deletions(-)

diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/ibex_uart.h
+++ b/include/hw/char/ibex_uart.h
@@ -XXX,XX +XXX,XX @@
 #define IBEX_UART_TIMEOUT_CTRL 0x2c
 
 #define IBEX_UART_TX_FIFO_SIZE 16
+#define IBEX_UART_CLOCK 50000000 /* 50MHz clock */
 
 #define TYPE_IBEX_UART "ibex-uart"
 #define IBEX_UART(obj) \
@@ -XXX,XX +XXX,XX @@ typedef struct {
     uint32_t uart_val;
     uint32_t uart_timeout_ctrl;
 
+    Clock *f_clk;
+
     CharBackend chr;
     qemu_irq tx_watermark;
     qemu_irq rx_watermark;
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "hw/char/ibex_uart.h"
 #include "hw/irq.h"
+#include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
 #include "qemu/log.h"
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
     ibex_uart_update_irqs(s);
 }
 
+static uint64_t ibex_uart_get_baud(IbexUartState *s)
+{
+    uint64_t baud;
+
+    baud = ((s->uart_ctrl & UART_CTRL_NCO) >> 16);
+    baud *= clock_get_hz(s->f_clk);
+    baud >>= 20;
+
+    return baud;
+}
+
 static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
                                        unsigned int size)
 {
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
                           "%s: UART_CTRL_RXBLVL is not supported\n", __func__);
         }
         if (value & UART_CTRL_NCO) {
-            uint64_t baud = ((value & UART_CTRL_NCO) >> 16);
-            baud *= 1000;
-            baud >>= 20;
+            uint64_t baud = ibex_uart_get_baud(s);
 
             s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;
         }
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
     }
 }
 
+static void ibex_uart_clk_update(void *opaque)
+{
+    IbexUartState *s = opaque;
+
+    /* recompute uart's speed on clock change */
+    uint64_t baud = ibex_uart_get_baud(s);
+
+    s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;
+}
+
 static void fifo_trigger_update(void *opaque)
 {
     IbexUartState *s = opaque;
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_init(Object *obj)
 {
     IbexUartState *s = IBEX_UART(obj);
 
+    s->f_clk = qdev_init_clock_in(DEVICE(obj), "f_clock",
+                                  ibex_uart_clk_update, s);
+    clock_set_hz(s->f_clk, IBEX_UART_CLOCK);
+
     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_watermark);
     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_watermark);
     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_empty);
-- 
2.27.0

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 06372c9cdeec715077899e71c858d9f0a2a3395b.1594332223.git.alistair.francis@wdc.com
Message-Id: <06372c9cdeec715077899e71c858d9f0a2a3395b.1594332223.git.alistair.francis@wdc.com>
---
 include/hw/char/ibex_uart.h |  76 ++++++++++-----------
 hw/char/ibex_uart.c         | 130 ++++++++++++++++++------------------
 2 files changed, 100 insertions(+), 106 deletions(-)

diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/ibex_uart.h
+++ b/include/hw/char/ibex_uart.h
@@ -XXX,XX +XXX,XX @@
 #define HW_IBEX_UART_H
 
 #include "hw/sysbus.h"
+#include "hw/registerfields.h"
 #include "chardev/char-fe.h"
 #include "qemu/timer.h"
 
-#define IBEX_UART_INTR_STATE   0x00
-    #define INTR_STATE_TX_WATERMARK (1 << 0)
-    #define INTR_STATE_RX_WATERMARK (1 << 1)
-    #define INTR_STATE_TX_EMPTY     (1 << 2)
-    #define INTR_STATE_RX_OVERFLOW  (1 << 3)
-#define IBEX_UART_INTR_ENABLE  0x04
-#define IBEX_UART_INTR_TEST    0x08
-
-#define IBEX_UART_CTRL         0x0c
-    #define UART_CTRL_TX_ENABLE     (1 << 0)
-    #define UART_CTRL_RX_ENABLE     (1 << 1)
-    #define UART_CTRL_NF            (1 << 2)
-    #define UART_CTRL_SLPBK         (1 << 4)
-    #define UART_CTRL_LLPBK         (1 << 5)
-    #define UART_CTRL_PARITY_EN     (1 << 6)
-    #define UART_CTRL_PARITY_ODD    (1 << 7)
-    #define UART_CTRL_RXBLVL        (3 << 8)
-    #define UART_CTRL_NCO           (0xFFFF << 16)
-
-#define IBEX_UART_STATUS       0x10
-    #define UART_STATUS_TXFULL  (1 << 0)
-    #define UART_STATUS_RXFULL  (1 << 1)
-    #define UART_STATUS_TXEMPTY (1 << 2)
-    #define UART_STATUS_RXIDLE  (1 << 4)
-    #define UART_STATUS_RXEMPTY (1 << 5)
-
-#define IBEX_UART_RDATA        0x14
-#define IBEX_UART_WDATA        0x18
-
-#define IBEX_UART_FIFO_CTRL    0x1c
-    #define FIFO_CTRL_RXRST          (1 << 0)
-    #define FIFO_CTRL_TXRST          (1 << 1)
-    #define FIFO_CTRL_RXILVL         (7 << 2)
-    #define FIFO_CTRL_RXILVL_SHIFT   (2)
-    #define FIFO_CTRL_TXILVL         (3 << 5)
-    #define FIFO_CTRL_TXILVL_SHIFT   (5)
-
-#define IBEX_UART_FIFO_STATUS  0x20
-#define IBEX_UART_OVRD         0x24
-#define IBEX_UART_VAL          0x28
-#define IBEX_UART_TIMEOUT_CTRL 0x2c
+REG32(INTR_STATE, 0x00)
+    FIELD(INTR_STATE, TX_WATERMARK, 0, 1)
+    FIELD(INTR_STATE, RX_WATERMARK, 1, 1)
+    FIELD(INTR_STATE, TX_EMPTY, 2, 1)
+    FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
+REG32(INTR_ENABLE, 0x04)
+REG32(INTR_TEST, 0x08)
+REG32(CTRL, 0x0C)
+    FIELD(CTRL, TX_ENABLE, 0, 1)
+    FIELD(CTRL, RX_ENABLE, 1, 1)
+    FIELD(CTRL, NF, 2, 1)
+    FIELD(CTRL, SLPBK, 4, 1)
+    FIELD(CTRL, LLPBK, 5, 1)
+    FIELD(CTRL, PARITY_EN, 6, 1)
+    FIELD(CTRL, PARITY_ODD, 7, 1)
+    FIELD(CTRL, RXBLVL, 8, 2)
+    FIELD(CTRL, NCO, 16, 16)
+REG32(STATUS, 0x10)
+    FIELD(STATUS, TXFULL, 0, 1)
+    FIELD(STATUS, RXFULL, 1, 1)
+    FIELD(STATUS, TXEMPTY, 2, 1)
+    FIELD(STATUS, RXIDLE, 4, 1)
+    FIELD(STATUS, RXEMPTY, 5, 1)
+REG32(RDATA, 0x14)
+REG32(WDATA, 0x18)
+REG32(FIFO_CTRL, 0x1c)
+    FIELD(FIFO_CTRL, RXRST, 0, 1)
+    FIELD(FIFO_CTRL, TXRST, 1, 1)
+    FIELD(FIFO_CTRL, RXILVL, 2, 3)
+    FIELD(FIFO_CTRL, TXILVL, 5, 2)
+REG32(FIFO_STATUS, 0x20)
+REG32(OVRD, 0x24)
+REG32(VAL, 0x28)
+REG32(TIMEOUT_CTRL, 0x2c)
 
 #define IBEX_UART_TX_FIFO_SIZE 16
 #define IBEX_UART_CLOCK 50000000 /* 50MHz clock */
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -XXX,XX +XXX,XX @@
 
 static void ibex_uart_update_irqs(IbexUartState *s)
 {
-    if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_TX_WATERMARK) {
+    if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) {
         qemu_set_irq(s->tx_watermark, 1);
     } else {
         qemu_set_irq(s->tx_watermark, 0);
     }
 
-    if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_RX_WATERMARK) {
+    if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_WATERMARK_MASK) {
         qemu_set_irq(s->rx_watermark, 1);
     } else {
         qemu_set_irq(s->rx_watermark, 0);
     }
 
-    if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_TX_EMPTY) {
+    if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_EMPTY_MASK) {
         qemu_set_irq(s->tx_empty, 1);
     } else {
         qemu_set_irq(s->tx_empty, 0);
     }
 
-    if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_RX_OVERFLOW) {
+    if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_OVERFLOW_MASK) {
         qemu_set_irq(s->rx_overflow, 1);
     } else {
         qemu_set_irq(s->rx_overflow, 0);
@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
 {
     IbexUartState *s = opaque;
 
-    if (s->uart_ctrl & UART_CTRL_RX_ENABLE) {
+    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
         return 1;
     }
 
@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
 static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
 {
     IbexUartState *s = opaque;
-    uint8_t rx_fifo_level = (s->uart_fifo_ctrl & FIFO_CTRL_RXILVL)
-                            >> FIFO_CTRL_RXILVL_SHIFT;
+    uint8_t rx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_RXILVL_MASK)
+                            >> R_FIFO_CTRL_RXILVL_SHIFT;
 
     s->uart_rdata = *buf;
 
-    s->uart_status &= ~UART_STATUS_RXIDLE;
-    s->uart_status &= ~UART_STATUS_RXEMPTY;
+    s->uart_status &= ~R_STATUS_RXIDLE_MASK;
+    s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
 
     if (size > rx_fifo_level) {
-        s->uart_intr_state |= INTR_STATE_RX_WATERMARK;
+        s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
     }
 
     ibex_uart_update_irqs(s);
@@ -XXX,XX +XXX,XX @@ static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond,
                                void *opaque)
 {
     IbexUartState *s = opaque;
-    uint8_t tx_fifo_level = (s->uart_fifo_ctrl & FIFO_CTRL_TXILVL)
-                            >> FIFO_CTRL_TXILVL_SHIFT;
+    uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK)
+                            >> R_FIFO_CTRL_TXILVL_SHIFT;
     int ret;
 
     /* instant drain the fifo when there's no back-end */
@@ -XXX,XX +XXX,XX @@ static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond,
     }
 
     if (!s->tx_level) {
-        s->uart_status &= ~UART_STATUS_TXFULL;
-        s->uart_status |= UART_STATUS_TXEMPTY;
-        s->uart_intr_state |= INTR_STATE_TX_EMPTY;
-        s->uart_intr_state &= ~INTR_STATE_TX_WATERMARK;
+        s->uart_status &= ~R_STATUS_TXFULL_MASK;
+        s->uart_status |= R_STATUS_TXEMPTY_MASK;
+        s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK;
+        s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK;
         ibex_uart_update_irqs(s);
         return FALSE;
     }
@@ -XXX,XX +XXX,XX @@ static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond,
 
     /* Clear the TX Full bit */
     if (s->tx_level != IBEX_UART_TX_FIFO_SIZE) {
-        s->uart_status &= ~UART_STATUS_TXFULL;
+        s->uart_status &= ~R_STATUS_TXFULL_MASK;
     }
 
     /* Disable the TX_WATERMARK IRQ */
     if (s->tx_level < tx_fifo_level) {
-        s->uart_intr_state &= ~INTR_STATE_TX_WATERMARK;
+        s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK;
     }
 
     /* Set TX empty */
     if (s->tx_level == 0) {
-        s->uart_status |= UART_STATUS_TXEMPTY;
-        s->uart_intr_state |= INTR_STATE_TX_EMPTY;
+        s->uart_status |= R_STATUS_TXEMPTY_MASK;
+        s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK;
     }
 
     ibex_uart_update_irqs(s);
@@ -XXX,XX +XXX,XX @@ static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf,
                                int size)
 {
     uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
-    uint8_t tx_fifo_level = (s->uart_fifo_ctrl & FIFO_CTRL_TXILVL)
-                            >> FIFO_CTRL_TXILVL_SHIFT;
+    uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK)
+                            >> R_FIFO_CTRL_TXILVL_SHIFT;
 
     if (size > IBEX_UART_TX_FIFO_SIZE - s->tx_level) {
         size = IBEX_UART_TX_FIFO_SIZE - s->tx_level;
@@ -XXX,XX +XXX,XX @@ static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf,
     s->tx_level += size;
 
     if (s->tx_level > 0) {
-        s->uart_status &= ~UART_STATUS_TXEMPTY;
+        s->uart_status &= ~R_STATUS_TXEMPTY_MASK;
     }
 
     if (s->tx_level >= tx_fifo_level) {
-        s->uart_intr_state |= INTR_STATE_TX_WATERMARK;
+        s->uart_intr_state |= R_INTR_STATE_TX_WATERMARK_MASK;
         ibex_uart_update_irqs(s);
     }
 
     if (s->tx_level == IBEX_UART_TX_FIFO_SIZE) {
-        s->uart_status |= UART_STATUS_TXFULL;
+        s->uart_status |= R_STATUS_TXFULL_MASK;
     }
 
     timer_mod(s->fifo_trigger_handle, current_time +
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_get_baud(IbexUartState *s)
 {
     uint64_t baud;
 
-    baud = ((s->uart_ctrl & UART_CTRL_NCO) >> 16);
+    baud = ((s->uart_ctrl & R_CTRL_NCO_MASK) >> 16);
     baud *= clock_get_hz(s->f_clk);
     baud >>= 20;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
     IbexUartState *s = opaque;
     uint64_t retvalue = 0;
 
-    switch (addr) {
-    case IBEX_UART_INTR_STATE:
+    switch (addr >> 2) {
+    case R_INTR_STATE:
         retvalue = s->uart_intr_state;
         break;
-    case IBEX_UART_INTR_ENABLE:
+    case R_INTR_ENABLE:
         retvalue = s->uart_intr_enable;
         break;
-    case IBEX_UART_INTR_TEST:
+    case R_INTR_TEST:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: wdata is write only\n", __func__);
         break;
 
-    case IBEX_UART_CTRL:
+    case R_CTRL:
         retvalue = s->uart_ctrl;
         break;
-    case IBEX_UART_STATUS:
+    case R_STATUS:
         retvalue = s->uart_status;
         break;
 
-    case IBEX_UART_RDATA:
+    case R_RDATA:
         retvalue = s->uart_rdata;
-        if (s->uart_ctrl & UART_CTRL_RX_ENABLE) {
+        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
             qemu_chr_fe_accept_input(&s->chr);
 
-            s->uart_status |= UART_STATUS_RXIDLE;
-            s->uart_status |= UART_STATUS_RXEMPTY;
+            s->uart_status |= R_STATUS_RXIDLE_MASK;
+            s->uart_status |= R_STATUS_RXEMPTY_MASK;
         }
         break;
-    case IBEX_UART_WDATA:
+    case R_WDATA:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: wdata is write only\n", __func__);
         break;
 
-    case IBEX_UART_FIFO_CTRL:
+    case R_FIFO_CTRL:
         retvalue = s->uart_fifo_ctrl;
         break;
-    case IBEX_UART_FIFO_STATUS:
+    case R_FIFO_STATUS:
         retvalue = s->uart_fifo_status;
 
         retvalue |= s->tx_level & 0x1F;
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
                       "%s: RX fifos are not supported\n", __func__);
         break;
 
-    case IBEX_UART_OVRD:
+    case R_OVRD:
         retvalue = s->uart_ovrd;
         qemu_log_mask(LOG_UNIMP,
                       "%s: ovrd is not supported\n", __func__);
         break;
-    case IBEX_UART_VAL:
+    case R_VAL:
         retvalue = s->uart_val;
         qemu_log_mask(LOG_UNIMP,
                       "%s: val is not supported\n", __func__);
         break;
-    case IBEX_UART_TIMEOUT_CTRL:
+    case R_TIMEOUT_CTRL:
         retvalue = s->uart_timeout_ctrl;
         qemu_log_mask(LOG_UNIMP,
                       "%s: timeout_ctrl is not supported\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
     IbexUartState *s = opaque;
     uint32_t value = val64;
 
-    switch (addr) {
-    case IBEX_UART_INTR_STATE:
+    switch (addr >> 2) {
+    case R_INTR_STATE:
         /* Write 1 clear */
         s->uart_intr_state &= ~value;
         ibex_uart_update_irqs(s);
         break;
-    case IBEX_UART_INTR_ENABLE:
+    case R_INTR_ENABLE:
         s->uart_intr_enable = value;
         ibex_uart_update_irqs(s);
         break;
-    case IBEX_UART_INTR_TEST:
+    case R_INTR_TEST:
         s->uart_intr_state |= value;
         ibex_uart_update_irqs(s);
         break;
 
-    case IBEX_UART_CTRL:
+    case R_CTRL:
         s->uart_ctrl = value;
 
-        if (value & UART_CTRL_NF) {
+        if (value & R_CTRL_NF_MASK) {
             qemu_log_mask(LOG_UNIMP,
                           "%s: UART_CTRL_NF is not supported\n", __func__);
         }
-        if (value & UART_CTRL_SLPBK) {
+        if (value & R_CTRL_SLPBK_MASK) {
             qemu_log_mask(LOG_UNIMP,
                           "%s: UART_CTRL_SLPBK is not supported\n", __func__);
         }
-        if (value & UART_CTRL_LLPBK) {
+        if (value & R_CTRL_LLPBK_MASK) {
             qemu_log_mask(LOG_UNIMP,
                           "%s: UART_CTRL_LLPBK is not supported\n", __func__);
         }
-        if (value & UART_CTRL_PARITY_EN) {
+        if (value & R_CTRL_PARITY_EN_MASK) {
             qemu_log_mask(LOG_UNIMP,
                           "%s: UART_CTRL_PARITY_EN is not supported\n",
                           __func__);
         }
-        if (value & UART_CTRL_PARITY_ODD) {
+        if (value & R_CTRL_PARITY_ODD_MASK) {
             qemu_log_mask(LOG_UNIMP,
                           "%s: UART_CTRL_PARITY_ODD is not supported\n",
                           __func__);
         }
-        if (value & UART_CTRL_RXBLVL) {
+        if (value & R_CTRL_RXBLVL_MASK) {
             qemu_log_mask(LOG_UNIMP,
                           "%s: UART_CTRL_RXBLVL is not supported\n", __func__);
         }
-        if (value & UART_CTRL_NCO) {
+        if (value & R_CTRL_NCO_MASK) {
             uint64_t baud = ibex_uart_get_baud(s);
 
             s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;
         }
         break;
-    case IBEX_UART_STATUS:
+    case R_STATUS:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: status is read only\n", __func__);
         break;
 
-    case IBEX_UART_RDATA:
+    case R_RDATA:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: rdata is read only\n", __func__);
         break;
-    case IBEX_UART_WDATA:
+    case R_WDATA:
         uart_write_tx_fifo(s, (uint8_t *) &value, 1);
         break;
 
-    case IBEX_UART_FIFO_CTRL:
+    case R_FIFO_CTRL:
         s->uart_fifo_ctrl = value;
 
-        if (value & FIFO_CTRL_RXRST) {
+        if (value & R_FIFO_CTRL_RXRST_MASK) {
             qemu_log_mask(LOG_UNIMP,
                           "%s: RX fifos are not supported\n", __func__);
         }
-        if (value & FIFO_CTRL_TXRST) {
+        if (value & R_FIFO_CTRL_TXRST_MASK) {
             s->tx_level = 0;
         }
         break;
-    case IBEX_UART_FIFO_STATUS:
+    case R_FIFO_STATUS:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: fifo_status is read only\n", __func__);
         break;
 
-    case IBEX_UART_OVRD:
+    case R_OVRD:
         s->uart_ovrd = value;
         qemu_log_mask(LOG_UNIMP,
                       "%s: ovrd is not supported\n", __func__);
         break;
-    case IBEX_UART_VAL:
+    case R_VAL:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: val is read only\n", __func__);
         break;
-    case IBEX_UART_TIMEOUT_CTRL:
+    case R_TIMEOUT_CTRL:
         s->uart_timeout_ctrl = value;
         qemu_log_mask(LOG_UNIMP,
                       "%s: timeout_ctrl is not supported\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void fifo_trigger_update(void *opaque)
 {
     IbexUartState *s = opaque;
 
-    if (s->uart_ctrl & UART_CTRL_TX_ENABLE) {
+    if (s->uart_ctrl & R_CTRL_TX_ENABLE_MASK) {
         ibex_uart_xmit(NULL, G_IO_OUT, s);
     }
 }
-- 
2.27.0

From: Liao Pingfang <liao.pingfang@zte.com.cn>

Remove superfluous breaks, as there is a "return" before them.

Signed-off-by: Liao Pingfang <liao.pingfang@zte.com.cn>
Signed-off-by: Yi Wang <wang.yi59@zte.com.cn>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1594600421-22942-1-git-send-email-wang.yi59@zte.com.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 tcg/riscv/tcg-target.inc.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
         break;
     case R_RISCV_JAL:
         return reloc_jimm20(code_ptr, (tcg_insn_unit *)value);
-        break;
     case R_RISCV_CALL:
         return reloc_call(code_ptr, (tcg_insn_unit *)value);
-        break;
     default:
         tcg_abort();
     }
-- 
2.27.0

From: Alexandre Mergnat <amergnat@baylibre.com>

The end address calculation for NA4 mode is wrong because the address
used isn't shifted.

It doesn't watch 4 bytes but a huge range because the end address
calculation is wrong.

The solution is to use the shifted address calculated for start address
variable.

Modifications are tested on Zephyr OS userspace test suite which works
for other RISC-V boards (E31 and E34 core).

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200706084550.24117-1-amergnat@baylibre.com
Message-Id: <20200706084550.24117-1-amergnat@baylibre.com>
[ Changes by AF:
 - Improve the commit title and message
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
 
     case PMP_AMATCH_NA4:
         sa = this_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
-        ea = (this_addr + 4u) - 1u;
+        ea = (sa + 4u) - 1u;
         break;
 
     case PMP_AMATCH_NAPOT:
-- 
2.27.0

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1:

Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122

for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3:

hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000)

----------------------------------------------------------------
Seventh RISC-V PR for QEMU 6.2

- Deprecate IF_NONE for SiFive OTP
 - Don't reset SiFive OTP content

----------------------------------------------------------------
Philippe Mathieu-Daudé (1):
      hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset

Thomas Huth (1):
      hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE

docs/about/deprecated.rst |  6 ++++++
 hw/misc/sifive_u_otp.c    | 22 +++++++++++++---------
 2 files changed, 19 insertions(+), 9 deletions(-)

From: Thomas Huth <thuth@redhat.com>

Configuring a drive with "if=none" is meant for creation of a backend
only, it should not get automatically assigned to a device frontend.
Use "if=pflash" for the One-Time-Programmable device instead (like
it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c).

Since the old way of configuring the device has already been published
with the previous QEMU versions, we cannot remove this immediately, but
have to deprecate it and support it for at least two more releases.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211119102549.217755-1-thuth@redhat.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/about/deprecated.rst | 6 ++++++
 hw/misc/sifive_u_otp.c    | 9 ++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``.
 However, short-form booleans are deprecated and full explicit ``arg_name=on``
 form is preferred.
 
+``-drive if=none`` for the sifive_u OTP device (since 6.2)
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+Using ``-drive if=none`` to configure the OTP device of the sifive_u
+RISC-V machine is deprecated. Use ``-drive if=pflash`` instead.
+
 
 QEMU Machine Protocol (QMP) commands
 ------------------------------------
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/sifive_u_otp.c
+++ b/hw/misc/sifive_u_otp.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
                           TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
 
-    dinfo = drive_get_next(IF_NONE);
+    dinfo = drive_get_next(IF_PFLASH);
+    if (!dinfo) {
+        dinfo = drive_get_next(IF_NONE);
+        if (dinfo) {
+            warn_report("using \"-drive if=none\" for the OTP is deprecated, "
+                        "use \"-drive if=pflash\" instead.");
+        }
+    }
     if (dinfo) {
         int ret;
         uint64_t perm;
-- 
2.31.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Once a "One Time Programmable" is programmed, it shouldn't be reset.

Do not re-initialize the OTP content in the DeviceReset handler,
initialize it once in the DeviceRealize one.

Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211119104757.331579-1-f4bug@amsat.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/misc/sifive_u_otp.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/sifive_u_otp.c
+++ b/hw/misc/sifive_u_otp.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
 
             if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
                 error_setg(errp, "failed to read the initial flash content");
+                return;
             }
         }
     }
-}
-
-static void sifive_u_otp_reset(DeviceState *dev)
-{
-    SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
 
     /* Initialize all fuses' initial value to 0xFFs */
     memset(s->fuse, 0xff, sizeof(s->fuse));
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
         serial_data = s->serial;
         if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
                        &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
-            error_report("write error index<%d>", index);
+            error_setg(errp, "failed to write index<%d>", index);
+            return;
         }
 
         serial_data = ~(s->serial);
         if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
                        &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
-            error_report("write error index<%d>", index + 1);
+            error_setg(errp, "failed to write index<%d>", index + 1);
+            return;
         }
     }
 
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
 
     device_class_set_props(dc, sifive_u_otp_properties);
     dc->realize = sifive_u_otp_realize;
-    dc->reset = sifive_u_otp_reset;
 }
 
 static const TypeInfo sifive_u_otp_info = {
-- 
2.31.1