On Tue, 7 Jul 2020 at 16:26, Aaron Lindsay <aaron@os.amperecomputing.com> wrote:
>
> Raw writes to this register when in KVM mode can cause interrupts to be
> raised (even when the PMU is disabled). Because the underlying state is
> already aliased to PMINTENSET (which already provides raw write
> functions), we can safely disable raw accesses to PMINTENCLR entirely.
>
> Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
> ---
> target/arm/helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index dc9c29f998..c69a2baf1d 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -2269,13 +2269,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
> .resetvalue = 0x0 },
> { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
> .access = PL1_RW, .accessfn = access_tpm,
> - .type = ARM_CP_ALIAS | ARM_CP_IO,
> + .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
> .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
> .writefn = pmintenclr_write, },
> { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
> .access = PL1_RW, .accessfn = access_tpm,
> - .type = ARM_CP_ALIAS | ARM_CP_IO,
> + .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
> .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
> .writefn = pmintenclr_write },
> { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
> --
> 2.17.1
Applied to target-arm.next, thanks. (Annoyingly I have forgotten
what the test case was and now can't repro it, but this fix
looks right.)
-- PMM