[PULL 0/2] tcg patch queue
[PULL 0/4] tcg patch queue
1
The following changes since commit eb6490f544388dd24c0d054a96dd304bc7284450:
1
Pretty small still, but there are two patches that ought
2
to get backported to stable, so no point in delaying.
2
3
3
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200703' into staging (2020-07-04 16:08:41 +0100)
4
r~
5
6
The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
7
8
Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
4
9
5
are available in the Git repository at:
10
are available in the Git repository at:
6
11
7
https://github.com/rth7680/qemu.git tags/pull-tcg-20200706
12
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212
8
13
9
for you to fetch changes up to 852f933e482518797f7785a2e017a215b88df815:
14
for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:
10
15
11
tcg: Fix do_nonatomic_op_* vs signed operations (2020-07-06 10:58:19 -0700)
16
target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)
12
17
13
----------------------------------------------------------------
18
----------------------------------------------------------------
14
Fix for ppc shifts
19
tcg: Reset free_temps before tcg_optimize
15
Fix for non-parallel atomic ops
20
tcg/riscv: Fix StoreStore barrier generation
21
include/exec: Introduce fpst alias in helper-head.h.inc
22
target/sparc: Use memcpy() and remove memcpy32()
16
23
17
----------------------------------------------------------------
24
----------------------------------------------------------------
18
Catherine A. Frederick (1):
25
Philippe Mathieu-Daudé (1):
19
tcg/ppc: Sanitize immediate shifts
26
target/sparc: Use memcpy() and remove memcpy32()
20
27
21
Richard Henderson (1):
28
Richard Henderson (2):
22
tcg: Fix do_nonatomic_op_* vs signed operations
29
tcg: Reset free_temps before tcg_optimize
30
include/exec: Introduce fpst alias in helper-head.h.inc
23
31
24
tcg/ppc/tcg-target.inc.c | 15 ++++++++++-----
32
Roman Artemev (1):
25
tcg/tcg-op.c | 10 ++++++----
33
tcg/riscv: Fix StoreStore barrier generation
26
2 files changed, 16 insertions(+), 9 deletions(-)
27
34
35
include/tcg/tcg-temp-internal.h | 6 ++++++
36
accel/tcg/plugin-gen.c | 2 +-
37
target/sparc/win_helper.c | 26 ++++++++------------------
38
tcg/tcg.c | 5 ++++-
39
include/exec/helper-head.h.inc | 3 +++
40
tcg/riscv/tcg-target.c.inc | 2 +-
41
6 files changed, 23 insertions(+), 21 deletions(-)
42
diff view generated by jsdifflib
New patch
[PULL 1/4] tcg: Reset free_temps before tcg_optimize
1
When allocating new temps during tcg_optmize, do not re-use
2
any EBB temps that were used within the TB. We do not have
3
any idea what span of the TB in which the temp was live.
1
4
5
Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
6
as well as replacing the equivalent in plugin_gen_inject and
7
tcg_func_start.
8
9
Cc: qemu-stable@nongnu.org
10
Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
11
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
12
Reported-by: wannacu <wannacu2049@gmail.com>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
16
---
17
include/tcg/tcg-temp-internal.h | 6 ++++++
18
accel/tcg/plugin-gen.c | 2 +-
19
tcg/tcg.c | 5 ++++-
20
3 files changed, 11 insertions(+), 2 deletions(-)
21
22
diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/include/tcg/tcg-temp-internal.h
25
+++ b/include/tcg/tcg-temp-internal.h
26
@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
27
TCGv_ptr tcg_temp_ebb_new_ptr(void);
28
TCGv_i128 tcg_temp_ebb_new_i128(void);
29
30
+/* Forget all freed EBB temps, so that new allocations produce new temps. */
31
+static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
32
+{
33
+ memset(s->free_temps, 0, sizeof(s->free_temps));
34
+}
35
+
36
#endif /* TCG_TEMP_FREE_H */
37
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/accel/tcg/plugin-gen.c
40
+++ b/accel/tcg/plugin-gen.c
41
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
42
* that might be live within the existing opcode stream.
43
* The simplest solution is to release them all and create new.
44
*/
45
- memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
46
+ tcg_temp_ebb_reset_freed(tcg_ctx);
47
48
QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
49
switch (op->opc) {
50
diff --git a/tcg/tcg.c b/tcg/tcg.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/tcg/tcg.c
53
+++ b/tcg/tcg.c
54
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
55
s->nb_temps = s->nb_globals;
56
57
/* No temps have been previously allocated for size or locality. */
58
- memset(s->free_temps, 0, sizeof(s->free_temps));
59
+ tcg_temp_ebb_reset_freed(s);
60
61
/* No constant temps have been previously allocated. */
62
for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
63
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
64
}
65
#endif
66
67
+ /* Do not reuse any EBB that may be allocated within the TB. */
68
+ tcg_temp_ebb_reset_freed(s);
69
+
70
tcg_optimize(s);
71
72
reachable_code_pass(s);
73
--
74
2.43.0
75
76
diff view generated by jsdifflib
New patch
[PULL 2/4] tcg/riscv: Fix StoreStore barrier generation
1
From: Roman Artemev <roman.artemev@syntacore.com>
1
2
3
On RISC-V to StoreStore barrier corresponds
4
`fence w, w` not `fence r, r`
5
6
Cc: qemu-stable@nongnu.org
7
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
10
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
11
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
14
tcg/riscv/tcg-target.c.inc | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
18
index XXXXXXX..XXXXXXX 100644
19
--- a/tcg/riscv/tcg-target.c.inc
20
+++ b/tcg/riscv/tcg-target.c.inc
21
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
22
insn |= 0x02100000;
23
}
24
if (a0 & TCG_MO_ST_ST) {
25
- insn |= 0x02200000;
26
+ insn |= 0x01100000;
27
}
28
tcg_out32(s, insn);
29
}
30
--
31
2.43.0
diff view generated by jsdifflib
[PULL 2/2] tcg: Fix do_nonatomic_op_* vs signed operations
[PULL 3/4] include/exec: Introduce fpst alias in helper-head.h.inc
1
The smin/smax/umin/umax operations require the operands to be
1
This allows targets to declare that the helper requires a
2
properly sign extended. Do not drop the MO_SIGN bit from the
2
float_status pointer and instead of a generic void pointer.
3
load, and additionally extend the val input.
4
3
5
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reported-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-Id: <20200701165646.1901320-1-richard.henderson@linaro.org>
9
---
6
---
10
tcg/tcg-op.c | 10 ++++++----
7
include/exec/helper-head.h.inc | 3 +++
11
1 file changed, 6 insertions(+), 4 deletions(-)
8
1 file changed, 3 insertions(+)
12
9
13
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
10
diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
14
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
15
--- a/tcg/tcg-op.c
12
--- a/include/exec/helper-head.h.inc
16
+++ b/tcg/tcg-op.c
13
+++ b/include/exec/helper-head.h.inc
17
@@ -XXX,XX +XXX,XX @@ static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,
14
@@ -XXX,XX +XXX,XX @@
18
15
#define dh_alias_ptr ptr
19
memop = tcg_canonicalize_memop(memop, 0, 0);
16
#define dh_alias_cptr ptr
20
17
#define dh_alias_env ptr
21
- tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN);
18
+#define dh_alias_fpst ptr
22
- gen(t2, t1, val);
19
#define dh_alias_void void
23
+ tcg_gen_qemu_ld_i32(t1, addr, idx, memop);
20
#define dh_alias_noreturn noreturn
24
+ tcg_gen_ext_i32(t2, val, memop);
21
#define dh_alias(t) glue(dh_alias_, t)
25
+ gen(t2, t1, t2);
22
@@ -XXX,XX +XXX,XX @@
26
tcg_gen_qemu_st_i32(t2, addr, idx, memop);
23
#define dh_ctype_ptr void *
27
24
#define dh_ctype_cptr const void *
28
tcg_gen_ext_i32(ret, (new_val ? t2 : t1), memop);
25
#define dh_ctype_env CPUArchState *
29
@@ -XXX,XX +XXX,XX @@ static void do_nonatomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
26
+#define dh_ctype_fpst float_status *
30
27
#define dh_ctype_void void
31
memop = tcg_canonicalize_memop(memop, 1, 0);
28
#define dh_ctype_noreturn G_NORETURN void
32
29
#define dh_ctype(t) dh_ctype_##t
33
- tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN);
30
@@ -XXX,XX +XXX,XX @@
34
- gen(t2, t1, val);
31
#define dh_typecode_f64 dh_typecode_i64
35
+ tcg_gen_qemu_ld_i64(t1, addr, idx, memop);
32
#define dh_typecode_cptr dh_typecode_ptr
36
+ tcg_gen_ext_i64(t2, val, memop);
33
#define dh_typecode_env dh_typecode_ptr
37
+ gen(t2, t1, t2);
34
+#define dh_typecode_fpst dh_typecode_ptr
38
tcg_gen_qemu_st_i64(t2, addr, idx, memop);
35
#define dh_typecode(t) dh_typecode_##t
39
36
40
tcg_gen_ext_i64(ret, (new_val ? t2 : t1), memop);
37
#define dh_callflag_i32 0
41
--
38
--
42
2.25.1
39
2.43.0
43
40
44
41
diff view generated by jsdifflib
[PULL 1/2] tcg/ppc: Sanitize immediate shifts
[PULL 4/4] target/sparc: Use memcpy() and remove memcpy32()
1
From: "Catherine A. Frederick" <chocola@animebitch.es>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Sanitize shift constants so that shift operations with
3
Rather than manually copying each register, use
4
large constants don't generate invalid instructions.
4
the libc memcpy(), which is well optimized nowadays.
5
5
6
Signed-off-by: Catherine A. Frederick <chocola@animebitch.es>
6
Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Message-Id: <20200607211100.22858-1-agrecascino123@gmail.com>
7
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-ID: <20241205205418.67613-1-philmd@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
12
---
10
tcg/ppc/tcg-target.inc.c | 15 ++++++++++-----
13
target/sparc/win_helper.c | 26 ++++++++------------------
11
1 file changed, 10 insertions(+), 5 deletions(-)
14
1 file changed, 8 insertions(+), 18 deletions(-)
12
15
13
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
16
diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/tcg/ppc/tcg-target.inc.c
18
--- a/target/sparc/win_helper.c
16
+++ b/tcg/ppc/tcg-target.inc.c
19
+++ b/target/sparc/win_helper.c
17
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
20
@@ -XXX,XX +XXX,XX @@
18
21
#include "exec/helper-proto.h"
19
case INDEX_op_shl_i32:
22
#include "trace.h"
20
if (const_args[2]) {
23
21
- tcg_out_shli32(s, args[0], args[1], args[2]);
24
-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
22
+ /* Limit immediate shift count lest we create an illegal insn. */
25
-{
23
+ tcg_out_shli32(s, args[0], args[1], args[2] & 31);
26
- dst[0] = src[0];
24
} else {
27
- dst[1] = src[1];
25
tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
28
- dst[2] = src[2];
26
}
29
- dst[3] = src[3];
27
break;
30
- dst[4] = src[4];
28
case INDEX_op_shr_i32:
31
- dst[5] = src[5];
29
if (const_args[2]) {
32
- dst[6] = src[6];
30
- tcg_out_shri32(s, args[0], args[1], args[2]);
33
- dst[7] = src[7];
31
+ /* Limit immediate shift count lest we create an illegal insn. */
34
-}
32
+ tcg_out_shri32(s, args[0], args[1], args[2] & 31);
35
-
33
} else {
36
void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
34
tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
37
{
35
}
38
/* put the modified wrap registers at their proper location */
36
break;
39
if (env->cwp == env->nwindows - 1) {
37
case INDEX_op_sar_i32:
40
- memcpy32(env->regbase, env->regbase + env->nwindows * 16);
38
if (const_args[2]) {
41
+ memcpy(env->regbase, env->regbase + env->nwindows * 16,
39
- tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2]));
42
+ sizeof(env->gregs));
40
+ /* Limit immediate shift count lest we create an illegal insn. */
43
}
41
+ tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2] & 31));
44
env->cwp = new_cwp;
42
} else {
45
43
tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
46
/* put the wrap registers at their temporary location */
44
}
47
if (new_cwp == env->nwindows - 1) {
45
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
48
- memcpy32(env->regbase + env->nwindows * 16, env->regbase);
46
49
+ memcpy(env->regbase + env->nwindows * 16, env->regbase,
47
case INDEX_op_shl_i64:
50
+ sizeof(env->gregs));
48
if (const_args[2]) {
51
}
49
- tcg_out_shli64(s, args[0], args[1], args[2]);
52
env->regwptr = env->regbase + (new_cwp * 16);
50
+ /* Limit immediate shift count lest we create an illegal insn. */
53
}
51
+ tcg_out_shli64(s, args[0], args[1], args[2] & 63);
54
@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
52
} else {
55
dst = get_gl_gregset(env, env->gl);
53
tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
56
54
}
57
if (src != dst) {
55
break;
58
- memcpy32(dst, env->gregs);
56
case INDEX_op_shr_i64:
59
- memcpy32(env->gregs, src);
57
if (const_args[2]) {
60
+ memcpy(dst, env->gregs, sizeof(env->gregs));
58
- tcg_out_shri64(s, args[0], args[1], args[2]);
61
+ memcpy(env->gregs, src, sizeof(env->gregs));
59
+ /* Limit immediate shift count lest we create an illegal insn. */
62
}
60
+ tcg_out_shri64(s, args[0], args[1], args[2] & 63);
63
}
61
} else {
64
62
tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
65
@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
63
}
66
/* Switch global register bank */
67
src = get_gregset(env, new_pstate_regs);
68
dst = get_gregset(env, pstate_regs);
69
- memcpy32(dst, env->gregs);
70
- memcpy32(env->gregs, src);
71
+ memcpy(dst, env->gregs, sizeof(env->gregs));
72
+ memcpy(env->gregs, src, sizeof(env->gregs));
73
} else {
74
trace_win_helper_no_switch_pstate(new_pstate_regs);
75
}
64
--
76
--
65
2.25.1
77
2.43.0
66
78
67
79
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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