[PULL 00/34] target-arm queue
[PULL 00/72] target-arm queue
1
I might squeeze in another pullreq before softfreeze, but the
1
First arm pullreq of the cycle; this is mostly my softfloat NaN
2
queue was already big enough that I wanted to send this lot out now.
2
handling series. (Lots more in my to-review queue, but I don't
3
like pullreqs growing too close to a hundred patches at a time :-))
3
4
5
thanks
4
-- PMM
6
-- PMM
5
7
6
The following changes since commit 4abf70a661a5df3886ac9d7c19c3617fa92b922a:
8
The following changes since commit 97f2796a3736ed37a1b85dc1c76a6c45b829dd17:
7
9
8
Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2020-06-24' into staging (2020-07-03 15:34:45 +0100)
10
Open 10.0 development tree (2024-12-10 17:41:17 +0000)
9
11
10
are available in the Git repository at:
12
are available in the Git repository at:
11
13
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200703
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241211
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15
14
for you to fetch changes up to 0f10bf84a9d489259a5b11c6aa1b05c1175b76ea:
16
for you to fetch changes up to 1abe28d519239eea5cf9620bb13149423e5665f8:
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17
16
Deprecate TileGX port (2020-07-03 16:59:46 +0100)
18
MAINTAINERS: Add correct email address for Vikram Garhwal (2024-12-11 15:31:09 +0000)
17
19
18
----------------------------------------------------------------
20
----------------------------------------------------------------
19
target-arm queue:
21
target-arm queue:
20
* i.MX6UL EVK board: put PHYs in the correct places
22
* hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs
21
* hw/arm/virt: Let the virtio-iommu bypass MSIs
23
* fpu: Make muladd NaN handling runtime-selected, not compile-time
22
* target/arm: kvm: Handle DABT with no valid ISS
24
* fpu: Make default NaN pattern runtime-selected, not compile-time
23
* hw/arm/virt-acpi-build: Only expose flash on older machine types
25
* fpu: Minor NaN-related cleanups
24
* target/arm: Fix temp double-free in sve ldr/str
26
* MAINTAINERS: email address updates
25
* hw/display/bcm2835_fb.c: Initialize all fields of struct
26
* hw/arm/spitz: Code cleanup to fix Coverity-detected memory leak
27
* Deprecate TileGX port
28
27
29
----------------------------------------------------------------
28
----------------------------------------------------------------
30
Andrew Jones (4):
29
Bernhard Beschow (5):
31
tests/acpi: remove stale allowed tables
30
hw/net/lan9118: Extract lan9118_phy
32
tests/acpi: virt: allow DSDT acpi table changes
31
hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
33
hw/arm/virt-acpi-build: Only expose flash on older machine types
32
hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
34
tests/acpi: virt: update golden masters for DSDT
33
hw/net/lan9118_phy: Reuse MII constants
34
hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
35
35
36
Beata Michalska (2):
36
Leif Lindholm (1):
37
target/arm: kvm: Handle DABT with no valid ISS
37
MAINTAINERS: update email address for Leif Lindholm
38
target/arm: kvm: Handle misconfigured dabt injection
39
38
40
Eric Auger (5):
39
Peter Maydell (54):
41
qdev: Introduce DEFINE_PROP_RESERVED_REGION
40
fpu: handle raising Invalid for infzero in pick_nan_muladd
42
virtio-iommu: Implement RESV_MEM probe request
41
fpu: Check for default_nan_mode before calling pickNaNMulAdd
43
virtio-iommu: Handle reserved regions in the translation process
42
softfloat: Allow runtime choice of inf * 0 + NaN result
44
virtio-iommu-pci: Add array of Interval properties
43
tests/fp: Explicitly set inf-zero-nan rule
45
hw/arm/virt: Let the virtio-iommu bypass MSIs
44
target/arm: Set FloatInfZeroNaNRule explicitly
45
target/s390: Set FloatInfZeroNaNRule explicitly
46
target/ppc: Set FloatInfZeroNaNRule explicitly
47
target/mips: Set FloatInfZeroNaNRule explicitly
48
target/sparc: Set FloatInfZeroNaNRule explicitly
49
target/xtensa: Set FloatInfZeroNaNRule explicitly
50
target/x86: Set FloatInfZeroNaNRule explicitly
51
target/loongarch: Set FloatInfZeroNaNRule explicitly
52
target/hppa: Set FloatInfZeroNaNRule explicitly
53
softfloat: Pass have_snan to pickNaNMulAdd
54
softfloat: Allow runtime choice of NaN propagation for muladd
55
tests/fp: Explicitly set 3-NaN propagation rule
56
target/arm: Set Float3NaNPropRule explicitly
57
target/loongarch: Set Float3NaNPropRule explicitly
58
target/ppc: Set Float3NaNPropRule explicitly
59
target/s390x: Set Float3NaNPropRule explicitly
60
target/sparc: Set Float3NaNPropRule explicitly
61
target/mips: Set Float3NaNPropRule explicitly
62
target/xtensa: Set Float3NaNPropRule explicitly
63
target/i386: Set Float3NaNPropRule explicitly
64
target/hppa: Set Float3NaNPropRule explicitly
65
fpu: Remove use_first_nan field from float_status
66
target/m68k: Don't pass NULL float_status to floatx80_default_nan()
67
softfloat: Create floatx80 default NaN from parts64_default_nan
68
target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
69
target/m68k: In frem helper, initialize local float_status from env->fp_status
70
target/m68k: Init local float_status from env fp_status in gdb get/set reg
71
target/sparc: Initialize local scratch float_status from env->fp_status
72
target/ppc: Use env->fp_status in helper_compute_fprf functions
73
fpu: Allow runtime choice of default NaN value
74
tests/fp: Set default NaN pattern explicitly
75
target/microblaze: Set default NaN pattern explicitly
76
target/i386: Set default NaN pattern explicitly
77
target/hppa: Set default NaN pattern explicitly
78
target/alpha: Set default NaN pattern explicitly
79
target/arm: Set default NaN pattern explicitly
80
target/loongarch: Set default NaN pattern explicitly
81
target/m68k: Set default NaN pattern explicitly
82
target/mips: Set default NaN pattern explicitly
83
target/openrisc: Set default NaN pattern explicitly
84
target/ppc: Set default NaN pattern explicitly
85
target/sh4: Set default NaN pattern explicitly
86
target/rx: Set default NaN pattern explicitly
87
target/s390x: Set default NaN pattern explicitly
88
target/sparc: Set default NaN pattern explicitly
89
target/xtensa: Set default NaN pattern explicitly
90
target/hexagon: Set default NaN pattern explicitly
91
target/riscv: Set default NaN pattern explicitly
92
target/tricore: Set default NaN pattern explicitly
93
fpu: Remove default handling for dnan_pattern
46
94
47
Jean-Christophe Dubois (3):
95
Richard Henderson (11):
48
Add a phy-num property to the i.MX FEC emulator
96
target/arm: Copy entire float_status in is_ebf
49
Add the ability to select a different PHY for each i.MX6UL FEC interface
97
softfloat: Inline pickNaNMulAdd
50
Select MDIO device 2 and 1 as PHY devices for i.MX6UL EVK board.
98
softfloat: Use goto for default nan case in pick_nan_muladd
99
softfloat: Remove which from parts_pick_nan_muladd
100
softfloat: Pad array size in pick_nan_muladd
101
softfloat: Move propagateFloatx80NaN to softfloat.c
102
softfloat: Use parts_pick_nan in propagateFloatx80NaN
103
softfloat: Inline pickNaN
104
softfloat: Share code between parts_pick_nan cases
105
softfloat: Sink frac_cmp in parts_pick_nan until needed
106
softfloat: Replace WHICH with RET in parts_pick_nan
51
107
52
Peter Maydell (19):
108
Vikram Garhwal (1):
53
hw/display/bcm2835_fb.c: Initialize all fields of struct
109
MAINTAINERS: Add correct email address for Vikram Garhwal
54
hw/arm/spitz: Detabify
55
hw/arm/spitz: Create SpitzMachineClass abstract base class
56
hw/arm/spitz: Keep pointers to MPU and SSI devices in SpitzMachineState
57
hw/arm/spitz: Keep pointers to scp0, scp1 in SpitzMachineState
58
hw/arm/spitz: Implement inbound GPIO lines for bit5 and power signals
59
hw/misc/max111x: provide QOM properties for setting initial values
60
hw/misc/max111x: Don't use vmstate_register()
61
ssi: Add ssi_realize_and_unref()
62
hw/arm/spitz: Use max111x properties to set initial values
63
hw/misc/max111x: Use GPIO lines rather than max111x_set_input()
64
hw/misc/max111x: Create header file for documentation, TYPE_ macros
65
hw/arm/spitz: Encapsulate misc GPIO handling in a device
66
hw/gpio/zaurus.c: Use LOG_GUEST_ERROR for bad guest register accesses
67
hw/arm/spitz: Use LOG_GUEST_ERROR for bad guest register accesses
68
hw/arm/pxa2xx_pic: Use LOG_GUEST_ERROR for bad guest register accesses
69
hw/arm/spitz: Provide usual QOM macros for corgi-ssp and spitz-lcdtg
70
Replace uses of FROM_SSI_SLAVE() macro with QOM casts
71
Deprecate TileGX port
72
110
73
Richard Henderson (1):
111
MAINTAINERS | 4 +-
74
target/arm: Fix temp double-free in sve ldr/str
112
include/fpu/softfloat-helpers.h | 38 +++-
75
113
include/fpu/softfloat-types.h | 89 +++++++-
76
docs/system/deprecated.rst | 11 +
114
include/hw/net/imx_fec.h | 9 +-
77
include/exec/memory.h | 6 +
115
include/hw/net/lan9118_phy.h | 37 ++++
78
include/hw/arm/fsl-imx6ul.h | 2 +
116
include/hw/net/mii.h | 6 +
79
include/hw/arm/pxa.h | 1 -
117
target/mips/fpu_helper.h | 20 ++
80
include/hw/arm/sharpsl.h | 3 -
118
target/sparc/helper.h | 4 +-
81
include/hw/arm/virt.h | 8 +
119
fpu/softfloat.c | 19 ++
82
include/hw/misc/max111x.h | 56 +++
120
hw/net/imx_fec.c | 146 ++------------
83
include/hw/net/imx_fec.h | 1 +
121
hw/net/lan9118.c | 137 ++-----------
84
include/hw/qdev-properties.h | 3 +
122
hw/net/lan9118_phy.c | 222 ++++++++++++++++++++
85
include/hw/ssi/ssi.h | 31 +-
123
linux-user/arm/nwfpe/fpa11.c | 5 +
86
include/hw/virtio/virtio-iommu.h | 2 +
124
target/alpha/cpu.c | 2 +
87
include/qemu/typedefs.h | 1 +
125
target/arm/cpu.c | 10 +
88
target/arm/cpu.h | 2 +
126
target/arm/tcg/vec_helper.c | 20 +-
89
target/arm/kvm_arm.h | 10 +
127
target/hexagon/cpu.c | 2 +
90
target/arm/translate-a64.h | 1 +
128
target/hppa/fpu_helper.c | 12 ++
91
tests/qtest/bios-tables-test-allowed-diff.h | 18 -
129
target/i386/tcg/fpu_helper.c | 12 ++
92
hw/arm/fsl-imx6ul.c | 10 +
130
target/loongarch/tcg/fpu_helper.c | 14 +-
93
hw/arm/mcimx6ul-evk.c | 2 +
131
target/m68k/cpu.c | 14 +-
94
hw/arm/pxa2xx_pic.c | 9 +-
132
target/m68k/fpu_helper.c | 6 +-
95
hw/arm/spitz.c | 507 ++++++++++++++++------------
133
target/m68k/helper.c | 6 +-
96
hw/arm/virt-acpi-build.c | 5 +-
134
target/microblaze/cpu.c | 2 +
97
hw/arm/virt.c | 33 ++
135
target/mips/msa.c | 10 +
98
hw/arm/z2.c | 11 +-
136
target/openrisc/cpu.c | 2 +
99
hw/core/qdev-properties.c | 89 +++++
137
target/ppc/cpu_init.c | 19 ++
100
hw/display/ads7846.c | 9 +-
138
target/ppc/fpu_helper.c | 3 +-
101
hw/display/bcm2835_fb.c | 4 +
139
target/riscv/cpu.c | 2 +
102
hw/display/ssd0323.c | 10 +-
140
target/rx/cpu.c | 2 +
103
hw/gpio/zaurus.c | 12 +-
141
target/s390x/cpu.c | 5 +
104
hw/misc/max111x.c | 86 +++--
142
target/sh4/cpu.c | 2 +
105
hw/net/imx_fec.c | 24 +-
143
target/sparc/cpu.c | 6 +
106
hw/sd/ssi-sd.c | 4 +-
144
target/sparc/fop_helper.c | 8 +-
107
hw/ssi/ssi.c | 7 +-
145
target/sparc/translate.c | 4 +-
108
hw/virtio/virtio-iommu-pci.c | 11 +
146
target/tricore/helper.c | 2 +
109
hw/virtio/virtio-iommu.c | 114 ++++++-
147
target/xtensa/cpu.c | 4 +
110
target/arm/kvm.c | 80 +++++
148
target/xtensa/fpu_helper.c | 3 +-
111
target/arm/kvm32.c | 34 ++
149
tests/fp/fp-bench.c | 7 +
112
target/arm/kvm64.c | 49 +++
150
tests/fp/fp-test-log2.c | 1 +
113
target/arm/translate-a64.c | 6 +
151
tests/fp/fp-test.c | 7 +
114
target/arm/translate-sve.c | 8 +-
152
fpu/softfloat-parts.c.inc | 152 +++++++++++---
115
MAINTAINERS | 1 +
153
fpu/softfloat-specialize.c.inc | 412 ++------------------------------------
116
hw/net/trace-events | 4 +-
154
.mailmap | 5 +-
117
hw/virtio/trace-events | 1 +
155
hw/net/Kconfig | 5 +
118
tests/data/acpi/virt/DSDT | Bin 5307 -> 5205 bytes
156
hw/net/meson.build | 1 +
119
tests/data/acpi/virt/DSDT.memhp | Bin 6668 -> 6566 bytes
157
hw/net/trace-events | 10 +-
120
tests/data/acpi/virt/DSDT.numamem | Bin 5307 -> 5205 bytes
158
47 files changed, 778 insertions(+), 730 deletions(-)
121
45 files changed, 974 insertions(+), 312 deletions(-)
159
create mode 100644 include/hw/net/lan9118_phy.h
122
create mode 100644 include/hw/misc/max111x.h
160
create mode 100644 hw/net/lan9118_phy.c
123
diff view generated by jsdifflib
[PULL 27/34] hw/misc/max111x: Create header file for documentation, TYPE_ macros
[PULL 01/72] hw/net/lan9118: Extract lan9118_phy
1
Create a header file for the hw/misc/max111x device, in the
1
From: Bernhard Beschow <shentey@gmail.com>
2
usual modern style for QOM devices:
3
* definition of the TYPE_ constants and macros
4
* definition of the device's state struct so that it can
5
be embedded in other structs if desired
6
* documentation of the interface
7
2
8
This allows us to use TYPE_MAX_1111 in the spitz.c code rather
3
A very similar implementation of the same device exists in imx_fec. Prepare for
9
than the string "max1111".
4
a common implementation by extracting a device model into its own files.
10
5
6
Some migration state has been moved into the new device model which breaks
7
migration compatibility for the following machines:
8
* smdkc210
9
* realview-*
10
* vexpress-*
11
* kzm
12
* mps2-*
13
14
While breaking migration ABI, fix the size of the MII registers to be 16 bit,
15
as defined by IEEE 802.3u.
16
17
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
18
Tested-by: Guenter Roeck <linux@roeck-us.net>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Message-id: 20241102125724.532843-2-shentey@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20200628142429.17111-12-peter.maydell@linaro.org
14
---
22
---
15
include/hw/misc/max111x.h | 56 +++++++++++++++++++++++++++++++++++++++
23
include/hw/net/lan9118_phy.h | 37 ++++++++
16
hw/arm/spitz.c | 3 ++-
24
hw/net/lan9118.c | 137 +++++-----------------------
17
hw/misc/max111x.c | 24 +----------------
25
hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++
18
MAINTAINERS | 1 +
26
hw/net/Kconfig | 4 +
19
4 files changed, 60 insertions(+), 24 deletions(-)
27
hw/net/meson.build | 1 +
20
create mode 100644 include/hw/misc/max111x.h
28
5 files changed, 233 insertions(+), 115 deletions(-)
29
create mode 100644 include/hw/net/lan9118_phy.h
30
create mode 100644 hw/net/lan9118_phy.c
21
31
22
diff --git a/include/hw/misc/max111x.h b/include/hw/misc/max111x.h
32
diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h
23
new file mode 100644
33
new file mode 100644
24
index XXXXXXX..XXXXXXX
34
index XXXXXXX..XXXXXXX
25
--- /dev/null
35
--- /dev/null
26
+++ b/include/hw/misc/max111x.h
36
+++ b/include/hw/net/lan9118_phy.h
27
@@ -XXX,XX +XXX,XX @@
37
@@ -XXX,XX +XXX,XX @@
28
+/*
38
+/*
29
+ * Maxim MAX1110/1111 ADC chip emulation.
39
+ * SMSC LAN9118 PHY emulation
30
+ *
40
+ *
31
+ * Copyright (c) 2006 Openedhand Ltd.
41
+ * Copyright (c) 2009 CodeSourcery, LLC.
32
+ * Written by Andrzej Zaborowski <balrog@zabor.org>
42
+ * Written by Paul Brook
33
+ *
43
+ *
34
+ * This code is licensed under the GNU GPLv2.
44
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
45
+ * See the COPYING file in the top-level directory.
46
+ */
47
+
48
+#ifndef HW_NET_LAN9118_PHY_H
49
+#define HW_NET_LAN9118_PHY_H
50
+
51
+#include "qom/object.h"
52
+#include "hw/sysbus.h"
53
+
54
+#define TYPE_LAN9118_PHY "lan9118-phy"
55
+OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY)
56
+
57
+typedef struct Lan9118PhyState {
58
+ SysBusDevice parent_obj;
59
+
60
+ uint16_t status;
61
+ uint16_t control;
62
+ uint16_t advertise;
63
+ uint16_t ints;
64
+ uint16_t int_mask;
65
+ qemu_irq irq;
66
+ bool link_down;
67
+} Lan9118PhyState;
68
+
69
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down);
70
+void lan9118_phy_reset(Lan9118PhyState *s);
71
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg);
72
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val);
73
+
74
+#endif
75
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
76
index XXXXXXX..XXXXXXX 100644
77
--- a/hw/net/lan9118.c
78
+++ b/hw/net/lan9118.c
79
@@ -XXX,XX +XXX,XX @@
80
#include "net/net.h"
81
#include "net/eth.h"
82
#include "hw/irq.h"
83
+#include "hw/net/lan9118_phy.h"
84
#include "hw/net/lan9118.h"
85
#include "hw/ptimer.h"
86
#include "hw/qdev-properties.h"
87
@@ -XXX,XX +XXX,XX @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
88
#define MAC_CR_RXEN 0x00000004
89
#define MAC_CR_RESERVED 0x7f404213
90
91
-#define PHY_INT_ENERGYON 0x80
92
-#define PHY_INT_AUTONEG_COMPLETE 0x40
93
-#define PHY_INT_FAULT 0x20
94
-#define PHY_INT_DOWN 0x10
95
-#define PHY_INT_AUTONEG_LP 0x08
96
-#define PHY_INT_PARFAULT 0x04
97
-#define PHY_INT_AUTONEG_PAGE 0x02
98
-
99
#define GPT_TIMER_EN 0x20000000
100
101
/*
102
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
103
uint32_t mac_mii_data;
104
uint32_t mac_flow;
105
106
- uint32_t phy_status;
107
- uint32_t phy_control;
108
- uint32_t phy_advertise;
109
- uint32_t phy_int;
110
- uint32_t phy_int_mask;
111
+ Lan9118PhyState mii;
112
+ IRQState mii_irq;
113
114
int32_t eeprom_writable;
115
uint8_t eeprom[128];
116
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
117
118
static const VMStateDescription vmstate_lan9118 = {
119
.name = "lan9118",
120
- .version_id = 2,
121
- .minimum_version_id = 1,
122
+ .version_id = 3,
123
+ .minimum_version_id = 3,
124
.fields = (const VMStateField[]) {
125
VMSTATE_PTIMER(timer, lan9118_state),
126
VMSTATE_UINT32(irq_cfg, lan9118_state),
127
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118 = {
128
VMSTATE_UINT32(mac_mii_acc, lan9118_state),
129
VMSTATE_UINT32(mac_mii_data, lan9118_state),
130
VMSTATE_UINT32(mac_flow, lan9118_state),
131
- VMSTATE_UINT32(phy_status, lan9118_state),
132
- VMSTATE_UINT32(phy_control, lan9118_state),
133
- VMSTATE_UINT32(phy_advertise, lan9118_state),
134
- VMSTATE_UINT32(phy_int, lan9118_state),
135
- VMSTATE_UINT32(phy_int_mask, lan9118_state),
136
VMSTATE_INT32(eeprom_writable, lan9118_state),
137
VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
138
VMSTATE_INT32(tx_fifo_size, lan9118_state),
139
@@ -XXX,XX +XXX,XX @@ static void lan9118_reload_eeprom(lan9118_state *s)
140
lan9118_mac_changed(s);
141
}
142
143
-static void phy_update_irq(lan9118_state *s)
144
+static void lan9118_update_irq(void *opaque, int n, int level)
145
{
146
- if (s->phy_int & s->phy_int_mask) {
147
+ lan9118_state *s = opaque;
148
+
149
+ if (level) {
150
s->int_sts |= PHY_INT;
151
} else {
152
s->int_sts &= ~PHY_INT;
153
@@ -XXX,XX +XXX,XX @@ static void phy_update_irq(lan9118_state *s)
154
lan9118_update(s);
155
}
156
157
-static void phy_update_link(lan9118_state *s)
158
-{
159
- /* Autonegotiation status mirrors link status. */
160
- if (qemu_get_queue(s->nic)->link_down) {
161
- s->phy_status &= ~0x0024;
162
- s->phy_int |= PHY_INT_DOWN;
163
- } else {
164
- s->phy_status |= 0x0024;
165
- s->phy_int |= PHY_INT_ENERGYON;
166
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
167
- }
168
- phy_update_irq(s);
169
-}
170
-
171
static void lan9118_set_link(NetClientState *nc)
172
{
173
- phy_update_link(qemu_get_nic_opaque(nc));
174
-}
175
-
176
-static void phy_reset(lan9118_state *s)
177
-{
178
- s->phy_status = 0x7809;
179
- s->phy_control = 0x3000;
180
- s->phy_advertise = 0x01e1;
181
- s->phy_int_mask = 0;
182
- s->phy_int = 0;
183
- phy_update_link(s);
184
+ lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii,
185
+ nc->link_down);
186
}
187
188
static void lan9118_reset(DeviceState *d)
189
@@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d)
190
s->read_word_n = 0;
191
s->write_word_n = 0;
192
193
- phy_reset(s);
194
-
195
s->eeprom_writable = 0;
196
lan9118_reload_eeprom(s);
197
}
198
@@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s)
199
uint32_t status;
200
201
/* FIXME: Honor TX disable, and allow queueing of packets. */
202
- if (s->phy_control & 0x4000) {
203
+ if (s->mii.control & 0x4000) {
204
/* This assumes the receive routine doesn't touch the VLANClient. */
205
qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
206
} else {
207
@@ -XXX,XX +XXX,XX @@ static void tx_fifo_push(lan9118_state *s, uint32_t val)
208
}
209
}
210
211
-static uint32_t do_phy_read(lan9118_state *s, int reg)
212
-{
213
- uint32_t val;
214
-
215
- switch (reg) {
216
- case 0: /* Basic Control */
217
- return s->phy_control;
218
- case 1: /* Basic Status */
219
- return s->phy_status;
220
- case 2: /* ID1 */
221
- return 0x0007;
222
- case 3: /* ID2 */
223
- return 0xc0d1;
224
- case 4: /* Auto-neg advertisement */
225
- return s->phy_advertise;
226
- case 5: /* Auto-neg Link Partner Ability */
227
- return 0x0f71;
228
- case 6: /* Auto-neg Expansion */
229
- return 1;
230
- /* TODO 17, 18, 27, 29, 30, 31 */
231
- case 29: /* Interrupt source. */
232
- val = s->phy_int;
233
- s->phy_int = 0;
234
- phy_update_irq(s);
235
- return val;
236
- case 30: /* Interrupt mask */
237
- return s->phy_int_mask;
238
- default:
239
- qemu_log_mask(LOG_GUEST_ERROR,
240
- "do_phy_read: PHY read reg %d\n", reg);
241
- return 0;
242
- }
243
-}
244
-
245
-static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
246
-{
247
- switch (reg) {
248
- case 0: /* Basic Control */
249
- if (val & 0x8000) {
250
- phy_reset(s);
251
- break;
252
- }
253
- s->phy_control = val & 0x7980;
254
- /* Complete autonegotiation immediately. */
255
- if (val & 0x1000) {
256
- s->phy_status |= 0x0020;
257
- }
258
- break;
259
- case 4: /* Auto-neg advertisement */
260
- s->phy_advertise = (val & 0x2d7f) | 0x80;
261
- break;
262
- /* TODO 17, 18, 27, 31 */
263
- case 30: /* Interrupt mask */
264
- s->phy_int_mask = val & 0xff;
265
- phy_update_irq(s);
266
- break;
267
- default:
268
- qemu_log_mask(LOG_GUEST_ERROR,
269
- "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
270
- }
271
-}
272
-
273
static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
274
{
275
switch (reg) {
276
@@ -XXX,XX +XXX,XX @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
277
if (val & 2) {
278
DPRINTF("PHY write %d = 0x%04x\n",
279
(val >> 6) & 0x1f, s->mac_mii_data);
280
- do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
281
+ lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data);
282
} else {
283
- s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
284
+ s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f);
285
DPRINTF("PHY read %d = 0x%04x\n",
286
(val >> 6) & 0x1f, s->mac_mii_data);
287
}
288
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
289
break;
290
case CSR_PMT_CTRL:
291
if (val & 0x400) {
292
- phy_reset(s);
293
+ lan9118_phy_reset(&s->mii);
294
}
295
s->pmt_ctrl &= ~0x34e;
296
s->pmt_ctrl |= (val & 0x34e);
297
@@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp)
298
const MemoryRegionOps *mem_ops =
299
s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops;
300
301
+ qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0);
302
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
303
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
304
+ return;
305
+ }
306
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
307
+
308
memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s,
309
"lan9118-mmio", 0x100);
310
sysbus_init_mmio(sbd, &s->mmio);
311
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
312
new file mode 100644
313
index XXXXXXX..XXXXXXX
314
--- /dev/null
315
+++ b/hw/net/lan9118_phy.c
316
@@ -XXX,XX +XXX,XX @@
317
+/*
318
+ * SMSC LAN9118 PHY emulation
319
+ *
320
+ * Copyright (c) 2009 CodeSourcery, LLC.
321
+ * Written by Paul Brook
322
+ *
323
+ * This code is licensed under the GNU GPL v2
35
+ *
324
+ *
36
+ * Contributions after 2012-01-13 are licensed under the terms of the
325
+ * Contributions after 2012-01-13 are licensed under the terms of the
37
+ * GNU GPL, version 2 or (at your option) any later version.
326
+ * GNU GPL, version 2 or (at your option) any later version.
38
+ */
327
+ */
39
+
328
+
40
+#ifndef HW_MISC_MAX111X_H
329
+#include "qemu/osdep.h"
41
+#define HW_MISC_MAX111X_H
330
+#include "hw/net/lan9118_phy.h"
42
+
331
+#include "hw/irq.h"
43
+#include "hw/ssi/ssi.h"
332
+#include "hw/resettable.h"
44
+
333
+#include "migration/vmstate.h"
45
+/*
334
+#include "qemu/log.h"
46
+ * This is a model of the Maxim MAX1110/1111 ADC chip, which for QEMU
335
+
47
+ * is an SSI slave device. It has either 4 (max1110) or 8 (max1111)
336
+#define PHY_INT_ENERGYON (1 << 7)
48
+ * 8-bit ADC channels.
337
+#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
49
+ *
338
+#define PHY_INT_FAULT (1 << 5)
50
+ * QEMU interface:
339
+#define PHY_INT_DOWN (1 << 4)
51
+ * + GPIO inputs 0..3 (for max1110) or 0..7 (for max1111): set the value
340
+#define PHY_INT_AUTONEG_LP (1 << 3)
52
+ * of each ADC input, as an unsigned 8-bit value
341
+#define PHY_INT_PARFAULT (1 << 2)
53
+ * + GPIO output 0: interrupt line
342
+#define PHY_INT_AUTONEG_PAGE (1 << 1)
54
+ * + Properties "input0" to "input3" (max1110) or "input0" to "input7"
343
+
55
+ * (max1111): initial reset values for ADC inputs.
344
+static void lan9118_phy_update_irq(Lan9118PhyState *s)
56
+ *
345
+{
57
+ * Known bugs:
346
+ qemu_set_irq(s->irq, !!(s->ints & s->int_mask));
58
+ * + the interrupt line is not correctly implemented, and will never
347
+}
59
+ * be lowered once it has been asserted.
348
+
60
+ */
349
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
61
+typedef struct {
350
+{
62
+ SSISlave parent_obj;
351
+ uint16_t val;
63
+
352
+
64
+ qemu_irq interrupt;
353
+ switch (reg) {
65
+ /* Values of inputs at system reset (settable by QOM property) */
354
+ case 0: /* Basic Control */
66
+ uint8_t reset_input[8];
355
+ return s->control;
67
+
356
+ case 1: /* Basic Status */
68
+ uint8_t tb1, rb2, rb3;
357
+ return s->status;
69
+ int cycle;
358
+ case 2: /* ID1 */
70
+
359
+ return 0x0007;
71
+ uint8_t input[8];
360
+ case 3: /* ID2 */
72
+ int inputs, com;
361
+ return 0xc0d1;
73
+} MAX111xState;
362
+ case 4: /* Auto-neg advertisement */
74
+
363
+ return s->advertise;
75
+#define TYPE_MAX_111X "max111x"
364
+ case 5: /* Auto-neg Link Partner Ability */
76
+
365
+ return 0x0f71;
77
+#define MAX_111X(obj) \
366
+ case 6: /* Auto-neg Expansion */
78
+ OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X)
367
+ return 1;
79
+
368
+ /* TODO 17, 18, 27, 29, 30, 31 */
80
+#define TYPE_MAX_1110 "max1110"
369
+ case 29: /* Interrupt source. */
81
+#define TYPE_MAX_1111 "max1111"
370
+ val = s->ints;
82
+
371
+ s->ints = 0;
83
+#endif
372
+ lan9118_phy_update_irq(s);
84
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
373
+ return val;
374
+ case 30: /* Interrupt mask */
375
+ return s->int_mask;
376
+ default:
377
+ qemu_log_mask(LOG_GUEST_ERROR,
378
+ "lan9118_phy_read: PHY read reg %d\n", reg);
379
+ return 0;
380
+ }
381
+}
382
+
383
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
384
+{
385
+ switch (reg) {
386
+ case 0: /* Basic Control */
387
+ if (val & 0x8000) {
388
+ lan9118_phy_reset(s);
389
+ break;
390
+ }
391
+ s->control = val & 0x7980;
392
+ /* Complete autonegotiation immediately. */
393
+ if (val & 0x1000) {
394
+ s->status |= 0x0020;
395
+ }
396
+ break;
397
+ case 4: /* Auto-neg advertisement */
398
+ s->advertise = (val & 0x2d7f) | 0x80;
399
+ break;
400
+ /* TODO 17, 18, 27, 31 */
401
+ case 30: /* Interrupt mask */
402
+ s->int_mask = val & 0xff;
403
+ lan9118_phy_update_irq(s);
404
+ break;
405
+ default:
406
+ qemu_log_mask(LOG_GUEST_ERROR,
407
+ "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
408
+ }
409
+}
410
+
411
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
412
+{
413
+ s->link_down = link_down;
414
+
415
+ /* Autonegotiation status mirrors link status. */
416
+ if (link_down) {
417
+ s->status &= ~0x0024;
418
+ s->ints |= PHY_INT_DOWN;
419
+ } else {
420
+ s->status |= 0x0024;
421
+ s->ints |= PHY_INT_ENERGYON;
422
+ s->ints |= PHY_INT_AUTONEG_COMPLETE;
423
+ }
424
+ lan9118_phy_update_irq(s);
425
+}
426
+
427
+void lan9118_phy_reset(Lan9118PhyState *s)
428
+{
429
+ s->control = 0x3000;
430
+ s->status = 0x7809;
431
+ s->advertise = 0x01e1;
432
+ s->int_mask = 0;
433
+ s->ints = 0;
434
+ lan9118_phy_update_link(s, s->link_down);
435
+}
436
+
437
+static void lan9118_phy_reset_hold(Object *obj, ResetType type)
438
+{
439
+ Lan9118PhyState *s = LAN9118_PHY(obj);
440
+
441
+ lan9118_phy_reset(s);
442
+}
443
+
444
+static void lan9118_phy_init(Object *obj)
445
+{
446
+ Lan9118PhyState *s = LAN9118_PHY(obj);
447
+
448
+ qdev_init_gpio_out(DEVICE(s), &s->irq, 1);
449
+}
450
+
451
+static const VMStateDescription vmstate_lan9118_phy = {
452
+ .name = "lan9118-phy",
453
+ .version_id = 1,
454
+ .minimum_version_id = 1,
455
+ .fields = (const VMStateField[]) {
456
+ VMSTATE_UINT16(control, Lan9118PhyState),
457
+ VMSTATE_UINT16(status, Lan9118PhyState),
458
+ VMSTATE_UINT16(advertise, Lan9118PhyState),
459
+ VMSTATE_UINT16(ints, Lan9118PhyState),
460
+ VMSTATE_UINT16(int_mask, Lan9118PhyState),
461
+ VMSTATE_BOOL(link_down, Lan9118PhyState),
462
+ VMSTATE_END_OF_LIST()
463
+ }
464
+};
465
+
466
+static void lan9118_phy_class_init(ObjectClass *klass, void *data)
467
+{
468
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
469
+ DeviceClass *dc = DEVICE_CLASS(klass);
470
+
471
+ rc->phases.hold = lan9118_phy_reset_hold;
472
+ dc->vmsd = &vmstate_lan9118_phy;
473
+}
474
+
475
+static const TypeInfo types[] = {
476
+ {
477
+ .name = TYPE_LAN9118_PHY,
478
+ .parent = TYPE_SYS_BUS_DEVICE,
479
+ .instance_size = sizeof(Lan9118PhyState),
480
+ .instance_init = lan9118_phy_init,
481
+ .class_init = lan9118_phy_class_init,
482
+ }
483
+};
484
+
485
+DEFINE_TYPES(types)
486
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
85
index XXXXXXX..XXXXXXX 100644
487
index XXXXXXX..XXXXXXX 100644
86
--- a/hw/arm/spitz.c
488
--- a/hw/net/Kconfig
87
+++ b/hw/arm/spitz.c
489
+++ b/hw/net/Kconfig
88
@@ -XXX,XX +XXX,XX @@
490
@@ -XXX,XX +XXX,XX @@ config VMXNET3_PCI
89
#include "audio/audio.h"
491
config SMC91C111
90
#include "hw/boards.h"
492
bool
91
#include "hw/sysbus.h"
493
92
+#include "hw/misc/max111x.h"
494
+config LAN9118_PHY
93
#include "migration/vmstate.h"
495
+ bool
94
#include "exec/address-spaces.h"
496
+
95
#include "cpu.h"
497
config LAN9118
96
@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
498
bool
97
qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
499
+ select LAN9118_PHY
98
500
select PTIMER
99
bus = qdev_get_child_bus(sms->mux, "ssi2");
501
100
- sms->max1111 = qdev_new("max1111");
502
config NE2000_ISA
101
+ sms->max1111 = qdev_new(TYPE_MAX_1111);
503
diff --git a/hw/net/meson.build b/hw/net/meson.build
102
max1111 = sms->max1111;
103
qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
104
SPITZ_BATTERY_VOLT);
105
diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
106
index XXXXXXX..XXXXXXX 100644
504
index XXXXXXX..XXXXXXX 100644
107
--- a/hw/misc/max111x.c
505
--- a/hw/net/meson.build
108
+++ b/hw/misc/max111x.c
506
+++ b/hw/net/meson.build
109
@@ -XXX,XX +XXX,XX @@
507
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c'))
110
*/
508
111
509
system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c'))
112
#include "qemu/osdep.h"
510
system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c'))
113
+#include "hw/misc/max111x.h"
511
+system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c'))
114
#include "hw/irq.h"
512
system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c'))
115
-#include "hw/ssi/ssi.h"
513
system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c'))
116
#include "migration/vmstate.h"
514
system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c'))
117
#include "qemu/module.h"
118
#include "hw/qdev-properties.h"
119
120
-typedef struct {
121
- SSISlave parent_obj;
122
-
123
- qemu_irq interrupt;
124
- /* Values of inputs at system reset (settable by QOM property) */
125
- uint8_t reset_input[8];
126
-
127
- uint8_t tb1, rb2, rb3;
128
- int cycle;
129
-
130
- uint8_t input[8];
131
- int inputs, com;
132
-} MAX111xState;
133
-
134
-#define TYPE_MAX_111X "max111x"
135
-
136
-#define MAX_111X(obj) \
137
- OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X)
138
-
139
-#define TYPE_MAX_1110 "max1110"
140
-#define TYPE_MAX_1111 "max1111"
141
-
142
/* Control-byte bitfields */
143
#define CB_PD0        (1 << 0)
144
#define CB_PD1        (1 << 1)
145
diff --git a/MAINTAINERS b/MAINTAINERS
146
index XXXXXXX..XXXXXXX 100644
147
--- a/MAINTAINERS
148
+++ b/MAINTAINERS
149
@@ -XXX,XX +XXX,XX @@ F: hw/gpio/max7310.c
150
F: hw/gpio/zaurus.c
151
F: hw/misc/mst_fpga.c
152
F: hw/misc/max111x.c
153
+F: include/hw/misc/max111x.h
154
F: include/hw/arm/pxa.h
155
F: include/hw/arm/sharpsl.h
156
F: include/hw/display/tc6393xb.h
157
--
515
--
158
2.20.1
516
2.34.1
159
160
diff view generated by jsdifflib
[PULL 01/34] Add a phy-num property to the i.MX FEC emulator
[PULL 02/72] hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
We need a solution to use an Ethernet PHY that is not the first device
3
imx_fec models the same PHY as lan9118_phy. The code is almost the same with
4
on the MDIO bus (device 0 on MDIO bus).
4
imx_fec having more logging and tracing. Merge these improvements into
5
lan9118_phy and reuse in imx_fec to fix the code duplication.
5
6
6
As an example with the i.MX6UL the NXP SOC has 2 Ethernet devices but
7
Some migration state how resides in the new device model which breaks migration
7
only one MDIO bus on which the 2 related PHY are connected but at unique
8
compatibility for the following machines:
8
addresses.
9
* imx25-pdk
10
* sabrelite
11
* mcimx7d-sabre
12
* mcimx6ul-evk
9
13
10
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
14
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
11
Message-id: a1a5c0e139d1c763194b8020573dcb6025daeefa.1593296112.git.jcd@tribudubois.net
15
Tested-by: Guenter Roeck <linux@roeck-us.net>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 20241102125724.532843-3-shentey@gmail.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
19
---
15
include/hw/net/imx_fec.h | 1 +
20
include/hw/net/imx_fec.h | 9 ++-
16
hw/net/imx_fec.c | 24 +++++++++++++++++-------
21
hw/net/imx_fec.c | 146 ++++-----------------------------------
17
hw/net/trace-events | 4 ++--
22
hw/net/lan9118_phy.c | 82 ++++++++++++++++------
18
3 files changed, 20 insertions(+), 9 deletions(-)
23
hw/net/Kconfig | 1 +
24
hw/net/trace-events | 10 +--
25
5 files changed, 85 insertions(+), 163 deletions(-)
19
26
20
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
27
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
21
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/net/imx_fec.h
29
--- a/include/hw/net/imx_fec.h
23
+++ b/include/hw/net/imx_fec.h
30
+++ b/include/hw/net/imx_fec.h
24
@@ -XXX,XX +XXX,XX @@ typedef struct IMXFECState {
31
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC)
25
uint32_t phy_advertise;
32
#define TYPE_IMX_ENET "imx.enet"
26
uint32_t phy_int;
33
27
uint32_t phy_int_mask;
34
#include "hw/sysbus.h"
28
+ uint32_t phy_num;
35
+#include "hw/net/lan9118_phy.h"
29
36
+#include "hw/irq.h"
30
bool is_fec;
37
#include "net/net.h"
31
38
39
#define ENET_EIR 1
40
@@ -XXX,XX +XXX,XX @@ struct IMXFECState {
41
uint32_t tx_descriptor[ENET_TX_RING_NUM];
42
uint32_t tx_ring_num;
43
44
- uint32_t phy_status;
45
- uint32_t phy_control;
46
- uint32_t phy_advertise;
47
- uint32_t phy_int;
48
- uint32_t phy_int_mask;
49
+ Lan9118PhyState mii;
50
+ IRQState mii_irq;
51
uint32_t phy_num;
52
bool phy_connected;
53
struct IMXFECState *phy_consumer;
32
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
54
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
33
index XXXXXXX..XXXXXXX 100644
55
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/net/imx_fec.c
56
--- a/hw/net/imx_fec.c
35
+++ b/hw/net/imx_fec.c
57
+++ b/hw/net/imx_fec.c
36
@@ -XXX,XX +XXX,XX @@ static void imx_phy_reset(IMXFECState *s)
58
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth_txdescs = {
59
60
static const VMStateDescription vmstate_imx_eth = {
61
.name = TYPE_IMX_FEC,
62
- .version_id = 2,
63
- .minimum_version_id = 2,
64
+ .version_id = 3,
65
+ .minimum_version_id = 3,
66
.fields = (const VMStateField[]) {
67
VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX),
68
VMSTATE_UINT32(rx_descriptor, IMXFECState),
69
VMSTATE_UINT32(tx_descriptor[0], IMXFECState),
70
- VMSTATE_UINT32(phy_status, IMXFECState),
71
- VMSTATE_UINT32(phy_control, IMXFECState),
72
- VMSTATE_UINT32(phy_advertise, IMXFECState),
73
- VMSTATE_UINT32(phy_int, IMXFECState),
74
- VMSTATE_UINT32(phy_int_mask, IMXFECState),
75
VMSTATE_END_OF_LIST()
76
},
77
.subsections = (const VMStateDescription * const []) {
78
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth = {
79
},
80
};
81
82
-#define PHY_INT_ENERGYON (1 << 7)
83
-#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
84
-#define PHY_INT_FAULT (1 << 5)
85
-#define PHY_INT_DOWN (1 << 4)
86
-#define PHY_INT_AUTONEG_LP (1 << 3)
87
-#define PHY_INT_PARFAULT (1 << 2)
88
-#define PHY_INT_AUTONEG_PAGE (1 << 1)
89
-
90
static void imx_eth_update(IMXFECState *s);
91
92
/*
93
@@ -XXX,XX +XXX,XX @@ static void imx_eth_update(IMXFECState *s);
94
* For now we don't handle any GPIO/interrupt line, so the OS will
95
* have to poll for the PHY status.
96
*/
97
-static void imx_phy_update_irq(IMXFECState *s)
98
+static void imx_phy_update_irq(void *opaque, int n, int level)
99
{
100
- imx_eth_update(s);
101
-}
102
-
103
-static void imx_phy_update_link(IMXFECState *s)
104
-{
105
- /* Autonegotiation status mirrors link status. */
106
- if (qemu_get_queue(s->nic)->link_down) {
107
- trace_imx_phy_update_link("down");
108
- s->phy_status &= ~0x0024;
109
- s->phy_int |= PHY_INT_DOWN;
110
- } else {
111
- trace_imx_phy_update_link("up");
112
- s->phy_status |= 0x0024;
113
- s->phy_int |= PHY_INT_ENERGYON;
114
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
115
- }
116
- imx_phy_update_irq(s);
117
+ imx_eth_update(opaque);
118
}
119
120
static void imx_eth_set_link(NetClientState *nc)
121
{
122
- imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc)));
123
-}
124
-
125
-static void imx_phy_reset(IMXFECState *s)
126
-{
127
- trace_imx_phy_reset();
128
-
129
- s->phy_status = 0x7809;
130
- s->phy_control = 0x3000;
131
- s->phy_advertise = 0x01e1;
132
- s->phy_int_mask = 0;
133
- s->phy_int = 0;
134
- imx_phy_update_link(s);
135
+ lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii,
136
+ nc->link_down);
137
}
138
37
static uint32_t imx_phy_read(IMXFECState *s, int reg)
139
static uint32_t imx_phy_read(IMXFECState *s, int reg)
38
{
140
{
39
uint32_t val;
141
- uint32_t val;
40
+ uint32_t phy = reg / 32;
142
uint32_t phy = reg / 32;
41
143
42
- if (reg > 31) {
144
if (!s->phy_connected) {
43
- /* we only advertise one phy */
145
@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
44
+ if (phy != s->phy_num) {
146
45
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
147
reg %= 32;
46
+ TYPE_IMX_FEC, __func__, phy);
148
47
return 0;
149
- switch (reg) {
150
- case 0: /* Basic Control */
151
- val = s->phy_control;
152
- break;
153
- case 1: /* Basic Status */
154
- val = s->phy_status;
155
- break;
156
- case 2: /* ID1 */
157
- val = 0x0007;
158
- break;
159
- case 3: /* ID2 */
160
- val = 0xc0d1;
161
- break;
162
- case 4: /* Auto-neg advertisement */
163
- val = s->phy_advertise;
164
- break;
165
- case 5: /* Auto-neg Link Partner Ability */
166
- val = 0x0f71;
167
- break;
168
- case 6: /* Auto-neg Expansion */
169
- val = 1;
170
- break;
171
- case 29: /* Interrupt source. */
172
- val = s->phy_int;
173
- s->phy_int = 0;
174
- imx_phy_update_irq(s);
175
- break;
176
- case 30: /* Interrupt mask */
177
- val = s->phy_int_mask;
178
- break;
179
- case 17:
180
- case 18:
181
- case 27:
182
- case 31:
183
- qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n",
184
- TYPE_IMX_FEC, __func__, reg);
185
- val = 0;
186
- break;
187
- default:
188
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
189
- TYPE_IMX_FEC, __func__, reg);
190
- val = 0;
191
- break;
192
- }
193
-
194
- trace_imx_phy_read(val, phy, reg);
195
-
196
- return val;
197
+ return lan9118_phy_read(&s->mii, reg);
198
}
199
200
static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
201
@@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
202
203
reg %= 32;
204
205
- trace_imx_phy_write(val, phy, reg);
206
-
207
- switch (reg) {
208
- case 0: /* Basic Control */
209
- if (val & 0x8000) {
210
- imx_phy_reset(s);
211
- } else {
212
- s->phy_control = val & 0x7980;
213
- /* Complete autonegotiation immediately. */
214
- if (val & 0x1000) {
215
- s->phy_status |= 0x0020;
216
- }
217
- }
218
- break;
219
- case 4: /* Auto-neg advertisement */
220
- s->phy_advertise = (val & 0x2d7f) | 0x80;
221
- break;
222
- case 30: /* Interrupt mask */
223
- s->phy_int_mask = val & 0xff;
224
- imx_phy_update_irq(s);
225
- break;
226
- case 17:
227
- case 18:
228
- case 27:
229
- case 31:
230
- qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n",
231
- TYPE_IMX_FEC, __func__, reg);
232
- break;
233
- default:
234
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
235
- TYPE_IMX_FEC, __func__, reg);
236
- break;
237
- }
238
+ lan9118_phy_write(&s->mii, reg, val);
239
}
240
241
static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr)
242
@@ -XXX,XX +XXX,XX @@ static void imx_eth_reset(DeviceState *d)
243
244
s->rx_descriptor = 0;
245
memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor));
246
-
247
- /* We also reset the PHY */
248
- imx_phy_reset(s);
249
}
250
251
static uint32_t imx_default_read(IMXFECState *s, uint32_t index)
252
@@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
253
sysbus_init_irq(sbd, &s->irq[0]);
254
sysbus_init_irq(sbd, &s->irq[1]);
255
256
+ qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0);
257
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
258
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
259
+ return;
260
+ }
261
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
262
+
263
qemu_macaddr_default_if_unset(&s->conf.macaddr);
264
265
s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf,
266
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
267
index XXXXXXX..XXXXXXX 100644
268
--- a/hw/net/lan9118_phy.c
269
+++ b/hw/net/lan9118_phy.c
270
@@ -XXX,XX +XXX,XX @@
271
* Copyright (c) 2009 CodeSourcery, LLC.
272
* Written by Paul Brook
273
*
274
+ * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
275
+ *
276
* This code is licensed under the GNU GPL v2
277
*
278
* Contributions after 2012-01-13 are licensed under the terms of the
279
@@ -XXX,XX +XXX,XX @@
280
#include "hw/resettable.h"
281
#include "migration/vmstate.h"
282
#include "qemu/log.h"
283
+#include "trace.h"
284
285
#define PHY_INT_ENERGYON (1 << 7)
286
#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
287
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
288
289
switch (reg) {
290
case 0: /* Basic Control */
291
- return s->control;
292
+ val = s->control;
293
+ break;
294
case 1: /* Basic Status */
295
- return s->status;
296
+ val = s->status;
297
+ break;
298
case 2: /* ID1 */
299
- return 0x0007;
300
+ val = 0x0007;
301
+ break;
302
case 3: /* ID2 */
303
- return 0xc0d1;
304
+ val = 0xc0d1;
305
+ break;
306
case 4: /* Auto-neg advertisement */
307
- return s->advertise;
308
+ val = s->advertise;
309
+ break;
310
case 5: /* Auto-neg Link Partner Ability */
311
- return 0x0f71;
312
+ val = 0x0f71;
313
+ break;
314
case 6: /* Auto-neg Expansion */
315
- return 1;
316
- /* TODO 17, 18, 27, 29, 30, 31 */
317
+ val = 1;
318
+ break;
319
case 29: /* Interrupt source. */
320
val = s->ints;
321
s->ints = 0;
322
lan9118_phy_update_irq(s);
323
- return val;
324
+ break;
325
case 30: /* Interrupt mask */
326
- return s->int_mask;
327
+ val = s->int_mask;
328
+ break;
329
+ case 17:
330
+ case 18:
331
+ case 27:
332
+ case 31:
333
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
334
+ __func__, reg);
335
+ val = 0;
336
+ break;
337
default:
338
- qemu_log_mask(LOG_GUEST_ERROR,
339
- "lan9118_phy_read: PHY read reg %d\n", reg);
340
- return 0;
341
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
342
+ __func__, reg);
343
+ val = 0;
344
+ break;
48
}
345
}
49
346
+
50
+ reg %= 32;
347
+ trace_lan9118_phy_read(val, reg);
348
+
349
+ return val;
350
}
351
352
void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
353
{
354
+ trace_lan9118_phy_write(val, reg);
51
+
355
+
52
switch (reg) {
356
switch (reg) {
53
case 0: /* Basic Control */
357
case 0: /* Basic Control */
54
val = s->phy_control;
358
if (val & 0x8000) {
55
@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
359
lan9118_phy_reset(s);
360
- break;
361
- }
362
- s->control = val & 0x7980;
363
- /* Complete autonegotiation immediately. */
364
- if (val & 0x1000) {
365
- s->status |= 0x0020;
366
+ } else {
367
+ s->control = val & 0x7980;
368
+ /* Complete autonegotiation immediately. */
369
+ if (val & 0x1000) {
370
+ s->status |= 0x0020;
371
+ }
372
}
56
break;
373
break;
374
case 4: /* Auto-neg advertisement */
375
s->advertise = (val & 0x2d7f) | 0x80;
376
break;
377
- /* TODO 17, 18, 27, 31 */
378
case 30: /* Interrupt mask */
379
s->int_mask = val & 0xff;
380
lan9118_phy_update_irq(s);
381
break;
382
+ case 17:
383
+ case 18:
384
+ case 27:
385
+ case 31:
386
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
387
+ __func__, reg);
388
+ break;
389
default:
390
- qemu_log_mask(LOG_GUEST_ERROR,
391
- "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
392
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
393
+ __func__, reg);
394
+ break;
57
}
395
}
58
396
}
59
- trace_imx_phy_read(val, reg);
397
60
+ trace_imx_phy_read(val, phy, reg);
398
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
61
399
62
return val;
400
/* Autonegotiation status mirrors link status. */
63
}
401
if (link_down) {
64
402
+ trace_lan9118_phy_update_link("down");
65
static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
403
s->status &= ~0x0024;
404
s->ints |= PHY_INT_DOWN;
405
} else {
406
+ trace_lan9118_phy_update_link("up");
407
s->status |= 0x0024;
408
s->ints |= PHY_INT_ENERGYON;
409
s->ints |= PHY_INT_AUTONEG_COMPLETE;
410
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
411
412
void lan9118_phy_reset(Lan9118PhyState *s)
66
{
413
{
67
- trace_imx_phy_write(val, reg);
414
+ trace_lan9118_phy_reset();
68
+ uint32_t phy = reg / 32;
415
+
69
416
s->control = 0x3000;
70
- if (reg > 31) {
417
s->status = 0x7809;
71
- /* we only advertise one phy */
418
s->advertise = 0x01e1;
72
+ if (phy != s->phy_num) {
419
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118_phy = {
73
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
420
.version_id = 1,
74
+ TYPE_IMX_FEC, __func__, phy);
421
.minimum_version_id = 1,
75
return;
422
.fields = (const VMStateField[]) {
76
}
423
- VMSTATE_UINT16(control, Lan9118PhyState),
77
424
VMSTATE_UINT16(status, Lan9118PhyState),
78
+ reg %= 32;
425
+ VMSTATE_UINT16(control, Lan9118PhyState),
79
+
426
VMSTATE_UINT16(advertise, Lan9118PhyState),
80
+ trace_imx_phy_write(val, phy, reg);
427
VMSTATE_UINT16(ints, Lan9118PhyState),
81
+
428
VMSTATE_UINT16(int_mask, Lan9118PhyState),
82
switch (reg) {
429
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
83
case 0: /* Basic Control */
430
index XXXXXXX..XXXXXXX 100644
84
if (val & 0x8000) {
431
--- a/hw/net/Kconfig
85
@@ -XXX,XX +XXX,XX @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
432
+++ b/hw/net/Kconfig
86
extract32(value,
433
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_SUN8I_EMAC
87
18, 10)));
434
88
} else {
435
config IMX_FEC
89
- /* This a write operation */
436
bool
90
+ /* This is a write operation */
437
+ select LAN9118_PHY
91
imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16));
438
92
}
439
config CADENCE
93
/* raise the interrupt as the PHY operation is done */
440
bool
94
@@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
95
static Property imx_eth_properties[] = {
96
DEFINE_NIC_PROPERTIES(IMXFECState, conf),
97
DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1),
98
+ DEFINE_PROP_UINT32("phy-num", IMXFECState, phy_num, 0),
99
DEFINE_PROP_END_OF_LIST(),
100
};
101
102
diff --git a/hw/net/trace-events b/hw/net/trace-events
441
diff --git a/hw/net/trace-events b/hw/net/trace-events
103
index XXXXXXX..XXXXXXX 100644
442
index XXXXXXX..XXXXXXX 100644
104
--- a/hw/net/trace-events
443
--- a/hw/net/trace-events
105
+++ b/hw/net/trace-events
444
+++ b/hw/net/trace-events
445
@@ -XXX,XX +XXX,XX @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
446
allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
447
allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
448
449
+# lan9118_phy.c
450
+lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16
451
+lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16
452
+lan9118_phy_update_link(const char *s) "%s"
453
+lan9118_phy_reset(void) ""
454
+
455
# lance.c
456
lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x"
457
lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x"
106
@@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
458
@@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
107
i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
459
i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
108
460
109
# imx_fec.c
461
# imx_fec.c
110
-imx_phy_read(uint32_t val, int reg) "0x%04"PRIx32" <= reg[%d]"
462
-imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
111
-imx_phy_write(uint32_t val, int reg) "0x%04"PRIx32" => reg[%d]"
463
imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)"
112
+imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
464
-imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
113
+imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
465
imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)"
114
imx_phy_update_link(const char *s) "%s"
466
-imx_phy_update_link(const char *s) "%s"
115
imx_phy_reset(void) ""
467
-imx_phy_reset(void) ""
116
imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
468
imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
469
imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x"
470
imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit"
117
--
471
--
118
2.20.1
472
2.34.1
119
120
diff view generated by jsdifflib
New patch
[PULL 03/72] hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
1
From: Bernhard Beschow <shentey@gmail.com>
1
2
3
Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and
4
fixes the MSB of selector field to be zero, as specified in the datasheet.
5
6
Fixes: 2a424990170b "LAN9118 emulation"
7
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
8
Tested-by: Guenter Roeck <linux@roeck-us.net>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20241102125724.532843-4-shentey@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/net/lan9118_phy.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/net/lan9118_phy.c
19
+++ b/hw/net/lan9118_phy.c
20
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
21
val = s->advertise;
22
break;
23
case 5: /* Auto-neg Link Partner Ability */
24
- val = 0x0f71;
25
+ val = 0x0fe1;
26
break;
27
case 6: /* Auto-neg Expansion */
28
val = 1;
29
--
30
2.34.1
diff view generated by jsdifflib
[PULL 14/34] tests/acpi: virt: update golden masters for DSDT
[PULL 04/72] hw/net/lan9118_phy: Reuse MII constants
1
From: Andrew Jones <drjones@redhat.com>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Differences between disassembled ASL files for DSDT:
3
Prefer named constants over magic values for better readability.
4
4
5
@@ -XXX,XX +XXX,XX @@
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
*
6
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
7
* Disassembling to symbolic ASL+ operators
7
Tested-by: Guenter Roeck <linux@roeck-us.net>
8
*
8
Message-id: 20241102125724.532843-5-shentey@gmail.com
9
- * Disassembly of a, Mon Jun 29 09:50:01 2020
10
+ * Disassembly of b, Mon Jun 29 09:50:03 2020
11
*
12
* Original Table Header:
13
* Signature "DSDT"
14
- * Length 0x000014BB (5307)
15
+ * Length 0x00001455 (5205)
16
* Revision 0x02
17
- * Checksum 0xD1
18
+ * Checksum 0xE1
19
* OEM ID "BOCHS "
20
* OEM Table ID "BXPCDSDT"
21
* OEM Revision 0x00000001 (1)
22
@@ -XXX,XX +XXX,XX @@
23
})
24
}
25
26
- Device (FLS0)
27
- {
28
- Name (_HID, "LNRO0015") // _HID: Hardware ID
29
- Name (_UID, Zero) // _UID: Unique ID
30
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
31
- {
32
- Memory32Fixed (ReadWrite,
33
- 0x00000000, // Address Base
34
- 0x04000000, // Address Length
35
- )
36
- })
37
- }
38
-
39
- Device (FLS1)
40
- {
41
- Name (_HID, "LNRO0015") // _HID: Hardware ID
42
- Name (_UID, One) // _UID: Unique ID
43
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
44
- {
45
- Memory32Fixed (ReadWrite,
46
- 0x04000000, // Address Base
47
- 0x04000000, // Address Length
48
- )
49
- })
50
- }
51
-
52
Device (FWCF)
53
{
54
Name (_HID, "QEMU0002") // _HID: Hardware ID
55
56
The other two binaries have the same changes (the removal of the
57
flash devices).
58
59
Signed-off-by: Andrew Jones <drjones@redhat.com>
60
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
61
Reviewed-by: Eric Auger <eric.auger@redhat.com>
62
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
63
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
64
Message-id: 20200629140938.17566-5-drjones@redhat.com
65
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
66
---
10
---
67
tests/qtest/bios-tables-test-allowed-diff.h | 3 ---
11
include/hw/net/mii.h | 6 +++++
68
tests/data/acpi/virt/DSDT | Bin 5307 -> 5205 bytes
12
hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++----------------
69
tests/data/acpi/virt/DSDT.memhp | Bin 6668 -> 6566 bytes
13
2 files changed, 46 insertions(+), 23 deletions(-)
70
tests/data/acpi/virt/DSDT.numamem | Bin 5307 -> 5205 bytes
71
4 files changed, 3 deletions(-)
72
14
73
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
15
diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h
74
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
75
--- a/tests/qtest/bios-tables-test-allowed-diff.h
17
--- a/include/hw/net/mii.h
76
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
18
+++ b/include/hw/net/mii.h
77
@@ -1,4 +1 @@
19
@@ -XXX,XX +XXX,XX @@
78
/* List of comma-separated changed AML files to ignore */
20
#define MII_BMSR_JABBER (1 << 1) /* Jabber detected */
79
-"tests/data/acpi/virt/DSDT",
21
#define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */
80
-"tests/data/acpi/virt/DSDT.memhp",
22
81
-"tests/data/acpi/virt/DSDT.numamem",
23
+#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */
82
diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/DSDT
24
#define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */
25
#define MII_ANAR_PAUSE (1 << 10) /* Try for pause */
26
#define MII_ANAR_TXFD (1 << 8)
27
@@ -XXX,XX +XXX,XX @@
28
#define MII_ANAR_10FD (1 << 6)
29
#define MII_ANAR_10 (1 << 5)
30
#define MII_ANAR_CSMACD (1 << 0)
31
+#define MII_ANAR_SELECT (0x001f) /* Selector bits */
32
33
#define MII_ANLPAR_ACK (1 << 14)
34
#define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */
35
@@ -XXX,XX +XXX,XX @@
36
#define RTL8201CP_PHYID1 0x0000
37
#define RTL8201CP_PHYID2 0x8201
38
39
+/* SMSC LAN9118 */
40
+#define SMSCLAN9118_PHYID1 0x0007
41
+#define SMSCLAN9118_PHYID2 0xc0d1
42
+
43
/* RealTek 8211E */
44
#define RTL8211E_PHYID1 0x001c
45
#define RTL8211E_PHYID2 0xc915
46
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
83
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
84
GIT binary patch
48
--- a/hw/net/lan9118_phy.c
85
delta 28
49
+++ b/hw/net/lan9118_phy.c
86
kcmdn3c~yhUCD<h-RD^+n>ET2!X{H9}iRuX(-<}f&0DgxFc>n+a
50
@@ -XXX,XX +XXX,XX @@
87
51
88
delta 156
52
#include "qemu/osdep.h"
89
zcmcbrv0IbNCD<iow+I6R)5VEg(oAih6V(&y4c&Z#4LIUGJY9Hw{DS-q3=B;fIO0P+
53
#include "hw/net/lan9118_phy.h"
90
zU4W!>P_UpN7hfAE10w?juv9WcH-WSmV$;Hiu7w4t3#`S$E!^1+q9xGPH`KtuzzAr5
54
+#include "hw/net/mii.h"
91
LaERl^1zUvy_;n(J
55
#include "hw/irq.h"
92
56
#include "hw/resettable.h"
93
diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.memhp
57
#include "migration/vmstate.h"
94
index XXXXXXX..XXXXXXX 100644
58
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
95
GIT binary patch
59
uint16_t val;
96
delta 28
60
97
kcmeA%S!T@T66_MPOp<|tiD@F2G*jb@iRuX(-^xn@0CHUjRR910
61
switch (reg) {
98
62
- case 0: /* Basic Control */
99
delta 156
63
+ case MII_BMCR:
100
zcmZ2x++)J!66_MfBgMeL^l>7WG*kP$iRuaUhHgH=1|0Doo-VvTenI{Q28N~#9Py!^
64
val = s->control;
101
zE<n;bC|FRCi?5B7fsp|MSSlH!n?PC&v1wsM*TMqS1=eEW7Vhi@(GuwD8){%+U<5Qj
65
break;
102
LIK*+|0yaqism~!^
66
- case 1: /* Basic Status */
103
67
+ case MII_BMSR:
104
diff --git a/tests/data/acpi/virt/DSDT.numamem b/tests/data/acpi/virt/DSDT.numamem
68
val = s->status;
105
index XXXXXXX..XXXXXXX 100644
69
break;
106
GIT binary patch
70
- case 2: /* ID1 */
107
delta 28
71
- val = 0x0007;
108
kcmdn3c~yhUCD<h-RD^+n>ET2!X{H9}iRuX(-<}f&0DgxFc>n+a
72
+ case MII_PHYID1:
109
73
+ val = SMSCLAN9118_PHYID1;
110
delta 156
74
break;
111
zcmcbrv0IbNCD<iow+I6R)5VEg(oAih6V(&y4c&Z#4LIUGJY9Hw{DS-q3=B;fIO0P+
75
- case 3: /* ID2 */
112
zU4W!>P_UpN7hfAE10w?juv9WcH-WSmV$;Hiu7w4t3#`S$E!^1+q9xGPH`KtuzzAr5
76
- val = 0xc0d1;
113
LaERl^1zUvy_;n(J
77
+ case MII_PHYID2:
114
78
+ val = SMSCLAN9118_PHYID2;
79
break;
80
- case 4: /* Auto-neg advertisement */
81
+ case MII_ANAR:
82
val = s->advertise;
83
break;
84
- case 5: /* Auto-neg Link Partner Ability */
85
- val = 0x0fe1;
86
+ case MII_ANLPAR:
87
+ val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 |
88
+ MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD |
89
+ MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
90
break;
91
- case 6: /* Auto-neg Expansion */
92
- val = 1;
93
+ case MII_ANER:
94
+ val = MII_ANER_NWAY;
95
break;
96
case 29: /* Interrupt source. */
97
val = s->ints;
98
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
99
trace_lan9118_phy_write(val, reg);
100
101
switch (reg) {
102
- case 0: /* Basic Control */
103
- if (val & 0x8000) {
104
+ case MII_BMCR:
105
+ if (val & MII_BMCR_RESET) {
106
lan9118_phy_reset(s);
107
} else {
108
- s->control = val & 0x7980;
109
+ s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 |
110
+ MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD |
111
+ MII_BMCR_CTST);
112
/* Complete autonegotiation immediately. */
113
- if (val & 0x1000) {
114
- s->status |= 0x0020;
115
+ if (val & MII_BMCR_AUTOEN) {
116
+ s->status |= MII_BMSR_AN_COMP;
117
}
118
}
119
break;
120
- case 4: /* Auto-neg advertisement */
121
- s->advertise = (val & 0x2d7f) | 0x80;
122
+ case MII_ANAR:
123
+ s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
124
+ MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
125
+ MII_ANAR_SELECT))
126
+ | MII_ANAR_TX;
127
break;
128
case 30: /* Interrupt mask */
129
s->int_mask = val & 0xff;
130
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
131
/* Autonegotiation status mirrors link status. */
132
if (link_down) {
133
trace_lan9118_phy_update_link("down");
134
- s->status &= ~0x0024;
135
+ s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST);
136
s->ints |= PHY_INT_DOWN;
137
} else {
138
trace_lan9118_phy_update_link("up");
139
- s->status |= 0x0024;
140
+ s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST;
141
s->ints |= PHY_INT_ENERGYON;
142
s->ints |= PHY_INT_AUTONEG_COMPLETE;
143
}
144
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_reset(Lan9118PhyState *s)
145
{
146
trace_lan9118_phy_reset();
147
148
- s->control = 0x3000;
149
- s->status = 0x7809;
150
- s->advertise = 0x01e1;
151
+ s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100;
152
+ s->status = MII_BMSR_100TX_FD
153
+ | MII_BMSR_100TX_HD
154
+ | MII_BMSR_10T_FD
155
+ | MII_BMSR_10T_HD
156
+ | MII_BMSR_AUTONEG
157
+ | MII_BMSR_EXTCAP;
158
+ s->advertise = MII_ANAR_TXFD
159
+ | MII_ANAR_TX
160
+ | MII_ANAR_10FD
161
+ | MII_ANAR_10
162
+ | MII_ANAR_CSMACD;
163
s->int_mask = 0;
164
s->ints = 0;
165
lan9118_phy_update_link(s, s->link_down);
115
--
166
--
116
2.20.1
167
2.34.1
117
118
diff view generated by jsdifflib
[PULL 12/34] tests/acpi: virt: allow DSDT acpi table changes
[PULL 05/72] hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
1
From: Andrew Jones <drjones@redhat.com>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Signed-off-by: Andrew Jones <drjones@redhat.com>
3
The real device advertises this mode and the device model already advertises
4
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
4
100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to
5
Reviewed-by: Eric Auger <eric.auger@redhat.com>
5
make the model more realistic.
6
Message-id: 20200629140938.17566-3-drjones@redhat.com
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
9
Tested-by: Guenter Roeck <linux@roeck-us.net>
10
Message-id: 20241102125724.532843-6-shentey@gmail.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
12
---
9
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
13
hw/net/lan9118_phy.c | 4 ++--
10
1 file changed, 3 insertions(+)
14
1 file changed, 2 insertions(+), 2 deletions(-)
11
15
12
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
13
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
14
--- a/tests/qtest/bios-tables-test-allowed-diff.h
18
--- a/hw/net/lan9118_phy.c
15
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
19
+++ b/hw/net/lan9118_phy.c
16
@@ -1 +1,4 @@
20
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
17
/* List of comma-separated changed AML files to ignore */
21
break;
18
+"tests/data/acpi/virt/DSDT",
22
case MII_ANAR:
19
+"tests/data/acpi/virt/DSDT.memhp",
23
s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
20
+"tests/data/acpi/virt/DSDT.numamem",
24
- MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
25
- MII_ANAR_SELECT))
26
+ MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD |
27
+ MII_ANAR_10 | MII_ANAR_SELECT))
28
| MII_ANAR_TX;
29
break;
30
case 30: /* Interrupt mask */
21
--
31
--
22
2.20.1
32
2.34.1
23
24
diff view generated by jsdifflib
[PULL 06/34] virtio-iommu: Handle reserved regions in the translation process
[PULL 06/72] fpu: handle raising Invalid for infzero in pick_nan_muladd
1
From: Eric Auger <eric.auger@redhat.com>
1
For IEEE fused multiply-add, the (0 * inf) + NaN case should raise
2
Invalid for the multiplication of 0 by infinity. Currently we handle
3
this in the per-architecture ifdef ladder in pickNaNMulAdd().
4
However, since this isn't really architecture specific we can hoist
5
it up to the generic code.
2
6
3
When translating an address we need to check if it belongs to
7
For the cases where the infzero test in pickNaNMulAdd was
4
a reserved virtual address range. If it does, there are 2 cases:
8
returning 2, we can delete the check entirely and allow the
9
code to fall into the normal pick-a-NaN handling, because this
10
will return 2 anyway (input 'c' being the only NaN in this case).
11
For the cases where infzero was returning 3 to indicate "return
12
the default NaN", we must retain that "return 3".
5
13
6
- it belongs to a RESERVED region: the guest should neither use
14
For Arm, this looks like it might be a behaviour change because we
7
this address in a MAP not instruct the end-point to DMA on
15
used to set float_flag_invalid | float_flag_invalid_imz only if C is
8
them. We report an error
16
a quiet NaN. However, it is not, because Arm target code never looks
17
at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we
18
already raised float_flag_invalid via the "abc_mask &
19
float_cmask_snan" check in pick_nan_muladd.
9
20
10
- It belongs to an MSI region: we bypass the translation.
21
For any target architecture using the "default implementation" at the
22
bottom of the ifdef, this is a behaviour change but will be fixing a
23
bug (where we failed to raise the Invalid exception for (0 * inf +
24
QNaN). The architectures using the default case are:
25
* hppa
26
* i386
27
* sh4
28
* tricore
11
29
12
Signed-off-by: Eric Auger <eric.auger@redhat.com>
30
The x86, Tricore and SH4 CPU architecture manuals are clear that this
13
Reviewed-by: Peter Xu <peterx@redhat.com>
31
should have raised Invalid; HPPA is a bit vaguer but still seems
14
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
32
clear enough.
15
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
33
16
Message-id: 20200629070404.10969-4-eric.auger@redhat.com
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
36
Message-id: 20241202131347.498124-2-peter.maydell@linaro.org
18
---
37
---
19
hw/virtio/virtio-iommu.c | 20 ++++++++++++++++++++
38
fpu/softfloat-parts.c.inc | 13 +++++++------
20
1 file changed, 20 insertions(+)
39
fpu/softfloat-specialize.c.inc | 29 +----------------------------
40
2 files changed, 8 insertions(+), 34 deletions(-)
21
41
22
diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c
42
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
23
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/virtio/virtio-iommu.c
44
--- a/fpu/softfloat-parts.c.inc
25
+++ b/hw/virtio/virtio-iommu.c
45
+++ b/fpu/softfloat-parts.c.inc
26
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr,
46
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
27
uint32_t sid, flags;
47
int ab_mask, int abc_mask)
28
bool bypass_allowed;
48
{
29
bool found;
49
int which;
30
+ int i;
50
+ bool infzero = (ab_mask == float_cmask_infzero);
31
51
32
interval.low = addr;
52
if (unlikely(abc_mask & float_cmask_snan)) {
33
interval.high = addr + 1;
53
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
34
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr,
35
goto unlock;
36
}
54
}
37
55
38
+ for (i = 0; i < s->nb_reserved_regions; i++) {
56
- which = pickNaNMulAdd(a->cls, b->cls, c->cls,
39
+ ReservedRegion *reg = &s->reserved_regions[i];
57
- ab_mask == float_cmask_infzero, s);
40
+
58
+ if (infzero) {
41
+ if (addr >= reg->low && addr <= reg->high) {
59
+ /* This is (0 * inf) + NaN or (inf * 0) + NaN */
42
+ switch (reg->type) {
60
+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
43
+ case VIRTIO_IOMMU_RESV_MEM_T_MSI:
44
+ entry.perm = flag;
45
+ break;
46
+ case VIRTIO_IOMMU_RESV_MEM_T_RESERVED:
47
+ default:
48
+ virtio_iommu_report_fault(s, VIRTIO_IOMMU_FAULT_R_MAPPING,
49
+ VIRTIO_IOMMU_FAULT_F_ADDRESS,
50
+ sid, addr);
51
+ break;
52
+ }
53
+ goto unlock;
54
+ }
55
+ }
61
+ }
56
+
62
+
57
if (!ep->domain) {
63
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
58
if (!bypass_allowed) {
64
59
error_report_once("%s %02x:%02x.%01x not attached to any domain",
65
if (s->default_nan_mode || which == 3) {
66
- /*
67
- * Note that this check is after pickNaNMulAdd so that function
68
- * has an opportunity to set the Invalid flag for infzero.
69
- */
70
parts_default_nan(a, s);
71
return a;
72
}
73
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
74
index XXXXXXX..XXXXXXX 100644
75
--- a/fpu/softfloat-specialize.c.inc
76
+++ b/fpu/softfloat-specialize.c.inc
77
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
78
* the default NaN
79
*/
80
if (infzero && is_qnan(c_cls)) {
81
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
82
return 3;
83
}
84
85
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
86
* case sets InvalidOp and returns the default NaN
87
*/
88
if (infzero) {
89
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
90
return 3;
91
}
92
/* Prefer sNaN over qNaN, in the a, b, c order. */
93
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
94
* For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
95
* case sets InvalidOp and returns the input value 'c'
96
*/
97
- if (infzero) {
98
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
99
- return 2;
100
- }
101
/* Prefer sNaN over qNaN, in the c, a, b order. */
102
if (is_snan(c_cls)) {
103
return 2;
104
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
105
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
106
* case sets InvalidOp and returns the input value 'c'
107
*/
108
- if (infzero) {
109
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
110
- return 2;
111
- }
112
+
113
/* Prefer sNaN over qNaN, in the c, a, b order. */
114
if (is_snan(c_cls)) {
115
return 2;
116
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
117
* to return an input NaN if we have one (ie c) rather than generating
118
* a default NaN
119
*/
120
- if (infzero) {
121
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
122
- return 2;
123
- }
124
125
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
126
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
127
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
128
return 1;
129
}
130
#elif defined(TARGET_RISCV)
131
- /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
132
- if (infzero) {
133
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
134
- }
135
return 3; /* default NaN */
136
#elif defined(TARGET_S390X)
137
if (infzero) {
138
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
139
return 3;
140
}
141
142
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
143
return 2;
144
}
145
#elif defined(TARGET_SPARC)
146
- /* For (inf,0,nan) return c. */
147
- if (infzero) {
148
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
149
- return 2;
150
- }
151
/* Prefer SNaN over QNaN, order C, B, A. */
152
if (is_snan(c_cls)) {
153
return 2;
154
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
155
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
156
* an input NaN if we have one (ie c).
157
*/
158
- if (infzero) {
159
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
160
- return 2;
161
- }
162
if (status->use_first_nan) {
163
if (is_nan(a_cls)) {
164
return 0;
60
--
165
--
61
2.20.1
166
2.34.1
62
63
diff view generated by jsdifflib
New patch
[PULL 07/72] fpu: Check for default_nan_mode before calling pickNaNMulAdd
1
If the target sets default_nan_mode then we're always going to return
2
the default NaN, and pickNaNMulAdd() no longer has any side effects.
3
For consistency with pickNaN(), check for default_nan_mode before
4
calling pickNaNMulAdd().
1
5
6
When we convert pickNaNMulAdd() to allow runtime selection of the NaN
7
propagation rule, this means we won't have to make the targets which
8
use default_nan_mode also set a propagation rule.
9
10
Since RiscV always uses default_nan_mode, this allows us to remove
11
its ifdef case from pickNaNMulAdd().
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-3-peter.maydell@linaro.org
16
---
17
fpu/softfloat-parts.c.inc | 8 ++++++--
18
fpu/softfloat-specialize.c.inc | 9 +++++++--
19
2 files changed, 13 insertions(+), 4 deletions(-)
20
21
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
22
index XXXXXXX..XXXXXXX 100644
23
--- a/fpu/softfloat-parts.c.inc
24
+++ b/fpu/softfloat-parts.c.inc
25
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
26
float_raise(float_flag_invalid | float_flag_invalid_imz, s);
27
}
28
29
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
30
+ if (s->default_nan_mode) {
31
+ which = 3;
32
+ } else {
33
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ }
35
36
- if (s->default_nan_mode || which == 3) {
37
+ if (which == 3) {
38
parts_default_nan(a, s);
39
return a;
40
}
41
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
42
index XXXXXXX..XXXXXXX 100644
43
--- a/fpu/softfloat-specialize.c.inc
44
+++ b/fpu/softfloat-specialize.c.inc
45
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
46
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
47
bool infzero, float_status *status)
48
{
49
+ /*
50
+ * We guarantee not to require the target to tell us how to
51
+ * pick a NaN if we're always returning the default NaN.
52
+ * But if we're not in default-NaN mode then the target must
53
+ * specify.
54
+ */
55
+ assert(!status->default_nan_mode);
56
#if defined(TARGET_ARM)
57
/* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
58
* the default NaN
59
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
60
} else {
61
return 1;
62
}
63
-#elif defined(TARGET_RISCV)
64
- return 3; /* default NaN */
65
#elif defined(TARGET_S390X)
66
if (infzero) {
67
return 3;
68
--
69
2.34.1
diff view generated by jsdifflib
[PULL 19/34] hw/arm/spitz: Keep pointers to MPU and SSI devices in SpitzMachineState
[PULL 08/72] softfloat: Allow runtime choice of inf * 0 + NaN result
1
Keep pointers to the MPU and the SSI devices in SpitzMachineState.
1
IEEE 758 does not define a fixed rule for what NaN to return in
2
We're going to want to make GPIO connections between some of the
2
the case of a fused multiply-add of inf * 0 + NaN. Different
3
SSI devices and the SCPs, so we want to keep hold of a pointer to
3
architectures thus do different things:
4
those; putting the MPU into the struct allows us to pass just
4
* some return the default NaN
5
one thing to spitz_ssp_attach() rather than two.
5
* some return the input NaN
6
6
* Arm returns the default NaN if the input NaN is quiet,
7
We have to retain the setting of the global "max1111" variable
7
and the input NaN if it is signalling
8
for the moment as it is used in spitz_adc_temp_on(); later in
8
9
this series of commits we will be able to remove it.
9
We want to make this logic be runtime selected rather than
10
hardcoded into the binary, because:
11
* this will let us have multiple targets in one QEMU binary
12
* the Arm FEAT_AFP architectural feature includes letting
13
the guest select a NaN propagation rule at runtime
14
15
In this commit we add an enum for the propagation rule, the field in
16
float_status, and the corresponding getters and setters. We change
17
pickNaNMulAdd to honour this, but because all targets still leave
18
this field at its default 0 value, the fallback logic will pick the
19
rule type with the old ifdef ladder.
20
21
Note that four architectures both use the muladd softfloat functions
22
and did not have a branch of the ifdef ladder to specify their
23
behaviour (and so were ending up with the "default" case, probably
24
wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set
25
default_nan_mode, and so will never get into pickNaNMulAdd(). For
26
HPPA and i386 we retain the same behaviour as the old default-case,
27
which is to not ever return the default NaN. This might not be
28
correct but it is not a behaviour change.
10
29
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
31
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20200628142429.17111-4-peter.maydell@linaro.org
32
Message-id: 20241202131347.498124-4-peter.maydell@linaro.org
14
---
33
---
15
hw/arm/spitz.c | 50 ++++++++++++++++++++++++++++----------------------
34
include/fpu/softfloat-helpers.h | 11 ++++
16
1 file changed, 28 insertions(+), 22 deletions(-)
35
include/fpu/softfloat-types.h | 23 +++++++++
17
36
fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++-----------
18
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
37
3 files changed, 95 insertions(+), 30 deletions(-)
38
39
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
19
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/spitz.c
41
--- a/include/fpu/softfloat-helpers.h
21
+++ b/hw/arm/spitz.c
42
+++ b/include/fpu/softfloat-helpers.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct {
43
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
23
44
status->float_2nan_prop_rule = rule;
24
typedef struct {
25
MachineState parent;
26
+ PXA2xxState *mpu;
27
+ DeviceState *mux;
28
+ DeviceState *lcdtg;
29
+ DeviceState *ads7846;
30
+ DeviceState *max1111;
31
} SpitzMachineState;
32
33
#define TYPE_SPITZ_MACHINE "spitz-common"
34
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_realize(SSISlave *d, Error **errp)
35
s->bus[2] = ssi_create_bus(dev, "ssi2");
36
}
45
}
37
46
38
-static void spitz_ssp_attach(PXA2xxState *cpu)
47
+static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
39
+static void spitz_ssp_attach(SpitzMachineState *sms)
48
+ float_status *status)
49
+{
50
+ status->float_infzeronan_rule = rule;
51
+}
52
+
53
static inline void set_flush_to_zero(bool val, float_status *status)
40
{
54
{
41
- DeviceState *mux;
55
status->flush_to_zero = val;
42
- DeviceState *dev;
56
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
43
void *bus;
57
return status->float_2nan_prop_rule;
44
45
- mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
46
+ sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
47
48
- bus = qdev_get_child_bus(mux, "ssi0");
49
- ssi_create_slave(bus, "spitz-lcdtg");
50
+ bus = qdev_get_child_bus(sms->mux, "ssi0");
51
+ sms->lcdtg = ssi_create_slave(bus, "spitz-lcdtg");
52
53
- bus = qdev_get_child_bus(mux, "ssi1");
54
- dev = ssi_create_slave(bus, "ads7846");
55
- qdev_connect_gpio_out(dev, 0,
56
- qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_TP_INT));
57
+ bus = qdev_get_child_bus(sms->mux, "ssi1");
58
+ sms->ads7846 = ssi_create_slave(bus, "ads7846");
59
+ qdev_connect_gpio_out(sms->ads7846, 0,
60
+ qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
61
62
- bus = qdev_get_child_bus(mux, "ssi2");
63
- max1111 = ssi_create_slave(bus, "max1111");
64
- max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
65
- max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
66
- max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
67
+ bus = qdev_get_child_bus(sms->mux, "ssi2");
68
+ sms->max1111 = ssi_create_slave(bus, "max1111");
69
+ max1111 = sms->max1111;
70
+ max111x_set_input(sms->max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
71
+ max111x_set_input(sms->max1111, MAX1111_BATT_TEMP, 0);
72
+ max111x_set_input(sms->max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
73
74
- qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
75
- qdev_get_gpio_in(mux, 0));
76
- qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
77
- qdev_get_gpio_in(mux, 1));
78
- qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
79
- qdev_get_gpio_in(mux, 2));
80
+ qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS,
81
+ qdev_get_gpio_in(sms->mux, 0));
82
+ qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_ADS7846_CS,
83
+ qdev_get_gpio_in(sms->mux, 1));
84
+ qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_MAX1111_CS,
85
+ qdev_get_gpio_in(sms->mux, 2));
86
}
58
}
87
59
88
/* CF Microdrive */
60
+static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
89
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info spitz_binfo = {
61
+{
90
static void spitz_common_init(MachineState *machine)
62
+ return status->float_infzeronan_rule;
63
+}
64
+
65
static inline bool get_flush_to_zero(float_status *status)
91
{
66
{
92
SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine);
67
return status->flush_to_zero;
93
+ SpitzMachineState *sms = SPITZ_MACHINE(machine);
68
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
94
enum spitz_model_e model = smc->model;
69
index XXXXXXX..XXXXXXX 100644
95
PXA2xxState *mpu;
70
--- a/include/fpu/softfloat-types.h
96
DeviceState *scp0, *scp1 = NULL;
71
+++ b/include/fpu/softfloat-types.h
97
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
72
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
98
/* Setup CPU & memory */
73
float_2nan_prop_x87,
99
mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,
74
} Float2NaNPropRule;
100
machine->cpu_type);
75
101
+ sms->mpu = mpu;
76
+/*
102
77
+ * Rule for result of fused multiply-add 0 * Inf + NaN.
103
sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
78
+ * This must be a NaN, but implementations differ on whether this
104
79
+ * is the input NaN or the default NaN.
105
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
80
+ *
106
/* Setup peripherals */
81
+ * You don't need to set this if default_nan_mode is enabled.
107
spitz_keyboard_register(mpu);
82
+ * When not in default-NaN mode, it is an error for the target
108
83
+ * not to set the rule in float_status if it uses muladd, and we
109
- spitz_ssp_attach(mpu);
84
+ * will assert if we need to handle an input NaN and no rule was
110
+ spitz_ssp_attach(sms);
85
+ * selected.
111
86
+ */
112
scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
87
+typedef enum __attribute__((__packed__)) {
113
if (model != akita) {
88
+ /* No propagation rule specified */
89
+ float_infzeronan_none = 0,
90
+ /* Result is never the default NaN (so always the input NaN) */
91
+ float_infzeronan_dnan_never,
92
+ /* Result is always the default NaN */
93
+ float_infzeronan_dnan_always,
94
+ /* Result is the default NaN if the input NaN is quiet */
95
+ float_infzeronan_dnan_if_qnan,
96
+} FloatInfZeroNaNRule;
97
+
98
/*
99
* Floating Point Status. Individual architectures may maintain
100
* several versions of float_status for different functions. The
101
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
102
FloatRoundMode float_rounding_mode;
103
FloatX80RoundPrec floatx80_rounding_precision;
104
Float2NaNPropRule float_2nan_prop_rule;
105
+ FloatInfZeroNaNRule float_infzeronan_rule;
106
bool tininess_before_rounding;
107
/* should denormalised results go to zero and set the inexact flag? */
108
bool flush_to_zero;
109
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
110
index XXXXXXX..XXXXXXX 100644
111
--- a/fpu/softfloat-specialize.c.inc
112
+++ b/fpu/softfloat-specialize.c.inc
113
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
114
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
115
bool infzero, float_status *status)
116
{
117
+ FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
118
+
119
/*
120
* We guarantee not to require the target to tell us how to
121
* pick a NaN if we're always returning the default NaN.
122
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
123
* specify.
124
*/
125
assert(!status->default_nan_mode);
126
+
127
+ if (rule == float_infzeronan_none) {
128
+ /*
129
+ * Temporarily fall back to ifdef ladder
130
+ */
131
#if defined(TARGET_ARM)
132
- /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
133
- * the default NaN
134
- */
135
- if (infzero && is_qnan(c_cls)) {
136
- return 3;
137
+ /*
138
+ * For ARM, the (inf,zero,qnan) case returns the default NaN,
139
+ * but (inf,zero,snan) returns the input NaN.
140
+ */
141
+ rule = float_infzeronan_dnan_if_qnan;
142
+#elif defined(TARGET_MIPS)
143
+ if (snan_bit_is_one(status)) {
144
+ /*
145
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
146
+ * case sets InvalidOp and returns the default NaN
147
+ */
148
+ rule = float_infzeronan_dnan_always;
149
+ } else {
150
+ /*
151
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
152
+ * case sets InvalidOp and returns the input value 'c'
153
+ */
154
+ rule = float_infzeronan_dnan_never;
155
+ }
156
+#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
157
+ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
158
+ defined(TARGET_I386) || defined(TARGET_LOONGARCH)
159
+ /*
160
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
161
+ * case sets InvalidOp and returns the input value 'c'
162
+ */
163
+ /*
164
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
165
+ * to return an input NaN if we have one (ie c) rather than generating
166
+ * a default NaN
167
+ */
168
+ rule = float_infzeronan_dnan_never;
169
+#elif defined(TARGET_S390X)
170
+ rule = float_infzeronan_dnan_always;
171
+#endif
172
}
173
174
+ if (infzero) {
175
+ /*
176
+ * Inf * 0 + NaN -- some implementations return the default NaN here,
177
+ * and some return the input NaN.
178
+ */
179
+ switch (rule) {
180
+ case float_infzeronan_dnan_never:
181
+ return 2;
182
+ case float_infzeronan_dnan_always:
183
+ return 3;
184
+ case float_infzeronan_dnan_if_qnan:
185
+ return is_qnan(c_cls) ? 3 : 2;
186
+ default:
187
+ g_assert_not_reached();
188
+ }
189
+ }
190
+
191
+#if defined(TARGET_ARM)
192
+
193
/* This looks different from the ARM ARM pseudocode, because the ARM ARM
194
* puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
195
*/
196
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
197
}
198
#elif defined(TARGET_MIPS)
199
if (snan_bit_is_one(status)) {
200
- /*
201
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
202
- * case sets InvalidOp and returns the default NaN
203
- */
204
- if (infzero) {
205
- return 3;
206
- }
207
/* Prefer sNaN over qNaN, in the a, b, c order. */
208
if (is_snan(a_cls)) {
209
return 0;
210
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
211
return 2;
212
}
213
} else {
214
- /*
215
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
216
- * case sets InvalidOp and returns the input value 'c'
217
- */
218
/* Prefer sNaN over qNaN, in the c, a, b order. */
219
if (is_snan(c_cls)) {
220
return 2;
221
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
222
}
223
}
224
#elif defined(TARGET_LOONGARCH64)
225
- /*
226
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
227
- * case sets InvalidOp and returns the input value 'c'
228
- */
229
-
230
/* Prefer sNaN over qNaN, in the c, a, b order. */
231
if (is_snan(c_cls)) {
232
return 2;
233
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
234
return 1;
235
}
236
#elif defined(TARGET_PPC)
237
- /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
238
- * to return an input NaN if we have one (ie c) rather than generating
239
- * a default NaN
240
- */
241
-
242
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
243
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
244
*/
245
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
246
return 1;
247
}
248
#elif defined(TARGET_S390X)
249
- if (infzero) {
250
- return 3;
251
- }
252
-
253
if (is_snan(a_cls)) {
254
return 0;
255
} else if (is_snan(b_cls)) {
114
--
256
--
115
2.20.1
257
2.34.1
116
117
diff view generated by jsdifflib
New patch
[PULL 09/72] tests/fp: Explicitly set inf-zero-nan rule
1
Explicitly set a rule in the softfloat tests for the inf-zero-nan
2
muladd special case. In meson.build we put -DTARGET_ARM in fpcflags,
3
and so we should select here the Arm rule of
4
float_infzeronan_dnan_if_qnan.
1
5
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241202131347.498124-5-peter.maydell@linaro.org
9
---
10
tests/fp/fp-bench.c | 5 +++++
11
tests/fp/fp-test.c | 5 +++++
12
2 files changed, 10 insertions(+)
13
14
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tests/fp/fp-bench.c
17
+++ b/tests/fp/fp-bench.c
18
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
19
{
20
bench_func_t f;
21
22
+ /*
23
+ * These implementation-defined choices for various things IEEE
24
+ * doesn't specify match those used by the Arm architecture.
25
+ */
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
28
29
f = bench_funcs[operation][precision];
30
g_assert(f);
31
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/tests/fp/fp-test.c
34
+++ b/tests/fp/fp-test.c
35
@@ -XXX,XX +XXX,XX @@ void run_test(void)
36
{
37
unsigned int i;
38
39
+ /*
40
+ * These implementation-defined choices for various things IEEE
41
+ * doesn't specify match those used by the Arm architecture.
42
+ */
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
44
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
45
46
genCases_setLevel(test_level);
47
verCases_maxErrorCount = n_max_errors;
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 10/72] target/arm: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the Arm target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-6-peter.maydell@linaro.org
7
---
8
target/arm/cpu.c | 3 +++
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 4 insertions(+), 7 deletions(-)
11
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
17
* * tininess-before-rounding
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
20
+ * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
21
+ * and the input NaN if it is signalling
22
*/
23
static void arm_set_default_fp_behaviours(float_status *s)
24
{
25
set_float_detect_tininess(float_tininess_before_rounding, s);
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
28
}
29
30
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
32
index XXXXXXX..XXXXXXX 100644
33
--- a/fpu/softfloat-specialize.c.inc
34
+++ b/fpu/softfloat-specialize.c.inc
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
36
/*
37
* Temporarily fall back to ifdef ladder
38
*/
39
-#if defined(TARGET_ARM)
40
- /*
41
- * For ARM, the (inf,zero,qnan) case returns the default NaN,
42
- * but (inf,zero,snan) returns the input NaN.
43
- */
44
- rule = float_infzeronan_dnan_if_qnan;
45
-#elif defined(TARGET_MIPS)
46
+#if defined(TARGET_MIPS)
47
if (snan_bit_is_one(status)) {
48
/*
49
* For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
50
--
51
2.34.1
diff view generated by jsdifflib
New patch
[PULL 11/72] target/s390: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for s390, so we
2
can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-7-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_infzeronan_rule(float_infzeronan_dnan_always,
21
+ &env->fpu_status);
22
/* fall through */
23
case RESET_TYPE_S390_CPU_NORMAL:
24
env->psw.mask &= ~PSW_MASK_RI;
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
* a default NaN
31
*/
32
rule = float_infzeronan_dnan_never;
33
-#elif defined(TARGET_S390X)
34
- rule = float_infzeronan_dnan_always;
35
#endif
36
}
37
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/72] target/ppc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the PPC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-8-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 7 +++++++
9
fpu/softfloat-specialize.c.inc | 7 +------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
22
+ * to return an input NaN if we have one (ie c) rather than generating
23
+ * a default NaN
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
27
28
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
29
ppc_spr_t *spr = &env->spr_cb[i];
30
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
31
index XXXXXXX..XXXXXXX 100644
32
--- a/fpu/softfloat-specialize.c.inc
33
+++ b/fpu/softfloat-specialize.c.inc
34
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
*/
36
rule = float_infzeronan_dnan_never;
37
}
38
-#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
39
+#elif defined(TARGET_SPARC) || \
40
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
41
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
42
/*
43
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
44
* case sets InvalidOp and returns the input value 'c'
45
*/
46
- /*
47
- * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
48
- * to return an input NaN if we have one (ie c) rather than generating
49
- * a default NaN
50
- */
51
rule = float_infzeronan_dnan_never;
52
#endif
53
}
54
--
55
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/72] target/mips: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the MIPS target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-9-peter.maydell@linaro.org
7
---
8
target/mips/fpu_helper.h | 9 +++++++++
9
target/mips/msa.c | 4 ++++
10
fpu/softfloat-specialize.c.inc | 16 +---------------
11
3 files changed, 14 insertions(+), 15 deletions(-)
12
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/mips/fpu_helper.h
16
+++ b/target/mips/fpu_helper.h
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_flush_mode(CPUMIPSState *env)
18
static inline void restore_snan_bit_mode(CPUMIPSState *env)
19
{
20
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
21
+ FloatInfZeroNaNRule izn_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status);
28
set_default_nan_mode(!nan2008, &env->active_fpu.fp_status);
29
+ /*
30
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
31
+ * case sets InvalidOp and returns the default NaN.
32
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
33
+ * case sets InvalidOp and returns the input value 'c'.
34
+ */
35
+ izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
36
+ set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
37
}
38
39
static inline void restore_fp_status(CPUMIPSState *env)
40
diff --git a/target/mips/msa.c b/target/mips/msa.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/mips/msa.c
43
+++ b/target/mips/msa.c
44
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
45
46
/* set proper signanling bit meaning ("1" means "quiet") */
47
set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
48
+
49
+ /* Inf * 0 + NaN returns the input NaN */
50
+ set_float_infzeronan_rule(float_infzeronan_dnan_never,
51
+ &env->active_tc.msa_fp_status);
52
}
53
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
54
index XXXXXXX..XXXXXXX 100644
55
--- a/fpu/softfloat-specialize.c.inc
56
+++ b/fpu/softfloat-specialize.c.inc
57
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
58
/*
59
* Temporarily fall back to ifdef ladder
60
*/
61
-#if defined(TARGET_MIPS)
62
- if (snan_bit_is_one(status)) {
63
- /*
64
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
65
- * case sets InvalidOp and returns the default NaN
66
- */
67
- rule = float_infzeronan_dnan_always;
68
- } else {
69
- /*
70
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
71
- * case sets InvalidOp and returns the input value 'c'
72
- */
73
- rule = float_infzeronan_dnan_never;
74
- }
75
-#elif defined(TARGET_SPARC) || \
76
+#if defined(TARGET_SPARC) || \
77
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
78
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
79
/*
80
--
81
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/72] target/sparc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the SPARC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-10-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_SPARC) || \
34
- defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
35
+#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
36
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
37
/*
38
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/72] target/xtensa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the xtensa target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-11-peter.maydell@linaro.org
7
---
8
target/xtensa/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 +-
10
2 files changed, 3 insertions(+), 1 deletion(-)
11
12
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/xtensa/cpu.c
15
+++ b/target/xtensa/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
17
reset_mmu(env);
18
cs->halted = env->runstall;
19
#endif
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
set_no_signaling_nans(!dfpu, &env->fp_status);
23
xtensa_use_first_nan(env, !dfpu);
24
}
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
34
+#if defined(TARGET_HPPA) || \
35
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
36
/*
37
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 16/72] target/x86: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the x86 target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-12-peter.maydell@linaro.org
6
---
7
target/i386/tcg/fpu_helper.c | 7 +++++++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 8 insertions(+), 1 deletion(-)
10
11
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/i386/tcg/fpu_helper.c
14
+++ b/target/i386/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status);
18
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status);
19
+ /*
20
+ * Only SSE has multiply-add instructions. In the SDM Section 14.5.2
21
+ * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is
22
+ * specified -- for 0 * inf + NaN the input NaN is selected, and if
23
+ * there are multiple input NaNs they are selected in the order a, b, c.
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
26
}
27
28
static inline uint8_t save_exception_flags(CPUX86State *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
34
* Temporarily fall back to ifdef ladder
35
*/
36
#if defined(TARGET_HPPA) || \
37
- defined(TARGET_I386) || defined(TARGET_LOONGARCH)
38
+ defined(TARGET_LOONGARCH)
39
/*
40
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
41
* case sets InvalidOp and returns the input value 'c'
42
--
43
2.34.1
diff view generated by jsdifflib
New patch
[PULL 17/72] target/loongarch: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the loongarch target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-13-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 5 +++++
8
fpu/softfloat-specialize.c.inc | 7 +------
9
2 files changed, 6 insertions(+), 6 deletions(-)
10
11
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/loongarch/tcg/fpu_helper.c
14
+++ b/target/loongarch/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
16
&env->fp_status);
17
set_flush_to_zero(0, &env->fp_status);
18
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
19
+ /*
20
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
21
+ * case sets InvalidOp and returns the input value 'c'
22
+ */
23
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
}
25
26
int ieee_ex_to_loongarch(int xcpt)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
32
/*
33
* Temporarily fall back to ifdef ladder
34
*/
35
-#if defined(TARGET_HPPA) || \
36
- defined(TARGET_LOONGARCH)
37
- /*
38
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
- * case sets InvalidOp and returns the input value 'c'
40
- */
41
+#if defined(TARGET_HPPA)
42
rule = float_infzeronan_dnan_never;
43
#endif
44
}
45
--
46
2.34.1
diff view generated by jsdifflib
New patch
[PULL 18/72] target/hppa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the HPPA target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
As this is the last target to be converted to explicitly setting
5
the rule, we can remove the fallback code in pickNaNMulAdd()
6
entirely.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20241202131347.498124-14-peter.maydell@linaro.org
11
---
12
target/hppa/fpu_helper.c | 2 ++
13
fpu/softfloat-specialize.c.inc | 13 +------------
14
2 files changed, 3 insertions(+), 12 deletions(-)
15
16
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/hppa/fpu_helper.c
19
+++ b/target/hppa/fpu_helper.c
20
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
21
* HPPA does note implement a CPU reset method at all...
22
*/
23
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
24
+ /* For inf * 0 + NaN, return the input NaN */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
}
27
28
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
34
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
bool infzero, float_status *status)
36
{
37
- FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
38
-
39
/*
40
* We guarantee not to require the target to tell us how to
41
* pick a NaN if we're always returning the default NaN.
42
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
43
*/
44
assert(!status->default_nan_mode);
45
46
- if (rule == float_infzeronan_none) {
47
- /*
48
- * Temporarily fall back to ifdef ladder
49
- */
50
-#if defined(TARGET_HPPA)
51
- rule = float_infzeronan_dnan_never;
52
-#endif
53
- }
54
-
55
if (infzero) {
56
/*
57
* Inf * 0 + NaN -- some implementations return the default NaN here,
58
* and some return the input NaN.
59
*/
60
- switch (rule) {
61
+ switch (status->float_infzeronan_rule) {
62
case float_infzeronan_dnan_never:
63
return 2;
64
case float_infzeronan_dnan_always:
65
--
66
2.34.1
diff view generated by jsdifflib
[PULL 20/34] hw/arm/spitz: Keep pointers to scp0, scp1 in SpitzMachineState
[PULL 19/72] softfloat: Pass have_snan to pickNaNMulAdd
1
Keep pointers to scp0, scp1 in SpitzMachineState, and just pass
1
The new implementation of pickNaNMulAdd() will find it convenient
2
that to spitz_scoop_gpio_setup().
2
to know whether at least one of the three arguments to the muladd
3
3
was a signaling NaN. We already calculate that in the caller,
4
(We'll want to use some of the other fields in SpitzMachineState
4
so pass it in as a new bool have_snan.
5
in that function in the next commit.)
6
5
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200628142429.17111-5-peter.maydell@linaro.org
8
Message-id: 20241202131347.498124-15-peter.maydell@linaro.org
10
---
9
---
11
hw/arm/spitz.c | 34 +++++++++++++++++++---------------
10
fpu/softfloat-parts.c.inc | 5 +++--
12
1 file changed, 19 insertions(+), 15 deletions(-)
11
fpu/softfloat-specialize.c.inc | 2 +-
12
2 files changed, 4 insertions(+), 3 deletions(-)
13
13
14
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/spitz.c
16
--- a/fpu/softfloat-parts.c.inc
17
+++ b/hw/arm/spitz.c
17
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ typedef struct {
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
DeviceState *lcdtg;
20
DeviceState *ads7846;
21
DeviceState *max1111;
22
+ DeviceState *scp0;
23
+ DeviceState *scp1;
24
} SpitzMachineState;
25
26
#define TYPE_SPITZ_MACHINE "spitz-common"
27
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
28
#define SPITZ_SCP2_BACKLIGHT_ON 8
29
#define SPITZ_SCP2_MIC_BIAS 9
30
31
-static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
32
- DeviceState *scp0, DeviceState *scp1)
33
+static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
34
{
19
{
35
- qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
20
int which;
36
+ qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, sms->mpu, 8);
21
bool infzero = (ab_mask == float_cmask_infzero);
37
22
+ bool have_snan = (abc_mask & float_cmask_snan);
38
- qdev_connect_gpio_out(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
23
39
- qdev_connect_gpio_out(scp0, SPITZ_SCP_JK_B, outsignals[1]);
24
- if (unlikely(abc_mask & float_cmask_snan)) {
40
- qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
25
+ if (unlikely(have_snan)) {
41
- qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
42
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
43
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, outsignals[1]);
44
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
45
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
46
47
- if (scp1) {
48
- qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
49
- qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
50
+ if (sms->scp1) {
51
+ qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT,
52
+ outsignals[4]);
53
+ qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON,
54
+ outsignals[5]);
55
}
27
}
56
28
57
- qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
58
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
30
if (s->default_nan_mode) {
59
}
31
which = 3;
60
32
} else {
61
#define SPITZ_GPIO_HSYNC 22
33
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
62
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
34
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
63
SpitzMachineState *sms = SPITZ_MACHINE(machine);
64
enum spitz_model_e model = smc->model;
65
PXA2xxState *mpu;
66
- DeviceState *scp0, *scp1 = NULL;
67
MemoryRegion *address_space_mem = get_system_memory();
68
MemoryRegion *rom = g_new(MemoryRegion, 1);
69
70
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
71
72
spitz_ssp_attach(sms);
73
74
- scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
75
+ sms->scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
76
if (model != akita) {
77
- scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
78
+ sms->scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
79
+ } else {
80
+ sms->scp1 = NULL;
81
}
35
}
82
36
83
- spitz_scoop_gpio_setup(mpu, scp0, scp1);
37
if (which == 3) {
84
+ spitz_scoop_gpio_setup(sms);
38
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
85
39
index XXXXXXX..XXXXXXX 100644
86
spitz_gpio_setup(mpu, (model == akita) ? 1 : 2);
40
--- a/fpu/softfloat-specialize.c.inc
87
41
+++ b/fpu/softfloat-specialize.c.inc
42
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
43
| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
44
*----------------------------------------------------------------------------*/
45
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
46
- bool infzero, float_status *status)
47
+ bool infzero, bool have_snan, float_status *status)
48
{
49
/*
50
* We guarantee not to require the target to tell us how to
88
--
51
--
89
2.20.1
52
2.34.1
90
91
diff view generated by jsdifflib
[PULL 17/34] hw/arm/spitz: Detabify
[PULL 20/72] softfloat: Allow runtime choice of NaN propagation for muladd
1
The spitz board has been around a long time, and still has a fair number
1
IEEE 758 does not define a fixed rule for which NaN to pick as the
2
of hard-coded tab characters in it. We're about to do some work on
2
result if both operands of a 3-operand fused multiply-add operation
3
this source file, so start out by expanding out the tabs.
3
are NaNs. As a result different architectures have ended up with
4
4
different rules for propagating NaNs.
5
This commit is a pure whitespace only change.
5
6
QEMU currently hardcodes the NaN propagation logic into the binary
7
because pickNaNMulAdd() has an ifdef ladder for different targets.
8
We want to make the propagation rule instead be selectable at
9
runtime, because:
10
* this will let us have multiple targets in one QEMU binary
11
* the Arm FEAT_AFP architectural feature includes letting
12
the guest select a NaN propagation rule at runtime
13
14
In this commit we add an enum for the propagation rule, the field in
15
float_status, and the corresponding getters and setters. We change
16
pickNaNMulAdd to honour this, but because all targets still leave
17
this field at its default 0 value, the fallback logic will pick the
18
rule type with the old ifdef ladder.
19
20
It's valid not to set a propagation rule if default_nan_mode is
21
enabled, because in that case there's no need to pick a NaN; all the
22
callers of pickNaNMulAdd() catch this case and skip calling it.
6
23
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
26
Message-id: 20241202131347.498124-16-peter.maydell@linaro.org
10
Message-id: 20200628142429.17111-2-peter.maydell@linaro.org
11
---
27
---
12
hw/arm/spitz.c | 156 ++++++++++++++++++++++++-------------------------
28
include/fpu/softfloat-helpers.h | 11 +++
13
1 file changed, 78 insertions(+), 78 deletions(-)
29
include/fpu/softfloat-types.h | 55 +++++++++++
14
30
fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------
15
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
31
3 files changed, 107 insertions(+), 126 deletions(-)
32
33
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
16
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/spitz.c
35
--- a/include/fpu/softfloat-helpers.h
18
+++ b/hw/arm/spitz.c
36
+++ b/include/fpu/softfloat-helpers.h
19
@@ -XXX,XX +XXX,XX @@
37
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
20
#include "cpu.h"
38
status->float_2nan_prop_rule = rule;
21
39
}
22
#undef REG_FMT
40
23
-#define REG_FMT            "0x%02lx"
41
+static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule,
24
+#define REG_FMT "0x%02lx"
42
+ float_status *status)
25
43
+{
26
/* Spitz Flash */
44
+ status->float_3nan_prop_rule = rule;
27
-#define FLASH_BASE        0x0c000000
45
+}
28
-#define FLASH_ECCLPLB        0x00    /* Line parity 7 - 0 bit */
46
+
29
-#define FLASH_ECCLPUB        0x04    /* Line parity 15 - 8 bit */
47
static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
30
-#define FLASH_ECCCP        0x08    /* Column parity 5 - 0 bit */
48
float_status *status)
31
-#define FLASH_ECCCNTR        0x0c    /* ECC byte counter */
32
-#define FLASH_ECCCLRR        0x10    /* Clear ECC */
33
-#define FLASH_FLASHIO        0x14    /* Flash I/O */
34
-#define FLASH_FLASHCTL        0x18    /* Flash Control */
35
+#define FLASH_BASE 0x0c000000
36
+#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
37
+#define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */
38
+#define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */
39
+#define FLASH_ECCCNTR 0x0c /* ECC byte counter */
40
+#define FLASH_ECCCLRR 0x10 /* Clear ECC */
41
+#define FLASH_FLASHIO 0x14 /* Flash I/O */
42
+#define FLASH_FLASHCTL 0x18 /* Flash Control */
43
44
-#define FLASHCTL_CE0        (1 << 0)
45
-#define FLASHCTL_CLE        (1 << 1)
46
-#define FLASHCTL_ALE        (1 << 2)
47
-#define FLASHCTL_WP        (1 << 3)
48
-#define FLASHCTL_CE1        (1 << 4)
49
-#define FLASHCTL_RYBY        (1 << 5)
50
-#define FLASHCTL_NCE        (FLASHCTL_CE0 | FLASHCTL_CE1)
51
+#define FLASHCTL_CE0 (1 << 0)
52
+#define FLASHCTL_CLE (1 << 1)
53
+#define FLASHCTL_ALE (1 << 2)
54
+#define FLASHCTL_WP (1 << 3)
55
+#define FLASHCTL_CE1 (1 << 4)
56
+#define FLASHCTL_RYBY (1 << 5)
57
+#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
58
59
#define TYPE_SL_NAND "sl-nand"
60
#define SL_NAND(obj) OBJECT_CHECK(SLNANDState, (obj), TYPE_SL_NAND)
61
@@ -XXX,XX +XXX,XX @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
62
int ryby;
63
64
switch (addr) {
65
-#define BSHR(byte, from, to)    ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
66
+#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
67
case FLASH_ECCLPLB:
68
return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
69
BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
70
71
-#define BSHL(byte, from, to)    ((s->ecc.lp[byte] << (to - from)) & (1 << to))
72
+#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
73
case FLASH_ECCLPUB:
74
return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
75
BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
76
@@ -XXX,XX +XXX,XX @@ static void sl_nand_realize(DeviceState *dev, Error **errp)
77
78
/* Spitz Keyboard */
79
80
-#define SPITZ_KEY_STROBE_NUM    11
81
-#define SPITZ_KEY_SENSE_NUM    7
82
+#define SPITZ_KEY_STROBE_NUM 11
83
+#define SPITZ_KEY_SENSE_NUM 7
84
85
static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
86
12, 17, 91, 34, 36, 38, 39
87
@@ -XXX,XX +XXX,XX @@ static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
88
{ 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 },
89
};
90
91
-#define SPITZ_GPIO_AK_INT    13    /* Remote control */
92
-#define SPITZ_GPIO_SYNC        16    /* Sync button */
93
-#define SPITZ_GPIO_ON_KEY    95    /* Power button */
94
-#define SPITZ_GPIO_SWA        97    /* Lid */
95
-#define SPITZ_GPIO_SWB        96    /* Tablet mode */
96
+#define SPITZ_GPIO_AK_INT 13 /* Remote control */
97
+#define SPITZ_GPIO_SYNC 16 /* Sync button */
98
+#define SPITZ_GPIO_ON_KEY 95 /* Power button */
99
+#define SPITZ_GPIO_SWA 97 /* Lid */
100
+#define SPITZ_GPIO_SWB 96 /* Tablet mode */
101
102
/* The special buttons are mapped to unused keys */
103
static const int spitz_gpiomap[5] = {
104
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
105
#define SPITZ_MOD_CTRL (1 << 8)
106
#define SPITZ_MOD_FN (1 << 9)
107
108
-#define QUEUE_KEY(c)    s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
109
+#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
110
111
static void spitz_keyboard_handler(void *opaque, int keycode)
112
{
49
{
113
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_handler(void *opaque, int keycode)
50
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
114
uint16_t code;
51
return status->float_2nan_prop_rule;
115
int mapcode;
116
switch (keycode) {
117
- case 0x2a:    /* Left Shift */
118
+ case 0x2a: /* Left Shift */
119
s->modifiers |= 1;
120
break;
121
case 0xaa:
122
s->modifiers &= ~1;
123
break;
124
- case 0x36:    /* Right Shift */
125
+ case 0x36: /* Right Shift */
126
s->modifiers |= 2;
127
break;
128
case 0xb6:
129
s->modifiers &= ~2;
130
break;
131
- case 0x1d:    /* Control */
132
+ case 0x1d: /* Control */
133
s->modifiers |= 4;
134
break;
135
case 0x9d:
136
s->modifiers &= ~4;
137
break;
138
- case 0x38:    /* Alt */
139
+ case 0x38: /* Alt */
140
s->modifiers |= 8;
141
break;
142
case 0xb8:
143
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp)
144
145
/* LCD backlight controller */
146
147
-#define LCDTG_RESCTL    0x00
148
-#define LCDTG_PHACTRL    0x01
149
-#define LCDTG_DUTYCTRL    0x02
150
-#define LCDTG_POWERREG0    0x03
151
-#define LCDTG_POWERREG1    0x04
152
-#define LCDTG_GPOR3    0x05
153
-#define LCDTG_PICTRL    0x06
154
-#define LCDTG_POLCTRL    0x07
155
+#define LCDTG_RESCTL 0x00
156
+#define LCDTG_PHACTRL 0x01
157
+#define LCDTG_DUTYCTRL 0x02
158
+#define LCDTG_POWERREG0 0x03
159
+#define LCDTG_POWERREG1 0x04
160
+#define LCDTG_GPOR3 0x05
161
+#define LCDTG_PICTRL 0x06
162
+#define LCDTG_POLCTRL 0x07
163
164
typedef struct {
165
SSISlave ssidev;
166
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *dev, Error **errp)
167
168
/* SSP devices */
169
170
-#define CORGI_SSP_PORT        2
171
+#define CORGI_SSP_PORT 2
172
173
-#define SPITZ_GPIO_LCDCON_CS    53
174
-#define SPITZ_GPIO_ADS7846_CS    14
175
-#define SPITZ_GPIO_MAX1111_CS    20
176
-#define SPITZ_GPIO_TP_INT    11
177
+#define SPITZ_GPIO_LCDCON_CS 53
178
+#define SPITZ_GPIO_ADS7846_CS 14
179
+#define SPITZ_GPIO_MAX1111_CS 20
180
+#define SPITZ_GPIO_TP_INT 11
181
182
static DeviceState *max1111;
183
184
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
185
s->enable[line] = !level;
186
}
52
}
187
53
188
-#define MAX1111_BATT_VOLT    1
54
+static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status)
189
-#define MAX1111_BATT_TEMP    2
55
+{
190
-#define MAX1111_ACIN_VOLT    3
56
+ return status->float_3nan_prop_rule;
191
+#define MAX1111_BATT_VOLT 1
57
+}
192
+#define MAX1111_BATT_TEMP 2
58
+
193
+#define MAX1111_ACIN_VOLT 3
59
static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
194
195
-#define SPITZ_BATTERY_TEMP    0xe0    /* About 2.9V */
196
-#define SPITZ_BATTERY_VOLT    0xd0    /* About 4.0V */
197
-#define SPITZ_CHARGEON_ACIN    0x80    /* About 5.0V */
198
+#define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */
199
+#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
200
+#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
201
202
static void spitz_adc_temp_on(void *opaque, int line, int level)
203
{
60
{
204
@@ -XXX,XX +XXX,XX @@ static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
61
return status->float_infzeronan_rule;
205
62
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
206
/* Wm8750 and Max7310 on I2C */
63
index XXXXXXX..XXXXXXX 100644
207
64
--- a/include/fpu/softfloat-types.h
208
-#define AKITA_MAX_ADDR    0x18
65
+++ b/include/fpu/softfloat-types.h
209
-#define SPITZ_WM_ADDRL    0x1b
66
@@ -XXX,XX +XXX,XX @@ this code that are retained.
210
-#define SPITZ_WM_ADDRH    0x1a
67
#ifndef SOFTFLOAT_TYPES_H
211
+#define AKITA_MAX_ADDR 0x18
68
#define SOFTFLOAT_TYPES_H
212
+#define SPITZ_WM_ADDRL 0x1b
69
213
+#define SPITZ_WM_ADDRH 0x1a
70
+#include "hw/registerfields.h"
214
71
+
215
-#define SPITZ_GPIO_WM    5
72
/*
216
+#define SPITZ_GPIO_WM 5
73
* Software IEC/IEEE floating-point types.
217
74
*/
218
static void spitz_wm8750_addr(void *opaque, int line, int level)
75
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
76
float_2nan_prop_x87,
77
} Float2NaNPropRule;
78
79
+/*
80
+ * 3-input NaN propagation rule, for fused multiply-add. Individual
81
+ * architectures have different rules for which input NaN is
82
+ * propagated to the output when there is more than one NaN on the
83
+ * input.
84
+ *
85
+ * If default_nan_mode is enabled then it is valid not to set a NaN
86
+ * propagation rule, because the softfloat code guarantees not to try
87
+ * to pick a NaN to propagate in default NaN mode. When not in
88
+ * default-NaN mode, it is an error for the target not to set the rule
89
+ * in float_status if it uses a muladd, and we will assert if we need
90
+ * to handle an input NaN and no rule was selected.
91
+ *
92
+ * The naming scheme for Float3NaNPropRule values is:
93
+ * float_3nan_prop_s_abc:
94
+ * = "Prefer SNaN over QNaN, then operand A over B over C"
95
+ * float_3nan_prop_abc:
96
+ * = "Prefer A over B over C regardless of SNaN vs QNAN"
97
+ *
98
+ * For QEMU, the multiply-add operation is A * B + C.
99
+ */
100
+
101
+/*
102
+ * We set the Float3NaNPropRule enum values up so we can select the
103
+ * right value in pickNaNMulAdd in a data driven way.
104
+ */
105
+FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */
106
+FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */
107
+FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */
108
+FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */
109
+
110
+#define PROPRULE(X, Y, Z) \
111
+ ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT))
112
+
113
+typedef enum __attribute__((__packed__)) {
114
+ float_3nan_prop_none = 0, /* No propagation rule specified */
115
+ float_3nan_prop_abc = PROPRULE(0, 1, 2),
116
+ float_3nan_prop_acb = PROPRULE(0, 2, 1),
117
+ float_3nan_prop_bac = PROPRULE(1, 0, 2),
118
+ float_3nan_prop_bca = PROPRULE(1, 2, 0),
119
+ float_3nan_prop_cab = PROPRULE(2, 0, 1),
120
+ float_3nan_prop_cba = PROPRULE(2, 1, 0),
121
+ float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK,
122
+ float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK,
123
+ float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK,
124
+ float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK,
125
+ float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK,
126
+ float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK,
127
+} Float3NaNPropRule;
128
+
129
+#undef PROPRULE
130
+
131
/*
132
* Rule for result of fused multiply-add 0 * Inf + NaN.
133
* This must be a NaN, but implementations differ on whether this
134
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
135
FloatRoundMode float_rounding_mode;
136
FloatX80RoundPrec floatx80_rounding_precision;
137
Float2NaNPropRule float_2nan_prop_rule;
138
+ Float3NaNPropRule float_3nan_prop_rule;
139
FloatInfZeroNaNRule float_infzeronan_rule;
140
bool tininess_before_rounding;
141
/* should denormalised results go to zero and set the inexact flag? */
142
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
143
index XXXXXXX..XXXXXXX 100644
144
--- a/fpu/softfloat-specialize.c.inc
145
+++ b/fpu/softfloat-specialize.c.inc
146
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
147
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
148
bool infzero, bool have_snan, float_status *status)
219
{
149
{
220
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
150
+ FloatClass cls[3] = { a_cls, b_cls, c_cls };
151
+ Float3NaNPropRule rule = status->float_3nan_prop_rule;
152
+ int which;
153
+
154
/*
155
* We guarantee not to require the target to tell us how to
156
* pick a NaN if we're always returning the default NaN.
157
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
158
}
221
}
159
}
160
161
+ if (rule == float_3nan_prop_none) {
162
#if defined(TARGET_ARM)
163
-
164
- /* This looks different from the ARM ARM pseudocode, because the ARM ARM
165
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
166
- */
167
- if (is_snan(c_cls)) {
168
- return 2;
169
- } else if (is_snan(a_cls)) {
170
- return 0;
171
- } else if (is_snan(b_cls)) {
172
- return 1;
173
- } else if (is_qnan(c_cls)) {
174
- return 2;
175
- } else if (is_qnan(a_cls)) {
176
- return 0;
177
- } else {
178
- return 1;
179
- }
180
+ /*
181
+ * This looks different from the ARM ARM pseudocode, because the ARM ARM
182
+ * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
183
+ */
184
+ rule = float_3nan_prop_s_cab;
185
#elif defined(TARGET_MIPS)
186
- if (snan_bit_is_one(status)) {
187
- /* Prefer sNaN over qNaN, in the a, b, c order. */
188
- if (is_snan(a_cls)) {
189
- return 0;
190
- } else if (is_snan(b_cls)) {
191
- return 1;
192
- } else if (is_snan(c_cls)) {
193
- return 2;
194
- } else if (is_qnan(a_cls)) {
195
- return 0;
196
- } else if (is_qnan(b_cls)) {
197
- return 1;
198
+ if (snan_bit_is_one(status)) {
199
+ rule = float_3nan_prop_s_abc;
200
} else {
201
- return 2;
202
+ rule = float_3nan_prop_s_cab;
203
}
204
- } else {
205
- /* Prefer sNaN over qNaN, in the c, a, b order. */
206
- if (is_snan(c_cls)) {
207
- return 2;
208
- } else if (is_snan(a_cls)) {
209
- return 0;
210
- } else if (is_snan(b_cls)) {
211
- return 1;
212
- } else if (is_qnan(c_cls)) {
213
- return 2;
214
- } else if (is_qnan(a_cls)) {
215
- return 0;
216
- } else {
217
- return 1;
218
- }
219
- }
220
#elif defined(TARGET_LOONGARCH64)
221
- /* Prefer sNaN over qNaN, in the c, a, b order. */
222
- if (is_snan(c_cls)) {
223
- return 2;
224
- } else if (is_snan(a_cls)) {
225
- return 0;
226
- } else if (is_snan(b_cls)) {
227
- return 1;
228
- } else if (is_qnan(c_cls)) {
229
- return 2;
230
- } else if (is_qnan(a_cls)) {
231
- return 0;
232
- } else {
233
- return 1;
234
- }
235
+ rule = float_3nan_prop_s_cab;
236
#elif defined(TARGET_PPC)
237
- /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
238
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
239
- */
240
- if (is_nan(a_cls)) {
241
- return 0;
242
- } else if (is_nan(c_cls)) {
243
- return 2;
244
- } else {
245
- return 1;
246
- }
247
+ /*
248
+ * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
249
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
250
+ */
251
+ rule = float_3nan_prop_acb;
252
#elif defined(TARGET_S390X)
253
- if (is_snan(a_cls)) {
254
- return 0;
255
- } else if (is_snan(b_cls)) {
256
- return 1;
257
- } else if (is_snan(c_cls)) {
258
- return 2;
259
- } else if (is_qnan(a_cls)) {
260
- return 0;
261
- } else if (is_qnan(b_cls)) {
262
- return 1;
263
- } else {
264
- return 2;
265
- }
266
+ rule = float_3nan_prop_s_abc;
267
#elif defined(TARGET_SPARC)
268
- /* Prefer SNaN over QNaN, order C, B, A. */
269
- if (is_snan(c_cls)) {
270
- return 2;
271
- } else if (is_snan(b_cls)) {
272
- return 1;
273
- } else if (is_snan(a_cls)) {
274
- return 0;
275
- } else if (is_qnan(c_cls)) {
276
- return 2;
277
- } else if (is_qnan(b_cls)) {
278
- return 1;
279
- } else {
280
- return 0;
281
- }
282
+ rule = float_3nan_prop_s_cba;
283
#elif defined(TARGET_XTENSA)
284
- /*
285
- * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
286
- * an input NaN if we have one (ie c).
287
- */
288
- if (status->use_first_nan) {
289
- if (is_nan(a_cls)) {
290
- return 0;
291
- } else if (is_nan(b_cls)) {
292
- return 1;
293
+ if (status->use_first_nan) {
294
+ rule = float_3nan_prop_abc;
295
} else {
296
- return 2;
297
+ rule = float_3nan_prop_cba;
298
}
299
- } else {
300
- if (is_nan(c_cls)) {
301
- return 2;
302
- } else if (is_nan(b_cls)) {
303
- return 1;
304
- } else {
305
- return 0;
306
- }
307
- }
308
#else
309
- /* A default implementation: prefer a to b to c.
310
- * This is unlikely to actually match any real implementation.
311
- */
312
- if (is_nan(a_cls)) {
313
- return 0;
314
- } else if (is_nan(b_cls)) {
315
- return 1;
316
- } else {
317
- return 2;
318
- }
319
+ rule = float_3nan_prop_abc;
320
#endif
321
+ }
322
+
323
+ assert(rule != float_3nan_prop_none);
324
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
325
+ /* We have at least one SNaN input and should prefer it */
326
+ do {
327
+ which = rule & R_3NAN_1ST_MASK;
328
+ rule >>= R_3NAN_1ST_LENGTH;
329
+ } while (!is_snan(cls[which]));
330
+ } else {
331
+ do {
332
+ which = rule & R_3NAN_1ST_MASK;
333
+ rule >>= R_3NAN_1ST_LENGTH;
334
+ } while (!is_nan(cls[which]));
335
+ }
336
+ return which;
222
}
337
}
223
338
224
-#define SPITZ_SCP_LED_GREEN        1
339
/*----------------------------------------------------------------------------
225
-#define SPITZ_SCP_JK_B            2
226
-#define SPITZ_SCP_CHRG_ON        3
227
-#define SPITZ_SCP_MUTE_L        4
228
-#define SPITZ_SCP_MUTE_R        5
229
-#define SPITZ_SCP_CF_POWER        6
230
-#define SPITZ_SCP_LED_ORANGE        7
231
-#define SPITZ_SCP_JK_A            8
232
-#define SPITZ_SCP_ADC_TEMP_ON        9
233
-#define SPITZ_SCP2_IR_ON        1
234
-#define SPITZ_SCP2_AKIN_PULLUP        2
235
-#define SPITZ_SCP2_BACKLIGHT_CONT    7
236
-#define SPITZ_SCP2_BACKLIGHT_ON        8
237
-#define SPITZ_SCP2_MIC_BIAS        9
238
+#define SPITZ_SCP_LED_GREEN 1
239
+#define SPITZ_SCP_JK_B 2
240
+#define SPITZ_SCP_CHRG_ON 3
241
+#define SPITZ_SCP_MUTE_L 4
242
+#define SPITZ_SCP_MUTE_R 5
243
+#define SPITZ_SCP_CF_POWER 6
244
+#define SPITZ_SCP_LED_ORANGE 7
245
+#define SPITZ_SCP_JK_A 8
246
+#define SPITZ_SCP_ADC_TEMP_ON 9
247
+#define SPITZ_SCP2_IR_ON 1
248
+#define SPITZ_SCP2_AKIN_PULLUP 2
249
+#define SPITZ_SCP2_BACKLIGHT_CONT 7
250
+#define SPITZ_SCP2_BACKLIGHT_ON 8
251
+#define SPITZ_SCP2_MIC_BIAS 9
252
253
static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
254
DeviceState *scp0, DeviceState *scp1)
255
@@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
256
qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
257
}
258
259
-#define SPITZ_GPIO_HSYNC        22
260
-#define SPITZ_GPIO_SD_DETECT        9
261
-#define SPITZ_GPIO_SD_WP        81
262
-#define SPITZ_GPIO_ON_RESET        89
263
-#define SPITZ_GPIO_BAT_COVER        90
264
-#define SPITZ_GPIO_CF1_IRQ        105
265
-#define SPITZ_GPIO_CF1_CD        94
266
-#define SPITZ_GPIO_CF2_IRQ        106
267
-#define SPITZ_GPIO_CF2_CD        93
268
+#define SPITZ_GPIO_HSYNC 22
269
+#define SPITZ_GPIO_SD_DETECT 9
270
+#define SPITZ_GPIO_SD_WP 81
271
+#define SPITZ_GPIO_ON_RESET 89
272
+#define SPITZ_GPIO_BAT_COVER 90
273
+#define SPITZ_GPIO_CF1_IRQ 105
274
+#define SPITZ_GPIO_CF1_CD 94
275
+#define SPITZ_GPIO_CF2_IRQ 106
276
+#define SPITZ_GPIO_CF2_CD 93
277
278
static int spitz_hsync;
279
280
@@ -XXX,XX +XXX,XX @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
281
/* Board init. */
282
enum spitz_model_e { spitz, akita, borzoi, terrier };
283
284
-#define SPITZ_RAM    0x04000000
285
-#define SPITZ_ROM    0x00800000
286
+#define SPITZ_RAM 0x04000000
287
+#define SPITZ_ROM 0x00800000
288
289
static struct arm_boot_info spitz_binfo = {
290
.loader_start = PXA2XX_SDRAM_BASE,
291
--
340
--
292
2.20.1
341
2.34.1
293
294
diff view generated by jsdifflib
New patch
[PULL 21/72] tests/fp: Explicitly set 3-NaN propagation rule
1
Explicitly set a rule in the softfloat tests for propagating NaNs in
2
the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and
3
so we should select here the Arm rule of float_3nan_prop_s_cab.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-17-peter.maydell@linaro.org
8
---
9
tests/fp/fp-bench.c | 1 +
10
tests/fp/fp-test.c | 1 +
11
2 files changed, 2 insertions(+)
12
13
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/tests/fp/fp-bench.c
16
+++ b/tests/fp/fp-bench.c
17
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
18
* doesn't specify match those used by the Arm architecture.
19
*/
20
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
22
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
23
24
f = bench_funcs[operation][precision];
25
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/tests/fp/fp-test.c
28
+++ b/tests/fp/fp-test.c
29
@@ -XXX,XX +XXX,XX @@ void run_test(void)
30
* doesn't specify match those used by the Arm architecture.
31
*/
32
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
33
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
34
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
35
36
genCases_setLevel(test_level);
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 22/72] target/arm: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-18-peter.maydell@linaro.org
7
---
8
target/arm/cpu.c | 5 +++++
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 6 insertions(+), 7 deletions(-)
11
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
17
* * tininess-before-rounding
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
20
+ * * 3-input NaN propagation prefers SNaN over QNaN, and then
21
+ * operand C over A over B (see FPProcessNaNs3() pseudocode,
22
+ * but note that for QEMU muladd is a * b + c, whereas for
23
+ * the pseudocode function the arguments are in the order c, a, b.
24
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
25
* and the input NaN if it is signalling
26
*/
27
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
28
{
29
set_float_detect_tininess(float_tininess_before_rounding, s);
30
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
31
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
32
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
33
}
34
35
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
36
index XXXXXXX..XXXXXXX 100644
37
--- a/fpu/softfloat-specialize.c.inc
38
+++ b/fpu/softfloat-specialize.c.inc
39
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
40
}
41
42
if (rule == float_3nan_prop_none) {
43
-#if defined(TARGET_ARM)
44
- /*
45
- * This looks different from the ARM ARM pseudocode, because the ARM ARM
46
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
47
- */
48
- rule = float_3nan_prop_s_cab;
49
-#elif defined(TARGET_MIPS)
50
+#if defined(TARGET_MIPS)
51
if (snan_bit_is_one(status)) {
52
rule = float_3nan_prop_s_abc;
53
} else {
54
--
55
2.34.1
diff view generated by jsdifflib
New patch
[PULL 23/72] target/loongarch: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for loongarch, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-19-peter.maydell@linaro.org
7
---
8
target/loongarch/tcg/fpu_helper.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/loongarch/tcg/fpu_helper.c
15
+++ b/target/loongarch/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
17
* case sets InvalidOp and returns the input value 'c'
18
*/
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
21
}
22
23
int ieee_ex_to_loongarch(int xcpt)
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_LOONGARCH64)
33
- rule = float_3nan_prop_s_cab;
34
#elif defined(TARGET_PPC)
35
/*
36
* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 24/72] target/ppc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for PPC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-20-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 8 ++++++++
9
fpu/softfloat-specialize.c.inc | 6 ------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * NaN propagation for fused multiply-add:
22
+ * if fRA is a NaN return it; otherwise if fRB is a NaN return it;
23
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
24
+ * whereas QEMU labels the operands as (a * b) + c.
25
+ */
26
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status);
27
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status);
28
/*
29
* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
30
* to return an input NaN if we have one (ie c) rather than generating
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
32
index XXXXXXX..XXXXXXX 100644
33
--- a/fpu/softfloat-specialize.c.inc
34
+++ b/fpu/softfloat-specialize.c.inc
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
36
} else {
37
rule = float_3nan_prop_s_cab;
38
}
39
-#elif defined(TARGET_PPC)
40
- /*
41
- * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
42
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
43
- */
44
- rule = float_3nan_prop_acb;
45
#elif defined(TARGET_S390X)
46
rule = float_3nan_prop_s_abc;
47
#elif defined(TARGET_SPARC)
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 25/72] target/s390x: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for s390x, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-21-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
21
set_float_infzeronan_rule(float_infzeronan_dnan_always,
22
&env->fpu_status);
23
/* fall through */
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_S390X)
33
- rule = float_3nan_prop_s_abc;
34
#elif defined(TARGET_SPARC)
35
rule = float_3nan_prop_s_cba;
36
#elif defined(TARGET_XTENSA)
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 26/72] target/sparc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for SPARC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-22-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
22
/* For inf * 0 + NaN, return the input NaN */
23
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
} else {
31
rule = float_3nan_prop_s_cab;
32
}
33
-#elif defined(TARGET_SPARC)
34
- rule = float_3nan_prop_s_cba;
35
#elif defined(TARGET_XTENSA)
36
if (status->use_first_nan) {
37
rule = float_3nan_prop_abc;
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 27/72] target/mips: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-23-peter.maydell@linaro.org
7
---
8
target/mips/fpu_helper.h | 4 ++++
9
target/mips/msa.c | 3 +++
10
fpu/softfloat-specialize.c.inc | 8 +-------
11
3 files changed, 8 insertions(+), 7 deletions(-)
12
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/mips/fpu_helper.h
16
+++ b/target/mips/fpu_helper.h
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
18
{
19
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
20
FloatInfZeroNaNRule izn_rule;
21
+ Float3NaNPropRule nan3_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
28
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
29
+ nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
30
+ set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
31
+
32
}
33
34
static inline void restore_fp_status(CPUMIPSState *env)
35
diff --git a/target/mips/msa.c b/target/mips/msa.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/mips/msa.c
38
+++ b/target/mips/msa.c
39
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
40
set_float_2nan_prop_rule(float_2nan_prop_s_ab,
41
&env->active_tc.msa_fp_status);
42
43
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab,
44
+ &env->active_tc.msa_fp_status);
45
+
46
/* clear float_status exception flags */
47
set_float_exception_flags(0, &env->active_tc.msa_fp_status);
48
49
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
50
index XXXXXXX..XXXXXXX 100644
51
--- a/fpu/softfloat-specialize.c.inc
52
+++ b/fpu/softfloat-specialize.c.inc
53
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
54
}
55
56
if (rule == float_3nan_prop_none) {
57
-#if defined(TARGET_MIPS)
58
- if (snan_bit_is_one(status)) {
59
- rule = float_3nan_prop_s_abc;
60
- } else {
61
- rule = float_3nan_prop_s_cab;
62
- }
63
-#elif defined(TARGET_XTENSA)
64
+#if defined(TARGET_XTENSA)
65
if (status->use_first_nan) {
66
rule = float_3nan_prop_abc;
67
} else {
68
--
69
2.34.1
diff view generated by jsdifflib
[PULL 21/34] hw/arm/spitz: Implement inbound GPIO lines for bit5 and power signals
[PULL 28/72] target/xtensa: Set Float3NaNPropRule explicitly
1
Currently the Spitz board uses a nasty hack for the GPIO lines
1
Set the Float3NaNPropRule explicitly for xtensa, and remove the
2
that pass "bit5" and "power" information to the LCD controller:
2
ifdef from pickNaNMulAdd().
3
the lcdtg realize function sets a global variable to point to
4
the instance it just realized, and then the functions spitz_bl_power()
5
and spitz_bl_bit5() use that to find the device they are changing
6
the internal state of. There is a comment reading:
7
FIXME: Implement GPIO properly and remove this hack.
8
which was added in 2009.
9
10
Implement GPIO properly and remove this hack.
11
3
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20200628142429.17111-6-peter.maydell@linaro.org
6
Message-id: 20241202131347.498124-24-peter.maydell@linaro.org
15
---
7
---
16
hw/arm/spitz.c | 28 ++++++++++++----------------
8
target/xtensa/fpu_helper.c | 2 ++
17
1 file changed, 12 insertions(+), 16 deletions(-)
9
fpu/softfloat-specialize.c.inc | 8 --------
10
2 files changed, 2 insertions(+), 8 deletions(-)
18
11
19
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
12
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
20
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/spitz.c
14
--- a/target/xtensa/fpu_helper.c
22
+++ b/hw/arm/spitz.c
15
+++ b/target/xtensa/fpu_helper.c
23
@@ -XXX,XX +XXX,XX @@ static void spitz_bl_update(SpitzLCDTG *s)
16
@@ -XXX,XX +XXX,XX @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
24
zaurus_printf("LCD Backlight now off\n");
17
set_use_first_nan(use_first, &env->fp_status);
18
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
19
&env->fp_status);
20
+ set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
21
+ &env->fp_status);
25
}
22
}
26
23
27
-/* FIXME: Implement GPIO properly and remove this hack. */
24
void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v)
28
-static SpitzLCDTG *spitz_lcdtg;
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
29
-
26
index XXXXXXX..XXXXXXX 100644
30
static inline void spitz_bl_bit5(void *opaque, int line, int level)
27
--- a/fpu/softfloat-specialize.c.inc
31
{
28
+++ b/fpu/softfloat-specialize.c.inc
32
- SpitzLCDTG *s = spitz_lcdtg;
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
33
+ SpitzLCDTG *s = opaque;
34
int prev = s->bl_intensity;
35
36
if (level)
37
@@ -XXX,XX +XXX,XX @@ static inline void spitz_bl_bit5(void *opaque, int line, int level)
38
39
static inline void spitz_bl_power(void *opaque, int line, int level)
40
{
41
- SpitzLCDTG *s = spitz_lcdtg;
42
+ SpitzLCDTG *s = opaque;
43
s->bl_power = !!level;
44
spitz_bl_update(s);
45
}
46
@@ -XXX,XX +XXX,XX @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
47
return 0;
48
}
49
50
-static void spitz_lcdtg_realize(SSISlave *dev, Error **errp)
51
+static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
52
{
53
- SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
54
+ SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, ssi);
55
+ DeviceState *dev = DEVICE(s);
56
57
- spitz_lcdtg = s;
58
s->bl_power = 0;
59
s->bl_intensity = 0x20;
60
+
61
+ qdev_init_gpio_in_named(dev, spitz_bl_bit5, "bl_bit5", 1);
62
+ qdev_init_gpio_in_named(dev, spitz_bl_power, "bl_power", 1);
63
}
64
65
/* SSP devices */
66
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
67
case 3:
68
zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
69
break;
70
- case 4:
71
- spitz_bl_bit5(opaque, line, level);
72
- break;
73
- case 5:
74
- spitz_bl_power(opaque, line, level);
75
- break;
76
case 6:
77
spitz_adc_temp_on(opaque, line, level);
78
break;
79
+ default:
80
+ g_assert_not_reached();
81
}
30
}
82
}
31
83
32
if (rule == float_3nan_prop_none) {
84
@@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
33
-#if defined(TARGET_XTENSA)
85
34
- if (status->use_first_nan) {
86
if (sms->scp1) {
35
- rule = float_3nan_prop_abc;
87
qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT,
36
- } else {
88
- outsignals[4]);
37
- rule = float_3nan_prop_cba;
89
+ qdev_get_gpio_in_named(sms->lcdtg, "bl_bit5", 0));
38
- }
90
qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON,
39
-#else
91
- outsignals[5]);
40
rule = float_3nan_prop_abc;
92
+ qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0));
41
-#endif
93
}
42
}
94
43
95
qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
44
assert(rule != float_3nan_prop_none);
96
--
45
--
97
2.20.1
46
2.34.1
98
99
diff view generated by jsdifflib
New patch
[PULL 29/72] target/i386: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for i386. We had no
2
i386-specific behaviour in the old ifdef ladder, so we were using the
3
default "prefer a then b then c" fallback; this is actually the
4
correct per-the-spec handling for i386.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-25-peter.maydell@linaro.org
9
---
10
target/i386/tcg/fpu_helper.c | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/i386/tcg/fpu_helper.c
16
+++ b/target/i386/tcg/fpu_helper.c
17
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
18
* there are multiple input NaNs they are selected in the order a, b, c.
19
*/
20
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
22
}
23
24
static inline uint8_t save_exception_flags(CPUX86State *env)
25
--
26
2.34.1
diff view generated by jsdifflib
New patch
[PULL 30/72] target/hppa: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for HPPA, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
HPPA is the only target that was using the default branch of the
5
ifdef ladder (other targets either do not use muladd or set
6
default_nan_mode), so we can remove the ifdef fallback entirely now
7
(allowing the "rule not set" case to fall into the default of the
8
switch statement and assert).
9
10
We add a TODO note that the HPPA rule is probably wrong; this is
11
not a behavioural change for this refactoring.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-26-peter.maydell@linaro.org
16
---
17
target/hppa/fpu_helper.c | 8 ++++++++
18
fpu/softfloat-specialize.c.inc | 4 ----
19
2 files changed, 8 insertions(+), 4 deletions(-)
20
21
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/hppa/fpu_helper.c
24
+++ b/target/hppa/fpu_helper.c
25
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
26
* HPPA does note implement a CPU reset method at all...
27
*/
28
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
29
+ /*
30
+ * TODO: The HPPA architecture reference only documents its NaN
31
+ * propagation rule for 2-operand operations. Testing on real hardware
32
+ * might be necessary to confirm whether this order for muladd is correct.
33
+ * Not preferring the SNaN is almost certainly incorrect as it diverges
34
+ * from the documented rules for 2-operand operations.
35
+ */
36
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
37
/* For inf * 0 + NaN, return the input NaN */
38
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
39
}
40
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
41
index XXXXXXX..XXXXXXX 100644
42
--- a/fpu/softfloat-specialize.c.inc
43
+++ b/fpu/softfloat-specialize.c.inc
44
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
45
}
46
}
47
48
- if (rule == float_3nan_prop_none) {
49
- rule = float_3nan_prop_abc;
50
- }
51
-
52
assert(rule != float_3nan_prop_none);
53
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
54
/* We have at least one SNaN input and should prefer it */
55
--
56
2.34.1
diff view generated by jsdifflib
[PULL 18/34] hw/arm/spitz: Create SpitzMachineClass abstract base class
[PULL 31/72] fpu: Remove use_first_nan field from float_status
1
For the four Spitz-family machines (akita, borzoi, spitz, terrier)
1
The use_first_nan field in float_status was an xtensa-specific way to
2
create a proper abstract class SpitzMachineClass which encapsulates
2
select at runtime from two different NaN propagation rules. Now that
3
the common behaviour, rather than having them all derive directly
3
xtensa is using the target-agnostic NaN propagation rule selection
4
from TYPE_MACHINE:
4
that we've just added, we can remove use_first_nan, because there is
5
* instead of each machine class setting mc->init to a wrapper
5
no longer any code that reads it.
6
function which calls spitz_common_init() with parameters,
7
put that data in the SpitzMachineClass and make spitz_common_init
8
the SpitzMachineClass machine-init function
9
* move the settings of mc->block_default_type and
10
mc->ignore_memory_transaction_failures into the SpitzMachineClass
11
class init rather than repeating them in each machine's class init
12
13
(The motivation is that we're going to want to keep some state in
14
the SpitzMachineState so we can connect GPIOs between devices created
15
in one sub-function of the machine init to devices created in a
16
different sub-function.)
17
6
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20200628142429.17111-3-peter.maydell@linaro.org
9
Message-id: 20241202131347.498124-27-peter.maydell@linaro.org
21
---
10
---
22
hw/arm/spitz.c | 91 ++++++++++++++++++++++++++++++--------------------
11
include/fpu/softfloat-helpers.h | 5 -----
23
1 file changed, 55 insertions(+), 36 deletions(-)
12
include/fpu/softfloat-types.h | 1 -
13
target/xtensa/fpu_helper.c | 1 -
14
3 files changed, 7 deletions(-)
24
15
25
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
16
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
26
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/spitz.c
18
--- a/include/fpu/softfloat-helpers.h
28
+++ b/hw/arm/spitz.c
19
+++ b/include/fpu/softfloat-helpers.h
29
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static inline void set_snan_bit_is_one(bool val, float_status *status)
30
#include "exec/address-spaces.h"
21
status->snan_bit_is_one = val;
31
#include "cpu.h"
32
33
+enum spitz_model_e { spitz, akita, borzoi, terrier };
34
+
35
+typedef struct {
36
+ MachineClass parent;
37
+ enum spitz_model_e model;
38
+ int arm_id;
39
+} SpitzMachineClass;
40
+
41
+typedef struct {
42
+ MachineState parent;
43
+} SpitzMachineState;
44
+
45
+#define TYPE_SPITZ_MACHINE "spitz-common"
46
+#define SPITZ_MACHINE(obj) \
47
+ OBJECT_CHECK(SpitzMachineState, obj, TYPE_SPITZ_MACHINE)
48
+#define SPITZ_MACHINE_GET_CLASS(obj) \
49
+ OBJECT_GET_CLASS(SpitzMachineClass, obj, TYPE_SPITZ_MACHINE)
50
+#define SPITZ_MACHINE_CLASS(klass) \
51
+ OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE)
52
+
53
#undef REG_FMT
54
#define REG_FMT "0x%02lx"
55
56
@@ -XXX,XX +XXX,XX @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
57
}
22
}
58
23
59
/* Board init. */
24
-static inline void set_use_first_nan(bool val, float_status *status)
60
-enum spitz_model_e { spitz, akita, borzoi, terrier };
61
-
62
#define SPITZ_RAM 0x04000000
63
#define SPITZ_ROM 0x00800000
64
65
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info spitz_binfo = {
66
.ram_size = 0x04000000,
67
};
68
69
-static void spitz_common_init(MachineState *machine,
70
- enum spitz_model_e model, int arm_id)
71
+static void spitz_common_init(MachineState *machine)
72
{
73
+ SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine);
74
+ enum spitz_model_e model = smc->model;
75
PXA2xxState *mpu;
76
DeviceState *scp0, *scp1 = NULL;
77
MemoryRegion *address_space_mem = get_system_memory();
78
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine,
79
/* A 4.0 GB microdrive is permanently sitting in CF slot 0. */
80
spitz_microdrive_attach(mpu, 0);
81
82
- spitz_binfo.board_id = arm_id;
83
+ spitz_binfo.board_id = smc->arm_id;
84
arm_load_kernel(mpu->cpu, machine, &spitz_binfo);
85
sl_bootparam_write(SL_PXA_PARAM_BASE);
86
}
87
88
-static void spitz_init(MachineState *machine)
89
+static void spitz_common_class_init(ObjectClass *oc, void *data)
90
{
91
- spitz_common_init(machine, spitz, 0x2c9);
92
+ MachineClass *mc = MACHINE_CLASS(oc);
93
+
94
+ mc->block_default_type = IF_IDE;
95
+ mc->ignore_memory_transaction_failures = true;
96
+ mc->init = spitz_common_init;
97
}
98
99
-static void borzoi_init(MachineState *machine)
100
-{
25
-{
101
- spitz_common_init(machine, borzoi, 0x33f);
26
- status->use_first_nan = val;
102
-}
27
-}
103
-
28
-
104
-static void akita_init(MachineState *machine)
29
static inline void set_no_signaling_nans(bool val, float_status *status)
105
-{
106
- spitz_common_init(machine, akita, 0x2e8);
107
-}
108
-
109
-static void terrier_init(MachineState *machine)
110
-{
111
- spitz_common_init(machine, terrier, 0x33f);
112
-}
113
+static const TypeInfo spitz_common_info = {
114
+ .name = TYPE_SPITZ_MACHINE,
115
+ .parent = TYPE_MACHINE,
116
+ .abstract = true,
117
+ .instance_size = sizeof(SpitzMachineState),
118
+ .class_size = sizeof(SpitzMachineClass),
119
+ .class_init = spitz_common_class_init,
120
+};
121
122
static void akitapda_class_init(ObjectClass *oc, void *data)
123
{
30
{
124
MachineClass *mc = MACHINE_CLASS(oc);
31
status->no_signaling_nans = val;
125
+ SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
32
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
126
33
index XXXXXXX..XXXXXXX 100644
127
mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)";
34
--- a/include/fpu/softfloat-types.h
128
- mc->init = akita_init;
35
+++ b/include/fpu/softfloat-types.h
129
- mc->ignore_memory_transaction_failures = true;
36
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
130
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
37
* softfloat-specialize.inc.c)
131
+ smc->model = akita;
38
*/
132
+ smc->arm_id = 0x2e8;
39
bool snan_bit_is_one;
133
}
40
- bool use_first_nan;
134
41
bool no_signaling_nans;
135
static const TypeInfo akitapda_type = {
42
/* should overflowed results subtract re_bias to its exponent? */
136
.name = MACHINE_TYPE_NAME("akita"),
43
bool rebias_overflow;
137
- .parent = TYPE_MACHINE,
44
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
138
+ .parent = TYPE_SPITZ_MACHINE,
45
index XXXXXXX..XXXXXXX 100644
139
.class_init = akitapda_class_init,
46
--- a/target/xtensa/fpu_helper.c
140
};
47
+++ b/target/xtensa/fpu_helper.c
141
48
@@ -XXX,XX +XXX,XX @@ static const struct {
142
static void spitzpda_class_init(ObjectClass *oc, void *data)
49
50
void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
143
{
51
{
144
MachineClass *mc = MACHINE_CLASS(oc);
52
- set_use_first_nan(use_first, &env->fp_status);
145
+ SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
53
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
146
54
&env->fp_status);
147
mc->desc = "Sharp SL-C3000 (Spitz) PDA (PXA270)";
55
set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
148
- mc->init = spitz_init;
149
- mc->block_default_type = IF_IDE;
150
- mc->ignore_memory_transaction_failures = true;
151
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
152
+ smc->model = spitz;
153
+ smc->arm_id = 0x2c9;
154
}
155
156
static const TypeInfo spitzpda_type = {
157
.name = MACHINE_TYPE_NAME("spitz"),
158
- .parent = TYPE_MACHINE,
159
+ .parent = TYPE_SPITZ_MACHINE,
160
.class_init = spitzpda_class_init,
161
};
162
163
static void borzoipda_class_init(ObjectClass *oc, void *data)
164
{
165
MachineClass *mc = MACHINE_CLASS(oc);
166
+ SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
167
168
mc->desc = "Sharp SL-C3100 (Borzoi) PDA (PXA270)";
169
- mc->init = borzoi_init;
170
- mc->block_default_type = IF_IDE;
171
- mc->ignore_memory_transaction_failures = true;
172
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
173
+ smc->model = borzoi;
174
+ smc->arm_id = 0x33f;
175
}
176
177
static const TypeInfo borzoipda_type = {
178
.name = MACHINE_TYPE_NAME("borzoi"),
179
- .parent = TYPE_MACHINE,
180
+ .parent = TYPE_SPITZ_MACHINE,
181
.class_init = borzoipda_class_init,
182
};
183
184
static void terrierpda_class_init(ObjectClass *oc, void *data)
185
{
186
MachineClass *mc = MACHINE_CLASS(oc);
187
+ SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
188
189
mc->desc = "Sharp SL-C3200 (Terrier) PDA (PXA270)";
190
- mc->init = terrier_init;
191
- mc->block_default_type = IF_IDE;
192
- mc->ignore_memory_transaction_failures = true;
193
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
194
+ smc->model = terrier;
195
+ smc->arm_id = 0x33f;
196
}
197
198
static const TypeInfo terrierpda_type = {
199
.name = MACHINE_TYPE_NAME("terrier"),
200
- .parent = TYPE_MACHINE,
201
+ .parent = TYPE_SPITZ_MACHINE,
202
.class_init = terrierpda_class_init,
203
};
204
205
static void spitz_machine_init(void)
206
{
207
+ type_register_static(&spitz_common_info);
208
type_register_static(&akitapda_type);
209
type_register_static(&spitzpda_type);
210
type_register_static(&borzoipda_type);
211
--
56
--
212
2.20.1
57
2.34.1
213
214
diff view generated by jsdifflib
[PULL 30/34] hw/arm/spitz: Use LOG_GUEST_ERROR for bad guest register accesses
[PULL 32/72] target/m68k: Don't pass NULL float_status to floatx80_default_nan()
1
Instead of logging guest accesses to invalid register offsets in the
1
Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL)
2
Spitz flash device with zaurus_printf() (which just prints to stderr),
2
to get the NaN bit pattern to reset the FPU registers. This
3
use the usual qemu_log_mask(LOG_GUEST_ERROR,...).
3
works because it happens that our implementation of
4
floatx80_default_nan() doesn't actually look at the float_status
5
pointer except for TARGET_MIPS. However, this isn't guaranteed,
6
and to be able to remove the ifdef in floatx80_default_nan()
7
we're going to need a real float_status here.
8
9
Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status
10
earlier, and thus can pass it to floatx80_default_nan().
4
11
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Message-id: 20241202131347.498124-28-peter.maydell@linaro.org
8
Message-id: 20200628142429.17111-15-peter.maydell@linaro.org
9
---
15
---
10
hw/arm/spitz.c | 12 +++++++-----
16
target/m68k/cpu.c | 12 +++++++-----
11
1 file changed, 7 insertions(+), 5 deletions(-)
17
1 file changed, 7 insertions(+), 5 deletions(-)
12
18
13
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
19
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
14
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/spitz.c
21
--- a/target/m68k/cpu.c
16
+++ b/hw/arm/spitz.c
22
+++ b/target/m68k/cpu.c
17
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
18
#include "hw/ssi/ssi.h"
24
CPUState *cs = CPU(obj);
19
#include "hw/block/flash.h"
25
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj);
20
#include "qemu/timer.h"
26
CPUM68KState *env = cpu_env(cs);
21
+#include "qemu/log.h"
27
- floatx80 nan = floatx80_default_nan(NULL);
22
#include "hw/arm/sharpsl.h"
28
+ floatx80 nan;
23
#include "ui/console.h"
29
int i;
24
#include "hw/audio/wm8750.h"
30
25
@@ -XXX,XX +XXX,XX @@ typedef struct {
31
if (mcc->parent_phases.hold) {
26
#define zaurus_printf(format, ...) \
32
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
27
fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
33
#else
28
34
cpu_m68k_set_sr(env, SR_S | SR_I);
29
-#undef REG_FMT
35
#endif
30
-#define REG_FMT "0x%02lx"
36
- for (i = 0; i < 8; i++) {
31
-
37
- env->fregs[i].d = nan;
32
/* Spitz Flash */
38
- }
33
#define FLASH_BASE 0x0c000000
39
- cpu_m68k_set_fpcr(env, 0);
34
#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
40
/*
35
@@ -XXX,XX +XXX,XX @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
41
* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
36
return ecc_digest(&s->ecc, nand_getio(s->nand));
42
* 3.4 FLOATING-POINT INSTRUCTION DETAILS
37
43
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
38
default:
44
* preceding paragraph for nonsignaling NaNs.
39
- zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
45
*/
40
+ qemu_log_mask(LOG_GUEST_ERROR,
46
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
41
+ "sl_read: bad register offset 0x%02" HWADDR_PRIx "\n",
47
+
42
+ addr);
48
+ nan = floatx80_default_nan(&env->fp_status);
43
}
49
+ for (i = 0; i < 8; i++) {
44
return 0;
50
+ env->fregs[i].d = nan;
45
}
51
+ }
46
@@ -XXX,XX +XXX,XX @@ static void sl_write(void *opaque, hwaddr addr,
52
+ cpu_m68k_set_fpcr(env, 0);
47
break;
53
env->fpsr = 0;
48
54
49
default:
55
/* TODO: We should set PC from the interrupt vector. */
50
- zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
51
+ qemu_log_mask(LOG_GUEST_ERROR,
52
+ "sl_write: bad register offset 0x%02" HWADDR_PRIx "\n",
53
+ addr);
54
}
55
}
56
57
--
56
--
58
2.20.1
57
2.34.1
59
60
diff view generated by jsdifflib
[PULL 34/34] Deprecate TileGX port
[PULL 33/72] softfloat: Create floatx80 default NaN from parts64_default_nan
1
Deprecate our TileGX target support:
1
We create our 128-bit default NaN by calling parts64_default_nan()
2
* we have no active maintainer for it
2
and then adjusting the result. We can do the same trick for creating
3
* it has had essentially no contributions (other than tree-wide cleanups
3
the floatx80 default NaN, which lets us drop a target ifdef.
4
and similar) since it was first added
5
* the Linux kernel dropped support in 2018, as has glibc
6
4
7
Note the deprecation in the manual, but don't try to print a warning
5
floatx80 is used only by:
8
when QEMU runs -- printing unsuppressable messages is more obtrusive
6
i386
9
for linux-user mode than it would be for system-emulation mode, and
7
m68k
10
it doesn't seem worth trying to invent a new suppressible-error
8
arm nwfpe old floating-point emulation emulation support
11
system for linux-user just for this.
9
(which is essentially dead, especially the parts involving floatx80)
10
PPC (only in the xsrqpxp instruction, which just rounds an input
11
value by converting to floatx80 and back, so will never generate
12
the default NaN)
13
14
The floatx80 default NaN as currently implemented is:
15
m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1
16
i386: sign = 1, exp = 1...1, int = 1, frac = 10...0
17
18
These are the same as the parts64_default_nan for these architectures.
19
20
This is technically a possible behaviour change for arm linux-user
21
nwfpe emulation emulation, because the default NaN will now have the
22
sign bit clear. But we were already generating a different floatx80
23
default NaN from the real kernel emulation we are supposedly
24
following, which appears to use an all-bits-1 value:
25
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267
26
27
This won't affect the only "real" use of the nwfpe emulation, which
28
is ancient binaries that used it as part of the old floating point
29
calling convention; that only uses loads and stores of 32 and 64 bit
30
floats, not any of the floatx80 behaviour the original hardware had.
31
We also get the nwfpe float64 default NaN value wrong:
32
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166
33
so if we ever cared about this obscure corner the right fix would be
34
to correct that so nwfpe used its own default-NaN setting rather
35
than the Arm VFP one.
12
36
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
37
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
38
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
39
Message-id: 20241202131347.498124-29-peter.maydell@linaro.org
16
Reviewed-by: Thomas Huth <thuth@redhat.com>
17
Message-id: 20200619154831.26319-1-peter.maydell@linaro.org
18
---
40
---
19
docs/system/deprecated.rst | 11 +++++++++++
41
fpu/softfloat-specialize.c.inc | 20 ++++++++++----------
20
1 file changed, 11 insertions(+)
42
1 file changed, 10 insertions(+), 10 deletions(-)
21
43
22
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
44
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
23
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
24
--- a/docs/system/deprecated.rst
46
--- a/fpu/softfloat-specialize.c.inc
25
+++ b/docs/system/deprecated.rst
47
+++ b/fpu/softfloat-specialize.c.inc
26
@@ -XXX,XX +XXX,XX @@ The above, converted to the current supported format::
48
@@ -XXX,XX +XXX,XX @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status)
27
49
floatx80 floatx80_default_nan(float_status *status)
28
json:{"file.driver":"rbd", "file.pool":"rbd", "file.image":"name"}
50
{
29
51
floatx80 r;
30
+linux-user mode CPUs
52
+ /*
31
+--------------------
53
+ * Extrapolate from the choices made by parts64_default_nan to fill
32
+
54
+ * in the floatx80 format. We assume that floatx80's explicit
33
+``tilegx`` CPUs (since 5.1.0)
55
+ * integer bit is always set (this is true for i386 and m68k,
34
+'''''''''''''''''''''''''''''
56
+ * which are the only real users of this format).
35
+
57
+ */
36
+The ``tilegx`` guest CPU support (which was only implemented in
58
+ FloatParts64 p64;
37
+linux-user mode) is deprecated and will be removed in a future version
59
+ parts64_default_nan(&p64, status);
38
+of QEMU. Support for this CPU was removed from the upstream Linux
60
39
+kernel in 2018, and has also been dropped from glibc.
61
- /* None of the targets that have snan_bit_is_one use floatx80. */
40
+
62
- assert(!snan_bit_is_one(status));
41
Related binaries
63
-#if defined(TARGET_M68K)
42
----------------
64
- r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
65
- r.high = 0x7FFF;
66
-#else
67
- /* X86 */
68
- r.low = UINT64_C(0xC000000000000000);
69
- r.high = 0xFFFF;
70
-#endif
71
+ r.high = 0x7FFF | (p64.sign << 15);
72
+ r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac;
73
return r;
74
}
43
75
44
--
76
--
45
2.20.1
77
2.34.1
46
47
diff view generated by jsdifflib
New patch
[PULL 34/72] target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
1
In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass
2
a zero-initialized float_status struct to float32_is_quiet_nan() and
3
float64_is_quiet_nan(), with the cryptic comment "for
4
snan_bit_is_one".
1
5
6
This pattern appears to have been copied from target/riscv, where it
7
is used because the functions there do not have ready access to the
8
CPU state struct. The comment presumably refers to the fact that the
9
main reason the is_quiet_nan() functions want the float_state is
10
because they want to know about the snan_bit_is_one config.
11
12
In the loongarch helpers, though, we have the CPU state struct
13
to hand. Use the usual env->fp_status here. This avoids our needing
14
to track that we need to update the initializer of the local
15
float_status structs when the core softfloat code adds new
16
options for targets to configure their behaviour.
17
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20241202131347.498124-30-peter.maydell@linaro.org
21
---
22
target/loongarch/tcg/fpu_helper.c | 6 ++----
23
1 file changed, 2 insertions(+), 4 deletions(-)
24
25
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/loongarch/tcg/fpu_helper.c
28
+++ b/target/loongarch/tcg/fpu_helper.c
29
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj)
30
} else if (float32_is_zero_or_denormal(f)) {
31
return sign ? 1 << 4 : 1 << 8;
32
} else if (float32_is_any_nan(f)) {
33
- float_status s = { }; /* for snan_bit_is_one */
34
- return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
35
+ return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
36
} else {
37
return sign ? 1 << 3 : 1 << 7;
38
}
39
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj)
40
} else if (float64_is_zero_or_denormal(f)) {
41
return sign ? 1 << 4 : 1 << 8;
42
} else if (float64_is_any_nan(f)) {
43
- float_status s = { }; /* for snan_bit_is_one */
44
- return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
45
+ return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
46
} else {
47
return sign ? 1 << 3 : 1 << 7;
48
}
49
--
50
2.34.1
diff view generated by jsdifflib
New patch
[PULL 35/72] target/m68k: In frem helper, initialize local float_status from env->fp_status
1
In the frem helper, we have a local float_status because we want to
2
execute the floatx80_div() with a custom rounding mode. Instead of
3
zero-initializing the local float_status and then having to set it up
4
with the m68k standard behaviour (including the NaN propagation rule
5
and copying the rounding precision from env->fp_status), initialize
6
it as a complete copy of env->fp_status. This will avoid our having
7
to add new code in this function for every new config knob we add
8
to fp_status.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-31-peter.maydell@linaro.org
13
---
14
target/m68k/fpu_helper.c | 6 ++----
15
1 file changed, 2 insertions(+), 4 deletions(-)
16
17
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/m68k/fpu_helper.c
20
+++ b/target/m68k/fpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
22
23
fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status);
24
if (!floatx80_is_any_nan(fp_rem)) {
25
- float_status fp_status = { };
26
+ /* Use local temporary fp_status to set different rounding mode */
27
+ float_status fp_status = env->fp_status;
28
uint32_t quotient;
29
int sign;
30
31
/* Calculate quotient directly using round to nearest mode */
32
- set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status);
33
set_float_rounding_mode(float_round_nearest_even, &fp_status);
34
- set_floatx80_rounding_precision(
35
- get_floatx80_rounding_precision(&env->fp_status), &fp_status);
36
fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status);
37
38
sign = extractFloatx80Sign(fp_quot.d);
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 36/72] target/m68k: Init local float_status from env fp_status in gdb get/set reg
1
In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion
2
from float64 to floatx80 using a scratch float_status, because we
3
don't want the conversion to affect the CPU's floating point exception
4
status. Currently we use a zero-initialized float_status. This will
5
get steadily more awkward as we add config knobs to float_status
6
that the target must initialize. Avoid having to add any of that
7
configuration here by instead initializing our local float_status
8
from the env->fp_status.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-32-peter.maydell@linaro.org
13
---
14
target/m68k/helper.c | 6 ++++--
15
1 file changed, 4 insertions(+), 2 deletions(-)
16
17
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/m68k/helper.c
20
+++ b/target/m68k/helper.c
21
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n)
22
CPUM68KState *env = &cpu->env;
23
24
if (n < 8) {
25
- float_status s = {};
26
+ /* Use scratch float_status so any exceptions don't change CPU state */
27
+ float_status s = env->fp_status;
28
return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s));
29
}
30
switch (n) {
31
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n)
32
CPUM68KState *env = &cpu->env;
33
34
if (n < 8) {
35
- float_status s = {};
36
+ /* Use scratch float_status so any exceptions don't change CPU state */
37
+ float_status s = env->fp_status;
38
env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s);
39
return 8;
40
}
41
--
42
2.34.1
diff view generated by jsdifflib
[PULL 22/34] hw/misc/max111x: provide QOM properties for setting initial values
[PULL 37/72] target/sparc: Initialize local scratch float_status from env->fp_status
1
Add some QOM properties to the max111x ADC device to allow the
1
In the helper functions flcmps and flcmpd we use a scratch float_status
2
initial values to be configured. Currently this is done by
2
so that we don't change the CPU state if the comparison raises any
3
board code calling max111x_set_input() after it creates the
3
floating point exception flags. Instead of zero-initializing this
4
device, which doesn't work on system reset.
4
scratch float_status, initialize it as a copy of env->fp_status. This
5
avoids the need to explicitly initialize settings like the NaN
6
propagation rule or others we might add to softfloat in future.
5
7
6
This requires us to implement a reset method for this device,
8
To do this we need to pass the CPU env pointer in to the helper.
7
so while we're doing that make sure we reset the other parts
8
of the device state.
9
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-id: 20241202131347.498124-33-peter.maydell@linaro.org
13
Message-id: 20200628142429.17111-7-peter.maydell@linaro.org
14
---
13
---
15
hw/misc/max111x.c | 57 ++++++++++++++++++++++++++++++++++++++---------
14
target/sparc/helper.h | 4 ++--
16
1 file changed, 47 insertions(+), 10 deletions(-)
15
target/sparc/fop_helper.c | 8 ++++----
16
target/sparc/translate.c | 4 ++--
17
3 files changed, 8 insertions(+), 8 deletions(-)
17
18
18
diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
19
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
19
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/misc/max111x.c
21
--- a/target/sparc/helper.h
21
+++ b/hw/misc/max111x.c
22
+++ b/target/sparc/helper.h
22
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64)
23
#include "hw/ssi/ssi.h"
24
DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64)
24
#include "migration/vmstate.h"
25
DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128)
25
#include "qemu/module.h"
26
DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128)
26
+#include "hw/qdev-properties.h"
27
-DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32)
27
28
-DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64)
28
typedef struct {
29
+DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32)
29
SSISlave parent_obj;
30
+DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64)
30
31
DEF_HELPER_2(raise_exception, noreturn, env, int)
31
qemu_irq interrupt;
32
32
+ /* Values of inputs at system reset (settable by QOM property) */
33
DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64)
33
+ uint8_t reset_input[8];
34
diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c
34
+
35
index XXXXXXX..XXXXXXX 100644
35
uint8_t tb1, rb2, rb3;
36
--- a/target/sparc/fop_helper.c
36
int cycle;
37
+++ b/target/sparc/fop_helper.c
37
38
@@ -XXX,XX +XXX,XX @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2)
38
@@ -XXX,XX +XXX,XX @@ static int max111x_init(SSISlave *d, int inputs)
39
return finish_fcmp(env, r, GETPC());
39
qdev_init_gpio_out(dev, &s->interrupt, 1);
40
41
s->inputs = inputs;
42
- /* TODO: add a user interface for setting these */
43
- s->input[0] = 0xf0;
44
- s->input[1] = 0xe0;
45
- s->input[2] = 0xd0;
46
- s->input[3] = 0xc0;
47
- s->input[4] = 0xb0;
48
- s->input[5] = 0xa0;
49
- s->input[6] = 0x90;
50
- s->input[7] = 0x80;
51
- s->com = 0;
52
53
vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY,
54
&vmstate_max111x, s);
55
@@ -XXX,XX +XXX,XX @@ void max111x_set_input(DeviceState *dev, int line, uint8_t value)
56
s->input[line] = value;
57
}
40
}
58
41
59
+static void max111x_reset(DeviceState *dev)
42
-uint32_t helper_flcmps(float32 src1, float32 src2)
60
+{
43
+uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2)
61
+ MAX111xState *s = MAX_111X(dev);
62
+ int i;
63
+
64
+ for (i = 0; i < s->inputs; i++) {
65
+ s->input[i] = s->reset_input[i];
66
+ }
67
+ s->com = 0;
68
+ s->tb1 = 0;
69
+ s->rb2 = 0;
70
+ s->rb3 = 0;
71
+ s->cycle = 0;
72
+}
73
+
74
+static Property max1110_properties[] = {
75
+ /* Reset values for ADC inputs */
76
+ DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0),
77
+ DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0),
78
+ DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0),
79
+ DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0),
80
+ DEFINE_PROP_END_OF_LIST(),
81
+};
82
+
83
+static Property max1111_properties[] = {
84
+ /* Reset values for ADC inputs */
85
+ DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0),
86
+ DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0),
87
+ DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0),
88
+ DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0),
89
+ DEFINE_PROP_UINT8("input4", MAX111xState, reset_input[4], 0xb0),
90
+ DEFINE_PROP_UINT8("input5", MAX111xState, reset_input[5], 0xa0),
91
+ DEFINE_PROP_UINT8("input6", MAX111xState, reset_input[6], 0x90),
92
+ DEFINE_PROP_UINT8("input7", MAX111xState, reset_input[7], 0x80),
93
+ DEFINE_PROP_END_OF_LIST(),
94
+};
95
+
96
static void max111x_class_init(ObjectClass *klass, void *data)
97
{
44
{
98
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
45
/*
99
+ DeviceClass *dc = DEVICE_CLASS(klass);
46
* FLCMP never raises an exception nor modifies any FSR fields.
100
47
* Perform the comparison with a dummy fp environment.
101
k->transfer = max111x_transfer;
48
*/
102
+ dc->reset = max111x_reset;
49
- float_status discard = { };
50
+ float_status discard = env->fp_status;
51
FloatRelation r;
52
53
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
54
@@ -XXX,XX +XXX,XX @@ uint32_t helper_flcmps(float32 src1, float32 src2)
55
g_assert_not_reached();
103
}
56
}
104
57
105
static const TypeInfo max111x_info = {
58
-uint32_t helper_flcmpd(float64 src1, float64 src2)
106
@@ -XXX,XX +XXX,XX @@ static const TypeInfo max111x_info = {
59
+uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2)
107
static void max1110_class_init(ObjectClass *klass, void *data)
108
{
60
{
109
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
61
- float_status discard = { };
110
+ DeviceClass *dc = DEVICE_CLASS(klass);
62
+ float_status discard = env->fp_status;
111
63
FloatRelation r;
112
k->realize = max1110_realize;
64
113
+ device_class_set_props(dc, max1110_properties);
65
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
66
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/sparc/translate.c
69
+++ b/target/sparc/translate.c
70
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a)
71
72
src1 = gen_load_fpr_F(dc, a->rs1);
73
src2 = gen_load_fpr_F(dc, a->rs2);
74
- gen_helper_flcmps(cpu_fcc[a->cc], src1, src2);
75
+ gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2);
76
return advance_pc(dc);
114
}
77
}
115
78
116
static const TypeInfo max1110_info = {
79
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a)
117
@@ -XXX,XX +XXX,XX @@ static const TypeInfo max1110_info = {
80
118
static void max1111_class_init(ObjectClass *klass, void *data)
81
src1 = gen_load_fpr_D(dc, a->rs1);
119
{
82
src2 = gen_load_fpr_D(dc, a->rs2);
120
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
83
- gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2);
121
+ DeviceClass *dc = DEVICE_CLASS(klass);
84
+ gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2);
122
85
return advance_pc(dc);
123
k->realize = max1111_realize;
124
+ device_class_set_props(dc, max1111_properties);
125
}
86
}
126
87
127
static const TypeInfo max1111_info = {
128
--
88
--
129
2.20.1
89
2.34.1
130
131
diff view generated by jsdifflib
New patch
[PULL 38/72] target/ppc: Use env->fp_status in helper_compute_fprf functions
1
In the helper_compute_fprf functions, we pass a dummy float_status
2
in to the is_signaling_nan() function. This is unnecessary, because
3
we have convenient access to the CPU env pointer here and that
4
is already set up with the correct values for the snan_bit_is_one
5
and no_signaling_nans config settings. is_signaling_nan() doesn't
6
ever update the fp_status with any exception flags, so there is
7
no reason not to use env->fp_status here.
1
8
9
Use env->fp_status instead of the dummy fp_status.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20241202131347.498124-34-peter.maydell@linaro.org
14
---
15
target/ppc/fpu_helper.c | 3 +--
16
1 file changed, 1 insertion(+), 2 deletions(-)
17
18
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/ppc/fpu_helper.c
21
+++ b/target/ppc/fpu_helper.c
22
@@ -XXX,XX +XXX,XX @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
23
} else if (tp##_is_infinity(arg)) { \
24
fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \
25
} else { \
26
- float_status dummy = { }; /* snan_bit_is_one = 0 */ \
27
- if (tp##_is_signaling_nan(arg, &dummy)) { \
28
+ if (tp##_is_signaling_nan(arg, &env->fp_status)) { \
29
fprf = 0x00 << FPSCR_FPRF; \
30
} else { \
31
fprf = 0x11 << FPSCR_FPRF; \
32
--
33
2.34.1
diff view generated by jsdifflib
[PULL 13/34] hw/arm/virt-acpi-build: Only expose flash on older machine types
[PULL 39/72] target/arm: Copy entire float_status in is_ebf
1
From: Andrew Jones <drjones@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The flash device is exclusively for the host-controlled firmware, so
3
Now that float_status has a bunch of fp parameters,
4
we should not expose it to the OS. Exposing it risks the OS messing
4
it is easier to copy an existing structure than create
5
with it, which could break firmware runtime services and surprise the
5
one from scratch. Begin by copying the structure that
6
OS when all its changes disappear after reboot.
6
corresponds to the FPSR and make only the adjustments
7
required for BFloat16 semantics.
7
8
8
As firmware needs the device and uses DT, we leave the device exposed
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
there. It's up to firmware to remove the nodes from DT before sending
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
it on to the OS. However, there's no need to force firmware to remove
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
tables from ACPI (which it doesn't know how to do anyway), so we
12
Message-id: 20241203203949.483774-2-richard.henderson@linaro.org
12
simply don't add the tables in the first place. But, as we've been
13
adding the tables for quite some time and don't want to change the
14
default hardware exposed to versioned machines, then we only stop
15
exposing the flash device tables for 5.1 and later machine types.
16
17
Suggested-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
18
Suggested-by: Laszlo Ersek <lersek@redhat.com>
19
Signed-off-by: Andrew Jones <drjones@redhat.com>
20
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
21
Reviewed-by: Eric Auger <eric.auger@redhat.com>
22
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
23
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
24
Message-id: 20200629140938.17566-4-drjones@redhat.com
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
---
14
---
27
include/hw/arm/virt.h | 1 +
15
target/arm/tcg/vec_helper.c | 20 +++++++-------------
28
hw/arm/virt-acpi-build.c | 5 ++++-
16
1 file changed, 7 insertions(+), 13 deletions(-)
29
hw/arm/virt.c | 3 +++
30
3 files changed, 8 insertions(+), 1 deletion(-)
31
17
32
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
18
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
33
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
34
--- a/include/hw/arm/virt.h
20
--- a/target/arm/tcg/vec_helper.c
35
+++ b/include/hw/arm/virt.h
21
+++ b/target/arm/tcg/vec_helper.c
36
@@ -XXX,XX +XXX,XX @@ typedef struct {
22
@@ -XXX,XX +XXX,XX @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp)
37
bool no_highmem_ecam;
23
* no effect on AArch32 instructions.
38
bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */
24
*/
39
bool kvm_no_adjvtime;
25
bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF;
40
+ bool acpi_expose_flash;
26
- *statusp = (float_status){
41
} VirtMachineClass;
27
- .tininess_before_rounding = float_tininess_before_rounding,
42
28
- .float_rounding_mode = float_round_to_odd_inf,
43
typedef struct {
29
- .flush_to_zero = true,
44
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
30
- .flush_inputs_to_zero = true,
45
index XXXXXXX..XXXXXXX 100644
31
- .default_nan_mode = true,
46
--- a/hw/arm/virt-acpi-build.c
32
- };
47
+++ b/hw/arm/virt-acpi-build.c
48
@@ -XXX,XX +XXX,XX @@ static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker,
49
static void
50
build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
51
{
52
+ VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
53
Aml *scope, *dsdt;
54
MachineState *ms = MACHINE(vms);
55
const MemMapEntry *memmap = vms->memmap;
56
@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
57
acpi_dsdt_add_cpus(scope, vms->smp_cpus);
58
acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
59
(irqmap[VIRT_UART] + ARM_SPI_BASE));
60
- acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
61
+ if (vmc->acpi_expose_flash) {
62
+ acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
63
+ }
64
acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
65
acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
66
(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
67
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/hw/arm/virt.c
70
+++ b/hw/arm/virt.c
71
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 1)
72
73
static void virt_machine_5_0_options(MachineClass *mc)
74
{
75
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
76
+
33
+
77
virt_machine_5_1_options(mc);
34
+ *statusp = env->vfp.fp_status;
78
compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
35
+ set_default_nan_mode(true, statusp);
79
mc->numa_mem_supported = true;
36
80
+ vmc->acpi_expose_flash = true;
37
if (ebf) {
38
- float_status *fpst = &env->vfp.fp_status;
39
- set_flush_to_zero(get_flush_to_zero(fpst), statusp);
40
- set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp);
41
- set_float_rounding_mode(get_float_rounding_mode(fpst), statusp);
42
-
43
/* EBF=1 needs to do a step with round-to-odd semantics */
44
*oddstatusp = *statusp;
45
set_float_rounding_mode(float_round_to_odd, oddstatusp);
46
+ } else {
47
+ set_flush_to_zero(true, statusp);
48
+ set_flush_inputs_to_zero(true, statusp);
49
+ set_float_rounding_mode(float_round_to_odd_inf, statusp);
50
}
51
-
52
return ebf;
81
}
53
}
82
DEFINE_VIRT_MACHINE(5, 0)
83
54
84
--
55
--
85
2.20.1
56
2.34.1
86
57
87
58
diff view generated by jsdifflib
[PULL 26/34] hw/misc/max111x: Use GPIO lines rather than max111x_set_input()
[PULL 40/72] fpu: Allow runtime choice of default NaN value
1
The max111x ADC device model allows other code to set the level on
1
Currently we hardcode the default NaN value in parts64_default_nan()
2
the 8 ADC inputs using the max111x_set_input() function. Replace
2
using a compile-time ifdef ladder. This is awkward for two cases:
3
this with generic qdev GPIO inputs, which also allow inputs to be set
3
* for single-QEMU-binary we can't hard-code target-specifics like this
4
to arbitrary values.
4
* for Arm FEAT_AFP the default NaN value depends on FPCR.AH
5
(specifically the sign bit is different)
5
6
6
Using GPIO lines will make it easier for board code to wire things
7
Add a field to float_status to specify the default NaN value; fall
7
up, so that if device A wants to set the ADC input it doesn't need to
8
back to the old ifdef behaviour if these are not set.
8
have a direct pointer to the max111x but can just set that value on
9
9
its output GPIO, which is then wired up by the board to the
10
The default NaN value is specified by setting a uint8_t to a
10
appropriate max111x input.
11
pattern corresponding to the sign and upper fraction parts of
12
the NaN; the lower bits of the fraction are set from bit 0 of
13
the pattern.
11
14
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20200628142429.17111-11-peter.maydell@linaro.org
17
Message-id: 20241202131347.498124-35-peter.maydell@linaro.org
15
---
18
---
16
include/hw/ssi/ssi.h | 3 ---
19
include/fpu/softfloat-helpers.h | 11 +++++++
17
hw/arm/spitz.c | 9 +++++----
20
include/fpu/softfloat-types.h | 10 ++++++
18
hw/misc/max111x.c | 16 +++++++++-------
21
fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++-------------
19
3 files changed, 14 insertions(+), 14 deletions(-)
22
3 files changed, 54 insertions(+), 22 deletions(-)
20
23
21
diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
24
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
22
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/ssi/ssi.h
26
--- a/include/fpu/softfloat-helpers.h
24
+++ b/include/hw/ssi/ssi.h
27
+++ b/include/fpu/softfloat-helpers.h
25
@@ -XXX,XX +XXX,XX @@ SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
28
@@ -XXX,XX +XXX,XX @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
26
29
status->float_infzeronan_rule = rule;
27
uint32_t ssi_transfer(SSIBus *bus, uint32_t val);
28
29
-/* max111x.c */
30
-void max111x_set_input(DeviceState *dev, int line, uint8_t value);
31
-
32
#endif
33
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/arm/spitz.c
36
+++ b/hw/arm/spitz.c
37
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
38
39
static void spitz_adc_temp_on(void *opaque, int line, int level)
40
{
41
+ int batt_temp;
42
+
43
if (!max1111)
44
return;
45
46
- if (level)
47
- max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
48
- else
49
- max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
50
+ batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
51
+
52
+ qemu_set_irq(qdev_get_gpio_in(max1111, MAX1111_BATT_TEMP), batt_temp);
53
}
30
}
54
31
55
static void corgi_ssp_realize(SSISlave *d, Error **errp)
32
+static inline void set_float_default_nan_pattern(uint8_t dnan_pattern,
56
diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
33
+ float_status *status)
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/misc/max111x.c
59
+++ b/hw/misc/max111x.c
60
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_max111x = {
61
}
62
};
63
64
+static void max111x_input_set(void *opaque, int line, int value)
65
+{
34
+{
66
+ MAX111xState *s = MAX_111X(opaque);
35
+ status->default_nan_pattern = dnan_pattern;
67
+
68
+ assert(line >= 0 && line < s->inputs);
69
+ s->input[line] = value;
70
+}
36
+}
71
+
37
+
72
static int max111x_init(SSISlave *d, int inputs)
38
static inline void set_flush_to_zero(bool val, float_status *status)
73
{
39
{
74
DeviceState *dev = DEVICE(d);
40
status->flush_to_zero = val;
75
MAX111xState *s = MAX_111X(dev);
41
@@ -XXX,XX +XXX,XX @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status
76
42
return status->float_infzeronan_rule;
77
qdev_init_gpio_out(dev, &s->interrupt, 1);
78
+ qdev_init_gpio_in(dev, max111x_input_set, inputs);
79
80
s->inputs = inputs;
81
82
@@ -XXX,XX +XXX,XX @@ static void max1111_realize(SSISlave *dev, Error **errp)
83
max111x_init(dev, 4);
84
}
43
}
85
44
86
-void max111x_set_input(DeviceState *dev, int line, uint8_t value)
45
+static inline uint8_t get_float_default_nan_pattern(float_status *status)
87
-{
46
+{
88
- MAX111xState *s = MAX_111X(dev);
47
+ return status->default_nan_pattern;
89
- assert(line >= 0 && line < s->inputs);
48
+}
90
- s->input[line] = value;
49
+
91
-}
50
static inline bool get_flush_to_zero(float_status *status)
92
-
93
static void max111x_reset(DeviceState *dev)
94
{
51
{
95
MAX111xState *s = MAX_111X(dev);
52
return status->flush_to_zero;
53
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
54
index XXXXXXX..XXXXXXX 100644
55
--- a/include/fpu/softfloat-types.h
56
+++ b/include/fpu/softfloat-types.h
57
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
58
/* should denormalised inputs go to zero and set the input_denormal flag? */
59
bool flush_inputs_to_zero;
60
bool default_nan_mode;
61
+ /*
62
+ * The pattern to use for the default NaN. Here the high bit specifies
63
+ * the default NaN's sign bit, and bits 6..0 specify the high bits of the
64
+ * fractional part. The low bits of the fractional part are copies of bit 0.
65
+ * The exponent of the default NaN is (as for any NaN) always all 1s.
66
+ * Note that a value of 0 here is not a valid NaN. The target must set
67
+ * this to the correct non-zero value, or we will assert when trying to
68
+ * create a default NaN.
69
+ */
70
+ uint8_t default_nan_pattern;
71
/*
72
* The flags below are not used on all specializations and may
73
* constant fold away (see snan_bit_is_one()/no_signalling_nans() in
74
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
75
index XXXXXXX..XXXXXXX 100644
76
--- a/fpu/softfloat-specialize.c.inc
77
+++ b/fpu/softfloat-specialize.c.inc
78
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
79
{
80
bool sign = 0;
81
uint64_t frac;
82
+ uint8_t dnan_pattern = status->default_nan_pattern;
83
84
+ if (dnan_pattern == 0) {
85
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
86
- /* !snan_bit_is_one, set all bits */
87
- frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
88
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
89
+ /* Sign bit clear, all frac bits set */
90
+ dnan_pattern = 0b01111111;
91
+#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
92
|| defined(TARGET_MICROBLAZE)
93
- /* !snan_bit_is_one, set sign and msb */
94
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
95
- sign = 1;
96
+ /* Sign bit set, most significant frac bit set */
97
+ dnan_pattern = 0b11000000;
98
#elif defined(TARGET_HPPA)
99
- /* snan_bit_is_one, set msb-1. */
100
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
101
+ /* Sign bit clear, msb-1 frac bit set */
102
+ dnan_pattern = 0b00100000;
103
#elif defined(TARGET_HEXAGON)
104
- sign = 1;
105
- frac = ~0ULL;
106
+ /* Sign bit set, all frac bits set. */
107
+ dnan_pattern = 0b11111111;
108
#else
109
- /*
110
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
111
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
112
- * do not have floating-point.
113
- */
114
- if (snan_bit_is_one(status)) {
115
- /* set all bits other than msb */
116
- frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
117
- } else {
118
- /* set msb */
119
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
120
- }
121
+ /*
122
+ * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
123
+ * S390, SH4, TriCore, and Xtensa. Our other supported targets
124
+ * do not have floating-point.
125
+ */
126
+ if (snan_bit_is_one(status)) {
127
+ /* sign bit clear, set all frac bits other than msb */
128
+ dnan_pattern = 0b00111111;
129
+ } else {
130
+ /* sign bit clear, set frac msb */
131
+ dnan_pattern = 0b01000000;
132
+ }
133
#endif
134
+ }
135
+ assert(dnan_pattern != 0);
136
+
137
+ sign = dnan_pattern >> 7;
138
+ /*
139
+ * Place default_nan_pattern [6:0] into bits [62:56],
140
+ * and replecate bit [0] down into [55:0]
141
+ */
142
+ frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern);
143
+ frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1));
144
145
*p = (FloatParts64) {
146
.cls = float_class_qnan,
96
--
147
--
97
2.20.1
148
2.34.1
98
99
diff view generated by jsdifflib
New patch
[PULL 41/72] tests/fp: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the tests/fp code.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-36-peter.maydell@linaro.org
6
---
7
tests/fp/fp-bench.c | 1 +
8
tests/fp/fp-test-log2.c | 1 +
9
tests/fp/fp-test.c | 1 +
10
3 files changed, 3 insertions(+)
11
12
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tests/fp/fp-bench.c
15
+++ b/tests/fp/fp-bench.c
16
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
17
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
18
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
19
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
20
+ set_float_default_nan_pattern(0b01000000, &soft_status);
21
22
f = bench_funcs[operation][precision];
23
g_assert(f);
24
diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/tests/fp/fp-test-log2.c
27
+++ b/tests/fp/fp-test-log2.c
28
@@ -XXX,XX +XXX,XX @@ int main(int ac, char **av)
29
int i;
30
31
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
32
+ set_float_default_nan_pattern(0b01000000, &qsf);
33
set_float_rounding_mode(float_round_nearest_even, &qsf);
34
35
test.d = 0.0;
36
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/tests/fp/fp-test.c
39
+++ b/tests/fp/fp-test.c
40
@@ -XXX,XX +XXX,XX @@ void run_test(void)
41
*/
42
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
43
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
44
+ set_float_default_nan_pattern(0b01000000, &qsf);
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
46
47
genCases_setLevel(test_level);
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 42/72] target/microblaze: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-37-peter.maydell@linaro.org
7
---
8
target/microblaze/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/microblaze/cpu.c
15
+++ b/target/microblaze/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj, ResetType type)
17
* this architecture.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
23
#if defined(CONFIG_USER_ONLY)
24
/* start in user mode with interrupts enabled. */
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
34
- || defined(TARGET_MICROBLAZE)
35
+#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
/* Sign bit set, most significant frac bit set */
37
dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 43/72] target/i386: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-38-peter.maydell@linaro.org
7
---
8
target/i386/tcg/fpu_helper.c | 4 ++++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 4 insertions(+), 3 deletions(-)
11
12
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/i386/tcg/fpu_helper.c
15
+++ b/target/i386/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
17
*/
18
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
19
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
+ set_float_default_nan_pattern(0b11000000, &env->mmx_status);
23
+ set_float_default_nan_pattern(0b11000000, &env->sse_status);
24
}
25
26
static inline uint8_t save_exception_flags(CPUX86State *env)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
32
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
/* Sign bit clear, all frac bits set */
34
dnan_pattern = 0b01111111;
35
-#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
- /* Sign bit set, most significant frac bit set */
37
- dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
/* Sign bit clear, msb-1 frac bit set */
40
dnan_pattern = 0b00100000;
41
--
42
2.34.1
diff view generated by jsdifflib
New patch
[PULL 44/72] target/hppa: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-39-peter.maydell@linaro.org
7
---
8
target/hppa/fpu_helper.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 2 insertions(+), 3 deletions(-)
11
12
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/hppa/fpu_helper.c
15
+++ b/target/hppa/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
17
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN: sign bit clear, msb-1 frac bit set */
21
+ set_float_default_nan_pattern(0b00100000, &env->fp_status);
22
}
23
24
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_HPPA)
34
- /* Sign bit clear, msb-1 frac bit set */
35
- dnan_pattern = 0b00100000;
36
#elif defined(TARGET_HEXAGON)
37
/* Sign bit set, all frac bits set. */
38
dnan_pattern = 0b11111111;
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 45/72] target/alpha: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the alpha target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-40-peter.maydell@linaro.org
6
---
7
target/alpha/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/alpha/cpu.c
13
+++ b/target/alpha/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj)
15
* operand in Fa. That is float_2nan_prop_ba.
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
18
+ /* Default NaN: sign bit clear, msb frac bit set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
#if defined(CONFIG_USER_ONLY)
21
env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
22
cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD
23
--
24
2.34.1
diff view generated by jsdifflib
[PULL 23/34] hw/misc/max111x: Don't use vmstate_register()
[PULL 46/72] target/arm: Set default NaN pattern explicitly
1
The max111x is a proper qdev device; we can use dc->vmsd rather than
1
Set the default NaN pattern explicitly for the arm target.
2
directly calling vmstate_register().
2
This includes setting it for the old linux-user nwfpe emulation.
3
3
For nwfpe, our default doesn't match the real kernel, but we
4
It's possible that this is a migration compat break, but the only
4
avoid making a behaviour change in this commit.
5
boards that use this device are the spitz-family ('akita', 'borzoi',
6
'spitz', 'terrier').
7
5
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20241202131347.498124-41-peter.maydell@linaro.org
11
Message-id: 20200628142429.17111-8-peter.maydell@linaro.org
12
---
9
---
13
hw/misc/max111x.c | 3 +--
10
linux-user/arm/nwfpe/fpa11.c | 5 +++++
14
1 file changed, 1 insertion(+), 2 deletions(-)
11
target/arm/cpu.c | 2 ++
12
2 files changed, 7 insertions(+)
15
13
16
diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
14
diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/misc/max111x.c
16
--- a/linux-user/arm/nwfpe/fpa11.c
19
+++ b/hw/misc/max111x.c
17
+++ b/linux-user/arm/nwfpe/fpa11.c
20
@@ -XXX,XX +XXX,XX @@ static int max111x_init(SSISlave *d, int inputs)
18
@@ -XXX,XX +XXX,XX @@ void resetFPA11(void)
21
19
* this late date.
22
s->inputs = inputs;
20
*/
23
21
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status);
24
- vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY,
22
+ /*
25
- &vmstate_max111x, s);
23
+ * Use the same default NaN value as Arm VFP. This doesn't match
26
return 0;
24
+ * the Linux kernel's nwfpe emulation, which uses an all-1s value.
25
+ */
26
+ set_float_default_nan_pattern(0b01000000, &fpa11->fp_status);
27
}
27
}
28
28
29
@@ -XXX,XX +XXX,XX @@ static void max111x_class_init(ObjectClass *klass, void *data)
29
void SetRoundingMode(const unsigned int opcode)
30
30
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
31
k->transfer = max111x_transfer;
31
index XXXXXXX..XXXXXXX 100644
32
dc->reset = max111x_reset;
32
--- a/target/arm/cpu.c
33
+ dc->vmsd = &vmstate_max111x;
33
+++ b/target/arm/cpu.c
34
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
35
* the pseudocode function the arguments are in the order c, a, b.
36
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
37
* and the input NaN if it is signalling
38
+ * * Default NaN has sign bit clear, msb frac bit set
39
*/
40
static void arm_set_default_fp_behaviours(float_status *s)
41
{
42
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
44
set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
46
+ set_float_default_nan_pattern(0b01000000, s);
34
}
47
}
35
48
36
static const TypeInfo max111x_info = {
49
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
37
--
50
--
38
2.20.1
51
2.34.1
39
40
diff view generated by jsdifflib
New patch
[PULL 47/72] target/loongarch: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for loongarch.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-42-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/loongarch/tcg/fpu_helper.c
13
+++ b/target/loongarch/tcg/fpu_helper.c
14
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
15
*/
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
17
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
18
+ /* Default NaN: sign bit clear, msb frac bit set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
}
21
22
int ieee_ex_to_loongarch(int xcpt)
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 48/72] target/m68k: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for m68k.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-43-peter.maydell@linaro.org
6
---
7
target/m68k/cpu.c | 2 ++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 3 insertions(+), 1 deletion(-)
10
11
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/m68k/cpu.c
14
+++ b/target/m68k/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
16
* preceding paragraph for nonsignaling NaNs.
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
+ /* Default NaN: sign bit clear, all frac bits set */
20
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
21
22
nan = floatx80_default_nan(&env->fp_status);
23
for (i = 0; i < 8; i++) {
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
29
uint8_t dnan_pattern = status->default_nan_pattern;
30
31
if (dnan_pattern == 0) {
32
-#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
+#if defined(TARGET_SPARC)
34
/* Sign bit clear, all frac bits set */
35
dnan_pattern = 0b01111111;
36
#elif defined(TARGET_HEXAGON)
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 49/72] target/mips: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for MIPS. Note that this
2
is our only target which currently changes the default NaN
3
at runtime (which it was previously doing indirectly when it
4
changed the snan_bit_is_one setting).
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-44-peter.maydell@linaro.org
9
---
10
target/mips/fpu_helper.h | 7 +++++++
11
target/mips/msa.c | 3 +++
12
2 files changed, 10 insertions(+)
13
14
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/mips/fpu_helper.h
17
+++ b/target/mips/fpu_helper.h
18
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
19
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
20
nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
21
set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
22
+ /*
23
+ * With nan2008, the default NaN value has the sign bit clear and the
24
+ * frac msb set; with the older mode, the sign bit is clear, and all
25
+ * frac bits except the msb are set.
26
+ */
27
+ set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111,
28
+ &env->active_fpu.fp_status);
29
30
}
31
32
diff --git a/target/mips/msa.c b/target/mips/msa.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/mips/msa.c
35
+++ b/target/mips/msa.c
36
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
37
/* Inf * 0 + NaN returns the input NaN */
38
set_float_infzeronan_rule(float_infzeronan_dnan_never,
39
&env->active_tc.msa_fp_status);
40
+ /* Default NaN: sign bit clear, frac msb set */
41
+ set_float_default_nan_pattern(0b01000000,
42
+ &env->active_tc.msa_fp_status);
43
}
44
--
45
2.34.1
diff view generated by jsdifflib
New patch
[PULL 50/72] target/openrisc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for openrisc.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-45-peter.maydell@linaro.org
6
---
7
target/openrisc/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/openrisc/cpu.c
13
+++ b/target/openrisc/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type)
15
*/
16
set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status);
17
18
+ /* Default NaN: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status);
20
21
#ifndef CONFIG_USER_ONLY
22
cpu->env.picmr = 0x00000000;
23
--
24
2.34.1
diff view generated by jsdifflib
[PULL 16/34] hw/display/bcm2835_fb.c: Initialize all fields of struct
[PULL 51/72] target/ppc: Set default NaN pattern explicitly
1
In bcm2835_fb_mbox_push(), Coverity complains (CID 1429989) that we
1
Set the default NaN pattern explicitly for ppc.
2
pass a pointer to a local struct to another function without
3
initializing all its fields. This is a real bug:
4
bcm2835_fb_reconfigure() copies the whole of our new BCM2385FBConfig
5
struct into s->config, so any fields we don't initialize will corrupt
6
the state of the device.
7
2
8
Copy the two fields which we don't want to update (pixo and alpha)
9
from the existing config so we don't accidentally change them.
10
11
Fixes: cfb7ba983857e40e88
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20200628195436.27582-1-peter.maydell@linaro.org
5
Message-id: 20241202131347.498124-46-peter.maydell@linaro.org
15
---
6
---
16
hw/display/bcm2835_fb.c | 4 ++++
7
target/ppc/cpu_init.c | 4 ++++
17
1 file changed, 4 insertions(+)
8
1 file changed, 4 insertions(+)
18
9
19
diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c
10
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
20
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/display/bcm2835_fb.c
12
--- a/target/ppc/cpu_init.c
22
+++ b/hw/display/bcm2835_fb.c
13
+++ b/target/ppc/cpu_init.c
23
@@ -XXX,XX +XXX,XX @@ static void bcm2835_fb_mbox_push(BCM2835FBState *s, uint32_t value)
14
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
24
newconf.base = s->vcram_base | (value & 0xc0000000);
15
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
25
newconf.base += BCM2835_FB_OFFSET;
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
26
17
27
+ /* Copy fields which we don't want to change from the existing config */
18
+ /* Default NaN: sign bit clear, set frac msb */
28
+ newconf.pixo = s->config.pixo;
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
29
+ newconf.alpha = s->config.alpha;
20
+ set_float_default_nan_pattern(0b01000000, &env->vec_status);
30
+
21
+
31
bcm2835_fb_validate_config(&newconf);
22
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
32
23
ppc_spr_t *spr = &env->spr_cb[i];
33
pitch = bcm2835_fb_get_pitch(&newconf);
24
34
--
25
--
35
2.20.1
26
2.34.1
36
37
diff view generated by jsdifflib
New patch
[PULL 52/72] target/sh4: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for sh4. Note that sh4
2
is one of the only three targets (the others being HPPA and
3
sometimes MIPS) that has snan_bit_is_one set.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-47-peter.maydell@linaro.org
8
---
9
target/sh4/cpu.c | 2 ++
10
1 file changed, 2 insertions(+)
11
12
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sh4/cpu.c
15
+++ b/target/sh4/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
17
set_flush_to_zero(1, &env->fp_status);
18
#endif
19
set_default_nan_mode(1, &env->fp_status);
20
+ /* sign bit clear, set all frac bits other than msb */
21
+ set_float_default_nan_pattern(0b00111111, &env->fp_status);
22
}
23
24
static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
25
--
26
2.34.1
diff view generated by jsdifflib
[PULL 33/34] Replace uses of FROM_SSI_SLAVE() macro with QOM casts
[PULL 53/72] target/rx: Set default NaN pattern explicitly
1
The FROM_SSI_SLAVE() macro predates QOM and is used as a typesafe way
1
Set the default NaN pattern explicitly for rx.
2
to cast from an SSISlave* to the instance struct of a subtype of
3
TYPE_SSI_SLAVE. Switch to using the QOM cast macros instead, which
4
have the same effect (by writing the QOM macros if the types were
5
previously missing them.)
6
7
(The FROM_SSI_SLAVE() macro allows the SSISlave member of the
8
subtype's struct to be anywhere as long as it is named "ssidev",
9
whereas a QOM cast macro insists that it is the first thing in the
10
subtype's struct. This is true for all the types we convert here.)
11
12
This removes all the uses of FROM_SSI_SLAVE() so we can delete the
13
definition.
14
2
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20241202131347.498124-48-peter.maydell@linaro.org
18
Message-id: 20200628142429.17111-18-peter.maydell@linaro.org
19
---
6
---
20
include/hw/ssi/ssi.h | 2 --
7
target/rx/cpu.c | 2 ++
21
hw/arm/z2.c | 11 +++++++----
8
1 file changed, 2 insertions(+)
22
hw/display/ads7846.c | 9 ++++++---
23
hw/display/ssd0323.c | 10 +++++++---
24
hw/sd/ssi-sd.c | 4 ++--
25
5 files changed, 22 insertions(+), 14 deletions(-)
26
9
27
diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
10
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
28
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
29
--- a/include/hw/ssi/ssi.h
12
--- a/target/rx/cpu.c
30
+++ b/include/hw/ssi/ssi.h
13
+++ b/target/rx/cpu.c
31
@@ -XXX,XX +XXX,XX @@ struct SSISlave {
14
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj, ResetType type)
32
bool cs;
15
* then prefer dest over source", which is float_2nan_prop_s_ab.
33
};
16
*/
34
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
35
-#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev)
18
+ /* Default NaN value: sign bit clear, set frac msb */
36
-
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
37
extern const VMStateDescription vmstate_ssi_slave;
38
39
#define VMSTATE_SSI_SLAVE(_field, _state) { \
40
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/arm/z2.c
43
+++ b/hw/arm/z2.c
44
@@ -XXX,XX +XXX,XX @@ typedef struct {
45
int pos;
46
} ZipitLCD;
47
48
+#define TYPE_ZIPIT_LCD "zipit-lcd"
49
+#define ZIPIT_LCD(obj) OBJECT_CHECK(ZipitLCD, (obj), TYPE_ZIPIT_LCD)
50
+
51
static uint32_t zipit_lcd_transfer(SSISlave *dev, uint32_t value)
52
{
53
- ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev);
54
+ ZipitLCD *z = ZIPIT_LCD(dev);
55
uint16_t val;
56
if (z->selected) {
57
z->buf[z->pos] = value & 0xff;
58
@@ -XXX,XX +XXX,XX @@ static void z2_lcd_cs(void *opaque, int line, int level)
59
60
static void zipit_lcd_realize(SSISlave *dev, Error **errp)
61
{
62
- ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev);
63
+ ZipitLCD *z = ZIPIT_LCD(dev);
64
z->selected = 0;
65
z->enabled = 0;
66
z->pos = 0;
67
@@ -XXX,XX +XXX,XX @@ static void zipit_lcd_class_init(ObjectClass *klass, void *data)
68
}
20
}
69
21
70
static const TypeInfo zipit_lcd_info = {
22
static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
71
- .name = "zipit-lcd",
72
+ .name = TYPE_ZIPIT_LCD,
73
.parent = TYPE_SSI_SLAVE,
74
.instance_size = sizeof(ZipitLCD),
75
.class_init = zipit_lcd_class_init,
76
@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
77
78
type_register_static(&zipit_lcd_info);
79
type_register_static(&aer915_info);
80
- z2_lcd = ssi_create_slave(mpu->ssp[1], "zipit-lcd");
81
+ z2_lcd = ssi_create_slave(mpu->ssp[1], TYPE_ZIPIT_LCD);
82
bus = pxa2xx_i2c_bus(mpu->i2c[0]);
83
i2c_create_slave(bus, TYPE_AER915, 0x55);
84
wm = i2c_create_slave(bus, TYPE_WM8750, 0x1b);
85
diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c
86
index XXXXXXX..XXXXXXX 100644
87
--- a/hw/display/ads7846.c
88
+++ b/hw/display/ads7846.c
89
@@ -XXX,XX +XXX,XX @@ typedef struct {
90
int output;
91
} ADS7846State;
92
93
+#define TYPE_ADS7846 "ads7846"
94
+#define ADS7846(obj) OBJECT_CHECK(ADS7846State, (obj), TYPE_ADS7846)
95
+
96
/* Control-byte bitfields */
97
#define CB_PD0        (1 << 0)
98
#define CB_PD1        (1 << 1)
99
@@ -XXX,XX +XXX,XX @@ static void ads7846_int_update(ADS7846State *s)
100
101
static uint32_t ads7846_transfer(SSISlave *dev, uint32_t value)
102
{
103
- ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, dev);
104
+ ADS7846State *s = ADS7846(dev);
105
106
switch (s->cycle ++) {
107
case 0:
108
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ads7846 = {
109
static void ads7846_realize(SSISlave *d, Error **errp)
110
{
111
DeviceState *dev = DEVICE(d);
112
- ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, d);
113
+ ADS7846State *s = ADS7846(d);
114
115
qdev_init_gpio_out(dev, &s->interrupt, 1);
116
117
@@ -XXX,XX +XXX,XX @@ static void ads7846_class_init(ObjectClass *klass, void *data)
118
}
119
120
static const TypeInfo ads7846_info = {
121
- .name = "ads7846",
122
+ .name = TYPE_ADS7846,
123
.parent = TYPE_SSI_SLAVE,
124
.instance_size = sizeof(ADS7846State),
125
.class_init = ads7846_class_init,
126
diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c
127
index XXXXXXX..XXXXXXX 100644
128
--- a/hw/display/ssd0323.c
129
+++ b/hw/display/ssd0323.c
130
@@ -XXX,XX +XXX,XX @@ typedef struct {
131
uint8_t framebuffer[128 * 80 / 2];
132
} ssd0323_state;
133
134
+#define TYPE_SSD0323 "ssd0323"
135
+#define SSD0323(obj) OBJECT_CHECK(ssd0323_state, (obj), TYPE_SSD0323)
136
+
137
+
138
static uint32_t ssd0323_transfer(SSISlave *dev, uint32_t data)
139
{
140
- ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, dev);
141
+ ssd0323_state *s = SSD0323(dev);
142
143
switch (s->mode) {
144
case SSD0323_DATA:
145
@@ -XXX,XX +XXX,XX @@ static const GraphicHwOps ssd0323_ops = {
146
static void ssd0323_realize(SSISlave *d, Error **errp)
147
{
148
DeviceState *dev = DEVICE(d);
149
- ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, d);
150
+ ssd0323_state *s = SSD0323(d);
151
152
s->col_end = 63;
153
s->row_end = 79;
154
@@ -XXX,XX +XXX,XX @@ static void ssd0323_class_init(ObjectClass *klass, void *data)
155
}
156
157
static const TypeInfo ssd0323_info = {
158
- .name = "ssd0323",
159
+ .name = TYPE_SSD0323,
160
.parent = TYPE_SSI_SLAVE,
161
.instance_size = sizeof(ssd0323_state),
162
.class_init = ssd0323_class_init,
163
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
164
index XXXXXXX..XXXXXXX 100644
165
--- a/hw/sd/ssi-sd.c
166
+++ b/hw/sd/ssi-sd.c
167
@@ -XXX,XX +XXX,XX @@ typedef struct {
168
169
static uint32_t ssi_sd_transfer(SSISlave *dev, uint32_t val)
170
{
171
- ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, dev);
172
+ ssi_sd_state *s = SSI_SD(dev);
173
174
/* Special case: allow CMD12 (STOP TRANSMISSION) while reading data. */
175
if (s->mode == SSI_SD_DATA_READ && val == 0x4d) {
176
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ssi_sd = {
177
178
static void ssi_sd_realize(SSISlave *d, Error **errp)
179
{
180
- ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, d);
181
+ ssi_sd_state *s = SSI_SD(d);
182
DeviceState *carddev;
183
DriveInfo *dinfo;
184
Error *err = NULL;
185
--
23
--
186
2.20.1
24
2.34.1
187
188
diff view generated by jsdifflib
New patch
[PULL 54/72] target/s390x: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for s390x.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-49-peter.maydell@linaro.org
6
---
7
target/s390x/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/s390x/cpu.c
13
+++ b/target/s390x/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
15
set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
16
set_float_infzeronan_rule(float_infzeronan_dnan_always,
17
&env->fpu_status);
18
+ /* Default NaN value: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fpu_status);
20
/* fall through */
21
case RESET_TYPE_S390_CPU_NORMAL:
22
env->psw.mask &= ~PSW_MASK_RI;
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 55/72] target/sparc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for SPARC, and remove
2
the ifdef from parts64_default_nan.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-50-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 5 +----
10
2 files changed, 3 insertions(+), 4 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN value: sign bit clear, all frac bits set */
21
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
uint8_t dnan_pattern = status->default_nan_pattern;
31
32
if (dnan_pattern == 0) {
33
-#if defined(TARGET_SPARC)
34
- /* Sign bit clear, all frac bits set */
35
- dnan_pattern = 0b01111111;
36
-#elif defined(TARGET_HEXAGON)
37
+#if defined(TARGET_HEXAGON)
38
/* Sign bit set, all frac bits set. */
39
dnan_pattern = 0b11111111;
40
#else
41
--
42
2.34.1
diff view generated by jsdifflib
[PULL 29/34] hw/gpio/zaurus.c: Use LOG_GUEST_ERROR for bad guest register accesses
[PULL 56/72] target/xtensa: Set default NaN pattern explicitly
1
Instead of logging guest accesses to invalid register offsets in this
1
Set the default NaN pattern explicitly for xtensa.
2
device using zaurus_printf() (which just prints to stderr), use the
3
usual qemu_log_mask(LOG_GUEST_ERROR,...).
4
5
Since this was the only use of the zaurus_printf() macro outside
6
spitz.c, we can move the definition of that macro from sharpsl.h
7
to spitz.c.
8
2
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20241202131347.498124-51-peter.maydell@linaro.org
12
Message-id: 20200628142429.17111-14-peter.maydell@linaro.org
13
---
6
---
14
include/hw/arm/sharpsl.h | 3 ---
7
target/xtensa/cpu.c | 2 ++
15
hw/arm/spitz.c | 3 +++
8
1 file changed, 2 insertions(+)
16
hw/gpio/zaurus.c | 12 +++++++-----
17
3 files changed, 10 insertions(+), 8 deletions(-)
18
9
19
diff --git a/include/hw/arm/sharpsl.h b/include/hw/arm/sharpsl.h
10
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
20
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/sharpsl.h
12
--- a/target/xtensa/cpu.c
22
+++ b/include/hw/arm/sharpsl.h
13
+++ b/target/xtensa/cpu.c
23
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
24
15
/* For inf * 0 + NaN, return the input NaN */
25
#include "exec/hwaddr.h"
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
17
set_no_signaling_nans(!dfpu, &env->fp_status);
27
-#define zaurus_printf(format, ...)    \
18
+ /* Default NaN value: sign bit clear, set frac msb */
28
- fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
29
-
20
xtensa_use_first_nan(env, !dfpu);
30
/* zaurus.c */
31
32
#define SL_PXA_PARAM_BASE    0xa0000a00
33
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/arm/spitz.c
36
+++ b/hw/arm/spitz.c
37
@@ -XXX,XX +XXX,XX @@ typedef struct {
38
#define SPITZ_MACHINE_CLASS(klass) \
39
OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE)
40
41
+#define zaurus_printf(format, ...) \
42
+ fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
43
+
44
#undef REG_FMT
45
#define REG_FMT "0x%02lx"
46
47
diff --git a/hw/gpio/zaurus.c b/hw/gpio/zaurus.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/gpio/zaurus.c
50
+++ b/hw/gpio/zaurus.c
51
@@ -XXX,XX +XXX,XX @@
52
#include "hw/sysbus.h"
53
#include "migration/vmstate.h"
54
#include "qemu/module.h"
55
-
56
-#undef REG_FMT
57
-#define REG_FMT            "0x%02lx"
58
+#include "qemu/log.h"
59
60
/* SCOOP devices */
61
62
@@ -XXX,XX +XXX,XX @@ static uint64_t scoop_read(void *opaque, hwaddr addr,
63
case SCOOP_GPRR:
64
return s->gpio_level;
65
default:
66
- zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
67
+ qemu_log_mask(LOG_GUEST_ERROR,
68
+ "scoop_read: bad register offset 0x%02" HWADDR_PRIx "\n",
69
+ addr);
70
}
71
72
return 0;
73
@@ -XXX,XX +XXX,XX @@ static void scoop_write(void *opaque, hwaddr addr,
74
scoop_gpio_handler_update(s);
75
break;
76
default:
77
- zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
78
+ qemu_log_mask(LOG_GUEST_ERROR,
79
+ "scoop_write: bad register offset 0x%02" HWADDR_PRIx "\n",
80
+ addr);
81
}
82
}
21
}
83
22
84
--
23
--
85
2.20.1
24
2.34.1
86
87
diff view generated by jsdifflib
[PULL 24/34] ssi: Add ssi_realize_and_unref()
[PULL 57/72] target/hexagon: Set default NaN pattern explicitly
1
Add an ssi_realize_and_unref(), for the benefit of callers
1
Set the default NaN pattern explicitly for hexagon.
2
who want to be able to create an SSI device, set QOM properties
2
Remove the ifdef from parts64_default_nan(); the only
3
on it, and then do the realize-and-unref afterwards.
3
remaining unconverted targets all use the default case.
4
5
The API works on the same principle as the recently added
6
qdev_realize_and_undef(), sysbus_realize_and_undef(), etc.
7
4
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-id: 20241202131347.498124-52-peter.maydell@linaro.org
11
Message-id: 20200628142429.17111-9-peter.maydell@linaro.org
12
---
8
---
13
include/hw/ssi/ssi.h | 26 ++++++++++++++++++++++++++
9
target/hexagon/cpu.c | 2 ++
14
hw/ssi/ssi.c | 7 ++++++-
10
fpu/softfloat-specialize.c.inc | 5 -----
15
2 files changed, 32 insertions(+), 1 deletion(-)
11
2 files changed, 2 insertions(+), 5 deletions(-)
16
12
17
diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
13
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
18
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/ssi/ssi.h
15
--- a/target/hexagon/cpu.c
20
+++ b/include/hw/ssi/ssi.h
16
+++ b/target/hexagon/cpu.c
21
@@ -XXX,XX +XXX,XX @@ extern const VMStateDescription vmstate_ssi_slave;
17
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
18
19
set_default_nan_mode(1, &env->fp_status);
20
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
21
+ /* Default NaN value: sign bit set, all frac bits set */
22
+ set_float_default_nan_pattern(0b11111111, &env->fp_status);
22
}
23
}
23
24
24
DeviceState *ssi_create_slave(SSIBus *bus, const char *name);
25
static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
25
+/**
26
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
+ * ssi_realize_and_unref: realize and unref an SSI slave device
27
+ * @dev: SSI slave device to realize
28
+ * @bus: SSI bus to put it on
29
+ * @errp: error pointer
30
+ *
31
+ * Call 'realize' on @dev, put it on the specified @bus, and drop the
32
+ * reference to it. Errors are reported via @errp and by returning
33
+ * false.
34
+ *
35
+ * This function is useful if you have created @dev via qdev_new()
36
+ * (which takes a reference to the device it returns to you), so that
37
+ * you can set properties on it before realizing it. If you don't need
38
+ * to set properties then ssi_create_slave() is probably better (as it
39
+ * does the create, init and realize in one step).
40
+ *
41
+ * If you are embedding the SSI slave into another QOM device and
42
+ * initialized it via some variant on object_initialize_child() then
43
+ * do not use this function, because that family of functions arrange
44
+ * for the only reference to the child device to be held by the parent
45
+ * via the child<> property, and so the reference-count-drop done here
46
+ * would be incorrect. (Instead you would want ssi_realize(), which
47
+ * doesn't currently exist but would be trivial to create if we had
48
+ * any code that wanted it.)
49
+ */
50
+bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp);
51
52
/* Master interface. */
53
SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
54
diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
55
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/ssi/ssi.c
28
--- a/fpu/softfloat-specialize.c.inc
57
+++ b/hw/ssi/ssi.c
29
+++ b/fpu/softfloat-specialize.c.inc
58
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ssi_slave_info = {
30
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
59
.abstract = true,
31
uint8_t dnan_pattern = status->default_nan_pattern;
60
};
32
61
33
if (dnan_pattern == 0) {
62
+bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp)
34
-#if defined(TARGET_HEXAGON)
63
+{
35
- /* Sign bit set, all frac bits set. */
64
+ return qdev_realize_and_unref(dev, &bus->parent_obj, errp);
36
- dnan_pattern = 0b11111111;
65
+}
37
-#else
66
+
38
/*
67
DeviceState *ssi_create_slave(SSIBus *bus, const char *name)
39
* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
68
{
40
* S390, SH4, TriCore, and Xtensa. Our other supported targets
69
DeviceState *dev = qdev_new(name);
41
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
70
42
/* sign bit clear, set frac msb */
71
- qdev_realize_and_unref(dev, &bus->parent_obj, &error_fatal);
43
dnan_pattern = 0b01000000;
72
+ ssi_realize_and_unref(dev, bus, &error_fatal);
44
}
73
return dev;
45
-#endif
74
}
46
}
47
assert(dnan_pattern != 0);
75
48
76
--
49
--
77
2.20.1
50
2.34.1
78
79
diff view generated by jsdifflib
[PULL 31/34] hw/arm/pxa2xx_pic: Use LOG_GUEST_ERROR for bad guest register accesses
[PULL 58/72] target/riscv: Set default NaN pattern explicitly
1
Instead of using printf() for logging guest accesses to invalid
1
Set the default NaN pattern explicitly for riscv.
2
register offsets in the pxa2xx PIC device, use the usual
3
qemu_log_mask(LOG_GUEST_ERROR,...).
4
5
This was the only user of the REG_FMT macro in pxa.h, so we can
6
remove that.
7
2
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20241202131347.498124-53-peter.maydell@linaro.org
11
Message-id: 20200628142429.17111-16-peter.maydell@linaro.org
12
---
6
---
13
include/hw/arm/pxa.h | 1 -
7
target/riscv/cpu.c | 2 ++
14
hw/arm/pxa2xx_pic.c | 9 +++++++--
8
1 file changed, 2 insertions(+)
15
2 files changed, 7 insertions(+), 3 deletions(-)
16
9
17
diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
10
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
18
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/pxa.h
12
--- a/target/riscv/cpu.c
20
+++ b/include/hw/arm/pxa.h
13
+++ b/target/riscv/cpu.c
21
@@ -XXX,XX +XXX,XX @@ struct PXA2xxI2SState {
14
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
22
};
15
cs->exception_index = RISCV_EXCP_NONE;
23
16
env->load_res = -1;
24
# define PA_FMT            "0x%08lx"
17
set_default_nan_mode(1, &env->fp_status);
25
-# define REG_FMT        "0x" TARGET_FMT_plx
18
+ /* Default NaN value: sign bit clear, frac msb set */
26
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
27
PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
20
env->vill = true;
28
const char *revision);
21
29
diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
22
#ifndef CONFIG_USER_ONLY
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/arm/pxa2xx_pic.c
32
+++ b/hw/arm/pxa2xx_pic.c
33
@@ -XXX,XX +XXX,XX @@
34
#include "qemu/osdep.h"
35
#include "qapi/error.h"
36
#include "qemu/module.h"
37
+#include "qemu/log.h"
38
#include "cpu.h"
39
#include "hw/arm/pxa.h"
40
#include "hw/sysbus.h"
41
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
42
case ICHP:    /* Highest Priority register */
43
return pxa2xx_pic_highest(s);
44
default:
45
- printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
46
+ qemu_log_mask(LOG_GUEST_ERROR,
47
+ "pxa2xx_pic_mem_read: bad register offset 0x%" HWADDR_PRIx
48
+ "\n", offset);
49
return 0;
50
}
51
}
52
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
53
s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
54
break;
55
default:
56
- printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
57
+ qemu_log_mask(LOG_GUEST_ERROR,
58
+ "pxa2xx_pic_mem_write: bad register offset 0x%"
59
+ HWADDR_PRIx "\n", offset);
60
return;
61
}
62
pxa2xx_pic_update(opaque);
63
--
23
--
64
2.20.1
24
2.34.1
65
66
diff view generated by jsdifflib
[PULL 32/34] hw/arm/spitz: Provide usual QOM macros for corgi-ssp and spitz-lcdtg
[PULL 59/72] target/tricore: Set default NaN pattern explicitly
1
The QOM types "spitz-lcdtg" and "corgi-ssp" are missing the
1
Set the default NaN pattern explicitly for tricore.
2
usual QOM TYPE and casting macros; provide and use them.
3
4
In particular, we can safely use the QOM cast macros instead of
5
FROM_SSI_SLAVE() because in both cases the 'ssidev' field of
6
the instance state struct is the first field in it.
7
2
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20241202131347.498124-54-peter.maydell@linaro.org
11
Message-id: 20200628142429.17111-17-peter.maydell@linaro.org
12
---
6
---
13
hw/arm/spitz.c | 23 +++++++++++++++--------
7
target/tricore/helper.c | 2 ++
14
1 file changed, 15 insertions(+), 8 deletions(-)
8
1 file changed, 2 insertions(+)
15
9
16
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
10
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
17
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/spitz.c
12
--- a/target/tricore/helper.c
19
+++ b/hw/arm/spitz.c
13
+++ b/target/tricore/helper.c
20
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp)
14
@@ -XXX,XX +XXX,XX @@ void fpu_set_state(CPUTriCoreState *env)
21
#define LCDTG_PICTRL 0x06
15
set_flush_to_zero(1, &env->fp_status);
22
#define LCDTG_POLCTRL 0x07
16
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
23
17
set_default_nan_mode(1, &env->fp_status);
24
+#define TYPE_SPITZ_LCDTG "spitz-lcdtg"
18
+ /* Default NaN pattern: sign bit clear, frac msb set */
25
+#define SPITZ_LCDTG(obj) OBJECT_CHECK(SpitzLCDTG, (obj), TYPE_SPITZ_LCDTG)
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
26
+
27
typedef struct {
28
SSISlave ssidev;
29
uint32_t bl_intensity;
30
@@ -XXX,XX +XXX,XX @@ static inline void spitz_bl_power(void *opaque, int line, int level)
31
32
static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
33
{
34
- SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
35
+ SpitzLCDTG *s = SPITZ_LCDTG(dev);
36
int addr;
37
addr = value >> 5;
38
value &= 0x1f;
39
@@ -XXX,XX +XXX,XX @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
40
41
static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
42
{
43
- SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, ssi);
44
+ SpitzLCDTG *s = SPITZ_LCDTG(ssi);
45
DeviceState *dev = DEVICE(s);
46
47
s->bl_power = 0;
48
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
49
#define SPITZ_GPIO_MAX1111_CS 20
50
#define SPITZ_GPIO_TP_INT 11
51
52
+#define TYPE_CORGI_SSP "corgi-ssp"
53
+#define CORGI_SSP(obj) OBJECT_CHECK(CorgiSSPState, (obj), TYPE_CORGI_SSP)
54
+
55
/* "Demux" the signal based on current chipselect */
56
typedef struct {
57
SSISlave ssidev;
58
@@ -XXX,XX +XXX,XX @@ typedef struct {
59
60
static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
61
{
62
- CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
63
+ CorgiSSPState *s = CORGI_SSP(dev);
64
int i;
65
66
for (i = 0; i < 3; i++) {
67
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
68
static void corgi_ssp_realize(SSISlave *d, Error **errp)
69
{
70
DeviceState *dev = DEVICE(d);
71
- CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, d);
72
+ CorgiSSPState *s = CORGI_SSP(d);
73
74
qdev_init_gpio_in(dev, corgi_ssp_gpio_cs, 3);
75
s->bus[0] = ssi_create_bus(dev, "ssi0");
76
@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
77
{
78
void *bus;
79
80
- sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
81
+ sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1],
82
+ TYPE_CORGI_SSP);
83
84
bus = qdev_get_child_bus(sms->mux, "ssi0");
85
- sms->lcdtg = ssi_create_slave(bus, "spitz-lcdtg");
86
+ sms->lcdtg = ssi_create_slave(bus, TYPE_SPITZ_LCDTG);
87
88
bus = qdev_get_child_bus(sms->mux, "ssi1");
89
sms->ads7846 = ssi_create_slave(bus, "ads7846");
90
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_class_init(ObjectClass *klass, void *data)
91
}
20
}
92
21
93
static const TypeInfo corgi_ssp_info = {
22
uint32_t psw_read(CPUTriCoreState *env)
94
- .name = "corgi-ssp",
95
+ .name = TYPE_CORGI_SSP,
96
.parent = TYPE_SSI_SLAVE,
97
.instance_size = sizeof(CorgiSSPState),
98
.class_init = corgi_ssp_class_init,
99
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_class_init(ObjectClass *klass, void *data)
100
}
101
102
static const TypeInfo spitz_lcdtg_info = {
103
- .name = "spitz-lcdtg",
104
+ .name = TYPE_SPITZ_LCDTG,
105
.parent = TYPE_SSI_SLAVE,
106
.instance_size = sizeof(SpitzLCDTG),
107
.class_init = spitz_lcdtg_class_init,
108
--
23
--
109
2.20.1
24
2.34.1
110
111
diff view generated by jsdifflib
[PULL 25/34] hw/arm/spitz: Use max111x properties to set initial values
[PULL 60/72] fpu: Remove default handling for dnan_pattern
1
Use the new max111x qdev properties to set the initial input
1
Now that all our targets have bene converted to explicitly specify
2
values rather than calling max111x_set_input(); this means that
2
their pattern for the default NaN value we can remove the remaining
3
on system reset the inputs will correctly return to their initial
3
fallback code in parts64_default_nan().
4
values.
5
4
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200628142429.17111-10-peter.maydell@linaro.org
7
Message-id: 20241202131347.498124-55-peter.maydell@linaro.org
9
---
8
---
10
hw/arm/spitz.c | 11 +++++++----
9
fpu/softfloat-specialize.c.inc | 14 --------------
11
1 file changed, 7 insertions(+), 4 deletions(-)
10
1 file changed, 14 deletions(-)
12
11
13
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
12
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
14
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/spitz.c
14
--- a/fpu/softfloat-specialize.c.inc
16
+++ b/hw/arm/spitz.c
15
+++ b/fpu/softfloat-specialize.c.inc
17
@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
16
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
18
qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
17
uint64_t frac;
19
18
uint8_t dnan_pattern = status->default_nan_pattern;
20
bus = qdev_get_child_bus(sms->mux, "ssi2");
19
21
- sms->max1111 = ssi_create_slave(bus, "max1111");
20
- if (dnan_pattern == 0) {
22
+ sms->max1111 = qdev_new("max1111");
21
- /*
23
max1111 = sms->max1111;
22
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
24
- max111x_set_input(sms->max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
23
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
25
- max111x_set_input(sms->max1111, MAX1111_BATT_TEMP, 0);
24
- * do not have floating-point.
26
- max111x_set_input(sms->max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
25
- */
27
+ qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
26
- if (snan_bit_is_one(status)) {
28
+ SPITZ_BATTERY_VOLT);
27
- /* sign bit clear, set all frac bits other than msb */
29
+ qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0);
28
- dnan_pattern = 0b00111111;
30
+ qdev_prop_set_uint8(sms->max1111, "input3" /* ACIN_VOLT */,
29
- } else {
31
+ SPITZ_CHARGEON_ACIN);
30
- /* sign bit clear, set frac msb */
32
+ ssi_realize_and_unref(sms->max1111, bus, &error_fatal);
31
- dnan_pattern = 0b01000000;
33
32
- }
34
qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS,
33
- }
35
qdev_get_gpio_in(sms->mux, 0));
34
assert(dnan_pattern != 0);
35
36
sign = dnan_pattern >> 7;
36
--
37
--
37
2.20.1
38
2.34.1
38
39
diff view generated by jsdifflib
[PULL 10/34] target/arm: kvm: Handle misconfigured dabt injection
[PULL 61/72] softfloat: Inline pickNaNMulAdd
1
From: Beata Michalska <beata.michalska@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Injecting external data abort through KVM might trigger
3
Inline pickNaNMulAdd into its only caller. This makes
4
an issue on kernels that do not get updated to include the KVM fix.
4
one assert redundant with the immediately preceding IF.
5
For those and aarch32 guests, the injected abort gets misconfigured
6
to be an implementation defined exception. This leads to the guest
7
repeatedly re-running the faulting instruction.
8
5
9
Add support for handling that case.
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
[
8
Message-id: 20241203203949.483774-3-richard.henderson@linaro.org
12
Fixed-by: 018f22f95e8a
9
[PMM: keep comment from old code in new location]
13
    ('KVM: arm: Fix DFSR setting for non-LPAE aarch32 guests')
14
Fixed-by: 21aecdbd7f3a
15
    ('KVM: arm: Make inject_abt32() inject an external abort instead')
16
]
17
18
Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
19
Acked-by: Andrew Jones <drjones@redhat.com>
20
Message-id: 20200629114110.30723-3-beata.michalska@linaro.org
21
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
---
11
---
24
target/arm/cpu.h | 2 ++
12
fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++-
25
target/arm/kvm_arm.h | 10 +++++++++
13
fpu/softfloat-specialize.c.inc | 54 ----------------------------------
26
target/arm/kvm.c | 30 ++++++++++++++++++++++++++-
14
2 files changed, 40 insertions(+), 55 deletions(-)
27
target/arm/kvm32.c | 34 ++++++++++++++++++++++++++++++
28
target/arm/kvm64.c | 49 ++++++++++++++++++++++++++++++++++++++++++++
29
5 files changed, 124 insertions(+), 1 deletion(-)
30
15
31
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
32
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/cpu.h
18
--- a/fpu/softfloat-parts.c.inc
34
+++ b/target/arm/cpu.h
19
+++ b/fpu/softfloat-parts.c.inc
35
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
36
uint64_t esr;
21
}
37
} serror;
22
38
23
if (s->default_nan_mode) {
39
+ uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
40
+
41
/* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
42
uint32_t irq_line_state;
43
44
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/kvm_arm.h
47
+++ b/target/arm/kvm_arm.h
48
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_hw_debug_active(CPUState *cs);
49
struct kvm_guest_debug_arch;
50
void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr);
51
52
+/**
53
+ * kvm_arm_verify_ext_dabt_pending:
54
+ * @cs: CPUState
55
+ *
56
+ * Verify the fault status code wrt the Ext DABT injection
57
+ *
58
+ * Returns: true if the fault status code is as expected, false otherwise
59
+ */
60
+bool kvm_arm_verify_ext_dabt_pending(CPUState *cs);
61
+
62
/**
63
* its_class_name:
64
*
65
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/kvm.c
68
+++ b/target/arm/kvm.c
69
@@ -XXX,XX +XXX,XX @@ int kvm_get_vcpu_events(ARMCPU *cpu)
70
71
void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
72
{
73
+ ARMCPU *cpu = ARM_CPU(cs);
74
+ CPUARMState *env = &cpu->env;
75
+
76
+ if (unlikely(env->ext_dabt_raised)) {
77
+ /*
24
+ /*
78
+ * Verifying that the ext DABT has been properly injected,
25
+ * We guarantee not to require the target to tell us how to
79
+ * otherwise risking indefinitely re-running the faulting instruction
26
+ * pick a NaN if we're always returning the default NaN.
80
+ * Covering a very narrow case for kernels 5.5..5.5.4
27
+ * But if we're not in default-NaN mode then the target must
81
+ * when injected abort was misconfigured to be
28
+ * specify.
82
+ * an IMPLEMENTATION DEFINED exception (for 32-bit EL1)
83
+ */
29
+ */
84
+ if (!arm_feature(env, ARM_FEATURE_AARCH64) &&
30
which = 3;
85
+ unlikely(!kvm_arm_verify_ext_dabt_pending(cs))) {
31
+ } else if (infzero) {
86
+
32
+ /*
87
+ error_report("Data abort exception with no valid ISS generated by "
33
+ * Inf * 0 + NaN -- some implementations return the
88
+ "guest memory access. KVM unable to emulate faulting "
34
+ * default NaN here, and some return the input NaN.
89
+ "instruction. Failed to inject an external data abort "
35
+ */
90
+ "into the guest.");
36
+ switch (s->float_infzeronan_rule) {
91
+ abort();
37
+ case float_infzeronan_dnan_never:
92
+ }
38
+ which = 2;
93
+ /* Clear the status */
39
+ break;
94
+ env->ext_dabt_raised = 0;
40
+ case float_infzeronan_dnan_always:
95
+ }
41
+ which = 3;
96
}
42
+ break;
97
43
+ case float_infzeronan_dnan_if_qnan:
98
MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
44
+ which = is_qnan(c->cls) ? 3 : 2;
99
@@ -XXX,XX +XXX,XX @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state)
45
+ break;
100
static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
46
+ default:
101
uint64_t fault_ipa)
47
+ g_assert_not_reached();
102
{
103
+ ARMCPU *cpu = ARM_CPU(cs);
104
+ CPUARMState *env = &cpu->env;
105
/*
106
* Request KVM to inject the external data abort into the guest
107
*/
108
@@ -XXX,XX +XXX,XX @@ static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
109
*/
110
events.exception.ext_dabt_pending = 1;
111
/* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */
112
- return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events);
113
+ if (!kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events)) {
114
+ env->ext_dabt_raised = 1;
115
+ return 0;
116
+ }
48
+ }
117
} else {
49
} else {
118
error_report("Data abort exception triggered by guest memory access "
50
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
119
"at physical address: 0x" TARGET_FMT_lx,
51
+ FloatClass cls[3] = { a->cls, b->cls, c->cls };
120
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
52
+ Float3NaNPropRule rule = s->float_3nan_prop_rule;
53
+
54
+ assert(rule != float_3nan_prop_none);
55
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
56
+ /* We have at least one SNaN input and should prefer it */
57
+ do {
58
+ which = rule & R_3NAN_1ST_MASK;
59
+ rule >>= R_3NAN_1ST_LENGTH;
60
+ } while (!is_snan(cls[which]));
61
+ } else {
62
+ do {
63
+ which = rule & R_3NAN_1ST_MASK;
64
+ rule >>= R_3NAN_1ST_LENGTH;
65
+ } while (!is_nan(cls[which]));
66
+ }
67
}
68
69
if (which == 3) {
70
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
121
index XXXXXXX..XXXXXXX 100644
71
index XXXXXXX..XXXXXXX 100644
122
--- a/target/arm/kvm32.c
72
--- a/fpu/softfloat-specialize.c.inc
123
+++ b/target/arm/kvm32.c
73
+++ b/fpu/softfloat-specialize.c.inc
124
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_init(CPUState *cs)
74
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
125
{
75
}
126
qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
127
}
76
}
128
+
77
129
+#define ARM_REG_DFSR ARM_CP15_REG32(0, 5, 0, 0)
78
-/*----------------------------------------------------------------------------
130
+#define ARM_REG_TTBCR ARM_CP15_REG32(0, 2, 0, 2)
79
-| Select which NaN to propagate for a three-input operation.
131
+/*
80
-| For the moment we assume that no CPU needs the 'larger significand'
132
+ *DFSR:
81
-| information.
133
+ * TTBCR.EAE == 0
82
-| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
134
+ * FS[4] - DFSR[10]
83
-*----------------------------------------------------------------------------*/
135
+ * FS[3:0] - DFSR[3:0]
84
-static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
136
+ * TTBCR.EAE == 1
85
- bool infzero, bool have_snan, float_status *status)
137
+ * FS, bits [5:0]
86
-{
138
+ */
87
- FloatClass cls[3] = { a_cls, b_cls, c_cls };
139
+#define DFSR_FSC(lpae, v) \
88
- Float3NaNPropRule rule = status->float_3nan_prop_rule;
140
+ ((lpae) ? ((v) & 0x3F) : (((v) >> 6) | ((v) & 0x1F)))
89
- int which;
141
+
90
-
142
+#define DFSC_EXTABT(lpae) ((lpae) ? 0x10 : 0x08)
91
- /*
143
+
92
- * We guarantee not to require the target to tell us how to
144
+bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
93
- * pick a NaN if we're always returning the default NaN.
145
+{
94
- * But if we're not in default-NaN mode then the target must
146
+ uint32_t dfsr_val;
95
- * specify.
147
+
96
- */
148
+ if (!kvm_get_one_reg(cs, ARM_REG_DFSR, &dfsr_val)) {
97
- assert(!status->default_nan_mode);
149
+ ARMCPU *cpu = ARM_CPU(cs);
98
-
150
+ CPUARMState *env = &cpu->env;
99
- if (infzero) {
151
+ uint32_t ttbcr;
100
- /*
152
+ int lpae = 0;
101
- * Inf * 0 + NaN -- some implementations return the default NaN here,
153
+
102
- * and some return the input NaN.
154
+ if (!kvm_get_one_reg(cs, ARM_REG_TTBCR, &ttbcr)) {
103
- */
155
+ lpae = arm_feature(env, ARM_FEATURE_LPAE) && (ttbcr & TTBCR_EAE);
104
- switch (status->float_infzeronan_rule) {
156
+ }
105
- case float_infzeronan_dnan_never:
157
+ /* The verification is based on FS filed of the DFSR reg only*/
106
- return 2;
158
+ return (DFSR_FSC(lpae, dfsr_val) == DFSC_EXTABT(lpae));
107
- case float_infzeronan_dnan_always:
159
+ }
108
- return 3;
160
+ return false;
109
- case float_infzeronan_dnan_if_qnan:
161
+}
110
- return is_qnan(c_cls) ? 3 : 2;
162
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
111
- default:
163
index XXXXXXX..XXXXXXX 100644
112
- g_assert_not_reached();
164
--- a/target/arm/kvm64.c
113
- }
165
+++ b/target/arm/kvm64.c
114
- }
166
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
115
-
167
116
- assert(rule != float_3nan_prop_none);
168
return false;
117
- if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
169
}
118
- /* We have at least one SNaN input and should prefer it */
170
+
119
- do {
171
+#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0)
120
- which = rule & R_3NAN_1ST_MASK;
172
+#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2)
121
- rule >>= R_3NAN_1ST_LENGTH;
173
+
122
- } while (!is_snan(cls[which]));
174
+/*
123
- } else {
175
+ * ESR_EL1
124
- do {
176
+ * ISS encoding
125
- which = rule & R_3NAN_1ST_MASK;
177
+ * AARCH64: DFSC, bits [5:0]
126
- rule >>= R_3NAN_1ST_LENGTH;
178
+ * AARCH32:
127
- } while (!is_nan(cls[which]));
179
+ * TTBCR.EAE == 0
128
- }
180
+ * FS[4] - DFSR[10]
129
- return which;
181
+ * FS[3:0] - DFSR[3:0]
130
-}
182
+ * TTBCR.EAE == 1
131
-
183
+ * FS, bits [5:0]
132
/*----------------------------------------------------------------------------
184
+ */
133
| Returns 1 if the double-precision floating-point value `a' is a quiet
185
+#define ESR_DFSC(aarch64, lpae, v) \
134
| NaN; otherwise returns 0.
186
+ ((aarch64 || (lpae)) ? ((v) & 0x3F) \
187
+ : (((v) >> 6) | ((v) & 0x1F)))
188
+
189
+#define ESR_DFSC_EXTABT(aarch64, lpae) \
190
+ ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8)
191
+
192
+bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
193
+{
194
+ uint64_t dfsr_val;
195
+
196
+ if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) {
197
+ ARMCPU *cpu = ARM_CPU(cs);
198
+ CPUARMState *env = &cpu->env;
199
+ int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64);
200
+ int lpae = 0;
201
+
202
+ if (!aarch64_mode) {
203
+ uint64_t ttbcr;
204
+
205
+ if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) {
206
+ lpae = arm_feature(env, ARM_FEATURE_LPAE)
207
+ && (ttbcr & TTBCR_EAE);
208
+ }
209
+ }
210
+ /*
211
+ * The verification here is based on the DFSC bits
212
+ * of the ESR_EL1 reg only
213
+ */
214
+ return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) ==
215
+ ESR_DFSC_EXTABT(aarch64_mode, lpae));
216
+ }
217
+ return false;
218
+}
219
--
135
--
220
2.20.1
136
2.34.1
221
137
222
138
diff view generated by jsdifflib
[PULL 15/34] target/arm: Fix temp double-free in sve ldr/str
[PULL 62/72] softfloat: Use goto for default nan case in pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The temp that gets assigned to clean_addr has been allocated with
3
Remove "3" as a special case for which and simply
4
new_tmp_a64, which means that it will be freed at the end of the
4
branch to return the desired value.
5
instruction. Freeing it earlier leads to assertion failure.
6
5
7
The loop creates a complication, in which we allocate a new local
8
temp, which does need freeing, and the final code path is shared
9
between the loop and non-loop.
10
11
Fix this complication by adding new_tmp_a64_local so that the new
12
local temp is freed at the end, and can be treated exactly like
13
the non-loop path.
14
15
Fixes: bba87d0a0f4
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
18
Message-id: 20200702175605.1987125-1-richard.henderson@linaro.org
8
Message-id: 20241203203949.483774-4-richard.henderson@linaro.org
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
10
---
21
target/arm/translate-a64.h | 1 +
11
fpu/softfloat-parts.c.inc | 20 ++++++++++----------
22
target/arm/translate-a64.c | 6 ++++++
12
1 file changed, 10 insertions(+), 10 deletions(-)
23
target/arm/translate-sve.c | 8 ++------
24
3 files changed, 9 insertions(+), 6 deletions(-)
25
13
26
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
27
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/translate-a64.h
16
--- a/fpu/softfloat-parts.c.inc
29
+++ b/target/arm/translate-a64.h
17
+++ b/fpu/softfloat-parts.c.inc
30
@@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s);
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
31
} while (0)
19
* But if we're not in default-NaN mode then the target must
32
20
* specify.
33
TCGv_i64 new_tmp_a64(DisasContext *s);
21
*/
34
+TCGv_i64 new_tmp_a64_local(DisasContext *s);
22
- which = 3;
35
TCGv_i64 new_tmp_a64_zero(DisasContext *s);
23
+ goto default_nan;
36
TCGv_i64 cpu_reg(DisasContext *s, int reg);
24
} else if (infzero) {
37
TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
25
/*
38
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
26
* Inf * 0 + NaN -- some implementations return the
39
index XXXXXXX..XXXXXXX 100644
27
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
40
--- a/target/arm/translate-a64.c
28
*/
41
+++ b/target/arm/translate-a64.c
29
switch (s->float_infzeronan_rule) {
42
@@ -XXX,XX +XXX,XX @@ TCGv_i64 new_tmp_a64(DisasContext *s)
30
case float_infzeronan_dnan_never:
43
return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
31
- which = 2;
32
break;
33
case float_infzeronan_dnan_always:
34
- which = 3;
35
- break;
36
+ goto default_nan;
37
case float_infzeronan_dnan_if_qnan:
38
- which = is_qnan(c->cls) ? 3 : 2;
39
+ if (is_qnan(c->cls)) {
40
+ goto default_nan;
41
+ }
42
break;
43
default:
44
g_assert_not_reached();
45
}
46
+ which = 2;
47
} else {
48
FloatClass cls[3] = { a->cls, b->cls, c->cls };
49
Float3NaNPropRule rule = s->float_3nan_prop_rule;
50
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
51
}
52
}
53
54
- if (which == 3) {
55
- parts_default_nan(a, s);
56
- return a;
57
- }
58
-
59
switch (which) {
60
case 0:
61
break;
62
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
63
parts_silence_nan(a, s);
64
}
65
return a;
66
+
67
+ default_nan:
68
+ parts_default_nan(a, s);
69
+ return a;
44
}
70
}
45
71
46
+TCGv_i64 new_tmp_a64_local(DisasContext *s)
72
/*
47
+{
48
+ assert(s->tmp_a64_count < TMP_A64_MAX);
49
+ return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_local_new_i64();
50
+}
51
+
52
TCGv_i64 new_tmp_a64_zero(DisasContext *s)
53
{
54
TCGv_i64 t = new_tmp_a64(s);
55
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/arm/translate-sve.c
58
+++ b/target/arm/translate-sve.c
59
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
60
61
/* Copy the clean address into a local temp, live across the loop. */
62
t0 = clean_addr;
63
- clean_addr = tcg_temp_local_new_i64();
64
+ clean_addr = new_tmp_a64_local(s);
65
tcg_gen_mov_i64(clean_addr, t0);
66
- tcg_temp_free_i64(t0);
67
68
gen_set_label(loop);
69
70
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
71
tcg_gen_st_i64(t0, cpu_env, vofs + len_align);
72
tcg_temp_free_i64(t0);
73
}
74
- tcg_temp_free_i64(clean_addr);
75
}
76
77
/* Similarly for stores. */
78
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
79
80
/* Copy the clean address into a local temp, live across the loop. */
81
t0 = clean_addr;
82
- clean_addr = tcg_temp_local_new_i64();
83
+ clean_addr = new_tmp_a64_local(s);
84
tcg_gen_mov_i64(clean_addr, t0);
85
- tcg_temp_free_i64(t0);
86
87
gen_set_label(loop);
88
89
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
90
}
91
tcg_temp_free_i64(t0);
92
}
93
- tcg_temp_free_i64(clean_addr);
94
}
95
96
static bool trans_LDR_zri(DisasContext *s, arg_rri *a)
97
--
73
--
98
2.20.1
74
2.34.1
99
75
100
76
diff view generated by jsdifflib
[PULL 28/34] hw/arm/spitz: Encapsulate misc GPIO handling in a device
[PULL 63/72] softfloat: Remove which from parts_pick_nan_muladd
1
Currently we have a free-floating set of IRQs and a function
1
From: Richard Henderson <richard.henderson@linaro.org>
2
spitz_out_switch() which handle some miscellaneous GPIO lines for the
3
spitz board. Encapsulate this behaviour in a simple QOM device.
4
2
5
At this point we can finally remove the 'max1111' global, because the
3
Assign the pointer return value to 'a' directly,
6
ADC battery-temperature value is now handled by the misc-gpio device
4
rather than going through an intermediary index.
7
writing the value to its outbound "adc-temp" GPIO, which the board
8
code wires up to the appropriate inbound GPIO line on the max1111.
9
5
10
This commit also fixes Coverity issue CID 1421913 (which pointed out
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
that the 'outsignals' in spitz_scoop_gpio_setup() were leaked),
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
because it removes the use of the qemu_allocate_irqs() API from this
8
Message-id: 20241203203949.483774-5-richard.henderson@linaro.org
13
code entirely.
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
fpu/softfloat-parts.c.inc | 32 ++++++++++----------------------
12
1 file changed, 10 insertions(+), 22 deletions(-)
14
13
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
16
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
18
Message-id: 20200628142429.17111-13-peter.maydell@linaro.org
19
---
20
hw/arm/spitz.c | 129 +++++++++++++++++++++++++++++++++----------------
21
1 file changed, 87 insertions(+), 42 deletions(-)
22
23
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
24
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/spitz.c
16
--- a/fpu/softfloat-parts.c.inc
26
+++ b/hw/arm/spitz.c
17
+++ b/fpu/softfloat-parts.c.inc
27
@@ -XXX,XX +XXX,XX @@ typedef struct {
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
28
DeviceState *max1111;
19
FloatPartsN *c, float_status *s,
29
DeviceState *scp0;
20
int ab_mask, int abc_mask)
30
DeviceState *scp1;
31
+ DeviceState *misc_gpio;
32
} SpitzMachineState;
33
34
#define TYPE_SPITZ_MACHINE "spitz-common"
35
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
36
#define SPITZ_GPIO_MAX1111_CS 20
37
#define SPITZ_GPIO_TP_INT 11
38
39
-static DeviceState *max1111;
40
-
41
/* "Demux" the signal based on current chipselect */
42
typedef struct {
43
SSISlave ssidev;
44
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
45
#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
46
#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
47
48
-static void spitz_adc_temp_on(void *opaque, int line, int level)
49
-{
50
- int batt_temp;
51
-
52
- if (!max1111)
53
- return;
54
-
55
- batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
56
-
57
- qemu_set_irq(qdev_get_gpio_in(max1111, MAX1111_BATT_TEMP), batt_temp);
58
-}
59
-
60
static void corgi_ssp_realize(SSISlave *d, Error **errp)
61
{
21
{
62
DeviceState *dev = DEVICE(d);
22
- int which;
63
@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
23
bool infzero = (ab_mask == float_cmask_infzero);
64
24
bool have_snan = (abc_mask & float_cmask_snan);
65
bus = qdev_get_child_bus(sms->mux, "ssi2");
25
+ FloatPartsN *ret;
66
sms->max1111 = qdev_new(TYPE_MAX_1111);
26
67
- max1111 = sms->max1111;
27
if (unlikely(have_snan)) {
68
qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
28
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
69
SPITZ_BATTERY_VOLT);
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
70
qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0);
30
default:
71
@@ -XXX,XX +XXX,XX @@ static void spitz_akita_i2c_setup(PXA2xxState *cpu)
31
g_assert_not_reached();
72
32
}
73
/* Other peripherals */
33
- which = 2;
74
34
+ ret = c;
75
-static void spitz_out_switch(void *opaque, int line, int level)
35
} else {
76
+/*
36
- FloatClass cls[3] = { a->cls, b->cls, c->cls };
77
+ * Encapsulation of some miscellaneous GPIO line behaviour for the Spitz boards.
37
+ FloatPartsN *val[3] = { a, b, c };
78
+ *
38
Float3NaNPropRule rule = s->float_3nan_prop_rule;
79
+ * QEMU interface:
39
80
+ * + named GPIO inputs "green-led", "orange-led", "charging", "discharging":
40
assert(rule != float_3nan_prop_none);
81
+ * these currently just print messages that the line has been signalled
41
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
82
+ * + named GPIO input "adc-temp-on": set to cause the battery-temperature
42
/* We have at least one SNaN input and should prefer it */
83
+ * value to be passed to the max111x ADC
43
do {
84
+ * + named GPIO output "adc-temp": the ADC value, to be wired up to the max111x
44
- which = rule & R_3NAN_1ST_MASK;
85
+ */
45
+ ret = val[rule & R_3NAN_1ST_MASK];
86
+#define TYPE_SPITZ_MISC_GPIO "spitz-misc-gpio"
46
rule >>= R_3NAN_1ST_LENGTH;
87
+#define SPITZ_MISC_GPIO(obj) \
47
- } while (!is_snan(cls[which]));
88
+ OBJECT_CHECK(SpitzMiscGPIOState, (obj), TYPE_SPITZ_MISC_GPIO)
48
+ } while (!is_snan(ret->cls));
89
+
49
} else {
90
+typedef struct SpitzMiscGPIOState {
50
do {
91
+ SysBusDevice parent_obj;
51
- which = rule & R_3NAN_1ST_MASK;
92
+
52
+ ret = val[rule & R_3NAN_1ST_MASK];
93
+ qemu_irq adc_value;
53
rule >>= R_3NAN_1ST_LENGTH;
94
+} SpitzMiscGPIOState;
54
- } while (!is_nan(cls[which]));
95
+
55
+ } while (!is_nan(ret->cls));
96
+static void spitz_misc_charging(void *opaque, int n, int level)
56
}
97
{
57
}
98
- switch (line) {
58
59
- switch (which) {
99
- case 0:
60
- case 0:
100
- zaurus_printf("Charging %s.\n", level ? "off" : "on");
101
- break;
61
- break;
102
- case 1:
62
- case 1:
103
- zaurus_printf("Discharging %s.\n", level ? "on" : "off");
63
- a = b;
104
- break;
64
- break;
105
- case 2:
65
- case 2:
106
- zaurus_printf("Green LED %s.\n", level ? "on" : "off");
66
- a = c;
107
- break;
108
- case 3:
109
- zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
110
- break;
111
- case 6:
112
- spitz_adc_temp_on(opaque, line, level);
113
- break;
67
- break;
114
- default:
68
- default:
115
- g_assert_not_reached();
69
- g_assert_not_reached();
70
+ if (is_snan(ret->cls)) {
71
+ parts_silence_nan(ret, s);
72
}
73
- if (is_snan(a->cls)) {
74
- parts_silence_nan(a, s);
116
- }
75
- }
117
+ zaurus_printf("Charging %s.\n", level ? "off" : "on");
76
- return a;
118
+}
77
+ return ret;
119
+
78
120
+static void spitz_misc_discharging(void *opaque, int n, int level)
79
default_nan:
121
+{
80
parts_default_nan(a, s);
122
+ zaurus_printf("Discharging %s.\n", level ? "off" : "on");
123
+}
124
+
125
+static void spitz_misc_green_led(void *opaque, int n, int level)
126
+{
127
+ zaurus_printf("Green LED %s.\n", level ? "off" : "on");
128
+}
129
+
130
+static void spitz_misc_orange_led(void *opaque, int n, int level)
131
+{
132
+ zaurus_printf("Orange LED %s.\n", level ? "off" : "on");
133
+}
134
+
135
+static void spitz_misc_adc_temp(void *opaque, int n, int level)
136
+{
137
+ SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(opaque);
138
+ int batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
139
+
140
+ qemu_set_irq(s->adc_value, batt_temp);
141
+}
142
+
143
+static void spitz_misc_gpio_init(Object *obj)
144
+{
145
+ SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(obj);
146
+ DeviceState *dev = DEVICE(obj);
147
+
148
+ qdev_init_gpio_in_named(dev, spitz_misc_charging, "charging", 1);
149
+ qdev_init_gpio_in_named(dev, spitz_misc_discharging, "discharging", 1);
150
+ qdev_init_gpio_in_named(dev, spitz_misc_green_led, "green-led", 1);
151
+ qdev_init_gpio_in_named(dev, spitz_misc_orange_led, "orange-led", 1);
152
+ qdev_init_gpio_in_named(dev, spitz_misc_adc_temp, "adc-temp-on", 1);
153
+
154
+ qdev_init_gpio_out_named(dev, &s->adc_value, "adc-temp", 1);
155
}
156
157
#define SPITZ_SCP_LED_GREEN 1
158
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
159
160
static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
161
{
162
- qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, sms->mpu, 8);
163
+ DeviceState *miscdev = sysbus_create_simple(TYPE_SPITZ_MISC_GPIO, -1, NULL);
164
165
- qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
166
- qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, outsignals[1]);
167
- qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
168
- qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
169
+ sms->misc_gpio = miscdev;
170
+
171
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON,
172
+ qdev_get_gpio_in_named(miscdev, "charging", 0));
173
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B,
174
+ qdev_get_gpio_in_named(miscdev, "discharging", 0));
175
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN,
176
+ qdev_get_gpio_in_named(miscdev, "green-led", 0));
177
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE,
178
+ qdev_get_gpio_in_named(miscdev, "orange-led", 0));
179
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON,
180
+ qdev_get_gpio_in_named(miscdev, "adc-temp-on", 0));
181
+ qdev_connect_gpio_out_named(miscdev, "adc-temp", 0,
182
+ qdev_get_gpio_in(sms->max1111, MAX1111_BATT_TEMP));
183
184
if (sms->scp1) {
185
qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT,
186
@@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
187
qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON,
188
qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0));
189
}
190
-
191
- qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
192
}
193
194
#define SPITZ_GPIO_HSYNC 22
195
@@ -XXX,XX +XXX,XX @@ static const TypeInfo spitz_lcdtg_info = {
196
.class_init = spitz_lcdtg_class_init,
197
};
198
199
+static const TypeInfo spitz_misc_gpio_info = {
200
+ .name = TYPE_SPITZ_MISC_GPIO,
201
+ .parent = TYPE_SYS_BUS_DEVICE,
202
+ .instance_size = sizeof(SpitzMiscGPIOState),
203
+ .instance_init = spitz_misc_gpio_init,
204
+ /*
205
+ * No class_init required: device has no internal state so does not
206
+ * need to set up reset or vmstate, and does not have a realize method.
207
+ */
208
+};
209
+
210
static void spitz_register_types(void)
211
{
212
type_register_static(&corgi_ssp_info);
213
type_register_static(&spitz_lcdtg_info);
214
type_register_static(&spitz_keyboard_info);
215
type_register_static(&sl_nand_info);
216
+ type_register_static(&spitz_misc_gpio_info);
217
}
218
219
type_init(spitz_register_types)
220
--
81
--
221
2.20.1
82
2.34.1
222
83
223
84
diff view generated by jsdifflib
[PULL 11/34] tests/acpi: remove stale allowed tables
[PULL 64/72] softfloat: Pad array size in pick_nan_muladd
1
From: Andrew Jones <drjones@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Fixes: 93dd625f8bf7 ("tests/acpi: update expected data files")
3
While all indices into val[] should be in [0-2], the mask
4
Signed-off-by: Andrew Jones <drjones@redhat.com>
4
applied is two bits. To help static analysis see there is
5
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
5
no possibility of read beyond the end of the array, pad the
6
Reviewed-by: Eric Auger <eric.auger@redhat.com>
6
array to 4 entries, with the final being (implicitly) NULL.
7
Message-id: 20200629140938.17566-2-drjones@redhat.com
7
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-id: 20241203203949.483774-6-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
tests/qtest/bios-tables-test-allowed-diff.h | 18 ------------------
13
fpu/softfloat-parts.c.inc | 2 +-
11
1 file changed, 18 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
12
15
13
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/tests/qtest/bios-tables-test-allowed-diff.h
18
--- a/fpu/softfloat-parts.c.inc
16
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
19
+++ b/fpu/softfloat-parts.c.inc
17
@@ -1,19 +1 @@
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
18
/* List of comma-separated changed AML files to ignore */
21
}
19
-"tests/data/acpi/pc/DSDT",
22
ret = c;
20
-"tests/data/acpi/pc/DSDT.acpihmat",
23
} else {
21
-"tests/data/acpi/pc/DSDT.bridge",
24
- FloatPartsN *val[3] = { a, b, c };
22
-"tests/data/acpi/pc/DSDT.cphp",
25
+ FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c };
23
-"tests/data/acpi/pc/DSDT.dimmpxm",
26
Float3NaNPropRule rule = s->float_3nan_prop_rule;
24
-"tests/data/acpi/pc/DSDT.ipmikcs",
27
25
-"tests/data/acpi/pc/DSDT.memhp",
28
assert(rule != float_3nan_prop_none);
26
-"tests/data/acpi/pc/DSDT.numamem",
27
-"tests/data/acpi/q35/DSDT",
28
-"tests/data/acpi/q35/DSDT.acpihmat",
29
-"tests/data/acpi/q35/DSDT.bridge",
30
-"tests/data/acpi/q35/DSDT.cphp",
31
-"tests/data/acpi/q35/DSDT.dimmpxm",
32
-"tests/data/acpi/q35/DSDT.ipmibt",
33
-"tests/data/acpi/q35/DSDT.memhp",
34
-"tests/data/acpi/q35/DSDT.mmio64",
35
-"tests/data/acpi/q35/DSDT.numamem",
36
-"tests/data/acpi/q35/DSDT.tis",
37
--
29
--
38
2.20.1
30
2.34.1
39
31
40
32
diff view generated by jsdifflib
[PULL 05/34] virtio-iommu: Implement RESV_MEM probe request
[PULL 65/72] softfloat: Move propagateFloatx80NaN to softfloat.c
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This patch implements the PROBE request. At the moment,
3
This function is part of the public interface and
4
only THE RESV_MEM property is handled. The first goal is
4
is not "specialized" to any target in any way.
5
to report iommu wide reserved regions such as the MSI regions
6
set by the machine code. On x86 this will be the IOAPIC MSI
7
region, [0xFEE00000 - 0xFEEFFFFF], on ARM this may be the ITS
8
doorbell.
9
5
10
In the future we may introduce per device reserved regions.
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
This will be useful when protecting host assigned devices
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
which may expose their own reserved regions
8
Message-id: 20241203203949.483774-7-richard.henderson@linaro.org
13
14
Signed-off-by: Eric Auger <eric.auger@redhat.com>
15
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
16
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
17
Message-id: 20200629070404.10969-3-eric.auger@redhat.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
10
---
20
include/hw/virtio/virtio-iommu.h | 2 +
11
fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++
21
hw/virtio/virtio-iommu.c | 94 ++++++++++++++++++++++++++++++--
12
fpu/softfloat-specialize.c.inc | 52 ----------------------------------
22
hw/virtio/trace-events | 1 +
13
2 files changed, 52 insertions(+), 52 deletions(-)
23
3 files changed, 93 insertions(+), 4 deletions(-)
24
14
25
diff --git a/include/hw/virtio/virtio-iommu.h b/include/hw/virtio/virtio-iommu.h
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
26
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
27
--- a/include/hw/virtio/virtio-iommu.h
17
--- a/fpu/softfloat.c
28
+++ b/include/hw/virtio/virtio-iommu.h
18
+++ b/fpu/softfloat.c
29
@@ -XXX,XX +XXX,XX @@ typedef struct VirtIOIOMMU {
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
30
GHashTable *as_by_busptr;
20
*zExpPtr = 1 - shiftCount;
31
IOMMUPciBus *iommu_pcibus_by_bus_num[PCI_BUS_MAX];
32
PCIBus *primary_bus;
33
+ ReservedRegion *reserved_regions;
34
+ uint32_t nb_reserved_regions;
35
GTree *domains;
36
QemuMutex mutex;
37
GTree *endpoints;
38
diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/virtio/virtio-iommu.c
41
+++ b/hw/virtio/virtio-iommu.c
42
@@ -XXX,XX +XXX,XX @@
43
44
/* Max size */
45
#define VIOMMU_DEFAULT_QUEUE_SIZE 256
46
+#define VIOMMU_PROBE_SIZE 512
47
48
typedef struct VirtIOIOMMUDomain {
49
uint32_t id;
50
@@ -XXX,XX +XXX,XX @@ static int virtio_iommu_unmap(VirtIOIOMMU *s,
51
return ret;
52
}
21
}
53
22
54
+static ssize_t virtio_iommu_fill_resv_mem_prop(VirtIOIOMMU *s, uint32_t ep,
23
+/*----------------------------------------------------------------------------
55
+ uint8_t *buf, size_t free)
24
+| Takes two extended double-precision floating-point values `a' and `b', one
25
+| of which is a NaN, and returns the appropriate NaN result. If either `a' or
26
+| `b' is a signaling NaN, the invalid exception is raised.
27
+*----------------------------------------------------------------------------*/
28
+
29
+floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
56
+{
30
+{
57
+ struct virtio_iommu_probe_resv_mem prop = {};
31
+ bool aIsLargerSignificand;
58
+ size_t size = sizeof(prop), length = size - sizeof(prop.head), total;
32
+ FloatClass a_cls, b_cls;
59
+ int i;
60
+
33
+
61
+ total = size * s->nb_reserved_regions;
34
+ /* This is not complete, but is good enough for pickNaN. */
35
+ a_cls = (!floatx80_is_any_nan(a)
36
+ ? float_class_normal
37
+ : floatx80_is_signaling_nan(a, status)
38
+ ? float_class_snan
39
+ : float_class_qnan);
40
+ b_cls = (!floatx80_is_any_nan(b)
41
+ ? float_class_normal
42
+ : floatx80_is_signaling_nan(b, status)
43
+ ? float_class_snan
44
+ : float_class_qnan);
62
+
45
+
63
+ if (total > free) {
46
+ if (is_snan(a_cls) || is_snan(b_cls)) {
64
+ return -ENOSPC;
47
+ float_raise(float_flag_invalid, status);
65
+ }
48
+ }
66
+
49
+
67
+ for (i = 0; i < s->nb_reserved_regions; i++) {
50
+ if (status->default_nan_mode) {
68
+ unsigned subtype = s->reserved_regions[i].type;
51
+ return floatx80_default_nan(status);
52
+ }
69
+
53
+
70
+ assert(subtype == VIRTIO_IOMMU_RESV_MEM_T_RESERVED ||
54
+ if (a.low < b.low) {
71
+ subtype == VIRTIO_IOMMU_RESV_MEM_T_MSI);
55
+ aIsLargerSignificand = 0;
72
+ prop.head.type = cpu_to_le16(VIRTIO_IOMMU_PROBE_T_RESV_MEM);
56
+ } else if (b.low < a.low) {
73
+ prop.head.length = cpu_to_le16(length);
57
+ aIsLargerSignificand = 1;
74
+ prop.subtype = subtype;
58
+ } else {
75
+ prop.start = cpu_to_le64(s->reserved_regions[i].low);
59
+ aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
76
+ prop.end = cpu_to_le64(s->reserved_regions[i].high);
60
+ }
77
+
61
+
78
+ memcpy(buf, &prop, size);
62
+ if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
79
+
63
+ if (is_snan(b_cls)) {
80
+ trace_virtio_iommu_fill_resv_property(ep, prop.subtype,
64
+ return floatx80_silence_nan(b, status);
81
+ prop.start, prop.end);
65
+ }
82
+ buf += size;
66
+ return b;
67
+ } else {
68
+ if (is_snan(a_cls)) {
69
+ return floatx80_silence_nan(a, status);
70
+ }
71
+ return a;
83
+ }
72
+ }
84
+ return total;
85
+}
73
+}
86
+
74
+
87
+/**
75
/*----------------------------------------------------------------------------
88
+ * virtio_iommu_probe - Fill the probe request buffer with
76
| Takes an abstract floating-point value having sign `zSign', exponent `zExp',
89
+ * the properties the device is able to return
77
| and extended significand formed by the concatenation of `zSig0' and `zSig1',
90
+ */
78
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
91
+static int virtio_iommu_probe(VirtIOIOMMU *s,
79
index XXXXXXX..XXXXXXX 100644
92
+ struct virtio_iommu_req_probe *req,
80
--- a/fpu/softfloat-specialize.c.inc
93
+ uint8_t *buf)
81
+++ b/fpu/softfloat-specialize.c.inc
94
+{
82
@@ -XXX,XX +XXX,XX @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
95
+ uint32_t ep_id = le32_to_cpu(req->endpoint);
83
return a;
96
+ size_t free = VIOMMU_PROBE_SIZE;
97
+ ssize_t count;
98
+
99
+ if (!virtio_iommu_mr(s, ep_id)) {
100
+ return VIRTIO_IOMMU_S_NOENT;
101
+ }
102
+
103
+ count = virtio_iommu_fill_resv_mem_prop(s, ep_id, buf, free);
104
+ if (count < 0) {
105
+ return VIRTIO_IOMMU_S_INVAL;
106
+ }
107
+ buf += count;
108
+ free -= count;
109
+
110
+ return VIRTIO_IOMMU_S_OK;
111
+}
112
+
113
static int virtio_iommu_iov_to_req(struct iovec *iov,
114
unsigned int iov_cnt,
115
void *req, size_t req_sz)
116
@@ -XXX,XX +XXX,XX @@ virtio_iommu_handle_req(detach)
117
virtio_iommu_handle_req(map)
118
virtio_iommu_handle_req(unmap)
119
120
+static int virtio_iommu_handle_probe(VirtIOIOMMU *s,
121
+ struct iovec *iov,
122
+ unsigned int iov_cnt,
123
+ uint8_t *buf)
124
+{
125
+ struct virtio_iommu_req_probe req;
126
+ int ret = virtio_iommu_iov_to_req(iov, iov_cnt, &req, sizeof(req));
127
+
128
+ return ret ? ret : virtio_iommu_probe(s, &req, buf);
129
+}
130
+
131
static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
132
{
133
VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
134
struct virtio_iommu_req_head head;
135
struct virtio_iommu_req_tail tail = {};
136
+ size_t output_size = sizeof(tail), sz;
137
VirtQueueElement *elem;
138
unsigned int iov_cnt;
139
struct iovec *iov;
140
- size_t sz;
141
+ void *buf = NULL;
142
143
for (;;) {
144
elem = virtqueue_pop(vq, sizeof(VirtQueueElement));
145
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
146
case VIRTIO_IOMMU_T_UNMAP:
147
tail.status = virtio_iommu_handle_unmap(s, iov, iov_cnt);
148
break;
149
+ case VIRTIO_IOMMU_T_PROBE:
150
+ {
151
+ struct virtio_iommu_req_tail *ptail;
152
+
153
+ output_size = s->config.probe_size + sizeof(tail);
154
+ buf = g_malloc0(output_size);
155
+
156
+ ptail = (struct virtio_iommu_req_tail *)
157
+ (buf + s->config.probe_size);
158
+ ptail->status = virtio_iommu_handle_probe(s, iov, iov_cnt, buf);
159
+ }
160
default:
161
tail.status = VIRTIO_IOMMU_S_UNSUPP;
162
}
163
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
164
165
out:
166
sz = iov_from_buf(elem->in_sg, elem->in_num, 0,
167
- &tail, sizeof(tail));
168
- assert(sz == sizeof(tail));
169
+ buf ? buf : &tail, output_size);
170
+ assert(sz == output_size);
171
172
- virtqueue_push(vq, elem, sizeof(tail));
173
+ virtqueue_push(vq, elem, sz);
174
virtio_notify(vdev, vq);
175
g_free(elem);
176
+ g_free(buf);
177
}
178
}
84
}
179
85
180
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp)
86
-/*----------------------------------------------------------------------------
181
s->config.page_size_mask = TARGET_PAGE_MASK;
87
-| Takes two extended double-precision floating-point values `a' and `b', one
182
s->config.input_range.end = -1UL;
88
-| of which is a NaN, and returns the appropriate NaN result. If either `a' or
183
s->config.domain_range.end = 32;
89
-| `b' is a signaling NaN, the invalid exception is raised.
184
+ s->config.probe_size = VIOMMU_PROBE_SIZE;
90
-*----------------------------------------------------------------------------*/
185
91
-
186
virtio_add_feature(&s->features, VIRTIO_RING_F_EVENT_IDX);
92
-floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
187
virtio_add_feature(&s->features, VIRTIO_RING_F_INDIRECT_DESC);
93
-{
188
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp)
94
- bool aIsLargerSignificand;
189
virtio_add_feature(&s->features, VIRTIO_IOMMU_F_MAP_UNMAP);
95
- FloatClass a_cls, b_cls;
190
virtio_add_feature(&s->features, VIRTIO_IOMMU_F_BYPASS);
96
-
191
virtio_add_feature(&s->features, VIRTIO_IOMMU_F_MMIO);
97
- /* This is not complete, but is good enough for pickNaN. */
192
+ virtio_add_feature(&s->features, VIRTIO_IOMMU_F_PROBE);
98
- a_cls = (!floatx80_is_any_nan(a)
193
99
- ? float_class_normal
194
qemu_mutex_init(&s->mutex);
100
- : floatx80_is_signaling_nan(a, status)
195
101
- ? float_class_snan
196
diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events
102
- : float_class_qnan);
197
index XXXXXXX..XXXXXXX 100644
103
- b_cls = (!floatx80_is_any_nan(b)
198
--- a/hw/virtio/trace-events
104
- ? float_class_normal
199
+++ b/hw/virtio/trace-events
105
- : floatx80_is_signaling_nan(b, status)
200
@@ -XXX,XX +XXX,XX @@ virtio_iommu_get_domain(uint32_t domain_id) "Alloc domain=%d"
106
- ? float_class_snan
201
virtio_iommu_put_domain(uint32_t domain_id) "Free domain=%d"
107
- : float_class_qnan);
202
virtio_iommu_translate_out(uint64_t virt_addr, uint64_t phys_addr, uint32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=%d"
108
-
203
virtio_iommu_report_fault(uint8_t reason, uint32_t flags, uint32_t endpoint, uint64_t addr) "FAULT reason=%d flags=%d endpoint=%d address =0x%"PRIx64
109
- if (is_snan(a_cls) || is_snan(b_cls)) {
204
+virtio_iommu_fill_resv_property(uint32_t devid, uint8_t subtype, uint64_t start, uint64_t end) "dev= %d, type=%d start=0x%"PRIx64" end=0x%"PRIx64
110
- float_raise(float_flag_invalid, status);
111
- }
112
-
113
- if (status->default_nan_mode) {
114
- return floatx80_default_nan(status);
115
- }
116
-
117
- if (a.low < b.low) {
118
- aIsLargerSignificand = 0;
119
- } else if (b.low < a.low) {
120
- aIsLargerSignificand = 1;
121
- } else {
122
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
123
- }
124
-
125
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
126
- if (is_snan(b_cls)) {
127
- return floatx80_silence_nan(b, status);
128
- }
129
- return b;
130
- } else {
131
- if (is_snan(a_cls)) {
132
- return floatx80_silence_nan(a, status);
133
- }
134
- return a;
135
- }
136
-}
137
-
138
/*----------------------------------------------------------------------------
139
| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
140
| NaN; otherwise returns 0.
205
--
141
--
206
2.20.1
142
2.34.1
207
208
diff view generated by jsdifflib
New patch
[PULL 66/72] softfloat: Use parts_pick_nan in propagateFloatx80NaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Unpacking and repacking the parts may be slightly more work
4
than we did before, but we get to reuse more code. For a
5
code path handling exceptional values, this is an improvement.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241203203949.483774-8-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
fpu/softfloat.c | 43 +++++--------------------------------------
13
1 file changed, 5 insertions(+), 38 deletions(-)
14
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/fpu/softfloat.c
18
+++ b/fpu/softfloat.c
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
20
21
floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
22
{
23
- bool aIsLargerSignificand;
24
- FloatClass a_cls, b_cls;
25
+ FloatParts128 pa, pb, *pr;
26
27
- /* This is not complete, but is good enough for pickNaN. */
28
- a_cls = (!floatx80_is_any_nan(a)
29
- ? float_class_normal
30
- : floatx80_is_signaling_nan(a, status)
31
- ? float_class_snan
32
- : float_class_qnan);
33
- b_cls = (!floatx80_is_any_nan(b)
34
- ? float_class_normal
35
- : floatx80_is_signaling_nan(b, status)
36
- ? float_class_snan
37
- : float_class_qnan);
38
-
39
- if (is_snan(a_cls) || is_snan(b_cls)) {
40
- float_raise(float_flag_invalid, status);
41
- }
42
-
43
- if (status->default_nan_mode) {
44
+ if (!floatx80_unpack_canonical(&pa, a, status) ||
45
+ !floatx80_unpack_canonical(&pb, b, status)) {
46
return floatx80_default_nan(status);
47
}
48
49
- if (a.low < b.low) {
50
- aIsLargerSignificand = 0;
51
- } else if (b.low < a.low) {
52
- aIsLargerSignificand = 1;
53
- } else {
54
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
55
- }
56
-
57
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
58
- if (is_snan(b_cls)) {
59
- return floatx80_silence_nan(b, status);
60
- }
61
- return b;
62
- } else {
63
- if (is_snan(a_cls)) {
64
- return floatx80_silence_nan(a, status);
65
- }
66
- return a;
67
- }
68
+ pr = parts_pick_nan(&pa, &pb, status);
69
+ return floatx80_round_pack_canonical(pr, status);
70
}
71
72
/*----------------------------------------------------------------------------
73
--
74
2.34.1
diff view generated by jsdifflib
[PULL 09/34] target/arm: kvm: Handle DABT with no valid ISS
[PULL 67/72] softfloat: Inline pickNaN
1
From: Beata Michalska <beata.michalska@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
3
Inline pickNaN into its only caller. This makes one assert
4
exception with no valid ISS info to be decoded. The lack of decode info
4
redundant with the immediately preceding IF.
5
makes it at least tricky to emulate those instruction which is one of the
5
6
(many) reasons why KVM will not even try to do so.
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Add support for handling those by requesting KVM to inject external
8
Message-id: 20241203203949.483774-9-richard.henderson@linaro.org
9
dabt into the quest.
10
11
Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
12
Reviewed-by: Andrew Jones <drjones@redhat.com>
13
Message-id: 20200629114110.30723-2-beata.michalska@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
10
---
16
target/arm/kvm.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
11
fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++----
17
1 file changed, 52 insertions(+)
12
fpu/softfloat-specialize.c.inc | 96 ----------------------------------
18
13
2 files changed, 73 insertions(+), 105 deletions(-)
19
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
14
15
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
20
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/kvm.c
17
--- a/fpu/softfloat-parts.c.inc
22
+++ b/target/arm/kvm.c
18
+++ b/fpu/softfloat-parts.c.inc
23
@@ -XXX,XX +XXX,XX @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
19
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
24
20
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
25
static bool cap_has_mp_state;
21
float_status *s)
26
static bool cap_has_inject_serror_esr;
22
{
27
+static bool cap_has_inject_ext_dabt;
23
+ int cmp, which;
28
24
+
29
static ARMHostCPUFeatures arm_host_cpu_features;
25
if (is_snan(a->cls) || is_snan(b->cls)) {
30
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
31
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s)
32
ret = -EINVAL;
33
}
27
}
34
28
35
+ if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) {
29
if (s->default_nan_mode) {
36
+ if (kvm_vm_enable_cap(s, KVM_CAP_ARM_NISV_TO_USER, 0)) {
30
parts_default_nan(a, s);
37
+ error_report("Failed to enable KVM_CAP_ARM_NISV_TO_USER cap");
31
- } else {
32
- int cmp = frac_cmp(a, b);
33
- if (cmp == 0) {
34
- cmp = a->sign < b->sign;
35
- }
36
+ return a;
37
+ }
38
39
- if (pickNaN(a->cls, b->cls, cmp > 0, s)) {
40
- a = b;
41
- }
42
+ cmp = frac_cmp(a, b);
43
+ if (cmp == 0) {
44
+ cmp = a->sign < b->sign;
45
+ }
46
+
47
+ switch (s->float_2nan_prop_rule) {
48
+ case float_2nan_prop_s_ab:
49
if (is_snan(a->cls)) {
50
- parts_silence_nan(a, s);
51
+ which = 0;
52
+ } else if (is_snan(b->cls)) {
53
+ which = 1;
54
+ } else if (is_qnan(a->cls)) {
55
+ which = 0;
38
+ } else {
56
+ } else {
39
+ /* Set status for supporting the external dabt injection */
57
+ which = 1;
40
+ cap_has_inject_ext_dabt = kvm_check_extension(s,
58
}
41
+ KVM_CAP_ARM_INJECT_EXT_DABT);
59
+ break;
60
+ case float_2nan_prop_s_ba:
61
+ if (is_snan(b->cls)) {
62
+ which = 1;
63
+ } else if (is_snan(a->cls)) {
64
+ which = 0;
65
+ } else if (is_qnan(b->cls)) {
66
+ which = 1;
67
+ } else {
68
+ which = 0;
42
+ }
69
+ }
70
+ break;
71
+ case float_2nan_prop_ab:
72
+ which = is_nan(a->cls) ? 0 : 1;
73
+ break;
74
+ case float_2nan_prop_ba:
75
+ which = is_nan(b->cls) ? 1 : 0;
76
+ break;
77
+ case float_2nan_prop_x87:
78
+ /*
79
+ * This implements x87 NaN propagation rules:
80
+ * SNaN + QNaN => return the QNaN
81
+ * two SNaNs => return the one with the larger significand, silenced
82
+ * two QNaNs => return the one with the larger significand
83
+ * SNaN and a non-NaN => return the SNaN, silenced
84
+ * QNaN and a non-NaN => return the QNaN
85
+ *
86
+ * If we get down to comparing significands and they are the same,
87
+ * return the NaN with the positive sign bit (if any).
88
+ */
89
+ if (is_snan(a->cls)) {
90
+ if (is_snan(b->cls)) {
91
+ which = cmp > 0 ? 0 : 1;
92
+ } else {
93
+ which = is_qnan(b->cls) ? 1 : 0;
94
+ }
95
+ } else if (is_qnan(a->cls)) {
96
+ if (is_snan(b->cls) || !is_qnan(b->cls)) {
97
+ which = 0;
98
+ } else {
99
+ which = cmp > 0 ? 0 : 1;
100
+ }
101
+ } else {
102
+ which = 1;
103
+ }
104
+ break;
105
+ default:
106
+ g_assert_not_reached();
43
+ }
107
+ }
44
+
108
+
45
return ret;
109
+ if (which) {
110
+ a = b;
111
+ }
112
+ if (is_snan(a->cls)) {
113
+ parts_silence_nan(a, s);
114
}
115
return a;
46
}
116
}
47
117
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
48
@@ -XXX,XX +XXX,XX @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state)
118
index XXXXXXX..XXXXXXX 100644
119
--- a/fpu/softfloat-specialize.c.inc
120
+++ b/fpu/softfloat-specialize.c.inc
121
@@ -XXX,XX +XXX,XX @@ bool float32_is_signaling_nan(float32 a_, float_status *status)
49
}
122
}
50
}
123
}
51
124
52
+/**
125
-/*----------------------------------------------------------------------------
53
+ * kvm_arm_handle_dabt_nisv:
126
-| Select which NaN to propagate for a two-input operation.
54
+ * @cs: CPUState
127
-| IEEE754 doesn't specify all the details of this, so the
55
+ * @esr_iss: ISS encoding (limited) for the exception from Data Abort
128
-| algorithm is target-specific.
56
+ * ISV bit set to '0b0' -> no valid instruction syndrome
129
-| The routine is passed various bits of information about the
57
+ * @fault_ipa: faulting address for the synchronous data abort
130
-| two NaNs and should return 0 to select NaN a and 1 for NaN b.
58
+ *
131
-| Note that signalling NaNs are always squashed to quiet NaNs
59
+ * Returns: 0 if the exception has been handled, < 0 otherwise
132
-| by the caller, by calling floatXX_silence_nan() before
60
+ */
133
-| returning them.
61
+static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
134
-|
62
+ uint64_t fault_ipa)
135
-| aIsLargerSignificand is only valid if both a and b are NaNs
63
+{
136
-| of some kind, and is true if a has the larger significand,
64
+ /*
137
-| or if both a and b have the same significand but a is
65
+ * Request KVM to inject the external data abort into the guest
138
-| positive but b is negative. It is only needed for the x87
66
+ */
139
-| tie-break rule.
67
+ if (cap_has_inject_ext_dabt) {
140
-*----------------------------------------------------------------------------*/
68
+ struct kvm_vcpu_events events = { };
141
-
69
+ /*
142
-static int pickNaN(FloatClass a_cls, FloatClass b_cls,
70
+ * The external data abort event will be handled immediately by KVM
143
- bool aIsLargerSignificand, float_status *status)
71
+ * using the address fault that triggered the exit on given VCPU.
144
-{
72
+ * Requesting injection of the external data abort does not rely
145
- /*
73
+ * on any other VCPU state. Therefore, in this particular case, the VCPU
146
- * We guarantee not to require the target to tell us how to
74
+ * synchronization can be exceptionally skipped.
147
- * pick a NaN if we're always returning the default NaN.
75
+ */
148
- * But if we're not in default-NaN mode then the target must
76
+ events.exception.ext_dabt_pending = 1;
149
- * specify via set_float_2nan_prop_rule().
77
+ /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */
150
- */
78
+ return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events);
151
- assert(!status->default_nan_mode);
79
+ } else {
152
-
80
+ error_report("Data abort exception triggered by guest memory access "
153
- switch (status->float_2nan_prop_rule) {
81
+ "at physical address: 0x" TARGET_FMT_lx,
154
- case float_2nan_prop_s_ab:
82
+ (target_ulong)fault_ipa);
155
- if (is_snan(a_cls)) {
83
+ error_printf("KVM unable to emulate faulting instruction.\n");
156
- return 0;
84
+ }
157
- } else if (is_snan(b_cls)) {
85
+ return -1;
158
- return 1;
86
+}
159
- } else if (is_qnan(a_cls)) {
87
+
160
- return 0;
88
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
161
- } else {
89
{
162
- return 1;
90
int ret = 0;
163
- }
91
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
164
- break;
92
ret = EXCP_DEBUG;
165
- case float_2nan_prop_s_ba:
93
} /* otherwise return to guest */
166
- if (is_snan(b_cls)) {
94
break;
167
- return 1;
95
+ case KVM_EXIT_ARM_NISV:
168
- } else if (is_snan(a_cls)) {
96
+ /* External DABT with no valid iss to decode */
169
- return 0;
97
+ ret = kvm_arm_handle_dabt_nisv(cs, run->arm_nisv.esr_iss,
170
- } else if (is_qnan(b_cls)) {
98
+ run->arm_nisv.fault_ipa);
171
- return 1;
99
+ break;
172
- } else {
100
default:
173
- return 0;
101
qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
174
- }
102
__func__, run->exit_reason);
175
- break;
176
- case float_2nan_prop_ab:
177
- if (is_nan(a_cls)) {
178
- return 0;
179
- } else {
180
- return 1;
181
- }
182
- break;
183
- case float_2nan_prop_ba:
184
- if (is_nan(b_cls)) {
185
- return 1;
186
- } else {
187
- return 0;
188
- }
189
- break;
190
- case float_2nan_prop_x87:
191
- /*
192
- * This implements x87 NaN propagation rules:
193
- * SNaN + QNaN => return the QNaN
194
- * two SNaNs => return the one with the larger significand, silenced
195
- * two QNaNs => return the one with the larger significand
196
- * SNaN and a non-NaN => return the SNaN, silenced
197
- * QNaN and a non-NaN => return the QNaN
198
- *
199
- * If we get down to comparing significands and they are the same,
200
- * return the NaN with the positive sign bit (if any).
201
- */
202
- if (is_snan(a_cls)) {
203
- if (is_snan(b_cls)) {
204
- return aIsLargerSignificand ? 0 : 1;
205
- }
206
- return is_qnan(b_cls) ? 1 : 0;
207
- } else if (is_qnan(a_cls)) {
208
- if (is_snan(b_cls) || !is_qnan(b_cls)) {
209
- return 0;
210
- } else {
211
- return aIsLargerSignificand ? 0 : 1;
212
- }
213
- } else {
214
- return 1;
215
- }
216
- default:
217
- g_assert_not_reached();
218
- }
219
-}
220
-
221
/*----------------------------------------------------------------------------
222
| Returns 1 if the double-precision floating-point value `a' is a quiet
223
| NaN; otherwise returns 0.
103
--
224
--
104
2.20.1
225
2.34.1
105
226
106
227
diff view generated by jsdifflib
[PULL 08/34] hw/arm/virt: Let the virtio-iommu bypass MSIs
[PULL 68/72] softfloat: Share code between parts_pick_nan cases
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
At the moment the virtio-iommu translates MSI transactions.
3
Remember if there was an SNaN, and use that to simplify
4
This behavior is inherited from ARM SMMU. The virt machine
4
float_2nan_prop_s_{ab,ba} to only the snan component.
5
code knows where the guest MSI doorbells are so we can easily
5
Then, fall through to the corresponding
6
declare those regions as VIRTIO_IOMMU_RESV_MEM_T_MSI. With that
6
float_2nan_prop_{ab,ba} case to handle any remaining
7
setting the guest will not map MSIs through the IOMMU and those
7
nans, which must be quiet.
8
transactions will be simply bypassed.
9
8
10
Depending on which MSI controller is in use (ITS or GICV2M),
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
we declare either:
12
- the ITS interrupt translation space (ITS_base + 0x10000),
13
containing the GITS_TRANSLATOR or
14
- The GICV2M single frame, containing the MSI_SETSP_NS register.
15
16
Signed-off-by: Eric Auger <eric.auger@redhat.com>
17
Message-id: 20200629070404.10969-6-eric.auger@redhat.com
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20241203203949.483774-10-richard.henderson@linaro.org
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
13
---
21
include/hw/arm/virt.h | 7 +++++++
14
fpu/softfloat-parts.c.inc | 32 ++++++++++++--------------------
22
hw/arm/virt.c | 30 ++++++++++++++++++++++++++++++
15
1 file changed, 12 insertions(+), 20 deletions(-)
23
2 files changed, 37 insertions(+)
24
16
25
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
26
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
27
--- a/include/hw/arm/virt.h
19
--- a/fpu/softfloat-parts.c.inc
28
+++ b/include/hw/arm/virt.h
20
+++ b/fpu/softfloat-parts.c.inc
29
@@ -XXX,XX +XXX,XX @@ typedef enum VirtIOMMUType {
21
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
30
VIRT_IOMMU_VIRTIO,
22
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
31
} VirtIOMMUType;
23
float_status *s)
32
24
{
33
+typedef enum VirtMSIControllerType {
25
+ bool have_snan = false;
34
+ VIRT_MSI_CTRL_NONE,
26
int cmp, which;
35
+ VIRT_MSI_CTRL_GICV2M,
27
36
+ VIRT_MSI_CTRL_ITS,
28
if (is_snan(a->cls) || is_snan(b->cls)) {
37
+} VirtMSIControllerType;
29
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
38
+
30
+ have_snan = true;
39
typedef enum VirtGICType {
40
VIRT_GIC_VERSION_MAX,
41
VIRT_GIC_VERSION_HOST,
42
@@ -XXX,XX +XXX,XX @@ typedef struct {
43
OnOffAuto acpi;
44
VirtGICType gic_version;
45
VirtIOMMUType iommu;
46
+ VirtMSIControllerType msi_controller;
47
uint16_t virtio_iommu_bdf;
48
struct arm_boot_info bootinfo;
49
MemMapEntry *memmap;
50
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/hw/arm/virt.c
53
+++ b/hw/arm/virt.c
54
@@ -XXX,XX +XXX,XX @@ static void create_its(VirtMachineState *vms)
55
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
56
57
fdt_add_its_gic_node(vms);
58
+ vms->msi_controller = VIRT_MSI_CTRL_ITS;
59
}
60
61
static void create_v2m(VirtMachineState *vms)
62
@@ -XXX,XX +XXX,XX @@ static void create_v2m(VirtMachineState *vms)
63
}
31
}
64
32
65
fdt_add_v2m_gic_node(vms);
33
if (s->default_nan_mode) {
66
+ vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
34
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
67
}
35
68
36
switch (s->float_2nan_prop_rule) {
69
static void create_gic(VirtMachineState *vms)
37
case float_2nan_prop_s_ab:
70
@@ -XXX,XX +XXX,XX @@ out:
38
- if (is_snan(a->cls)) {
71
static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
39
- which = 0;
72
DeviceState *dev, Error **errp)
40
- } else if (is_snan(b->cls)) {
73
{
41
- which = 1;
74
+ VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
42
- } else if (is_qnan(a->cls)) {
75
+
43
- which = 0;
76
if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
44
- } else {
77
virt_memory_pre_plug(hotplug_dev, dev, errp);
45
- which = 1;
78
+ } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
46
+ if (have_snan) {
79
+ hwaddr db_start = 0, db_end = 0;
47
+ which = is_snan(a->cls) ? 0 : 1;
80
+ char *resv_prop_str;
81
+
82
+ switch (vms->msi_controller) {
83
+ case VIRT_MSI_CTRL_NONE:
84
+ return;
85
+ case VIRT_MSI_CTRL_ITS:
86
+ /* GITS_TRANSLATER page */
87
+ db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
88
+ db_end = base_memmap[VIRT_GIC_ITS].base +
89
+ base_memmap[VIRT_GIC_ITS].size - 1;
90
+ break;
48
+ break;
91
+ case VIRT_MSI_CTRL_GICV2M:
49
}
92
+ /* MSI_SETSPI_NS page */
50
- break;
93
+ db_start = base_memmap[VIRT_GIC_V2M].base;
51
- case float_2nan_prop_s_ba:
94
+ db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
52
- if (is_snan(b->cls)) {
53
- which = 1;
54
- } else if (is_snan(a->cls)) {
55
- which = 0;
56
- } else if (is_qnan(b->cls)) {
57
- which = 1;
58
- } else {
59
- which = 0;
60
- }
61
- break;
62
+ /* fall through */
63
case float_2nan_prop_ab:
64
which = is_nan(a->cls) ? 0 : 1;
65
break;
66
+ case float_2nan_prop_s_ba:
67
+ if (have_snan) {
68
+ which = is_snan(b->cls) ? 1 : 0;
95
+ break;
69
+ break;
96
+ }
70
+ }
97
+ resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
71
+ /* fall through */
98
+ db_start, db_end,
72
case float_2nan_prop_ba:
99
+ VIRTIO_IOMMU_RESV_MEM_T_MSI);
73
which = is_nan(b->cls) ? 1 : 0;
100
+
74
break;
101
+ qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
102
+ qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
103
+ g_free(resv_prop_str);
104
}
105
}
106
107
--
75
--
108
2.20.1
76
2.34.1
109
110
diff view generated by jsdifflib
[PULL 07/34] virtio-iommu-pci: Add array of Interval properties
[PULL 69/72] softfloat: Sink frac_cmp in parts_pick_nan until needed
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The machine may need to pass reserved regions to the
3
Move the fractional comparison to the end of the
4
virtio-iommu-pci device (such as the MSI window on x86
4
float_2nan_prop_x87 case. This is not required for
5
or the MSI doorbells on ARM).
5
any other 2nan propagation rule. Reorganize the
6
x87 case itself to break out of the switch when the
7
fractional comparison is not required.
6
8
7
So let's add an array of Interval properties.
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Note: if some reserved regions are already set by the
11
Message-id: 20241203203949.483774-11-richard.henderson@linaro.org
10
machine code - which should be the case in general -,
11
the length of the property array is already set and
12
prevents the end-user from modifying them. For example,
13
attempting to use:
14
15
-device virtio-iommu-pci,\
16
len-reserved-regions=1,reserved-regions[0]=0xfee00000:0xfeefffff:1
17
18
would result in the following error message:
19
20
qemu-system-aarch64: -device virtio-iommu-pci,addr=0xa,
21
len-reserved-regions=1,reserved-regions[0]=0xfee00000:0xfeefffff:1:
22
array size property len-reserved-regions may not be set more than once
23
24
Otherwise, for example, adding two reserved regions is achieved
25
using the following options:
26
27
-device virtio-iommu-pci,addr=0xa,len-reserved-regions=2,\
28
reserved-regions[0]=0xfee00000:0xfeefffff:1,\
29
reserved-regions[1]=0x1000000:100ffff:1
30
31
Signed-off-by: Eric Auger <eric.auger@redhat.com>
32
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
33
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
34
Reviewed-by: Peter Xu <peterx@redhat.com>
35
Message-id: 20200629070404.10969-5-eric.auger@redhat.com
36
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
37
---
13
---
38
hw/virtio/virtio-iommu-pci.c | 11 +++++++++++
14
fpu/softfloat-parts.c.inc | 19 +++++++++----------
39
1 file changed, 11 insertions(+)
15
1 file changed, 9 insertions(+), 10 deletions(-)
40
16
41
diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
42
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/virtio/virtio-iommu-pci.c
19
--- a/fpu/softfloat-parts.c.inc
44
+++ b/hw/virtio/virtio-iommu-pci.c
20
+++ b/fpu/softfloat-parts.c.inc
45
@@ -XXX,XX +XXX,XX @@ struct VirtIOIOMMUPCI {
21
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
46
22
return a;
47
static Property virtio_iommu_pci_properties[] = {
48
DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0),
49
+ DEFINE_PROP_ARRAY("reserved-regions", VirtIOIOMMUPCI,
50
+ vdev.nb_reserved_regions, vdev.reserved_regions,
51
+ qdev_prop_reserved_region, ReservedRegion),
52
DEFINE_PROP_END_OF_LIST(),
53
};
54
55
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
56
{
57
VirtIOIOMMUPCI *dev = VIRTIO_IOMMU_PCI(vpci_dev);
58
DeviceState *vdev = DEVICE(&dev->vdev);
59
+ VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
60
61
if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) {
62
MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
63
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
64
"-no-acpi\n");
65
return;
66
}
23
}
67
+ for (int i = 0; i < s->nb_reserved_regions; i++) {
24
68
+ if (s->reserved_regions[i].type != VIRTIO_IOMMU_RESV_MEM_T_RESERVED &&
25
- cmp = frac_cmp(a, b);
69
+ s->reserved_regions[i].type != VIRTIO_IOMMU_RESV_MEM_T_MSI) {
26
- if (cmp == 0) {
70
+ error_setg(errp, "reserved region %d has an invalid type", i);
27
- cmp = a->sign < b->sign;
71
+ error_append_hint(errp, "Valid values are 0 and 1\n");
28
- }
29
-
30
switch (s->float_2nan_prop_rule) {
31
case float_2nan_prop_s_ab:
32
if (have_snan) {
33
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
34
* return the NaN with the positive sign bit (if any).
35
*/
36
if (is_snan(a->cls)) {
37
- if (is_snan(b->cls)) {
38
- which = cmp > 0 ? 0 : 1;
39
- } else {
40
+ if (!is_snan(b->cls)) {
41
which = is_qnan(b->cls) ? 1 : 0;
42
+ break;
43
}
44
} else if (is_qnan(a->cls)) {
45
if (is_snan(b->cls) || !is_qnan(b->cls)) {
46
which = 0;
47
- } else {
48
- which = cmp > 0 ? 0 : 1;
49
+ break;
50
}
51
} else {
52
which = 1;
53
+ break;
54
}
55
+ cmp = frac_cmp(a, b);
56
+ if (cmp == 0) {
57
+ cmp = a->sign < b->sign;
72
+ }
58
+ }
73
+ }
59
+ which = cmp > 0 ? 0 : 1;
74
object_property_set_link(OBJECT(dev),
60
break;
75
OBJECT(pci_get_bus(&vpci_dev->pci_dev)),
61
default:
76
"primary-bus", &error_abort);
62
g_assert_not_reached();
77
--
63
--
78
2.20.1
64
2.34.1
79
80
diff view generated by jsdifflib
[PULL 02/34] Add the ability to select a different PHY for each i.MX6UL FEC interface
[PULL 70/72] softfloat: Replace WHICH with RET in parts_pick_nan
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add properties to the i.MX6UL processor to be able to select a
3
Replace the "index" selecting between A and B with a result variable
4
particular PHY on the MDIO bus for each FEC device.
4
of the proper type. This improves clarity within the function.
5
5
6
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: ea1d604198b6b73ea6521676e45bacfc597aba53.1593296112.git.jcd@tribudubois.net
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-12-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
include/hw/arm/fsl-imx6ul.h | 2 ++
11
fpu/softfloat-parts.c.inc | 28 +++++++++++++---------------
12
hw/arm/fsl-imx6ul.c | 10 ++++++++++
12
1 file changed, 13 insertions(+), 15 deletions(-)
13
2 files changed, 12 insertions(+)
14
13
15
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/fsl-imx6ul.h
16
--- a/fpu/softfloat-parts.c.inc
18
+++ b/include/hw/arm/fsl-imx6ul.h
17
+++ b/fpu/softfloat-parts.c.inc
19
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6ULState {
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
20
MemoryRegion caam;
19
float_status *s)
21
MemoryRegion ocram;
20
{
22
MemoryRegion ocram_alias;
21
bool have_snan = false;
23
+
22
- int cmp, which;
24
+ uint32_t phy_num[FSL_IMX6UL_NUM_ETHS];
23
+ FloatPartsN *ret;
25
} FslIMX6ULState;
24
+ int cmp;
26
25
27
enum FslIMX6ULMemoryMap {
26
if (is_snan(a->cls) || is_snan(b->cls)) {
28
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
27
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
29
index XXXXXXX..XXXXXXX 100644
28
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
30
--- a/hw/arm/fsl-imx6ul.c
29
switch (s->float_2nan_prop_rule) {
31
+++ b/hw/arm/fsl-imx6ul.c
30
case float_2nan_prop_s_ab:
32
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
31
if (have_snan) {
33
FSL_IMX6UL_ENET2_TIMER_IRQ,
32
- which = is_snan(a->cls) ? 0 : 1;
34
};
33
+ ret = is_snan(a->cls) ? a : b;
35
34
break;
36
+ object_property_set_uint(OBJECT(&s->eth[i]),
35
}
37
+ s->phy_num[i],
36
/* fall through */
38
+ "phy-num", &error_abort);
37
case float_2nan_prop_ab:
39
object_property_set_uint(OBJECT(&s->eth[i]),
38
- which = is_nan(a->cls) ? 0 : 1;
40
FSL_IMX6UL_ETH_NUM_TX_RINGS,
39
+ ret = is_nan(a->cls) ? a : b;
41
"tx-ring-num", &error_abort);
40
break;
42
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
41
case float_2nan_prop_s_ba:
43
FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias);
42
if (have_snan) {
43
- which = is_snan(b->cls) ? 1 : 0;
44
+ ret = is_snan(b->cls) ? b : a;
45
break;
46
}
47
/* fall through */
48
case float_2nan_prop_ba:
49
- which = is_nan(b->cls) ? 1 : 0;
50
+ ret = is_nan(b->cls) ? b : a;
51
break;
52
case float_2nan_prop_x87:
53
/*
54
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
55
*/
56
if (is_snan(a->cls)) {
57
if (!is_snan(b->cls)) {
58
- which = is_qnan(b->cls) ? 1 : 0;
59
+ ret = is_qnan(b->cls) ? b : a;
60
break;
61
}
62
} else if (is_qnan(a->cls)) {
63
if (is_snan(b->cls) || !is_qnan(b->cls)) {
64
- which = 0;
65
+ ret = a;
66
break;
67
}
68
} else {
69
- which = 1;
70
+ ret = b;
71
break;
72
}
73
cmp = frac_cmp(a, b);
74
if (cmp == 0) {
75
cmp = a->sign < b->sign;
76
}
77
- which = cmp > 0 ? 0 : 1;
78
+ ret = cmp > 0 ? a : b;
79
break;
80
default:
81
g_assert_not_reached();
82
}
83
84
- if (which) {
85
- a = b;
86
+ if (is_snan(ret->cls)) {
87
+ parts_silence_nan(ret, s);
88
}
89
- if (is_snan(a->cls)) {
90
- parts_silence_nan(a, s);
91
- }
92
- return a;
93
+ return ret;
44
}
94
}
45
95
46
+static Property fsl_imx6ul_properties[] = {
96
static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
47
+ DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0),
48
+ DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1),
49
+ DEFINE_PROP_END_OF_LIST(),
50
+};
51
+
52
static void fsl_imx6ul_class_init(ObjectClass *oc, void *data)
53
{
54
DeviceClass *dc = DEVICE_CLASS(oc);
55
56
+ device_class_set_props(dc, fsl_imx6ul_properties);
57
dc->realize = fsl_imx6ul_realize;
58
dc->desc = "i.MX6UL SOC";
59
/* Reason: Uses serial_hds and nd_table in realize() directly */
60
--
97
--
61
2.20.1
98
2.34.1
62
99
63
100
diff view generated by jsdifflib
[PULL 04/34] qdev: Introduce DEFINE_PROP_RESERVED_REGION
[PULL 71/72] MAINTAINERS: update email address for Leif Lindholm
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
2
2
3
Introduce a new property defining a reserved region:
3
I'm migrating to Qualcomm's new open source email infrastructure, so
4
<low address>:<high address>:<type>.
4
update my email address, and update the mailmap to match.
5
5
6
This will be used to encode reserved IOVA regions.
6
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
7
7
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
8
For instance, in virtio-iommu use case, reserved IOVA regions
8
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
9
will be passed by the machine code to the virtio-iommu-pci
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
device (an array of those). The type of the reserved region
10
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
will match the virtio_iommu_probe_resv_mem subtype value:
11
Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com
12
- VIRTIO_IOMMU_RESV_MEM_T_RESERVED (0)
13
- VIRTIO_IOMMU_RESV_MEM_T_MSI (1)
14
15
on PC/Q35 machine, this will be used to inform the
16
virtio-iommu-pci device it should bypass the MSI region.
17
The reserved region will be: 0xfee00000:0xfeefffff:1.
18
19
On ARM, we can declare the ITS MSI doorbell as an MSI
20
region to prevent MSIs from being mapped on guest side.
21
22
Signed-off-by: Eric Auger <eric.auger@redhat.com>
23
Reviewed-by: Markus Armbruster <armbru@redhat.com>
24
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
25
Message-id: 20200629070404.10969-2-eric.auger@redhat.com
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
---
13
---
28
include/exec/memory.h | 6 +++
14
MAINTAINERS | 2 +-
29
include/hw/qdev-properties.h | 3 ++
15
.mailmap | 5 +++--
30
include/qemu/typedefs.h | 1 +
16
2 files changed, 4 insertions(+), 3 deletions(-)
31
hw/core/qdev-properties.c | 89 ++++++++++++++++++++++++++++++++++++
32
4 files changed, 99 insertions(+)
33
17
34
diff --git a/include/exec/memory.h b/include/exec/memory.h
18
diff --git a/MAINTAINERS b/MAINTAINERS
35
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
36
--- a/include/exec/memory.h
20
--- a/MAINTAINERS
37
+++ b/include/exec/memory.h
21
+++ b/MAINTAINERS
38
@@ -XXX,XX +XXX,XX @@ extern bool global_dirty_log;
22
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
39
23
SBSA-REF
40
typedef struct MemoryRegionOps MemoryRegionOps;
24
M: Radoslaw Biernacki <rad@semihalf.com>
41
25
M: Peter Maydell <peter.maydell@linaro.org>
42
+struct ReservedRegion {
26
-R: Leif Lindholm <quic_llindhol@quicinc.com>
43
+ hwaddr low;
27
+R: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
44
+ hwaddr high;
28
R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
45
+ unsigned type;
29
L: qemu-arm@nongnu.org
46
+};
30
S: Maintained
47
+
31
diff --git a/.mailmap b/.mailmap
48
typedef struct IOMMUTLBEntry IOMMUTLBEntry;
49
50
/* See address_space_translate: bit 0 is read, bit 1 is write. */
51
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
52
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
53
--- a/include/hw/qdev-properties.h
33
--- a/.mailmap
54
+++ b/include/hw/qdev-properties.h
34
+++ b/.mailmap
55
@@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_string;
35
@@ -XXX,XX +XXX,XX @@ Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
56
extern const PropertyInfo qdev_prop_chr;
36
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
57
extern const PropertyInfo qdev_prop_tpm;
37
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
58
extern const PropertyInfo qdev_prop_macaddr;
38
Juan Quintela <quintela@trasno.org> <quintela@redhat.com>
59
+extern const PropertyInfo qdev_prop_reserved_region;
39
-Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
60
extern const PropertyInfo qdev_prop_on_off_auto;
40
-Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
61
extern const PropertyInfo qdev_prop_multifd_compression;
41
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <quic_llindhol@quicinc.com>
62
extern const PropertyInfo qdev_prop_losttickpolicy;
42
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif.lindholm@linaro.org>
63
@@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_pcie_link_width;
43
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif@nuviainc.com>
64
DEFINE_PROP(_n, _s, _f, qdev_prop_drive_iothread, BlockBackend *)
44
Luc Michel <luc@lmichel.fr> <luc.michel@git.antfield.fr>
65
#define DEFINE_PROP_MACADDR(_n, _s, _f) \
45
Luc Michel <luc@lmichel.fr> <luc.michel@greensocs.com>
66
DEFINE_PROP(_n, _s, _f, qdev_prop_macaddr, MACAddr)
46
Luc Michel <luc@lmichel.fr> <lmichel@kalray.eu>
67
+#define DEFINE_PROP_RESERVED_REGION(_n, _s, _f) \
68
+ DEFINE_PROP(_n, _s, _f, qdev_prop_reserved_region, ReservedRegion)
69
#define DEFINE_PROP_ON_OFF_AUTO(_n, _s, _f, _d) \
70
DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_on_off_auto, OnOffAuto)
71
#define DEFINE_PROP_MULTIFD_COMPRESSION(_n, _s, _f, _d) \
72
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
73
index XXXXXXX..XXXXXXX 100644
74
--- a/include/qemu/typedefs.h
75
+++ b/include/qemu/typedefs.h
76
@@ -XXX,XX +XXX,XX @@ typedef struct ISABus ISABus;
77
typedef struct ISADevice ISADevice;
78
typedef struct IsaDma IsaDma;
79
typedef struct MACAddr MACAddr;
80
+typedef struct ReservedRegion ReservedRegion;
81
typedef struct MachineClass MachineClass;
82
typedef struct MachineState MachineState;
83
typedef struct MemoryListener MemoryListener;
84
diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/hw/core/qdev-properties.c
87
+++ b/hw/core/qdev-properties.c
88
@@ -XXX,XX +XXX,XX @@
89
#include "chardev/char.h"
90
#include "qemu/uuid.h"
91
#include "qemu/units.h"
92
+#include "qemu/cutils.h"
93
94
void qdev_prop_set_after_realize(DeviceState *dev, const char *name,
95
Error **errp)
96
@@ -XXX,XX +XXX,XX @@ const PropertyInfo qdev_prop_macaddr = {
97
.set = set_mac,
98
};
99
100
+/* --- Reserved Region --- */
101
+
102
+/*
103
+ * Accepted syntax:
104
+ * <low address>:<high address>:<type>
105
+ * where low/high addresses are uint64_t in hexadecimal
106
+ * and type is a non-negative decimal integer
107
+ */
108
+static void get_reserved_region(Object *obj, Visitor *v, const char *name,
109
+ void *opaque, Error **errp)
110
+{
111
+ DeviceState *dev = DEVICE(obj);
112
+ Property *prop = opaque;
113
+ ReservedRegion *rr = qdev_get_prop_ptr(dev, prop);
114
+ char buffer[64];
115
+ char *p = buffer;
116
+ int rc;
117
+
118
+ rc = snprintf(buffer, sizeof(buffer), "0x%"PRIx64":0x%"PRIx64":%u",
119
+ rr->low, rr->high, rr->type);
120
+ assert(rc < sizeof(buffer));
121
+
122
+ visit_type_str(v, name, &p, errp);
123
+}
124
+
125
+static void set_reserved_region(Object *obj, Visitor *v, const char *name,
126
+ void *opaque, Error **errp)
127
+{
128
+ DeviceState *dev = DEVICE(obj);
129
+ Property *prop = opaque;
130
+ ReservedRegion *rr = qdev_get_prop_ptr(dev, prop);
131
+ Error *local_err = NULL;
132
+ const char *endptr;
133
+ char *str;
134
+ int ret;
135
+
136
+ if (dev->realized) {
137
+ qdev_prop_set_after_realize(dev, name, errp);
138
+ return;
139
+ }
140
+
141
+ visit_type_str(v, name, &str, &local_err);
142
+ if (local_err) {
143
+ error_propagate(errp, local_err);
144
+ return;
145
+ }
146
+
147
+ ret = qemu_strtou64(str, &endptr, 16, &rr->low);
148
+ if (ret) {
149
+ error_setg(errp, "start address of '%s'"
150
+ " must be a hexadecimal integer", name);
151
+ goto out;
152
+ }
153
+ if (*endptr != ':') {
154
+ goto separator_error;
155
+ }
156
+
157
+ ret = qemu_strtou64(endptr + 1, &endptr, 16, &rr->high);
158
+ if (ret) {
159
+ error_setg(errp, "end address of '%s'"
160
+ " must be a hexadecimal integer", name);
161
+ goto out;
162
+ }
163
+ if (*endptr != ':') {
164
+ goto separator_error;
165
+ }
166
+
167
+ ret = qemu_strtoui(endptr + 1, &endptr, 10, &rr->type);
168
+ if (ret) {
169
+ error_setg(errp, "type of '%s'"
170
+ " must be a non-negative decimal integer", name);
171
+ }
172
+ goto out;
173
+
174
+separator_error:
175
+ error_setg(errp, "reserved region fields must be separated with ':'");
176
+out:
177
+ g_free(str);
178
+ return;
179
+}
180
+
181
+const PropertyInfo qdev_prop_reserved_region = {
182
+ .name = "reserved_region",
183
+ .description = "Reserved Region, example: 0xFEE00000:0xFEEFFFFF:0",
184
+ .get = get_reserved_region,
185
+ .set = set_reserved_region,
186
+};
187
+
188
/* --- on/off/auto --- */
189
190
const PropertyInfo qdev_prop_on_off_auto = {
191
--
47
--
192
2.20.1
48
2.34.1
193
49
194
50
diff view generated by jsdifflib
[PULL 03/34] Select MDIO device 2 and 1 as PHY devices for i.MX6UL EVK board.
[PULL 72/72] MAINTAINERS: Add correct email address for Vikram Garhwal
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
From: Vikram Garhwal <vikram.garhwal@bytedance.com>
2
2
3
The i.MX6UL EVK 14x14 board uses:
3
Previously, maintainer role was paused due to inactive email id. Commit id:
4
- PHY 2 for FEC 1
4
c009d715721861984c4987bcc78b7ee183e86d75.
5
- PHY 1 for FEC 2
6
5
7
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
6
Signed-off-by: Vikram Garhwal <vikram.garhwal@bytedance.com>
8
Message-id: fb41992126c091a71d76ab3d1898959091f60583.1593296112.git.jcd@tribudubois.net
7
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
hw/arm/mcimx6ul-evk.c | 2 ++
11
MAINTAINERS | 2 ++
13
1 file changed, 2 insertions(+)
12
1 file changed, 2 insertions(+)
14
13
15
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
14
diff --git a/MAINTAINERS b/MAINTAINERS
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/mcimx6ul-evk.c
16
--- a/MAINTAINERS
18
+++ b/hw/arm/mcimx6ul-evk.c
17
+++ b/MAINTAINERS
19
@@ -XXX,XX +XXX,XX @@ static void mcimx6ul_evk_init(MachineState *machine)
18
@@ -XXX,XX +XXX,XX @@ F: tests/qtest/fuzz-sb16-test.c
20
19
21
s = FSL_IMX6UL(object_new(TYPE_FSL_IMX6UL));
20
Xilinx CAN
22
object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
21
M: Francisco Iglesias <francisco.iglesias@amd.com>
23
+ object_property_set_uint(OBJECT(s), 2, "fec1-phy-num", &error_fatal);
22
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
24
+ object_property_set_uint(OBJECT(s), 1, "fec2-phy-num", &error_fatal);
23
S: Maintained
25
qdev_realize(DEVICE(s), NULL, &error_fatal);
24
F: hw/net/can/xlnx-*
26
25
F: include/hw/net/xlnx-*
27
memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_MMDC_ADDR,
26
@@ -XXX,XX +XXX,XX @@ F: include/hw/rx/
27
CAN bus subsystem and hardware
28
M: Pavel Pisa <pisa@cmp.felk.cvut.cz>
29
M: Francisco Iglesias <francisco.iglesias@amd.com>
30
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
31
S: Maintained
32
W: https://canbus.pages.fel.cvut.cz/
33
F: net/can/*
28
--
34
--
29
2.20.1
35
2.34.1
30
31
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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