[PULL v2 00/64] riscv-to-apply queue

Alistair Francis posted 64 patches 3 years, 9 months ago
Test FreeBSD passed
Test docker-quick@centos7 passed
Test checkpatch failed
Test docker-mingw@fedora passed
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20200702162354.928528-1-alistair.francis@wdc.com
Maintainers: Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>
There is a newer version of this series
target/riscv/cpu.h                      |   82 +-
target/riscv/cpu_bits.h                 |   15 +
target/riscv/helper.h                   | 1069 +++++++
target/riscv/internals.h                |   41 +
target/riscv/insn32-64.decode           |   11 +
target/riscv/insn32.decode              |  372 +++
hw/riscv/sifive_clint.c                 |    2 +-
hw/riscv/sifive_plic.c                  |   20 +-
target/riscv/cpu.c                      |   50 +
target/riscv/csr.c                      |   75 +-
target/riscv/fpu_helper.c               |   33 +-
target/riscv/insn_trans/trans_rvv.inc.c | 2888 ++++++++++++++++++
target/riscv/translate.c                |   27 +-
target/riscv/vector_helper.c            | 4899 +++++++++++++++++++++++++++++++
target/riscv/Makefile.objs              |    2 +-
15 files changed, 9535 insertions(+), 51 deletions(-)
create mode 100644 target/riscv/internals.h
create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
create mode 100644 target/riscv/vector_helper.c
[PULL v2 00/64] riscv-to-apply queue
Posted by Alistair Francis 3 years, 9 months ago
The following changes since commit 64f0ad8ad8e13257e7c912df470d46784b55c3fd:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2020-07-02' into staging (2020-07-02 15:54:09 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200702-1

for you to fetch changes up to 6bf91617f47c74efc99ef48236765d9677c0898e:

  target/riscv: configure and turn on vector extension from command line (2020-07-02 09:19:34 -0700)

----------------------------------------------------------------
This PR contains two patches to improve PLIC support in QEMU.

It also contains one patch that fixes CLINT accesses for RISC-V. This
fixes a regression for most RISC-V boards.

The rest of the PR is adding support for the v0.7.1 RISC-V vector
extensions. This is experimental support as the vector extensions are
still in a draft state.

This is a v2 pull request that has fixed the building on big endian
machines failure.

----------------------------------------------------------------
Alistair Francis (1):
      hw/riscv: Allow 64 bit access to SiFive CLINT

Jessica Clarke (2):
      riscv: plic: Honour source priorities
      riscv: plic: Add a couple of mising sifive_plic_update calls

LIU Zhiwei (61):
      target/riscv: add vector extension field in CPURISCVState
      target/riscv: implementation-defined constant parameters
      target/riscv: support vector extension csr
      target/riscv: add vector configure instruction
      target/riscv: add an internals.h header
      target/riscv: add vector stride load and store instructions
      target/riscv: add vector index load and store instructions
      target/riscv: add fault-only-first unit stride load
      target/riscv: add vector amo operations
      target/riscv: vector single-width integer add and subtract
      target/riscv: vector widening integer add and subtract
      target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
      target/riscv: vector bitwise logical instructions
      target/riscv: vector single-width bit shift instructions
      target/riscv: vector narrowing integer right shift instructions
      target/riscv: vector integer comparison instructions
      target/riscv: vector integer min/max instructions
      target/riscv: vector single-width integer multiply instructions
      target/riscv: vector integer divide instructions
      target/riscv: vector widening integer multiply instructions
      target/riscv: vector single-width integer multiply-add instructions
      target/riscv: vector widening integer multiply-add instructions
      target/riscv: vector integer merge and move instructions
      target/riscv: vector single-width saturating add and subtract
      target/riscv: vector single-width averaging add and subtract
      target/riscv: vector single-width fractional multiply with rounding and saturation
      target/riscv: vector widening saturating scaled multiply-add
      target/riscv: vector single-width scaling shift instructions
      target/riscv: vector narrowing fixed-point clip instructions
      target/riscv: vector single-width floating-point add/subtract instructions
      target/riscv: vector widening floating-point add/subtract instructions
      target/riscv: vector single-width floating-point multiply/divide instructions
      target/riscv: vector widening floating-point multiply
      target/riscv: vector single-width floating-point fused multiply-add instructions
      target/riscv: vector widening floating-point fused multiply-add instructions
      target/riscv: vector floating-point square-root instruction
      target/riscv: vector floating-point min/max instructions
      target/riscv: vector floating-point sign-injection instructions
      target/riscv: vector floating-point compare instructions
      target/riscv: vector floating-point classify instructions
      target/riscv: vector floating-point merge instructions
      target/riscv: vector floating-point/integer type-convert instructions
      target/riscv: widening floating-point/integer type-convert instructions
      target/riscv: narrowing floating-point/integer type-convert instructions
      target/riscv: vector single-width integer reduction instructions
      target/riscv: vector wideing integer reduction instructions
      target/riscv: vector single-width floating-point reduction instructions
      target/riscv: vector widening floating-point reduction instructions
      target/riscv: vector mask-register logical instructions
      target/riscv: vector mask population count vmpopc
      target/riscv: vmfirst find-first-set mask bit
      target/riscv: set-X-first mask bit
      target/riscv: vector iota instruction
      target/riscv: vector element index instruction
      target/riscv: integer extract instruction
      target/riscv: integer scalar move instruction
      target/riscv: floating-point scalar move instructions
      target/riscv: vector slide instructions
      target/riscv: vector register gather instruction
      target/riscv: vector compress instruction
      target/riscv: configure and turn on vector extension from command line

 target/riscv/cpu.h                      |   82 +-
 target/riscv/cpu_bits.h                 |   15 +
 target/riscv/helper.h                   | 1069 +++++++
 target/riscv/internals.h                |   41 +
 target/riscv/insn32-64.decode           |   11 +
 target/riscv/insn32.decode              |  372 +++
 hw/riscv/sifive_clint.c                 |    2 +-
 hw/riscv/sifive_plic.c                  |   20 +-
 target/riscv/cpu.c                      |   50 +
 target/riscv/csr.c                      |   75 +-
 target/riscv/fpu_helper.c               |   33 +-
 target/riscv/insn_trans/trans_rvv.inc.c | 2888 ++++++++++++++++++
 target/riscv/translate.c                |   27 +-
 target/riscv/vector_helper.c            | 4899 +++++++++++++++++++++++++++++++
 target/riscv/Makefile.objs              |    2 +-
 15 files changed, 9535 insertions(+), 51 deletions(-)
 create mode 100644 target/riscv/internals.h
 create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
 create mode 100644 target/riscv/vector_helper.c

Re: [PULL v2 00/64] riscv-to-apply queue
Posted by Peter Maydell 3 years, 9 months ago
On Thu, 2 Jul 2020 at 17:33, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 64f0ad8ad8e13257e7c912df470d46784b55c3fd:
>
>   Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2020-07-02' into staging (2020-07-02 15:54:09 +0100)
>
> are available in the Git repository at:
>
>   git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200702-1
>
> for you to fetch changes up to 6bf91617f47c74efc99ef48236765d9677c0898e:
>
>   target/riscv: configure and turn on vector extension from command line (2020-07-02 09:19:34 -0700)
>
> ----------------------------------------------------------------
> This PR contains two patches to improve PLIC support in QEMU.
>
> It also contains one patch that fixes CLINT accesses for RISC-V. This
> fixes a regression for most RISC-V boards.
>
> The rest of the PR is adding support for the v0.7.1 RISC-V vector
> extensions. This is experimental support as the vector extensions are
> still in a draft state.
>
> This is a v2 pull request that has fixed the building on big endian
> machines failure.
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1
for any user-visible changes.

-- PMM

Re: [PULL v2 00/64] riscv-to-apply queue
Posted by no-reply@patchew.org 3 years, 9 months ago
Patchew URL: https://patchew.org/QEMU/20200702162354.928528-1-alistair.francis@wdc.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PULL v2 00/64] riscv-to-apply queue
Type: series
Message-id: 20200702162354.928528-1-alistair.francis@wdc.com

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20200626205917.4545-1-zhiwei_liu@c-sky.com -> patchew/20200626205917.4545-1-zhiwei_liu@c-sky.com
 - [tag update]      patchew/20200702155000.3455325-1-armbru@redhat.com -> patchew/20200702155000.3455325-1-armbru@redhat.com
 * [new tag]         patchew/20200702162354.928528-1-alistair.francis@wdc.com -> patchew/20200702162354.928528-1-alistair.francis@wdc.com
Auto packing the repository for optimum performance. You may also
run "git gc" manually. See "git help gc" for more information.
Switched to a new branch 'test'
c699943 target/riscv: configure and turn on vector extension from command line
732f3eb target/riscv: vector compress instruction
c6d5c84 target/riscv: vector register gather instruction
58ef2f9a target/riscv: vector slide instructions
86b29f6 target/riscv: floating-point scalar move instructions
3733dbf target/riscv: integer scalar move instruction
a18d3f8 target/riscv: integer extract instruction
a6f1b41 target/riscv: vector element index instruction
9b2fe33 target/riscv: vector iota instruction
c7d4f38 target/riscv: set-X-first mask bit
89b4226 target/riscv: vmfirst find-first-set mask bit
e7d47c0 target/riscv: vector mask population count vmpopc
31f5cff target/riscv: vector mask-register logical instructions
98408cc target/riscv: vector widening floating-point reduction instructions
88bb037 target/riscv: vector single-width floating-point reduction instructions
f8e3620 target/riscv: vector wideing integer reduction instructions
04223c4 target/riscv: vector single-width integer reduction instructions
2063495 target/riscv: narrowing floating-point/integer type-convert instructions
72e4f87 target/riscv: widening floating-point/integer type-convert instructions
40ba0d4 target/riscv: vector floating-point/integer type-convert instructions
5a23e19 target/riscv: vector floating-point merge instructions
94f3fdc target/riscv: vector floating-point classify instructions
fee4c2b target/riscv: vector floating-point compare instructions
4cb87fc target/riscv: vector floating-point sign-injection instructions
16645ad target/riscv: vector floating-point min/max instructions
6f2f9d5 target/riscv: vector floating-point square-root instruction
77c7bd8 target/riscv: vector widening floating-point fused multiply-add instructions
0d2f616 target/riscv: vector single-width floating-point fused multiply-add instructions
3ada8da target/riscv: vector widening floating-point multiply
3cbcddb target/riscv: vector single-width floating-point multiply/divide instructions
2f366b2 target/riscv: vector widening floating-point add/subtract instructions
47a556a target/riscv: vector single-width floating-point add/subtract instructions
e0e7c92 target/riscv: vector narrowing fixed-point clip instructions
b58ff25 target/riscv: vector single-width scaling shift instructions
755ee49 target/riscv: vector widening saturating scaled multiply-add
0a98938 target/riscv: vector single-width fractional multiply with rounding and saturation
3d7426a target/riscv: vector single-width averaging add and subtract
30ceab7 target/riscv: vector single-width saturating add and subtract
8e02288 target/riscv: vector integer merge and move instructions
9db0138 target/riscv: vector widening integer multiply-add instructions
02b7bec target/riscv: vector single-width integer multiply-add instructions
9886644 target/riscv: vector widening integer multiply instructions
f78affb target/riscv: vector integer divide instructions
ebbe4a2 target/riscv: vector single-width integer multiply instructions
a084a45 target/riscv: vector integer min/max instructions
cfdaebf target/riscv: vector integer comparison instructions
e5bf7c63 target/riscv: vector narrowing integer right shift instructions
7d312c9 target/riscv: vector single-width bit shift instructions
677d526 target/riscv: vector bitwise logical instructions
d2c5b92 target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
82c573f target/riscv: vector widening integer add and subtract
3e2e49e target/riscv: vector single-width integer add and subtract
4d097c0 target/riscv: add vector amo operations
97cf7da target/riscv: add fault-only-first unit stride load
9c30857 target/riscv: add vector index load and store instructions
34499bd target/riscv: add vector stride load and store instructions
321f3ad target/riscv: add an internals.h header
95d85f1 target/riscv: add vector configure instruction
da2ee3b target/riscv: support vector extension csr
cd5833b target/riscv: implementation-defined constant parameters
3bf4bb1 target/riscv: add vector extension field in CPURISCVState
fc10543 hw/riscv: Allow 64 bit access to SiFive CLINT
6e393b0 riscv: plic: Add a couple of mising sifive_plic_update calls
9153361 riscv: plic: Honour source priorities

=== OUTPUT BEGIN ===
1/64 Checking commit 91533613453f (riscv: plic: Honour source priorities)
2/64 Checking commit 6e393b03aca6 (riscv: plic: Add a couple of mising sifive_plic_update calls)
3/64 Checking commit fc1054348aea (hw/riscv: Allow 64 bit access to SiFive CLINT)
4/64 Checking commit 3bf4bb170a8b (target/riscv: add vector extension field in CPURISCVState)
5/64 Checking commit cd5833ba2a37 (target/riscv: implementation-defined constant parameters)
6/64 Checking commit da2ee3ba0736 (target/riscv: support vector extension csr)
7/64 Checking commit 95d85f120ce7 (target/riscv: add vector configure instruction)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#163: 
new file mode 100644

total: 0 errors, 1 warnings, 295 lines checked

Patch 7/64 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/64 Checking commit 321f3ad3a25d (target/riscv: add an internals.h header)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#18: 
new file mode 100644

total: 0 errors, 1 warnings, 24 lines checked

Patch 8/64 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/64 Checking commit 34499bd27196 (target/riscv: add vector stride load and store instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#276: FILE: target/riscv/insn_trans/trans_rvv.inc.c:143:
+static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
                                                         ^

ERROR: spaces required around that '*' (ctx:WxV)
#837: FILE: target/riscv/vector_helper.c:260:
+                 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                    ^

ERROR: spaces required around that '*' (ctx:WxV)
#837: FILE: target/riscv/vector_helper.c:260:
+                 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                                         ^

ERROR: spaces required around that '*' (ctx:WxV)
#939: FILE: target/riscv/vector_helper.c:362:
+             vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                ^

ERROR: spaces required around that '*' (ctx:WxV)
#939: FILE: target/riscv/vector_helper.c:362:
+             vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                                     ^

total: 5 errors, 0 warnings, 982 lines checked

Patch 9/64 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

10/64 Checking commit 9c30857387b9 (target/riscv: add vector index load and store instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#253: FILE: target/riscv/vector_helper.c:487:
+                vext_ldst_elem_fn *ldst_elem,
                                   ^

ERROR: spaces required around that '*' (ctx:WxV)
#254: FILE: target/riscv/vector_helper.c:488:
+                clear_fn *clear_elem,
                          ^

total: 2 errors, 0 warnings, 308 lines checked

Patch 10/64 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

11/64 Checking commit 97cf7da09aed (target/riscv: add fault-only-first unit stride load)
ERROR: spaces required around that '*' (ctx:WxV)
#163: FILE: target/riscv/vector_helper.c:587:
+          vext_ldst_elem_fn *ldst_elem,
                             ^

ERROR: spaces required around that '*' (ctx:WxV)
#164: FILE: target/riscv/vector_helper.c:588:
+          clear_fn *clear_elem,
                    ^

total: 2 errors, 0 warnings, 227 lines checked

Patch 11/64 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

12/64 Checking commit 4d097c00ec44 (target/riscv: add vector amo operations)
ERROR: spaces required around that '*' (ctx:WxV)
#367: FILE: target/riscv/vector_helper.c:770:
+                  vext_amo_noatomic_fn *noatomic_op,
                                        ^

ERROR: spaces required around that '*' (ctx:WxV)
#368: FILE: target/riscv/vector_helper.c:771:
+                  clear_fn *clear_elem,
                            ^

total: 2 errors, 0 warnings, 382 lines checked

Patch 12/64 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

13/64 Checking commit 3e2e49ea0caa (target/riscv: vector single-width integer add and subtract)
ERROR: spaces required around that '*' (ctx:WxV)
#95: FILE: target/riscv/insn_trans/trans_rvv.inc.c:781:
+static bool opivv_check(DisasContext *s, arg_rmrr *a)
                                                   ^

ERROR: spaces required around that '*' (ctx:WxV)
#427: FILE: target/riscv/vector_helper.c:876:
+                       opivv2_fn *fn, clear_fn *clearfn)
                                  ^

ERROR: spaces required around that '*' (ctx:WxV)
#427: FILE: target/riscv/vector_helper.c:876:
+                       opivv2_fn *fn, clear_fn *clearfn)
                                                ^

ERROR: spaces required around that '*' (ctx:WxV)
#492: FILE: target/riscv/vector_helper.c:941:
+                       opivx2_fn fn, clear_fn *clearfn)
                                               ^

total: 4 errors, 0 warnings, 535 lines checked

Patch 13/64 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

14/64 Checking commit 82c573f4247a (target/riscv: vector widening integer add and subtract)
15/64 Checking commit d2c5b92028e8 (target/riscv: vector integer add-with-carry / subtract-with-borrow instructions)
16/64 Checking commit 677d526fd2dc (target/riscv: vector bitwise logical instructions)
17/64 Checking commit 7d312c99270e (target/riscv: vector single-width bit shift instructions)
18/64 Checking commit e5bf7c63fb67 (target/riscv: vector narrowing integer right shift instructions)
19/64 Checking commit cfdaebfde0b4 (target/riscv: vector integer comparison instructions)
20/64 Checking commit a084a450d8e6 (target/riscv: vector integer min/max instructions)
21/64 Checking commit ebbe4a2dd14b (target/riscv: vector single-width integer multiply instructions)
22/64 Checking commit f78affbfecf1 (target/riscv: vector integer divide instructions)
23/64 Checking commit 98866448c1b2 (target/riscv: vector widening integer multiply instructions)
24/64 Checking commit 02b7bece2261 (target/riscv: vector single-width integer multiply-add instructions)
25/64 Checking commit 9db013822003 (target/riscv: vector widening integer multiply-add instructions)
26/64 Checking commit 8e022884c840 (target/riscv: vector integer merge and move instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#74: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1623:
+static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
                                                        ^

total: 1 errors, 0 warnings, 246 lines checked

Patch 26/64 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

27/64 Checking commit 30ceab781d25 (target/riscv: vector single-width saturating add and subtract)
28/64 Checking commit 3d7426a774aa (target/riscv: vector single-width averaging add and subtract)
29/64 Checking commit 0a989388dc9a (target/riscv: vector single-width fractional multiply with rounding and saturation)
30/64 Checking commit 755ee49cdc13 (target/riscv: vector widening saturating scaled multiply-add)
31/64 Checking commit b58ff25f2c00 (target/riscv: vector single-width scaling shift instructions)
32/64 Checking commit e0e7c9268d3f (target/riscv: vector narrowing fixed-point clip instructions)
33/64 Checking commit 47a556a4dd3a (target/riscv: vector single-width floating-point add/subtract instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#285: FILE: target/riscv/vector_helper.c:3260:
+static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
                                                                   ^

total: 1 errors, 0 warnings, 271 lines checked

Patch 33/64 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

34/64 Checking commit 2f366b2e2a72 (target/riscv: vector widening floating-point add/subtract instructions)
35/64 Checking commit 3cbcddb9f5c4 (target/riscv: vector single-width floating-point multiply/divide instructions)
36/64 Checking commit 3ada8daf4718 (target/riscv: vector widening floating-point multiply)
37/64 Checking commit 0d2f61633e5d (target/riscv: vector single-width floating-point fused multiply-add instructions)
38/64 Checking commit 77c7bd81de58 (target/riscv: vector widening floating-point fused multiply-add instructions)
39/64 Checking commit 6f2f9d53de51 (target/riscv: vector floating-point square-root instruction)
ERROR: spaces required around that '*' (ctx:WxV)
#69: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2099:
+static bool opfv_check(DisasContext *s, arg_rmr *a)
                                                 ^

ERROR: spaces required around that '*' (ctx:WxV)
#79: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2109:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 120 lines checked

Patch 39/64 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

40/64 Checking commit 16645ada1608 (target/riscv: vector floating-point min/max instructions)
41/64 Checking commit 4cb87fc43cfd (target/riscv: vector floating-point sign-injection instructions)
42/64 Checking commit fee4c2bc6055 (target/riscv: vector floating-point compare instructions)
43/64 Checking commit 94f3fdc0d68b (target/riscv: vector floating-point classify instructions)
44/64 Checking commit 5a23e1927d77 (target/riscv: vector floating-point merge instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#51: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2191:
+static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
                                                          ^

total: 1 errors, 0 warnings, 83 lines checked

Patch 44/64 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

45/64 Checking commit 40ba0d4a8e8a (target/riscv: vector floating-point/integer type-convert instructions)
46/64 Checking commit 72e4f8786241 (target/riscv: widening floating-point/integer type-convert instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#64: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2238:
+static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
                                                       ^

ERROR: spaces required around that '*' (ctx:WxV)
#76: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2250:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 121 lines checked

Patch 46/64 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

47/64 Checking commit 20634952f5d7 (target/riscv: narrowing floating-point/integer type-convert instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#64: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2286:
+static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
                                                        ^

ERROR: spaces required around that '*' (ctx:WxV)
#76: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2298:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 118 lines checked

Patch 47/64 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

48/64 Checking commit 04223c43340e (target/riscv: vector single-width integer reduction instructions)
49/64 Checking commit f8e3620b20ee (target/riscv: vector wideing integer reduction instructions)
50/64 Checking commit 88bb0377570f (target/riscv: vector single-width floating-point reduction instructions)
51/64 Checking commit 98408cca4888 (target/riscv: vector widening floating-point reduction instructions)
52/64 Checking commit 31f5cffa1380 (target/riscv: vector mask-register logical instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#64: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2364:
+static bool trans_##NAME(DisasContext *s, arg_r *a)                \
                                                 ^

total: 1 errors, 0 warnings, 107 lines checked

Patch 52/64 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

53/64 Checking commit e7d47c046e3c (target/riscv: vector mask population count vmpopc)
ERROR: spaces required around that '*' (ctx:WxV)
#45: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2394:
+static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
                                                     ^

total: 1 errors, 0 warnings, 70 lines checked

Patch 53/64 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

54/64 Checking commit 89b4226e4a6c (target/riscv: vmfirst find-first-set mask bit)
55/64 Checking commit c7d4f38f52bf (target/riscv: set-X-first mask bit)
56/64 Checking commit 9b2fe33560e2 (target/riscv: vector iota instruction)
ERROR: spaces required around that '*' (ctx:WxV)
#48: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2486:
+static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
                                                        ^

total: 1 errors, 0 warnings, 77 lines checked

Patch 56/64 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

57/64 Checking commit a6f1b41d47c9 (target/riscv: vector element index instruction)
58/64 Checking commit a18d3f870fa2 (target/riscv: integer extract instruction)
59/64 Checking commit 3733dbf4f44b (target/riscv: integer scalar move instruction)
60/64 Checking commit 86b29f60d2ba (target/riscv: floating-point scalar move instructions)
61/64 Checking commit 58ef2f9a3e0c (target/riscv: vector slide instructions)
62/64 Checking commit c6d5c84c7d09 (target/riscv: vector register gather instruction)
63/64 Checking commit 732f3ebd393f (target/riscv: vector compress instruction)
64/64 Checking commit c6999437790d (target/riscv: configure and turn on vector extension from command line)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20200702162354.928528-1-alistair.francis@wdc.com/testing.checkpatch/?type=message.
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