1. Patchew
  2. QEMU
  3. View series

[PULL 00/63] riscv-to-apply queue

Alistair Francis posted 63 patches 3 years, 10 months ago
Test FreeBSD passed
Test docker-quick@centos7 failed
Test checkpatch failed
Test docker-mingw@fedora failed
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20200626214410.3613258-1-alistair.francis@wdc.com
Maintainers: Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Palmer Dabbelt <palmer@dabbelt.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
There is a newer version of this series
target/riscv/cpu.h                      |   82 +-
target/riscv/cpu_bits.h                 |   15 +
target/riscv/helper.h                   | 1069 +++++++
target/riscv/internals.h                |   41 +
target/riscv/insn32-64.decode           |   11 +
target/riscv/insn32.decode              |  372 +++
hw/riscv/sifive_plic.c                  |   20 +-
target/riscv/cpu.c                      |   50 +
target/riscv/csr.c                      |   75 +-
target/riscv/fpu_helper.c               |   33 +-
target/riscv/insn_trans/trans_rvv.inc.c | 2888 ++++++++++++++++++
target/riscv/translate.c                |   27 +-
target/riscv/vector_helper.c            | 4899 +++++++++++++++++++++++++++++++
target/riscv/Makefile.objs              |    2 +-
14 files changed, 9534 insertions(+), 50 deletions(-)
create mode 100644 target/riscv/internals.h
create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
create mode 100644 target/riscv/vector_helper.c
[PULL 00/63] riscv-to-apply queue
Posted by Alistair Francis 3 years, 10 months ago 
The following changes since commit 553cf5d7c47bee05a3dec9461c1f8430316d516b:

  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging (2020-06-26 18:22:36 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200626-1

for you to fetch changes up to b39d59434ea10649fdb9e0a339c30c76e38c5e17:

  target/riscv: configure and turn on vector extension from command line (2020-06-26 14:22:15 -0700)

----------------------------------------------------------------
This PR contains two patches to improve PLIC support in QEMU.

The rest of the PR is adding support for the v0.7.1 RISC-V vector
extensions. This is experimental support as the vector extensions are
still in a draft state.

----------------------------------------------------------------
Jessica Clarke (2):
      riscv: plic: Honour source priorities
      riscv: plic: Add a couple of mising sifive_plic_update calls

LIU Zhiwei (61):
      target/riscv: add vector extension field in CPURISCVState
      target/riscv: implementation-defined constant parameters
      target/riscv: support vector extension csr
      target/riscv: add vector configure instruction
      target/riscv: add an internals.h header
      target/riscv: add vector stride load and store instructions
      target/riscv: add vector index load and store instructions
      target/riscv: add fault-only-first unit stride load
      target/riscv: add vector amo operations
      target/riscv: vector single-width integer add and subtract
      target/riscv: vector widening integer add and subtract
      target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
      target/riscv: vector bitwise logical instructions
      target/riscv: vector single-width bit shift instructions
      target/riscv: vector narrowing integer right shift instructions
      target/riscv: vector integer comparison instructions
      target/riscv: vector integer min/max instructions
      target/riscv: vector single-width integer multiply instructions
      target/riscv: vector integer divide instructions
      target/riscv: vector widening integer multiply instructions
      target/riscv: vector single-width integer multiply-add instructions
      target/riscv: vector widening integer multiply-add instructions
      target/riscv: vector integer merge and move instructions
      target/riscv: vector single-width saturating add and subtract
      target/riscv: vector single-width averaging add and subtract
      target/riscv: vector single-width fractional multiply with rounding and saturation
      target/riscv: vector widening saturating scaled multiply-add
      target/riscv: vector single-width scaling shift instructions
      target/riscv: vector narrowing fixed-point clip instructions
      target/riscv: vector single-width floating-point add/subtract instructions
      target/riscv: vector widening floating-point add/subtract instructions
      target/riscv: vector single-width floating-point multiply/divide instructions
      target/riscv: vector widening floating-point multiply
      target/riscv: vector single-width floating-point fused multiply-add instructions
      target/riscv: vector widening floating-point fused multiply-add instructions
      target/riscv: vector floating-point square-root instruction
      target/riscv: vector floating-point min/max instructions
      target/riscv: vector floating-point sign-injection instructions
      target/riscv: vector floating-point compare instructions
      target/riscv: vector floating-point classify instructions
      target/riscv: vector floating-point merge instructions
      target/riscv: vector floating-point/integer type-convert instructions
      target/riscv: widening floating-point/integer type-convert instructions
      target/riscv: narrowing floating-point/integer type-convert instructions
      target/riscv: vector single-width integer reduction instructions
      target/riscv: vector wideing integer reduction instructions
      target/riscv: vector single-width floating-point reduction instructions
      target/riscv: vector widening floating-point reduction instructions
      target/riscv: vector mask-register logical instructions
      target/riscv: vector mask population count vmpopc
      target/riscv: vmfirst find-first-set mask bit
      target/riscv: set-X-first mask bit
      target/riscv: vector iota instruction
      target/riscv: vector element index instruction
      target/riscv: integer extract instruction
      target/riscv: integer scalar move instruction
      target/riscv: floating-point scalar move instructions
      target/riscv: vector slide instructions
      target/riscv: vector register gather instruction
      target/riscv: vector compress instruction
      target/riscv: configure and turn on vector extension from command line

 target/riscv/cpu.h                      |   82 +-
 target/riscv/cpu_bits.h                 |   15 +
 target/riscv/helper.h                   | 1069 +++++++
 target/riscv/internals.h                |   41 +
 target/riscv/insn32-64.decode           |   11 +
 target/riscv/insn32.decode              |  372 +++
 hw/riscv/sifive_plic.c                  |   20 +-
 target/riscv/cpu.c                      |   50 +
 target/riscv/csr.c                      |   75 +-
 target/riscv/fpu_helper.c               |   33 +-
 target/riscv/insn_trans/trans_rvv.inc.c | 2888 ++++++++++++++++++
 target/riscv/translate.c                |   27 +-
 target/riscv/vector_helper.c            | 4899 +++++++++++++++++++++++++++++++
 target/riscv/Makefile.objs              |    2 +-
 14 files changed, 9534 insertions(+), 50 deletions(-)
 create mode 100644 target/riscv/internals.h
 create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
 create mode 100644 target/riscv/vector_helper.c
Re: [PULL 00/63] riscv-to-apply queue
Posted by no-reply@patchew.org 3 years, 10 months ago 
Patchew URL: https://patchew.org/QEMU/20200626214410.3613258-1-alistair.francis@wdc.com/



Hi,

This series failed the docker-mingw@fedora build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

=== TEST SCRIPT BEGIN ===
#! /bin/bash
export ARCH=x86_64
make docker-image-fedora V=1 NETWORK=1
time make docker-test-mingw@fedora J=14 NETWORK=1
=== TEST SCRIPT END ===

    raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sudo', '-n', 'docker', 'run', '--label', 'com.qemu.instance.uuid=3227ad66ddf54e91801ba30034f49d0d', '-u', '1001', '--security-opt', 'seccomp=unconfined', '--rm', '-e', 'TARGET_LIST=', '-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=14', '-e', 'DEBUG=', '-e', 'SHOW_ENV=', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', '/home/patchew/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', '/var/tmp/patchew-tester-tmp-nymx7cv5/src/docker-src.2020-06-26-18.37.24.5231:/var/tmp/qemu:z,ro', 'qemu:fedora', '/var/tmp/qemu/run', 'test-mingw']' returned non-zero exit status 2.
filter=--filter=label=com.qemu.instance.uuid=3227ad66ddf54e91801ba30034f49d0d
make[1]: *** [docker-run] Error 1
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-nymx7cv5/src'
make: *** [docker-run-test-mingw@fedora] Error 2

real    6m37.447s
user    0m9.016s


The full log is available at
http://patchew.org/logs/20200626214410.3613258-1-alistair.francis@wdc.com/testing.docker-mingw@fedora/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
Re: [PULL 00/63] riscv-to-apply queue
Posted by no-reply@patchew.org 3 years, 10 months ago 
Patchew URL: https://patchew.org/QEMU/20200626214410.3613258-1-alistair.francis@wdc.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PULL 00/63] riscv-to-apply queue
Type: series
Message-id: 20200626214410.3613258-1-alistair.francis@wdc.com

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

From https://github.com/patchew-project/qemu
 * [new tag]         patchew/20200626214410.3613258-1-alistair.francis@wdc.com -> patchew/20200626214410.3613258-1-alistair.francis@wdc.com
Auto packing the repository for optimum performance. You may also
run "git gc" manually. See "git help gc" for more information.
Switched to a new branch 'test'
cd5b7c4 target/riscv: configure and turn on vector extension from command line
c58857c target/riscv: vector compress instruction
dfd9589 target/riscv: vector register gather instruction
f686a11 target/riscv: vector slide instructions
cbaef7d target/riscv: floating-point scalar move instructions
869e2ea target/riscv: integer scalar move instruction
cc89401 target/riscv: integer extract instruction
80ff8d1 target/riscv: vector element index instruction
7b77a67 target/riscv: vector iota instruction
2401535 target/riscv: set-X-first mask bit
3b818e7 target/riscv: vmfirst find-first-set mask bit
2b926a8 target/riscv: vector mask population count vmpopc
a188474 target/riscv: vector mask-register logical instructions
89e4b56 target/riscv: vector widening floating-point reduction instructions
a9d5e44 target/riscv: vector single-width floating-point reduction instructions
f0313f4 target/riscv: vector wideing integer reduction instructions
3ad6c50 target/riscv: vector single-width integer reduction instructions
3ea3f11 target/riscv: narrowing floating-point/integer type-convert instructions
583cb8d target/riscv: widening floating-point/integer type-convert instructions
f233822 target/riscv: vector floating-point/integer type-convert instructions
82c1888 target/riscv: vector floating-point merge instructions
08c2fe7 target/riscv: vector floating-point classify instructions
81c1632 target/riscv: vector floating-point compare instructions
e34823e target/riscv: vector floating-point sign-injection instructions
8d5d4eb target/riscv: vector floating-point min/max instructions
11148eb target/riscv: vector floating-point square-root instruction
fb66a6a target/riscv: vector widening floating-point fused multiply-add instructions
23781ba target/riscv: vector single-width floating-point fused multiply-add instructions
f543e1d target/riscv: vector widening floating-point multiply
77558b0 target/riscv: vector single-width floating-point multiply/divide instructions
644657b target/riscv: vector widening floating-point add/subtract instructions
737c4ae target/riscv: vector single-width floating-point add/subtract instructions
e5365b3 target/riscv: vector narrowing fixed-point clip instructions
9948ef4 target/riscv: vector single-width scaling shift instructions
f9763c2 target/riscv: vector widening saturating scaled multiply-add
651cee5 target/riscv: vector single-width fractional multiply with rounding and saturation
02c1db1 target/riscv: vector single-width averaging add and subtract
0240b96 target/riscv: vector single-width saturating add and subtract
13da6db target/riscv: vector integer merge and move instructions
817d651 target/riscv: vector widening integer multiply-add instructions
55dbb3d target/riscv: vector single-width integer multiply-add instructions
caa7cd7 target/riscv: vector widening integer multiply instructions
6ee55f1 target/riscv: vector integer divide instructions
53dac4b target/riscv: vector single-width integer multiply instructions
e105f4a target/riscv: vector integer min/max instructions
555b7eb target/riscv: vector integer comparison instructions
041ad12 target/riscv: vector narrowing integer right shift instructions
1ee9221 target/riscv: vector single-width bit shift instructions
60d2872 target/riscv: vector bitwise logical instructions
1b4efd2 target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
42cd1fc target/riscv: vector widening integer add and subtract
bfb10da target/riscv: vector single-width integer add and subtract
c3da998 target/riscv: add vector amo operations
f7d8b4f target/riscv: add fault-only-first unit stride load
404b17c target/riscv: add vector index load and store instructions
ee691fd target/riscv: add vector stride load and store instructions
f2ab6d0 target/riscv: add an internals.h header
3e9d956 target/riscv: add vector configure instruction
560561b target/riscv: support vector extension csr
4eac3b3 target/riscv: implementation-defined constant parameters
bf4f637 target/riscv: add vector extension field in CPURISCVState
b5a0bb5 riscv: plic: Add a couple of mising sifive_plic_update calls
66a322b riscv: plic: Honour source priorities

=== OUTPUT BEGIN ===
1/63 Checking commit 66a322b1bd40 (riscv: plic: Honour source priorities)
2/63 Checking commit b5a0bb5457e3 (riscv: plic: Add a couple of mising sifive_plic_update calls)
3/63 Checking commit bf4f6372afcf (target/riscv: add vector extension field in CPURISCVState)
4/63 Checking commit 4eac3b308efc (target/riscv: implementation-defined constant parameters)
5/63 Checking commit 560561bc1703 (target/riscv: support vector extension csr)
6/63 Checking commit 3e9d9568b7b8 (target/riscv: add vector configure instruction)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#163: 
new file mode 100644

total: 0 errors, 1 warnings, 295 lines checked

Patch 6/63 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/63 Checking commit f2ab6d0f9cee (target/riscv: add an internals.h header)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#18: 
new file mode 100644

total: 0 errors, 1 warnings, 24 lines checked

Patch 7/63 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/63 Checking commit ee691fd31473 (target/riscv: add vector stride load and store instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#276: FILE: target/riscv/insn_trans/trans_rvv.inc.c:143:
+static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
                                                         ^

ERROR: spaces required around that '*' (ctx:WxV)
#837: FILE: target/riscv/vector_helper.c:260:
+                 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                    ^

ERROR: spaces required around that '*' (ctx:WxV)
#837: FILE: target/riscv/vector_helper.c:260:
+                 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                                         ^

ERROR: spaces required around that '*' (ctx:WxV)
#939: FILE: target/riscv/vector_helper.c:362:
+             vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                ^

ERROR: spaces required around that '*' (ctx:WxV)
#939: FILE: target/riscv/vector_helper.c:362:
+             vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                                     ^

total: 5 errors, 0 warnings, 982 lines checked

Patch 8/63 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

9/63 Checking commit 404b17c49401 (target/riscv: add vector index load and store instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#253: FILE: target/riscv/vector_helper.c:487:
+                vext_ldst_elem_fn *ldst_elem,
                                   ^

ERROR: spaces required around that '*' (ctx:WxV)
#254: FILE: target/riscv/vector_helper.c:488:
+                clear_fn *clear_elem,
                          ^

total: 2 errors, 0 warnings, 308 lines checked

Patch 9/63 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

10/63 Checking commit f7d8b4fcfae4 (target/riscv: add fault-only-first unit stride load)
ERROR: spaces required around that '*' (ctx:WxV)
#163: FILE: target/riscv/vector_helper.c:587:
+          vext_ldst_elem_fn *ldst_elem,
                             ^

ERROR: spaces required around that '*' (ctx:WxV)
#164: FILE: target/riscv/vector_helper.c:588:
+          clear_fn *clear_elem,
                    ^

total: 2 errors, 0 warnings, 227 lines checked

Patch 10/63 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

11/63 Checking commit c3da998a39f0 (target/riscv: add vector amo operations)
ERROR: spaces required around that '*' (ctx:WxV)
#367: FILE: target/riscv/vector_helper.c:770:
+                  vext_amo_noatomic_fn *noatomic_op,
                                        ^

ERROR: spaces required around that '*' (ctx:WxV)
#368: FILE: target/riscv/vector_helper.c:771:
+                  clear_fn *clear_elem,
                            ^

total: 2 errors, 0 warnings, 382 lines checked

Patch 11/63 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

12/63 Checking commit bfb10daaf26c (target/riscv: vector single-width integer add and subtract)
ERROR: spaces required around that '*' (ctx:WxV)
#95: FILE: target/riscv/insn_trans/trans_rvv.inc.c:781:
+static bool opivv_check(DisasContext *s, arg_rmrr *a)
                                                   ^

ERROR: spaces required around that '*' (ctx:WxV)
#427: FILE: target/riscv/vector_helper.c:876:
+                       opivv2_fn *fn, clear_fn *clearfn)
                                  ^

ERROR: spaces required around that '*' (ctx:WxV)
#427: FILE: target/riscv/vector_helper.c:876:
+                       opivv2_fn *fn, clear_fn *clearfn)
                                                ^

ERROR: spaces required around that '*' (ctx:WxV)
#492: FILE: target/riscv/vector_helper.c:941:
+                       opivx2_fn fn, clear_fn *clearfn)
                                               ^

total: 4 errors, 0 warnings, 535 lines checked

Patch 12/63 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

13/63 Checking commit 42cd1fc008b2 (target/riscv: vector widening integer add and subtract)
14/63 Checking commit 1b4efd24f70a (target/riscv: vector integer add-with-carry / subtract-with-borrow instructions)
15/63 Checking commit 60d28722e81d (target/riscv: vector bitwise logical instructions)
16/63 Checking commit 1ee9221fab7b (target/riscv: vector single-width bit shift instructions)
17/63 Checking commit 041ad12f0fd3 (target/riscv: vector narrowing integer right shift instructions)
18/63 Checking commit 555b7eb0eb3c (target/riscv: vector integer comparison instructions)
19/63 Checking commit e105f4a08905 (target/riscv: vector integer min/max instructions)
20/63 Checking commit 53dac4bfba2f (target/riscv: vector single-width integer multiply instructions)
21/63 Checking commit 6ee55f1f8a75 (target/riscv: vector integer divide instructions)
22/63 Checking commit caa7cd7b9f51 (target/riscv: vector widening integer multiply instructions)
23/63 Checking commit 55dbb3db3cb0 (target/riscv: vector single-width integer multiply-add instructions)
24/63 Checking commit 817d6517b470 (target/riscv: vector widening integer multiply-add instructions)
25/63 Checking commit 13da6dbdfba7 (target/riscv: vector integer merge and move instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#74: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1623:
+static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
                                                        ^

total: 1 errors, 0 warnings, 246 lines checked

Patch 25/63 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

26/63 Checking commit 0240b960485b (target/riscv: vector single-width saturating add and subtract)
27/63 Checking commit 02c1db164f49 (target/riscv: vector single-width averaging add and subtract)
28/63 Checking commit 651cee550f8e (target/riscv: vector single-width fractional multiply with rounding and saturation)
29/63 Checking commit f9763c28b863 (target/riscv: vector widening saturating scaled multiply-add)
30/63 Checking commit 9948ef4cfac9 (target/riscv: vector single-width scaling shift instructions)
31/63 Checking commit e5365b3a68d1 (target/riscv: vector narrowing fixed-point clip instructions)
32/63 Checking commit 737c4ae6ee17 (target/riscv: vector single-width floating-point add/subtract instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#285: FILE: target/riscv/vector_helper.c:3260:
+static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
                                                                   ^

total: 1 errors, 0 warnings, 271 lines checked

Patch 32/63 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

33/63 Checking commit 644657b191a6 (target/riscv: vector widening floating-point add/subtract instructions)
34/63 Checking commit 77558b0ce350 (target/riscv: vector single-width floating-point multiply/divide instructions)
35/63 Checking commit f543e1d074fd (target/riscv: vector widening floating-point multiply)
36/63 Checking commit 23781badadf6 (target/riscv: vector single-width floating-point fused multiply-add instructions)
37/63 Checking commit fb66a6a72480 (target/riscv: vector widening floating-point fused multiply-add instructions)
38/63 Checking commit 11148eb0c732 (target/riscv: vector floating-point square-root instruction)
ERROR: spaces required around that '*' (ctx:WxV)
#69: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2099:
+static bool opfv_check(DisasContext *s, arg_rmr *a)
                                                 ^

ERROR: spaces required around that '*' (ctx:WxV)
#79: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2109:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 120 lines checked

Patch 38/63 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

39/63 Checking commit 8d5d4eb4e456 (target/riscv: vector floating-point min/max instructions)
40/63 Checking commit e34823edc8c0 (target/riscv: vector floating-point sign-injection instructions)
41/63 Checking commit 81c1632a7b14 (target/riscv: vector floating-point compare instructions)
42/63 Checking commit 08c2fe73e15a (target/riscv: vector floating-point classify instructions)
43/63 Checking commit 82c1888ce1f0 (target/riscv: vector floating-point merge instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#51: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2191:
+static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
                                                          ^

total: 1 errors, 0 warnings, 83 lines checked

Patch 43/63 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

44/63 Checking commit f233822667f7 (target/riscv: vector floating-point/integer type-convert instructions)
45/63 Checking commit 583cb8d18ebb (target/riscv: widening floating-point/integer type-convert instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#64: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2238:
+static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
                                                       ^

ERROR: spaces required around that '*' (ctx:WxV)
#76: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2250:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 121 lines checked

Patch 45/63 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

46/63 Checking commit 3ea3f112af09 (target/riscv: narrowing floating-point/integer type-convert instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#64: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2286:
+static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
                                                        ^

ERROR: spaces required around that '*' (ctx:WxV)
#76: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2298:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 118 lines checked

Patch 46/63 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

47/63 Checking commit 3ad6c50d6215 (target/riscv: vector single-width integer reduction instructions)
48/63 Checking commit f0313f4fc2ed (target/riscv: vector wideing integer reduction instructions)
49/63 Checking commit a9d5e44a6490 (target/riscv: vector single-width floating-point reduction instructions)
50/63 Checking commit 89e4b561b398 (target/riscv: vector widening floating-point reduction instructions)
51/63 Checking commit a188474058d8 (target/riscv: vector mask-register logical instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#64: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2364:
+static bool trans_##NAME(DisasContext *s, arg_r *a)                \
                                                 ^

total: 1 errors, 0 warnings, 107 lines checked

Patch 51/63 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

52/63 Checking commit 2b926a832fc0 (target/riscv: vector mask population count vmpopc)
ERROR: spaces required around that '*' (ctx:WxV)
#45: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2394:
+static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
                                                     ^

total: 1 errors, 0 warnings, 70 lines checked

Patch 52/63 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

53/63 Checking commit 3b818e7cc0e5 (target/riscv: vmfirst find-first-set mask bit)
54/63 Checking commit 2401535ce68b (target/riscv: set-X-first mask bit)
55/63 Checking commit 7b77a671bf95 (target/riscv: vector iota instruction)
ERROR: spaces required around that '*' (ctx:WxV)
#48: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2486:
+static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
                                                        ^

total: 1 errors, 0 warnings, 77 lines checked

Patch 55/63 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

56/63 Checking commit 80ff8d117484 (target/riscv: vector element index instruction)
57/63 Checking commit cc8940130953 (target/riscv: integer extract instruction)
58/63 Checking commit 869e2ea22335 (target/riscv: integer scalar move instruction)
59/63 Checking commit cbaef7dc4394 (target/riscv: floating-point scalar move instructions)
60/63 Checking commit f686a11dd085 (target/riscv: vector slide instructions)
61/63 Checking commit dfd9589f79db (target/riscv: vector register gather instruction)
62/63 Checking commit c58857c35622 (target/riscv: vector compress instruction)
63/63 Checking commit cd5b7c498a51 (target/riscv: configure and turn on vector extension from command line)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20200626214410.3613258-1-alistair.francis@wdc.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
Re: [PULL 00/63] riscv-to-apply queue
Posted by Peter Maydell 3 years, 10 months ago 
On Fri, 26 Jun 2020 at 22:53, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 553cf5d7c47bee05a3dec9461c1f8430316d516b:
>
>   Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging (2020-06-26 18:22:36 +0100)
>
> are available in the Git repository at:
>
>   git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200626-1
>
> for you to fetch changes up to b39d59434ea10649fdb9e0a339c30c76e38c5e17:
>
>   target/riscv: configure and turn on vector extension from command line (2020-06-26 14:22:15 -0700)
>
> ----------------------------------------------------------------
> This PR contains two patches to improve PLIC support in QEMU.
>
> The rest of the PR is adding support for the v0.7.1 RISC-V vector
> extensions. This is experimental support as the vector extensions are
> still in a draft state.
>

Hi; I'm afraid this fails to build on PPC64 and s390x (ie
our big-endian hosts):

/home/ubuntu/qemu/target/riscv/vector_helper.c: In function ‘vext_clear’:
/home/ubuntu/qemu/target/riscv/vector_helper.c: In function ‘vext_clear’:
/home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
         memset(tail & ~(7ULL), 0, part1);
                     ^
/home/ubuntu/qemu/target/riscv/vector_helper.c:155:27: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
         memset((tail + 8) & ~(7ULL), 0, part2);
                ~~~~~~~~~~ ^
/home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
         memset(tail & ~(7ULL), 0, part1);
                     ^
/home/ubuntu/qemu/target/riscv/vector_helper.c:155:27: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
         memset((tail + 8) & ~(7ULL), 0, part2);
                ~~~~~~~~~~ ^
/home/ubuntu/qemu/rules.mak:69: recipe for target
'target/riscv/vector_helper.o' failed


thanks
-- PMM
Re: [PULL 00/63] riscv-to-apply queue
Posted by Alistair Francis 3 years, 10 months ago 
On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Fri, 26 Jun 2020 at 22:53, Alistair Francis <alistair.francis@wdc.com> wrote:
> >
> > The following changes since commit 553cf5d7c47bee05a3dec9461c1f8430316d516b:
> >
> >   Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging (2020-06-26 18:22:36 +0100)
> >
> > are available in the Git repository at:
> >
> >   git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200626-1
> >
> > for you to fetch changes up to b39d59434ea10649fdb9e0a339c30c76e38c5e17:
> >
> >   target/riscv: configure and turn on vector extension from command line (2020-06-26 14:22:15 -0700)
> >
> > ----------------------------------------------------------------
> > This PR contains two patches to improve PLIC support in QEMU.
> >
> > The rest of the PR is adding support for the v0.7.1 RISC-V vector
> > extensions. This is experimental support as the vector extensions are
> > still in a draft state.
> >
>
> Hi; I'm afraid this fails to build on PPC64 and s390x (ie
> our big-endian hosts):

LIU Zhiwei do you mind looking into this?

Alistair

>
> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function ‘vext_clear’:
> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function ‘vext_clear’:
> /home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>          memset(tail & ~(7ULL), 0, part1);
>                      ^
> /home/ubuntu/qemu/target/riscv/vector_helper.c:155:27: error: invalid
> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>          memset((tail + 8) & ~(7ULL), 0, part2);
>                 ~~~~~~~~~~ ^
> /home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>          memset(tail & ~(7ULL), 0, part1);
>                      ^
> /home/ubuntu/qemu/target/riscv/vector_helper.c:155:27: error: invalid
> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>          memset((tail + 8) & ~(7ULL), 0, part2);
>                 ~~~~~~~~~~ ^
> /home/ubuntu/qemu/rules.mak:69: recipe for target
> 'target/riscv/vector_helper.o' failed
>
>
> thanks
> -- PMM
Re: [PULL 00/63] riscv-to-apply queue
Posted by LIU Zhiwei 3 years, 10 months ago 

On 2020/6/29 6:51, Alistair Francis wrote:
> On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell <peter.maydell@linaro.org> wrote:
>> On Fri, 26 Jun 2020 at 22:53, Alistair Francis <alistair.francis@wdc.com> wrote:
>>> The following changes since commit 553cf5d7c47bee05a3dec9461c1f8430316d516b:
>>>
>>>    Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging (2020-06-26 18:22:36 +0100)
>>>
>>> are available in the Git repository at:
>>>
>>>    git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200626-1
>>>
>>> for you to fetch changes up to b39d59434ea10649fdb9e0a339c30c76e38c5e17:
>>>
>>>    target/riscv: configure and turn on vector extension from command line (2020-06-26 14:22:15 -0700)
>>>
>>> ----------------------------------------------------------------
>>> This PR contains two patches to improve PLIC support in QEMU.
>>>
>>> The rest of the PR is adding support for the v0.7.1 RISC-V vector
>>> extensions. This is experimental support as the vector extensions are
>>> still in a draft state.
>>>
>> Hi; I'm afraid this fails to build on PPC64 and s390x (ie
>> our big-endian hosts):
> LIU Zhiwei do you mind looking into this?
Sure, I will.
I have applied for a gcc compile farm account today, but it maybe a few 
days later before I can login.
Please accept my apologies for my oversight.

Zhiwei
>
> Alistair
>
>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function ‘vext_clear’:
>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function ‘vext_clear’:
>> /home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
>> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>>           memset(tail & ~(7ULL), 0, part1);
>>                       ^
>> /home/ubuntu/qemu/target/riscv/vector_helper.c:155:27: error: invalid
>> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>>           memset((tail + 8) & ~(7ULL), 0, part2);
>>                  ~~~~~~~~~~ ^
>> /home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
>> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>>           memset(tail & ~(7ULL), 0, part1);
>>                       ^
>> /home/ubuntu/qemu/target/riscv/vector_helper.c:155:27: error: invalid
>> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>>           memset((tail + 8) & ~(7ULL), 0, part2);
>>                  ~~~~~~~~~~ ^
>> /home/ubuntu/qemu/rules.mak:69: recipe for target
>> 'target/riscv/vector_helper.o' failed
>>
>>
>> thanks
>> -- PMM
Re: [PULL 00/63] riscv-to-apply queue
Posted by LIU Zhiwei 3 years, 10 months ago 

On 2020/6/29 6:51, Alistair Francis wrote:
> On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell <peter.maydell@linaro.org> wrote:
>> On Fri, 26 Jun 2020 at 22:53, Alistair Francis <alistair.francis@wdc.com> wrote:
>>> The following changes since commit 553cf5d7c47bee05a3dec9461c1f8430316d516b:
>>>
>>>    Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging (2020-06-26 18:22:36 +0100)
>>>
>>> are available in the Git repository at:
>>>
>>>    git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200626-1
>>>
>>> for you to fetch changes up to b39d59434ea10649fdb9e0a339c30c76e38c5e17:
>>>
>>>    target/riscv: configure and turn on vector extension from command line (2020-06-26 14:22:15 -0700)
>>>
>>> ----------------------------------------------------------------
>>> This PR contains two patches to improve PLIC support in QEMU.
>>>
>>> The rest of the PR is adding support for the v0.7.1 RISC-V vector
>>> extensions. This is experimental support as the vector extensions are
>>> still in a draft state.
>>>
>> Hi; I'm afraid this fails to build on PPC64 and s390x (ie
>> our big-endian hosts):
Hi Peter,

Do you mean you built the patch set on PPC64 or s390x and got errors in 
the list? Or just a worry?

I have built the patch set on Ubuntu 18.04 X86-64. I don't know which 
compile option
will fails the compilation. If you compiled on Ubuntu x86-64, could you 
show me the
compile option?

As a note: I try to find a PPC64 for test, but I'm afraid it will be too 
later.
Is there an available  PPC64  machine in the community?

Thanks very much.

Zhiwei
> LIU Zhiwei do you mind looking into this?
>
> Alistair
>
>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function ‘vext_clear’:
>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function ‘vext_clear’:
>> /home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
>> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>>           memset(tail & ~(7ULL), 0, part1);
>>                       ^
>> /home/ubuntu/qemu/target/riscv/vector_helper.c:155:27: error: invalid
>> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>>           memset((tail + 8) & ~(7ULL), 0, part2);
>>                  ~~~~~~~~~~ ^
>> /home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
>> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>>           memset(tail & ~(7ULL), 0, part1);
>>                       ^
>> /home/ubuntu/qemu/target/riscv/vector_helper.c:155:27: error: invalid
>> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>>           memset((tail + 8) & ~(7ULL), 0, part2);
>>                  ~~~~~~~~~~ ^
>> /home/ubuntu/qemu/rules.mak:69: recipe for target
>> 'target/riscv/vector_helper.o' failed
>>
>>
>> thanks
>> -- PMM
Re: [PULL 00/63] riscv-to-apply queue
Posted by Thomas Huth 3 years, 10 months ago 
On 30/06/2020 08.56, LIU Zhiwei wrote:
> 
> 
> On 2020/6/29 6:51, Alistair Francis wrote:
>> On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell 
>> <peter.maydell@linaro.org> wrote:
>>> On Fri, 26 Jun 2020 at 22:53, Alistair Francis 
>>> <alistair.francis@wdc.com> wrote:
>>>> The following changes since commit 
>>>> 553cf5d7c47bee05a3dec9461c1f8430316d516b:
>>>>
>>>>    Merge remote-tracking branch 
>>>> 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging 
>>>> (2020-06-26 18:22:36 +0100)
>>>>
>>>> are available in the Git repository at:
>>>>
>>>>    git@github.com:alistair23/qemu.git 
>>>> tags/pull-riscv-to-apply-20200626-1
>>>>
>>>> for you to fetch changes up to 
>>>> b39d59434ea10649fdb9e0a339c30c76e38c5e17:
>>>>
>>>>    target/riscv: configure and turn on vector extension from command 
>>>> line (2020-06-26 14:22:15 -0700)
>>>>
>>>> ----------------------------------------------------------------
>>>> This PR contains two patches to improve PLIC support in QEMU.
>>>>
>>>> The rest of the PR is adding support for the v0.7.1 RISC-V vector
>>>> extensions. This is experimental support as the vector extensions are
>>>> still in a draft state.
>>>>
>>> Hi; I'm afraid this fails to build on PPC64 and s390x (ie
>>> our big-endian hosts):
> Hi Peter,
> 
> Do you mean you built the patch set on PPC64 or s390x and got errors in 
> the list? Or just a worry?
 >
> I have built the patch set on Ubuntu 18.04 X86-64. I don't know which 
> compile option
> will fails the compilation. If you compiled on Ubuntu x86-64, could you 
> show me the
> compile option?

The related code in your patch "target/riscv: add vector stride load and 
store instructions" is in a "#ifdef HOST_WORDS_BIGENDIAN" section, so of 
course this bug does not trigger on a x86 host. You could temporarily 
turn the "#ifdef HOST_WORDS_BIGENDIAN" into a "#if 1" to see whether you 
can then also reproduce the error on x86.

> As a note: I try to find a PPC64 for test, but I'm afraid it will be too 
> later.
> Is there an available  PPC64  machine in the community?

Maybe the easiest way to test your code on a big endian machine, too, is 
to get a github account, clone the QEMU repository there, and enable 
Travis for that repo. Then your code gets built on some non-x86 
architectures (including a big-endian s390x) as soon as you push it to 
the repo (see .travis.yml for details).

>>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function 
>>> ‘vext_clear’:
>>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function 
>>> ‘vext_clear’:
>>> /home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
>>> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>>>           memset(tail & ~(7ULL), 0, part1);

You obviously must not use "&" with a pointer. I guess you have to cast 
to "uintptr_t" and back, or think of some other smart way to fix this.

  Thomas
Re: [PULL 00/63] riscv-to-apply queue
Posted by LIU Zhiwei 3 years, 10 months ago 

On 2020/6/30 16:11, Thomas Huth wrote:
> On 30/06/2020 08.56, LIU Zhiwei wrote:
>>
>>
>> On 2020/6/29 6:51, Alistair Francis wrote:
>>> On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell 
>>> <peter.maydell@linaro.org> wrote:
>>>> On Fri, 26 Jun 2020 at 22:53, Alistair Francis 
>>>> <alistair.francis@wdc.com> wrote:
>>>>> The following changes since commit 
>>>>> 553cf5d7c47bee05a3dec9461c1f8430316d516b:
>>>>>
>>>>>    Merge remote-tracking branch 
>>>>> 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging 
>>>>> (2020-06-26 18:22:36 +0100)
>>>>>
>>>>> are available in the Git repository at:
>>>>>
>>>>>    git@github.com:alistair23/qemu.git 
>>>>> tags/pull-riscv-to-apply-20200626-1
>>>>>
>>>>> for you to fetch changes up to 
>>>>> b39d59434ea10649fdb9e0a339c30c76e38c5e17:
>>>>>
>>>>>    target/riscv: configure and turn on vector extension from 
>>>>> command line (2020-06-26 14:22:15 -0700)
>>>>>
>>>>> ----------------------------------------------------------------
>>>>> This PR contains two patches to improve PLIC support in QEMU.
>>>>>
>>>>> The rest of the PR is adding support for the v0.7.1 RISC-V vector
>>>>> extensions. This is experimental support as the vector extensions are
>>>>> still in a draft state.
>>>>>
>>>> Hi; I'm afraid this fails to build on PPC64 and s390x (ie
>>>> our big-endian hosts):
>> Hi Peter,
>>
>> Do you mean you built the patch set on PPC64 or s390x and got errors 
>> in the list? Or just a worry?
> >
>> I have built the patch set on Ubuntu 18.04 X86-64. I don't know which 
>> compile option
>> will fails the compilation. If you compiled on Ubuntu x86-64, could 
>> you show me the
>> compile option?
>
> The related code in your patch "target/riscv: add vector stride load 
> and store instructions" is in a "#ifdef HOST_WORDS_BIGENDIAN" section, 
> so of course this bug does not trigger on a x86 host. You could 
> temporarily turn the "#ifdef HOST_WORDS_BIGENDIAN" into a "#if 1" to 
> see whether you can then also reproduce the error on x86.
>
Yes. I can reproduce it in this way.
>> As a note: I try to find a PPC64 for test, but I'm afraid it will be 
>> too later.
>> Is there an available  PPC64  machine in the community?
>
> Maybe the easiest way to test your code on a big endian machine, too, 
> is to get a github account, clone the QEMU repository there, and 
> enable Travis for that repo. Then your code gets built on some non-x86 
> architectures (including a big-endian s390x) as soon as you push it to 
> the repo (see .travis.yml for details).
>
Thanks very much. I will have a try.
>>>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function 
>>>> ‘vext_clear’:
>>>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function 
>>>> ‘vext_clear’:
>>>> /home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
>>>> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>>>>           memset(tail & ~(7ULL), 0, part1);
>
> You obviously must not use "&" with a pointer. I guess you have to 
> cast to "uintptr_t" and back, or think of some other smart way to fix 
> this.
>
Yes. That's the error. It  build successfully after the cast.

Best Regards，
Zhiwei
>  Thomas
Re: [PULL 00/63] riscv-to-apply queue
Posted by Thomas Huth 3 years, 8 months ago 
On 30/06/2020 10.44, LIU Zhiwei wrote:
> 
> 
> On 2020/6/30 16:11, Thomas Huth wrote:
>> On 30/06/2020 08.56, LIU Zhiwei wrote:
>>>
>>>
>>> On 2020/6/29 6:51, Alistair Francis wrote:
>>>> On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell
>>>> <peter.maydell@linaro.org> wrote:
>>>>> On Fri, 26 Jun 2020 at 22:53, Alistair Francis
>>>>> <alistair.francis@wdc.com> wrote:
>>>>>> The following changes since commit
>>>>>> 553cf5d7c47bee05a3dec9461c1f8430316d516b:
>>>>>>
>>>>>>    Merge remote-tracking branch
>>>>>> 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging
>>>>>> (2020-06-26 18:22:36 +0100)
>>>>>>
>>>>>> are available in the Git repository at:
>>>>>>
>>>>>>    git@github.com:alistair23/qemu.git
>>>>>> tags/pull-riscv-to-apply-20200626-1
>>>>>>
>>>>>> for you to fetch changes up to
>>>>>> b39d59434ea10649fdb9e0a339c30c76e38c5e17:
>>>>>>
>>>>>>    target/riscv: configure and turn on vector extension from
>>>>>> command line (2020-06-26 14:22:15 -0700)
>>>>>>
>>>>>> ----------------------------------------------------------------
>>>>>> This PR contains two patches to improve PLIC support in QEMU.
>>>>>>
>>>>>> The rest of the PR is adding support for the v0.7.1 RISC-V vector
>>>>>> extensions. This is experimental support as the vector extensions are
>>>>>> still in a draft state.
>>>>>>
>>>>> Hi; I'm afraid this fails to build on PPC64 and s390x (ie
>>>>> our big-endian hosts):
>>> Hi Peter,
>>>
>>> Do you mean you built the patch set on PPC64 or s390x and got errors
>>> in the list? Or just a worry?
>> >
>>> I have built the patch set on Ubuntu 18.04 X86-64. I don't know which
>>> compile option
>>> will fails the compilation. If you compiled on Ubuntu x86-64, could
>>> you show me the
>>> compile option?
>>
>> The related code in your patch "target/riscv: add vector stride load
>> and store instructions" is in a "#ifdef HOST_WORDS_BIGENDIAN" section,
>> so of course this bug does not trigger on a x86 host. You could
>> temporarily turn the "#ifdef HOST_WORDS_BIGENDIAN" into a "#if 1" to
>> see whether you can then also reproduce the error on x86.
>>
> Yes. I can reproduce it in this way.
>>> As a note: I try to find a PPC64 for test, but I'm afraid it will be
>>> too later.
>>> Is there an available  PPC64  machine in the community?
>>
>> Maybe the easiest way to test your code on a big endian machine, too,
>> is to get a github account, clone the QEMU repository there, and
>> enable Travis for that repo. Then your code gets built on some non-x86
>> architectures (including a big-endian s390x) as soon as you push it to
>> the repo (see .travis.yml for details).
>>
> Thanks very much. I will have a try.
>>>>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function
>>>>> ‘vext_clear’:
>>>>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function
>>>>> ‘vext_clear’:
>>>>> /home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
>>>>> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>>>>>           memset(tail & ~(7ULL), 0, part1);
>>
>> You obviously must not use "&" with a pointer. I guess you have to
>> cast to "uintptr_t" and back, or think of some other smart way to fix
>> this.
>>
> Yes. That's the error. It  build successfully after the cast.

I'm sorry, but the new code fails to compile on big endian 32-bit
targets, see https://gitlab.com/huth/qemu/-/jobs/667762754#L3434 :

/builds/huth/qemu/target/riscv/vector_helper.c: In function 'vext_clear':
/builds/huth/qemu/target/riscv/vector_helper.c:154:16: error: cast to
pointer from integer of different size [-Werror=int-to-pointer-cast]
         memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1);
                ^
/builds/huth/qemu/target/riscv/vector_helper.c:155:16: error: cast to
pointer from integer of different size [-Werror=int-to-pointer-cast]
        memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2);
                ^
cc1: all warnings being treated as errors

A quick work-around is maybe to replace "ULL" with simply "UL" ?

 Thomas
Re: [PULL 00/63] riscv-to-apply queue
Posted by Philippe Mathieu-Daudé 3 years, 8 months ago 
On 8/3/20 7:53 PM, Thomas Huth wrote:
> On 30/06/2020 10.44, LIU Zhiwei wrote:
>>
>>
>> On 2020/6/30 16:11, Thomas Huth wrote:
>>> On 30/06/2020 08.56, LIU Zhiwei wrote:
>>>>
>>>>
>>>> On 2020/6/29 6:51, Alistair Francis wrote:
>>>>> On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell
>>>>> <peter.maydell@linaro.org> wrote:
>>>>>> On Fri, 26 Jun 2020 at 22:53, Alistair Francis
>>>>>> <alistair.francis@wdc.com> wrote:
>>>>>>> The following changes since commit
>>>>>>> 553cf5d7c47bee05a3dec9461c1f8430316d516b:
>>>>>>>
>>>>>>>    Merge remote-tracking branch
>>>>>>> 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging
>>>>>>> (2020-06-26 18:22:36 +0100)
>>>>>>>
>>>>>>> are available in the Git repository at:
>>>>>>>
>>>>>>>    git@github.com:alistair23/qemu.git
>>>>>>> tags/pull-riscv-to-apply-20200626-1
>>>>>>>
>>>>>>> for you to fetch changes up to
>>>>>>> b39d59434ea10649fdb9e0a339c30c76e38c5e17:
>>>>>>>
>>>>>>>    target/riscv: configure and turn on vector extension from
>>>>>>> command line (2020-06-26 14:22:15 -0700)
>>>>>>>
>>>>>>> ----------------------------------------------------------------
>>>>>>> This PR contains two patches to improve PLIC support in QEMU.
>>>>>>>
>>>>>>> The rest of the PR is adding support for the v0.7.1 RISC-V vector
>>>>>>> extensions. This is experimental support as the vector extensions are
>>>>>>> still in a draft state.
>>>>>>>
>>>>>> Hi; I'm afraid this fails to build on PPC64 and s390x (ie
>>>>>> our big-endian hosts):
>>>> Hi Peter,
>>>>
>>>> Do you mean you built the patch set on PPC64 or s390x and got errors
>>>> in the list? Or just a worry?
>>>>
>>>> I have built the patch set on Ubuntu 18.04 X86-64. I don't know which
>>>> compile option
>>>> will fails the compilation. If you compiled on Ubuntu x86-64, could
>>>> you show me the
>>>> compile option?
>>>
>>> The related code in your patch "target/riscv: add vector stride load
>>> and store instructions" is in a "#ifdef HOST_WORDS_BIGENDIAN" section,
>>> so of course this bug does not trigger on a x86 host. You could
>>> temporarily turn the "#ifdef HOST_WORDS_BIGENDIAN" into a "#if 1" to
>>> see whether you can then also reproduce the error on x86.
>>>
>> Yes. I can reproduce it in this way.
>>>> As a note: I try to find a PPC64 for test, but I'm afraid it will be
>>>> too later.
>>>> Is there an available  PPC64  machine in the community?
>>>
>>> Maybe the easiest way to test your code on a big endian machine, too,
>>> is to get a github account, clone the QEMU repository there, and
>>> enable Travis for that repo. Then your code gets built on some non-x86
>>> architectures (including a big-endian s390x) as soon as you push it to
>>> the repo (see .travis.yml for details).
>>>
>> Thanks very much. I will have a try.
>>>>>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function
>>>>>> ‘vext_clear’:
>>>>>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function
>>>>>> ‘vext_clear’:
>>>>>> /home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
>>>>>> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>>>>>>           memset(tail & ~(7ULL), 0, part1);
>>>
>>> You obviously must not use "&" with a pointer. I guess you have to
>>> cast to "uintptr_t" and back, or think of some other smart way to fix
>>> this.
>>>
>> Yes. That's the error. It  build successfully after the cast.
> 
> I'm sorry, but the new code fails to compile on big endian 32-bit
> targets, see https://gitlab.com/huth/qemu/-/jobs/667762754#L3434 :
> 
> /builds/huth/qemu/target/riscv/vector_helper.c: In function 'vext_clear':
> /builds/huth/qemu/target/riscv/vector_helper.c:154:16: error: cast to
> pointer from integer of different size [-Werror=int-to-pointer-cast]
>          memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1);
>                 ^
> /builds/huth/qemu/target/riscv/vector_helper.c:155:16: error: cast to
> pointer from integer of different size [-Werror=int-to-pointer-cast]
>         memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2);
>                 ^
> cc1: all warnings being treated as errors
> 
> A quick work-around is maybe to replace "ULL" with simply "UL" ?

Or use QEMU_ALIGN_PTR_DOWN?

> 
>  Thomas
> 
>
Re: [PULL 00/63] riscv-to-apply queue
Posted by Thomas Huth 3 years, 8 months ago 
On 03/08/2020 20.00, Philippe Mathieu-Daudé wrote:
> On 8/3/20 7:53 PM, Thomas Huth wrote:
>> On 30/06/2020 10.44, LIU Zhiwei wrote:
>>>
>>>
>>> On 2020/6/30 16:11, Thomas Huth wrote:
>>>> On 30/06/2020 08.56, LIU Zhiwei wrote:
>>>>>
>>>>>
>>>>> On 2020/6/29 6:51, Alistair Francis wrote:
>>>>>> On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell
>>>>>> <peter.maydell@linaro.org> wrote:
>>>>>>> On Fri, 26 Jun 2020 at 22:53, Alistair Francis
>>>>>>> <alistair.francis@wdc.com> wrote:
>>>>>>>> The following changes since commit
>>>>>>>> 553cf5d7c47bee05a3dec9461c1f8430316d516b:
>>>>>>>>
>>>>>>>>    Merge remote-tracking branch
>>>>>>>> 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging
>>>>>>>> (2020-06-26 18:22:36 +0100)
>>>>>>>>
>>>>>>>> are available in the Git repository at:
>>>>>>>>
>>>>>>>>    git@github.com:alistair23/qemu.git
>>>>>>>> tags/pull-riscv-to-apply-20200626-1
>>>>>>>>
>>>>>>>> for you to fetch changes up to
>>>>>>>> b39d59434ea10649fdb9e0a339c30c76e38c5e17:
>>>>>>>>
>>>>>>>>    target/riscv: configure and turn on vector extension from
>>>>>>>> command line (2020-06-26 14:22:15 -0700)
>>>>>>>>
>>>>>>>> ----------------------------------------------------------------
>>>>>>>> This PR contains two patches to improve PLIC support in QEMU.
>>>>>>>>
>>>>>>>> The rest of the PR is adding support for the v0.7.1 RISC-V vector
>>>>>>>> extensions. This is experimental support as the vector extensions are
>>>>>>>> still in a draft state.
>>>>>>>>
>>>>>>> Hi; I'm afraid this fails to build on PPC64 and s390x (ie
>>>>>>> our big-endian hosts):
>>>>> Hi Peter,
>>>>>
>>>>> Do you mean you built the patch set on PPC64 or s390x and got errors
>>>>> in the list? Or just a worry?
>>>>>
>>>>> I have built the patch set on Ubuntu 18.04 X86-64. I don't know which
>>>>> compile option
>>>>> will fails the compilation. If you compiled on Ubuntu x86-64, could
>>>>> you show me the
>>>>> compile option?
>>>>
>>>> The related code in your patch "target/riscv: add vector stride load
>>>> and store instructions" is in a "#ifdef HOST_WORDS_BIGENDIAN" section,
>>>> so of course this bug does not trigger on a x86 host. You could
>>>> temporarily turn the "#ifdef HOST_WORDS_BIGENDIAN" into a "#if 1" to
>>>> see whether you can then also reproduce the error on x86.
>>>>
>>> Yes. I can reproduce it in this way.
>>>>> As a note: I try to find a PPC64 for test, but I'm afraid it will be
>>>>> too later.
>>>>> Is there an available  PPC64  machine in the community?
>>>>
>>>> Maybe the easiest way to test your code on a big endian machine, too,
>>>> is to get a github account, clone the QEMU repository there, and
>>>> enable Travis for that repo. Then your code gets built on some non-x86
>>>> architectures (including a big-endian s390x) as soon as you push it to
>>>> the repo (see .travis.yml for details).
>>>>
>>> Thanks very much. I will have a try.
>>>>>>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function
>>>>>>> ‘vext_clear’:
>>>>>>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function
>>>>>>> ‘vext_clear’:
>>>>>>> /home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
>>>>>>> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>>>>>>>           memset(tail & ~(7ULL), 0, part1);
>>>>
>>>> You obviously must not use "&" with a pointer. I guess you have to
>>>> cast to "uintptr_t" and back, or think of some other smart way to fix
>>>> this.
>>>>
>>> Yes. That's the error. It  build successfully after the cast.
>>
>> I'm sorry, but the new code fails to compile on big endian 32-bit
>> targets, see https://gitlab.com/huth/qemu/-/jobs/667762754#L3434 :
>>
>> /builds/huth/qemu/target/riscv/vector_helper.c: In function 'vext_clear':
>> /builds/huth/qemu/target/riscv/vector_helper.c:154:16: error: cast to
>> pointer from integer of different size [-Werror=int-to-pointer-cast]
>>          memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1);
>>                 ^
>> /builds/huth/qemu/target/riscv/vector_helper.c:155:16: error: cast to
>> pointer from integer of different size [-Werror=int-to-pointer-cast]
>>         memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2);
>>                 ^
>> cc1: all warnings being treated as errors
>>
>> A quick work-around is maybe to replace "ULL" with simply "UL" ?
> 
> Or use QEMU_ALIGN_PTR_DOWN?

Sounds like a good idea! I'll give it a try and send a patch ...

 Thomas

Patchew 2.1-devel-0870f84

© 2016 - 2024 Red Hat, Inc.