1 | Mostly this is RTH's memtag series, but there are also some cleanups | 1 | Small pile of bug fixes for rc1. I've included my patches to get |
---|---|---|---|
2 | from Philippe. | 2 | our docs building with Sphinx 3, just for convenience... |
3 | 3 | ||
4 | thanks | ||
5 | -- PMM | 4 | -- PMM |
6 | 5 | ||
7 | The following changes since commit 10f7ffabf9c507fc02382b89912003b1c43c3231: | 6 | The following changes since commit b149dea55cce97cb226683d06af61984a1c11e96: |
8 | 7 | ||
9 | Merge remote-tracking branch 'remotes/mcayland/tags/qemu-macppc-20200626' into staging (2020-06-26 12:14:18 +0100) | 8 | Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20201102' into staging (2020-11-02 10:57:48 +0000) |
10 | 9 | ||
11 | are available in the Git repository at: | 10 | are available in the Git repository at: |
12 | 11 | ||
13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200626 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201102 |
14 | 13 | ||
15 | for you to fetch changes up to c7459633baa71d1781fde4a245d6ec9ce2f008cf: | 14 | for you to fetch changes up to ffb4fbf90a2f63c9cb33e4bb9f854c79bf04ca4a: |
16 | 15 | ||
17 | target/arm: Enable MTE (2020-06-26 14:32:24 +0100) | 16 | tests/qtest/npcm7xx_rng-test: Disable randomness tests (2020-11-02 16:52:18 +0000) |
18 | 17 | ||
19 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
20 | target-arm queue: | 19 | target-arm queue: |
21 | * hw/arm/aspeed: improve QOM usage | 20 | * target/arm: Fix Neon emulation bugs on big-endian hosts |
22 | * hw/misc/pca9552: trace GPIO change events | 21 | * target/arm: fix handling of HCR.FB |
23 | * target/arm: Implement ARMv8.5-MemTag for system emulation | 22 | * target/arm: fix LORID_EL1 access check |
23 | * disas/capstone: Fix monitor disassembly of >32 bytes | ||
24 | * hw/arm/smmuv3: Fix potential integer overflow (CID 1432363) | ||
25 | * hw/arm/boot: fix SVE for EL3 direct kernel boot | ||
26 | * hw/display/omap_lcdc: Fix potential NULL pointer dereference | ||
27 | * hw/display/exynos4210_fimd: Fix potential NULL pointer dereference | ||
28 | * target/arm: Get correct MMU index for other-security-state | ||
29 | * configure: Test that gio libs from pkg-config work | ||
30 | * hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work | ||
31 | * docs: Fix building with Sphinx 3 | ||
32 | * tests/qtest/npcm7xx_rng-test: Disable randomness tests | ||
24 | 33 | ||
25 | ---------------------------------------------------------------- | 34 | ---------------------------------------------------------------- |
26 | Philippe Mathieu-Daudé (12): | 35 | AlexChen (2): |
27 | hw/arm/aspeed: Remove extraneous MemoryRegion object owner | 36 | hw/display/omap_lcdc: Fix potential NULL pointer dereference |
28 | hw/arm/aspeed: Rename AspeedBoardState as AspeedMachineState | 37 | hw/display/exynos4210_fimd: Fix potential NULL pointer dereference |
29 | hw/arm/aspeed: QOM'ify AspeedMachineState | ||
30 | hw/i2c/core: Add i2c_try_create_slave() and i2c_realize_and_unref() | ||
31 | hw/misc/pca9552: Rename 'nr_leds' as 'pin_count' | ||
32 | hw/misc/pca9552: Rename generic code as pca955x | ||
33 | hw/misc/pca9552: Add generic PCA955xClass, parent of TYPE_PCA9552 | ||
34 | hw/misc/pca9552: Add a 'description' property for debugging purpose | ||
35 | hw/misc/pca9552: Trace GPIO High/Low events | ||
36 | hw/arm/aspeed: Describe each PCA9552 device | ||
37 | hw/misc/pca9552: Trace GPIO change events | ||
38 | hw/misc/pca9552: Model qdev output GPIOs | ||
39 | 38 | ||
40 | Richard Henderson (45): | 39 | Peter Maydell (9): |
41 | target/arm: Add isar tests for mte | 40 | target/arm: Fix float16 pairwise Neon ops on big-endian hosts |
42 | target/arm: Improve masking of SCR RES0 bits | 41 | target/arm: Fix VUDOT/VSDOT (scalar) on big-endian hosts |
43 | target/arm: Add support for MTE to SCTLR_ELx | 42 | disas/capstone: Fix monitor disassembly of >32 bytes |
44 | target/arm: Add support for MTE to HCR_EL2 and SCR_EL3 | 43 | target/arm: Get correct MMU index for other-security-state |
45 | target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT | 44 | configure: Test that gio libs from pkg-config work |
46 | target/arm: Add DISAS_UPDATE_NOCHAIN | 45 | hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work |
47 | target/arm: Add MTE system registers | 46 | scripts/kerneldoc: For Sphinx 3 use c:macro for macros with arguments |
48 | target/arm: Add MTE bits to tb_flags | 47 | qemu-option-trace.rst.inc: Don't use option:: markup |
49 | target/arm: Implement the IRG instruction | 48 | tests/qtest/npcm7xx_rng-test: Disable randomness tests |
50 | target/arm: Revise decoding for disas_add_sub_imm | ||
51 | target/arm: Implement the ADDG, SUBG instructions | ||
52 | target/arm: Implement the GMI instruction | ||
53 | target/arm: Implement the SUBP instruction | ||
54 | target/arm: Define arm_cpu_do_unaligned_access for user-only | ||
55 | target/arm: Implement LDG, STG, ST2G instructions | ||
56 | target/arm: Implement the STGP instruction | ||
57 | target/arm: Restrict the values of DCZID.BS under TCG | ||
58 | target/arm: Simplify DC_ZVA | ||
59 | target/arm: Implement the LDGM, STGM, STZGM instructions | ||
60 | target/arm: Implement the access tag cache flushes | ||
61 | target/arm: Move regime_el to internals.h | ||
62 | target/arm: Move regime_tcr to internals.h | ||
63 | target/arm: Add gen_mte_check1 | ||
64 | target/arm: Add gen_mte_checkN | ||
65 | target/arm: Implement helper_mte_check1 | ||
66 | target/arm: Implement helper_mte_checkN | ||
67 | target/arm: Add helper_mte_check_zva | ||
68 | target/arm: Use mte_checkN for sve unpredicated loads | ||
69 | target/arm: Use mte_checkN for sve unpredicated stores | ||
70 | target/arm: Use mte_check1 for sve LD1R | ||
71 | target/arm: Tidy trans_LD1R_zpri | ||
72 | target/arm: Add arm_tlb_bti_gp | ||
73 | target/arm: Add mte helpers for sve scalar + int loads | ||
74 | target/arm: Add mte helpers for sve scalar + int stores | ||
75 | target/arm: Add mte helpers for sve scalar + int ff/nf loads | ||
76 | target/arm: Handle TBI for sve scalar + int memory ops | ||
77 | target/arm: Add mte helpers for sve scatter/gather memory ops | ||
78 | target/arm: Complete TBI clearing for user-only for SVE | ||
79 | target/arm: Implement data cache set allocation tags | ||
80 | target/arm: Set PSTATE.TCO on exception entry | ||
81 | target/arm: Always pass cacheattr to get_phys_addr | ||
82 | target/arm: Cache the Tagged bit for a page in MemTxAttrs | ||
83 | target/arm: Create tagged ram when MTE is enabled | ||
84 | target/arm: Add allocation tag storage for system mode | ||
85 | target/arm: Enable MTE | ||
86 | 49 | ||
87 | include/hw/arm/aspeed.h | 12 +- | 50 | Philippe Mathieu-Daudé (1): |
88 | include/hw/i2c/i2c.h | 2 + | 51 | hw/arm/smmuv3: Fix potential integer overflow (CID 1432363) |
89 | include/hw/misc/pca9552.h | 16 +- | ||
90 | target/arm/cpu.h | 50 +- | ||
91 | target/arm/helper-a64.h | 16 + | ||
92 | target/arm/helper-sve.h | 488 ++++++++++++++ | ||
93 | target/arm/helper.h | 2 + | ||
94 | target/arm/internals.h | 153 ++++- | ||
95 | target/arm/translate-a64.h | 5 + | ||
96 | target/arm/translate.h | 23 +- | ||
97 | hw/arm/aspeed.c | 46 +- | ||
98 | hw/arm/virt.c | 55 +- | ||
99 | hw/i2c/core.c | 18 +- | ||
100 | hw/misc/pca9552.c | 216 +++++-- | ||
101 | target/arm/cpu.c | 81 ++- | ||
102 | target/arm/cpu64.c | 5 + | ||
103 | target/arm/helper-a64.c | 94 +-- | ||
104 | target/arm/helper.c | 423 ++++++++++--- | ||
105 | target/arm/m_helper.c | 11 +- | ||
106 | target/arm/mte_helper.c | 906 ++++++++++++++++++++++++++ | ||
107 | target/arm/op_helper.c | 16 + | ||
108 | target/arm/sve_helper.c | 616 ++++++++++++++---- | ||
109 | target/arm/tlb_helper.c | 13 +- | ||
110 | target/arm/translate-a64.c | 657 ++++++++++++++++--- | ||
111 | target/arm/translate-sve.c | 1366 ++++++++++++++++++++++++++-------------- | ||
112 | target/arm/translate-vfp.inc.c | 4 +- | ||
113 | target/arm/translate.c | 16 +- | ||
114 | hw/misc/trace-events | 4 + | ||
115 | target/arm/Makefile.objs | 1 + | ||
116 | 29 files changed, 4391 insertions(+), 924 deletions(-) | ||
117 | create mode 100644 target/arm/mte_helper.c | ||
118 | 52 | ||
53 | Richard Henderson (11): | ||
54 | target/arm: Introduce neon_full_reg_offset | ||
55 | target/arm: Move neon_element_offset to translate.c | ||
56 | target/arm: Use neon_element_offset in neon_load/store_reg | ||
57 | target/arm: Use neon_element_offset in vfp_reg_offset | ||
58 | target/arm: Add read/write_neon_element32 | ||
59 | target/arm: Expand read/write_neon_element32 to all MemOp | ||
60 | target/arm: Rename neon_load_reg32 to vfp_load_reg32 | ||
61 | target/arm: Add read/write_neon_element64 | ||
62 | target/arm: Rename neon_load_reg64 to vfp_load_reg64 | ||
63 | target/arm: Simplify do_long_3d and do_2scalar_long | ||
64 | target/arm: Improve do_prewiden_3d | ||
65 | |||
66 | Rémi Denis-Courmont (3): | ||
67 | target/arm: fix handling of HCR.FB | ||
68 | target/arm: fix LORID_EL1 access check | ||
69 | hw/arm/boot: fix SVE for EL3 direct kernel boot | ||
70 | |||
71 | docs/qemu-option-trace.rst.inc | 6 +- | ||
72 | configure | 10 +- | ||
73 | include/hw/intc/arm_gicv3_common.h | 1 - | ||
74 | disas/capstone.c | 2 +- | ||
75 | hw/arm/boot.c | 3 + | ||
76 | hw/arm/smmuv3.c | 3 +- | ||
77 | hw/display/exynos4210_fimd.c | 4 +- | ||
78 | hw/display/omap_lcdc.c | 10 +- | ||
79 | hw/intc/arm_gicv3_cpuif.c | 5 +- | ||
80 | target/arm/helper.c | 24 +- | ||
81 | target/arm/m_helper.c | 3 +- | ||
82 | target/arm/translate.c | 153 +++++++++--- | ||
83 | target/arm/vec_helper.c | 12 +- | ||
84 | tests/qtest/npcm7xx_rng-test.c | 14 +- | ||
85 | scripts/kernel-doc | 18 +- | ||
86 | target/arm/translate-neon.c.inc | 472 ++++++++++++++++++++----------------- | ||
87 | target/arm/translate-vfp.c.inc | 341 +++++++++++---------------- | ||
88 | 17 files changed, 588 insertions(+), 493 deletions(-) | ||
89 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | I'm confused by this code, 'bmc' is created as: | ||
4 | |||
5 | bmc = g_new0(AspeedBoardState, 1); | ||
6 | |||
7 | Then we use it as QOM owner for different MemoryRegion objects. | ||
8 | But looking at memory_region_init_ram (similarly for ROM): | ||
9 | |||
10 | void memory_region_init_ram(MemoryRegion *mr, | ||
11 | struct Object *owner, | ||
12 | const char *name, | ||
13 | uint64_t size, | ||
14 | Error **errp) | ||
15 | { | ||
16 | DeviceState *owner_dev; | ||
17 | Error *err = NULL; | ||
18 | |||
19 | memory_region_init_ram_nomigrate(mr, owner, name, size, &err); | ||
20 | if (err) { | ||
21 | error_propagate(errp, err); | ||
22 | return; | ||
23 | } | ||
24 | /* This will assert if owner is neither NULL nor a DeviceState. | ||
25 | * We only want the owner here for the purposes of defining a | ||
26 | * unique name for migration. TODO: Ideally we should implement | ||
27 | * a naming scheme for Objects which are not DeviceStates, in | ||
28 | * which case we can relax this restriction. | ||
29 | */ | ||
30 | owner_dev = DEVICE(owner); | ||
31 | vmstate_register_ram(mr, owner_dev); | ||
32 | } | ||
33 | |||
34 | The expected assertion is not triggered ('bmc' is not NULL neither | ||
35 | a DeviceState). | ||
36 | |||
37 | 'bmc' structure is defined as: | ||
38 | |||
39 | struct AspeedBoardState { | ||
40 | AspeedSoCState soc; | ||
41 | MemoryRegion ram_container; | ||
42 | MemoryRegion max_ram; | ||
43 | }; | ||
44 | |||
45 | What happens is when using 'OBJECT(bmc)', the QOM macros cast the | ||
46 | memory pointed by bmc, which first member is 'soc', which is | ||
47 | initialized ...: | ||
48 | |||
49 | object_initialize_child(OBJECT(machine), "soc", | ||
50 | &bmc->soc, amc->soc_name); | ||
51 | |||
52 | The 'soc' object is indeed a DeviceState, so the assertion passes. | ||
53 | |||
54 | Since this is fragile and only happens to work by luck, remove the | ||
55 | dangerous OBJECT(bmc) owner argument. | ||
56 | |||
57 | Note, this probably breaks migration for this machine. | ||
58 | |||
59 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
60 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
61 | Message-id: 20200623072132.2868-2-f4bug@amsat.org | ||
62 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
63 | --- | ||
64 | hw/arm/aspeed.c | 6 +++--- | ||
65 | 1 file changed, 3 insertions(+), 3 deletions(-) | ||
66 | |||
67 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | ||
68 | index XXXXXXX..XXXXXXX 100644 | ||
69 | --- a/hw/arm/aspeed.c | ||
70 | +++ b/hw/arm/aspeed.c | ||
71 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine) | ||
72 | * needed by the flash modules of the Aspeed machines. | ||
73 | */ | ||
74 | if (ASPEED_MACHINE(machine)->mmio_exec) { | ||
75 | - memory_region_init_alias(boot_rom, OBJECT(bmc), "aspeed.boot_rom", | ||
76 | + memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom", | ||
77 | &fl->mmio, 0, fl->size); | ||
78 | memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, | ||
79 | boot_rom); | ||
80 | } else { | ||
81 | - memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", | ||
82 | + memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", | ||
83 | fl->size, &error_abort); | ||
84 | memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, | ||
85 | boot_rom); | ||
86 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine) | ||
87 | if (machine->kernel_filename && sc->num_cpus > 1) { | ||
88 | /* With no u-boot we must set up a boot stub for the secondary CPU */ | ||
89 | MemoryRegion *smpboot = g_new(MemoryRegion, 1); | ||
90 | - memory_region_init_ram(smpboot, OBJECT(bmc), "aspeed.smpboot", | ||
91 | + memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", | ||
92 | 0x80, &error_abort); | ||
93 | memory_region_add_subregion(get_system_memory(), | ||
94 | AST_SMP_MAILBOX_BASE, smpboot); | ||
95 | -- | ||
96 | 2.20.1 | ||
97 | |||
98 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This function makes it clear that we're talking about the whole | ||
4 | register, and not the 32-bit piece at index 0. This fixes a bug | ||
5 | when running on a big-endian host. | ||
6 | |||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20201030022618.785675-2-richard.henderson@linaro.org | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Message-id: 20200626033144.790098-44-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 11 | --- |
8 | target/arm/cpu.h | 6 ++++++ | 12 | target/arm/translate.c | 8 ++++++ |
9 | hw/arm/virt.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++-- | 13 | target/arm/translate-neon.c.inc | 44 ++++++++++++++++----------------- |
10 | target/arm/cpu.c | 52 +++++++++++++++++++++++++++++++++++++++++---- | 14 | target/arm/translate-vfp.c.inc | 2 +- |
11 | 3 files changed, 107 insertions(+), 6 deletions(-) | 15 | 3 files changed, 31 insertions(+), 23 deletions(-) |
12 | 16 | ||
13 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 17 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
14 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/cpu.h | 19 | --- a/target/arm/translate.c |
16 | +++ b/target/arm/cpu.h | 20 | +++ b/target/arm/translate.c |
17 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | 21 | @@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm) |
18 | /* MemoryRegion to use for secure physical accesses */ | 22 | unallocated_encoding(s); |
19 | MemoryRegion *secure_memory; | ||
20 | |||
21 | + /* MemoryRegion to use for allocation tag accesses */ | ||
22 | + MemoryRegion *tag_memory; | ||
23 | + MemoryRegion *secure_tag_memory; | ||
24 | + | ||
25 | /* For v8M, pointer to the IDAU interface provided by board/SoC */ | ||
26 | Object *idau; | ||
27 | |||
28 | @@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit { | ||
29 | typedef enum ARMASIdx { | ||
30 | ARMASIdx_NS = 0, | ||
31 | ARMASIdx_S = 1, | ||
32 | + ARMASIdx_TagNS = 2, | ||
33 | + ARMASIdx_TagS = 3, | ||
34 | } ARMASIdx; | ||
35 | |||
36 | /* Return the Exception Level targeted by debug exceptions. */ | ||
37 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/hw/arm/virt.c | ||
40 | +++ b/hw/arm/virt.c | ||
41 | @@ -XXX,XX +XXX,XX @@ static void create_platform_bus(VirtMachineState *vms) | ||
42 | sysbus_mmio_get_region(s, 0)); | ||
43 | } | 23 | } |
44 | 24 | ||
45 | +static void create_tag_ram(MemoryRegion *tag_sysmem, | 25 | +/* |
46 | + hwaddr base, hwaddr size, | 26 | + * Return the offset of a "full" NEON Dreg. |
47 | + const char *name) | 27 | + */ |
28 | +static long neon_full_reg_offset(unsigned reg) | ||
48 | +{ | 29 | +{ |
49 | + MemoryRegion *tagram = g_new(MemoryRegion, 1); | 30 | + return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); |
50 | + | ||
51 | + memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); | ||
52 | + memory_region_add_subregion(tag_sysmem, base / 32, tagram); | ||
53 | +} | 31 | +} |
54 | + | 32 | + |
55 | static void create_secure_ram(VirtMachineState *vms, | 33 | static inline long vfp_reg_offset(bool dp, unsigned reg) |
56 | - MemoryRegion *secure_sysmem) | ||
57 | + MemoryRegion *secure_sysmem, | ||
58 | + MemoryRegion *secure_tag_sysmem) | ||
59 | { | 34 | { |
60 | MemoryRegion *secram = g_new(MemoryRegion, 1); | 35 | if (dp) { |
61 | char *nodename; | 36 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc |
62 | @@ -XXX,XX +XXX,XX @@ static void create_secure_ram(VirtMachineState *vms, | 37 | index XXXXXXX..XXXXXXX 100644 |
63 | qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); | 38 | --- a/target/arm/translate-neon.c.inc |
64 | qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); | 39 | +++ b/target/arm/translate-neon.c.inc |
65 | 40 | @@ -XXX,XX +XXX,XX @@ neon_element_offset(int reg, int element, MemOp size) | |
66 | + if (secure_tag_sysmem) { | 41 | ofs ^= 8 - element_size; |
67 | + create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); | 42 | } |
68 | + } | 43 | #endif |
69 | + | 44 | - return neon_reg_offset(reg, 0) + ofs; |
70 | g_free(nodename); | 45 | + return neon_full_reg_offset(reg) + ofs; |
71 | } | 46 | } |
72 | 47 | ||
73 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | 48 | static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) |
74 | const CPUArchIdList *possible_cpus; | 49 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) |
75 | MemoryRegion *sysmem = get_system_memory(); | 50 | * We cannot write 16 bytes at once because the |
76 | MemoryRegion *secure_sysmem = NULL; | 51 | * destination is unaligned. |
77 | + MemoryRegion *tag_sysmem = NULL; | 52 | */ |
78 | + MemoryRegion *secure_tag_sysmem = NULL; | 53 | - tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0), |
79 | int n, virt_max_cpus; | 54 | + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd), |
80 | bool firmware_loaded; | 55 | 8, 8, tmp); |
81 | bool aarch64 = true; | 56 | - tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0), |
82 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | 57 | - neon_reg_offset(vd, 0), 8, 8); |
83 | "secure-memory", &error_abort); | 58 | + tcg_gen_gvec_mov(0, neon_full_reg_offset(vd + 1), |
59 | + neon_full_reg_offset(vd), 8, 8); | ||
60 | } else { | ||
61 | - tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0), | ||
62 | + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd), | ||
63 | vec_size, vec_size, tmp); | ||
84 | } | 64 | } |
85 | 65 | tcg_gen_addi_i32(addr, addr, 1 << size); | |
86 | + /* | 66 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) |
87 | + * The cpu adds the property if and only if MemTag is supported. | 67 | static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn) |
88 | + * If it is, we must allocate the ram to back that up. | 68 | { |
89 | + */ | 69 | int vec_size = a->q ? 16 : 8; |
90 | + if (object_property_find(cpuobj, "tag-memory", NULL)) { | 70 | - int rd_ofs = neon_reg_offset(a->vd, 0); |
91 | + if (!tag_sysmem) { | 71 | - int rn_ofs = neon_reg_offset(a->vn, 0); |
92 | + tag_sysmem = g_new(MemoryRegion, 1); | 72 | - int rm_ofs = neon_reg_offset(a->vm, 0); |
93 | + memory_region_init(tag_sysmem, OBJECT(machine), | 73 | + int rd_ofs = neon_full_reg_offset(a->vd); |
94 | + "tag-memory", UINT64_MAX / 32); | 74 | + int rn_ofs = neon_full_reg_offset(a->vn); |
95 | + | 75 | + int rm_ofs = neon_full_reg_offset(a->vm); |
96 | + if (vms->secure) { | 76 | |
97 | + secure_tag_sysmem = g_new(MemoryRegion, 1); | 77 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { |
98 | + memory_region_init(secure_tag_sysmem, OBJECT(machine), | 78 | return false; |
99 | + "secure-tag-memory", UINT64_MAX / 32); | 79 | @@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn) |
100 | + | 80 | { |
101 | + /* As with ram, secure-tag takes precedence over tag. */ | 81 | /* Handle a 2-reg-shift insn which can be vectorized. */ |
102 | + memory_region_add_subregion_overlap(secure_tag_sysmem, 0, | 82 | int vec_size = a->q ? 16 : 8; |
103 | + tag_sysmem, -1); | 83 | - int rd_ofs = neon_reg_offset(a->vd, 0); |
104 | + } | 84 | - int rm_ofs = neon_reg_offset(a->vm, 0); |
105 | + } | 85 | + int rd_ofs = neon_full_reg_offset(a->vd); |
106 | + | 86 | + int rm_ofs = neon_full_reg_offset(a->vm); |
107 | + object_property_set_link(cpuobj, OBJECT(tag_sysmem), | 87 | |
108 | + "tag-memory", &error_abort); | 88 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { |
109 | + if (vms->secure) { | 89 | return false; |
110 | + object_property_set_link(cpuobj, OBJECT(secure_tag_sysmem), | 90 | @@ -XXX,XX +XXX,XX @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a, |
111 | + "secure-tag-memory", &error_abort); | 91 | { |
112 | + } | 92 | /* FP operations in 2-reg-and-shift group */ |
113 | + } | 93 | int vec_size = a->q ? 16 : 8; |
114 | + | 94 | - int rd_ofs = neon_reg_offset(a->vd, 0); |
115 | qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); | 95 | - int rm_ofs = neon_reg_offset(a->vm, 0); |
116 | object_unref(cpuobj); | 96 | + int rd_ofs = neon_full_reg_offset(a->vd); |
97 | + int rm_ofs = neon_full_reg_offset(a->vm); | ||
98 | TCGv_ptr fpst; | ||
99 | |||
100 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
101 | @@ -XXX,XX +XXX,XX @@ static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a, | ||
102 | return true; | ||
117 | } | 103 | } |
118 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | 104 | |
119 | create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); | 105 | - reg_ofs = neon_reg_offset(a->vd, 0); |
120 | 106 | + reg_ofs = neon_full_reg_offset(a->vd); | |
121 | if (vms->secure) { | 107 | vec_size = a->q ? 16 : 8; |
122 | - create_secure_ram(vms, secure_sysmem); | 108 | imm = asimd_imm_const(a->imm, a->cmode, a->op); |
123 | + create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); | 109 | |
124 | create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); | 110 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a) |
111 | return true; | ||
125 | } | 112 | } |
126 | 113 | ||
127 | + if (tag_sysmem) { | 114 | - tcg_gen_gvec_3_ool(neon_reg_offset(a->vd, 0), |
128 | + create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, | 115 | - neon_reg_offset(a->vn, 0), |
129 | + machine->ram_size, "mach-virt.tag"); | 116 | - neon_reg_offset(a->vm, 0), |
130 | + } | 117 | + tcg_gen_gvec_3_ool(neon_full_reg_offset(a->vd), |
131 | + | 118 | + neon_full_reg_offset(a->vn), |
132 | vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64); | 119 | + neon_full_reg_offset(a->vm), |
133 | 120 | 16, 16, 0, fn_gvec); | |
134 | create_rtc(vms); | 121 | return true; |
135 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 122 | } |
123 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a, | ||
124 | { | ||
125 | /* Two registers and a scalar, using gvec */ | ||
126 | int vec_size = a->q ? 16 : 8; | ||
127 | - int rd_ofs = neon_reg_offset(a->vd, 0); | ||
128 | - int rn_ofs = neon_reg_offset(a->vn, 0); | ||
129 | + int rd_ofs = neon_full_reg_offset(a->vd); | ||
130 | + int rn_ofs = neon_full_reg_offset(a->vn); | ||
131 | int rm_ofs; | ||
132 | int idx; | ||
133 | TCGv_ptr fpstatus; | ||
134 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a, | ||
135 | /* a->vm is M:Vm, which encodes both register and index */ | ||
136 | idx = extract32(a->vm, a->size + 2, 2); | ||
137 | a->vm = extract32(a->vm, 0, a->size + 2); | ||
138 | - rm_ofs = neon_reg_offset(a->vm, 0); | ||
139 | + rm_ofs = neon_full_reg_offset(a->vm); | ||
140 | |||
141 | fpstatus = fpstatus_ptr(a->size == 1 ? FPST_STD_F16 : FPST_STD); | ||
142 | tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpstatus, | ||
143 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a) | ||
144 | return true; | ||
145 | } | ||
146 | |||
147 | - tcg_gen_gvec_dup_mem(a->size, neon_reg_offset(a->vd, 0), | ||
148 | + tcg_gen_gvec_dup_mem(a->size, neon_full_reg_offset(a->vd), | ||
149 | neon_element_offset(a->vm, a->index, a->size), | ||
150 | a->q ? 16 : 8, a->q ? 16 : 8); | ||
151 | return true; | ||
152 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a) | ||
153 | static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn) | ||
154 | { | ||
155 | int vec_size = a->q ? 16 : 8; | ||
156 | - int rd_ofs = neon_reg_offset(a->vd, 0); | ||
157 | - int rm_ofs = neon_reg_offset(a->vm, 0); | ||
158 | + int rd_ofs = neon_full_reg_offset(a->vd); | ||
159 | + int rm_ofs = neon_full_reg_offset(a->vm); | ||
160 | |||
161 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
162 | return false; | ||
163 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
136 | index XXXXXXX..XXXXXXX 100644 | 164 | index XXXXXXX..XXXXXXX 100644 |
137 | --- a/target/arm/cpu.c | 165 | --- a/target/arm/translate-vfp.c.inc |
138 | +++ b/target/arm/cpu.c | 166 | +++ b/target/arm/translate-vfp.c.inc |
139 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj) | 167 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) |
140 | if (kvm_enabled()) { | ||
141 | kvm_arm_add_vcpu_properties(obj); | ||
142 | } | 168 | } |
143 | + | 169 | |
144 | +#ifndef CONFIG_USER_ONLY | 170 | tmp = load_reg(s, a->rt); |
145 | + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && | 171 | - tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0), |
146 | + cpu_isar_feature(aa64_mte, cpu)) { | 172 | + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(a->vn), |
147 | + object_property_add_link(obj, "tag-memory", | 173 | vec_size, vec_size, tmp); |
148 | + TYPE_MEMORY_REGION, | 174 | tcg_temp_free_i32(tmp); |
149 | + (Object **)&cpu->tag_memory, | 175 | |
150 | + qdev_prop_allow_set_link_before_realize, | ||
151 | + OBJ_PROP_LINK_STRONG); | ||
152 | + | ||
153 | + if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { | ||
154 | + object_property_add_link(obj, "secure-tag-memory", | ||
155 | + TYPE_MEMORY_REGION, | ||
156 | + (Object **)&cpu->secure_tag_memory, | ||
157 | + qdev_prop_allow_set_link_before_realize, | ||
158 | + OBJ_PROP_LINK_STRONG); | ||
159 | + } | ||
160 | + } | ||
161 | +#endif | ||
162 | } | ||
163 | |||
164 | static void arm_cpu_finalizefn(Object *obj) | ||
165 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
166 | #ifndef CONFIG_USER_ONLY | ||
167 | MachineState *ms = MACHINE(qdev_get_machine()); | ||
168 | unsigned int smp_cpus = ms->smp.cpus; | ||
169 | + bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); | ||
170 | |||
171 | - if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { | ||
172 | - cs->num_ases = 2; | ||
173 | + /* | ||
174 | + * We must set cs->num_ases to the final value before | ||
175 | + * the first call to cpu_address_space_init. | ||
176 | + */ | ||
177 | + if (cpu->tag_memory != NULL) { | ||
178 | + cs->num_ases = 3 + has_secure; | ||
179 | + } else { | ||
180 | + cs->num_ases = 1 + has_secure; | ||
181 | + } | ||
182 | |||
183 | + if (has_secure) { | ||
184 | if (!cpu->secure_memory) { | ||
185 | cpu->secure_memory = cs->memory; | ||
186 | } | ||
187 | cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", | ||
188 | cpu->secure_memory); | ||
189 | - } else { | ||
190 | - cs->num_ases = 1; | ||
191 | } | ||
192 | + | ||
193 | + if (cpu->tag_memory != NULL) { | ||
194 | + cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", | ||
195 | + cpu->tag_memory); | ||
196 | + if (has_secure) { | ||
197 | + cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", | ||
198 | + cpu->secure_tag_memory); | ||
199 | + } | ||
200 | + } else if (cpu_isar_feature(aa64_mte, cpu)) { | ||
201 | + /* | ||
202 | + * Since there is no tag memory, we can't meaningfully support MTE | ||
203 | + * to its fullest. To avoid problems later, when we would come to | ||
204 | + * use the tag memory, downgrade support to insns only. | ||
205 | + */ | ||
206 | + cpu->isar.id_aa64pfr1 = | ||
207 | + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); | ||
208 | + } | ||
209 | + | ||
210 | cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); | ||
211 | |||
212 | /* No core_count specified, default to smp_cpus. */ | ||
213 | -- | 176 | -- |
214 | 2.20.1 | 177 | 2.20.1 |
215 | 178 | ||
216 | 179 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We will shortly need this in mte_helper.c as well. | 3 | This will shortly have users outside of translate-neon.c.inc. |
4 | 4 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20201030022618.785675-3-richard.henderson@linaro.org | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20200626033144.790098-23-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 9 | --- |
10 | target/arm/internals.h | 9 +++++++++ | 10 | target/arm/translate.c | 20 ++++++++++++++++++++ |
11 | target/arm/helper.c | 9 --------- | 11 | target/arm/translate-neon.c.inc | 19 ------------------- |
12 | 2 files changed, 9 insertions(+), 9 deletions(-) | 12 | 2 files changed, 20 insertions(+), 19 deletions(-) |
13 | 13 | ||
14 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 14 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/internals.h | 16 | --- a/target/arm/translate.c |
17 | +++ b/target/arm/internals.h | 17 | +++ b/target/arm/translate.c |
18 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | 18 | @@ -XXX,XX +XXX,XX @@ static long neon_full_reg_offset(unsigned reg) |
19 | } | 19 | return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); |
20 | } | 20 | } |
21 | 21 | ||
22 | +/* Return the TCR controlling this translation regime */ | 22 | +/* |
23 | +static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) | 23 | + * Return the offset of a 2**SIZE piece of a NEON register, at index ELE, |
24 | + * where 0 is the least significant end of the register. | ||
25 | + */ | ||
26 | +static long neon_element_offset(int reg, int element, MemOp size) | ||
24 | +{ | 27 | +{ |
25 | + if (mmu_idx == ARMMMUIdx_Stage2) { | 28 | + int element_size = 1 << size; |
26 | + return &env->cp15.vtcr_el2; | 29 | + int ofs = element * element_size; |
30 | +#ifdef HOST_WORDS_BIGENDIAN | ||
31 | + /* | ||
32 | + * Calculate the offset assuming fully little-endian, | ||
33 | + * then XOR to account for the order of the 8-byte units. | ||
34 | + */ | ||
35 | + if (element_size < 8) { | ||
36 | + ofs ^= 8 - element_size; | ||
27 | + } | 37 | + } |
28 | + return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; | 38 | +#endif |
39 | + return neon_full_reg_offset(reg) + ofs; | ||
29 | +} | 40 | +} |
30 | + | 41 | + |
31 | /* Return the FSR value for a debug exception (watchpoint, hardware | 42 | static inline long vfp_reg_offset(bool dp, unsigned reg) |
32 | * breakpoint or BKPT insn) targeting the specified exception level. | 43 | { |
33 | */ | 44 | if (dp) { |
34 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 45 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc |
35 | index XXXXXXX..XXXXXXX 100644 | 46 | index XXXXXXX..XXXXXXX 100644 |
36 | --- a/target/arm/helper.c | 47 | --- a/target/arm/translate-neon.c.inc |
37 | +++ b/target/arm/helper.c | 48 | +++ b/target/arm/translate-neon.c.inc |
38 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, | 49 | @@ -XXX,XX +XXX,XX @@ static inline int neon_3same_fp_size(DisasContext *s, int x) |
39 | 50 | #include "decode-neon-ls.c.inc" | |
40 | #endif /* !CONFIG_USER_ONLY */ | 51 | #include "decode-neon-shared.c.inc" |
41 | 52 | ||
42 | -/* Return the TCR controlling this translation regime */ | 53 | -/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE, |
43 | -static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) | 54 | - * where 0 is the least significant end of the register. |
55 | - */ | ||
56 | -static inline long | ||
57 | -neon_element_offset(int reg, int element, MemOp size) | ||
44 | -{ | 58 | -{ |
45 | - if (mmu_idx == ARMMMUIdx_Stage2) { | 59 | - int element_size = 1 << size; |
46 | - return &env->cp15.vtcr_el2; | 60 | - int ofs = element * element_size; |
61 | -#ifdef HOST_WORDS_BIGENDIAN | ||
62 | - /* Calculate the offset assuming fully little-endian, | ||
63 | - * then XOR to account for the order of the 8-byte units. | ||
64 | - */ | ||
65 | - if (element_size < 8) { | ||
66 | - ofs ^= 8 - element_size; | ||
47 | - } | 67 | - } |
48 | - return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; | 68 | -#endif |
69 | - return neon_full_reg_offset(reg) + ofs; | ||
49 | -} | 70 | -} |
50 | - | 71 | - |
51 | /* Convert a possible stage1+2 MMU index into the appropriate | 72 | static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) |
52 | * stage 1 MMU index | 73 | { |
53 | */ | 74 | long offset = neon_element_offset(reg, ele, mop & MO_SIZE); |
54 | -- | 75 | -- |
55 | 2.20.1 | 76 | 2.20.1 |
56 | 77 | ||
57 | 78 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Because the elements are sequential, we can eliminate many tests all | 3 | These are the only users of neon_reg_offset, so remove that. |
4 | at once when the tag hits TCMA, or if the page(s) are not Tagged. | ||
5 | 4 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20201030022618.785675-4-richard.henderson@linaro.org | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20200626033144.790098-35-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 9 | --- |
11 | target/arm/helper-sve.h | 47 +++++++++++ | 10 | target/arm/translate.c | 14 ++------------ |
12 | target/arm/sve_helper.c | 95 ++++++++++++++++------ | 11 | 1 file changed, 2 insertions(+), 12 deletions(-) |
13 | target/arm/translate-sve.c | 162 ++++++++++++++++++++++++------------- | ||
14 | 3 files changed, 226 insertions(+), 78 deletions(-) | ||
15 | 12 | ||
16 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | 13 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
17 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/helper-sve.h | 15 | --- a/target/arm/translate.c |
19 | +++ b/target/arm/helper-sve.h | 16 | +++ b/target/arm/translate.c |
20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_st1hd_be_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | 17 | @@ -XXX,XX +XXX,XX @@ static inline long vfp_reg_offset(bool dp, unsigned reg) |
21 | DEF_HELPER_FLAGS_4(sve_st1sd_le_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
22 | DEF_HELPER_FLAGS_4(sve_st1sd_be_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
23 | |||
24 | +DEF_HELPER_FLAGS_4(sve_st1bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
25 | +DEF_HELPER_FLAGS_4(sve_st2bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
26 | +DEF_HELPER_FLAGS_4(sve_st3bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
27 | +DEF_HELPER_FLAGS_4(sve_st4bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
28 | + | ||
29 | +DEF_HELPER_FLAGS_4(sve_st1hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
30 | +DEF_HELPER_FLAGS_4(sve_st2hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
31 | +DEF_HELPER_FLAGS_4(sve_st3hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
32 | +DEF_HELPER_FLAGS_4(sve_st4hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
33 | + | ||
34 | +DEF_HELPER_FLAGS_4(sve_st1hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
35 | +DEF_HELPER_FLAGS_4(sve_st2hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
36 | +DEF_HELPER_FLAGS_4(sve_st3hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
37 | +DEF_HELPER_FLAGS_4(sve_st4hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
38 | + | ||
39 | +DEF_HELPER_FLAGS_4(sve_st1ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
40 | +DEF_HELPER_FLAGS_4(sve_st2ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
41 | +DEF_HELPER_FLAGS_4(sve_st3ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
42 | +DEF_HELPER_FLAGS_4(sve_st4ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
43 | + | ||
44 | +DEF_HELPER_FLAGS_4(sve_st1ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
45 | +DEF_HELPER_FLAGS_4(sve_st2ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
46 | +DEF_HELPER_FLAGS_4(sve_st3ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
47 | +DEF_HELPER_FLAGS_4(sve_st4ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
48 | + | ||
49 | +DEF_HELPER_FLAGS_4(sve_st1dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
50 | +DEF_HELPER_FLAGS_4(sve_st2dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
51 | +DEF_HELPER_FLAGS_4(sve_st3dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
52 | +DEF_HELPER_FLAGS_4(sve_st4dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
53 | + | ||
54 | +DEF_HELPER_FLAGS_4(sve_st1dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
55 | +DEF_HELPER_FLAGS_4(sve_st2dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
56 | +DEF_HELPER_FLAGS_4(sve_st3dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
57 | +DEF_HELPER_FLAGS_4(sve_st4dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
58 | + | ||
59 | +DEF_HELPER_FLAGS_4(sve_st1bh_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
60 | +DEF_HELPER_FLAGS_4(sve_st1bs_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
61 | +DEF_HELPER_FLAGS_4(sve_st1bd_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
62 | + | ||
63 | +DEF_HELPER_FLAGS_4(sve_st1hs_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
64 | +DEF_HELPER_FLAGS_4(sve_st1hd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
65 | +DEF_HELPER_FLAGS_4(sve_st1hs_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
66 | +DEF_HELPER_FLAGS_4(sve_st1hd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
67 | + | ||
68 | +DEF_HELPER_FLAGS_4(sve_st1sd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
69 | +DEF_HELPER_FLAGS_4(sve_st1sd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
70 | + | ||
71 | DEF_HELPER_FLAGS_6(sve_ldbsu_zsu, TCG_CALL_NO_WG, | ||
72 | void, env, ptr, ptr, ptr, tl, i32) | ||
73 | DEF_HELPER_FLAGS_6(sve_ldhsu_le_zsu, TCG_CALL_NO_WG, | ||
74 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | ||
75 | index XXXXXXX..XXXXXXX 100644 | ||
76 | --- a/target/arm/sve_helper.c | ||
77 | +++ b/target/arm/sve_helper.c | ||
78 | @@ -XXX,XX +XXX,XX @@ DO_LDFF1_LDNF1_2(dd, MO_64, MO_64) | ||
79 | */ | ||
80 | |||
81 | static inline QEMU_ALWAYS_INLINE | ||
82 | -void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, uint32_t desc, | ||
83 | - const uintptr_t retaddr, const int esz, | ||
84 | - const int msz, const int N, | ||
85 | +void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, | ||
86 | + uint32_t desc, const uintptr_t retaddr, | ||
87 | + const int esz, const int msz, const int N, uint32_t mtedesc, | ||
88 | sve_ldst1_host_fn *host_fn, | ||
89 | - sve_ldst1_tlb_fn *tlb_fn) | ||
90 | + sve_ldst1_tlb_fn *tlb_fn, | ||
91 | + sve_cont_ldst_mte_check_fn *mte_check_fn) | ||
92 | { | ||
93 | const unsigned rd = simd_data(desc); | ||
94 | const intptr_t reg_max = simd_oprsz(desc); | ||
95 | @@ -XXX,XX +XXX,XX @@ void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, uint32_t desc, | ||
96 | sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, N << msz, | ||
97 | BP_MEM_WRITE, retaddr); | ||
98 | |||
99 | - /* TODO: MTE check. */ | ||
100 | + /* | ||
101 | + * Handle mte checks for all active elements. | ||
102 | + * Since TBI must be set for MTE, !mtedesc => !mte_active. | ||
103 | + */ | ||
104 | + if (mte_check_fn && mtedesc) { | ||
105 | + mte_check_fn(&info, env, vg, addr, 1 << esz, N << msz, | ||
106 | + mtedesc, retaddr); | ||
107 | + } | ||
108 | |||
109 | flags = info.page[0].flags | info.page[1].flags; | ||
110 | if (unlikely(flags != 0)) { | ||
111 | @@ -XXX,XX +XXX,XX @@ void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, uint32_t desc, | ||
112 | } | 18 | } |
113 | } | 19 | } |
114 | 20 | ||
115 | -#define DO_STN_1(N, NAME, ESZ) \ | 21 | -/* Return the offset of a 32-bit piece of a NEON register. |
116 | -void HELPER(sve_st##N##NAME##_r)(CPUARMState *env, void *vg, \ | 22 | - zero is the least significant end of the register. */ |
117 | - target_ulong addr, uint32_t desc) \ | 23 | -static inline long |
118 | -{ \ | 24 | -neon_reg_offset (int reg, int n) |
119 | - sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, N, \ | 25 | -{ |
120 | - sve_st1##NAME##_host, sve_st1##NAME##_tlb); \ | 26 | - int sreg; |
121 | +static inline QEMU_ALWAYS_INLINE | 27 | - sreg = reg * 2 + n; |
122 | +void sve_stN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr, | 28 | - return vfp_reg_offset(0, sreg); |
123 | + uint32_t desc, const uintptr_t ra, | 29 | -} |
124 | + const int esz, const int msz, const int N, | 30 | - |
125 | + sve_ldst1_host_fn *host_fn, | 31 | static TCGv_i32 neon_load_reg(int reg, int pass) |
126 | + sve_ldst1_tlb_fn *tlb_fn) | 32 | { |
127 | +{ | 33 | TCGv_i32 tmp = tcg_temp_new_i32(); |
128 | + uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); | 34 | - tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass)); |
129 | + int bit55 = extract64(addr, 55, 1); | 35 | + tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32)); |
130 | + | 36 | return tmp; |
131 | + /* Remove mtedesc from the normal sve descriptor. */ | ||
132 | + desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); | ||
133 | + | ||
134 | + /* Perform gross MTE suppression early. */ | ||
135 | + if (!tbi_check(desc, bit55) || | ||
136 | + tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { | ||
137 | + mtedesc = 0; | ||
138 | + } | ||
139 | + | ||
140 | + sve_stN_r(env, vg, addr, desc, ra, esz, msz, N, mtedesc, host_fn, tlb_fn, | ||
141 | + N == 1 ? sve_cont_ldst_mte_check1 : sve_cont_ldst_mte_checkN); | ||
142 | } | 37 | } |
143 | 38 | ||
144 | -#define DO_STN_2(N, NAME, ESZ, MSZ) \ | 39 | static void neon_store_reg(int reg, int pass, TCGv_i32 var) |
145 | -void HELPER(sve_st##N##NAME##_le_r)(CPUARMState *env, void *vg, \ | 40 | { |
146 | - target_ulong addr, uint32_t desc) \ | 41 | - tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass)); |
147 | -{ \ | 42 | + tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32)); |
148 | - sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, \ | 43 | tcg_temp_free_i32(var); |
149 | - sve_st1##NAME##_le_host, sve_st1##NAME##_le_tlb); \ | ||
150 | -} \ | ||
151 | -void HELPER(sve_st##N##NAME##_be_r)(CPUARMState *env, void *vg, \ | ||
152 | - target_ulong addr, uint32_t desc) \ | ||
153 | -{ \ | ||
154 | - sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, \ | ||
155 | - sve_st1##NAME##_be_host, sve_st1##NAME##_be_tlb); \ | ||
156 | +#define DO_STN_1(N, NAME, ESZ) \ | ||
157 | +void HELPER(sve_st##N##NAME##_r)(CPUARMState *env, void *vg, \ | ||
158 | + target_ulong addr, uint32_t desc) \ | ||
159 | +{ \ | ||
160 | + sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, N, 0, \ | ||
161 | + sve_st1##NAME##_host, sve_st1##NAME##_tlb, NULL); \ | ||
162 | +} \ | ||
163 | +void HELPER(sve_st##N##NAME##_r_mte)(CPUARMState *env, void *vg, \ | ||
164 | + target_ulong addr, uint32_t desc) \ | ||
165 | +{ \ | ||
166 | + sve_stN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MO_8, N, \ | ||
167 | + sve_st1##NAME##_host, sve_st1##NAME##_tlb); \ | ||
168 | +} | ||
169 | + | ||
170 | +#define DO_STN_2(N, NAME, ESZ, MSZ) \ | ||
171 | +void HELPER(sve_st##N##NAME##_le_r)(CPUARMState *env, void *vg, \ | ||
172 | + target_ulong addr, uint32_t desc) \ | ||
173 | +{ \ | ||
174 | + sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, 0, \ | ||
175 | + sve_st1##NAME##_le_host, sve_st1##NAME##_le_tlb, NULL); \ | ||
176 | +} \ | ||
177 | +void HELPER(sve_st##N##NAME##_be_r)(CPUARMState *env, void *vg, \ | ||
178 | + target_ulong addr, uint32_t desc) \ | ||
179 | +{ \ | ||
180 | + sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, 0, \ | ||
181 | + sve_st1##NAME##_be_host, sve_st1##NAME##_be_tlb, NULL); \ | ||
182 | +} \ | ||
183 | +void HELPER(sve_st##N##NAME##_le_r_mte)(CPUARMState *env, void *vg, \ | ||
184 | + target_ulong addr, uint32_t desc) \ | ||
185 | +{ \ | ||
186 | + sve_stN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, \ | ||
187 | + sve_st1##NAME##_le_host, sve_st1##NAME##_le_tlb); \ | ||
188 | +} \ | ||
189 | +void HELPER(sve_st##N##NAME##_be_r_mte)(CPUARMState *env, void *vg, \ | ||
190 | + target_ulong addr, uint32_t desc) \ | ||
191 | +{ \ | ||
192 | + sve_stN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, \ | ||
193 | + sve_st1##NAME##_be_host, sve_st1##NAME##_be_tlb); \ | ||
194 | } | 44 | } |
195 | 45 | ||
196 | DO_STN_1(1, bb, MO_8) | ||
197 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
198 | index XXXXXXX..XXXXXXX 100644 | ||
199 | --- a/target/arm/translate-sve.c | ||
200 | +++ b/target/arm/translate-sve.c | ||
201 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a) | ||
202 | static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | ||
203 | int msz, int esz, int nreg) | ||
204 | { | ||
205 | - static gen_helper_gvec_mem * const fn_single[2][4][4] = { | ||
206 | - { { gen_helper_sve_st1bb_r, | ||
207 | - gen_helper_sve_st1bh_r, | ||
208 | - gen_helper_sve_st1bs_r, | ||
209 | - gen_helper_sve_st1bd_r }, | ||
210 | - { NULL, | ||
211 | - gen_helper_sve_st1hh_le_r, | ||
212 | - gen_helper_sve_st1hs_le_r, | ||
213 | - gen_helper_sve_st1hd_le_r }, | ||
214 | - { NULL, NULL, | ||
215 | - gen_helper_sve_st1ss_le_r, | ||
216 | - gen_helper_sve_st1sd_le_r }, | ||
217 | - { NULL, NULL, NULL, | ||
218 | - gen_helper_sve_st1dd_le_r } }, | ||
219 | - { { gen_helper_sve_st1bb_r, | ||
220 | - gen_helper_sve_st1bh_r, | ||
221 | - gen_helper_sve_st1bs_r, | ||
222 | - gen_helper_sve_st1bd_r }, | ||
223 | - { NULL, | ||
224 | - gen_helper_sve_st1hh_be_r, | ||
225 | - gen_helper_sve_st1hs_be_r, | ||
226 | - gen_helper_sve_st1hd_be_r }, | ||
227 | - { NULL, NULL, | ||
228 | - gen_helper_sve_st1ss_be_r, | ||
229 | - gen_helper_sve_st1sd_be_r }, | ||
230 | - { NULL, NULL, NULL, | ||
231 | - gen_helper_sve_st1dd_be_r } }, | ||
232 | + static gen_helper_gvec_mem * const fn_single[2][2][4][4] = { | ||
233 | + { { { gen_helper_sve_st1bb_r, | ||
234 | + gen_helper_sve_st1bh_r, | ||
235 | + gen_helper_sve_st1bs_r, | ||
236 | + gen_helper_sve_st1bd_r }, | ||
237 | + { NULL, | ||
238 | + gen_helper_sve_st1hh_le_r, | ||
239 | + gen_helper_sve_st1hs_le_r, | ||
240 | + gen_helper_sve_st1hd_le_r }, | ||
241 | + { NULL, NULL, | ||
242 | + gen_helper_sve_st1ss_le_r, | ||
243 | + gen_helper_sve_st1sd_le_r }, | ||
244 | + { NULL, NULL, NULL, | ||
245 | + gen_helper_sve_st1dd_le_r } }, | ||
246 | + { { gen_helper_sve_st1bb_r, | ||
247 | + gen_helper_sve_st1bh_r, | ||
248 | + gen_helper_sve_st1bs_r, | ||
249 | + gen_helper_sve_st1bd_r }, | ||
250 | + { NULL, | ||
251 | + gen_helper_sve_st1hh_be_r, | ||
252 | + gen_helper_sve_st1hs_be_r, | ||
253 | + gen_helper_sve_st1hd_be_r }, | ||
254 | + { NULL, NULL, | ||
255 | + gen_helper_sve_st1ss_be_r, | ||
256 | + gen_helper_sve_st1sd_be_r }, | ||
257 | + { NULL, NULL, NULL, | ||
258 | + gen_helper_sve_st1dd_be_r } } }, | ||
259 | + | ||
260 | + { { { gen_helper_sve_st1bb_r_mte, | ||
261 | + gen_helper_sve_st1bh_r_mte, | ||
262 | + gen_helper_sve_st1bs_r_mte, | ||
263 | + gen_helper_sve_st1bd_r_mte }, | ||
264 | + { NULL, | ||
265 | + gen_helper_sve_st1hh_le_r_mte, | ||
266 | + gen_helper_sve_st1hs_le_r_mte, | ||
267 | + gen_helper_sve_st1hd_le_r_mte }, | ||
268 | + { NULL, NULL, | ||
269 | + gen_helper_sve_st1ss_le_r_mte, | ||
270 | + gen_helper_sve_st1sd_le_r_mte }, | ||
271 | + { NULL, NULL, NULL, | ||
272 | + gen_helper_sve_st1dd_le_r_mte } }, | ||
273 | + { { gen_helper_sve_st1bb_r_mte, | ||
274 | + gen_helper_sve_st1bh_r_mte, | ||
275 | + gen_helper_sve_st1bs_r_mte, | ||
276 | + gen_helper_sve_st1bd_r_mte }, | ||
277 | + { NULL, | ||
278 | + gen_helper_sve_st1hh_be_r_mte, | ||
279 | + gen_helper_sve_st1hs_be_r_mte, | ||
280 | + gen_helper_sve_st1hd_be_r_mte }, | ||
281 | + { NULL, NULL, | ||
282 | + gen_helper_sve_st1ss_be_r_mte, | ||
283 | + gen_helper_sve_st1sd_be_r_mte }, | ||
284 | + { NULL, NULL, NULL, | ||
285 | + gen_helper_sve_st1dd_be_r_mte } } }, | ||
286 | }; | ||
287 | - static gen_helper_gvec_mem * const fn_multiple[2][3][4] = { | ||
288 | - { { gen_helper_sve_st2bb_r, | ||
289 | - gen_helper_sve_st2hh_le_r, | ||
290 | - gen_helper_sve_st2ss_le_r, | ||
291 | - gen_helper_sve_st2dd_le_r }, | ||
292 | - { gen_helper_sve_st3bb_r, | ||
293 | - gen_helper_sve_st3hh_le_r, | ||
294 | - gen_helper_sve_st3ss_le_r, | ||
295 | - gen_helper_sve_st3dd_le_r }, | ||
296 | - { gen_helper_sve_st4bb_r, | ||
297 | - gen_helper_sve_st4hh_le_r, | ||
298 | - gen_helper_sve_st4ss_le_r, | ||
299 | - gen_helper_sve_st4dd_le_r } }, | ||
300 | - { { gen_helper_sve_st2bb_r, | ||
301 | - gen_helper_sve_st2hh_be_r, | ||
302 | - gen_helper_sve_st2ss_be_r, | ||
303 | - gen_helper_sve_st2dd_be_r }, | ||
304 | - { gen_helper_sve_st3bb_r, | ||
305 | - gen_helper_sve_st3hh_be_r, | ||
306 | - gen_helper_sve_st3ss_be_r, | ||
307 | - gen_helper_sve_st3dd_be_r }, | ||
308 | - { gen_helper_sve_st4bb_r, | ||
309 | - gen_helper_sve_st4hh_be_r, | ||
310 | - gen_helper_sve_st4ss_be_r, | ||
311 | - gen_helper_sve_st4dd_be_r } }, | ||
312 | + static gen_helper_gvec_mem * const fn_multiple[2][2][3][4] = { | ||
313 | + { { { gen_helper_sve_st2bb_r, | ||
314 | + gen_helper_sve_st2hh_le_r, | ||
315 | + gen_helper_sve_st2ss_le_r, | ||
316 | + gen_helper_sve_st2dd_le_r }, | ||
317 | + { gen_helper_sve_st3bb_r, | ||
318 | + gen_helper_sve_st3hh_le_r, | ||
319 | + gen_helper_sve_st3ss_le_r, | ||
320 | + gen_helper_sve_st3dd_le_r }, | ||
321 | + { gen_helper_sve_st4bb_r, | ||
322 | + gen_helper_sve_st4hh_le_r, | ||
323 | + gen_helper_sve_st4ss_le_r, | ||
324 | + gen_helper_sve_st4dd_le_r } }, | ||
325 | + { { gen_helper_sve_st2bb_r, | ||
326 | + gen_helper_sve_st2hh_be_r, | ||
327 | + gen_helper_sve_st2ss_be_r, | ||
328 | + gen_helper_sve_st2dd_be_r }, | ||
329 | + { gen_helper_sve_st3bb_r, | ||
330 | + gen_helper_sve_st3hh_be_r, | ||
331 | + gen_helper_sve_st3ss_be_r, | ||
332 | + gen_helper_sve_st3dd_be_r }, | ||
333 | + { gen_helper_sve_st4bb_r, | ||
334 | + gen_helper_sve_st4hh_be_r, | ||
335 | + gen_helper_sve_st4ss_be_r, | ||
336 | + gen_helper_sve_st4dd_be_r } } }, | ||
337 | + { { { gen_helper_sve_st2bb_r_mte, | ||
338 | + gen_helper_sve_st2hh_le_r_mte, | ||
339 | + gen_helper_sve_st2ss_le_r_mte, | ||
340 | + gen_helper_sve_st2dd_le_r_mte }, | ||
341 | + { gen_helper_sve_st3bb_r_mte, | ||
342 | + gen_helper_sve_st3hh_le_r_mte, | ||
343 | + gen_helper_sve_st3ss_le_r_mte, | ||
344 | + gen_helper_sve_st3dd_le_r_mte }, | ||
345 | + { gen_helper_sve_st4bb_r_mte, | ||
346 | + gen_helper_sve_st4hh_le_r_mte, | ||
347 | + gen_helper_sve_st4ss_le_r_mte, | ||
348 | + gen_helper_sve_st4dd_le_r_mte } }, | ||
349 | + { { gen_helper_sve_st2bb_r_mte, | ||
350 | + gen_helper_sve_st2hh_be_r_mte, | ||
351 | + gen_helper_sve_st2ss_be_r_mte, | ||
352 | + gen_helper_sve_st2dd_be_r_mte }, | ||
353 | + { gen_helper_sve_st3bb_r_mte, | ||
354 | + gen_helper_sve_st3hh_be_r_mte, | ||
355 | + gen_helper_sve_st3ss_be_r_mte, | ||
356 | + gen_helper_sve_st3dd_be_r_mte }, | ||
357 | + { gen_helper_sve_st4bb_r_mte, | ||
358 | + gen_helper_sve_st4hh_be_r_mte, | ||
359 | + gen_helper_sve_st4ss_be_r_mte, | ||
360 | + gen_helper_sve_st4dd_be_r_mte } } }, | ||
361 | }; | ||
362 | gen_helper_gvec_mem *fn; | ||
363 | int be = s->be_data == MO_BE; | ||
364 | |||
365 | if (nreg == 0) { | ||
366 | /* ST1 */ | ||
367 | - fn = fn_single[be][msz][esz]; | ||
368 | + fn = fn_single[s->mte_active[0]][be][msz][esz]; | ||
369 | + nreg = 1; | ||
370 | } else { | ||
371 | /* ST2, ST3, ST4 -- msz == esz, enforced by encoding */ | ||
372 | assert(msz == esz); | ||
373 | - fn = fn_multiple[be][nreg - 1][msz]; | ||
374 | + fn = fn_multiple[s->mte_active[0]][be][nreg - 1][msz]; | ||
375 | } | ||
376 | assert(fn != NULL); | ||
377 | - do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), 0, true, fn); | ||
378 | + do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg, true, fn); | ||
379 | } | ||
380 | |||
381 | static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a) | ||
382 | -- | 46 | -- |
383 | 2.20.1 | 47 | 2.20.1 |
384 | 48 | ||
385 | 49 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Because the elements are sequential, we can eliminate many tests all | 3 | This seems a bit more readable than using offsetof CPU_DoubleU. |
4 | at once when the tag hits TCMA, or if the page(s) are not Tagged. | ||
5 | 4 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20201030022618.785675-5-richard.henderson@linaro.org | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20200626033144.790098-34-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 9 | --- |
11 | target/arm/cpu.h | 1 + | 10 | target/arm/translate.c | 13 ++++--------- |
12 | target/arm/helper-sve.h | 58 ++++++++++ | 11 | 1 file changed, 4 insertions(+), 9 deletions(-) |
13 | target/arm/internals.h | 6 + | ||
14 | target/arm/sve_helper.c | 218 ++++++++++++++++++++++++++++++------- | ||
15 | target/arm/translate-sve.c | 186 ++++++++++++++++++++++--------- | ||
16 | 5 files changed, 378 insertions(+), 91 deletions(-) | ||
17 | 12 | ||
18 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 13 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
19 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/cpu.h | 15 | --- a/target/arm/translate.c |
21 | +++ b/target/arm/cpu.h | 16 | +++ b/target/arm/translate.c |
22 | @@ -XXX,XX +XXX,XX @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) | 17 | @@ -XXX,XX +XXX,XX @@ static long neon_element_offset(int reg, int element, MemOp size) |
23 | * generic target bits directly. | 18 | return neon_full_reg_offset(reg) + ofs; |
24 | */ | ||
25 | #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) | ||
26 | +#define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) | ||
27 | |||
28 | /* | ||
29 | * Naming convention for isar_feature functions: | ||
30 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/helper-sve.h | ||
33 | +++ b/target/arm/helper-sve.h | ||
34 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_ld1sds_le_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
35 | DEF_HELPER_FLAGS_4(sve_ld1sdu_be_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
36 | DEF_HELPER_FLAGS_4(sve_ld1sds_be_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
37 | |||
38 | +DEF_HELPER_FLAGS_4(sve_ld1bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
39 | +DEF_HELPER_FLAGS_4(sve_ld2bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
40 | +DEF_HELPER_FLAGS_4(sve_ld3bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
41 | +DEF_HELPER_FLAGS_4(sve_ld4bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
42 | + | ||
43 | +DEF_HELPER_FLAGS_4(sve_ld1hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
44 | +DEF_HELPER_FLAGS_4(sve_ld2hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
45 | +DEF_HELPER_FLAGS_4(sve_ld3hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
46 | +DEF_HELPER_FLAGS_4(sve_ld4hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
47 | + | ||
48 | +DEF_HELPER_FLAGS_4(sve_ld1hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
49 | +DEF_HELPER_FLAGS_4(sve_ld2hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
50 | +DEF_HELPER_FLAGS_4(sve_ld3hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
51 | +DEF_HELPER_FLAGS_4(sve_ld4hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
52 | + | ||
53 | +DEF_HELPER_FLAGS_4(sve_ld1ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
54 | +DEF_HELPER_FLAGS_4(sve_ld2ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
55 | +DEF_HELPER_FLAGS_4(sve_ld3ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
56 | +DEF_HELPER_FLAGS_4(sve_ld4ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
57 | + | ||
58 | +DEF_HELPER_FLAGS_4(sve_ld1ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
59 | +DEF_HELPER_FLAGS_4(sve_ld2ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
60 | +DEF_HELPER_FLAGS_4(sve_ld3ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
61 | +DEF_HELPER_FLAGS_4(sve_ld4ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
62 | + | ||
63 | +DEF_HELPER_FLAGS_4(sve_ld1dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
64 | +DEF_HELPER_FLAGS_4(sve_ld2dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
65 | +DEF_HELPER_FLAGS_4(sve_ld3dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
66 | +DEF_HELPER_FLAGS_4(sve_ld4dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
67 | + | ||
68 | +DEF_HELPER_FLAGS_4(sve_ld1dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
69 | +DEF_HELPER_FLAGS_4(sve_ld2dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
70 | +DEF_HELPER_FLAGS_4(sve_ld3dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
71 | +DEF_HELPER_FLAGS_4(sve_ld4dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
72 | + | ||
73 | +DEF_HELPER_FLAGS_4(sve_ld1bhu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
74 | +DEF_HELPER_FLAGS_4(sve_ld1bsu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
75 | +DEF_HELPER_FLAGS_4(sve_ld1bdu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
76 | +DEF_HELPER_FLAGS_4(sve_ld1bhs_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
77 | +DEF_HELPER_FLAGS_4(sve_ld1bss_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
78 | +DEF_HELPER_FLAGS_4(sve_ld1bds_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
79 | + | ||
80 | +DEF_HELPER_FLAGS_4(sve_ld1hsu_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
81 | +DEF_HELPER_FLAGS_4(sve_ld1hdu_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
82 | +DEF_HELPER_FLAGS_4(sve_ld1hss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
83 | +DEF_HELPER_FLAGS_4(sve_ld1hds_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
84 | + | ||
85 | +DEF_HELPER_FLAGS_4(sve_ld1hsu_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
86 | +DEF_HELPER_FLAGS_4(sve_ld1hdu_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
87 | +DEF_HELPER_FLAGS_4(sve_ld1hss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
88 | +DEF_HELPER_FLAGS_4(sve_ld1hds_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
89 | + | ||
90 | +DEF_HELPER_FLAGS_4(sve_ld1sdu_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
91 | +DEF_HELPER_FLAGS_4(sve_ld1sds_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
92 | + | ||
93 | +DEF_HELPER_FLAGS_4(sve_ld1sdu_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
94 | +DEF_HELPER_FLAGS_4(sve_ld1sds_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
95 | + | ||
96 | DEF_HELPER_FLAGS_4(sve_ldff1bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
97 | DEF_HELPER_FLAGS_4(sve_ldff1bhu_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
98 | DEF_HELPER_FLAGS_4(sve_ldff1bsu_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
99 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
100 | index XXXXXXX..XXXXXXX 100644 | ||
101 | --- a/target/arm/internals.h | ||
102 | +++ b/target/arm/internals.h | ||
103 | @@ -XXX,XX +XXX,XX @@ void arm_log_exception(int idx); | ||
104 | #define LOG2_TAG_GRANULE 4 | ||
105 | #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) | ||
106 | |||
107 | +/* | ||
108 | + * The SVE simd_data field, for memory ops, contains either | ||
109 | + * rd (5 bits) or a shift count (2 bits). | ||
110 | + */ | ||
111 | +#define SVE_MTEDESC_SHIFT 5 | ||
112 | + | ||
113 | /* Bits within a descriptor passed to the helper_mte_check* functions. */ | ||
114 | FIELD(MTEDESC, MIDX, 0, 4) | ||
115 | FIELD(MTEDESC, TBI, 4, 2) | ||
116 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | ||
117 | index XXXXXXX..XXXXXXX 100644 | ||
118 | --- a/target/arm/sve_helper.c | ||
119 | +++ b/target/arm/sve_helper.c | ||
120 | @@ -XXX,XX +XXX,XX @@ static void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env, | ||
121 | #endif | ||
122 | } | 19 | } |
123 | 20 | ||
124 | +typedef uint64_t mte_check_fn(CPUARMState *, uint32_t, uint64_t, uintptr_t); | 21 | -static inline long vfp_reg_offset(bool dp, unsigned reg) |
125 | + | 22 | +/* Return the offset of a VFP Dreg (dp = true) or VFP Sreg (dp = false). */ |
126 | +static inline QEMU_ALWAYS_INLINE | 23 | +static long vfp_reg_offset(bool dp, unsigned reg) |
127 | +void sve_cont_ldst_mte_check_int(SVEContLdSt *info, CPUARMState *env, | ||
128 | + uint64_t *vg, target_ulong addr, int esize, | ||
129 | + int msize, uint32_t mtedesc, uintptr_t ra, | ||
130 | + mte_check_fn *check) | ||
131 | +{ | ||
132 | + intptr_t mem_off, reg_off, reg_last; | ||
133 | + | ||
134 | + /* Process the page only if MemAttr == Tagged. */ | ||
135 | + if (arm_tlb_mte_tagged(&info->page[0].attrs)) { | ||
136 | + mem_off = info->mem_off_first[0]; | ||
137 | + reg_off = info->reg_off_first[0]; | ||
138 | + reg_last = info->reg_off_split; | ||
139 | + if (reg_last < 0) { | ||
140 | + reg_last = info->reg_off_last[0]; | ||
141 | + } | ||
142 | + | ||
143 | + do { | ||
144 | + uint64_t pg = vg[reg_off >> 6]; | ||
145 | + do { | ||
146 | + if ((pg >> (reg_off & 63)) & 1) { | ||
147 | + check(env, mtedesc, addr, ra); | ||
148 | + } | ||
149 | + reg_off += esize; | ||
150 | + mem_off += msize; | ||
151 | + } while (reg_off <= reg_last && (reg_off & 63)); | ||
152 | + } while (reg_off <= reg_last); | ||
153 | + } | ||
154 | + | ||
155 | + mem_off = info->mem_off_first[1]; | ||
156 | + if (mem_off >= 0 && arm_tlb_mte_tagged(&info->page[1].attrs)) { | ||
157 | + reg_off = info->reg_off_first[1]; | ||
158 | + reg_last = info->reg_off_last[1]; | ||
159 | + | ||
160 | + do { | ||
161 | + uint64_t pg = vg[reg_off >> 6]; | ||
162 | + do { | ||
163 | + if ((pg >> (reg_off & 63)) & 1) { | ||
164 | + check(env, mtedesc, addr, ra); | ||
165 | + } | ||
166 | + reg_off += esize; | ||
167 | + mem_off += msize; | ||
168 | + } while (reg_off & 63); | ||
169 | + } while (reg_off <= reg_last); | ||
170 | + } | ||
171 | +} | ||
172 | + | ||
173 | +typedef void sve_cont_ldst_mte_check_fn(SVEContLdSt *info, CPUARMState *env, | ||
174 | + uint64_t *vg, target_ulong addr, | ||
175 | + int esize, int msize, uint32_t mtedesc, | ||
176 | + uintptr_t ra); | ||
177 | + | ||
178 | +static void sve_cont_ldst_mte_check1(SVEContLdSt *info, CPUARMState *env, | ||
179 | + uint64_t *vg, target_ulong addr, | ||
180 | + int esize, int msize, uint32_t mtedesc, | ||
181 | + uintptr_t ra) | ||
182 | +{ | ||
183 | + sve_cont_ldst_mte_check_int(info, env, vg, addr, esize, msize, | ||
184 | + mtedesc, ra, mte_check1); | ||
185 | +} | ||
186 | + | ||
187 | +static void sve_cont_ldst_mte_checkN(SVEContLdSt *info, CPUARMState *env, | ||
188 | + uint64_t *vg, target_ulong addr, | ||
189 | + int esize, int msize, uint32_t mtedesc, | ||
190 | + uintptr_t ra) | ||
191 | +{ | ||
192 | + sve_cont_ldst_mte_check_int(info, env, vg, addr, esize, msize, | ||
193 | + mtedesc, ra, mte_checkN); | ||
194 | +} | ||
195 | + | ||
196 | + | ||
197 | /* | ||
198 | * Common helper for all contiguous 1,2,3,4-register predicated stores. | ||
199 | */ | ||
200 | static inline QEMU_ALWAYS_INLINE | ||
201 | void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr, | ||
202 | uint32_t desc, const uintptr_t retaddr, | ||
203 | - const int esz, const int msz, const int N, | ||
204 | + const int esz, const int msz, const int N, uint32_t mtedesc, | ||
205 | sve_ldst1_host_fn *host_fn, | ||
206 | - sve_ldst1_tlb_fn *tlb_fn) | ||
207 | + sve_ldst1_tlb_fn *tlb_fn, | ||
208 | + sve_cont_ldst_mte_check_fn *mte_check_fn) | ||
209 | { | 24 | { |
210 | const unsigned rd = simd_data(desc); | 25 | if (dp) { |
211 | const intptr_t reg_max = simd_oprsz(desc); | 26 | - return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); |
212 | @@ -XXX,XX +XXX,XX @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr, | 27 | + return neon_element_offset(reg, 0, MO_64); |
213 | sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, N << msz, | 28 | } else { |
214 | BP_MEM_READ, retaddr); | 29 | - long ofs = offsetof(CPUARMState, vfp.zregs[reg >> 2].d[(reg >> 1) & 1]); |
215 | 30 | - if (reg & 1) { | |
216 | - /* TODO: MTE check. */ | 31 | - ofs += offsetof(CPU_DoubleU, l.upper); |
217 | + /* | 32 | - } else { |
218 | + * Handle mte checks for all active elements. | 33 | - ofs += offsetof(CPU_DoubleU, l.lower); |
219 | + * Since TBI must be set for MTE, !mtedesc => !mte_active. | 34 | - } |
220 | + */ | 35 | - return ofs; |
221 | + if (mte_check_fn && mtedesc) { | 36 | + return neon_element_offset(reg >> 1, reg & 1, MO_32); |
222 | + mte_check_fn(&info, env, vg, addr, 1 << esz, N << msz, | ||
223 | + mtedesc, retaddr); | ||
224 | + } | ||
225 | |||
226 | flags = info.page[0].flags | info.page[1].flags; | ||
227 | if (unlikely(flags != 0)) { | ||
228 | @@ -XXX,XX +XXX,XX @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr, | ||
229 | } | 37 | } |
230 | } | 38 | } |
231 | 39 | ||
232 | -#define DO_LD1_1(NAME, ESZ) \ | ||
233 | -void HELPER(sve_##NAME##_r)(CPUARMState *env, void *vg, \ | ||
234 | - target_ulong addr, uint32_t desc) \ | ||
235 | -{ \ | ||
236 | - sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, 1, \ | ||
237 | - sve_##NAME##_host, sve_##NAME##_tlb); \ | ||
238 | +static inline QEMU_ALWAYS_INLINE | ||
239 | +void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr, | ||
240 | + uint32_t desc, const uintptr_t ra, | ||
241 | + const int esz, const int msz, const int N, | ||
242 | + sve_ldst1_host_fn *host_fn, | ||
243 | + sve_ldst1_tlb_fn *tlb_fn) | ||
244 | +{ | ||
245 | + uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); | ||
246 | + int bit55 = extract64(addr, 55, 1); | ||
247 | + | ||
248 | + /* Remove mtedesc from the normal sve descriptor. */ | ||
249 | + desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); | ||
250 | + | ||
251 | + /* Perform gross MTE suppression early. */ | ||
252 | + if (!tbi_check(desc, bit55) || | ||
253 | + tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { | ||
254 | + mtedesc = 0; | ||
255 | + } | ||
256 | + | ||
257 | + sve_ldN_r(env, vg, addr, desc, ra, esz, msz, N, mtedesc, host_fn, tlb_fn, | ||
258 | + N == 1 ? sve_cont_ldst_mte_check1 : sve_cont_ldst_mte_checkN); | ||
259 | } | ||
260 | |||
261 | -#define DO_LD1_2(NAME, ESZ, MSZ) \ | ||
262 | -void HELPER(sve_##NAME##_le_r)(CPUARMState *env, void *vg, \ | ||
263 | - target_ulong addr, uint32_t desc) \ | ||
264 | -{ \ | ||
265 | - sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \ | ||
266 | - sve_##NAME##_le_host, sve_##NAME##_le_tlb); \ | ||
267 | -} \ | ||
268 | -void HELPER(sve_##NAME##_be_r)(CPUARMState *env, void *vg, \ | ||
269 | - target_ulong addr, uint32_t desc) \ | ||
270 | -{ \ | ||
271 | - sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \ | ||
272 | - sve_##NAME##_be_host, sve_##NAME##_be_tlb); \ | ||
273 | +#define DO_LD1_1(NAME, ESZ) \ | ||
274 | +void HELPER(sve_##NAME##_r)(CPUARMState *env, void *vg, \ | ||
275 | + target_ulong addr, uint32_t desc) \ | ||
276 | +{ \ | ||
277 | + sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, 1, 0, \ | ||
278 | + sve_##NAME##_host, sve_##NAME##_tlb, NULL); \ | ||
279 | +} \ | ||
280 | +void HELPER(sve_##NAME##_r_mte)(CPUARMState *env, void *vg, \ | ||
281 | + target_ulong addr, uint32_t desc) \ | ||
282 | +{ \ | ||
283 | + sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MO_8, 1, \ | ||
284 | + sve_##NAME##_host, sve_##NAME##_tlb); \ | ||
285 | +} | ||
286 | + | ||
287 | +#define DO_LD1_2(NAME, ESZ, MSZ) \ | ||
288 | +void HELPER(sve_##NAME##_le_r)(CPUARMState *env, void *vg, \ | ||
289 | + target_ulong addr, uint32_t desc) \ | ||
290 | +{ \ | ||
291 | + sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, 0, \ | ||
292 | + sve_##NAME##_le_host, sve_##NAME##_le_tlb, NULL); \ | ||
293 | +} \ | ||
294 | +void HELPER(sve_##NAME##_be_r)(CPUARMState *env, void *vg, \ | ||
295 | + target_ulong addr, uint32_t desc) \ | ||
296 | +{ \ | ||
297 | + sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, 0, \ | ||
298 | + sve_##NAME##_be_host, sve_##NAME##_be_tlb, NULL); \ | ||
299 | +} \ | ||
300 | +void HELPER(sve_##NAME##_le_r_mte)(CPUARMState *env, void *vg, \ | ||
301 | + target_ulong addr, uint32_t desc) \ | ||
302 | +{ \ | ||
303 | + sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \ | ||
304 | + sve_##NAME##_le_host, sve_##NAME##_le_tlb); \ | ||
305 | +} \ | ||
306 | +void HELPER(sve_##NAME##_be_r_mte)(CPUARMState *env, void *vg, \ | ||
307 | + target_ulong addr, uint32_t desc) \ | ||
308 | +{ \ | ||
309 | + sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \ | ||
310 | + sve_##NAME##_be_host, sve_##NAME##_be_tlb); \ | ||
311 | } | ||
312 | |||
313 | DO_LD1_1(ld1bb, MO_8) | ||
314 | @@ -XXX,XX +XXX,XX @@ DO_LD1_2(ld1dd, MO_64, MO_64) | ||
315 | #undef DO_LD1_1 | ||
316 | #undef DO_LD1_2 | ||
317 | |||
318 | -#define DO_LDN_1(N) \ | ||
319 | -void HELPER(sve_ld##N##bb_r)(CPUARMState *env, void *vg, \ | ||
320 | - target_ulong addr, uint32_t desc) \ | ||
321 | -{ \ | ||
322 | - sve_ldN_r(env, vg, addr, desc, GETPC(), MO_8, MO_8, N, \ | ||
323 | - sve_ld1bb_host, sve_ld1bb_tlb); \ | ||
324 | +#define DO_LDN_1(N) \ | ||
325 | +void HELPER(sve_ld##N##bb_r)(CPUARMState *env, void *vg, \ | ||
326 | + target_ulong addr, uint32_t desc) \ | ||
327 | +{ \ | ||
328 | + sve_ldN_r(env, vg, addr, desc, GETPC(), MO_8, MO_8, N, 0, \ | ||
329 | + sve_ld1bb_host, sve_ld1bb_tlb, NULL); \ | ||
330 | +} \ | ||
331 | +void HELPER(sve_ld##N##bb_r_mte)(CPUARMState *env, void *vg, \ | ||
332 | + target_ulong addr, uint32_t desc) \ | ||
333 | +{ \ | ||
334 | + sve_ldN_r_mte(env, vg, addr, desc, GETPC(), MO_8, MO_8, N, \ | ||
335 | + sve_ld1bb_host, sve_ld1bb_tlb); \ | ||
336 | } | ||
337 | |||
338 | -#define DO_LDN_2(N, SUFF, ESZ) \ | ||
339 | -void HELPER(sve_ld##N##SUFF##_le_r)(CPUARMState *env, void *vg, \ | ||
340 | - target_ulong addr, uint32_t desc) \ | ||
341 | -{ \ | ||
342 | - sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \ | ||
343 | - sve_ld1##SUFF##_le_host, sve_ld1##SUFF##_le_tlb); \ | ||
344 | -} \ | ||
345 | -void HELPER(sve_ld##N##SUFF##_be_r)(CPUARMState *env, void *vg, \ | ||
346 | - target_ulong addr, uint32_t desc) \ | ||
347 | -{ \ | ||
348 | - sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \ | ||
349 | - sve_ld1##SUFF##_be_host, sve_ld1##SUFF##_be_tlb); \ | ||
350 | +#define DO_LDN_2(N, SUFF, ESZ) \ | ||
351 | +void HELPER(sve_ld##N##SUFF##_le_r)(CPUARMState *env, void *vg, \ | ||
352 | + target_ulong addr, uint32_t desc) \ | ||
353 | +{ \ | ||
354 | + sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, 0, \ | ||
355 | + sve_ld1##SUFF##_le_host, sve_ld1##SUFF##_le_tlb, NULL); \ | ||
356 | +} \ | ||
357 | +void HELPER(sve_ld##N##SUFF##_be_r)(CPUARMState *env, void *vg, \ | ||
358 | + target_ulong addr, uint32_t desc) \ | ||
359 | +{ \ | ||
360 | + sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, 0, \ | ||
361 | + sve_ld1##SUFF##_be_host, sve_ld1##SUFF##_be_tlb, NULL); \ | ||
362 | +} \ | ||
363 | +void HELPER(sve_ld##N##SUFF##_le_r_mte)(CPUARMState *env, void *vg, \ | ||
364 | + target_ulong addr, uint32_t desc) \ | ||
365 | +{ \ | ||
366 | + sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \ | ||
367 | + sve_ld1##SUFF##_le_host, sve_ld1##SUFF##_le_tlb); \ | ||
368 | +} \ | ||
369 | +void HELPER(sve_ld##N##SUFF##_be_r_mte)(CPUARMState *env, void *vg, \ | ||
370 | + target_ulong addr, uint32_t desc) \ | ||
371 | +{ \ | ||
372 | + sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \ | ||
373 | + sve_ld1##SUFF##_be_host, sve_ld1##SUFF##_be_tlb); \ | ||
374 | } | ||
375 | |||
376 | DO_LDN_1(2) | ||
377 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
378 | index XXXXXXX..XXXXXXX 100644 | ||
379 | --- a/target/arm/translate-sve.c | ||
380 | +++ b/target/arm/translate-sve.c | ||
381 | @@ -XXX,XX +XXX,XX @@ static const uint8_t dtype_esz[16] = { | ||
382 | }; | ||
383 | |||
384 | static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | ||
385 | - int dtype, gen_helper_gvec_mem *fn) | ||
386 | + int dtype, uint32_t mte_n, bool is_write, | ||
387 | + gen_helper_gvec_mem *fn) | ||
388 | { | ||
389 | unsigned vsz = vec_full_reg_size(s); | ||
390 | TCGv_ptr t_pg; | ||
391 | TCGv_i32 t_desc; | ||
392 | - int desc; | ||
393 | + int desc = 0; | ||
394 | |||
395 | - /* For e.g. LD4, there are not enough arguments to pass all 4 | ||
396 | + /* | ||
397 | + * For e.g. LD4, there are not enough arguments to pass all 4 | ||
398 | * registers as pointers, so encode the regno into the data field. | ||
399 | * For consistency, do this even for LD1. | ||
400 | + * TODO: mte_n check here while callers are updated. | ||
401 | */ | ||
402 | - desc = simd_desc(vsz, vsz, zt); | ||
403 | + if (mte_n && s->mte_active[0]) { | ||
404 | + int msz = dtype_msz(dtype); | ||
405 | + | ||
406 | + desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | ||
407 | + desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | ||
408 | + desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | ||
409 | + desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | ||
410 | + desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz); | ||
411 | + desc = FIELD_DP32(desc, MTEDESC, TSIZE, mte_n << msz); | ||
412 | + desc <<= SVE_MTEDESC_SHIFT; | ||
413 | + } | ||
414 | + desc = simd_desc(vsz, vsz, zt | desc); | ||
415 | t_desc = tcg_const_i32(desc); | ||
416 | t_pg = tcg_temp_new_ptr(); | ||
417 | |||
418 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | ||
419 | static void do_ld_zpa(DisasContext *s, int zt, int pg, | ||
420 | TCGv_i64 addr, int dtype, int nreg) | ||
421 | { | ||
422 | - static gen_helper_gvec_mem * const fns[2][16][4] = { | ||
423 | - /* Little-endian */ | ||
424 | - { { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r, | ||
425 | + static gen_helper_gvec_mem * const fns[2][2][16][4] = { | ||
426 | + { /* mte inactive, little-endian */ | ||
427 | + { { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r, | ||
428 | gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r }, | ||
429 | - { gen_helper_sve_ld1bhu_r, NULL, NULL, NULL }, | ||
430 | - { gen_helper_sve_ld1bsu_r, NULL, NULL, NULL }, | ||
431 | - { gen_helper_sve_ld1bdu_r, NULL, NULL, NULL }, | ||
432 | + { gen_helper_sve_ld1bhu_r, NULL, NULL, NULL }, | ||
433 | + { gen_helper_sve_ld1bsu_r, NULL, NULL, NULL }, | ||
434 | + { gen_helper_sve_ld1bdu_r, NULL, NULL, NULL }, | ||
435 | |||
436 | - { gen_helper_sve_ld1sds_le_r, NULL, NULL, NULL }, | ||
437 | - { gen_helper_sve_ld1hh_le_r, gen_helper_sve_ld2hh_le_r, | ||
438 | - gen_helper_sve_ld3hh_le_r, gen_helper_sve_ld4hh_le_r }, | ||
439 | - { gen_helper_sve_ld1hsu_le_r, NULL, NULL, NULL }, | ||
440 | - { gen_helper_sve_ld1hdu_le_r, NULL, NULL, NULL }, | ||
441 | + { gen_helper_sve_ld1sds_le_r, NULL, NULL, NULL }, | ||
442 | + { gen_helper_sve_ld1hh_le_r, gen_helper_sve_ld2hh_le_r, | ||
443 | + gen_helper_sve_ld3hh_le_r, gen_helper_sve_ld4hh_le_r }, | ||
444 | + { gen_helper_sve_ld1hsu_le_r, NULL, NULL, NULL }, | ||
445 | + { gen_helper_sve_ld1hdu_le_r, NULL, NULL, NULL }, | ||
446 | |||
447 | - { gen_helper_sve_ld1hds_le_r, NULL, NULL, NULL }, | ||
448 | - { gen_helper_sve_ld1hss_le_r, NULL, NULL, NULL }, | ||
449 | - { gen_helper_sve_ld1ss_le_r, gen_helper_sve_ld2ss_le_r, | ||
450 | - gen_helper_sve_ld3ss_le_r, gen_helper_sve_ld4ss_le_r }, | ||
451 | - { gen_helper_sve_ld1sdu_le_r, NULL, NULL, NULL }, | ||
452 | + { gen_helper_sve_ld1hds_le_r, NULL, NULL, NULL }, | ||
453 | + { gen_helper_sve_ld1hss_le_r, NULL, NULL, NULL }, | ||
454 | + { gen_helper_sve_ld1ss_le_r, gen_helper_sve_ld2ss_le_r, | ||
455 | + gen_helper_sve_ld3ss_le_r, gen_helper_sve_ld4ss_le_r }, | ||
456 | + { gen_helper_sve_ld1sdu_le_r, NULL, NULL, NULL }, | ||
457 | |||
458 | - { gen_helper_sve_ld1bds_r, NULL, NULL, NULL }, | ||
459 | - { gen_helper_sve_ld1bss_r, NULL, NULL, NULL }, | ||
460 | - { gen_helper_sve_ld1bhs_r, NULL, NULL, NULL }, | ||
461 | - { gen_helper_sve_ld1dd_le_r, gen_helper_sve_ld2dd_le_r, | ||
462 | - gen_helper_sve_ld3dd_le_r, gen_helper_sve_ld4dd_le_r } }, | ||
463 | + { gen_helper_sve_ld1bds_r, NULL, NULL, NULL }, | ||
464 | + { gen_helper_sve_ld1bss_r, NULL, NULL, NULL }, | ||
465 | + { gen_helper_sve_ld1bhs_r, NULL, NULL, NULL }, | ||
466 | + { gen_helper_sve_ld1dd_le_r, gen_helper_sve_ld2dd_le_r, | ||
467 | + gen_helper_sve_ld3dd_le_r, gen_helper_sve_ld4dd_le_r } }, | ||
468 | |||
469 | - /* Big-endian */ | ||
470 | - { { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r, | ||
471 | - gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r }, | ||
472 | - { gen_helper_sve_ld1bhu_r, NULL, NULL, NULL }, | ||
473 | - { gen_helper_sve_ld1bsu_r, NULL, NULL, NULL }, | ||
474 | - { gen_helper_sve_ld1bdu_r, NULL, NULL, NULL }, | ||
475 | + /* mte inactive, big-endian */ | ||
476 | + { { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r, | ||
477 | + gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r }, | ||
478 | + { gen_helper_sve_ld1bhu_r, NULL, NULL, NULL }, | ||
479 | + { gen_helper_sve_ld1bsu_r, NULL, NULL, NULL }, | ||
480 | + { gen_helper_sve_ld1bdu_r, NULL, NULL, NULL }, | ||
481 | |||
482 | - { gen_helper_sve_ld1sds_be_r, NULL, NULL, NULL }, | ||
483 | - { gen_helper_sve_ld1hh_be_r, gen_helper_sve_ld2hh_be_r, | ||
484 | - gen_helper_sve_ld3hh_be_r, gen_helper_sve_ld4hh_be_r }, | ||
485 | - { gen_helper_sve_ld1hsu_be_r, NULL, NULL, NULL }, | ||
486 | - { gen_helper_sve_ld1hdu_be_r, NULL, NULL, NULL }, | ||
487 | + { gen_helper_sve_ld1sds_be_r, NULL, NULL, NULL }, | ||
488 | + { gen_helper_sve_ld1hh_be_r, gen_helper_sve_ld2hh_be_r, | ||
489 | + gen_helper_sve_ld3hh_be_r, gen_helper_sve_ld4hh_be_r }, | ||
490 | + { gen_helper_sve_ld1hsu_be_r, NULL, NULL, NULL }, | ||
491 | + { gen_helper_sve_ld1hdu_be_r, NULL, NULL, NULL }, | ||
492 | |||
493 | - { gen_helper_sve_ld1hds_be_r, NULL, NULL, NULL }, | ||
494 | - { gen_helper_sve_ld1hss_be_r, NULL, NULL, NULL }, | ||
495 | - { gen_helper_sve_ld1ss_be_r, gen_helper_sve_ld2ss_be_r, | ||
496 | - gen_helper_sve_ld3ss_be_r, gen_helper_sve_ld4ss_be_r }, | ||
497 | - { gen_helper_sve_ld1sdu_be_r, NULL, NULL, NULL }, | ||
498 | + { gen_helper_sve_ld1hds_be_r, NULL, NULL, NULL }, | ||
499 | + { gen_helper_sve_ld1hss_be_r, NULL, NULL, NULL }, | ||
500 | + { gen_helper_sve_ld1ss_be_r, gen_helper_sve_ld2ss_be_r, | ||
501 | + gen_helper_sve_ld3ss_be_r, gen_helper_sve_ld4ss_be_r }, | ||
502 | + { gen_helper_sve_ld1sdu_be_r, NULL, NULL, NULL }, | ||
503 | |||
504 | - { gen_helper_sve_ld1bds_r, NULL, NULL, NULL }, | ||
505 | - { gen_helper_sve_ld1bss_r, NULL, NULL, NULL }, | ||
506 | - { gen_helper_sve_ld1bhs_r, NULL, NULL, NULL }, | ||
507 | - { gen_helper_sve_ld1dd_be_r, gen_helper_sve_ld2dd_be_r, | ||
508 | - gen_helper_sve_ld3dd_be_r, gen_helper_sve_ld4dd_be_r } } | ||
509 | + { gen_helper_sve_ld1bds_r, NULL, NULL, NULL }, | ||
510 | + { gen_helper_sve_ld1bss_r, NULL, NULL, NULL }, | ||
511 | + { gen_helper_sve_ld1bhs_r, NULL, NULL, NULL }, | ||
512 | + { gen_helper_sve_ld1dd_be_r, gen_helper_sve_ld2dd_be_r, | ||
513 | + gen_helper_sve_ld3dd_be_r, gen_helper_sve_ld4dd_be_r } } }, | ||
514 | + | ||
515 | + { /* mte active, little-endian */ | ||
516 | + { { gen_helper_sve_ld1bb_r_mte, | ||
517 | + gen_helper_sve_ld2bb_r_mte, | ||
518 | + gen_helper_sve_ld3bb_r_mte, | ||
519 | + gen_helper_sve_ld4bb_r_mte }, | ||
520 | + { gen_helper_sve_ld1bhu_r_mte, NULL, NULL, NULL }, | ||
521 | + { gen_helper_sve_ld1bsu_r_mte, NULL, NULL, NULL }, | ||
522 | + { gen_helper_sve_ld1bdu_r_mte, NULL, NULL, NULL }, | ||
523 | + | ||
524 | + { gen_helper_sve_ld1sds_le_r_mte, NULL, NULL, NULL }, | ||
525 | + { gen_helper_sve_ld1hh_le_r_mte, | ||
526 | + gen_helper_sve_ld2hh_le_r_mte, | ||
527 | + gen_helper_sve_ld3hh_le_r_mte, | ||
528 | + gen_helper_sve_ld4hh_le_r_mte }, | ||
529 | + { gen_helper_sve_ld1hsu_le_r_mte, NULL, NULL, NULL }, | ||
530 | + { gen_helper_sve_ld1hdu_le_r_mte, NULL, NULL, NULL }, | ||
531 | + | ||
532 | + { gen_helper_sve_ld1hds_le_r_mte, NULL, NULL, NULL }, | ||
533 | + { gen_helper_sve_ld1hss_le_r_mte, NULL, NULL, NULL }, | ||
534 | + { gen_helper_sve_ld1ss_le_r_mte, | ||
535 | + gen_helper_sve_ld2ss_le_r_mte, | ||
536 | + gen_helper_sve_ld3ss_le_r_mte, | ||
537 | + gen_helper_sve_ld4ss_le_r_mte }, | ||
538 | + { gen_helper_sve_ld1sdu_le_r_mte, NULL, NULL, NULL }, | ||
539 | + | ||
540 | + { gen_helper_sve_ld1bds_r_mte, NULL, NULL, NULL }, | ||
541 | + { gen_helper_sve_ld1bss_r_mte, NULL, NULL, NULL }, | ||
542 | + { gen_helper_sve_ld1bhs_r_mte, NULL, NULL, NULL }, | ||
543 | + { gen_helper_sve_ld1dd_le_r_mte, | ||
544 | + gen_helper_sve_ld2dd_le_r_mte, | ||
545 | + gen_helper_sve_ld3dd_le_r_mte, | ||
546 | + gen_helper_sve_ld4dd_le_r_mte } }, | ||
547 | + | ||
548 | + /* mte active, big-endian */ | ||
549 | + { { gen_helper_sve_ld1bb_r_mte, | ||
550 | + gen_helper_sve_ld2bb_r_mte, | ||
551 | + gen_helper_sve_ld3bb_r_mte, | ||
552 | + gen_helper_sve_ld4bb_r_mte }, | ||
553 | + { gen_helper_sve_ld1bhu_r_mte, NULL, NULL, NULL }, | ||
554 | + { gen_helper_sve_ld1bsu_r_mte, NULL, NULL, NULL }, | ||
555 | + { gen_helper_sve_ld1bdu_r_mte, NULL, NULL, NULL }, | ||
556 | + | ||
557 | + { gen_helper_sve_ld1sds_be_r_mte, NULL, NULL, NULL }, | ||
558 | + { gen_helper_sve_ld1hh_be_r_mte, | ||
559 | + gen_helper_sve_ld2hh_be_r_mte, | ||
560 | + gen_helper_sve_ld3hh_be_r_mte, | ||
561 | + gen_helper_sve_ld4hh_be_r_mte }, | ||
562 | + { gen_helper_sve_ld1hsu_be_r_mte, NULL, NULL, NULL }, | ||
563 | + { gen_helper_sve_ld1hdu_be_r_mte, NULL, NULL, NULL }, | ||
564 | + | ||
565 | + { gen_helper_sve_ld1hds_be_r_mte, NULL, NULL, NULL }, | ||
566 | + { gen_helper_sve_ld1hss_be_r_mte, NULL, NULL, NULL }, | ||
567 | + { gen_helper_sve_ld1ss_be_r_mte, | ||
568 | + gen_helper_sve_ld2ss_be_r_mte, | ||
569 | + gen_helper_sve_ld3ss_be_r_mte, | ||
570 | + gen_helper_sve_ld4ss_be_r_mte }, | ||
571 | + { gen_helper_sve_ld1sdu_be_r_mte, NULL, NULL, NULL }, | ||
572 | + | ||
573 | + { gen_helper_sve_ld1bds_r_mte, NULL, NULL, NULL }, | ||
574 | + { gen_helper_sve_ld1bss_r_mte, NULL, NULL, NULL }, | ||
575 | + { gen_helper_sve_ld1bhs_r_mte, NULL, NULL, NULL }, | ||
576 | + { gen_helper_sve_ld1dd_be_r_mte, | ||
577 | + gen_helper_sve_ld2dd_be_r_mte, | ||
578 | + gen_helper_sve_ld3dd_be_r_mte, | ||
579 | + gen_helper_sve_ld4dd_be_r_mte } } }, | ||
580 | }; | ||
581 | - gen_helper_gvec_mem *fn = fns[s->be_data == MO_BE][dtype][nreg]; | ||
582 | + gen_helper_gvec_mem *fn | ||
583 | + = fns[s->mte_active[0]][s->be_data == MO_BE][dtype][nreg]; | ||
584 | |||
585 | - /* While there are holes in the table, they are not | ||
586 | + /* | ||
587 | + * While there are holes in the table, they are not | ||
588 | * accessible via the instruction encoding. | ||
589 | */ | ||
590 | assert(fn != NULL); | ||
591 | - do_mem_zpa(s, zt, pg, addr, dtype, fn); | ||
592 | + do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn); | ||
593 | } | ||
594 | |||
595 | static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a) | ||
596 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDFF1_zprr(DisasContext *s, arg_rprr_load *a) | ||
597 | TCGv_i64 addr = new_tmp_a64(s); | ||
598 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); | ||
599 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); | ||
600 | - do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, | ||
601 | + do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 0, false, | ||
602 | fns[s->be_data == MO_BE][a->dtype]); | ||
603 | } | ||
604 | return true; | ||
605 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a) | ||
606 | TCGv_i64 addr = new_tmp_a64(s); | ||
607 | |||
608 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), off); | ||
609 | - do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, | ||
610 | + do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 0, false, | ||
611 | fns[s->be_data == MO_BE][a->dtype]); | ||
612 | } | ||
613 | return true; | ||
614 | @@ -XXX,XX +XXX,XX @@ static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | ||
615 | fn = fn_multiple[be][nreg - 1][msz]; | ||
616 | } | ||
617 | assert(fn != NULL); | ||
618 | - do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), fn); | ||
619 | + do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), 0, true, fn); | ||
620 | } | ||
621 | |||
622 | static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a) | ||
623 | -- | 40 | -- |
624 | 2.20.1 | 41 | 2.20.1 |
625 | 42 | ||
626 | 43 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Model these off the aa64 read/write_vec_element functions. | ||
4 | Use it within translate-neon.c.inc. The new functions do | ||
5 | not allocate or free temps, so this rearranges the calling | ||
6 | code a bit. | ||
7 | |||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20201030022618.785675-6-richard.henderson@linaro.org | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20200626033144.790098-16-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 12 | --- |
8 | target/arm/helper-a64.h | 7 ++ | 13 | target/arm/translate.c | 26 ++++ |
9 | target/arm/helper.h | 2 + | 14 | target/arm/translate-neon.c.inc | 256 ++++++++++++++++++++------------ |
10 | target/arm/mte_helper.c | 194 +++++++++++++++++++++++++++++++++++++ | 15 | 2 files changed, 183 insertions(+), 99 deletions(-) |
11 | target/arm/op_helper.c | 16 +++ | ||
12 | target/arm/translate-a64.c | 172 +++++++++++++++++++++++++++++++- | ||
13 | 5 files changed, 386 insertions(+), 5 deletions(-) | ||
14 | 16 | ||
15 | diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h | 17 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
16 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper-a64.h | 19 | --- a/target/arm/translate.c |
18 | +++ b/target/arm/helper-a64.h | 20 | +++ b/target/arm/translate.c |
19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) | 21 | @@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg) |
20 | 22 | tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); | |
21 | DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) | 23 | } |
22 | DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32) | 24 | |
23 | +DEF_HELPER_FLAGS_3(ldg, TCG_CALL_NO_WG, i64, env, i64, i64) | 25 | +static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size) |
24 | +DEF_HELPER_FLAGS_3(stg, TCG_CALL_NO_WG, void, env, i64, i64) | ||
25 | +DEF_HELPER_FLAGS_3(stg_parallel, TCG_CALL_NO_WG, void, env, i64, i64) | ||
26 | +DEF_HELPER_FLAGS_2(stg_stub, TCG_CALL_NO_WG, void, env, i64) | ||
27 | +DEF_HELPER_FLAGS_3(st2g, TCG_CALL_NO_WG, void, env, i64, i64) | ||
28 | +DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64) | ||
29 | +DEF_HELPER_FLAGS_2(st2g_stub, TCG_CALL_NO_WG, void, env, i64) | ||
30 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/helper.h | ||
33 | +++ b/target/arm/helper.h | ||
34 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env) | ||
35 | DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) | ||
36 | DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) | ||
37 | |||
38 | +DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, tl, i32, i32, i32) | ||
39 | + | ||
40 | DEF_HELPER_1(vfp_get_fpscr, i32, env) | ||
41 | DEF_HELPER_2(vfp_set_fpscr, void, env, i32) | ||
42 | |||
43 | diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/target/arm/mte_helper.c | ||
46 | +++ b/target/arm/mte_helper.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) | ||
48 | return tag; | ||
49 | } | ||
50 | |||
51 | +/** | ||
52 | + * allocation_tag_mem: | ||
53 | + * @env: the cpu environment | ||
54 | + * @ptr_mmu_idx: the addressing regime to use for the virtual address | ||
55 | + * @ptr: the virtual address for which to look up tag memory | ||
56 | + * @ptr_access: the access to use for the virtual address | ||
57 | + * @ptr_size: the number of bytes in the normal memory access | ||
58 | + * @tag_access: the access to use for the tag memory | ||
59 | + * @tag_size: the number of bytes in the tag memory access | ||
60 | + * @ra: the return address for exception handling | ||
61 | + * | ||
62 | + * Our tag memory is formatted as a sequence of little-endian nibbles. | ||
63 | + * That is, the byte at (addr >> (LOG2_TAG_GRANULE + 1)) contains two | ||
64 | + * tags, with the tag at [3:0] for the lower addr and the tag at [7:4] | ||
65 | + * for the higher addr. | ||
66 | + * | ||
67 | + * Here, resolve the physical address from the virtual address, and return | ||
68 | + * a pointer to the corresponding tag byte. Exit with exception if the | ||
69 | + * virtual address is not accessible for @ptr_access. | ||
70 | + * | ||
71 | + * The @ptr_size and @tag_size values may not have an obvious relation | ||
72 | + * due to the alignment of @ptr, and the number of tag checks required. | ||
73 | + * | ||
74 | + * If there is no tag storage corresponding to @ptr, return NULL. | ||
75 | + */ | ||
76 | +static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, | ||
77 | + uint64_t ptr, MMUAccessType ptr_access, | ||
78 | + int ptr_size, MMUAccessType tag_access, | ||
79 | + int tag_size, uintptr_t ra) | ||
80 | +{ | 26 | +{ |
81 | + /* Tag storage not implemented. */ | 27 | + long off = neon_element_offset(reg, ele, size); |
82 | + return NULL; | 28 | + |
83 | +} | 29 | + switch (size) { |
84 | + | 30 | + case MO_32: |
85 | uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) | 31 | + tcg_gen_ld_i32(dest, cpu_env, off); |
86 | { | 32 | + break; |
87 | int rtag; | 33 | + default: |
88 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(addsubg)(CPUARMState *env, uint64_t ptr, | ||
89 | |||
90 | return address_with_allocation_tag(ptr + offset, rtag); | ||
91 | } | ||
92 | + | ||
93 | +static int load_tag1(uint64_t ptr, uint8_t *mem) | ||
94 | +{ | ||
95 | + int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; | ||
96 | + return extract32(*mem, ofs, 4); | ||
97 | +} | ||
98 | + | ||
99 | +uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt) | ||
100 | +{ | ||
101 | + int mmu_idx = cpu_mmu_index(env, false); | ||
102 | + uint8_t *mem; | ||
103 | + int rtag = 0; | ||
104 | + | ||
105 | + /* Trap if accessing an invalid page. */ | ||
106 | + mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD, 1, | ||
107 | + MMU_DATA_LOAD, 1, GETPC()); | ||
108 | + | ||
109 | + /* Load if page supports tags. */ | ||
110 | + if (mem) { | ||
111 | + rtag = load_tag1(ptr, mem); | ||
112 | + } | ||
113 | + | ||
114 | + return address_with_allocation_tag(xt, rtag); | ||
115 | +} | ||
116 | + | ||
117 | +static void check_tag_aligned(CPUARMState *env, uint64_t ptr, uintptr_t ra) | ||
118 | +{ | ||
119 | + if (unlikely(!QEMU_IS_ALIGNED(ptr, TAG_GRANULE))) { | ||
120 | + arm_cpu_do_unaligned_access(env_cpu(env), ptr, MMU_DATA_STORE, | ||
121 | + cpu_mmu_index(env, false), ra); | ||
122 | + g_assert_not_reached(); | 34 | + g_assert_not_reached(); |
123 | + } | 35 | + } |
124 | +} | 36 | +} |
125 | + | 37 | + |
126 | +/* For use in a non-parallel context, store to the given nibble. */ | 38 | +static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size) |
127 | +static void store_tag1(uint64_t ptr, uint8_t *mem, int tag) | ||
128 | +{ | 39 | +{ |
129 | + int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; | 40 | + long off = neon_element_offset(reg, ele, size); |
130 | + *mem = deposit32(*mem, ofs, 4, tag); | 41 | + |
131 | +} | 42 | + switch (size) { |
132 | + | 43 | + case MO_32: |
133 | +/* For use in a parallel context, atomically store to the given nibble. */ | 44 | + tcg_gen_st_i32(src, cpu_env, off); |
134 | +static void store_tag1_parallel(uint64_t ptr, uint8_t *mem, int tag) | 45 | + break; |
135 | +{ | 46 | + default: |
136 | + int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; | 47 | + g_assert_not_reached(); |
137 | + uint8_t old = atomic_read(mem); | ||
138 | + | ||
139 | + while (1) { | ||
140 | + uint8_t new = deposit32(old, ofs, 4, tag); | ||
141 | + uint8_t cmp = atomic_cmpxchg(mem, old, new); | ||
142 | + if (likely(cmp == old)) { | ||
143 | + return; | ||
144 | + } | ||
145 | + old = cmp; | ||
146 | + } | 48 | + } |
147 | +} | 49 | +} |
148 | + | 50 | + |
149 | +typedef void stg_store1(uint64_t, uint8_t *, int); | 51 | static TCGv_ptr vfp_reg_ptr(bool dp, int reg) |
150 | + | 52 | { |
151 | +static inline void do_stg(CPUARMState *env, uint64_t ptr, uint64_t xt, | 53 | TCGv_ptr ret = tcg_temp_new_ptr(); |
152 | + uintptr_t ra, stg_store1 store1) | 54 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc |
153 | +{ | ||
154 | + int mmu_idx = cpu_mmu_index(env, false); | ||
155 | + uint8_t *mem; | ||
156 | + | ||
157 | + check_tag_aligned(env, ptr, ra); | ||
158 | + | ||
159 | + /* Trap if accessing an invalid page. */ | ||
160 | + mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, TAG_GRANULE, | ||
161 | + MMU_DATA_STORE, 1, ra); | ||
162 | + | ||
163 | + /* Store if page supports tags. */ | ||
164 | + if (mem) { | ||
165 | + store1(ptr, mem, allocation_tag_from_addr(xt)); | ||
166 | + } | ||
167 | +} | ||
168 | + | ||
169 | +void HELPER(stg)(CPUARMState *env, uint64_t ptr, uint64_t xt) | ||
170 | +{ | ||
171 | + do_stg(env, ptr, xt, GETPC(), store_tag1); | ||
172 | +} | ||
173 | + | ||
174 | +void HELPER(stg_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt) | ||
175 | +{ | ||
176 | + do_stg(env, ptr, xt, GETPC(), store_tag1_parallel); | ||
177 | +} | ||
178 | + | ||
179 | +void HELPER(stg_stub)(CPUARMState *env, uint64_t ptr) | ||
180 | +{ | ||
181 | + int mmu_idx = cpu_mmu_index(env, false); | ||
182 | + uintptr_t ra = GETPC(); | ||
183 | + | ||
184 | + check_tag_aligned(env, ptr, ra); | ||
185 | + probe_write(env, ptr, TAG_GRANULE, mmu_idx, ra); | ||
186 | +} | ||
187 | + | ||
188 | +static inline void do_st2g(CPUARMState *env, uint64_t ptr, uint64_t xt, | ||
189 | + uintptr_t ra, stg_store1 store1) | ||
190 | +{ | ||
191 | + int mmu_idx = cpu_mmu_index(env, false); | ||
192 | + int tag = allocation_tag_from_addr(xt); | ||
193 | + uint8_t *mem1, *mem2; | ||
194 | + | ||
195 | + check_tag_aligned(env, ptr, ra); | ||
196 | + | ||
197 | + /* | ||
198 | + * Trap if accessing an invalid page(s). | ||
199 | + * This takes priority over !allocation_tag_access_enabled. | ||
200 | + */ | ||
201 | + if (ptr & TAG_GRANULE) { | ||
202 | + /* Two stores unaligned mod TAG_GRANULE*2 -- modify two bytes. */ | ||
203 | + mem1 = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, | ||
204 | + TAG_GRANULE, MMU_DATA_STORE, 1, ra); | ||
205 | + mem2 = allocation_tag_mem(env, mmu_idx, ptr + TAG_GRANULE, | ||
206 | + MMU_DATA_STORE, TAG_GRANULE, | ||
207 | + MMU_DATA_STORE, 1, ra); | ||
208 | + | ||
209 | + /* Store if page(s) support tags. */ | ||
210 | + if (mem1) { | ||
211 | + store1(TAG_GRANULE, mem1, tag); | ||
212 | + } | ||
213 | + if (mem2) { | ||
214 | + store1(0, mem2, tag); | ||
215 | + } | ||
216 | + } else { | ||
217 | + /* Two stores aligned mod TAG_GRANULE*2 -- modify one byte. */ | ||
218 | + mem1 = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, | ||
219 | + 2 * TAG_GRANULE, MMU_DATA_STORE, 1, ra); | ||
220 | + if (mem1) { | ||
221 | + tag |= tag << 4; | ||
222 | + atomic_set(mem1, tag); | ||
223 | + } | ||
224 | + } | ||
225 | +} | ||
226 | + | ||
227 | +void HELPER(st2g)(CPUARMState *env, uint64_t ptr, uint64_t xt) | ||
228 | +{ | ||
229 | + do_st2g(env, ptr, xt, GETPC(), store_tag1); | ||
230 | +} | ||
231 | + | ||
232 | +void HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt) | ||
233 | +{ | ||
234 | + do_st2g(env, ptr, xt, GETPC(), store_tag1_parallel); | ||
235 | +} | ||
236 | + | ||
237 | +void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr) | ||
238 | +{ | ||
239 | + int mmu_idx = cpu_mmu_index(env, false); | ||
240 | + uintptr_t ra = GETPC(); | ||
241 | + int in_page = -(ptr | TARGET_PAGE_MASK); | ||
242 | + | ||
243 | + check_tag_aligned(env, ptr, ra); | ||
244 | + | ||
245 | + if (likely(in_page >= 2 * TAG_GRANULE)) { | ||
246 | + probe_write(env, ptr, 2 * TAG_GRANULE, mmu_idx, ra); | ||
247 | + } else { | ||
248 | + probe_write(env, ptr, TAG_GRANULE, mmu_idx, ra); | ||
249 | + probe_write(env, ptr + TAG_GRANULE, TAG_GRANULE, mmu_idx, ra); | ||
250 | + } | ||
251 | +} | ||
252 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
253 | index XXXXXXX..XXXXXXX 100644 | 55 | index XXXXXXX..XXXXXXX 100644 |
254 | --- a/target/arm/op_helper.c | 56 | --- a/target/arm/translate-neon.c.inc |
255 | +++ b/target/arm/op_helper.c | 57 | +++ b/target/arm/translate-neon.c.inc |
256 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i) | 58 | @@ -XXX,XX +XXX,XX @@ static bool do_3same_pair(DisasContext *s, arg_3same *a, NeonGenTwoOpFn *fn) |
257 | return ((uint32_t)x >> shift) | (x << (32 - shift)); | 59 | * early. Since Q is 0 there are always just two passes, so instead |
258 | } | 60 | * of a complicated loop over each pass we just unroll. |
259 | } | 61 | */ |
260 | + | 62 | - tmp = neon_load_reg(a->vn, 0); |
261 | +void HELPER(probe_access)(CPUARMState *env, target_ulong ptr, | 63 | - tmp2 = neon_load_reg(a->vn, 1); |
262 | + uint32_t access_type, uint32_t mmu_idx, | 64 | + tmp = tcg_temp_new_i32(); |
263 | + uint32_t size) | 65 | + tmp2 = tcg_temp_new_i32(); |
264 | +{ | 66 | + tmp3 = tcg_temp_new_i32(); |
265 | + uint32_t in_page = -((uint32_t)ptr | TARGET_PAGE_SIZE); | 67 | + |
266 | + uintptr_t ra = GETPC(); | 68 | + read_neon_element32(tmp, a->vn, 0, MO_32); |
267 | + | 69 | + read_neon_element32(tmp2, a->vn, 1, MO_32); |
268 | + if (likely(size <= in_page)) { | 70 | fn(tmp, tmp, tmp2); |
269 | + probe_access(env, ptr, size, access_type, mmu_idx, ra); | 71 | - tcg_temp_free_i32(tmp2); |
270 | + } else { | 72 | |
271 | + probe_access(env, ptr, in_page, access_type, mmu_idx, ra); | 73 | - tmp3 = neon_load_reg(a->vm, 0); |
272 | + probe_access(env, ptr + in_page, size - in_page, | 74 | - tmp2 = neon_load_reg(a->vm, 1); |
273 | + access_type, mmu_idx, ra); | 75 | + read_neon_element32(tmp3, a->vm, 0, MO_32); |
274 | + } | 76 | + read_neon_element32(tmp2, a->vm, 1, MO_32); |
275 | +} | 77 | fn(tmp3, tmp3, tmp2); |
276 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 78 | - tcg_temp_free_i32(tmp2); |
277 | index XXXXXXX..XXXXXXX 100644 | 79 | |
278 | --- a/target/arm/translate-a64.c | 80 | - neon_store_reg(a->vd, 0, tmp); |
279 | +++ b/target/arm/translate-a64.c | 81 | - neon_store_reg(a->vd, 1, tmp3); |
280 | @@ -XXX,XX +XXX,XX @@ static void gen_address_with_allocation_tag0(TCGv_i64 dst, TCGv_i64 src) | 82 | + write_neon_element32(tmp, a->vd, 0, MO_32); |
281 | tcg_gen_andi_i64(dst, src, ~MAKE_64BIT_MASK(56, 4)); | 83 | + write_neon_element32(tmp3, a->vd, 1, MO_32); |
282 | } | 84 | + |
283 | 85 | + tcg_temp_free_i32(tmp); | |
284 | +static void gen_probe_access(DisasContext *s, TCGv_i64 ptr, | 86 | + tcg_temp_free_i32(tmp2); |
285 | + MMUAccessType acc, int log2_size) | 87 | + tcg_temp_free_i32(tmp3); |
286 | +{ | 88 | return true; |
287 | + TCGv_i32 t_acc = tcg_const_i32(acc); | 89 | } |
288 | + TCGv_i32 t_idx = tcg_const_i32(get_mem_index(s)); | 90 | |
289 | + TCGv_i32 t_size = tcg_const_i32(1 << log2_size); | 91 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a, |
290 | + | 92 | * 2-reg-and-shift operations, size < 3 case, where the |
291 | + gen_helper_probe_access(cpu_env, ptr, t_acc, t_idx, t_size); | 93 | * helper needs to be passed cpu_env. |
292 | + tcg_temp_free_i32(t_acc); | 94 | */ |
293 | + tcg_temp_free_i32(t_idx); | 95 | - TCGv_i32 constimm; |
294 | + tcg_temp_free_i32(t_size); | 96 | + TCGv_i32 constimm, tmp; |
295 | +} | 97 | int pass; |
296 | + | 98 | |
297 | typedef struct DisasCompare64 { | 99 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { |
298 | TCGCond cond; | 100 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a, |
299 | TCGv_i64 value; | 101 | * by immediate using the variable shift operations. |
300 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) | 102 | */ |
301 | } | 103 | constimm = tcg_const_i32(dup_const(a->size, a->shift)); |
302 | } | 104 | + tmp = tcg_temp_new_i32(); |
303 | 105 | ||
304 | +/* | 106 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { |
305 | + * Load/Store memory tags | 107 | - TCGv_i32 tmp = neon_load_reg(a->vm, pass); |
306 | + * | 108 | + read_neon_element32(tmp, a->vm, pass, MO_32); |
307 | + * 31 30 29 24 22 21 12 10 5 0 | 109 | fn(tmp, cpu_env, tmp, constimm); |
308 | + * +-----+-------------+-----+---+------+-----+------+------+ | 110 | - neon_store_reg(a->vd, pass, tmp); |
309 | + * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt | | 111 | + write_neon_element32(tmp, a->vd, pass, MO_32); |
310 | + * +-----+-------------+-----+---+------+-----+------+------+ | 112 | } |
311 | + */ | 113 | + tcg_temp_free_i32(tmp); |
312 | +static void disas_ldst_tag(DisasContext *s, uint32_t insn) | 114 | tcg_temp_free_i32(constimm); |
313 | +{ | 115 | return true; |
314 | + int rt = extract32(insn, 0, 5); | 116 | } |
315 | + int rn = extract32(insn, 5, 5); | 117 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a, |
316 | + uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; | 118 | constimm = tcg_const_i64(-a->shift); |
317 | + int op2 = extract32(insn, 10, 2); | 119 | rm1 = tcg_temp_new_i64(); |
318 | + int op1 = extract32(insn, 22, 2); | 120 | rm2 = tcg_temp_new_i64(); |
319 | + bool is_load = false, is_pair = false, is_zero = false; | 121 | + rd = tcg_temp_new_i32(); |
320 | + int index = 0; | 122 | |
321 | + TCGv_i64 addr, clean_addr, tcg_rt; | 123 | /* Load both inputs first to avoid potential overwrite if rm == rd */ |
322 | + | 124 | neon_load_reg64(rm1, a->vm); |
323 | + /* We checked insn bits [29:24,21] in the caller. */ | 125 | neon_load_reg64(rm2, a->vm + 1); |
324 | + if (extract32(insn, 30, 2) != 3) { | 126 | |
325 | + goto do_unallocated; | 127 | shiftfn(rm1, rm1, constimm); |
326 | + } | 128 | - rd = tcg_temp_new_i32(); |
327 | + | 129 | narrowfn(rd, cpu_env, rm1); |
328 | + /* | 130 | - neon_store_reg(a->vd, 0, rd); |
329 | + * @index is a tri-state variable which has 3 states: | 131 | + write_neon_element32(rd, a->vd, 0, MO_32); |
330 | + * < 0 : post-index, writeback | 132 | |
331 | + * = 0 : signed offset | 133 | shiftfn(rm2, rm2, constimm); |
332 | + * > 0 : pre-index, writeback | 134 | - rd = tcg_temp_new_i32(); |
333 | + */ | 135 | narrowfn(rd, cpu_env, rm2); |
334 | + switch (op1) { | 136 | - neon_store_reg(a->vd, 1, rd); |
335 | + case 0: | 137 | + write_neon_element32(rd, a->vd, 1, MO_32); |
336 | + if (op2 != 0) { | 138 | |
337 | + /* STG */ | 139 | + tcg_temp_free_i32(rd); |
338 | + index = op2 - 2; | 140 | tcg_temp_free_i64(rm1); |
339 | + break; | 141 | tcg_temp_free_i64(rm2); |
340 | + } | 142 | tcg_temp_free_i64(constimm); |
341 | + goto do_unallocated; | 143 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, |
342 | + case 1: | 144 | constimm = tcg_const_i32(imm); |
343 | + if (op2 != 0) { | 145 | |
344 | + /* STZG */ | 146 | /* Load all inputs first to avoid potential overwrite */ |
345 | + is_zero = true; | 147 | - rm1 = neon_load_reg(a->vm, 0); |
346 | + index = op2 - 2; | 148 | - rm2 = neon_load_reg(a->vm, 1); |
347 | + } else { | 149 | - rm3 = neon_load_reg(a->vm + 1, 0); |
348 | + /* LDG */ | 150 | - rm4 = neon_load_reg(a->vm + 1, 1); |
349 | + is_load = true; | 151 | + rm1 = tcg_temp_new_i32(); |
350 | + } | 152 | + rm2 = tcg_temp_new_i32(); |
351 | + break; | 153 | + rm3 = tcg_temp_new_i32(); |
352 | + case 2: | 154 | + rm4 = tcg_temp_new_i32(); |
353 | + if (op2 != 0) { | 155 | + read_neon_element32(rm1, a->vm, 0, MO_32); |
354 | + /* ST2G */ | 156 | + read_neon_element32(rm2, a->vm, 1, MO_32); |
355 | + is_pair = true; | 157 | + read_neon_element32(rm3, a->vm, 2, MO_32); |
356 | + index = op2 - 2; | 158 | + read_neon_element32(rm4, a->vm, 3, MO_32); |
357 | + break; | 159 | rtmp = tcg_temp_new_i64(); |
358 | + } | 160 | |
359 | + goto do_unallocated; | 161 | shiftfn(rm1, rm1, constimm); |
360 | + case 3: | 162 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, |
361 | + if (op2 != 0) { | 163 | tcg_temp_free_i32(rm2); |
362 | + /* STZ2G */ | 164 | |
363 | + is_pair = is_zero = true; | 165 | narrowfn(rm1, cpu_env, rtmp); |
364 | + index = op2 - 2; | 166 | - neon_store_reg(a->vd, 0, rm1); |
365 | + break; | 167 | + write_neon_element32(rm1, a->vd, 0, MO_32); |
366 | + } | 168 | + tcg_temp_free_i32(rm1); |
367 | + goto do_unallocated; | 169 | |
368 | + | 170 | shiftfn(rm3, rm3, constimm); |
369 | + default: | 171 | shiftfn(rm4, rm4, constimm); |
370 | + do_unallocated: | 172 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, |
371 | + unallocated_encoding(s); | 173 | |
372 | + return; | 174 | narrowfn(rm3, cpu_env, rtmp); |
373 | + } | 175 | tcg_temp_free_i64(rtmp); |
374 | + | 176 | - neon_store_reg(a->vd, 1, rm3); |
375 | + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { | 177 | + write_neon_element32(rm3, a->vd, 1, MO_32); |
376 | + goto do_unallocated; | 178 | + tcg_temp_free_i32(rm3); |
377 | + } | 179 | return true; |
378 | + | 180 | } |
379 | + if (rn == 31) { | 181 | |
380 | + gen_check_sp_alignment(s); | 182 | @@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, |
381 | + } | 183 | widen_mask = dup_const(a->size + 1, widen_mask); |
382 | + | 184 | } |
383 | + addr = read_cpu_reg_sp(s, rn, true); | 185 | |
384 | + if (index >= 0) { | 186 | - rm0 = neon_load_reg(a->vm, 0); |
385 | + /* pre-index or signed offset */ | 187 | - rm1 = neon_load_reg(a->vm, 1); |
386 | + tcg_gen_addi_i64(addr, addr, offset); | 188 | + rm0 = tcg_temp_new_i32(); |
387 | + } | 189 | + rm1 = tcg_temp_new_i32(); |
388 | + | 190 | + read_neon_element32(rm0, a->vm, 0, MO_32); |
389 | + if (is_load) { | 191 | + read_neon_element32(rm1, a->vm, 1, MO_32); |
390 | + tcg_gen_andi_i64(addr, addr, -TAG_GRANULE); | 192 | tmp = tcg_temp_new_i64(); |
391 | + tcg_rt = cpu_reg(s, rt); | 193 | |
392 | + if (s->ata) { | 194 | widenfn(tmp, rm0); |
393 | + gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); | 195 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, |
394 | + } else { | 196 | if (src1_wide) { |
395 | + clean_addr = clean_data_tbi(s, addr); | 197 | neon_load_reg64(rn0_64, a->vn); |
396 | + gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8); | 198 | } else { |
397 | + gen_address_with_allocation_tag0(tcg_rt, addr); | 199 | - TCGv_i32 tmp = neon_load_reg(a->vn, 0); |
398 | + } | 200 | + TCGv_i32 tmp = tcg_temp_new_i32(); |
399 | + } else { | 201 | + read_neon_element32(tmp, a->vn, 0, MO_32); |
400 | + tcg_rt = cpu_reg_sp(s, rt); | 202 | widenfn(rn0_64, tmp); |
401 | + if (!s->ata) { | 203 | tcg_temp_free_i32(tmp); |
402 | + /* | 204 | } |
403 | + * For STG and ST2G, we need to check alignment and probe memory. | 205 | - rm = neon_load_reg(a->vm, 0); |
404 | + * TODO: For STZG and STZ2G, we could rely on the stores below, | 206 | + rm = tcg_temp_new_i32(); |
405 | + * at least for system mode; user-only won't enforce alignment. | 207 | + read_neon_element32(rm, a->vm, 0, MO_32); |
406 | + */ | 208 | |
407 | + if (is_pair) { | 209 | widenfn(rm_64, rm); |
408 | + gen_helper_st2g_stub(cpu_env, addr); | 210 | tcg_temp_free_i32(rm); |
409 | + } else { | 211 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, |
410 | + gen_helper_stg_stub(cpu_env, addr); | 212 | if (src1_wide) { |
411 | + } | 213 | neon_load_reg64(rn1_64, a->vn + 1); |
412 | + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { | 214 | } else { |
413 | + if (is_pair) { | 215 | - TCGv_i32 tmp = neon_load_reg(a->vn, 1); |
414 | + gen_helper_st2g_parallel(cpu_env, addr, tcg_rt); | 216 | + TCGv_i32 tmp = tcg_temp_new_i32(); |
415 | + } else { | 217 | + read_neon_element32(tmp, a->vn, 1, MO_32); |
416 | + gen_helper_stg_parallel(cpu_env, addr, tcg_rt); | 218 | widenfn(rn1_64, tmp); |
417 | + } | 219 | tcg_temp_free_i32(tmp); |
418 | + } else { | 220 | } |
419 | + if (is_pair) { | 221 | - rm = neon_load_reg(a->vm, 1); |
420 | + gen_helper_st2g(cpu_env, addr, tcg_rt); | 222 | + rm = tcg_temp_new_i32(); |
421 | + } else { | 223 | + read_neon_element32(rm, a->vm, 1, MO_32); |
422 | + gen_helper_stg(cpu_env, addr, tcg_rt); | 224 | |
423 | + } | 225 | neon_store_reg64(rn0_64, a->vd); |
424 | + } | 226 | |
425 | + } | 227 | @@ -XXX,XX +XXX,XX @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a, |
426 | + | 228 | |
427 | + if (is_zero) { | 229 | narrowfn(rd1, rn_64); |
428 | + TCGv_i64 clean_addr = clean_data_tbi(s, addr); | 230 | |
429 | + TCGv_i64 tcg_zero = tcg_const_i64(0); | 231 | - neon_store_reg(a->vd, 0, rd0); |
430 | + int mem_index = get_mem_index(s); | 232 | - neon_store_reg(a->vd, 1, rd1); |
431 | + int i, n = (1 + is_pair) << LOG2_TAG_GRANULE; | 233 | + write_neon_element32(rd0, a->vd, 0, MO_32); |
432 | + | 234 | + write_neon_element32(rd1, a->vd, 1, MO_32); |
433 | + tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, | 235 | |
434 | + MO_Q | MO_ALIGN_16); | 236 | + tcg_temp_free_i32(rd0); |
435 | + for (i = 8; i < n; i += 8) { | 237 | + tcg_temp_free_i32(rd1); |
436 | + tcg_gen_addi_i64(clean_addr, clean_addr, 8); | 238 | tcg_temp_free_i64(rn_64); |
437 | + tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_Q); | 239 | tcg_temp_free_i64(rm_64); |
438 | + } | 240 | |
439 | + tcg_temp_free_i64(tcg_zero); | 241 | @@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a, |
440 | + } | 242 | rd0 = tcg_temp_new_i64(); |
441 | + | 243 | rd1 = tcg_temp_new_i64(); |
442 | + if (index != 0) { | 244 | |
443 | + /* pre-index or post-index */ | 245 | - rn = neon_load_reg(a->vn, 0); |
444 | + if (index < 0) { | 246 | - rm = neon_load_reg(a->vm, 0); |
445 | + /* post-index */ | 247 | + rn = tcg_temp_new_i32(); |
446 | + tcg_gen_addi_i64(addr, addr, offset); | 248 | + rm = tcg_temp_new_i32(); |
447 | + } | 249 | + read_neon_element32(rn, a->vn, 0, MO_32); |
448 | + tcg_gen_mov_i64(cpu_reg_sp(s, rn), addr); | 250 | + read_neon_element32(rm, a->vm, 0, MO_32); |
449 | + } | 251 | opfn(rd0, rn, rm); |
450 | +} | 252 | - tcg_temp_free_i32(rn); |
451 | + | 253 | - tcg_temp_free_i32(rm); |
452 | /* Loads and stores */ | 254 | |
453 | static void disas_ldst(DisasContext *s, uint32_t insn) | 255 | - rn = neon_load_reg(a->vn, 1); |
256 | - rm = neon_load_reg(a->vm, 1); | ||
257 | + read_neon_element32(rn, a->vn, 1, MO_32); | ||
258 | + read_neon_element32(rm, a->vm, 1, MO_32); | ||
259 | opfn(rd1, rn, rm); | ||
260 | tcg_temp_free_i32(rn); | ||
261 | tcg_temp_free_i32(rm); | ||
262 | @@ -XXX,XX +XXX,XX @@ static void gen_neon_dup_high16(TCGv_i32 var) | ||
263 | |||
264 | static inline TCGv_i32 neon_get_scalar(int size, int reg) | ||
454 | { | 265 | { |
455 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst(DisasContext *s, uint32_t insn) | 266 | - TCGv_i32 tmp; |
456 | case 0x0d: /* AdvSIMD load/store single structure */ | 267 | - if (size == 1) { |
457 | disas_ldst_single_struct(s, insn); | 268 | - tmp = neon_load_reg(reg & 7, reg >> 4); |
458 | break; | 269 | + TCGv_i32 tmp = tcg_temp_new_i32(); |
459 | - case 0x19: /* LDAPR/STLR (unscaled immediate) */ | 270 | + if (size == MO_16) { |
460 | - if (extract32(insn, 10, 2) != 0 || | 271 | + read_neon_element32(tmp, reg & 7, reg >> 4, MO_32); |
461 | - extract32(insn, 21, 1) != 0) { | 272 | if (reg & 8) { |
462 | + case 0x19: | 273 | gen_neon_dup_high16(tmp); |
463 | + if (extract32(insn, 21, 1) != 0) { | 274 | } else { |
464 | + disas_ldst_tag(s, insn); | 275 | gen_neon_dup_low16(tmp); |
465 | + } else if (extract32(insn, 10, 2) == 0) { | ||
466 | + disas_ldst_ldapr_stlr(s, insn); | ||
467 | + } else { | ||
468 | unallocated_encoding(s); | ||
469 | - break; | ||
470 | } | 276 | } |
471 | - disas_ldst_ldapr_stlr(s, insn); | 277 | } else { |
472 | break; | 278 | - tmp = neon_load_reg(reg & 15, reg >> 4); |
473 | default: | 279 | + read_neon_element32(tmp, reg & 15, reg >> 4, MO_32); |
474 | unallocated_encoding(s); | 280 | } |
281 | return tmp; | ||
282 | } | ||
283 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar(DisasContext *s, arg_2scalar *a, | ||
284 | * perform an accumulation operation of that result into the | ||
285 | * destination. | ||
286 | */ | ||
287 | - TCGv_i32 scalar; | ||
288 | + TCGv_i32 scalar, tmp; | ||
289 | int pass; | ||
290 | |||
291 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
292 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar(DisasContext *s, arg_2scalar *a, | ||
293 | } | ||
294 | |||
295 | scalar = neon_get_scalar(a->size, a->vm); | ||
296 | + tmp = tcg_temp_new_i32(); | ||
297 | |||
298 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
299 | - TCGv_i32 tmp = neon_load_reg(a->vn, pass); | ||
300 | + read_neon_element32(tmp, a->vn, pass, MO_32); | ||
301 | opfn(tmp, tmp, scalar); | ||
302 | if (accfn) { | ||
303 | - TCGv_i32 rd = neon_load_reg(a->vd, pass); | ||
304 | + TCGv_i32 rd = tcg_temp_new_i32(); | ||
305 | + read_neon_element32(rd, a->vd, pass, MO_32); | ||
306 | accfn(tmp, rd, tmp); | ||
307 | tcg_temp_free_i32(rd); | ||
308 | } | ||
309 | - neon_store_reg(a->vd, pass, tmp); | ||
310 | + write_neon_element32(tmp, a->vd, pass, MO_32); | ||
311 | } | ||
312 | + tcg_temp_free_i32(tmp); | ||
313 | tcg_temp_free_i32(scalar); | ||
314 | return true; | ||
315 | } | ||
316 | @@ -XXX,XX +XXX,XX @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a, | ||
317 | * performs a kind of fused op-then-accumulate using a helper | ||
318 | * function that takes all of rd, rn and the scalar at once. | ||
319 | */ | ||
320 | - TCGv_i32 scalar; | ||
321 | + TCGv_i32 scalar, rn, rd; | ||
322 | int pass; | ||
323 | |||
324 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
325 | @@ -XXX,XX +XXX,XX @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a, | ||
326 | } | ||
327 | |||
328 | scalar = neon_get_scalar(a->size, a->vm); | ||
329 | + rn = tcg_temp_new_i32(); | ||
330 | + rd = tcg_temp_new_i32(); | ||
331 | |||
332 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
333 | - TCGv_i32 rn = neon_load_reg(a->vn, pass); | ||
334 | - TCGv_i32 rd = neon_load_reg(a->vd, pass); | ||
335 | + read_neon_element32(rn, a->vn, pass, MO_32); | ||
336 | + read_neon_element32(rd, a->vd, pass, MO_32); | ||
337 | opfn(rd, cpu_env, rn, scalar, rd); | ||
338 | - tcg_temp_free_i32(rn); | ||
339 | - neon_store_reg(a->vd, pass, rd); | ||
340 | + write_neon_element32(rd, a->vd, pass, MO_32); | ||
341 | } | ||
342 | + tcg_temp_free_i32(rn); | ||
343 | + tcg_temp_free_i32(rd); | ||
344 | tcg_temp_free_i32(scalar); | ||
345 | |||
346 | return true; | ||
347 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a, | ||
348 | scalar = neon_get_scalar(a->size, a->vm); | ||
349 | |||
350 | /* Load all inputs before writing any outputs, in case of overlap */ | ||
351 | - rn = neon_load_reg(a->vn, 0); | ||
352 | + rn = tcg_temp_new_i32(); | ||
353 | + read_neon_element32(rn, a->vn, 0, MO_32); | ||
354 | rn0_64 = tcg_temp_new_i64(); | ||
355 | opfn(rn0_64, rn, scalar); | ||
356 | - tcg_temp_free_i32(rn); | ||
357 | |||
358 | - rn = neon_load_reg(a->vn, 1); | ||
359 | + read_neon_element32(rn, a->vn, 1, MO_32); | ||
360 | rn1_64 = tcg_temp_new_i64(); | ||
361 | opfn(rn1_64, rn, scalar); | ||
362 | tcg_temp_free_i32(rn); | ||
363 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
364 | return false; | ||
365 | } | ||
366 | n <<= 3; | ||
367 | + tmp = tcg_temp_new_i32(); | ||
368 | if (a->op) { | ||
369 | - tmp = neon_load_reg(a->vd, 0); | ||
370 | + read_neon_element32(tmp, a->vd, 0, MO_32); | ||
371 | } else { | ||
372 | - tmp = tcg_temp_new_i32(); | ||
373 | tcg_gen_movi_i32(tmp, 0); | ||
374 | } | ||
375 | - tmp2 = neon_load_reg(a->vm, 0); | ||
376 | + tmp2 = tcg_temp_new_i32(); | ||
377 | + read_neon_element32(tmp2, a->vm, 0, MO_32); | ||
378 | ptr1 = vfp_reg_ptr(true, a->vn); | ||
379 | tmp4 = tcg_const_i32(n); | ||
380 | gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4); | ||
381 | - tcg_temp_free_i32(tmp); | ||
382 | + | ||
383 | if (a->op) { | ||
384 | - tmp = neon_load_reg(a->vd, 1); | ||
385 | + read_neon_element32(tmp, a->vd, 1, MO_32); | ||
386 | } else { | ||
387 | - tmp = tcg_temp_new_i32(); | ||
388 | tcg_gen_movi_i32(tmp, 0); | ||
389 | } | ||
390 | - tmp3 = neon_load_reg(a->vm, 1); | ||
391 | + tmp3 = tcg_temp_new_i32(); | ||
392 | + read_neon_element32(tmp3, a->vm, 1, MO_32); | ||
393 | gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4); | ||
394 | + tcg_temp_free_i32(tmp); | ||
395 | tcg_temp_free_i32(tmp4); | ||
396 | tcg_temp_free_ptr(ptr1); | ||
397 | - neon_store_reg(a->vd, 0, tmp2); | ||
398 | - neon_store_reg(a->vd, 1, tmp3); | ||
399 | - tcg_temp_free_i32(tmp); | ||
400 | + | ||
401 | + write_neon_element32(tmp2, a->vd, 0, MO_32); | ||
402 | + write_neon_element32(tmp3, a->vd, 1, MO_32); | ||
403 | + tcg_temp_free_i32(tmp2); | ||
404 | + tcg_temp_free_i32(tmp3); | ||
405 | return true; | ||
406 | } | ||
407 | |||
408 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a) | ||
409 | static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) | ||
410 | { | ||
411 | int pass, half; | ||
412 | + TCGv_i32 tmp[2]; | ||
413 | |||
414 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
415 | return false; | ||
416 | @@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) | ||
417 | return true; | ||
418 | } | ||
419 | |||
420 | - for (pass = 0; pass < (a->q ? 2 : 1); pass++) { | ||
421 | - TCGv_i32 tmp[2]; | ||
422 | + tmp[0] = tcg_temp_new_i32(); | ||
423 | + tmp[1] = tcg_temp_new_i32(); | ||
424 | |||
425 | + for (pass = 0; pass < (a->q ? 2 : 1); pass++) { | ||
426 | for (half = 0; half < 2; half++) { | ||
427 | - tmp[half] = neon_load_reg(a->vm, pass * 2 + half); | ||
428 | + read_neon_element32(tmp[half], a->vm, pass * 2 + half, MO_32); | ||
429 | switch (a->size) { | ||
430 | case 0: | ||
431 | tcg_gen_bswap32_i32(tmp[half], tmp[half]); | ||
432 | @@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) | ||
433 | g_assert_not_reached(); | ||
434 | } | ||
435 | } | ||
436 | - neon_store_reg(a->vd, pass * 2, tmp[1]); | ||
437 | - neon_store_reg(a->vd, pass * 2 + 1, tmp[0]); | ||
438 | + write_neon_element32(tmp[1], a->vd, pass * 2, MO_32); | ||
439 | + write_neon_element32(tmp[0], a->vd, pass * 2 + 1, MO_32); | ||
440 | } | ||
441 | + | ||
442 | + tcg_temp_free_i32(tmp[0]); | ||
443 | + tcg_temp_free_i32(tmp[1]); | ||
444 | return true; | ||
445 | } | ||
446 | |||
447 | @@ -XXX,XX +XXX,XX @@ static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a, | ||
448 | rm0_64 = tcg_temp_new_i64(); | ||
449 | rm1_64 = tcg_temp_new_i64(); | ||
450 | rd_64 = tcg_temp_new_i64(); | ||
451 | - tmp = neon_load_reg(a->vm, pass * 2); | ||
452 | + | ||
453 | + tmp = tcg_temp_new_i32(); | ||
454 | + read_neon_element32(tmp, a->vm, pass * 2, MO_32); | ||
455 | widenfn(rm0_64, tmp); | ||
456 | - tcg_temp_free_i32(tmp); | ||
457 | - tmp = neon_load_reg(a->vm, pass * 2 + 1); | ||
458 | + read_neon_element32(tmp, a->vm, pass * 2 + 1, MO_32); | ||
459 | widenfn(rm1_64, tmp); | ||
460 | tcg_temp_free_i32(tmp); | ||
461 | + | ||
462 | opfn(rd_64, rm0_64, rm1_64); | ||
463 | tcg_temp_free_i64(rm0_64); | ||
464 | tcg_temp_free_i64(rm1_64); | ||
465 | @@ -XXX,XX +XXX,XX @@ static bool do_vmovn(DisasContext *s, arg_2misc *a, | ||
466 | narrowfn(rd0, cpu_env, rm); | ||
467 | neon_load_reg64(rm, a->vm + 1); | ||
468 | narrowfn(rd1, cpu_env, rm); | ||
469 | - neon_store_reg(a->vd, 0, rd0); | ||
470 | - neon_store_reg(a->vd, 1, rd1); | ||
471 | + write_neon_element32(rd0, a->vd, 0, MO_32); | ||
472 | + write_neon_element32(rd1, a->vd, 1, MO_32); | ||
473 | + tcg_temp_free_i32(rd0); | ||
474 | + tcg_temp_free_i32(rd1); | ||
475 | tcg_temp_free_i64(rm); | ||
476 | return true; | ||
477 | } | ||
478 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a) | ||
479 | } | ||
480 | |||
481 | rd = tcg_temp_new_i64(); | ||
482 | + rm0 = tcg_temp_new_i32(); | ||
483 | + rm1 = tcg_temp_new_i32(); | ||
484 | |||
485 | - rm0 = neon_load_reg(a->vm, 0); | ||
486 | - rm1 = neon_load_reg(a->vm, 1); | ||
487 | + read_neon_element32(rm0, a->vm, 0, MO_32); | ||
488 | + read_neon_element32(rm1, a->vm, 1, MO_32); | ||
489 | |||
490 | widenfn(rd, rm0); | ||
491 | tcg_gen_shli_i64(rd, rd, 8 << a->size); | ||
492 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a) | ||
493 | |||
494 | fpst = fpstatus_ptr(FPST_STD); | ||
495 | ahp = get_ahp_flag(); | ||
496 | - tmp = neon_load_reg(a->vm, 0); | ||
497 | + tmp = tcg_temp_new_i32(); | ||
498 | + read_neon_element32(tmp, a->vm, 0, MO_32); | ||
499 | gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); | ||
500 | - tmp2 = neon_load_reg(a->vm, 1); | ||
501 | + tmp2 = tcg_temp_new_i32(); | ||
502 | + read_neon_element32(tmp2, a->vm, 1, MO_32); | ||
503 | gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp); | ||
504 | tcg_gen_shli_i32(tmp2, tmp2, 16); | ||
505 | tcg_gen_or_i32(tmp2, tmp2, tmp); | ||
506 | - tcg_temp_free_i32(tmp); | ||
507 | - tmp = neon_load_reg(a->vm, 2); | ||
508 | + read_neon_element32(tmp, a->vm, 2, MO_32); | ||
509 | gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); | ||
510 | - tmp3 = neon_load_reg(a->vm, 3); | ||
511 | - neon_store_reg(a->vd, 0, tmp2); | ||
512 | + tmp3 = tcg_temp_new_i32(); | ||
513 | + read_neon_element32(tmp3, a->vm, 3, MO_32); | ||
514 | + write_neon_element32(tmp2, a->vd, 0, MO_32); | ||
515 | + tcg_temp_free_i32(tmp2); | ||
516 | gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp); | ||
517 | tcg_gen_shli_i32(tmp3, tmp3, 16); | ||
518 | tcg_gen_or_i32(tmp3, tmp3, tmp); | ||
519 | - neon_store_reg(a->vd, 1, tmp3); | ||
520 | + write_neon_element32(tmp3, a->vd, 1, MO_32); | ||
521 | + tcg_temp_free_i32(tmp3); | ||
522 | tcg_temp_free_i32(tmp); | ||
523 | tcg_temp_free_i32(ahp); | ||
524 | tcg_temp_free_ptr(fpst); | ||
525 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a) | ||
526 | fpst = fpstatus_ptr(FPST_STD); | ||
527 | ahp = get_ahp_flag(); | ||
528 | tmp3 = tcg_temp_new_i32(); | ||
529 | - tmp = neon_load_reg(a->vm, 0); | ||
530 | - tmp2 = neon_load_reg(a->vm, 1); | ||
531 | + tmp2 = tcg_temp_new_i32(); | ||
532 | + tmp = tcg_temp_new_i32(); | ||
533 | + read_neon_element32(tmp, a->vm, 0, MO_32); | ||
534 | + read_neon_element32(tmp2, a->vm, 1, MO_32); | ||
535 | tcg_gen_ext16u_i32(tmp3, tmp); | ||
536 | gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); | ||
537 | - neon_store_reg(a->vd, 0, tmp3); | ||
538 | + write_neon_element32(tmp3, a->vd, 0, MO_32); | ||
539 | tcg_gen_shri_i32(tmp, tmp, 16); | ||
540 | gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp); | ||
541 | - neon_store_reg(a->vd, 1, tmp); | ||
542 | - tmp3 = tcg_temp_new_i32(); | ||
543 | + write_neon_element32(tmp, a->vd, 1, MO_32); | ||
544 | + tcg_temp_free_i32(tmp); | ||
545 | tcg_gen_ext16u_i32(tmp3, tmp2); | ||
546 | gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); | ||
547 | - neon_store_reg(a->vd, 2, tmp3); | ||
548 | + write_neon_element32(tmp3, a->vd, 2, MO_32); | ||
549 | + tcg_temp_free_i32(tmp3); | ||
550 | tcg_gen_shri_i32(tmp2, tmp2, 16); | ||
551 | gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp); | ||
552 | - neon_store_reg(a->vd, 3, tmp2); | ||
553 | + write_neon_element32(tmp2, a->vd, 3, MO_32); | ||
554 | + tcg_temp_free_i32(tmp2); | ||
555 | tcg_temp_free_i32(ahp); | ||
556 | tcg_temp_free_ptr(fpst); | ||
557 | |||
558 | @@ -XXX,XX +XXX,XX @@ DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2) | ||
559 | |||
560 | static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn) | ||
561 | { | ||
562 | + TCGv_i32 tmp; | ||
563 | int pass; | ||
564 | |||
565 | /* Handle a 2-reg-misc operation by iterating 32 bits at a time */ | ||
566 | @@ -XXX,XX +XXX,XX @@ static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn) | ||
567 | return true; | ||
568 | } | ||
569 | |||
570 | + tmp = tcg_temp_new_i32(); | ||
571 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
572 | - TCGv_i32 tmp = neon_load_reg(a->vm, pass); | ||
573 | + read_neon_element32(tmp, a->vm, pass, MO_32); | ||
574 | fn(tmp, tmp); | ||
575 | - neon_store_reg(a->vd, pass, tmp); | ||
576 | + write_neon_element32(tmp, a->vd, pass, MO_32); | ||
577 | } | ||
578 | + tcg_temp_free_i32(tmp); | ||
579 | |||
580 | return true; | ||
581 | } | ||
582 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTRN(DisasContext *s, arg_2misc *a) | ||
583 | return true; | ||
584 | } | ||
585 | |||
586 | - if (a->size == 2) { | ||
587 | + tmp = tcg_temp_new_i32(); | ||
588 | + tmp2 = tcg_temp_new_i32(); | ||
589 | + if (a->size == MO_32) { | ||
590 | for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) { | ||
591 | - tmp = neon_load_reg(a->vm, pass); | ||
592 | - tmp2 = neon_load_reg(a->vd, pass + 1); | ||
593 | - neon_store_reg(a->vm, pass, tmp2); | ||
594 | - neon_store_reg(a->vd, pass + 1, tmp); | ||
595 | + read_neon_element32(tmp, a->vm, pass, MO_32); | ||
596 | + read_neon_element32(tmp2, a->vd, pass + 1, MO_32); | ||
597 | + write_neon_element32(tmp2, a->vm, pass, MO_32); | ||
598 | + write_neon_element32(tmp, a->vd, pass + 1, MO_32); | ||
599 | } | ||
600 | } else { | ||
601 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
602 | - tmp = neon_load_reg(a->vm, pass); | ||
603 | - tmp2 = neon_load_reg(a->vd, pass); | ||
604 | - if (a->size == 0) { | ||
605 | + read_neon_element32(tmp, a->vm, pass, MO_32); | ||
606 | + read_neon_element32(tmp2, a->vd, pass, MO_32); | ||
607 | + if (a->size == MO_8) { | ||
608 | gen_neon_trn_u8(tmp, tmp2); | ||
609 | } else { | ||
610 | gen_neon_trn_u16(tmp, tmp2); | ||
611 | } | ||
612 | - neon_store_reg(a->vm, pass, tmp2); | ||
613 | - neon_store_reg(a->vd, pass, tmp); | ||
614 | + write_neon_element32(tmp2, a->vm, pass, MO_32); | ||
615 | + write_neon_element32(tmp, a->vd, pass, MO_32); | ||
616 | } | ||
617 | } | ||
618 | + tcg_temp_free_i32(tmp); | ||
619 | + tcg_temp_free_i32(tmp2); | ||
620 | return true; | ||
621 | } | ||
475 | -- | 622 | -- |
476 | 2.20.1 | 623 | 2.20.1 |
477 | 624 | ||
478 | 625 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Because the elements are non-sequential, we cannot eliminate many | 3 | We can then use this to improve VMOV (scalar to gp) and |
4 | tests straight away like we can for sequential operations. But | 4 | VMOV (gp to scalar) so that we simply perform the memory |
5 | we often have the PTE details handy, so we can test for Tagged. | 5 | operation that we wanted, rather than inserting or |
6 | 6 | extracting from a 32-bit quantity. | |
7 | |||
8 | These were the last uses of neon_load/store_reg, so remove them. | ||
9 | |||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20201030022618.785675-7-richard.henderson@linaro.org | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20200626033144.790098-38-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 14 | --- |
12 | target/arm/helper-sve.h | 285 ++++++++++++++++ | 15 | target/arm/translate.c | 50 +++++++++++++----------- |
13 | target/arm/sve_helper.c | 185 +++++++++-- | 16 | target/arm/translate-vfp.c.inc | 71 +++++----------------------------- |
14 | target/arm/translate-sve.c | 650 +++++++++++++++++++++++++------------ | 17 | 2 files changed, 37 insertions(+), 84 deletions(-) |
15 | 3 files changed, 872 insertions(+), 248 deletions(-) | 18 | |
16 | 19 | diff --git a/target/arm/translate.c b/target/arm/translate.c | |
17 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/helper-sve.h | 21 | --- a/target/arm/translate.c |
20 | +++ b/target/arm/helper-sve.h | 22 | +++ b/target/arm/translate.c |
21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_6(sve_ldsds_le_zd, TCG_CALL_NO_WG, | 23 | @@ -XXX,XX +XXX,XX @@ static long neon_full_reg_offset(unsigned reg) |
22 | DEF_HELPER_FLAGS_6(sve_ldsds_be_zd, TCG_CALL_NO_WG, | 24 | * Return the offset of a 2**SIZE piece of a NEON register, at index ELE, |
23 | void, env, ptr, ptr, ptr, tl, i32) | 25 | * where 0 is the least significant end of the register. |
24 | |||
25 | +DEF_HELPER_FLAGS_6(sve_ldbsu_zsu_mte, TCG_CALL_NO_WG, | ||
26 | + void, env, ptr, ptr, ptr, tl, i32) | ||
27 | +DEF_HELPER_FLAGS_6(sve_ldhsu_le_zsu_mte, TCG_CALL_NO_WG, | ||
28 | + void, env, ptr, ptr, ptr, tl, i32) | ||
29 | +DEF_HELPER_FLAGS_6(sve_ldhsu_be_zsu_mte, TCG_CALL_NO_WG, | ||
30 | + void, env, ptr, ptr, ptr, tl, i32) | ||
31 | +DEF_HELPER_FLAGS_6(sve_ldss_le_zsu_mte, TCG_CALL_NO_WG, | ||
32 | + void, env, ptr, ptr, ptr, tl, i32) | ||
33 | +DEF_HELPER_FLAGS_6(sve_ldss_be_zsu_mte, TCG_CALL_NO_WG, | ||
34 | + void, env, ptr, ptr, ptr, tl, i32) | ||
35 | +DEF_HELPER_FLAGS_6(sve_ldbss_zsu_mte, TCG_CALL_NO_WG, | ||
36 | + void, env, ptr, ptr, ptr, tl, i32) | ||
37 | +DEF_HELPER_FLAGS_6(sve_ldhss_le_zsu_mte, TCG_CALL_NO_WG, | ||
38 | + void, env, ptr, ptr, ptr, tl, i32) | ||
39 | +DEF_HELPER_FLAGS_6(sve_ldhss_be_zsu_mte, TCG_CALL_NO_WG, | ||
40 | + void, env, ptr, ptr, ptr, tl, i32) | ||
41 | + | ||
42 | +DEF_HELPER_FLAGS_6(sve_ldbsu_zss_mte, TCG_CALL_NO_WG, | ||
43 | + void, env, ptr, ptr, ptr, tl, i32) | ||
44 | +DEF_HELPER_FLAGS_6(sve_ldhsu_le_zss_mte, TCG_CALL_NO_WG, | ||
45 | + void, env, ptr, ptr, ptr, tl, i32) | ||
46 | +DEF_HELPER_FLAGS_6(sve_ldhsu_be_zss_mte, TCG_CALL_NO_WG, | ||
47 | + void, env, ptr, ptr, ptr, tl, i32) | ||
48 | +DEF_HELPER_FLAGS_6(sve_ldss_le_zss_mte, TCG_CALL_NO_WG, | ||
49 | + void, env, ptr, ptr, ptr, tl, i32) | ||
50 | +DEF_HELPER_FLAGS_6(sve_ldss_be_zss_mte, TCG_CALL_NO_WG, | ||
51 | + void, env, ptr, ptr, ptr, tl, i32) | ||
52 | +DEF_HELPER_FLAGS_6(sve_ldbss_zss_mte, TCG_CALL_NO_WG, | ||
53 | + void, env, ptr, ptr, ptr, tl, i32) | ||
54 | +DEF_HELPER_FLAGS_6(sve_ldhss_le_zss_mte, TCG_CALL_NO_WG, | ||
55 | + void, env, ptr, ptr, ptr, tl, i32) | ||
56 | +DEF_HELPER_FLAGS_6(sve_ldhss_be_zss_mte, TCG_CALL_NO_WG, | ||
57 | + void, env, ptr, ptr, ptr, tl, i32) | ||
58 | + | ||
59 | +DEF_HELPER_FLAGS_6(sve_ldbdu_zsu_mte, TCG_CALL_NO_WG, | ||
60 | + void, env, ptr, ptr, ptr, tl, i32) | ||
61 | +DEF_HELPER_FLAGS_6(sve_ldhdu_le_zsu_mte, TCG_CALL_NO_WG, | ||
62 | + void, env, ptr, ptr, ptr, tl, i32) | ||
63 | +DEF_HELPER_FLAGS_6(sve_ldhdu_be_zsu_mte, TCG_CALL_NO_WG, | ||
64 | + void, env, ptr, ptr, ptr, tl, i32) | ||
65 | +DEF_HELPER_FLAGS_6(sve_ldsdu_le_zsu_mte, TCG_CALL_NO_WG, | ||
66 | + void, env, ptr, ptr, ptr, tl, i32) | ||
67 | +DEF_HELPER_FLAGS_6(sve_ldsdu_be_zsu_mte, TCG_CALL_NO_WG, | ||
68 | + void, env, ptr, ptr, ptr, tl, i32) | ||
69 | +DEF_HELPER_FLAGS_6(sve_lddd_le_zsu_mte, TCG_CALL_NO_WG, | ||
70 | + void, env, ptr, ptr, ptr, tl, i32) | ||
71 | +DEF_HELPER_FLAGS_6(sve_lddd_be_zsu_mte, TCG_CALL_NO_WG, | ||
72 | + void, env, ptr, ptr, ptr, tl, i32) | ||
73 | +DEF_HELPER_FLAGS_6(sve_ldbds_zsu_mte, TCG_CALL_NO_WG, | ||
74 | + void, env, ptr, ptr, ptr, tl, i32) | ||
75 | +DEF_HELPER_FLAGS_6(sve_ldhds_le_zsu_mte, TCG_CALL_NO_WG, | ||
76 | + void, env, ptr, ptr, ptr, tl, i32) | ||
77 | +DEF_HELPER_FLAGS_6(sve_ldhds_be_zsu_mte, TCG_CALL_NO_WG, | ||
78 | + void, env, ptr, ptr, ptr, tl, i32) | ||
79 | +DEF_HELPER_FLAGS_6(sve_ldsds_le_zsu_mte, TCG_CALL_NO_WG, | ||
80 | + void, env, ptr, ptr, ptr, tl, i32) | ||
81 | +DEF_HELPER_FLAGS_6(sve_ldsds_be_zsu_mte, TCG_CALL_NO_WG, | ||
82 | + void, env, ptr, ptr, ptr, tl, i32) | ||
83 | + | ||
84 | +DEF_HELPER_FLAGS_6(sve_ldbdu_zss_mte, TCG_CALL_NO_WG, | ||
85 | + void, env, ptr, ptr, ptr, tl, i32) | ||
86 | +DEF_HELPER_FLAGS_6(sve_ldhdu_le_zss_mte, TCG_CALL_NO_WG, | ||
87 | + void, env, ptr, ptr, ptr, tl, i32) | ||
88 | +DEF_HELPER_FLAGS_6(sve_ldhdu_be_zss_mte, TCG_CALL_NO_WG, | ||
89 | + void, env, ptr, ptr, ptr, tl, i32) | ||
90 | +DEF_HELPER_FLAGS_6(sve_ldsdu_le_zss_mte, TCG_CALL_NO_WG, | ||
91 | + void, env, ptr, ptr, ptr, tl, i32) | ||
92 | +DEF_HELPER_FLAGS_6(sve_ldsdu_be_zss_mte, TCG_CALL_NO_WG, | ||
93 | + void, env, ptr, ptr, ptr, tl, i32) | ||
94 | +DEF_HELPER_FLAGS_6(sve_lddd_le_zss_mte, TCG_CALL_NO_WG, | ||
95 | + void, env, ptr, ptr, ptr, tl, i32) | ||
96 | +DEF_HELPER_FLAGS_6(sve_lddd_be_zss_mte, TCG_CALL_NO_WG, | ||
97 | + void, env, ptr, ptr, ptr, tl, i32) | ||
98 | +DEF_HELPER_FLAGS_6(sve_ldbds_zss_mte, TCG_CALL_NO_WG, | ||
99 | + void, env, ptr, ptr, ptr, tl, i32) | ||
100 | +DEF_HELPER_FLAGS_6(sve_ldhds_le_zss_mte, TCG_CALL_NO_WG, | ||
101 | + void, env, ptr, ptr, ptr, tl, i32) | ||
102 | +DEF_HELPER_FLAGS_6(sve_ldhds_be_zss_mte, TCG_CALL_NO_WG, | ||
103 | + void, env, ptr, ptr, ptr, tl, i32) | ||
104 | +DEF_HELPER_FLAGS_6(sve_ldsds_le_zss_mte, TCG_CALL_NO_WG, | ||
105 | + void, env, ptr, ptr, ptr, tl, i32) | ||
106 | +DEF_HELPER_FLAGS_6(sve_ldsds_be_zss_mte, TCG_CALL_NO_WG, | ||
107 | + void, env, ptr, ptr, ptr, tl, i32) | ||
108 | + | ||
109 | +DEF_HELPER_FLAGS_6(sve_ldbdu_zd_mte, TCG_CALL_NO_WG, | ||
110 | + void, env, ptr, ptr, ptr, tl, i32) | ||
111 | +DEF_HELPER_FLAGS_6(sve_ldhdu_le_zd_mte, TCG_CALL_NO_WG, | ||
112 | + void, env, ptr, ptr, ptr, tl, i32) | ||
113 | +DEF_HELPER_FLAGS_6(sve_ldhdu_be_zd_mte, TCG_CALL_NO_WG, | ||
114 | + void, env, ptr, ptr, ptr, tl, i32) | ||
115 | +DEF_HELPER_FLAGS_6(sve_ldsdu_le_zd_mte, TCG_CALL_NO_WG, | ||
116 | + void, env, ptr, ptr, ptr, tl, i32) | ||
117 | +DEF_HELPER_FLAGS_6(sve_ldsdu_be_zd_mte, TCG_CALL_NO_WG, | ||
118 | + void, env, ptr, ptr, ptr, tl, i32) | ||
119 | +DEF_HELPER_FLAGS_6(sve_lddd_le_zd_mte, TCG_CALL_NO_WG, | ||
120 | + void, env, ptr, ptr, ptr, tl, i32) | ||
121 | +DEF_HELPER_FLAGS_6(sve_lddd_be_zd_mte, TCG_CALL_NO_WG, | ||
122 | + void, env, ptr, ptr, ptr, tl, i32) | ||
123 | +DEF_HELPER_FLAGS_6(sve_ldbds_zd_mte, TCG_CALL_NO_WG, | ||
124 | + void, env, ptr, ptr, ptr, tl, i32) | ||
125 | +DEF_HELPER_FLAGS_6(sve_ldhds_le_zd_mte, TCG_CALL_NO_WG, | ||
126 | + void, env, ptr, ptr, ptr, tl, i32) | ||
127 | +DEF_HELPER_FLAGS_6(sve_ldhds_be_zd_mte, TCG_CALL_NO_WG, | ||
128 | + void, env, ptr, ptr, ptr, tl, i32) | ||
129 | +DEF_HELPER_FLAGS_6(sve_ldsds_le_zd_mte, TCG_CALL_NO_WG, | ||
130 | + void, env, ptr, ptr, ptr, tl, i32) | ||
131 | +DEF_HELPER_FLAGS_6(sve_ldsds_be_zd_mte, TCG_CALL_NO_WG, | ||
132 | + void, env, ptr, ptr, ptr, tl, i32) | ||
133 | + | ||
134 | DEF_HELPER_FLAGS_6(sve_ldffbsu_zsu, TCG_CALL_NO_WG, | ||
135 | void, env, ptr, ptr, ptr, tl, i32) | ||
136 | DEF_HELPER_FLAGS_6(sve_ldffhsu_le_zsu, TCG_CALL_NO_WG, | ||
137 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_6(sve_ldffsds_le_zd, TCG_CALL_NO_WG, | ||
138 | DEF_HELPER_FLAGS_6(sve_ldffsds_be_zd, TCG_CALL_NO_WG, | ||
139 | void, env, ptr, ptr, ptr, tl, i32) | ||
140 | |||
141 | +DEF_HELPER_FLAGS_6(sve_ldffbsu_zsu_mte, TCG_CALL_NO_WG, | ||
142 | + void, env, ptr, ptr, ptr, tl, i32) | ||
143 | +DEF_HELPER_FLAGS_6(sve_ldffhsu_le_zsu_mte, TCG_CALL_NO_WG, | ||
144 | + void, env, ptr, ptr, ptr, tl, i32) | ||
145 | +DEF_HELPER_FLAGS_6(sve_ldffhsu_be_zsu_mte, TCG_CALL_NO_WG, | ||
146 | + void, env, ptr, ptr, ptr, tl, i32) | ||
147 | +DEF_HELPER_FLAGS_6(sve_ldffss_le_zsu_mte, TCG_CALL_NO_WG, | ||
148 | + void, env, ptr, ptr, ptr, tl, i32) | ||
149 | +DEF_HELPER_FLAGS_6(sve_ldffss_be_zsu_mte, TCG_CALL_NO_WG, | ||
150 | + void, env, ptr, ptr, ptr, tl, i32) | ||
151 | +DEF_HELPER_FLAGS_6(sve_ldffbss_zsu_mte, TCG_CALL_NO_WG, | ||
152 | + void, env, ptr, ptr, ptr, tl, i32) | ||
153 | +DEF_HELPER_FLAGS_6(sve_ldffhss_le_zsu_mte, TCG_CALL_NO_WG, | ||
154 | + void, env, ptr, ptr, ptr, tl, i32) | ||
155 | +DEF_HELPER_FLAGS_6(sve_ldffhss_be_zsu_mte, TCG_CALL_NO_WG, | ||
156 | + void, env, ptr, ptr, ptr, tl, i32) | ||
157 | + | ||
158 | +DEF_HELPER_FLAGS_6(sve_ldffbsu_zss_mte, TCG_CALL_NO_WG, | ||
159 | + void, env, ptr, ptr, ptr, tl, i32) | ||
160 | +DEF_HELPER_FLAGS_6(sve_ldffhsu_le_zss_mte, TCG_CALL_NO_WG, | ||
161 | + void, env, ptr, ptr, ptr, tl, i32) | ||
162 | +DEF_HELPER_FLAGS_6(sve_ldffhsu_be_zss_mte, TCG_CALL_NO_WG, | ||
163 | + void, env, ptr, ptr, ptr, tl, i32) | ||
164 | +DEF_HELPER_FLAGS_6(sve_ldffss_le_zss_mte, TCG_CALL_NO_WG, | ||
165 | + void, env, ptr, ptr, ptr, tl, i32) | ||
166 | +DEF_HELPER_FLAGS_6(sve_ldffss_be_zss_mte, TCG_CALL_NO_WG, | ||
167 | + void, env, ptr, ptr, ptr, tl, i32) | ||
168 | +DEF_HELPER_FLAGS_6(sve_ldffbss_zss_mte, TCG_CALL_NO_WG, | ||
169 | + void, env, ptr, ptr, ptr, tl, i32) | ||
170 | +DEF_HELPER_FLAGS_6(sve_ldffhss_le_zss_mte, TCG_CALL_NO_WG, | ||
171 | + void, env, ptr, ptr, ptr, tl, i32) | ||
172 | +DEF_HELPER_FLAGS_6(sve_ldffhss_be_zss_mte, TCG_CALL_NO_WG, | ||
173 | + void, env, ptr, ptr, ptr, tl, i32) | ||
174 | + | ||
175 | +DEF_HELPER_FLAGS_6(sve_ldffbdu_zsu_mte, TCG_CALL_NO_WG, | ||
176 | + void, env, ptr, ptr, ptr, tl, i32) | ||
177 | +DEF_HELPER_FLAGS_6(sve_ldffhdu_le_zsu_mte, TCG_CALL_NO_WG, | ||
178 | + void, env, ptr, ptr, ptr, tl, i32) | ||
179 | +DEF_HELPER_FLAGS_6(sve_ldffhdu_be_zsu_mte, TCG_CALL_NO_WG, | ||
180 | + void, env, ptr, ptr, ptr, tl, i32) | ||
181 | +DEF_HELPER_FLAGS_6(sve_ldffsdu_le_zsu_mte, TCG_CALL_NO_WG, | ||
182 | + void, env, ptr, ptr, ptr, tl, i32) | ||
183 | +DEF_HELPER_FLAGS_6(sve_ldffsdu_be_zsu_mte, TCG_CALL_NO_WG, | ||
184 | + void, env, ptr, ptr, ptr, tl, i32) | ||
185 | +DEF_HELPER_FLAGS_6(sve_ldffdd_le_zsu_mte, TCG_CALL_NO_WG, | ||
186 | + void, env, ptr, ptr, ptr, tl, i32) | ||
187 | +DEF_HELPER_FLAGS_6(sve_ldffdd_be_zsu_mte, TCG_CALL_NO_WG, | ||
188 | + void, env, ptr, ptr, ptr, tl, i32) | ||
189 | +DEF_HELPER_FLAGS_6(sve_ldffbds_zsu_mte, TCG_CALL_NO_WG, | ||
190 | + void, env, ptr, ptr, ptr, tl, i32) | ||
191 | +DEF_HELPER_FLAGS_6(sve_ldffhds_le_zsu_mte, TCG_CALL_NO_WG, | ||
192 | + void, env, ptr, ptr, ptr, tl, i32) | ||
193 | +DEF_HELPER_FLAGS_6(sve_ldffhds_be_zsu_mte, TCG_CALL_NO_WG, | ||
194 | + void, env, ptr, ptr, ptr, tl, i32) | ||
195 | +DEF_HELPER_FLAGS_6(sve_ldffsds_le_zsu_mte, TCG_CALL_NO_WG, | ||
196 | + void, env, ptr, ptr, ptr, tl, i32) | ||
197 | +DEF_HELPER_FLAGS_6(sve_ldffsds_be_zsu_mte, TCG_CALL_NO_WG, | ||
198 | + void, env, ptr, ptr, ptr, tl, i32) | ||
199 | + | ||
200 | +DEF_HELPER_FLAGS_6(sve_ldffbdu_zss_mte, TCG_CALL_NO_WG, | ||
201 | + void, env, ptr, ptr, ptr, tl, i32) | ||
202 | +DEF_HELPER_FLAGS_6(sve_ldffhdu_le_zss_mte, TCG_CALL_NO_WG, | ||
203 | + void, env, ptr, ptr, ptr, tl, i32) | ||
204 | +DEF_HELPER_FLAGS_6(sve_ldffhdu_be_zss_mte, TCG_CALL_NO_WG, | ||
205 | + void, env, ptr, ptr, ptr, tl, i32) | ||
206 | +DEF_HELPER_FLAGS_6(sve_ldffsdu_le_zss_mte, TCG_CALL_NO_WG, | ||
207 | + void, env, ptr, ptr, ptr, tl, i32) | ||
208 | +DEF_HELPER_FLAGS_6(sve_ldffsdu_be_zss_mte, TCG_CALL_NO_WG, | ||
209 | + void, env, ptr, ptr, ptr, tl, i32) | ||
210 | +DEF_HELPER_FLAGS_6(sve_ldffdd_le_zss_mte, TCG_CALL_NO_WG, | ||
211 | + void, env, ptr, ptr, ptr, tl, i32) | ||
212 | +DEF_HELPER_FLAGS_6(sve_ldffdd_be_zss_mte, TCG_CALL_NO_WG, | ||
213 | + void, env, ptr, ptr, ptr, tl, i32) | ||
214 | +DEF_HELPER_FLAGS_6(sve_ldffbds_zss_mte, TCG_CALL_NO_WG, | ||
215 | + void, env, ptr, ptr, ptr, tl, i32) | ||
216 | +DEF_HELPER_FLAGS_6(sve_ldffhds_le_zss_mte, TCG_CALL_NO_WG, | ||
217 | + void, env, ptr, ptr, ptr, tl, i32) | ||
218 | +DEF_HELPER_FLAGS_6(sve_ldffhds_be_zss_mte, TCG_CALL_NO_WG, | ||
219 | + void, env, ptr, ptr, ptr, tl, i32) | ||
220 | +DEF_HELPER_FLAGS_6(sve_ldffsds_le_zss_mte, TCG_CALL_NO_WG, | ||
221 | + void, env, ptr, ptr, ptr, tl, i32) | ||
222 | +DEF_HELPER_FLAGS_6(sve_ldffsds_be_zss_mte, TCG_CALL_NO_WG, | ||
223 | + void, env, ptr, ptr, ptr, tl, i32) | ||
224 | + | ||
225 | +DEF_HELPER_FLAGS_6(sve_ldffbdu_zd_mte, TCG_CALL_NO_WG, | ||
226 | + void, env, ptr, ptr, ptr, tl, i32) | ||
227 | +DEF_HELPER_FLAGS_6(sve_ldffhdu_le_zd_mte, TCG_CALL_NO_WG, | ||
228 | + void, env, ptr, ptr, ptr, tl, i32) | ||
229 | +DEF_HELPER_FLAGS_6(sve_ldffhdu_be_zd_mte, TCG_CALL_NO_WG, | ||
230 | + void, env, ptr, ptr, ptr, tl, i32) | ||
231 | +DEF_HELPER_FLAGS_6(sve_ldffsdu_le_zd_mte, TCG_CALL_NO_WG, | ||
232 | + void, env, ptr, ptr, ptr, tl, i32) | ||
233 | +DEF_HELPER_FLAGS_6(sve_ldffsdu_be_zd_mte, TCG_CALL_NO_WG, | ||
234 | + void, env, ptr, ptr, ptr, tl, i32) | ||
235 | +DEF_HELPER_FLAGS_6(sve_ldffdd_le_zd_mte, TCG_CALL_NO_WG, | ||
236 | + void, env, ptr, ptr, ptr, tl, i32) | ||
237 | +DEF_HELPER_FLAGS_6(sve_ldffdd_be_zd_mte, TCG_CALL_NO_WG, | ||
238 | + void, env, ptr, ptr, ptr, tl, i32) | ||
239 | +DEF_HELPER_FLAGS_6(sve_ldffbds_zd_mte, TCG_CALL_NO_WG, | ||
240 | + void, env, ptr, ptr, ptr, tl, i32) | ||
241 | +DEF_HELPER_FLAGS_6(sve_ldffhds_le_zd_mte, TCG_CALL_NO_WG, | ||
242 | + void, env, ptr, ptr, ptr, tl, i32) | ||
243 | +DEF_HELPER_FLAGS_6(sve_ldffhds_be_zd_mte, TCG_CALL_NO_WG, | ||
244 | + void, env, ptr, ptr, ptr, tl, i32) | ||
245 | +DEF_HELPER_FLAGS_6(sve_ldffsds_le_zd_mte, TCG_CALL_NO_WG, | ||
246 | + void, env, ptr, ptr, ptr, tl, i32) | ||
247 | +DEF_HELPER_FLAGS_6(sve_ldffsds_be_zd_mte, TCG_CALL_NO_WG, | ||
248 | + void, env, ptr, ptr, ptr, tl, i32) | ||
249 | + | ||
250 | DEF_HELPER_FLAGS_6(sve_stbs_zsu, TCG_CALL_NO_WG, | ||
251 | void, env, ptr, ptr, ptr, tl, i32) | ||
252 | DEF_HELPER_FLAGS_6(sve_sths_le_zsu, TCG_CALL_NO_WG, | ||
253 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_6(sve_stdd_le_zd, TCG_CALL_NO_WG, | ||
254 | DEF_HELPER_FLAGS_6(sve_stdd_be_zd, TCG_CALL_NO_WG, | ||
255 | void, env, ptr, ptr, ptr, tl, i32) | ||
256 | |||
257 | +DEF_HELPER_FLAGS_6(sve_stbs_zsu_mte, TCG_CALL_NO_WG, | ||
258 | + void, env, ptr, ptr, ptr, tl, i32) | ||
259 | +DEF_HELPER_FLAGS_6(sve_sths_le_zsu_mte, TCG_CALL_NO_WG, | ||
260 | + void, env, ptr, ptr, ptr, tl, i32) | ||
261 | +DEF_HELPER_FLAGS_6(sve_sths_be_zsu_mte, TCG_CALL_NO_WG, | ||
262 | + void, env, ptr, ptr, ptr, tl, i32) | ||
263 | +DEF_HELPER_FLAGS_6(sve_stss_le_zsu_mte, TCG_CALL_NO_WG, | ||
264 | + void, env, ptr, ptr, ptr, tl, i32) | ||
265 | +DEF_HELPER_FLAGS_6(sve_stss_be_zsu_mte, TCG_CALL_NO_WG, | ||
266 | + void, env, ptr, ptr, ptr, tl, i32) | ||
267 | + | ||
268 | +DEF_HELPER_FLAGS_6(sve_stbs_zss_mte, TCG_CALL_NO_WG, | ||
269 | + void, env, ptr, ptr, ptr, tl, i32) | ||
270 | +DEF_HELPER_FLAGS_6(sve_sths_le_zss_mte, TCG_CALL_NO_WG, | ||
271 | + void, env, ptr, ptr, ptr, tl, i32) | ||
272 | +DEF_HELPER_FLAGS_6(sve_sths_be_zss_mte, TCG_CALL_NO_WG, | ||
273 | + void, env, ptr, ptr, ptr, tl, i32) | ||
274 | +DEF_HELPER_FLAGS_6(sve_stss_le_zss_mte, TCG_CALL_NO_WG, | ||
275 | + void, env, ptr, ptr, ptr, tl, i32) | ||
276 | +DEF_HELPER_FLAGS_6(sve_stss_be_zss_mte, TCG_CALL_NO_WG, | ||
277 | + void, env, ptr, ptr, ptr, tl, i32) | ||
278 | + | ||
279 | +DEF_HELPER_FLAGS_6(sve_stbd_zsu_mte, TCG_CALL_NO_WG, | ||
280 | + void, env, ptr, ptr, ptr, tl, i32) | ||
281 | +DEF_HELPER_FLAGS_6(sve_sthd_le_zsu_mte, TCG_CALL_NO_WG, | ||
282 | + void, env, ptr, ptr, ptr, tl, i32) | ||
283 | +DEF_HELPER_FLAGS_6(sve_sthd_be_zsu_mte, TCG_CALL_NO_WG, | ||
284 | + void, env, ptr, ptr, ptr, tl, i32) | ||
285 | +DEF_HELPER_FLAGS_6(sve_stsd_le_zsu_mte, TCG_CALL_NO_WG, | ||
286 | + void, env, ptr, ptr, ptr, tl, i32) | ||
287 | +DEF_HELPER_FLAGS_6(sve_stsd_be_zsu_mte, TCG_CALL_NO_WG, | ||
288 | + void, env, ptr, ptr, ptr, tl, i32) | ||
289 | +DEF_HELPER_FLAGS_6(sve_stdd_le_zsu_mte, TCG_CALL_NO_WG, | ||
290 | + void, env, ptr, ptr, ptr, tl, i32) | ||
291 | +DEF_HELPER_FLAGS_6(sve_stdd_be_zsu_mte, TCG_CALL_NO_WG, | ||
292 | + void, env, ptr, ptr, ptr, tl, i32) | ||
293 | + | ||
294 | +DEF_HELPER_FLAGS_6(sve_stbd_zss_mte, TCG_CALL_NO_WG, | ||
295 | + void, env, ptr, ptr, ptr, tl, i32) | ||
296 | +DEF_HELPER_FLAGS_6(sve_sthd_le_zss_mte, TCG_CALL_NO_WG, | ||
297 | + void, env, ptr, ptr, ptr, tl, i32) | ||
298 | +DEF_HELPER_FLAGS_6(sve_sthd_be_zss_mte, TCG_CALL_NO_WG, | ||
299 | + void, env, ptr, ptr, ptr, tl, i32) | ||
300 | +DEF_HELPER_FLAGS_6(sve_stsd_le_zss_mte, TCG_CALL_NO_WG, | ||
301 | + void, env, ptr, ptr, ptr, tl, i32) | ||
302 | +DEF_HELPER_FLAGS_6(sve_stsd_be_zss_mte, TCG_CALL_NO_WG, | ||
303 | + void, env, ptr, ptr, ptr, tl, i32) | ||
304 | +DEF_HELPER_FLAGS_6(sve_stdd_le_zss_mte, TCG_CALL_NO_WG, | ||
305 | + void, env, ptr, ptr, ptr, tl, i32) | ||
306 | +DEF_HELPER_FLAGS_6(sve_stdd_be_zss_mte, TCG_CALL_NO_WG, | ||
307 | + void, env, ptr, ptr, ptr, tl, i32) | ||
308 | + | ||
309 | +DEF_HELPER_FLAGS_6(sve_stbd_zd_mte, TCG_CALL_NO_WG, | ||
310 | + void, env, ptr, ptr, ptr, tl, i32) | ||
311 | +DEF_HELPER_FLAGS_6(sve_sthd_le_zd_mte, TCG_CALL_NO_WG, | ||
312 | + void, env, ptr, ptr, ptr, tl, i32) | ||
313 | +DEF_HELPER_FLAGS_6(sve_sthd_be_zd_mte, TCG_CALL_NO_WG, | ||
314 | + void, env, ptr, ptr, ptr, tl, i32) | ||
315 | +DEF_HELPER_FLAGS_6(sve_stsd_le_zd_mte, TCG_CALL_NO_WG, | ||
316 | + void, env, ptr, ptr, ptr, tl, i32) | ||
317 | +DEF_HELPER_FLAGS_6(sve_stsd_be_zd_mte, TCG_CALL_NO_WG, | ||
318 | + void, env, ptr, ptr, ptr, tl, i32) | ||
319 | +DEF_HELPER_FLAGS_6(sve_stdd_le_zd_mte, TCG_CALL_NO_WG, | ||
320 | + void, env, ptr, ptr, ptr, tl, i32) | ||
321 | +DEF_HELPER_FLAGS_6(sve_stdd_be_zd_mte, TCG_CALL_NO_WG, | ||
322 | + void, env, ptr, ptr, ptr, tl, i32) | ||
323 | + | ||
324 | DEF_HELPER_FLAGS_4(sve2_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
325 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | ||
326 | index XXXXXXX..XXXXXXX 100644 | ||
327 | --- a/target/arm/sve_helper.c | ||
328 | +++ b/target/arm/sve_helper.c | ||
329 | @@ -XXX,XX +XXX,XX @@ static target_ulong off_zd_d(void *reg, intptr_t reg_ofs) | ||
330 | static inline QEMU_ALWAYS_INLINE | ||
331 | void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, | ||
332 | target_ulong base, uint32_t desc, uintptr_t retaddr, | ||
333 | - int esize, int msize, zreg_off_fn *off_fn, | ||
334 | + uint32_t mtedesc, int esize, int msize, | ||
335 | + zreg_off_fn *off_fn, | ||
336 | sve_ldst1_host_fn *host_fn, | ||
337 | sve_ldst1_tlb_fn *tlb_fn) | ||
338 | { | ||
339 | @@ -XXX,XX +XXX,XX @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, | ||
340 | cpu_check_watchpoint(env_cpu(env), addr, msize, | ||
341 | info.attrs, BP_MEM_READ, retaddr); | ||
342 | } | ||
343 | - /* TODO: MTE check */ | ||
344 | + if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { | ||
345 | + mte_check1(env, mtedesc, addr, retaddr); | ||
346 | + } | ||
347 | host_fn(&scratch, reg_off, info.host); | ||
348 | } else { | ||
349 | /* Element crosses the page boundary. */ | ||
350 | @@ -XXX,XX +XXX,XX @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, | ||
351 | msize, info.attrs, | ||
352 | BP_MEM_READ, retaddr); | ||
353 | } | ||
354 | - /* TODO: MTE check */ | ||
355 | + if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { | ||
356 | + mte_check1(env, mtedesc, addr, retaddr); | ||
357 | + } | ||
358 | tlb_fn(env, &scratch, reg_off, addr, retaddr); | ||
359 | } | ||
360 | } | ||
361 | @@ -XXX,XX +XXX,XX @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, | ||
362 | memcpy(vd, &scratch, reg_max); | ||
363 | } | ||
364 | |||
365 | +static inline QEMU_ALWAYS_INLINE | ||
366 | +void sve_ld1_z_mte(CPUARMState *env, void *vd, uint64_t *vg, void *vm, | ||
367 | + target_ulong base, uint32_t desc, uintptr_t retaddr, | ||
368 | + int esize, int msize, zreg_off_fn *off_fn, | ||
369 | + sve_ldst1_host_fn *host_fn, | ||
370 | + sve_ldst1_tlb_fn *tlb_fn) | ||
371 | +{ | ||
372 | + uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); | ||
373 | + /* Remove mtedesc from the normal sve descriptor. */ | ||
374 | + desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); | ||
375 | + | ||
376 | + /* | ||
377 | + * ??? TODO: For the 32-bit offset extractions, base + ofs cannot | ||
378 | + * offset base entirely over the address space hole to change the | ||
379 | + * pointer tag, or change the bit55 selector. So we could here | ||
380 | + * examine TBI + TCMA like we do for sve_ldN_r_mte(). | ||
381 | + */ | ||
382 | + sve_ld1_z(env, vd, vg, vm, base, desc, retaddr, mtedesc, | ||
383 | + esize, msize, off_fn, host_fn, tlb_fn); | ||
384 | +} | ||
385 | + | ||
386 | #define DO_LD1_ZPZ_S(MEM, OFS, MSZ) \ | ||
387 | void HELPER(sve_ld##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \ | ||
388 | void *vm, target_ulong base, uint32_t desc) \ | ||
389 | { \ | ||
390 | - sve_ld1_z(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, \ | ||
391 | + sve_ld1_z(env, vd, vg, vm, base, desc, GETPC(), 0, 4, 1 << MSZ, \ | ||
392 | off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \ | ||
393 | +} \ | ||
394 | +void HELPER(sve_ld##MEM##_##OFS##_mte)(CPUARMState *env, void *vd, void *vg, \ | ||
395 | + void *vm, target_ulong base, uint32_t desc) \ | ||
396 | +{ \ | ||
397 | + sve_ld1_z_mte(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, \ | ||
398 | + off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \ | ||
399 | } | ||
400 | |||
401 | #define DO_LD1_ZPZ_D(MEM, OFS, MSZ) \ | ||
402 | void HELPER(sve_ld##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \ | ||
403 | void *vm, target_ulong base, uint32_t desc) \ | ||
404 | { \ | ||
405 | - sve_ld1_z(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, \ | ||
406 | + sve_ld1_z(env, vd, vg, vm, base, desc, GETPC(), 0, 8, 1 << MSZ, \ | ||
407 | off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \ | ||
408 | +} \ | ||
409 | +void HELPER(sve_ld##MEM##_##OFS##_mte)(CPUARMState *env, void *vd, void *vg, \ | ||
410 | + void *vm, target_ulong base, uint32_t desc) \ | ||
411 | +{ \ | ||
412 | + sve_ld1_z_mte(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, \ | ||
413 | + off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \ | ||
414 | } | ||
415 | |||
416 | DO_LD1_ZPZ_S(bsu, zsu, MO_8) | ||
417 | @@ -XXX,XX +XXX,XX @@ DO_LD1_ZPZ_D(dd_be, zd, MO_64) | ||
418 | static inline QEMU_ALWAYS_INLINE | ||
419 | void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, | ||
420 | target_ulong base, uint32_t desc, uintptr_t retaddr, | ||
421 | - const int esz, const int msz, zreg_off_fn *off_fn, | ||
422 | + uint32_t mtedesc, const int esz, const int msz, | ||
423 | + zreg_off_fn *off_fn, | ||
424 | sve_ldst1_host_fn *host_fn, | ||
425 | sve_ldst1_tlb_fn *tlb_fn) | ||
426 | { | ||
427 | @@ -XXX,XX +XXX,XX @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, | ||
428 | * Probe the first element, allowing faults. | ||
429 | */ | ||
430 | addr = base + (off_fn(vm, reg_off) << scale); | ||
431 | + if (mtedesc) { | ||
432 | + mte_check1(env, mtedesc, addr, retaddr); | ||
433 | + } | ||
434 | tlb_fn(env, vd, reg_off, addr, retaddr); | ||
435 | |||
436 | /* After any fault, zero the other elements. */ | ||
437 | @@ -XXX,XX +XXX,XX @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, | ||
438 | (env_cpu(env), addr, msize) & BP_MEM_READ)) { | ||
439 | goto fault; | ||
440 | } | ||
441 | - /* TODO: MTE check. */ | ||
442 | + if (mtedesc && | ||
443 | + arm_tlb_mte_tagged(&info.attrs) && | ||
444 | + !mte_probe1(env, mtedesc, addr)) { | ||
445 | + goto fault; | ||
446 | + } | ||
447 | |||
448 | host_fn(vd, reg_off, info.host); | ||
449 | } | ||
450 | @@ -XXX,XX +XXX,XX @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, | ||
451 | record_fault(env, reg_off, reg_max); | ||
452 | } | ||
453 | |||
454 | -#define DO_LDFF1_ZPZ_S(MEM, OFS, MSZ) \ | ||
455 | -void HELPER(sve_ldff##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \ | ||
456 | - void *vm, target_ulong base, uint32_t desc) \ | ||
457 | -{ \ | ||
458 | - sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), MO_32, MSZ, \ | ||
459 | - off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \ | ||
460 | +static inline QEMU_ALWAYS_INLINE | ||
461 | +void sve_ldff1_z_mte(CPUARMState *env, void *vd, uint64_t *vg, void *vm, | ||
462 | + target_ulong base, uint32_t desc, uintptr_t retaddr, | ||
463 | + const int esz, const int msz, | ||
464 | + zreg_off_fn *off_fn, | ||
465 | + sve_ldst1_host_fn *host_fn, | ||
466 | + sve_ldst1_tlb_fn *tlb_fn) | ||
467 | +{ | ||
468 | + uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); | ||
469 | + /* Remove mtedesc from the normal sve descriptor. */ | ||
470 | + desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); | ||
471 | + | ||
472 | + /* | ||
473 | + * ??? TODO: For the 32-bit offset extractions, base + ofs cannot | ||
474 | + * offset base entirely over the address space hole to change the | ||
475 | + * pointer tag, or change the bit55 selector. So we could here | ||
476 | + * examine TBI + TCMA like we do for sve_ldN_r_mte(). | ||
477 | + */ | ||
478 | + sve_ldff1_z(env, vd, vg, vm, base, desc, retaddr, mtedesc, | ||
479 | + esz, msz, off_fn, host_fn, tlb_fn); | ||
480 | } | ||
481 | |||
482 | -#define DO_LDFF1_ZPZ_D(MEM, OFS, MSZ) \ | ||
483 | -void HELPER(sve_ldff##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \ | ||
484 | - void *vm, target_ulong base, uint32_t desc) \ | ||
485 | -{ \ | ||
486 | - sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), MO_64, MSZ, \ | ||
487 | - off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \ | ||
488 | +#define DO_LDFF1_ZPZ_S(MEM, OFS, MSZ) \ | ||
489 | +void HELPER(sve_ldff##MEM##_##OFS) \ | ||
490 | + (CPUARMState *env, void *vd, void *vg, \ | ||
491 | + void *vm, target_ulong base, uint32_t desc) \ | ||
492 | +{ \ | ||
493 | + sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), 0, MO_32, MSZ, \ | ||
494 | + off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \ | ||
495 | +} \ | ||
496 | +void HELPER(sve_ldff##MEM##_##OFS##_mte) \ | ||
497 | + (CPUARMState *env, void *vd, void *vg, \ | ||
498 | + void *vm, target_ulong base, uint32_t desc) \ | ||
499 | +{ \ | ||
500 | + sve_ldff1_z_mte(env, vd, vg, vm, base, desc, GETPC(), MO_32, MSZ, \ | ||
501 | + off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \ | ||
502 | +} | ||
503 | + | ||
504 | +#define DO_LDFF1_ZPZ_D(MEM, OFS, MSZ) \ | ||
505 | +void HELPER(sve_ldff##MEM##_##OFS) \ | ||
506 | + (CPUARMState *env, void *vd, void *vg, \ | ||
507 | + void *vm, target_ulong base, uint32_t desc) \ | ||
508 | +{ \ | ||
509 | + sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), 0, MO_64, MSZ, \ | ||
510 | + off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \ | ||
511 | +} \ | ||
512 | +void HELPER(sve_ldff##MEM##_##OFS##_mte) \ | ||
513 | + (CPUARMState *env, void *vd, void *vg, \ | ||
514 | + void *vm, target_ulong base, uint32_t desc) \ | ||
515 | +{ \ | ||
516 | + sve_ldff1_z_mte(env, vd, vg, vm, base, desc, GETPC(), MO_64, MSZ, \ | ||
517 | + off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \ | ||
518 | } | ||
519 | |||
520 | DO_LDFF1_ZPZ_S(bsu, zsu, MO_8) | ||
521 | @@ -XXX,XX +XXX,XX @@ DO_LDFF1_ZPZ_D(dd_be, zd, MO_64) | ||
522 | static inline QEMU_ALWAYS_INLINE | ||
523 | void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, | ||
524 | target_ulong base, uint32_t desc, uintptr_t retaddr, | ||
525 | - int esize, int msize, zreg_off_fn *off_fn, | ||
526 | + uint32_t mtedesc, int esize, int msize, | ||
527 | + zreg_off_fn *off_fn, | ||
528 | sve_ldst1_host_fn *host_fn, | ||
529 | sve_ldst1_tlb_fn *tlb_fn) | ||
530 | { | ||
531 | @@ -XXX,XX +XXX,XX @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, | ||
532 | cpu_check_watchpoint(env_cpu(env), addr, msize, | ||
533 | info.attrs, BP_MEM_WRITE, retaddr); | ||
534 | } | ||
535 | - /* TODO: MTE check. */ | ||
536 | + | ||
537 | + if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { | ||
538 | + mte_check1(env, mtedesc, addr, retaddr); | ||
539 | + } | ||
540 | } | ||
541 | i += 1; | ||
542 | reg_off += esize; | ||
543 | @@ -XXX,XX +XXX,XX @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, | ||
544 | } while (reg_off < reg_max); | ||
545 | } | ||
546 | |||
547 | -#define DO_ST1_ZPZ_S(MEM, OFS, MSZ) \ | ||
548 | -void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \ | ||
549 | - void *vm, target_ulong base, uint32_t desc) \ | ||
550 | -{ \ | ||
551 | - sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, \ | ||
552 | - off_##OFS##_s, sve_st1##MEM##_host, sve_st1##MEM##_tlb); \ | ||
553 | +static inline QEMU_ALWAYS_INLINE | ||
554 | +void sve_st1_z_mte(CPUARMState *env, void *vd, uint64_t *vg, void *vm, | ||
555 | + target_ulong base, uint32_t desc, uintptr_t retaddr, | ||
556 | + int esize, int msize, zreg_off_fn *off_fn, | ||
557 | + sve_ldst1_host_fn *host_fn, | ||
558 | + sve_ldst1_tlb_fn *tlb_fn) | ||
559 | +{ | ||
560 | + uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); | ||
561 | + /* Remove mtedesc from the normal sve descriptor. */ | ||
562 | + desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); | ||
563 | + | ||
564 | + /* | ||
565 | + * ??? TODO: For the 32-bit offset extractions, base + ofs cannot | ||
566 | + * offset base entirely over the address space hole to change the | ||
567 | + * pointer tag, or change the bit55 selector. So we could here | ||
568 | + * examine TBI + TCMA like we do for sve_ldN_r_mte(). | ||
569 | + */ | ||
570 | + sve_st1_z(env, vd, vg, vm, base, desc, retaddr, mtedesc, | ||
571 | + esize, msize, off_fn, host_fn, tlb_fn); | ||
572 | } | ||
573 | |||
574 | -#define DO_ST1_ZPZ_D(MEM, OFS, MSZ) \ | ||
575 | -void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \ | ||
576 | +#define DO_ST1_ZPZ_S(MEM, OFS, MSZ) \ | ||
577 | +void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \ | ||
578 | void *vm, target_ulong base, uint32_t desc) \ | ||
579 | -{ \ | ||
580 | - sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, \ | ||
581 | - off_##OFS##_d, sve_st1##MEM##_host, sve_st1##MEM##_tlb); \ | ||
582 | +{ \ | ||
583 | + sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 0, 4, 1 << MSZ, \ | ||
584 | + off_##OFS##_s, sve_st1##MEM##_host, sve_st1##MEM##_tlb); \ | ||
585 | +} \ | ||
586 | +void HELPER(sve_st##MEM##_##OFS##_mte)(CPUARMState *env, void *vd, void *vg, \ | ||
587 | + void *vm, target_ulong base, uint32_t desc) \ | ||
588 | +{ \ | ||
589 | + sve_st1_z_mte(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, \ | ||
590 | + off_##OFS##_s, sve_st1##MEM##_host, sve_st1##MEM##_tlb); \ | ||
591 | +} | ||
592 | + | ||
593 | +#define DO_ST1_ZPZ_D(MEM, OFS, MSZ) \ | ||
594 | +void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \ | ||
595 | + void *vm, target_ulong base, uint32_t desc) \ | ||
596 | +{ \ | ||
597 | + sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 0, 8, 1 << MSZ, \ | ||
598 | + off_##OFS##_d, sve_st1##MEM##_host, sve_st1##MEM##_tlb); \ | ||
599 | +} \ | ||
600 | +void HELPER(sve_st##MEM##_##OFS##_mte)(CPUARMState *env, void *vd, void *vg, \ | ||
601 | + void *vm, target_ulong base, uint32_t desc) \ | ||
602 | +{ \ | ||
603 | + sve_st1_z_mte(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, \ | ||
604 | + off_##OFS##_d, sve_st1##MEM##_host, sve_st1##MEM##_tlb); \ | ||
605 | } | ||
606 | |||
607 | DO_ST1_ZPZ_S(bs, zsu, MO_8) | ||
608 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
609 | index XXXXXXX..XXXXXXX 100644 | ||
610 | --- a/target/arm/translate-sve.c | ||
611 | +++ b/target/arm/translate-sve.c | ||
612 | @@ -XXX,XX +XXX,XX @@ static bool trans_ST_zpri(DisasContext *s, arg_rpri_store *a) | ||
613 | */ | 26 | */ |
614 | 27 | -static long neon_element_offset(int reg, int element, MemOp size) | |
615 | static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, | 28 | +static long neon_element_offset(int reg, int element, MemOp memop) |
616 | - int scale, TCGv_i64 scalar, int msz, | 29 | { |
617 | + int scale, TCGv_i64 scalar, int msz, bool is_write, | 30 | - int element_size = 1 << size; |
618 | gen_helper_gvec_mem_scatter *fn) | 31 | + int element_size = 1 << (memop & MO_SIZE); |
619 | { | 32 | int ofs = element * element_size; |
620 | unsigned vsz = vec_full_reg_size(s); | 33 | #ifdef HOST_WORDS_BIGENDIAN |
621 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, | 34 | /* |
622 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | 35 | @@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg) |
623 | TCGv_ptr t_zt = tcg_temp_new_ptr(); | 36 | } |
624 | TCGv_i32 t_desc; | 37 | } |
625 | - int desc; | 38 | |
626 | + int desc = 0; | 39 | -static TCGv_i32 neon_load_reg(int reg, int pass) |
627 | 40 | -{ | |
628 | + if (s->mte_active[0]) { | 41 | - TCGv_i32 tmp = tcg_temp_new_i32(); |
629 | + desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | 42 | - tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32)); |
630 | + desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | 43 | - return tmp; |
631 | + desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | 44 | -} |
632 | + desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | 45 | - |
633 | + desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz); | 46 | -static void neon_store_reg(int reg, int pass, TCGv_i32 var) |
634 | + desc <<= SVE_MTEDESC_SHIFT; | 47 | -{ |
635 | + } | 48 | - tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32)); |
636 | desc = simd_desc(vsz, vsz, scale); | 49 | - tcg_temp_free_i32(var); |
637 | t_desc = tcg_const_i32(desc); | 50 | -} |
638 | 51 | - | |
639 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, | 52 | static inline void neon_load_reg64(TCGv_i64 var, int reg) |
640 | tcg_temp_free_i32(t_desc); | 53 | { |
641 | } | 54 | tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); |
642 | 55 | @@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg) | |
643 | -/* Indexed by [be][ff][xs][u][msz]. */ | 56 | tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); |
644 | -static gen_helper_gvec_mem_scatter * const gather_load_fn32[2][2][2][2][3] = { | 57 | } |
645 | - /* Little-endian */ | 58 | |
646 | - { { { { gen_helper_sve_ldbss_zsu, | 59 | -static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size) |
647 | - gen_helper_sve_ldhss_le_zsu, | 60 | +static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) |
648 | - NULL, }, | 61 | { |
649 | - { gen_helper_sve_ldbsu_zsu, | 62 | - long off = neon_element_offset(reg, ele, size); |
650 | - gen_helper_sve_ldhsu_le_zsu, | 63 | + long off = neon_element_offset(reg, ele, memop); |
651 | - gen_helper_sve_ldss_le_zsu, } }, | 64 | |
652 | - { { gen_helper_sve_ldbss_zss, | 65 | - switch (size) { |
653 | - gen_helper_sve_ldhss_le_zss, | 66 | - case MO_32: |
654 | - NULL, }, | 67 | + switch (memop) { |
655 | - { gen_helper_sve_ldbsu_zss, | 68 | + case MO_SB: |
656 | - gen_helper_sve_ldhsu_le_zss, | 69 | + tcg_gen_ld8s_i32(dest, cpu_env, off); |
657 | - gen_helper_sve_ldss_le_zss, } } }, | 70 | + break; |
658 | +/* Indexed by [mte][be][ff][xs][u][msz]. */ | 71 | + case MO_UB: |
659 | +static gen_helper_gvec_mem_scatter * const | 72 | + tcg_gen_ld8u_i32(dest, cpu_env, off); |
660 | +gather_load_fn32[2][2][2][2][2][3] = { | 73 | + break; |
661 | + { /* MTE Inactive */ | 74 | + case MO_SW: |
662 | + { /* Little-endian */ | 75 | + tcg_gen_ld16s_i32(dest, cpu_env, off); |
663 | + { { { gen_helper_sve_ldbss_zsu, | 76 | + break; |
664 | + gen_helper_sve_ldhss_le_zsu, | 77 | + case MO_UW: |
665 | + NULL, }, | 78 | + tcg_gen_ld16u_i32(dest, cpu_env, off); |
666 | + { gen_helper_sve_ldbsu_zsu, | 79 | + break; |
667 | + gen_helper_sve_ldhsu_le_zsu, | 80 | + case MO_UL: |
668 | + gen_helper_sve_ldss_le_zsu, } }, | 81 | + case MO_SL: |
669 | + { { gen_helper_sve_ldbss_zss, | 82 | tcg_gen_ld_i32(dest, cpu_env, off); |
670 | + gen_helper_sve_ldhss_le_zss, | ||
671 | + NULL, }, | ||
672 | + { gen_helper_sve_ldbsu_zss, | ||
673 | + gen_helper_sve_ldhsu_le_zss, | ||
674 | + gen_helper_sve_ldss_le_zss, } } }, | ||
675 | |||
676 | - /* First-fault */ | ||
677 | - { { { gen_helper_sve_ldffbss_zsu, | ||
678 | - gen_helper_sve_ldffhss_le_zsu, | ||
679 | - NULL, }, | ||
680 | - { gen_helper_sve_ldffbsu_zsu, | ||
681 | - gen_helper_sve_ldffhsu_le_zsu, | ||
682 | - gen_helper_sve_ldffss_le_zsu, } }, | ||
683 | - { { gen_helper_sve_ldffbss_zss, | ||
684 | - gen_helper_sve_ldffhss_le_zss, | ||
685 | - NULL, }, | ||
686 | - { gen_helper_sve_ldffbsu_zss, | ||
687 | - gen_helper_sve_ldffhsu_le_zss, | ||
688 | - gen_helper_sve_ldffss_le_zss, } } } }, | ||
689 | + /* First-fault */ | ||
690 | + { { { gen_helper_sve_ldffbss_zsu, | ||
691 | + gen_helper_sve_ldffhss_le_zsu, | ||
692 | + NULL, }, | ||
693 | + { gen_helper_sve_ldffbsu_zsu, | ||
694 | + gen_helper_sve_ldffhsu_le_zsu, | ||
695 | + gen_helper_sve_ldffss_le_zsu, } }, | ||
696 | + { { gen_helper_sve_ldffbss_zss, | ||
697 | + gen_helper_sve_ldffhss_le_zss, | ||
698 | + NULL, }, | ||
699 | + { gen_helper_sve_ldffbsu_zss, | ||
700 | + gen_helper_sve_ldffhsu_le_zss, | ||
701 | + gen_helper_sve_ldffss_le_zss, } } } }, | ||
702 | |||
703 | - /* Big-endian */ | ||
704 | - { { { { gen_helper_sve_ldbss_zsu, | ||
705 | - gen_helper_sve_ldhss_be_zsu, | ||
706 | - NULL, }, | ||
707 | - { gen_helper_sve_ldbsu_zsu, | ||
708 | - gen_helper_sve_ldhsu_be_zsu, | ||
709 | - gen_helper_sve_ldss_be_zsu, } }, | ||
710 | - { { gen_helper_sve_ldbss_zss, | ||
711 | - gen_helper_sve_ldhss_be_zss, | ||
712 | - NULL, }, | ||
713 | - { gen_helper_sve_ldbsu_zss, | ||
714 | - gen_helper_sve_ldhsu_be_zss, | ||
715 | - gen_helper_sve_ldss_be_zss, } } }, | ||
716 | + { /* Big-endian */ | ||
717 | + { { { gen_helper_sve_ldbss_zsu, | ||
718 | + gen_helper_sve_ldhss_be_zsu, | ||
719 | + NULL, }, | ||
720 | + { gen_helper_sve_ldbsu_zsu, | ||
721 | + gen_helper_sve_ldhsu_be_zsu, | ||
722 | + gen_helper_sve_ldss_be_zsu, } }, | ||
723 | + { { gen_helper_sve_ldbss_zss, | ||
724 | + gen_helper_sve_ldhss_be_zss, | ||
725 | + NULL, }, | ||
726 | + { gen_helper_sve_ldbsu_zss, | ||
727 | + gen_helper_sve_ldhsu_be_zss, | ||
728 | + gen_helper_sve_ldss_be_zss, } } }, | ||
729 | |||
730 | - /* First-fault */ | ||
731 | - { { { gen_helper_sve_ldffbss_zsu, | ||
732 | - gen_helper_sve_ldffhss_be_zsu, | ||
733 | - NULL, }, | ||
734 | - { gen_helper_sve_ldffbsu_zsu, | ||
735 | - gen_helper_sve_ldffhsu_be_zsu, | ||
736 | - gen_helper_sve_ldffss_be_zsu, } }, | ||
737 | - { { gen_helper_sve_ldffbss_zss, | ||
738 | - gen_helper_sve_ldffhss_be_zss, | ||
739 | - NULL, }, | ||
740 | - { gen_helper_sve_ldffbsu_zss, | ||
741 | - gen_helper_sve_ldffhsu_be_zss, | ||
742 | - gen_helper_sve_ldffss_be_zss, } } } }, | ||
743 | + /* First-fault */ | ||
744 | + { { { gen_helper_sve_ldffbss_zsu, | ||
745 | + gen_helper_sve_ldffhss_be_zsu, | ||
746 | + NULL, }, | ||
747 | + { gen_helper_sve_ldffbsu_zsu, | ||
748 | + gen_helper_sve_ldffhsu_be_zsu, | ||
749 | + gen_helper_sve_ldffss_be_zsu, } }, | ||
750 | + { { gen_helper_sve_ldffbss_zss, | ||
751 | + gen_helper_sve_ldffhss_be_zss, | ||
752 | + NULL, }, | ||
753 | + { gen_helper_sve_ldffbsu_zss, | ||
754 | + gen_helper_sve_ldffhsu_be_zss, | ||
755 | + gen_helper_sve_ldffss_be_zss, } } } } }, | ||
756 | + { /* MTE Active */ | ||
757 | + { /* Little-endian */ | ||
758 | + { { { gen_helper_sve_ldbss_zsu_mte, | ||
759 | + gen_helper_sve_ldhss_le_zsu_mte, | ||
760 | + NULL, }, | ||
761 | + { gen_helper_sve_ldbsu_zsu_mte, | ||
762 | + gen_helper_sve_ldhsu_le_zsu_mte, | ||
763 | + gen_helper_sve_ldss_le_zsu_mte, } }, | ||
764 | + { { gen_helper_sve_ldbss_zss_mte, | ||
765 | + gen_helper_sve_ldhss_le_zss_mte, | ||
766 | + NULL, }, | ||
767 | + { gen_helper_sve_ldbsu_zss_mte, | ||
768 | + gen_helper_sve_ldhsu_le_zss_mte, | ||
769 | + gen_helper_sve_ldss_le_zss_mte, } } }, | ||
770 | + | ||
771 | + /* First-fault */ | ||
772 | + { { { gen_helper_sve_ldffbss_zsu_mte, | ||
773 | + gen_helper_sve_ldffhss_le_zsu_mte, | ||
774 | + NULL, }, | ||
775 | + { gen_helper_sve_ldffbsu_zsu_mte, | ||
776 | + gen_helper_sve_ldffhsu_le_zsu_mte, | ||
777 | + gen_helper_sve_ldffss_le_zsu_mte, } }, | ||
778 | + { { gen_helper_sve_ldffbss_zss_mte, | ||
779 | + gen_helper_sve_ldffhss_le_zss_mte, | ||
780 | + NULL, }, | ||
781 | + { gen_helper_sve_ldffbsu_zss_mte, | ||
782 | + gen_helper_sve_ldffhsu_le_zss_mte, | ||
783 | + gen_helper_sve_ldffss_le_zss_mte, } } } }, | ||
784 | + | ||
785 | + { /* Big-endian */ | ||
786 | + { { { gen_helper_sve_ldbss_zsu_mte, | ||
787 | + gen_helper_sve_ldhss_be_zsu_mte, | ||
788 | + NULL, }, | ||
789 | + { gen_helper_sve_ldbsu_zsu_mte, | ||
790 | + gen_helper_sve_ldhsu_be_zsu_mte, | ||
791 | + gen_helper_sve_ldss_be_zsu_mte, } }, | ||
792 | + { { gen_helper_sve_ldbss_zss_mte, | ||
793 | + gen_helper_sve_ldhss_be_zss_mte, | ||
794 | + NULL, }, | ||
795 | + { gen_helper_sve_ldbsu_zss_mte, | ||
796 | + gen_helper_sve_ldhsu_be_zss_mte, | ||
797 | + gen_helper_sve_ldss_be_zss_mte, } } }, | ||
798 | + | ||
799 | + /* First-fault */ | ||
800 | + { { { gen_helper_sve_ldffbss_zsu_mte, | ||
801 | + gen_helper_sve_ldffhss_be_zsu_mte, | ||
802 | + NULL, }, | ||
803 | + { gen_helper_sve_ldffbsu_zsu_mte, | ||
804 | + gen_helper_sve_ldffhsu_be_zsu_mte, | ||
805 | + gen_helper_sve_ldffss_be_zsu_mte, } }, | ||
806 | + { { gen_helper_sve_ldffbss_zss_mte, | ||
807 | + gen_helper_sve_ldffhss_be_zss_mte, | ||
808 | + NULL, }, | ||
809 | + { gen_helper_sve_ldffbsu_zss_mte, | ||
810 | + gen_helper_sve_ldffhsu_be_zss_mte, | ||
811 | + gen_helper_sve_ldffss_be_zss_mte, } } } } }, | ||
812 | }; | ||
813 | |||
814 | /* Note that we overload xs=2 to indicate 64-bit offset. */ | ||
815 | -static gen_helper_gvec_mem_scatter * const gather_load_fn64[2][2][3][2][4] = { | ||
816 | - /* Little-endian */ | ||
817 | - { { { { gen_helper_sve_ldbds_zsu, | ||
818 | - gen_helper_sve_ldhds_le_zsu, | ||
819 | - gen_helper_sve_ldsds_le_zsu, | ||
820 | - NULL, }, | ||
821 | - { gen_helper_sve_ldbdu_zsu, | ||
822 | - gen_helper_sve_ldhdu_le_zsu, | ||
823 | - gen_helper_sve_ldsdu_le_zsu, | ||
824 | - gen_helper_sve_lddd_le_zsu, } }, | ||
825 | - { { gen_helper_sve_ldbds_zss, | ||
826 | - gen_helper_sve_ldhds_le_zss, | ||
827 | - gen_helper_sve_ldsds_le_zss, | ||
828 | - NULL, }, | ||
829 | - { gen_helper_sve_ldbdu_zss, | ||
830 | - gen_helper_sve_ldhdu_le_zss, | ||
831 | - gen_helper_sve_ldsdu_le_zss, | ||
832 | - gen_helper_sve_lddd_le_zss, } }, | ||
833 | - { { gen_helper_sve_ldbds_zd, | ||
834 | - gen_helper_sve_ldhds_le_zd, | ||
835 | - gen_helper_sve_ldsds_le_zd, | ||
836 | - NULL, }, | ||
837 | - { gen_helper_sve_ldbdu_zd, | ||
838 | - gen_helper_sve_ldhdu_le_zd, | ||
839 | - gen_helper_sve_ldsdu_le_zd, | ||
840 | - gen_helper_sve_lddd_le_zd, } } }, | ||
841 | +static gen_helper_gvec_mem_scatter * const | ||
842 | +gather_load_fn64[2][2][2][3][2][4] = { | ||
843 | + { /* MTE Inactive */ | ||
844 | + { /* Little-endian */ | ||
845 | + { { { gen_helper_sve_ldbds_zsu, | ||
846 | + gen_helper_sve_ldhds_le_zsu, | ||
847 | + gen_helper_sve_ldsds_le_zsu, | ||
848 | + NULL, }, | ||
849 | + { gen_helper_sve_ldbdu_zsu, | ||
850 | + gen_helper_sve_ldhdu_le_zsu, | ||
851 | + gen_helper_sve_ldsdu_le_zsu, | ||
852 | + gen_helper_sve_lddd_le_zsu, } }, | ||
853 | + { { gen_helper_sve_ldbds_zss, | ||
854 | + gen_helper_sve_ldhds_le_zss, | ||
855 | + gen_helper_sve_ldsds_le_zss, | ||
856 | + NULL, }, | ||
857 | + { gen_helper_sve_ldbdu_zss, | ||
858 | + gen_helper_sve_ldhdu_le_zss, | ||
859 | + gen_helper_sve_ldsdu_le_zss, | ||
860 | + gen_helper_sve_lddd_le_zss, } }, | ||
861 | + { { gen_helper_sve_ldbds_zd, | ||
862 | + gen_helper_sve_ldhds_le_zd, | ||
863 | + gen_helper_sve_ldsds_le_zd, | ||
864 | + NULL, }, | ||
865 | + { gen_helper_sve_ldbdu_zd, | ||
866 | + gen_helper_sve_ldhdu_le_zd, | ||
867 | + gen_helper_sve_ldsdu_le_zd, | ||
868 | + gen_helper_sve_lddd_le_zd, } } }, | ||
869 | |||
870 | - /* First-fault */ | ||
871 | - { { { gen_helper_sve_ldffbds_zsu, | ||
872 | - gen_helper_sve_ldffhds_le_zsu, | ||
873 | - gen_helper_sve_ldffsds_le_zsu, | ||
874 | - NULL, }, | ||
875 | - { gen_helper_sve_ldffbdu_zsu, | ||
876 | - gen_helper_sve_ldffhdu_le_zsu, | ||
877 | - gen_helper_sve_ldffsdu_le_zsu, | ||
878 | - gen_helper_sve_ldffdd_le_zsu, } }, | ||
879 | - { { gen_helper_sve_ldffbds_zss, | ||
880 | - gen_helper_sve_ldffhds_le_zss, | ||
881 | - gen_helper_sve_ldffsds_le_zss, | ||
882 | - NULL, }, | ||
883 | - { gen_helper_sve_ldffbdu_zss, | ||
884 | - gen_helper_sve_ldffhdu_le_zss, | ||
885 | - gen_helper_sve_ldffsdu_le_zss, | ||
886 | - gen_helper_sve_ldffdd_le_zss, } }, | ||
887 | - { { gen_helper_sve_ldffbds_zd, | ||
888 | - gen_helper_sve_ldffhds_le_zd, | ||
889 | - gen_helper_sve_ldffsds_le_zd, | ||
890 | - NULL, }, | ||
891 | - { gen_helper_sve_ldffbdu_zd, | ||
892 | - gen_helper_sve_ldffhdu_le_zd, | ||
893 | - gen_helper_sve_ldffsdu_le_zd, | ||
894 | - gen_helper_sve_ldffdd_le_zd, } } } }, | ||
895 | + /* First-fault */ | ||
896 | + { { { gen_helper_sve_ldffbds_zsu, | ||
897 | + gen_helper_sve_ldffhds_le_zsu, | ||
898 | + gen_helper_sve_ldffsds_le_zsu, | ||
899 | + NULL, }, | ||
900 | + { gen_helper_sve_ldffbdu_zsu, | ||
901 | + gen_helper_sve_ldffhdu_le_zsu, | ||
902 | + gen_helper_sve_ldffsdu_le_zsu, | ||
903 | + gen_helper_sve_ldffdd_le_zsu, } }, | ||
904 | + { { gen_helper_sve_ldffbds_zss, | ||
905 | + gen_helper_sve_ldffhds_le_zss, | ||
906 | + gen_helper_sve_ldffsds_le_zss, | ||
907 | + NULL, }, | ||
908 | + { gen_helper_sve_ldffbdu_zss, | ||
909 | + gen_helper_sve_ldffhdu_le_zss, | ||
910 | + gen_helper_sve_ldffsdu_le_zss, | ||
911 | + gen_helper_sve_ldffdd_le_zss, } }, | ||
912 | + { { gen_helper_sve_ldffbds_zd, | ||
913 | + gen_helper_sve_ldffhds_le_zd, | ||
914 | + gen_helper_sve_ldffsds_le_zd, | ||
915 | + NULL, }, | ||
916 | + { gen_helper_sve_ldffbdu_zd, | ||
917 | + gen_helper_sve_ldffhdu_le_zd, | ||
918 | + gen_helper_sve_ldffsdu_le_zd, | ||
919 | + gen_helper_sve_ldffdd_le_zd, } } } }, | ||
920 | + { /* Big-endian */ | ||
921 | + { { { gen_helper_sve_ldbds_zsu, | ||
922 | + gen_helper_sve_ldhds_be_zsu, | ||
923 | + gen_helper_sve_ldsds_be_zsu, | ||
924 | + NULL, }, | ||
925 | + { gen_helper_sve_ldbdu_zsu, | ||
926 | + gen_helper_sve_ldhdu_be_zsu, | ||
927 | + gen_helper_sve_ldsdu_be_zsu, | ||
928 | + gen_helper_sve_lddd_be_zsu, } }, | ||
929 | + { { gen_helper_sve_ldbds_zss, | ||
930 | + gen_helper_sve_ldhds_be_zss, | ||
931 | + gen_helper_sve_ldsds_be_zss, | ||
932 | + NULL, }, | ||
933 | + { gen_helper_sve_ldbdu_zss, | ||
934 | + gen_helper_sve_ldhdu_be_zss, | ||
935 | + gen_helper_sve_ldsdu_be_zss, | ||
936 | + gen_helper_sve_lddd_be_zss, } }, | ||
937 | + { { gen_helper_sve_ldbds_zd, | ||
938 | + gen_helper_sve_ldhds_be_zd, | ||
939 | + gen_helper_sve_ldsds_be_zd, | ||
940 | + NULL, }, | ||
941 | + { gen_helper_sve_ldbdu_zd, | ||
942 | + gen_helper_sve_ldhdu_be_zd, | ||
943 | + gen_helper_sve_ldsdu_be_zd, | ||
944 | + gen_helper_sve_lddd_be_zd, } } }, | ||
945 | |||
946 | - /* Big-endian */ | ||
947 | - { { { { gen_helper_sve_ldbds_zsu, | ||
948 | - gen_helper_sve_ldhds_be_zsu, | ||
949 | - gen_helper_sve_ldsds_be_zsu, | ||
950 | - NULL, }, | ||
951 | - { gen_helper_sve_ldbdu_zsu, | ||
952 | - gen_helper_sve_ldhdu_be_zsu, | ||
953 | - gen_helper_sve_ldsdu_be_zsu, | ||
954 | - gen_helper_sve_lddd_be_zsu, } }, | ||
955 | - { { gen_helper_sve_ldbds_zss, | ||
956 | - gen_helper_sve_ldhds_be_zss, | ||
957 | - gen_helper_sve_ldsds_be_zss, | ||
958 | - NULL, }, | ||
959 | - { gen_helper_sve_ldbdu_zss, | ||
960 | - gen_helper_sve_ldhdu_be_zss, | ||
961 | - gen_helper_sve_ldsdu_be_zss, | ||
962 | - gen_helper_sve_lddd_be_zss, } }, | ||
963 | - { { gen_helper_sve_ldbds_zd, | ||
964 | - gen_helper_sve_ldhds_be_zd, | ||
965 | - gen_helper_sve_ldsds_be_zd, | ||
966 | - NULL, }, | ||
967 | - { gen_helper_sve_ldbdu_zd, | ||
968 | - gen_helper_sve_ldhdu_be_zd, | ||
969 | - gen_helper_sve_ldsdu_be_zd, | ||
970 | - gen_helper_sve_lddd_be_zd, } } }, | ||
971 | + /* First-fault */ | ||
972 | + { { { gen_helper_sve_ldffbds_zsu, | ||
973 | + gen_helper_sve_ldffhds_be_zsu, | ||
974 | + gen_helper_sve_ldffsds_be_zsu, | ||
975 | + NULL, }, | ||
976 | + { gen_helper_sve_ldffbdu_zsu, | ||
977 | + gen_helper_sve_ldffhdu_be_zsu, | ||
978 | + gen_helper_sve_ldffsdu_be_zsu, | ||
979 | + gen_helper_sve_ldffdd_be_zsu, } }, | ||
980 | + { { gen_helper_sve_ldffbds_zss, | ||
981 | + gen_helper_sve_ldffhds_be_zss, | ||
982 | + gen_helper_sve_ldffsds_be_zss, | ||
983 | + NULL, }, | ||
984 | + { gen_helper_sve_ldffbdu_zss, | ||
985 | + gen_helper_sve_ldffhdu_be_zss, | ||
986 | + gen_helper_sve_ldffsdu_be_zss, | ||
987 | + gen_helper_sve_ldffdd_be_zss, } }, | ||
988 | + { { gen_helper_sve_ldffbds_zd, | ||
989 | + gen_helper_sve_ldffhds_be_zd, | ||
990 | + gen_helper_sve_ldffsds_be_zd, | ||
991 | + NULL, }, | ||
992 | + { gen_helper_sve_ldffbdu_zd, | ||
993 | + gen_helper_sve_ldffhdu_be_zd, | ||
994 | + gen_helper_sve_ldffsdu_be_zd, | ||
995 | + gen_helper_sve_ldffdd_be_zd, } } } } }, | ||
996 | + { /* MTE Active */ | ||
997 | + { /* Little-endian */ | ||
998 | + { { { gen_helper_sve_ldbds_zsu_mte, | ||
999 | + gen_helper_sve_ldhds_le_zsu_mte, | ||
1000 | + gen_helper_sve_ldsds_le_zsu_mte, | ||
1001 | + NULL, }, | ||
1002 | + { gen_helper_sve_ldbdu_zsu_mte, | ||
1003 | + gen_helper_sve_ldhdu_le_zsu_mte, | ||
1004 | + gen_helper_sve_ldsdu_le_zsu_mte, | ||
1005 | + gen_helper_sve_lddd_le_zsu_mte, } }, | ||
1006 | + { { gen_helper_sve_ldbds_zss_mte, | ||
1007 | + gen_helper_sve_ldhds_le_zss_mte, | ||
1008 | + gen_helper_sve_ldsds_le_zss_mte, | ||
1009 | + NULL, }, | ||
1010 | + { gen_helper_sve_ldbdu_zss_mte, | ||
1011 | + gen_helper_sve_ldhdu_le_zss_mte, | ||
1012 | + gen_helper_sve_ldsdu_le_zss_mte, | ||
1013 | + gen_helper_sve_lddd_le_zss_mte, } }, | ||
1014 | + { { gen_helper_sve_ldbds_zd_mte, | ||
1015 | + gen_helper_sve_ldhds_le_zd_mte, | ||
1016 | + gen_helper_sve_ldsds_le_zd_mte, | ||
1017 | + NULL, }, | ||
1018 | + { gen_helper_sve_ldbdu_zd_mte, | ||
1019 | + gen_helper_sve_ldhdu_le_zd_mte, | ||
1020 | + gen_helper_sve_ldsdu_le_zd_mte, | ||
1021 | + gen_helper_sve_lddd_le_zd_mte, } } }, | ||
1022 | |||
1023 | - /* First-fault */ | ||
1024 | - { { { gen_helper_sve_ldffbds_zsu, | ||
1025 | - gen_helper_sve_ldffhds_be_zsu, | ||
1026 | - gen_helper_sve_ldffsds_be_zsu, | ||
1027 | - NULL, }, | ||
1028 | - { gen_helper_sve_ldffbdu_zsu, | ||
1029 | - gen_helper_sve_ldffhdu_be_zsu, | ||
1030 | - gen_helper_sve_ldffsdu_be_zsu, | ||
1031 | - gen_helper_sve_ldffdd_be_zsu, } }, | ||
1032 | - { { gen_helper_sve_ldffbds_zss, | ||
1033 | - gen_helper_sve_ldffhds_be_zss, | ||
1034 | - gen_helper_sve_ldffsds_be_zss, | ||
1035 | - NULL, }, | ||
1036 | - { gen_helper_sve_ldffbdu_zss, | ||
1037 | - gen_helper_sve_ldffhdu_be_zss, | ||
1038 | - gen_helper_sve_ldffsdu_be_zss, | ||
1039 | - gen_helper_sve_ldffdd_be_zss, } }, | ||
1040 | - { { gen_helper_sve_ldffbds_zd, | ||
1041 | - gen_helper_sve_ldffhds_be_zd, | ||
1042 | - gen_helper_sve_ldffsds_be_zd, | ||
1043 | - NULL, }, | ||
1044 | - { gen_helper_sve_ldffbdu_zd, | ||
1045 | - gen_helper_sve_ldffhdu_be_zd, | ||
1046 | - gen_helper_sve_ldffsdu_be_zd, | ||
1047 | - gen_helper_sve_ldffdd_be_zd, } } } }, | ||
1048 | + /* First-fault */ | ||
1049 | + { { { gen_helper_sve_ldffbds_zsu_mte, | ||
1050 | + gen_helper_sve_ldffhds_le_zsu_mte, | ||
1051 | + gen_helper_sve_ldffsds_le_zsu_mte, | ||
1052 | + NULL, }, | ||
1053 | + { gen_helper_sve_ldffbdu_zsu_mte, | ||
1054 | + gen_helper_sve_ldffhdu_le_zsu_mte, | ||
1055 | + gen_helper_sve_ldffsdu_le_zsu_mte, | ||
1056 | + gen_helper_sve_ldffdd_le_zsu_mte, } }, | ||
1057 | + { { gen_helper_sve_ldffbds_zss_mte, | ||
1058 | + gen_helper_sve_ldffhds_le_zss_mte, | ||
1059 | + gen_helper_sve_ldffsds_le_zss_mte, | ||
1060 | + NULL, }, | ||
1061 | + { gen_helper_sve_ldffbdu_zss_mte, | ||
1062 | + gen_helper_sve_ldffhdu_le_zss_mte, | ||
1063 | + gen_helper_sve_ldffsdu_le_zss_mte, | ||
1064 | + gen_helper_sve_ldffdd_le_zss_mte, } }, | ||
1065 | + { { gen_helper_sve_ldffbds_zd_mte, | ||
1066 | + gen_helper_sve_ldffhds_le_zd_mte, | ||
1067 | + gen_helper_sve_ldffsds_le_zd_mte, | ||
1068 | + NULL, }, | ||
1069 | + { gen_helper_sve_ldffbdu_zd_mte, | ||
1070 | + gen_helper_sve_ldffhdu_le_zd_mte, | ||
1071 | + gen_helper_sve_ldffsdu_le_zd_mte, | ||
1072 | + gen_helper_sve_ldffdd_le_zd_mte, } } } }, | ||
1073 | + { /* Big-endian */ | ||
1074 | + { { { gen_helper_sve_ldbds_zsu_mte, | ||
1075 | + gen_helper_sve_ldhds_be_zsu_mte, | ||
1076 | + gen_helper_sve_ldsds_be_zsu_mte, | ||
1077 | + NULL, }, | ||
1078 | + { gen_helper_sve_ldbdu_zsu_mte, | ||
1079 | + gen_helper_sve_ldhdu_be_zsu_mte, | ||
1080 | + gen_helper_sve_ldsdu_be_zsu_mte, | ||
1081 | + gen_helper_sve_lddd_be_zsu_mte, } }, | ||
1082 | + { { gen_helper_sve_ldbds_zss_mte, | ||
1083 | + gen_helper_sve_ldhds_be_zss_mte, | ||
1084 | + gen_helper_sve_ldsds_be_zss_mte, | ||
1085 | + NULL, }, | ||
1086 | + { gen_helper_sve_ldbdu_zss_mte, | ||
1087 | + gen_helper_sve_ldhdu_be_zss_mte, | ||
1088 | + gen_helper_sve_ldsdu_be_zss_mte, | ||
1089 | + gen_helper_sve_lddd_be_zss_mte, } }, | ||
1090 | + { { gen_helper_sve_ldbds_zd_mte, | ||
1091 | + gen_helper_sve_ldhds_be_zd_mte, | ||
1092 | + gen_helper_sve_ldsds_be_zd_mte, | ||
1093 | + NULL, }, | ||
1094 | + { gen_helper_sve_ldbdu_zd_mte, | ||
1095 | + gen_helper_sve_ldhdu_be_zd_mte, | ||
1096 | + gen_helper_sve_ldsdu_be_zd_mte, | ||
1097 | + gen_helper_sve_lddd_be_zd_mte, } } }, | ||
1098 | + | ||
1099 | + /* First-fault */ | ||
1100 | + { { { gen_helper_sve_ldffbds_zsu_mte, | ||
1101 | + gen_helper_sve_ldffhds_be_zsu_mte, | ||
1102 | + gen_helper_sve_ldffsds_be_zsu_mte, | ||
1103 | + NULL, }, | ||
1104 | + { gen_helper_sve_ldffbdu_zsu_mte, | ||
1105 | + gen_helper_sve_ldffhdu_be_zsu_mte, | ||
1106 | + gen_helper_sve_ldffsdu_be_zsu_mte, | ||
1107 | + gen_helper_sve_ldffdd_be_zsu_mte, } }, | ||
1108 | + { { gen_helper_sve_ldffbds_zss_mte, | ||
1109 | + gen_helper_sve_ldffhds_be_zss_mte, | ||
1110 | + gen_helper_sve_ldffsds_be_zss_mte, | ||
1111 | + NULL, }, | ||
1112 | + { gen_helper_sve_ldffbdu_zss_mte, | ||
1113 | + gen_helper_sve_ldffhdu_be_zss_mte, | ||
1114 | + gen_helper_sve_ldffsdu_be_zss_mte, | ||
1115 | + gen_helper_sve_ldffdd_be_zss_mte, } }, | ||
1116 | + { { gen_helper_sve_ldffbds_zd_mte, | ||
1117 | + gen_helper_sve_ldffhds_be_zd_mte, | ||
1118 | + gen_helper_sve_ldffsds_be_zd_mte, | ||
1119 | + NULL, }, | ||
1120 | + { gen_helper_sve_ldffbdu_zd_mte, | ||
1121 | + gen_helper_sve_ldffhdu_be_zd_mte, | ||
1122 | + gen_helper_sve_ldffsdu_be_zd_mte, | ||
1123 | + gen_helper_sve_ldffdd_be_zd_mte, } } } } }, | ||
1124 | }; | ||
1125 | |||
1126 | static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a) | ||
1127 | { | ||
1128 | gen_helper_gvec_mem_scatter *fn = NULL; | ||
1129 | - int be = s->be_data == MO_BE; | ||
1130 | + bool be = s->be_data == MO_BE; | ||
1131 | + bool mte = s->mte_active[0]; | ||
1132 | |||
1133 | if (!sve_access_check(s)) { | ||
1134 | return true; | ||
1135 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a) | ||
1136 | |||
1137 | switch (a->esz) { | ||
1138 | case MO_32: | ||
1139 | - fn = gather_load_fn32[be][a->ff][a->xs][a->u][a->msz]; | ||
1140 | + fn = gather_load_fn32[mte][be][a->ff][a->xs][a->u][a->msz]; | ||
1141 | break; | ||
1142 | case MO_64: | ||
1143 | - fn = gather_load_fn64[be][a->ff][a->xs][a->u][a->msz]; | ||
1144 | + fn = gather_load_fn64[mte][be][a->ff][a->xs][a->u][a->msz]; | ||
1145 | break; | ||
1146 | } | ||
1147 | assert(fn != NULL); | ||
1148 | |||
1149 | do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz, | ||
1150 | - cpu_reg_sp(s, a->rn), a->msz, fn); | ||
1151 | + cpu_reg_sp(s, a->rn), a->msz, false, fn); | ||
1152 | return true; | ||
1153 | } | ||
1154 | |||
1155 | static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a) | ||
1156 | { | ||
1157 | gen_helper_gvec_mem_scatter *fn = NULL; | ||
1158 | - int be = s->be_data == MO_BE; | ||
1159 | + bool be = s->be_data == MO_BE; | ||
1160 | + bool mte = s->mte_active[0]; | ||
1161 | TCGv_i64 imm; | ||
1162 | |||
1163 | if (a->esz < a->msz || (a->esz == a->msz && !a->u)) { | ||
1164 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a) | ||
1165 | |||
1166 | switch (a->esz) { | ||
1167 | case MO_32: | ||
1168 | - fn = gather_load_fn32[be][a->ff][0][a->u][a->msz]; | ||
1169 | + fn = gather_load_fn32[mte][be][a->ff][0][a->u][a->msz]; | ||
1170 | break; | ||
1171 | case MO_64: | ||
1172 | - fn = gather_load_fn64[be][a->ff][2][a->u][a->msz]; | ||
1173 | + fn = gather_load_fn64[mte][be][a->ff][2][a->u][a->msz]; | ||
1174 | break; | ||
1175 | } | ||
1176 | assert(fn != NULL); | ||
1177 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a) | ||
1178 | * by loading the immediate into the scalar parameter. | ||
1179 | */ | ||
1180 | imm = tcg_const_i64(a->imm << a->msz); | ||
1181 | - do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, fn); | ||
1182 | + do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, false, fn); | ||
1183 | tcg_temp_free_i64(imm); | ||
1184 | return true; | ||
1185 | } | ||
1186 | |||
1187 | -/* Indexed by [be][xs][msz]. */ | ||
1188 | -static gen_helper_gvec_mem_scatter * const scatter_store_fn32[2][2][3] = { | ||
1189 | - /* Little-endian */ | ||
1190 | - { { gen_helper_sve_stbs_zsu, | ||
1191 | - gen_helper_sve_sths_le_zsu, | ||
1192 | - gen_helper_sve_stss_le_zsu, }, | ||
1193 | - { gen_helper_sve_stbs_zss, | ||
1194 | - gen_helper_sve_sths_le_zss, | ||
1195 | - gen_helper_sve_stss_le_zss, } }, | ||
1196 | - /* Big-endian */ | ||
1197 | - { { gen_helper_sve_stbs_zsu, | ||
1198 | - gen_helper_sve_sths_be_zsu, | ||
1199 | - gen_helper_sve_stss_be_zsu, }, | ||
1200 | - { gen_helper_sve_stbs_zss, | ||
1201 | - gen_helper_sve_sths_be_zss, | ||
1202 | - gen_helper_sve_stss_be_zss, } }, | ||
1203 | +/* Indexed by [mte][be][xs][msz]. */ | ||
1204 | +static gen_helper_gvec_mem_scatter * const scatter_store_fn32[2][2][2][3] = { | ||
1205 | + { /* MTE Inactive */ | ||
1206 | + { /* Little-endian */ | ||
1207 | + { gen_helper_sve_stbs_zsu, | ||
1208 | + gen_helper_sve_sths_le_zsu, | ||
1209 | + gen_helper_sve_stss_le_zsu, }, | ||
1210 | + { gen_helper_sve_stbs_zss, | ||
1211 | + gen_helper_sve_sths_le_zss, | ||
1212 | + gen_helper_sve_stss_le_zss, } }, | ||
1213 | + { /* Big-endian */ | ||
1214 | + { gen_helper_sve_stbs_zsu, | ||
1215 | + gen_helper_sve_sths_be_zsu, | ||
1216 | + gen_helper_sve_stss_be_zsu, }, | ||
1217 | + { gen_helper_sve_stbs_zss, | ||
1218 | + gen_helper_sve_sths_be_zss, | ||
1219 | + gen_helper_sve_stss_be_zss, } } }, | ||
1220 | + { /* MTE Active */ | ||
1221 | + { /* Little-endian */ | ||
1222 | + { gen_helper_sve_stbs_zsu_mte, | ||
1223 | + gen_helper_sve_sths_le_zsu_mte, | ||
1224 | + gen_helper_sve_stss_le_zsu_mte, }, | ||
1225 | + { gen_helper_sve_stbs_zss_mte, | ||
1226 | + gen_helper_sve_sths_le_zss_mte, | ||
1227 | + gen_helper_sve_stss_le_zss_mte, } }, | ||
1228 | + { /* Big-endian */ | ||
1229 | + { gen_helper_sve_stbs_zsu_mte, | ||
1230 | + gen_helper_sve_sths_be_zsu_mte, | ||
1231 | + gen_helper_sve_stss_be_zsu_mte, }, | ||
1232 | + { gen_helper_sve_stbs_zss_mte, | ||
1233 | + gen_helper_sve_sths_be_zss_mte, | ||
1234 | + gen_helper_sve_stss_be_zss_mte, } } }, | ||
1235 | }; | ||
1236 | |||
1237 | /* Note that we overload xs=2 to indicate 64-bit offset. */ | ||
1238 | -static gen_helper_gvec_mem_scatter * const scatter_store_fn64[2][3][4] = { | ||
1239 | - /* Little-endian */ | ||
1240 | - { { gen_helper_sve_stbd_zsu, | ||
1241 | - gen_helper_sve_sthd_le_zsu, | ||
1242 | - gen_helper_sve_stsd_le_zsu, | ||
1243 | - gen_helper_sve_stdd_le_zsu, }, | ||
1244 | - { gen_helper_sve_stbd_zss, | ||
1245 | - gen_helper_sve_sthd_le_zss, | ||
1246 | - gen_helper_sve_stsd_le_zss, | ||
1247 | - gen_helper_sve_stdd_le_zss, }, | ||
1248 | - { gen_helper_sve_stbd_zd, | ||
1249 | - gen_helper_sve_sthd_le_zd, | ||
1250 | - gen_helper_sve_stsd_le_zd, | ||
1251 | - gen_helper_sve_stdd_le_zd, } }, | ||
1252 | - /* Big-endian */ | ||
1253 | - { { gen_helper_sve_stbd_zsu, | ||
1254 | - gen_helper_sve_sthd_be_zsu, | ||
1255 | - gen_helper_sve_stsd_be_zsu, | ||
1256 | - gen_helper_sve_stdd_be_zsu, }, | ||
1257 | - { gen_helper_sve_stbd_zss, | ||
1258 | - gen_helper_sve_sthd_be_zss, | ||
1259 | - gen_helper_sve_stsd_be_zss, | ||
1260 | - gen_helper_sve_stdd_be_zss, }, | ||
1261 | - { gen_helper_sve_stbd_zd, | ||
1262 | - gen_helper_sve_sthd_be_zd, | ||
1263 | - gen_helper_sve_stsd_be_zd, | ||
1264 | - gen_helper_sve_stdd_be_zd, } }, | ||
1265 | +static gen_helper_gvec_mem_scatter * const scatter_store_fn64[2][2][3][4] = { | ||
1266 | + { /* MTE Inactive */ | ||
1267 | + { /* Little-endian */ | ||
1268 | + { gen_helper_sve_stbd_zsu, | ||
1269 | + gen_helper_sve_sthd_le_zsu, | ||
1270 | + gen_helper_sve_stsd_le_zsu, | ||
1271 | + gen_helper_sve_stdd_le_zsu, }, | ||
1272 | + { gen_helper_sve_stbd_zss, | ||
1273 | + gen_helper_sve_sthd_le_zss, | ||
1274 | + gen_helper_sve_stsd_le_zss, | ||
1275 | + gen_helper_sve_stdd_le_zss, }, | ||
1276 | + { gen_helper_sve_stbd_zd, | ||
1277 | + gen_helper_sve_sthd_le_zd, | ||
1278 | + gen_helper_sve_stsd_le_zd, | ||
1279 | + gen_helper_sve_stdd_le_zd, } }, | ||
1280 | + { /* Big-endian */ | ||
1281 | + { gen_helper_sve_stbd_zsu, | ||
1282 | + gen_helper_sve_sthd_be_zsu, | ||
1283 | + gen_helper_sve_stsd_be_zsu, | ||
1284 | + gen_helper_sve_stdd_be_zsu, }, | ||
1285 | + { gen_helper_sve_stbd_zss, | ||
1286 | + gen_helper_sve_sthd_be_zss, | ||
1287 | + gen_helper_sve_stsd_be_zss, | ||
1288 | + gen_helper_sve_stdd_be_zss, }, | ||
1289 | + { gen_helper_sve_stbd_zd, | ||
1290 | + gen_helper_sve_sthd_be_zd, | ||
1291 | + gen_helper_sve_stsd_be_zd, | ||
1292 | + gen_helper_sve_stdd_be_zd, } } }, | ||
1293 | + { /* MTE Inactive */ | ||
1294 | + { /* Little-endian */ | ||
1295 | + { gen_helper_sve_stbd_zsu_mte, | ||
1296 | + gen_helper_sve_sthd_le_zsu_mte, | ||
1297 | + gen_helper_sve_stsd_le_zsu_mte, | ||
1298 | + gen_helper_sve_stdd_le_zsu_mte, }, | ||
1299 | + { gen_helper_sve_stbd_zss_mte, | ||
1300 | + gen_helper_sve_sthd_le_zss_mte, | ||
1301 | + gen_helper_sve_stsd_le_zss_mte, | ||
1302 | + gen_helper_sve_stdd_le_zss_mte, }, | ||
1303 | + { gen_helper_sve_stbd_zd_mte, | ||
1304 | + gen_helper_sve_sthd_le_zd_mte, | ||
1305 | + gen_helper_sve_stsd_le_zd_mte, | ||
1306 | + gen_helper_sve_stdd_le_zd_mte, } }, | ||
1307 | + { /* Big-endian */ | ||
1308 | + { gen_helper_sve_stbd_zsu_mte, | ||
1309 | + gen_helper_sve_sthd_be_zsu_mte, | ||
1310 | + gen_helper_sve_stsd_be_zsu_mte, | ||
1311 | + gen_helper_sve_stdd_be_zsu_mte, }, | ||
1312 | + { gen_helper_sve_stbd_zss_mte, | ||
1313 | + gen_helper_sve_sthd_be_zss_mte, | ||
1314 | + gen_helper_sve_stsd_be_zss_mte, | ||
1315 | + gen_helper_sve_stdd_be_zss_mte, }, | ||
1316 | + { gen_helper_sve_stbd_zd_mte, | ||
1317 | + gen_helper_sve_sthd_be_zd_mte, | ||
1318 | + gen_helper_sve_stsd_be_zd_mte, | ||
1319 | + gen_helper_sve_stdd_be_zd_mte, } } }, | ||
1320 | }; | ||
1321 | |||
1322 | static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a) | ||
1323 | { | ||
1324 | gen_helper_gvec_mem_scatter *fn; | ||
1325 | - int be = s->be_data == MO_BE; | ||
1326 | + bool be = s->be_data == MO_BE; | ||
1327 | + bool mte = s->mte_active[0]; | ||
1328 | |||
1329 | if (a->esz < a->msz || (a->msz == 0 && a->scale)) { | ||
1330 | return false; | ||
1331 | @@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a) | ||
1332 | } | ||
1333 | switch (a->esz) { | ||
1334 | case MO_32: | ||
1335 | - fn = scatter_store_fn32[be][a->xs][a->msz]; | ||
1336 | + fn = scatter_store_fn32[mte][be][a->xs][a->msz]; | ||
1337 | break; | ||
1338 | case MO_64: | ||
1339 | - fn = scatter_store_fn64[be][a->xs][a->msz]; | ||
1340 | + fn = scatter_store_fn64[mte][be][a->xs][a->msz]; | ||
1341 | break; | 83 | break; |
1342 | default: | 84 | default: |
1343 | g_assert_not_reached(); | 85 | @@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size) |
1344 | } | 86 | } |
1345 | do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz, | 87 | } |
1346 | - cpu_reg_sp(s, a->rn), a->msz, fn); | 88 | |
1347 | + cpu_reg_sp(s, a->rn), a->msz, true, fn); | 89 | -static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size) |
90 | +static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) | ||
91 | { | ||
92 | - long off = neon_element_offset(reg, ele, size); | ||
93 | + long off = neon_element_offset(reg, ele, memop); | ||
94 | |||
95 | - switch (size) { | ||
96 | + switch (memop) { | ||
97 | + case MO_8: | ||
98 | + tcg_gen_st8_i32(src, cpu_env, off); | ||
99 | + break; | ||
100 | + case MO_16: | ||
101 | + tcg_gen_st16_i32(src, cpu_env, off); | ||
102 | + break; | ||
103 | case MO_32: | ||
104 | tcg_gen_st_i32(src, cpu_env, off); | ||
105 | break; | ||
106 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
107 | index XXXXXXX..XXXXXXX 100644 | ||
108 | --- a/target/arm/translate-vfp.c.inc | ||
109 | +++ b/target/arm/translate-vfp.c.inc | ||
110 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) | ||
111 | { | ||
112 | /* VMOV scalar to general purpose register */ | ||
113 | TCGv_i32 tmp; | ||
114 | - int pass; | ||
115 | - uint32_t offset; | ||
116 | |||
117 | - /* SIZE == 2 is a VFP instruction; otherwise NEON. */ | ||
118 | - if (a->size == 2 | ||
119 | + /* SIZE == MO_32 is a VFP instruction; otherwise NEON. */ | ||
120 | + if (a->size == MO_32 | ||
121 | ? !dc_isar_feature(aa32_fpsp_v2, s) | ||
122 | : !arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
123 | return false; | ||
124 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) | ||
125 | return false; | ||
126 | } | ||
127 | |||
128 | - offset = a->index << a->size; | ||
129 | - pass = extract32(offset, 2, 1); | ||
130 | - offset = extract32(offset, 0, 2) * 8; | ||
131 | - | ||
132 | if (!vfp_access_check(s)) { | ||
133 | return true; | ||
134 | } | ||
135 | |||
136 | - tmp = neon_load_reg(a->vn, pass); | ||
137 | - switch (a->size) { | ||
138 | - case 0: | ||
139 | - if (offset) { | ||
140 | - tcg_gen_shri_i32(tmp, tmp, offset); | ||
141 | - } | ||
142 | - if (a->u) { | ||
143 | - gen_uxtb(tmp); | ||
144 | - } else { | ||
145 | - gen_sxtb(tmp); | ||
146 | - } | ||
147 | - break; | ||
148 | - case 1: | ||
149 | - if (a->u) { | ||
150 | - if (offset) { | ||
151 | - tcg_gen_shri_i32(tmp, tmp, 16); | ||
152 | - } else { | ||
153 | - gen_uxth(tmp); | ||
154 | - } | ||
155 | - } else { | ||
156 | - if (offset) { | ||
157 | - tcg_gen_sari_i32(tmp, tmp, 16); | ||
158 | - } else { | ||
159 | - gen_sxth(tmp); | ||
160 | - } | ||
161 | - } | ||
162 | - break; | ||
163 | - case 2: | ||
164 | - break; | ||
165 | - } | ||
166 | + tmp = tcg_temp_new_i32(); | ||
167 | + read_neon_element32(tmp, a->vn, a->index, a->size | (a->u ? 0 : MO_SIGN)); | ||
168 | store_reg(s, a->rt, tmp); | ||
169 | |||
1348 | return true; | 170 | return true; |
1349 | } | 171 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) |
1350 | 172 | static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a) | |
1351 | static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a) | 173 | { |
1352 | { | 174 | /* VMOV general purpose register to scalar */ |
1353 | gen_helper_gvec_mem_scatter *fn = NULL; | 175 | - TCGv_i32 tmp, tmp2; |
1354 | - int be = s->be_data == MO_BE; | 176 | - int pass; |
1355 | + bool be = s->be_data == MO_BE; | 177 | - uint32_t offset; |
1356 | + bool mte = s->mte_active[0]; | 178 | + TCGv_i32 tmp; |
1357 | TCGv_i64 imm; | 179 | |
1358 | 180 | - /* SIZE == 2 is a VFP instruction; otherwise NEON. */ | |
1359 | if (a->esz < a->msz) { | 181 | - if (a->size == 2 |
1360 | @@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a) | 182 | + /* SIZE == MO_32 is a VFP instruction; otherwise NEON. */ |
1361 | 183 | + if (a->size == MO_32 | |
1362 | switch (a->esz) { | 184 | ? !dc_isar_feature(aa32_fpsp_v2, s) |
1363 | case MO_32: | 185 | : !arm_dc_feature(s, ARM_FEATURE_NEON)) { |
1364 | - fn = scatter_store_fn32[be][0][a->msz]; | 186 | return false; |
1365 | + fn = scatter_store_fn32[mte][be][0][a->msz]; | 187 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a) |
1366 | break; | 188 | return false; |
1367 | case MO_64: | 189 | } |
1368 | - fn = scatter_store_fn64[be][2][a->msz]; | 190 | |
1369 | + fn = scatter_store_fn64[mte][be][2][a->msz]; | 191 | - offset = a->index << a->size; |
1370 | break; | 192 | - pass = extract32(offset, 2, 1); |
1371 | } | 193 | - offset = extract32(offset, 0, 2) * 8; |
1372 | assert(fn != NULL); | 194 | - |
1373 | @@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a) | 195 | if (!vfp_access_check(s)) { |
1374 | * by loading the immediate into the scalar parameter. | 196 | return true; |
1375 | */ | 197 | } |
1376 | imm = tcg_const_i64(a->imm << a->msz); | 198 | |
1377 | - do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, fn); | 199 | tmp = load_reg(s, a->rt); |
1378 | + do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, true, fn); | 200 | - switch (a->size) { |
1379 | tcg_temp_free_i64(imm); | 201 | - case 0: |
202 | - tmp2 = neon_load_reg(a->vn, pass); | ||
203 | - tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8); | ||
204 | - tcg_temp_free_i32(tmp2); | ||
205 | - break; | ||
206 | - case 1: | ||
207 | - tmp2 = neon_load_reg(a->vn, pass); | ||
208 | - tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16); | ||
209 | - tcg_temp_free_i32(tmp2); | ||
210 | - break; | ||
211 | - case 2: | ||
212 | - break; | ||
213 | - } | ||
214 | - neon_store_reg(a->vn, pass, tmp); | ||
215 | + write_neon_element32(tmp, a->vn, a->index, a->size); | ||
216 | + tcg_temp_free_i32(tmp); | ||
217 | |||
1380 | return true; | 218 | return true; |
1381 | } | 219 | } |
1382 | -- | 220 | -- |
1383 | 2.20.1 | 221 | 2.20.1 |
1384 | 222 | ||
1385 | 223 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Emphasize that the is_jmp option exits to the main loop. | 3 | The only uses of this function are for loading VFP |
4 | single-precision values, and nothing to do with NEON. | ||
4 | 5 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20201030022618.785675-8-richard.henderson@linaro.org | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20200626033144.790098-6-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | target/arm/translate.h | 14 ++++++++------ | 11 | target/arm/translate.c | 4 +- |
11 | target/arm/translate-a64.c | 8 ++++---- | 12 | target/arm/translate-vfp.c.inc | 184 ++++++++++++++++----------------- |
12 | target/arm/translate-vfp.inc.c | 4 ++-- | 13 | 2 files changed, 94 insertions(+), 94 deletions(-) |
13 | target/arm/translate.c | 12 ++++++------ | ||
14 | 4 files changed, 20 insertions(+), 18 deletions(-) | ||
15 | 14 | ||
16 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/translate.h | ||
19 | +++ b/target/arm/translate.h | ||
20 | @@ -XXX,XX +XXX,XX @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) | ||
21 | |||
22 | /* is_jmp field values */ | ||
23 | #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ | ||
24 | -#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ | ||
25 | +/* CPU state was modified dynamically; exit to main loop for interrupts. */ | ||
26 | +#define DISAS_UPDATE_EXIT DISAS_TARGET_1 | ||
27 | /* These instructions trap after executing, so the A32/T32 decoder must | ||
28 | * defer them until after the conditional execution state has been updated. | ||
29 | * WFI also needs special handling when single-stepping. | ||
30 | @@ -XXX,XX +XXX,XX @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) | ||
31 | * custom end-of-TB code) | ||
32 | */ | ||
33 | #define DISAS_BX_EXCRET DISAS_TARGET_8 | ||
34 | -/* For instructions which want an immediate exit to the main loop, | ||
35 | - * as opposed to attempting to use lookup_and_goto_ptr. Unlike | ||
36 | - * DISAS_UPDATE this doesn't write the PC on exiting the translation | ||
37 | - * loop so you need to ensure something (gen_a64_set_pc_im or runtime | ||
38 | - * helper) has done so before we reach return from cpu_tb_exec. | ||
39 | +/* | ||
40 | + * For instructions which want an immediate exit to the main loop, as opposed | ||
41 | + * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this | ||
42 | + * doesn't write the PC on exiting the translation loop so you need to ensure | ||
43 | + * something (gen_a64_set_pc_im or runtime helper) has done so before we reach | ||
44 | + * return from cpu_tb_exec. | ||
45 | */ | ||
46 | #define DISAS_EXIT DISAS_TARGET_9 | ||
47 | |||
48 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/target/arm/translate-a64.c | ||
51 | +++ b/target/arm/translate-a64.c | ||
52 | @@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn, | ||
53 | gen_helper_msr_i_daifclear(cpu_env, t1); | ||
54 | tcg_temp_free_i32(t1); | ||
55 | /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ | ||
56 | - s->base.is_jmp = DISAS_UPDATE; | ||
57 | + s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
58 | break; | ||
59 | |||
60 | default: | ||
61 | @@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | ||
62 | |||
63 | if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { | ||
64 | /* I/O operations must end the TB here (whether read or write) */ | ||
65 | - s->base.is_jmp = DISAS_UPDATE; | ||
66 | + s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
67 | } | ||
68 | if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { | ||
69 | /* | ||
70 | @@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | ||
71 | * but allow this to be suppressed by the register definition | ||
72 | * (usually only necessary to work around guest bugs). | ||
73 | */ | ||
74 | - s->base.is_jmp = DISAS_UPDATE; | ||
75 | + s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
76 | } | ||
77 | } | ||
78 | |||
79 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
80 | gen_goto_tb(dc, 1, dc->base.pc_next); | ||
81 | break; | ||
82 | default: | ||
83 | - case DISAS_UPDATE: | ||
84 | + case DISAS_UPDATE_EXIT: | ||
85 | gen_a64_set_pc_im(dc->base.pc_next); | ||
86 | /* fall through */ | ||
87 | case DISAS_EXIT: | ||
88 | diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c | ||
89 | index XXXXXXX..XXXXXXX 100644 | ||
90 | --- a/target/arm/translate-vfp.inc.c | ||
91 | +++ b/target/arm/translate-vfp.inc.c | ||
92 | @@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) | ||
93 | * this to be the last insn in the TB). | ||
94 | */ | ||
95 | if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { | ||
96 | - s->base.is_jmp = DISAS_UPDATE; | ||
97 | + s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
98 | gen_io_start(); | ||
99 | } | ||
100 | gen_helper_v7m_preserve_fp_state(cpu_env); | ||
101 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) | ||
102 | tcg_temp_free_i32(fptr); | ||
103 | |||
104 | /* End the TB, because we have updated FP control bits */ | ||
105 | - s->base.is_jmp = DISAS_UPDATE; | ||
106 | + s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
107 | return true; | ||
108 | } | ||
109 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 15 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
110 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
111 | --- a/target/arm/translate.c | 17 | --- a/target/arm/translate.c |
112 | +++ b/target/arm/translate.c | 18 | +++ b/target/arm/translate.c |
113 | @@ -XXX,XX +XXX,XX @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn) | 19 | @@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg64(TCGv_i64 var, int reg) |
114 | tcg_temp_free_i32(tcg_tgtmode); | 20 | tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); |
115 | tcg_temp_free_i32(tcg_regno); | ||
116 | tcg_temp_free_i32(tcg_reg); | ||
117 | - s->base.is_jmp = DISAS_UPDATE; | ||
118 | + s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
119 | } | 21 | } |
120 | 22 | ||
121 | static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) | 23 | -static inline void neon_load_reg32(TCGv_i32 var, int reg) |
122 | @@ -XXX,XX +XXX,XX @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) | 24 | +static inline void vfp_load_reg32(TCGv_i32 var, int reg) |
123 | tcg_temp_free_i32(tcg_tgtmode); | 25 | { |
124 | tcg_temp_free_i32(tcg_regno); | 26 | tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg)); |
125 | store_reg(s, rn, tcg_reg); | ||
126 | - s->base.is_jmp = DISAS_UPDATE; | ||
127 | + s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
128 | } | 27 | } |
129 | 28 | ||
130 | /* Store value to PC as for an exception return (ie don't | 29 | -static inline void neon_store_reg32(TCGv_i32 var, int reg) |
131 | @@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s, | 30 | +static inline void vfp_store_reg32(TCGv_i32 var, int reg) |
31 | { | ||
32 | tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); | ||
33 | } | ||
34 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/target/arm/translate-vfp.c.inc | ||
37 | +++ b/target/arm/translate-vfp.c.inc | ||
38 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | ||
39 | frn = tcg_temp_new_i32(); | ||
40 | frm = tcg_temp_new_i32(); | ||
41 | dest = tcg_temp_new_i32(); | ||
42 | - neon_load_reg32(frn, rn); | ||
43 | - neon_load_reg32(frm, rm); | ||
44 | + vfp_load_reg32(frn, rn); | ||
45 | + vfp_load_reg32(frm, rm); | ||
46 | switch (a->cc) { | ||
47 | case 0: /* eq: Z */ | ||
48 | tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, | ||
49 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | ||
50 | if (sz == 1) { | ||
51 | tcg_gen_andi_i32(dest, dest, 0xffff); | ||
52 | } | ||
53 | - neon_store_reg32(dest, rd); | ||
54 | + vfp_store_reg32(dest, rd); | ||
55 | tcg_temp_free_i32(frn); | ||
56 | tcg_temp_free_i32(frm); | ||
57 | tcg_temp_free_i32(dest); | ||
58 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) | ||
59 | TCGv_i32 tcg_res; | ||
60 | tcg_op = tcg_temp_new_i32(); | ||
61 | tcg_res = tcg_temp_new_i32(); | ||
62 | - neon_load_reg32(tcg_op, rm); | ||
63 | + vfp_load_reg32(tcg_op, rm); | ||
64 | if (sz == 1) { | ||
65 | gen_helper_rinth(tcg_res, tcg_op, fpst); | ||
66 | } else { | ||
67 | gen_helper_rints(tcg_res, tcg_op, fpst); | ||
68 | } | ||
69 | - neon_store_reg32(tcg_res, rd); | ||
70 | + vfp_store_reg32(tcg_res, rd); | ||
71 | tcg_temp_free_i32(tcg_op); | ||
72 | tcg_temp_free_i32(tcg_res); | ||
73 | } | ||
74 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | ||
75 | gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst); | ||
76 | } | ||
77 | tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res); | ||
78 | - neon_store_reg32(tcg_tmp, rd); | ||
79 | + vfp_store_reg32(tcg_tmp, rd); | ||
80 | tcg_temp_free_i32(tcg_tmp); | ||
81 | tcg_temp_free_i64(tcg_res); | ||
82 | tcg_temp_free_i64(tcg_double); | ||
83 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | ||
84 | TCGv_i32 tcg_single, tcg_res; | ||
85 | tcg_single = tcg_temp_new_i32(); | ||
86 | tcg_res = tcg_temp_new_i32(); | ||
87 | - neon_load_reg32(tcg_single, rm); | ||
88 | + vfp_load_reg32(tcg_single, rm); | ||
89 | if (sz == 1) { | ||
90 | if (is_signed) { | ||
91 | gen_helper_vfp_toslh(tcg_res, tcg_single, tcg_shift, fpst); | ||
92 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | ||
93 | gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst); | ||
94 | } | ||
95 | } | ||
96 | - neon_store_reg32(tcg_res, rd); | ||
97 | + vfp_store_reg32(tcg_res, rd); | ||
98 | tcg_temp_free_i32(tcg_res); | ||
99 | tcg_temp_free_i32(tcg_single); | ||
100 | } | ||
101 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a) | ||
102 | if (a->l) { | ||
103 | /* VFP to general purpose register */ | ||
104 | tmp = tcg_temp_new_i32(); | ||
105 | - neon_load_reg32(tmp, a->vn); | ||
106 | + vfp_load_reg32(tmp, a->vn); | ||
107 | tcg_gen_andi_i32(tmp, tmp, 0xffff); | ||
108 | store_reg(s, a->rt, tmp); | ||
109 | } else { | ||
110 | /* general purpose register to VFP */ | ||
111 | tmp = load_reg(s, a->rt); | ||
112 | tcg_gen_andi_i32(tmp, tmp, 0xffff); | ||
113 | - neon_store_reg32(tmp, a->vn); | ||
114 | + vfp_store_reg32(tmp, a->vn); | ||
132 | tcg_temp_free_i32(tmp); | 115 | tcg_temp_free_i32(tmp); |
133 | } | 116 | } |
134 | tcg_temp_free_i32(addr); | 117 | |
135 | - s->base.is_jmp = DISAS_UPDATE; | 118 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a) |
136 | + s->base.is_jmp = DISAS_UPDATE_EXIT; | 119 | if (a->l) { |
120 | /* VFP to general purpose register */ | ||
121 | tmp = tcg_temp_new_i32(); | ||
122 | - neon_load_reg32(tmp, a->vn); | ||
123 | + vfp_load_reg32(tmp, a->vn); | ||
124 | if (a->rt == 15) { | ||
125 | /* Set the 4 flag bits in the CPSR. */ | ||
126 | gen_set_nzcv(tmp); | ||
127 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a) | ||
128 | } else { | ||
129 | /* general purpose register to VFP */ | ||
130 | tmp = load_reg(s, a->rt); | ||
131 | - neon_store_reg32(tmp, a->vn); | ||
132 | + vfp_store_reg32(tmp, a->vn); | ||
133 | tcg_temp_free_i32(tmp); | ||
134 | } | ||
135 | |||
136 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a) | ||
137 | if (a->op) { | ||
138 | /* fpreg to gpreg */ | ||
139 | tmp = tcg_temp_new_i32(); | ||
140 | - neon_load_reg32(tmp, a->vm); | ||
141 | + vfp_load_reg32(tmp, a->vm); | ||
142 | store_reg(s, a->rt, tmp); | ||
143 | tmp = tcg_temp_new_i32(); | ||
144 | - neon_load_reg32(tmp, a->vm + 1); | ||
145 | + vfp_load_reg32(tmp, a->vm + 1); | ||
146 | store_reg(s, a->rt2, tmp); | ||
147 | } else { | ||
148 | /* gpreg to fpreg */ | ||
149 | tmp = load_reg(s, a->rt); | ||
150 | - neon_store_reg32(tmp, a->vm); | ||
151 | + vfp_store_reg32(tmp, a->vm); | ||
152 | tcg_temp_free_i32(tmp); | ||
153 | tmp = load_reg(s, a->rt2); | ||
154 | - neon_store_reg32(tmp, a->vm + 1); | ||
155 | + vfp_store_reg32(tmp, a->vm + 1); | ||
156 | tcg_temp_free_i32(tmp); | ||
157 | } | ||
158 | |||
159 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a) | ||
160 | if (a->op) { | ||
161 | /* fpreg to gpreg */ | ||
162 | tmp = tcg_temp_new_i32(); | ||
163 | - neon_load_reg32(tmp, a->vm * 2); | ||
164 | + vfp_load_reg32(tmp, a->vm * 2); | ||
165 | store_reg(s, a->rt, tmp); | ||
166 | tmp = tcg_temp_new_i32(); | ||
167 | - neon_load_reg32(tmp, a->vm * 2 + 1); | ||
168 | + vfp_load_reg32(tmp, a->vm * 2 + 1); | ||
169 | store_reg(s, a->rt2, tmp); | ||
170 | } else { | ||
171 | /* gpreg to fpreg */ | ||
172 | tmp = load_reg(s, a->rt); | ||
173 | - neon_store_reg32(tmp, a->vm * 2); | ||
174 | + vfp_store_reg32(tmp, a->vm * 2); | ||
175 | tcg_temp_free_i32(tmp); | ||
176 | tmp = load_reg(s, a->rt2); | ||
177 | - neon_store_reg32(tmp, a->vm * 2 + 1); | ||
178 | + vfp_store_reg32(tmp, a->vm * 2 + 1); | ||
179 | tcg_temp_free_i32(tmp); | ||
180 | } | ||
181 | |||
182 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_VLDR_VSTR_sp *a) | ||
183 | tmp = tcg_temp_new_i32(); | ||
184 | if (a->l) { | ||
185 | gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); | ||
186 | - neon_store_reg32(tmp, a->vd); | ||
187 | + vfp_store_reg32(tmp, a->vd); | ||
188 | } else { | ||
189 | - neon_load_reg32(tmp, a->vd); | ||
190 | + vfp_load_reg32(tmp, a->vd); | ||
191 | gen_aa32_st16(s, tmp, addr, get_mem_index(s)); | ||
192 | } | ||
193 | tcg_temp_free_i32(tmp); | ||
194 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a) | ||
195 | tmp = tcg_temp_new_i32(); | ||
196 | if (a->l) { | ||
197 | gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); | ||
198 | - neon_store_reg32(tmp, a->vd); | ||
199 | + vfp_store_reg32(tmp, a->vd); | ||
200 | } else { | ||
201 | - neon_load_reg32(tmp, a->vd); | ||
202 | + vfp_load_reg32(tmp, a->vd); | ||
203 | gen_aa32_st32(s, tmp, addr, get_mem_index(s)); | ||
204 | } | ||
205 | tcg_temp_free_i32(tmp); | ||
206 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a) | ||
207 | if (a->l) { | ||
208 | /* load */ | ||
209 | gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); | ||
210 | - neon_store_reg32(tmp, a->vd + i); | ||
211 | + vfp_store_reg32(tmp, a->vd + i); | ||
212 | } else { | ||
213 | /* store */ | ||
214 | - neon_load_reg32(tmp, a->vd + i); | ||
215 | + vfp_load_reg32(tmp, a->vd + i); | ||
216 | gen_aa32_st32(s, tmp, addr, get_mem_index(s)); | ||
217 | } | ||
218 | tcg_gen_addi_i32(addr, addr, offset); | ||
219 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn, | ||
220 | fd = tcg_temp_new_i32(); | ||
221 | fpst = fpstatus_ptr(FPST_FPCR); | ||
222 | |||
223 | - neon_load_reg32(f0, vn); | ||
224 | - neon_load_reg32(f1, vm); | ||
225 | + vfp_load_reg32(f0, vn); | ||
226 | + vfp_load_reg32(f1, vm); | ||
227 | |||
228 | for (;;) { | ||
229 | if (reads_vd) { | ||
230 | - neon_load_reg32(fd, vd); | ||
231 | + vfp_load_reg32(fd, vd); | ||
232 | } | ||
233 | fn(fd, f0, f1, fpst); | ||
234 | - neon_store_reg32(fd, vd); | ||
235 | + vfp_store_reg32(fd, vd); | ||
236 | |||
237 | if (veclen == 0) { | ||
238 | break; | ||
239 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn, | ||
240 | veclen--; | ||
241 | vd = vfp_advance_sreg(vd, delta_d); | ||
242 | vn = vfp_advance_sreg(vn, delta_d); | ||
243 | - neon_load_reg32(f0, vn); | ||
244 | + vfp_load_reg32(f0, vn); | ||
245 | if (delta_m) { | ||
246 | vm = vfp_advance_sreg(vm, delta_m); | ||
247 | - neon_load_reg32(f1, vm); | ||
248 | + vfp_load_reg32(f1, vm); | ||
249 | } | ||
250 | } | ||
251 | |||
252 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3OpSPFn *fn, | ||
253 | fd = tcg_temp_new_i32(); | ||
254 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
255 | |||
256 | - neon_load_reg32(f0, vn); | ||
257 | - neon_load_reg32(f1, vm); | ||
258 | + vfp_load_reg32(f0, vn); | ||
259 | + vfp_load_reg32(f1, vm); | ||
260 | |||
261 | if (reads_vd) { | ||
262 | - neon_load_reg32(fd, vd); | ||
263 | + vfp_load_reg32(fd, vd); | ||
264 | } | ||
265 | fn(fd, f0, f1, fpst); | ||
266 | - neon_store_reg32(fd, vd); | ||
267 | + vfp_store_reg32(fd, vd); | ||
268 | |||
269 | tcg_temp_free_i32(f0); | ||
270 | tcg_temp_free_i32(f1); | ||
271 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) | ||
272 | f0 = tcg_temp_new_i32(); | ||
273 | fd = tcg_temp_new_i32(); | ||
274 | |||
275 | - neon_load_reg32(f0, vm); | ||
276 | + vfp_load_reg32(f0, vm); | ||
277 | |||
278 | for (;;) { | ||
279 | fn(fd, f0); | ||
280 | - neon_store_reg32(fd, vd); | ||
281 | + vfp_store_reg32(fd, vd); | ||
282 | |||
283 | if (veclen == 0) { | ||
284 | break; | ||
285 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) | ||
286 | /* single source one-many */ | ||
287 | while (veclen--) { | ||
288 | vd = vfp_advance_sreg(vd, delta_d); | ||
289 | - neon_store_reg32(fd, vd); | ||
290 | + vfp_store_reg32(fd, vd); | ||
291 | } | ||
292 | break; | ||
293 | } | ||
294 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) | ||
295 | veclen--; | ||
296 | vd = vfp_advance_sreg(vd, delta_d); | ||
297 | vm = vfp_advance_sreg(vm, delta_m); | ||
298 | - neon_load_reg32(f0, vm); | ||
299 | + vfp_load_reg32(f0, vm); | ||
300 | } | ||
301 | |||
302 | tcg_temp_free_i32(f0); | ||
303 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_hp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) | ||
304 | } | ||
305 | |||
306 | f0 = tcg_temp_new_i32(); | ||
307 | - neon_load_reg32(f0, vm); | ||
308 | + vfp_load_reg32(f0, vm); | ||
309 | fn(f0, f0); | ||
310 | - neon_store_reg32(f0, vd); | ||
311 | + vfp_store_reg32(f0, vd); | ||
312 | tcg_temp_free_i32(f0); | ||
313 | |||
314 | return true; | ||
315 | @@ -XXX,XX +XXX,XX @@ static bool do_vfm_hp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d) | ||
316 | vm = tcg_temp_new_i32(); | ||
317 | vd = tcg_temp_new_i32(); | ||
318 | |||
319 | - neon_load_reg32(vn, a->vn); | ||
320 | - neon_load_reg32(vm, a->vm); | ||
321 | + vfp_load_reg32(vn, a->vn); | ||
322 | + vfp_load_reg32(vm, a->vm); | ||
323 | if (neg_n) { | ||
324 | /* VFNMS, VFMS */ | ||
325 | gen_helper_vfp_negh(vn, vn); | ||
326 | } | ||
327 | - neon_load_reg32(vd, a->vd); | ||
328 | + vfp_load_reg32(vd, a->vd); | ||
329 | if (neg_d) { | ||
330 | /* VFNMA, VFNMS */ | ||
331 | gen_helper_vfp_negh(vd, vd); | ||
332 | } | ||
333 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
334 | gen_helper_vfp_muladdh(vd, vn, vm, vd, fpst); | ||
335 | - neon_store_reg32(vd, a->vd); | ||
336 | + vfp_store_reg32(vd, a->vd); | ||
337 | |||
338 | tcg_temp_free_ptr(fpst); | ||
339 | tcg_temp_free_i32(vn); | ||
340 | @@ -XXX,XX +XXX,XX @@ static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d) | ||
341 | vm = tcg_temp_new_i32(); | ||
342 | vd = tcg_temp_new_i32(); | ||
343 | |||
344 | - neon_load_reg32(vn, a->vn); | ||
345 | - neon_load_reg32(vm, a->vm); | ||
346 | + vfp_load_reg32(vn, a->vn); | ||
347 | + vfp_load_reg32(vm, a->vm); | ||
348 | if (neg_n) { | ||
349 | /* VFNMS, VFMS */ | ||
350 | gen_helper_vfp_negs(vn, vn); | ||
351 | } | ||
352 | - neon_load_reg32(vd, a->vd); | ||
353 | + vfp_load_reg32(vd, a->vd); | ||
354 | if (neg_d) { | ||
355 | /* VFNMA, VFNMS */ | ||
356 | gen_helper_vfp_negs(vd, vd); | ||
357 | } | ||
358 | fpst = fpstatus_ptr(FPST_FPCR); | ||
359 | gen_helper_vfp_muladds(vd, vn, vm, vd, fpst); | ||
360 | - neon_store_reg32(vd, a->vd); | ||
361 | + vfp_store_reg32(vd, a->vd); | ||
362 | |||
363 | tcg_temp_free_ptr(fpst); | ||
364 | tcg_temp_free_i32(vn); | ||
365 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_hp(DisasContext *s, arg_VMOV_imm_sp *a) | ||
366 | } | ||
367 | |||
368 | fd = tcg_const_i32(vfp_expand_imm(MO_16, a->imm)); | ||
369 | - neon_store_reg32(fd, a->vd); | ||
370 | + vfp_store_reg32(fd, a->vd); | ||
371 | tcg_temp_free_i32(fd); | ||
372 | return true; | ||
137 | } | 373 | } |
138 | 374 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a) | |
139 | /* Generate a label used for skipping this instruction */ | 375 | fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm)); |
140 | @@ -XXX,XX +XXX,XX @@ static bool trans_SETEND(DisasContext *s, arg_SETEND *a) | 376 | |
141 | } | 377 | for (;;) { |
142 | if (a->E != (s->be_data == MO_BE)) { | 378 | - neon_store_reg32(fd, vd); |
143 | gen_helper_setend(cpu_env); | 379 | + vfp_store_reg32(fd, vd); |
144 | - s->base.is_jmp = DISAS_UPDATE; | 380 | |
145 | + s->base.is_jmp = DISAS_UPDATE_EXIT; | 381 | if (veclen == 0) { |
146 | } | 382 | break; |
383 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_hp(DisasContext *s, arg_VCMP_sp *a) | ||
384 | vd = tcg_temp_new_i32(); | ||
385 | vm = tcg_temp_new_i32(); | ||
386 | |||
387 | - neon_load_reg32(vd, a->vd); | ||
388 | + vfp_load_reg32(vd, a->vd); | ||
389 | if (a->z) { | ||
390 | tcg_gen_movi_i32(vm, 0); | ||
391 | } else { | ||
392 | - neon_load_reg32(vm, a->vm); | ||
393 | + vfp_load_reg32(vm, a->vm); | ||
394 | } | ||
395 | |||
396 | if (a->e) { | ||
397 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a) | ||
398 | vd = tcg_temp_new_i32(); | ||
399 | vm = tcg_temp_new_i32(); | ||
400 | |||
401 | - neon_load_reg32(vd, a->vd); | ||
402 | + vfp_load_reg32(vd, a->vd); | ||
403 | if (a->z) { | ||
404 | tcg_gen_movi_i32(vm, 0); | ||
405 | } else { | ||
406 | - neon_load_reg32(vm, a->vm); | ||
407 | + vfp_load_reg32(vm, a->vm); | ||
408 | } | ||
409 | |||
410 | if (a->e) { | ||
411 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a) | ||
412 | /* The T bit tells us if we want the low or high 16 bits of Vm */ | ||
413 | tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); | ||
414 | gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode); | ||
415 | - neon_store_reg32(tmp, a->vd); | ||
416 | + vfp_store_reg32(tmp, a->vd); | ||
417 | tcg_temp_free_i32(ahp_mode); | ||
418 | tcg_temp_free_ptr(fpst); | ||
419 | tcg_temp_free_i32(tmp); | ||
420 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a) | ||
421 | ahp_mode = get_ahp_flag(); | ||
422 | tmp = tcg_temp_new_i32(); | ||
423 | |||
424 | - neon_load_reg32(tmp, a->vm); | ||
425 | + vfp_load_reg32(tmp, a->vm); | ||
426 | gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode); | ||
427 | tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); | ||
428 | tcg_temp_free_i32(ahp_mode); | ||
429 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_hp(DisasContext *s, arg_VRINTR_sp *a) | ||
430 | } | ||
431 | |||
432 | tmp = tcg_temp_new_i32(); | ||
433 | - neon_load_reg32(tmp, a->vm); | ||
434 | + vfp_load_reg32(tmp, a->vm); | ||
435 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
436 | gen_helper_rinth(tmp, tmp, fpst); | ||
437 | - neon_store_reg32(tmp, a->vd); | ||
438 | + vfp_store_reg32(tmp, a->vd); | ||
439 | tcg_temp_free_ptr(fpst); | ||
440 | tcg_temp_free_i32(tmp); | ||
441 | return true; | ||
442 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a) | ||
443 | } | ||
444 | |||
445 | tmp = tcg_temp_new_i32(); | ||
446 | - neon_load_reg32(tmp, a->vm); | ||
447 | + vfp_load_reg32(tmp, a->vm); | ||
448 | fpst = fpstatus_ptr(FPST_FPCR); | ||
449 | gen_helper_rints(tmp, tmp, fpst); | ||
450 | - neon_store_reg32(tmp, a->vd); | ||
451 | + vfp_store_reg32(tmp, a->vd); | ||
452 | tcg_temp_free_ptr(fpst); | ||
453 | tcg_temp_free_i32(tmp); | ||
454 | return true; | ||
455 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a) | ||
456 | } | ||
457 | |||
458 | tmp = tcg_temp_new_i32(); | ||
459 | - neon_load_reg32(tmp, a->vm); | ||
460 | + vfp_load_reg32(tmp, a->vm); | ||
461 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
462 | tcg_rmode = tcg_const_i32(float_round_to_zero); | ||
463 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
464 | gen_helper_rinth(tmp, tmp, fpst); | ||
465 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
466 | - neon_store_reg32(tmp, a->vd); | ||
467 | + vfp_store_reg32(tmp, a->vd); | ||
468 | tcg_temp_free_ptr(fpst); | ||
469 | tcg_temp_free_i32(tcg_rmode); | ||
470 | tcg_temp_free_i32(tmp); | ||
471 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a) | ||
472 | } | ||
473 | |||
474 | tmp = tcg_temp_new_i32(); | ||
475 | - neon_load_reg32(tmp, a->vm); | ||
476 | + vfp_load_reg32(tmp, a->vm); | ||
477 | fpst = fpstatus_ptr(FPST_FPCR); | ||
478 | tcg_rmode = tcg_const_i32(float_round_to_zero); | ||
479 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
480 | gen_helper_rints(tmp, tmp, fpst); | ||
481 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
482 | - neon_store_reg32(tmp, a->vd); | ||
483 | + vfp_store_reg32(tmp, a->vd); | ||
484 | tcg_temp_free_ptr(fpst); | ||
485 | tcg_temp_free_i32(tcg_rmode); | ||
486 | tcg_temp_free_i32(tmp); | ||
487 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_hp(DisasContext *s, arg_VRINTX_sp *a) | ||
488 | } | ||
489 | |||
490 | tmp = tcg_temp_new_i32(); | ||
491 | - neon_load_reg32(tmp, a->vm); | ||
492 | + vfp_load_reg32(tmp, a->vm); | ||
493 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
494 | gen_helper_rinth_exact(tmp, tmp, fpst); | ||
495 | - neon_store_reg32(tmp, a->vd); | ||
496 | + vfp_store_reg32(tmp, a->vd); | ||
497 | tcg_temp_free_ptr(fpst); | ||
498 | tcg_temp_free_i32(tmp); | ||
499 | return true; | ||
500 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a) | ||
501 | } | ||
502 | |||
503 | tmp = tcg_temp_new_i32(); | ||
504 | - neon_load_reg32(tmp, a->vm); | ||
505 | + vfp_load_reg32(tmp, a->vm); | ||
506 | fpst = fpstatus_ptr(FPST_FPCR); | ||
507 | gen_helper_rints_exact(tmp, tmp, fpst); | ||
508 | - neon_store_reg32(tmp, a->vd); | ||
509 | + vfp_store_reg32(tmp, a->vd); | ||
510 | tcg_temp_free_ptr(fpst); | ||
511 | tcg_temp_free_i32(tmp); | ||
512 | return true; | ||
513 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a) | ||
514 | |||
515 | vm = tcg_temp_new_i32(); | ||
516 | vd = tcg_temp_new_i64(); | ||
517 | - neon_load_reg32(vm, a->vm); | ||
518 | + vfp_load_reg32(vm, a->vm); | ||
519 | gen_helper_vfp_fcvtds(vd, vm, cpu_env); | ||
520 | neon_store_reg64(vd, a->vd); | ||
521 | tcg_temp_free_i32(vm); | ||
522 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a) | ||
523 | vm = tcg_temp_new_i64(); | ||
524 | neon_load_reg64(vm, a->vm); | ||
525 | gen_helper_vfp_fcvtsd(vd, vm, cpu_env); | ||
526 | - neon_store_reg32(vd, a->vd); | ||
527 | + vfp_store_reg32(vd, a->vd); | ||
528 | tcg_temp_free_i32(vd); | ||
529 | tcg_temp_free_i64(vm); | ||
530 | return true; | ||
531 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a) | ||
532 | } | ||
533 | |||
534 | vm = tcg_temp_new_i32(); | ||
535 | - neon_load_reg32(vm, a->vm); | ||
536 | + vfp_load_reg32(vm, a->vm); | ||
537 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
538 | if (a->s) { | ||
539 | /* i32 -> f16 */ | ||
540 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a) | ||
541 | /* u32 -> f16 */ | ||
542 | gen_helper_vfp_uitoh(vm, vm, fpst); | ||
543 | } | ||
544 | - neon_store_reg32(vm, a->vd); | ||
545 | + vfp_store_reg32(vm, a->vd); | ||
546 | tcg_temp_free_i32(vm); | ||
547 | tcg_temp_free_ptr(fpst); | ||
548 | return true; | ||
549 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a) | ||
550 | } | ||
551 | |||
552 | vm = tcg_temp_new_i32(); | ||
553 | - neon_load_reg32(vm, a->vm); | ||
554 | + vfp_load_reg32(vm, a->vm); | ||
555 | fpst = fpstatus_ptr(FPST_FPCR); | ||
556 | if (a->s) { | ||
557 | /* i32 -> f32 */ | ||
558 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a) | ||
559 | /* u32 -> f32 */ | ||
560 | gen_helper_vfp_uitos(vm, vm, fpst); | ||
561 | } | ||
562 | - neon_store_reg32(vm, a->vd); | ||
563 | + vfp_store_reg32(vm, a->vd); | ||
564 | tcg_temp_free_i32(vm); | ||
565 | tcg_temp_free_ptr(fpst); | ||
566 | return true; | ||
567 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a) | ||
568 | |||
569 | vm = tcg_temp_new_i32(); | ||
570 | vd = tcg_temp_new_i64(); | ||
571 | - neon_load_reg32(vm, a->vm); | ||
572 | + vfp_load_reg32(vm, a->vm); | ||
573 | fpst = fpstatus_ptr(FPST_FPCR); | ||
574 | if (a->s) { | ||
575 | /* i32 -> f64 */ | ||
576 | @@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) | ||
577 | vd = tcg_temp_new_i32(); | ||
578 | neon_load_reg64(vm, a->vm); | ||
579 | gen_helper_vjcvt(vd, vm, cpu_env); | ||
580 | - neon_store_reg32(vd, a->vd); | ||
581 | + vfp_store_reg32(vd, a->vd); | ||
582 | tcg_temp_free_i64(vm); | ||
583 | tcg_temp_free_i32(vd); | ||
584 | return true; | ||
585 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a) | ||
586 | frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); | ||
587 | |||
588 | vd = tcg_temp_new_i32(); | ||
589 | - neon_load_reg32(vd, a->vd); | ||
590 | + vfp_load_reg32(vd, a->vd); | ||
591 | |||
592 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
593 | shift = tcg_const_i32(frac_bits); | ||
594 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a) | ||
595 | g_assert_not_reached(); | ||
596 | } | ||
597 | |||
598 | - neon_store_reg32(vd, a->vd); | ||
599 | + vfp_store_reg32(vd, a->vd); | ||
600 | tcg_temp_free_i32(vd); | ||
601 | tcg_temp_free_i32(shift); | ||
602 | tcg_temp_free_ptr(fpst); | ||
603 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a) | ||
604 | frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); | ||
605 | |||
606 | vd = tcg_temp_new_i32(); | ||
607 | - neon_load_reg32(vd, a->vd); | ||
608 | + vfp_load_reg32(vd, a->vd); | ||
609 | |||
610 | fpst = fpstatus_ptr(FPST_FPCR); | ||
611 | shift = tcg_const_i32(frac_bits); | ||
612 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a) | ||
613 | g_assert_not_reached(); | ||
614 | } | ||
615 | |||
616 | - neon_store_reg32(vd, a->vd); | ||
617 | + vfp_store_reg32(vd, a->vd); | ||
618 | tcg_temp_free_i32(vd); | ||
619 | tcg_temp_free_i32(shift); | ||
620 | tcg_temp_free_ptr(fpst); | ||
621 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a) | ||
622 | |||
623 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
624 | vm = tcg_temp_new_i32(); | ||
625 | - neon_load_reg32(vm, a->vm); | ||
626 | + vfp_load_reg32(vm, a->vm); | ||
627 | |||
628 | if (a->s) { | ||
629 | if (a->rz) { | ||
630 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a) | ||
631 | gen_helper_vfp_touih(vm, vm, fpst); | ||
632 | } | ||
633 | } | ||
634 | - neon_store_reg32(vm, a->vd); | ||
635 | + vfp_store_reg32(vm, a->vd); | ||
636 | tcg_temp_free_i32(vm); | ||
637 | tcg_temp_free_ptr(fpst); | ||
638 | return true; | ||
639 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a) | ||
640 | |||
641 | fpst = fpstatus_ptr(FPST_FPCR); | ||
642 | vm = tcg_temp_new_i32(); | ||
643 | - neon_load_reg32(vm, a->vm); | ||
644 | + vfp_load_reg32(vm, a->vm); | ||
645 | |||
646 | if (a->s) { | ||
647 | if (a->rz) { | ||
648 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a) | ||
649 | gen_helper_vfp_touis(vm, vm, fpst); | ||
650 | } | ||
651 | } | ||
652 | - neon_store_reg32(vm, a->vd); | ||
653 | + vfp_store_reg32(vm, a->vd); | ||
654 | tcg_temp_free_i32(vm); | ||
655 | tcg_temp_free_ptr(fpst); | ||
656 | return true; | ||
657 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) | ||
658 | gen_helper_vfp_touid(vd, vm, fpst); | ||
659 | } | ||
660 | } | ||
661 | - neon_store_reg32(vd, a->vd); | ||
662 | + vfp_store_reg32(vd, a->vd); | ||
663 | tcg_temp_free_i32(vd); | ||
664 | tcg_temp_free_i64(vm); | ||
665 | tcg_temp_free_ptr(fpst); | ||
666 | @@ -XXX,XX +XXX,XX @@ static bool trans_VINS(DisasContext *s, arg_VINS *a) | ||
667 | /* Insert low half of Vm into high half of Vd */ | ||
668 | rm = tcg_temp_new_i32(); | ||
669 | rd = tcg_temp_new_i32(); | ||
670 | - neon_load_reg32(rm, a->vm); | ||
671 | - neon_load_reg32(rd, a->vd); | ||
672 | + vfp_load_reg32(rm, a->vm); | ||
673 | + vfp_load_reg32(rd, a->vd); | ||
674 | tcg_gen_deposit_i32(rd, rd, rm, 16, 16); | ||
675 | - neon_store_reg32(rd, a->vd); | ||
676 | + vfp_store_reg32(rd, a->vd); | ||
677 | tcg_temp_free_i32(rm); | ||
678 | tcg_temp_free_i32(rd); | ||
679 | return true; | ||
680 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOVX(DisasContext *s, arg_VINS *a) | ||
681 | |||
682 | /* Set Vd to high half of Vm */ | ||
683 | rm = tcg_temp_new_i32(); | ||
684 | - neon_load_reg32(rm, a->vm); | ||
685 | + vfp_load_reg32(rm, a->vm); | ||
686 | tcg_gen_shri_i32(rm, rm, 16); | ||
687 | - neon_store_reg32(rm, a->vd); | ||
688 | + vfp_store_reg32(rm, a->vd); | ||
689 | tcg_temp_free_i32(rm); | ||
147 | return true; | 690 | return true; |
148 | } | 691 | } |
149 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
150 | break; | ||
151 | case DISAS_NEXT: | ||
152 | case DISAS_TOO_MANY: | ||
153 | - case DISAS_UPDATE: | ||
154 | + case DISAS_UPDATE_EXIT: | ||
155 | gen_set_pc_im(dc, dc->base.pc_next); | ||
156 | /* fall through */ | ||
157 | default: | ||
158 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
159 | case DISAS_JUMP: | ||
160 | gen_goto_ptr(); | ||
161 | break; | ||
162 | - case DISAS_UPDATE: | ||
163 | + case DISAS_UPDATE_EXIT: | ||
164 | gen_set_pc_im(dc, dc->base.pc_next); | ||
165 | /* fall through */ | ||
166 | default: | ||
167 | -- | 692 | -- |
168 | 2.20.1 | 693 | 2.20.1 |
169 | 694 | ||
170 | 695 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We will shortly need this in mte_helper.c as well. | 3 | Replace all uses of neon_load/store_reg64 within translate-neon.c.inc. |
4 | 4 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20201030022618.785675-9-richard.henderson@linaro.org | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20200626033144.790098-22-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 9 | --- |
10 | target/arm/internals.h | 36 ++++++++++++++++++++++++++++++++++++ | 10 | target/arm/translate.c | 26 +++++++++ |
11 | target/arm/helper.c | 36 ------------------------------------ | 11 | target/arm/translate-neon.c.inc | 94 ++++++++++++++++----------------- |
12 | 2 files changed, 36 insertions(+), 36 deletions(-) | 12 | 2 files changed, 73 insertions(+), 47 deletions(-) |
13 | 13 | ||
14 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 14 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/internals.h | 16 | --- a/target/arm/translate.c |
17 | +++ b/target/arm/internals.h | 17 | +++ b/target/arm/translate.c |
18 | @@ -XXX,XX +XXX,XX @@ static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) | 18 | @@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) |
19 | } | 19 | } |
20 | } | 20 | } |
21 | 21 | ||
22 | +/* Return the exception level which controls this address translation regime */ | 22 | +static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) |
23 | +static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | ||
24 | +{ | 23 | +{ |
25 | + switch (mmu_idx) { | 24 | + long off = neon_element_offset(reg, ele, memop); |
26 | + case ARMMMUIdx_E20_0: | 25 | + |
27 | + case ARMMMUIdx_E20_2: | 26 | + switch (memop) { |
28 | + case ARMMMUIdx_E20_2_PAN: | 27 | + case MO_Q: |
29 | + case ARMMMUIdx_Stage2: | 28 | + tcg_gen_ld_i64(dest, cpu_env, off); |
30 | + case ARMMMUIdx_E2: | 29 | + break; |
31 | + return 2; | ||
32 | + case ARMMMUIdx_SE3: | ||
33 | + return 3; | ||
34 | + case ARMMMUIdx_SE10_0: | ||
35 | + return arm_el_is_aa64(env, 3) ? 1 : 3; | ||
36 | + case ARMMMUIdx_SE10_1: | ||
37 | + case ARMMMUIdx_SE10_1_PAN: | ||
38 | + case ARMMMUIdx_Stage1_E0: | ||
39 | + case ARMMMUIdx_Stage1_E1: | ||
40 | + case ARMMMUIdx_Stage1_E1_PAN: | ||
41 | + case ARMMMUIdx_E10_0: | ||
42 | + case ARMMMUIdx_E10_1: | ||
43 | + case ARMMMUIdx_E10_1_PAN: | ||
44 | + case ARMMMUIdx_MPrivNegPri: | ||
45 | + case ARMMMUIdx_MUserNegPri: | ||
46 | + case ARMMMUIdx_MPriv: | ||
47 | + case ARMMMUIdx_MUser: | ||
48 | + case ARMMMUIdx_MSPrivNegPri: | ||
49 | + case ARMMMUIdx_MSUserNegPri: | ||
50 | + case ARMMMUIdx_MSPriv: | ||
51 | + case ARMMMUIdx_MSUser: | ||
52 | + return 1; | ||
53 | + default: | 30 | + default: |
54 | + g_assert_not_reached(); | 31 | + g_assert_not_reached(); |
55 | + } | 32 | + } |
56 | +} | 33 | +} |
57 | + | 34 | + |
58 | /* Return the FSR value for a debug exception (watchpoint, hardware | 35 | static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) |
59 | * breakpoint or BKPT insn) targeting the specified exception level. | 36 | { |
60 | */ | 37 | long off = neon_element_offset(reg, ele, memop); |
61 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 38 | @@ -XXX,XX +XXX,XX @@ static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) |
39 | } | ||
40 | } | ||
41 | |||
42 | +static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) | ||
43 | +{ | ||
44 | + long off = neon_element_offset(reg, ele, memop); | ||
45 | + | ||
46 | + switch (memop) { | ||
47 | + case MO_64: | ||
48 | + tcg_gen_st_i64(src, cpu_env, off); | ||
49 | + break; | ||
50 | + default: | ||
51 | + g_assert_not_reached(); | ||
52 | + } | ||
53 | +} | ||
54 | + | ||
55 | static TCGv_ptr vfp_reg_ptr(bool dp, int reg) | ||
56 | { | ||
57 | TCGv_ptr ret = tcg_temp_new_ptr(); | ||
58 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | ||
62 | index XXXXXXX..XXXXXXX 100644 | 59 | index XXXXXXX..XXXXXXX 100644 |
63 | --- a/target/arm/helper.c | 60 | --- a/target/arm/translate-neon.c.inc |
64 | +++ b/target/arm/helper.c | 61 | +++ b/target/arm/translate-neon.c.inc |
65 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs) | 62 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a, |
63 | for (pass = 0; pass < a->q + 1; pass++) { | ||
64 | TCGv_i64 tmp = tcg_temp_new_i64(); | ||
65 | |||
66 | - neon_load_reg64(tmp, a->vm + pass); | ||
67 | + read_neon_element64(tmp, a->vm, pass, MO_64); | ||
68 | fn(tmp, cpu_env, tmp, constimm); | ||
69 | - neon_store_reg64(tmp, a->vd + pass); | ||
70 | + write_neon_element64(tmp, a->vd, pass, MO_64); | ||
71 | tcg_temp_free_i64(tmp); | ||
72 | } | ||
73 | tcg_temp_free_i64(constimm); | ||
74 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a, | ||
75 | rd = tcg_temp_new_i32(); | ||
76 | |||
77 | /* Load both inputs first to avoid potential overwrite if rm == rd */ | ||
78 | - neon_load_reg64(rm1, a->vm); | ||
79 | - neon_load_reg64(rm2, a->vm + 1); | ||
80 | + read_neon_element64(rm1, a->vm, 0, MO_64); | ||
81 | + read_neon_element64(rm2, a->vm, 1, MO_64); | ||
82 | |||
83 | shiftfn(rm1, rm1, constimm); | ||
84 | narrowfn(rd, cpu_env, rm1); | ||
85 | @@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, | ||
86 | tcg_gen_shli_i64(tmp, tmp, a->shift); | ||
87 | tcg_gen_andi_i64(tmp, tmp, ~widen_mask); | ||
88 | } | ||
89 | - neon_store_reg64(tmp, a->vd); | ||
90 | + write_neon_element64(tmp, a->vd, 0, MO_64); | ||
91 | |||
92 | widenfn(tmp, rm1); | ||
93 | tcg_temp_free_i32(rm1); | ||
94 | @@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, | ||
95 | tcg_gen_shli_i64(tmp, tmp, a->shift); | ||
96 | tcg_gen_andi_i64(tmp, tmp, ~widen_mask); | ||
97 | } | ||
98 | - neon_store_reg64(tmp, a->vd + 1); | ||
99 | + write_neon_element64(tmp, a->vd, 1, MO_64); | ||
100 | tcg_temp_free_i64(tmp); | ||
101 | return true; | ||
66 | } | 102 | } |
67 | #endif /* !CONFIG_USER_ONLY */ | 103 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, |
68 | 104 | rm_64 = tcg_temp_new_i64(); | |
69 | -/* Return the exception level which controls this address translation regime */ | 105 | |
70 | -static uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | 106 | if (src1_wide) { |
71 | -{ | 107 | - neon_load_reg64(rn0_64, a->vn); |
72 | - switch (mmu_idx) { | 108 | + read_neon_element64(rn0_64, a->vn, 0, MO_64); |
73 | - case ARMMMUIdx_E20_0: | 109 | } else { |
74 | - case ARMMMUIdx_E20_2: | 110 | TCGv_i32 tmp = tcg_temp_new_i32(); |
75 | - case ARMMMUIdx_E20_2_PAN: | 111 | read_neon_element32(tmp, a->vn, 0, MO_32); |
76 | - case ARMMMUIdx_Stage2: | 112 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, |
77 | - case ARMMMUIdx_E2: | 113 | * avoid incorrect results if a narrow input overlaps with the result. |
78 | - return 2; | 114 | */ |
79 | - case ARMMMUIdx_SE3: | 115 | if (src1_wide) { |
80 | - return 3; | 116 | - neon_load_reg64(rn1_64, a->vn + 1); |
81 | - case ARMMMUIdx_SE10_0: | 117 | + read_neon_element64(rn1_64, a->vn, 1, MO_64); |
82 | - return arm_el_is_aa64(env, 3) ? 1 : 3; | 118 | } else { |
83 | - case ARMMMUIdx_SE10_1: | 119 | TCGv_i32 tmp = tcg_temp_new_i32(); |
84 | - case ARMMMUIdx_SE10_1_PAN: | 120 | read_neon_element32(tmp, a->vn, 1, MO_32); |
85 | - case ARMMMUIdx_Stage1_E0: | 121 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, |
86 | - case ARMMMUIdx_Stage1_E1: | 122 | rm = tcg_temp_new_i32(); |
87 | - case ARMMMUIdx_Stage1_E1_PAN: | 123 | read_neon_element32(rm, a->vm, 1, MO_32); |
88 | - case ARMMMUIdx_E10_0: | 124 | |
89 | - case ARMMMUIdx_E10_1: | 125 | - neon_store_reg64(rn0_64, a->vd); |
90 | - case ARMMMUIdx_E10_1_PAN: | 126 | + write_neon_element64(rn0_64, a->vd, 0, MO_64); |
91 | - case ARMMMUIdx_MPrivNegPri: | 127 | |
92 | - case ARMMMUIdx_MUserNegPri: | 128 | widenfn(rm_64, rm); |
93 | - case ARMMMUIdx_MPriv: | 129 | tcg_temp_free_i32(rm); |
94 | - case ARMMMUIdx_MUser: | 130 | opfn(rn1_64, rn1_64, rm_64); |
95 | - case ARMMMUIdx_MSPrivNegPri: | 131 | - neon_store_reg64(rn1_64, a->vd + 1); |
96 | - case ARMMMUIdx_MSUserNegPri: | 132 | + write_neon_element64(rn1_64, a->vd, 1, MO_64); |
97 | - case ARMMMUIdx_MSPriv: | 133 | |
98 | - case ARMMMUIdx_MSUser: | 134 | tcg_temp_free_i64(rn0_64); |
99 | - return 1; | 135 | tcg_temp_free_i64(rn1_64); |
100 | - default: | 136 | @@ -XXX,XX +XXX,XX @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a, |
101 | - g_assert_not_reached(); | 137 | rd0 = tcg_temp_new_i32(); |
102 | - } | 138 | rd1 = tcg_temp_new_i32(); |
103 | -} | 139 | |
104 | - | 140 | - neon_load_reg64(rn_64, a->vn); |
105 | uint64_t arm_sctlr(CPUARMState *env, int el) | 141 | - neon_load_reg64(rm_64, a->vm); |
106 | { | 142 | + read_neon_element64(rn_64, a->vn, 0, MO_64); |
107 | /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ | 143 | + read_neon_element64(rm_64, a->vm, 0, MO_64); |
144 | |||
145 | opfn(rn_64, rn_64, rm_64); | ||
146 | |||
147 | narrowfn(rd0, rn_64); | ||
148 | |||
149 | - neon_load_reg64(rn_64, a->vn + 1); | ||
150 | - neon_load_reg64(rm_64, a->vm + 1); | ||
151 | + read_neon_element64(rn_64, a->vn, 1, MO_64); | ||
152 | + read_neon_element64(rm_64, a->vm, 1, MO_64); | ||
153 | |||
154 | opfn(rn_64, rn_64, rm_64); | ||
155 | |||
156 | @@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a, | ||
157 | /* Don't store results until after all loads: they might overlap */ | ||
158 | if (accfn) { | ||
159 | tmp = tcg_temp_new_i64(); | ||
160 | - neon_load_reg64(tmp, a->vd); | ||
161 | + read_neon_element64(tmp, a->vd, 0, MO_64); | ||
162 | accfn(tmp, tmp, rd0); | ||
163 | - neon_store_reg64(tmp, a->vd); | ||
164 | - neon_load_reg64(tmp, a->vd + 1); | ||
165 | + write_neon_element64(tmp, a->vd, 0, MO_64); | ||
166 | + read_neon_element64(tmp, a->vd, 1, MO_64); | ||
167 | accfn(tmp, tmp, rd1); | ||
168 | - neon_store_reg64(tmp, a->vd + 1); | ||
169 | + write_neon_element64(tmp, a->vd, 1, MO_64); | ||
170 | tcg_temp_free_i64(tmp); | ||
171 | } else { | ||
172 | - neon_store_reg64(rd0, a->vd); | ||
173 | - neon_store_reg64(rd1, a->vd + 1); | ||
174 | + write_neon_element64(rd0, a->vd, 0, MO_64); | ||
175 | + write_neon_element64(rd1, a->vd, 1, MO_64); | ||
176 | } | ||
177 | |||
178 | tcg_temp_free_i64(rd0); | ||
179 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a, | ||
180 | |||
181 | if (accfn) { | ||
182 | TCGv_i64 t64 = tcg_temp_new_i64(); | ||
183 | - neon_load_reg64(t64, a->vd); | ||
184 | + read_neon_element64(t64, a->vd, 0, MO_64); | ||
185 | accfn(t64, t64, rn0_64); | ||
186 | - neon_store_reg64(t64, a->vd); | ||
187 | - neon_load_reg64(t64, a->vd + 1); | ||
188 | + write_neon_element64(t64, a->vd, 0, MO_64); | ||
189 | + read_neon_element64(t64, a->vd, 1, MO_64); | ||
190 | accfn(t64, t64, rn1_64); | ||
191 | - neon_store_reg64(t64, a->vd + 1); | ||
192 | + write_neon_element64(t64, a->vd, 1, MO_64); | ||
193 | tcg_temp_free_i64(t64); | ||
194 | } else { | ||
195 | - neon_store_reg64(rn0_64, a->vd); | ||
196 | - neon_store_reg64(rn1_64, a->vd + 1); | ||
197 | + write_neon_element64(rn0_64, a->vd, 0, MO_64); | ||
198 | + write_neon_element64(rn1_64, a->vd, 1, MO_64); | ||
199 | } | ||
200 | tcg_temp_free_i64(rn0_64); | ||
201 | tcg_temp_free_i64(rn1_64); | ||
202 | @@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) | ||
203 | right = tcg_temp_new_i64(); | ||
204 | dest = tcg_temp_new_i64(); | ||
205 | |||
206 | - neon_load_reg64(right, a->vn); | ||
207 | - neon_load_reg64(left, a->vm); | ||
208 | + read_neon_element64(right, a->vn, 0, MO_64); | ||
209 | + read_neon_element64(left, a->vm, 0, MO_64); | ||
210 | tcg_gen_extract2_i64(dest, right, left, a->imm * 8); | ||
211 | - neon_store_reg64(dest, a->vd); | ||
212 | + write_neon_element64(dest, a->vd, 0, MO_64); | ||
213 | |||
214 | tcg_temp_free_i64(left); | ||
215 | tcg_temp_free_i64(right); | ||
216 | @@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) | ||
217 | destright = tcg_temp_new_i64(); | ||
218 | |||
219 | if (a->imm < 8) { | ||
220 | - neon_load_reg64(right, a->vn); | ||
221 | - neon_load_reg64(middle, a->vn + 1); | ||
222 | + read_neon_element64(right, a->vn, 0, MO_64); | ||
223 | + read_neon_element64(middle, a->vn, 1, MO_64); | ||
224 | tcg_gen_extract2_i64(destright, right, middle, a->imm * 8); | ||
225 | - neon_load_reg64(left, a->vm); | ||
226 | + read_neon_element64(left, a->vm, 0, MO_64); | ||
227 | tcg_gen_extract2_i64(destleft, middle, left, a->imm * 8); | ||
228 | } else { | ||
229 | - neon_load_reg64(right, a->vn + 1); | ||
230 | - neon_load_reg64(middle, a->vm); | ||
231 | + read_neon_element64(right, a->vn, 1, MO_64); | ||
232 | + read_neon_element64(middle, a->vm, 0, MO_64); | ||
233 | tcg_gen_extract2_i64(destright, right, middle, (a->imm - 8) * 8); | ||
234 | - neon_load_reg64(left, a->vm + 1); | ||
235 | + read_neon_element64(left, a->vm, 1, MO_64); | ||
236 | tcg_gen_extract2_i64(destleft, middle, left, (a->imm - 8) * 8); | ||
237 | } | ||
238 | |||
239 | - neon_store_reg64(destright, a->vd); | ||
240 | - neon_store_reg64(destleft, a->vd + 1); | ||
241 | + write_neon_element64(destright, a->vd, 0, MO_64); | ||
242 | + write_neon_element64(destleft, a->vd, 1, MO_64); | ||
243 | |||
244 | tcg_temp_free_i64(destright); | ||
245 | tcg_temp_free_i64(destleft); | ||
246 | @@ -XXX,XX +XXX,XX @@ static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a, | ||
247 | |||
248 | if (accfn) { | ||
249 | TCGv_i64 tmp64 = tcg_temp_new_i64(); | ||
250 | - neon_load_reg64(tmp64, a->vd + pass); | ||
251 | + read_neon_element64(tmp64, a->vd, pass, MO_64); | ||
252 | accfn(rd_64, tmp64, rd_64); | ||
253 | tcg_temp_free_i64(tmp64); | ||
254 | } | ||
255 | - neon_store_reg64(rd_64, a->vd + pass); | ||
256 | + write_neon_element64(rd_64, a->vd, pass, MO_64); | ||
257 | tcg_temp_free_i64(rd_64); | ||
258 | } | ||
259 | return true; | ||
260 | @@ -XXX,XX +XXX,XX @@ static bool do_vmovn(DisasContext *s, arg_2misc *a, | ||
261 | rd0 = tcg_temp_new_i32(); | ||
262 | rd1 = tcg_temp_new_i32(); | ||
263 | |||
264 | - neon_load_reg64(rm, a->vm); | ||
265 | + read_neon_element64(rm, a->vm, 0, MO_64); | ||
266 | narrowfn(rd0, cpu_env, rm); | ||
267 | - neon_load_reg64(rm, a->vm + 1); | ||
268 | + read_neon_element64(rm, a->vm, 1, MO_64); | ||
269 | narrowfn(rd1, cpu_env, rm); | ||
270 | write_neon_element32(rd0, a->vd, 0, MO_32); | ||
271 | write_neon_element32(rd1, a->vd, 1, MO_32); | ||
272 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a) | ||
273 | |||
274 | widenfn(rd, rm0); | ||
275 | tcg_gen_shli_i64(rd, rd, 8 << a->size); | ||
276 | - neon_store_reg64(rd, a->vd); | ||
277 | + write_neon_element64(rd, a->vd, 0, MO_64); | ||
278 | widenfn(rd, rm1); | ||
279 | tcg_gen_shli_i64(rd, rd, 8 << a->size); | ||
280 | - neon_store_reg64(rd, a->vd + 1); | ||
281 | + write_neon_element64(rd, a->vd, 1, MO_64); | ||
282 | |||
283 | tcg_temp_free_i64(rd); | ||
284 | tcg_temp_free_i32(rm0); | ||
285 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSWP(DisasContext *s, arg_2misc *a) | ||
286 | rm = tcg_temp_new_i64(); | ||
287 | rd = tcg_temp_new_i64(); | ||
288 | for (pass = 0; pass < (a->q ? 2 : 1); pass++) { | ||
289 | - neon_load_reg64(rm, a->vm + pass); | ||
290 | - neon_load_reg64(rd, a->vd + pass); | ||
291 | - neon_store_reg64(rm, a->vd + pass); | ||
292 | - neon_store_reg64(rd, a->vm + pass); | ||
293 | + read_neon_element64(rm, a->vm, pass, MO_64); | ||
294 | + read_neon_element64(rd, a->vd, pass, MO_64); | ||
295 | + write_neon_element64(rm, a->vd, pass, MO_64); | ||
296 | + write_neon_element64(rd, a->vm, pass, MO_64); | ||
297 | } | ||
298 | tcg_temp_free_i64(rm); | ||
299 | tcg_temp_free_i64(rd); | ||
108 | -- | 300 | -- |
109 | 2.20.1 | 301 | 2.20.1 |
110 | 302 | ||
111 | 303 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Add an option that writes back the PC, like DISAS_UPDATE_EXIT, | 3 | The only uses of this function are for loading VFP |
4 | but does not exit back to the main loop. | 4 | double-precision values, and nothing to do with NEON. |
5 | 5 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20201030022618.785675-10-richard.henderson@linaro.org | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20200626033144.790098-7-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | target/arm/translate.h | 2 ++ | 11 | target/arm/translate.c | 8 ++-- |
12 | target/arm/translate-a64.c | 3 +++ | 12 | target/arm/translate-vfp.c.inc | 84 +++++++++++++++++----------------- |
13 | target/arm/translate.c | 4 ++++ | 13 | 2 files changed, 46 insertions(+), 46 deletions(-) |
14 | 3 files changed, 9 insertions(+) | 14 | |
15 | |||
16 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/translate.h | ||
19 | +++ b/target/arm/translate.h | ||
20 | @@ -XXX,XX +XXX,XX @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) | ||
21 | * return from cpu_tb_exec. | ||
22 | */ | ||
23 | #define DISAS_EXIT DISAS_TARGET_9 | ||
24 | +/* CPU state was modified dynamically; no need to exit, but do not chain. */ | ||
25 | +#define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10 | ||
26 | |||
27 | #ifdef TARGET_AARCH64 | ||
28 | void a64_translate_init(void); | ||
29 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/translate-a64.c | ||
32 | +++ b/target/arm/translate-a64.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
34 | case DISAS_EXIT: | ||
35 | tcg_gen_exit_tb(NULL, 0); | ||
36 | break; | ||
37 | + case DISAS_UPDATE_NOCHAIN: | ||
38 | + gen_a64_set_pc_im(dc->base.pc_next); | ||
39 | + /* fall through */ | ||
40 | case DISAS_JUMP: | ||
41 | tcg_gen_lookup_and_goto_ptr(); | ||
42 | break; | ||
43 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 15 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
44 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
45 | --- a/target/arm/translate.c | 17 | --- a/target/arm/translate.c |
46 | +++ b/target/arm/translate.c | 18 | +++ b/target/arm/translate.c |
47 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | 19 | @@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg) |
48 | case DISAS_NEXT: | 20 | } |
49 | case DISAS_TOO_MANY: | 21 | } |
50 | case DISAS_UPDATE_EXIT: | 22 | |
51 | + case DISAS_UPDATE_NOCHAIN: | 23 | -static inline void neon_load_reg64(TCGv_i64 var, int reg) |
52 | gen_set_pc_im(dc, dc->base.pc_next); | 24 | +static inline void vfp_load_reg64(TCGv_i64 var, int reg) |
53 | /* fall through */ | 25 | { |
54 | default: | 26 | - tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); |
55 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | 27 | + tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg)); |
56 | case DISAS_TOO_MANY: | 28 | } |
57 | gen_goto_tb(dc, 1, dc->base.pc_next); | 29 | |
58 | break; | 30 | -static inline void neon_store_reg64(TCGv_i64 var, int reg) |
59 | + case DISAS_UPDATE_NOCHAIN: | 31 | +static inline void vfp_store_reg64(TCGv_i64 var, int reg) |
60 | + gen_set_pc_im(dc, dc->base.pc_next); | 32 | { |
61 | + /* fall through */ | 33 | - tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); |
62 | case DISAS_JUMP: | 34 | + tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg)); |
63 | gen_goto_ptr(); | 35 | } |
64 | break; | 36 | |
37 | static inline void vfp_load_reg32(TCGv_i32 var, int reg) | ||
38 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/target/arm/translate-vfp.c.inc | ||
41 | +++ b/target/arm/translate-vfp.c.inc | ||
42 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | ||
43 | tcg_gen_ext_i32_i64(nf, cpu_NF); | ||
44 | tcg_gen_ext_i32_i64(vf, cpu_VF); | ||
45 | |||
46 | - neon_load_reg64(frn, rn); | ||
47 | - neon_load_reg64(frm, rm); | ||
48 | + vfp_load_reg64(frn, rn); | ||
49 | + vfp_load_reg64(frm, rm); | ||
50 | switch (a->cc) { | ||
51 | case 0: /* eq: Z */ | ||
52 | tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero, | ||
53 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | ||
54 | tcg_temp_free_i64(tmp); | ||
55 | break; | ||
56 | } | ||
57 | - neon_store_reg64(dest, rd); | ||
58 | + vfp_store_reg64(dest, rd); | ||
59 | tcg_temp_free_i64(frn); | ||
60 | tcg_temp_free_i64(frm); | ||
61 | tcg_temp_free_i64(dest); | ||
62 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) | ||
63 | TCGv_i64 tcg_res; | ||
64 | tcg_op = tcg_temp_new_i64(); | ||
65 | tcg_res = tcg_temp_new_i64(); | ||
66 | - neon_load_reg64(tcg_op, rm); | ||
67 | + vfp_load_reg64(tcg_op, rm); | ||
68 | gen_helper_rintd(tcg_res, tcg_op, fpst); | ||
69 | - neon_store_reg64(tcg_res, rd); | ||
70 | + vfp_store_reg64(tcg_res, rd); | ||
71 | tcg_temp_free_i64(tcg_op); | ||
72 | tcg_temp_free_i64(tcg_res); | ||
73 | } else { | ||
74 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | ||
75 | tcg_double = tcg_temp_new_i64(); | ||
76 | tcg_res = tcg_temp_new_i64(); | ||
77 | tcg_tmp = tcg_temp_new_i32(); | ||
78 | - neon_load_reg64(tcg_double, rm); | ||
79 | + vfp_load_reg64(tcg_double, rm); | ||
80 | if (is_signed) { | ||
81 | gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst); | ||
82 | } else { | ||
83 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a) | ||
84 | tmp = tcg_temp_new_i64(); | ||
85 | if (a->l) { | ||
86 | gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); | ||
87 | - neon_store_reg64(tmp, a->vd); | ||
88 | + vfp_store_reg64(tmp, a->vd); | ||
89 | } else { | ||
90 | - neon_load_reg64(tmp, a->vd); | ||
91 | + vfp_load_reg64(tmp, a->vd); | ||
92 | gen_aa32_st64(s, tmp, addr, get_mem_index(s)); | ||
93 | } | ||
94 | tcg_temp_free_i64(tmp); | ||
95 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a) | ||
96 | if (a->l) { | ||
97 | /* load */ | ||
98 | gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); | ||
99 | - neon_store_reg64(tmp, a->vd + i); | ||
100 | + vfp_store_reg64(tmp, a->vd + i); | ||
101 | } else { | ||
102 | /* store */ | ||
103 | - neon_load_reg64(tmp, a->vd + i); | ||
104 | + vfp_load_reg64(tmp, a->vd + i); | ||
105 | gen_aa32_st64(s, tmp, addr, get_mem_index(s)); | ||
106 | } | ||
107 | tcg_gen_addi_i32(addr, addr, offset); | ||
108 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn, | ||
109 | fd = tcg_temp_new_i64(); | ||
110 | fpst = fpstatus_ptr(FPST_FPCR); | ||
111 | |||
112 | - neon_load_reg64(f0, vn); | ||
113 | - neon_load_reg64(f1, vm); | ||
114 | + vfp_load_reg64(f0, vn); | ||
115 | + vfp_load_reg64(f1, vm); | ||
116 | |||
117 | for (;;) { | ||
118 | if (reads_vd) { | ||
119 | - neon_load_reg64(fd, vd); | ||
120 | + vfp_load_reg64(fd, vd); | ||
121 | } | ||
122 | fn(fd, f0, f1, fpst); | ||
123 | - neon_store_reg64(fd, vd); | ||
124 | + vfp_store_reg64(fd, vd); | ||
125 | |||
126 | if (veclen == 0) { | ||
127 | break; | ||
128 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn, | ||
129 | veclen--; | ||
130 | vd = vfp_advance_dreg(vd, delta_d); | ||
131 | vn = vfp_advance_dreg(vn, delta_d); | ||
132 | - neon_load_reg64(f0, vn); | ||
133 | + vfp_load_reg64(f0, vn); | ||
134 | if (delta_m) { | ||
135 | vm = vfp_advance_dreg(vm, delta_m); | ||
136 | - neon_load_reg64(f1, vm); | ||
137 | + vfp_load_reg64(f1, vm); | ||
138 | } | ||
139 | } | ||
140 | |||
141 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm) | ||
142 | f0 = tcg_temp_new_i64(); | ||
143 | fd = tcg_temp_new_i64(); | ||
144 | |||
145 | - neon_load_reg64(f0, vm); | ||
146 | + vfp_load_reg64(f0, vm); | ||
147 | |||
148 | for (;;) { | ||
149 | fn(fd, f0); | ||
150 | - neon_store_reg64(fd, vd); | ||
151 | + vfp_store_reg64(fd, vd); | ||
152 | |||
153 | if (veclen == 0) { | ||
154 | break; | ||
155 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm) | ||
156 | /* single source one-many */ | ||
157 | while (veclen--) { | ||
158 | vd = vfp_advance_dreg(vd, delta_d); | ||
159 | - neon_store_reg64(fd, vd); | ||
160 | + vfp_store_reg64(fd, vd); | ||
161 | } | ||
162 | break; | ||
163 | } | ||
164 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm) | ||
165 | veclen--; | ||
166 | vd = vfp_advance_dreg(vd, delta_d); | ||
167 | vd = vfp_advance_dreg(vm, delta_m); | ||
168 | - neon_load_reg64(f0, vm); | ||
169 | + vfp_load_reg64(f0, vm); | ||
170 | } | ||
171 | |||
172 | tcg_temp_free_i64(f0); | ||
173 | @@ -XXX,XX +XXX,XX @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d) | ||
174 | vm = tcg_temp_new_i64(); | ||
175 | vd = tcg_temp_new_i64(); | ||
176 | |||
177 | - neon_load_reg64(vn, a->vn); | ||
178 | - neon_load_reg64(vm, a->vm); | ||
179 | + vfp_load_reg64(vn, a->vn); | ||
180 | + vfp_load_reg64(vm, a->vm); | ||
181 | if (neg_n) { | ||
182 | /* VFNMS, VFMS */ | ||
183 | gen_helper_vfp_negd(vn, vn); | ||
184 | } | ||
185 | - neon_load_reg64(vd, a->vd); | ||
186 | + vfp_load_reg64(vd, a->vd); | ||
187 | if (neg_d) { | ||
188 | /* VFNMA, VFNMS */ | ||
189 | gen_helper_vfp_negd(vd, vd); | ||
190 | } | ||
191 | fpst = fpstatus_ptr(FPST_FPCR); | ||
192 | gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst); | ||
193 | - neon_store_reg64(vd, a->vd); | ||
194 | + vfp_store_reg64(vd, a->vd); | ||
195 | |||
196 | tcg_temp_free_ptr(fpst); | ||
197 | tcg_temp_free_i64(vn); | ||
198 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) | ||
199 | fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm)); | ||
200 | |||
201 | for (;;) { | ||
202 | - neon_store_reg64(fd, vd); | ||
203 | + vfp_store_reg64(fd, vd); | ||
204 | |||
205 | if (veclen == 0) { | ||
206 | break; | ||
207 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a) | ||
208 | vd = tcg_temp_new_i64(); | ||
209 | vm = tcg_temp_new_i64(); | ||
210 | |||
211 | - neon_load_reg64(vd, a->vd); | ||
212 | + vfp_load_reg64(vd, a->vd); | ||
213 | if (a->z) { | ||
214 | tcg_gen_movi_i64(vm, 0); | ||
215 | } else { | ||
216 | - neon_load_reg64(vm, a->vm); | ||
217 | + vfp_load_reg64(vm, a->vm); | ||
218 | } | ||
219 | |||
220 | if (a->e) { | ||
221 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a) | ||
222 | tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); | ||
223 | vd = tcg_temp_new_i64(); | ||
224 | gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode); | ||
225 | - neon_store_reg64(vd, a->vd); | ||
226 | + vfp_store_reg64(vd, a->vd); | ||
227 | tcg_temp_free_i32(ahp_mode); | ||
228 | tcg_temp_free_ptr(fpst); | ||
229 | tcg_temp_free_i32(tmp); | ||
230 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a) | ||
231 | tmp = tcg_temp_new_i32(); | ||
232 | vm = tcg_temp_new_i64(); | ||
233 | |||
234 | - neon_load_reg64(vm, a->vm); | ||
235 | + vfp_load_reg64(vm, a->vm); | ||
236 | gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode); | ||
237 | tcg_temp_free_i64(vm); | ||
238 | tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); | ||
239 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a) | ||
240 | } | ||
241 | |||
242 | tmp = tcg_temp_new_i64(); | ||
243 | - neon_load_reg64(tmp, a->vm); | ||
244 | + vfp_load_reg64(tmp, a->vm); | ||
245 | fpst = fpstatus_ptr(FPST_FPCR); | ||
246 | gen_helper_rintd(tmp, tmp, fpst); | ||
247 | - neon_store_reg64(tmp, a->vd); | ||
248 | + vfp_store_reg64(tmp, a->vd); | ||
249 | tcg_temp_free_ptr(fpst); | ||
250 | tcg_temp_free_i64(tmp); | ||
251 | return true; | ||
252 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a) | ||
253 | } | ||
254 | |||
255 | tmp = tcg_temp_new_i64(); | ||
256 | - neon_load_reg64(tmp, a->vm); | ||
257 | + vfp_load_reg64(tmp, a->vm); | ||
258 | fpst = fpstatus_ptr(FPST_FPCR); | ||
259 | tcg_rmode = tcg_const_i32(float_round_to_zero); | ||
260 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
261 | gen_helper_rintd(tmp, tmp, fpst); | ||
262 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
263 | - neon_store_reg64(tmp, a->vd); | ||
264 | + vfp_store_reg64(tmp, a->vd); | ||
265 | tcg_temp_free_ptr(fpst); | ||
266 | tcg_temp_free_i64(tmp); | ||
267 | tcg_temp_free_i32(tcg_rmode); | ||
268 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a) | ||
269 | } | ||
270 | |||
271 | tmp = tcg_temp_new_i64(); | ||
272 | - neon_load_reg64(tmp, a->vm); | ||
273 | + vfp_load_reg64(tmp, a->vm); | ||
274 | fpst = fpstatus_ptr(FPST_FPCR); | ||
275 | gen_helper_rintd_exact(tmp, tmp, fpst); | ||
276 | - neon_store_reg64(tmp, a->vd); | ||
277 | + vfp_store_reg64(tmp, a->vd); | ||
278 | tcg_temp_free_ptr(fpst); | ||
279 | tcg_temp_free_i64(tmp); | ||
280 | return true; | ||
281 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a) | ||
282 | vd = tcg_temp_new_i64(); | ||
283 | vfp_load_reg32(vm, a->vm); | ||
284 | gen_helper_vfp_fcvtds(vd, vm, cpu_env); | ||
285 | - neon_store_reg64(vd, a->vd); | ||
286 | + vfp_store_reg64(vd, a->vd); | ||
287 | tcg_temp_free_i32(vm); | ||
288 | tcg_temp_free_i64(vd); | ||
289 | return true; | ||
290 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a) | ||
291 | |||
292 | vd = tcg_temp_new_i32(); | ||
293 | vm = tcg_temp_new_i64(); | ||
294 | - neon_load_reg64(vm, a->vm); | ||
295 | + vfp_load_reg64(vm, a->vm); | ||
296 | gen_helper_vfp_fcvtsd(vd, vm, cpu_env); | ||
297 | vfp_store_reg32(vd, a->vd); | ||
298 | tcg_temp_free_i32(vd); | ||
299 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a) | ||
300 | /* u32 -> f64 */ | ||
301 | gen_helper_vfp_uitod(vd, vm, fpst); | ||
302 | } | ||
303 | - neon_store_reg64(vd, a->vd); | ||
304 | + vfp_store_reg64(vd, a->vd); | ||
305 | tcg_temp_free_i32(vm); | ||
306 | tcg_temp_free_i64(vd); | ||
307 | tcg_temp_free_ptr(fpst); | ||
308 | @@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) | ||
309 | |||
310 | vm = tcg_temp_new_i64(); | ||
311 | vd = tcg_temp_new_i32(); | ||
312 | - neon_load_reg64(vm, a->vm); | ||
313 | + vfp_load_reg64(vm, a->vm); | ||
314 | gen_helper_vjcvt(vd, vm, cpu_env); | ||
315 | vfp_store_reg32(vd, a->vd); | ||
316 | tcg_temp_free_i64(vm); | ||
317 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a) | ||
318 | frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); | ||
319 | |||
320 | vd = tcg_temp_new_i64(); | ||
321 | - neon_load_reg64(vd, a->vd); | ||
322 | + vfp_load_reg64(vd, a->vd); | ||
323 | |||
324 | fpst = fpstatus_ptr(FPST_FPCR); | ||
325 | shift = tcg_const_i32(frac_bits); | ||
326 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a) | ||
327 | g_assert_not_reached(); | ||
328 | } | ||
329 | |||
330 | - neon_store_reg64(vd, a->vd); | ||
331 | + vfp_store_reg64(vd, a->vd); | ||
332 | tcg_temp_free_i64(vd); | ||
333 | tcg_temp_free_i32(shift); | ||
334 | tcg_temp_free_ptr(fpst); | ||
335 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) | ||
336 | fpst = fpstatus_ptr(FPST_FPCR); | ||
337 | vm = tcg_temp_new_i64(); | ||
338 | vd = tcg_temp_new_i32(); | ||
339 | - neon_load_reg64(vm, a->vm); | ||
340 | + vfp_load_reg64(vm, a->vm); | ||
341 | |||
342 | if (a->s) { | ||
343 | if (a->rz) { | ||
65 | -- | 344 | -- |
66 | 2.20.1 | 345 | 2.20.1 |
67 | 346 | ||
68 | 347 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Look up the physical address for the given virtual address, | 3 | In both cases, we can sink the write-back and perform |
4 | convert that to a tag physical address, and finally return | 4 | the accumulate into the normal destination temps. |
5 | the host address that backs it. | ||
6 | 5 | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20200626033144.790098-45-richard.henderson@linaro.org | 7 | Message-id: 20201030022618.785675-11-richard.henderson@linaro.org |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 10 | --- |
12 | target/arm/mte_helper.c | 131 ++++++++++++++++++++++++++++++++++++++++ | 11 | target/arm/translate-neon.c.inc | 23 +++++++++-------------- |
13 | 1 file changed, 131 insertions(+) | 12 | 1 file changed, 9 insertions(+), 14 deletions(-) |
14 | 13 | ||
15 | diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c | 14 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc |
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/mte_helper.c | 16 | --- a/target/arm/translate-neon.c.inc |
18 | +++ b/target/arm/mte_helper.c | 17 | +++ b/target/arm/translate-neon.c.inc |
19 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a, |
20 | #include "cpu.h" | 19 | if (accfn) { |
21 | #include "internals.h" | 20 | tmp = tcg_temp_new_i64(); |
22 | #include "exec/exec-all.h" | 21 | read_neon_element64(tmp, a->vd, 0, MO_64); |
23 | +#include "exec/ram_addr.h" | 22 | - accfn(tmp, tmp, rd0); |
24 | #include "exec/cpu_ldst.h" | 23 | - write_neon_element64(tmp, a->vd, 0, MO_64); |
25 | #include "exec/helper-proto.h" | 24 | + accfn(rd0, tmp, rd0); |
26 | 25 | read_neon_element64(tmp, a->vd, 1, MO_64); | |
27 | @@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, | 26 | - accfn(tmp, tmp, rd1); |
28 | int ptr_size, MMUAccessType tag_access, | 27 | - write_neon_element64(tmp, a->vd, 1, MO_64); |
29 | int tag_size, uintptr_t ra) | 28 | + accfn(rd1, tmp, rd1); |
30 | { | 29 | tcg_temp_free_i64(tmp); |
31 | +#ifdef CONFIG_USER_ONLY | 30 | - } else { |
32 | /* Tag storage not implemented. */ | 31 | - write_neon_element64(rd0, a->vd, 0, MO_64); |
33 | return NULL; | 32 | - write_neon_element64(rd1, a->vd, 1, MO_64); |
34 | +#else | 33 | } |
35 | + uintptr_t index; | 34 | |
36 | + CPUIOTLBEntry *iotlbentry; | 35 | + write_neon_element64(rd0, a->vd, 0, MO_64); |
37 | + int in_page, flags; | 36 | + write_neon_element64(rd1, a->vd, 1, MO_64); |
38 | + ram_addr_t ptr_ra; | 37 | tcg_temp_free_i64(rd0); |
39 | + hwaddr ptr_paddr, tag_paddr, xlat; | 38 | tcg_temp_free_i64(rd1); |
40 | + MemoryRegion *mr; | 39 | |
41 | + ARMASIdx tag_asi; | 40 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a, |
42 | + AddressSpace *tag_as; | 41 | if (accfn) { |
43 | + void *host; | 42 | TCGv_i64 t64 = tcg_temp_new_i64(); |
43 | read_neon_element64(t64, a->vd, 0, MO_64); | ||
44 | - accfn(t64, t64, rn0_64); | ||
45 | - write_neon_element64(t64, a->vd, 0, MO_64); | ||
46 | + accfn(rn0_64, t64, rn0_64); | ||
47 | read_neon_element64(t64, a->vd, 1, MO_64); | ||
48 | - accfn(t64, t64, rn1_64); | ||
49 | - write_neon_element64(t64, a->vd, 1, MO_64); | ||
50 | + accfn(rn1_64, t64, rn1_64); | ||
51 | tcg_temp_free_i64(t64); | ||
52 | - } else { | ||
53 | - write_neon_element64(rn0_64, a->vd, 0, MO_64); | ||
54 | - write_neon_element64(rn1_64, a->vd, 1, MO_64); | ||
55 | } | ||
44 | + | 56 | + |
45 | + /* | 57 | + write_neon_element64(rn0_64, a->vd, 0, MO_64); |
46 | + * Probe the first byte of the virtual address. This raises an | 58 | + write_neon_element64(rn1_64, a->vd, 1, MO_64); |
47 | + * exception for inaccessible pages, and resolves the virtual address | 59 | tcg_temp_free_i64(rn0_64); |
48 | + * into the softmmu tlb. | 60 | tcg_temp_free_i64(rn1_64); |
49 | + * | 61 | return true; |
50 | + * When RA == 0, this is for mte_probe1. The page is expected to be | ||
51 | + * valid. Indicate to probe_access_flags no-fault, then assert that | ||
52 | + * we received a valid page. | ||
53 | + */ | ||
54 | + flags = probe_access_flags(env, ptr, ptr_access, ptr_mmu_idx, | ||
55 | + ra == 0, &host, ra); | ||
56 | + assert(!(flags & TLB_INVALID_MASK)); | ||
57 | + | ||
58 | + /* | ||
59 | + * Find the iotlbentry for ptr. This *must* be present in the TLB | ||
60 | + * because we just found the mapping. | ||
61 | + * TODO: Perhaps there should be a cputlb helper that returns a | ||
62 | + * matching tlb entry + iotlb entry. | ||
63 | + */ | ||
64 | + index = tlb_index(env, ptr_mmu_idx, ptr); | ||
65 | +# ifdef CONFIG_DEBUG_TCG | ||
66 | + { | ||
67 | + CPUTLBEntry *entry = tlb_entry(env, ptr_mmu_idx, ptr); | ||
68 | + target_ulong comparator = (ptr_access == MMU_DATA_LOAD | ||
69 | + ? entry->addr_read | ||
70 | + : tlb_addr_write(entry)); | ||
71 | + g_assert(tlb_hit(comparator, ptr)); | ||
72 | + } | ||
73 | +# endif | ||
74 | + iotlbentry = &env_tlb(env)->d[ptr_mmu_idx].iotlb[index]; | ||
75 | + | ||
76 | + /* If the virtual page MemAttr != Tagged, access unchecked. */ | ||
77 | + if (!arm_tlb_mte_tagged(&iotlbentry->attrs)) { | ||
78 | + return NULL; | ||
79 | + } | ||
80 | + | ||
81 | + /* | ||
82 | + * If not backed by host ram, there is no tag storage: access unchecked. | ||
83 | + * This is probably a guest os bug though, so log it. | ||
84 | + */ | ||
85 | + if (unlikely(flags & TLB_MMIO)) { | ||
86 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
87 | + "Page @ 0x%" PRIx64 " indicates Tagged Normal memory " | ||
88 | + "but is not backed by host ram\n", ptr); | ||
89 | + return NULL; | ||
90 | + } | ||
91 | + | ||
92 | + /* | ||
93 | + * The Normal memory access can extend to the next page. E.g. a single | ||
94 | + * 8-byte access to the last byte of a page will check only the last | ||
95 | + * tag on the first page. | ||
96 | + * Any page access exception has priority over tag check exception. | ||
97 | + */ | ||
98 | + in_page = -(ptr | TARGET_PAGE_MASK); | ||
99 | + if (unlikely(ptr_size > in_page)) { | ||
100 | + void *ignore; | ||
101 | + flags |= probe_access_flags(env, ptr + in_page, ptr_access, | ||
102 | + ptr_mmu_idx, ra == 0, &ignore, ra); | ||
103 | + assert(!(flags & TLB_INVALID_MASK)); | ||
104 | + } | ||
105 | + | ||
106 | + /* Any debug exception has priority over a tag check exception. */ | ||
107 | + if (unlikely(flags & TLB_WATCHPOINT)) { | ||
108 | + int wp = ptr_access == MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_WRITE; | ||
109 | + assert(ra != 0); | ||
110 | + cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, | ||
111 | + iotlbentry->attrs, wp, ra); | ||
112 | + } | ||
113 | + | ||
114 | + /* | ||
115 | + * Find the physical address within the normal mem space. | ||
116 | + * The memory region lookup must succeed because TLB_MMIO was | ||
117 | + * not set in the cputlb lookup above. | ||
118 | + */ | ||
119 | + mr = memory_region_from_host(host, &ptr_ra); | ||
120 | + tcg_debug_assert(mr != NULL); | ||
121 | + tcg_debug_assert(memory_region_is_ram(mr)); | ||
122 | + ptr_paddr = ptr_ra; | ||
123 | + do { | ||
124 | + ptr_paddr += mr->addr; | ||
125 | + mr = mr->container; | ||
126 | + } while (mr); | ||
127 | + | ||
128 | + /* Convert to the physical address in tag space. */ | ||
129 | + tag_paddr = ptr_paddr >> (LOG2_TAG_GRANULE + 1); | ||
130 | + | ||
131 | + /* Look up the address in tag space. */ | ||
132 | + tag_asi = iotlbentry->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; | ||
133 | + tag_as = cpu_get_address_space(env_cpu(env), tag_asi); | ||
134 | + mr = address_space_translate(tag_as, tag_paddr, &xlat, NULL, | ||
135 | + tag_access == MMU_DATA_STORE, | ||
136 | + iotlbentry->attrs); | ||
137 | + | ||
138 | + /* | ||
139 | + * Note that @mr will never be NULL. If there is nothing in the address | ||
140 | + * space at @tag_paddr, the translation will return the unallocated memory | ||
141 | + * region. For our purposes, the result must be ram. | ||
142 | + */ | ||
143 | + if (unlikely(!memory_region_is_ram(mr))) { | ||
144 | + /* ??? Failure is a board configuration error. */ | ||
145 | + qemu_log_mask(LOG_UNIMP, | ||
146 | + "Tag Memory @ 0x%" HWADDR_PRIx " not found for " | ||
147 | + "Normal Memory @ 0x%" HWADDR_PRIx "\n", | ||
148 | + tag_paddr, ptr_paddr); | ||
149 | + return NULL; | ||
150 | + } | ||
151 | + | ||
152 | + /* | ||
153 | + * Ensure the tag memory is dirty on write, for migration. | ||
154 | + * Tag memory can never contain code or display memory (vga). | ||
155 | + */ | ||
156 | + if (tag_access == MMU_DATA_STORE) { | ||
157 | + ram_addr_t tag_ra = memory_region_get_ram_addr(mr) + xlat; | ||
158 | + cpu_physical_memory_set_dirty_flag(tag_ra, DIRTY_MEMORY_MIGRATION); | ||
159 | + } | ||
160 | + | ||
161 | + return memory_region_get_ram_ptr(mr) + xlat; | ||
162 | +#endif | ||
163 | } | ||
164 | |||
165 | uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) | ||
166 | -- | 62 | -- |
167 | 2.20.1 | 63 | 2.20.1 |
168 | 64 | ||
169 | 65 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Because the elements are sequential, we can eliminate many tests all | 3 | We can use proper widening loads to extend 32-bit inputs, |
4 | at once when the tag hits TCMA, or if the page(s) are not Tagged. | 4 | and skip the "widenfn" step. |
5 | 5 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20201030022618.785675-12-richard.henderson@linaro.org | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20200626033144.790098-36-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | target/arm/helper-sve.h | 98 ++++++++++++++++ | 11 | target/arm/translate.c | 6 +++ |
12 | target/arm/sve_helper.c | 99 ++++++++++++++-- | 12 | target/arm/translate-neon.c.inc | 66 ++++++++++++++++++--------------- |
13 | target/arm/translate-sve.c | 232 +++++++++++++++++++++++++------------ | 13 | 2 files changed, 43 insertions(+), 29 deletions(-) |
14 | 3 files changed, 343 insertions(+), 86 deletions(-) | ||
15 | 14 | ||
16 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | 15 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/helper-sve.h | 17 | --- a/target/arm/translate.c |
19 | +++ b/target/arm/helper-sve.h | 18 | +++ b/target/arm/translate.c |
20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_ldff1sds_be_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | 19 | @@ -XXX,XX +XXX,XX @@ static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) |
21 | DEF_HELPER_FLAGS_4(sve_ldff1dd_le_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | 20 | long off = neon_element_offset(reg, ele, memop); |
22 | DEF_HELPER_FLAGS_4(sve_ldff1dd_be_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | 21 | |
23 | 22 | switch (memop) { | |
24 | +DEF_HELPER_FLAGS_4(sve_ldff1bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | 23 | + case MO_SL: |
25 | +DEF_HELPER_FLAGS_4(sve_ldff1bhu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | 24 | + tcg_gen_ld32s_i64(dest, cpu_env, off); |
26 | +DEF_HELPER_FLAGS_4(sve_ldff1bsu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | 25 | + break; |
27 | +DEF_HELPER_FLAGS_4(sve_ldff1bdu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | 26 | + case MO_UL: |
28 | +DEF_HELPER_FLAGS_4(sve_ldff1bhs_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | 27 | + tcg_gen_ld32u_i64(dest, cpu_env, off); |
29 | +DEF_HELPER_FLAGS_4(sve_ldff1bss_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | 28 | + break; |
30 | +DEF_HELPER_FLAGS_4(sve_ldff1bds_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | 29 | case MO_Q: |
31 | + | 30 | tcg_gen_ld_i64(dest, cpu_env, off); |
32 | +DEF_HELPER_FLAGS_4(sve_ldff1hh_le_r_mte, TCG_CALL_NO_WG, | 31 | break; |
33 | + void, env, ptr, tl, i32) | 32 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc |
34 | +DEF_HELPER_FLAGS_4(sve_ldff1hsu_le_r_mte, TCG_CALL_NO_WG, | ||
35 | + void, env, ptr, tl, i32) | ||
36 | +DEF_HELPER_FLAGS_4(sve_ldff1hdu_le_r_mte, TCG_CALL_NO_WG, | ||
37 | + void, env, ptr, tl, i32) | ||
38 | +DEF_HELPER_FLAGS_4(sve_ldff1hss_le_r_mte, TCG_CALL_NO_WG, | ||
39 | + void, env, ptr, tl, i32) | ||
40 | +DEF_HELPER_FLAGS_4(sve_ldff1hds_le_r_mte, TCG_CALL_NO_WG, | ||
41 | + void, env, ptr, tl, i32) | ||
42 | + | ||
43 | +DEF_HELPER_FLAGS_4(sve_ldff1hh_be_r_mte, TCG_CALL_NO_WG, | ||
44 | + void, env, ptr, tl, i32) | ||
45 | +DEF_HELPER_FLAGS_4(sve_ldff1hsu_be_r_mte, TCG_CALL_NO_WG, | ||
46 | + void, env, ptr, tl, i32) | ||
47 | +DEF_HELPER_FLAGS_4(sve_ldff1hdu_be_r_mte, TCG_CALL_NO_WG, | ||
48 | + void, env, ptr, tl, i32) | ||
49 | +DEF_HELPER_FLAGS_4(sve_ldff1hss_be_r_mte, TCG_CALL_NO_WG, | ||
50 | + void, env, ptr, tl, i32) | ||
51 | +DEF_HELPER_FLAGS_4(sve_ldff1hds_be_r_mte, TCG_CALL_NO_WG, | ||
52 | + void, env, ptr, tl, i32) | ||
53 | + | ||
54 | +DEF_HELPER_FLAGS_4(sve_ldff1ss_le_r_mte, TCG_CALL_NO_WG, | ||
55 | + void, env, ptr, tl, i32) | ||
56 | +DEF_HELPER_FLAGS_4(sve_ldff1sdu_le_r_mte, TCG_CALL_NO_WG, | ||
57 | + void, env, ptr, tl, i32) | ||
58 | +DEF_HELPER_FLAGS_4(sve_ldff1sds_le_r_mte, TCG_CALL_NO_WG, | ||
59 | + void, env, ptr, tl, i32) | ||
60 | + | ||
61 | +DEF_HELPER_FLAGS_4(sve_ldff1ss_be_r_mte, TCG_CALL_NO_WG, | ||
62 | + void, env, ptr, tl, i32) | ||
63 | +DEF_HELPER_FLAGS_4(sve_ldff1sdu_be_r_mte, TCG_CALL_NO_WG, | ||
64 | + void, env, ptr, tl, i32) | ||
65 | +DEF_HELPER_FLAGS_4(sve_ldff1sds_be_r_mte, TCG_CALL_NO_WG, | ||
66 | + void, env, ptr, tl, i32) | ||
67 | + | ||
68 | +DEF_HELPER_FLAGS_4(sve_ldff1dd_le_r_mte, TCG_CALL_NO_WG, | ||
69 | + void, env, ptr, tl, i32) | ||
70 | +DEF_HELPER_FLAGS_4(sve_ldff1dd_be_r_mte, TCG_CALL_NO_WG, | ||
71 | + void, env, ptr, tl, i32) | ||
72 | + | ||
73 | DEF_HELPER_FLAGS_4(sve_ldnf1bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
74 | DEF_HELPER_FLAGS_4(sve_ldnf1bhu_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
75 | DEF_HELPER_FLAGS_4(sve_ldnf1bsu_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
76 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_ldnf1sds_be_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
77 | DEF_HELPER_FLAGS_4(sve_ldnf1dd_le_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
78 | DEF_HELPER_FLAGS_4(sve_ldnf1dd_be_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
79 | |||
80 | +DEF_HELPER_FLAGS_4(sve_ldnf1bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
81 | +DEF_HELPER_FLAGS_4(sve_ldnf1bhu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
82 | +DEF_HELPER_FLAGS_4(sve_ldnf1bsu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
83 | +DEF_HELPER_FLAGS_4(sve_ldnf1bdu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
84 | +DEF_HELPER_FLAGS_4(sve_ldnf1bhs_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
85 | +DEF_HELPER_FLAGS_4(sve_ldnf1bss_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
86 | +DEF_HELPER_FLAGS_4(sve_ldnf1bds_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
87 | + | ||
88 | +DEF_HELPER_FLAGS_4(sve_ldnf1hh_le_r_mte, TCG_CALL_NO_WG, | ||
89 | + void, env, ptr, tl, i32) | ||
90 | +DEF_HELPER_FLAGS_4(sve_ldnf1hsu_le_r_mte, TCG_CALL_NO_WG, | ||
91 | + void, env, ptr, tl, i32) | ||
92 | +DEF_HELPER_FLAGS_4(sve_ldnf1hdu_le_r_mte, TCG_CALL_NO_WG, | ||
93 | + void, env, ptr, tl, i32) | ||
94 | +DEF_HELPER_FLAGS_4(sve_ldnf1hss_le_r_mte, TCG_CALL_NO_WG, | ||
95 | + void, env, ptr, tl, i32) | ||
96 | +DEF_HELPER_FLAGS_4(sve_ldnf1hds_le_r_mte, TCG_CALL_NO_WG, | ||
97 | + void, env, ptr, tl, i32) | ||
98 | + | ||
99 | +DEF_HELPER_FLAGS_4(sve_ldnf1hh_be_r_mte, TCG_CALL_NO_WG, | ||
100 | + void, env, ptr, tl, i32) | ||
101 | +DEF_HELPER_FLAGS_4(sve_ldnf1hsu_be_r_mte, TCG_CALL_NO_WG, | ||
102 | + void, env, ptr, tl, i32) | ||
103 | +DEF_HELPER_FLAGS_4(sve_ldnf1hdu_be_r_mte, TCG_CALL_NO_WG, | ||
104 | + void, env, ptr, tl, i32) | ||
105 | +DEF_HELPER_FLAGS_4(sve_ldnf1hss_be_r_mte, TCG_CALL_NO_WG, | ||
106 | + void, env, ptr, tl, i32) | ||
107 | +DEF_HELPER_FLAGS_4(sve_ldnf1hds_be_r_mte, TCG_CALL_NO_WG, | ||
108 | + void, env, ptr, tl, i32) | ||
109 | + | ||
110 | +DEF_HELPER_FLAGS_4(sve_ldnf1ss_le_r_mte, TCG_CALL_NO_WG, | ||
111 | + void, env, ptr, tl, i32) | ||
112 | +DEF_HELPER_FLAGS_4(sve_ldnf1sdu_le_r_mte, TCG_CALL_NO_WG, | ||
113 | + void, env, ptr, tl, i32) | ||
114 | +DEF_HELPER_FLAGS_4(sve_ldnf1sds_le_r_mte, TCG_CALL_NO_WG, | ||
115 | + void, env, ptr, tl, i32) | ||
116 | + | ||
117 | +DEF_HELPER_FLAGS_4(sve_ldnf1ss_be_r_mte, TCG_CALL_NO_WG, | ||
118 | + void, env, ptr, tl, i32) | ||
119 | +DEF_HELPER_FLAGS_4(sve_ldnf1sdu_be_r_mte, TCG_CALL_NO_WG, | ||
120 | + void, env, ptr, tl, i32) | ||
121 | +DEF_HELPER_FLAGS_4(sve_ldnf1sds_be_r_mte, TCG_CALL_NO_WG, | ||
122 | + void, env, ptr, tl, i32) | ||
123 | + | ||
124 | +DEF_HELPER_FLAGS_4(sve_ldnf1dd_le_r_mte, TCG_CALL_NO_WG, | ||
125 | + void, env, ptr, tl, i32) | ||
126 | +DEF_HELPER_FLAGS_4(sve_ldnf1dd_be_r_mte, TCG_CALL_NO_WG, | ||
127 | + void, env, ptr, tl, i32) | ||
128 | + | ||
129 | DEF_HELPER_FLAGS_4(sve_st1bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
130 | DEF_HELPER_FLAGS_4(sve_st2bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
131 | DEF_HELPER_FLAGS_4(sve_st3bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) | ||
132 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | ||
133 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
134 | --- a/target/arm/sve_helper.c | 34 | --- a/target/arm/translate-neon.c.inc |
135 | +++ b/target/arm/sve_helper.c | 35 | +++ b/target/arm/translate-neon.c.inc |
136 | @@ -XXX,XX +XXX,XX @@ static void record_fault(CPUARMState *env, uintptr_t i, uintptr_t oprsz) | 36 | @@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a) |
137 | */ | 37 | static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, |
138 | static inline QEMU_ALWAYS_INLINE | 38 | NeonGenWidenFn *widenfn, |
139 | void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr, | 39 | NeonGenTwo64OpFn *opfn, |
140 | - uint32_t desc, const uintptr_t retaddr, | 40 | - bool src1_wide) |
141 | + uint32_t desc, const uintptr_t retaddr, uint32_t mtedesc, | 41 | + int src1_mop, int src2_mop) |
142 | const int esz, const int msz, const SVEContFault fault, | 42 | { |
143 | sve_ldst1_host_fn *host_fn, | 43 | /* 3-regs different lengths, prewidening case (VADDL/VSUBL/VAADW/VSUBW) */ |
144 | sve_ldst1_tlb_fn *tlb_fn) | 44 | TCGv_i64 rn0_64, rn1_64, rm_64; |
145 | @@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr, | 45 | - TCGv_i32 rm; |
146 | mem_off = info.mem_off_first[0]; | 46 | |
147 | flags = info.page[0].flags; | 47 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { |
148 | 48 | return false; | |
149 | + /* | 49 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, |
150 | + * Disable MTE checking if the Tagged bit is not set. Since TBI must | 50 | return false; |
151 | + * be set within MTEDESC for MTE, !mtedesc => !mte_active. | 51 | } |
152 | + */ | 52 | |
153 | + if (arm_tlb_mte_tagged(&info.page[0].attrs)) { | 53 | - if (!widenfn || !opfn) { |
154 | + mtedesc = 0; | 54 | + if (!opfn) { |
55 | /* size == 3 case, which is an entirely different insn group */ | ||
56 | return false; | ||
57 | } | ||
58 | |||
59 | - if ((a->vd & 1) || (src1_wide && (a->vn & 1))) { | ||
60 | + if ((a->vd & 1) || (src1_mop == MO_Q && (a->vn & 1))) { | ||
61 | return false; | ||
62 | } | ||
63 | |||
64 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
65 | rn1_64 = tcg_temp_new_i64(); | ||
66 | rm_64 = tcg_temp_new_i64(); | ||
67 | |||
68 | - if (src1_wide) { | ||
69 | - read_neon_element64(rn0_64, a->vn, 0, MO_64); | ||
70 | + if (src1_mop >= 0) { | ||
71 | + read_neon_element64(rn0_64, a->vn, 0, src1_mop); | ||
72 | } else { | ||
73 | TCGv_i32 tmp = tcg_temp_new_i32(); | ||
74 | read_neon_element32(tmp, a->vn, 0, MO_32); | ||
75 | widenfn(rn0_64, tmp); | ||
76 | tcg_temp_free_i32(tmp); | ||
77 | } | ||
78 | - rm = tcg_temp_new_i32(); | ||
79 | - read_neon_element32(rm, a->vm, 0, MO_32); | ||
80 | + if (src2_mop >= 0) { | ||
81 | + read_neon_element64(rm_64, a->vm, 0, src2_mop); | ||
82 | + } else { | ||
83 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
84 | + read_neon_element32(tmp, a->vm, 0, MO_32); | ||
85 | + widenfn(rm_64, tmp); | ||
86 | + tcg_temp_free_i32(tmp); | ||
155 | + } | 87 | + } |
156 | + | 88 | |
157 | if (fault == FAULT_FIRST) { | 89 | - widenfn(rm_64, rm); |
158 | + /* Trapping mte check for the first-fault element. */ | 90 | - tcg_temp_free_i32(rm); |
159 | + if (mtedesc) { | 91 | opfn(rn0_64, rn0_64, rm_64); |
160 | + mte_check1(env, mtedesc, addr + mem_off, retaddr); | 92 | |
161 | + } | 93 | /* |
162 | + | 94 | * Load second pass inputs before storing the first pass result, to |
163 | /* | 95 | * avoid incorrect results if a narrow input overlaps with the result. |
164 | * Special handling of the first active element, | 96 | */ |
165 | * if it crosses a page boundary or is MMIO. | 97 | - if (src1_wide) { |
166 | */ | 98 | - read_neon_element64(rn1_64, a->vn, 1, MO_64); |
167 | bool is_split = mem_off == info.mem_off_split; | 99 | + if (src1_mop >= 0) { |
168 | - /* TODO: MTE check. */ | 100 | + read_neon_element64(rn1_64, a->vn, 1, src1_mop); |
169 | if (unlikely(flags != 0) || unlikely(is_split)) { | 101 | } else { |
170 | /* | 102 | TCGv_i32 tmp = tcg_temp_new_i32(); |
171 | * Use the slow path for cross-page handling. | 103 | read_neon_element32(tmp, a->vn, 1, MO_32); |
172 | @@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr, | 104 | widenfn(rn1_64, tmp); |
173 | /* Watchpoint hit, see below. */ | 105 | tcg_temp_free_i32(tmp); |
174 | goto do_fault; | 106 | } |
175 | } | 107 | - rm = tcg_temp_new_i32(); |
176 | - /* TODO: MTE check. */ | 108 | - read_neon_element32(rm, a->vm, 1, MO_32); |
177 | + if (mtedesc && !mte_probe1(env, mtedesc, addr + mem_off)) { | 109 | + if (src2_mop >= 0) { |
178 | + goto do_fault; | 110 | + read_neon_element64(rm_64, a->vm, 1, src2_mop); |
179 | + } | 111 | + } else { |
180 | /* | 112 | + TCGv_i32 tmp = tcg_temp_new_i32(); |
181 | * Use the slow path for cross-page handling. | 113 | + read_neon_element32(tmp, a->vm, 1, MO_32); |
182 | * This is RAM, without a watchpoint, and will not trap. | 114 | + widenfn(rm_64, tmp); |
183 | @@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr, | 115 | + tcg_temp_free_i32(tmp); |
184 | & BP_MEM_READ)) { | ||
185 | goto do_fault; | ||
186 | } | ||
187 | - /* TODO: MTE check. */ | ||
188 | + if (mtedesc && !mte_probe1(env, mtedesc, addr + mem_off)) { | ||
189 | + goto do_fault; | ||
190 | + } | ||
191 | host_fn(vd, reg_off, host + mem_off); | ||
192 | } | ||
193 | reg_off += 1 << esz; | ||
194 | @@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr, | ||
195 | record_fault(env, reg_off, reg_max); | ||
196 | } | ||
197 | |||
198 | -#define DO_LDFF1_LDNF1_1(PART, ESZ) \ | ||
199 | +static inline QEMU_ALWAYS_INLINE | ||
200 | +void sve_ldnfff1_r_mte(CPUARMState *env, void *vg, target_ulong addr, | ||
201 | + uint32_t desc, const uintptr_t retaddr, | ||
202 | + const int esz, const int msz, const SVEContFault fault, | ||
203 | + sve_ldst1_host_fn *host_fn, | ||
204 | + sve_ldst1_tlb_fn *tlb_fn) | ||
205 | +{ | ||
206 | + uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); | ||
207 | + int bit55 = extract64(addr, 55, 1); | ||
208 | + | ||
209 | + /* Remove mtedesc from the normal sve descriptor. */ | ||
210 | + desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); | ||
211 | + | ||
212 | + /* Perform gross MTE suppression early. */ | ||
213 | + if (!tbi_check(desc, bit55) || | ||
214 | + tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { | ||
215 | + mtedesc = 0; | ||
216 | + } | 116 | + } |
217 | + | 117 | |
218 | + sve_ldnfff1_r(env, vg, addr, desc, retaddr, mtedesc, | 118 | write_neon_element64(rn0_64, a->vd, 0, MO_64); |
219 | + esz, msz, fault, host_fn, tlb_fn); | 119 | |
220 | +} | 120 | - widenfn(rm_64, rm); |
221 | + | 121 | - tcg_temp_free_i32(rm); |
222 | +#define DO_LDFF1_LDNF1_1(PART, ESZ) \ | 122 | opfn(rn1_64, rn1_64, rm_64); |
223 | void HELPER(sve_ldff1##PART##_r)(CPUARMState *env, void *vg, \ | 123 | write_neon_element64(rn1_64, a->vd, 1, MO_64); |
224 | target_ulong addr, uint32_t desc) \ | 124 | |
225 | { \ | 125 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, |
226 | - sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, FAULT_FIRST, \ | ||
227 | + sve_ldnfff1_r(env, vg, addr, desc, GETPC(), 0, ESZ, MO_8, FAULT_FIRST, \ | ||
228 | sve_ld1##PART##_host, sve_ld1##PART##_tlb); \ | ||
229 | } \ | ||
230 | void HELPER(sve_ldnf1##PART##_r)(CPUARMState *env, void *vg, \ | ||
231 | target_ulong addr, uint32_t desc) \ | ||
232 | { \ | ||
233 | - sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, FAULT_NO, \ | ||
234 | + sve_ldnfff1_r(env, vg, addr, desc, GETPC(), 0, ESZ, MO_8, FAULT_NO, \ | ||
235 | + sve_ld1##PART##_host, sve_ld1##PART##_tlb); \ | ||
236 | +} \ | ||
237 | +void HELPER(sve_ldff1##PART##_r_mte)(CPUARMState *env, void *vg, \ | ||
238 | + target_ulong addr, uint32_t desc) \ | ||
239 | +{ \ | ||
240 | + sve_ldnfff1_r_mte(env, vg, addr, desc, GETPC(), ESZ, MO_8, FAULT_FIRST, \ | ||
241 | + sve_ld1##PART##_host, sve_ld1##PART##_tlb); \ | ||
242 | +} \ | ||
243 | +void HELPER(sve_ldnf1##PART##_r_mte)(CPUARMState *env, void *vg, \ | ||
244 | + target_ulong addr, uint32_t desc) \ | ||
245 | +{ \ | ||
246 | + sve_ldnfff1_r_mte(env, vg, addr, desc, GETPC(), ESZ, MO_8, FAULT_NO, \ | ||
247 | sve_ld1##PART##_host, sve_ld1##PART##_tlb); \ | ||
248 | } | ||
249 | |||
250 | -#define DO_LDFF1_LDNF1_2(PART, ESZ, MSZ) \ | ||
251 | +#define DO_LDFF1_LDNF1_2(PART, ESZ, MSZ) \ | ||
252 | void HELPER(sve_ldff1##PART##_le_r)(CPUARMState *env, void *vg, \ | ||
253 | target_ulong addr, uint32_t desc) \ | ||
254 | { \ | ||
255 | - sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_FIRST, \ | ||
256 | + sve_ldnfff1_r(env, vg, addr, desc, GETPC(), 0, ESZ, MSZ, FAULT_FIRST, \ | ||
257 | sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \ | ||
258 | } \ | ||
259 | void HELPER(sve_ldnf1##PART##_le_r)(CPUARMState *env, void *vg, \ | ||
260 | target_ulong addr, uint32_t desc) \ | ||
261 | { \ | ||
262 | - sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_NO, \ | ||
263 | + sve_ldnfff1_r(env, vg, addr, desc, GETPC(), 0, ESZ, MSZ, FAULT_NO, \ | ||
264 | sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \ | ||
265 | } \ | ||
266 | void HELPER(sve_ldff1##PART##_be_r)(CPUARMState *env, void *vg, \ | ||
267 | target_ulong addr, uint32_t desc) \ | ||
268 | { \ | ||
269 | - sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_FIRST, \ | ||
270 | + sve_ldnfff1_r(env, vg, addr, desc, GETPC(), 0, ESZ, MSZ, FAULT_FIRST, \ | ||
271 | sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \ | ||
272 | } \ | ||
273 | void HELPER(sve_ldnf1##PART##_be_r)(CPUARMState *env, void *vg, \ | ||
274 | target_ulong addr, uint32_t desc) \ | ||
275 | { \ | ||
276 | - sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_NO, \ | ||
277 | + sve_ldnfff1_r(env, vg, addr, desc, GETPC(), 0, ESZ, MSZ, FAULT_NO, \ | ||
278 | sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \ | ||
279 | +} \ | ||
280 | +void HELPER(sve_ldff1##PART##_le_r_mte)(CPUARMState *env, void *vg, \ | ||
281 | + target_ulong addr, uint32_t desc) \ | ||
282 | +{ \ | ||
283 | + sve_ldnfff1_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_FIRST, \ | ||
284 | + sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \ | ||
285 | +} \ | ||
286 | +void HELPER(sve_ldnf1##PART##_le_r_mte)(CPUARMState *env, void *vg, \ | ||
287 | + target_ulong addr, uint32_t desc) \ | ||
288 | +{ \ | ||
289 | + sve_ldnfff1_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_NO, \ | ||
290 | + sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \ | ||
291 | +} \ | ||
292 | +void HELPER(sve_ldff1##PART##_be_r_mte)(CPUARMState *env, void *vg, \ | ||
293 | + target_ulong addr, uint32_t desc) \ | ||
294 | +{ \ | ||
295 | + sve_ldnfff1_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_FIRST, \ | ||
296 | + sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \ | ||
297 | +} \ | ||
298 | +void HELPER(sve_ldnf1##PART##_be_r_mte)(CPUARMState *env, void *vg, \ | ||
299 | + target_ulong addr, uint32_t desc) \ | ||
300 | +{ \ | ||
301 | + sve_ldnfff1_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_NO, \ | ||
302 | + sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \ | ||
303 | } | ||
304 | |||
305 | DO_LDFF1_LDNF1_1(bb, MO_8) | ||
306 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
307 | index XXXXXXX..XXXXXXX 100644 | ||
308 | --- a/target/arm/translate-sve.c | ||
309 | +++ b/target/arm/translate-sve.c | ||
310 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD_zpri(DisasContext *s, arg_rpri_load *a) | ||
311 | |||
312 | static bool trans_LDFF1_zprr(DisasContext *s, arg_rprr_load *a) | ||
313 | { | ||
314 | - static gen_helper_gvec_mem * const fns[2][16] = { | ||
315 | - /* Little-endian */ | ||
316 | - { gen_helper_sve_ldff1bb_r, | ||
317 | - gen_helper_sve_ldff1bhu_r, | ||
318 | - gen_helper_sve_ldff1bsu_r, | ||
319 | - gen_helper_sve_ldff1bdu_r, | ||
320 | + static gen_helper_gvec_mem * const fns[2][2][16] = { | ||
321 | + { /* mte inactive, little-endian */ | ||
322 | + { gen_helper_sve_ldff1bb_r, | ||
323 | + gen_helper_sve_ldff1bhu_r, | ||
324 | + gen_helper_sve_ldff1bsu_r, | ||
325 | + gen_helper_sve_ldff1bdu_r, | ||
326 | |||
327 | - gen_helper_sve_ldff1sds_le_r, | ||
328 | - gen_helper_sve_ldff1hh_le_r, | ||
329 | - gen_helper_sve_ldff1hsu_le_r, | ||
330 | - gen_helper_sve_ldff1hdu_le_r, | ||
331 | + gen_helper_sve_ldff1sds_le_r, | ||
332 | + gen_helper_sve_ldff1hh_le_r, | ||
333 | + gen_helper_sve_ldff1hsu_le_r, | ||
334 | + gen_helper_sve_ldff1hdu_le_r, | ||
335 | |||
336 | - gen_helper_sve_ldff1hds_le_r, | ||
337 | - gen_helper_sve_ldff1hss_le_r, | ||
338 | - gen_helper_sve_ldff1ss_le_r, | ||
339 | - gen_helper_sve_ldff1sdu_le_r, | ||
340 | + gen_helper_sve_ldff1hds_le_r, | ||
341 | + gen_helper_sve_ldff1hss_le_r, | ||
342 | + gen_helper_sve_ldff1ss_le_r, | ||
343 | + gen_helper_sve_ldff1sdu_le_r, | ||
344 | |||
345 | - gen_helper_sve_ldff1bds_r, | ||
346 | - gen_helper_sve_ldff1bss_r, | ||
347 | - gen_helper_sve_ldff1bhs_r, | ||
348 | - gen_helper_sve_ldff1dd_le_r }, | ||
349 | + gen_helper_sve_ldff1bds_r, | ||
350 | + gen_helper_sve_ldff1bss_r, | ||
351 | + gen_helper_sve_ldff1bhs_r, | ||
352 | + gen_helper_sve_ldff1dd_le_r }, | ||
353 | |||
354 | - /* Big-endian */ | ||
355 | - { gen_helper_sve_ldff1bb_r, | ||
356 | - gen_helper_sve_ldff1bhu_r, | ||
357 | - gen_helper_sve_ldff1bsu_r, | ||
358 | - gen_helper_sve_ldff1bdu_r, | ||
359 | + /* mte inactive, big-endian */ | ||
360 | + { gen_helper_sve_ldff1bb_r, | ||
361 | + gen_helper_sve_ldff1bhu_r, | ||
362 | + gen_helper_sve_ldff1bsu_r, | ||
363 | + gen_helper_sve_ldff1bdu_r, | ||
364 | |||
365 | - gen_helper_sve_ldff1sds_be_r, | ||
366 | - gen_helper_sve_ldff1hh_be_r, | ||
367 | - gen_helper_sve_ldff1hsu_be_r, | ||
368 | - gen_helper_sve_ldff1hdu_be_r, | ||
369 | + gen_helper_sve_ldff1sds_be_r, | ||
370 | + gen_helper_sve_ldff1hh_be_r, | ||
371 | + gen_helper_sve_ldff1hsu_be_r, | ||
372 | + gen_helper_sve_ldff1hdu_be_r, | ||
373 | |||
374 | - gen_helper_sve_ldff1hds_be_r, | ||
375 | - gen_helper_sve_ldff1hss_be_r, | ||
376 | - gen_helper_sve_ldff1ss_be_r, | ||
377 | - gen_helper_sve_ldff1sdu_be_r, | ||
378 | + gen_helper_sve_ldff1hds_be_r, | ||
379 | + gen_helper_sve_ldff1hss_be_r, | ||
380 | + gen_helper_sve_ldff1ss_be_r, | ||
381 | + gen_helper_sve_ldff1sdu_be_r, | ||
382 | |||
383 | - gen_helper_sve_ldff1bds_r, | ||
384 | - gen_helper_sve_ldff1bss_r, | ||
385 | - gen_helper_sve_ldff1bhs_r, | ||
386 | - gen_helper_sve_ldff1dd_be_r }, | ||
387 | + gen_helper_sve_ldff1bds_r, | ||
388 | + gen_helper_sve_ldff1bss_r, | ||
389 | + gen_helper_sve_ldff1bhs_r, | ||
390 | + gen_helper_sve_ldff1dd_be_r } }, | ||
391 | + | ||
392 | + { /* mte active, little-endian */ | ||
393 | + { gen_helper_sve_ldff1bb_r_mte, | ||
394 | + gen_helper_sve_ldff1bhu_r_mte, | ||
395 | + gen_helper_sve_ldff1bsu_r_mte, | ||
396 | + gen_helper_sve_ldff1bdu_r_mte, | ||
397 | + | ||
398 | + gen_helper_sve_ldff1sds_le_r_mte, | ||
399 | + gen_helper_sve_ldff1hh_le_r_mte, | ||
400 | + gen_helper_sve_ldff1hsu_le_r_mte, | ||
401 | + gen_helper_sve_ldff1hdu_le_r_mte, | ||
402 | + | ||
403 | + gen_helper_sve_ldff1hds_le_r_mte, | ||
404 | + gen_helper_sve_ldff1hss_le_r_mte, | ||
405 | + gen_helper_sve_ldff1ss_le_r_mte, | ||
406 | + gen_helper_sve_ldff1sdu_le_r_mte, | ||
407 | + | ||
408 | + gen_helper_sve_ldff1bds_r_mte, | ||
409 | + gen_helper_sve_ldff1bss_r_mte, | ||
410 | + gen_helper_sve_ldff1bhs_r_mte, | ||
411 | + gen_helper_sve_ldff1dd_le_r_mte }, | ||
412 | + | ||
413 | + /* mte active, big-endian */ | ||
414 | + { gen_helper_sve_ldff1bb_r_mte, | ||
415 | + gen_helper_sve_ldff1bhu_r_mte, | ||
416 | + gen_helper_sve_ldff1bsu_r_mte, | ||
417 | + gen_helper_sve_ldff1bdu_r_mte, | ||
418 | + | ||
419 | + gen_helper_sve_ldff1sds_be_r_mte, | ||
420 | + gen_helper_sve_ldff1hh_be_r_mte, | ||
421 | + gen_helper_sve_ldff1hsu_be_r_mte, | ||
422 | + gen_helper_sve_ldff1hdu_be_r_mte, | ||
423 | + | ||
424 | + gen_helper_sve_ldff1hds_be_r_mte, | ||
425 | + gen_helper_sve_ldff1hss_be_r_mte, | ||
426 | + gen_helper_sve_ldff1ss_be_r_mte, | ||
427 | + gen_helper_sve_ldff1sdu_be_r_mte, | ||
428 | + | ||
429 | + gen_helper_sve_ldff1bds_r_mte, | ||
430 | + gen_helper_sve_ldff1bss_r_mte, | ||
431 | + gen_helper_sve_ldff1bhs_r_mte, | ||
432 | + gen_helper_sve_ldff1dd_be_r_mte } }, | ||
433 | }; | ||
434 | |||
435 | if (sve_access_check(s)) { | ||
436 | TCGv_i64 addr = new_tmp_a64(s); | ||
437 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); | ||
438 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); | ||
439 | - do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 0, false, | ||
440 | - fns[s->be_data == MO_BE][a->dtype]); | ||
441 | + do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 1, false, | ||
442 | + fns[s->mte_active[0]][s->be_data == MO_BE][a->dtype]); | ||
443 | } | ||
444 | return true; | 126 | return true; |
445 | } | 127 | } |
446 | 128 | ||
447 | static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a) | 129 | -#define DO_PREWIDEN(INSN, S, EXT, OP, SRC1WIDE) \ |
448 | { | 130 | +#define DO_PREWIDEN(INSN, S, OP, SRC1WIDE, SIGN) \ |
449 | - static gen_helper_gvec_mem * const fns[2][16] = { | 131 | static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ |
450 | - /* Little-endian */ | 132 | { \ |
451 | - { gen_helper_sve_ldnf1bb_r, | 133 | static NeonGenWidenFn * const widenfn[] = { \ |
452 | - gen_helper_sve_ldnf1bhu_r, | 134 | gen_helper_neon_widen_##S##8, \ |
453 | - gen_helper_sve_ldnf1bsu_r, | 135 | gen_helper_neon_widen_##S##16, \ |
454 | - gen_helper_sve_ldnf1bdu_r, | 136 | - tcg_gen_##EXT##_i32_i64, \ |
455 | + static gen_helper_gvec_mem * const fns[2][2][16] = { | 137 | - NULL, \ |
456 | + { /* mte inactive, little-endian */ | 138 | + NULL, NULL, \ |
457 | + { gen_helper_sve_ldnf1bb_r, | 139 | }; \ |
458 | + gen_helper_sve_ldnf1bhu_r, | 140 | static NeonGenTwo64OpFn * const addfn[] = { \ |
459 | + gen_helper_sve_ldnf1bsu_r, | 141 | gen_helper_neon_##OP##l_u16, \ |
460 | + gen_helper_sve_ldnf1bdu_r, | 142 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, |
461 | 143 | tcg_gen_##OP##_i64, \ | |
462 | - gen_helper_sve_ldnf1sds_le_r, | 144 | NULL, \ |
463 | - gen_helper_sve_ldnf1hh_le_r, | 145 | }; \ |
464 | - gen_helper_sve_ldnf1hsu_le_r, | 146 | - return do_prewiden_3d(s, a, widenfn[a->size], \ |
465 | - gen_helper_sve_ldnf1hdu_le_r, | 147 | - addfn[a->size], SRC1WIDE); \ |
466 | + gen_helper_sve_ldnf1sds_le_r, | 148 | + int narrow_mop = a->size == MO_32 ? MO_32 | SIGN : -1; \ |
467 | + gen_helper_sve_ldnf1hh_le_r, | 149 | + return do_prewiden_3d(s, a, widenfn[a->size], addfn[a->size], \ |
468 | + gen_helper_sve_ldnf1hsu_le_r, | 150 | + SRC1WIDE ? MO_Q : narrow_mop, \ |
469 | + gen_helper_sve_ldnf1hdu_le_r, | 151 | + narrow_mop); \ |
470 | |||
471 | - gen_helper_sve_ldnf1hds_le_r, | ||
472 | - gen_helper_sve_ldnf1hss_le_r, | ||
473 | - gen_helper_sve_ldnf1ss_le_r, | ||
474 | - gen_helper_sve_ldnf1sdu_le_r, | ||
475 | + gen_helper_sve_ldnf1hds_le_r, | ||
476 | + gen_helper_sve_ldnf1hss_le_r, | ||
477 | + gen_helper_sve_ldnf1ss_le_r, | ||
478 | + gen_helper_sve_ldnf1sdu_le_r, | ||
479 | |||
480 | - gen_helper_sve_ldnf1bds_r, | ||
481 | - gen_helper_sve_ldnf1bss_r, | ||
482 | - gen_helper_sve_ldnf1bhs_r, | ||
483 | - gen_helper_sve_ldnf1dd_le_r }, | ||
484 | + gen_helper_sve_ldnf1bds_r, | ||
485 | + gen_helper_sve_ldnf1bss_r, | ||
486 | + gen_helper_sve_ldnf1bhs_r, | ||
487 | + gen_helper_sve_ldnf1dd_le_r }, | ||
488 | |||
489 | - /* Big-endian */ | ||
490 | - { gen_helper_sve_ldnf1bb_r, | ||
491 | - gen_helper_sve_ldnf1bhu_r, | ||
492 | - gen_helper_sve_ldnf1bsu_r, | ||
493 | - gen_helper_sve_ldnf1bdu_r, | ||
494 | + /* mte inactive, big-endian */ | ||
495 | + { gen_helper_sve_ldnf1bb_r, | ||
496 | + gen_helper_sve_ldnf1bhu_r, | ||
497 | + gen_helper_sve_ldnf1bsu_r, | ||
498 | + gen_helper_sve_ldnf1bdu_r, | ||
499 | |||
500 | - gen_helper_sve_ldnf1sds_be_r, | ||
501 | - gen_helper_sve_ldnf1hh_be_r, | ||
502 | - gen_helper_sve_ldnf1hsu_be_r, | ||
503 | - gen_helper_sve_ldnf1hdu_be_r, | ||
504 | + gen_helper_sve_ldnf1sds_be_r, | ||
505 | + gen_helper_sve_ldnf1hh_be_r, | ||
506 | + gen_helper_sve_ldnf1hsu_be_r, | ||
507 | + gen_helper_sve_ldnf1hdu_be_r, | ||
508 | |||
509 | - gen_helper_sve_ldnf1hds_be_r, | ||
510 | - gen_helper_sve_ldnf1hss_be_r, | ||
511 | - gen_helper_sve_ldnf1ss_be_r, | ||
512 | - gen_helper_sve_ldnf1sdu_be_r, | ||
513 | + gen_helper_sve_ldnf1hds_be_r, | ||
514 | + gen_helper_sve_ldnf1hss_be_r, | ||
515 | + gen_helper_sve_ldnf1ss_be_r, | ||
516 | + gen_helper_sve_ldnf1sdu_be_r, | ||
517 | |||
518 | - gen_helper_sve_ldnf1bds_r, | ||
519 | - gen_helper_sve_ldnf1bss_r, | ||
520 | - gen_helper_sve_ldnf1bhs_r, | ||
521 | - gen_helper_sve_ldnf1dd_be_r }, | ||
522 | + gen_helper_sve_ldnf1bds_r, | ||
523 | + gen_helper_sve_ldnf1bss_r, | ||
524 | + gen_helper_sve_ldnf1bhs_r, | ||
525 | + gen_helper_sve_ldnf1dd_be_r } }, | ||
526 | + | ||
527 | + { /* mte inactive, little-endian */ | ||
528 | + { gen_helper_sve_ldnf1bb_r_mte, | ||
529 | + gen_helper_sve_ldnf1bhu_r_mte, | ||
530 | + gen_helper_sve_ldnf1bsu_r_mte, | ||
531 | + gen_helper_sve_ldnf1bdu_r_mte, | ||
532 | + | ||
533 | + gen_helper_sve_ldnf1sds_le_r_mte, | ||
534 | + gen_helper_sve_ldnf1hh_le_r_mte, | ||
535 | + gen_helper_sve_ldnf1hsu_le_r_mte, | ||
536 | + gen_helper_sve_ldnf1hdu_le_r_mte, | ||
537 | + | ||
538 | + gen_helper_sve_ldnf1hds_le_r_mte, | ||
539 | + gen_helper_sve_ldnf1hss_le_r_mte, | ||
540 | + gen_helper_sve_ldnf1ss_le_r_mte, | ||
541 | + gen_helper_sve_ldnf1sdu_le_r_mte, | ||
542 | + | ||
543 | + gen_helper_sve_ldnf1bds_r_mte, | ||
544 | + gen_helper_sve_ldnf1bss_r_mte, | ||
545 | + gen_helper_sve_ldnf1bhs_r_mte, | ||
546 | + gen_helper_sve_ldnf1dd_le_r_mte }, | ||
547 | + | ||
548 | + /* mte inactive, big-endian */ | ||
549 | + { gen_helper_sve_ldnf1bb_r_mte, | ||
550 | + gen_helper_sve_ldnf1bhu_r_mte, | ||
551 | + gen_helper_sve_ldnf1bsu_r_mte, | ||
552 | + gen_helper_sve_ldnf1bdu_r_mte, | ||
553 | + | ||
554 | + gen_helper_sve_ldnf1sds_be_r_mte, | ||
555 | + gen_helper_sve_ldnf1hh_be_r_mte, | ||
556 | + gen_helper_sve_ldnf1hsu_be_r_mte, | ||
557 | + gen_helper_sve_ldnf1hdu_be_r_mte, | ||
558 | + | ||
559 | + gen_helper_sve_ldnf1hds_be_r_mte, | ||
560 | + gen_helper_sve_ldnf1hss_be_r_mte, | ||
561 | + gen_helper_sve_ldnf1ss_be_r_mte, | ||
562 | + gen_helper_sve_ldnf1sdu_be_r_mte, | ||
563 | + | ||
564 | + gen_helper_sve_ldnf1bds_r_mte, | ||
565 | + gen_helper_sve_ldnf1bss_r_mte, | ||
566 | + gen_helper_sve_ldnf1bhs_r_mte, | ||
567 | + gen_helper_sve_ldnf1dd_be_r_mte } }, | ||
568 | }; | ||
569 | |||
570 | if (sve_access_check(s)) { | ||
571 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a) | ||
572 | TCGv_i64 addr = new_tmp_a64(s); | ||
573 | |||
574 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), off); | ||
575 | - do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 0, false, | ||
576 | - fns[s->be_data == MO_BE][a->dtype]); | ||
577 | + do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 1, false, | ||
578 | + fns[s->mte_active[0]][s->be_data == MO_BE][a->dtype]); | ||
579 | } | 152 | } |
580 | return true; | 153 | |
581 | } | 154 | -DO_PREWIDEN(VADDL_S, s, ext, add, false) |
155 | -DO_PREWIDEN(VADDL_U, u, extu, add, false) | ||
156 | -DO_PREWIDEN(VSUBL_S, s, ext, sub, false) | ||
157 | -DO_PREWIDEN(VSUBL_U, u, extu, sub, false) | ||
158 | -DO_PREWIDEN(VADDW_S, s, ext, add, true) | ||
159 | -DO_PREWIDEN(VADDW_U, u, extu, add, true) | ||
160 | -DO_PREWIDEN(VSUBW_S, s, ext, sub, true) | ||
161 | -DO_PREWIDEN(VSUBW_U, u, extu, sub, true) | ||
162 | +DO_PREWIDEN(VADDL_S, s, add, false, MO_SIGN) | ||
163 | +DO_PREWIDEN(VADDL_U, u, add, false, 0) | ||
164 | +DO_PREWIDEN(VSUBL_S, s, sub, false, MO_SIGN) | ||
165 | +DO_PREWIDEN(VSUBL_U, u, sub, false, 0) | ||
166 | +DO_PREWIDEN(VADDW_S, s, add, true, MO_SIGN) | ||
167 | +DO_PREWIDEN(VADDW_U, u, add, true, 0) | ||
168 | +DO_PREWIDEN(VSUBW_S, s, sub, true, MO_SIGN) | ||
169 | +DO_PREWIDEN(VSUBW_U, u, sub, true, 0) | ||
170 | |||
171 | static bool do_narrow_3d(DisasContext *s, arg_3diff *a, | ||
172 | NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn) | ||
582 | -- | 173 | -- |
583 | 2.20.1 | 174 | 2.20.1 |
584 | 175 | ||
585 | 176 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | In the neon_padd/pmax/pmin helpers for float16, a cut-and-paste error |
---|---|---|---|
2 | meant we were using the H4() address swizzler macro rather than the | ||
3 | H2() which is required for 2-byte data. This had no effect on | ||
4 | little-endian hosts but meant we put the result data into the | ||
5 | destination Dreg in the wrong order on big-endian hosts. | ||
2 | 6 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20200626033144.790098-29-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
10 | Message-id: 20201028191712.4910-2-peter.maydell@linaro.org | ||
7 | --- | 11 | --- |
8 | target/arm/translate-sve.c | 61 +++++++++++++++++++++----------------- | 12 | target/arm/vec_helper.c | 8 ++++---- |
9 | 1 file changed, 33 insertions(+), 28 deletions(-) | 13 | 1 file changed, 4 insertions(+), 4 deletions(-) |
10 | 14 | ||
11 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | 15 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c |
12 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate-sve.c | 17 | --- a/target/arm/vec_helper.c |
14 | +++ b/target/arm/translate-sve.c | 18 | +++ b/target/arm/vec_helper.c |
15 | @@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) | 19 | @@ -XXX,XX +XXX,XX @@ DO_ABA(gvec_uaba_d, uint64_t) |
16 | int len_remain = len % 8; | 20 | r2 = float16_##OP(m[H2(0)], m[H2(1)], fpst); \ |
17 | int nparts = len / 8 + ctpop8(len_remain); | 21 | r3 = float16_##OP(m[H2(2)], m[H2(3)], fpst); \ |
18 | int midx = get_mem_index(s); | 22 | \ |
19 | - TCGv_i64 addr, t0, t1; | 23 | - d[H4(0)] = r0; \ |
20 | + TCGv_i64 dirty_addr, clean_addr, t0, t1; | 24 | - d[H4(1)] = r1; \ |
21 | 25 | - d[H4(2)] = r2; \ | |
22 | - addr = tcg_temp_new_i64(); | 26 | - d[H4(3)] = r3; \ |
23 | - t0 = tcg_temp_new_i64(); | 27 | + d[H2(0)] = r0; \ |
24 | + dirty_addr = tcg_temp_new_i64(); | 28 | + d[H2(1)] = r1; \ |
25 | + tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); | 29 | + d[H2(2)] = r2; \ |
26 | + clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len, MO_8); | 30 | + d[H2(3)] = r3; \ |
27 | + tcg_temp_free_i64(dirty_addr); | ||
28 | |||
29 | - /* Note that unpredicated load/store of vector/predicate registers | ||
30 | + /* | ||
31 | + * Note that unpredicated load/store of vector/predicate registers | ||
32 | * are defined as a stream of bytes, which equates to little-endian | ||
33 | - * operations on larger quantities. There is no nice way to force | ||
34 | - * a little-endian load for aarch64_be-linux-user out of line. | ||
35 | - * | ||
36 | + * operations on larger quantities. | ||
37 | * Attempt to keep code expansion to a minimum by limiting the | ||
38 | * amount of unrolling done. | ||
39 | */ | ||
40 | if (nparts <= 4) { | ||
41 | int i; | ||
42 | |||
43 | + t0 = tcg_temp_new_i64(); | ||
44 | for (i = 0; i < len_align; i += 8) { | ||
45 | - tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + i); | ||
46 | - tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LEQ); | ||
47 | + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEQ); | ||
48 | tcg_gen_st_i64(t0, cpu_env, vofs + i); | ||
49 | + tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8); | ||
50 | } | ||
51 | + tcg_temp_free_i64(t0); | ||
52 | } else { | ||
53 | TCGLabel *loop = gen_new_label(); | ||
54 | TCGv_ptr tp, i = tcg_const_local_ptr(0); | ||
55 | |||
56 | + /* Copy the clean address into a local temp, live across the loop. */ | ||
57 | + t0 = clean_addr; | ||
58 | + clean_addr = tcg_temp_local_new_i64(); | ||
59 | + tcg_gen_mov_i64(clean_addr, t0); | ||
60 | + tcg_temp_free_i64(t0); | ||
61 | + | ||
62 | gen_set_label(loop); | ||
63 | |||
64 | - /* Minimize the number of local temps that must be re-read from | ||
65 | - * the stack each iteration. Instead, re-compute values other | ||
66 | - * than the loop counter. | ||
67 | - */ | ||
68 | + t0 = tcg_temp_new_i64(); | ||
69 | + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEQ); | ||
70 | + tcg_gen_addi_i64(clean_addr, clean_addr, 8); | ||
71 | + | ||
72 | tp = tcg_temp_new_ptr(); | ||
73 | - tcg_gen_addi_ptr(tp, i, imm); | ||
74 | - tcg_gen_extu_ptr_i64(addr, tp); | ||
75 | - tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, rn)); | ||
76 | - | ||
77 | - tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LEQ); | ||
78 | - | ||
79 | tcg_gen_add_ptr(tp, cpu_env, i); | ||
80 | tcg_gen_addi_ptr(i, i, 8); | ||
81 | tcg_gen_st_i64(t0, tp, vofs); | ||
82 | tcg_temp_free_ptr(tp); | ||
83 | + tcg_temp_free_i64(t0); | ||
84 | |||
85 | tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); | ||
86 | tcg_temp_free_ptr(i); | ||
87 | } | 31 | } |
88 | 32 | ||
89 | - /* Predicate register loads can be any multiple of 2. | 33 | DO_NEON_PAIRWISE(neon_padd, add) |
90 | + /* | ||
91 | + * Predicate register loads can be any multiple of 2. | ||
92 | * Note that we still store the entire 64-bit unit into cpu_env. | ||
93 | */ | ||
94 | if (len_remain) { | ||
95 | - tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + len_align); | ||
96 | - | ||
97 | + t0 = tcg_temp_new_i64(); | ||
98 | switch (len_remain) { | ||
99 | case 2: | ||
100 | case 4: | ||
101 | case 8: | ||
102 | - tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LE | ctz32(len_remain)); | ||
103 | + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, | ||
104 | + MO_LE | ctz32(len_remain)); | ||
105 | break; | ||
106 | |||
107 | case 6: | ||
108 | t1 = tcg_temp_new_i64(); | ||
109 | - tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LEUL); | ||
110 | - tcg_gen_addi_i64(addr, addr, 4); | ||
111 | - tcg_gen_qemu_ld_i64(t1, addr, midx, MO_LEUW); | ||
112 | + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUL); | ||
113 | + tcg_gen_addi_i64(clean_addr, clean_addr, 4); | ||
114 | + tcg_gen_qemu_ld_i64(t1, clean_addr, midx, MO_LEUW); | ||
115 | tcg_gen_deposit_i64(t0, t0, t1, 32, 32); | ||
116 | tcg_temp_free_i64(t1); | ||
117 | break; | ||
118 | @@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) | ||
119 | g_assert_not_reached(); | ||
120 | } | ||
121 | tcg_gen_st_i64(t0, cpu_env, vofs + len_align); | ||
122 | + tcg_temp_free_i64(t0); | ||
123 | } | ||
124 | - tcg_temp_free_i64(addr); | ||
125 | - tcg_temp_free_i64(t0); | ||
126 | + tcg_temp_free_i64(clean_addr); | ||
127 | } | ||
128 | |||
129 | /* Similarly for stores. */ | ||
130 | -- | 34 | -- |
131 | 2.20.1 | 35 | 2.20.1 |
132 | 36 | ||
133 | 37 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | The helper functions for performing the udot/sdot operations against |
---|---|---|---|
2 | a scalar were not using an address-swizzling macro when converting | ||
3 | the index of the scalar element into a pointer into the vm array. | ||
4 | This had no effect on little-endian hosts but meant we generated | ||
5 | incorrect results on big-endian hosts. | ||
2 | 6 | ||
3 | We now implement all of the components of MTE, without actually | 7 | For these insns, the index is indexing over group of 4 8-bit values, |
4 | supporting any tagged memory. All MTE instructions will work, | 8 | so 32 bits per indexed entity, and H4() is therefore what we want. |
5 | trivially, so we can enable support. | 9 | (For Neon the only possible input indexes are 0 and 1.) |
6 | 10 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20200626033144.790098-46-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
14 | Message-id: 20201028191712.4910-3-peter.maydell@linaro.org | ||
11 | --- | 15 | --- |
12 | target/arm/cpu64.c | 5 +++++ | 16 | target/arm/vec_helper.c | 4 ++-- |
13 | 1 file changed, 5 insertions(+) | 17 | 1 file changed, 2 insertions(+), 2 deletions(-) |
14 | 18 | ||
15 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 19 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c |
16 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu64.c | 21 | --- a/target/arm/vec_helper.c |
18 | +++ b/target/arm/cpu64.c | 22 | +++ b/target/arm/vec_helper.c |
19 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 23 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sdot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc) |
20 | 24 | intptr_t index = simd_data(desc); | |
21 | t = cpu->isar.id_aa64pfr1; | 25 | uint32_t *d = vd; |
22 | t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); | 26 | int8_t *n = vn; |
23 | + /* | 27 | - int8_t *m_indexed = (int8_t *)vm + index * 4; |
24 | + * Begin with full support for MTE; will be downgraded to MTE=1 | 28 | + int8_t *m_indexed = (int8_t *)vm + H4(index) * 4; |
25 | + * during realize if the board provides no tag memory. | 29 | |
26 | + */ | 30 | /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd. |
27 | + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); | 31 | * Otherwise opr_sz is a multiple of 16. |
28 | cpu->isar.id_aa64pfr1 = t; | 32 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_udot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc) |
29 | 33 | intptr_t index = simd_data(desc); | |
30 | t = cpu->isar.id_aa64mmfr1; | 34 | uint32_t *d = vd; |
35 | uint8_t *n = vn; | ||
36 | - uint8_t *m_indexed = (uint8_t *)vm + index * 4; | ||
37 | + uint8_t *m_indexed = (uint8_t *)vm + H4(index) * 4; | ||
38 | |||
39 | /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd. | ||
40 | * Otherwise opr_sz is a multiple of 16. | ||
31 | -- | 41 | -- |
32 | 2.20.1 | 42 | 2.20.1 |
33 | 43 | ||
34 | 44 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | This "bit" is a particular value of the page's MemAttr. | 3 | HCR should be applied when NS is set, not when it is cleared. |
4 | 4 | ||
5 | Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20200626033144.790098-43-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 8 | --- |
10 | target/arm/helper.c | 48 ++++++++++++++++++++++++++++++++++++++--- | 9 | target/arm/helper.c | 5 ++--- |
11 | target/arm/tlb_helper.c | 5 +++++ | 10 | 1 file changed, 2 insertions(+), 3 deletions(-) |
12 | 2 files changed, 50 insertions(+), 3 deletions(-) | ||
13 | 11 | ||
14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 12 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
15 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper.c | 14 | --- a/target/arm/helper.c |
17 | +++ b/target/arm/helper.c | 15 | +++ b/target/arm/helper.c |
18 | @@ -XXX,XX +XXX,XX @@ static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2) | 16 | @@ -XXX,XX +XXX,XX @@ static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
17 | |||
18 | /* | ||
19 | * Non-IS variants of TLB operations are upgraded to | ||
20 | - * IS versions if we are at NS EL1 and HCR_EL2.FB is set to | ||
21 | + * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to | ||
22 | * force broadcast of these operations. | ||
19 | */ | 23 | */ |
20 | static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) | 24 | static bool tlb_force_broadcast(CPUARMState *env) |
21 | { | 25 | { |
22 | - uint8_t s1lo = extract32(s1.attrs, 0, 4), s2lo = extract32(s2.attrs, 0, 4); | 26 | - return (env->cp15.hcr_el2 & HCR_FB) && |
23 | - uint8_t s1hi = extract32(s1.attrs, 4, 4), s2hi = extract32(s2.attrs, 4, 4); | 27 | - arm_current_el(env) == 1 && arm_is_secure_below_el3(env); |
24 | + uint8_t s1lo, s2lo, s1hi, s2hi; | 28 | + return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB); |
25 | ARMCacheAttrs ret; | ||
26 | + bool tagged = false; | ||
27 | + | ||
28 | + if (s1.attrs == 0xf0) { | ||
29 | + tagged = true; | ||
30 | + s1.attrs = 0xff; | ||
31 | + } | ||
32 | + | ||
33 | + s1lo = extract32(s1.attrs, 0, 4); | ||
34 | + s2lo = extract32(s2.attrs, 0, 4); | ||
35 | + s1hi = extract32(s1.attrs, 4, 4); | ||
36 | + s2hi = extract32(s2.attrs, 4, 4); | ||
37 | |||
38 | /* Combine shareability attributes (table D4-43) */ | ||
39 | if (s1.shareability == 2 || s2.shareability == 2) { | ||
40 | @@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) | ||
41 | } | ||
42 | } | ||
43 | |||
44 | + /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */ | ||
45 | + if (tagged && ret.attrs == 0xff) { | ||
46 | + ret.attrs = 0xf0; | ||
47 | + } | ||
48 | + | ||
49 | return ret; | ||
50 | } | 29 | } |
51 | 30 | ||
52 | @@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address, | 31 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
53 | * Normal Non-Shareable, | ||
54 | * Inner Write-Back Read-Allocate Write-Allocate, | ||
55 | * Outer Write-Back Read-Allocate Write-Allocate. | ||
56 | + * Do not overwrite Tagged within attrs. | ||
57 | */ | ||
58 | - cacheattrs->attrs = 0xff; | ||
59 | + if (cacheattrs->attrs != 0xf0) { | ||
60 | + cacheattrs->attrs = 0xff; | ||
61 | + } | ||
62 | cacheattrs->shareability = 0; | ||
63 | } | ||
64 | *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2); | ||
65 | @@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address, | ||
66 | /* Definitely a real MMU, not an MPU */ | ||
67 | |||
68 | if (regime_translation_disabled(env, mmu_idx)) { | ||
69 | + uint64_t hcr; | ||
70 | + uint8_t memattr; | ||
71 | + | ||
72 | /* | ||
73 | * MMU disabled. S1 addresses within aa64 translation regimes are | ||
74 | * still checked for bounds -- see AArch64.TranslateAddressS1Off. | ||
75 | @@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address, | ||
76 | *phys_ptr = address; | ||
77 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | ||
78 | *page_size = TARGET_PAGE_SIZE; | ||
79 | + | ||
80 | + /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ | ||
81 | + hcr = arm_hcr_el2_eff(env); | ||
82 | + cacheattrs->shareability = 0; | ||
83 | + if (hcr & HCR_DC) { | ||
84 | + if (hcr & HCR_DCT) { | ||
85 | + memattr = 0xf0; /* Tagged, Normal, WB, RWA */ | ||
86 | + } else { | ||
87 | + memattr = 0xff; /* Normal, WB, RWA */ | ||
88 | + } | ||
89 | + } else if (access_type == MMU_INST_FETCH) { | ||
90 | + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { | ||
91 | + memattr = 0xee; /* Normal, WT, RA, NT */ | ||
92 | + } else { | ||
93 | + memattr = 0x44; /* Normal, NC, No */ | ||
94 | + } | ||
95 | + cacheattrs->shareability = 2; /* outer sharable */ | ||
96 | + } else { | ||
97 | + memattr = 0x00; /* Device, nGnRnE */ | ||
98 | + } | ||
99 | + cacheattrs->attrs = memattr; | ||
100 | return 0; | ||
101 | } | ||
102 | |||
103 | diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c | ||
104 | index XXXXXXX..XXXXXXX 100644 | ||
105 | --- a/target/arm/tlb_helper.c | ||
106 | +++ b/target/arm/tlb_helper.c | ||
107 | @@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
108 | phys_addr &= TARGET_PAGE_MASK; | ||
109 | address &= TARGET_PAGE_MASK; | ||
110 | } | ||
111 | + /* Notice and record tagged memory. */ | ||
112 | + if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs == 0xf0) { | ||
113 | + arm_tlb_mte_tagged(&attrs) = true; | ||
114 | + } | ||
115 | + | ||
116 | tlb_set_page_with_attrs(cs, address, phys_addr, attrs, | ||
117 | prot, mmu_idx, page_size); | ||
118 | return true; | ||
119 | -- | 32 | -- |
120 | 2.20.1 | 33 | 2.20.1 |
121 | 34 | ||
122 | 35 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | Like the regular data cache flushes, these are nops within qemu. | 3 | Secure mode is not exempted from checking SCR_EL3.TLOR, and in the |
4 | future HCR_EL2.TLOR when S-EL2 is enabled. | ||
4 | 5 | ||
6 | Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20200626033144.790098-21-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 9 | --- |
10 | target/arm/helper.c | 65 +++++++++++++++++++++++++++++++++++++++++++++ | 10 | target/arm/helper.c | 19 +++++-------------- |
11 | 1 file changed, 65 insertions(+) | 11 | 1 file changed, 5 insertions(+), 14 deletions(-) |
12 | 12 | ||
13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 13 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
14 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.c | 15 | --- a/target/arm/helper.c |
16 | +++ b/target/arm/helper.c | 16 | +++ b/target/arm/helper.c |
17 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = { | 17 | @@ -XXX,XX +XXX,XX @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | 18 | #endif |
19 | .type = ARM_CP_NO_RAW, | 19 | |
20 | .access = PL0_RW, .readfn = tco_read, .writefn = tco_write }, | 20 | /* Shared logic between LORID and the rest of the LOR* registers. |
21 | + { .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64, | 21 | - * Secure state has already been delt with. |
22 | + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3, | 22 | + * Secure state exclusion has already been dealt with. |
23 | + .type = ARM_CP_NOP, .access = PL1_W, | 23 | */ |
24 | + .accessfn = aa64_cacheop_poc_access }, | 24 | -static CPAccessResult access_lor_ns(CPUARMState *env) |
25 | + { .name = "DC_IGSW", .state = ARM_CP_STATE_AA64, | 25 | +static CPAccessResult access_lor_ns(CPUARMState *env, |
26 | + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4, | 26 | + const ARMCPRegInfo *ri, bool isread) |
27 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | 27 | { |
28 | + { .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64, | 28 | int el = arm_current_el(env); |
29 | + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5, | 29 | |
30 | + .type = ARM_CP_NOP, .access = PL1_W, | 30 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_ns(CPUARMState *env) |
31 | + .accessfn = aa64_cacheop_poc_access }, | 31 | return CP_ACCESS_OK; |
32 | + { .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64, | 32 | } |
33 | + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6, | 33 | |
34 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | 34 | -static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri, |
35 | + { .name = "DC_CGSW", .state = ARM_CP_STATE_AA64, | 35 | - bool isread) |
36 | + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4, | 36 | -{ |
37 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | 37 | - if (arm_is_secure_below_el3(env)) { |
38 | + { .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64, | 38 | - /* Access ok in secure mode. */ |
39 | + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6, | 39 | - return CP_ACCESS_OK; |
40 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | 40 | - } |
41 | + { .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64, | 41 | - return access_lor_ns(env); |
42 | + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4, | 42 | -} |
43 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | 43 | - |
44 | + { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64, | 44 | static CPAccessResult access_lor_other(CPUARMState *env, |
45 | + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6, | 45 | const ARMCPRegInfo *ri, bool isread) |
46 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | 46 | { |
47 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_other(CPUARMState *env, | ||
48 | /* Access denied in secure mode. */ | ||
49 | return CP_ACCESS_TRAP; | ||
50 | } | ||
51 | - return access_lor_ns(env); | ||
52 | + return access_lor_ns(env, ri, isread); | ||
53 | } | ||
54 | |||
55 | /* | ||
56 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = { | ||
57 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
58 | { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, | ||
59 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, | ||
60 | - .access = PL1_R, .accessfn = access_lorid, | ||
61 | + .access = PL1_R, .accessfn = access_lor_ns, | ||
62 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
47 | REGINFO_SENTINEL | 63 | REGINFO_SENTINEL |
48 | }; | 64 | }; |
49 | |||
50 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_tco_ro_reginfo[] = { | ||
51 | .type = ARM_CP_CONST, .access = PL0_RW, }, | ||
52 | REGINFO_SENTINEL | ||
53 | }; | ||
54 | + | ||
55 | +static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | ||
56 | + { .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64, | ||
57 | + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3, | ||
58 | + .type = ARM_CP_NOP, .access = PL0_W, | ||
59 | + .accessfn = aa64_cacheop_poc_access }, | ||
60 | + { .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64, | ||
61 | + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5, | ||
62 | + .type = ARM_CP_NOP, .access = PL0_W, | ||
63 | + .accessfn = aa64_cacheop_poc_access }, | ||
64 | + { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64, | ||
65 | + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3, | ||
66 | + .type = ARM_CP_NOP, .access = PL0_W, | ||
67 | + .accessfn = aa64_cacheop_poc_access }, | ||
68 | + { .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64, | ||
69 | + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5, | ||
70 | + .type = ARM_CP_NOP, .access = PL0_W, | ||
71 | + .accessfn = aa64_cacheop_poc_access }, | ||
72 | + { .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64, | ||
73 | + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3, | ||
74 | + .type = ARM_CP_NOP, .access = PL0_W, | ||
75 | + .accessfn = aa64_cacheop_poc_access }, | ||
76 | + { .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64, | ||
77 | + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5, | ||
78 | + .type = ARM_CP_NOP, .access = PL0_W, | ||
79 | + .accessfn = aa64_cacheop_poc_access }, | ||
80 | + { .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64, | ||
81 | + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3, | ||
82 | + .type = ARM_CP_NOP, .access = PL0_W, | ||
83 | + .accessfn = aa64_cacheop_poc_access }, | ||
84 | + { .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64, | ||
85 | + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, | ||
86 | + .type = ARM_CP_NOP, .access = PL0_W, | ||
87 | + .accessfn = aa64_cacheop_poc_access }, | ||
88 | + REGINFO_SENTINEL | ||
89 | +}; | ||
90 | + | ||
91 | #endif | ||
92 | |||
93 | static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, | ||
94 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
95 | */ | ||
96 | if (cpu_isar_feature(aa64_mte, cpu)) { | ||
97 | define_arm_cp_regs(cpu, mte_reginfo); | ||
98 | + define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); | ||
99 | } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { | ||
100 | define_arm_cp_regs(cpu, mte_tco_ro_reginfo); | ||
101 | + define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); | ||
102 | } | ||
103 | #endif | ||
104 | |||
105 | -- | 65 | -- |
106 | 2.20.1 | 66 | 2.20.1 |
107 | 67 | ||
108 | 68 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | If we're using the capstone disassembler, disassembly of a run of |
---|---|---|---|
2 | instructions more than 32 bytes long disassembles the wrong data for | ||
3 | instructions beyond the 32 byte mark: | ||
2 | 4 | ||
3 | This is DC GVA and DC GZVA, and the tag check for DC ZVA. | 5 | (qemu) xp /16x 0x100 |
6 | 0000000000000100: 0x00000005 0x54410001 0x00000001 0x00001000 | ||
7 | 0000000000000110: 0x00000000 0x00000004 0x54410002 0x3c000000 | ||
8 | 0000000000000120: 0x00000000 0x00000004 0x54410009 0x74736574 | ||
9 | 0000000000000130: 0x00000000 0x00000000 0x00000000 0x00000000 | ||
10 | (qemu) xp /16i 0x100 | ||
11 | 0x00000100: 00000005 andeq r0, r0, r5 | ||
12 | 0x00000104: 54410001 strbpl r0, [r1], #-1 | ||
13 | 0x00000108: 00000001 andeq r0, r0, r1 | ||
14 | 0x0000010c: 00001000 andeq r1, r0, r0 | ||
15 | 0x00000110: 00000000 andeq r0, r0, r0 | ||
16 | 0x00000114: 00000004 andeq r0, r0, r4 | ||
17 | 0x00000118: 54410002 strbpl r0, [r1], #-2 | ||
18 | 0x0000011c: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c | ||
19 | 0x00000120: 54410001 strbpl r0, [r1], #-1 | ||
20 | 0x00000124: 00000001 andeq r0, r0, r1 | ||
21 | 0x00000128: 00001000 andeq r1, r0, r0 | ||
22 | 0x0000012c: 00000000 andeq r0, r0, r0 | ||
23 | 0x00000130: 00000004 andeq r0, r0, r4 | ||
24 | 0x00000134: 54410002 strbpl r0, [r1], #-2 | ||
25 | 0x00000138: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c | ||
26 | 0x0000013c: 00000000 andeq r0, r0, r0 | ||
4 | 27 | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 28 | Here the disassembly of 0x120..0x13f is using the data that is in |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 29 | 0x104..0x123. |
7 | Message-id: 20200626033144.790098-40-richard.henderson@linaro.org | 30 | |
31 | This is caused by passing the wrong value to the read_memory_func(). | ||
32 | The intention is that at this point in the loop the 'cap_buf' buffer | ||
33 | already contains 'csize' bytes of data for the instruction at guest | ||
34 | addr 'pc', and we want to read in an extra 'tsize' bytes. Those | ||
35 | extra bytes are therefore at 'pc + csize', not 'pc'. On the first | ||
36 | time through the loop 'csize' happens to be zero, so the initial read | ||
37 | of 32 bytes into cap_buf is correct and as long as the disassembly | ||
38 | never needs to read more data we return the correct information. | ||
39 | |||
40 | Use the correct guest address in the call to read_memory_func(). | ||
41 | |||
42 | Cc: qemu-stable@nongnu.org | ||
43 | Fixes: https://bugs.launchpad.net/qemu/+bug/1900779 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 44 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
45 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
46 | Message-id: 20201022132445.25039-1-peter.maydell@linaro.org | ||
9 | --- | 47 | --- |
10 | target/arm/cpu.h | 4 +++- | 48 | disas/capstone.c | 2 +- |
11 | target/arm/helper.c | 16 ++++++++++++++++ | 49 | 1 file changed, 1 insertion(+), 1 deletion(-) |
12 | target/arm/translate-a64.c | 39 ++++++++++++++++++++++++++++++++++++++ | ||
13 | 3 files changed, 58 insertions(+), 1 deletion(-) | ||
14 | 50 | ||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 51 | diff --git a/disas/capstone.c b/disas/capstone.c |
16 | index XXXXXXX..XXXXXXX 100644 | 52 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu.h | 53 | --- a/disas/capstone.c |
18 | +++ b/target/arm/cpu.h | 54 | +++ b/disas/capstone.c |
19 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | 55 | @@ -XXX,XX +XXX,XX @@ bool cap_disas_monitor(disassemble_info *info, uint64_t pc, int count) |
20 | #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) | 56 | |
21 | #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) | 57 | /* Make certain that we can make progress. */ |
22 | #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) | 58 | assert(tsize != 0); |
23 | -#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA | 59 | - info->read_memory_func(pc, cap_buf + csize, tsize, info); |
24 | +#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) | 60 | + info->read_memory_func(pc + csize, cap_buf + csize, tsize, info); |
25 | +#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) | 61 | csize += tsize; |
26 | +#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA | 62 | |
27 | #define ARM_CP_FPU 0x1000 | 63 | if (cs_disasm_iter(handle, &cbuf, &csize, &pc, insn)) { |
28 | #define ARM_CP_SVE 0x2000 | ||
29 | #define ARM_CP_NO_GDB 0x4000 | ||
30 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/helper.c | ||
33 | +++ b/target/arm/helper.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | ||
35 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, | ||
36 | .type = ARM_CP_NOP, .access = PL0_W, | ||
37 | .accessfn = aa64_cacheop_poc_access }, | ||
38 | + { .name = "DC_GVA", .state = ARM_CP_STATE_AA64, | ||
39 | + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3, | ||
40 | + .access = PL0_W, .type = ARM_CP_DC_GVA, | ||
41 | +#ifndef CONFIG_USER_ONLY | ||
42 | + /* Avoid overhead of an access check that always passes in user-mode */ | ||
43 | + .accessfn = aa64_zva_access, | ||
44 | +#endif | ||
45 | + }, | ||
46 | + { .name = "DC_GZVA", .state = ARM_CP_STATE_AA64, | ||
47 | + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4, | ||
48 | + .access = PL0_W, .type = ARM_CP_DC_GZVA, | ||
49 | +#ifndef CONFIG_USER_ONLY | ||
50 | + /* Avoid overhead of an access check that always passes in user-mode */ | ||
51 | + .accessfn = aa64_zva_access, | ||
52 | +#endif | ||
53 | + }, | ||
54 | REGINFO_SENTINEL | ||
55 | }; | ||
56 | |||
57 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
58 | index XXXXXXX..XXXXXXX 100644 | ||
59 | --- a/target/arm/translate-a64.c | ||
60 | +++ b/target/arm/translate-a64.c | ||
61 | @@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | ||
62 | } | ||
63 | gen_helper_dc_zva(cpu_env, tcg_rt); | ||
64 | return; | ||
65 | + case ARM_CP_DC_GVA: | ||
66 | + { | ||
67 | + TCGv_i64 clean_addr, tag; | ||
68 | + | ||
69 | + /* | ||
70 | + * DC_GVA, like DC_ZVA, requires that we supply the original | ||
71 | + * pointer for an invalid page. Probe that address first. | ||
72 | + */ | ||
73 | + tcg_rt = cpu_reg(s, rt); | ||
74 | + clean_addr = clean_data_tbi(s, tcg_rt); | ||
75 | + gen_probe_access(s, clean_addr, MMU_DATA_STORE, MO_8); | ||
76 | + | ||
77 | + if (s->ata) { | ||
78 | + /* Extract the tag from the register to match STZGM. */ | ||
79 | + tag = tcg_temp_new_i64(); | ||
80 | + tcg_gen_shri_i64(tag, tcg_rt, 56); | ||
81 | + gen_helper_stzgm_tags(cpu_env, clean_addr, tag); | ||
82 | + tcg_temp_free_i64(tag); | ||
83 | + } | ||
84 | + } | ||
85 | + return; | ||
86 | + case ARM_CP_DC_GZVA: | ||
87 | + { | ||
88 | + TCGv_i64 clean_addr, tag; | ||
89 | + | ||
90 | + /* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */ | ||
91 | + tcg_rt = cpu_reg(s, rt); | ||
92 | + clean_addr = clean_data_tbi(s, tcg_rt); | ||
93 | + gen_helper_dc_zva(cpu_env, clean_addr); | ||
94 | + | ||
95 | + if (s->ata) { | ||
96 | + /* Extract the tag from the register to match STZGM. */ | ||
97 | + tag = tcg_temp_new_i64(); | ||
98 | + tcg_gen_shri_i64(tag, tcg_rt, 56); | ||
99 | + gen_helper_stzgm_tags(cpu_env, clean_addr, tag); | ||
100 | + tcg_temp_free_i64(tag); | ||
101 | + } | ||
102 | + } | ||
103 | + return; | ||
104 | default: | ||
105 | break; | ||
106 | } | ||
107 | -- | 64 | -- |
108 | 2.20.1 | 65 | 2.20.1 |
109 | 66 | ||
110 | 67 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | We still need to handle tbi for user-only when mte is inactive. | 3 | Use the BIT_ULL() macro to ensure we use 64-bit arithmetic. |
4 | This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN): | ||
4 | 5 | ||
6 | CID 1432363 (#1 of 1): Unintentional integer overflow: | ||
7 | |||
8 | overflow_before_widen: | ||
9 | Potentially overflowing expression 1 << scale with type int | ||
10 | (32 bits, signed) is evaluated using 32-bit arithmetic, and | ||
11 | then used in a context that expects an expression of type | ||
12 | hwaddr (64 bits, unsigned). | ||
13 | |||
14 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
15 | Acked-by: Eric Auger <eric.auger@redhat.com> | ||
16 | Message-id: 20201030144617.1535064-1-philmd@redhat.com | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20200626033144.790098-37-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 19 | --- |
10 | target/arm/translate-a64.h | 1 + | 20 | hw/arm/smmuv3.c | 3 ++- |
11 | target/arm/translate-a64.c | 2 +- | 21 | 1 file changed, 2 insertions(+), 1 deletion(-) |
12 | target/arm/translate-sve.c | 6 ++++-- | ||
13 | 3 files changed, 6 insertions(+), 3 deletions(-) | ||
14 | 22 | ||
15 | diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h | 23 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c |
16 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate-a64.h | 25 | --- a/hw/arm/smmuv3.c |
18 | +++ b/target/arm/translate-a64.h | 26 | +++ b/hw/arm/smmuv3.c |
19 | @@ -XXX,XX +XXX,XX @@ TCGv_ptr get_fpstatus_ptr(bool); | 27 | @@ -XXX,XX +XXX,XX @@ |
20 | bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, | ||
21 | unsigned int imms, unsigned int immr); | ||
22 | bool sve_access_check(DisasContext *s); | ||
23 | +TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); | ||
24 | TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, | ||
25 | bool tag_checked, int log2_size); | ||
26 | TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, | ||
27 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/translate-a64.c | ||
30 | +++ b/target/arm/translate-a64.c | ||
31 | @@ -XXX,XX +XXX,XX @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) | ||
32 | * of the write-back address. | ||
33 | */ | 28 | */ |
34 | 29 | ||
35 | -static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) | 30 | #include "qemu/osdep.h" |
36 | +TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) | 31 | +#include "qemu/bitops.h" |
37 | { | 32 | #include "hw/irq.h" |
38 | TCGv_i64 clean = new_tmp_a64(s); | 33 | #include "hw/sysbus.h" |
39 | #ifdef CONFIG_USER_ONLY | 34 | #include "migration/vmstate.h" |
40 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | 35 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd) |
41 | index XXXXXXX..XXXXXXX 100644 | 36 | scale = CMD_SCALE(cmd); |
42 | --- a/target/arm/translate-sve.c | 37 | num = CMD_NUM(cmd); |
43 | +++ b/target/arm/translate-sve.c | 38 | ttl = CMD_TTL(cmd); |
44 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | 39 | - num_pages = (num + 1) * (1 << (scale)); |
45 | * For e.g. LD4, there are not enough arguments to pass all 4 | 40 | + num_pages = (num + 1) * BIT_ULL(scale); |
46 | * registers as pointers, so encode the regno into the data field. | ||
47 | * For consistency, do this even for LD1. | ||
48 | - * TODO: mte_n check here while callers are updated. | ||
49 | */ | ||
50 | - if (mte_n && s->mte_active[0]) { | ||
51 | + if (s->mte_active[0]) { | ||
52 | int msz = dtype_msz(dtype); | ||
53 | |||
54 | desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | ||
55 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | ||
56 | desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz); | ||
57 | desc = FIELD_DP32(desc, MTEDESC, TSIZE, mte_n << msz); | ||
58 | desc <<= SVE_MTEDESC_SHIFT; | ||
59 | + } else { | ||
60 | + addr = clean_data_tbi(s, addr); | ||
61 | } | 41 | } |
62 | + | 42 | |
63 | desc = simd_desc(vsz, vsz, zt | desc); | 43 | if (type == SMMU_CMD_TLBI_NH_VA) { |
64 | t_desc = tcg_const_i32(desc); | ||
65 | t_pg = tcg_temp_new_ptr(); | ||
66 | -- | 44 | -- |
67 | 2.20.1 | 45 | 2.20.1 |
68 | 46 | ||
69 | 47 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | D1.10 specifies that exception handlers begin with tag checks overridden. | 3 | When booting a CPU with EL3 using the -kernel flag, set up CPTR_EL3 so |
4 | that SVE will not trap to EL3. | ||
4 | 5 | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20200626033144.790098-41-richard.henderson@linaro.org | 8 | Message-id: 20201030151541.11976-1-remi@remlab.net |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | target/arm/helper.c | 3 +++ | 11 | hw/arm/boot.c | 3 +++ |
11 | 1 file changed, 3 insertions(+) | 12 | 1 file changed, 3 insertions(+) |
12 | 13 | ||
13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 14 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c |
14 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.c | 16 | --- a/hw/arm/boot.c |
16 | +++ b/target/arm/helper.c | 17 | +++ b/hw/arm/boot.c |
17 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | 18 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) |
18 | break; | 19 | if (cpu_isar_feature(aa64_mte, cpu)) { |
19 | } | 20 | env->cp15.scr_el3 |= SCR_ATA; |
20 | } | 21 | } |
21 | + if (cpu_isar_feature(aa64_mte, cpu)) { | 22 | + if (cpu_isar_feature(aa64_sve, cpu)) { |
22 | + new_mode |= PSTATE_TCO; | 23 | + env->cp15.cptr_el[3] |= CPTR_EZ; |
23 | + } | 24 | + } |
24 | 25 | /* AArch64 kernels never boot in secure mode */ | |
25 | pstate_write(env, PSTATE_DAIF | new_mode); | 26 | assert(!info->secure_boot); |
26 | env->aarch64 = 1; | 27 | /* This hook is only supported for AArch32 currently: |
27 | -- | 28 | -- |
28 | 2.20.1 | 29 | 2.20.1 |
29 | 30 | ||
30 | 31 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: AlexChen <alex.chen@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | In omap_lcd_interrupts(), the pointer omap_lcd is dereferinced before | ||
4 | being check if it is valid, which may lead to NULL pointer dereference. | ||
5 | So move the assignment to surface after checking that the omap_lcd is valid | ||
6 | and move surface_bits_per_pixel(surface) to after the surface assignment. | ||
7 | |||
8 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
9 | Signed-off-by: AlexChen <alex.chen@huawei.com> | ||
10 | Message-id: 5F9CDB8A.9000001@huawei.com | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20200626033144.790098-20-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 13 | --- |
8 | target/arm/helper-a64.h | 3 ++ | 14 | hw/display/omap_lcdc.c | 10 +++++++--- |
9 | target/arm/translate.h | 2 + | 15 | 1 file changed, 7 insertions(+), 3 deletions(-) |
10 | target/arm/mte_helper.c | 84 ++++++++++++++++++++++++++++++++++++++ | ||
11 | target/arm/translate-a64.c | 72 ++++++++++++++++++++++++++++---- | ||
12 | 4 files changed, 153 insertions(+), 8 deletions(-) | ||
13 | 16 | ||
14 | diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h | 17 | diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c |
15 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper-a64.h | 19 | --- a/hw/display/omap_lcdc.c |
17 | +++ b/target/arm/helper-a64.h | 20 | +++ b/hw/display/omap_lcdc.c |
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(stg_stub, TCG_CALL_NO_WG, void, env, i64) | 21 | @@ -XXX,XX +XXX,XX @@ static void omap_lcd_interrupts(struct omap_lcd_panel_s *s) |
19 | DEF_HELPER_FLAGS_3(st2g, TCG_CALL_NO_WG, void, env, i64, i64) | 22 | static void omap_update_display(void *opaque) |
20 | DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64) | 23 | { |
21 | DEF_HELPER_FLAGS_2(st2g_stub, TCG_CALL_NO_WG, void, env, i64) | 24 | struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque; |
22 | +DEF_HELPER_FLAGS_2(ldgm, TCG_CALL_NO_WG, i64, env, i64) | 25 | - DisplaySurface *surface = qemu_console_surface(omap_lcd->con); |
23 | +DEF_HELPER_FLAGS_3(stgm, TCG_CALL_NO_WG, void, env, i64, i64) | 26 | + DisplaySurface *surface; |
24 | +DEF_HELPER_FLAGS_3(stzgm_tags, TCG_CALL_NO_WG, void, env, i64, i64) | 27 | draw_line_func draw_line; |
25 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 28 | int size, height, first, last; |
26 | index XXXXXXX..XXXXXXX 100644 | 29 | int width, linesize, step, bpp, frame_offset; |
27 | --- a/target/arm/translate.h | 30 | hwaddr frame_base; |
28 | +++ b/target/arm/translate.h | 31 | |
29 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | 32 | - if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable || |
30 | * < 0, set by the current instruction. | 33 | - !surface_bits_per_pixel(surface)) { |
31 | */ | 34 | + if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable) { |
32 | int8_t btype; | ||
33 | + /* A copy of cpu->dcz_blocksize. */ | ||
34 | + uint8_t dcz_blocksize; | ||
35 | /* True if this page is guarded. */ | ||
36 | bool guarded_page; | ||
37 | /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ | ||
38 | diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/target/arm/mte_helper.c | ||
41 | +++ b/target/arm/mte_helper.c | ||
42 | @@ -XXX,XX +XXX,XX @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr) | ||
43 | probe_write(env, ptr + TAG_GRANULE, TAG_GRANULE, mmu_idx, ra); | ||
44 | } | ||
45 | } | ||
46 | + | ||
47 | +#define LDGM_STGM_SIZE (4 << GMID_EL1_BS) | ||
48 | + | ||
49 | +uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) | ||
50 | +{ | ||
51 | + int mmu_idx = cpu_mmu_index(env, false); | ||
52 | + uintptr_t ra = GETPC(); | ||
53 | + void *tag_mem; | ||
54 | + | ||
55 | + ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE); | ||
56 | + | ||
57 | + /* Trap if accessing an invalid page. */ | ||
58 | + tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD, | ||
59 | + LDGM_STGM_SIZE, MMU_DATA_LOAD, | ||
60 | + LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra); | ||
61 | + | ||
62 | + /* The tag is squashed to zero if the page does not support tags. */ | ||
63 | + if (!tag_mem) { | ||
64 | + return 0; | ||
65 | + } | ||
66 | + | ||
67 | + QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6); | ||
68 | + /* | ||
69 | + * We are loading 64-bits worth of tags. The ordering of elements | ||
70 | + * within the word corresponds to a 64-bit little-endian operation. | ||
71 | + */ | ||
72 | + return ldq_le_p(tag_mem); | ||
73 | +} | ||
74 | + | ||
75 | +void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) | ||
76 | +{ | ||
77 | + int mmu_idx = cpu_mmu_index(env, false); | ||
78 | + uintptr_t ra = GETPC(); | ||
79 | + void *tag_mem; | ||
80 | + | ||
81 | + ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE); | ||
82 | + | ||
83 | + /* Trap if accessing an invalid page. */ | ||
84 | + tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, | ||
85 | + LDGM_STGM_SIZE, MMU_DATA_LOAD, | ||
86 | + LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra); | ||
87 | + | ||
88 | + /* | ||
89 | + * Tag store only happens if the page support tags, | ||
90 | + * and if the OS has enabled access to the tags. | ||
91 | + */ | ||
92 | + if (!tag_mem) { | ||
93 | + return; | 35 | + return; |
94 | + } | 36 | + } |
95 | + | 37 | + |
96 | + QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6); | 38 | + surface = qemu_console_surface(omap_lcd->con); |
97 | + /* | 39 | + if (!surface_bits_per_pixel(surface)) { |
98 | + * We are storing 64-bits worth of tags. The ordering of elements | ||
99 | + * within the word corresponds to a 64-bit little-endian operation. | ||
100 | + */ | ||
101 | + stq_le_p(tag_mem, val); | ||
102 | +} | ||
103 | + | ||
104 | +void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val) | ||
105 | +{ | ||
106 | + uintptr_t ra = GETPC(); | ||
107 | + int mmu_idx = cpu_mmu_index(env, false); | ||
108 | + int log2_dcz_bytes, log2_tag_bytes; | ||
109 | + intptr_t dcz_bytes, tag_bytes; | ||
110 | + uint8_t *mem; | ||
111 | + | ||
112 | + /* | ||
113 | + * In arm_cpu_realizefn, we assert that dcz > LOG2_TAG_GRANULE+1, | ||
114 | + * i.e. 32 bytes, which is an unreasonably small dcz anyway, | ||
115 | + * to make sure that we can access one complete tag byte here. | ||
116 | + */ | ||
117 | + log2_dcz_bytes = env_archcpu(env)->dcz_blocksize + 2; | ||
118 | + log2_tag_bytes = log2_dcz_bytes - (LOG2_TAG_GRANULE + 1); | ||
119 | + dcz_bytes = (intptr_t)1 << log2_dcz_bytes; | ||
120 | + tag_bytes = (intptr_t)1 << log2_tag_bytes; | ||
121 | + ptr &= -dcz_bytes; | ||
122 | + | ||
123 | + mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, dcz_bytes, | ||
124 | + MMU_DATA_STORE, tag_bytes, ra); | ||
125 | + if (mem) { | ||
126 | + int tag_pair = (val & 0xf) * 0x11; | ||
127 | + memset(mem, tag_pair, tag_bytes); | ||
128 | + } | ||
129 | +} | ||
130 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
131 | index XXXXXXX..XXXXXXX 100644 | ||
132 | --- a/target/arm/translate-a64.c | ||
133 | +++ b/target/arm/translate-a64.c | ||
134 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) | ||
135 | uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; | ||
136 | int op2 = extract32(insn, 10, 2); | ||
137 | int op1 = extract32(insn, 22, 2); | ||
138 | - bool is_load = false, is_pair = false, is_zero = false; | ||
139 | + bool is_load = false, is_pair = false, is_zero = false, is_mult = false; | ||
140 | int index = 0; | ||
141 | TCGv_i64 addr, clean_addr, tcg_rt; | ||
142 | |||
143 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) | ||
144 | if (op2 != 0) { | ||
145 | /* STG */ | ||
146 | index = op2 - 2; | ||
147 | - break; | ||
148 | + } else { | ||
149 | + /* STZGM */ | ||
150 | + if (s->current_el == 0 || offset != 0) { | ||
151 | + goto do_unallocated; | ||
152 | + } | ||
153 | + is_mult = is_zero = true; | ||
154 | } | ||
155 | - goto do_unallocated; | ||
156 | + break; | ||
157 | case 1: | ||
158 | if (op2 != 0) { | ||
159 | /* STZG */ | ||
160 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) | ||
161 | /* ST2G */ | ||
162 | is_pair = true; | ||
163 | index = op2 - 2; | ||
164 | - break; | ||
165 | + } else { | ||
166 | + /* STGM */ | ||
167 | + if (s->current_el == 0 || offset != 0) { | ||
168 | + goto do_unallocated; | ||
169 | + } | ||
170 | + is_mult = true; | ||
171 | } | ||
172 | - goto do_unallocated; | ||
173 | + break; | ||
174 | case 3: | ||
175 | if (op2 != 0) { | ||
176 | /* STZ2G */ | ||
177 | is_pair = is_zero = true; | ||
178 | index = op2 - 2; | ||
179 | - break; | ||
180 | + } else { | ||
181 | + /* LDGM */ | ||
182 | + if (s->current_el == 0 || offset != 0) { | ||
183 | + goto do_unallocated; | ||
184 | + } | ||
185 | + is_mult = is_load = true; | ||
186 | } | ||
187 | - goto do_unallocated; | ||
188 | + break; | ||
189 | |||
190 | default: | ||
191 | do_unallocated: | ||
192 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) | ||
193 | return; | 40 | return; |
194 | } | 41 | } |
195 | 42 | ||
196 | - if (!dc_isar_feature(aa64_mte_insn_reg, s)) { | ||
197 | + if (is_mult | ||
198 | + ? !dc_isar_feature(aa64_mte, s) | ||
199 | + : !dc_isar_feature(aa64_mte_insn_reg, s)) { | ||
200 | goto do_unallocated; | ||
201 | } | ||
202 | |||
203 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) | ||
204 | tcg_gen_addi_i64(addr, addr, offset); | ||
205 | } | ||
206 | |||
207 | + if (is_mult) { | ||
208 | + tcg_rt = cpu_reg(s, rt); | ||
209 | + | ||
210 | + if (is_zero) { | ||
211 | + int size = 4 << s->dcz_blocksize; | ||
212 | + | ||
213 | + if (s->ata) { | ||
214 | + gen_helper_stzgm_tags(cpu_env, addr, tcg_rt); | ||
215 | + } | ||
216 | + /* | ||
217 | + * The non-tags portion of STZGM is mostly like DC_ZVA, | ||
218 | + * except the alignment happens before the access. | ||
219 | + */ | ||
220 | + clean_addr = clean_data_tbi(s, addr); | ||
221 | + tcg_gen_andi_i64(clean_addr, clean_addr, -size); | ||
222 | + gen_helper_dc_zva(cpu_env, clean_addr); | ||
223 | + } else if (s->ata) { | ||
224 | + if (is_load) { | ||
225 | + gen_helper_ldgm(tcg_rt, cpu_env, addr); | ||
226 | + } else { | ||
227 | + gen_helper_stgm(cpu_env, addr, tcg_rt); | ||
228 | + } | ||
229 | + } else { | ||
230 | + MMUAccessType acc = is_load ? MMU_DATA_LOAD : MMU_DATA_STORE; | ||
231 | + int size = 4 << GMID_EL1_BS; | ||
232 | + | ||
233 | + clean_addr = clean_data_tbi(s, addr); | ||
234 | + tcg_gen_andi_i64(clean_addr, clean_addr, -size); | ||
235 | + gen_probe_access(s, clean_addr, acc, size); | ||
236 | + | ||
237 | + if (is_load) { | ||
238 | + /* The result tags are zeros. */ | ||
239 | + tcg_gen_movi_i64(tcg_rt, 0); | ||
240 | + } | ||
241 | + } | ||
242 | + return; | ||
243 | + } | ||
244 | + | ||
245 | if (is_load) { | ||
246 | tcg_gen_andi_i64(addr, addr, -TAG_GRANULE); | ||
247 | tcg_rt = cpu_reg(s, rt); | ||
248 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, | ||
249 | dc->vec_stride = 0; | ||
250 | dc->cp_regs = arm_cpu->cp_regs; | ||
251 | dc->features = env->features; | ||
252 | + dc->dcz_blocksize = arm_cpu->dcz_blocksize; | ||
253 | |||
254 | /* Single step state. The code-generation logic here is: | ||
255 | * SS_ACTIVE == 0: | ||
256 | -- | 43 | -- |
257 | 2.20.1 | 44 | 2.20.1 |
258 | 45 | ||
259 | 46 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: AlexChen <alex.chen@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | This does not attempt to rectify all of the res0 bits, but does | 3 | In exynos4210_fimd_update(), the pointer s is dereferinced before |
4 | clear the mte bits when not enabled. Since there is no high-part | 4 | being check if it is valid, which may lead to NULL pointer dereference. |
5 | mapping of SCTLR, aa32 mode cannot write to these bits. | 5 | So move the assignment to global_width after checking that the s is valid. |
6 | 6 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reported-by: Euler Robot <euler.robot@huawei.com> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Alex Chen <alex.chen@huawei.com> |
9 | Message-id: 20200626033144.790098-4-richard.henderson@linaro.org | 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
10 | Message-id: 5F9F8D88.9030102@huawei.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 12 | --- |
12 | target/arm/helper.c | 23 +++++++++++++++++------ | 13 | hw/display/exynos4210_fimd.c | 4 +++- |
13 | 1 file changed, 17 insertions(+), 6 deletions(-) | 14 | 1 file changed, 3 insertions(+), 1 deletion(-) |
14 | 15 | ||
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 16 | diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c |
16 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper.c | 18 | --- a/hw/display/exynos4210_fimd.c |
18 | +++ b/target/arm/helper.c | 19 | +++ b/hw/display/exynos4210_fimd.c |
19 | @@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, | 20 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_fimd_update(void *opaque) |
20 | { | 21 | bool blend = false; |
21 | ARMCPU *cpu = env_archcpu(env); | 22 | uint8_t *host_fb_addr; |
22 | 23 | bool is_dirty = false; | |
23 | + if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { | 24 | - const int global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1; |
24 | + /* M bit is RAZ/WI for PMSA with no MPU implemented */ | 25 | + int global_width; |
25 | + value &= ~SCTLR_M; | 26 | |
26 | + } | 27 | if (!s || !s->console || !s->enabled || |
27 | + | 28 | surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) { |
28 | + /* ??? Lots of these bits are not implemented. */ | ||
29 | + | ||
30 | + if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) { | ||
31 | + if (ri->opc1 == 6) { /* SCTLR_EL3 */ | ||
32 | + value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); | ||
33 | + } else { | ||
34 | + value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | | ||
35 | + SCTLR_ATA0 | SCTLR_ATA); | ||
36 | + } | ||
37 | + } | ||
38 | + | ||
39 | if (raw_read(env, ri) == value) { | ||
40 | /* Skip the TLB flush if nothing actually changed; Linux likes | ||
41 | * to do a lot of pointless SCTLR writes. | ||
42 | @@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
43 | return; | 29 | return; |
44 | } | 30 | } |
45 | |||
46 | - if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { | ||
47 | - /* M bit is RAZ/WI for PMSA with no MPU implemented */ | ||
48 | - value &= ~SCTLR_M; | ||
49 | - } | ||
50 | - | ||
51 | raw_write(env, ri, value); | ||
52 | - /* ??? Lots of these bits are not implemented. */ | ||
53 | + | 31 | + |
54 | /* This may enable/disable the MMU, so do a TLB flush. */ | 32 | + global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1; |
55 | tlb_flush(CPU(cpu)); | 33 | exynos4210_update_resolution(s); |
34 | surface = qemu_console_surface(s->console); | ||
56 | 35 | ||
57 | -- | 36 | -- |
58 | 2.20.1 | 37 | 2.20.1 |
59 | 38 | ||
60 | 39 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | In arm_v7m_mmu_idx_for_secstate() we get the 'priv' level to pass to |
---|---|---|---|
2 | armv7m_mmu_idx_for_secstate_and_priv() by calling arm_current_el(). | ||
3 | This is incorrect when the security state being queried is not the | ||
4 | current one, because arm_current_el() uses the current security state | ||
5 | to determine which of the banked CONTROL.nPRIV bits to look at. | ||
6 | The effect was that if (for instance) Secure state was in privileged | ||
7 | mode but Non-Secure was not then we would return the wrong MMU index. | ||
2 | 8 | ||
3 | We need to check the memattr of a page in order to determine | 9 | The only places where we are using this function in a way that could |
4 | whether it is Tagged for MTE. Between Stage1 and Stage2, | 10 | trigger this bug are for the stack loads during a v8M function-return |
5 | this becomes simpler if we always collect this data, instead | 11 | and for the instruction fetch of a v8M SG insn. |
6 | of occasionally being presented with NULL. | ||
7 | 12 | ||
8 | Use the nonnull attribute to allow the compiler to check that | 13 | Fix the bug by expanding out the M-profile version of the |
9 | all pointer arguments are non-null. | 14 | arm_current_el() logic inline so it can use the passed in secstate |
15 | rather than env->v7m.secure. | ||
10 | 16 | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Message-id: 20200626033144.790098-42-richard.henderson@linaro.org | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
19 | Message-id: 20201022164408.13214-1-peter.maydell@linaro.org | ||
15 | --- | 20 | --- |
16 | target/arm/internals.h | 3 ++- | 21 | target/arm/m_helper.c | 3 ++- |
17 | target/arm/helper.c | 60 ++++++++++++++++++++--------------------- | 22 | 1 file changed, 2 insertions(+), 1 deletion(-) |
18 | target/arm/m_helper.c | 11 +++++--- | ||
19 | target/arm/tlb_helper.c | 4 ++- | ||
20 | 4 files changed, 42 insertions(+), 36 deletions(-) | ||
21 | 23 | ||
22 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/target/arm/internals.h | ||
25 | +++ b/target/arm/internals.h | ||
26 | @@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address, | ||
27 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | ||
28 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, | ||
29 | target_ulong *page_size, | ||
30 | - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); | ||
31 | + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) | ||
32 | + __attribute__((nonnull)); | ||
33 | |||
34 | void arm_log_exception(int idx); | ||
35 | |||
36 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/helper.c | ||
39 | +++ b/target/arm/helper.c | ||
40 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, | ||
41 | bool s1_is_el0, | ||
42 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, | ||
43 | target_ulong *page_size_ptr, | ||
44 | - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); | ||
45 | + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) | ||
46 | + __attribute__((nonnull)); | ||
47 | #endif | ||
48 | |||
49 | static void switch_mode(CPUARMState *env, int mode); | ||
50 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, | ||
51 | arm_tlb_bti_gp(txattrs) = true; | ||
52 | } | ||
53 | |||
54 | - if (cacheattrs != NULL) { | ||
55 | - if (mmu_idx == ARMMMUIdx_Stage2) { | ||
56 | - cacheattrs->attrs = convert_stage2_attrs(env, | ||
57 | - extract32(attrs, 0, 4)); | ||
58 | - } else { | ||
59 | - /* Index into MAIR registers for cache attributes */ | ||
60 | - uint8_t attrindx = extract32(attrs, 0, 3); | ||
61 | - uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; | ||
62 | - assert(attrindx <= 7); | ||
63 | - cacheattrs->attrs = extract64(mair, attrindx * 8, 8); | ||
64 | - } | ||
65 | - cacheattrs->shareability = extract32(attrs, 6, 2); | ||
66 | + if (mmu_idx == ARMMMUIdx_Stage2) { | ||
67 | + cacheattrs->attrs = convert_stage2_attrs(env, extract32(attrs, 0, 4)); | ||
68 | + } else { | ||
69 | + /* Index into MAIR registers for cache attributes */ | ||
70 | + uint8_t attrindx = extract32(attrs, 0, 3); | ||
71 | + uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; | ||
72 | + assert(attrindx <= 7); | ||
73 | + cacheattrs->attrs = extract64(mair, attrindx * 8, 8); | ||
74 | } | ||
75 | + cacheattrs->shareability = extract32(attrs, 6, 2); | ||
76 | |||
77 | *phys_ptr = descaddr; | ||
78 | *page_size_ptr = page_size; | ||
79 | @@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address, | ||
80 | ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_Stage2, | ||
81 | mmu_idx == ARMMMUIdx_E10_0, | ||
82 | phys_ptr, attrs, &s2_prot, | ||
83 | - page_size, fi, | ||
84 | - cacheattrs != NULL ? &cacheattrs2 : NULL); | ||
85 | + page_size, fi, &cacheattrs2); | ||
86 | fi->s2addr = ipa; | ||
87 | /* Combine the S1 and S2 perms. */ | ||
88 | *prot &= s2_prot; | ||
89 | |||
90 | - /* Combine the S1 and S2 cache attributes, if needed */ | ||
91 | - if (!ret && cacheattrs != NULL) { | ||
92 | - if (env->cp15.hcr_el2 & HCR_DC) { | ||
93 | - /* | ||
94 | - * HCR.DC forces the first stage attributes to | ||
95 | - * Normal Non-Shareable, | ||
96 | - * Inner Write-Back Read-Allocate Write-Allocate, | ||
97 | - * Outer Write-Back Read-Allocate Write-Allocate. | ||
98 | - */ | ||
99 | - cacheattrs->attrs = 0xff; | ||
100 | - cacheattrs->shareability = 0; | ||
101 | - } | ||
102 | - *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2); | ||
103 | + /* If S2 fails, return early. */ | ||
104 | + if (ret) { | ||
105 | + return ret; | ||
106 | } | ||
107 | |||
108 | - return ret; | ||
109 | + /* Combine the S1 and S2 cache attributes. */ | ||
110 | + if (env->cp15.hcr_el2 & HCR_DC) { | ||
111 | + /* | ||
112 | + * HCR.DC forces the first stage attributes to | ||
113 | + * Normal Non-Shareable, | ||
114 | + * Inner Write-Back Read-Allocate Write-Allocate, | ||
115 | + * Outer Write-Back Read-Allocate Write-Allocate. | ||
116 | + */ | ||
117 | + cacheattrs->attrs = 0xff; | ||
118 | + cacheattrs->shareability = 0; | ||
119 | + } | ||
120 | + *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2); | ||
121 | + return 0; | ||
122 | } else { | ||
123 | /* | ||
124 | * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. | ||
125 | @@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, | ||
126 | bool ret; | ||
127 | ARMMMUFaultInfo fi = {}; | ||
128 | ARMMMUIdx mmu_idx = arm_mmu_idx(env); | ||
129 | + ARMCacheAttrs cacheattrs = {}; | ||
130 | |||
131 | *attrs = (MemTxAttrs) {}; | ||
132 | |||
133 | ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr, | ||
134 | - attrs, &prot, &page_size, &fi, NULL); | ||
135 | + attrs, &prot, &page_size, &fi, &cacheattrs); | ||
136 | |||
137 | if (ret) { | ||
138 | return -1; | ||
139 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | 24 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c |
140 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
141 | --- a/target/arm/m_helper.c | 26 | --- a/target/arm/m_helper.c |
142 | +++ b/target/arm/m_helper.c | 27 | +++ b/target/arm/m_helper.c |
143 | @@ -XXX,XX +XXX,XX @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, | 28 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, |
144 | hwaddr physaddr; | 29 | /* Return the MMU index for a v7M CPU in the specified security state */ |
145 | int prot; | 30 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
146 | ARMMMUFaultInfo fi = {}; | 31 | { |
147 | + ARMCacheAttrs cacheattrs = {}; | 32 | - bool priv = arm_current_el(env) != 0; |
148 | bool secure = mmu_idx & ARM_MMU_IDX_M_S; | 33 | + bool priv = arm_v7m_is_handler_mode(env) || |
149 | int exc; | 34 | + !(env->v7m.control[secstate] & 1); |
150 | bool exc_secure; | 35 | |
151 | 36 | return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); | |
152 | if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &physaddr, | 37 | } |
153 | - &attrs, &prot, &page_size, &fi, NULL)) { | ||
154 | + &attrs, &prot, &page_size, &fi, &cacheattrs)) { | ||
155 | /* MPU/SAU lookup failed */ | ||
156 | if (fi.type == ARMFault_QEMU_SFault) { | ||
157 | if (mode == STACK_LAZYFP) { | ||
158 | @@ -XXX,XX +XXX,XX @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr, | ||
159 | hwaddr physaddr; | ||
160 | int prot; | ||
161 | ARMMMUFaultInfo fi = {}; | ||
162 | + ARMCacheAttrs cacheattrs = {}; | ||
163 | bool secure = mmu_idx & ARM_MMU_IDX_M_S; | ||
164 | int exc; | ||
165 | bool exc_secure; | ||
166 | uint32_t value; | ||
167 | |||
168 | if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr, | ||
169 | - &attrs, &prot, &page_size, &fi, NULL)) { | ||
170 | + &attrs, &prot, &page_size, &fi, &cacheattrs)) { | ||
171 | /* MPU/SAU lookup failed */ | ||
172 | if (fi.type == ARMFault_QEMU_SFault) { | ||
173 | qemu_log_mask(CPU_LOG_INT, | ||
174 | @@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, | ||
175 | V8M_SAttributes sattrs = {}; | ||
176 | MemTxAttrs attrs = {}; | ||
177 | ARMMMUFaultInfo fi = {}; | ||
178 | + ARMCacheAttrs cacheattrs = {}; | ||
179 | MemTxResult txres; | ||
180 | target_ulong page_size; | ||
181 | hwaddr physaddr; | ||
182 | @@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, | ||
183 | "...really SecureFault with SFSR.INVEP\n"); | ||
184 | return false; | ||
185 | } | ||
186 | - if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, | ||
187 | - &physaddr, &attrs, &prot, &page_size, &fi, NULL)) { | ||
188 | + if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &physaddr, | ||
189 | + &attrs, &prot, &page_size, &fi, &cacheattrs)) { | ||
190 | /* the MPU lookup failed */ | ||
191 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; | ||
192 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure); | ||
193 | diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c | ||
194 | index XXXXXXX..XXXXXXX 100644 | ||
195 | --- a/target/arm/tlb_helper.c | ||
196 | +++ b/target/arm/tlb_helper.c | ||
197 | @@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
198 | int prot, ret; | ||
199 | MemTxAttrs attrs = {}; | ||
200 | ARMMMUFaultInfo fi = {}; | ||
201 | + ARMCacheAttrs cacheattrs = {}; | ||
202 | |||
203 | /* | ||
204 | * Walk the page table and (if the mapping exists) add the page | ||
205 | @@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
206 | */ | ||
207 | ret = get_phys_addr(&cpu->env, address, access_type, | ||
208 | core_to_arm_mmu_idx(&cpu->env, mmu_idx), | ||
209 | - &phys_addr, &attrs, &prot, &page_size, &fi, NULL); | ||
210 | + &phys_addr, &attrs, &prot, &page_size, | ||
211 | + &fi, &cacheattrs); | ||
212 | if (likely(!ret)) { | ||
213 | /* | ||
214 | * Map a single [sub]page. Regions smaller than our declared | ||
215 | -- | 38 | -- |
216 | 2.20.1 | 39 | 2.20.1 |
217 | 40 | ||
218 | 41 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | On some hosts (eg Ubuntu Bionic) pkg-config returns a set of |
---|---|---|---|
2 | libraries for gio-2.0 which don't actually work when compiling | ||
3 | statically. (Specifically, the returned library string includes | ||
4 | -lmount, but not -lblkid which -lmount depends upon, so linking | ||
5 | fails due to missing symbols.) | ||
2 | 6 | ||
3 | There are a number of paths by which the TBI is still intact | 7 | Check that the libraries work, and don't enable gio if they don't, |
4 | for user-only in the SVE helpers. | 8 | in the same way we do for gnutls. |
5 | 9 | ||
6 | Because we currently always set TBI for user-only, we do not | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | need to pass down the actual TBI setting from above, and we | 11 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> |
8 | can remove the top byte in the inner-most primitives, so that | 12 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
9 | none are forgotten. Moreover, this keeps the "dirty" pointer | 13 | Message-id: 20200928160402.7961-1-peter.maydell@linaro.org |
10 | around at the higher levels, where we need it for any MTE checking. | 14 | --- |
15 | configure | 10 +++++++++- | ||
16 | 1 file changed, 9 insertions(+), 1 deletion(-) | ||
11 | 17 | ||
12 | Since the normal case, especially for user-only, goes through | 18 | diff --git a/configure b/configure |
13 | RAM, this clearing merely adds two insns per page lookup, which | 19 | index XXXXXXX..XXXXXXX 100755 |
14 | will be completely in the noise. | 20 | --- a/configure |
15 | 21 | +++ b/configure | |
16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 22 | @@ -XXX,XX +XXX,XX @@ if test "$static" = yes && test "$mingw32" = yes; then |
17 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 23 | fi |
18 | Message-id: 20200626033144.790098-39-richard.henderson@linaro.org | 24 | |
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 25 | if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then |
20 | --- | 26 | - gio=yes |
21 | target/arm/cpu.c | 3 +++ | 27 | gio_cflags=$($pkg_config --cflags gio-2.0) |
22 | target/arm/sve_helper.c | 19 +++++++++++++++++-- | 28 | gio_libs=$($pkg_config --libs gio-2.0) |
23 | target/arm/translate-a64.c | 5 +++++ | 29 | gdbus_codegen=$($pkg_config --variable=gdbus_codegen gio-2.0) |
24 | 3 files changed, 25 insertions(+), 2 deletions(-) | 30 | if [ ! -x "$gdbus_codegen" ]; then |
25 | 31 | gdbus_codegen= | |
26 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 32 | fi |
27 | index XXXXXXX..XXXXXXX 100644 | 33 | + # Check that the libraries actually work -- Ubuntu 18.04 ships |
28 | --- a/target/arm/cpu.c | 34 | + # with pkg-config --static --libs data for gio-2.0 that is missing |
29 | +++ b/target/arm/cpu.c | 35 | + # -lblkid and will give a link error. |
30 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) | 36 | + write_c_skeleton |
31 | * Enable TBI0 and TBI1. While the real kernel only enables TBI0, | 37 | + if compile_prog "" "gio_libs" ; then |
32 | * turning on both here will produce smaller code and otherwise | 38 | + gio=yes |
33 | * make no difference to the user-level emulation. | 39 | + else |
34 | + * | 40 | + gio=no |
35 | + * In sve_probe_page, we assume that this is set. | 41 | + fi |
36 | + * Do not modify this without other changes. | 42 | else |
37 | */ | 43 | gio=no |
38 | env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); | 44 | fi |
39 | #else | ||
40 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/target/arm/sve_helper.c | ||
43 | +++ b/target/arm/sve_helper.c | ||
44 | @@ -XXX,XX +XXX,XX @@ static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \ | ||
45 | static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \ | ||
46 | target_ulong addr, uintptr_t ra) \ | ||
47 | { \ | ||
48 | - *(TYPEE *)(vd + H(reg_off)) = (TYPEM)TLB(env, addr, ra); \ | ||
49 | + *(TYPEE *)(vd + H(reg_off)) = \ | ||
50 | + (TYPEM)TLB(env, useronly_clean_ptr(addr), ra); \ | ||
51 | } | ||
52 | |||
53 | #define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \ | ||
54 | static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \ | ||
55 | target_ulong addr, uintptr_t ra) \ | ||
56 | { \ | ||
57 | - TLB(env, addr, (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); \ | ||
58 | + TLB(env, useronly_clean_ptr(addr), \ | ||
59 | + (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); \ | ||
60 | } | ||
61 | |||
62 | #define DO_LD_PRIM_1(NAME, H, TE, TM) \ | ||
63 | @@ -XXX,XX +XXX,XX @@ static bool sve_probe_page(SVEHostPage *info, bool nofault, | ||
64 | int flags; | ||
65 | |||
66 | addr += mem_off; | ||
67 | + | ||
68 | + /* | ||
69 | + * User-only currently always issues with TBI. See the comment | ||
70 | + * above useronly_clean_ptr. Usually we clean this top byte away | ||
71 | + * during translation, but we can't do that for e.g. vector + imm | ||
72 | + * addressing modes. | ||
73 | + * | ||
74 | + * We currently always enable TBI for user-only, and do not provide | ||
75 | + * a way to turn it off. So clean the pointer unconditionally here, | ||
76 | + * rather than look it up here, or pass it down from above. | ||
77 | + */ | ||
78 | + addr = useronly_clean_ptr(addr); | ||
79 | + | ||
80 | flags = probe_access_flags(env, addr, access_type, mmu_idx, nofault, | ||
81 | &info->host, retaddr); | ||
82 | info->flags = flags; | ||
83 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
84 | index XXXXXXX..XXXXXXX 100644 | ||
85 | --- a/target/arm/translate-a64.c | ||
86 | +++ b/target/arm/translate-a64.c | ||
87 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, | ||
88 | dc->features = env->features; | ||
89 | dc->dcz_blocksize = arm_cpu->dcz_blocksize; | ||
90 | |||
91 | +#ifdef CONFIG_USER_ONLY | ||
92 | + /* In sve_probe_page, we assume TBI is enabled. */ | ||
93 | + tcg_debug_assert(dc->tbid & 1); | ||
94 | +#endif | ||
95 | + | ||
96 | /* Single step state. The code-generation logic here is: | ||
97 | * SS_ACTIVE == 0: | ||
98 | * generate code with no special handling for single-stepping (except | ||
99 | -- | 45 | -- |
100 | 2.20.1 | 46 | 2.20.1 |
101 | 47 | ||
102 | 48 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | In gicv3_init_cpuif() we copy the ARMCPU gicv3_maintenance_interrupt |
---|---|---|---|
2 | into the GICv3CPUState struct's maintenance_irq field. This will | ||
3 | only work if the board happens to have already wired up the CPU | ||
4 | maintenance IRQ before the GIC was realized. Unfortunately this is | ||
5 | not the case for the 'virt' board, and so the value that gets copied | ||
6 | is NULL (since a qemu_irq is really a pointer to an IRQState struct | ||
7 | under the hood). The effect is that the CPU interface code never | ||
8 | actually raises the maintenance interrupt line. | ||
2 | 9 | ||
3 | Introduce an lvalue macro to wrap target_tlb_bit0. | 10 | Instead, since the GICv3CPUState has a pointer to the CPUState, make |
11 | the dereference at the point where we want to raise the interrupt, to | ||
12 | avoid an implicit requirement on board code to wire things up in a | ||
13 | particular order. | ||
4 | 14 | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Reported-by: Jose Martins <josemartins90@gmail.com> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20200626033144.790098-33-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | Message-id: 20201009153904.28529-1-peter.maydell@linaro.org | ||
18 | Reviewed-by: Luc Michel <luc@lmichel.fr> | ||
9 | --- | 19 | --- |
10 | target/arm/cpu.h | 13 +++++++++++++ | 20 | include/hw/intc/arm_gicv3_common.h | 1 - |
11 | target/arm/helper.c | 2 +- | 21 | hw/intc/arm_gicv3_cpuif.c | 5 ++--- |
12 | target/arm/translate-a64.c | 2 +- | 22 | 2 files changed, 2 insertions(+), 4 deletions(-) |
13 | 3 files changed, 15 insertions(+), 2 deletions(-) | ||
14 | 23 | ||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 24 | diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h |
16 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu.h | 26 | --- a/include/hw/intc/arm_gicv3_common.h |
18 | +++ b/target/arm/cpu.h | 27 | +++ b/include/hw/intc/arm_gicv3_common.h |
19 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) | 28 | @@ -XXX,XX +XXX,XX @@ struct GICv3CPUState { |
20 | /* Shared between translate-sve.c and sve_helper.c. */ | 29 | qemu_irq parent_fiq; |
21 | extern const uint64_t pred_esz_masks[4]; | 30 | qemu_irq parent_virq; |
22 | 31 | qemu_irq parent_vfiq; | |
23 | +/* Helper for the macros below, validating the argument type. */ | 32 | - qemu_irq maintenance_irq; |
24 | +static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) | 33 | |
25 | +{ | 34 | /* Redistributor */ |
26 | + return x; | 35 | uint32_t level; /* Current IRQ level */ |
27 | +} | 36 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c |
28 | + | ||
29 | +/* | ||
30 | + * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. | ||
31 | + * Using these should be a bit more self-documenting than using the | ||
32 | + * generic target bits directly. | ||
33 | + */ | ||
34 | +#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) | ||
35 | + | ||
36 | /* | ||
37 | * Naming convention for isar_feature functions: | ||
38 | * Functions which test 32-bit ID registers should have _aa32_ in | ||
39 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
40 | index XXXXXXX..XXXXXXX 100644 | 37 | index XXXXXXX..XXXXXXX 100644 |
41 | --- a/target/arm/helper.c | 38 | --- a/hw/intc/arm_gicv3_cpuif.c |
42 | +++ b/target/arm/helper.c | 39 | +++ b/hw/intc/arm_gicv3_cpuif.c |
43 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, | 40 | @@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) |
44 | } | 41 | int irqlevel = 0; |
45 | /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */ | 42 | int fiqlevel = 0; |
46 | if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { | 43 | int maintlevel = 0; |
47 | - txattrs->target_tlb_bit0 = true; | 44 | + ARMCPU *cpu = ARM_CPU(cs->cpu); |
48 | + arm_tlb_bti_gp(txattrs) = true; | 45 | |
49 | } | 46 | idx = hppvi_index(cs); |
50 | 47 | trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx); | |
51 | if (cacheattrs != NULL) { | 48 | @@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) |
52 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 49 | |
53 | index XXXXXXX..XXXXXXX 100644 | 50 | qemu_set_irq(cs->parent_vfiq, fiqlevel); |
54 | --- a/target/arm/translate-a64.c | 51 | qemu_set_irq(cs->parent_virq, irqlevel); |
55 | +++ b/target/arm/translate-a64.c | 52 | - qemu_set_irq(cs->maintenance_irq, maintlevel); |
56 | @@ -XXX,XX +XXX,XX @@ static bool is_guarded_page(CPUARMState *env, DisasContext *s) | 53 | + qemu_set_irq(cpu->gicv3_maintenance_interrupt, maintlevel); |
57 | * table entry even for that case. | ||
58 | */ | ||
59 | return (tlb_hit(entry->addr_code, addr) && | ||
60 | - env_tlb(env)->d[mmu_idx].iotlb[index].attrs.target_tlb_bit0); | ||
61 | + arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].iotlb[index].attrs)); | ||
62 | #endif | ||
63 | } | 54 | } |
64 | 55 | ||
56 | static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
57 | @@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s) | ||
58 | && cpu->gic_num_lrs) { | ||
59 | int j; | ||
60 | |||
61 | - cs->maintenance_irq = cpu->gicv3_maintenance_interrupt; | ||
62 | - | ||
63 | cs->num_list_regs = cpu->gic_num_lrs; | ||
64 | cs->vpribits = cpu->gic_vpribits; | ||
65 | cs->vprebits = cpu->gic_vprebits; | ||
65 | -- | 66 | -- |
66 | 2.20.1 | 67 | 2.20.1 |
67 | 68 | ||
68 | 69 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | The kerneldoc script currently emits Sphinx markup for a macro with |
---|---|---|---|
2 | arguments that uses the c:function directive. This is correct for | ||
3 | Sphinx versions earlier than Sphinx 3, where c:macro doesn't allow | ||
4 | documentation of macros with arguments and c:function is not picky | ||
5 | about the syntax of what it is passed. However, in Sphinx 3 the | ||
6 | c:macro directive was enhanced to support macros with arguments, | ||
7 | and c:function was made more picky about what syntax it accepted. | ||
2 | 8 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | When kerneldoc is told that it needs to produce output for Sphinx |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | 3 or later, make it emit c:function only for functions and c:macro |
5 | Message-id: 20200626033144.790098-5-richard.henderson@linaro.org | 11 | for macros with arguments. We assume that anything with a return |
12 | type is a function and anything without is a macro. | ||
13 | |||
14 | This fixes the Sphinx error: | ||
15 | |||
16 | /home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/qom/object.h:155:Error in declarator | ||
17 | If declarator-id with parameters (e.g., 'void f(int arg)'): | ||
18 | Invalid C declaration: Expected identifier in nested name. [error at 25] | ||
19 | DECLARE_INSTANCE_CHECKER ( InstanceType, OBJ_NAME, TYPENAME) | ||
20 | -------------------------^ | ||
21 | If parenthesis in noptr-declarator (e.g., 'void (*f(int arg))(double)'): | ||
22 | Error in declarator or parameters | ||
23 | Invalid C declaration: Expecting "(" in parameters. [error at 39] | ||
24 | DECLARE_INSTANCE_CHECKER ( InstanceType, OBJ_NAME, TYPENAME) | ||
25 | ---------------------------------------^ | ||
26 | |||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
28 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> | ||
29 | Tested-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
30 | Message-id: 20201030174700.7204-2-peter.maydell@linaro.org | ||
7 | --- | 31 | --- |
8 | target/arm/helper.c | 14 +++++++++++--- | 32 | scripts/kernel-doc | 18 +++++++++++++++++- |
9 | 1 file changed, 11 insertions(+), 3 deletions(-) | 33 | 1 file changed, 17 insertions(+), 1 deletion(-) |
10 | 34 | ||
11 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 35 | diff --git a/scripts/kernel-doc b/scripts/kernel-doc |
12 | index XXXXXXX..XXXXXXX 100644 | 36 | index XXXXXXX..XXXXXXX 100755 |
13 | --- a/target/arm/helper.c | 37 | --- a/scripts/kernel-doc |
14 | +++ b/target/arm/helper.c | 38 | +++ b/scripts/kernel-doc |
15 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | 39 | @@ -XXX,XX +XXX,XX @@ sub output_function_rst(%) { |
16 | if (cpu_isar_feature(aa64_pauth, cpu)) { | 40 | output_highlight_rst($args{'purpose'}); |
17 | valid_mask |= SCR_API | SCR_APK; | 41 | $start = "\n\n**Syntax**\n\n ``"; |
18 | } | ||
19 | + if (cpu_isar_feature(aa64_mte, cpu)) { | ||
20 | + valid_mask |= SCR_ATA; | ||
21 | + } | ||
22 | } else { | 42 | } else { |
23 | valid_mask &= ~(SCR_RW | SCR_ST); | 43 | - print ".. c:function:: "; |
24 | } | 44 | + if ((split(/\./, $sphinx_version))[0] >= 3) { |
25 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | 45 | + # Sphinx 3 and later distinguish macros and functions and |
26 | if (cpu_isar_feature(aa64_pauth, cpu)) { | 46 | + # complain if you use c:function with something that's not |
27 | valid_mask |= HCR_API | HCR_APK; | 47 | + # syntactically valid as a function declaration. |
28 | } | 48 | + # We assume that anything with a return type is a function |
29 | + if (cpu_isar_feature(aa64_mte, cpu)) { | 49 | + # and anything without is a macro. |
30 | + valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5; | 50 | + if ($args{'functiontype'} ne "") { |
51 | + print ".. c:function:: "; | ||
52 | + } else { | ||
53 | + print ".. c:macro:: "; | ||
54 | + } | ||
55 | + } else { | ||
56 | + # Older Sphinx don't support documenting macros that take | ||
57 | + # arguments with c:macro, and don't complain about the use | ||
58 | + # of c:function for this. | ||
59 | + print ".. c:function:: "; | ||
31 | + } | 60 | + } |
32 | } | 61 | } |
33 | 62 | if ($args{'functiontype'} ne "") { | |
34 | /* Clear RES0 bits. */ | 63 | $start .= $args{'functiontype'} . " " . $args{'function'} . " ("; |
35 | value &= valid_mask; | ||
36 | |||
37 | - /* These bits change the MMU setup: | ||
38 | + /* | ||
39 | + * These bits change the MMU setup: | ||
40 | * HCR_VM enables stage 2 translation | ||
41 | * HCR_PTW forbids certain page-table setups | ||
42 | - * HCR_DC Disables stage1 and enables stage2 translation | ||
43 | + * HCR_DC disables stage1 and enables stage2 translation | ||
44 | + * HCR_DCT enables tagging on (disabled) stage1 translation | ||
45 | */ | ||
46 | - if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { | ||
47 | + if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT)) { | ||
48 | tlb_flush(CPU(cpu)); | ||
49 | } | ||
50 | env->cp15.hcr_el2 = value; | ||
51 | -- | 64 | -- |
52 | 2.20.1 | 65 | 2.20.1 |
53 | 66 | ||
54 | 67 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | Sphinx 3.2 is pickier than earlier versions about the option:: markup, |
---|---|---|---|
2 | and complains about our usage in qemu-option-trace.rst: | ||
2 | 3 | ||
3 | To have a more consistent naming, rename AspeedBoardState | 4 | ../../docs/qemu-option-trace.rst.inc:4:Malformed option description |
4 | as AspeedMachineState. | 5 | '[enable=]PATTERN', should look like "opt", "-opt args", "--opt args", |
6 | "/opt args" or "+opt args" | ||
5 | 7 | ||
6 | Suggested-by: Cédric Le Goater <clg@kaod.org> | 8 | In this file, we're really trying to document the different parts of |
7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 9 | the top-level --trace option, which qemu-nbd.rst and qemu-img.rst |
8 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 10 | have already introduced with an option:: markup. So it's not right |
9 | Message-id: 20200623072132.2868-3-f4bug@amsat.org | 11 | to use option:: here anyway. Switch to a different markup |
12 | (definition lists) which gives about the same formatted output. | ||
13 | |||
14 | (Unlike option::, this markup doesn't produce index entries; but | ||
15 | at the moment we don't do anything much with indexes anyway, and | ||
16 | in any case I think it doesn't make much sense to have individual | ||
17 | index entries for the sub-parts of the --trace option.) | ||
18 | |||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
20 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> | ||
21 | Tested-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
22 | Message-id: 20201030174700.7204-3-peter.maydell@linaro.org | ||
11 | --- | 23 | --- |
12 | include/hw/arm/aspeed.h | 4 ++-- | 24 | docs/qemu-option-trace.rst.inc | 6 +++--- |
13 | hw/arm/aspeed.c | 20 ++++++++++---------- | 25 | 1 file changed, 3 insertions(+), 3 deletions(-) |
14 | 2 files changed, 12 insertions(+), 12 deletions(-) | ||
15 | 26 | ||
16 | diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h | 27 | diff --git a/docs/qemu-option-trace.rst.inc b/docs/qemu-option-trace.rst.inc |
17 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/aspeed.h | 29 | --- a/docs/qemu-option-trace.rst.inc |
19 | +++ b/include/hw/arm/aspeed.h | 30 | +++ b/docs/qemu-option-trace.rst.inc |
20 | @@ -XXX,XX +XXX,XX @@ | 31 | @@ -XXX,XX +XXX,XX @@ |
21 | 32 | ||
22 | #include "hw/boards.h" | 33 | Specify tracing options. |
23 | 34 | ||
24 | -typedef struct AspeedBoardState AspeedBoardState; | 35 | -.. option:: [enable=]PATTERN |
25 | +typedef struct AspeedMachineState AspeedMachineState; | 36 | +``[enable=]PATTERN`` |
26 | 37 | ||
27 | #define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed") | 38 | Immediately enable events matching *PATTERN* |
28 | #define ASPEED_MACHINE(obj) \ | 39 | (either event name or a globbing pattern). This option is only |
29 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedMachineClass { | 40 | @@ -XXX,XX +XXX,XX @@ Specify tracing options. |
30 | const char *spi_model; | 41 | |
31 | uint32_t num_cs; | 42 | Use :option:`-trace help` to print a list of names of trace points. |
32 | uint32_t macs_mask; | 43 | |
33 | - void (*i2c_init)(AspeedBoardState *bmc); | 44 | -.. option:: events=FILE |
34 | + void (*i2c_init)(AspeedMachineState *bmc); | 45 | +``events=FILE`` |
35 | } AspeedMachineClass; | 46 | |
36 | 47 | Immediately enable events listed in *FILE*. | |
37 | 48 | The file must contain one event name (as listed in the ``trace-events-all`` | |
38 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | 49 | @@ -XXX,XX +XXX,XX @@ Specify tracing options. |
39 | index XXXXXXX..XXXXXXX 100644 | 50 | available if QEMU has been compiled with the ``simple``, ``log`` or |
40 | --- a/hw/arm/aspeed.c | 51 | ``ftrace`` tracing backend. |
41 | +++ b/hw/arm/aspeed.c | 52 | |
42 | @@ -XXX,XX +XXX,XX @@ static struct arm_boot_info aspeed_board_binfo = { | 53 | -.. option:: file=FILE |
43 | .board_id = -1, /* device-tree-only board */ | 54 | +``file=FILE`` |
44 | }; | 55 | |
45 | 56 | Log output traces to *FILE*. | |
46 | -struct AspeedBoardState { | 57 | This option is only available if QEMU has been compiled with |
47 | +struct AspeedMachineState { | ||
48 | AspeedSoCState soc; | ||
49 | MemoryRegion ram_container; | ||
50 | MemoryRegion max_ram; | ||
51 | @@ -XXX,XX +XXX,XX @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) | ||
52 | |||
53 | static void aspeed_machine_init(MachineState *machine) | ||
54 | { | ||
55 | - AspeedBoardState *bmc; | ||
56 | + AspeedMachineState *bmc; | ||
57 | AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); | ||
58 | AspeedSoCClass *sc; | ||
59 | DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); | ||
60 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine) | ||
61 | int i; | ||
62 | NICInfo *nd = &nd_table[0]; | ||
63 | |||
64 | - bmc = g_new0(AspeedBoardState, 1); | ||
65 | + bmc = g_new0(AspeedMachineState, 1); | ||
66 | |||
67 | memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", | ||
68 | 4 * GiB); | ||
69 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine) | ||
70 | arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); | ||
71 | } | ||
72 | |||
73 | -static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) | ||
74 | +static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) | ||
75 | { | ||
76 | AspeedSoCState *soc = &bmc->soc; | ||
77 | DeviceState *dev; | ||
78 | @@ -XXX,XX +XXX,XX @@ static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) | ||
79 | object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort); | ||
80 | } | ||
81 | |||
82 | -static void ast2500_evb_i2c_init(AspeedBoardState *bmc) | ||
83 | +static void ast2500_evb_i2c_init(AspeedMachineState *bmc) | ||
84 | { | ||
85 | AspeedSoCState *soc = &bmc->soc; | ||
86 | uint8_t *eeprom_buf = g_malloc0(8 * 1024); | ||
87 | @@ -XXX,XX +XXX,XX @@ static void ast2500_evb_i2c_init(AspeedBoardState *bmc) | ||
88 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); | ||
89 | } | ||
90 | |||
91 | -static void ast2600_evb_i2c_init(AspeedBoardState *bmc) | ||
92 | +static void ast2600_evb_i2c_init(AspeedMachineState *bmc) | ||
93 | { | ||
94 | /* Start with some devices on our I2C busses */ | ||
95 | ast2500_evb_i2c_init(bmc); | ||
96 | } | ||
97 | |||
98 | -static void romulus_bmc_i2c_init(AspeedBoardState *bmc) | ||
99 | +static void romulus_bmc_i2c_init(AspeedMachineState *bmc) | ||
100 | { | ||
101 | AspeedSoCState *soc = &bmc->soc; | ||
102 | |||
103 | @@ -XXX,XX +XXX,XX @@ static void romulus_bmc_i2c_init(AspeedBoardState *bmc) | ||
104 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); | ||
105 | } | ||
106 | |||
107 | -static void swift_bmc_i2c_init(AspeedBoardState *bmc) | ||
108 | +static void swift_bmc_i2c_init(AspeedMachineState *bmc) | ||
109 | { | ||
110 | AspeedSoCState *soc = &bmc->soc; | ||
111 | |||
112 | @@ -XXX,XX +XXX,XX @@ static void swift_bmc_i2c_init(AspeedBoardState *bmc) | ||
113 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x4a); | ||
114 | } | ||
115 | |||
116 | -static void sonorapass_bmc_i2c_init(AspeedBoardState *bmc) | ||
117 | +static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) | ||
118 | { | ||
119 | AspeedSoCState *soc = &bmc->soc; | ||
120 | |||
121 | @@ -XXX,XX +XXX,XX @@ static void sonorapass_bmc_i2c_init(AspeedBoardState *bmc) | ||
122 | |||
123 | } | ||
124 | |||
125 | -static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) | ||
126 | +static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) | ||
127 | { | ||
128 | AspeedSoCState *soc = &bmc->soc; | ||
129 | uint8_t *eeprom_buf = g_malloc0(8 * 1024); | ||
130 | -- | 58 | -- |
131 | 2.20.1 | 59 | 2.20.1 |
132 | 60 | ||
133 | 61 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | AspeedMachineState seems crippled. We use incorrectly 2 | ||
4 | different structures to do the same thing. Merge them | ||
5 | altogether: | ||
6 | - Move AspeedMachine fields to AspeedMachineState | ||
7 | - AspeedMachineState is now QOM | ||
8 | - Remove unused AspeedMachine structure | ||
9 | |||
10 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
12 | Message-id: 20200623072132.2868-4-f4bug@amsat.org | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | include/hw/arm/aspeed.h | 8 +------- | ||
16 | hw/arm/aspeed.c | 11 +++++++---- | ||
17 | 2 files changed, 8 insertions(+), 11 deletions(-) | ||
18 | |||
19 | diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/include/hw/arm/aspeed.h | ||
22 | +++ b/include/hw/arm/aspeed.h | ||
23 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedMachineState AspeedMachineState; | ||
24 | |||
25 | #define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed") | ||
26 | #define ASPEED_MACHINE(obj) \ | ||
27 | - OBJECT_CHECK(AspeedMachine, (obj), TYPE_ASPEED_MACHINE) | ||
28 | - | ||
29 | -typedef struct AspeedMachine { | ||
30 | - MachineState parent_obj; | ||
31 | - | ||
32 | - bool mmio_exec; | ||
33 | -} AspeedMachine; | ||
34 | + OBJECT_CHECK(AspeedMachineState, (obj), TYPE_ASPEED_MACHINE) | ||
35 | |||
36 | #define ASPEED_MAC0_ON (1 << 0) | ||
37 | #define ASPEED_MAC1_ON (1 << 1) | ||
38 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/hw/arm/aspeed.c | ||
41 | +++ b/hw/arm/aspeed.c | ||
42 | @@ -XXX,XX +XXX,XX @@ static struct arm_boot_info aspeed_board_binfo = { | ||
43 | }; | ||
44 | |||
45 | struct AspeedMachineState { | ||
46 | + /* Private */ | ||
47 | + MachineState parent_obj; | ||
48 | + /* Public */ | ||
49 | + | ||
50 | AspeedSoCState soc; | ||
51 | MemoryRegion ram_container; | ||
52 | MemoryRegion max_ram; | ||
53 | + bool mmio_exec; | ||
54 | }; | ||
55 | |||
56 | /* Palmetto hardware value: 0x120CE416 */ | ||
57 | @@ -XXX,XX +XXX,XX @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) | ||
58 | |||
59 | static void aspeed_machine_init(MachineState *machine) | ||
60 | { | ||
61 | - AspeedMachineState *bmc; | ||
62 | + AspeedMachineState *bmc = ASPEED_MACHINE(machine); | ||
63 | AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); | ||
64 | AspeedSoCClass *sc; | ||
65 | DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); | ||
66 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine) | ||
67 | int i; | ||
68 | NICInfo *nd = &nd_table[0]; | ||
69 | |||
70 | - bmc = g_new0(AspeedMachineState, 1); | ||
71 | - | ||
72 | memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", | ||
73 | 4 * GiB); | ||
74 | memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); | ||
75 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = { | ||
76 | }, { | ||
77 | .name = TYPE_ASPEED_MACHINE, | ||
78 | .parent = TYPE_MACHINE, | ||
79 | - .instance_size = sizeof(AspeedMachine), | ||
80 | + .instance_size = sizeof(AspeedMachineState), | ||
81 | .instance_init = aspeed_machine_instance_init, | ||
82 | .class_size = sizeof(AspeedMachineClass), | ||
83 | .class_init = aspeed_machine_class_init, | ||
84 | -- | ||
85 | 2.20.1 | ||
86 | |||
87 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Extract i2c_try_create_slave() and i2c_realize_and_unref() | ||
4 | from i2c_create_slave(). | ||
5 | We can now set properties on a I2CSlave before it is realized. | ||
6 | |||
7 | This is in line with the recent qdev/QOM changes merged | ||
8 | in commit 6675a653d2e. | ||
9 | |||
10 | Reviewed-by: Corey Minyard <cminyard@mvista.com> | ||
11 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
12 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
13 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | ||
14 | Tested-by: Cédric Le Goater <clg@kaod.org> | ||
15 | Message-id: 20200623072723.6324-2-f4bug@amsat.org | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | --- | ||
18 | include/hw/i2c/i2c.h | 2 ++ | ||
19 | hw/i2c/core.c | 18 ++++++++++++++++-- | ||
20 | 2 files changed, 18 insertions(+), 2 deletions(-) | ||
21 | |||
22 | diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/include/hw/i2c/i2c.h | ||
25 | +++ b/include/hw/i2c/i2c.h | ||
26 | @@ -XXX,XX +XXX,XX @@ int i2c_send(I2CBus *bus, uint8_t data); | ||
27 | uint8_t i2c_recv(I2CBus *bus); | ||
28 | |||
29 | DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr); | ||
30 | +DeviceState *i2c_try_create_slave(const char *name, uint8_t addr); | ||
31 | +bool i2c_realize_and_unref(DeviceState *dev, I2CBus *bus, Error **errp); | ||
32 | |||
33 | /* lm832x.c */ | ||
34 | void lm832x_key_event(DeviceState *dev, int key, int state); | ||
35 | diff --git a/hw/i2c/core.c b/hw/i2c/core.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/hw/i2c/core.c | ||
38 | +++ b/hw/i2c/core.c | ||
39 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_i2c_slave = { | ||
40 | } | ||
41 | }; | ||
42 | |||
43 | -DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr) | ||
44 | +DeviceState *i2c_try_create_slave(const char *name, uint8_t addr) | ||
45 | { | ||
46 | DeviceState *dev; | ||
47 | |||
48 | dev = qdev_new(name); | ||
49 | qdev_prop_set_uint8(dev, "address", addr); | ||
50 | - qdev_realize_and_unref(dev, &bus->qbus, &error_fatal); | ||
51 | + return dev; | ||
52 | +} | ||
53 | + | ||
54 | +bool i2c_realize_and_unref(DeviceState *dev, I2CBus *bus, Error **errp) | ||
55 | +{ | ||
56 | + return qdev_realize_and_unref(dev, &bus->qbus, errp); | ||
57 | +} | ||
58 | + | ||
59 | +DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr) | ||
60 | +{ | ||
61 | + DeviceState *dev; | ||
62 | + | ||
63 | + dev = i2c_try_create_slave(name, addr); | ||
64 | + i2c_realize_and_unref(dev, bus, &error_fatal); | ||
65 | + | ||
66 | return dev; | ||
67 | } | ||
68 | |||
69 | -- | ||
70 | 2.20.1 | ||
71 | |||
72 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | The PCA9552 device does not expose LEDs, but simple pins | ||
4 | to connnect LEDs to. To be clearer with the device model, | ||
5 | rename 'nr_leds' as 'pin_count'. | ||
6 | |||
7 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
8 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Tested-by: Cédric Le Goater <clg@kaod.org> | ||
10 | Message-id: 20200623072723.6324-3-f4bug@amsat.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | include/hw/misc/pca9552.h | 2 +- | ||
14 | hw/misc/pca9552.c | 10 +++++----- | ||
15 | 2 files changed, 6 insertions(+), 6 deletions(-) | ||
16 | |||
17 | diff --git a/include/hw/misc/pca9552.h b/include/hw/misc/pca9552.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/hw/misc/pca9552.h | ||
20 | +++ b/include/hw/misc/pca9552.h | ||
21 | @@ -XXX,XX +XXX,XX @@ typedef struct PCA9552State { | ||
22 | |||
23 | uint8_t regs[PCA9552_NR_REGS]; | ||
24 | uint8_t max_reg; | ||
25 | - uint8_t nr_leds; | ||
26 | + uint8_t pin_count; | ||
27 | } PCA9552State; | ||
28 | |||
29 | #endif | ||
30 | diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/hw/misc/pca9552.c | ||
33 | +++ b/hw/misc/pca9552.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static void pca9552_update_pin_input(PCA9552State *s) | ||
35 | { | ||
36 | int i; | ||
37 | |||
38 | - for (i = 0; i < s->nr_leds; i++) { | ||
39 | + for (i = 0; i < s->pin_count; i++) { | ||
40 | uint8_t input_reg = PCA9552_INPUT0 + (i / 8); | ||
41 | uint8_t input_shift = (i % 8); | ||
42 | uint8_t config = pca9552_pin_get_config(s, i); | ||
43 | @@ -XXX,XX +XXX,XX @@ static void pca9552_get_led(Object *obj, Visitor *v, const char *name, | ||
44 | error_setg(errp, "%s: error reading %s", __func__, name); | ||
45 | return; | ||
46 | } | ||
47 | - if (led < 0 || led > s->nr_leds) { | ||
48 | + if (led < 0 || led > s->pin_count) { | ||
49 | error_setg(errp, "%s invalid led %s", __func__, name); | ||
50 | return; | ||
51 | } | ||
52 | @@ -XXX,XX +XXX,XX @@ static void pca9552_set_led(Object *obj, Visitor *v, const char *name, | ||
53 | error_setg(errp, "%s: error reading %s", __func__, name); | ||
54 | return; | ||
55 | } | ||
56 | - if (led < 0 || led > s->nr_leds) { | ||
57 | + if (led < 0 || led > s->pin_count) { | ||
58 | error_setg(errp, "%s invalid led %s", __func__, name); | ||
59 | return; | ||
60 | } | ||
61 | @@ -XXX,XX +XXX,XX @@ static void pca9552_initfn(Object *obj) | ||
62 | * PCA955X device | ||
63 | */ | ||
64 | s->max_reg = PCA9552_LS3; | ||
65 | - s->nr_leds = 16; | ||
66 | + s->pin_count = 16; | ||
67 | |||
68 | - for (led = 0; led < s->nr_leds; led++) { | ||
69 | + for (led = 0; led < s->pin_count; led++) { | ||
70 | char *name; | ||
71 | |||
72 | name = g_strdup_printf("led%d", led); | ||
73 | -- | ||
74 | 2.20.1 | ||
75 | |||
76 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Various code from the PCA9552 device model is generic to the | ||
4 | PCA955X family. We'll split the generic code in a base class | ||
5 | in the next commit. To ease review, first do a dumb renaming. | ||
6 | |||
7 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
8 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Tested-by: Cédric Le Goater <clg@kaod.org> | ||
10 | Message-id: 20200623072723.6324-4-f4bug@amsat.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | include/hw/misc/pca9552.h | 10 ++--- | ||
14 | hw/misc/pca9552.c | 80 +++++++++++++++++++-------------------- | ||
15 | 2 files changed, 45 insertions(+), 45 deletions(-) | ||
16 | |||
17 | diff --git a/include/hw/misc/pca9552.h b/include/hw/misc/pca9552.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/hw/misc/pca9552.h | ||
20 | +++ b/include/hw/misc/pca9552.h | ||
21 | @@ -XXX,XX +XXX,XX @@ | ||
22 | #include "hw/i2c/i2c.h" | ||
23 | |||
24 | #define TYPE_PCA9552 "pca9552" | ||
25 | -#define PCA9552(obj) OBJECT_CHECK(PCA9552State, (obj), TYPE_PCA9552) | ||
26 | +#define PCA955X(obj) OBJECT_CHECK(PCA955xState, (obj), TYPE_PCA9552) | ||
27 | |||
28 | -#define PCA9552_NR_REGS 10 | ||
29 | +#define PCA955X_NR_REGS 10 | ||
30 | |||
31 | -typedef struct PCA9552State { | ||
32 | +typedef struct PCA955xState { | ||
33 | /*< private >*/ | ||
34 | I2CSlave i2c; | ||
35 | /*< public >*/ | ||
36 | @@ -XXX,XX +XXX,XX @@ typedef struct PCA9552State { | ||
37 | uint8_t len; | ||
38 | uint8_t pointer; | ||
39 | |||
40 | - uint8_t regs[PCA9552_NR_REGS]; | ||
41 | + uint8_t regs[PCA955X_NR_REGS]; | ||
42 | uint8_t max_reg; | ||
43 | uint8_t pin_count; | ||
44 | -} PCA9552State; | ||
45 | +} PCA955xState; | ||
46 | |||
47 | #endif | ||
48 | diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/hw/misc/pca9552.c | ||
51 | +++ b/hw/misc/pca9552.c | ||
52 | @@ -XXX,XX +XXX,XX @@ | ||
53 | |||
54 | static const char *led_state[] = {"on", "off", "pwm0", "pwm1"}; | ||
55 | |||
56 | -static uint8_t pca9552_pin_get_config(PCA9552State *s, int pin) | ||
57 | +static uint8_t pca955x_pin_get_config(PCA955xState *s, int pin) | ||
58 | { | ||
59 | uint8_t reg = PCA9552_LS0 + (pin / 4); | ||
60 | uint8_t shift = (pin % 4) << 1; | ||
61 | @@ -XXX,XX +XXX,XX @@ static uint8_t pca9552_pin_get_config(PCA9552State *s, int pin) | ||
62 | return extract32(s->regs[reg], shift, 2); | ||
63 | } | ||
64 | |||
65 | -static void pca9552_update_pin_input(PCA9552State *s) | ||
66 | +static void pca955x_update_pin_input(PCA955xState *s) | ||
67 | { | ||
68 | int i; | ||
69 | |||
70 | for (i = 0; i < s->pin_count; i++) { | ||
71 | uint8_t input_reg = PCA9552_INPUT0 + (i / 8); | ||
72 | uint8_t input_shift = (i % 8); | ||
73 | - uint8_t config = pca9552_pin_get_config(s, i); | ||
74 | + uint8_t config = pca955x_pin_get_config(s, i); | ||
75 | |||
76 | switch (config) { | ||
77 | case PCA9552_LED_ON: | ||
78 | @@ -XXX,XX +XXX,XX @@ static void pca9552_update_pin_input(PCA9552State *s) | ||
79 | } | ||
80 | } | ||
81 | |||
82 | -static uint8_t pca9552_read(PCA9552State *s, uint8_t reg) | ||
83 | +static uint8_t pca955x_read(PCA955xState *s, uint8_t reg) | ||
84 | { | ||
85 | switch (reg) { | ||
86 | case PCA9552_INPUT0: | ||
87 | @@ -XXX,XX +XXX,XX @@ static uint8_t pca9552_read(PCA9552State *s, uint8_t reg) | ||
88 | } | ||
89 | } | ||
90 | |||
91 | -static void pca9552_write(PCA9552State *s, uint8_t reg, uint8_t data) | ||
92 | +static void pca955x_write(PCA955xState *s, uint8_t reg, uint8_t data) | ||
93 | { | ||
94 | switch (reg) { | ||
95 | case PCA9552_PSC0: | ||
96 | @@ -XXX,XX +XXX,XX @@ static void pca9552_write(PCA9552State *s, uint8_t reg, uint8_t data) | ||
97 | case PCA9552_LS2: | ||
98 | case PCA9552_LS3: | ||
99 | s->regs[reg] = data; | ||
100 | - pca9552_update_pin_input(s); | ||
101 | + pca955x_update_pin_input(s); | ||
102 | break; | ||
103 | |||
104 | case PCA9552_INPUT0: | ||
105 | @@ -XXX,XX +XXX,XX @@ static void pca9552_write(PCA9552State *s, uint8_t reg, uint8_t data) | ||
106 | * after each byte is sent to or received by the device. The index | ||
107 | * rollovers to 0 when the maximum register address is reached. | ||
108 | */ | ||
109 | -static void pca9552_autoinc(PCA9552State *s) | ||
110 | +static void pca955x_autoinc(PCA955xState *s) | ||
111 | { | ||
112 | if (s->pointer != 0xFF && s->pointer & PCA9552_AUTOINC) { | ||
113 | uint8_t reg = s->pointer & 0xf; | ||
114 | @@ -XXX,XX +XXX,XX @@ static void pca9552_autoinc(PCA9552State *s) | ||
115 | } | ||
116 | } | ||
117 | |||
118 | -static uint8_t pca9552_recv(I2CSlave *i2c) | ||
119 | +static uint8_t pca955x_recv(I2CSlave *i2c) | ||
120 | { | ||
121 | - PCA9552State *s = PCA9552(i2c); | ||
122 | + PCA955xState *s = PCA955X(i2c); | ||
123 | uint8_t ret; | ||
124 | |||
125 | - ret = pca9552_read(s, s->pointer & 0xf); | ||
126 | + ret = pca955x_read(s, s->pointer & 0xf); | ||
127 | |||
128 | /* | ||
129 | * From the Specs: | ||
130 | @@ -XXX,XX +XXX,XX @@ static uint8_t pca9552_recv(I2CSlave *i2c) | ||
131 | __func__); | ||
132 | } | ||
133 | |||
134 | - pca9552_autoinc(s); | ||
135 | + pca955x_autoinc(s); | ||
136 | |||
137 | return ret; | ||
138 | } | ||
139 | |||
140 | -static int pca9552_send(I2CSlave *i2c, uint8_t data) | ||
141 | +static int pca955x_send(I2CSlave *i2c, uint8_t data) | ||
142 | { | ||
143 | - PCA9552State *s = PCA9552(i2c); | ||
144 | + PCA955xState *s = PCA955X(i2c); | ||
145 | |||
146 | /* First byte sent by is the register address */ | ||
147 | if (s->len == 0) { | ||
148 | s->pointer = data; | ||
149 | s->len++; | ||
150 | } else { | ||
151 | - pca9552_write(s, s->pointer & 0xf, data); | ||
152 | + pca955x_write(s, s->pointer & 0xf, data); | ||
153 | |||
154 | - pca9552_autoinc(s); | ||
155 | + pca955x_autoinc(s); | ||
156 | } | ||
157 | |||
158 | return 0; | ||
159 | } | ||
160 | |||
161 | -static int pca9552_event(I2CSlave *i2c, enum i2c_event event) | ||
162 | +static int pca955x_event(I2CSlave *i2c, enum i2c_event event) | ||
163 | { | ||
164 | - PCA9552State *s = PCA9552(i2c); | ||
165 | + PCA955xState *s = PCA955X(i2c); | ||
166 | |||
167 | s->len = 0; | ||
168 | return 0; | ||
169 | } | ||
170 | |||
171 | -static void pca9552_get_led(Object *obj, Visitor *v, const char *name, | ||
172 | +static void pca955x_get_led(Object *obj, Visitor *v, const char *name, | ||
173 | void *opaque, Error **errp) | ||
174 | { | ||
175 | - PCA9552State *s = PCA9552(obj); | ||
176 | + PCA955xState *s = PCA955X(obj); | ||
177 | int led, rc, reg; | ||
178 | uint8_t state; | ||
179 | |||
180 | @@ -XXX,XX +XXX,XX @@ static void pca9552_get_led(Object *obj, Visitor *v, const char *name, | ||
181 | * reading the INPUTx reg | ||
182 | */ | ||
183 | reg = PCA9552_LS0 + led / 4; | ||
184 | - state = (pca9552_read(s, reg) >> (led % 8)) & 0x3; | ||
185 | + state = (pca955x_read(s, reg) >> (led % 8)) & 0x3; | ||
186 | visit_type_str(v, name, (char **)&led_state[state], errp); | ||
187 | } | ||
188 | |||
189 | @@ -XXX,XX +XXX,XX @@ static inline uint8_t pca955x_ledsel(uint8_t oldval, int led_num, int state) | ||
190 | ((state & 0x3) << (led_num << 1)); | ||
191 | } | ||
192 | |||
193 | -static void pca9552_set_led(Object *obj, Visitor *v, const char *name, | ||
194 | +static void pca955x_set_led(Object *obj, Visitor *v, const char *name, | ||
195 | void *opaque, Error **errp) | ||
196 | { | ||
197 | - PCA9552State *s = PCA9552(obj); | ||
198 | + PCA955xState *s = PCA955X(obj); | ||
199 | Error *local_err = NULL; | ||
200 | int led, rc, reg, val; | ||
201 | uint8_t state; | ||
202 | @@ -XXX,XX +XXX,XX @@ static void pca9552_set_led(Object *obj, Visitor *v, const char *name, | ||
203 | } | ||
204 | |||
205 | reg = PCA9552_LS0 + led / 4; | ||
206 | - val = pca9552_read(s, reg); | ||
207 | + val = pca955x_read(s, reg); | ||
208 | val = pca955x_ledsel(val, led % 4, state); | ||
209 | - pca9552_write(s, reg, val); | ||
210 | + pca955x_write(s, reg, val); | ||
211 | } | ||
212 | |||
213 | static const VMStateDescription pca9552_vmstate = { | ||
214 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription pca9552_vmstate = { | ||
215 | .version_id = 0, | ||
216 | .minimum_version_id = 0, | ||
217 | .fields = (VMStateField[]) { | ||
218 | - VMSTATE_UINT8(len, PCA9552State), | ||
219 | - VMSTATE_UINT8(pointer, PCA9552State), | ||
220 | - VMSTATE_UINT8_ARRAY(regs, PCA9552State, PCA9552_NR_REGS), | ||
221 | - VMSTATE_I2C_SLAVE(i2c, PCA9552State), | ||
222 | + VMSTATE_UINT8(len, PCA955xState), | ||
223 | + VMSTATE_UINT8(pointer, PCA955xState), | ||
224 | + VMSTATE_UINT8_ARRAY(regs, PCA955xState, PCA955X_NR_REGS), | ||
225 | + VMSTATE_I2C_SLAVE(i2c, PCA955xState), | ||
226 | VMSTATE_END_OF_LIST() | ||
227 | } | ||
228 | }; | ||
229 | |||
230 | static void pca9552_reset(DeviceState *dev) | ||
231 | { | ||
232 | - PCA9552State *s = PCA9552(dev); | ||
233 | + PCA955xState *s = PCA955X(dev); | ||
234 | |||
235 | s->regs[PCA9552_PSC0] = 0xFF; | ||
236 | s->regs[PCA9552_PWM0] = 0x80; | ||
237 | @@ -XXX,XX +XXX,XX @@ static void pca9552_reset(DeviceState *dev) | ||
238 | s->regs[PCA9552_LS2] = 0x55; | ||
239 | s->regs[PCA9552_LS3] = 0x55; | ||
240 | |||
241 | - pca9552_update_pin_input(s); | ||
242 | + pca955x_update_pin_input(s); | ||
243 | |||
244 | s->pointer = 0xFF; | ||
245 | s->len = 0; | ||
246 | } | ||
247 | |||
248 | -static void pca9552_initfn(Object *obj) | ||
249 | +static void pca955x_initfn(Object *obj) | ||
250 | { | ||
251 | - PCA9552State *s = PCA9552(obj); | ||
252 | + PCA955xState *s = PCA955X(obj); | ||
253 | int led; | ||
254 | |||
255 | /* If support for the other PCA955X devices are implemented, these | ||
256 | @@ -XXX,XX +XXX,XX @@ static void pca9552_initfn(Object *obj) | ||
257 | char *name; | ||
258 | |||
259 | name = g_strdup_printf("led%d", led); | ||
260 | - object_property_add(obj, name, "bool", pca9552_get_led, pca9552_set_led, | ||
261 | + object_property_add(obj, name, "bool", pca955x_get_led, pca955x_set_led, | ||
262 | NULL, NULL); | ||
263 | g_free(name); | ||
264 | } | ||
265 | @@ -XXX,XX +XXX,XX @@ static void pca9552_class_init(ObjectClass *klass, void *data) | ||
266 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
267 | I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); | ||
268 | |||
269 | - k->event = pca9552_event; | ||
270 | - k->recv = pca9552_recv; | ||
271 | - k->send = pca9552_send; | ||
272 | + k->event = pca955x_event; | ||
273 | + k->recv = pca955x_recv; | ||
274 | + k->send = pca955x_send; | ||
275 | dc->reset = pca9552_reset; | ||
276 | dc->vmsd = &pca9552_vmstate; | ||
277 | } | ||
278 | @@ -XXX,XX +XXX,XX @@ static void pca9552_class_init(ObjectClass *klass, void *data) | ||
279 | static const TypeInfo pca9552_info = { | ||
280 | .name = TYPE_PCA9552, | ||
281 | .parent = TYPE_I2C_SLAVE, | ||
282 | - .instance_init = pca9552_initfn, | ||
283 | - .instance_size = sizeof(PCA9552State), | ||
284 | + .instance_init = pca955x_initfn, | ||
285 | + .instance_size = sizeof(PCA955xState), | ||
286 | .class_init = pca9552_class_init, | ||
287 | }; | ||
288 | |||
289 | -static void pca9552_register_types(void) | ||
290 | +static void pca955x_register_types(void) | ||
291 | { | ||
292 | type_register_static(&pca9552_info); | ||
293 | } | ||
294 | |||
295 | -type_init(pca9552_register_types) | ||
296 | +type_init(pca955x_register_types) | ||
297 | -- | ||
298 | 2.20.1 | ||
299 | |||
300 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Extract the code common to the PCA955x family in PCA955xClass, | ||
4 | keeping the PCA9552 specific parts into pca9552_class_init(). | ||
5 | Remove the 'TODO' comment added in commit 5141d4158cf. | ||
6 | |||
7 | Suggested-by: Cédric Le Goater <clg@kaod.org> | ||
8 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
9 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
10 | Tested-by: Cédric Le Goater <clg@kaod.org> | ||
11 | Message-id: 20200623072723.6324-5-f4bug@amsat.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | include/hw/misc/pca9552.h | 6 ++-- | ||
15 | hw/misc/pca9552.c | 66 ++++++++++++++++++++++++++++----------- | ||
16 | 2 files changed, 51 insertions(+), 21 deletions(-) | ||
17 | |||
18 | diff --git a/include/hw/misc/pca9552.h b/include/hw/misc/pca9552.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/misc/pca9552.h | ||
21 | +++ b/include/hw/misc/pca9552.h | ||
22 | @@ -XXX,XX +XXX,XX @@ | ||
23 | #include "hw/i2c/i2c.h" | ||
24 | |||
25 | #define TYPE_PCA9552 "pca9552" | ||
26 | -#define PCA955X(obj) OBJECT_CHECK(PCA955xState, (obj), TYPE_PCA9552) | ||
27 | +#define TYPE_PCA955X "pca955x" | ||
28 | +#define PCA955X(obj) OBJECT_CHECK(PCA955xState, (obj), TYPE_PCA955X) | ||
29 | |||
30 | #define PCA955X_NR_REGS 10 | ||
31 | +#define PCA955X_PIN_COUNT_MAX 16 | ||
32 | |||
33 | typedef struct PCA955xState { | ||
34 | /*< private >*/ | ||
35 | @@ -XXX,XX +XXX,XX @@ typedef struct PCA955xState { | ||
36 | uint8_t pointer; | ||
37 | |||
38 | uint8_t regs[PCA955X_NR_REGS]; | ||
39 | - uint8_t max_reg; | ||
40 | - uint8_t pin_count; | ||
41 | } PCA955xState; | ||
42 | |||
43 | #endif | ||
44 | diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/hw/misc/pca9552.c | ||
47 | +++ b/hw/misc/pca9552.c | ||
48 | @@ -XXX,XX +XXX,XX @@ | ||
49 | * https://www.nxp.com/docs/en/application-note/AN264.pdf | ||
50 | * | ||
51 | * Copyright (c) 2017-2018, IBM Corporation. | ||
52 | + * Copyright (c) 2020 Philippe Mathieu-Daudé | ||
53 | * | ||
54 | * This work is licensed under the terms of the GNU GPL, version 2 or | ||
55 | * later. See the COPYING file in the top-level directory. | ||
56 | @@ -XXX,XX +XXX,XX @@ | ||
57 | #include "qapi/error.h" | ||
58 | #include "qapi/visitor.h" | ||
59 | |||
60 | +typedef struct PCA955xClass { | ||
61 | + /*< private >*/ | ||
62 | + I2CSlaveClass parent_class; | ||
63 | + /*< public >*/ | ||
64 | + | ||
65 | + uint8_t pin_count; | ||
66 | + uint8_t max_reg; | ||
67 | +} PCA955xClass; | ||
68 | + | ||
69 | +#define PCA955X_CLASS(klass) \ | ||
70 | + OBJECT_CLASS_CHECK(PCA955xClass, (klass), TYPE_PCA955X) | ||
71 | +#define PCA955X_GET_CLASS(obj) \ | ||
72 | + OBJECT_GET_CLASS(PCA955xClass, (obj), TYPE_PCA955X) | ||
73 | + | ||
74 | #define PCA9552_LED_ON 0x0 | ||
75 | #define PCA9552_LED_OFF 0x1 | ||
76 | #define PCA9552_LED_PWM0 0x2 | ||
77 | @@ -XXX,XX +XXX,XX @@ static uint8_t pca955x_pin_get_config(PCA955xState *s, int pin) | ||
78 | |||
79 | static void pca955x_update_pin_input(PCA955xState *s) | ||
80 | { | ||
81 | + PCA955xClass *k = PCA955X_GET_CLASS(s); | ||
82 | int i; | ||
83 | |||
84 | - for (i = 0; i < s->pin_count; i++) { | ||
85 | + for (i = 0; i < k->pin_count; i++) { | ||
86 | uint8_t input_reg = PCA9552_INPUT0 + (i / 8); | ||
87 | uint8_t input_shift = (i % 8); | ||
88 | uint8_t config = pca955x_pin_get_config(s, i); | ||
89 | @@ -XXX,XX +XXX,XX @@ static void pca955x_write(PCA955xState *s, uint8_t reg, uint8_t data) | ||
90 | */ | ||
91 | static void pca955x_autoinc(PCA955xState *s) | ||
92 | { | ||
93 | + PCA955xClass *k = PCA955X_GET_CLASS(s); | ||
94 | + | ||
95 | if (s->pointer != 0xFF && s->pointer & PCA9552_AUTOINC) { | ||
96 | uint8_t reg = s->pointer & 0xf; | ||
97 | |||
98 | - reg = (reg + 1) % (s->max_reg + 1); | ||
99 | + reg = (reg + 1) % (k->max_reg + 1); | ||
100 | s->pointer = reg | PCA9552_AUTOINC; | ||
101 | } | ||
102 | } | ||
103 | @@ -XXX,XX +XXX,XX @@ static int pca955x_event(I2CSlave *i2c, enum i2c_event event) | ||
104 | static void pca955x_get_led(Object *obj, Visitor *v, const char *name, | ||
105 | void *opaque, Error **errp) | ||
106 | { | ||
107 | + PCA955xClass *k = PCA955X_GET_CLASS(obj); | ||
108 | PCA955xState *s = PCA955X(obj); | ||
109 | int led, rc, reg; | ||
110 | uint8_t state; | ||
111 | @@ -XXX,XX +XXX,XX @@ static void pca955x_get_led(Object *obj, Visitor *v, const char *name, | ||
112 | error_setg(errp, "%s: error reading %s", __func__, name); | ||
113 | return; | ||
114 | } | ||
115 | - if (led < 0 || led > s->pin_count) { | ||
116 | + if (led < 0 || led > k->pin_count) { | ||
117 | error_setg(errp, "%s invalid led %s", __func__, name); | ||
118 | return; | ||
119 | } | ||
120 | @@ -XXX,XX +XXX,XX @@ static inline uint8_t pca955x_ledsel(uint8_t oldval, int led_num, int state) | ||
121 | static void pca955x_set_led(Object *obj, Visitor *v, const char *name, | ||
122 | void *opaque, Error **errp) | ||
123 | { | ||
124 | + PCA955xClass *k = PCA955X_GET_CLASS(obj); | ||
125 | PCA955xState *s = PCA955X(obj); | ||
126 | Error *local_err = NULL; | ||
127 | int led, rc, reg, val; | ||
128 | @@ -XXX,XX +XXX,XX @@ static void pca955x_set_led(Object *obj, Visitor *v, const char *name, | ||
129 | error_setg(errp, "%s: error reading %s", __func__, name); | ||
130 | return; | ||
131 | } | ||
132 | - if (led < 0 || led > s->pin_count) { | ||
133 | + if (led < 0 || led > k->pin_count) { | ||
134 | error_setg(errp, "%s invalid led %s", __func__, name); | ||
135 | return; | ||
136 | } | ||
137 | @@ -XXX,XX +XXX,XX @@ static void pca9552_reset(DeviceState *dev) | ||
138 | |||
139 | static void pca955x_initfn(Object *obj) | ||
140 | { | ||
141 | - PCA955xState *s = PCA955X(obj); | ||
142 | + PCA955xClass *k = PCA955X_GET_CLASS(obj); | ||
143 | int led; | ||
144 | |||
145 | - /* If support for the other PCA955X devices are implemented, these | ||
146 | - * constant values might be part of class structure describing the | ||
147 | - * PCA955X device | ||
148 | - */ | ||
149 | - s->max_reg = PCA9552_LS3; | ||
150 | - s->pin_count = 16; | ||
151 | - | ||
152 | - for (led = 0; led < s->pin_count; led++) { | ||
153 | + assert(k->pin_count <= PCA955X_PIN_COUNT_MAX); | ||
154 | + for (led = 0; led < k->pin_count; led++) { | ||
155 | char *name; | ||
156 | |||
157 | name = g_strdup_printf("led%d", led); | ||
158 | @@ -XXX,XX +XXX,XX @@ static void pca955x_initfn(Object *obj) | ||
159 | } | ||
160 | } | ||
161 | |||
162 | -static void pca9552_class_init(ObjectClass *klass, void *data) | ||
163 | +static void pca955x_class_init(ObjectClass *klass, void *data) | ||
164 | { | ||
165 | - DeviceClass *dc = DEVICE_CLASS(klass); | ||
166 | I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); | ||
167 | |||
168 | k->event = pca955x_event; | ||
169 | k->recv = pca955x_recv; | ||
170 | k->send = pca955x_send; | ||
171 | +} | ||
172 | + | ||
173 | +static const TypeInfo pca955x_info = { | ||
174 | + .name = TYPE_PCA955X, | ||
175 | + .parent = TYPE_I2C_SLAVE, | ||
176 | + .instance_init = pca955x_initfn, | ||
177 | + .instance_size = sizeof(PCA955xState), | ||
178 | + .class_init = pca955x_class_init, | ||
179 | + .abstract = true, | ||
180 | +}; | ||
181 | + | ||
182 | +static void pca9552_class_init(ObjectClass *oc, void *data) | ||
183 | +{ | ||
184 | + DeviceClass *dc = DEVICE_CLASS(oc); | ||
185 | + PCA955xClass *pc = PCA955X_CLASS(oc); | ||
186 | + | ||
187 | dc->reset = pca9552_reset; | ||
188 | dc->vmsd = &pca9552_vmstate; | ||
189 | + pc->max_reg = PCA9552_LS3; | ||
190 | + pc->pin_count = 16; | ||
191 | } | ||
192 | |||
193 | static const TypeInfo pca9552_info = { | ||
194 | .name = TYPE_PCA9552, | ||
195 | - .parent = TYPE_I2C_SLAVE, | ||
196 | - .instance_init = pca955x_initfn, | ||
197 | - .instance_size = sizeof(PCA955xState), | ||
198 | + .parent = TYPE_PCA955X, | ||
199 | .class_init = pca9552_class_init, | ||
200 | }; | ||
201 | |||
202 | static void pca955x_register_types(void) | ||
203 | { | ||
204 | + type_register_static(&pca955x_info); | ||
205 | type_register_static(&pca9552_info); | ||
206 | } | ||
207 | |||
208 | -- | ||
209 | 2.20.1 | ||
210 | |||
211 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Add a description field to distinguish between multiple devices. | ||
4 | |||
5 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
6 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Tested-by: Cédric Le Goater <clg@kaod.org> | ||
8 | Message-id: 20200623072723.6324-6-f4bug@amsat.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | include/hw/misc/pca9552.h | 1 + | ||
12 | hw/misc/pca9552.c | 18 ++++++++++++++++++ | ||
13 | 2 files changed, 19 insertions(+) | ||
14 | |||
15 | diff --git a/include/hw/misc/pca9552.h b/include/hw/misc/pca9552.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/misc/pca9552.h | ||
18 | +++ b/include/hw/misc/pca9552.h | ||
19 | @@ -XXX,XX +XXX,XX @@ typedef struct PCA955xState { | ||
20 | uint8_t pointer; | ||
21 | |||
22 | uint8_t regs[PCA955X_NR_REGS]; | ||
23 | + char *description; /* For debugging purpose only */ | ||
24 | } PCA955xState; | ||
25 | |||
26 | #endif | ||
27 | diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/hw/misc/pca9552.c | ||
30 | +++ b/hw/misc/pca9552.c | ||
31 | @@ -XXX,XX +XXX,XX @@ | ||
32 | #include "qemu/osdep.h" | ||
33 | #include "qemu/log.h" | ||
34 | #include "qemu/module.h" | ||
35 | +#include "hw/qdev-properties.h" | ||
36 | #include "hw/misc/pca9552.h" | ||
37 | #include "hw/misc/pca9552_regs.h" | ||
38 | #include "migration/vmstate.h" | ||
39 | @@ -XXX,XX +XXX,XX @@ static void pca955x_initfn(Object *obj) | ||
40 | } | ||
41 | } | ||
42 | |||
43 | +static void pca955x_realize(DeviceState *dev, Error **errp) | ||
44 | +{ | ||
45 | + PCA955xState *s = PCA955X(dev); | ||
46 | + | ||
47 | + if (!s->description) { | ||
48 | + s->description = g_strdup("pca-unspecified"); | ||
49 | + } | ||
50 | +} | ||
51 | + | ||
52 | +static Property pca955x_properties[] = { | ||
53 | + DEFINE_PROP_STRING("description", PCA955xState, description), | ||
54 | + DEFINE_PROP_END_OF_LIST(), | ||
55 | +}; | ||
56 | + | ||
57 | static void pca955x_class_init(ObjectClass *klass, void *data) | ||
58 | { | ||
59 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
60 | I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); | ||
61 | |||
62 | k->event = pca955x_event; | ||
63 | k->recv = pca955x_recv; | ||
64 | k->send = pca955x_send; | ||
65 | + dc->realize = pca955x_realize; | ||
66 | + device_class_set_props(dc, pca955x_properties); | ||
67 | } | ||
68 | |||
69 | static const TypeInfo pca955x_info = { | ||
70 | -- | ||
71 | 2.20.1 | ||
72 | |||
73 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Add a trivial representation of the PCA9552 GPIOs. | ||
4 | |||
5 | Example booting obmc-phosphor-image: | ||
6 | |||
7 | $ qemu-system-arm -M witherspoon-bmc -trace pca955x_gpio_status | ||
8 | 1592689902.327837:pca955x_gpio_status pca-unspecified GPIOs 0-15 [*...............] | ||
9 | 1592689902.329934:pca955x_gpio_status pca-unspecified GPIOs 0-15 [**..............] | ||
10 | 1592689902.330717:pca955x_gpio_status pca-unspecified GPIOs 0-15 [***.............] | ||
11 | 1592689902.331431:pca955x_gpio_status pca-unspecified GPIOs 0-15 [****............] | ||
12 | 1592689902.332163:pca955x_gpio_status pca-unspecified GPIOs 0-15 [****.........*..] | ||
13 | 1592689902.332888:pca955x_gpio_status pca-unspecified GPIOs 0-15 [****.........**.] | ||
14 | 1592689902.333629:pca955x_gpio_status pca-unspecified GPIOs 0-15 [****.........***] | ||
15 | 1592690032.793289:pca955x_gpio_status pca-unspecified GPIOs 0-15 [****.........*.*] | ||
16 | 1592690033.303163:pca955x_gpio_status pca-unspecified GPIOs 0-15 [****.........***] | ||
17 | 1592690033.812962:pca955x_gpio_status pca-unspecified GPIOs 0-15 [****.........*.*] | ||
18 | 1592690034.323234:pca955x_gpio_status pca-unspecified GPIOs 0-15 [****.........***] | ||
19 | 1592690034.832922:pca955x_gpio_status pca-unspecified GPIOs 0-15 [****.........*.*] | ||
20 | |||
21 | We notice the GPIO #14 (front-power LED) starts to blink. | ||
22 | |||
23 | This LED is described in the witherspoon device-tree [*]: | ||
24 | |||
25 | front-power { | ||
26 | retain-state-shutdown; | ||
27 | default-state = "keep"; | ||
28 | gpios = <&pca0 14 GPIO_ACTIVE_LOW>; | ||
29 | }; | ||
30 | |||
31 | [*] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts?id=b1f9be9392f0#n140 | ||
32 | |||
33 | Suggested-by: Cédric Le Goater <clg@kaod.org> | ||
34 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
35 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
36 | Tested-by: Cédric Le Goater <clg@kaod.org> | ||
37 | Message-id: 20200623072723.6324-7-f4bug@amsat.org | ||
38 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
39 | --- | ||
40 | hw/misc/pca9552.c | 39 +++++++++++++++++++++++++++++++++++++++ | ||
41 | hw/misc/trace-events | 3 +++ | ||
42 | 2 files changed, 42 insertions(+) | ||
43 | |||
44 | diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/hw/misc/pca9552.c | ||
47 | +++ b/hw/misc/pca9552.c | ||
48 | @@ -XXX,XX +XXX,XX @@ | ||
49 | #include "qemu/osdep.h" | ||
50 | #include "qemu/log.h" | ||
51 | #include "qemu/module.h" | ||
52 | +#include "qemu/bitops.h" | ||
53 | #include "hw/qdev-properties.h" | ||
54 | #include "hw/misc/pca9552.h" | ||
55 | #include "hw/misc/pca9552_regs.h" | ||
56 | #include "migration/vmstate.h" | ||
57 | #include "qapi/error.h" | ||
58 | #include "qapi/visitor.h" | ||
59 | +#include "trace.h" | ||
60 | |||
61 | typedef struct PCA955xClass { | ||
62 | /*< private >*/ | ||
63 | @@ -XXX,XX +XXX,XX @@ static uint8_t pca955x_pin_get_config(PCA955xState *s, int pin) | ||
64 | return extract32(s->regs[reg], shift, 2); | ||
65 | } | ||
66 | |||
67 | +/* Return INPUT status (bit #N belongs to GPIO #N) */ | ||
68 | +static uint16_t pca955x_pins_get_status(PCA955xState *s) | ||
69 | +{ | ||
70 | + return (s->regs[PCA9552_INPUT1] << 8) | s->regs[PCA9552_INPUT0]; | ||
71 | +} | ||
72 | + | ||
73 | +static void pca955x_display_pins_status(PCA955xState *s, | ||
74 | + uint16_t previous_pins_status) | ||
75 | +{ | ||
76 | + PCA955xClass *k = PCA955X_GET_CLASS(s); | ||
77 | + uint16_t pins_status, pins_changed; | ||
78 | + int i; | ||
79 | + | ||
80 | + pins_status = pca955x_pins_get_status(s); | ||
81 | + pins_changed = previous_pins_status ^ pins_status; | ||
82 | + if (!pins_changed) { | ||
83 | + return; | ||
84 | + } | ||
85 | + if (trace_event_get_state_backends(TRACE_PCA955X_GPIO_STATUS)) { | ||
86 | + char *buf = g_newa(char, k->pin_count + 1); | ||
87 | + | ||
88 | + for (i = 0; i < k->pin_count; i++) { | ||
89 | + if (extract32(pins_status, i, 1)) { | ||
90 | + buf[i] = '*'; | ||
91 | + } else { | ||
92 | + buf[i] = '.'; | ||
93 | + } | ||
94 | + } | ||
95 | + buf[i] = '\0'; | ||
96 | + trace_pca955x_gpio_status(s->description, buf); | ||
97 | + } | ||
98 | +} | ||
99 | + | ||
100 | static void pca955x_update_pin_input(PCA955xState *s) | ||
101 | { | ||
102 | PCA955xClass *k = PCA955X_GET_CLASS(s); | ||
103 | @@ -XXX,XX +XXX,XX @@ static uint8_t pca955x_read(PCA955xState *s, uint8_t reg) | ||
104 | |||
105 | static void pca955x_write(PCA955xState *s, uint8_t reg, uint8_t data) | ||
106 | { | ||
107 | + uint16_t pins_status; | ||
108 | + | ||
109 | switch (reg) { | ||
110 | case PCA9552_PSC0: | ||
111 | case PCA9552_PWM0: | ||
112 | @@ -XXX,XX +XXX,XX @@ static void pca955x_write(PCA955xState *s, uint8_t reg, uint8_t data) | ||
113 | case PCA9552_LS1: | ||
114 | case PCA9552_LS2: | ||
115 | case PCA9552_LS3: | ||
116 | + pins_status = pca955x_pins_get_status(s); | ||
117 | s->regs[reg] = data; | ||
118 | pca955x_update_pin_input(s); | ||
119 | + pca955x_display_pins_status(s, pins_status); | ||
120 | break; | ||
121 | |||
122 | case PCA9552_INPUT0: | ||
123 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
124 | index XXXXXXX..XXXXXXX 100644 | ||
125 | --- a/hw/misc/trace-events | ||
126 | +++ b/hw/misc/trace-events | ||
127 | @@ -XXX,XX +XXX,XX @@ via1_adb_poll(uint8_t data, const char *vadbint, int status, int index, int size | ||
128 | # grlib_ahb_apb_pnp.c | ||
129 | grlib_ahb_pnp_read(uint64_t addr, uint32_t value) "AHB PnP read addr:0x%03"PRIx64" data:0x%08x" | ||
130 | grlib_apb_pnp_read(uint64_t addr, uint32_t value) "APB PnP read addr:0x%03"PRIx64" data:0x%08x" | ||
131 | + | ||
132 | +# pca9552.c | ||
133 | +pca955x_gpio_status(const char *description, const char *buf) "%s GPIOs 0-15 [%s]" | ||
134 | -- | ||
135 | 2.20.1 | ||
136 | |||
137 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | We have 2 distinct PCA9552 devices. Set their description | ||
4 | to distinguish them when looking at the trace events. | ||
5 | |||
6 | Description name taken from: | ||
7 | https://github.com/open-power/witherspoon-xml/blob/master/witherspoon.xml | ||
8 | |||
9 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
10 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Reviewed-by: Corey Minyard <cminyard@mvista.com> | ||
12 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | ||
13 | Tested-by: Cédric Le Goater <clg@kaod.org> | ||
14 | Message-id: 20200623072723.6324-8-f4bug@amsat.org | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | --- | ||
17 | hw/arm/aspeed.c | 13 +++++++++---- | ||
18 | 1 file changed, 9 insertions(+), 4 deletions(-) | ||
19 | |||
20 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/hw/arm/aspeed.c | ||
23 | +++ b/hw/arm/aspeed.c | ||
24 | @@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) | ||
25 | { | ||
26 | AspeedSoCState *soc = &bmc->soc; | ||
27 | uint8_t *eeprom_buf = g_malloc0(8 * 1024); | ||
28 | + DeviceState *dev; | ||
29 | |||
30 | /* Bus 3: TODO bmp280@77 */ | ||
31 | /* Bus 3: TODO max31785@52 */ | ||
32 | /* Bus 3: TODO dps310@76 */ | ||
33 | - i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), TYPE_PCA9552, | ||
34 | - 0x60); | ||
35 | + dev = i2c_try_create_slave(TYPE_PCA9552, 0x60); | ||
36 | + qdev_prop_set_string(dev, "description", "pca1"); | ||
37 | + i2c_realize_and_unref(dev, aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), | ||
38 | + &error_fatal); | ||
39 | |||
40 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c); | ||
41 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c); | ||
42 | @@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) | ||
43 | |||
44 | smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51, | ||
45 | eeprom_buf); | ||
46 | - i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), TYPE_PCA9552, | ||
47 | - 0x60); | ||
48 | + dev = i2c_try_create_slave(TYPE_PCA9552, 0x60); | ||
49 | + qdev_prop_set_string(dev, "description", "pca0"); | ||
50 | + i2c_realize_and_unref(dev, aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), | ||
51 | + &error_fatal); | ||
52 | /* Bus 11: TODO ucd90160@64 */ | ||
53 | } | ||
54 | |||
55 | -- | ||
56 | 2.20.1 | ||
57 | |||
58 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Emit a trace event when a GPIO change its state. | ||
4 | |||
5 | Example booting obmc-phosphor-image: | ||
6 | |||
7 | $ qemu-system-arm -M witherspoon-bmc -trace pca955x_gpio_change | ||
8 | 1592690552.687372:pca955x_gpio_change pca1 GPIO id:0 status: 0 -> 1 | ||
9 | 1592690552.690169:pca955x_gpio_change pca1 GPIO id:1 status: 0 -> 1 | ||
10 | 1592690552.691673:pca955x_gpio_change pca1 GPIO id:2 status: 0 -> 1 | ||
11 | 1592690552.696886:pca955x_gpio_change pca1 GPIO id:3 status: 0 -> 1 | ||
12 | 1592690552.698614:pca955x_gpio_change pca1 GPIO id:13 status: 0 -> 1 | ||
13 | 1592690552.699833:pca955x_gpio_change pca1 GPIO id:14 status: 0 -> 1 | ||
14 | 1592690552.700842:pca955x_gpio_change pca1 GPIO id:15 status: 0 -> 1 | ||
15 | 1592690683.841921:pca955x_gpio_change pca1 GPIO id:14 status: 1 -> 0 | ||
16 | 1592690683.861660:pca955x_gpio_change pca1 GPIO id:14 status: 0 -> 1 | ||
17 | 1592690684.371460:pca955x_gpio_change pca1 GPIO id:14 status: 1 -> 0 | ||
18 | 1592690684.882115:pca955x_gpio_change pca1 GPIO id:14 status: 0 -> 1 | ||
19 | 1592690685.391411:pca955x_gpio_change pca1 GPIO id:14 status: 1 -> 0 | ||
20 | 1592690685.901391:pca955x_gpio_change pca1 GPIO id:14 status: 0 -> 1 | ||
21 | 1592690686.411678:pca955x_gpio_change pca1 GPIO id:14 status: 1 -> 0 | ||
22 | 1592690686.921279:pca955x_gpio_change pca1 GPIO id:14 status: 0 -> 1 | ||
23 | |||
24 | We notice the GPIO #14 (front-power LED) starts to blink. | ||
25 | |||
26 | This LED is described in the witherspoon device-tree [*]: | ||
27 | |||
28 | front-power { | ||
29 | retain-state-shutdown; | ||
30 | default-state = "keep"; | ||
31 | gpios = <&pca0 14 GPIO_ACTIVE_LOW>; | ||
32 | }; | ||
33 | |||
34 | [*] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts?id=b1f9be9392f0#n140 | ||
35 | |||
36 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
37 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
38 | Tested-by: Cédric Le Goater <clg@kaod.org> | ||
39 | Message-id: 20200623072723.6324-9-f4bug@amsat.org | ||
40 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
41 | --- | ||
42 | hw/misc/pca9552.c | 15 +++++++++++++++ | ||
43 | hw/misc/trace-events | 1 + | ||
44 | 2 files changed, 16 insertions(+) | ||
45 | |||
46 | diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/hw/misc/pca9552.c | ||
49 | +++ b/hw/misc/pca9552.c | ||
50 | @@ -XXX,XX +XXX,XX @@ static void pca955x_display_pins_status(PCA955xState *s, | ||
51 | buf[i] = '\0'; | ||
52 | trace_pca955x_gpio_status(s->description, buf); | ||
53 | } | ||
54 | + if (trace_event_get_state_backends(TRACE_PCA955X_GPIO_CHANGE)) { | ||
55 | + for (i = 0; i < k->pin_count; i++) { | ||
56 | + if (extract32(pins_changed, i, 1)) { | ||
57 | + unsigned new_state = extract32(pins_status, i, 1); | ||
58 | + | ||
59 | + /* | ||
60 | + * We display the state using the PCA logic ("active-high"). | ||
61 | + * This is not the state of the LED, which signal might be | ||
62 | + * wired "active-low" on the board. | ||
63 | + */ | ||
64 | + trace_pca955x_gpio_change(s->description, i, | ||
65 | + !new_state, new_state); | ||
66 | + } | ||
67 | + } | ||
68 | + } | ||
69 | } | ||
70 | |||
71 | static void pca955x_update_pin_input(PCA955xState *s) | ||
72 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/hw/misc/trace-events | ||
75 | +++ b/hw/misc/trace-events | ||
76 | @@ -XXX,XX +XXX,XX @@ grlib_apb_pnp_read(uint64_t addr, uint32_t value) "APB PnP read addr:0x%03"PRIx6 | ||
77 | |||
78 | # pca9552.c | ||
79 | pca955x_gpio_status(const char *description, const char *buf) "%s GPIOs 0-15 [%s]" | ||
80 | +pca955x_gpio_change(const char *description, unsigned id, unsigned prev_state, unsigned current_state) "%s GPIO id:%u status: %u -> %u" | ||
81 | -- | ||
82 | 2.20.1 | ||
83 | |||
84 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | The PCA9552 has 16 GPIOs which can be used as input, | ||
4 | output or PWM mode. QEMU models the output GPIO with | ||
5 | the qemu_irq type. Let the device expose the 16 GPIOs | ||
6 | to allow us to later connect LEDs to these outputs. | ||
7 | |||
8 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
9 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
10 | Tested-by: Cédric Le Goater <clg@kaod.org> | ||
11 | Message-id: 20200623072723.6324-10-f4bug@amsat.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | include/hw/misc/pca9552.h | 1 + | ||
15 | hw/misc/pca9552.c | 6 ++++++ | ||
16 | 2 files changed, 7 insertions(+) | ||
17 | |||
18 | diff --git a/include/hw/misc/pca9552.h b/include/hw/misc/pca9552.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/misc/pca9552.h | ||
21 | +++ b/include/hw/misc/pca9552.h | ||
22 | @@ -XXX,XX +XXX,XX @@ typedef struct PCA955xState { | ||
23 | uint8_t pointer; | ||
24 | |||
25 | uint8_t regs[PCA955X_NR_REGS]; | ||
26 | + qemu_irq gpio[PCA955X_PIN_COUNT_MAX]; | ||
27 | char *description; /* For debugging purpose only */ | ||
28 | } PCA955xState; | ||
29 | |||
30 | diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/hw/misc/pca9552.c | ||
33 | +++ b/hw/misc/pca9552.c | ||
34 | @@ -XXX,XX +XXX,XX @@ | ||
35 | #include "hw/qdev-properties.h" | ||
36 | #include "hw/misc/pca9552.h" | ||
37 | #include "hw/misc/pca9552_regs.h" | ||
38 | +#include "hw/irq.h" | ||
39 | #include "migration/vmstate.h" | ||
40 | #include "qapi/error.h" | ||
41 | #include "qapi/visitor.h" | ||
42 | @@ -XXX,XX +XXX,XX @@ static void pca955x_update_pin_input(PCA955xState *s) | ||
43 | |||
44 | switch (config) { | ||
45 | case PCA9552_LED_ON: | ||
46 | + qemu_set_irq(s->gpio[i], 1); | ||
47 | s->regs[input_reg] |= 1 << input_shift; | ||
48 | break; | ||
49 | case PCA9552_LED_OFF: | ||
50 | + qemu_set_irq(s->gpio[i], 0); | ||
51 | s->regs[input_reg] &= ~(1 << input_shift); | ||
52 | break; | ||
53 | case PCA9552_LED_PWM0: | ||
54 | @@ -XXX,XX +XXX,XX @@ static void pca955x_initfn(Object *obj) | ||
55 | |||
56 | static void pca955x_realize(DeviceState *dev, Error **errp) | ||
57 | { | ||
58 | + PCA955xClass *k = PCA955X_GET_CLASS(dev); | ||
59 | PCA955xState *s = PCA955X(dev); | ||
60 | |||
61 | if (!s->description) { | ||
62 | s->description = g_strdup("pca-unspecified"); | ||
63 | } | ||
64 | + | ||
65 | + qdev_init_gpio_out(dev, s->gpio, k->pin_count); | ||
66 | } | ||
67 | |||
68 | static Property pca955x_properties[] = { | ||
69 | -- | ||
70 | 2.20.1 | ||
71 | |||
72 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20200626033144.790098-2-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/cpu.h | 10 ++++++++++ | ||
9 | 1 file changed, 10 insertions(+) | ||
10 | |||
11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/cpu.h | ||
14 | +++ b/target/arm/cpu.h | ||
15 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) | ||
16 | return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; | ||
17 | } | ||
18 | |||
19 | +static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) | ||
20 | +{ | ||
21 | + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; | ||
22 | +} | ||
23 | + | ||
24 | +static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) | ||
25 | +{ | ||
26 | + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; | ||
27 | +} | ||
28 | + | ||
29 | static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) | ||
30 | { | ||
31 | return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && | ||
32 | -- | ||
33 | 2.20.1 | ||
34 | |||
35 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Protect reads of aa64 id registers with ARM_CP_STATE_AA64. | ||
4 | Use this as a simpler test than arm_el_is_aa64, since EL3 | ||
5 | cannot change mode. | ||
6 | |||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20200626033144.790098-3-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/helper.c | 15 ++++++++------- | ||
13 | 1 file changed, 8 insertions(+), 7 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/helper.c | ||
18 | +++ b/target/arm/helper.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
20 | uint32_t valid_mask = 0x3fff; | ||
21 | ARMCPU *cpu = env_archcpu(env); | ||
22 | |||
23 | - if (arm_el_is_aa64(env, 3)) { | ||
24 | + if (ri->state == ARM_CP_STATE_AA64) { | ||
25 | value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ | ||
26 | valid_mask &= ~SCR_NET; | ||
27 | + | ||
28 | + if (cpu_isar_feature(aa64_lor, cpu)) { | ||
29 | + valid_mask |= SCR_TLOR; | ||
30 | + } | ||
31 | + if (cpu_isar_feature(aa64_pauth, cpu)) { | ||
32 | + valid_mask |= SCR_API | SCR_APK; | ||
33 | + } | ||
34 | } else { | ||
35 | valid_mask &= ~(SCR_RW | SCR_ST); | ||
36 | } | ||
37 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
38 | valid_mask &= ~SCR_SMD; | ||
39 | } | ||
40 | } | ||
41 | - if (cpu_isar_feature(aa64_lor, cpu)) { | ||
42 | - valid_mask |= SCR_TLOR; | ||
43 | - } | ||
44 | - if (cpu_isar_feature(aa64_pauth, cpu)) { | ||
45 | - valid_mask |= SCR_API | SCR_APK; | ||
46 | - } | ||
47 | |||
48 | /* Clear all-context RES0 bits. */ | ||
49 | value &= valid_mask; | ||
50 | -- | ||
51 | 2.20.1 | ||
52 | |||
53 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | The randomness tests in the NPCM7xx RNG test fail intermittently |
---|---|---|---|
2 | but fairly frequently. On my machine running the test in a loop: | ||
3 | while QTEST_QEMU_BINARY=./qemu-system-aarch64 ./tests/qtest/npcm7xx_rng-test; do true; done | ||
2 | 4 | ||
3 | This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, | 5 | will fail in less than a minute with an error like: |
4 | RGSR_EL1, GCR_EL1, GMID_EL1, and PSTATE.TCO. | 6 | ERROR:../../tests/qtest/npcm7xx_rng-test.c:256:test_first_byte_runs: |
7 | assertion failed (calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE) > 0.01): (0.00286205989 > 0.01) | ||
5 | 8 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | (Failures have been observed on all 4 of the randomness tests, |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | not just first_byte_runs.) |
8 | Message-id: 20200626033144.790098-8-richard.henderson@linaro.org | 11 | |
12 | It's not clear why these tests are failing like this, but intermittent | ||
13 | failures make CI and merge testing awkward, so disable running them | ||
14 | unless a developer specifically sets QEMU_TEST_FLAKY_RNG_TESTS when | ||
15 | running the test suite, until we work out the cause. | ||
16 | |||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
19 | Message-id: 20201102152454.8287-1-peter.maydell@linaro.org | ||
20 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
10 | --- | 21 | --- |
11 | target/arm/cpu.h | 4 ++ | 22 | tests/qtest/npcm7xx_rng-test.c | 14 ++++++++++---- |
12 | target/arm/internals.h | 9 ++++ | 23 | 1 file changed, 10 insertions(+), 4 deletions(-) |
13 | target/arm/helper.c | 94 ++++++++++++++++++++++++++++++++++++++ | ||
14 | target/arm/translate-a64.c | 21 +++++++++ | ||
15 | 4 files changed, 128 insertions(+) | ||
16 | 24 | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 25 | diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c |
18 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 27 | --- a/tests/qtest/npcm7xx_rng-test.c |
20 | +++ b/target/arm/cpu.h | 28 | +++ b/tests/qtest/npcm7xx_rng-test.c |
21 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 29 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv) |
22 | uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ | 30 | |
23 | uint64_t vpidr_el2; /* Virtualization Processor ID Register */ | 31 | qtest_add_func("npcm7xx_rng/enable_disable", test_enable_disable); |
24 | uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ | 32 | qtest_add_func("npcm7xx_rng/rosel", test_rosel); |
25 | + uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ | 33 | - qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit); |
26 | + uint64_t gcr_el1; | 34 | - qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs); |
27 | + uint64_t rgsr_el1; | 35 | - qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit); |
28 | } cp15; | 36 | - qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs); |
29 | 37 | + /* | |
30 | struct { | 38 | + * These tests fail intermittently; only run them on explicit |
31 | @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); | 39 | + * request until we figure out why. |
32 | #define PSTATE_SS (1U << 21) | 40 | + */ |
33 | #define PSTATE_PAN (1U << 22) | 41 | + if (getenv("QEMU_TEST_FLAKY_RNG_TESTS")) { |
34 | #define PSTATE_UAO (1U << 23) | 42 | + qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit); |
35 | +#define PSTATE_TCO (1U << 25) | 43 | + qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs); |
36 | #define PSTATE_V (1U << 28) | 44 | + qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit); |
37 | #define PSTATE_C (1U << 29) | 45 | + qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs); |
38 | #define PSTATE_Z (1U << 30) | ||
39 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/target/arm/internals.h | ||
42 | +++ b/target/arm/internals.h | ||
43 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) | ||
44 | if (isar_feature_aa64_uao(id)) { | ||
45 | valid |= PSTATE_UAO; | ||
46 | } | ||
47 | + if (isar_feature_aa64_mte(id)) { | ||
48 | + valid |= PSTATE_TCO; | ||
49 | + } | 46 | + } |
50 | 47 | ||
51 | return valid; | 48 | qtest_start("-machine npcm750-evb"); |
52 | } | 49 | ret = g_test_run(); |
53 | @@ -XXX,XX +XXX,XX @@ void arm_log_exception(int idx); | ||
54 | |||
55 | #endif /* !CONFIG_USER_ONLY */ | ||
56 | |||
57 | +/* | ||
58 | + * The log2 of the words in the tag block, for GMID_EL1.BS. | ||
59 | + * The is the maximum, 256 bytes, which manipulates 64-bits of tags. | ||
60 | + */ | ||
61 | +#define GMID_EL1_BS 6 | ||
62 | + | ||
63 | #endif | ||
64 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
65 | index XXXXXXX..XXXXXXX 100644 | ||
66 | --- a/target/arm/helper.c | ||
67 | +++ b/target/arm/helper.c | ||
68 | @@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | ||
69 | { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), | ||
70 | "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, | ||
71 | |||
72 | + { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), | ||
73 | + "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, | ||
74 | + | ||
75 | /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ | ||
76 | /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ | ||
77 | }; | ||
78 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpodp_reg[] = { | ||
79 | }; | ||
80 | #endif /*CONFIG_USER_ONLY*/ | ||
81 | |||
82 | +static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInfo *ri, | ||
83 | + bool isread) | ||
84 | +{ | ||
85 | + if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) { | ||
86 | + return CP_ACCESS_TRAP_EL2; | ||
87 | + } | ||
88 | + | ||
89 | + return CP_ACCESS_OK; | ||
90 | +} | ||
91 | + | ||
92 | +static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, | ||
93 | + bool isread) | ||
94 | +{ | ||
95 | + int el = arm_current_el(env); | ||
96 | + | ||
97 | + if (el < 2 && | ||
98 | + arm_feature(env, ARM_FEATURE_EL2) && | ||
99 | + !(arm_hcr_el2_eff(env) & HCR_ATA)) { | ||
100 | + return CP_ACCESS_TRAP_EL2; | ||
101 | + } | ||
102 | + if (el < 3 && | ||
103 | + arm_feature(env, ARM_FEATURE_EL3) && | ||
104 | + !(env->cp15.scr_el3 & SCR_ATA)) { | ||
105 | + return CP_ACCESS_TRAP_EL3; | ||
106 | + } | ||
107 | + return CP_ACCESS_OK; | ||
108 | +} | ||
109 | + | ||
110 | +static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
111 | +{ | ||
112 | + return env->pstate & PSTATE_TCO; | ||
113 | +} | ||
114 | + | ||
115 | +static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | ||
116 | +{ | ||
117 | + env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); | ||
118 | +} | ||
119 | + | ||
120 | +static const ARMCPRegInfo mte_reginfo[] = { | ||
121 | + { .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64, | ||
122 | + .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 1, | ||
123 | + .access = PL1_RW, .accessfn = access_mte, | ||
124 | + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) }, | ||
125 | + { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64, | ||
126 | + .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 0, | ||
127 | + .access = PL1_RW, .accessfn = access_mte, | ||
128 | + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) }, | ||
129 | + { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64, | ||
130 | + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 6, .opc2 = 0, | ||
131 | + .access = PL2_RW, .accessfn = access_mte, | ||
132 | + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) }, | ||
133 | + { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64, | ||
134 | + .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 6, .opc2 = 0, | ||
135 | + .access = PL3_RW, | ||
136 | + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) }, | ||
137 | + { .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64, | ||
138 | + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5, | ||
139 | + .access = PL1_RW, .accessfn = access_mte, | ||
140 | + .fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) }, | ||
141 | + { .name = "GCR_EL1", .state = ARM_CP_STATE_AA64, | ||
142 | + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, | ||
143 | + .access = PL1_RW, .accessfn = access_mte, | ||
144 | + .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, | ||
145 | + { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, | ||
146 | + .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, | ||
147 | + .access = PL1_R, .accessfn = access_aa64_tid5, | ||
148 | + .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, | ||
149 | + { .name = "TCO", .state = ARM_CP_STATE_AA64, | ||
150 | + .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | ||
151 | + .type = ARM_CP_NO_RAW, | ||
152 | + .access = PL0_RW, .readfn = tco_read, .writefn = tco_write }, | ||
153 | + REGINFO_SENTINEL | ||
154 | +}; | ||
155 | + | ||
156 | +static const ARMCPRegInfo mte_tco_ro_reginfo[] = { | ||
157 | + { .name = "TCO", .state = ARM_CP_STATE_AA64, | ||
158 | + .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | ||
159 | + .type = ARM_CP_CONST, .access = PL0_RW, }, | ||
160 | + REGINFO_SENTINEL | ||
161 | +}; | ||
162 | #endif | ||
163 | |||
164 | static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, | ||
165 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
166 | } | ||
167 | } | ||
168 | #endif /*CONFIG_USER_ONLY*/ | ||
169 | + | ||
170 | + /* | ||
171 | + * If full MTE is enabled, add all of the system registers. | ||
172 | + * If only "instructions available at EL0" are enabled, | ||
173 | + * then define only a RAZ/WI version of PSTATE.TCO. | ||
174 | + */ | ||
175 | + if (cpu_isar_feature(aa64_mte, cpu)) { | ||
176 | + define_arm_cp_regs(cpu, mte_reginfo); | ||
177 | + } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { | ||
178 | + define_arm_cp_regs(cpu, mte_tco_ro_reginfo); | ||
179 | + } | ||
180 | #endif | ||
181 | |||
182 | if (cpu_isar_feature(any_predinv, cpu)) { | ||
183 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
184 | index XXXXXXX..XXXXXXX 100644 | ||
185 | --- a/target/arm/translate-a64.c | ||
186 | +++ b/target/arm/translate-a64.c | ||
187 | @@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn, | ||
188 | s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
189 | break; | ||
190 | |||
191 | + case 0x1c: /* TCO */ | ||
192 | + if (dc_isar_feature(aa64_mte, s)) { | ||
193 | + /* Full MTE is enabled -- set the TCO bit as directed. */ | ||
194 | + if (crm & 1) { | ||
195 | + set_pstate_bits(PSTATE_TCO); | ||
196 | + } else { | ||
197 | + clear_pstate_bits(PSTATE_TCO); | ||
198 | + } | ||
199 | + t1 = tcg_const_i32(s->current_el); | ||
200 | + gen_helper_rebuild_hflags_a64(cpu_env, t1); | ||
201 | + tcg_temp_free_i32(t1); | ||
202 | + /* Many factors, including TCO, go into MTE_ACTIVE. */ | ||
203 | + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; | ||
204 | + } else if (dc_isar_feature(aa64_mte_insn_reg, s)) { | ||
205 | + /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */ | ||
206 | + s->base.is_jmp = DISAS_NEXT; | ||
207 | + } else { | ||
208 | + goto do_unallocated; | ||
209 | + } | ||
210 | + break; | ||
211 | + | ||
212 | default: | ||
213 | do_unallocated: | ||
214 | unallocated_encoding(s); | ||
215 | -- | 50 | -- |
216 | 2.20.1 | 51 | 2.20.1 |
217 | 52 | ||
218 | 53 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Cache the composite ATA setting. | ||
4 | |||
5 | Cache when MTE is fully enabled, i.e. access to tags are enabled | ||
6 | and tag checks affect the PE. Do this for both the normal context | ||
7 | and the UNPRIV context. | ||
8 | |||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20200626033144.790098-9-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | target/arm/cpu.h | 12 ++++++++---- | ||
15 | target/arm/internals.h | 18 +++++++++++++++++ | ||
16 | target/arm/translate.h | 5 +++++ | ||
17 | target/arm/helper.c | 40 ++++++++++++++++++++++++++++++++++++++ | ||
18 | target/arm/translate-a64.c | 4 ++++ | ||
19 | 5 files changed, 75 insertions(+), 4 deletions(-) | ||
20 | |||
21 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/target/arm/cpu.h | ||
24 | +++ b/target/arm/cpu.h | ||
25 | @@ -XXX,XX +XXX,XX @@ typedef ARMCPU ArchCPU; | ||
26 | * | | | TBFLAG_A32 | | | ||
27 | * | | +-----+----------+ TBFLAG_AM32 | | ||
28 | * | TBFLAG_ANY | |TBFLAG_M32| | | ||
29 | - * | | +-+----------+--------------| | ||
30 | - * | | | TBFLAG_A64 | | ||
31 | - * +--------------+---------+---------------------------+ | ||
32 | - * 31 20 15 0 | ||
33 | + * | +-----------+----------+--------------| | ||
34 | + * | | TBFLAG_A64 | | ||
35 | + * +--------------+-------------------------------------+ | ||
36 | + * 31 20 0 | ||
37 | * | ||
38 | * Unless otherwise noted, these bits are cached in env->hflags. | ||
39 | */ | ||
40 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, BT, 9, 1) | ||
41 | FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ | ||
42 | FIELD(TBFLAG_A64, TBID, 12, 2) | ||
43 | FIELD(TBFLAG_A64, UNPRIV, 14, 1) | ||
44 | +FIELD(TBFLAG_A64, ATA, 15, 1) | ||
45 | +FIELD(TBFLAG_A64, TCMA, 16, 2) | ||
46 | +FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) | ||
47 | +FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) | ||
48 | |||
49 | /** | ||
50 | * cpu_mmu_index: | ||
51 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
52 | index XXXXXXX..XXXXXXX 100644 | ||
53 | --- a/target/arm/internals.h | ||
54 | +++ b/target/arm/internals.h | ||
55 | @@ -XXX,XX +XXX,XX @@ static inline int exception_target_el(CPUARMState *env) | ||
56 | return target_el; | ||
57 | } | ||
58 | |||
59 | +/* Determine if allocation tags are available. */ | ||
60 | +static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, | ||
61 | + uint64_t sctlr) | ||
62 | +{ | ||
63 | + if (el < 3 | ||
64 | + && arm_feature(env, ARM_FEATURE_EL3) | ||
65 | + && !(env->cp15.scr_el3 & SCR_ATA)) { | ||
66 | + return false; | ||
67 | + } | ||
68 | + if (el < 2 | ||
69 | + && arm_feature(env, ARM_FEATURE_EL2) | ||
70 | + && !(arm_hcr_el2_eff(env) & HCR_ATA)) { | ||
71 | + return false; | ||
72 | + } | ||
73 | + sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA); | ||
74 | + return sctlr != 0; | ||
75 | +} | ||
76 | + | ||
77 | #ifndef CONFIG_USER_ONLY | ||
78 | |||
79 | /* Security attributes for an address, as returned by v8m_security_lookup. */ | ||
80 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
81 | index XXXXXXX..XXXXXXX 100644 | ||
82 | --- a/target/arm/translate.h | ||
83 | +++ b/target/arm/translate.h | ||
84 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | ||
85 | ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ | ||
86 | uint8_t tbii; /* TBI1|TBI0 for insns */ | ||
87 | uint8_t tbid; /* TBI1|TBI0 for data */ | ||
88 | + uint8_t tcma; /* TCMA1|TCMA0 for MTE */ | ||
89 | bool ns; /* Use non-secure CPREG bank on access */ | ||
90 | int fp_excp_el; /* FP exception EL or 0 if enabled */ | ||
91 | int sve_excp_el; /* SVE exception EL or 0 if enabled */ | ||
92 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | ||
93 | bool unpriv; | ||
94 | /* True if v8.3-PAuth is active. */ | ||
95 | bool pauth_active; | ||
96 | + /* True if v8.5-MTE access to tags is enabled. */ | ||
97 | + bool ata; | ||
98 | + /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv. */ | ||
99 | + bool mte_active[2]; | ||
100 | /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ | ||
101 | bool bt; | ||
102 | /* True if any CP15 access is trapped by HSTR_EL2 */ | ||
103 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
104 | index XXXXXXX..XXXXXXX 100644 | ||
105 | --- a/target/arm/helper.c | ||
106 | +++ b/target/arm/helper.c | ||
107 | @@ -XXX,XX +XXX,XX @@ static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) | ||
108 | } | ||
109 | } | ||
110 | |||
111 | +static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) | ||
112 | +{ | ||
113 | + if (regime_has_2_ranges(mmu_idx)) { | ||
114 | + return extract64(tcr, 57, 2); | ||
115 | + } else { | ||
116 | + /* Replicate the single TCMA bit so we always have 2 bits. */ | ||
117 | + return extract32(tcr, 30, 1) * 3; | ||
118 | + } | ||
119 | +} | ||
120 | + | ||
121 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
122 | ARMMMUIdx mmu_idx, bool data) | ||
123 | { | ||
124 | @@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, | ||
125 | } | ||
126 | } | ||
127 | |||
128 | + if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { | ||
129 | + /* | ||
130 | + * Set MTE_ACTIVE if any access may be Checked, and leave clear | ||
131 | + * if all accesses must be Unchecked: | ||
132 | + * 1) If no TBI, then there are no tags in the address to check, | ||
133 | + * 2) If Tag Check Override, then all accesses are Unchecked, | ||
134 | + * 3) If Tag Check Fail == 0, then Checked access have no effect, | ||
135 | + * 4) If no Allocation Tag Access, then all accesses are Unchecked. | ||
136 | + */ | ||
137 | + if (allocation_tag_access_enabled(env, el, sctlr)) { | ||
138 | + flags = FIELD_DP32(flags, TBFLAG_A64, ATA, 1); | ||
139 | + if (tbid | ||
140 | + && !(env->pstate & PSTATE_TCO) | ||
141 | + && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) { | ||
142 | + flags = FIELD_DP32(flags, TBFLAG_A64, MTE_ACTIVE, 1); | ||
143 | + } | ||
144 | + } | ||
145 | + /* And again for unprivileged accesses, if required. */ | ||
146 | + if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV) | ||
147 | + && tbid | ||
148 | + && !(env->pstate & PSTATE_TCO) | ||
149 | + && (sctlr & SCTLR_TCF0) | ||
150 | + && allocation_tag_access_enabled(env, 0, sctlr)) { | ||
151 | + flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1); | ||
152 | + } | ||
153 | + /* Cache TCMA as well as TBI. */ | ||
154 | + flags = FIELD_DP32(flags, TBFLAG_A64, TCMA, | ||
155 | + aa64_va_parameter_tcma(tcr, mmu_idx)); | ||
156 | + } | ||
157 | + | ||
158 | return rebuild_hflags_common(env, fp_el, mmu_idx, flags); | ||
159 | } | ||
160 | |||
161 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
162 | index XXXXXXX..XXXXXXX 100644 | ||
163 | --- a/target/arm/translate-a64.c | ||
164 | +++ b/target/arm/translate-a64.c | ||
165 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, | ||
166 | dc->mmu_idx = core_to_aa64_mmu_idx(core_mmu_idx); | ||
167 | dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII); | ||
168 | dc->tbid = FIELD_EX32(tb_flags, TBFLAG_A64, TBID); | ||
169 | + dc->tcma = FIELD_EX32(tb_flags, TBFLAG_A64, TCMA); | ||
170 | dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); | ||
171 | #if !defined(CONFIG_USER_ONLY) | ||
172 | dc->user = (dc->current_el == 0); | ||
173 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, | ||
174 | dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT); | ||
175 | dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); | ||
176 | dc->unpriv = FIELD_EX32(tb_flags, TBFLAG_A64, UNPRIV); | ||
177 | + dc->ata = FIELD_EX32(tb_flags, TBFLAG_A64, ATA); | ||
178 | + dc->mte_active[0] = FIELD_EX32(tb_flags, TBFLAG_A64, MTE_ACTIVE); | ||
179 | + dc->mte_active[1] = FIELD_EX32(tb_flags, TBFLAG_A64, MTE0_ACTIVE); | ||
180 | dc->vec_len = 0; | ||
181 | dc->vec_stride = 0; | ||
182 | dc->cp_regs = arm_cpu->cp_regs; | ||
183 | -- | ||
184 | 2.20.1 | ||
185 | |||
186 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20200626033144.790098-10-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/helper-a64.h | 2 ++ | ||
9 | target/arm/internals.h | 5 +++ | ||
10 | target/arm/mte_helper.c | 72 ++++++++++++++++++++++++++++++++++++++ | ||
11 | target/arm/translate-a64.c | 18 ++++++++++ | ||
12 | target/arm/Makefile.objs | 1 + | ||
13 | 5 files changed, 98 insertions(+) | ||
14 | create mode 100644 target/arm/mte_helper.c | ||
15 | |||
16 | diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/helper-a64.h | ||
19 | +++ b/target/arm/helper-a64.h | ||
20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64, i64) | ||
21 | DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) | ||
22 | DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) | ||
23 | DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) | ||
24 | + | ||
25 | +DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
26 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/target/arm/internals.h | ||
29 | +++ b/target/arm/internals.h | ||
30 | @@ -XXX,XX +XXX,XX @@ void arm_log_exception(int idx); | ||
31 | */ | ||
32 | #define GMID_EL1_BS 6 | ||
33 | |||
34 | +static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) | ||
35 | +{ | ||
36 | + return deposit64(ptr, 56, 4, rtag); | ||
37 | +} | ||
38 | + | ||
39 | #endif | ||
40 | diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c | ||
41 | new file mode 100644 | ||
42 | index XXXXXXX..XXXXXXX | ||
43 | --- /dev/null | ||
44 | +++ b/target/arm/mte_helper.c | ||
45 | @@ -XXX,XX +XXX,XX @@ | ||
46 | +/* | ||
47 | + * ARM v8.5-MemTag Operations | ||
48 | + * | ||
49 | + * Copyright (c) 2020 Linaro, Ltd. | ||
50 | + * | ||
51 | + * This library is free software; you can redistribute it and/or | ||
52 | + * modify it under the terms of the GNU Lesser General Public | ||
53 | + * License as published by the Free Software Foundation; either | ||
54 | + * version 2.1 of the License, or (at your option) any later version. | ||
55 | + * | ||
56 | + * This library is distributed in the hope that it will be useful, | ||
57 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
58 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
59 | + * Lesser General Public License for more details. | ||
60 | + * | ||
61 | + * You should have received a copy of the GNU Lesser General Public | ||
62 | + * License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
63 | + */ | ||
64 | + | ||
65 | +#include "qemu/osdep.h" | ||
66 | +#include "cpu.h" | ||
67 | +#include "internals.h" | ||
68 | +#include "exec/exec-all.h" | ||
69 | +#include "exec/cpu_ldst.h" | ||
70 | +#include "exec/helper-proto.h" | ||
71 | + | ||
72 | + | ||
73 | +static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) | ||
74 | +{ | ||
75 | + if (exclude == 0xffff) { | ||
76 | + return 0; | ||
77 | + } | ||
78 | + if (offset == 0) { | ||
79 | + while (exclude & (1 << tag)) { | ||
80 | + tag = (tag + 1) & 15; | ||
81 | + } | ||
82 | + } else { | ||
83 | + do { | ||
84 | + do { | ||
85 | + tag = (tag + 1) & 15; | ||
86 | + } while (exclude & (1 << tag)); | ||
87 | + } while (--offset > 0); | ||
88 | + } | ||
89 | + return tag; | ||
90 | +} | ||
91 | + | ||
92 | +uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) | ||
93 | +{ | ||
94 | + int rtag; | ||
95 | + | ||
96 | + /* | ||
97 | + * Our IMPDEF choice for GCR_EL1.RRND==1 is to behave as if | ||
98 | + * GCR_EL1.RRND==0, always producing deterministic results. | ||
99 | + */ | ||
100 | + uint16_t exclude = extract32(rm | env->cp15.gcr_el1, 0, 16); | ||
101 | + int start = extract32(env->cp15.rgsr_el1, 0, 4); | ||
102 | + int seed = extract32(env->cp15.rgsr_el1, 8, 16); | ||
103 | + int offset, i; | ||
104 | + | ||
105 | + /* RandomTag */ | ||
106 | + for (i = offset = 0; i < 4; ++i) { | ||
107 | + /* NextRandomTagBit */ | ||
108 | + int top = (extract32(seed, 5, 1) ^ extract32(seed, 3, 1) ^ | ||
109 | + extract32(seed, 2, 1) ^ extract32(seed, 0, 1)); | ||
110 | + seed = (top << 15) | (seed >> 1); | ||
111 | + offset |= top << i; | ||
112 | + } | ||
113 | + rtag = choose_nonexcluded_tag(start, offset, exclude); | ||
114 | + env->cp15.rgsr_el1 = rtag | (seed << 8); | ||
115 | + | ||
116 | + return address_with_allocation_tag(rn, rtag); | ||
117 | +} | ||
118 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
119 | index XXXXXXX..XXXXXXX 100644 | ||
120 | --- a/target/arm/translate-a64.c | ||
121 | +++ b/target/arm/translate-a64.c | ||
122 | @@ -XXX,XX +XXX,XX @@ static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) | ||
123 | return clean; | ||
124 | } | ||
125 | |||
126 | +/* Insert a zero tag into src, with the result at dst. */ | ||
127 | +static void gen_address_with_allocation_tag0(TCGv_i64 dst, TCGv_i64 src) | ||
128 | +{ | ||
129 | + tcg_gen_andi_i64(dst, src, ~MAKE_64BIT_MASK(56, 4)); | ||
130 | +} | ||
131 | + | ||
132 | typedef struct DisasCompare64 { | ||
133 | TCGCond cond; | ||
134 | TCGv_i64 value; | ||
135 | @@ -XXX,XX +XXX,XX @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) | ||
136 | case 3: /* SDIV */ | ||
137 | handle_div(s, true, sf, rm, rn, rd); | ||
138 | break; | ||
139 | + case 4: /* IRG */ | ||
140 | + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { | ||
141 | + goto do_unallocated; | ||
142 | + } | ||
143 | + if (s->ata) { | ||
144 | + gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, | ||
145 | + cpu_reg_sp(s, rn), cpu_reg(s, rm)); | ||
146 | + } else { | ||
147 | + gen_address_with_allocation_tag0(cpu_reg_sp(s, rd), | ||
148 | + cpu_reg_sp(s, rn)); | ||
149 | + } | ||
150 | + break; | ||
151 | case 8: /* LSLV */ | ||
152 | handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); | ||
153 | break; | ||
154 | diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs | ||
155 | index XXXXXXX..XXXXXXX 100644 | ||
156 | --- a/target/arm/Makefile.objs | ||
157 | +++ b/target/arm/Makefile.objs | ||
158 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_SOFTMMU) += psci.o | ||
159 | obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o | ||
160 | obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o | ||
161 | obj-$(TARGET_AARCH64) += pauth_helper.o | ||
162 | +obj-$(TARGET_AARCH64) += mte_helper.o | ||
163 | -- | ||
164 | 2.20.1 | ||
165 | |||
166 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | The current Arm ARM has adjusted the official decode of | ||
4 | "Add/subtract (immediate)" so that the shift field is only bit 22, | ||
5 | and bit 23 is part of the op1 field of the parent category | ||
6 | "Data processing - immediate". | ||
7 | |||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20200626033144.790098-11-richard.henderson@linaro.org | ||
11 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | target/arm/translate-a64.c | 23 ++++++++--------------- | ||
16 | 1 file changed, 8 insertions(+), 15 deletions(-) | ||
17 | |||
18 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/translate-a64.c | ||
21 | +++ b/target/arm/translate-a64.c | ||
22 | @@ -XXX,XX +XXX,XX @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) | ||
23 | /* | ||
24 | * Add/subtract (immediate) | ||
25 | * | ||
26 | - * 31 30 29 28 24 23 22 21 10 9 5 4 0 | ||
27 | - * +--+--+--+-----------+-----+-------------+-----+-----+ | ||
28 | - * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd | | ||
29 | - * +--+--+--+-----------+-----+-------------+-----+-----+ | ||
30 | + * 31 30 29 28 23 22 21 10 9 5 4 0 | ||
31 | + * +--+--+--+-------------+--+-------------+-----+-----+ | ||
32 | + * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd | | ||
33 | + * +--+--+--+-------------+--+-------------+-----+-----+ | ||
34 | * | ||
35 | * sf: 0 -> 32bit, 1 -> 64bit | ||
36 | * op: 0 -> add , 1 -> sub | ||
37 | * S: 1 -> set flags | ||
38 | - * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12 | ||
39 | + * sh: 1 -> LSL imm by 12 | ||
40 | */ | ||
41 | static void disas_add_sub_imm(DisasContext *s, uint32_t insn) | ||
42 | { | ||
43 | int rd = extract32(insn, 0, 5); | ||
44 | int rn = extract32(insn, 5, 5); | ||
45 | uint64_t imm = extract32(insn, 10, 12); | ||
46 | - int shift = extract32(insn, 22, 2); | ||
47 | + bool shift = extract32(insn, 22, 1); | ||
48 | bool setflags = extract32(insn, 29, 1); | ||
49 | bool sub_op = extract32(insn, 30, 1); | ||
50 | bool is_64bit = extract32(insn, 31, 1); | ||
51 | @@ -XXX,XX +XXX,XX @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) | ||
52 | TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); | ||
53 | TCGv_i64 tcg_result; | ||
54 | |||
55 | - switch (shift) { | ||
56 | - case 0x0: | ||
57 | - break; | ||
58 | - case 0x1: | ||
59 | + if (shift) { | ||
60 | imm <<= 12; | ||
61 | - break; | ||
62 | - default: | ||
63 | - unallocated_encoding(s); | ||
64 | - return; | ||
65 | } | ||
66 | |||
67 | tcg_result = tcg_temp_new_i64(); | ||
68 | @@ -XXX,XX +XXX,XX @@ static void disas_data_proc_imm(DisasContext *s, uint32_t insn) | ||
69 | case 0x20: case 0x21: /* PC-rel. addressing */ | ||
70 | disas_pc_rel_adr(s, insn); | ||
71 | break; | ||
72 | - case 0x22: case 0x23: /* Add/subtract (immediate) */ | ||
73 | + case 0x22: /* Add/subtract (immediate) */ | ||
74 | disas_add_sub_imm(s, insn); | ||
75 | break; | ||
76 | case 0x24: /* Logical (immediate) */ | ||
77 | -- | ||
78 | 2.20.1 | ||
79 | |||
80 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20200626033144.790098-12-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/helper-a64.h | 1 + | ||
9 | target/arm/internals.h | 9 +++++++ | ||
10 | target/arm/mte_helper.c | 10 ++++++++ | ||
11 | target/arm/translate-a64.c | 51 ++++++++++++++++++++++++++++++++++++++ | ||
12 | 4 files changed, 71 insertions(+) | ||
13 | |||
14 | diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/helper-a64.h | ||
17 | +++ b/target/arm/helper-a64.h | ||
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) | ||
19 | DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) | ||
20 | |||
21 | DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
22 | +DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32) | ||
23 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/target/arm/internals.h | ||
26 | +++ b/target/arm/internals.h | ||
27 | @@ -XXX,XX +XXX,XX @@ void arm_log_exception(int idx); | ||
28 | */ | ||
29 | #define GMID_EL1_BS 6 | ||
30 | |||
31 | +/* We associate one allocation tag per 16 bytes, the minimum. */ | ||
32 | +#define LOG2_TAG_GRANULE 4 | ||
33 | +#define TAG_GRANULE (1 << LOG2_TAG_GRANULE) | ||
34 | + | ||
35 | +static inline int allocation_tag_from_addr(uint64_t ptr) | ||
36 | +{ | ||
37 | + return extract64(ptr, 56, 4); | ||
38 | +} | ||
39 | + | ||
40 | static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) | ||
41 | { | ||
42 | return deposit64(ptr, 56, 4, rtag); | ||
43 | diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/target/arm/mte_helper.c | ||
46 | +++ b/target/arm/mte_helper.c | ||
47 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) | ||
48 | |||
49 | return address_with_allocation_tag(rn, rtag); | ||
50 | } | ||
51 | + | ||
52 | +uint64_t HELPER(addsubg)(CPUARMState *env, uint64_t ptr, | ||
53 | + int32_t offset, uint32_t tag_offset) | ||
54 | +{ | ||
55 | + int start_tag = allocation_tag_from_addr(ptr); | ||
56 | + uint16_t exclude = extract32(env->cp15.gcr_el1, 0, 16); | ||
57 | + int rtag = choose_nonexcluded_tag(start_tag, tag_offset, exclude); | ||
58 | + | ||
59 | + return address_with_allocation_tag(ptr + offset, rtag); | ||
60 | +} | ||
61 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/target/arm/translate-a64.c | ||
64 | +++ b/target/arm/translate-a64.c | ||
65 | @@ -XXX,XX +XXX,XX @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) | ||
66 | tcg_temp_free_i64(tcg_result); | ||
67 | } | ||
68 | |||
69 | +/* | ||
70 | + * Add/subtract (immediate, with tags) | ||
71 | + * | ||
72 | + * 31 30 29 28 23 22 21 16 14 10 9 5 4 0 | ||
73 | + * +--+--+--+-------------+--+---------+--+-------+-----+-----+ | ||
74 | + * |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd | | ||
75 | + * +--+--+--+-------------+--+---------+--+-------+-----+-----+ | ||
76 | + * | ||
77 | + * op: 0 -> add, 1 -> sub | ||
78 | + */ | ||
79 | +static void disas_add_sub_imm_with_tags(DisasContext *s, uint32_t insn) | ||
80 | +{ | ||
81 | + int rd = extract32(insn, 0, 5); | ||
82 | + int rn = extract32(insn, 5, 5); | ||
83 | + int uimm4 = extract32(insn, 10, 4); | ||
84 | + int uimm6 = extract32(insn, 16, 6); | ||
85 | + bool sub_op = extract32(insn, 30, 1); | ||
86 | + TCGv_i64 tcg_rn, tcg_rd; | ||
87 | + int imm; | ||
88 | + | ||
89 | + /* Test all of sf=1, S=0, o2=0, o3=0. */ | ||
90 | + if ((insn & 0xa040c000u) != 0x80000000u || | ||
91 | + !dc_isar_feature(aa64_mte_insn_reg, s)) { | ||
92 | + unallocated_encoding(s); | ||
93 | + return; | ||
94 | + } | ||
95 | + | ||
96 | + imm = uimm6 << LOG2_TAG_GRANULE; | ||
97 | + if (sub_op) { | ||
98 | + imm = -imm; | ||
99 | + } | ||
100 | + | ||
101 | + tcg_rn = cpu_reg_sp(s, rn); | ||
102 | + tcg_rd = cpu_reg_sp(s, rd); | ||
103 | + | ||
104 | + if (s->ata) { | ||
105 | + TCGv_i32 offset = tcg_const_i32(imm); | ||
106 | + TCGv_i32 tag_offset = tcg_const_i32(uimm4); | ||
107 | + | ||
108 | + gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); | ||
109 | + tcg_temp_free_i32(tag_offset); | ||
110 | + tcg_temp_free_i32(offset); | ||
111 | + } else { | ||
112 | + tcg_gen_addi_i64(tcg_rd, tcg_rn, imm); | ||
113 | + gen_address_with_allocation_tag0(tcg_rd, tcg_rd); | ||
114 | + } | ||
115 | +} | ||
116 | + | ||
117 | /* The input should be a value in the bottom e bits (with higher | ||
118 | * bits zero); returns that value replicated into every element | ||
119 | * of size e in a 64 bit integer. | ||
120 | @@ -XXX,XX +XXX,XX @@ static void disas_data_proc_imm(DisasContext *s, uint32_t insn) | ||
121 | case 0x22: /* Add/subtract (immediate) */ | ||
122 | disas_add_sub_imm(s, insn); | ||
123 | break; | ||
124 | + case 0x23: /* Add/subtract (immediate, with tags) */ | ||
125 | + disas_add_sub_imm_with_tags(s, insn); | ||
126 | + break; | ||
127 | case 0x24: /* Logical (immediate) */ | ||
128 | disas_logic_imm(s, insn); | ||
129 | break; | ||
130 | -- | ||
131 | 2.20.1 | ||
132 | |||
133 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20200626033144.790098-13-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-a64.c | 15 +++++++++++++++ | ||
9 | 1 file changed, 15 insertions(+) | ||
10 | |||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-a64.c | ||
14 | +++ b/target/arm/translate-a64.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) | ||
16 | cpu_reg_sp(s, rn)); | ||
17 | } | ||
18 | break; | ||
19 | + case 5: /* GMI */ | ||
20 | + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { | ||
21 | + goto do_unallocated; | ||
22 | + } else { | ||
23 | + TCGv_i64 t1 = tcg_const_i64(1); | ||
24 | + TCGv_i64 t2 = tcg_temp_new_i64(); | ||
25 | + | ||
26 | + tcg_gen_extract_i64(t2, cpu_reg_sp(s, rn), 56, 4); | ||
27 | + tcg_gen_shl_i64(t1, t1, t2); | ||
28 | + tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t1); | ||
29 | + | ||
30 | + tcg_temp_free_i64(t1); | ||
31 | + tcg_temp_free_i64(t2); | ||
32 | + } | ||
33 | + break; | ||
34 | case 8: /* LSLV */ | ||
35 | handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); | ||
36 | break; | ||
37 | -- | ||
38 | 2.20.1 | ||
39 | |||
40 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20200626033144.790098-14-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-a64.c | 24 ++++++++++++++++++++++-- | ||
9 | 1 file changed, 22 insertions(+), 2 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-a64.c | ||
14 | +++ b/target/arm/translate-a64.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void handle_crc32(DisasContext *s, | ||
16 | */ | ||
17 | static void disas_data_proc_2src(DisasContext *s, uint32_t insn) | ||
18 | { | ||
19 | - unsigned int sf, rm, opcode, rn, rd; | ||
20 | + unsigned int sf, rm, opcode, rn, rd, setflag; | ||
21 | sf = extract32(insn, 31, 1); | ||
22 | + setflag = extract32(insn, 29, 1); | ||
23 | rm = extract32(insn, 16, 5); | ||
24 | opcode = extract32(insn, 10, 6); | ||
25 | rn = extract32(insn, 5, 5); | ||
26 | rd = extract32(insn, 0, 5); | ||
27 | |||
28 | - if (extract32(insn, 29, 1)) { | ||
29 | + if (setflag && opcode != 0) { | ||
30 | unallocated_encoding(s); | ||
31 | return; | ||
32 | } | ||
33 | |||
34 | switch (opcode) { | ||
35 | + case 0: /* SUBP(S) */ | ||
36 | + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { | ||
37 | + goto do_unallocated; | ||
38 | + } else { | ||
39 | + TCGv_i64 tcg_n, tcg_m, tcg_d; | ||
40 | + | ||
41 | + tcg_n = read_cpu_reg_sp(s, rn, true); | ||
42 | + tcg_m = read_cpu_reg_sp(s, rm, true); | ||
43 | + tcg_gen_sextract_i64(tcg_n, tcg_n, 0, 56); | ||
44 | + tcg_gen_sextract_i64(tcg_m, tcg_m, 0, 56); | ||
45 | + tcg_d = cpu_reg(s, rd); | ||
46 | + | ||
47 | + if (setflag) { | ||
48 | + gen_sub_CC(true, tcg_d, tcg_n, tcg_m); | ||
49 | + } else { | ||
50 | + tcg_gen_sub_i64(tcg_d, tcg_n, tcg_m); | ||
51 | + } | ||
52 | + } | ||
53 | + break; | ||
54 | case 2: /* UDIV */ | ||
55 | handle_div(s, false, sf, rm, rn, rd); | ||
56 | break; | ||
57 | -- | ||
58 | 2.20.1 | ||
59 | |||
60 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Use the same code as system mode, so that we generate the same | ||
4 | exception + syndrome for the unaligned access. | ||
5 | |||
6 | For the moment, if MTE is enabled so that this path is reachable, | ||
7 | this would generate a SIGSEGV in the user-only cpu_loop. Decoding | ||
8 | the syndrome to produce the proper SIGBUS will be done later. | ||
9 | |||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20200626033144.790098-15-richard.henderson@linaro.org | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | target/arm/cpu.c | 2 +- | ||
16 | target/arm/tlb_helper.c | 4 ++-- | ||
17 | 2 files changed, 3 insertions(+), 3 deletions(-) | ||
18 | |||
19 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/arm/cpu.c | ||
22 | +++ b/target/arm/cpu.c | ||
23 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) | ||
24 | cc->tlb_fill = arm_cpu_tlb_fill; | ||
25 | cc->debug_excp_handler = arm_debug_excp_handler; | ||
26 | cc->debug_check_watchpoint = arm_debug_check_watchpoint; | ||
27 | -#if !defined(CONFIG_USER_ONLY) | ||
28 | cc->do_unaligned_access = arm_cpu_do_unaligned_access; | ||
29 | +#if !defined(CONFIG_USER_ONLY) | ||
30 | cc->do_transaction_failed = arm_cpu_do_transaction_failed; | ||
31 | cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; | ||
32 | #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ | ||
33 | diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/tlb_helper.c | ||
36 | +++ b/target/arm/tlb_helper.c | ||
37 | @@ -XXX,XX +XXX,XX @@ | ||
38 | #include "internals.h" | ||
39 | #include "exec/exec-all.h" | ||
40 | |||
41 | -#if !defined(CONFIG_USER_ONLY) | ||
42 | - | ||
43 | static inline uint32_t merge_syn_data_abort(uint32_t template_syn, | ||
44 | unsigned int target_el, | ||
45 | bool same_el, bool ea, | ||
46 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, | ||
47 | arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); | ||
48 | } | ||
49 | |||
50 | +#if !defined(CONFIG_USER_ONLY) | ||
51 | + | ||
52 | /* | ||
53 | * arm_cpu_do_transaction_failed: handle a memory system error response | ||
54 | * (eg "no device/memory present at address") by raising an external abort | ||
55 | -- | ||
56 | 2.20.1 | ||
57 | |||
58 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20200626033144.790098-17-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-a64.c | 29 ++++++++++++++++++++++++++--- | ||
9 | 1 file changed, 26 insertions(+), 3 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-a64.c | ||
14 | +++ b/target/arm/translate-a64.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) | ||
16 | * +-----+-------+---+---+-------+---+-------+-------+------+------+ | ||
17 | * | ||
18 | * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit | ||
19 | - * LDPSW 01 | ||
20 | + * LDPSW/STGP 01 | ||
21 | * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit | ||
22 | * V: 0 -> GPR, 1 -> Vector | ||
23 | * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, | ||
24 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) | ||
25 | bool is_signed = false; | ||
26 | bool postindex = false; | ||
27 | bool wback = false; | ||
28 | + bool set_tag = false; | ||
29 | |||
30 | TCGv_i64 clean_addr, dirty_addr; | ||
31 | |||
32 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) | ||
33 | |||
34 | if (is_vector) { | ||
35 | size = 2 + opc; | ||
36 | + } else if (opc == 1 && !is_load) { | ||
37 | + /* STGP */ | ||
38 | + if (!dc_isar_feature(aa64_mte_insn_reg, s) || index == 0) { | ||
39 | + unallocated_encoding(s); | ||
40 | + return; | ||
41 | + } | ||
42 | + size = 3; | ||
43 | + set_tag = true; | ||
44 | } else { | ||
45 | size = 2 + extract32(opc, 1, 1); | ||
46 | is_signed = extract32(opc, 0, 1); | ||
47 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) | ||
48 | return; | ||
49 | } | ||
50 | |||
51 | - offset <<= size; | ||
52 | + offset <<= (set_tag ? LOG2_TAG_GRANULE : size); | ||
53 | |||
54 | if (rn == 31) { | ||
55 | gen_check_sp_alignment(s); | ||
56 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) | ||
57 | if (!postindex) { | ||
58 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | ||
59 | } | ||
60 | - clean_addr = clean_data_tbi(s, dirty_addr); | ||
61 | |||
62 | + if (set_tag) { | ||
63 | + if (!s->ata) { | ||
64 | + /* | ||
65 | + * TODO: We could rely on the stores below, at least for | ||
66 | + * system mode, if we arrange to add MO_ALIGN_16. | ||
67 | + */ | ||
68 | + gen_helper_stg_stub(cpu_env, dirty_addr); | ||
69 | + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { | ||
70 | + gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr); | ||
71 | + } else { | ||
72 | + gen_helper_stg(cpu_env, dirty_addr, dirty_addr); | ||
73 | + } | ||
74 | + } | ||
75 | + | ||
76 | + clean_addr = clean_data_tbi(s, dirty_addr); | ||
77 | if (is_vector) { | ||
78 | if (is_load) { | ||
79 | do_fp_ld(s, rt, clean_addr, size); | ||
80 | -- | ||
81 | 2.20.1 | ||
82 | |||
83 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | We can simplify our DC_ZVA if we recognize that the largest BS | ||
4 | that we actually use in system mode is 64. Let us just assert | ||
5 | that it fits within TARGET_PAGE_SIZE. | ||
6 | |||
7 | For DC_GVA and STZGM, we want to be able to write whole bytes | ||
8 | of tag memory, so assert that BS is >= 2 * TAG_GRANULE, or 32. | ||
9 | |||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20200626033144.790098-18-richard.henderson@linaro.org | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | target/arm/cpu.c | 24 ++++++++++++++++++++++++ | ||
16 | 1 file changed, 24 insertions(+) | ||
17 | |||
18 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/cpu.c | ||
21 | +++ b/target/arm/cpu.c | ||
22 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
23 | } | ||
24 | #endif | ||
25 | |||
26 | + if (tcg_enabled()) { | ||
27 | + int dcz_blocklen = 4 << cpu->dcz_blocksize; | ||
28 | + | ||
29 | + /* | ||
30 | + * We only support DCZ blocklen that fits on one page. | ||
31 | + * | ||
32 | + * Architectually this is always true. However TARGET_PAGE_SIZE | ||
33 | + * is variable and, for compatibility with -machine virt-2.7, | ||
34 | + * is only 1KiB, as an artifact of legacy ARMv5 subpage support. | ||
35 | + * But even then, while the largest architectural DCZ blocklen | ||
36 | + * is 2KiB, no cpu actually uses such a large blocklen. | ||
37 | + */ | ||
38 | + assert(dcz_blocklen <= TARGET_PAGE_SIZE); | ||
39 | + | ||
40 | + /* | ||
41 | + * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say | ||
42 | + * both nibbles of each byte storing tag data may be written at once. | ||
43 | + * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. | ||
44 | + */ | ||
45 | + if (cpu_isar_feature(aa64_mte, cpu)) { | ||
46 | + assert(dcz_blocklen >= 2 * TAG_GRANULE); | ||
47 | + } | ||
48 | + } | ||
49 | + | ||
50 | qemu_init_vcpu(cs); | ||
51 | cpu_reset(cs); | ||
52 | |||
53 | -- | ||
54 | 2.20.1 | ||
55 | |||
56 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Now that we know that the operation is on a single page, | ||
4 | we need not loop over pages while probing. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20200626033144.790098-19-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/helper-a64.c | 94 +++++++++++------------------------------ | ||
12 | 1 file changed, 25 insertions(+), 69 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/helper-a64.c | ||
17 | +++ b/target/arm/helper-a64.c | ||
18 | @@ -XXX,XX +XXX,XX @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) | ||
19 | * (which matches the usual QEMU behaviour of not implementing either | ||
20 | * alignment faults or any memory attribute handling). | ||
21 | */ | ||
22 | - | ||
23 | - ARMCPU *cpu = env_archcpu(env); | ||
24 | - uint64_t blocklen = 4 << cpu->dcz_blocksize; | ||
25 | + int blocklen = 4 << env_archcpu(env)->dcz_blocksize; | ||
26 | uint64_t vaddr = vaddr_in & ~(blocklen - 1); | ||
27 | + int mmu_idx = cpu_mmu_index(env, false); | ||
28 | + void *mem; | ||
29 | + | ||
30 | + /* | ||
31 | + * Trapless lookup. In addition to actual invalid page, may | ||
32 | + * return NULL for I/O, watchpoints, clean pages, etc. | ||
33 | + */ | ||
34 | + mem = tlb_vaddr_to_host(env, vaddr, MMU_DATA_STORE, mmu_idx); | ||
35 | |||
36 | #ifndef CONFIG_USER_ONLY | ||
37 | - { | ||
38 | + if (unlikely(!mem)) { | ||
39 | + uintptr_t ra = GETPC(); | ||
40 | + | ||
41 | /* | ||
42 | - * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than | ||
43 | - * the block size so we might have to do more than one TLB lookup. | ||
44 | - * We know that in fact for any v8 CPU the page size is at least 4K | ||
45 | - * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only | ||
46 | - * 1K as an artefact of legacy v5 subpage support being present in the | ||
47 | - * same QEMU executable. So in practice the hostaddr[] array has | ||
48 | - * two entries, given the current setting of TARGET_PAGE_BITS_MIN. | ||
49 | + * Trap if accessing an invalid page. DC_ZVA requires that we supply | ||
50 | + * the original pointer for an invalid page. But watchpoints require | ||
51 | + * that we probe the actual space. So do both. | ||
52 | */ | ||
53 | - int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); | ||
54 | - void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)]; | ||
55 | - int try, i; | ||
56 | - unsigned mmu_idx = cpu_mmu_index(env, false); | ||
57 | - TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); | ||
58 | + (void) probe_write(env, vaddr_in, 1, mmu_idx, ra); | ||
59 | + mem = probe_write(env, vaddr, blocklen, mmu_idx, ra); | ||
60 | |||
61 | - assert(maxidx <= ARRAY_SIZE(hostaddr)); | ||
62 | - | ||
63 | - for (try = 0; try < 2; try++) { | ||
64 | - | ||
65 | - for (i = 0; i < maxidx; i++) { | ||
66 | - hostaddr[i] = tlb_vaddr_to_host(env, | ||
67 | - vaddr + TARGET_PAGE_SIZE * i, | ||
68 | - 1, mmu_idx); | ||
69 | - if (!hostaddr[i]) { | ||
70 | - break; | ||
71 | - } | ||
72 | - } | ||
73 | - if (i == maxidx) { | ||
74 | - /* | ||
75 | - * If it's all in the TLB it's fair game for just writing to; | ||
76 | - * we know we don't need to update dirty status, etc. | ||
77 | - */ | ||
78 | - for (i = 0; i < maxidx - 1; i++) { | ||
79 | - memset(hostaddr[i], 0, TARGET_PAGE_SIZE); | ||
80 | - } | ||
81 | - memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); | ||
82 | - return; | ||
83 | - } | ||
84 | + if (unlikely(!mem)) { | ||
85 | /* | ||
86 | - * OK, try a store and see if we can populate the tlb. This | ||
87 | - * might cause an exception if the memory isn't writable, | ||
88 | - * in which case we will longjmp out of here. We must for | ||
89 | - * this purpose use the actual register value passed to us | ||
90 | - * so that we get the fault address right. | ||
91 | + * The only remaining reason for mem == NULL is I/O. | ||
92 | + * Just do a series of byte writes as the architecture demands. | ||
93 | */ | ||
94 | - helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC()); | ||
95 | - /* Now we can populate the other TLB entries, if any */ | ||
96 | - for (i = 0; i < maxidx; i++) { | ||
97 | - uint64_t va = vaddr + TARGET_PAGE_SIZE * i; | ||
98 | - if (va != (vaddr_in & TARGET_PAGE_MASK)) { | ||
99 | - helper_ret_stb_mmu(env, va, 0, oi, GETPC()); | ||
100 | - } | ||
101 | + for (int i = 0; i < blocklen; i++) { | ||
102 | + cpu_stb_mmuidx_ra(env, vaddr + i, 0, mmu_idx, ra); | ||
103 | } | ||
104 | - } | ||
105 | - | ||
106 | - /* | ||
107 | - * Slow path (probably attempt to do this to an I/O device or | ||
108 | - * similar, or clearing of a block of code we have translations | ||
109 | - * cached for). Just do a series of byte writes as the architecture | ||
110 | - * demands. It's not worth trying to use a cpu_physical_memory_map(), | ||
111 | - * memset(), unmap() sequence here because: | ||
112 | - * + we'd need to account for the blocksize being larger than a page | ||
113 | - * + the direct-RAM access case is almost always going to be dealt | ||
114 | - * with in the fastpath code above, so there's no speed benefit | ||
115 | - * + we would have to deal with the map returning NULL because the | ||
116 | - * bounce buffer was in use | ||
117 | - */ | ||
118 | - for (i = 0; i < blocklen; i++) { | ||
119 | - helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC()); | ||
120 | + return; | ||
121 | } | ||
122 | } | ||
123 | -#else | ||
124 | - memset(g2h(vaddr), 0, blocklen); | ||
125 | #endif | ||
126 | + | ||
127 | + memset(mem, 0, blocklen); | ||
128 | } | ||
129 | -- | ||
130 | 2.20.1 | ||
131 | |||
132 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Replace existing uses of check_data_tbi in translate-a64.c that | ||
4 | perform a single logical memory access. Leave the helper blank | ||
5 | for now to reduce the patch size. | ||
6 | |||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20200626033144.790098-24-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/helper-a64.h | 1 + | ||
13 | target/arm/internals.h | 8 +++ | ||
14 | target/arm/translate-a64.h | 2 + | ||
15 | target/arm/mte_helper.c | 8 +++ | ||
16 | target/arm/translate-a64.c | 100 ++++++++++++++++++++++++++++--------- | ||
17 | 5 files changed, 95 insertions(+), 24 deletions(-) | ||
18 | |||
19 | diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/arm/helper-a64.h | ||
22 | +++ b/target/arm/helper-a64.h | ||
23 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) | ||
24 | DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) | ||
25 | DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) | ||
26 | |||
27 | +DEF_HELPER_FLAGS_3(mte_check1, TCG_CALL_NO_WG, i64, env, i32, i64) | ||
28 | DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
29 | DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32) | ||
30 | DEF_HELPER_FLAGS_3(ldg, TCG_CALL_NO_WG, i64, env, i64, i64) | ||
31 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/target/arm/internals.h | ||
34 | +++ b/target/arm/internals.h | ||
35 | @@ -XXX,XX +XXX,XX @@ void arm_log_exception(int idx); | ||
36 | #define LOG2_TAG_GRANULE 4 | ||
37 | #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) | ||
38 | |||
39 | +/* Bits within a descriptor passed to the helper_mte_check* functions. */ | ||
40 | +FIELD(MTEDESC, MIDX, 0, 4) | ||
41 | +FIELD(MTEDESC, TBI, 4, 2) | ||
42 | +FIELD(MTEDESC, TCMA, 6, 2) | ||
43 | +FIELD(MTEDESC, WRITE, 8, 1) | ||
44 | +FIELD(MTEDESC, ESIZE, 9, 5) | ||
45 | +FIELD(MTEDESC, TSIZE, 14, 10) /* mte_checkN only */ | ||
46 | + | ||
47 | static inline int allocation_tag_from_addr(uint64_t ptr) | ||
48 | { | ||
49 | return extract64(ptr, 56, 4); | ||
50 | diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h | ||
51 | index XXXXXXX..XXXXXXX 100644 | ||
52 | --- a/target/arm/translate-a64.h | ||
53 | +++ b/target/arm/translate-a64.h | ||
54 | @@ -XXX,XX +XXX,XX @@ TCGv_ptr get_fpstatus_ptr(bool); | ||
55 | bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, | ||
56 | unsigned int imms, unsigned int immr); | ||
57 | bool sve_access_check(DisasContext *s); | ||
58 | +TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, | ||
59 | + bool tag_checked, int log2_size); | ||
60 | |||
61 | /* We should have at some point before trying to access an FP register | ||
62 | * done the necessary access check, so assert that | ||
63 | diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c | ||
64 | index XXXXXXX..XXXXXXX 100644 | ||
65 | --- a/target/arm/mte_helper.c | ||
66 | +++ b/target/arm/mte_helper.c | ||
67 | @@ -XXX,XX +XXX,XX @@ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val) | ||
68 | memset(mem, tag_pair, tag_bytes); | ||
69 | } | ||
70 | } | ||
71 | + | ||
72 | +/* | ||
73 | + * Perform an MTE checked access for a single logical or atomic access. | ||
74 | + */ | ||
75 | +uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr) | ||
76 | +{ | ||
77 | + return ptr; | ||
78 | +} | ||
79 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
80 | index XXXXXXX..XXXXXXX 100644 | ||
81 | --- a/target/arm/translate-a64.c | ||
82 | +++ b/target/arm/translate-a64.c | ||
83 | @@ -XXX,XX +XXX,XX @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) | ||
84 | } | ||
85 | |||
86 | /* | ||
87 | - * Return a "clean" address for ADDR according to TBID. | ||
88 | - * This is always a fresh temporary, as we need to be able to | ||
89 | - * increment this independently of a dirty write-back address. | ||
90 | + * Handle MTE and/or TBI. | ||
91 | + * | ||
92 | + * For TBI, ideally, we would do nothing. Proper behaviour on fault is | ||
93 | + * for the tag to be present in the FAR_ELx register. But for user-only | ||
94 | + * mode we do not have a TLB with which to implement this, so we must | ||
95 | + * remove the top byte now. | ||
96 | + * | ||
97 | + * Always return a fresh temporary that we can increment independently | ||
98 | + * of the write-back address. | ||
99 | */ | ||
100 | + | ||
101 | static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) | ||
102 | { | ||
103 | TCGv_i64 clean = new_tmp_a64(s); | ||
104 | - /* | ||
105 | - * In order to get the correct value in the FAR_ELx register, | ||
106 | - * we must present the memory subsystem with the "dirty" address | ||
107 | - * including the TBI. In system mode we can make this work via | ||
108 | - * the TLB, dropping the TBI during translation. But for user-only | ||
109 | - * mode we don't have that option, and must remove the top byte now. | ||
110 | - */ | ||
111 | #ifdef CONFIG_USER_ONLY | ||
112 | gen_top_byte_ignore(s, clean, addr, s->tbid); | ||
113 | #else | ||
114 | @@ -XXX,XX +XXX,XX @@ static void gen_probe_access(DisasContext *s, TCGv_i64 ptr, | ||
115 | tcg_temp_free_i32(t_size); | ||
116 | } | ||
117 | |||
118 | +/* | ||
119 | + * For MTE, check a single logical or atomic access. This probes a single | ||
120 | + * address, the exact one specified. The size and alignment of the access | ||
121 | + * is not relevant to MTE, per se, but watchpoints do require the size, | ||
122 | + * and we want to recognize those before making any other changes to state. | ||
123 | + */ | ||
124 | +static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr, | ||
125 | + bool is_write, bool tag_checked, | ||
126 | + int log2_size, bool is_unpriv, | ||
127 | + int core_idx) | ||
128 | +{ | ||
129 | + if (tag_checked && s->mte_active[is_unpriv]) { | ||
130 | + TCGv_i32 tcg_desc; | ||
131 | + TCGv_i64 ret; | ||
132 | + int desc = 0; | ||
133 | + | ||
134 | + desc = FIELD_DP32(desc, MTEDESC, MIDX, core_idx); | ||
135 | + desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | ||
136 | + desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | ||
137 | + desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | ||
138 | + desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << log2_size); | ||
139 | + tcg_desc = tcg_const_i32(desc); | ||
140 | + | ||
141 | + ret = new_tmp_a64(s); | ||
142 | + gen_helper_mte_check1(ret, cpu_env, tcg_desc, addr); | ||
143 | + tcg_temp_free_i32(tcg_desc); | ||
144 | + | ||
145 | + return ret; | ||
146 | + } | ||
147 | + return clean_data_tbi(s, addr); | ||
148 | +} | ||
149 | + | ||
150 | +TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, | ||
151 | + bool tag_checked, int log2_size) | ||
152 | +{ | ||
153 | + return gen_mte_check1_mmuidx(s, addr, is_write, tag_checked, log2_size, | ||
154 | + false, get_mem_index(s)); | ||
155 | +} | ||
156 | + | ||
157 | typedef struct DisasCompare64 { | ||
158 | TCGCond cond; | ||
159 | TCGv_i64 value; | ||
160 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap(DisasContext *s, int rs, int rt, | ||
161 | if (rn == 31) { | ||
162 | gen_check_sp_alignment(s); | ||
163 | } | ||
164 | - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
165 | + clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, size); | ||
166 | tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, | ||
167 | size | MO_ALIGN | s->be_data); | ||
168 | } | ||
169 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | ||
170 | if (rn == 31) { | ||
171 | gen_check_sp_alignment(s); | ||
172 | } | ||
173 | - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
174 | + | ||
175 | + /* This is a single atomic access, despite the "pair". */ | ||
176 | + clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, size + 1); | ||
177 | |||
178 | if (size == 2) { | ||
179 | TCGv_i64 cmp = tcg_temp_new_i64(); | ||
180 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
181 | if (is_lasr) { | ||
182 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | ||
183 | } | ||
184 | - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
185 | + clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), | ||
186 | + true, rn != 31, size); | ||
187 | gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); | ||
188 | return; | ||
189 | |||
190 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
191 | if (rn == 31) { | ||
192 | gen_check_sp_alignment(s); | ||
193 | } | ||
194 | - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
195 | + clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), | ||
196 | + false, rn != 31, size); | ||
197 | s->is_ldex = true; | ||
198 | gen_load_exclusive(s, rt, rt2, clean_addr, size, false); | ||
199 | if (is_lasr) { | ||
200 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
201 | gen_check_sp_alignment(s); | ||
202 | } | ||
203 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | ||
204 | - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
205 | + clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), | ||
206 | + true, rn != 31, size); | ||
207 | do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, | ||
208 | disas_ldst_compute_iss_sf(size, false, 0), is_lasr); | ||
209 | return; | ||
210 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
211 | if (rn == 31) { | ||
212 | gen_check_sp_alignment(s); | ||
213 | } | ||
214 | - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
215 | + clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), | ||
216 | + false, rn != 31, size); | ||
217 | do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt, | ||
218 | disas_ldst_compute_iss_sf(size, false, 0), is_lasr); | ||
219 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | ||
220 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
221 | if (is_lasr) { | ||
222 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | ||
223 | } | ||
224 | - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
225 | + clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), | ||
226 | + true, rn != 31, size); | ||
227 | gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); | ||
228 | return; | ||
229 | } | ||
230 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
231 | if (rn == 31) { | ||
232 | gen_check_sp_alignment(s); | ||
233 | } | ||
234 | - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
235 | + clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), | ||
236 | + false, rn != 31, size); | ||
237 | s->is_ldex = true; | ||
238 | gen_load_exclusive(s, rt, rt2, clean_addr, size, true); | ||
239 | if (is_lasr) { | ||
240 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, | ||
241 | bool iss_valid = !is_vector; | ||
242 | bool post_index; | ||
243 | bool writeback; | ||
244 | + int memidx; | ||
245 | |||
246 | TCGv_i64 clean_addr, dirty_addr; | ||
247 | |||
248 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, | ||
249 | if (!post_index) { | ||
250 | tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); | ||
251 | } | ||
252 | - clean_addr = clean_data_tbi(s, dirty_addr); | ||
253 | + | ||
254 | + memidx = is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); | ||
255 | + clean_addr = gen_mte_check1_mmuidx(s, dirty_addr, is_store, | ||
256 | + writeback || rn != 31, | ||
257 | + size, is_unpriv, memidx); | ||
258 | |||
259 | if (is_vector) { | ||
260 | if (is_store) { | ||
261 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, | ||
262 | } | ||
263 | } else { | ||
264 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | ||
265 | - int memidx = is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); | ||
266 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); | ||
267 | |||
268 | if (is_store) { | ||
269 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, | ||
270 | ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); | ||
271 | |||
272 | tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); | ||
273 | - clean_addr = clean_data_tbi(s, dirty_addr); | ||
274 | + clean_addr = gen_mte_check1(s, dirty_addr, is_store, true, size); | ||
275 | |||
276 | if (is_vector) { | ||
277 | if (is_store) { | ||
278 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, | ||
279 | dirty_addr = read_cpu_reg_sp(s, rn, 1); | ||
280 | offset = imm12 << size; | ||
281 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | ||
282 | - clean_addr = clean_data_tbi(s, dirty_addr); | ||
283 | + clean_addr = gen_mte_check1(s, dirty_addr, is_store, rn != 31, size); | ||
284 | |||
285 | if (is_vector) { | ||
286 | if (is_store) { | ||
287 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | ||
288 | if (rn == 31) { | ||
289 | gen_check_sp_alignment(s); | ||
290 | } | ||
291 | - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
292 | + clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn != 31, size); | ||
293 | |||
294 | if (o3_opc == 014) { | ||
295 | /* | ||
296 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, | ||
297 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | ||
298 | |||
299 | /* Note that "clean" and "dirty" here refer to TBI not PAC. */ | ||
300 | - clean_addr = clean_data_tbi(s, dirty_addr); | ||
301 | + clean_addr = gen_mte_check1(s, dirty_addr, false, | ||
302 | + is_wback || rn != 31, size); | ||
303 | |||
304 | tcg_rt = cpu_reg(s, rt); | ||
305 | do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, | ||
306 | -- | ||
307 | 2.20.1 | ||
308 | |||
309 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Replace existing uses of check_data_tbi in translate-a64.c that | ||
4 | perform multiple logical memory access. Leave the helper blank | ||
5 | for now to reduce the patch size. | ||
6 | |||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20200626033144.790098-25-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/helper-a64.h | 1 + | ||
13 | target/arm/translate-a64.h | 2 ++ | ||
14 | target/arm/mte_helper.c | 8 +++++ | ||
15 | target/arm/translate-a64.c | 71 +++++++++++++++++++++++++++++--------- | ||
16 | 4 files changed, 66 insertions(+), 16 deletions(-) | ||
17 | |||
18 | diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/helper-a64.h | ||
21 | +++ b/target/arm/helper-a64.h | ||
22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) | ||
23 | DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) | ||
24 | |||
25 | DEF_HELPER_FLAGS_3(mte_check1, TCG_CALL_NO_WG, i64, env, i32, i64) | ||
26 | +DEF_HELPER_FLAGS_3(mte_checkN, TCG_CALL_NO_WG, i64, env, i32, i64) | ||
27 | DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
28 | DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32) | ||
29 | DEF_HELPER_FLAGS_3(ldg, TCG_CALL_NO_WG, i64, env, i64, i64) | ||
30 | diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/translate-a64.h | ||
33 | +++ b/target/arm/translate-a64.h | ||
34 | @@ -XXX,XX +XXX,XX @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, | ||
35 | bool sve_access_check(DisasContext *s); | ||
36 | TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, | ||
37 | bool tag_checked, int log2_size); | ||
38 | +TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, | ||
39 | + bool tag_checked, int count, int log2_esize); | ||
40 | |||
41 | /* We should have at some point before trying to access an FP register | ||
42 | * done the necessary access check, so assert that | ||
43 | diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/target/arm/mte_helper.c | ||
46 | +++ b/target/arm/mte_helper.c | ||
47 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr) | ||
48 | { | ||
49 | return ptr; | ||
50 | } | ||
51 | + | ||
52 | +/* | ||
53 | + * Perform an MTE checked access for multiple logical accesses. | ||
54 | + */ | ||
55 | +uint64_t HELPER(mte_checkN)(CPUARMState *env, uint32_t desc, uint64_t ptr) | ||
56 | +{ | ||
57 | + return ptr; | ||
58 | +} | ||
59 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
60 | index XXXXXXX..XXXXXXX 100644 | ||
61 | --- a/target/arm/translate-a64.c | ||
62 | +++ b/target/arm/translate-a64.c | ||
63 | @@ -XXX,XX +XXX,XX @@ TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, | ||
64 | false, get_mem_index(s)); | ||
65 | } | ||
66 | |||
67 | +/* | ||
68 | + * For MTE, check multiple logical sequential accesses. | ||
69 | + */ | ||
70 | +TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, | ||
71 | + bool tag_checked, int log2_esize, int total_size) | ||
72 | +{ | ||
73 | + if (tag_checked && s->mte_active[0] && total_size != (1 << log2_esize)) { | ||
74 | + TCGv_i32 tcg_desc; | ||
75 | + TCGv_i64 ret; | ||
76 | + int desc = 0; | ||
77 | + | ||
78 | + desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | ||
79 | + desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | ||
80 | + desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | ||
81 | + desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | ||
82 | + desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << log2_esize); | ||
83 | + desc = FIELD_DP32(desc, MTEDESC, TSIZE, total_size); | ||
84 | + tcg_desc = tcg_const_i32(desc); | ||
85 | + | ||
86 | + ret = new_tmp_a64(s); | ||
87 | + gen_helper_mte_checkN(ret, cpu_env, tcg_desc, addr); | ||
88 | + tcg_temp_free_i32(tcg_desc); | ||
89 | + | ||
90 | + return ret; | ||
91 | + } | ||
92 | + return gen_mte_check1(s, addr, is_write, tag_checked, log2_esize); | ||
93 | +} | ||
94 | + | ||
95 | typedef struct DisasCompare64 { | ||
96 | TCGCond cond; | ||
97 | TCGv_i64 value; | ||
98 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) | ||
99 | } | ||
100 | } | ||
101 | |||
102 | - clean_addr = clean_data_tbi(s, dirty_addr); | ||
103 | + clean_addr = gen_mte_checkN(s, dirty_addr, !is_load, | ||
104 | + (wback || rn != 31) && !set_tag, | ||
105 | + size, 2 << size); | ||
106 | + | ||
107 | if (is_vector) { | ||
108 | if (is_load) { | ||
109 | do_fp_ld(s, rt, clean_addr, size); | ||
110 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) | ||
111 | TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; | ||
112 | MemOp endian = s->be_data; | ||
113 | |||
114 | - int ebytes; /* bytes per element */ | ||
115 | + int total; /* total bytes */ | ||
116 | int elements; /* elements per vector */ | ||
117 | int rpt; /* num iterations */ | ||
118 | int selem; /* structure elements */ | ||
119 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) | ||
120 | endian = MO_LE; | ||
121 | } | ||
122 | |||
123 | - /* Consecutive little-endian elements from a single register | ||
124 | + total = rpt * selem * (is_q ? 16 : 8); | ||
125 | + tcg_rn = cpu_reg_sp(s, rn); | ||
126 | + | ||
127 | + /* | ||
128 | + * Issue the MTE check vs the logical repeat count, before we | ||
129 | + * promote consecutive little-endian elements below. | ||
130 | + */ | ||
131 | + clean_addr = gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != 31, | ||
132 | + size, total); | ||
133 | + | ||
134 | + /* | ||
135 | + * Consecutive little-endian elements from a single register | ||
136 | * can be promoted to a larger little-endian operation. | ||
137 | */ | ||
138 | if (selem == 1 && endian == MO_LE) { | ||
139 | size = 3; | ||
140 | } | ||
141 | - ebytes = 1 << size; | ||
142 | - elements = (is_q ? 16 : 8) / ebytes; | ||
143 | - | ||
144 | - tcg_rn = cpu_reg_sp(s, rn); | ||
145 | - clean_addr = clean_data_tbi(s, tcg_rn); | ||
146 | - tcg_ebytes = tcg_const_i64(ebytes); | ||
147 | + elements = (is_q ? 16 : 8) >> size; | ||
148 | |||
149 | + tcg_ebytes = tcg_const_i64(1 << size); | ||
150 | for (r = 0; r < rpt; r++) { | ||
151 | int e; | ||
152 | for (e = 0; e < elements; e++) { | ||
153 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) | ||
154 | |||
155 | if (is_postidx) { | ||
156 | if (rm == 31) { | ||
157 | - tcg_gen_addi_i64(tcg_rn, tcg_rn, rpt * elements * selem * ebytes); | ||
158 | + tcg_gen_addi_i64(tcg_rn, tcg_rn, total); | ||
159 | } else { | ||
160 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | ||
161 | } | ||
162 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) | ||
163 | int selem = (extract32(opc, 0, 1) << 1 | R) + 1; | ||
164 | bool replicate = false; | ||
165 | int index = is_q << 3 | S << 2 | size; | ||
166 | - int ebytes, xs; | ||
167 | + int xs, total; | ||
168 | TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; | ||
169 | |||
170 | if (extract32(insn, 31, 1)) { | ||
171 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) | ||
172 | return; | ||
173 | } | ||
174 | |||
175 | - ebytes = 1 << scale; | ||
176 | - | ||
177 | if (rn == 31) { | ||
178 | gen_check_sp_alignment(s); | ||
179 | } | ||
180 | |||
181 | + total = selem << scale; | ||
182 | tcg_rn = cpu_reg_sp(s, rn); | ||
183 | - clean_addr = clean_data_tbi(s, tcg_rn); | ||
184 | - tcg_ebytes = tcg_const_i64(ebytes); | ||
185 | |||
186 | + clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31, | ||
187 | + scale, total); | ||
188 | + | ||
189 | + tcg_ebytes = tcg_const_i64(1 << scale); | ||
190 | for (xs = 0; xs < selem; xs++) { | ||
191 | if (replicate) { | ||
192 | /* Load and replicate to all elements */ | ||
193 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) | ||
194 | |||
195 | if (is_postidx) { | ||
196 | if (rm == 31) { | ||
197 | - tcg_gen_addi_i64(tcg_rn, tcg_rn, selem * ebytes); | ||
198 | + tcg_gen_addi_i64(tcg_rn, tcg_rn, total); | ||
199 | } else { | ||
200 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | ||
201 | } | ||
202 | -- | ||
203 | 2.20.1 | ||
204 | |||
205 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Fill out the stub that was added earlier. | ||
4 | |||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20200626033144.790098-26-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/internals.h | 48 +++++++++++++++ | ||
11 | target/arm/mte_helper.c | 132 +++++++++++++++++++++++++++++++++++++++- | ||
12 | 2 files changed, 179 insertions(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/internals.h | ||
17 | +++ b/target/arm/internals.h | ||
18 | @@ -XXX,XX +XXX,XX @@ FIELD(MTEDESC, WRITE, 8, 1) | ||
19 | FIELD(MTEDESC, ESIZE, 9, 5) | ||
20 | FIELD(MTEDESC, TSIZE, 14, 10) /* mte_checkN only */ | ||
21 | |||
22 | +bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr); | ||
23 | +uint64_t mte_check1(CPUARMState *env, uint32_t desc, | ||
24 | + uint64_t ptr, uintptr_t ra); | ||
25 | + | ||
26 | static inline int allocation_tag_from_addr(uint64_t ptr) | ||
27 | { | ||
28 | return extract64(ptr, 56, 4); | ||
29 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) | ||
30 | return deposit64(ptr, 56, 4, rtag); | ||
31 | } | ||
32 | |||
33 | +/* Return true if tbi bits mean that the access is checked. */ | ||
34 | +static inline bool tbi_check(uint32_t desc, int bit55) | ||
35 | +{ | ||
36 | + return (desc >> (R_MTEDESC_TBI_SHIFT + bit55)) & 1; | ||
37 | +} | ||
38 | + | ||
39 | +/* Return true if tcma bits mean that the access is unchecked. */ | ||
40 | +static inline bool tcma_check(uint32_t desc, int bit55, int ptr_tag) | ||
41 | +{ | ||
42 | + /* | ||
43 | + * We had extracted bit55 and ptr_tag for other reasons, so fold | ||
44 | + * (ptr<59:55> == 00000 || ptr<59:55> == 11111) into a single test. | ||
45 | + */ | ||
46 | + bool match = ((ptr_tag + bit55) & 0xf) == 0; | ||
47 | + bool tcma = (desc >> (R_MTEDESC_TCMA_SHIFT + bit55)) & 1; | ||
48 | + return tcma && match; | ||
49 | +} | ||
50 | + | ||
51 | +/* | ||
52 | + * For TBI, ideally, we would do nothing. Proper behaviour on fault is | ||
53 | + * for the tag to be present in the FAR_ELx register. But for user-only | ||
54 | + * mode, we do not have a TLB with which to implement this, so we must | ||
55 | + * remove the top byte. | ||
56 | + */ | ||
57 | +static inline uint64_t useronly_clean_ptr(uint64_t ptr) | ||
58 | +{ | ||
59 | + /* TBI is known to be enabled. */ | ||
60 | +#ifdef CONFIG_USER_ONLY | ||
61 | + ptr = sextract64(ptr, 0, 56); | ||
62 | +#endif | ||
63 | + return ptr; | ||
64 | +} | ||
65 | + | ||
66 | +static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc, uint64_t ptr) | ||
67 | +{ | ||
68 | +#ifdef CONFIG_USER_ONLY | ||
69 | + int64_t clean_ptr = sextract64(ptr, 0, 56); | ||
70 | + if (tbi_check(desc, clean_ptr < 0)) { | ||
71 | + ptr = clean_ptr; | ||
72 | + } | ||
73 | +#endif | ||
74 | + return ptr; | ||
75 | +} | ||
76 | + | ||
77 | #endif | ||
78 | diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c | ||
79 | index XXXXXXX..XXXXXXX 100644 | ||
80 | --- a/target/arm/mte_helper.c | ||
81 | +++ b/target/arm/mte_helper.c | ||
82 | @@ -XXX,XX +XXX,XX @@ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val) | ||
83 | } | ||
84 | } | ||
85 | |||
86 | +/* Record a tag check failure. */ | ||
87 | +static void mte_check_fail(CPUARMState *env, int mmu_idx, | ||
88 | + uint64_t dirty_ptr, uintptr_t ra) | ||
89 | +{ | ||
90 | + ARMMMUIdx arm_mmu_idx = core_to_aa64_mmu_idx(mmu_idx); | ||
91 | + int el, reg_el, tcf, select; | ||
92 | + uint64_t sctlr; | ||
93 | + | ||
94 | + reg_el = regime_el(env, arm_mmu_idx); | ||
95 | + sctlr = env->cp15.sctlr_el[reg_el]; | ||
96 | + | ||
97 | + switch (arm_mmu_idx) { | ||
98 | + case ARMMMUIdx_E10_0: | ||
99 | + case ARMMMUIdx_E20_0: | ||
100 | + el = 0; | ||
101 | + tcf = extract64(sctlr, 38, 2); | ||
102 | + break; | ||
103 | + default: | ||
104 | + el = reg_el; | ||
105 | + tcf = extract64(sctlr, 40, 2); | ||
106 | + } | ||
107 | + | ||
108 | + switch (tcf) { | ||
109 | + case 1: | ||
110 | + /* | ||
111 | + * Tag check fail causes a synchronous exception. | ||
112 | + * | ||
113 | + * In restore_state_to_opc, we set the exception syndrome | ||
114 | + * for the load or store operation. Unwind first so we | ||
115 | + * may overwrite that with the syndrome for the tag check. | ||
116 | + */ | ||
117 | + cpu_restore_state(env_cpu(env), ra, true); | ||
118 | + env->exception.vaddress = dirty_ptr; | ||
119 | + raise_exception(env, EXCP_DATA_ABORT, | ||
120 | + syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, 0, 0x11), | ||
121 | + exception_target_el(env)); | ||
122 | + /* noreturn, but fall through to the assert anyway */ | ||
123 | + | ||
124 | + case 0: | ||
125 | + /* | ||
126 | + * Tag check fail does not affect the PE. | ||
127 | + * We eliminate this case by not setting MTE_ACTIVE | ||
128 | + * in tb_flags, so that we never make this runtime call. | ||
129 | + */ | ||
130 | + g_assert_not_reached(); | ||
131 | + | ||
132 | + case 2: | ||
133 | + /* Tag check fail causes asynchronous flag set. */ | ||
134 | + mmu_idx = arm_mmu_idx_el(env, el); | ||
135 | + if (regime_has_2_ranges(mmu_idx)) { | ||
136 | + select = extract64(dirty_ptr, 55, 1); | ||
137 | + } else { | ||
138 | + select = 0; | ||
139 | + } | ||
140 | + env->cp15.tfsr_el[el] |= 1 << select; | ||
141 | + break; | ||
142 | + | ||
143 | + default: | ||
144 | + /* Case 3: Reserved. */ | ||
145 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
146 | + "Tag check failure with SCTLR_EL%d.TCF%s " | ||
147 | + "set to reserved value %d\n", | ||
148 | + reg_el, el ? "" : "0", tcf); | ||
149 | + break; | ||
150 | + } | ||
151 | +} | ||
152 | + | ||
153 | /* | ||
154 | * Perform an MTE checked access for a single logical or atomic access. | ||
155 | */ | ||
156 | +static bool mte_probe1_int(CPUARMState *env, uint32_t desc, uint64_t ptr, | ||
157 | + uintptr_t ra, int bit55) | ||
158 | +{ | ||
159 | + int mem_tag, mmu_idx, ptr_tag, size; | ||
160 | + MMUAccessType type; | ||
161 | + uint8_t *mem; | ||
162 | + | ||
163 | + ptr_tag = allocation_tag_from_addr(ptr); | ||
164 | + | ||
165 | + if (tcma_check(desc, bit55, ptr_tag)) { | ||
166 | + return true; | ||
167 | + } | ||
168 | + | ||
169 | + mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); | ||
170 | + type = FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_LOAD; | ||
171 | + size = FIELD_EX32(desc, MTEDESC, ESIZE); | ||
172 | + | ||
173 | + mem = allocation_tag_mem(env, mmu_idx, ptr, type, size, | ||
174 | + MMU_DATA_LOAD, 1, ra); | ||
175 | + if (!mem) { | ||
176 | + return true; | ||
177 | + } | ||
178 | + | ||
179 | + mem_tag = load_tag1(ptr, mem); | ||
180 | + return ptr_tag == mem_tag; | ||
181 | +} | ||
182 | + | ||
183 | +/* | ||
184 | + * No-fault version of mte_check1, to be used by SVE for MemSingleNF. | ||
185 | + * Returns false if the access is Checked and the check failed. This | ||
186 | + * is only intended to probe the tag -- the validity of the page must | ||
187 | + * be checked beforehand. | ||
188 | + */ | ||
189 | +bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr) | ||
190 | +{ | ||
191 | + int bit55 = extract64(ptr, 55, 1); | ||
192 | + | ||
193 | + /* If TBI is disabled, the access is unchecked. */ | ||
194 | + if (unlikely(!tbi_check(desc, bit55))) { | ||
195 | + return true; | ||
196 | + } | ||
197 | + | ||
198 | + return mte_probe1_int(env, desc, ptr, 0, bit55); | ||
199 | +} | ||
200 | + | ||
201 | +uint64_t mte_check1(CPUARMState *env, uint32_t desc, | ||
202 | + uint64_t ptr, uintptr_t ra) | ||
203 | +{ | ||
204 | + int bit55 = extract64(ptr, 55, 1); | ||
205 | + | ||
206 | + /* If TBI is disabled, the access is unchecked, and ptr is not dirty. */ | ||
207 | + if (unlikely(!tbi_check(desc, bit55))) { | ||
208 | + return ptr; | ||
209 | + } | ||
210 | + | ||
211 | + if (unlikely(!mte_probe1_int(env, desc, ptr, ra, bit55))) { | ||
212 | + int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); | ||
213 | + mte_check_fail(env, mmu_idx, ptr, ra); | ||
214 | + } | ||
215 | + | ||
216 | + return useronly_clean_ptr(ptr); | ||
217 | +} | ||
218 | + | ||
219 | uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr) | ||
220 | { | ||
221 | - return ptr; | ||
222 | + return mte_check1(env, desc, ptr, GETPC()); | ||
223 | } | ||
224 | |||
225 | /* | ||
226 | -- | ||
227 | 2.20.1 | ||
228 | |||
229 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Fill out the stub that was added earlier. | ||
4 | |||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20200626033144.790098-27-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/internals.h | 2 + | ||
11 | target/arm/mte_helper.c | 165 +++++++++++++++++++++++++++++++++++++++- | ||
12 | 2 files changed, 166 insertions(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/internals.h | ||
17 | +++ b/target/arm/internals.h | ||
18 | @@ -XXX,XX +XXX,XX @@ FIELD(MTEDESC, TSIZE, 14, 10) /* mte_checkN only */ | ||
19 | bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr); | ||
20 | uint64_t mte_check1(CPUARMState *env, uint32_t desc, | ||
21 | uint64_t ptr, uintptr_t ra); | ||
22 | +uint64_t mte_checkN(CPUARMState *env, uint32_t desc, | ||
23 | + uint64_t ptr, uintptr_t ra); | ||
24 | |||
25 | static inline int allocation_tag_from_addr(uint64_t ptr) | ||
26 | { | ||
27 | diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/mte_helper.c | ||
30 | +++ b/target/arm/mte_helper.c | ||
31 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr) | ||
32 | /* | ||
33 | * Perform an MTE checked access for multiple logical accesses. | ||
34 | */ | ||
35 | + | ||
36 | +/** | ||
37 | + * checkN: | ||
38 | + * @tag: tag memory to test | ||
39 | + * @odd: true to begin testing at tags at odd nibble | ||
40 | + * @cmp: the tag to compare against | ||
41 | + * @count: number of tags to test | ||
42 | + * | ||
43 | + * Return the number of successful tests. | ||
44 | + * Thus a return value < @count indicates a failure. | ||
45 | + * | ||
46 | + * A note about sizes: count is expected to be small. | ||
47 | + * | ||
48 | + * The most common use will be LDP/STP of two integer registers, | ||
49 | + * which means 16 bytes of memory touching at most 2 tags, but | ||
50 | + * often the access is aligned and thus just 1 tag. | ||
51 | + * | ||
52 | + * Using AdvSIMD LD/ST (multiple), one can access 64 bytes of memory, | ||
53 | + * touching at most 5 tags. SVE LDR/STR (vector) with the default | ||
54 | + * vector length is also 64 bytes; the maximum architectural length | ||
55 | + * is 256 bytes touching at most 9 tags. | ||
56 | + * | ||
57 | + * The loop below uses 7 logical operations and 1 memory operation | ||
58 | + * per tag pair. An implementation that loads an aligned word and | ||
59 | + * uses masking to ignore adjacent tags requires 18 logical operations | ||
60 | + * and thus does not begin to pay off until 6 tags. | ||
61 | + * Which, according to the survey above, is unlikely to be common. | ||
62 | + */ | ||
63 | +static int checkN(uint8_t *mem, int odd, int cmp, int count) | ||
64 | +{ | ||
65 | + int n = 0, diff; | ||
66 | + | ||
67 | + /* Replicate the test tag and compare. */ | ||
68 | + cmp *= 0x11; | ||
69 | + diff = *mem++ ^ cmp; | ||
70 | + | ||
71 | + if (odd) { | ||
72 | + goto start_odd; | ||
73 | + } | ||
74 | + | ||
75 | + while (1) { | ||
76 | + /* Test even tag. */ | ||
77 | + if (unlikely((diff) & 0x0f)) { | ||
78 | + break; | ||
79 | + } | ||
80 | + if (++n == count) { | ||
81 | + break; | ||
82 | + } | ||
83 | + | ||
84 | + start_odd: | ||
85 | + /* Test odd tag. */ | ||
86 | + if (unlikely((diff) & 0xf0)) { | ||
87 | + break; | ||
88 | + } | ||
89 | + if (++n == count) { | ||
90 | + break; | ||
91 | + } | ||
92 | + | ||
93 | + diff = *mem++ ^ cmp; | ||
94 | + } | ||
95 | + return n; | ||
96 | +} | ||
97 | + | ||
98 | +uint64_t mte_checkN(CPUARMState *env, uint32_t desc, | ||
99 | + uint64_t ptr, uintptr_t ra) | ||
100 | +{ | ||
101 | + int mmu_idx, ptr_tag, bit55; | ||
102 | + uint64_t ptr_last, ptr_end, prev_page, next_page; | ||
103 | + uint64_t tag_first, tag_end; | ||
104 | + uint64_t tag_byte_first, tag_byte_end; | ||
105 | + uint32_t esize, total, tag_count, tag_size, n, c; | ||
106 | + uint8_t *mem1, *mem2; | ||
107 | + MMUAccessType type; | ||
108 | + | ||
109 | + bit55 = extract64(ptr, 55, 1); | ||
110 | + | ||
111 | + /* If TBI is disabled, the access is unchecked, and ptr is not dirty. */ | ||
112 | + if (unlikely(!tbi_check(desc, bit55))) { | ||
113 | + return ptr; | ||
114 | + } | ||
115 | + | ||
116 | + ptr_tag = allocation_tag_from_addr(ptr); | ||
117 | + | ||
118 | + if (tcma_check(desc, bit55, ptr_tag)) { | ||
119 | + goto done; | ||
120 | + } | ||
121 | + | ||
122 | + mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); | ||
123 | + type = FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_LOAD; | ||
124 | + esize = FIELD_EX32(desc, MTEDESC, ESIZE); | ||
125 | + total = FIELD_EX32(desc, MTEDESC, TSIZE); | ||
126 | + | ||
127 | + /* Find the addr of the end of the access, and of the last element. */ | ||
128 | + ptr_end = ptr + total; | ||
129 | + ptr_last = ptr_end - esize; | ||
130 | + | ||
131 | + /* Round the bounds to the tag granule, and compute the number of tags. */ | ||
132 | + tag_first = QEMU_ALIGN_DOWN(ptr, TAG_GRANULE); | ||
133 | + tag_end = QEMU_ALIGN_UP(ptr_last, TAG_GRANULE); | ||
134 | + tag_count = (tag_end - tag_first) / TAG_GRANULE; | ||
135 | + | ||
136 | + /* Round the bounds to twice the tag granule, and compute the bytes. */ | ||
137 | + tag_byte_first = QEMU_ALIGN_DOWN(ptr, 2 * TAG_GRANULE); | ||
138 | + tag_byte_end = QEMU_ALIGN_UP(ptr_last, 2 * TAG_GRANULE); | ||
139 | + | ||
140 | + /* Locate the page boundaries. */ | ||
141 | + prev_page = ptr & TARGET_PAGE_MASK; | ||
142 | + next_page = prev_page + TARGET_PAGE_SIZE; | ||
143 | + | ||
144 | + if (likely(tag_end - prev_page <= TARGET_PAGE_SIZE)) { | ||
145 | + /* Memory access stays on one page. */ | ||
146 | + tag_size = (tag_byte_end - tag_byte_first) / (2 * TAG_GRANULE); | ||
147 | + mem1 = allocation_tag_mem(env, mmu_idx, ptr, type, total, | ||
148 | + MMU_DATA_LOAD, tag_size, ra); | ||
149 | + if (!mem1) { | ||
150 | + goto done; | ||
151 | + } | ||
152 | + /* Perform all of the comparisons. */ | ||
153 | + n = checkN(mem1, ptr & TAG_GRANULE, ptr_tag, tag_count); | ||
154 | + } else { | ||
155 | + /* Memory access crosses to next page. */ | ||
156 | + tag_size = (next_page - tag_byte_first) / (2 * TAG_GRANULE); | ||
157 | + mem1 = allocation_tag_mem(env, mmu_idx, ptr, type, next_page - ptr, | ||
158 | + MMU_DATA_LOAD, tag_size, ra); | ||
159 | + | ||
160 | + tag_size = (tag_byte_end - next_page) / (2 * TAG_GRANULE); | ||
161 | + mem2 = allocation_tag_mem(env, mmu_idx, next_page, type, | ||
162 | + ptr_end - next_page, | ||
163 | + MMU_DATA_LOAD, tag_size, ra); | ||
164 | + | ||
165 | + /* | ||
166 | + * Perform all of the comparisons. | ||
167 | + * Note the possible but unlikely case of the operation spanning | ||
168 | + * two pages that do not both have tagging enabled. | ||
169 | + */ | ||
170 | + n = c = (next_page - tag_first) / TAG_GRANULE; | ||
171 | + if (mem1) { | ||
172 | + n = checkN(mem1, ptr & TAG_GRANULE, ptr_tag, c); | ||
173 | + } | ||
174 | + if (n == c) { | ||
175 | + if (!mem2) { | ||
176 | + goto done; | ||
177 | + } | ||
178 | + n += checkN(mem2, 0, ptr_tag, tag_count - c); | ||
179 | + } | ||
180 | + } | ||
181 | + | ||
182 | + /* | ||
183 | + * If we failed, we know which granule. Compute the element that | ||
184 | + * is first in that granule, and signal failure on that element. | ||
185 | + */ | ||
186 | + if (unlikely(n < tag_count)) { | ||
187 | + uint64_t fail_ofs; | ||
188 | + | ||
189 | + fail_ofs = tag_first + n * TAG_GRANULE - ptr; | ||
190 | + fail_ofs = ROUND_UP(fail_ofs, esize); | ||
191 | + mte_check_fail(env, mmu_idx, ptr + fail_ofs, ra); | ||
192 | + } | ||
193 | + | ||
194 | + done: | ||
195 | + return useronly_clean_ptr(ptr); | ||
196 | +} | ||
197 | + | ||
198 | uint64_t HELPER(mte_checkN)(CPUARMState *env, uint32_t desc, uint64_t ptr) | ||
199 | { | ||
200 | - return ptr; | ||
201 | + return mte_checkN(env, desc, ptr, GETPC()); | ||
202 | } | ||
203 | -- | ||
204 | 2.20.1 | ||
205 | |||
206 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Use a special helper for DC_ZVA, rather than the more | ||
4 | general mte_checkN. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20200626033144.790098-28-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/helper-a64.h | 1 + | ||
12 | target/arm/mte_helper.c | 106 +++++++++++++++++++++++++++++++++++++ | ||
13 | target/arm/translate-a64.c | 16 +++++- | ||
14 | 3 files changed, 122 insertions(+), 1 deletion(-) | ||
15 | |||
16 | diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/helper-a64.h | ||
19 | +++ b/target/arm/helper-a64.h | ||
20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) | ||
21 | |||
22 | DEF_HELPER_FLAGS_3(mte_check1, TCG_CALL_NO_WG, i64, env, i32, i64) | ||
23 | DEF_HELPER_FLAGS_3(mte_checkN, TCG_CALL_NO_WG, i64, env, i32, i64) | ||
24 | +DEF_HELPER_FLAGS_3(mte_check_zva, TCG_CALL_NO_WG, i64, env, i32, i64) | ||
25 | DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
26 | DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32) | ||
27 | DEF_HELPER_FLAGS_3(ldg, TCG_CALL_NO_WG, i64, env, i64, i64) | ||
28 | diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/target/arm/mte_helper.c | ||
31 | +++ b/target/arm/mte_helper.c | ||
32 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mte_checkN)(CPUARMState *env, uint32_t desc, uint64_t ptr) | ||
33 | { | ||
34 | return mte_checkN(env, desc, ptr, GETPC()); | ||
35 | } | ||
36 | + | ||
37 | +/* | ||
38 | + * Perform an MTE checked access for DC_ZVA. | ||
39 | + */ | ||
40 | +uint64_t HELPER(mte_check_zva)(CPUARMState *env, uint32_t desc, uint64_t ptr) | ||
41 | +{ | ||
42 | + uintptr_t ra = GETPC(); | ||
43 | + int log2_dcz_bytes, log2_tag_bytes; | ||
44 | + int mmu_idx, bit55; | ||
45 | + intptr_t dcz_bytes, tag_bytes, i; | ||
46 | + void *mem; | ||
47 | + uint64_t ptr_tag, mem_tag, align_ptr; | ||
48 | + | ||
49 | + bit55 = extract64(ptr, 55, 1); | ||
50 | + | ||
51 | + /* If TBI is disabled, the access is unchecked, and ptr is not dirty. */ | ||
52 | + if (unlikely(!tbi_check(desc, bit55))) { | ||
53 | + return ptr; | ||
54 | + } | ||
55 | + | ||
56 | + ptr_tag = allocation_tag_from_addr(ptr); | ||
57 | + | ||
58 | + if (tcma_check(desc, bit55, ptr_tag)) { | ||
59 | + goto done; | ||
60 | + } | ||
61 | + | ||
62 | + /* | ||
63 | + * In arm_cpu_realizefn, we asserted that dcz > LOG2_TAG_GRANULE+1, | ||
64 | + * i.e. 32 bytes, which is an unreasonably small dcz anyway, to make | ||
65 | + * sure that we can access one complete tag byte here. | ||
66 | + */ | ||
67 | + log2_dcz_bytes = env_archcpu(env)->dcz_blocksize + 2; | ||
68 | + log2_tag_bytes = log2_dcz_bytes - (LOG2_TAG_GRANULE + 1); | ||
69 | + dcz_bytes = (intptr_t)1 << log2_dcz_bytes; | ||
70 | + tag_bytes = (intptr_t)1 << log2_tag_bytes; | ||
71 | + align_ptr = ptr & -dcz_bytes; | ||
72 | + | ||
73 | + /* | ||
74 | + * Trap if accessing an invalid page. DC_ZVA requires that we supply | ||
75 | + * the original pointer for an invalid page. But watchpoints require | ||
76 | + * that we probe the actual space. So do both. | ||
77 | + */ | ||
78 | + mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); | ||
79 | + (void) probe_write(env, ptr, 1, mmu_idx, ra); | ||
80 | + mem = allocation_tag_mem(env, mmu_idx, align_ptr, MMU_DATA_STORE, | ||
81 | + dcz_bytes, MMU_DATA_LOAD, tag_bytes, ra); | ||
82 | + if (!mem) { | ||
83 | + goto done; | ||
84 | + } | ||
85 | + | ||
86 | + /* | ||
87 | + * Unlike the reasoning for checkN, DC_ZVA is always aligned, and thus | ||
88 | + * it is quite easy to perform all of the comparisons at once without | ||
89 | + * any extra masking. | ||
90 | + * | ||
91 | + * The most common zva block size is 64; some of the thunderx cpus use | ||
92 | + * a block size of 128. For user-only, aarch64_max_initfn will set the | ||
93 | + * block size to 512. Fill out the other cases for future-proofing. | ||
94 | + * | ||
95 | + * In order to be able to find the first miscompare later, we want the | ||
96 | + * tag bytes to be in little-endian order. | ||
97 | + */ | ||
98 | + switch (log2_tag_bytes) { | ||
99 | + case 0: /* zva_blocksize 32 */ | ||
100 | + mem_tag = *(uint8_t *)mem; | ||
101 | + ptr_tag *= 0x11u; | ||
102 | + break; | ||
103 | + case 1: /* zva_blocksize 64 */ | ||
104 | + mem_tag = cpu_to_le16(*(uint16_t *)mem); | ||
105 | + ptr_tag *= 0x1111u; | ||
106 | + break; | ||
107 | + case 2: /* zva_blocksize 128 */ | ||
108 | + mem_tag = cpu_to_le32(*(uint32_t *)mem); | ||
109 | + ptr_tag *= 0x11111111u; | ||
110 | + break; | ||
111 | + case 3: /* zva_blocksize 256 */ | ||
112 | + mem_tag = cpu_to_le64(*(uint64_t *)mem); | ||
113 | + ptr_tag *= 0x1111111111111111ull; | ||
114 | + break; | ||
115 | + | ||
116 | + default: /* zva_blocksize 512, 1024, 2048 */ | ||
117 | + ptr_tag *= 0x1111111111111111ull; | ||
118 | + i = 0; | ||
119 | + do { | ||
120 | + mem_tag = cpu_to_le64(*(uint64_t *)(mem + i)); | ||
121 | + if (unlikely(mem_tag != ptr_tag)) { | ||
122 | + goto fail; | ||
123 | + } | ||
124 | + i += 8; | ||
125 | + align_ptr += 16 * TAG_GRANULE; | ||
126 | + } while (i < tag_bytes); | ||
127 | + goto done; | ||
128 | + } | ||
129 | + | ||
130 | + if (likely(mem_tag == ptr_tag)) { | ||
131 | + goto done; | ||
132 | + } | ||
133 | + | ||
134 | + fail: | ||
135 | + /* Locate the first nibble that differs. */ | ||
136 | + i = ctz64(mem_tag ^ ptr_tag) >> 4; | ||
137 | + mte_check_fail(env, mmu_idx, align_ptr + i * TAG_GRANULE, ra); | ||
138 | + | ||
139 | + done: | ||
140 | + return useronly_clean_ptr(ptr); | ||
141 | +} | ||
142 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
143 | index XXXXXXX..XXXXXXX 100644 | ||
144 | --- a/target/arm/translate-a64.c | ||
145 | +++ b/target/arm/translate-a64.c | ||
146 | @@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | ||
147 | return; | ||
148 | case ARM_CP_DC_ZVA: | ||
149 | /* Writes clear the aligned block of memory which rt points into. */ | ||
150 | - tcg_rt = clean_data_tbi(s, cpu_reg(s, rt)); | ||
151 | + if (s->mte_active[0]) { | ||
152 | + TCGv_i32 t_desc; | ||
153 | + int desc = 0; | ||
154 | + | ||
155 | + desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | ||
156 | + desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | ||
157 | + desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | ||
158 | + t_desc = tcg_const_i32(desc); | ||
159 | + | ||
160 | + tcg_rt = new_tmp_a64(s); | ||
161 | + gen_helper_mte_check_zva(tcg_rt, cpu_env, t_desc, cpu_reg(s, rt)); | ||
162 | + tcg_temp_free_i32(t_desc); | ||
163 | + } else { | ||
164 | + tcg_rt = clean_data_tbi(s, cpu_reg(s, rt)); | ||
165 | + } | ||
166 | gen_helper_dc_zva(cpu_env, tcg_rt); | ||
167 | return; | ||
168 | default: | ||
169 | -- | ||
170 | 2.20.1 | ||
171 | |||
172 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20200626033144.790098-30-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-sve.c | 61 +++++++++++++++++++++----------------- | ||
9 | 1 file changed, 33 insertions(+), 28 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-sve.c | ||
14 | +++ b/target/arm/translate-sve.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) | ||
16 | int len_remain = len % 8; | ||
17 | int nparts = len / 8 + ctpop8(len_remain); | ||
18 | int midx = get_mem_index(s); | ||
19 | - TCGv_i64 addr, t0; | ||
20 | + TCGv_i64 dirty_addr, clean_addr, t0; | ||
21 | |||
22 | - addr = tcg_temp_new_i64(); | ||
23 | - t0 = tcg_temp_new_i64(); | ||
24 | + dirty_addr = tcg_temp_new_i64(); | ||
25 | + tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); | ||
26 | + clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len, MO_8); | ||
27 | + tcg_temp_free_i64(dirty_addr); | ||
28 | |||
29 | /* Note that unpredicated load/store of vector/predicate registers | ||
30 | * are defined as a stream of bytes, which equates to little-endian | ||
31 | @@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) | ||
32 | if (nparts <= 4) { | ||
33 | int i; | ||
34 | |||
35 | + t0 = tcg_temp_new_i64(); | ||
36 | for (i = 0; i < len_align; i += 8) { | ||
37 | tcg_gen_ld_i64(t0, cpu_env, vofs + i); | ||
38 | - tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + i); | ||
39 | - tcg_gen_qemu_st_i64(t0, addr, midx, MO_LEQ); | ||
40 | + tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEQ); | ||
41 | + tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8); | ||
42 | } | ||
43 | + tcg_temp_free_i64(t0); | ||
44 | } else { | ||
45 | TCGLabel *loop = gen_new_label(); | ||
46 | - TCGv_ptr t2, i = tcg_const_local_ptr(0); | ||
47 | + TCGv_ptr tp, i = tcg_const_local_ptr(0); | ||
48 | + | ||
49 | + /* Copy the clean address into a local temp, live across the loop. */ | ||
50 | + t0 = clean_addr; | ||
51 | + clean_addr = tcg_temp_local_new_i64(); | ||
52 | + tcg_gen_mov_i64(clean_addr, t0); | ||
53 | + tcg_temp_free_i64(t0); | ||
54 | |||
55 | gen_set_label(loop); | ||
56 | |||
57 | - t2 = tcg_temp_new_ptr(); | ||
58 | - tcg_gen_add_ptr(t2, cpu_env, i); | ||
59 | - tcg_gen_ld_i64(t0, t2, vofs); | ||
60 | - | ||
61 | - /* Minimize the number of local temps that must be re-read from | ||
62 | - * the stack each iteration. Instead, re-compute values other | ||
63 | - * than the loop counter. | ||
64 | - */ | ||
65 | - tcg_gen_addi_ptr(t2, i, imm); | ||
66 | - tcg_gen_extu_ptr_i64(addr, t2); | ||
67 | - tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, rn)); | ||
68 | - tcg_temp_free_ptr(t2); | ||
69 | - | ||
70 | - tcg_gen_qemu_st_i64(t0, addr, midx, MO_LEQ); | ||
71 | - | ||
72 | + t0 = tcg_temp_new_i64(); | ||
73 | + tp = tcg_temp_new_ptr(); | ||
74 | + tcg_gen_add_ptr(tp, cpu_env, i); | ||
75 | + tcg_gen_ld_i64(t0, tp, vofs); | ||
76 | tcg_gen_addi_ptr(i, i, 8); | ||
77 | + tcg_temp_free_ptr(tp); | ||
78 | + | ||
79 | + tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEQ); | ||
80 | + tcg_gen_addi_i64(clean_addr, clean_addr, 8); | ||
81 | + tcg_temp_free_i64(t0); | ||
82 | |||
83 | tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); | ||
84 | tcg_temp_free_ptr(i); | ||
85 | @@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) | ||
86 | |||
87 | /* Predicate register stores can be any multiple of 2. */ | ||
88 | if (len_remain) { | ||
89 | + t0 = tcg_temp_new_i64(); | ||
90 | tcg_gen_ld_i64(t0, cpu_env, vofs + len_align); | ||
91 | - tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + len_align); | ||
92 | |||
93 | switch (len_remain) { | ||
94 | case 2: | ||
95 | case 4: | ||
96 | case 8: | ||
97 | - tcg_gen_qemu_st_i64(t0, addr, midx, MO_LE | ctz32(len_remain)); | ||
98 | + tcg_gen_qemu_st_i64(t0, clean_addr, midx, | ||
99 | + MO_LE | ctz32(len_remain)); | ||
100 | break; | ||
101 | |||
102 | case 6: | ||
103 | - tcg_gen_qemu_st_i64(t0, addr, midx, MO_LEUL); | ||
104 | - tcg_gen_addi_i64(addr, addr, 4); | ||
105 | + tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUL); | ||
106 | + tcg_gen_addi_i64(clean_addr, clean_addr, 4); | ||
107 | tcg_gen_shri_i64(t0, t0, 32); | ||
108 | - tcg_gen_qemu_st_i64(t0, addr, midx, MO_LEUW); | ||
109 | + tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUW); | ||
110 | break; | ||
111 | |||
112 | default: | ||
113 | g_assert_not_reached(); | ||
114 | } | ||
115 | + tcg_temp_free_i64(t0); | ||
116 | } | ||
117 | - tcg_temp_free_i64(addr); | ||
118 | - tcg_temp_free_i64(t0); | ||
119 | + tcg_temp_free_i64(clean_addr); | ||
120 | } | ||
121 | |||
122 | static bool trans_LDR_zri(DisasContext *s, arg_rri *a) | ||
123 | -- | ||
124 | 2.20.1 | ||
125 | |||
126 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20200626033144.790098-31-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-sve.c | 6 ++++-- | ||
9 | 1 file changed, 4 insertions(+), 2 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-sve.c | ||
14 | +++ b/target/arm/translate-sve.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a) | ||
16 | unsigned esz = dtype_esz[a->dtype]; | ||
17 | unsigned msz = dtype_msz(a->dtype); | ||
18 | TCGLabel *over = gen_new_label(); | ||
19 | - TCGv_i64 temp; | ||
20 | + TCGv_i64 temp, clean_addr; | ||
21 | |||
22 | /* If the guarding predicate has no bits set, no load occurs. */ | ||
23 | if (psz <= 8) { | ||
24 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a) | ||
25 | /* Load the data. */ | ||
26 | temp = tcg_temp_new_i64(); | ||
27 | tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz); | ||
28 | - tcg_gen_qemu_ld_i64(temp, temp, get_mem_index(s), | ||
29 | + clean_addr = gen_mte_check1(s, temp, false, true, msz); | ||
30 | + | ||
31 | + tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s), | ||
32 | s->be_data | dtype_mop[a->dtype]); | ||
33 | |||
34 | /* Broadcast to *all* elements. */ | ||
35 | -- | ||
36 | 2.20.1 | ||
37 | |||
38 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Move the variable declarations to the top of the function, | ||
4 | but do not create a new label before sve_access_check. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20200626033144.790098-32-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/translate-sve.c | 12 +++++++----- | ||
12 | 1 file changed, 7 insertions(+), 5 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/translate-sve.c | ||
17 | +++ b/target/arm/translate-sve.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD1RQ_zpri(DisasContext *s, arg_rpri_load *a) | ||
19 | /* Load and broadcast element. */ | ||
20 | static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a) | ||
21 | { | ||
22 | - if (!sve_access_check(s)) { | ||
23 | - return true; | ||
24 | - } | ||
25 | - | ||
26 | unsigned vsz = vec_full_reg_size(s); | ||
27 | unsigned psz = pred_full_reg_size(s); | ||
28 | unsigned esz = dtype_esz[a->dtype]; | ||
29 | unsigned msz = dtype_msz(a->dtype); | ||
30 | - TCGLabel *over = gen_new_label(); | ||
31 | + TCGLabel *over; | ||
32 | TCGv_i64 temp, clean_addr; | ||
33 | |||
34 | + if (!sve_access_check(s)) { | ||
35 | + return true; | ||
36 | + } | ||
37 | + | ||
38 | + over = gen_new_label(); | ||
39 | + | ||
40 | /* If the guarding predicate has no bits set, no load occurs. */ | ||
41 | if (psz <= 8) { | ||
42 | /* Reduce the pred_esz_masks value simply to reduce the | ||
43 | -- | ||
44 | 2.20.1 | ||
45 | |||
46 | diff view generated by jsdifflib |