1
The following changes since commit 61fee7f45955cd0bf9b79be9fa9c7ebabb5e6a85:
1
Last minute pullreq for arm related patches; quite large because
2
there were several series that only just made it through code review
3
in time.
2
4
3
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/acceptance-testing-20200622' into staging (2020-06-22 20:50:10 +0100)
5
thanks
6
-- PMM
7
8
The following changes since commit 091e3e3dbc499d84c004e1c50bc9870af37f6e99:
9
10
Merge remote-tracking branch 'remotes/ericb/tags/pull-bitmaps-2020-10-26' into staging (2020-10-26 22:36:35 +0000)
4
11
5
are available in the Git repository at:
12
are available in the Git repository at:
6
13
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200623
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201027-1
8
15
9
for you to fetch changes up to 539533b85fbd269f777bed931de8ccae1dd837e9:
16
for you to fetch changes up to 32bd322a0134ed89db00f2b9b3894982db3dedcb:
10
17
11
arm/virt: Add memory hot remove support (2020-06-23 11:39:48 +0100)
18
hw/timer/armv7m_systick: Rewrite to use ptimers (2020-10-27 11:15:31 +0000)
12
19
13
----------------------------------------------------------------
20
----------------------------------------------------------------
14
target-arm queue:
21
target-arm queue:
15
* util/oslib-posix : qemu_init_exec_dir implementation for Mac
22
* raspi: add model of cprman clock manager
16
* target/arm: Last parts of neon decodetree conversion
23
* sbsa-ref: add an SBSA generic watchdog device
17
* hw/arm/virt: Add 5.0 HW compat props
24
* arm/trace: Fix hex printing
18
* hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status
25
* raspi: Add models of Pi 3 model A+, Pi Zero and Pi A+
19
* mps2: Add CMSDK APB watchdog, FPGAIO block, S2I devices and I2C devices
26
* hw/arm/smmuv3: Set the restoration priority of the vSMMUv3 explicitly
20
* mps2: Add some unimplemented-device stubs for audio and GPIO
27
* Nuvoton NPCM7xx: Add USB, RNG, GPIO and watchdog support
21
* mps2-tz: Use the ARM SBCon two-wire serial bus interface
28
* hw/arm: fix min_cpus for xlnx-versal-virt platform
22
* target/arm: Check supported KVM features globally (not per vCPU)
29
* hw/arm/highbank: Silence warnings about missing fallthrough statements
23
* tests/qtest/arm-cpu-features: Add feature setting tests
30
* linux-user: Support Aarch64 BTI
24
* arm/virt: Add memory hot remove support
31
* Armv7M systick: fix corner case bugs by rewriting to use ptimer
25
32
26
----------------------------------------------------------------
33
----------------------------------------------------------------
27
Andrew Jones (2):
34
Dr. David Alan Gilbert (1):
28
hw/arm/virt: Add 5.0 HW compat props
35
arm/trace: Fix hex printing
29
tests/qtest/arm-cpu-features: Add feature setting tests
30
36
31
David CARLIER (1):
37
Hao Wu (1):
32
util/oslib-posix : qemu_init_exec_dir implementation for Mac
38
hw/timer: Adding watchdog for NPCM7XX Timer.
33
39
34
Peter Maydell (23):
40
Havard Skinnemoen (4):
35
target/arm: Convert Neon 2-reg-misc VREV64 to decodetree
41
Move npcm7xx_timer_reached_zero call out of npcm7xx_timer_pause
36
target/arm: Convert Neon 2-reg-misc pairwise ops to decodetree
42
hw/misc: Add npcm7xx random number generator
37
target/arm: Convert VZIP, VUZP to decodetree
43
hw/arm/npcm7xx: Add EHCI and OHCI controllers
38
target/arm: Convert Neon narrowing moves to decodetree
44
hw/gpio: Add GPIO model for Nuvoton NPCM7xx
39
target/arm: Convert Neon 2-reg-misc VSHLL to decodetree
40
target/arm: Convert Neon VCVT f16/f32 insns to decodetree
41
target/arm: Convert vectorised 2-reg-misc Neon ops to decodetree
42
target/arm: Convert Neon 2-reg-misc crypto operations to decodetree
43
target/arm: Rename NeonGenOneOpFn to NeonGenOne64OpFn
44
target/arm: Fix capitalization in NeonGenTwo{Single, Double}OPFn typedefs
45
target/arm: Make gen_swap_half() take separate src and dest
46
target/arm: Convert Neon 2-reg-misc VREV32 and VREV16 to decodetree
47
target/arm: Convert remaining simple 2-reg-misc Neon ops
48
target/arm: Convert Neon VQABS, VQNEG to decodetree
49
target/arm: Convert simple fp Neon 2-reg-misc insns
50
target/arm: Convert Neon 2-reg-misc fp-compare-with-zero insns to decodetree
51
target/arm: Convert Neon 2-reg-misc VRINT insns to decodetree
52
target/arm: Convert Neon 2-reg-misc VCVT insns to decodetree
53
target/arm: Convert Neon VSWP to decodetree
54
target/arm: Convert Neon VTRN to decodetree
55
target/arm: Move some functions used only in translate-neon.inc.c to that file
56
target/arm: Remove unnecessary gen_io_end() calls
57
target/arm: Remove dead code relating to SABA and UABA
58
45
59
Philippe Mathieu-Daudé (15):
46
Luc Michel (14):
60
hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status
47
hw/core/clock: provide the VMSTATE_ARRAY_CLOCK macro
61
hw/i2c/versatile_i2c: Add definitions for register addresses
48
hw/core/clock: trace clock values in Hz instead of ns
62
hw/i2c/versatile_i2c: Add SCL/SDA definitions
49
hw/arm/raspi: fix CPRMAN base address
63
hw/i2c: Add header for ARM SBCon two-wire serial bus interface
50
hw/arm/raspi: add a skeleton implementation of the CPRMAN
64
hw/arm: Use TYPE_VERSATILE_I2C instead of hardcoded string
51
hw/misc/bcm2835_cprman: add a PLL skeleton implementation
65
hw/arm/mps2: Document CMSDK/FPGA APB subsystem sections
52
hw/misc/bcm2835_cprman: implement PLLs behaviour
66
hw/arm/mps2: Rename CMSDK AHB peripheral region
53
hw/misc/bcm2835_cprman: add a PLL channel skeleton implementation
67
hw/arm/mps2: Add CMSDK APB watchdog device
54
hw/misc/bcm2835_cprman: implement PLL channels behaviour
68
hw/arm/mps2: Add CMSDK AHB GPIO peripherals as unimplemented devices
55
hw/misc/bcm2835_cprman: add a clock mux skeleton implementation
69
hw/arm/mps2: Map the FPGA I/O block
56
hw/misc/bcm2835_cprman: implement clock mux behaviour
70
hw/arm/mps2: Add SPI devices
57
hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer
71
hw/arm/mps2: Add I2C devices
58
hw/misc/bcm2835_cprman: add sane reset values to the registers
72
hw/arm/mps2: Add audio I2S interface as unimplemented device
59
hw/char/pl011: add a clock input
73
hw/arm/mps2-tz: Use the ARM SBCon two-wire serial bus interface
60
hw/arm/bcm2835_peripherals: connect the UART clock
74
target/arm: Check supported KVM features globally (not per vCPU)
75
61
76
Shameer Kolothum (1):
62
Pavel Dovgalyuk (1):
77
arm/virt: Add memory hot remove support
63
hw/arm: fix min_cpus for xlnx-versal-virt platform
78
64
79
include/hw/i2c/arm_sbcon_i2c.h | 35 ++
65
Peter Maydell (2):
80
target/arm/cpu.h | 2 +-
66
hw/core/ptimer: Support ptimer being disabled by timer callback
81
target/arm/kvm_arm.h | 21 +-
67
hw/timer/armv7m_systick: Rewrite to use ptimers
82
target/arm/translate.h | 8 +-
83
target/arm/neon-dp.decode | 106 ++++
84
hw/acpi/generic_event_device.c | 29 +
85
hw/arm/mps2-tz.c | 23 +-
86
hw/arm/mps2.c | 65 ++-
87
hw/arm/realview.c | 3 +-
88
hw/arm/versatilepb.c | 3 +-
89
hw/arm/vexpress.c | 3 +-
90
hw/arm/virt.c | 63 +-
91
hw/i2c/versatile_i2c.c | 38 +-
92
hw/watchdog/cmsdk-apb-watchdog.c | 1 +
93
target/arm/cpu.c | 2 +-
94
target/arm/cpu64.c | 10 +-
95
target/arm/kvm.c | 4 +-
96
target/arm/kvm64.c | 14 +-
97
target/arm/translate-a64.c | 20 +-
98
target/arm/translate-neon.inc.c | 1191 +++++++++++++++++++++++++++++++++++++-
99
target/arm/translate-vfp.inc.c | 7 +-
100
target/arm/translate.c | 1064 +---------------------------------
101
tests/qtest/arm-cpu-features.c | 38 +-
102
util/oslib-posix.c | 15 +
103
MAINTAINERS | 1 +
104
hw/arm/Kconfig | 8 +-
105
hw/watchdog/trace-events | 1 +
106
27 files changed, 1624 insertions(+), 1151 deletions(-)
107
create mode 100644 include/hw/i2c/arm_sbcon_i2c.h
108
68
69
Philippe Mathieu-Daudé (10):
70
linux-user/elfload: Avoid leaking interp_name using GLib memory API
71
hw/arm/bcm2836: Restrict BCM283XInfo declaration to C source
72
hw/arm/bcm2836: QOM'ify more by adding class_init() to each SoC type
73
hw/arm/bcm2836: Introduce BCM283XClass::core_count
74
hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCs
75
hw/arm/bcm2836: Split out common realize() code
76
hw/arm/bcm2836: Introduce the BCM2835 SoC
77
hw/arm/raspi: Add the Raspberry Pi A+ machine
78
hw/arm/raspi: Add the Raspberry Pi Zero machine
79
hw/arm/raspi: Add the Raspberry Pi 3 model A+
80
81
Richard Henderson (11):
82
linux-user/aarch64: Reset btype for signals
83
linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI
84
include/elf: Add defines related to GNU property notes for AArch64
85
linux-user/elfload: Fix coding style in load_elf_image
86
linux-user/elfload: Adjust iteration over phdr
87
linux-user/elfload: Move PT_INTERP detection to first loop
88
linux-user/elfload: Use Error for load_elf_image
89
linux-user/elfload: Use Error for load_elf_interp
90
linux-user/elfload: Parse NT_GNU_PROPERTY_TYPE_0 notes
91
linux-user/elfload: Parse GNU_PROPERTY_AARCH64_FEATURE_1_AND
92
tests/tcg/aarch64: Add bti smoke tests
93
94
Shashi Mallela (2):
95
hw/watchdog: Implement SBSA watchdog device
96
hw/arm/sbsa-ref: add SBSA watchdog device
97
98
Thomas Huth (1):
99
hw/arm/highbank: Silence warnings about missing fallthrough statements
100
101
Zenghui Yu (1):
102
hw/arm/smmuv3: Set the restoration priority of the vSMMUv3 explicitly
103
104
docs/system/arm/nuvoton.rst | 6 +-
105
hw/usb/hcd-ehci.h | 1 +
106
include/elf.h | 22 +
107
include/exec/cpu-all.h | 2 +
108
include/hw/arm/bcm2835_peripherals.h | 5 +-
109
include/hw/arm/bcm2836.h | 9 +-
110
include/hw/arm/npcm7xx.h | 8 +
111
include/hw/arm/raspi_platform.h | 5 +-
112
include/hw/char/pl011.h | 1 +
113
include/hw/clock.h | 5 +
114
include/hw/gpio/npcm7xx_gpio.h | 55 ++
115
include/hw/misc/bcm2835_cprman.h | 210 ++++++
116
include/hw/misc/bcm2835_cprman_internals.h | 1019 ++++++++++++++++++++++++++++
117
include/hw/misc/npcm7xx_clk.h | 2 +
118
include/hw/misc/npcm7xx_rng.h | 34 +
119
include/hw/timer/armv7m_systick.h | 3 +-
120
include/hw/timer/npcm7xx_timer.h | 48 +-
121
include/hw/watchdog/sbsa_gwdt.h | 79 +++
122
linux-user/qemu.h | 4 +
123
linux-user/syscall_defs.h | 4 +
124
target/arm/cpu.h | 5 +
125
hw/arm/bcm2835_peripherals.c | 15 +-
126
hw/arm/bcm2836.c | 182 +++--
127
hw/arm/highbank.c | 2 +
128
hw/arm/npcm7xx.c | 126 +++-
129
hw/arm/raspi.c | 41 ++
130
hw/arm/sbsa-ref.c | 23 +
131
hw/arm/smmuv3.c | 1 +
132
hw/arm/xlnx-versal-virt.c | 1 +
133
hw/char/pl011.c | 45 ++
134
hw/core/clock.c | 6 +-
135
hw/core/ptimer.c | 4 +
136
hw/gpio/npcm7xx_gpio.c | 424 ++++++++++++
137
hw/misc/bcm2835_cprman.c | 808 ++++++++++++++++++++++
138
hw/misc/npcm7xx_clk.c | 28 +
139
hw/misc/npcm7xx_rng.c | 180 +++++
140
hw/timer/armv7m_systick.c | 124 ++--
141
hw/timer/npcm7xx_timer.c | 270 ++++++--
142
hw/usb/hcd-ehci-sysbus.c | 19 +
143
hw/watchdog/sbsa_gwdt.c | 293 ++++++++
144
linux-user/aarch64/signal.c | 10 +-
145
linux-user/elfload.c | 326 +++++++--
146
linux-user/mmap.c | 16 +
147
target/arm/translate-a64.c | 6 +-
148
tests/qtest/npcm7xx_gpio-test.c | 385 +++++++++++
149
tests/qtest/npcm7xx_rng-test.c | 278 ++++++++
150
tests/qtest/npcm7xx_watchdog_timer-test.c | 319 +++++++++
151
tests/tcg/aarch64/bti-1.c | 62 ++
152
tests/tcg/aarch64/bti-2.c | 116 ++++
153
tests/tcg/aarch64/bti-crt.inc.c | 51 ++
154
MAINTAINERS | 1 +
155
hw/arm/Kconfig | 1 +
156
hw/arm/trace-events | 2 +-
157
hw/char/trace-events | 1 +
158
hw/core/trace-events | 4 +-
159
hw/gpio/meson.build | 1 +
160
hw/gpio/trace-events | 7 +
161
hw/misc/meson.build | 2 +
162
hw/misc/trace-events | 9 +
163
hw/watchdog/Kconfig | 3 +
164
hw/watchdog/meson.build | 1 +
165
tests/qtest/meson.build | 6 +-
166
tests/tcg/aarch64/Makefile.target | 10 +
167
tests/tcg/configure.sh | 4 +
168
64 files changed, 5461 insertions(+), 279 deletions(-)
169
create mode 100644 include/hw/gpio/npcm7xx_gpio.h
170
create mode 100644 include/hw/misc/bcm2835_cprman.h
171
create mode 100644 include/hw/misc/bcm2835_cprman_internals.h
172
create mode 100644 include/hw/misc/npcm7xx_rng.h
173
create mode 100644 include/hw/watchdog/sbsa_gwdt.h
174
create mode 100644 hw/gpio/npcm7xx_gpio.c
175
create mode 100644 hw/misc/bcm2835_cprman.c
176
create mode 100644 hw/misc/npcm7xx_rng.c
177
create mode 100644 hw/watchdog/sbsa_gwdt.c
178
create mode 100644 tests/qtest/npcm7xx_gpio-test.c
179
create mode 100644 tests/qtest/npcm7xx_rng-test.c
180
create mode 100644 tests/qtest/npcm7xx_watchdog_timer-test.c
181
create mode 100644 tests/tcg/aarch64/bti-1.c
182
create mode 100644 tests/tcg/aarch64/bti-2.c
183
create mode 100644 tests/tcg/aarch64/bti-crt.inc.c
184
diff view generated by jsdifflib
1
Convert the Neon VSWP insn to decodetree. Since the new implementation
1
From: Richard Henderson <richard.henderson@linaro.org>
2
doesn't have to share a pass-loop with the other 2-reg-misc operations
3
we can implement the swap with 64-bit accesses rather than 32-bits
4
(which brings us into line with the pseudocode and is more efficient).
5
2
3
The kernel sets btype for the signal handler as if for a call.
4
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201021173749.111103-2-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200616170844.13318-20-peter.maydell@linaro.org
9
---
9
---
10
target/arm/neon-dp.decode | 2 ++
10
linux-user/aarch64/signal.c | 10 ++++++++--
11
target/arm/translate-neon.inc.c | 41 +++++++++++++++++++++++++++++++++
11
1 file changed, 8 insertions(+), 2 deletions(-)
12
target/arm/translate.c | 5 +---
13
3 files changed, 44 insertions(+), 4 deletions(-)
14
12
15
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
13
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/neon-dp.decode
15
--- a/linux-user/aarch64/signal.c
18
+++ b/target/arm/neon-dp.decode
16
+++ b/linux-user/aarch64/signal.c
19
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
17
@@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
20
VABS_F 1111 001 11 . 11 .. 01 .... 0 1110 . . 0 .... @2misc
18
+ offsetof(struct target_rt_frame_record, tramp);
21
VNEG_F 1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc
19
}
22
20
env->xregs[0] = usig;
23
+ VSWP 1111 001 11 . 11 .. 10 .... 0 0000 . . 0 .... @2misc
21
- env->xregs[31] = frame_addr;
22
env->xregs[29] = frame_addr + fr_ofs;
23
- env->pc = ka->_sa_handler;
24
env->xregs[30] = return_addr;
25
+ env->xregs[31] = frame_addr;
26
+ env->pc = ka->_sa_handler;
24
+
27
+
25
VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc
28
+ /* Invoke the signal handler as if by indirect call. */
26
VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc
29
+ if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
27
30
+ env->btype = 2;
28
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/translate-neon.inc.c
31
+++ b/target/arm/translate-neon.inc.c
32
@@ -XXX,XX +XXX,XX @@ DO_VCVT(VCVTPU, FPROUNDING_POSINF, false)
33
DO_VCVT(VCVTPS, FPROUNDING_POSINF, true)
34
DO_VCVT(VCVTMU, FPROUNDING_NEGINF, false)
35
DO_VCVT(VCVTMS, FPROUNDING_NEGINF, true)
36
+
37
+static bool trans_VSWP(DisasContext *s, arg_2misc *a)
38
+{
39
+ TCGv_i64 rm, rd;
40
+ int pass;
41
+
42
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
43
+ return false;
44
+ }
31
+ }
45
+
32
+
46
+ /* UNDEF accesses to D16-D31 if they don't exist. */
33
if (info) {
47
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
34
tswap_siginfo(&frame->info, info);
48
+ ((a->vd | a->vm) & 0x10)) {
35
env->xregs[1] = frame_addr + offsetof(struct target_rt_sigframe, info);
49
+ return false;
50
+ }
51
+
52
+ if (a->size != 0) {
53
+ return false;
54
+ }
55
+
56
+ if ((a->vd | a->vm) & a->q) {
57
+ return false;
58
+ }
59
+
60
+ if (!vfp_access_check(s)) {
61
+ return true;
62
+ }
63
+
64
+ rm = tcg_temp_new_i64();
65
+ rd = tcg_temp_new_i64();
66
+ for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
67
+ neon_load_reg64(rm, a->vm + pass);
68
+ neon_load_reg64(rd, a->vd + pass);
69
+ neon_store_reg64(rm, a->vd + pass);
70
+ neon_store_reg64(rd, a->vm + pass);
71
+ }
72
+ tcg_temp_free_i64(rm);
73
+ tcg_temp_free_i64(rd);
74
+
75
+ return true;
76
+}
77
diff --git a/target/arm/translate.c b/target/arm/translate.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/target/arm/translate.c
80
+++ b/target/arm/translate.c
81
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
82
case NEON_2RM_VCVTPS:
83
case NEON_2RM_VCVTMU:
84
case NEON_2RM_VCVTMS:
85
+ case NEON_2RM_VSWP:
86
/* handled by decodetree */
87
return 1;
88
case NEON_2RM_VTRN:
89
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
90
for (pass = 0; pass < (q ? 4 : 2); pass++) {
91
tmp = neon_load_reg(rm, pass);
92
switch (op) {
93
- case NEON_2RM_VSWP:
94
- tmp2 = neon_load_reg(rd, pass);
95
- neon_store_reg(rm, pass, tmp2);
96
- break;
97
case NEON_2RM_VTRN:
98
tmp2 = neon_load_reg(rd, pass);
99
switch (size) {
100
--
36
--
101
2.20.1
37
2.20.1
102
38
103
39
diff view generated by jsdifflib
1
In commit cfdb2c0c95ae9205b0 ("target/arm: Vectorize SABA/UABA") we
1
From: Richard Henderson <richard.henderson@linaro.org>
2
replaced the old handling of SABA/UABA with a vectorized implementation
3
which returns early rather than falling into the loop-ever-elements
4
code. We forgot to delete the part of the old looping code that
5
did the accumulate step, and Coverity correctly warns (CID 1428955)
6
that this code is now dead. Delete it.
7
2
8
Fixes: cfdb2c0c95ae9205b0
3
Transform the prot bit to a qemu internal page bit, and save
4
it in the page tables.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201021173749.111103-3-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200619171547.29780-1-peter.maydell@linaro.org
13
---
10
---
14
target/arm/translate-a64.c | 12 ------------
11
include/exec/cpu-all.h | 2 ++
15
1 file changed, 12 deletions(-)
12
linux-user/syscall_defs.h | 4 ++++
13
target/arm/cpu.h | 5 +++++
14
linux-user/mmap.c | 16 ++++++++++++++++
15
target/arm/translate-a64.c | 6 +++---
16
5 files changed, 30 insertions(+), 3 deletions(-)
16
17
18
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/exec/cpu-all.h
21
+++ b/include/exec/cpu-all.h
22
@@ -XXX,XX +XXX,XX @@ extern intptr_t qemu_host_page_mask;
23
/* FIXME: Code that sets/uses this is broken and needs to go away. */
24
#define PAGE_RESERVED 0x0020
25
#endif
26
+/* Target-specific bits that will be used via page_get_flags(). */
27
+#define PAGE_TARGET_1 0x0080
28
29
#if defined(CONFIG_USER_ONLY)
30
void page_dump(FILE *f);
31
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/linux-user/syscall_defs.h
34
+++ b/linux-user/syscall_defs.h
35
@@ -XXX,XX +XXX,XX @@ struct target_winsize {
36
#define TARGET_PROT_SEM 0x08
37
#endif
38
39
+#ifdef TARGET_AARCH64
40
+#define TARGET_PROT_BTI 0x10
41
+#endif
42
+
43
/* Common */
44
#define TARGET_MAP_SHARED    0x01        /* Share changes */
45
#define TARGET_MAP_PRIVATE    0x02        /* Changes are private */
46
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/cpu.h
49
+++ b/target/arm/cpu.h
50
@@ -XXX,XX +XXX,XX @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
51
#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
52
#define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1)
53
54
+/*
55
+ * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
56
+ */
57
+#define PAGE_BTI PAGE_TARGET_1
58
+
59
/*
60
* Naming convention for isar_feature functions:
61
* Functions which test 32-bit ID registers should have _aa32_ in
62
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/linux-user/mmap.c
65
+++ b/linux-user/mmap.c
66
@@ -XXX,XX +XXX,XX @@ static int validate_prot_to_pageflags(int *host_prot, int prot)
67
*host_prot = (prot & (PROT_READ | PROT_WRITE))
68
| (prot & PROT_EXEC ? PROT_READ : 0);
69
70
+#ifdef TARGET_AARCH64
71
+ /*
72
+ * The PROT_BTI bit is only accepted if the cpu supports the feature.
73
+ * Since this is the unusual case, don't bother checking unless
74
+ * the bit has been requested. If set and valid, record the bit
75
+ * within QEMU's page_flags.
76
+ */
77
+ if (prot & TARGET_PROT_BTI) {
78
+ ARMCPU *cpu = ARM_CPU(thread_cpu);
79
+ if (cpu_isar_feature(aa64_bti, cpu)) {
80
+ valid |= TARGET_PROT_BTI;
81
+ page_flags |= PAGE_BTI;
82
+ }
83
+ }
84
+#endif
85
+
86
return prot & ~valid ? 0 : page_flags;
87
}
88
17
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
89
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
18
index XXXXXXX..XXXXXXX 100644
90
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate-a64.c
91
--- a/target/arm/translate-a64.c
20
+++ b/target/arm/translate-a64.c
92
+++ b/target/arm/translate-a64.c
21
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
93
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
22
genfn(tcg_res, tcg_op1, tcg_op2);
94
*/
23
}
95
static bool is_guarded_page(CPUARMState *env, DisasContext *s)
24
96
{
25
- if (opcode == 0xf) {
97
-#ifdef CONFIG_USER_ONLY
26
- /* SABA, UABA: accumulating ops */
98
- return false; /* FIXME */
27
- static NeonGenTwoOpFn * const fns[3] = {
99
-#else
28
- gen_helper_neon_add_u8,
100
uint64_t addr = s->base.pc_first;
29
- gen_helper_neon_add_u16,
101
+#ifdef CONFIG_USER_ONLY
30
- tcg_gen_add_i32,
102
+ return page_get_flags(addr) & PAGE_BTI;
31
- };
103
+#else
32
-
104
int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx);
33
- read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);
105
unsigned int index = tlb_index(env, mmu_idx, addr);
34
- fns[size](tcg_res, tcg_op1, tcg_res);
106
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
35
- }
36
-
37
write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
38
39
tcg_temp_free_i32(tcg_res);
40
--
107
--
41
2.20.1
108
2.20.1
42
109
43
110
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
These are all of the defines required to parse
4
GNU_PROPERTY_AARCH64_FEATURE_1_AND, copied from binutils.
5
Other missing defines related to other GNU program headers
6
and notes are elided for now.
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20201021173749.111103-4-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/elf.h | 22 ++++++++++++++++++++++
14
1 file changed, 22 insertions(+)
15
16
diff --git a/include/elf.h b/include/elf.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/elf.h
19
+++ b/include/elf.h
20
@@ -XXX,XX +XXX,XX @@ typedef int64_t Elf64_Sxword;
21
#define PT_NOTE 4
22
#define PT_SHLIB 5
23
#define PT_PHDR 6
24
+#define PT_LOOS 0x60000000
25
+#define PT_HIOS 0x6fffffff
26
#define PT_LOPROC 0x70000000
27
#define PT_HIPROC 0x7fffffff
28
29
+#define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
30
+
31
#define PT_MIPS_REGINFO 0x70000000
32
#define PT_MIPS_RTPROC 0x70000001
33
#define PT_MIPS_OPTIONS 0x70000002
34
@@ -XXX,XX +XXX,XX @@ typedef struct elf64_shdr {
35
#define NT_ARM_SYSTEM_CALL 0x404 /* ARM system call number */
36
#define NT_ARM_SVE 0x405 /* ARM Scalable Vector Extension regs */
37
38
+/* Defined note types for GNU systems. */
39
+
40
+#define NT_GNU_PROPERTY_TYPE_0 5 /* Program property */
41
+
42
+/* Values used in GNU .note.gnu.property notes (NT_GNU_PROPERTY_TYPE_0). */
43
+
44
+#define GNU_PROPERTY_STACK_SIZE 1
45
+#define GNU_PROPERTY_NO_COPY_ON_PROTECTED 2
46
+
47
+#define GNU_PROPERTY_LOPROC 0xc0000000
48
+#define GNU_PROPERTY_HIPROC 0xdfffffff
49
+#define GNU_PROPERTY_LOUSER 0xe0000000
50
+#define GNU_PROPERTY_HIUSER 0xffffffff
51
+
52
+#define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
53
+#define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1u << 0)
54
+#define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1u << 1)
55
+
56
/*
57
* Physical entry point into the kernel.
58
*
59
--
60
2.20.1
61
62
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
From 'Application Note AN385', chapter 3.14:
3
Fix an unlikely memory leak in load_elf_image().
4
4
5
The SMM implements a simple SBCon interface based on I2C.
5
Fixes: bf858897b7 ("linux-user: Re-use load_elf_image for the main binary.")
6
7
There are 4 SBCon interfaces on the FPGA APB subsystem.
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20200617072539.32686-13-f4bug@amsat.org
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201021173749.111103-5-richard.henderson@linaro.org
9
Message-Id: <20201003174944.1972444-1-f4bug@amsat.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
13
---
14
hw/arm/mps2.c | 8 ++++++++
14
linux-user/elfload.c | 8 ++++----
15
hw/arm/Kconfig | 1 +
15
1 file changed, 4 insertions(+), 4 deletions(-)
16
2 files changed, 9 insertions(+)
17
16
18
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
17
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
19
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/mps2.c
19
--- a/linux-user/elfload.c
21
+++ b/hw/arm/mps2.c
20
+++ b/linux-user/elfload.c
22
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
23
#include "hw/misc/mps2-scc.h"
22
info->brk = vaddr_em;
24
#include "hw/misc/mps2-fpgaio.h"
23
}
25
#include "hw/ssi/pl022.h"
24
} else if (eppnt->p_type == PT_INTERP && pinterp_name) {
26
+#include "hw/i2c/arm_sbcon_i2c.h"
25
- char *interp_name;
27
#include "hw/net/lan9118.h"
26
+ g_autofree char *interp_name = NULL;
28
#include "net/net.h"
27
29
#include "hw/watchdog/cmsdk-apb-watchdog.h"
28
if (*pinterp_name) {
30
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
29
errmsg = "Multiple PT_INTERP entries";
31
qdev_get_gpio_in(orgate_dev, j));
30
goto exit_errmsg;
32
}
31
}
32
- interp_name = malloc(eppnt->p_filesz);
33
+ interp_name = g_malloc(eppnt->p_filesz);
34
if (!interp_name) {
35
goto exit_perror;
36
}
37
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
38
errmsg = "Invalid PT_INTERP entry";
39
goto exit_errmsg;
40
}
41
- *pinterp_name = interp_name;
42
+ *pinterp_name = g_steal_pointer(&interp_name);
43
#ifdef TARGET_MIPS
44
} else if (eppnt->p_type == PT_MIPS_ABIFLAGS) {
45
Mips_elf_abiflags_v0 abiflags;
46
@@ -XXX,XX +XXX,XX @@ int load_elf_binary(struct linux_binprm *bprm, struct image_info *info)
47
if (elf_interpreter) {
48
info->load_bias = interp_info.load_bias;
49
info->entry = interp_info.entry;
50
- free(elf_interpreter);
51
+ g_free(elf_interpreter);
33
}
52
}
34
+ for (i = 0; i < 4; i++) {
53
35
+ static const hwaddr i2cbase[] = {0x40022000, /* Touch */
54
#ifdef USE_ELF_CORE_DUMP
36
+ 0x40023000, /* Audio */
37
+ 0x40029000, /* Shield0 */
38
+ 0x4002a000}; /* Shield1 */
39
+ sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL);
40
+ }
41
42
/* In hardware this is a LAN9220; the LAN9118 is software compatible
43
* except that it doesn't support the checksum-offload feature.
44
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/arm/Kconfig
47
+++ b/hw/arm/Kconfig
48
@@ -XXX,XX +XXX,XX @@ config MPS2
49
select SPLIT_IRQ
50
select UNIMP
51
select CMSDK_APB_WATCHDOG
52
+ select VERSATILE_I2C
53
54
config FSL_IMX7
55
bool
56
--
55
--
57
2.20.1
56
2.20.1
58
57
59
58
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Fixing this now will clarify following patches.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20201021173749.111103-6-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
linux-user/elfload.c | 12 +++++++++---
11
1 file changed, 9 insertions(+), 3 deletions(-)
12
13
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/linux-user/elfload.c
16
+++ b/linux-user/elfload.c
17
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
18
abi_ulong vaddr, vaddr_po, vaddr_ps, vaddr_ef, vaddr_em, vaddr_len;
19
int elf_prot = 0;
20
21
- if (eppnt->p_flags & PF_R) elf_prot = PROT_READ;
22
- if (eppnt->p_flags & PF_W) elf_prot |= PROT_WRITE;
23
- if (eppnt->p_flags & PF_X) elf_prot |= PROT_EXEC;
24
+ if (eppnt->p_flags & PF_R) {
25
+ elf_prot |= PROT_READ;
26
+ }
27
+ if (eppnt->p_flags & PF_W) {
28
+ elf_prot |= PROT_WRITE;
29
+ }
30
+ if (eppnt->p_flags & PF_X) {
31
+ elf_prot |= PROT_EXEC;
32
+ }
33
34
vaddr = load_bias + eppnt->p_vaddr;
35
vaddr_po = TARGET_ELF_PAGEOFFSET(vaddr);
36
--
37
2.20.1
38
39
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The second loop uses a loop induction variable, and the first
4
does not. Transform the first to match the second, to simplify
5
a following patch moving code between them.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201021173749.111103-7-richard.henderson@linaro.org
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
linux-user/elfload.c | 9 +++++----
13
1 file changed, 5 insertions(+), 4 deletions(-)
14
15
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/linux-user/elfload.c
18
+++ b/linux-user/elfload.c
19
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
20
loaddr = -1, hiaddr = 0;
21
info->alignment = 0;
22
for (i = 0; i < ehdr->e_phnum; ++i) {
23
- if (phdr[i].p_type == PT_LOAD) {
24
- abi_ulong a = phdr[i].p_vaddr - phdr[i].p_offset;
25
+ struct elf_phdr *eppnt = phdr + i;
26
+ if (eppnt->p_type == PT_LOAD) {
27
+ abi_ulong a = eppnt->p_vaddr - eppnt->p_offset;
28
if (a < loaddr) {
29
loaddr = a;
30
}
31
- a = phdr[i].p_vaddr + phdr[i].p_memsz;
32
+ a = eppnt->p_vaddr + eppnt->p_memsz;
33
if (a > hiaddr) {
34
hiaddr = a;
35
}
36
++info->nsegs;
37
- info->alignment |= phdr[i].p_align;
38
+ info->alignment |= eppnt->p_align;
39
}
40
}
41
42
--
43
2.20.1
44
45
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
By using the TYPE_* definitions for devices, we can:
3
For BTI, we need to know if the executable is static or dynamic,
4
- quickly find where devices are used with 'git-grep'
4
which means looking for PT_INTERP earlier.
5
- easily rename a device (one-line change).
6
5
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200617072539.32686-6-f4bug@amsat.org
7
Message-id: 20201021173749.111103-8-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
hw/arm/realview.c | 3 ++-
11
linux-user/elfload.c | 60 +++++++++++++++++++++++---------------------
13
hw/arm/versatilepb.c | 3 ++-
12
1 file changed, 31 insertions(+), 29 deletions(-)
14
hw/arm/vexpress.c | 3 ++-
15
3 files changed, 6 insertions(+), 3 deletions(-)
16
13
17
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
14
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/realview.c
16
--- a/linux-user/elfload.c
20
+++ b/hw/arm/realview.c
17
+++ b/linux-user/elfload.c
21
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
22
#include "hw/cpu/a9mpcore.h"
19
23
#include "hw/intc/realview_gic.h"
20
mmap_lock();
24
#include "hw/irq.h"
21
25
+#include "hw/i2c/arm_sbcon_i2c.h"
22
- /* Find the maximum size of the image and allocate an appropriate
26
23
- amount of memory to handle that. */
27
#define SMP_BOOT_ADDR 0xe0000000
24
+ /*
28
#define SMP_BOOTREG_ADDR 0x10000030
25
+ * Find the maximum size of the image and allocate an appropriate
29
@@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine,
26
+ * amount of memory to handle that. Locate the interpreter, if any.
27
+ */
28
loaddr = -1, hiaddr = 0;
29
info->alignment = 0;
30
for (i = 0; i < ehdr->e_phnum; ++i) {
31
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
32
}
33
++info->nsegs;
34
info->alignment |= eppnt->p_align;
35
+ } else if (eppnt->p_type == PT_INTERP && pinterp_name) {
36
+ g_autofree char *interp_name = NULL;
37
+
38
+ if (*pinterp_name) {
39
+ errmsg = "Multiple PT_INTERP entries";
40
+ goto exit_errmsg;
41
+ }
42
+ interp_name = g_malloc(eppnt->p_filesz);
43
+ if (!interp_name) {
44
+ goto exit_perror;
45
+ }
46
+
47
+ if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) {
48
+ memcpy(interp_name, bprm_buf + eppnt->p_offset,
49
+ eppnt->p_filesz);
50
+ } else {
51
+ retval = pread(image_fd, interp_name, eppnt->p_filesz,
52
+ eppnt->p_offset);
53
+ if (retval != eppnt->p_filesz) {
54
+ goto exit_perror;
55
+ }
56
+ }
57
+ if (interp_name[eppnt->p_filesz - 1] != 0) {
58
+ errmsg = "Invalid PT_INTERP entry";
59
+ goto exit_errmsg;
60
+ }
61
+ *pinterp_name = g_steal_pointer(&interp_name);
30
}
62
}
31
}
63
}
32
64
33
- dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
65
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
34
+ dev = sysbus_create_simple(TYPE_VERSATILE_I2C, 0x10002000, NULL);
66
if (vaddr_em > info->brk) {
35
i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
67
info->brk = vaddr_em;
36
i2c_create_slave(i2c, "ds1338", 0x68);
68
}
37
69
- } else if (eppnt->p_type == PT_INTERP && pinterp_name) {
38
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
70
- g_autofree char *interp_name = NULL;
39
index XXXXXXX..XXXXXXX 100644
71
-
40
--- a/hw/arm/versatilepb.c
72
- if (*pinterp_name) {
41
+++ b/hw/arm/versatilepb.c
73
- errmsg = "Multiple PT_INTERP entries";
42
@@ -XXX,XX +XXX,XX @@
74
- goto exit_errmsg;
43
#include "sysemu/sysemu.h"
75
- }
44
#include "hw/pci/pci.h"
76
- interp_name = g_malloc(eppnt->p_filesz);
45
#include "hw/i2c/i2c.h"
77
- if (!interp_name) {
46
+#include "hw/i2c/arm_sbcon_i2c.h"
78
- goto exit_perror;
47
#include "hw/irq.h"
79
- }
48
#include "hw/boards.h"
80
-
49
#include "exec/address-spaces.h"
81
- if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) {
50
@@ -XXX,XX +XXX,XX @@ static void versatile_init(MachineState *machine, int board_id)
82
- memcpy(interp_name, bprm_buf + eppnt->p_offset,
51
/* Add PL031 Real Time Clock. */
83
- eppnt->p_filesz);
52
sysbus_create_simple("pl031", 0x101e8000, pic[10]);
84
- } else {
53
85
- retval = pread(image_fd, interp_name, eppnt->p_filesz,
54
- dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
86
- eppnt->p_offset);
55
+ dev = sysbus_create_simple(TYPE_VERSATILE_I2C, 0x10002000, NULL);
87
- if (retval != eppnt->p_filesz) {
56
i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
88
- goto exit_perror;
57
i2c_create_slave(i2c, "ds1338", 0x68);
89
- }
58
90
- }
59
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
91
- if (interp_name[eppnt->p_filesz - 1] != 0) {
60
index XXXXXXX..XXXXXXX 100644
92
- errmsg = "Invalid PT_INTERP entry";
61
--- a/hw/arm/vexpress.c
93
- goto exit_errmsg;
62
+++ b/hw/arm/vexpress.c
94
- }
63
@@ -XXX,XX +XXX,XX @@
95
- *pinterp_name = g_steal_pointer(&interp_name);
64
#include "hw/char/pl011.h"
96
#ifdef TARGET_MIPS
65
#include "hw/cpu/a9mpcore.h"
97
} else if (eppnt->p_type == PT_MIPS_ABIFLAGS) {
66
#include "hw/cpu/a15mpcore.h"
98
Mips_elf_abiflags_v0 abiflags;
67
+#include "hw/i2c/arm_sbcon_i2c.h"
68
69
#define VEXPRESS_BOARD_ID 0x8e0
70
#define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
71
@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
72
sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
73
sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
74
75
- dev = sysbus_create_simple("versatile_i2c", map[VE_SERIALDVI], NULL);
76
+ dev = sysbus_create_simple(TYPE_VERSATILE_I2C, map[VE_SERIALDVI], NULL);
77
i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
78
i2c_create_slave(i2c, "sii9022", 0x39);
79
80
--
99
--
81
2.20.1
100
2.20.1
82
101
83
102
diff view generated by jsdifflib
1
Convert the VSHLL insn in the 2-reg-misc Neon group to decodetree.
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This is a bit clearer than open-coding some of this
4
with a bare c string.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201021173749.111103-9-richard.henderson@linaro.org
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200616170844.13318-6-peter.maydell@linaro.org
6
---
10
---
7
target/arm/neon-dp.decode | 2 ++
11
linux-user/elfload.c | 37 ++++++++++++++++++++-----------------
8
target/arm/translate-neon.inc.c | 52 +++++++++++++++++++++++++++++++++
12
1 file changed, 20 insertions(+), 17 deletions(-)
9
target/arm/translate.c | 35 +---------------------
10
3 files changed, 55 insertions(+), 34 deletions(-)
11
13
12
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
14
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
13
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/neon-dp.decode
16
--- a/linux-user/elfload.c
15
+++ b/target/arm/neon-dp.decode
17
+++ b/linux-user/elfload.c
16
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
18
@@ -XXX,XX +XXX,XX @@
17
# VQMOVN: signed result, source may be signed (_S) or unsigned (_U)
19
#include "qemu/guest-random.h"
18
VQMOVN_S 1111 001 11 . 11 .. 10 .... 0 0101 0 . 0 .... @2misc_q0
20
#include "qemu/units.h"
19
VQMOVN_U 1111 001 11 . 11 .. 10 .... 0 0101 1 . 0 .... @2misc_q0
21
#include "qemu/selfmap.h"
22
+#include "qapi/error.h"
23
24
#ifdef _ARCH_PPC64
25
#undef ARCH_DLINFO
26
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
27
struct elf_phdr *phdr;
28
abi_ulong load_addr, load_bias, loaddr, hiaddr, error;
29
int i, retval;
30
- const char *errmsg;
31
+ Error *err = NULL;
32
33
/* First of all, some simple consistency checks */
34
- errmsg = "Invalid ELF image for this architecture";
35
if (!elf_check_ident(ehdr)) {
36
+ error_setg(&err, "Invalid ELF image for this architecture");
37
goto exit_errmsg;
38
}
39
bswap_ehdr(ehdr);
40
if (!elf_check_ehdr(ehdr)) {
41
+ error_setg(&err, "Invalid ELF image for this architecture");
42
goto exit_errmsg;
43
}
44
45
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
46
g_autofree char *interp_name = NULL;
47
48
if (*pinterp_name) {
49
- errmsg = "Multiple PT_INTERP entries";
50
+ error_setg(&err, "Multiple PT_INTERP entries");
51
goto exit_errmsg;
52
}
20
+
53
+
21
+ VSHLL 1111 001 11 . 11 .. 10 .... 0 0110 0 . 0 .... @2misc_q0
54
interp_name = g_malloc(eppnt->p_filesz);
22
]
55
- if (!interp_name) {
23
56
- goto exit_perror;
24
# Subgroup for size != 0b11
57
- }
25
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
58
26
index XXXXXXX..XXXXXXX 100644
59
if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) {
27
--- a/target/arm/translate-neon.inc.c
60
memcpy(interp_name, bprm_buf + eppnt->p_offset,
28
+++ b/target/arm/translate-neon.inc.c
61
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
29
@@ -XXX,XX +XXX,XX @@ DO_VMOVN(VMOVN, gen_neon_narrow_u)
62
retval = pread(image_fd, interp_name, eppnt->p_filesz,
30
DO_VMOVN(VQMOVUN, gen_helper_neon_unarrow_sat)
63
eppnt->p_offset);
31
DO_VMOVN(VQMOVN_S, gen_helper_neon_narrow_sat_s)
64
if (retval != eppnt->p_filesz) {
32
DO_VMOVN(VQMOVN_U, gen_helper_neon_narrow_sat_u)
65
- goto exit_perror;
33
+
66
+ goto exit_read;
34
+static bool trans_VSHLL(DisasContext *s, arg_2misc *a)
67
}
35
+{
68
}
36
+ TCGv_i32 rm0, rm1;
69
if (interp_name[eppnt->p_filesz - 1] != 0) {
37
+ TCGv_i64 rd;
70
- errmsg = "Invalid PT_INTERP entry";
38
+ static NeonGenWidenFn * const widenfns[] = {
71
+ error_setg(&err, "Invalid PT_INTERP entry");
39
+ gen_helper_neon_widen_u8,
72
goto exit_errmsg;
40
+ gen_helper_neon_widen_u16,
73
}
41
+ tcg_gen_extu_i32_i64,
74
*pinterp_name = g_steal_pointer(&interp_name);
42
+ NULL,
75
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
43
+ };
76
(ehdr->e_type == ET_EXEC ? MAP_FIXED : 0),
44
+ NeonGenWidenFn *widenfn = widenfns[a->size];
77
-1, 0);
45
+
78
if (load_addr == -1) {
46
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
79
- goto exit_perror;
47
+ return false;
80
+ goto exit_mmap;
48
+ }
81
}
49
+
82
load_bias = load_addr - loaddr;
50
+ /* UNDEF accesses to D16-D31 if they don't exist. */
83
51
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
84
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
52
+ ((a->vd | a->vm) & 0x10)) {
85
image_fd, eppnt->p_offset - vaddr_po);
53
+ return false;
86
54
+ }
87
if (error == -1) {
55
+
88
- goto exit_perror;
56
+ if (a->vd & 1) {
89
+ goto exit_mmap;
57
+ return false;
90
}
58
+ }
91
}
59
+
92
60
+ if (!widenfn) {
93
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
61
+ return false;
94
} else if (eppnt->p_type == PT_MIPS_ABIFLAGS) {
62
+ }
95
Mips_elf_abiflags_v0 abiflags;
63
+
96
if (eppnt->p_filesz < sizeof(Mips_elf_abiflags_v0)) {
64
+ if (!vfp_access_check(s)) {
97
- errmsg = "Invalid PT_MIPS_ABIFLAGS entry";
65
+ return true;
98
+ error_setg(&err, "Invalid PT_MIPS_ABIFLAGS entry");
66
+ }
99
goto exit_errmsg;
67
+
100
}
68
+ rd = tcg_temp_new_i64();
101
if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) {
69
+
102
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
70
+ rm0 = neon_load_reg(a->vm, 0);
103
retval = pread(image_fd, &abiflags, sizeof(Mips_elf_abiflags_v0),
71
+ rm1 = neon_load_reg(a->vm, 1);
104
eppnt->p_offset);
72
+
105
if (retval != sizeof(Mips_elf_abiflags_v0)) {
73
+ widenfn(rd, rm0);
106
- goto exit_perror;
74
+ tcg_gen_shli_i64(rd, rd, 8 << a->size);
107
+ goto exit_read;
75
+ neon_store_reg64(rd, a->vd);
108
}
76
+ widenfn(rd, rm1);
109
}
77
+ tcg_gen_shli_i64(rd, rd, 8 << a->size);
110
bswap_mips_abiflags(&abiflags);
78
+ neon_store_reg64(rd, a->vd + 1);
111
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
79
+
112
80
+ tcg_temp_free_i64(rd);
113
exit_read:
81
+ tcg_temp_free_i32(rm0);
114
if (retval >= 0) {
82
+ tcg_temp_free_i32(rm1);
115
- errmsg = "Incomplete read of file header";
83
+ return true;
116
- goto exit_errmsg;
84
+}
117
+ error_setg(&err, "Incomplete read of file header");
85
diff --git a/target/arm/translate.c b/target/arm/translate.c
118
+ } else {
86
index XXXXXXX..XXXXXXX 100644
119
+ error_setg_errno(&err, errno, "Error reading file header");
87
--- a/target/arm/translate.c
120
}
88
+++ b/target/arm/translate.c
121
- exit_perror:
89
@@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
122
- errmsg = strerror(errno);
90
tcg_temp_free_i32(rd);
123
+ goto exit_errmsg;
124
+ exit_mmap:
125
+ error_setg_errno(&err, errno, "Error mapping file");
126
+ goto exit_errmsg;
127
exit_errmsg:
128
- fprintf(stderr, "%s: %s\n", image_name, errmsg);
129
+ error_reportf_err(err, "%s: ", image_name);
130
exit(-1);
91
}
131
}
92
132
93
-static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u)
94
-{
95
- if (u) {
96
- switch (size) {
97
- case 0: gen_helper_neon_widen_u8(dest, src); break;
98
- case 1: gen_helper_neon_widen_u16(dest, src); break;
99
- case 2: tcg_gen_extu_i32_i64(dest, src); break;
100
- default: abort();
101
- }
102
- } else {
103
- switch (size) {
104
- case 0: gen_helper_neon_widen_s8(dest, src); break;
105
- case 1: gen_helper_neon_widen_s16(dest, src); break;
106
- case 2: tcg_gen_ext_i32_i64(dest, src); break;
107
- default: abort();
108
- }
109
- }
110
- tcg_temp_free_i32(src);
111
-}
112
-
113
/* Symbolic constants for op fields for Neon 2-register miscellaneous.
114
* The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B
115
* table A7-13.
116
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
117
case NEON_2RM_VUZP:
118
case NEON_2RM_VZIP:
119
case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN:
120
+ case NEON_2RM_VSHLL:
121
/* handled by decodetree */
122
return 1;
123
case NEON_2RM_VTRN:
124
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
125
goto elementwise;
126
}
127
break;
128
- case NEON_2RM_VSHLL:
129
- if (q || (rd & 1)) {
130
- return 1;
131
- }
132
- tmp = neon_load_reg(rm, 0);
133
- tmp2 = neon_load_reg(rm, 1);
134
- for (pass = 0; pass < 2; pass++) {
135
- if (pass == 1)
136
- tmp = tmp2;
137
- gen_neon_widen(cpu_V0, tmp, size, 1);
138
- tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size);
139
- neon_store_reg64(cpu_V0, rd + pass);
140
- }
141
- break;
142
case NEON_2RM_VCVT_F16_F32:
143
{
144
TCGv_ptr fpst;
145
--
133
--
146
2.20.1
134
2.20.1
147
135
148
136
diff view generated by jsdifflib
1
All the other typedefs like these spell "Op" with a lowercase 'p';
1
From: Richard Henderson <richard.henderson@linaro.org>
2
remane the NeonGenTwoSingleOPFn and NeonGenTwoDoubleOPFn typedefs to
3
match.
4
2
3
This is slightly clearer than just using strerror, though
4
the different forms produced by error_setg_file_open and
5
error_setg_errno isn't entirely convenient.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201021173749.111103-10-richard.henderson@linaro.org
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200616170844.13318-11-peter.maydell@linaro.org
8
---
11
---
9
target/arm/translate.h | 4 ++--
12
linux-user/elfload.c | 15 ++++++++-------
10
target/arm/translate-a64.c | 4 ++--
13
1 file changed, 8 insertions(+), 7 deletions(-)
11
target/arm/translate-neon.inc.c | 2 +-
12
3 files changed, 5 insertions(+), 5 deletions(-)
13
14
14
diff --git a/target/arm/translate.h b/target/arm/translate.h
15
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.h
17
--- a/linux-user/elfload.c
17
+++ b/target/arm/translate.h
18
+++ b/linux-user/elfload.c
18
@@ -XXX,XX +XXX,XX @@ typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
19
@@ -XXX,XX +XXX,XX @@ static void load_elf_interp(const char *filename, struct image_info *info,
19
typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
20
char bprm_buf[BPRM_BUF_SIZE])
20
typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
21
{
21
typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
22
int fd, retval;
22
-typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
23
+ Error *err = NULL;
23
-typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
24
24
+typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
25
fd = open(path(filename), O_RDONLY);
25
+typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
26
if (fd < 0) {
26
typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
27
- goto exit_perror;
27
typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
28
+ error_setg_file_open(&err, errno, filename);
28
typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
29
+ error_report_err(err);
29
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
30
+ exit(-1);
30
index XXXXXXX..XXXXXXX 100644
31
}
31
--- a/target/arm/translate-a64.c
32
32
+++ b/target/arm/translate-a64.c
33
retval = read(fd, bprm_buf, BPRM_BUF_SIZE);
33
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
34
if (retval < 0) {
34
TCGv_i64 tcg_op = tcg_temp_new_i64();
35
- goto exit_perror;
35
TCGv_i64 tcg_zero = tcg_const_i64(0);
36
+ error_setg_errno(&err, errno, "Error reading file header");
36
TCGv_i64 tcg_res = tcg_temp_new_i64();
37
+ error_reportf_err(err, "%s: ", filename);
37
- NeonGenTwoDoubleOPFn *genfn;
38
+ exit(-1);
38
+ NeonGenTwoDoubleOpFn *genfn;
39
}
39
bool swap = false;
40
+
40
int pass;
41
if (retval < BPRM_BUF_SIZE) {
41
42
memset(bprm_buf + retval, 0, BPRM_BUF_SIZE - retval);
42
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
43
}
43
TCGv_i32 tcg_op = tcg_temp_new_i32();
44
44
TCGv_i32 tcg_zero = tcg_const_i32(0);
45
load_elf_image(filename, fd, info, NULL, bprm_buf);
45
TCGv_i32 tcg_res = tcg_temp_new_i32();
46
- return;
46
- NeonGenTwoSingleOPFn *genfn;
47
-
47
+ NeonGenTwoSingleOpFn *genfn;
48
- exit_perror:
48
bool swap = false;
49
- fprintf(stderr, "%s: %s\n", filename, strerror(errno));
49
int pass, maxpasses;
50
- exit(-1);
50
51
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/translate-neon.inc.c
54
+++ b/target/arm/translate-neon.inc.c
55
@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a)
56
}
51
}
57
52
58
static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
53
static int symfind(const void *s0, const void *s1)
59
- NeonGenTwoSingleOPFn *fn)
60
+ NeonGenTwoSingleOpFn *fn)
61
{
62
/* FP operations in 2-reg-and-shift group */
63
TCGv_i32 tmp, shiftv;
64
--
54
--
65
2.20.1
55
2.20.1
66
56
67
57
diff view generated by jsdifflib
1
Convert the Neon 2-reg-misc insns which are implemented with
1
From: Richard Henderson <richard.henderson@linaro.org>
2
simple calls to functions that take the input, output and
2
3
fpstatus pointer.
3
This is generic support, with the code disabled for all targets.
4
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20201021173749.111103-11-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200616170844.13318-16-peter.maydell@linaro.org
8
---
9
---
9
target/arm/translate.h | 1 +
10
linux-user/qemu.h | 4 ++
10
target/arm/neon-dp.decode | 8 +++++
11
linux-user/elfload.c | 157 +++++++++++++++++++++++++++++++++++++++++++
11
target/arm/translate-neon.inc.c | 62 +++++++++++++++++++++++++++++++++
12
2 files changed, 161 insertions(+)
12
target/arm/translate.c | 56 ++++-------------------------
13
13
4 files changed, 78 insertions(+), 49 deletions(-)
14
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
14
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.h
16
--- a/linux-user/qemu.h
18
+++ b/target/arm/translate.h
17
+++ b/linux-user/qemu.h
19
@@ -XXX,XX +XXX,XX @@ typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
18
@@ -XXX,XX +XXX,XX @@ struct image_info {
20
typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
19
abi_ulong interpreter_loadmap_addr;
21
typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
20
abi_ulong interpreter_pt_dynamic_addr;
22
typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
21
struct image_info *other_info;
23
+typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr);
22
+
24
typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
23
+ /* For target-specific processing of NT_GNU_PROPERTY_TYPE_0. */
25
typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
24
+ uint32_t note_flags;
26
typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
25
+
27
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
26
#ifdef TARGET_MIPS
27
int fp_abi;
28
int interp_fp_abi;
29
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
28
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/neon-dp.decode
31
--- a/linux-user/elfload.c
30
+++ b/target/arm/neon-dp.decode
32
+++ b/linux-user/elfload.c
31
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
33
@@ -XXX,XX +XXX,XX @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
32
SHA1SU1 1111 001 11 . 11 .. 10 .... 0 0111 0 . 0 .... @2misc_q1
34
33
SHA256SU0 1111 001 11 . 11 .. 10 .... 0 0111 1 . 0 .... @2misc_q1
35
#include "elf.h"
34
36
35
+ VRINTX 1111 001 11 . 11 .. 10 .... 0 1001 . . 0 .... @2misc
37
+static bool arch_parse_elf_property(uint32_t pr_type, uint32_t pr_datasz,
36
+
38
+ const uint32_t *data,
37
VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0
39
+ struct image_info *info,
38
VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0
40
+ Error **errp)
39
41
+{
40
VRECPE 1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc
42
+ g_assert_not_reached();
41
VRSQRTE 1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc
43
+}
42
+ VRECPE_F 1111 001 11 . 11 .. 11 .... 0 1010 . . 0 .... @2misc
44
+#define ARCH_USE_GNU_PROPERTY 0
43
+ VRSQRTE_F 1111 001 11 . 11 .. 11 .... 0 1011 . . 0 .... @2misc
45
+
44
+ VCVT_FS 1111 001 11 . 11 .. 11 .... 0 1100 . . 0 .... @2misc
46
struct exec
45
+ VCVT_FU 1111 001 11 . 11 .. 11 .... 0 1101 . . 0 .... @2misc
47
{
46
+ VCVT_SF 1111 001 11 . 11 .. 11 .... 0 1110 . . 0 .... @2misc
48
unsigned int a_info; /* Use macros N_MAGIC, etc for access */
47
+ VCVT_UF 1111 001 11 . 11 .. 11 .... 0 1111 . . 0 .... @2misc
49
@@ -XXX,XX +XXX,XX @@ void probe_guest_base(const char *image_name, abi_ulong guest_loaddr,
48
]
50
"@ 0x%" PRIx64 "\n", (uint64_t)guest_base);
49
50
# Subgroup for size != 0b11
51
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/translate-neon.inc.c
54
+++ b/target/arm/translate-neon.inc.c
55
@@ -XXX,XX +XXX,XX @@ static bool trans_VQNEG(DisasContext *s, arg_2misc *a)
56
};
57
return do_2misc(s, a, fn[a->size]);
58
}
51
}
59
+
52
60
+static bool do_2misc_fp(DisasContext *s, arg_2misc *a,
53
+enum {
61
+ NeonGenOneSingleOpFn *fn)
54
+ /* The string "GNU\0" as a magic number. */
55
+ GNU0_MAGIC = const_le32('G' | 'N' << 8 | 'U' << 16),
56
+ NOTE_DATA_SZ = 1 * KiB,
57
+ NOTE_NAME_SZ = 4,
58
+ ELF_GNU_PROPERTY_ALIGN = ELF_CLASS == ELFCLASS32 ? 4 : 8,
59
+};
60
+
61
+/*
62
+ * Process a single gnu_property entry.
63
+ * Return false for error.
64
+ */
65
+static bool parse_elf_property(const uint32_t *data, int *off, int datasz,
66
+ struct image_info *info, bool have_prev_type,
67
+ uint32_t *prev_type, Error **errp)
62
+{
68
+{
63
+ int pass;
69
+ uint32_t pr_type, pr_datasz, step;
64
+ TCGv_ptr fpst;
70
+
65
+
71
+ if (*off > datasz || !QEMU_IS_ALIGNED(*off, ELF_GNU_PROPERTY_ALIGN)) {
66
+ /* Handle a 2-reg-misc operation by iterating 32 bits at a time */
72
+ goto error_data;
67
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
73
+ }
68
+ return false;
74
+ datasz -= *off;
69
+ }
75
+ data += *off / sizeof(uint32_t);
70
+
76
+
71
+ /* UNDEF accesses to D16-D31 if they don't exist. */
77
+ if (datasz < 2 * sizeof(uint32_t)) {
72
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
78
+ goto error_data;
73
+ ((a->vd | a->vm) & 0x10)) {
79
+ }
74
+ return false;
80
+ pr_type = data[0];
75
+ }
81
+ pr_datasz = data[1];
76
+
82
+ data += 2;
77
+ if (a->size != 2) {
83
+ datasz -= 2 * sizeof(uint32_t);
78
+ /* TODO: FP16 will be the size == 1 case */
84
+ step = ROUND_UP(pr_datasz, ELF_GNU_PROPERTY_ALIGN);
79
+ return false;
85
+ if (step > datasz) {
80
+ }
86
+ goto error_data;
81
+
87
+ }
82
+ if ((a->vd | a->vm) & a->q) {
88
+
83
+ return false;
89
+ /* Properties are supposed to be unique and sorted on pr_type. */
84
+ }
90
+ if (have_prev_type && pr_type <= *prev_type) {
85
+
91
+ if (pr_type == *prev_type) {
86
+ if (!vfp_access_check(s)) {
92
+ error_setg(errp, "Duplicate property in PT_GNU_PROPERTY");
93
+ } else {
94
+ error_setg(errp, "Unsorted property in PT_GNU_PROPERTY");
95
+ }
96
+ return false;
97
+ }
98
+ *prev_type = pr_type;
99
+
100
+ if (!arch_parse_elf_property(pr_type, pr_datasz, data, info, errp)) {
101
+ return false;
102
+ }
103
+
104
+ *off += 2 * sizeof(uint32_t) + step;
105
+ return true;
106
+
107
+ error_data:
108
+ error_setg(errp, "Ill-formed property in PT_GNU_PROPERTY");
109
+ return false;
110
+}
111
+
112
+/* Process NT_GNU_PROPERTY_TYPE_0. */
113
+static bool parse_elf_properties(int image_fd,
114
+ struct image_info *info,
115
+ const struct elf_phdr *phdr,
116
+ char bprm_buf[BPRM_BUF_SIZE],
117
+ Error **errp)
118
+{
119
+ union {
120
+ struct elf_note nhdr;
121
+ uint32_t data[NOTE_DATA_SZ / sizeof(uint32_t)];
122
+ } note;
123
+
124
+ int n, off, datasz;
125
+ bool have_prev_type;
126
+ uint32_t prev_type;
127
+
128
+ /* Unless the arch requires properties, ignore them. */
129
+ if (!ARCH_USE_GNU_PROPERTY) {
87
+ return true;
130
+ return true;
88
+ }
131
+ }
89
+
132
+
90
+ fpst = get_fpstatus_ptr(1);
133
+ /* If the properties are crazy large, that's too bad. */
91
+ for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
134
+ n = phdr->p_filesz;
92
+ TCGv_i32 tmp = neon_load_reg(a->vm, pass);
135
+ if (n > sizeof(note)) {
93
+ fn(tmp, tmp, fpst);
136
+ error_setg(errp, "PT_GNU_PROPERTY too large");
94
+ neon_store_reg(a->vd, pass, tmp);
137
+ return false;
95
+ }
138
+ }
96
+ tcg_temp_free_ptr(fpst);
139
+ if (n < sizeof(note.nhdr)) {
97
+
140
+ error_setg(errp, "PT_GNU_PROPERTY too small");
98
+ return true;
141
+ return false;
142
+ }
143
+
144
+ if (phdr->p_offset + n <= BPRM_BUF_SIZE) {
145
+ memcpy(&note, bprm_buf + phdr->p_offset, n);
146
+ } else {
147
+ ssize_t len = pread(image_fd, &note, n, phdr->p_offset);
148
+ if (len != n) {
149
+ error_setg_errno(errp, errno, "Error reading file header");
150
+ return false;
151
+ }
152
+ }
153
+
154
+ /*
155
+ * The contents of a valid PT_GNU_PROPERTY is a sequence
156
+ * of uint32_t -- swap them all now.
157
+ */
158
+#ifdef BSWAP_NEEDED
159
+ for (int i = 0; i < n / 4; i++) {
160
+ bswap32s(note.data + i);
161
+ }
162
+#endif
163
+
164
+ /*
165
+ * Note that nhdr is 3 words, and that the "name" described by namesz
166
+ * immediately follows nhdr and is thus at the 4th word. Further, all
167
+ * of the inputs to the kernel's round_up are multiples of 4.
168
+ */
169
+ if (note.nhdr.n_type != NT_GNU_PROPERTY_TYPE_0 ||
170
+ note.nhdr.n_namesz != NOTE_NAME_SZ ||
171
+ note.data[3] != GNU0_MAGIC) {
172
+ error_setg(errp, "Invalid note in PT_GNU_PROPERTY");
173
+ return false;
174
+ }
175
+ off = sizeof(note.nhdr) + NOTE_NAME_SZ;
176
+
177
+ datasz = note.nhdr.n_descsz + off;
178
+ if (datasz > n) {
179
+ error_setg(errp, "Invalid note size in PT_GNU_PROPERTY");
180
+ return false;
181
+ }
182
+
183
+ have_prev_type = false;
184
+ prev_type = 0;
185
+ while (1) {
186
+ if (off == datasz) {
187
+ return true; /* end, exit ok */
188
+ }
189
+ if (!parse_elf_property(note.data, &off, datasz, info,
190
+ have_prev_type, &prev_type, errp)) {
191
+ return false;
192
+ }
193
+ have_prev_type = true;
194
+ }
99
+}
195
+}
100
+
196
+
101
+#define DO_2MISC_FP(INSN, FUNC) \
197
/* Load an ELF image into the address space.
102
+ static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
198
103
+ { \
199
IMAGE_NAME is the filename of the image, to use in error messages.
104
+ return do_2misc_fp(s, a, FUNC); \
200
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
105
+ }
201
goto exit_errmsg;
106
+
202
}
107
+DO_2MISC_FP(VRECPE_F, gen_helper_recpe_f32)
203
*pinterp_name = g_steal_pointer(&interp_name);
108
+DO_2MISC_FP(VRSQRTE_F, gen_helper_rsqrte_f32)
204
+ } else if (eppnt->p_type == PT_GNU_PROPERTY) {
109
+DO_2MISC_FP(VCVT_FS, gen_helper_vfp_sitos)
205
+ if (!parse_elf_properties(image_fd, info, eppnt, bprm_buf, &err)) {
110
+DO_2MISC_FP(VCVT_FU, gen_helper_vfp_uitos)
206
+ goto exit_errmsg;
111
+DO_2MISC_FP(VCVT_SF, gen_helper_vfp_tosizs)
207
+ }
112
+DO_2MISC_FP(VCVT_UF, gen_helper_vfp_touizs)
208
}
113
+
209
}
114
+static bool trans_VRINTX(DisasContext *s, arg_2misc *a)
210
115
+{
116
+ if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
117
+ return false;
118
+ }
119
+ return do_2misc_fp(s, a, gen_helper_rints_exact);
120
+}
121
diff --git a/target/arm/translate.c b/target/arm/translate.c
122
index XXXXXXX..XXXXXXX 100644
123
--- a/target/arm/translate.c
124
+++ b/target/arm/translate.c
125
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
126
case NEON_2RM_VRSQRTE:
127
case NEON_2RM_VQABS:
128
case NEON_2RM_VQNEG:
129
+ case NEON_2RM_VRECPE_F:
130
+ case NEON_2RM_VRSQRTE_F:
131
+ case NEON_2RM_VCVT_FS:
132
+ case NEON_2RM_VCVT_FU:
133
+ case NEON_2RM_VCVT_SF:
134
+ case NEON_2RM_VCVT_UF:
135
+ case NEON_2RM_VRINTX:
136
/* handled by decodetree */
137
return 1;
138
case NEON_2RM_VTRN:
139
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
140
tcg_temp_free_i32(tcg_rmode);
141
break;
142
}
143
- case NEON_2RM_VRINTX:
144
- {
145
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
146
- gen_helper_rints_exact(tmp, tmp, fpstatus);
147
- tcg_temp_free_ptr(fpstatus);
148
- break;
149
- }
150
case NEON_2RM_VCVTAU:
151
case NEON_2RM_VCVTAS:
152
case NEON_2RM_VCVTNU:
153
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
154
tcg_temp_free_ptr(fpst);
155
break;
156
}
157
- case NEON_2RM_VRECPE_F:
158
- {
159
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
160
- gen_helper_recpe_f32(tmp, tmp, fpstatus);
161
- tcg_temp_free_ptr(fpstatus);
162
- break;
163
- }
164
- case NEON_2RM_VRSQRTE_F:
165
- {
166
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
167
- gen_helper_rsqrte_f32(tmp, tmp, fpstatus);
168
- tcg_temp_free_ptr(fpstatus);
169
- break;
170
- }
171
- case NEON_2RM_VCVT_FS: /* VCVT.F32.S32 */
172
- {
173
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
174
- gen_helper_vfp_sitos(tmp, tmp, fpstatus);
175
- tcg_temp_free_ptr(fpstatus);
176
- break;
177
- }
178
- case NEON_2RM_VCVT_FU: /* VCVT.F32.U32 */
179
- {
180
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
181
- gen_helper_vfp_uitos(tmp, tmp, fpstatus);
182
- tcg_temp_free_ptr(fpstatus);
183
- break;
184
- }
185
- case NEON_2RM_VCVT_SF: /* VCVT.S32.F32 */
186
- {
187
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
188
- gen_helper_vfp_tosizs(tmp, tmp, fpstatus);
189
- tcg_temp_free_ptr(fpstatus);
190
- break;
191
- }
192
- case NEON_2RM_VCVT_UF: /* VCVT.U32.F32 */
193
- {
194
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
195
- gen_helper_vfp_touizs(tmp, tmp, fpstatus);
196
- tcg_temp_free_ptr(fpstatus);
197
- break;
198
- }
199
default:
200
/* Reserved op values were caught by the
201
* neon_2rm_sizes[] check earlier.
202
--
211
--
203
2.20.1
212
2.20.1
204
213
205
214
diff view generated by jsdifflib
1
Convert the Neon VREV64 insn from the 2-reg-misc grouping to decodetree.
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use the new generic support for NT_GNU_PROPERTY_TYPE_0.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20201021173749.111103-12-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200616170844.13318-2-peter.maydell@linaro.org
6
---
9
---
7
target/arm/neon-dp.decode | 12 ++++++++
10
linux-user/elfload.c | 48 ++++++++++++++++++++++++++++++++++++++++++--
8
target/arm/translate-neon.inc.c | 50 +++++++++++++++++++++++++++++++++
11
1 file changed, 46 insertions(+), 2 deletions(-)
9
target/arm/translate.c | 24 ++--------------
10
3 files changed, 64 insertions(+), 22 deletions(-)
11
12
12
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
13
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
13
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/neon-dp.decode
15
--- a/linux-user/elfload.c
15
+++ b/target/arm/neon-dp.decode
16
+++ b/linux-user/elfload.c
16
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
17
@@ -XXX,XX +XXX,XX @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
17
vm=%vm_dp vd=%vd_dp size=1
18
18
VDUP_scalar 1111 001 1 1 . 11 index:1 100 .... 11 000 q:1 . 0 .... \
19
#include "elf.h"
19
vm=%vm_dp vd=%vd_dp size=2
20
21
+/* We must delay the following stanzas until after "elf.h". */
22
+#if defined(TARGET_AARCH64)
20
+
23
+
21
+ ##################################################################
24
+static bool arch_parse_elf_property(uint32_t pr_type, uint32_t pr_datasz,
22
+ # 2-reg-misc grouping:
25
+ const uint32_t *data,
23
+ # 1111 001 11 D 11 size:2 opc1:2 Vd:4 0 opc2:4 q:1 M 0 Vm:4
26
+ struct image_info *info,
24
+ ##################################################################
27
+ Error **errp)
25
+
26
+ &2misc vd vm q size
27
+
28
+ @2misc .... ... .. . .. size:2 .. .... . .... q:1 . . .... \
29
+ &2misc vm=%vm_dp vd=%vd_dp
30
+
31
+ VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc
32
]
33
34
# Subgroup for size != 0b11
35
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/translate-neon.inc.c
38
+++ b/target/arm/translate-neon.inc.c
39
@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
40
a->q ? 16 : 8, a->q ? 16 : 8);
41
return true;
42
}
43
+
44
+static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
45
+{
28
+{
46
+ int pass, half;
29
+ if (pr_type == GNU_PROPERTY_AARCH64_FEATURE_1_AND) {
47
+
30
+ if (pr_datasz != sizeof(uint32_t)) {
48
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
31
+ error_setg(errp, "Ill-formed GNU_PROPERTY_AARCH64_FEATURE_1_AND");
49
+ return false;
32
+ return false;
50
+ }
51
+
52
+ /* UNDEF accesses to D16-D31 if they don't exist. */
53
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
54
+ ((a->vd | a->vm) & 0x10)) {
55
+ return false;
56
+ }
57
+
58
+ if ((a->vd | a->vm) & a->q) {
59
+ return false;
60
+ }
61
+
62
+ if (a->size == 3) {
63
+ return false;
64
+ }
65
+
66
+ if (!vfp_access_check(s)) {
67
+ return true;
68
+ }
69
+
70
+ for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
71
+ TCGv_i32 tmp[2];
72
+
73
+ for (half = 0; half < 2; half++) {
74
+ tmp[half] = neon_load_reg(a->vm, pass * 2 + half);
75
+ switch (a->size) {
76
+ case 0:
77
+ tcg_gen_bswap32_i32(tmp[half], tmp[half]);
78
+ break;
79
+ case 1:
80
+ gen_swap_half(tmp[half]);
81
+ break;
82
+ case 2:
83
+ break;
84
+ default:
85
+ g_assert_not_reached();
86
+ }
87
+ }
33
+ }
88
+ neon_store_reg(a->vd, pass * 2, tmp[1]);
34
+ /* We will extract GNU_PROPERTY_AARCH64_FEATURE_1_BTI later. */
89
+ neon_store_reg(a->vd, pass * 2 + 1, tmp[0]);
35
+ info->note_flags = *data;
90
+ }
36
+ }
91
+ return true;
37
+ return true;
92
+}
38
+}
93
diff --git a/target/arm/translate.c b/target/arm/translate.c
39
+#define ARCH_USE_GNU_PROPERTY 1
94
index XXXXXXX..XXXXXXX 100644
40
+
95
--- a/target/arm/translate.c
41
+#else
96
+++ b/target/arm/translate.c
42
+
97
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
43
static bool arch_parse_elf_property(uint32_t pr_type, uint32_t pr_datasz,
98
}
44
const uint32_t *data,
99
switch (op) {
45
struct image_info *info,
100
case NEON_2RM_VREV64:
46
@@ -XXX,XX +XXX,XX @@ static bool arch_parse_elf_property(uint32_t pr_type, uint32_t pr_datasz,
101
- for (pass = 0; pass < (q ? 2 : 1); pass++) {
47
}
102
- tmp = neon_load_reg(rm, pass * 2);
48
#define ARCH_USE_GNU_PROPERTY 0
103
- tmp2 = neon_load_reg(rm, pass * 2 + 1);
49
104
- switch (size) {
50
+#endif
105
- case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
51
+
106
- case 1: gen_swap_half(tmp); break;
52
struct exec
107
- case 2: /* no-op */ break;
53
{
108
- default: abort();
54
unsigned int a_info; /* Use macros N_MAGIC, etc for access */
109
- }
55
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
110
- neon_store_reg(rd, pass * 2 + 1, tmp);
56
struct elfhdr *ehdr = (struct elfhdr *)bprm_buf;
111
- if (size == 2) {
57
struct elf_phdr *phdr;
112
- neon_store_reg(rd, pass * 2, tmp2);
58
abi_ulong load_addr, load_bias, loaddr, hiaddr, error;
113
- } else {
59
- int i, retval;
114
- switch (size) {
60
+ int i, retval, prot_exec;
115
- case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
61
Error *err = NULL;
116
- case 1: gen_swap_half(tmp2); break;
62
117
- default: abort();
63
/* First of all, some simple consistency checks */
118
- }
64
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
119
- neon_store_reg(rd, pass * 2, tmp2);
65
info->brk = 0;
120
- }
66
info->elf_flags = ehdr->e_flags;
121
- }
67
122
- break;
68
+ prot_exec = PROT_EXEC;
123
+ /* handled by decodetree */
69
+#ifdef TARGET_AARCH64
124
+ return 1;
70
+ /*
125
case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U:
71
+ * If the BTI feature is present, this indicates that the executable
126
case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U:
72
+ * pages of the startup binary should be mapped with PROT_BTI, so that
127
for (pass = 0; pass < q + 1; pass++) {
73
+ * branch targets are enforced.
74
+ *
75
+ * The startup binary is either the interpreter or the static executable.
76
+ * The interpreter is responsible for all pages of a dynamic executable.
77
+ *
78
+ * Elf notes are backward compatible to older cpus.
79
+ * Do not enable BTI unless it is supported.
80
+ */
81
+ if ((info->note_flags & GNU_PROPERTY_AARCH64_FEATURE_1_BTI)
82
+ && (pinterp_name == NULL || *pinterp_name == 0)
83
+ && cpu_isar_feature(aa64_bti, ARM_CPU(thread_cpu))) {
84
+ prot_exec |= TARGET_PROT_BTI;
85
+ }
86
+#endif
87
+
88
for (i = 0; i < ehdr->e_phnum; i++) {
89
struct elf_phdr *eppnt = phdr + i;
90
if (eppnt->p_type == PT_LOAD) {
91
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
92
elf_prot |= PROT_WRITE;
93
}
94
if (eppnt->p_flags & PF_X) {
95
- elf_prot |= PROT_EXEC;
96
+ elf_prot |= prot_exec;
97
}
98
99
vaddr = load_bias + eppnt->p_vaddr;
128
--
100
--
129
2.20.1
101
2.20.1
130
102
131
103
diff view generated by jsdifflib
1
Make gen_swap_half() take a source and destination TCGv_i32 rather
1
From: Richard Henderson <richard.henderson@linaro.org>
2
than modifying the input TCGv_i32; we're going to want to be able to
2
3
use it with the more flexible function signature, and this also
3
The note test requires gcc 10 for -mbranch-protection=standard.
4
brings it into line with other functions like gen_rev16() and
4
The mmap test uses PROT_BTI and does not require special compiler support.
5
gen_revsh().
5
6
6
Acked-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20201021173749.111103-13-richard.henderson@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200616170844.13318-12-peter.maydell@linaro.org
10
---
11
---
11
target/arm/translate-neon.inc.c | 2 +-
12
tests/tcg/aarch64/bti-1.c | 62 ++++++++++++++++
12
target/arm/translate.c | 10 +++++-----
13
tests/tcg/aarch64/bti-2.c | 116 ++++++++++++++++++++++++++++++
13
2 files changed, 6 insertions(+), 6 deletions(-)
14
tests/tcg/aarch64/bti-crt.inc.c | 51 +++++++++++++
14
15
tests/tcg/aarch64/Makefile.target | 10 +++
15
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
16
tests/tcg/configure.sh | 4 ++
17
5 files changed, 243 insertions(+)
18
create mode 100644 tests/tcg/aarch64/bti-1.c
19
create mode 100644 tests/tcg/aarch64/bti-2.c
20
create mode 100644 tests/tcg/aarch64/bti-crt.inc.c
21
22
diff --git a/tests/tcg/aarch64/bti-1.c b/tests/tcg/aarch64/bti-1.c
23
new file mode 100644
24
index XXXXXXX..XXXXXXX
25
--- /dev/null
26
+++ b/tests/tcg/aarch64/bti-1.c
27
@@ -XXX,XX +XXX,XX @@
28
+/*
29
+ * Branch target identification, basic notskip cases.
30
+ */
31
+
32
+#include "bti-crt.inc.c"
33
+
34
+static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc)
35
+{
36
+ uc->uc_mcontext.pc += 8;
37
+ uc->uc_mcontext.pstate = 1;
38
+}
39
+
40
+#define NOP "nop"
41
+#define BTI_N "hint #32"
42
+#define BTI_C "hint #34"
43
+#define BTI_J "hint #36"
44
+#define BTI_JC "hint #38"
45
+
46
+#define BTYPE_1(DEST) \
47
+ asm("mov %0,#1; adr x16, 1f; br x16; 1: " DEST "; mov %0,#0" \
48
+ : "=r"(skipped) : : "x16")
49
+
50
+#define BTYPE_2(DEST) \
51
+ asm("mov %0,#1; adr x16, 1f; blr x16; 1: " DEST "; mov %0,#0" \
52
+ : "=r"(skipped) : : "x16", "x30")
53
+
54
+#define BTYPE_3(DEST) \
55
+ asm("mov %0,#1; adr x15, 1f; br x15; 1: " DEST "; mov %0,#0" \
56
+ : "=r"(skipped) : : "x15")
57
+
58
+#define TEST(WHICH, DEST, EXPECT) \
59
+ do { WHICH(DEST); fail += skipped ^ EXPECT; } while (0)
60
+
61
+
62
+int main()
63
+{
64
+ int fail = 0;
65
+ int skipped;
66
+
67
+ /* Signal-like with SA_SIGINFO. */
68
+ signal_info(SIGILL, skip2_sigill);
69
+
70
+ TEST(BTYPE_1, NOP, 1);
71
+ TEST(BTYPE_1, BTI_N, 1);
72
+ TEST(BTYPE_1, BTI_C, 0);
73
+ TEST(BTYPE_1, BTI_J, 0);
74
+ TEST(BTYPE_1, BTI_JC, 0);
75
+
76
+ TEST(BTYPE_2, NOP, 1);
77
+ TEST(BTYPE_2, BTI_N, 1);
78
+ TEST(BTYPE_2, BTI_C, 0);
79
+ TEST(BTYPE_2, BTI_J, 1);
80
+ TEST(BTYPE_2, BTI_JC, 0);
81
+
82
+ TEST(BTYPE_3, NOP, 1);
83
+ TEST(BTYPE_3, BTI_N, 1);
84
+ TEST(BTYPE_3, BTI_C, 1);
85
+ TEST(BTYPE_3, BTI_J, 0);
86
+ TEST(BTYPE_3, BTI_JC, 0);
87
+
88
+ return fail;
89
+}
90
diff --git a/tests/tcg/aarch64/bti-2.c b/tests/tcg/aarch64/bti-2.c
91
new file mode 100644
92
index XXXXXXX..XXXXXXX
93
--- /dev/null
94
+++ b/tests/tcg/aarch64/bti-2.c
95
@@ -XXX,XX +XXX,XX @@
96
+/*
97
+ * Branch target identification, basic notskip cases.
98
+ */
99
+
100
+#include <stdio.h>
101
+#include <signal.h>
102
+#include <string.h>
103
+#include <unistd.h>
104
+#include <sys/mman.h>
105
+
106
+#ifndef PROT_BTI
107
+#define PROT_BTI 0x10
108
+#endif
109
+
110
+static void skip2_sigill(int sig, siginfo_t *info, void *vuc)
111
+{
112
+ ucontext_t *uc = vuc;
113
+ uc->uc_mcontext.pc += 8;
114
+ uc->uc_mcontext.pstate = 1;
115
+}
116
+
117
+#define NOP "nop"
118
+#define BTI_N "hint #32"
119
+#define BTI_C "hint #34"
120
+#define BTI_J "hint #36"
121
+#define BTI_JC "hint #38"
122
+
123
+#define BTYPE_1(DEST) \
124
+ "mov x1, #1\n\t" \
125
+ "adr x16, 1f\n\t" \
126
+ "br x16\n" \
127
+"1: " DEST "\n\t" \
128
+ "mov x1, #0"
129
+
130
+#define BTYPE_2(DEST) \
131
+ "mov x1, #1\n\t" \
132
+ "adr x16, 1f\n\t" \
133
+ "blr x16\n" \
134
+"1: " DEST "\n\t" \
135
+ "mov x1, #0"
136
+
137
+#define BTYPE_3(DEST) \
138
+ "mov x1, #1\n\t" \
139
+ "adr x15, 1f\n\t" \
140
+ "br x15\n" \
141
+"1: " DEST "\n\t" \
142
+ "mov x1, #0"
143
+
144
+#define TEST(WHICH, DEST, EXPECT) \
145
+ WHICH(DEST) "\n" \
146
+ ".if " #EXPECT "\n\t" \
147
+ "eor x1, x1," #EXPECT "\n" \
148
+ ".endif\n\t" \
149
+ "add x0, x0, x1\n\t"
150
+
151
+asm("\n"
152
+"test_begin:\n\t"
153
+ BTI_C "\n\t"
154
+ "mov x2, x30\n\t"
155
+ "mov x0, #0\n\t"
156
+
157
+ TEST(BTYPE_1, NOP, 1)
158
+ TEST(BTYPE_1, BTI_N, 1)
159
+ TEST(BTYPE_1, BTI_C, 0)
160
+ TEST(BTYPE_1, BTI_J, 0)
161
+ TEST(BTYPE_1, BTI_JC, 0)
162
+
163
+ TEST(BTYPE_2, NOP, 1)
164
+ TEST(BTYPE_2, BTI_N, 1)
165
+ TEST(BTYPE_2, BTI_C, 0)
166
+ TEST(BTYPE_2, BTI_J, 1)
167
+ TEST(BTYPE_2, BTI_JC, 0)
168
+
169
+ TEST(BTYPE_3, NOP, 1)
170
+ TEST(BTYPE_3, BTI_N, 1)
171
+ TEST(BTYPE_3, BTI_C, 1)
172
+ TEST(BTYPE_3, BTI_J, 0)
173
+ TEST(BTYPE_3, BTI_JC, 0)
174
+
175
+ "ret x2\n"
176
+"test_end:"
177
+);
178
+
179
+int main()
180
+{
181
+ struct sigaction sa;
182
+ void *tb, *te;
183
+
184
+ void *p = mmap(0, getpagesize(),
185
+ PROT_EXEC | PROT_READ | PROT_WRITE | PROT_BTI,
186
+ MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
187
+ if (p == MAP_FAILED) {
188
+ perror("mmap");
189
+ return 1;
190
+ }
191
+
192
+ memset(&sa, 0, sizeof(sa));
193
+ sa.sa_sigaction = skip2_sigill;
194
+ sa.sa_flags = SA_SIGINFO;
195
+ if (sigaction(SIGILL, &sa, NULL) < 0) {
196
+ perror("sigaction");
197
+ return 1;
198
+ }
199
+
200
+ /*
201
+ * ??? With "extern char test_begin[]", some compiler versions
202
+ * will use :got references, and some linker versions will
203
+ * resolve this reference to a static symbol incorrectly.
204
+ * Bypass this error by using a pc-relative reference directly.
205
+ */
206
+ asm("adr %0, test_begin; adr %1, test_end" : "=r"(tb), "=r"(te));
207
+
208
+ memcpy(p, tb, te - tb);
209
+
210
+ return ((int (*)(void))p)();
211
+}
212
diff --git a/tests/tcg/aarch64/bti-crt.inc.c b/tests/tcg/aarch64/bti-crt.inc.c
213
new file mode 100644
214
index XXXXXXX..XXXXXXX
215
--- /dev/null
216
+++ b/tests/tcg/aarch64/bti-crt.inc.c
217
@@ -XXX,XX +XXX,XX @@
218
+/*
219
+ * Minimal user-environment for testing BTI.
220
+ *
221
+ * Normal libc is not (yet) built with BTI support enabled,
222
+ * and so could generate a BTI TRAP before ever reaching main.
223
+ */
224
+
225
+#include <stdlib.h>
226
+#include <signal.h>
227
+#include <ucontext.h>
228
+#include <asm/unistd.h>
229
+
230
+int main(void);
231
+
232
+void _start(void)
233
+{
234
+ exit(main());
235
+}
236
+
237
+void exit(int ret)
238
+{
239
+ register int x0 __asm__("x0") = ret;
240
+ register int x8 __asm__("x8") = __NR_exit;
241
+
242
+ asm volatile("svc #0" : : "r"(x0), "r"(x8));
243
+ __builtin_unreachable();
244
+}
245
+
246
+/*
247
+ * Irritatingly, the user API struct sigaction does not match the
248
+ * kernel API struct sigaction. So for simplicity, isolate the
249
+ * kernel ABI here, and make this act like signal.
250
+ */
251
+void signal_info(int sig, void (*fn)(int, siginfo_t *, ucontext_t *))
252
+{
253
+ struct kernel_sigaction {
254
+ void (*handler)(int, siginfo_t *, ucontext_t *);
255
+ unsigned long flags;
256
+ unsigned long restorer;
257
+ unsigned long mask;
258
+ } sa = { fn, SA_SIGINFO, 0, 0 };
259
+
260
+ register int x0 __asm__("x0") = sig;
261
+ register void *x1 __asm__("x1") = &sa;
262
+ register void *x2 __asm__("x2") = 0;
263
+ register int x3 __asm__("x3") = sizeof(unsigned long);
264
+ register int x8 __asm__("x8") = __NR_rt_sigaction;
265
+
266
+ asm volatile("svc #0"
267
+ : : "r"(x0), "r"(x1), "r"(x2), "r"(x3), "r"(x8) : "memory");
268
+}
269
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
16
index XXXXXXX..XXXXXXX 100644
270
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-neon.inc.c
271
--- a/tests/tcg/aarch64/Makefile.target
18
+++ b/target/arm/translate-neon.inc.c
272
+++ b/tests/tcg/aarch64/Makefile.target
19
@@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
273
@@ -XXX,XX +XXX,XX @@ run-pauth-%: QEMU_OPTS += -cpu max
20
tcg_gen_bswap32_i32(tmp[half], tmp[half]);
274
run-plugin-pauth-%: QEMU_OPTS += -cpu max
21
break;
275
endif
22
case 1:
276
23
- gen_swap_half(tmp[half]);
277
+# BTI Tests
24
+ gen_swap_half(tmp[half], tmp[half]);
278
+# bti-1 tests the elf notes, so we require special compiler support.
25
break;
279
+ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_BTI),)
26
case 2:
280
+AARCH64_TESTS += bti-1
27
break;
281
+bti-1: CFLAGS += -mbranch-protection=standard
28
diff --git a/target/arm/translate.c b/target/arm/translate.c
282
+bti-1: LDFLAGS += -nostdlib
29
index XXXXXXX..XXXXXXX 100644
283
+endif
30
--- a/target/arm/translate.c
284
+# bti-2 tests PROT_BTI, so no special compiler support required.
31
+++ b/target/arm/translate.c
285
+AARCH64_TESTS += bti-2
32
@@ -XXX,XX +XXX,XX @@ static void gen_revsh(TCGv_i32 dest, TCGv_i32 var)
286
+
33
}
287
# Semihosting smoke test for linux-user
34
288
AARCH64_TESTS += semihosting
35
/* Swap low and high halfwords. */
289
run-semihosting: semihosting
36
-static void gen_swap_half(TCGv_i32 var)
290
diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
37
+static void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
291
index XXXXXXX..XXXXXXX 100755
38
{
292
--- a/tests/tcg/configure.sh
39
- tcg_gen_rotri_i32(var, var, 16);
293
+++ b/tests/tcg/configure.sh
40
+ tcg_gen_rotri_i32(dest, var, 16);
294
@@ -XXX,XX +XXX,XX @@ for target in $target_list; do
41
}
295
-march=armv8.3-a -o $TMPE $TMPC; then
42
296
echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak
43
/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
297
fi
44
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
298
+ if do_compiler "$target_compiler" $target_compiler_cflags \
45
case NEON_2RM_VREV32:
299
+ -mbranch-protection=standard -o $TMPE $TMPC; then
46
switch (size) {
300
+ echo "CROSS_CC_HAS_ARMV8_BTI=y" >> $config_target_mak
47
case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
301
+ fi
48
- case 1: gen_swap_half(tmp); break;
302
;;
49
+ case 1: gen_swap_half(tmp, tmp); break;
303
esac
50
default: abort();
51
}
52
break;
53
@@ -XXX,XX +XXX,XX @@ static bool op_smlad(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub)
54
t1 = load_reg(s, a->rn);
55
t2 = load_reg(s, a->rm);
56
if (m_swap) {
57
- gen_swap_half(t2);
58
+ gen_swap_half(t2, t2);
59
}
60
gen_smul_dual(t1, t2);
61
62
@@ -XXX,XX +XXX,XX @@ static bool op_smlald(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub)
63
t1 = load_reg(s, a->rn);
64
t2 = load_reg(s, a->rm);
65
if (m_swap) {
66
- gen_swap_half(t2);
67
+ gen_swap_half(t2, t2);
68
}
69
gen_smul_dual(t1, t2);
70
304
71
--
305
--
72
2.20.1
306
2.20.1
73
307
74
308
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Thomas Huth <thuth@redhat.com>
2
2
3
We already model the CMSDK APB watchdog device, let's use it!
3
When compiling with -Werror=implicit-fallthrough, gcc complains about
4
missing fallthrough annotations in this file. Looking at the code,
5
the fallthrough is very likely intended here, so add some comments
6
to silence the compiler warnings.
4
7
5
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Thomas Huth <thuth@redhat.com>
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20201020105938.23209-1-thuth@redhat.com
7
Message-id: 20200617072539.32686-9-f4bug@amsat.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
hw/arm/mps2.c | 7 +++++++
13
hw/arm/highbank.c | 2 ++
12
hw/arm/Kconfig | 1 +
14
1 file changed, 2 insertions(+)
13
2 files changed, 8 insertions(+)
14
15
15
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
16
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/mps2.c
18
--- a/hw/arm/highbank.c
18
+++ b/hw/arm/mps2.c
19
+++ b/hw/arm/highbank.c
19
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
20
@@ -XXX,XX +XXX,XX @@ static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
20
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
21
address_space_stl_notdirty(&address_space_memory,
21
qdev_get_gpio_in(armv7m, 10));
22
SMP_BOOT_REG + 0x30, 0,
22
sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
23
MEMTXATTRS_UNSPECIFIED, NULL);
23
+ object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
24
+ /* fallthrough */
24
+ TYPE_CMSDK_APB_WATCHDOG);
25
case 3:
25
+ qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ);
26
address_space_stl_notdirty(&address_space_memory,
26
+ sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
27
SMP_BOOT_REG + 0x20, 0,
27
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
28
MEMTXATTRS_UNSPECIFIED, NULL);
28
+ qdev_get_gpio_in_named(armv7m, "NMI", 0));
29
+ /* fallthrough */
29
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0x40008000);
30
case 2:
30
31
address_space_stl_notdirty(&address_space_memory,
31
/* FPGA APB subsystem */
32
SMP_BOOT_REG + 0x10, 0,
32
object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
33
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/arm/Kconfig
36
+++ b/hw/arm/Kconfig
37
@@ -XXX,XX +XXX,XX @@ config MPS2
38
select PL080 # DMA controller
39
select SPLIT_IRQ
40
select UNIMP
41
+ select CMSDK_APB_WATCHDOG
42
43
config FSL_IMX7
44
bool
45
--
33
--
46
2.20.1
34
2.20.1
47
35
48
36
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
This patch sets min_cpus field for xlnx-versal-virt platform,
4
Message-id: 20200617072539.32686-14-f4bug@amsat.org
4
because it always creates XLNX_VERSAL_NR_ACPUS cpus even with
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
-smp 1 command line option.
6
7
Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
Message-id: 160343854912.8460.17915238517799132371.stgit@pasha-ThinkPad-X280
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
12
---
8
hw/arm/mps2.c | 1 +
13
hw/arm/xlnx-versal-virt.c | 1 +
9
1 file changed, 1 insertion(+)
14
1 file changed, 1 insertion(+)
10
15
11
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
16
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
12
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/mps2.c
18
--- a/hw/arm/xlnx-versal-virt.c
14
+++ b/hw/arm/mps2.c
19
+++ b/hw/arm/xlnx-versal-virt.c
15
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
20
@@ -XXX,XX +XXX,XX @@ static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
16
0x4002a000}; /* Shield1 */
21
17
sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL);
22
mc->desc = "Xilinx Versal Virtual development board";
18
}
23
mc->init = versal_virt_init;
19
+ create_unimplemented_device("i2s", 0x40024000, 0x400);
24
+ mc->min_cpus = XLNX_VERSAL_NR_ACPUS;
20
25
mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
21
/* In hardware this is a LAN9220; the LAN9118 is software compatible
26
mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
22
* except that it doesn't support the checksum-offload feature.
27
mc->no_cdrom = true;
23
--
28
--
24
2.20.1
29
2.20.1
25
30
26
31
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Havard Skinnemoen <hskinnemoen@google.com>
2
2
3
Since commit d70c996df23f, when enabling the PMU we get:
3
This allows us to reuse npcm7xx_timer_pause for the watchdog timer.
4
4
5
$ qemu-system-aarch64 -cpu host,pmu=on -M virt,accel=kvm,gic-version=3
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Segmentation fault (core dumped)
6
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
7
8
Thread 1 "qemu-system-aar" received signal SIGSEGV, Segmentation fault.
9
0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at accel/kvm/kvm-all.c:2588
10
2588 ret = ioctl(s->fd, type, arg);
11
(gdb) bt
12
#0 0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at accel/kvm/kvm-all.c:2588
13
#1 0x0000aaaaaae31568 in kvm_check_extension (s=0x0, extension=126) at accel/kvm/kvm-all.c:916
14
#2 0x0000aaaaaafce254 in kvm_arm_pmu_supported (cpu=0xaaaaac214ab0) at target/arm/kvm.c:213
15
#3 0x0000aaaaaafc0f94 in arm_set_pmu (obj=0xaaaaac214ab0, value=true, errp=0xffffffffe438) at target/arm/cpu.c:1111
16
#4 0x0000aaaaab5533ac in property_set_bool (obj=0xaaaaac214ab0, v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", opaque=0xaaaaac222730, errp=0xffffffffe438) at qom/object.c:2170
17
#5 0x0000aaaaab5512f0 in object_property_set (obj=0xaaaaac214ab0, v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at qom/object.c:1328
18
#6 0x0000aaaaab551e10 in object_property_parse (obj=0xaaaaac214ab0, string=0xaaaaac11b4c0 "on", name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at qom/object.c:1561
19
#7 0x0000aaaaab54ee8c in object_apply_global_props (obj=0xaaaaac214ab0, props=0xaaaaac018e20, errp=0xaaaaabd6fd88 <error_fatal>) at qom/object.c:407
20
#8 0x0000aaaaab1dd5a4 in qdev_prop_set_globals (dev=0xaaaaac214ab0) at hw/core/qdev-properties.c:1218
21
#9 0x0000aaaaab1d9fac in device_post_init (obj=0xaaaaac214ab0) at hw/core/qdev.c:1050
22
...
23
#15 0x0000aaaaab54f310 in object_initialize_with_type (obj=0xaaaaac214ab0, size=52208, type=0xaaaaabe237f0) at qom/object.c:512
24
#16 0x0000aaaaab54fa24 in object_new_with_type (type=0xaaaaabe237f0) at qom/object.c:687
25
#17 0x0000aaaaab54fa80 in object_new (typename=0xaaaaabe23970 "host-arm-cpu") at qom/object.c:702
26
#18 0x0000aaaaaaf04a74 in machvirt_init (machine=0xaaaaac0a8550) at hw/arm/virt.c:1770
27
#19 0x0000aaaaab1e8720 in machine_run_board_init (machine=0xaaaaac0a8550) at hw/core/machine.c:1138
28
#20 0x0000aaaaaaf95394 in qemu_init (argc=5, argv=0xffffffffea58, envp=0xffffffffea88) at softmmu/vl.c:4348
29
#21 0x0000aaaaaada3f74 in main (argc=<optimized out>, argv=<optimized out>, envp=<optimized out>) at softmmu/main.c:48
30
31
This is because in frame #2, cpu->kvm_state is still NULL
32
(the vCPU is not yet realized).
33
34
KVM has a hard requirement of all cores supporting the same
35
feature set. We only need to check if the accelerator supports
36
a feature, not each vCPU individually.
37
38
Fix by removing the 'CPUState *cpu' argument from the
39
kvm_arm_<FEATURE>_supported() functions.
40
41
Fixes: d70c996df23f ('Use CPUState::kvm_state in kvm_arm_pmu_supported')
42
Reported-by: Haibo Xu <haibo.xu@linaro.org>
43
Reviewed-by: Andrew Jones <drjones@redhat.com>
44
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
45
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
46
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
47
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
48
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
49
---
8
---
50
target/arm/kvm_arm.h | 21 +++++++++------------
9
hw/timer/npcm7xx_timer.c | 6 +++---
51
target/arm/cpu.c | 2 +-
10
1 file changed, 3 insertions(+), 3 deletions(-)
52
target/arm/cpu64.c | 10 +++++-----
53
target/arm/kvm.c | 4 ++--
54
target/arm/kvm64.c | 14 +++++---------
55
5 files changed, 22 insertions(+), 29 deletions(-)
56
11
57
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
12
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
58
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/kvm_arm.h
14
--- a/hw/timer/npcm7xx_timer.c
60
+++ b/target/arm/kvm_arm.h
15
+++ b/hw/timer/npcm7xx_timer.c
61
@@ -XXX,XX +XXX,XX @@ void kvm_arm_add_vcpu_properties(Object *obj);
16
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_pause(NPCM7xxTimer *t)
62
17
timer_del(&t->qtimer);
63
/**
18
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
64
* kvm_arm_aarch32_supported:
19
t->remaining_ns = t->expires_ns - now;
65
- * @cs: CPUState
20
- if (t->remaining_ns <= 0) {
66
*
21
- npcm7xx_timer_reached_zero(t);
67
- * Returns: true if the KVM VCPU can enable AArch32 mode
22
- }
68
+ * Returns: true if KVM can enable AArch32 mode
69
* and false otherwise.
70
*/
71
-bool kvm_arm_aarch32_supported(CPUState *cs);
72
+bool kvm_arm_aarch32_supported(void);
73
74
/**
75
* kvm_arm_pmu_supported:
76
- * @cs: CPUState
77
*
78
- * Returns: true if the KVM VCPU can enable its PMU
79
+ * Returns: true if KVM can enable the PMU
80
* and false otherwise.
81
*/
82
-bool kvm_arm_pmu_supported(CPUState *cs);
83
+bool kvm_arm_pmu_supported(void);
84
85
/**
86
* kvm_arm_sve_supported:
87
- * @cs: CPUState
88
*
89
- * Returns true if the KVM VCPU can enable SVE and false otherwise.
90
+ * Returns true if KVM can enable SVE and false otherwise.
91
*/
92
-bool kvm_arm_sve_supported(CPUState *cs);
93
+bool kvm_arm_sve_supported(void);
94
95
/**
96
* kvm_arm_get_max_vm_ipa_size:
97
@@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
98
99
static inline void kvm_arm_add_vcpu_properties(Object *obj) {}
100
101
-static inline bool kvm_arm_aarch32_supported(CPUState *cs)
102
+static inline bool kvm_arm_aarch32_supported(void)
103
{
104
return false;
105
}
23
}
106
24
107
-static inline bool kvm_arm_pmu_supported(CPUState *cs)
25
/*
108
+static inline bool kvm_arm_pmu_supported(void)
26
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
109
{
27
} else {
110
return false;
28
t->tcsr &= ~NPCM7XX_TCSR_CACT;
111
}
29
npcm7xx_timer_pause(t);
112
30
+ if (t->remaining_ns <= 0) {
113
-static inline bool kvm_arm_sve_supported(CPUState *cs)
31
+ npcm7xx_timer_reached_zero(t);
114
+static inline bool kvm_arm_sve_supported(void)
32
+ }
115
{
116
return false;
117
}
118
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
119
index XXXXXXX..XXXXXXX 100644
120
--- a/target/arm/cpu.c
121
+++ b/target/arm/cpu.c
122
@@ -XXX,XX +XXX,XX @@ static void arm_set_pmu(Object *obj, bool value, Error **errp)
123
ARMCPU *cpu = ARM_CPU(obj);
124
125
if (value) {
126
- if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu))) {
127
+ if (kvm_enabled() && !kvm_arm_pmu_supported()) {
128
error_setg(errp, "'pmu' feature not supported by KVM on this host");
129
return;
130
}
33
}
131
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/target/arm/cpu64.c
134
+++ b/target/arm/cpu64.c
135
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
136
137
/* Collect the set of vector lengths supported by KVM. */
138
bitmap_zero(kvm_supported, ARM_MAX_VQ);
139
- if (kvm_enabled() && kvm_arm_sve_supported(CPU(cpu))) {
140
+ if (kvm_enabled() && kvm_arm_sve_supported()) {
141
kvm_arm_sve_get_vls(CPU(cpu), kvm_supported);
142
} else if (kvm_enabled()) {
143
assert(!cpu_isar_feature(aa64_sve, cpu));
144
@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
145
return;
146
}
147
148
- if (kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
149
+ if (kvm_enabled() && !kvm_arm_sve_supported()) {
150
error_setg(errp, "cannot set sve-max-vq");
151
error_append_hint(errp, "SVE not supported by KVM on this host\n");
152
return;
153
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name,
154
return;
155
}
156
157
- if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
158
+ if (value && kvm_enabled() && !kvm_arm_sve_supported()) {
159
error_setg(errp, "cannot enable %s", name);
160
error_append_hint(errp, "SVE not supported by KVM on this host\n");
161
return;
162
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
163
return;
164
}
165
166
- if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
167
+ if (value && kvm_enabled() && !kvm_arm_sve_supported()) {
168
error_setg(errp, "'sve' feature not supported by KVM on this host");
169
return;
170
}
171
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
172
* uniform execution state like do_interrupt.
173
*/
174
if (value == false) {
175
- if (!kvm_enabled() || !kvm_arm_aarch32_supported(CPU(cpu))) {
176
+ if (!kvm_enabled() || !kvm_arm_aarch32_supported()) {
177
error_setg(errp, "'aarch64' feature cannot be disabled "
178
"unless KVM is enabled and 32-bit EL1 "
179
"is supported");
180
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
181
index XXXXXXX..XXXXXXX 100644
182
--- a/target/arm/kvm.c
183
+++ b/target/arm/kvm.c
184
@@ -XXX,XX +XXX,XX @@ void kvm_arm_add_vcpu_properties(Object *obj)
185
}
34
}
186
}
35
}
187
188
-bool kvm_arm_pmu_supported(CPUState *cpu)
189
+bool kvm_arm_pmu_supported(void)
190
{
191
- return kvm_check_extension(cpu->kvm_state, KVM_CAP_ARM_PMU_V3);
192
+ return kvm_check_extension(kvm_state, KVM_CAP_ARM_PMU_V3);
193
}
194
195
int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
196
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
197
index XXXXXXX..XXXXXXX 100644
198
--- a/target/arm/kvm64.c
199
+++ b/target/arm/kvm64.c
200
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
201
return true;
202
}
203
204
-bool kvm_arm_aarch32_supported(CPUState *cpu)
205
+bool kvm_arm_aarch32_supported(void)
206
{
207
- KVMState *s = KVM_STATE(current_accel());
208
-
209
- return kvm_check_extension(s, KVM_CAP_ARM_EL1_32BIT);
210
+ return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT);
211
}
212
213
-bool kvm_arm_sve_supported(CPUState *cpu)
214
+bool kvm_arm_sve_supported(void)
215
{
216
- KVMState *s = KVM_STATE(current_accel());
217
-
218
- return kvm_check_extension(s, KVM_CAP_ARM_SVE);
219
+ return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE);
220
}
221
222
QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1);
223
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
224
env->features &= ~(1ULL << ARM_FEATURE_PMU);
225
}
226
if (cpu_isar_feature(aa64_sve, cpu)) {
227
- assert(kvm_arm_sve_supported(cs));
228
+ assert(kvm_arm_sve_supported());
229
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE;
230
}
231
232
--
36
--
233
2.20.1
37
2.20.1
234
38
235
39
diff view generated by jsdifflib
1
The functions neon_element_offset(), neon_load_element(),
1
From: Hao Wu <wuhaotsh@google.com>
2
neon_load_element64(), neon_store_element() and
3
neon_store_element64() are used only in the translate-neon.inc.c
4
file, so move their definitions there.
5
2
6
Since the .inc.c file is #included in translate.c this doesn't make
3
The watchdog is part of NPCM7XX's timer module. Its behavior is
7
much difference currently, but it's a more logical place to put the
4
controlled by the WTCR register in the timer.
8
functions and it might be helpful if we ever decide to try to make
9
the .inc.c files genuinely separate compilation units.
10
5
6
When enabled, the watchdog issues an interrupt signal after a pre-set
7
amount of cycles, and issues a reset signal shortly after that.
8
9
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
10
Signed-off-by: Hao Wu <wuhaotsh@google.com>
11
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
[PMM: deleted blank line at end of npcm_watchdog_timer-test.c]
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20200616170844.13318-22-peter.maydell@linaro.org
14
---
15
---
15
target/arm/translate-neon.inc.c | 101 ++++++++++++++++++++++++++++++++
16
include/hw/misc/npcm7xx_clk.h | 2 +
16
target/arm/translate.c | 101 --------------------------------
17
include/hw/timer/npcm7xx_timer.h | 48 +++-
17
2 files changed, 101 insertions(+), 101 deletions(-)
18
hw/arm/npcm7xx.c | 12 +
19
hw/misc/npcm7xx_clk.c | 28 ++
20
hw/timer/npcm7xx_timer.c | 266 ++++++++++++++----
21
tests/qtest/npcm7xx_watchdog_timer-test.c | 319 ++++++++++++++++++++++
22
MAINTAINERS | 1 +
23
tests/qtest/meson.build | 2 +-
24
8 files changed, 624 insertions(+), 54 deletions(-)
25
create mode 100644 tests/qtest/npcm7xx_watchdog_timer-test.c
18
26
19
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
27
diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
20
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate-neon.inc.c
29
--- a/include/hw/misc/npcm7xx_clk.h
22
+++ b/target/arm/translate-neon.inc.c
30
+++ b/include/hw/misc/npcm7xx_clk.h
23
@@ -XXX,XX +XXX,XX @@ static inline int rsub_8(DisasContext *s, int x)
31
@@ -XXX,XX +XXX,XX @@
24
#include "decode-neon-ls.inc.c"
32
*/
25
#include "decode-neon-shared.inc.c"
33
#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t))
26
34
27
+/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
35
+#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
28
+ * where 0 is the least significant end of the register.
36
+
37
typedef struct NPCM7xxCLKState {
38
SysBusDevice parent;
39
40
diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h
41
index XXXXXXX..XXXXXXX 100644
42
--- a/include/hw/timer/npcm7xx_timer.h
43
+++ b/include/hw/timer/npcm7xx_timer.h
44
@@ -XXX,XX +XXX,XX @@
45
*/
46
#define NPCM7XX_TIMER_NR_REGS (0x54 / sizeof(uint32_t))
47
48
+/* The basic watchdog timer period is 2^14 clock cycles. */
49
+#define NPCM7XX_WATCHDOG_BASETIME_SHIFT 14
50
+
51
+#define NPCM7XX_WATCHDOG_RESET_GPIO_OUT "npcm7xx-clk-watchdog-reset-gpio-out"
52
+
53
typedef struct NPCM7xxTimerCtrlState NPCM7xxTimerCtrlState;
54
55
/**
56
- * struct NPCM7xxTimer - Individual timer state.
57
- * @irq: GIC interrupt line to fire on expiration (if enabled).
58
+ * struct NPCM7xxBaseTimer - Basic functionality that both regular timer and
59
+ * watchdog timer use.
60
* @qtimer: QEMU timer that notifies us on expiration.
61
* @expires_ns: Absolute virtual expiration time.
62
* @remaining_ns: Remaining time until expiration if timer is paused.
29
+ */
63
+ */
30
+static inline long
64
+typedef struct NPCM7xxBaseTimer {
31
+neon_element_offset(int reg, int element, MemOp size)
65
+ QEMUTimer qtimer;
32
+{
66
+ int64_t expires_ns;
33
+ int element_size = 1 << size;
67
+ int64_t remaining_ns;
34
+ int ofs = element * element_size;
68
+} NPCM7xxBaseTimer;
35
+#ifdef HOST_WORDS_BIGENDIAN
69
+
36
+ /* Calculate the offset assuming fully little-endian,
70
+/**
37
+ * then XOR to account for the order of the 8-byte units.
71
+ * struct NPCM7xxTimer - Individual timer state.
38
+ */
72
+ * @ctrl: The timer module that owns this timer.
39
+ if (element_size < 8) {
73
+ * @irq: GIC interrupt line to fire on expiration (if enabled).
40
+ ofs ^= 8 - element_size;
74
+ * @base_timer: The basic timer functionality for this timer.
75
* @tcsr: The Timer Control and Status Register.
76
* @ticr: The Timer Initial Count Register.
77
*/
78
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxTimer {
79
NPCM7xxTimerCtrlState *ctrl;
80
81
qemu_irq irq;
82
- QEMUTimer qtimer;
83
- int64_t expires_ns;
84
- int64_t remaining_ns;
85
+ NPCM7xxBaseTimer base_timer;
86
87
uint32_t tcsr;
88
uint32_t ticr;
89
} NPCM7xxTimer;
90
91
+/**
92
+ * struct NPCM7xxWatchdogTimer - The watchdog timer state.
93
+ * @ctrl: The timer module that owns this timer.
94
+ * @irq: GIC interrupt line to fire on expiration (if enabled).
95
+ * @reset_signal: The GPIO used to send a reset signal.
96
+ * @base_timer: The basic timer functionality for this timer.
97
+ * @wtcr: The Watchdog Timer Control Register.
98
+ */
99
+typedef struct NPCM7xxWatchdogTimer {
100
+ NPCM7xxTimerCtrlState *ctrl;
101
+
102
+ qemu_irq irq;
103
+ qemu_irq reset_signal;
104
+ NPCM7xxBaseTimer base_timer;
105
+
106
+ uint32_t wtcr;
107
+} NPCM7xxWatchdogTimer;
108
+
109
/**
110
* struct NPCM7xxTimerCtrlState - Timer Module device state.
111
* @parent: System bus device.
112
* @iomem: Memory region through which registers are accessed.
113
+ * @index: The index of this timer module.
114
* @tisr: The Timer Interrupt Status Register.
115
- * @wtcr: The Watchdog Timer Control Register.
116
* @timer: The five individual timers managed by this module.
117
+ * @watchdog_timer: The watchdog timer managed by this module.
118
*/
119
struct NPCM7xxTimerCtrlState {
120
SysBusDevice parent;
121
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState {
122
MemoryRegion iomem;
123
124
uint32_t tisr;
125
- uint32_t wtcr;
126
127
NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
128
+ NPCM7xxWatchdogTimer watchdog_timer;
129
};
130
131
#define TYPE_NPCM7XX_TIMER "npcm7xx-timer"
132
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
133
index XXXXXXX..XXXXXXX 100644
134
--- a/hw/arm/npcm7xx.c
135
+++ b/hw/arm/npcm7xx.c
136
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
137
NPCM7XX_TIMER12_IRQ,
138
NPCM7XX_TIMER13_IRQ,
139
NPCM7XX_TIMER14_IRQ,
140
+ NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */
141
+ NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */
142
+ NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
143
};
144
145
/* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
146
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
147
qemu_irq irq = npcm7xx_irq(s, first_irq + j);
148
sysbus_connect_irq(sbd, j, irq);
149
}
150
+
151
+ /* IRQ for watchdogs */
152
+ sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL,
153
+ npcm7xx_irq(s, NPCM7XX_WDG0_IRQ + i));
154
+ /* GPIO that connects clk module with watchdog */
155
+ qdev_connect_gpio_out_named(DEVICE(&s->tim[i]),
156
+ NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0,
157
+ qdev_get_gpio_in_named(DEVICE(&s->clk),
158
+ NPCM7XX_WATCHDOG_RESET_GPIO_IN, i));
159
}
160
161
/* UART0..3 (16550 compatible) */
162
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
163
index XXXXXXX..XXXXXXX 100644
164
--- a/hw/misc/npcm7xx_clk.c
165
+++ b/hw/misc/npcm7xx_clk.c
166
@@ -XXX,XX +XXX,XX @@
167
#include "qemu/osdep.h"
168
169
#include "hw/misc/npcm7xx_clk.h"
170
+#include "hw/timer/npcm7xx_timer.h"
171
#include "migration/vmstate.h"
172
#include "qemu/error-report.h"
173
#include "qemu/log.h"
174
@@ -XXX,XX +XXX,XX @@
175
#include "qemu/timer.h"
176
#include "qemu/units.h"
177
#include "trace.h"
178
+#include "sysemu/watchdog.h"
179
180
#define PLLCON_LOKI BIT(31)
181
#define PLLCON_LOKS BIT(30)
182
@@ -XXX,XX +XXX,XX @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
183
[NPCM7XX_CLK_AHBCKFI] = 0x000000c8,
184
};
185
186
+/* Register Field Definitions */
187
+#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */
188
+
189
+/* The number of watchdogs that can trigger a reset. */
190
+#define NPCM7XX_NR_WATCHDOGS (3)
191
+
192
static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
193
{
194
uint32_t reg = offset / sizeof(uint32_t);
195
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
196
s->regs[reg] = value;
197
}
198
199
+/* Perform reset action triggered by a watchdog */
200
+static void npcm7xx_clk_perform_watchdog_reset(void *opaque, int n,
201
+ int level)
202
+{
203
+ NPCM7xxCLKState *clk = NPCM7XX_CLK(opaque);
204
+ uint32_t rcr;
205
+
206
+ g_assert(n >= 0 && n <= NPCM7XX_NR_WATCHDOGS);
207
+ rcr = clk->regs[NPCM7XX_CLK_WD0RCR + n];
208
+ if (rcr & NPCM7XX_CLK_WDRCR_CA9C) {
209
+ watchdog_perform_action();
210
+ } else {
211
+ qemu_log_mask(LOG_UNIMP,
212
+ "%s: only CPU reset is implemented. (requested 0x%" PRIx32")\n",
213
+ __func__, rcr);
41
+ }
214
+ }
42
+#endif
215
+}
43
+ return neon_reg_offset(reg, 0) + ofs;
216
+
44
+}
217
static const struct MemoryRegionOps npcm7xx_clk_ops = {
45
+
218
.read = npcm7xx_clk_read,
46
+static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
219
.write = npcm7xx_clk_write,
47
+{
220
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
48
+ long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
221
memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
49
+
222
TYPE_NPCM7XX_CLK, 4 * KiB);
50
+ switch (mop) {
223
sysbus_init_mmio(&s->parent, &s->iomem);
51
+ case MO_UB:
224
+ qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
52
+ tcg_gen_ld8u_i32(var, cpu_env, offset);
225
+ NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
53
+ break;
226
}
54
+ case MO_UW:
227
55
+ tcg_gen_ld16u_i32(var, cpu_env, offset);
228
static const VMStateDescription vmstate_npcm7xx_clk = {
56
+ break;
229
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
57
+ case MO_UL:
230
index XXXXXXX..XXXXXXX 100644
58
+ tcg_gen_ld_i32(var, cpu_env, offset);
231
--- a/hw/timer/npcm7xx_timer.c
59
+ break;
232
+++ b/hw/timer/npcm7xx_timer.c
233
@@ -XXX,XX +XXX,XX @@
234
#include "qemu/osdep.h"
235
236
#include "hw/irq.h"
237
+#include "hw/qdev-properties.h"
238
#include "hw/misc/npcm7xx_clk.h"
239
#include "hw/timer/npcm7xx_timer.h"
240
#include "migration/vmstate.h"
241
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxTimerRegisters {
242
#define NPCM7XX_TCSR_PRESCALE_START 0
243
#define NPCM7XX_TCSR_PRESCALE_LEN 8
244
245
+#define NPCM7XX_WTCR_WTCLK(rv) extract32(rv, 10, 2)
246
+#define NPCM7XX_WTCR_FREEZE_EN BIT(9)
247
+#define NPCM7XX_WTCR_WTE BIT(7)
248
+#define NPCM7XX_WTCR_WTIE BIT(6)
249
+#define NPCM7XX_WTCR_WTIS(rv) extract32(rv, 4, 2)
250
+#define NPCM7XX_WTCR_WTIF BIT(3)
251
+#define NPCM7XX_WTCR_WTRF BIT(2)
252
+#define NPCM7XX_WTCR_WTRE BIT(1)
253
+#define NPCM7XX_WTCR_WTR BIT(0)
254
+
255
+/*
256
+ * The number of clock cycles between interrupt and reset in watchdog, used
257
+ * by the software to handle the interrupt before system is reset.
258
+ */
259
+#define NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES 1024
260
+
261
+/* Start or resume the timer. */
262
+static void npcm7xx_timer_start(NPCM7xxBaseTimer *t)
263
+{
264
+ int64_t now;
265
+
266
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
267
+ t->expires_ns = now + t->remaining_ns;
268
+ timer_mod(&t->qtimer, t->expires_ns);
269
+}
270
+
271
+/* Stop counting. Record the time remaining so we can continue later. */
272
+static void npcm7xx_timer_pause(NPCM7xxBaseTimer *t)
273
+{
274
+ int64_t now;
275
+
276
+ timer_del(&t->qtimer);
277
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
278
+ t->remaining_ns = t->expires_ns - now;
279
+}
280
+
281
+/* Delete the timer and reset it to default state. */
282
+static void npcm7xx_timer_clear(NPCM7xxBaseTimer *t)
283
+{
284
+ timer_del(&t->qtimer);
285
+ t->expires_ns = 0;
286
+ t->remaining_ns = 0;
287
+}
288
+
289
/*
290
* Returns the index of timer in the tc->timer array. This can be used to
291
* locate the registers that belong to this timer.
292
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
293
return count;
294
}
295
296
+static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
297
+{
298
+ switch (NPCM7XX_WTCR_WTCLK(t->wtcr)) {
299
+ case 0:
300
+ return 1;
301
+ case 1:
302
+ return 256;
303
+ case 2:
304
+ return 2048;
305
+ case 3:
306
+ return 65536;
60
+ default:
307
+ default:
61
+ g_assert_not_reached();
308
+ g_assert_not_reached();
62
+ }
309
+ }
63
+}
310
+}
64
+
311
+
65
+static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop)
312
+static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
66
+{
313
+ int64_t cycles)
67
+ long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
314
+{
68
+
315
+ uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
69
+ switch (mop) {
316
+ int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
70
+ case MO_UB:
317
+
71
+ tcg_gen_ld8u_i64(var, cpu_env, offset);
318
+ /*
72
+ break;
319
+ * The reset function always clears the current timer. The caller of the
73
+ case MO_UW:
320
+ * this needs to decide whether to start the watchdog timer based on
74
+ tcg_gen_ld16u_i64(var, cpu_env, offset);
321
+ * specific flag in WTCR.
75
+ break;
322
+ */
76
+ case MO_UL:
323
+ npcm7xx_timer_clear(&t->base_timer);
77
+ tcg_gen_ld32u_i64(var, cpu_env, offset);
324
+
78
+ break;
325
+ ns *= prescaler;
79
+ case MO_Q:
326
+ t->base_timer.remaining_ns = ns;
80
+ tcg_gen_ld_i64(var, cpu_env, offset);
327
+}
81
+ break;
328
+
329
+static void npcm7xx_watchdog_timer_reset(NPCM7xxWatchdogTimer *t)
330
+{
331
+ int64_t cycles = 1;
332
+ uint32_t s = NPCM7XX_WTCR_WTIS(t->wtcr);
333
+
334
+ g_assert(s <= 3);
335
+
336
+ cycles <<= NPCM7XX_WATCHDOG_BASETIME_SHIFT;
337
+ cycles <<= 2 * s;
338
+
339
+ npcm7xx_watchdog_timer_reset_cycles(t, cycles);
340
+}
341
+
342
/*
343
* Raise the interrupt line if there's a pending interrupt and interrupts are
344
* enabled for this timer. If not, lower it.
345
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_check_interrupt(NPCM7xxTimer *t)
346
trace_npcm7xx_timer_irq(DEVICE(tc)->canonical_path, index, pending);
347
}
348
349
-/* Start or resume the timer. */
350
-static void npcm7xx_timer_start(NPCM7xxTimer *t)
351
-{
352
- int64_t now;
353
-
354
- now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
355
- t->expires_ns = now + t->remaining_ns;
356
- timer_mod(&t->qtimer, t->expires_ns);
357
-}
358
-
359
/*
360
* Called when the counter reaches zero. Sets the interrupt flag, and either
361
* restarts or disables the timer.
362
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_reached_zero(NPCM7xxTimer *t)
363
tc->tisr |= BIT(index);
364
365
if (t->tcsr & NPCM7XX_TCSR_PERIODIC) {
366
- t->remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
367
+ t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
368
if (t->tcsr & NPCM7XX_TCSR_CEN) {
369
- npcm7xx_timer_start(t);
370
+ npcm7xx_timer_start(&t->base_timer);
371
}
372
} else {
373
t->tcsr &= ~(NPCM7XX_TCSR_CEN | NPCM7XX_TCSR_CACT);
374
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_reached_zero(NPCM7xxTimer *t)
375
npcm7xx_timer_check_interrupt(t);
376
}
377
378
-/* Stop counting. Record the time remaining so we can continue later. */
379
-static void npcm7xx_timer_pause(NPCM7xxTimer *t)
380
-{
381
- int64_t now;
382
-
383
- timer_del(&t->qtimer);
384
- now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
385
- t->remaining_ns = t->expires_ns - now;
386
-}
387
388
/*
389
* Restart the timer from its initial value. If the timer was enabled and stays
390
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_pause(NPCM7xxTimer *t)
391
*/
392
static void npcm7xx_timer_restart(NPCM7xxTimer *t, uint32_t old_tcsr)
393
{
394
- t->remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
395
+ t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
396
397
if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
398
- npcm7xx_timer_start(t);
399
+ npcm7xx_timer_start(&t->base_timer);
400
}
401
}
402
403
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_timer_read_tdr(NPCM7xxTimer *t)
404
if (t->tcsr & NPCM7XX_TCSR_CEN) {
405
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
406
407
- return npcm7xx_timer_ns_to_count(t, t->expires_ns - now);
408
+ return npcm7xx_timer_ns_to_count(t, t->base_timer.expires_ns - now);
409
}
410
411
- return npcm7xx_timer_ns_to_count(t, t->remaining_ns);
412
+ return npcm7xx_timer_ns_to_count(t, t->base_timer.remaining_ns);
413
}
414
415
static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
416
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
417
418
if (npcm7xx_tcsr_prescaler(old_tcsr) != npcm7xx_tcsr_prescaler(new_tcsr)) {
419
/* Recalculate time remaining based on the current TDR value. */
420
- t->remaining_ns = npcm7xx_timer_count_to_ns(t, tdr);
421
+ t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, tdr);
422
if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
423
- npcm7xx_timer_start(t);
424
+ npcm7xx_timer_start(&t->base_timer);
425
}
426
}
427
428
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
429
if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_CEN) {
430
if (new_tcsr & NPCM7XX_TCSR_CEN) {
431
t->tcsr |= NPCM7XX_TCSR_CACT;
432
- npcm7xx_timer_start(t);
433
+ npcm7xx_timer_start(&t->base_timer);
434
} else {
435
t->tcsr &= ~NPCM7XX_TCSR_CACT;
436
- npcm7xx_timer_pause(t);
437
- if (t->remaining_ns <= 0) {
438
+ npcm7xx_timer_pause(&t->base_timer);
439
+ if (t->base_timer.remaining_ns <= 0) {
440
npcm7xx_timer_reached_zero(t);
441
}
442
}
443
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_write_tisr(NPCM7xxTimerCtrlState *s, uint32_t value)
444
if (value & (1U << i)) {
445
npcm7xx_timer_check_interrupt(&s->timer[i]);
446
}
447
+
448
}
449
}
450
451
+static void npcm7xx_timer_write_wtcr(NPCM7xxWatchdogTimer *t, uint32_t new_wtcr)
452
+{
453
+ uint32_t old_wtcr = t->wtcr;
454
+
455
+ /*
456
+ * WTIF and WTRF are cleared by writing 1. Writing 0 makes these bits
457
+ * unchanged.
458
+ */
459
+ if (new_wtcr & NPCM7XX_WTCR_WTIF) {
460
+ new_wtcr &= ~NPCM7XX_WTCR_WTIF;
461
+ } else if (old_wtcr & NPCM7XX_WTCR_WTIF) {
462
+ new_wtcr |= NPCM7XX_WTCR_WTIF;
463
+ }
464
+ if (new_wtcr & NPCM7XX_WTCR_WTRF) {
465
+ new_wtcr &= ~NPCM7XX_WTCR_WTRF;
466
+ } else if (old_wtcr & NPCM7XX_WTCR_WTRF) {
467
+ new_wtcr |= NPCM7XX_WTCR_WTRF;
468
+ }
469
+
470
+ t->wtcr = new_wtcr;
471
+
472
+ if (new_wtcr & NPCM7XX_WTCR_WTR) {
473
+ t->wtcr &= ~NPCM7XX_WTCR_WTR;
474
+ npcm7xx_watchdog_timer_reset(t);
475
+ if (new_wtcr & NPCM7XX_WTCR_WTE) {
476
+ npcm7xx_timer_start(&t->base_timer);
477
+ }
478
+ } else if ((old_wtcr ^ new_wtcr) & NPCM7XX_WTCR_WTE) {
479
+ if (new_wtcr & NPCM7XX_WTCR_WTE) {
480
+ npcm7xx_timer_start(&t->base_timer);
481
+ } else {
482
+ npcm7xx_timer_pause(&t->base_timer);
483
+ }
484
+ }
485
+
486
+}
487
+
488
static hwaddr npcm7xx_tcsr_index(hwaddr reg)
489
{
490
switch (reg) {
491
@@ -XXX,XX +XXX,XX @@ static uint64_t npcm7xx_timer_read(void *opaque, hwaddr offset, unsigned size)
492
break;
493
494
case NPCM7XX_TIMER_WTCR:
495
- value = s->wtcr;
496
+ value = s->watchdog_timer.wtcr;
497
break;
498
499
default:
500
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_write(void *opaque, hwaddr offset,
501
return;
502
503
case NPCM7XX_TIMER_WTCR:
504
- qemu_log_mask(LOG_UNIMP, "%s: WTCR write not implemented: 0x%08x\n",
505
- __func__, value);
506
+ npcm7xx_timer_write_wtcr(&s->watchdog_timer, value);
507
return;
508
}
509
510
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_enter_reset(Object *obj, ResetType type)
511
for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
512
NPCM7xxTimer *t = &s->timer[i];
513
514
- timer_del(&t->qtimer);
515
- t->expires_ns = 0;
516
- t->remaining_ns = 0;
517
+ npcm7xx_timer_clear(&t->base_timer);
518
t->tcsr = 0x00000005;
519
t->ticr = 0x00000000;
520
}
521
522
s->tisr = 0x00000000;
523
- s->wtcr = 0x00000400;
524
+ /*
525
+ * Set WTCLK to 1(default) and reset all flags except WTRF.
526
+ * WTRF is not reset during a core domain reset.
527
+ */
528
+ s->watchdog_timer.wtcr = 0x00000400 | (s->watchdog_timer.wtcr &
529
+ NPCM7XX_WTCR_WTRF);
530
+}
531
+
532
+static void npcm7xx_watchdog_timer_expired(void *opaque)
533
+{
534
+ NPCM7xxWatchdogTimer *t = opaque;
535
+
536
+ if (t->wtcr & NPCM7XX_WTCR_WTE) {
537
+ if (t->wtcr & NPCM7XX_WTCR_WTIF) {
538
+ if (t->wtcr & NPCM7XX_WTCR_WTRE) {
539
+ t->wtcr |= NPCM7XX_WTCR_WTRF;
540
+ /* send reset signal to CLK module*/
541
+ qemu_irq_raise(t->reset_signal);
542
+ }
543
+ } else {
544
+ t->wtcr |= NPCM7XX_WTCR_WTIF;
545
+ if (t->wtcr & NPCM7XX_WTCR_WTIE) {
546
+ /* send interrupt */
547
+ qemu_irq_raise(t->irq);
548
+ }
549
+ npcm7xx_watchdog_timer_reset_cycles(t,
550
+ NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES);
551
+ npcm7xx_timer_start(&t->base_timer);
552
+ }
553
+ }
554
}
555
556
static void npcm7xx_timer_hold_reset(Object *obj)
557
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj)
558
for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
559
qemu_irq_lower(s->timer[i].irq);
560
}
561
+ qemu_irq_lower(s->watchdog_timer.irq);
562
}
563
564
static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
565
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
566
NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
567
SysBusDevice *sbd = &s->parent;
568
int i;
569
+ NPCM7xxWatchdogTimer *w;
570
571
for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
572
NPCM7xxTimer *t = &s->timer[i];
573
t->ctrl = s;
574
- timer_init_ns(&t->qtimer, QEMU_CLOCK_VIRTUAL, npcm7xx_timer_expired, t);
575
+ timer_init_ns(&t->base_timer.qtimer, QEMU_CLOCK_VIRTUAL,
576
+ npcm7xx_timer_expired, t);
577
sysbus_init_irq(sbd, &t->irq);
578
}
579
580
+ w = &s->watchdog_timer;
581
+ w->ctrl = s;
582
+ timer_init_ns(&w->base_timer.qtimer, QEMU_CLOCK_VIRTUAL,
583
+ npcm7xx_watchdog_timer_expired, w);
584
+ sysbus_init_irq(sbd, &w->irq);
585
+
586
memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
587
TYPE_NPCM7XX_TIMER, 4 * KiB);
588
sysbus_init_mmio(sbd, &s->iomem);
589
+ qdev_init_gpio_out_named(dev, &w->reset_signal,
590
+ NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
591
}
592
593
-static const VMStateDescription vmstate_npcm7xx_timer = {
594
- .name = "npcm7xx-timer",
595
+static const VMStateDescription vmstate_npcm7xx_base_timer = {
596
+ .name = "npcm7xx-base-timer",
597
.version_id = 0,
598
.minimum_version_id = 0,
599
.fields = (VMStateField[]) {
600
- VMSTATE_TIMER(qtimer, NPCM7xxTimer),
601
- VMSTATE_INT64(expires_ns, NPCM7xxTimer),
602
- VMSTATE_INT64(remaining_ns, NPCM7xxTimer),
603
+ VMSTATE_TIMER(qtimer, NPCM7xxBaseTimer),
604
+ VMSTATE_INT64(expires_ns, NPCM7xxBaseTimer),
605
+ VMSTATE_INT64(remaining_ns, NPCM7xxBaseTimer),
606
+ VMSTATE_END_OF_LIST(),
607
+ },
608
+};
609
+
610
+static const VMStateDescription vmstate_npcm7xx_timer = {
611
+ .name = "npcm7xx-timer",
612
+ .version_id = 1,
613
+ .minimum_version_id = 1,
614
+ .fields = (VMStateField[]) {
615
+ VMSTATE_STRUCT(base_timer, NPCM7xxTimer,
616
+ 0, vmstate_npcm7xx_base_timer,
617
+ NPCM7xxBaseTimer),
618
VMSTATE_UINT32(tcsr, NPCM7xxTimer),
619
VMSTATE_UINT32(ticr, NPCM7xxTimer),
620
VMSTATE_END_OF_LIST(),
621
},
622
};
623
624
-static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
625
- .name = "npcm7xx-timer-ctrl",
626
+static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
627
+ .name = "npcm7xx-watchdog-timer",
628
.version_id = 0,
629
.minimum_version_id = 0,
630
+ .fields = (VMStateField[]) {
631
+ VMSTATE_STRUCT(base_timer, NPCM7xxWatchdogTimer,
632
+ 0, vmstate_npcm7xx_base_timer,
633
+ NPCM7xxBaseTimer),
634
+ VMSTATE_UINT32(wtcr, NPCM7xxWatchdogTimer),
635
+ VMSTATE_END_OF_LIST(),
636
+ },
637
+};
638
+
639
+static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
640
+ .name = "npcm7xx-timer-ctrl",
641
+ .version_id = 1,
642
+ .minimum_version_id = 1,
643
.fields = (VMStateField[]) {
644
VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
645
- VMSTATE_UINT32(wtcr, NPCM7xxTimerCtrlState),
646
VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
647
NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
648
NPCM7xxTimer),
649
+ VMSTATE_STRUCT(watchdog_timer, NPCM7xxTimerCtrlState,
650
+ 0, vmstate_npcm7xx_watchdog_timer,
651
+ NPCM7xxWatchdogTimer),
652
VMSTATE_END_OF_LIST(),
653
},
654
};
655
diff --git a/tests/qtest/npcm7xx_watchdog_timer-test.c b/tests/qtest/npcm7xx_watchdog_timer-test.c
656
new file mode 100644
657
index XXXXXXX..XXXXXXX
658
--- /dev/null
659
+++ b/tests/qtest/npcm7xx_watchdog_timer-test.c
660
@@ -XXX,XX +XXX,XX @@
661
+/*
662
+ * QTests for Nuvoton NPCM7xx Timer Watchdog Modules.
663
+ *
664
+ * Copyright 2020 Google LLC
665
+ *
666
+ * This program is free software; you can redistribute it and/or modify it
667
+ * under the terms of the GNU General Public License as published by the
668
+ * Free Software Foundation; either version 2 of the License, or
669
+ * (at your option) any later version.
670
+ *
671
+ * This program is distributed in the hope that it will be useful, but WITHOUT
672
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
673
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
674
+ * for more details.
675
+ */
676
+
677
+#include "qemu/osdep.h"
678
+#include "qemu/timer.h"
679
+
680
+#include "libqos/libqtest.h"
681
+#include "qapi/qmp/qdict.h"
682
+
683
+#define WTCR_OFFSET 0x1c
684
+#define REF_HZ (25000000)
685
+
686
+/* WTCR bit fields */
687
+#define WTCLK(rv) ((rv) << 10)
688
+#define WTE BIT(7)
689
+#define WTIE BIT(6)
690
+#define WTIS(rv) ((rv) << 4)
691
+#define WTIF BIT(3)
692
+#define WTRF BIT(2)
693
+#define WTRE BIT(1)
694
+#define WTR BIT(0)
695
+
696
+typedef struct Watchdog {
697
+ int irq;
698
+ uint64_t base_addr;
699
+} Watchdog;
700
+
701
+static const Watchdog watchdog_list[] = {
702
+ {
703
+ .irq = 47,
704
+ .base_addr = 0xf0008000
705
+ },
706
+ {
707
+ .irq = 48,
708
+ .base_addr = 0xf0009000
709
+ },
710
+ {
711
+ .irq = 49,
712
+ .base_addr = 0xf000a000
713
+ }
714
+};
715
+
716
+static int watchdog_index(const Watchdog *wd)
717
+{
718
+ ptrdiff_t diff = wd - watchdog_list;
719
+
720
+ g_assert(diff >= 0 && diff < ARRAY_SIZE(watchdog_list));
721
+
722
+ return diff;
723
+}
724
+
725
+static uint32_t watchdog_read_wtcr(QTestState *qts, const Watchdog *wd)
726
+{
727
+ return qtest_readl(qts, wd->base_addr + WTCR_OFFSET);
728
+}
729
+
730
+static void watchdog_write_wtcr(QTestState *qts, const Watchdog *wd,
731
+ uint32_t value)
732
+{
733
+ qtest_writel(qts, wd->base_addr + WTCR_OFFSET, value);
734
+}
735
+
736
+static uint32_t watchdog_prescaler(QTestState *qts, const Watchdog *wd)
737
+{
738
+ switch (extract32(watchdog_read_wtcr(qts, wd), 10, 2)) {
739
+ case 0:
740
+ return 1;
741
+ case 1:
742
+ return 256;
743
+ case 2:
744
+ return 2048;
745
+ case 3:
746
+ return 65536;
82
+ default:
747
+ default:
83
+ g_assert_not_reached();
748
+ g_assert_not_reached();
84
+ }
749
+ }
85
+}
750
+}
86
+
751
+
87
+static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var)
752
+static QDict *get_watchdog_action(QTestState *qts)
88
+{
753
+{
89
+ long offset = neon_element_offset(reg, ele, size);
754
+ QDict *ev = qtest_qmp_eventwait_ref(qts, "WATCHDOG");
90
+
755
+ QDict *data;
91
+ switch (size) {
756
+
92
+ case MO_8:
757
+ data = qdict_get_qdict(ev, "data");
93
+ tcg_gen_st8_i32(var, cpu_env, offset);
758
+ qobject_ref(data);
94
+ break;
759
+ qobject_unref(ev);
95
+ case MO_16:
760
+ return data;
96
+ tcg_gen_st16_i32(var, cpu_env, offset);
761
+}
97
+ break;
762
+
98
+ case MO_32:
763
+#define RESET_CYCLES 1024
99
+ tcg_gen_st_i32(var, cpu_env, offset);
764
+static uint32_t watchdog_interrupt_cycles(QTestState *qts, const Watchdog *wd)
100
+ break;
765
+{
101
+ default:
766
+ uint32_t wtis = extract32(watchdog_read_wtcr(qts, wd), 4, 2);
102
+ g_assert_not_reached();
767
+ return 1 << (14 + 2 * wtis);
768
+}
769
+
770
+static int64_t watchdog_calculate_steps(uint32_t count, uint32_t prescale)
771
+{
772
+ return (NANOSECONDS_PER_SECOND / REF_HZ) * count * prescale;
773
+}
774
+
775
+static int64_t watchdog_interrupt_steps(QTestState *qts, const Watchdog *wd)
776
+{
777
+ return watchdog_calculate_steps(watchdog_interrupt_cycles(qts, wd),
778
+ watchdog_prescaler(qts, wd));
779
+}
780
+
781
+/* Check wtcr can be reset to default value */
782
+static void test_init(gconstpointer watchdog)
783
+{
784
+ const Watchdog *wd = watchdog;
785
+ QTestState *qts = qtest_init("-machine quanta-gsj");
786
+
787
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
788
+
789
+ watchdog_write_wtcr(qts, wd, WTCLK(1) | WTRF | WTIF | WTR);
790
+ g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(1));
791
+
792
+ qtest_quit(qts);
793
+}
794
+
795
+/* Check a watchdog can generate interrupt and reset actions */
796
+static void test_reset_action(gconstpointer watchdog)
797
+{
798
+ const Watchdog *wd = watchdog;
799
+ QTestState *qts = qtest_init("-machine quanta-gsj");
800
+ QDict *ad;
801
+
802
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
803
+
804
+ watchdog_write_wtcr(qts, wd,
805
+ WTCLK(0) | WTE | WTRF | WTRE | WTIF | WTIE | WTR);
806
+ g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==,
807
+ WTCLK(0) | WTE | WTRE | WTIE);
808
+
809
+ /* Check a watchdog can generate an interrupt */
810
+ qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
811
+ g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==,
812
+ WTCLK(0) | WTE | WTIF | WTIE | WTRE);
813
+ g_assert_true(qtest_get_irq(qts, wd->irq));
814
+
815
+ /* Check a watchdog can generate a reset signal */
816
+ qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
817
+ watchdog_prescaler(qts, wd)));
818
+ ad = get_watchdog_action(qts);
819
+ /* The signal is a reset signal */
820
+ g_assert_false(strcmp(qdict_get_str(ad, "action"), "reset"));
821
+ qobject_unref(ad);
822
+ qtest_qmp_eventwait(qts, "RESET");
823
+ /*
824
+ * Make sure WTCR is reset to default except for WTRF bit which shouldn't
825
+ * be reset.
826
+ */
827
+ g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(1) | WTRF);
828
+ qtest_quit(qts);
829
+}
830
+
831
+/* Check a watchdog works with all possible WTCLK prescalers and WTIS cycles */
832
+static void test_prescaler(gconstpointer watchdog)
833
+{
834
+ const Watchdog *wd = watchdog;
835
+
836
+ for (int wtclk = 0; wtclk < 4; ++wtclk) {
837
+ for (int wtis = 0; wtis < 4; ++wtis) {
838
+ QTestState *qts = qtest_init("-machine quanta-gsj");
839
+
840
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
841
+ watchdog_write_wtcr(qts, wd,
842
+ WTCLK(wtclk) | WTE | WTIF | WTIS(wtis) | WTIE | WTR);
843
+ /*
844
+ * The interrupt doesn't fire until watchdog_interrupt_steps()
845
+ * cycles passed
846
+ */
847
+ qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd) - 1);
848
+ g_assert_false(watchdog_read_wtcr(qts, wd) & WTIF);
849
+ g_assert_false(qtest_get_irq(qts, wd->irq));
850
+ qtest_clock_step(qts, 1);
851
+ g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
852
+ g_assert_true(qtest_get_irq(qts, wd->irq));
853
+
854
+ qtest_quit(qts);
855
+ }
103
+ }
856
+ }
104
+}
857
+}
105
+
858
+
106
+static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var)
859
+/*
107
+{
860
+ * Check a watchdog doesn't fire if corresponding flags (WTIE and WTRE) are not
108
+ long offset = neon_element_offset(reg, ele, size);
861
+ * set.
109
+
862
+ */
110
+ switch (size) {
863
+static void test_enabling_flags(gconstpointer watchdog)
111
+ case MO_8:
864
+{
112
+ tcg_gen_st8_i64(var, cpu_env, offset);
865
+ const Watchdog *wd = watchdog;
113
+ break;
866
+ QTestState *qts;
114
+ case MO_16:
867
+
115
+ tcg_gen_st16_i64(var, cpu_env, offset);
868
+ /* Neither WTIE or WTRE is set, no interrupt or reset should happen */
116
+ break;
869
+ qts = qtest_init("-machine quanta-gsj");
117
+ case MO_32:
870
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
118
+ tcg_gen_st32_i64(var, cpu_env, offset);
871
+ watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTRF | WTR);
119
+ break;
872
+ qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
120
+ case MO_64:
873
+ g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
121
+ tcg_gen_st_i64(var, cpu_env, offset);
874
+ g_assert_false(qtest_get_irq(qts, wd->irq));
122
+ break;
875
+ qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
123
+ default:
876
+ watchdog_prescaler(qts, wd)));
124
+ g_assert_not_reached();
877
+ g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
878
+ g_assert_false(watchdog_read_wtcr(qts, wd) & WTRF);
879
+ qtest_quit(qts);
880
+
881
+ /* Only WTIE is set, interrupt is triggered but reset should not happen */
882
+ qts = qtest_init("-machine quanta-gsj");
883
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
884
+ watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTIE | WTRF | WTR);
885
+ qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
886
+ g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
887
+ g_assert_true(qtest_get_irq(qts, wd->irq));
888
+ qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
889
+ watchdog_prescaler(qts, wd)));
890
+ g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
891
+ g_assert_false(watchdog_read_wtcr(qts, wd) & WTRF);
892
+ qtest_quit(qts);
893
+
894
+ /* Only WTRE is set, interrupt is triggered but reset should not happen */
895
+ qts = qtest_init("-machine quanta-gsj");
896
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
897
+ watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTRE | WTRF | WTR);
898
+ qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
899
+ g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
900
+ g_assert_false(qtest_get_irq(qts, wd->irq));
901
+ qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
902
+ watchdog_prescaler(qts, wd)));
903
+ g_assert_false(strcmp(qdict_get_str(get_watchdog_action(qts), "action"),
904
+ "reset"));
905
+ qtest_qmp_eventwait(qts, "RESET");
906
+ qtest_quit(qts);
907
+
908
+ /*
909
+ * The case when both flags are set is already tested in
910
+ * test_reset_action().
911
+ */
912
+}
913
+
914
+/* Check a watchdog can pause and resume by setting WTE bits */
915
+static void test_pause(gconstpointer watchdog)
916
+{
917
+ const Watchdog *wd = watchdog;
918
+ QTestState *qts;
919
+ int64_t remaining_steps, steps;
920
+
921
+ qts = qtest_init("-machine quanta-gsj");
922
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
923
+ watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTIE | WTRF | WTR);
924
+ remaining_steps = watchdog_interrupt_steps(qts, wd);
925
+ g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTE | WTIE);
926
+
927
+ /* Run for half of the execution period. */
928
+ steps = remaining_steps / 2;
929
+ remaining_steps -= steps;
930
+ qtest_clock_step(qts, steps);
931
+
932
+ /* Pause the watchdog */
933
+ watchdog_write_wtcr(qts, wd, WTCLK(0) | WTIE);
934
+ g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTIE);
935
+
936
+ /* Run for a long period of time, the watchdog shouldn't fire */
937
+ qtest_clock_step(qts, steps << 4);
938
+ g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTIE);
939
+ g_assert_false(qtest_get_irq(qts, wd->irq));
940
+
941
+ /* Resume the watchdog */
942
+ watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIE);
943
+ g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTE | WTIE);
944
+
945
+ /* Run for the reset of the execution period, the watchdog should fire */
946
+ qtest_clock_step(qts, remaining_steps);
947
+ g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==,
948
+ WTCLK(0) | WTE | WTIF | WTIE);
949
+ g_assert_true(qtest_get_irq(qts, wd->irq));
950
+
951
+ qtest_quit(qts);
952
+}
953
+
954
+static void watchdog_add_test(const char *name, const Watchdog* wd,
955
+ GTestDataFunc fn)
956
+{
957
+ g_autofree char *full_name = g_strdup_printf(
958
+ "npcm7xx_watchdog_timer[%d]/%s", watchdog_index(wd), name);
959
+ qtest_add_data_func(full_name, wd, fn);
960
+}
961
+#define add_test(name, td) watchdog_add_test(#name, td, test_##name)
962
+
963
+int main(int argc, char **argv)
964
+{
965
+ g_test_init(&argc, &argv, NULL);
966
+ g_test_set_nonfatal_assertions();
967
+
968
+ for (int i = 0; i < ARRAY_SIZE(watchdog_list); ++i) {
969
+ const Watchdog *wd = &watchdog_list[i];
970
+
971
+ add_test(init, wd);
972
+ add_test(reset_action, wd);
973
+ add_test(prescaler, wd);
974
+ add_test(enabling_flags, wd);
975
+ add_test(pause, wd);
125
+ }
976
+ }
126
+}
977
+
127
+
978
+ return g_test_run();
128
static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
979
+}
129
{
980
diff --git a/MAINTAINERS b/MAINTAINERS
130
int opr_sz;
131
diff --git a/target/arm/translate.c b/target/arm/translate.c
132
index XXXXXXX..XXXXXXX 100644
981
index XXXXXXX..XXXXXXX 100644
133
--- a/target/arm/translate.c
982
--- a/MAINTAINERS
134
+++ b/target/arm/translate.c
983
+++ b/MAINTAINERS
135
@@ -XXX,XX +XXX,XX @@ neon_reg_offset (int reg, int n)
984
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
136
return vfp_reg_offset(0, sreg);
985
S: Supported
137
}
986
F: hw/*/npcm7xx*
138
987
F: include/hw/*/npcm7xx*
139
-/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
988
+F: tests/qtest/npcm7xx*
140
- * where 0 is the least significant end of the register.
989
F: pc-bios/npcm7xx_bootrom.bin
141
- */
990
F: roms/vbootrom
142
-static inline long
991
143
-neon_element_offset(int reg, int element, MemOp size)
992
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
144
-{
993
index XXXXXXX..XXXXXXX 100644
145
- int element_size = 1 << size;
994
--- a/tests/qtest/meson.build
146
- int ofs = element * element_size;
995
+++ b/tests/qtest/meson.build
147
-#ifdef HOST_WORDS_BIGENDIAN
996
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
148
- /* Calculate the offset assuming fully little-endian,
997
(config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] : []) + \
149
- * then XOR to account for the order of the 8-byte units.
998
['prom-env-test', 'boot-serial-test']
150
- */
999
151
- if (element_size < 8) {
1000
-qtests_npcm7xx = ['npcm7xx_timer-test']
152
- ofs ^= 8 - element_size;
1001
+qtests_npcm7xx = ['npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test']
153
- }
1002
qtests_arm = \
154
-#endif
1003
(config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
155
- return neon_reg_offset(reg, 0) + ofs;
1004
(config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
156
-}
157
-
158
static TCGv_i32 neon_load_reg(int reg, int pass)
159
{
160
TCGv_i32 tmp = tcg_temp_new_i32();
161
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 neon_load_reg(int reg, int pass)
162
return tmp;
163
}
164
165
-static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
166
-{
167
- long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
168
-
169
- switch (mop) {
170
- case MO_UB:
171
- tcg_gen_ld8u_i32(var, cpu_env, offset);
172
- break;
173
- case MO_UW:
174
- tcg_gen_ld16u_i32(var, cpu_env, offset);
175
- break;
176
- case MO_UL:
177
- tcg_gen_ld_i32(var, cpu_env, offset);
178
- break;
179
- default:
180
- g_assert_not_reached();
181
- }
182
-}
183
-
184
-static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop)
185
-{
186
- long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
187
-
188
- switch (mop) {
189
- case MO_UB:
190
- tcg_gen_ld8u_i64(var, cpu_env, offset);
191
- break;
192
- case MO_UW:
193
- tcg_gen_ld16u_i64(var, cpu_env, offset);
194
- break;
195
- case MO_UL:
196
- tcg_gen_ld32u_i64(var, cpu_env, offset);
197
- break;
198
- case MO_Q:
199
- tcg_gen_ld_i64(var, cpu_env, offset);
200
- break;
201
- default:
202
- g_assert_not_reached();
203
- }
204
-}
205
-
206
static void neon_store_reg(int reg, int pass, TCGv_i32 var)
207
{
208
tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
209
tcg_temp_free_i32(var);
210
}
211
212
-static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var)
213
-{
214
- long offset = neon_element_offset(reg, ele, size);
215
-
216
- switch (size) {
217
- case MO_8:
218
- tcg_gen_st8_i32(var, cpu_env, offset);
219
- break;
220
- case MO_16:
221
- tcg_gen_st16_i32(var, cpu_env, offset);
222
- break;
223
- case MO_32:
224
- tcg_gen_st_i32(var, cpu_env, offset);
225
- break;
226
- default:
227
- g_assert_not_reached();
228
- }
229
-}
230
-
231
-static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var)
232
-{
233
- long offset = neon_element_offset(reg, ele, size);
234
-
235
- switch (size) {
236
- case MO_8:
237
- tcg_gen_st8_i64(var, cpu_env, offset);
238
- break;
239
- case MO_16:
240
- tcg_gen_st16_i64(var, cpu_env, offset);
241
- break;
242
- case MO_32:
243
- tcg_gen_st32_i64(var, cpu_env, offset);
244
- break;
245
- case MO_64:
246
- tcg_gen_st_i64(var, cpu_env, offset);
247
- break;
248
- default:
249
- g_assert_not_reached();
250
- }
251
-}
252
-
253
static inline void neon_load_reg64(TCGv_i64 var, int reg)
254
{
255
tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
256
--
1005
--
257
2.20.1
1006
2.20.1
258
1007
259
1008
diff view generated by jsdifflib
1
From: Andrew Jones <drjones@redhat.com>
1
From: Havard Skinnemoen <hskinnemoen@google.com>
2
2
3
Some cpu features may be enabled and disabled for all configurations
3
The RNG module returns a byte of randomness when the Data Valid bit is
4
that support the feature. Let's test that.
4
set.
5
5
6
A recent regression[*] inspired adding these tests.
6
This implementation ignores the prescaler setting, and loads a new value
7
into RNGD every time RNGCS is read while the RNG is enabled and random
8
data is available.
7
9
8
[*] '-cpu host,pmu=on' caused a segfault
10
A qtest featuring some simple randomness tests is included.
9
11
10
Signed-off-by: Andrew Jones <drjones@redhat.com>
12
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
11
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20200623090622.30365-2-philmd@redhat.com
13
Message-Id: <20200623082310.17577-1-drjones@redhat.com>
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
16
---
17
tests/qtest/arm-cpu-features.c | 38 ++++++++++++++++++++++++++++++----
17
docs/system/arm/nuvoton.rst | 2 +-
18
1 file changed, 34 insertions(+), 4 deletions(-)
18
include/hw/arm/npcm7xx.h | 2 +
19
include/hw/misc/npcm7xx_rng.h | 34 ++++
20
hw/arm/npcm7xx.c | 7 +-
21
hw/misc/npcm7xx_rng.c | 180 +++++++++++++++++++++
22
tests/qtest/npcm7xx_rng-test.c | 278 +++++++++++++++++++++++++++++++++
23
hw/misc/meson.build | 1 +
24
hw/misc/trace-events | 4 +
25
tests/qtest/meson.build | 5 +-
26
9 files changed, 510 insertions(+), 3 deletions(-)
27
create mode 100644 include/hw/misc/npcm7xx_rng.h
28
create mode 100644 hw/misc/npcm7xx_rng.c
29
create mode 100644 tests/qtest/npcm7xx_rng-test.c
19
30
20
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
31
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
21
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
22
--- a/tests/qtest/arm-cpu-features.c
33
--- a/docs/system/arm/nuvoton.rst
23
+++ b/tests/qtest/arm-cpu-features.c
34
+++ b/docs/system/arm/nuvoton.rst
24
@@ -XXX,XX +XXX,XX @@ static bool resp_get_feature(QDict *resp, const char *feature)
35
@@ -XXX,XX +XXX,XX @@ Supported devices
25
qobject_unref(_resp); \
36
* DDR4 memory controller (dummy interface indicating memory training is done)
26
})
37
* OTP controllers (no protection features)
27
38
* Flash Interface Unit (FIU; no protection features)
28
-#define assert_feature(qts, cpu_type, feature, expected_value) \
39
+ * Random Number Generator (RNG)
29
+#define resp_assert_feature(resp, feature, expected_value) \
40
30
({ \
41
Missing devices
31
- QDict *_resp, *_props; \
42
---------------
32
+ QDict *_props; \
43
@@ -XXX,XX +XXX,XX @@ Missing devices
33
\
44
* Peripheral SPI controller (PSPI)
34
- _resp = do_query_no_props(qts, cpu_type); \
45
* Analog to Digital Converter (ADC)
35
g_assert(_resp); \
46
* SD/MMC host
36
g_assert(resp_has_props(_resp)); \
47
- * Random Number Generator (RNG)
37
_props = resp_get_props(_resp); \
48
* PECI interface
38
g_assert(qdict_get(_props, feature)); \
49
* Pulse Width Modulation (PWM)
39
g_assert(qdict_get_bool(_props, feature) == (expected_value)); \
50
* Tachometer
40
+})
51
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
41
+
52
index XXXXXXX..XXXXXXX 100644
42
+#define assert_feature(qts, cpu_type, feature, expected_value) \
53
--- a/include/hw/arm/npcm7xx.h
43
+({ \
54
+++ b/include/hw/arm/npcm7xx.h
44
+ QDict *_resp; \
55
@@ -XXX,XX +XXX,XX @@
45
+ \
56
#include "hw/mem/npcm7xx_mc.h"
46
+ _resp = do_query_no_props(qts, cpu_type); \
57
#include "hw/misc/npcm7xx_clk.h"
47
+ g_assert(_resp); \
58
#include "hw/misc/npcm7xx_gcr.h"
48
+ resp_assert_feature(_resp, feature, expected_value); \
59
+#include "hw/misc/npcm7xx_rng.h"
49
+ qobject_unref(_resp); \
60
#include "hw/nvram/npcm7xx_otp.h"
50
+})
61
#include "hw/timer/npcm7xx_timer.h"
51
+
62
#include "hw/ssi/npcm7xx_fiu.h"
52
+#define assert_set_feature(qts, cpu_type, feature, value) \
63
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
53
+({ \
64
NPCM7xxOTPState key_storage;
54
+ const char *_fmt = (value) ? "{ %s: true }" : "{ %s: false }"; \
65
NPCM7xxOTPState fuse_array;
55
+ QDict *_resp; \
66
NPCM7xxMCState mc;
56
+ \
67
+ NPCM7xxRNGState rng;
57
+ _resp = do_query(qts, cpu_type, _fmt, feature); \
68
NPCM7xxFIUState fiu[2];
58
+ g_assert(_resp); \
69
} NPCM7xxState;
59
+ resp_assert_feature(_resp, feature, value); \
70
60
qobject_unref(_resp); \
71
diff --git a/include/hw/misc/npcm7xx_rng.h b/include/hw/misc/npcm7xx_rng.h
61
})
72
new file mode 100644
62
73
index XXXXXXX..XXXXXXX
63
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
74
--- /dev/null
64
assert_error(qts, "host", "The CPU type 'host' requires KVM", NULL);
75
+++ b/include/hw/misc/npcm7xx_rng.h
65
76
@@ -XXX,XX +XXX,XX @@
66
/* Test expected feature presence/absence for some cpu types */
77
+/*
67
- assert_has_feature_enabled(qts, "max", "pmu");
78
+ * Nuvoton NPCM7xx Random Number Generator.
68
assert_has_feature_enabled(qts, "cortex-a15", "pmu");
79
+ *
69
assert_has_not_feature(qts, "cortex-a15", "aarch64");
80
+ * Copyright 2020 Google LLC
70
81
+ *
71
+ /* Enabling and disabling pmu should always work. */
82
+ * This program is free software; you can redistribute it and/or modify it
72
+ assert_has_feature_enabled(qts, "max", "pmu");
83
+ * under the terms of the GNU General Public License as published by the
73
+ assert_set_feature(qts, "max", "pmu", false);
84
+ * Free Software Foundation; either version 2 of the License, or
74
+ assert_set_feature(qts, "max", "pmu", true);
85
+ * (at your option) any later version.
75
+
86
+ *
76
assert_has_not_feature(qts, "max", "kvm-no-adjvtime");
87
+ * This program is distributed in the hope that it will be useful, but WITHOUT
77
88
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
78
if (g_str_equal(qtest_get_arch(), "aarch64")) {
89
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
79
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
90
+ * for more details.
80
return;
91
+ */
92
+#ifndef NPCM7XX_RNG_H
93
+#define NPCM7XX_RNG_H
94
+
95
+#include "hw/sysbus.h"
96
+
97
+typedef struct NPCM7xxRNGState {
98
+ SysBusDevice parent;
99
+
100
+ MemoryRegion iomem;
101
+
102
+ uint8_t rngcs;
103
+ uint8_t rngd;
104
+ uint8_t rngmode;
105
+} NPCM7xxRNGState;
106
+
107
+#define TYPE_NPCM7XX_RNG "npcm7xx-rng"
108
+#define NPCM7XX_RNG(obj) OBJECT_CHECK(NPCM7xxRNGState, (obj), TYPE_NPCM7XX_RNG)
109
+
110
+#endif /* NPCM7XX_RNG_H */
111
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
112
index XXXXXXX..XXXXXXX 100644
113
--- a/hw/arm/npcm7xx.c
114
+++ b/hw/arm/npcm7xx.c
115
@@ -XXX,XX +XXX,XX @@
116
#define NPCM7XX_GCR_BA (0xf0800000)
117
#define NPCM7XX_CLK_BA (0xf0801000)
118
#define NPCM7XX_MC_BA (0xf0824000)
119
+#define NPCM7XX_RNG_BA (0xf000b000)
120
121
/* Internal AHB SRAM */
122
#define NPCM7XX_RAM3_BA (0xc0008000)
123
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
124
object_initialize_child(obj, "otp2", &s->fuse_array,
125
TYPE_NPCM7XX_FUSE_ARRAY);
126
object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
127
+ object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
128
129
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
130
object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
131
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
132
serial_hd(i), DEVICE_LITTLE_ENDIAN);
81
}
133
}
82
134
83
+ /* Enabling and disabling kvm-no-adjvtime should always work. */
135
+ /* Random Number Generator. Cannot fail. */
84
assert_has_feature_disabled(qts, "host", "kvm-no-adjvtime");
136
+ sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort);
85
+ assert_set_feature(qts, "host", "kvm-no-adjvtime", true);
137
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA);
86
+ assert_set_feature(qts, "host", "kvm-no-adjvtime", false);
138
+
87
139
/*
88
if (g_str_equal(qtest_get_arch(), "aarch64")) {
140
* Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
89
bool kvm_supports_sve;
141
* specified, but this is a programming error.
90
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
142
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
91
char *error;
143
create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB);
92
144
create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
93
assert_has_feature_enabled(qts, "host", "aarch64");
145
create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);
94
+
146
- create_unimplemented_device("npcm7xx.rng", 0xf000b000, 4 * KiB);
95
+ /* Enabling and disabling pmu should always work. */
147
create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB);
96
assert_has_feature_enabled(qts, "host", "pmu");
148
create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB);
97
+ assert_set_feature(qts, "host", "pmu", false);
149
create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB);
98
+ assert_set_feature(qts, "host", "pmu", true);
150
diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c
99
151
new file mode 100644
100
assert_error(qts, "cortex-a15",
152
index XXXXXXX..XXXXXXX
101
"We cannot guarantee the CPU type 'cortex-a15' works "
153
--- /dev/null
154
+++ b/hw/misc/npcm7xx_rng.c
155
@@ -XXX,XX +XXX,XX @@
156
+/*
157
+ * Nuvoton NPCM7xx Random Number Generator.
158
+ *
159
+ * Copyright 2020 Google LLC
160
+ *
161
+ * This program is free software; you can redistribute it and/or modify it
162
+ * under the terms of the GNU General Public License as published by the
163
+ * Free Software Foundation; either version 2 of the License, or
164
+ * (at your option) any later version.
165
+ *
166
+ * This program is distributed in the hope that it will be useful, but WITHOUT
167
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
168
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
169
+ * for more details.
170
+ */
171
+
172
+#include "qemu/osdep.h"
173
+
174
+#include "hw/misc/npcm7xx_rng.h"
175
+#include "migration/vmstate.h"
176
+#include "qemu/bitops.h"
177
+#include "qemu/guest-random.h"
178
+#include "qemu/log.h"
179
+#include "qemu/module.h"
180
+#include "qemu/units.h"
181
+
182
+#include "trace.h"
183
+
184
+#define NPCM7XX_RNG_REGS_SIZE (4 * KiB)
185
+
186
+#define NPCM7XX_RNGCS (0x00)
187
+#define NPCM7XX_RNGCS_CLKP(rv) extract32(rv, 2, 4)
188
+#define NPCM7XX_RNGCS_DVALID BIT(1)
189
+#define NPCM7XX_RNGCS_RNGE BIT(0)
190
+
191
+#define NPCM7XX_RNGD (0x04)
192
+#define NPCM7XX_RNGMODE (0x08)
193
+#define NPCM7XX_RNGMODE_NORMAL (0x02)
194
+
195
+static bool npcm7xx_rng_is_enabled(NPCM7xxRNGState *s)
196
+{
197
+ return (s->rngcs & NPCM7XX_RNGCS_RNGE) &&
198
+ (s->rngmode == NPCM7XX_RNGMODE_NORMAL);
199
+}
200
+
201
+static uint64_t npcm7xx_rng_read(void *opaque, hwaddr offset, unsigned size)
202
+{
203
+ NPCM7xxRNGState *s = opaque;
204
+ uint64_t value = 0;
205
+
206
+ switch (offset) {
207
+ case NPCM7XX_RNGCS:
208
+ /*
209
+ * If the RNG is enabled, but we don't have any valid random data, try
210
+ * obtaining some and update the DVALID bit accordingly.
211
+ */
212
+ if (!npcm7xx_rng_is_enabled(s)) {
213
+ s->rngcs &= ~NPCM7XX_RNGCS_DVALID;
214
+ } else if (!(s->rngcs & NPCM7XX_RNGCS_DVALID)) {
215
+ uint8_t byte = 0;
216
+
217
+ if (qemu_guest_getrandom(&byte, sizeof(byte), NULL) == 0) {
218
+ s->rngd = byte;
219
+ s->rngcs |= NPCM7XX_RNGCS_DVALID;
220
+ }
221
+ }
222
+ value = s->rngcs;
223
+ break;
224
+ case NPCM7XX_RNGD:
225
+ if (npcm7xx_rng_is_enabled(s) && s->rngcs & NPCM7XX_RNGCS_DVALID) {
226
+ s->rngcs &= ~NPCM7XX_RNGCS_DVALID;
227
+ value = s->rngd;
228
+ s->rngd = 0;
229
+ }
230
+ break;
231
+ case NPCM7XX_RNGMODE:
232
+ value = s->rngmode;
233
+ break;
234
+
235
+ default:
236
+ qemu_log_mask(LOG_GUEST_ERROR,
237
+ "%s: read from invalid offset 0x%" HWADDR_PRIx "\n",
238
+ DEVICE(s)->canonical_path, offset);
239
+ break;
240
+ }
241
+
242
+ trace_npcm7xx_rng_read(offset, value, size);
243
+
244
+ return value;
245
+}
246
+
247
+static void npcm7xx_rng_write(void *opaque, hwaddr offset, uint64_t value,
248
+ unsigned size)
249
+{
250
+ NPCM7xxRNGState *s = opaque;
251
+
252
+ trace_npcm7xx_rng_write(offset, value, size);
253
+
254
+ switch (offset) {
255
+ case NPCM7XX_RNGCS:
256
+ s->rngcs &= NPCM7XX_RNGCS_DVALID;
257
+ s->rngcs |= value & ~NPCM7XX_RNGCS_DVALID;
258
+ break;
259
+ case NPCM7XX_RNGD:
260
+ qemu_log_mask(LOG_GUEST_ERROR,
261
+ "%s: write to read-only register @ 0x%" HWADDR_PRIx "\n",
262
+ DEVICE(s)->canonical_path, offset);
263
+ break;
264
+ case NPCM7XX_RNGMODE:
265
+ s->rngmode = value;
266
+ break;
267
+ default:
268
+ qemu_log_mask(LOG_GUEST_ERROR,
269
+ "%s: write to invalid offset 0x%" HWADDR_PRIx "\n",
270
+ DEVICE(s)->canonical_path, offset);
271
+ break;
272
+ }
273
+}
274
+
275
+static const MemoryRegionOps npcm7xx_rng_ops = {
276
+ .read = npcm7xx_rng_read,
277
+ .write = npcm7xx_rng_write,
278
+ .endianness = DEVICE_LITTLE_ENDIAN,
279
+ .valid = {
280
+ .min_access_size = 1,
281
+ .max_access_size = 4,
282
+ .unaligned = false,
283
+ },
284
+};
285
+
286
+static void npcm7xx_rng_enter_reset(Object *obj, ResetType type)
287
+{
288
+ NPCM7xxRNGState *s = NPCM7XX_RNG(obj);
289
+
290
+ s->rngcs = 0;
291
+ s->rngd = 0;
292
+ s->rngmode = 0;
293
+}
294
+
295
+static void npcm7xx_rng_init(Object *obj)
296
+{
297
+ NPCM7xxRNGState *s = NPCM7XX_RNG(obj);
298
+
299
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs",
300
+ NPCM7XX_RNG_REGS_SIZE);
301
+ sysbus_init_mmio(&s->parent, &s->iomem);
302
+}
303
+
304
+static const VMStateDescription vmstate_npcm7xx_rng = {
305
+ .name = "npcm7xx-rng",
306
+ .version_id = 0,
307
+ .minimum_version_id = 0,
308
+ .fields = (VMStateField[]) {
309
+ VMSTATE_UINT8(rngcs, NPCM7xxRNGState),
310
+ VMSTATE_UINT8(rngd, NPCM7xxRNGState),
311
+ VMSTATE_UINT8(rngmode, NPCM7xxRNGState),
312
+ VMSTATE_END_OF_LIST(),
313
+ },
314
+};
315
+
316
+static void npcm7xx_rng_class_init(ObjectClass *klass, void *data)
317
+{
318
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
319
+ DeviceClass *dc = DEVICE_CLASS(klass);
320
+
321
+ dc->desc = "NPCM7xx Random Number Generator";
322
+ dc->vmsd = &vmstate_npcm7xx_rng;
323
+ rc->phases.enter = npcm7xx_rng_enter_reset;
324
+}
325
+
326
+static const TypeInfo npcm7xx_rng_types[] = {
327
+ {
328
+ .name = TYPE_NPCM7XX_RNG,
329
+ .parent = TYPE_SYS_BUS_DEVICE,
330
+ .instance_size = sizeof(NPCM7xxRNGState),
331
+ .class_init = npcm7xx_rng_class_init,
332
+ .instance_init = npcm7xx_rng_init,
333
+ },
334
+};
335
+DEFINE_TYPES(npcm7xx_rng_types);
336
diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
337
new file mode 100644
338
index XXXXXXX..XXXXXXX
339
--- /dev/null
340
+++ b/tests/qtest/npcm7xx_rng-test.c
341
@@ -XXX,XX +XXX,XX @@
342
+/*
343
+ * QTest testcase for the Nuvoton NPCM7xx Random Number Generator
344
+ *
345
+ * Copyright 2020 Google LLC
346
+ *
347
+ * This program is free software; you can redistribute it and/or modify it
348
+ * under the terms of the GNU General Public License as published by the
349
+ * Free Software Foundation; either version 2 of the License, or
350
+ * (at your option) any later version.
351
+ *
352
+ * This program is distributed in the hope that it will be useful, but WITHOUT
353
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
354
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
355
+ * for more details.
356
+ */
357
+
358
+#include "qemu/osdep.h"
359
+
360
+#include <math.h>
361
+
362
+#include "libqtest-single.h"
363
+#include "qemu/bitops.h"
364
+
365
+#define RNG_BASE_ADDR 0xf000b000
366
+
367
+/* Control and Status Register */
368
+#define RNGCS 0x00
369
+# define DVALID BIT(1) /* Data Valid */
370
+# define RNGE BIT(0) /* RNG Enable */
371
+/* Data Register */
372
+#define RNGD 0x04
373
+/* Mode Register */
374
+#define RNGMODE 0x08
375
+# define ROSEL_NORMAL (2) /* RNG only works in this mode */
376
+
377
+/* Number of bits to collect for randomness tests. */
378
+#define TEST_INPUT_BITS (128)
379
+
380
+static void rng_writeb(unsigned int offset, uint8_t value)
381
+{
382
+ writeb(RNG_BASE_ADDR + offset, value);
383
+}
384
+
385
+static uint8_t rng_readb(unsigned int offset)
386
+{
387
+ return readb(RNG_BASE_ADDR + offset);
388
+}
389
+
390
+/* Disable RNG and set normal ring oscillator mode. */
391
+static void rng_reset(void)
392
+{
393
+ rng_writeb(RNGCS, 0);
394
+ rng_writeb(RNGMODE, ROSEL_NORMAL);
395
+}
396
+
397
+/* Reset RNG and then enable it. */
398
+static void rng_reset_enable(void)
399
+{
400
+ rng_reset();
401
+ rng_writeb(RNGCS, RNGE);
402
+}
403
+
404
+/* Wait until Data Valid bit is set. */
405
+static bool rng_wait_ready(void)
406
+{
407
+ /* qemu_guest_getrandom may fail. Assume it won't fail 10 times in a row. */
408
+ int retries = 10;
409
+
410
+ while (retries-- > 0) {
411
+ if (rng_readb(RNGCS) & DVALID) {
412
+ return true;
413
+ }
414
+ }
415
+
416
+ return false;
417
+}
418
+
419
+/*
420
+ * Perform a frequency (monobit) test, as defined by NIST SP 800-22, on the
421
+ * sequence in buf and return the P-value. This represents the probability of a
422
+ * truly random sequence having the same proportion of zeros and ones as the
423
+ * sequence in buf.
424
+ *
425
+ * An RNG which always returns 0x00 or 0xff, or has some bits stuck at 0 or 1,
426
+ * will fail this test. However, an RNG which always returns 0x55, 0xf0 or some
427
+ * other value with an equal number of zeroes and ones will pass.
428
+ */
429
+static double calc_monobit_p(const uint8_t *buf, unsigned int len)
430
+{
431
+ unsigned int i;
432
+ double s_obs;
433
+ int sn = 0;
434
+
435
+ for (i = 0; i < len; i++) {
436
+ /*
437
+ * Each 1 counts as 1, each 0 counts as -1.
438
+ * s = cp - (8 - cp) = 2 * cp - 8
439
+ */
440
+ sn += 2 * ctpop8(buf[i]) - 8;
441
+ }
442
+
443
+ s_obs = abs(sn) / sqrt(len * BITS_PER_BYTE);
444
+
445
+ return erfc(s_obs / sqrt(2));
446
+}
447
+
448
+/*
449
+ * Perform a runs test, as defined by NIST SP 800-22, and return the P-value.
450
+ * This represents the probability of a truly random sequence having the same
451
+ * number of runs (i.e. uninterrupted sequences of identical bits) as the
452
+ * sequence in buf.
453
+ */
454
+static double calc_runs_p(const unsigned long *buf, unsigned int nr_bits)
455
+{
456
+ unsigned int j;
457
+ unsigned int k;
458
+ int nr_ones = 0;
459
+ int vn_obs = 0;
460
+ double pi;
461
+
462
+ g_assert(nr_bits % BITS_PER_LONG == 0);
463
+
464
+ for (j = 0; j < nr_bits / BITS_PER_LONG; j++) {
465
+ nr_ones += __builtin_popcountl(buf[j]);
466
+ }
467
+ pi = (double)nr_ones / nr_bits;
468
+
469
+ for (k = 0; k < nr_bits - 1; k++) {
470
+ vn_obs += !(test_bit(k, buf) ^ test_bit(k + 1, buf));
471
+ }
472
+ vn_obs += 1;
473
+
474
+ return erfc(fabs(vn_obs - 2 * nr_bits * pi * (1.0 - pi))
475
+ / (2 * sqrt(2 * nr_bits) * pi * (1.0 - pi)));
476
+}
477
+
478
+/*
479
+ * Verifies that DVALID is clear, and RNGD reads zero, when RNGE is cleared,
480
+ * and DVALID eventually becomes set when RNGE is set.
481
+ */
482
+static void test_enable_disable(void)
483
+{
484
+ /* Disable: DVALID should not be set, and RNGD should read zero */
485
+ rng_reset();
486
+ g_assert_cmphex(rng_readb(RNGCS), ==, 0);
487
+ g_assert_cmphex(rng_readb(RNGD), ==, 0);
488
+
489
+ /* Enable: DVALID should be set, but we can't make assumptions about RNGD */
490
+ rng_writeb(RNGCS, RNGE);
491
+ g_assert_true(rng_wait_ready());
492
+ g_assert_cmphex(rng_readb(RNGCS), ==, DVALID | RNGE);
493
+
494
+ /* Disable: DVALID should not be set, and RNGD should read zero */
495
+ rng_writeb(RNGCS, 0);
496
+ g_assert_cmphex(rng_readb(RNGCS), ==, 0);
497
+ g_assert_cmphex(rng_readb(RNGD), ==, 0);
498
+}
499
+
500
+/*
501
+ * Verifies that the RNG only produces data when RNGMODE is set to 'normal'
502
+ * ring oscillator mode.
503
+ */
504
+static void test_rosel(void)
505
+{
506
+ rng_reset_enable();
507
+ g_assert_true(rng_wait_ready());
508
+ rng_writeb(RNGMODE, 0);
509
+ g_assert_false(rng_wait_ready());
510
+ rng_writeb(RNGMODE, ROSEL_NORMAL);
511
+ g_assert_true(rng_wait_ready());
512
+ rng_writeb(RNGMODE, 0);
513
+ g_assert_false(rng_wait_ready());
514
+}
515
+
516
+/*
517
+ * Verifies that a continuous sequence of bits collected after enabling the RNG
518
+ * satisfies a monobit test.
519
+ */
520
+static void test_continuous_monobit(void)
521
+{
522
+ uint8_t buf[TEST_INPUT_BITS / BITS_PER_BYTE];
523
+ unsigned int i;
524
+
525
+ rng_reset_enable();
526
+ for (i = 0; i < sizeof(buf); i++) {
527
+ g_assert_true(rng_wait_ready());
528
+ buf[i] = rng_readb(RNGD);
529
+ }
530
+
531
+ g_assert_cmpfloat(calc_monobit_p(buf, sizeof(buf)), >, 0.01);
532
+}
533
+
534
+/*
535
+ * Verifies that a continuous sequence of bits collected after enabling the RNG
536
+ * satisfies a runs test.
537
+ */
538
+static void test_continuous_runs(void)
539
+{
540
+ union {
541
+ unsigned long l[TEST_INPUT_BITS / BITS_PER_LONG];
542
+ uint8_t c[TEST_INPUT_BITS / BITS_PER_BYTE];
543
+ } buf;
544
+ unsigned int i;
545
+
546
+ rng_reset_enable();
547
+ for (i = 0; i < sizeof(buf); i++) {
548
+ g_assert_true(rng_wait_ready());
549
+ buf.c[i] = rng_readb(RNGD);
550
+ }
551
+
552
+ g_assert_cmpfloat(calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE), >, 0.01);
553
+}
554
+
555
+/*
556
+ * Verifies that the first data byte collected after enabling the RNG satisfies
557
+ * a monobit test.
558
+ */
559
+static void test_first_byte_monobit(void)
560
+{
561
+ /* Enable, collect one byte, disable. Repeat until we have 100 bits. */
562
+ uint8_t buf[TEST_INPUT_BITS / BITS_PER_BYTE];
563
+ unsigned int i;
564
+
565
+ rng_reset();
566
+ for (i = 0; i < sizeof(buf); i++) {
567
+ rng_writeb(RNGCS, RNGE);
568
+ g_assert_true(rng_wait_ready());
569
+ buf[i] = rng_readb(RNGD);
570
+ rng_writeb(RNGCS, 0);
571
+ }
572
+
573
+ g_assert_cmpfloat(calc_monobit_p(buf, sizeof(buf)), >, 0.01);
574
+}
575
+
576
+/*
577
+ * Verifies that the first data byte collected after enabling the RNG satisfies
578
+ * a runs test.
579
+ */
580
+static void test_first_byte_runs(void)
581
+{
582
+ /* Enable, collect one byte, disable. Repeat until we have 100 bits. */
583
+ union {
584
+ unsigned long l[TEST_INPUT_BITS / BITS_PER_LONG];
585
+ uint8_t c[TEST_INPUT_BITS / BITS_PER_BYTE];
586
+ } buf;
587
+ unsigned int i;
588
+
589
+ rng_reset();
590
+ for (i = 0; i < sizeof(buf); i++) {
591
+ rng_writeb(RNGCS, RNGE);
592
+ g_assert_true(rng_wait_ready());
593
+ buf.c[i] = rng_readb(RNGD);
594
+ rng_writeb(RNGCS, 0);
595
+ }
596
+
597
+ g_assert_cmpfloat(calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE), >, 0.01);
598
+}
599
+
600
+int main(int argc, char **argv)
601
+{
602
+ int ret;
603
+
604
+ g_test_init(&argc, &argv, NULL);
605
+ g_test_set_nonfatal_assertions();
606
+
607
+ qtest_add_func("npcm7xx_rng/enable_disable", test_enable_disable);
608
+ qtest_add_func("npcm7xx_rng/rosel", test_rosel);
609
+ qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit);
610
+ qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs);
611
+ qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit);
612
+ qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs);
613
+
614
+ qtest_start("-machine npcm750-evb");
615
+ ret = g_test_run();
616
+ qtest_end();
617
+
618
+ return ret;
619
+}
620
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
621
index XXXXXXX..XXXXXXX 100644
622
--- a/hw/misc/meson.build
623
+++ b/hw/misc/meson.build
624
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
625
softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
626
'npcm7xx_clk.c',
627
'npcm7xx_gcr.c',
628
+ 'npcm7xx_rng.c',
629
))
630
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
631
'omap_clk.c',
632
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
633
index XXXXXXX..XXXXXXX 100644
634
--- a/hw/misc/trace-events
635
+++ b/hw/misc/trace-events
636
@@ -XXX,XX +XXX,XX @@ npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu
637
npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
638
npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
639
640
+# npcm7xx_rng.c
641
+npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
642
+npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
643
+
644
# stm32f4xx_syscfg.c
645
stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
646
stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
647
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
648
index XXXXXXX..XXXXXXX 100644
649
--- a/tests/qtest/meson.build
650
+++ b/tests/qtest/meson.build
651
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
652
(config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] : []) + \
653
['prom-env-test', 'boot-serial-test']
654
655
-qtests_npcm7xx = ['npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test']
656
+qtests_npcm7xx = \
657
+ ['npcm7xx_rng-test',
658
+ 'npcm7xx_timer-test',
659
+ 'npcm7xx_watchdog_timer-test']
660
qtests_arm = \
661
(config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
662
(config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
102
--
663
--
103
2.20.1
664
2.20.1
104
665
105
666
diff view generated by jsdifflib
1
Convert the VCVT instructions in the 2-reg-misc grouping to
1
From: Havard Skinnemoen <hskinnemoen@google.com>
2
decodetree.
3
2
3
The NPCM730 and NPCM750 chips have a single USB host port shared between
4
a USB 2.0 EHCI host controller and a USB 1.1 OHCI host controller. This
5
adds support for both of them.
6
7
Testing notes:
8
* With -device usb-kbd, qemu will automatically insert a full-speed
9
hub, and the keyboard becomes controlled by the OHCI controller.
10
* With -device usb-kbd,bus=usb-bus.0,port=1, the keyboard is directly
11
attached to the port without any hubs, and the device becomes
12
controlled by the EHCI controller since it's high speed capable.
13
* With -device usb-kbd,bus=usb-bus.0,port=1,usb_version=1, the
14
keyboard is directly attached to the port, but it only advertises
15
itself as full-speed capable, so it becomes controlled by the OHCI
16
controller.
17
18
In all cases, the keyboard device enumerates correctly.
19
20
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
21
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
22
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200616170844.13318-19-peter.maydell@linaro.org
7
---
24
---
8
target/arm/neon-dp.decode | 9 +++++
25
docs/system/arm/nuvoton.rst | 2 +-
9
target/arm/translate-neon.inc.c | 70 +++++++++++++++++++++++++++++++++
26
hw/usb/hcd-ehci.h | 1 +
10
target/arm/translate.c | 70 ++++-----------------------------
27
include/hw/arm/npcm7xx.h | 4 ++++
11
3 files changed, 87 insertions(+), 62 deletions(-)
28
hw/arm/npcm7xx.c | 27 +++++++++++++++++++++++++--
29
hw/usb/hcd-ehci-sysbus.c | 19 +++++++++++++++++++
30
5 files changed, 50 insertions(+), 3 deletions(-)
12
31
13
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
32
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
14
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/neon-dp.decode
34
--- a/docs/system/arm/nuvoton.rst
16
+++ b/target/arm/neon-dp.decode
35
+++ b/docs/system/arm/nuvoton.rst
17
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
36
@@ -XXX,XX +XXX,XX @@ Supported devices
18
37
* OTP controllers (no protection features)
19
VRINTP 1111 001 11 . 11 .. 10 .... 0 1111 . . 0 .... @2misc
38
* Flash Interface Unit (FIU; no protection features)
20
39
* Random Number Generator (RNG)
21
+ VCVTAS 1111 001 11 . 11 .. 11 .... 0 0000 . . 0 .... @2misc
40
+ * USB host (USBH)
22
+ VCVTAU 1111 001 11 . 11 .. 11 .... 0 0001 . . 0 .... @2misc
41
23
+ VCVTNS 1111 001 11 . 11 .. 11 .... 0 0010 . . 0 .... @2misc
42
Missing devices
24
+ VCVTNU 1111 001 11 . 11 .. 11 .... 0 0011 . . 0 .... @2misc
43
---------------
25
+ VCVTPS 1111 001 11 . 11 .. 11 .... 0 0100 . . 0 .... @2misc
44
@@ -XXX,XX +XXX,XX @@ Missing devices
26
+ VCVTPU 1111 001 11 . 11 .. 11 .... 0 0101 . . 0 .... @2misc
45
* eSPI slave interface
27
+ VCVTMS 1111 001 11 . 11 .. 11 .... 0 0110 . . 0 .... @2misc
46
28
+ VCVTMU 1111 001 11 . 11 .. 11 .... 0 0111 . . 0 .... @2misc
47
* Ethernet controllers (GMAC and EMC)
48
- * USB host (USBH)
49
* USB device (USBD)
50
* SMBus controller (SMBF)
51
* Peripheral SPI controller (PSPI)
52
diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/usb/hcd-ehci.h
55
+++ b/hw/usb/hcd-ehci.h
56
@@ -XXX,XX +XXX,XX @@ struct EHCIPCIState {
57
#define TYPE_PLATFORM_EHCI "platform-ehci-usb"
58
#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
59
#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb"
60
+#define TYPE_NPCM7XX_EHCI "npcm7xx-ehci-usb"
61
#define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"
62
#define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"
63
#define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"
64
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
65
index XXXXXXX..XXXXXXX 100644
66
--- a/include/hw/arm/npcm7xx.h
67
+++ b/include/hw/arm/npcm7xx.h
68
@@ -XXX,XX +XXX,XX @@
69
#include "hw/nvram/npcm7xx_otp.h"
70
#include "hw/timer/npcm7xx_timer.h"
71
#include "hw/ssi/npcm7xx_fiu.h"
72
+#include "hw/usb/hcd-ehci.h"
73
+#include "hw/usb/hcd-ohci.h"
74
#include "target/arm/cpu.h"
75
76
#define NPCM7XX_MAX_NUM_CPUS (2)
77
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
78
NPCM7xxOTPState fuse_array;
79
NPCM7xxMCState mc;
80
NPCM7xxRNGState rng;
81
+ EHCISysBusState ehci;
82
+ OHCISysBusState ohci;
83
NPCM7xxFIUState fiu[2];
84
} NPCM7xxState;
85
86
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/hw/arm/npcm7xx.c
89
+++ b/hw/arm/npcm7xx.c
90
@@ -XXX,XX +XXX,XX @@
91
#define NPCM7XX_MC_BA (0xf0824000)
92
#define NPCM7XX_RNG_BA (0xf000b000)
93
94
+/* USB Host modules */
95
+#define NPCM7XX_EHCI_BA (0xf0806000)
96
+#define NPCM7XX_OHCI_BA (0xf0807000)
29
+
97
+
30
VRECPE 1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc
98
/* Internal AHB SRAM */
31
VRSQRTE 1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc
99
#define NPCM7XX_RAM3_BA (0xc0008000)
32
VRECPE_F 1111 001 11 . 11 .. 11 .... 0 1010 . . 0 .... @2misc
100
#define NPCM7XX_RAM3_SZ (4 * KiB)
33
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
101
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
102
NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */
103
NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */
104
NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
105
+ NPCM7XX_EHCI_IRQ = 61,
106
+ NPCM7XX_OHCI_IRQ = 62,
107
};
108
109
/* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
110
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
111
object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
112
}
113
114
+ object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI);
115
+ object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI);
116
+
117
QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
118
for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
119
object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
120
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
121
sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort);
122
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA);
123
124
+ /* USB Host */
125
+ object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true,
126
+ &error_abort);
127
+ sysbus_realize(SYS_BUS_DEVICE(&s->ehci), &error_abort);
128
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci), 0, NPCM7XX_EHCI_BA);
129
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci), 0,
130
+ npcm7xx_irq(s, NPCM7XX_EHCI_IRQ));
131
+
132
+ object_property_set_str(OBJECT(&s->ohci), "masterbus", "usb-bus.0",
133
+ &error_abort);
134
+ object_property_set_uint(OBJECT(&s->ohci), "num-ports", 1, &error_abort);
135
+ sysbus_realize(SYS_BUS_DEVICE(&s->ohci), &error_abort);
136
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci), 0, NPCM7XX_OHCI_BA);
137
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
138
+ npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
139
+
140
/*
141
* Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
142
* specified, but this is a programming error.
143
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
144
create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB);
145
create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB);
146
create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB);
147
- create_unimplemented_device("npcm7xx.ehci", 0xf0806000, 4 * KiB);
148
- create_unimplemented_device("npcm7xx.ohci", 0xf0807000, 4 * KiB);
149
create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB);
150
create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB);
151
create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB);
152
diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
34
index XXXXXXX..XXXXXXX 100644
153
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/translate-neon.inc.c
154
--- a/hw/usb/hcd-ehci-sysbus.c
36
+++ b/target/arm/translate-neon.inc.c
155
+++ b/hw/usb/hcd-ehci-sysbus.c
37
@@ -XXX,XX +XXX,XX @@ DO_VRINT(VRINTA, FPROUNDING_TIEAWAY)
156
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ehci_aw_h3_type_info = {
38
DO_VRINT(VRINTZ, FPROUNDING_ZERO)
157
.class_init = ehci_aw_h3_class_init,
39
DO_VRINT(VRINTM, FPROUNDING_NEGINF)
158
};
40
DO_VRINT(VRINTP, FPROUNDING_POSINF)
159
160
+static void ehci_npcm7xx_class_init(ObjectClass *oc, void *data)
161
+{
162
+ SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
163
+ DeviceClass *dc = DEVICE_CLASS(oc);
41
+
164
+
42
+static bool do_vcvt(DisasContext *s, arg_2misc *a, int rmode, bool is_signed)
165
+ sec->capsbase = 0x0;
43
+{
166
+ sec->opregbase = 0x10;
44
+ /*
167
+ sec->portscbase = 0x44;
45
+ * Handle a VCVT* operation by iterating 32 bits at a time,
168
+ sec->portnr = 1;
46
+ * with a specified rounding mode in operation.
169
+ set_bit(DEVICE_CATEGORY_USB, dc->categories);
47
+ */
48
+ int pass;
49
+ TCGv_ptr fpst;
50
+ TCGv_i32 tcg_rmode, tcg_shift;
51
+
52
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
53
+ !arm_dc_feature(s, ARM_FEATURE_V8)) {
54
+ return false;
55
+ }
56
+
57
+ /* UNDEF accesses to D16-D31 if they don't exist. */
58
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
59
+ ((a->vd | a->vm) & 0x10)) {
60
+ return false;
61
+ }
62
+
63
+ if (a->size != 2) {
64
+ /* TODO: FP16 will be the size == 1 case */
65
+ return false;
66
+ }
67
+
68
+ if ((a->vd | a->vm) & a->q) {
69
+ return false;
70
+ }
71
+
72
+ if (!vfp_access_check(s)) {
73
+ return true;
74
+ }
75
+
76
+ fpst = get_fpstatus_ptr(1);
77
+ tcg_shift = tcg_const_i32(0);
78
+ tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
79
+ gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env);
80
+ for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
81
+ TCGv_i32 tmp = neon_load_reg(a->vm, pass);
82
+ if (is_signed) {
83
+ gen_helper_vfp_tosls(tmp, tmp, tcg_shift, fpst);
84
+ } else {
85
+ gen_helper_vfp_touls(tmp, tmp, tcg_shift, fpst);
86
+ }
87
+ neon_store_reg(a->vd, pass, tmp);
88
+ }
89
+ gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env);
90
+ tcg_temp_free_i32(tcg_rmode);
91
+ tcg_temp_free_i32(tcg_shift);
92
+ tcg_temp_free_ptr(fpst);
93
+
94
+ return true;
95
+}
170
+}
96
+
171
+
97
+#define DO_VCVT(INSN, RMODE, SIGNED) \
172
+static const TypeInfo ehci_npcm7xx_type_info = {
98
+ static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
173
+ .name = TYPE_NPCM7XX_EHCI,
99
+ { \
174
+ .parent = TYPE_SYS_BUS_EHCI,
100
+ return do_vcvt(s, a, RMODE, SIGNED); \
175
+ .class_init = ehci_npcm7xx_class_init,
101
+ }
176
+};
102
+
177
+
103
+DO_VCVT(VCVTAU, FPROUNDING_TIEAWAY, false)
178
static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
104
+DO_VCVT(VCVTAS, FPROUNDING_TIEAWAY, true)
179
{
105
+DO_VCVT(VCVTNU, FPROUNDING_TIEEVEN, false)
180
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
106
+DO_VCVT(VCVTNS, FPROUNDING_TIEEVEN, true)
181
@@ -XXX,XX +XXX,XX @@ static void ehci_sysbus_register_types(void)
107
+DO_VCVT(VCVTPU, FPROUNDING_POSINF, false)
182
type_register_static(&ehci_platform_type_info);
108
+DO_VCVT(VCVTPS, FPROUNDING_POSINF, true)
183
type_register_static(&ehci_exynos4210_type_info);
109
+DO_VCVT(VCVTMU, FPROUNDING_NEGINF, false)
184
type_register_static(&ehci_aw_h3_type_info);
110
+DO_VCVT(VCVTMS, FPROUNDING_NEGINF, true)
185
+ type_register_static(&ehci_npcm7xx_type_info);
111
diff --git a/target/arm/translate.c b/target/arm/translate.c
186
type_register_static(&ehci_tegra2_type_info);
112
index XXXXXXX..XXXXXXX 100644
187
type_register_static(&ehci_ppc4xx_type_info);
113
--- a/target/arm/translate.c
188
type_register_static(&ehci_fusbh200_type_info);
114
+++ b/target/arm/translate.c
115
@@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
116
#define NEON_2RM_VCVT_SF 62
117
#define NEON_2RM_VCVT_UF 63
118
119
-static bool neon_2rm_is_v8_op(int op)
120
-{
121
- /* Return true if this neon 2reg-misc op is ARMv8 and up */
122
- switch (op) {
123
- case NEON_2RM_VRINTN:
124
- case NEON_2RM_VRINTA:
125
- case NEON_2RM_VRINTM:
126
- case NEON_2RM_VRINTP:
127
- case NEON_2RM_VRINTZ:
128
- case NEON_2RM_VRINTX:
129
- case NEON_2RM_VCVTAU:
130
- case NEON_2RM_VCVTAS:
131
- case NEON_2RM_VCVTNU:
132
- case NEON_2RM_VCVTNS:
133
- case NEON_2RM_VCVTPU:
134
- case NEON_2RM_VCVTPS:
135
- case NEON_2RM_VCVTMU:
136
- case NEON_2RM_VCVTMS:
137
- return true;
138
- default:
139
- return false;
140
- }
141
-}
142
-
143
/* Each entry in this array has bit n set if the insn allows
144
* size value n (otherwise it will UNDEF). Since unallocated
145
* op values will have no bits set they always UNDEF.
146
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
147
if ((neon_2rm_sizes[op] & (1 << size)) == 0) {
148
return 1;
149
}
150
- if (neon_2rm_is_v8_op(op) &&
151
- !arm_dc_feature(s, ARM_FEATURE_V8)) {
152
- return 1;
153
- }
154
if (q && ((rm | rd) & 1)) {
155
return 1;
156
}
157
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
158
case NEON_2RM_VRINTM:
159
case NEON_2RM_VRINTP:
160
case NEON_2RM_VRINTZ:
161
+ case NEON_2RM_VCVTAU:
162
+ case NEON_2RM_VCVTAS:
163
+ case NEON_2RM_VCVTNU:
164
+ case NEON_2RM_VCVTNS:
165
+ case NEON_2RM_VCVTPU:
166
+ case NEON_2RM_VCVTPS:
167
+ case NEON_2RM_VCVTMU:
168
+ case NEON_2RM_VCVTMS:
169
/* handled by decodetree */
170
return 1;
171
case NEON_2RM_VTRN:
172
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
173
}
174
neon_store_reg(rm, pass, tmp2);
175
break;
176
- case NEON_2RM_VCVTAU:
177
- case NEON_2RM_VCVTAS:
178
- case NEON_2RM_VCVTNU:
179
- case NEON_2RM_VCVTNS:
180
- case NEON_2RM_VCVTPU:
181
- case NEON_2RM_VCVTPS:
182
- case NEON_2RM_VCVTMU:
183
- case NEON_2RM_VCVTMS:
184
- {
185
- bool is_signed = !extract32(insn, 7, 1);
186
- TCGv_ptr fpst = get_fpstatus_ptr(1);
187
- TCGv_i32 tcg_rmode, tcg_shift;
188
- int rmode = fp_decode_rm[extract32(insn, 8, 2)];
189
-
190
- tcg_shift = tcg_const_i32(0);
191
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
192
- gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
193
- cpu_env);
194
-
195
- if (is_signed) {
196
- gen_helper_vfp_tosls(tmp, tmp,
197
- tcg_shift, fpst);
198
- } else {
199
- gen_helper_vfp_touls(tmp, tmp,
200
- tcg_shift, fpst);
201
- }
202
-
203
- gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
204
- cpu_env);
205
- tcg_temp_free_i32(tcg_rmode);
206
- tcg_temp_free_i32(tcg_shift);
207
- tcg_temp_free_ptr(fpst);
208
- break;
209
- }
210
default:
211
/* Reserved op values were caught by the
212
* neon_2rm_sizes[] check earlier.
213
--
189
--
214
2.20.1
190
2.20.1
215
191
216
192
diff view generated by jsdifflib
1
Convert the VREV32 and VREV16 insns in the Neon 2-reg-misc group
1
From: Havard Skinnemoen <hskinnemoen@google.com>
2
to decodetree.
3
2
3
The NPCM7xx chips have multiple GPIO controllers that are mostly
4
identical except for some minor differences like the reset values of
5
some registers. Each controller controls up to 32 pins.
6
7
Each individual pin is modeled as a pair of unnamed GPIOs -- one for
8
emitting the actual pin state, and one for driving the pin externally.
9
Like the nRF51 GPIO controller, a gpio level may be negative, which
10
means the pin is not driven, or floating.
11
12
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
13
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200616170844.13318-13-peter.maydell@linaro.org
7
---
16
---
8
target/arm/translate.h | 1 +
17
docs/system/arm/nuvoton.rst | 2 +-
9
target/arm/neon-dp.decode | 2 ++
18
include/hw/arm/npcm7xx.h | 2 +
10
target/arm/translate-neon.inc.c | 55 +++++++++++++++++++++++++++++++++
19
include/hw/gpio/npcm7xx_gpio.h | 55 +++++
11
target/arm/translate.c | 12 ++-----
20
hw/arm/npcm7xx.c | 80 ++++++
12
4 files changed, 60 insertions(+), 10 deletions(-)
21
hw/gpio/npcm7xx_gpio.c | 424 ++++++++++++++++++++++++++++++++
22
tests/qtest/npcm7xx_gpio-test.c | 385 +++++++++++++++++++++++++++++
23
hw/gpio/meson.build | 1 +
24
hw/gpio/trace-events | 7 +
25
tests/qtest/meson.build | 3 +-
26
9 files changed, 957 insertions(+), 2 deletions(-)
27
create mode 100644 include/hw/gpio/npcm7xx_gpio.h
28
create mode 100644 hw/gpio/npcm7xx_gpio.c
29
create mode 100644 tests/qtest/npcm7xx_gpio-test.c
13
30
14
diff --git a/target/arm/translate.h b/target/arm/translate.h
31
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
15
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.h
33
--- a/docs/system/arm/nuvoton.rst
17
+++ b/target/arm/translate.h
34
+++ b/docs/system/arm/nuvoton.rst
18
@@ -XXX,XX +XXX,XX @@ typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
35
@@ -XXX,XX +XXX,XX @@ Supported devices
19
uint32_t, uint32_t, uint32_t);
36
* Flash Interface Unit (FIU; no protection features)
20
37
* Random Number Generator (RNG)
21
/* Function prototype for gen_ functions for calling Neon helpers */
38
* USB host (USBH)
22
+typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32);
39
+ * GPIO controller
23
typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
40
24
typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
41
Missing devices
25
typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
42
---------------
26
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
43
44
- * GPIO controller
45
* LPC/eSPI host-to-BMC interface, including
46
47
* Keyboard and mouse controller interface (KBCI)
48
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
27
index XXXXXXX..XXXXXXX 100644
49
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/neon-dp.decode
50
--- a/include/hw/arm/npcm7xx.h
29
+++ b/target/arm/neon-dp.decode
51
+++ b/include/hw/arm/npcm7xx.h
30
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
52
@@ -XXX,XX +XXX,XX @@
31
&2misc vm=%vm_dp vd=%vd_dp q=1
53
32
54
#include "hw/boards.h"
33
VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc
55
#include "hw/cpu/a9mpcore.h"
34
+ VREV32 1111 001 11 . 11 .. 00 .... 0 0001 . . 0 .... @2misc
56
+#include "hw/gpio/npcm7xx_gpio.h"
35
+ VREV16 1111 001 11 . 11 .. 00 .... 0 0010 . . 0 .... @2misc
57
#include "hw/mem/npcm7xx_mc.h"
36
58
#include "hw/misc/npcm7xx_clk.h"
37
VPADDL_S 1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc
59
#include "hw/misc/npcm7xx_gcr.h"
38
VPADDL_U 1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc
60
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
39
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
61
NPCM7xxOTPState fuse_array;
62
NPCM7xxMCState mc;
63
NPCM7xxRNGState rng;
64
+ NPCM7xxGPIOState gpio[8];
65
EHCISysBusState ehci;
66
OHCISysBusState ohci;
67
NPCM7xxFIUState fiu[2];
68
diff --git a/include/hw/gpio/npcm7xx_gpio.h b/include/hw/gpio/npcm7xx_gpio.h
69
new file mode 100644
70
index XXXXXXX..XXXXXXX
71
--- /dev/null
72
+++ b/include/hw/gpio/npcm7xx_gpio.h
73
@@ -XXX,XX +XXX,XX @@
74
+/*
75
+ * Nuvoton NPCM7xx General Purpose Input / Output (GPIO)
76
+ *
77
+ * Copyright 2020 Google LLC
78
+ *
79
+ * This program is free software; you can redistribute it and/or
80
+ * modify it under the terms of the GNU General Public License
81
+ * version 2 as published by the Free Software Foundation.
82
+ *
83
+ * This program is distributed in the hope that it will be useful,
84
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
85
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
86
+ * GNU General Public License for more details.
87
+ */
88
+#ifndef NPCM7XX_GPIO_H
89
+#define NPCM7XX_GPIO_H
90
+
91
+#include "exec/memory.h"
92
+#include "hw/sysbus.h"
93
+
94
+/* Number of pins managed by each controller. */
95
+#define NPCM7XX_GPIO_NR_PINS (32)
96
+
97
+/*
98
+ * Number of registers in our device state structure. Don't change this without
99
+ * incrementing the version_id in the vmstate.
100
+ */
101
+#define NPCM7XX_GPIO_NR_REGS (0x80 / sizeof(uint32_t))
102
+
103
+typedef struct NPCM7xxGPIOState {
104
+ SysBusDevice parent;
105
+
106
+ /* Properties to be defined by the SoC */
107
+ uint32_t reset_pu;
108
+ uint32_t reset_pd;
109
+ uint32_t reset_osrc;
110
+ uint32_t reset_odsc;
111
+
112
+ MemoryRegion mmio;
113
+
114
+ qemu_irq irq;
115
+ qemu_irq output[NPCM7XX_GPIO_NR_PINS];
116
+
117
+ uint32_t pin_level;
118
+ uint32_t ext_level;
119
+ uint32_t ext_driven;
120
+
121
+ uint32_t regs[NPCM7XX_GPIO_NR_REGS];
122
+} NPCM7xxGPIOState;
123
+
124
+#define TYPE_NPCM7XX_GPIO "npcm7xx-gpio"
125
+#define NPCM7XX_GPIO(obj) \
126
+ OBJECT_CHECK(NPCM7xxGPIOState, (obj), TYPE_NPCM7XX_GPIO)
127
+
128
+#endif /* NPCM7XX_GPIO_H */
129
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
40
index XXXXXXX..XXXXXXX 100644
130
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/translate-neon.inc.c
131
--- a/hw/arm/npcm7xx.c
42
+++ b/target/arm/translate-neon.inc.c
132
+++ b/hw/arm/npcm7xx.c
43
@@ -XXX,XX +XXX,XX @@ DO_2M_CRYPTO(AESIMC, aa32_aes, 0)
133
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
44
DO_2M_CRYPTO(SHA1H, aa32_sha1, 2)
134
NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
45
DO_2M_CRYPTO(SHA1SU1, aa32_sha1, 2)
135
NPCM7XX_EHCI_IRQ = 61,
46
DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2)
136
NPCM7XX_OHCI_IRQ = 62,
47
+
137
+ NPCM7XX_GPIO0_IRQ = 116,
48
+static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn)
138
+ NPCM7XX_GPIO1_IRQ,
49
+{
139
+ NPCM7XX_GPIO2_IRQ,
50
+ int pass;
140
+ NPCM7XX_GPIO3_IRQ,
51
+
141
+ NPCM7XX_GPIO4_IRQ,
52
+ /* Handle a 2-reg-misc operation by iterating 32 bits at a time */
142
+ NPCM7XX_GPIO5_IRQ,
53
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
143
+ NPCM7XX_GPIO6_IRQ,
54
+ return false;
144
+ NPCM7XX_GPIO7_IRQ,
145
};
146
147
/* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
148
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {
149
0xb8000000, /* CS3 */
150
};
151
152
+static const struct {
153
+ hwaddr regs_addr;
154
+ uint32_t unconnected_pins;
155
+ uint32_t reset_pu;
156
+ uint32_t reset_pd;
157
+ uint32_t reset_osrc;
158
+ uint32_t reset_odsc;
159
+} npcm7xx_gpio[] = {
160
+ {
161
+ .regs_addr = 0xf0010000,
162
+ .reset_pu = 0xff03ffff,
163
+ .reset_pd = 0x00fc0000,
164
+ }, {
165
+ .regs_addr = 0xf0011000,
166
+ .unconnected_pins = 0x0000001e,
167
+ .reset_pu = 0xfefffe07,
168
+ .reset_pd = 0x010001e0,
169
+ }, {
170
+ .regs_addr = 0xf0012000,
171
+ .reset_pu = 0x780fffff,
172
+ .reset_pd = 0x07f00000,
173
+ .reset_odsc = 0x00700000,
174
+ }, {
175
+ .regs_addr = 0xf0013000,
176
+ .reset_pu = 0x00fc0000,
177
+ .reset_pd = 0xff000000,
178
+ }, {
179
+ .regs_addr = 0xf0014000,
180
+ .reset_pu = 0xffffffff,
181
+ }, {
182
+ .regs_addr = 0xf0015000,
183
+ .reset_pu = 0xbf83f801,
184
+ .reset_pd = 0x007c0000,
185
+ .reset_osrc = 0x000000f1,
186
+ .reset_odsc = 0x3f9f80f1,
187
+ }, {
188
+ .regs_addr = 0xf0016000,
189
+ .reset_pu = 0xfc00f801,
190
+ .reset_pd = 0x000007fe,
191
+ .reset_odsc = 0x00000800,
192
+ }, {
193
+ .regs_addr = 0xf0017000,
194
+ .unconnected_pins = 0xffffff00,
195
+ .reset_pu = 0x0000007f,
196
+ .reset_osrc = 0x0000007f,
197
+ .reset_odsc = 0x0000007f,
198
+ },
199
+};
200
+
201
static const struct {
202
const char *name;
203
hwaddr regs_addr;
204
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
205
object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
206
}
207
208
+ for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
209
+ object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO);
55
+ }
210
+ }
56
+
211
+
57
+ /* UNDEF accesses to D16-D31 if they don't exist. */
212
object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI);
58
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
213
object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI);
59
+ ((a->vd | a->vm) & 0x10)) {
214
60
+ return false;
215
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
216
sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort);
217
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA);
218
219
+ /* GPIO modules. Cannot fail. */
220
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gpio) != ARRAY_SIZE(s->gpio));
221
+ for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
222
+ Object *obj = OBJECT(&s->gpio[i]);
223
+
224
+ object_property_set_uint(obj, "reset-pullup",
225
+ npcm7xx_gpio[i].reset_pu, &error_abort);
226
+ object_property_set_uint(obj, "reset-pulldown",
227
+ npcm7xx_gpio[i].reset_pd, &error_abort);
228
+ object_property_set_uint(obj, "reset-osrc",
229
+ npcm7xx_gpio[i].reset_osrc, &error_abort);
230
+ object_property_set_uint(obj, "reset-odsc",
231
+ npcm7xx_gpio[i].reset_odsc, &error_abort);
232
+ sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort);
233
+ sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_gpio[i].regs_addr);
234
+ sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0,
235
+ npcm7xx_irq(s, NPCM7XX_GPIO0_IRQ + i));
61
+ }
236
+ }
62
+
237
+
63
+ if (!fn) {
238
/* USB Host */
64
+ return false;
239
object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true,
240
&error_abort);
241
diff --git a/hw/gpio/npcm7xx_gpio.c b/hw/gpio/npcm7xx_gpio.c
242
new file mode 100644
243
index XXXXXXX..XXXXXXX
244
--- /dev/null
245
+++ b/hw/gpio/npcm7xx_gpio.c
246
@@ -XXX,XX +XXX,XX @@
247
+/*
248
+ * Nuvoton NPCM7xx General Purpose Input / Output (GPIO)
249
+ *
250
+ * Copyright 2020 Google LLC
251
+ *
252
+ * This program is free software; you can redistribute it and/or
253
+ * modify it under the terms of the GNU General Public License
254
+ * version 2 as published by the Free Software Foundation.
255
+ *
256
+ * This program is distributed in the hope that it will be useful,
257
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
258
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
259
+ * GNU General Public License for more details.
260
+ */
261
+
262
+#include "qemu/osdep.h"
263
+
264
+#include "hw/gpio/npcm7xx_gpio.h"
265
+#include "hw/irq.h"
266
+#include "hw/qdev-properties.h"
267
+#include "migration/vmstate.h"
268
+#include "qapi/error.h"
269
+#include "qemu/log.h"
270
+#include "qemu/module.h"
271
+#include "qemu/units.h"
272
+#include "trace.h"
273
+
274
+/* 32-bit register indices. */
275
+enum NPCM7xxGPIORegister {
276
+ NPCM7XX_GPIO_TLOCK1,
277
+ NPCM7XX_GPIO_DIN,
278
+ NPCM7XX_GPIO_POL,
279
+ NPCM7XX_GPIO_DOUT,
280
+ NPCM7XX_GPIO_OE,
281
+ NPCM7XX_GPIO_OTYP,
282
+ NPCM7XX_GPIO_MP,
283
+ NPCM7XX_GPIO_PU,
284
+ NPCM7XX_GPIO_PD,
285
+ NPCM7XX_GPIO_DBNC,
286
+ NPCM7XX_GPIO_EVTYP,
287
+ NPCM7XX_GPIO_EVBE,
288
+ NPCM7XX_GPIO_OBL0,
289
+ NPCM7XX_GPIO_OBL1,
290
+ NPCM7XX_GPIO_OBL2,
291
+ NPCM7XX_GPIO_OBL3,
292
+ NPCM7XX_GPIO_EVEN,
293
+ NPCM7XX_GPIO_EVENS,
294
+ NPCM7XX_GPIO_EVENC,
295
+ NPCM7XX_GPIO_EVST,
296
+ NPCM7XX_GPIO_SPLCK,
297
+ NPCM7XX_GPIO_MPLCK,
298
+ NPCM7XX_GPIO_IEM,
299
+ NPCM7XX_GPIO_OSRC,
300
+ NPCM7XX_GPIO_ODSC,
301
+ NPCM7XX_GPIO_DOS = 0x68 / sizeof(uint32_t),
302
+ NPCM7XX_GPIO_DOC,
303
+ NPCM7XX_GPIO_OES,
304
+ NPCM7XX_GPIO_OEC,
305
+ NPCM7XX_GPIO_TLOCK2 = 0x7c / sizeof(uint32_t),
306
+ NPCM7XX_GPIO_REGS_END,
307
+};
308
+
309
+#define NPCM7XX_GPIO_REGS_SIZE (4 * KiB)
310
+
311
+#define NPCM7XX_GPIO_LOCK_MAGIC1 (0xc0defa73)
312
+#define NPCM7XX_GPIO_LOCK_MAGIC2 (0xc0de1248)
313
+
314
+static void npcm7xx_gpio_update_events(NPCM7xxGPIOState *s, uint32_t din_diff)
315
+{
316
+ uint32_t din_new = s->regs[NPCM7XX_GPIO_DIN];
317
+
318
+ /* Trigger on high level */
319
+ s->regs[NPCM7XX_GPIO_EVST] |= din_new & ~s->regs[NPCM7XX_GPIO_EVTYP];
320
+ /* Trigger on both edges */
321
+ s->regs[NPCM7XX_GPIO_EVST] |= (din_diff & s->regs[NPCM7XX_GPIO_EVTYP]
322
+ & s->regs[NPCM7XX_GPIO_EVBE]);
323
+ /* Trigger on rising edge */
324
+ s->regs[NPCM7XX_GPIO_EVST] |= (din_diff & din_new
325
+ & s->regs[NPCM7XX_GPIO_EVTYP]);
326
+
327
+ trace_npcm7xx_gpio_update_events(DEVICE(s)->canonical_path,
328
+ s->regs[NPCM7XX_GPIO_EVST],
329
+ s->regs[NPCM7XX_GPIO_EVEN]);
330
+ qemu_set_irq(s->irq, !!(s->regs[NPCM7XX_GPIO_EVST]
331
+ & s->regs[NPCM7XX_GPIO_EVEN]));
332
+}
333
+
334
+static void npcm7xx_gpio_update_pins(NPCM7xxGPIOState *s, uint32_t diff)
335
+{
336
+ uint32_t drive_en;
337
+ uint32_t drive_lvl;
338
+ uint32_t not_driven;
339
+ uint32_t undefined;
340
+ uint32_t pin_diff;
341
+ uint32_t din_old;
342
+
343
+ /* Calculate level of each pin driven by GPIO controller. */
344
+ drive_lvl = s->regs[NPCM7XX_GPIO_DOUT] ^ s->regs[NPCM7XX_GPIO_POL];
345
+ /* If OTYP=1, only drive low (open drain) */
346
+ drive_en = s->regs[NPCM7XX_GPIO_OE] & ~(s->regs[NPCM7XX_GPIO_OTYP]
347
+ & drive_lvl);
348
+ /*
349
+ * If a pin is driven to opposite levels by the GPIO controller and the
350
+ * external driver, the result is undefined.
351
+ */
352
+ undefined = drive_en & s->ext_driven & (drive_lvl ^ s->ext_level);
353
+ if (undefined) {
354
+ qemu_log_mask(LOG_GUEST_ERROR,
355
+ "%s: pins have multiple drivers: 0x%" PRIx32 "\n",
356
+ DEVICE(s)->canonical_path, undefined);
65
+ }
357
+ }
66
+
358
+
67
+ if ((a->vd | a->vm) & a->q) {
359
+ not_driven = ~(drive_en | s->ext_driven);
68
+ return false;
360
+ pin_diff = s->pin_level;
361
+
362
+ /* Set pins to externally driven level. */
363
+ s->pin_level = s->ext_level & s->ext_driven;
364
+ /* Set internally driven pins, ignoring any conflicts. */
365
+ s->pin_level |= drive_lvl & drive_en;
366
+ /* Pull up undriven pins with internal pull-up enabled. */
367
+ s->pin_level |= not_driven & s->regs[NPCM7XX_GPIO_PU];
368
+ /* Pins not driven, pulled up or pulled down are undefined */
369
+ undefined |= not_driven & ~(s->regs[NPCM7XX_GPIO_PU]
370
+ | s->regs[NPCM7XX_GPIO_PD]);
371
+
372
+ /* If any pins changed state, update the outgoing GPIOs. */
373
+ pin_diff ^= s->pin_level;
374
+ pin_diff |= undefined & diff;
375
+ if (pin_diff) {
376
+ int i;
377
+
378
+ for (i = 0; i < NPCM7XX_GPIO_NR_PINS; i++) {
379
+ uint32_t mask = BIT(i);
380
+ if (pin_diff & mask) {
381
+ int level = (undefined & mask) ? -1 : !!(s->pin_level & mask);
382
+ trace_npcm7xx_gpio_set_output(DEVICE(s)->canonical_path,
383
+ i, level);
384
+ qemu_set_irq(s->output[i], level);
385
+ }
386
+ }
69
+ }
387
+ }
70
+
388
+
71
+ if (!vfp_access_check(s)) {
389
+ /* Calculate new value of DIN after masking and polarity setting. */
72
+ return true;
390
+ din_old = s->regs[NPCM7XX_GPIO_DIN];
391
+ s->regs[NPCM7XX_GPIO_DIN] = ((s->pin_level & s->regs[NPCM7XX_GPIO_IEM])
392
+ ^ s->regs[NPCM7XX_GPIO_POL]);
393
+
394
+ /* See if any new events triggered because of all this. */
395
+ npcm7xx_gpio_update_events(s, din_old ^ s->regs[NPCM7XX_GPIO_DIN]);
396
+}
397
+
398
+static bool npcm7xx_gpio_is_locked(NPCM7xxGPIOState *s)
399
+{
400
+ return s->regs[NPCM7XX_GPIO_TLOCK1] == 1;
401
+}
402
+
403
+static uint64_t npcm7xx_gpio_regs_read(void *opaque, hwaddr addr,
404
+ unsigned int size)
405
+{
406
+ hwaddr reg = addr / sizeof(uint32_t);
407
+ NPCM7xxGPIOState *s = opaque;
408
+ uint64_t value = 0;
409
+
410
+ switch (reg) {
411
+ case NPCM7XX_GPIO_TLOCK1 ... NPCM7XX_GPIO_EVEN:
412
+ case NPCM7XX_GPIO_EVST ... NPCM7XX_GPIO_ODSC:
413
+ value = s->regs[reg];
414
+ break;
415
+
416
+ case NPCM7XX_GPIO_EVENS ... NPCM7XX_GPIO_EVENC:
417
+ case NPCM7XX_GPIO_DOS ... NPCM7XX_GPIO_TLOCK2:
418
+ qemu_log_mask(LOG_GUEST_ERROR,
419
+ "%s: read from write-only register 0x%" HWADDR_PRIx "\n",
420
+ DEVICE(s)->canonical_path, addr);
421
+ break;
422
+
423
+ default:
424
+ qemu_log_mask(LOG_GUEST_ERROR,
425
+ "%s: read from invalid offset 0x%" HWADDR_PRIx "\n",
426
+ DEVICE(s)->canonical_path, addr);
427
+ break;
73
+ }
428
+ }
74
+
429
+
75
+ for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
430
+ trace_npcm7xx_gpio_read(DEVICE(s)->canonical_path, addr, value);
76
+ TCGv_i32 tmp = neon_load_reg(a->vm, pass);
431
+
77
+ fn(tmp, tmp);
432
+ return value;
78
+ neon_store_reg(a->vd, pass, tmp);
433
+}
434
+
435
+static void npcm7xx_gpio_regs_write(void *opaque, hwaddr addr, uint64_t v,
436
+ unsigned int size)
437
+{
438
+ hwaddr reg = addr / sizeof(uint32_t);
439
+ NPCM7xxGPIOState *s = opaque;
440
+ uint32_t value = v;
441
+ uint32_t diff;
442
+
443
+ trace_npcm7xx_gpio_write(DEVICE(s)->canonical_path, addr, v);
444
+
445
+ if (npcm7xx_gpio_is_locked(s)) {
446
+ switch (reg) {
447
+ case NPCM7XX_GPIO_TLOCK1:
448
+ if (s->regs[NPCM7XX_GPIO_TLOCK2] == NPCM7XX_GPIO_LOCK_MAGIC2 &&
449
+ value == NPCM7XX_GPIO_LOCK_MAGIC1) {
450
+ s->regs[NPCM7XX_GPIO_TLOCK1] = 0;
451
+ s->regs[NPCM7XX_GPIO_TLOCK2] = 0;
452
+ }
453
+ break;
454
+
455
+ case NPCM7XX_GPIO_TLOCK2:
456
+ s->regs[reg] = value;
457
+ break;
458
+
459
+ default:
460
+ qemu_log_mask(LOG_GUEST_ERROR,
461
+ "%s: write to locked register @ 0x%" HWADDR_PRIx "\n",
462
+ DEVICE(s)->canonical_path, addr);
463
+ break;
464
+ }
465
+
466
+ return;
79
+ }
467
+ }
80
+
468
+
81
+ return true;
469
+ diff = s->regs[reg] ^ value;
82
+}
470
+
83
+
471
+ switch (reg) {
84
+static bool trans_VREV32(DisasContext *s, arg_2misc *a)
472
+ case NPCM7XX_GPIO_TLOCK1:
85
+{
473
+ case NPCM7XX_GPIO_TLOCK2:
86
+ static NeonGenOneOpFn * const fn[] = {
474
+ s->regs[NPCM7XX_GPIO_TLOCK1] = 1;
87
+ tcg_gen_bswap32_i32,
475
+ s->regs[NPCM7XX_GPIO_TLOCK2] = 0;
88
+ gen_swap_half,
476
+ break;
89
+ NULL,
477
+
90
+ NULL,
478
+ case NPCM7XX_GPIO_DIN:
91
+ };
479
+ qemu_log_mask(LOG_GUEST_ERROR,
92
+ return do_2misc(s, a, fn[a->size]);
480
+ "%s: write to read-only register @ 0x%" HWADDR_PRIx "\n",
93
+}
481
+ DEVICE(s)->canonical_path, addr);
94
+
482
+ break;
95
+static bool trans_VREV16(DisasContext *s, arg_2misc *a)
483
+
96
+{
484
+ case NPCM7XX_GPIO_POL:
97
+ if (a->size != 0) {
485
+ case NPCM7XX_GPIO_DOUT:
98
+ return false;
486
+ case NPCM7XX_GPIO_OE:
487
+ case NPCM7XX_GPIO_OTYP:
488
+ case NPCM7XX_GPIO_PU:
489
+ case NPCM7XX_GPIO_PD:
490
+ case NPCM7XX_GPIO_IEM:
491
+ s->regs[reg] = value;
492
+ npcm7xx_gpio_update_pins(s, diff);
493
+ break;
494
+
495
+ case NPCM7XX_GPIO_DOS:
496
+ s->regs[NPCM7XX_GPIO_DOUT] |= value;
497
+ npcm7xx_gpio_update_pins(s, value);
498
+ break;
499
+ case NPCM7XX_GPIO_DOC:
500
+ s->regs[NPCM7XX_GPIO_DOUT] &= ~value;
501
+ npcm7xx_gpio_update_pins(s, value);
502
+ break;
503
+ case NPCM7XX_GPIO_OES:
504
+ s->regs[NPCM7XX_GPIO_OE] |= value;
505
+ npcm7xx_gpio_update_pins(s, value);
506
+ break;
507
+ case NPCM7XX_GPIO_OEC:
508
+ s->regs[NPCM7XX_GPIO_OE] &= ~value;
509
+ npcm7xx_gpio_update_pins(s, value);
510
+ break;
511
+
512
+ case NPCM7XX_GPIO_EVTYP:
513
+ case NPCM7XX_GPIO_EVBE:
514
+ case NPCM7XX_GPIO_EVEN:
515
+ s->regs[reg] = value;
516
+ npcm7xx_gpio_update_events(s, 0);
517
+ break;
518
+
519
+ case NPCM7XX_GPIO_EVENS:
520
+ s->regs[NPCM7XX_GPIO_EVEN] |= value;
521
+ npcm7xx_gpio_update_events(s, 0);
522
+ break;
523
+ case NPCM7XX_GPIO_EVENC:
524
+ s->regs[NPCM7XX_GPIO_EVEN] &= ~value;
525
+ npcm7xx_gpio_update_events(s, 0);
526
+ break;
527
+
528
+ case NPCM7XX_GPIO_EVST:
529
+ s->regs[reg] &= ~value;
530
+ npcm7xx_gpio_update_events(s, 0);
531
+ break;
532
+
533
+ case NPCM7XX_GPIO_MP:
534
+ case NPCM7XX_GPIO_DBNC:
535
+ case NPCM7XX_GPIO_OSRC:
536
+ case NPCM7XX_GPIO_ODSC:
537
+ /* Nothing to do; just store the value. */
538
+ s->regs[reg] = value;
539
+ break;
540
+
541
+ case NPCM7XX_GPIO_OBL0:
542
+ case NPCM7XX_GPIO_OBL1:
543
+ case NPCM7XX_GPIO_OBL2:
544
+ case NPCM7XX_GPIO_OBL3:
545
+ s->regs[reg] = value;
546
+ qemu_log_mask(LOG_UNIMP, "%s: Blinking is not implemented\n",
547
+ __func__);
548
+ break;
549
+
550
+ case NPCM7XX_GPIO_SPLCK:
551
+ case NPCM7XX_GPIO_MPLCK:
552
+ qemu_log_mask(LOG_UNIMP, "%s: Per-pin lock is not implemented\n",
553
+ __func__);
554
+ break;
555
+
556
+ default:
557
+ qemu_log_mask(LOG_GUEST_ERROR,
558
+ "%s: write to invalid offset 0x%" HWADDR_PRIx "\n",
559
+ DEVICE(s)->canonical_path, addr);
560
+ break;
99
+ }
561
+ }
100
+ return do_2misc(s, a, gen_rev16);
562
+}
101
+}
563
+
102
diff --git a/target/arm/translate.c b/target/arm/translate.c
564
+static const MemoryRegionOps npcm7xx_gpio_regs_ops = {
565
+ .read = npcm7xx_gpio_regs_read,
566
+ .write = npcm7xx_gpio_regs_write,
567
+ .endianness = DEVICE_NATIVE_ENDIAN,
568
+ .valid = {
569
+ .min_access_size = 4,
570
+ .max_access_size = 4,
571
+ .unaligned = false,
572
+ },
573
+};
574
+
575
+static void npcm7xx_gpio_set_input(void *opaque, int line, int level)
576
+{
577
+ NPCM7xxGPIOState *s = opaque;
578
+
579
+ trace_npcm7xx_gpio_set_input(DEVICE(s)->canonical_path, line, level);
580
+
581
+ g_assert(line >= 0 && line < NPCM7XX_GPIO_NR_PINS);
582
+
583
+ s->ext_driven = deposit32(s->ext_driven, line, 1, level >= 0);
584
+ s->ext_level = deposit32(s->ext_level, line, 1, level > 0);
585
+
586
+ npcm7xx_gpio_update_pins(s, BIT(line));
587
+}
588
+
589
+static void npcm7xx_gpio_enter_reset(Object *obj, ResetType type)
590
+{
591
+ NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
592
+
593
+ memset(s->regs, 0, sizeof(s->regs));
594
+
595
+ s->regs[NPCM7XX_GPIO_PU] = s->reset_pu;
596
+ s->regs[NPCM7XX_GPIO_PD] = s->reset_pd;
597
+ s->regs[NPCM7XX_GPIO_OSRC] = s->reset_osrc;
598
+ s->regs[NPCM7XX_GPIO_ODSC] = s->reset_odsc;
599
+}
600
+
601
+static void npcm7xx_gpio_hold_reset(Object *obj)
602
+{
603
+ NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
604
+
605
+ npcm7xx_gpio_update_pins(s, -1);
606
+}
607
+
608
+static void npcm7xx_gpio_init(Object *obj)
609
+{
610
+ NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
611
+ DeviceState *dev = DEVICE(obj);
612
+
613
+ memory_region_init_io(&s->mmio, obj, &npcm7xx_gpio_regs_ops, s,
614
+ "regs", NPCM7XX_GPIO_REGS_SIZE);
615
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
616
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
617
+
618
+ qdev_init_gpio_in(dev, npcm7xx_gpio_set_input, NPCM7XX_GPIO_NR_PINS);
619
+ qdev_init_gpio_out(dev, s->output, NPCM7XX_GPIO_NR_PINS);
620
+}
621
+
622
+static const VMStateDescription vmstate_npcm7xx_gpio = {
623
+ .name = "npcm7xx-gpio",
624
+ .version_id = 0,
625
+ .minimum_version_id = 0,
626
+ .fields = (VMStateField[]) {
627
+ VMSTATE_UINT32(pin_level, NPCM7xxGPIOState),
628
+ VMSTATE_UINT32(ext_level, NPCM7xxGPIOState),
629
+ VMSTATE_UINT32(ext_driven, NPCM7xxGPIOState),
630
+ VMSTATE_UINT32_ARRAY(regs, NPCM7xxGPIOState, NPCM7XX_GPIO_NR_REGS),
631
+ VMSTATE_END_OF_LIST(),
632
+ },
633
+};
634
+
635
+static Property npcm7xx_gpio_properties[] = {
636
+ /* Bit n set => pin n has pullup enabled by default. */
637
+ DEFINE_PROP_UINT32("reset-pullup", NPCM7xxGPIOState, reset_pu, 0),
638
+ /* Bit n set => pin n has pulldown enabled by default. */
639
+ DEFINE_PROP_UINT32("reset-pulldown", NPCM7xxGPIOState, reset_pd, 0),
640
+ /* Bit n set => pin n has high slew rate by default. */
641
+ DEFINE_PROP_UINT32("reset-osrc", NPCM7xxGPIOState, reset_osrc, 0),
642
+ /* Bit n set => pin n has high drive strength by default. */
643
+ DEFINE_PROP_UINT32("reset-odsc", NPCM7xxGPIOState, reset_odsc, 0),
644
+ DEFINE_PROP_END_OF_LIST(),
645
+};
646
+
647
+static void npcm7xx_gpio_class_init(ObjectClass *klass, void *data)
648
+{
649
+ ResettableClass *reset = RESETTABLE_CLASS(klass);
650
+ DeviceClass *dc = DEVICE_CLASS(klass);
651
+
652
+ QEMU_BUILD_BUG_ON(NPCM7XX_GPIO_REGS_END > NPCM7XX_GPIO_NR_REGS);
653
+
654
+ dc->desc = "NPCM7xx GPIO Controller";
655
+ dc->vmsd = &vmstate_npcm7xx_gpio;
656
+ reset->phases.enter = npcm7xx_gpio_enter_reset;
657
+ reset->phases.hold = npcm7xx_gpio_hold_reset;
658
+ device_class_set_props(dc, npcm7xx_gpio_properties);
659
+}
660
+
661
+static const TypeInfo npcm7xx_gpio_types[] = {
662
+ {
663
+ .name = TYPE_NPCM7XX_GPIO,
664
+ .parent = TYPE_SYS_BUS_DEVICE,
665
+ .instance_size = sizeof(NPCM7xxGPIOState),
666
+ .class_init = npcm7xx_gpio_class_init,
667
+ .instance_init = npcm7xx_gpio_init,
668
+ },
669
+};
670
+DEFINE_TYPES(npcm7xx_gpio_types);
671
diff --git a/tests/qtest/npcm7xx_gpio-test.c b/tests/qtest/npcm7xx_gpio-test.c
672
new file mode 100644
673
index XXXXXXX..XXXXXXX
674
--- /dev/null
675
+++ b/tests/qtest/npcm7xx_gpio-test.c
676
@@ -XXX,XX +XXX,XX @@
677
+/*
678
+ * QTest testcase for the Nuvoton NPCM7xx GPIO modules.
679
+ *
680
+ * Copyright 2020 Google LLC
681
+ *
682
+ * This program is free software; you can redistribute it and/or modify it
683
+ * under the terms of the GNU General Public License as published by the
684
+ * Free Software Foundation; either version 2 of the License, or
685
+ * (at your option) any later version.
686
+ *
687
+ * This program is distributed in the hope that it will be useful, but WITHOUT
688
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
689
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
690
+ * for more details.
691
+ */
692
+
693
+#include "qemu/osdep.h"
694
+#include "libqtest-single.h"
695
+
696
+#define NR_GPIO_DEVICES (8)
697
+#define GPIO(x) (0xf0010000 + (x) * 0x1000)
698
+#define GPIO_IRQ(x) (116 + (x))
699
+
700
+/* GPIO registers */
701
+#define GP_N_TLOCK1 0x00
702
+#define GP_N_DIN 0x04 /* Data IN */
703
+#define GP_N_POL 0x08 /* Polarity */
704
+#define GP_N_DOUT 0x0c /* Data OUT */
705
+#define GP_N_OE 0x10 /* Output Enable */
706
+#define GP_N_OTYP 0x14
707
+#define GP_N_MP 0x18
708
+#define GP_N_PU 0x1c /* Pull-up */
709
+#define GP_N_PD 0x20 /* Pull-down */
710
+#define GP_N_DBNC 0x24 /* Debounce */
711
+#define GP_N_EVTYP 0x28 /* Event Type */
712
+#define GP_N_EVBE 0x2c /* Event Both Edge */
713
+#define GP_N_OBL0 0x30
714
+#define GP_N_OBL1 0x34
715
+#define GP_N_OBL2 0x38
716
+#define GP_N_OBL3 0x3c
717
+#define GP_N_EVEN 0x40 /* Event Enable */
718
+#define GP_N_EVENS 0x44 /* Event Set (enable) */
719
+#define GP_N_EVENC 0x48 /* Event Clear (disable) */
720
+#define GP_N_EVST 0x4c /* Event Status */
721
+#define GP_N_SPLCK 0x50
722
+#define GP_N_MPLCK 0x54
723
+#define GP_N_IEM 0x58 /* Input Enable */
724
+#define GP_N_OSRC 0x5c
725
+#define GP_N_ODSC 0x60
726
+#define GP_N_DOS 0x68 /* Data OUT Set */
727
+#define GP_N_DOC 0x6c /* Data OUT Clear */
728
+#define GP_N_OES 0x70 /* Output Enable Set */
729
+#define GP_N_OEC 0x74 /* Output Enable Clear */
730
+#define GP_N_TLOCK2 0x7c
731
+
732
+static void gpio_unlock(int n)
733
+{
734
+ if (readl(GPIO(n) + GP_N_TLOCK1) != 0) {
735
+ writel(GPIO(n) + GP_N_TLOCK2, 0xc0de1248);
736
+ writel(GPIO(n) + GP_N_TLOCK1, 0xc0defa73);
737
+ }
738
+}
739
+
740
+/* Restore the GPIO controller to a sensible default state. */
741
+static void gpio_reset(int n)
742
+{
743
+ gpio_unlock(0);
744
+
745
+ writel(GPIO(n) + GP_N_EVEN, 0x00000000);
746
+ writel(GPIO(n) + GP_N_EVST, 0xffffffff);
747
+ writel(GPIO(n) + GP_N_POL, 0x00000000);
748
+ writel(GPIO(n) + GP_N_DOUT, 0x00000000);
749
+ writel(GPIO(n) + GP_N_OE, 0x00000000);
750
+ writel(GPIO(n) + GP_N_OTYP, 0x00000000);
751
+ writel(GPIO(n) + GP_N_PU, 0xffffffff);
752
+ writel(GPIO(n) + GP_N_PD, 0x00000000);
753
+ writel(GPIO(n) + GP_N_IEM, 0xffffffff);
754
+}
755
+
756
+static void test_dout_to_din(void)
757
+{
758
+ gpio_reset(0);
759
+
760
+ /* When output is enabled, DOUT should be reflected on DIN. */
761
+ writel(GPIO(0) + GP_N_OE, 0xffffffff);
762
+ /* PU and PD shouldn't have any impact on DIN. */
763
+ writel(GPIO(0) + GP_N_PU, 0xffff0000);
764
+ writel(GPIO(0) + GP_N_PD, 0x0000ffff);
765
+ writel(GPIO(0) + GP_N_DOUT, 0x12345678);
766
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0x12345678);
767
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x12345678);
768
+}
769
+
770
+static void test_pullup_pulldown(void)
771
+{
772
+ gpio_reset(0);
773
+
774
+ /*
775
+ * When output is disabled, and PD is the inverse of PU, PU should be
776
+ * reflected on DIN. If PD is not the inverse of PU, the state of DIN is
777
+ * undefined, so we don't test that.
778
+ */
779
+ writel(GPIO(0) + GP_N_OE, 0x00000000);
780
+ /* DOUT shouldn't have any impact on DIN. */
781
+ writel(GPIO(0) + GP_N_DOUT, 0xffff0000);
782
+ writel(GPIO(0) + GP_N_PU, 0x23456789);
783
+ writel(GPIO(0) + GP_N_PD, ~0x23456789U);
784
+ g_assert_cmphex(readl(GPIO(0) + GP_N_PU), ==, 0x23456789);
785
+ g_assert_cmphex(readl(GPIO(0) + GP_N_PD), ==, ~0x23456789U);
786
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x23456789);
787
+}
788
+
789
+static void test_output_enable(void)
790
+{
791
+ gpio_reset(0);
792
+
793
+ /*
794
+ * With all pins weakly pulled down, and DOUT all-ones, OE should be
795
+ * reflected on DIN.
796
+ */
797
+ writel(GPIO(0) + GP_N_DOUT, 0xffffffff);
798
+ writel(GPIO(0) + GP_N_PU, 0x00000000);
799
+ writel(GPIO(0) + GP_N_PD, 0xffffffff);
800
+ writel(GPIO(0) + GP_N_OE, 0x3456789a);
801
+ g_assert_cmphex(readl(GPIO(0) + GP_N_OE), ==, 0x3456789a);
802
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x3456789a);
803
+
804
+ writel(GPIO(0) + GP_N_OEC, 0x00030002);
805
+ g_assert_cmphex(readl(GPIO(0) + GP_N_OE), ==, 0x34547898);
806
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x34547898);
807
+
808
+ writel(GPIO(0) + GP_N_OES, 0x0000f001);
809
+ g_assert_cmphex(readl(GPIO(0) + GP_N_OE), ==, 0x3454f899);
810
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x3454f899);
811
+}
812
+
813
+static void test_open_drain(void)
814
+{
815
+ gpio_reset(0);
816
+
817
+ /*
818
+ * Upper half of DOUT drives a 1 only if the corresponding bit in OTYP is
819
+ * not set. If OTYP is set, DIN is determined by PU/PD. Lower half of
820
+ * DOUT always drives a 0 regardless of OTYP; PU/PD have no effect. When
821
+ * OE is 0, output is determined by PU/PD; OTYP has no effect.
822
+ */
823
+ writel(GPIO(0) + GP_N_OTYP, 0x456789ab);
824
+ writel(GPIO(0) + GP_N_OE, 0xf0f0f0f0);
825
+ writel(GPIO(0) + GP_N_DOUT, 0xffff0000);
826
+ writel(GPIO(0) + GP_N_PU, 0xff00ff00);
827
+ writel(GPIO(0) + GP_N_PD, 0x00ff00ff);
828
+ g_assert_cmphex(readl(GPIO(0) + GP_N_OTYP), ==, 0x456789ab);
829
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0xff900f00);
830
+}
831
+
832
+static void test_polarity(void)
833
+{
834
+ gpio_reset(0);
835
+
836
+ /*
837
+ * In push-pull mode, DIN should reflect DOUT because the signal is
838
+ * inverted in both directions.
839
+ */
840
+ writel(GPIO(0) + GP_N_OTYP, 0x00000000);
841
+ writel(GPIO(0) + GP_N_OE, 0xffffffff);
842
+ writel(GPIO(0) + GP_N_DOUT, 0x56789abc);
843
+ writel(GPIO(0) + GP_N_POL, 0x6789abcd);
844
+ g_assert_cmphex(readl(GPIO(0) + GP_N_POL), ==, 0x6789abcd);
845
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x56789abc);
846
+
847
+ /*
848
+ * When turning off the drivers, DIN should reflect the inverse of the
849
+ * pulled-up lines.
850
+ */
851
+ writel(GPIO(0) + GP_N_OE, 0x00000000);
852
+ writel(GPIO(0) + GP_N_POL, 0xffffffff);
853
+ writel(GPIO(0) + GP_N_PU, 0x789abcde);
854
+ writel(GPIO(0) + GP_N_PD, ~0x789abcdeU);
855
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, ~0x789abcdeU);
856
+
857
+ /*
858
+ * In open-drain mode, DOUT=1 will appear to drive the pin high (since DIN
859
+ * is inverted), while DOUT=0 will leave the pin floating.
860
+ */
861
+ writel(GPIO(0) + GP_N_OTYP, 0xffffffff);
862
+ writel(GPIO(0) + GP_N_OE, 0xffffffff);
863
+ writel(GPIO(0) + GP_N_PU, 0xffff0000);
864
+ writel(GPIO(0) + GP_N_PD, 0x0000ffff);
865
+ writel(GPIO(0) + GP_N_DOUT, 0xff00ff00);
866
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0xff00ffff);
867
+}
868
+
869
+static void test_input_mask(void)
870
+{
871
+ gpio_reset(0);
872
+
873
+ /* IEM=0 forces the input to zero before polarity inversion. */
874
+ writel(GPIO(0) + GP_N_OE, 0xffffffff);
875
+ writel(GPIO(0) + GP_N_DOUT, 0xff00ff00);
876
+ writel(GPIO(0) + GP_N_POL, 0xffff0000);
877
+ writel(GPIO(0) + GP_N_IEM, 0x87654321);
878
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0xff9a4300);
879
+}
880
+
881
+static void test_temp_lock(void)
882
+{
883
+ gpio_reset(0);
884
+
885
+ writel(GPIO(0) + GP_N_DOUT, 0x98765432);
886
+
887
+ /* Make sure we're unlocked initially. */
888
+ g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 0);
889
+ /* Writing any value to TLOCK1 will lock. */
890
+ writel(GPIO(0) + GP_N_TLOCK1, 0);
891
+ g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 1);
892
+ writel(GPIO(0) + GP_N_DOUT, 0xa9876543);
893
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0x98765432);
894
+ /* Now, try to unlock. */
895
+ gpio_unlock(0);
896
+ g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 0);
897
+ writel(GPIO(0) + GP_N_DOUT, 0xa9876543);
898
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0xa9876543);
899
+
900
+ /* Try it again, but write TLOCK2 to lock. */
901
+ writel(GPIO(0) + GP_N_TLOCK2, 0);
902
+ g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 1);
903
+ writel(GPIO(0) + GP_N_DOUT, 0x98765432);
904
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0xa9876543);
905
+ /* Now, try to unlock. */
906
+ gpio_unlock(0);
907
+ g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 0);
908
+ writel(GPIO(0) + GP_N_DOUT, 0x98765432);
909
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0x98765432);
910
+}
911
+
912
+static void test_events_level(void)
913
+{
914
+ gpio_reset(0);
915
+
916
+ writel(GPIO(0) + GP_N_EVTYP, 0x00000000);
917
+ writel(GPIO(0) + GP_N_DOUT, 0xba987654);
918
+ writel(GPIO(0) + GP_N_OE, 0xffffffff);
919
+ writel(GPIO(0) + GP_N_EVST, 0xffffffff);
920
+
921
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0xba987654);
922
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
923
+ writel(GPIO(0) + GP_N_DOUT, 0x00000000);
924
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0xba987654);
925
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
926
+ writel(GPIO(0) + GP_N_EVST, 0x00007654);
927
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0xba980000);
928
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
929
+ writel(GPIO(0) + GP_N_EVST, 0xba980000);
930
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);
931
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
932
+}
933
+
934
+static void test_events_rising_edge(void)
935
+{
936
+ gpio_reset(0);
937
+
938
+ writel(GPIO(0) + GP_N_EVTYP, 0xffffffff);
939
+ writel(GPIO(0) + GP_N_EVBE, 0x00000000);
940
+ writel(GPIO(0) + GP_N_DOUT, 0xffff0000);
941
+ writel(GPIO(0) + GP_N_OE, 0xffffffff);
942
+ writel(GPIO(0) + GP_N_EVST, 0xffffffff);
943
+
944
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);
945
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
946
+ writel(GPIO(0) + GP_N_DOUT, 0xff00ff00);
947
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x0000ff00);
948
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
949
+ writel(GPIO(0) + GP_N_DOUT, 0x00ff0000);
950
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00ffff00);
951
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
952
+ writel(GPIO(0) + GP_N_EVST, 0x0000f000);
953
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00ff0f00);
954
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
955
+ writel(GPIO(0) + GP_N_EVST, 0x00ff0f00);
956
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);
957
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
958
+}
959
+
960
+static void test_events_both_edges(void)
961
+{
962
+ gpio_reset(0);
963
+
964
+ writel(GPIO(0) + GP_N_EVTYP, 0xffffffff);
965
+ writel(GPIO(0) + GP_N_EVBE, 0xffffffff);
966
+ writel(GPIO(0) + GP_N_DOUT, 0xffff0000);
967
+ writel(GPIO(0) + GP_N_OE, 0xffffffff);
968
+ writel(GPIO(0) + GP_N_EVST, 0xffffffff);
969
+
970
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);
971
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
972
+ writel(GPIO(0) + GP_N_DOUT, 0xff00ff00);
973
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00ffff00);
974
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
975
+ writel(GPIO(0) + GP_N_DOUT, 0xef00ff08);
976
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x10ffff08);
977
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
978
+ writel(GPIO(0) + GP_N_EVST, 0x0000f000);
979
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x10ff0f08);
980
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
981
+ writel(GPIO(0) + GP_N_EVST, 0x10ff0f08);
982
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);
983
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
984
+}
985
+
986
+static void test_gpion_irq(gconstpointer test_data)
987
+{
988
+ intptr_t n = (intptr_t)test_data;
989
+
990
+ gpio_reset(n);
991
+
992
+ writel(GPIO(n) + GP_N_EVTYP, 0x00000000);
993
+ writel(GPIO(n) + GP_N_DOUT, 0x00000000);
994
+ writel(GPIO(n) + GP_N_OE, 0xffffffff);
995
+ writel(GPIO(n) + GP_N_EVST, 0xffffffff);
996
+ writel(GPIO(n) + GP_N_EVEN, 0x00000000);
997
+
998
+ /* Trigger an event; interrupts are masked. */
999
+ g_assert_cmphex(readl(GPIO(n) + GP_N_EVST), ==, 0x00000000);
1000
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
1001
+ writel(GPIO(n) + GP_N_DOS, 0x00008000);
1002
+ g_assert_cmphex(readl(GPIO(n) + GP_N_EVST), ==, 0x00008000);
1003
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
1004
+
1005
+ /* Unmask all event interrupts; verify that the interrupt fired. */
1006
+ writel(GPIO(n) + GP_N_EVEN, 0xffffffff);
1007
+ g_assert_true(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
1008
+
1009
+ /* Clear the current bit, set a new bit, irq stays asserted. */
1010
+ writel(GPIO(n) + GP_N_DOC, 0x00008000);
1011
+ g_assert_true(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
1012
+ writel(GPIO(n) + GP_N_DOS, 0x00000200);
1013
+ g_assert_true(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
1014
+ writel(GPIO(n) + GP_N_EVST, 0x00008000);
1015
+ g_assert_true(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
1016
+
1017
+ /* Mask/unmask the event that's currently active. */
1018
+ writel(GPIO(n) + GP_N_EVENC, 0x00000200);
1019
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
1020
+ writel(GPIO(n) + GP_N_EVENS, 0x00000200);
1021
+ g_assert_true(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
1022
+
1023
+ /* Clear the input and the status bit, irq is deasserted. */
1024
+ writel(GPIO(n) + GP_N_DOC, 0x00000200);
1025
+ g_assert_true(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
1026
+ writel(GPIO(n) + GP_N_EVST, 0x00000200);
1027
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
1028
+}
1029
+
1030
+int main(int argc, char **argv)
1031
+{
1032
+ int ret;
1033
+ int i;
1034
+
1035
+ g_test_init(&argc, &argv, NULL);
1036
+ g_test_set_nonfatal_assertions();
1037
+
1038
+ qtest_add_func("/npcm7xx_gpio/dout_to_din", test_dout_to_din);
1039
+ qtest_add_func("/npcm7xx_gpio/pullup_pulldown", test_pullup_pulldown);
1040
+ qtest_add_func("/npcm7xx_gpio/output_enable", test_output_enable);
1041
+ qtest_add_func("/npcm7xx_gpio/open_drain", test_open_drain);
1042
+ qtest_add_func("/npcm7xx_gpio/polarity", test_polarity);
1043
+ qtest_add_func("/npcm7xx_gpio/input_mask", test_input_mask);
1044
+ qtest_add_func("/npcm7xx_gpio/temp_lock", test_temp_lock);
1045
+ qtest_add_func("/npcm7xx_gpio/events/level", test_events_level);
1046
+ qtest_add_func("/npcm7xx_gpio/events/rising_edge", test_events_rising_edge);
1047
+ qtest_add_func("/npcm7xx_gpio/events/both_edges", test_events_both_edges);
1048
+
1049
+ for (i = 0; i < NR_GPIO_DEVICES; i++) {
1050
+ g_autofree char *test_name =
1051
+ g_strdup_printf("/npcm7xx_gpio/gpio[%d]/irq", i);
1052
+ qtest_add_data_func(test_name, (void *)(intptr_t)i, test_gpion_irq);
1053
+ }
1054
+
1055
+ qtest_start("-machine npcm750-evb");
1056
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/a9mpcore/gic");
1057
+ ret = g_test_run();
1058
+ qtest_end();
1059
+
1060
+ return ret;
1061
+}
1062
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
103
index XXXXXXX..XXXXXXX 100644
1063
index XXXXXXX..XXXXXXX 100644
104
--- a/target/arm/translate.c
1064
--- a/hw/gpio/meson.build
105
+++ b/target/arm/translate.c
1065
+++ b/hw/gpio/meson.build
106
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
1066
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_gpio.c'))
107
case NEON_2RM_AESE: case NEON_2RM_AESMC:
1067
softmmu_ss.add(when: 'CONFIG_ZAURUS', if_true: files('zaurus.c'))
108
case NEON_2RM_SHA1H:
1068
109
case NEON_2RM_SHA1SU1:
1069
softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_gpio.c'))
110
+ case NEON_2RM_VREV32:
1070
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_gpio.c'))
111
+ case NEON_2RM_VREV16:
1071
softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c'))
112
/* handled by decodetree */
1072
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
113
return 1;
1073
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
114
case NEON_2RM_VTRN:
1074
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
115
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
1075
index XXXXXXX..XXXXXXX 100644
116
for (pass = 0; pass < (q ? 4 : 2); pass++) {
1076
--- a/hw/gpio/trace-events
117
tmp = neon_load_reg(rm, pass);
1077
+++ b/hw/gpio/trace-events
118
switch (op) {
1078
@@ -XXX,XX +XXX,XX @@
119
- case NEON_2RM_VREV32:
1079
# See docs/devel/tracing.txt for syntax documentation.
120
- switch (size) {
1080
121
- case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
1081
+# npcm7xx_gpio.c
122
- case 1: gen_swap_half(tmp, tmp); break;
1082
+npcm7xx_gpio_read(const char *id, uint64_t offset, uint64_t value) " %s offset: 0x%04" PRIx64 " value 0x%08" PRIx64
123
- default: abort();
1083
+npcm7xx_gpio_write(const char *id, uint64_t offset, uint64_t value) "%s offset: 0x%04" PRIx64 " value 0x%08" PRIx64
124
- }
1084
+npcm7xx_gpio_set_input(const char *id, int32_t line, int32_t level) "%s line: %" PRIi32 " level: %" PRIi32
125
- break;
1085
+npcm7xx_gpio_set_output(const char *id, int32_t line, int32_t level) "%s line: %" PRIi32 " level: %" PRIi32
126
- case NEON_2RM_VREV16:
1086
+npcm7xx_gpio_update_events(const char *id, uint32_t evst, uint32_t even) "%s evst: 0x%08" PRIx32 " even: 0x%08" PRIx32
127
- gen_rev16(tmp, tmp);
1087
+
128
- break;
1088
# nrf51_gpio.c
129
case NEON_2RM_VCLS:
1089
nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
130
switch (size) {
1090
nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
131
case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
1091
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
1092
index XXXXXXX..XXXXXXX 100644
1093
--- a/tests/qtest/meson.build
1094
+++ b/tests/qtest/meson.build
1095
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
1096
['prom-env-test', 'boot-serial-test']
1097
1098
qtests_npcm7xx = \
1099
- ['npcm7xx_rng-test',
1100
+ ['npcm7xx_gpio-test',
1101
+ 'npcm7xx_rng-test',
1102
'npcm7xx_timer-test',
1103
'npcm7xx_watchdog_timer-test']
1104
qtests_arm = \
132
--
1105
--
133
2.20.1
1106
2.20.1
134
1107
135
1108
diff view generated by jsdifflib
1
From: Andrew Jones <drjones@redhat.com>
1
From: Zenghui Yu <yuzenghui@huawei.com>
2
2
3
Cc: Cornelia Huck <cohuck@redhat.com>
3
Ensure the vSMMUv3 will be restored before all PCIe devices so that DMA
4
Signed-off-by: Andrew Jones <drjones@redhat.com>
4
translation can work properly during migration.
5
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
5
6
Message-id: 20200616140803.25515-1-drjones@redhat.com
6
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
7
Message-id: 20201019091508.197-1-yuzenghui@huawei.com
8
Acked-by: Eric Auger <eric.auger@redhat.com>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
10
---
9
hw/arm/virt.c | 1 +
11
hw/arm/smmuv3.c | 1 +
10
1 file changed, 1 insertion(+)
12
1 file changed, 1 insertion(+)
11
13
12
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
14
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
13
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/arm/virt.c
16
--- a/hw/arm/smmuv3.c
15
+++ b/hw/arm/virt.c
17
+++ b/hw/arm/smmuv3.c
16
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 1)
18
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = {
17
static void virt_machine_5_0_options(MachineClass *mc)
19
.name = "smmuv3",
18
{
20
.version_id = 1,
19
virt_machine_5_1_options(mc);
21
.minimum_version_id = 1,
20
+ compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
22
+ .priority = MIG_PRI_IOMMU,
21
}
23
.fields = (VMStateField[]) {
22
DEFINE_VIRT_MACHINE(5, 0)
24
VMSTATE_UINT32(features, SMMUv3State),
23
25
VMSTATE_UINT8(sid_size, SMMUv3State),
24
--
26
--
25
2.20.1
27
2.20.1
26
28
27
29
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
No code out of bcm2836.c uses (or requires) the BCM283XInfo
4
declarations. Move it locally to the C source file.
5
6
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Message-id: 20200617072539.32686-11-f4bug@amsat.org
8
Message-id: 20201024170127.3592182-2-f4bug@amsat.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
hw/arm/mps2.c | 9 +++++++++
11
include/hw/arm/bcm2836.h | 8 --------
9
1 file changed, 9 insertions(+)
12
hw/arm/bcm2836.c | 14 ++++++++++++++
13
2 files changed, 14 insertions(+), 8 deletions(-)
10
14
11
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
15
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/mps2.c
17
--- a/include/hw/arm/bcm2836.h
14
+++ b/hw/arm/mps2.c
18
+++ b/include/hw/arm/bcm2836.h
19
@@ -XXX,XX +XXX,XX @@ struct BCM283XState {
20
BCM2835PeripheralState peripherals;
21
};
22
23
-typedef struct BCM283XInfo BCM283XInfo;
24
-
25
-struct BCM283XClass {
26
- DeviceClass parent_class;
27
- const BCM283XInfo *info;
28
-};
29
-
30
-
31
#endif /* BCM2836_H */
32
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/bcm2836.c
35
+++ b/hw/arm/bcm2836.c
15
@@ -XXX,XX +XXX,XX @@
36
@@ -XXX,XX +XXX,XX @@
16
#include "hw/timer/cmsdk-apb-timer.h"
37
#include "hw/arm/raspi_platform.h"
17
#include "hw/timer/cmsdk-apb-dualtimer.h"
38
#include "hw/sysbus.h"
18
#include "hw/misc/mps2-scc.h"
39
19
+#include "hw/misc/mps2-fpgaio.h"
40
+typedef struct BCM283XInfo BCM283XInfo;
20
#include "hw/net/lan9118.h"
41
+
21
#include "net/net.h"
42
+typedef struct BCM283XClass {
22
+#include "hw/watchdog/cmsdk-apb-watchdog.h"
43
+ /*< private >*/
23
44
+ DeviceClass parent_class;
24
typedef enum MPS2FPGAType {
45
+ /*< public >*/
25
FPGA_AN385,
46
+ const BCM283XInfo *info;
26
@@ -XXX,XX +XXX,XX @@ typedef struct {
47
+} BCM283XClass;
27
MemoryRegion sram;
48
+
28
/* FPGA APB subsystem */
49
struct BCM283XInfo {
29
MPS2SCC scc;
50
const char *name;
30
+ MPS2FPGAIO fpgaio;
51
const char *cpu_type;
31
/* CMSDK APB subsystem */
52
@@ -XXX,XX +XXX,XX @@ struct BCM283XInfo {
32
CMSDKAPBDualTimer dualtimer;
53
int clusterid;
33
+ CMSDKAPBWatchdog watchdog;
54
};
34
} MPS2MachineState;
55
35
56
+#define BCM283X_CLASS(klass) \
36
#define TYPE_MPS2_MACHINE "mps2"
57
+ OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
37
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
58
+#define BCM283X_GET_CLASS(obj) \
38
qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
59
+ OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
39
sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
60
+
40
sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000);
61
static const BCM283XInfo bcm283x_socs[] = {
41
+ object_initialize_child(OBJECT(mms), "fpgaio",
62
{
42
+ &mms->fpgaio, TYPE_MPS2_FPGAIO);
63
.name = TYPE_BCM2836,
43
+ qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", 25000000);
44
+ sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
45
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0x40028000);
46
47
/* In hardware this is a LAN9220; the LAN9118 is software compatible
48
* except that it doesn't support the checksum-offload feature.
49
--
64
--
50
2.20.1
65
2.20.1
51
66
52
67
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Register the GPIO peripherals as unimplemented to better
3
Remove usage of TypeInfo::class_data. Instead fill the fields in
4
follow their accesses, for example booting Zephyr:
4
the corresponding class_init().
5
5
6
----------------
6
So far all children use the same values for almost all fields,
7
IN: arm_mps2_pinmux_init
7
but we are going to add the BCM2711/BCM2838 SoC for the raspi4
8
0x00001160: f64f 0231 movw r2, #0xf831
8
machine which use different fields.
9
0x00001164: 4b06 ldr r3, [pc, #0x18]
9
10
0x00001166: 2000 movs r0, #0
10
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
11
0x00001168: 619a str r2, [r3, #0x18]
12
0x0000116a: f24c 426f movw r2, #0xc46f
13
0x0000116e: f503 5380 add.w r3, r3, #0x1000
14
0x00001172: 619a str r2, [r3, #0x18]
15
0x00001174: f44f 529e mov.w r2, #0x13c0
16
0x00001178: f503 5380 add.w r3, r3, #0x1000
17
0x0000117c: 619a str r2, [r3, #0x18]
18
0x0000117e: 4770 bx lr
19
cmsdk-ahb-gpio: unimplemented device write (size 4, value 0xf831, offset 0x18)
20
cmsdk-ahb-gpio: unimplemented device write (size 4, value 0xc46f, offset 0x18)
21
cmsdk-ahb-gpio: unimplemented device write (size 4, value 0x13c0, offset 0x18)
22
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
25
Message-id: 20200617072539.32686-10-f4bug@amsat.org
12
Message-id: 20201024170127.3592182-3-f4bug@amsat.org
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
---
14
---
28
hw/arm/mps2.c | 8 ++++++--
15
hw/arm/bcm2836.c | 108 ++++++++++++++++++++++-------------------------
29
1 file changed, 6 insertions(+), 2 deletions(-)
16
1 file changed, 51 insertions(+), 57 deletions(-)
30
17
31
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
18
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
32
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/mps2.c
20
--- a/hw/arm/bcm2836.c
34
+++ b/hw/arm/mps2.c
21
+++ b/hw/arm/bcm2836.c
35
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
22
@@ -XXX,XX +XXX,XX @@
36
MemoryRegion *system_memory = get_system_memory();
23
#include "hw/arm/raspi_platform.h"
37
MachineClass *mc = MACHINE_GET_CLASS(machine);
24
#include "hw/sysbus.h"
38
DeviceState *armv7m, *sccdev;
25
39
+ int i;
26
-typedef struct BCM283XInfo BCM283XInfo;
40
27
-
41
if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
28
typedef struct BCM283XClass {
42
error_report("This board can only be used with CPU %s",
29
/*< private >*/
43
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
30
DeviceClass parent_class;
44
*/
31
/*< public >*/
45
Object *orgate;
32
- const BCM283XInfo *info;
46
DeviceState *orgate_dev;
33
-} BCM283XClass;
47
- int i;
34
-
48
35
-struct BCM283XInfo {
49
orgate = object_new(TYPE_OR_IRQ);
36
const char *name;
50
object_property_set_int(orgate, 6, "num-lines", &error_fatal);
37
const char *cpu_type;
51
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
38
hwaddr peri_base; /* Peripheral base address seen by the CPU */
52
*/
39
hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
53
Object *orgate;
40
int clusterid;
54
DeviceState *orgate_dev;
41
-};
55
- int i;
42
+} BCM283XClass;
56
43
57
orgate = object_new(TYPE_OR_IRQ);
44
#define BCM283X_CLASS(klass) \
58
object_property_set_int(orgate, 10, "num-lines", &error_fatal);
45
OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
59
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
46
#define BCM283X_GET_CLASS(obj) \
60
default:
47
OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
61
g_assert_not_reached();
48
49
-static const BCM283XInfo bcm283x_socs[] = {
50
- {
51
- .name = TYPE_BCM2836,
52
- .cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"),
53
- .peri_base = 0x3f000000,
54
- .ctrl_base = 0x40000000,
55
- .clusterid = 0xf,
56
- },
57
-#ifdef TARGET_AARCH64
58
- {
59
- .name = TYPE_BCM2837,
60
- .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
61
- .peri_base = 0x3f000000,
62
- .ctrl_base = 0x40000000,
63
- .clusterid = 0x0,
64
- },
65
-#endif
66
-};
67
-
68
static void bcm2836_init(Object *obj)
69
{
70
BCM283XState *s = BCM283X(obj);
71
BCM283XClass *bc = BCM283X_GET_CLASS(obj);
72
- const BCM283XInfo *info = bc->info;
73
int n;
74
75
for (n = 0; n < BCM283X_NCPUS; n++) {
76
object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
77
- info->cpu_type);
78
+ bc->cpu_type);
62
}
79
}
63
+ for (i = 0; i < 4; i++) {
80
64
+ static const hwaddr gpiobase[] = {0x40010000, 0x40011000,
81
object_initialize_child(obj, "control", &s->control, TYPE_BCM2836_CONTROL);
65
+ 0x40012000, 0x40013000};
82
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
66
+ create_unimplemented_device("cmsdk-ahb-gpio", gpiobase[i], 0x1000);
83
{
67
+ }
84
BCM283XState *s = BCM283X(dev);
68
85
BCM283XClass *bc = BCM283X_GET_CLASS(dev);
69
/* CMSDK APB subsystem */
86
- const BCM283XInfo *info = bc->info;
70
cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
87
Object *obj;
88
int n;
89
90
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
91
"sd-bus");
92
93
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0,
94
- info->peri_base, 1);
95
+ bc->peri_base, 1);
96
97
/* bcm2836 interrupt controller (and mailboxes, etc.) */
98
if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) {
99
return;
100
}
101
102
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, info->ctrl_base);
103
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base);
104
105
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
106
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0));
107
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
108
109
for (n = 0; n < BCM283X_NCPUS; n++) {
110
/* TODO: this should be converted to a property of ARM_CPU */
111
- s->cpu[n].core.mp_affinity = (info->clusterid << 8) | n;
112
+ s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n;
113
114
/* set periphbase/CBAR value for CPU-local registers */
115
if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar",
116
- info->peri_base, errp)) {
117
+ bc->peri_base, errp)) {
118
return;
119
}
120
121
@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
122
static void bcm283x_class_init(ObjectClass *oc, void *data)
123
{
124
DeviceClass *dc = DEVICE_CLASS(oc);
125
- BCM283XClass *bc = BCM283X_CLASS(oc);
126
127
- bc->info = data;
128
- dc->realize = bcm2836_realize;
129
- device_class_set_props(dc, bcm2836_props);
130
/* Reason: Must be wired up in code (see raspi_init() function) */
131
dc->user_creatable = false;
132
}
133
134
-static const TypeInfo bcm283x_type_info = {
135
- .name = TYPE_BCM283X,
136
- .parent = TYPE_DEVICE,
137
- .instance_size = sizeof(BCM283XState),
138
- .instance_init = bcm2836_init,
139
- .class_size = sizeof(BCM283XClass),
140
- .abstract = true,
141
+static void bcm2836_class_init(ObjectClass *oc, void *data)
142
+{
143
+ DeviceClass *dc = DEVICE_CLASS(oc);
144
+ BCM283XClass *bc = BCM283X_CLASS(oc);
145
+
146
+ bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
147
+ bc->peri_base = 0x3f000000;
148
+ bc->ctrl_base = 0x40000000;
149
+ bc->clusterid = 0xf;
150
+ dc->realize = bcm2836_realize;
151
+ device_class_set_props(dc, bcm2836_props);
152
};
153
154
-static void bcm2836_register_types(void)
155
+#ifdef TARGET_AARCH64
156
+static void bcm2837_class_init(ObjectClass *oc, void *data)
157
{
158
- int i;
159
+ DeviceClass *dc = DEVICE_CLASS(oc);
160
+ BCM283XClass *bc = BCM283X_CLASS(oc);
161
162
- type_register_static(&bcm283x_type_info);
163
- for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
164
- TypeInfo ti = {
165
- .name = bcm283x_socs[i].name,
166
- .parent = TYPE_BCM283X,
167
- .class_init = bcm283x_class_init,
168
- .class_data = (void *) &bcm283x_socs[i],
169
- };
170
- type_register(&ti);
171
+ bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
172
+ bc->peri_base = 0x3f000000;
173
+ bc->ctrl_base = 0x40000000;
174
+ bc->clusterid = 0x0;
175
+ dc->realize = bcm2836_realize;
176
+ device_class_set_props(dc, bcm2836_props);
177
+};
178
+#endif
179
+
180
+static const TypeInfo bcm283x_types[] = {
181
+ {
182
+ .name = TYPE_BCM2836,
183
+ .parent = TYPE_BCM283X,
184
+ .class_init = bcm2836_class_init,
185
+#ifdef TARGET_AARCH64
186
+ }, {
187
+ .name = TYPE_BCM2837,
188
+ .parent = TYPE_BCM283X,
189
+ .class_init = bcm2837_class_init,
190
+#endif
191
+ }, {
192
+ .name = TYPE_BCM283X,
193
+ .parent = TYPE_DEVICE,
194
+ .instance_size = sizeof(BCM283XState),
195
+ .instance_init = bcm2836_init,
196
+ .class_size = sizeof(BCM283XClass),
197
+ .class_init = bcm283x_class_init,
198
+ .abstract = true,
199
}
200
-}
201
+};
202
203
-type_init(bcm2836_register_types)
204
+DEFINE_TYPES(bcm283x_types)
71
--
205
--
72
2.20.1
206
2.20.1
73
207
74
208
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
The BCM2835 has only one core. Introduce the core_count field to
4
be able to use values different than BCM283X_NCPUS (4).
5
6
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Message-id: 20200617072539.32686-7-f4bug@amsat.org
8
Message-id: 20201024170127.3592182-4-f4bug@amsat.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
hw/arm/mps2.c | 5 ++++-
11
hw/arm/bcm2836.c | 5 ++++-
9
1 file changed, 4 insertions(+), 1 deletion(-)
12
1 file changed, 4 insertions(+), 1 deletion(-)
10
13
11
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
14
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/mps2.c
16
--- a/hw/arm/bcm2836.c
14
+++ b/hw/arm/mps2.c
17
+++ b/hw/arm/bcm2836.c
15
@@ -XXX,XX +XXX,XX @@ typedef struct {
18
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XClass {
16
MemoryRegion blockram_m2;
19
/*< public >*/
17
MemoryRegion blockram_m3;
20
const char *name;
18
MemoryRegion sram;
21
const char *cpu_type;
19
+ /* FPGA APB subsystem */
22
+ unsigned core_count;
20
MPS2SCC scc;
23
hwaddr peri_base; /* Peripheral base address seen by the CPU */
21
+ /* CMSDK APB subsystem */
24
hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
22
CMSDKAPBDualTimer dualtimer;
25
int clusterid;
23
} MPS2MachineState;
26
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
24
27
BCM283XClass *bc = BCM283X_GET_CLASS(obj);
25
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
28
int n;
26
g_assert_not_reached();
29
30
- for (n = 0; n < BCM283X_NCPUS; n++) {
31
+ for (n = 0; n < bc->core_count; n++) {
32
object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
33
bc->cpu_type);
27
}
34
}
28
35
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
29
+ /* CMSDK APB subsystem */
36
BCM283XClass *bc = BCM283X_CLASS(oc);
30
cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
37
31
cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ);
38
bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
32
-
39
+ bc->core_count = BCM283X_NCPUS;
33
object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
40
bc->peri_base = 0x3f000000;
34
TYPE_CMSDK_APB_DUALTIMER);
41
bc->ctrl_base = 0x40000000;
35
qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
42
bc->clusterid = 0xf;
36
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
43
@@ -XXX,XX +XXX,XX @@ static void bcm2837_class_init(ObjectClass *oc, void *data)
37
qdev_get_gpio_in(armv7m, 10));
44
BCM283XClass *bc = BCM283X_CLASS(oc);
38
sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
45
39
46
bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
40
+ /* FPGA APB subsystem */
47
+ bc->core_count = BCM283X_NCPUS;
41
object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
48
bc->peri_base = 0x3f000000;
42
sccdev = DEVICE(&mms->scc);
49
bc->ctrl_base = 0x40000000;
43
qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
50
bc->clusterid = 0x0;
44
--
51
--
45
2.20.1
52
2.20.1
46
53
47
54
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
To differenciate with the CMSDK APB peripheral region,
3
It makes no sense to set enabled-cpus=0 on single core SoCs.
4
rename this region 'CMSDK AHB peripheral region'.
5
4
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20200617072539.32686-8-f4bug@amsat.org
7
Message-id: 20201024170127.3592182-5-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
9
---
11
hw/arm/mps2.c | 3 ++-
10
hw/arm/bcm2836.c | 15 +++++++--------
12
1 file changed, 2 insertions(+), 1 deletion(-)
11
1 file changed, 7 insertions(+), 8 deletions(-)
13
12
14
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
13
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/mps2.c
15
--- a/hw/arm/bcm2836.c
17
+++ b/hw/arm/mps2.c
16
+++ b/hw/arm/bcm2836.c
18
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
17
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XClass {
19
*/
18
#define BCM283X_GET_CLASS(obj) \
20
create_unimplemented_device("CMSDK APB peripheral region @0x40000000",
19
OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
21
0x40000000, 0x00010000);
20
22
- create_unimplemented_device("CMSDK peripheral region @0x40010000",
21
+static Property bcm2836_enabled_cores_property =
23
+ create_unimplemented_device("CMSDK AHB peripheral region @0x40010000",
22
+ DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0);
24
0x40010000, 0x00010000);
25
create_unimplemented_device("Extra peripheral region @0x40020000",
26
0x40020000, 0x00010000);
27
+
23
+
28
create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000);
24
static void bcm2836_init(Object *obj)
29
create_unimplemented_device("VGA", 0x41000000, 0x0200000);
25
{
26
BCM283XState *s = BCM283X(obj);
27
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
28
object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
29
bc->cpu_type);
30
}
31
+ if (bc->core_count > 1) {
32
+ qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property);
33
+ qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count);
34
+ }
35
36
object_initialize_child(obj, "control", &s->control, TYPE_BCM2836_CONTROL);
37
38
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
39
}
40
}
41
42
-static Property bcm2836_props[] = {
43
- DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
44
- BCM283X_NCPUS),
45
- DEFINE_PROP_END_OF_LIST()
46
-};
47
-
48
static void bcm283x_class_init(ObjectClass *oc, void *data)
49
{
50
DeviceClass *dc = DEVICE_CLASS(oc);
51
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
52
bc->ctrl_base = 0x40000000;
53
bc->clusterid = 0xf;
54
dc->realize = bcm2836_realize;
55
- device_class_set_props(dc, bcm2836_props);
56
};
57
58
#ifdef TARGET_AARCH64
59
@@ -XXX,XX +XXX,XX @@ static void bcm2837_class_init(ObjectClass *oc, void *data)
60
bc->ctrl_base = 0x40000000;
61
bc->clusterid = 0x0;
62
dc->realize = bcm2836_realize;
63
- device_class_set_props(dc, bcm2836_props);
64
};
65
#endif
30
66
31
--
67
--
32
2.20.1
68
2.20.1
33
69
34
70
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
From 'Application Note AN521', chapter 4.7:
3
The realize() function is clearly composed of two parts,
4
each described by a comment:
4
5
5
The SMM implements four SBCon serial modules:
6
void realize()
7
{
8
/* common peripherals from bcm2835 */
9
...
10
/* bcm2836 interrupt controller (and mailboxes, etc.) */
11
...
12
}
6
13
7
One SBCon module for use by the Color LCD touch interface.
14
Split the two part, so we can reuse the common part with other
8
One SBCon module to configure the audio controller.
15
SoCs from this family.
9
Two general purpose SBCon modules, that connect to the
10
Expansion headers J7 and J8, are intended for use with the
11
V2C-Shield1 which provide an I2C interface on the headers.
12
16
17
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20200617072539.32686-15-f4bug@amsat.org
19
Message-id: 20201024170127.3592182-6-f4bug@amsat.org
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
21
---
18
hw/arm/mps2-tz.c | 23 ++++++++++++++++++-----
22
hw/arm/bcm2836.c | 22 ++++++++++++++++++----
19
1 file changed, 18 insertions(+), 5 deletions(-)
23
1 file changed, 18 insertions(+), 4 deletions(-)
20
24
21
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
25
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
22
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/mps2-tz.c
27
--- a/hw/arm/bcm2836.c
24
+++ b/hw/arm/mps2-tz.c
28
+++ b/hw/arm/bcm2836.c
25
@@ -XXX,XX +XXX,XX @@
29
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
26
#include "hw/arm/armsse.h"
30
qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count);
27
#include "hw/dma/pl080.h"
31
}
28
#include "hw/ssi/pl022.h"
32
29
+#include "hw/i2c/arm_sbcon_i2c.h"
33
- object_initialize_child(obj, "control", &s->control, TYPE_BCM2836_CONTROL);
30
#include "hw/net/lan9118.h"
34
+ if (bc->ctrl_base) {
31
#include "net/net.h"
35
+ object_initialize_child(obj, "control", &s->control,
32
#include "hw/core/split-irq.h"
36
+ TYPE_BCM2836_CONTROL);
33
@@ -XXX,XX +XXX,XX @@ typedef struct {
37
+ }
34
TZPPC ppc[5];
38
35
TZMPC ssram_mpc[3];
39
object_initialize_child(obj, "peripherals", &s->peripherals,
36
PL022State spi[5];
40
TYPE_BCM2835_PERIPHERALS);
37
- UnimplementedDeviceState i2c[4];
41
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
38
+ ArmSbconI2CState i2c[4];
42
"vcram-size");
39
UnimplementedDeviceState i2s_audio;
40
UnimplementedDeviceState gpio[4];
41
UnimplementedDeviceState gfx;
42
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque,
43
return sysbus_mmio_get_region(s, 0);
44
}
43
}
45
44
46
+static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque,
45
-static void bcm2836_realize(DeviceState *dev, Error **errp)
47
+ const char *name, hwaddr size)
46
+static bool bcm283x_common_realize(DeviceState *dev, Error **errp)
48
+{
47
{
49
+ ArmSbconI2CState *i2c = opaque;
48
BCM283XState *s = BCM283X(dev);
50
+ SysBusDevice *s;
49
BCM283XClass *bc = BCM283X_GET_CLASS(dev);
51
+
50
Object *obj;
52
+ object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C);
51
- int n;
53
+ s = SYS_BUS_DEVICE(i2c);
52
54
+ sysbus_realize(s, &error_fatal);
53
/* common peripherals from bcm2835 */
55
+ return sysbus_mmio_get_region(s, 0);
54
55
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
56
object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj);
57
58
if (!sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), errp)) {
59
- return;
60
+ return false;
61
}
62
63
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals),
64
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
65
66
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0,
67
bc->peri_base, 1);
68
+ return true;
56
+}
69
+}
57
+
70
+
58
static void mps2tz_common_init(MachineState *machine)
71
+static void bcm2836_realize(DeviceState *dev, Error **errp)
59
{
72
+{
60
MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine);
73
+ BCM283XState *s = BCM283X(dev);
61
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
74
+ BCM283XClass *bc = BCM283X_GET_CLASS(dev);
62
{ "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 },
75
+ int n;
63
{ "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 },
76
+
64
{ "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 },
77
+ if (!bcm283x_common_realize(dev, errp)) {
65
- { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 },
78
+ return;
66
- { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 },
79
+ }
67
- { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 },
80
68
- { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 },
81
/* bcm2836 interrupt controller (and mailboxes, etc.) */
69
+ { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 },
82
if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) {
70
+ { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 },
71
+ { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 },
72
+ { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000 },
73
},
74
}, {
75
.name = "apb_ppcexp2",
76
--
83
--
77
2.20.1
84
2.20.1
78
85
79
86
diff view generated by jsdifflib
1
Convert to decodetree the insns in the Neon 2-reg-misc grouping which
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
we implement using gvec.
3
2
3
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
4
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-id: 20201024170127.3592182-7-f4bug@amsat.org
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200616170844.13318-8-peter.maydell@linaro.org
7
---
7
---
8
target/arm/neon-dp.decode | 11 +++++++
8
include/hw/arm/bcm2836.h | 1 +
9
target/arm/translate-neon.inc.c | 55 +++++++++++++++++++++++++++++++++
9
hw/arm/bcm2836.c | 34 ++++++++++++++++++++++++++++++++++
10
target/arm/translate.c | 35 +++++----------------
10
hw/arm/raspi.c | 2 ++
11
3 files changed, 74 insertions(+), 27 deletions(-)
11
3 files changed, 37 insertions(+)
12
12
13
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
13
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
14
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/neon-dp.decode
15
--- a/include/hw/arm/bcm2836.h
16
+++ b/target/arm/neon-dp.decode
16
+++ b/include/hw/arm/bcm2836.h
17
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
17
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)
18
VPADDL_S 1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc
18
* them, code using these devices should always handle them via the
19
VPADDL_U 1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc
19
* BCM283x base class, so they have no BCM2836(obj) etc macros.
20
20
*/
21
+ VMVN 1111 001 11 . 11 .. 00 .... 0 1011 . . 0 .... @2misc
21
+#define TYPE_BCM2835 "bcm2835"
22
+
22
#define TYPE_BCM2836 "bcm2836"
23
VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc
23
#define TYPE_BCM2837 "bcm2837"
24
VPADAL_U 1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc
24
25
25
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
26
+ VCGT0 1111 001 11 . 11 .. 01 .... 0 0000 . . 0 .... @2misc
27
+ VCGE0 1111 001 11 . 11 .. 01 .... 0 0001 . . 0 .... @2misc
28
+ VCEQ0 1111 001 11 . 11 .. 01 .... 0 0010 . . 0 .... @2misc
29
+ VCLE0 1111 001 11 . 11 .. 01 .... 0 0011 . . 0 .... @2misc
30
+ VCLT0 1111 001 11 . 11 .. 01 .... 0 0100 . . 0 .... @2misc
31
+
32
+ VABS 1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc
33
+ VNEG 1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc
34
+
35
VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc
36
VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc
37
38
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
39
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/translate-neon.inc.c
27
--- a/hw/arm/bcm2836.c
41
+++ b/target/arm/translate-neon.inc.c
28
+++ b/hw/arm/bcm2836.c
42
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a)
29
@@ -XXX,XX +XXX,XX @@ static bool bcm283x_common_realize(DeviceState *dev, Error **errp)
43
44
return true;
30
return true;
45
}
31
}
32
33
+static void bcm2835_realize(DeviceState *dev, Error **errp)
34
+{
35
+ BCM283XState *s = BCM283X(dev);
46
+
36
+
47
+static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn)
37
+ if (!bcm283x_common_realize(dev, errp)) {
48
+{
38
+ return;
49
+ int vec_size = a->q ? 16 : 8;
50
+ int rd_ofs = neon_reg_offset(a->vd, 0);
51
+ int rm_ofs = neon_reg_offset(a->vm, 0);
52
+
53
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
54
+ return false;
55
+ }
39
+ }
56
+
40
+
57
+ /* UNDEF accesses to D16-D31 if they don't exist. */
41
+ if (!qdev_realize(DEVICE(&s->cpu[0].core), NULL, errp)) {
58
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
42
+ return;
59
+ ((a->vd | a->vm) & 0x10)) {
60
+ return false;
61
+ }
43
+ }
62
+
44
+
63
+ if (a->size == 3) {
45
+ /* Connect irq/fiq outputs from the interrupt controller. */
64
+ return false;
46
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
65
+ }
47
+ qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ));
66
+
48
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
67
+ if ((a->vd | a->vm) & a->q) {
49
+ qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ));
68
+ return false;
69
+ }
70
+
71
+ if (!vfp_access_check(s)) {
72
+ return true;
73
+ }
74
+
75
+ fn(a->size, rd_ofs, rm_ofs, vec_size, vec_size);
76
+
77
+ return true;
78
+}
50
+}
79
+
51
+
80
+#define DO_2MISC_VEC(INSN, FN) \
52
static void bcm2836_realize(DeviceState *dev, Error **errp)
81
+ static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
53
{
82
+ { \
54
BCM283XState *s = BCM283X(dev);
83
+ return do_2misc_vec(s, a, FN); \
55
@@ -XXX,XX +XXX,XX @@ static void bcm283x_class_init(ObjectClass *oc, void *data)
84
+ }
56
dc->user_creatable = false;
57
}
58
59
+static void bcm2835_class_init(ObjectClass *oc, void *data)
60
+{
61
+ DeviceClass *dc = DEVICE_CLASS(oc);
62
+ BCM283XClass *bc = BCM283X_CLASS(oc);
85
+
63
+
86
+DO_2MISC_VEC(VNEG, tcg_gen_gvec_neg)
64
+ bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
87
+DO_2MISC_VEC(VABS, tcg_gen_gvec_abs)
65
+ bc->core_count = 1;
88
+DO_2MISC_VEC(VCEQ0, gen_gvec_ceq0)
66
+ bc->peri_base = 0x20000000;
89
+DO_2MISC_VEC(VCGT0, gen_gvec_cgt0)
67
+ dc->realize = bcm2835_realize;
90
+DO_2MISC_VEC(VCLE0, gen_gvec_cle0)
68
+};
91
+DO_2MISC_VEC(VCGE0, gen_gvec_cge0)
92
+DO_2MISC_VEC(VCLT0, gen_gvec_clt0)
93
+
69
+
94
+static bool trans_VMVN(DisasContext *s, arg_2misc *a)
70
static void bcm2836_class_init(ObjectClass *oc, void *data)
95
+{
71
{
96
+ if (a->size != 0) {
72
DeviceClass *dc = DEVICE_CLASS(oc);
97
+ return false;
73
@@ -XXX,XX +XXX,XX @@ static void bcm2837_class_init(ObjectClass *oc, void *data)
98
+ }
74
99
+ return do_2misc_vec(s, a, tcg_gen_gvec_not);
75
static const TypeInfo bcm283x_types[] = {
100
+}
76
{
101
diff --git a/target/arm/translate.c b/target/arm/translate.c
77
+ .name = TYPE_BCM2835,
78
+ .parent = TYPE_BCM283X,
79
+ .class_init = bcm2835_class_init,
80
+ }, {
81
.name = TYPE_BCM2836,
82
.parent = TYPE_BCM283X,
83
.class_init = bcm2836_class_init,
84
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
102
index XXXXXXX..XXXXXXX 100644
85
index XXXXXXX..XXXXXXX 100644
103
--- a/target/arm/translate.c
86
--- a/hw/arm/raspi.c
104
+++ b/target/arm/translate.c
87
+++ b/hw/arm/raspi.c
105
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
88
@@ -XXX,XX +XXX,XX @@ FIELD(REV_CODE, MEMORY_SIZE, 20, 3);
106
int size;
89
FIELD(REV_CODE, STYLE, 23, 1);
107
int pass;
90
108
int u;
91
typedef enum RaspiProcessorId {
109
- int vec_size;
92
+ PROCESSOR_ID_BCM2835 = 0,
110
TCGv_i32 tmp, tmp2;
93
PROCESSOR_ID_BCM2836 = 1,
111
94
PROCESSOR_ID_BCM2837 = 2,
112
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
95
} RaspiProcessorId;
113
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
96
@@ -XXX,XX +XXX,XX @@ static const struct {
114
VFP_DREG_D(rd, insn);
97
const char *type;
115
VFP_DREG_M(rm, insn);
98
int cores_count;
116
size = (insn >> 20) & 3;
99
} soc_property[] = {
117
- vec_size = q ? 16 : 8;
100
+ [PROCESSOR_ID_BCM2835] = {TYPE_BCM2835, 1},
118
rd_ofs = neon_reg_offset(rd, 0);
101
[PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS},
119
rm_ofs = neon_reg_offset(rm, 0);
102
[PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS},
120
103
};
121
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
122
case NEON_2RM_VSHLL:
123
case NEON_2RM_VCVT_F16_F32:
124
case NEON_2RM_VCVT_F32_F16:
125
+ case NEON_2RM_VMVN:
126
+ case NEON_2RM_VNEG:
127
+ case NEON_2RM_VABS:
128
+ case NEON_2RM_VCEQ0:
129
+ case NEON_2RM_VCGT0:
130
+ case NEON_2RM_VCLE0:
131
+ case NEON_2RM_VCGE0:
132
+ case NEON_2RM_VCLT0:
133
/* handled by decodetree */
134
return 1;
135
case NEON_2RM_VTRN:
136
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
137
q ? gen_helper_crypto_sha256su0
138
: gen_helper_crypto_sha1su1);
139
break;
140
- case NEON_2RM_VMVN:
141
- tcg_gen_gvec_not(0, rd_ofs, rm_ofs, vec_size, vec_size);
142
- break;
143
- case NEON_2RM_VNEG:
144
- tcg_gen_gvec_neg(size, rd_ofs, rm_ofs, vec_size, vec_size);
145
- break;
146
- case NEON_2RM_VABS:
147
- tcg_gen_gvec_abs(size, rd_ofs, rm_ofs, vec_size, vec_size);
148
- break;
149
-
150
- case NEON_2RM_VCEQ0:
151
- gen_gvec_ceq0(size, rd_ofs, rm_ofs, vec_size, vec_size);
152
- break;
153
- case NEON_2RM_VCGT0:
154
- gen_gvec_cgt0(size, rd_ofs, rm_ofs, vec_size, vec_size);
155
- break;
156
- case NEON_2RM_VCLE0:
157
- gen_gvec_cle0(size, rd_ofs, rm_ofs, vec_size, vec_size);
158
- break;
159
- case NEON_2RM_VCGE0:
160
- gen_gvec_cge0(size, rd_ofs, rm_ofs, vec_size, vec_size);
161
- break;
162
- case NEON_2RM_VCLT0:
163
- gen_gvec_clt0(size, rd_ofs, rm_ofs, vec_size, vec_size);
164
- break;
165
166
default:
167
elementwise:
168
--
104
--
169
2.20.1
105
2.20.1
170
106
171
107
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Use self-explicit definitions instead of magic values.
3
The Pi A is almost the first machine released.
4
It uses a BCM2835 SoC which includes a ARMv6Z core.
4
5
6
Example booting the machine using content from [*]
7
(we use the device tree from the B model):
8
9
$ qemu-system-arm -M raspi1ap -serial stdio \
10
-kernel raspberrypi/firmware/boot/kernel.img \
11
-dtb raspberrypi/firmware/boot/bcm2708-rpi-b-plus.dtb \
12
-append 'earlycon=pl011,0x20201000 console=ttyAMA0'
13
[ 0.000000] Booting Linux on physical CPU 0x0
14
[ 0.000000] Linux version 4.19.118+ (dom@buildbot) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1311 Mon Apr 27 14:16:15 BST 2020
15
[ 0.000000] CPU: ARMv6-compatible processor [410fb767] revision 7 (ARMv7), cr=00c5387d
16
[ 0.000000] CPU: VIPT aliasing data cache, unknown instruction cache
17
[ 0.000000] OF: fdt: Machine model: Raspberry Pi Model B+
18
...
19
20
[*] http://archive.raspberrypi.org/debian/pool/main/r/raspberrypi-firmware/raspberrypi-kernel_1.20200512-2_armhf.deb
21
22
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
23
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-id: 20200617072539.32686-4-f4bug@amsat.org
24
Message-id: 20201024170127.3592182-8-f4bug@amsat.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
26
---
10
hw/i2c/versatile_i2c.c | 7 +++++--
27
hw/arm/raspi.c | 13 +++++++++++++
11
1 file changed, 5 insertions(+), 2 deletions(-)
28
1 file changed, 13 insertions(+)
12
29
13
diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
30
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
14
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/i2c/versatile_i2c.c
32
--- a/hw/arm/raspi.c
16
+++ b/hw/i2c/versatile_i2c.c
33
+++ b/hw/arm/raspi.c
17
@@ -XXX,XX +XXX,XX @@ REG32(CONTROL_GET, 0)
34
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_common_init(MachineClass *mc,
18
REG32(CONTROL_SET, 0)
35
mc->default_ram_id = "ram";
19
REG32(CONTROL_CLR, 4)
36
};
20
37
21
+#define SCL BIT(0)
38
+static void raspi1ap_machine_class_init(ObjectClass *oc, void *data)
22
+#define SDA BIT(1)
39
+{
40
+ MachineClass *mc = MACHINE_CLASS(oc);
41
+ RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
23
+
42
+
24
static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
43
+ rmc->board_rev = 0x900021; /* Revision 1.1 */
25
unsigned size)
44
+ raspi_machine_class_common_init(mc, rmc->board_rev);
45
+};
46
+
47
static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
26
{
48
{
27
@@ -XXX,XX +XXX,XX @@ static void versatile_i2c_write(void *opaque, hwaddr offset,
49
MachineClass *mc = MACHINE_CLASS(oc);
28
qemu_log_mask(LOG_GUEST_ERROR,
50
@@ -XXX,XX +XXX,XX @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
29
"%s: Bad offset 0x%x\n", __func__, (int)offset);
51
30
}
52
static const TypeInfo raspi_machine_types[] = {
31
- bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0);
53
{
32
- s->in = bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0);
54
+ .name = MACHINE_TYPE_NAME("raspi1ap"),
33
+ bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SCL, (s->out & SCL) != 0);
55
+ .parent = TYPE_RASPI_MACHINE,
34
+ s->in = bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SDA, (s->out & SDA) != 0);
56
+ .class_init = raspi1ap_machine_class_init,
35
}
57
+ }, {
36
58
.name = MACHINE_TYPE_NAME("raspi2b"),
37
static const MemoryRegionOps versatile_i2c_ops = {
59
.parent = TYPE_RASPI_MACHINE,
60
.class_init = raspi2b_machine_class_init,
38
--
61
--
39
2.20.1
62
2.20.1
40
63
41
64
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Use self-explicit definitions instead of magic values.
3
Similarly to the Pi A, the Pi Zero uses a BCM2835 SoC (ARMv6Z core).
4
4
5
The only difference between the revision 1.2 and 1.3 is the latter
6
exposes a CSI camera connector. As we do not implement the Unicam
7
peripheral, there is no point in exposing a camera connector :)
8
Therefore we choose to model the 1.2 revision.
9
10
Example booting the machine using content from [*]:
11
12
$ qemu-system-arm -M raspi0 -serial stdio \
13
-kernel raspberrypi/firmware/boot/kernel.img \
14
-dtb raspberrypi/firmware/boot/bcm2708-rpi-zero.dtb \
15
-append 'printk.time=0 earlycon=pl011,0x20201000 console=ttyAMA0'
16
[ 0.000000] Booting Linux on physical CPU 0x0
17
[ 0.000000] Linux version 4.19.118+ (dom@buildbot) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1311 Mon Apr 27 14:16:15 BST 2020
18
[ 0.000000] CPU: ARMv6-compatible processor [410fb767] revision 7 (ARMv7), cr=00c5387d
19
[ 0.000000] CPU: VIPT aliasing data cache, unknown instruction cache
20
[ 0.000000] OF: fdt: Machine model: Raspberry Pi Zero
21
...
22
23
[*] http://archive.raspberrypi.org/debian/pool/main/r/raspberrypi-firmware/raspberrypi-kernel_1.20200512-2_armhf.deb
24
25
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
26
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
27
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-id: 20200617072539.32686-3-f4bug@amsat.org
28
Message-id: 20201024170127.3592182-9-f4bug@amsat.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
30
---
10
hw/i2c/versatile_i2c.c | 14 ++++++++++----
31
hw/arm/raspi.c | 13 +++++++++++++
11
1 file changed, 10 insertions(+), 4 deletions(-)
32
1 file changed, 13 insertions(+)
12
33
13
diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
34
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
14
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/i2c/versatile_i2c.c
36
--- a/hw/arm/raspi.c
16
+++ b/hw/i2c/versatile_i2c.c
37
+++ b/hw/arm/raspi.c
17
@@ -XXX,XX +XXX,XX @@
38
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_common_init(MachineClass *mc,
18
#include "qemu/osdep.h"
39
mc->default_ram_id = "ram";
19
#include "hw/sysbus.h"
40
};
20
#include "hw/i2c/bitbang_i2c.h"
41
21
+#include "hw/registerfields.h"
42
+static void raspi0_machine_class_init(ObjectClass *oc, void *data)
22
#include "qemu/log.h"
43
+{
23
#include "qemu/module.h"
44
+ MachineClass *mc = MACHINE_CLASS(oc);
24
45
+ RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
25
@@ -XXX,XX +XXX,XX @@ typedef struct VersatileI2CState {
26
int in;
27
} VersatileI2CState;
28
29
+REG32(CONTROL_GET, 0)
30
+REG32(CONTROL_SET, 0)
31
+REG32(CONTROL_CLR, 4)
32
+
46
+
33
static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
47
+ rmc->board_rev = 0x920092; /* Revision 1.2 */
34
unsigned size)
48
+ raspi_machine_class_common_init(mc, rmc->board_rev);
49
+};
50
+
51
static void raspi1ap_machine_class_init(ObjectClass *oc, void *data)
35
{
52
{
36
VersatileI2CState *s = (VersatileI2CState *)opaque;
53
MachineClass *mc = MACHINE_CLASS(oc);
37
54
@@ -XXX,XX +XXX,XX @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
38
- if (offset == 0) {
55
39
+ switch (offset) {
56
static const TypeInfo raspi_machine_types[] = {
40
+ case A_CONTROL_SET:
57
{
41
return (s->out & 1) | (s->in << 1);
58
+ .name = MACHINE_TYPE_NAME("raspi0"),
42
- } else {
59
+ .parent = TYPE_RASPI_MACHINE,
43
+ default:
60
+ .class_init = raspi0_machine_class_init,
44
qemu_log_mask(LOG_GUEST_ERROR,
61
+ }, {
45
"%s: Bad offset 0x%x\n", __func__, (int)offset);
62
.name = MACHINE_TYPE_NAME("raspi1ap"),
46
return -1;
63
.parent = TYPE_RASPI_MACHINE,
47
@@ -XXX,XX +XXX,XX @@ static void versatile_i2c_write(void *opaque, hwaddr offset,
64
.class_init = raspi1ap_machine_class_init,
48
VersatileI2CState *s = (VersatileI2CState *)opaque;
49
50
switch (offset) {
51
- case 0:
52
+ case A_CONTROL_SET:
53
s->out |= value & 3;
54
break;
55
- case 4:
56
+ case A_CONTROL_CLR:
57
s->out &= ~value;
58
break;
59
default:
60
--
65
--
61
2.20.1
66
2.20.1
62
67
63
68
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Add a trace event to see when a guest disable/enable the watchdog.
3
The Pi 3A+ is a stripped down version of the 3B:
4
- 512 MiB of RAM instead of 1 GiB
5
- no on-board ethernet chipset
4
6
7
Add it as it is a closer match to what we model.
8
9
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-id: 20200617072539.32686-2-f4bug@amsat.org
11
Message-id: 20201024170127.3592182-10-f4bug@amsat.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
13
---
10
hw/watchdog/cmsdk-apb-watchdog.c | 1 +
14
hw/arm/raspi.c | 13 +++++++++++++
11
hw/watchdog/trace-events | 1 +
15
1 file changed, 13 insertions(+)
12
2 files changed, 2 insertions(+)
13
16
14
diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c
17
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/watchdog/cmsdk-apb-watchdog.c
19
--- a/hw/arm/raspi.c
17
+++ b/hw/watchdog/cmsdk-apb-watchdog.c
20
+++ b/hw/arm/raspi.c
18
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset,
21
@@ -XXX,XX +XXX,XX @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
19
break;
22
};
20
case A_WDOGLOCK:
23
21
s->lock = (value != WDOG_UNLOCK_VALUE);
24
#ifdef TARGET_AARCH64
22
+ trace_cmsdk_apb_watchdog_lock(s->lock);
25
+static void raspi3ap_machine_class_init(ObjectClass *oc, void *data)
23
break;
26
+{
24
case A_WDOGITCR:
27
+ MachineClass *mc = MACHINE_CLASS(oc);
25
if (s->is_luminary) {
28
+ RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
26
diff --git a/hw/watchdog/trace-events b/hw/watchdog/trace-events
29
+
27
index XXXXXXX..XXXXXXX 100644
30
+ rmc->board_rev = 0x9020e0; /* Revision 1.0 */
28
--- a/hw/watchdog/trace-events
31
+ raspi_machine_class_common_init(mc, rmc->board_rev);
29
+++ b/hw/watchdog/trace-events
32
+};
30
@@ -XXX,XX +XXX,XX @@
33
+
31
cmsdk_apb_watchdog_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
34
static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
32
cmsdk_apb_watchdog_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
35
{
33
cmsdk_apb_watchdog_reset(void) "CMSDK APB watchdog: reset"
36
MachineClass *mc = MACHINE_CLASS(oc);
34
+cmsdk_apb_watchdog_lock(uint32_t lock) "CMSDK APB watchdog: lock %" PRIu32
37
@@ -XXX,XX +XXX,XX @@ static const TypeInfo raspi_machine_types[] = {
38
.parent = TYPE_RASPI_MACHINE,
39
.class_init = raspi2b_machine_class_init,
40
#ifdef TARGET_AARCH64
41
+ }, {
42
+ .name = MACHINE_TYPE_NAME("raspi3ap"),
43
+ .parent = TYPE_RASPI_MACHINE,
44
+ .class_init = raspi3ap_machine_class_init,
45
}, {
46
.name = MACHINE_TYPE_NAME("raspi3b"),
47
.parent = TYPE_RASPI_MACHINE,
35
--
48
--
36
2.20.1
49
2.20.1
37
50
38
51
diff view generated by jsdifflib
New patch
1
From: "Dr. David Alan Gilbert" <dgilbert@redhat.com>
1
2
3
Use of 0x%d - make up our mind as 0x%x
4
5
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Acked-by: Eric Auger <eric.auger@redhat.com>
8
Message-id: 20201014193355.53074-1-dgilbert@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/trace-events | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/trace-events
17
+++ b/hw/arm/trace-events
18
@@ -XXX,XX +XXX,XX @@ smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64
19
smmuv3_decode_cd(uint32_t oas) "oas=%d"
20
smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz, bool had) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d had:%d"
21
smmuv3_cmdq_cfgi_ste(int streamid) "streamid =%d"
22
-smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%d - end=0x%d"
23
+smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%x - end=0x%x"
24
smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid = %d"
25
smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid %d (hits=%d, misses=%d, hit rate=%d)"
26
smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid %d (hits=%d, misses=%d, hit rate=%d)"
27
--
28
2.20.1
29
30
diff view generated by jsdifflib
New patch
1
From: Luc Michel <luc@lmichel.fr>
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
5
Signed-off-by: Luc Michel <luc@lmichel.fr>
6
Tested-by: Guenter Roeck <linux@roeck-us.net>
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
include/hw/clock.h | 5 +++++
11
1 file changed, 5 insertions(+)
12
13
diff --git a/include/hw/clock.h b/include/hw/clock.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/clock.h
16
+++ b/include/hw/clock.h
17
@@ -XXX,XX +XXX,XX @@ extern const VMStateDescription vmstate_clock;
18
VMSTATE_CLOCK_V(field, state, 0)
19
#define VMSTATE_CLOCK_V(field, state, version) \
20
VMSTATE_STRUCT_POINTER_V(field, state, version, vmstate_clock, Clock)
21
+#define VMSTATE_ARRAY_CLOCK(field, state, num) \
22
+ VMSTATE_ARRAY_CLOCK_V(field, state, num, 0)
23
+#define VMSTATE_ARRAY_CLOCK_V(field, state, num, version) \
24
+ VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(field, state, num, version, \
25
+ vmstate_clock, Clock)
26
27
/**
28
* clock_setup_canonical_path:
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
New patch
1
From: Luc Michel <luc@lmichel.fr>
1
2
3
The nanosecond unit greatly limits the dynamic range we can display in
4
clock value traces, for values in the order of 1GHz and more. The
5
internal representation can go way beyond this value and it is quite
6
common for today's clocks to be within those ranges.
7
8
For example, a frequency between 500MHz+ and 1GHz will be displayed as
9
1ns. Beyond 1GHz, it will show up as 0ns.
10
11
Replace nanosecond periods traces with frequencies in the Hz unit
12
to have more dynamic range in the trace output.
13
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
16
Signed-off-by: Luc Michel <luc@lmichel.fr>
17
Tested-by: Guenter Roeck <linux@roeck-us.net>
18
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
hw/core/clock.c | 6 +++---
22
hw/core/trace-events | 4 ++--
23
2 files changed, 5 insertions(+), 5 deletions(-)
24
25
diff --git a/hw/core/clock.c b/hw/core/clock.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/core/clock.c
28
+++ b/hw/core/clock.c
29
@@ -XXX,XX +XXX,XX @@ bool clock_set(Clock *clk, uint64_t period)
30
if (clk->period == period) {
31
return false;
32
}
33
- trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_NS(clk->period),
34
- CLOCK_PERIOD_TO_NS(period));
35
+ trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_HZ(clk->period),
36
+ CLOCK_PERIOD_TO_HZ(period));
37
clk->period = period;
38
39
return true;
40
@@ -XXX,XX +XXX,XX @@ static void clock_propagate_period(Clock *clk, bool call_callbacks)
41
if (child->period != clk->period) {
42
child->period = clk->period;
43
trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk),
44
- CLOCK_PERIOD_TO_NS(clk->period),
45
+ CLOCK_PERIOD_TO_HZ(clk->period),
46
call_callbacks);
47
if (call_callbacks && child->callback) {
48
child->callback(child->callback_opaque);
49
diff --git a/hw/core/trace-events b/hw/core/trace-events
50
index XXXXXXX..XXXXXXX 100644
51
--- a/hw/core/trace-events
52
+++ b/hw/core/trace-events
53
@@ -XXX,XX +XXX,XX @@ resettable_transitional_function(void *obj, const char *objtype) "obj=%p(%s)"
54
# clock.c
55
clock_set_source(const char *clk, const char *src) "'%s', src='%s'"
56
clock_disconnect(const char *clk) "'%s'"
57
-clock_set(const char *clk, uint64_t old, uint64_t new) "'%s', ns=%"PRIu64"->%"PRIu64
58
+clock_set(const char *clk, uint64_t old, uint64_t new) "'%s', %"PRIu64"Hz->%"PRIu64"Hz"
59
clock_propagate(const char *clk) "'%s'"
60
-clock_update(const char *clk, const char *src, uint64_t val, int cb) "'%s', src='%s', ns=%"PRIu64", cb=%d"
61
+clock_update(const char *clk, const char *src, uint64_t hz, int cb) "'%s', src='%s', val=%"PRIu64"Hz cb=%d"
62
--
63
2.20.1
64
65
diff view generated by jsdifflib
1
Since commit ba3e7926691ed3 it has been unnecessary for target code
1
From: Luc Michel <luc@lmichel.fr>
2
to call gen_io_end() after an IO instruction in icount mode; it is
3
sufficient to call gen_io_start() before it and to force the end of
4
the TB.
5
2
6
Many now-unnecessary calls to gen_io_end() were removed in commit
3
The CPRMAN (clock controller) was mapped at the watchdog/power manager
7
9e9b10c6491153b, but some were missed or accidentally added later.
4
address. It was also split into two unimplemented peripherals (CM and
8
Remove unneeded calls from the arm target:
5
A2W) but this is really the same one, as shown by this extract of the
6
Raspberry Pi 3 Linux device tree:
9
7
10
* the call in the handling of exception-return-via-LDM is
8
watchdog@7e100000 {
11
unnecessary, and the code is already forcing end-of-TB
9
compatible = "brcm,bcm2835-pm\0brcm,bcm2835-pm-wdt";
12
* the call in the VFP access check code is more complicated:
10
[...]
13
we weren't ending the TB, so we need to add the code to
11
reg = <0x7e100000 0x114 0x7e00a000 0x24>;
14
force that by setting DISAS_UPDATE
12
[...]
15
* the doc comment for ARM_CP_IO doesn't need to mention
13
};
16
gen_io_end() any more
17
14
15
[...]
16
cprman@7e101000 {
17
compatible = "brcm,bcm2835-cprman";
18
[...]
19
reg = <0x7e101000 0x2000>;
20
[...]
21
};
22
23
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
24
Signed-off-by: Luc Michel <luc@lmichel.fr>
25
Tested-by: Guenter Roeck <linux@roeck-us.net>
26
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru>
22
Message-id: 20200619170324.12093-1-peter.maydell@linaro.org
23
---
28
---
24
target/arm/cpu.h | 2 +-
29
include/hw/arm/bcm2835_peripherals.h | 2 +-
25
target/arm/translate-vfp.inc.c | 7 +++----
30
include/hw/arm/raspi_platform.h | 5 ++---
26
target/arm/translate.c | 3 ---
31
hw/arm/bcm2835_peripherals.c | 4 ++--
27
3 files changed, 4 insertions(+), 8 deletions(-)
32
3 files changed, 5 insertions(+), 6 deletions(-)
28
33
29
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
34
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
30
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/cpu.h
36
--- a/include/hw/arm/bcm2835_peripherals.h
32
+++ b/target/arm/cpu.h
37
+++ b/include/hw/arm/bcm2835_peripherals.h
33
@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
38
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
34
* migration or KVM state synchronization. (Typically this is for "registers"
39
BCM2835MphiState mphi;
35
* which are actually used as instructions for cache maintenance and so on.)
40
UnimplementedDeviceState txp;
36
* IO indicates that this register does I/O and therefore its accesses
41
UnimplementedDeviceState armtmr;
37
- * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
42
+ UnimplementedDeviceState powermgt;
38
+ * need to be marked with gen_io_start() and also end the TB. In particular,
43
UnimplementedDeviceState cprman;
39
* registers which implement clocks or timers require this.
44
- UnimplementedDeviceState a2w;
40
* RAISES_EXC is for when the read or write hook might raise an exception;
45
PL011State uart0;
41
* the generated code will synchronize the CPU state before calling the hook
46
BCM2835AuxState aux;
42
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
47
BCM2835FBState fb;
48
diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h
43
index XXXXXXX..XXXXXXX 100644
49
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/translate-vfp.inc.c
50
--- a/include/hw/arm/raspi_platform.h
45
+++ b/target/arm/translate-vfp.inc.c
51
+++ b/include/hw/arm/raspi_platform.h
46
@@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
52
@@ -XXX,XX +XXX,XX @@
47
if (s->v7m_lspact) {
53
#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */
48
/*
54
#define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
49
* Lazy state saving affects external memory and also the NVIC,
55
* Doorbells & Mailboxes */
50
- * so we must mark it as an IO operation for icount.
56
-#define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */
51
+ * so we must mark it as an IO operation for icount (and cause
57
-#define CM_OFFSET 0x101000 /* Clock Management */
52
+ * this to be the last insn in the TB).
58
-#define A2W_OFFSET 0x102000 /* Reset controller */
53
*/
59
+#define PM_OFFSET 0x100000 /* Power Management */
54
if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
60
+#define CPRMAN_OFFSET 0x101000 /* Clock Management */
55
+ s->base.is_jmp = DISAS_UPDATE;
61
#define AVS_OFFSET 0x103000 /* Audio Video Standard */
56
gen_io_start();
62
#define RNG_OFFSET 0x104000
57
}
63
#define GPIO_OFFSET 0x200000
58
gen_helper_v7m_preserve_fp_state(cpu_env);
64
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
59
- if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
60
- gen_io_end();
61
- }
62
/*
63
* If the preserve_fp_state helper doesn't throw an exception
64
* then it will clear LSPACT; we don't need to repeat this for
65
diff --git a/target/arm/translate.c b/target/arm/translate.c
66
index XXXXXXX..XXXXXXX 100644
65
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/translate.c
66
--- a/hw/arm/bcm2835_peripherals.c
68
+++ b/target/arm/translate.c
67
+++ b/hw/arm/bcm2835_peripherals.c
69
@@ -XXX,XX +XXX,XX @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
68
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
70
gen_io_start();
69
71
}
70
create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
72
gen_helper_cpsr_write_eret(cpu_env, tmp);
71
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
73
- if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
72
- create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
74
- gen_io_end();
73
- create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
75
- }
74
+ create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
76
tcg_temp_free_i32(tmp);
75
+ create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x2000);
77
/* Must exit loop to check un-masked IRQs */
76
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
78
s->base.is_jmp = DISAS_EXIT;
77
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
78
create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
79
--
79
--
80
2.20.1
80
2.20.1
81
81
82
82
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Luc Michel <luc@lmichel.fr>
2
2
3
'ARM SBCon two-wire serial bus interface' is the official
3
The BCM2835 CPRMAN is the clock manager of the SoC. It is composed of a
4
name describing the pair of registers used to bitbanging
4
main oscillator, and several sub-components (PLLs, multiplexers, ...) to
5
I2C in the Versatile boards.
5
generate the BCM2835 clock tree.
6
6
7
Make the private VersatileI2CState structure as public
7
This commit adds a skeleton of the CPRMAN, with a dummy register
8
ArmSbconI2CState.
8
read/write implementation. It embeds the main oscillator (xosc) from
9
Add the TYPE_ARM_SBCON_I2C, alias to our current
9
which all the clocks will be derived.
10
TYPE_VERSATILE_I2C model.
10
11
Rename the memory region description as 'arm_sbcon_i2c'.
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
12
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Signed-off-by: Luc Michel <luc@lmichel.fr>
14
Message-id: 20200617072539.32686-5-f4bug@amsat.org
14
Tested-by: Guenter Roeck <linux@roeck-us.net>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
16
---
18
include/hw/i2c/arm_sbcon_i2c.h | 35 ++++++++++++++++++++++++++++++++++
17
include/hw/arm/bcm2835_peripherals.h | 3 +-
19
hw/i2c/versatile_i2c.c | 17 +++++------------
18
include/hw/misc/bcm2835_cprman.h | 37 +++++
20
MAINTAINERS | 1 +
19
include/hw/misc/bcm2835_cprman_internals.h | 24 +++
21
3 files changed, 41 insertions(+), 12 deletions(-)
20
hw/arm/bcm2835_peripherals.c | 11 +-
22
create mode 100644 include/hw/i2c/arm_sbcon_i2c.h
21
hw/misc/bcm2835_cprman.c | 163 +++++++++++++++++++++
23
22
hw/misc/meson.build | 1 +
24
diff --git a/include/hw/i2c/arm_sbcon_i2c.h b/include/hw/i2c/arm_sbcon_i2c.h
23
hw/misc/trace-events | 5 +
24
7 files changed, 242 insertions(+), 2 deletions(-)
25
create mode 100644 include/hw/misc/bcm2835_cprman.h
26
create mode 100644 include/hw/misc/bcm2835_cprman_internals.h
27
create mode 100644 hw/misc/bcm2835_cprman.c
28
29
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/include/hw/arm/bcm2835_peripherals.h
32
+++ b/include/hw/arm/bcm2835_peripherals.h
33
@@ -XXX,XX +XXX,XX @@
34
#include "hw/misc/bcm2835_mbox.h"
35
#include "hw/misc/bcm2835_mphi.h"
36
#include "hw/misc/bcm2835_thermal.h"
37
+#include "hw/misc/bcm2835_cprman.h"
38
#include "hw/sd/sdhci.h"
39
#include "hw/sd/bcm2835_sdhost.h"
40
#include "hw/gpio/bcm2835_gpio.h"
41
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
42
UnimplementedDeviceState txp;
43
UnimplementedDeviceState armtmr;
44
UnimplementedDeviceState powermgt;
45
- UnimplementedDeviceState cprman;
46
+ BCM2835CprmanState cprman;
47
PL011State uart0;
48
BCM2835AuxState aux;
49
BCM2835FBState fb;
50
diff --git a/include/hw/misc/bcm2835_cprman.h b/include/hw/misc/bcm2835_cprman.h
25
new file mode 100644
51
new file mode 100644
26
index XXXXXXX..XXXXXXX
52
index XXXXXXX..XXXXXXX
27
--- /dev/null
53
--- /dev/null
28
+++ b/include/hw/i2c/arm_sbcon_i2c.h
54
+++ b/include/hw/misc/bcm2835_cprman.h
29
@@ -XXX,XX +XXX,XX @@
55
@@ -XXX,XX +XXX,XX @@
30
+/*
56
+/*
31
+ * ARM SBCon two-wire serial bus interface (I2C bitbang)
57
+ * BCM2835 CPRMAN clock manager
32
+ * a.k.a.
58
+ *
33
+ * ARM Versatile I2C controller
59
+ * Copyright (c) 2020 Luc Michel <luc@lmichel.fr>
34
+ *
35
+ * Copyright (c) 2006-2007 CodeSourcery.
36
+ * Copyright (c) 2012 Oskar Andero <oskar.andero@gmail.com>
37
+ * Copyright (C) 2020 Philippe Mathieu-Daudé <f4bug@amsat.org>
38
+ *
60
+ *
39
+ * SPDX-License-Identifier: GPL-2.0-or-later
61
+ * SPDX-License-Identifier: GPL-2.0-or-later
40
+ */
62
+ */
41
+#ifndef HW_I2C_ARM_SBCON_H
63
+
42
+#define HW_I2C_ARM_SBCON_H
64
+#ifndef HW_MISC_CPRMAN_H
65
+#define HW_MISC_CPRMAN_H
43
+
66
+
44
+#include "hw/sysbus.h"
67
+#include "hw/sysbus.h"
45
+#include "hw/i2c/bitbang_i2c.h"
68
+#include "hw/qdev-clock.h"
46
+
69
+
47
+#define TYPE_VERSATILE_I2C "versatile_i2c"
70
+#define TYPE_BCM2835_CPRMAN "bcm2835-cprman"
48
+#define TYPE_ARM_SBCON_I2C TYPE_VERSATILE_I2C
71
+
49
+
72
+typedef struct BCM2835CprmanState BCM2835CprmanState;
50
+#define ARM_SBCON_I2C(obj) \
73
+
51
+ OBJECT_CHECK(ArmSbconI2CState, (obj), TYPE_ARM_SBCON_I2C)
74
+DECLARE_INSTANCE_CHECKER(BCM2835CprmanState, CPRMAN,
52
+
75
+ TYPE_BCM2835_CPRMAN)
53
+typedef struct ArmSbconI2CState {
76
+
77
+#define CPRMAN_NUM_REGS (0x2000 / sizeof(uint32_t))
78
+
79
+struct BCM2835CprmanState {
54
+ /*< private >*/
80
+ /*< private >*/
55
+ SysBusDevice parent_obj;
81
+ SysBusDevice parent_obj;
82
+
56
+ /*< public >*/
83
+ /*< public >*/
57
+
58
+ MemoryRegion iomem;
84
+ MemoryRegion iomem;
59
+ bitbang_i2c_interface bitbang;
85
+
60
+ int out;
86
+ uint32_t regs[CPRMAN_NUM_REGS];
61
+ int in;
87
+ uint32_t xosc_freq;
62
+} ArmSbconI2CState;
88
+
63
+
89
+ Clock *xosc;
64
+#endif /* HW_I2C_ARM_SBCON_H */
90
+};
65
diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
91
+
92
+#endif
93
diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/bcm2835_cprman_internals.h
94
new file mode 100644
95
index XXXXXXX..XXXXXXX
96
--- /dev/null
97
+++ b/include/hw/misc/bcm2835_cprman_internals.h
98
@@ -XXX,XX +XXX,XX @@
99
+/*
100
+ * BCM2835 CPRMAN clock manager
101
+ *
102
+ * Copyright (c) 2020 Luc Michel <luc@lmichel.fr>
103
+ *
104
+ * SPDX-License-Identifier: GPL-2.0-or-later
105
+ */
106
+
107
+#ifndef HW_MISC_CPRMAN_INTERNALS_H
108
+#define HW_MISC_CPRMAN_INTERNALS_H
109
+
110
+#include "hw/registerfields.h"
111
+#include "hw/misc/bcm2835_cprman.h"
112
+
113
+/* Register map */
114
+
115
+/*
116
+ * This field is common to all registers. Each register write value must match
117
+ * the CPRMAN_PASSWORD magic value in its 8 MSB.
118
+ */
119
+FIELD(CPRMAN, PASSWORD, 24, 8)
120
+#define CPRMAN_PASSWORD 0x5a
121
+
122
+#endif
123
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
66
index XXXXXXX..XXXXXXX 100644
124
index XXXXXXX..XXXXXXX 100644
67
--- a/hw/i2c/versatile_i2c.c
125
--- a/hw/arm/bcm2835_peripherals.c
68
+++ b/hw/i2c/versatile_i2c.c
126
+++ b/hw/arm/bcm2835_peripherals.c
127
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
128
/* DWC2 */
129
object_initialize_child(obj, "dwc2", &s->dwc2, TYPE_DWC2_USB);
130
131
+ /* CPRMAN clock manager */
132
+ object_initialize_child(obj, "cprman", &s->cprman, TYPE_BCM2835_CPRMAN);
133
+
134
object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
135
OBJECT(&s->gpu_bus_mr));
136
}
137
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
138
return;
139
}
140
141
+ /* CPRMAN clock manager */
142
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->cprman), errp)) {
143
+ return;
144
+ }
145
+ memory_region_add_subregion(&s->peri_mr, CPRMAN_OFFSET,
146
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cprman), 0));
147
+
148
memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET,
149
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0));
150
sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic));
151
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
152
create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
153
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
154
create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
155
- create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x2000);
156
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
157
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
158
create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
159
diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c
160
new file mode 100644
161
index XXXXXXX..XXXXXXX
162
--- /dev/null
163
+++ b/hw/misc/bcm2835_cprman.c
69
@@ -XXX,XX +XXX,XX @@
164
@@ -XXX,XX +XXX,XX @@
70
/*
165
+/*
71
- * ARM Versatile I2C controller
166
+ * BCM2835 CPRMAN clock manager
72
+ * ARM SBCon two-wire serial bus interface (I2C bitbang)
167
+ *
73
+ * a.k.a. ARM Versatile I2C controller
168
+ * Copyright (c) 2020 Luc Michel <luc@lmichel.fr>
74
*
169
+ *
75
* Copyright (c) 2006-2007 CodeSourcery.
170
+ * SPDX-License-Identifier: GPL-2.0-or-later
76
* Copyright (c) 2012 Oskar Andero <oskar.andero@gmail.com>
171
+ */
77
@@ -XXX,XX +XXX,XX @@
172
+
78
*/
173
+/*
79
174
+ * This peripheral is roughly divided into 3 main parts:
80
#include "qemu/osdep.h"
175
+ * - the PLLs
81
-#include "hw/sysbus.h"
176
+ * - the PLL channels
82
-#include "hw/i2c/bitbang_i2c.h"
177
+ * - the clock muxes
83
+#include "hw/i2c/arm_sbcon_i2c.h"
178
+ *
84
#include "hw/registerfields.h"
179
+ * A main oscillator (xosc) feeds all the PLLs. Each PLLs has one or more
85
#include "qemu/log.h"
180
+ * channels. Those channel are then connected to the clock muxes. Each mux has
86
#include "qemu/module.h"
181
+ * multiples sources (usually the xosc, some of the PLL channels and some "test
87
182
+ * debug" clocks). A mux is configured to select a given source through its
88
-#define TYPE_VERSATILE_I2C "versatile_i2c"
183
+ * control register. Each mux has one output clock that also goes out of the
89
#define VERSATILE_I2C(obj) \
184
+ * CPRMAN. This output clock usually connects to another peripheral in the SoC
90
OBJECT_CHECK(VersatileI2CState, (obj), TYPE_VERSATILE_I2C)
185
+ * (so a given mux is dedicated to a peripheral).
91
186
+ *
92
-typedef struct VersatileI2CState {
187
+ * At each level (PLL, channel and mux), the clock can be altered through
93
- SysBusDevice parent_obj;
188
+ * dividers (and multipliers in case of the PLLs), and can be disabled (in this
94
+typedef ArmSbconI2CState VersatileI2CState;
189
+ * case, the next levels see no clock).
95
190
+ *
96
- MemoryRegion iomem;
191
+ * This can be sum-up as follows (this is an example and not the actual BCM2835
97
- bitbang_i2c_interface bitbang;
192
+ * clock tree):
98
- int out;
193
+ *
99
- int in;
194
+ * /-->[PLL]-|->[PLL channel]--... [mux]--> to peripherals
100
-} VersatileI2CState;
195
+ * | |->[PLL channel] muxes takes [mux]
101
196
+ * | \->[PLL channel] inputs from [mux]
102
REG32(CONTROL_GET, 0)
197
+ * | some channels [mux]
103
REG32(CONTROL_SET, 0)
198
+ * [xosc]---|-->[PLL]-|->[PLL channel] and other srcs [mux]
104
@@ -XXX,XX +XXX,XX @@ static void versatile_i2c_init(Object *obj)
199
+ * | \->[PLL channel] ...-->[mux]
105
bus = i2c_init_bus(dev, "i2c");
200
+ * | [mux]
106
bitbang_i2c_init(&s->bitbang, bus);
201
+ * \-->[PLL]--->[PLL channel] [mux]
107
memory_region_init_io(&s->iomem, obj, &versatile_i2c_ops, s,
202
+ *
108
- "versatile_i2c", 0x1000);
203
+ * The page at https://elinux.org/The_Undocumented_Pi gives the actual clock
109
+ "arm_sbcon_i2c", 0x1000);
204
+ * tree configuration.
110
sysbus_init_mmio(sbd, &s->iomem);
205
+ */
111
}
206
+
112
207
+#include "qemu/osdep.h"
113
diff --git a/MAINTAINERS b/MAINTAINERS
208
+#include "qemu/log.h"
209
+#include "migration/vmstate.h"
210
+#include "hw/qdev-properties.h"
211
+#include "hw/misc/bcm2835_cprman.h"
212
+#include "hw/misc/bcm2835_cprman_internals.h"
213
+#include "trace.h"
214
+
215
+/* CPRMAN "top level" model */
216
+
217
+static uint64_t cprman_read(void *opaque, hwaddr offset,
218
+ unsigned size)
219
+{
220
+ BCM2835CprmanState *s = CPRMAN(opaque);
221
+ uint64_t r = 0;
222
+ size_t idx = offset / sizeof(uint32_t);
223
+
224
+ switch (idx) {
225
+ default:
226
+ r = s->regs[idx];
227
+ }
228
+
229
+ trace_bcm2835_cprman_read(offset, r);
230
+ return r;
231
+}
232
+
233
+static void cprman_write(void *opaque, hwaddr offset,
234
+ uint64_t value, unsigned size)
235
+{
236
+ BCM2835CprmanState *s = CPRMAN(opaque);
237
+ size_t idx = offset / sizeof(uint32_t);
238
+
239
+ if (FIELD_EX32(value, CPRMAN, PASSWORD) != CPRMAN_PASSWORD) {
240
+ trace_bcm2835_cprman_write_invalid_magic(offset, value);
241
+ return;
242
+ }
243
+
244
+ value &= ~R_CPRMAN_PASSWORD_MASK;
245
+
246
+ trace_bcm2835_cprman_write(offset, value);
247
+ s->regs[idx] = value;
248
+
249
+}
250
+
251
+static const MemoryRegionOps cprman_ops = {
252
+ .read = cprman_read,
253
+ .write = cprman_write,
254
+ .endianness = DEVICE_LITTLE_ENDIAN,
255
+ .valid = {
256
+ /*
257
+ * Although this hasn't been checked against real hardware, nor the
258
+ * information can be found in a datasheet, it seems reasonable because
259
+ * of the "PASSWORD" magic value found in every registers.
260
+ */
261
+ .min_access_size = 4,
262
+ .max_access_size = 4,
263
+ .unaligned = false,
264
+ },
265
+ .impl = {
266
+ .max_access_size = 4,
267
+ },
268
+};
269
+
270
+static void cprman_reset(DeviceState *dev)
271
+{
272
+ BCM2835CprmanState *s = CPRMAN(dev);
273
+
274
+ memset(s->regs, 0, sizeof(s->regs));
275
+
276
+ clock_update_hz(s->xosc, s->xosc_freq);
277
+}
278
+
279
+static void cprman_init(Object *obj)
280
+{
281
+ BCM2835CprmanState *s = CPRMAN(obj);
282
+
283
+ s->xosc = clock_new(obj, "xosc");
284
+
285
+ memory_region_init_io(&s->iomem, obj, &cprman_ops,
286
+ s, "bcm2835-cprman", 0x2000);
287
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
288
+}
289
+
290
+static const VMStateDescription cprman_vmstate = {
291
+ .name = TYPE_BCM2835_CPRMAN,
292
+ .version_id = 1,
293
+ .minimum_version_id = 1,
294
+ .fields = (VMStateField[]) {
295
+ VMSTATE_UINT32_ARRAY(regs, BCM2835CprmanState, CPRMAN_NUM_REGS),
296
+ VMSTATE_END_OF_LIST()
297
+ }
298
+};
299
+
300
+static Property cprman_properties[] = {
301
+ DEFINE_PROP_UINT32("xosc-freq-hz", BCM2835CprmanState, xosc_freq, 19200000),
302
+ DEFINE_PROP_END_OF_LIST()
303
+};
304
+
305
+static void cprman_class_init(ObjectClass *klass, void *data)
306
+{
307
+ DeviceClass *dc = DEVICE_CLASS(klass);
308
+
309
+ dc->reset = cprman_reset;
310
+ dc->vmsd = &cprman_vmstate;
311
+ device_class_set_props(dc, cprman_properties);
312
+}
313
+
314
+static const TypeInfo cprman_info = {
315
+ .name = TYPE_BCM2835_CPRMAN,
316
+ .parent = TYPE_SYS_BUS_DEVICE,
317
+ .instance_size = sizeof(BCM2835CprmanState),
318
+ .class_init = cprman_class_init,
319
+ .instance_init = cprman_init,
320
+};
321
+
322
+static void cprman_register_types(void)
323
+{
324
+ type_register_static(&cprman_info);
325
+}
326
+
327
+type_init(cprman_register_types);
328
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
114
index XXXXXXX..XXXXXXX 100644
329
index XXXXXXX..XXXXXXX 100644
115
--- a/MAINTAINERS
330
--- a/hw/misc/meson.build
116
+++ b/MAINTAINERS
331
+++ b/hw/misc/meson.build
117
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
332
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
118
L: qemu-arm@nongnu.org
333
'bcm2835_property.c',
119
S: Maintained
334
'bcm2835_rng.c',
120
F: hw/*/versatile*
335
'bcm2835_thermal.c',
121
+F: include/hw/i2c/arm_sbcon_i2c.h
336
+ 'bcm2835_cprman.c',
122
F: hw/misc/arm_sysctl.c
337
))
123
F: docs/system/arm/versatile.rst
338
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
124
339
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
340
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
341
index XXXXXXX..XXXXXXX 100644
342
--- a/hw/misc/trace-events
343
+++ b/hw/misc/trace-events
344
@@ -XXX,XX +XXX,XX @@ grlib_apb_pnp_read(uint64_t addr, uint32_t value) "APB PnP read addr:0x%03"PRIx6
345
# pca9552.c
346
pca955x_gpio_status(const char *description, const char *buf) "%s GPIOs 0-15 [%s]"
347
pca955x_gpio_change(const char *description, unsigned id, unsigned prev_state, unsigned current_state) "%s GPIO id:%u status: %u -> %u"
348
+
349
+# bcm2835_cprman.c
350
+bcm2835_cprman_read(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64
351
+bcm2835_cprman_write(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64
352
+bcm2835_cprman_write_invalid_magic(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64
125
--
353
--
126
2.20.1
354
2.20.1
127
355
128
356
diff view generated by jsdifflib
1
Convert the Neon VZIP and VUZP insns in the 2-reg-misc group to
1
From: Luc Michel <luc@lmichel.fr>
2
decodetree.
2
3
3
There are 5 PLLs in the CPRMAN, namely PLL A, C, D, H and B. All of them
4
take the xosc clock as input and produce a new clock.
5
6
This commit adds a skeleton implementation for the PLLs as sub-devices
7
of the CPRMAN. The PLLs are instantiated and connected internally to the
8
main oscillator.
9
10
Each PLL has 6 registers : CM, A2W_CTRL, A2W_ANA[0,1,2,3], A2W_FRAC. A
11
write to any of them triggers a call to the (not yet implemented)
12
pll_update function.
13
14
If the main oscillator changes frequency, an update is also triggered.
15
16
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Signed-off-by: Luc Michel <luc@lmichel.fr>
19
Tested-by: Guenter Roeck <linux@roeck-us.net>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200616170844.13318-4-peter.maydell@linaro.org
7
---
21
---
8
target/arm/neon-dp.decode | 3 ++
22
include/hw/misc/bcm2835_cprman.h | 29 +++++
9
target/arm/translate-neon.inc.c | 74 ++++++++++++++++++++++++++
23
include/hw/misc/bcm2835_cprman_internals.h | 144 +++++++++++++++++++++
10
target/arm/translate.c | 92 +--------------------------------
24
hw/misc/bcm2835_cprman.c | 108 ++++++++++++++++
11
3 files changed, 79 insertions(+), 90 deletions(-)
25
3 files changed, 281 insertions(+)
12
26
13
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
27
diff --git a/include/hw/misc/bcm2835_cprman.h b/include/hw/misc/bcm2835_cprman.h
14
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/neon-dp.decode
29
--- a/include/hw/misc/bcm2835_cprman.h
16
+++ b/target/arm/neon-dp.decode
30
+++ b/include/hw/misc/bcm2835_cprman.h
17
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
31
@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(BCM2835CprmanState, CPRMAN,
18
32
19
VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc
33
#define CPRMAN_NUM_REGS (0x2000 / sizeof(uint32_t))
20
VPADAL_U 1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc
34
21
+
35
+typedef enum CprmanPll {
22
+ VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc
36
+ CPRMAN_PLLA = 0,
23
+ VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc
37
+ CPRMAN_PLLC,
24
]
38
+ CPRMAN_PLLD,
25
39
+ CPRMAN_PLLH,
26
# Subgroup for size != 0b11
40
+ CPRMAN_PLLB,
27
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
41
+
42
+ CPRMAN_NUM_PLL
43
+} CprmanPll;
44
+
45
+typedef struct CprmanPllState {
46
+ /*< private >*/
47
+ DeviceState parent_obj;
48
+
49
+ /*< public >*/
50
+ CprmanPll id;
51
+
52
+ uint32_t *reg_cm;
53
+ uint32_t *reg_a2w_ctrl;
54
+ uint32_t *reg_a2w_ana; /* ANA[0] .. ANA[3] */
55
+ uint32_t prediv_mask; /* prediv bit in ana[1] */
56
+ uint32_t *reg_a2w_frac;
57
+
58
+ Clock *xosc_in;
59
+ Clock *out;
60
+} CprmanPllState;
61
+
62
struct BCM2835CprmanState {
63
/*< private >*/
64
SysBusDevice parent_obj;
65
@@ -XXX,XX +XXX,XX @@ struct BCM2835CprmanState {
66
/*< public >*/
67
MemoryRegion iomem;
68
69
+ CprmanPllState plls[CPRMAN_NUM_PLL];
70
+
71
uint32_t regs[CPRMAN_NUM_REGS];
72
uint32_t xosc_freq;
73
74
diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/bcm2835_cprman_internals.h
28
index XXXXXXX..XXXXXXX 100644
75
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/translate-neon.inc.c
76
--- a/include/hw/misc/bcm2835_cprman_internals.h
30
+++ b/target/arm/translate-neon.inc.c
77
+++ b/include/hw/misc/bcm2835_cprman_internals.h
31
@@ -XXX,XX +XXX,XX @@ static bool trans_VPADAL_U(DisasContext *s, arg_2misc *a)
78
@@ -XXX,XX +XXX,XX @@
32
return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size],
79
#include "hw/registerfields.h"
33
accfn[a->size]);
80
#include "hw/misc/bcm2835_cprman.h"
81
82
+#define TYPE_CPRMAN_PLL "bcm2835-cprman-pll"
83
+
84
+DECLARE_INSTANCE_CHECKER(CprmanPllState, CPRMAN_PLL,
85
+ TYPE_CPRMAN_PLL)
86
+
87
/* Register map */
88
89
+/* PLLs */
90
+REG32(CM_PLLA, 0x104)
91
+ FIELD(CM_PLLA, LOADDSI0, 0, 1)
92
+ FIELD(CM_PLLA, HOLDDSI0, 1, 1)
93
+ FIELD(CM_PLLA, LOADCCP2, 2, 1)
94
+ FIELD(CM_PLLA, HOLDCCP2, 3, 1)
95
+ FIELD(CM_PLLA, LOADCORE, 4, 1)
96
+ FIELD(CM_PLLA, HOLDCORE, 5, 1)
97
+ FIELD(CM_PLLA, LOADPER, 6, 1)
98
+ FIELD(CM_PLLA, HOLDPER, 7, 1)
99
+ FIELD(CM_PLLx, ANARST, 8, 1)
100
+REG32(CM_PLLC, 0x108)
101
+ FIELD(CM_PLLC, LOADCORE0, 0, 1)
102
+ FIELD(CM_PLLC, HOLDCORE0, 1, 1)
103
+ FIELD(CM_PLLC, LOADCORE1, 2, 1)
104
+ FIELD(CM_PLLC, HOLDCORE1, 3, 1)
105
+ FIELD(CM_PLLC, LOADCORE2, 4, 1)
106
+ FIELD(CM_PLLC, HOLDCORE2, 5, 1)
107
+ FIELD(CM_PLLC, LOADPER, 6, 1)
108
+ FIELD(CM_PLLC, HOLDPER, 7, 1)
109
+REG32(CM_PLLD, 0x10c)
110
+ FIELD(CM_PLLD, LOADDSI0, 0, 1)
111
+ FIELD(CM_PLLD, HOLDDSI0, 1, 1)
112
+ FIELD(CM_PLLD, LOADDSI1, 2, 1)
113
+ FIELD(CM_PLLD, HOLDDSI1, 3, 1)
114
+ FIELD(CM_PLLD, LOADCORE, 4, 1)
115
+ FIELD(CM_PLLD, HOLDCORE, 5, 1)
116
+ FIELD(CM_PLLD, LOADPER, 6, 1)
117
+ FIELD(CM_PLLD, HOLDPER, 7, 1)
118
+REG32(CM_PLLH, 0x110)
119
+ FIELD(CM_PLLH, LOADPIX, 0, 1)
120
+ FIELD(CM_PLLH, LOADAUX, 1, 1)
121
+ FIELD(CM_PLLH, LOADRCAL, 2, 1)
122
+REG32(CM_PLLB, 0x170)
123
+ FIELD(CM_PLLB, LOADARM, 0, 1)
124
+ FIELD(CM_PLLB, HOLDARM, 1, 1)
125
+
126
+REG32(A2W_PLLA_CTRL, 0x1100)
127
+ FIELD(A2W_PLLx_CTRL, NDIV, 0, 10)
128
+ FIELD(A2W_PLLx_CTRL, PDIV, 12, 3)
129
+ FIELD(A2W_PLLx_CTRL, PWRDN, 16, 1)
130
+ FIELD(A2W_PLLx_CTRL, PRST_DISABLE, 17, 1)
131
+REG32(A2W_PLLC_CTRL, 0x1120)
132
+REG32(A2W_PLLD_CTRL, 0x1140)
133
+REG32(A2W_PLLH_CTRL, 0x1160)
134
+REG32(A2W_PLLB_CTRL, 0x11e0)
135
+
136
+REG32(A2W_PLLA_ANA0, 0x1010)
137
+REG32(A2W_PLLA_ANA1, 0x1014)
138
+ FIELD(A2W_PLLx_ANA1, FB_PREDIV, 14, 1)
139
+REG32(A2W_PLLA_ANA2, 0x1018)
140
+REG32(A2W_PLLA_ANA3, 0x101c)
141
+
142
+REG32(A2W_PLLC_ANA0, 0x1030)
143
+REG32(A2W_PLLC_ANA1, 0x1034)
144
+REG32(A2W_PLLC_ANA2, 0x1038)
145
+REG32(A2W_PLLC_ANA3, 0x103c)
146
+
147
+REG32(A2W_PLLD_ANA0, 0x1050)
148
+REG32(A2W_PLLD_ANA1, 0x1054)
149
+REG32(A2W_PLLD_ANA2, 0x1058)
150
+REG32(A2W_PLLD_ANA3, 0x105c)
151
+
152
+REG32(A2W_PLLH_ANA0, 0x1070)
153
+REG32(A2W_PLLH_ANA1, 0x1074)
154
+ FIELD(A2W_PLLH_ANA1, FB_PREDIV, 11, 1)
155
+REG32(A2W_PLLH_ANA2, 0x1078)
156
+REG32(A2W_PLLH_ANA3, 0x107c)
157
+
158
+REG32(A2W_PLLB_ANA0, 0x10f0)
159
+REG32(A2W_PLLB_ANA1, 0x10f4)
160
+REG32(A2W_PLLB_ANA2, 0x10f8)
161
+REG32(A2W_PLLB_ANA3, 0x10fc)
162
+
163
+REG32(A2W_PLLA_FRAC, 0x1200)
164
+ FIELD(A2W_PLLx_FRAC, FRAC, 0, 20)
165
+REG32(A2W_PLLC_FRAC, 0x1220)
166
+REG32(A2W_PLLD_FRAC, 0x1240)
167
+REG32(A2W_PLLH_FRAC, 0x1260)
168
+REG32(A2W_PLLB_FRAC, 0x12e0)
169
+
170
/*
171
* This field is common to all registers. Each register write value must match
172
* the CPRMAN_PASSWORD magic value in its 8 MSB.
173
@@ -XXX,XX +XXX,XX @@
174
FIELD(CPRMAN, PASSWORD, 24, 8)
175
#define CPRMAN_PASSWORD 0x5a
176
177
+/* PLL init info */
178
+typedef struct PLLInitInfo {
179
+ const char *name;
180
+ size_t cm_offset;
181
+ size_t a2w_ctrl_offset;
182
+ size_t a2w_ana_offset;
183
+ uint32_t prediv_mask; /* Prediv bit in ana[1] */
184
+ size_t a2w_frac_offset;
185
+} PLLInitInfo;
186
+
187
+#define FILL_PLL_INIT_INFO(pll_) \
188
+ .cm_offset = R_CM_ ## pll_, \
189
+ .a2w_ctrl_offset = R_A2W_ ## pll_ ## _CTRL, \
190
+ .a2w_ana_offset = R_A2W_ ## pll_ ## _ANA0, \
191
+ .a2w_frac_offset = R_A2W_ ## pll_ ## _FRAC
192
+
193
+static const PLLInitInfo PLL_INIT_INFO[] = {
194
+ [CPRMAN_PLLA] = {
195
+ .name = "plla",
196
+ .prediv_mask = R_A2W_PLLx_ANA1_FB_PREDIV_MASK,
197
+ FILL_PLL_INIT_INFO(PLLA),
198
+ },
199
+ [CPRMAN_PLLC] = {
200
+ .name = "pllc",
201
+ .prediv_mask = R_A2W_PLLx_ANA1_FB_PREDIV_MASK,
202
+ FILL_PLL_INIT_INFO(PLLC),
203
+ },
204
+ [CPRMAN_PLLD] = {
205
+ .name = "plld",
206
+ .prediv_mask = R_A2W_PLLx_ANA1_FB_PREDIV_MASK,
207
+ FILL_PLL_INIT_INFO(PLLD),
208
+ },
209
+ [CPRMAN_PLLH] = {
210
+ .name = "pllh",
211
+ .prediv_mask = R_A2W_PLLH_ANA1_FB_PREDIV_MASK,
212
+ FILL_PLL_INIT_INFO(PLLH),
213
+ },
214
+ [CPRMAN_PLLB] = {
215
+ .name = "pllb",
216
+ .prediv_mask = R_A2W_PLLx_ANA1_FB_PREDIV_MASK,
217
+ FILL_PLL_INIT_INFO(PLLB),
218
+ },
219
+};
220
+
221
+#undef FILL_PLL_CHANNEL_INIT_INFO
222
+
223
+static inline void set_pll_init_info(BCM2835CprmanState *s,
224
+ CprmanPllState *pll,
225
+ CprmanPll id)
226
+{
227
+ pll->id = id;
228
+ pll->reg_cm = &s->regs[PLL_INIT_INFO[id].cm_offset];
229
+ pll->reg_a2w_ctrl = &s->regs[PLL_INIT_INFO[id].a2w_ctrl_offset];
230
+ pll->reg_a2w_ana = &s->regs[PLL_INIT_INFO[id].a2w_ana_offset];
231
+ pll->prediv_mask = PLL_INIT_INFO[id].prediv_mask;
232
+ pll->reg_a2w_frac = &s->regs[PLL_INIT_INFO[id].a2w_frac_offset];
233
+}
234
+
235
#endif
236
diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c
237
index XXXXXXX..XXXXXXX 100644
238
--- a/hw/misc/bcm2835_cprman.c
239
+++ b/hw/misc/bcm2835_cprman.c
240
@@ -XXX,XX +XXX,XX @@
241
#include "hw/misc/bcm2835_cprman_internals.h"
242
#include "trace.h"
243
244
+/* PLL */
245
+
246
+static void pll_update(CprmanPllState *pll)
247
+{
248
+ clock_update(pll->out, 0);
249
+}
250
+
251
+static void pll_xosc_update(void *opaque)
252
+{
253
+ pll_update(CPRMAN_PLL(opaque));
254
+}
255
+
256
+static void pll_init(Object *obj)
257
+{
258
+ CprmanPllState *s = CPRMAN_PLL(obj);
259
+
260
+ s->xosc_in = qdev_init_clock_in(DEVICE(s), "xosc-in", pll_xosc_update, s);
261
+ s->out = qdev_init_clock_out(DEVICE(s), "out");
262
+}
263
+
264
+static const VMStateDescription pll_vmstate = {
265
+ .name = TYPE_CPRMAN_PLL,
266
+ .version_id = 1,
267
+ .minimum_version_id = 1,
268
+ .fields = (VMStateField[]) {
269
+ VMSTATE_CLOCK(xosc_in, CprmanPllState),
270
+ VMSTATE_END_OF_LIST()
271
+ }
272
+};
273
+
274
+static void pll_class_init(ObjectClass *klass, void *data)
275
+{
276
+ DeviceClass *dc = DEVICE_CLASS(klass);
277
+
278
+ dc->vmsd = &pll_vmstate;
279
+}
280
+
281
+static const TypeInfo cprman_pll_info = {
282
+ .name = TYPE_CPRMAN_PLL,
283
+ .parent = TYPE_DEVICE,
284
+ .instance_size = sizeof(CprmanPllState),
285
+ .class_init = pll_class_init,
286
+ .instance_init = pll_init,
287
+};
288
+
289
+
290
/* CPRMAN "top level" model */
291
292
static uint64_t cprman_read(void *opaque, hwaddr offset,
293
@@ -XXX,XX +XXX,XX @@ static uint64_t cprman_read(void *opaque, hwaddr offset,
294
return r;
34
}
295
}
35
+
296
36
+typedef void ZipFn(TCGv_ptr, TCGv_ptr);
297
+#define CASE_PLL_REGS(pll_) \
37
+
298
+ case R_CM_ ## pll_: \
38
+static bool do_zip_uzp(DisasContext *s, arg_2misc *a,
299
+ case R_A2W_ ## pll_ ## _CTRL: \
39
+ ZipFn *fn)
300
+ case R_A2W_ ## pll_ ## _ANA0: \
40
+{
301
+ case R_A2W_ ## pll_ ## _ANA1: \
41
+ TCGv_ptr pd, pm;
302
+ case R_A2W_ ## pll_ ## _ANA2: \
42
+
303
+ case R_A2W_ ## pll_ ## _ANA3: \
43
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
304
+ case R_A2W_ ## pll_ ## _FRAC
44
+ return false;
305
+
306
static void cprman_write(void *opaque, hwaddr offset,
307
uint64_t value, unsigned size)
308
{
309
@@ -XXX,XX +XXX,XX @@ static void cprman_write(void *opaque, hwaddr offset,
310
trace_bcm2835_cprman_write(offset, value);
311
s->regs[idx] = value;
312
313
+ switch (idx) {
314
+ CASE_PLL_REGS(PLLA) :
315
+ pll_update(&s->plls[CPRMAN_PLLA]);
316
+ break;
317
+
318
+ CASE_PLL_REGS(PLLC) :
319
+ pll_update(&s->plls[CPRMAN_PLLC]);
320
+ break;
321
+
322
+ CASE_PLL_REGS(PLLD) :
323
+ pll_update(&s->plls[CPRMAN_PLLD]);
324
+ break;
325
+
326
+ CASE_PLL_REGS(PLLH) :
327
+ pll_update(&s->plls[CPRMAN_PLLH]);
328
+ break;
329
+
330
+ CASE_PLL_REGS(PLLB) :
331
+ pll_update(&s->plls[CPRMAN_PLLB]);
332
+ break;
45
+ }
333
+ }
46
+
334
}
47
+ /* UNDEF accesses to D16-D31 if they don't exist. */
335
48
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
336
+#undef CASE_PLL_REGS
49
+ ((a->vd | a->vm) & 0x10)) {
337
+
50
+ return false;
338
static const MemoryRegionOps cprman_ops = {
339
.read = cprman_read,
340
.write = cprman_write,
341
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps cprman_ops = {
342
static void cprman_reset(DeviceState *dev)
343
{
344
BCM2835CprmanState *s = CPRMAN(dev);
345
+ size_t i;
346
347
memset(s->regs, 0, sizeof(s->regs));
348
349
+ for (i = 0; i < CPRMAN_NUM_PLL; i++) {
350
+ device_cold_reset(DEVICE(&s->plls[i]));
51
+ }
351
+ }
52
+
352
+
53
+ if ((a->vd | a->vm) & a->q) {
353
clock_update_hz(s->xosc, s->xosc_freq);
54
+ return false;
354
}
355
356
static void cprman_init(Object *obj)
357
{
358
BCM2835CprmanState *s = CPRMAN(obj);
359
+ size_t i;
360
+
361
+ for (i = 0; i < CPRMAN_NUM_PLL; i++) {
362
+ object_initialize_child(obj, PLL_INIT_INFO[i].name,
363
+ &s->plls[i], TYPE_CPRMAN_PLL);
364
+ set_pll_init_info(s, &s->plls[i], i);
55
+ }
365
+ }
56
+
366
57
+ if (!fn) {
367
s->xosc = clock_new(obj, "xosc");
58
+ /* Bad size or size/q combination */
368
59
+ return false;
369
@@ -XXX,XX +XXX,XX @@ static void cprman_init(Object *obj)
370
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
371
}
372
373
+static void cprman_realize(DeviceState *dev, Error **errp)
374
+{
375
+ BCM2835CprmanState *s = CPRMAN(dev);
376
+ size_t i;
377
+
378
+ for (i = 0; i < CPRMAN_NUM_PLL; i++) {
379
+ CprmanPllState *pll = &s->plls[i];
380
+
381
+ clock_set_source(pll->xosc_in, s->xosc);
382
+
383
+ if (!qdev_realize(DEVICE(pll), NULL, errp)) {
384
+ return;
385
+ }
60
+ }
386
+ }
61
+
387
+}
62
+ if (!vfp_access_check(s)) {
388
+
63
+ return true;
389
static const VMStateDescription cprman_vmstate = {
64
+ }
390
.name = TYPE_BCM2835_CPRMAN,
65
+
391
.version_id = 1,
66
+ pd = vfp_reg_ptr(true, a->vd);
392
@@ -XXX,XX +XXX,XX @@ static void cprman_class_init(ObjectClass *klass, void *data)
67
+ pm = vfp_reg_ptr(true, a->vm);
393
{
68
+ fn(pd, pm);
394
DeviceClass *dc = DEVICE_CLASS(klass);
69
+ tcg_temp_free_ptr(pd);
395
70
+ tcg_temp_free_ptr(pm);
396
+ dc->realize = cprman_realize;
71
+ return true;
397
dc->reset = cprman_reset;
72
+}
398
dc->vmsd = &cprman_vmstate;
73
+
399
device_class_set_props(dc, cprman_properties);
74
+static bool trans_VUZP(DisasContext *s, arg_2misc *a)
400
@@ -XXX,XX +XXX,XX @@ static const TypeInfo cprman_info = {
75
+{
401
static void cprman_register_types(void)
76
+ static ZipFn * const fn[2][4] = {
402
{
77
+ {
403
type_register_static(&cprman_info);
78
+ gen_helper_neon_unzip8,
404
+ type_register_static(&cprman_pll_info);
79
+ gen_helper_neon_unzip16,
80
+ NULL,
81
+ NULL,
82
+ }, {
83
+ gen_helper_neon_qunzip8,
84
+ gen_helper_neon_qunzip16,
85
+ gen_helper_neon_qunzip32,
86
+ NULL,
87
+ }
88
+ };
89
+ return do_zip_uzp(s, a, fn[a->q][a->size]);
90
+}
91
+
92
+static bool trans_VZIP(DisasContext *s, arg_2misc *a)
93
+{
94
+ static ZipFn * const fn[2][4] = {
95
+ {
96
+ gen_helper_neon_zip8,
97
+ gen_helper_neon_zip16,
98
+ NULL,
99
+ NULL,
100
+ }, {
101
+ gen_helper_neon_qzip8,
102
+ gen_helper_neon_qzip16,
103
+ gen_helper_neon_qzip32,
104
+ NULL,
105
+ }
106
+ };
107
+ return do_zip_uzp(s, a, fn[a->q][a->size]);
108
+}
109
diff --git a/target/arm/translate.c b/target/arm/translate.c
110
index XXXXXXX..XXXXXXX 100644
111
--- a/target/arm/translate.c
112
+++ b/target/arm/translate.c
113
@@ -XXX,XX +XXX,XX @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc)
114
gen_rfe(s, pc, load_cpu_field(spsr));
115
}
405
}
116
406
117
-static int gen_neon_unzip(int rd, int rm, int size, int q)
407
type_init(cprman_register_types);
118
-{
119
- TCGv_ptr pd, pm;
120
-
121
- if (!q && size == 2) {
122
- return 1;
123
- }
124
- pd = vfp_reg_ptr(true, rd);
125
- pm = vfp_reg_ptr(true, rm);
126
- if (q) {
127
- switch (size) {
128
- case 0:
129
- gen_helper_neon_qunzip8(pd, pm);
130
- break;
131
- case 1:
132
- gen_helper_neon_qunzip16(pd, pm);
133
- break;
134
- case 2:
135
- gen_helper_neon_qunzip32(pd, pm);
136
- break;
137
- default:
138
- abort();
139
- }
140
- } else {
141
- switch (size) {
142
- case 0:
143
- gen_helper_neon_unzip8(pd, pm);
144
- break;
145
- case 1:
146
- gen_helper_neon_unzip16(pd, pm);
147
- break;
148
- default:
149
- abort();
150
- }
151
- }
152
- tcg_temp_free_ptr(pd);
153
- tcg_temp_free_ptr(pm);
154
- return 0;
155
-}
156
-
157
-static int gen_neon_zip(int rd, int rm, int size, int q)
158
-{
159
- TCGv_ptr pd, pm;
160
-
161
- if (!q && size == 2) {
162
- return 1;
163
- }
164
- pd = vfp_reg_ptr(true, rd);
165
- pm = vfp_reg_ptr(true, rm);
166
- if (q) {
167
- switch (size) {
168
- case 0:
169
- gen_helper_neon_qzip8(pd, pm);
170
- break;
171
- case 1:
172
- gen_helper_neon_qzip16(pd, pm);
173
- break;
174
- case 2:
175
- gen_helper_neon_qzip32(pd, pm);
176
- break;
177
- default:
178
- abort();
179
- }
180
- } else {
181
- switch (size) {
182
- case 0:
183
- gen_helper_neon_zip8(pd, pm);
184
- break;
185
- case 1:
186
- gen_helper_neon_zip16(pd, pm);
187
- break;
188
- default:
189
- abort();
190
- }
191
- }
192
- tcg_temp_free_ptr(pd);
193
- tcg_temp_free_ptr(pm);
194
- return 0;
195
-}
196
-
197
static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1)
198
{
199
TCGv_i32 rd, tmp;
200
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
201
case NEON_2RM_VREV64:
202
case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U:
203
case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U:
204
+ case NEON_2RM_VUZP:
205
+ case NEON_2RM_VZIP:
206
/* handled by decodetree */
207
return 1;
208
case NEON_2RM_VTRN:
209
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
210
goto elementwise;
211
}
212
break;
213
- case NEON_2RM_VUZP:
214
- if (gen_neon_unzip(rd, rm, size, q)) {
215
- return 1;
216
- }
217
- break;
218
- case NEON_2RM_VZIP:
219
- if (gen_neon_zip(rd, rm, size, q)) {
220
- return 1;
221
- }
222
- break;
223
case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN:
224
/* also VQMOVUN; op field and mnemonics don't line up */
225
if (rm & 1) {
226
--
408
--
227
2.20.1
409
2.20.1
228
410
229
411
diff view generated by jsdifflib
1
Convert the Neon 2-reg-misc VRINT insns to decodetree.
1
From: Luc Michel <luc@lmichel.fr>
2
Giving these insns their own do_vrint() function allows us
3
to change the rounding mode just once at the start and end
4
rather than doing it for every element in the vector.
5
2
3
The CPRMAN PLLs generate a clock based on a prescaler, a multiplier and
4
a divider. The prescaler doubles the parent (xosc) frequency, then the
5
multiplier/divider are applied. The multiplier has an integer and a
6
fractional part.
7
8
This commit also implements the CPRMAN CM_LOCK register. This register
9
reports which PLL is currently locked. We consider a PLL has being
10
locked as soon as it is enabled (on real hardware, there is a delay
11
after turning a PLL on, for it to stabilize).
12
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Signed-off-by: Luc Michel <luc@lmichel.fr>
16
Tested-by: Guenter Roeck <linux@roeck-us.net>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200616170844.13318-18-peter.maydell@linaro.org
9
---
18
---
10
target/arm/neon-dp.decode | 8 +++++
19
include/hw/misc/bcm2835_cprman_internals.h | 8 +++
11
target/arm/translate-neon.inc.c | 61 +++++++++++++++++++++++++++++++++
20
hw/misc/bcm2835_cprman.c | 64 +++++++++++++++++++++-
12
target/arm/translate.c | 31 +++--------------
21
2 files changed, 71 insertions(+), 1 deletion(-)
13
3 files changed, 74 insertions(+), 26 deletions(-)
14
22
15
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
23
diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/bcm2835_cprman_internals.h
16
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/neon-dp.decode
25
--- a/include/hw/misc/bcm2835_cprman_internals.h
18
+++ b/target/arm/neon-dp.decode
26
+++ b/include/hw/misc/bcm2835_cprman_internals.h
19
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
27
@@ -XXX,XX +XXX,XX @@ REG32(A2W_PLLD_FRAC, 0x1240)
20
SHA1SU1 1111 001 11 . 11 .. 10 .... 0 0111 0 . 0 .... @2misc_q1
28
REG32(A2W_PLLH_FRAC, 0x1260)
21
SHA256SU0 1111 001 11 . 11 .. 10 .... 0 0111 1 . 0 .... @2misc_q1
29
REG32(A2W_PLLB_FRAC, 0x12e0)
22
30
23
+ VRINTN 1111 001 11 . 11 .. 10 .... 0 1000 . . 0 .... @2misc
31
+/* misc registers */
24
VRINTX 1111 001 11 . 11 .. 10 .... 0 1001 . . 0 .... @2misc
32
+REG32(CM_LOCK, 0x114)
25
+ VRINTA 1111 001 11 . 11 .. 10 .... 0 1010 . . 0 .... @2misc
33
+ FIELD(CM_LOCK, FLOCKH, 12, 1)
26
+ VRINTZ 1111 001 11 . 11 .. 10 .... 0 1011 . . 0 .... @2misc
34
+ FIELD(CM_LOCK, FLOCKD, 11, 1)
27
35
+ FIELD(CM_LOCK, FLOCKC, 10, 1)
28
VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0
36
+ FIELD(CM_LOCK, FLOCKB, 9, 1)
37
+ FIELD(CM_LOCK, FLOCKA, 8, 1)
29
+
38
+
30
+ VRINTM 1111 001 11 . 11 .. 10 .... 0 1101 . . 0 .... @2misc
39
/*
40
* This field is common to all registers. Each register write value must match
41
* the CPRMAN_PASSWORD magic value in its 8 MSB.
42
diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/misc/bcm2835_cprman.c
45
+++ b/hw/misc/bcm2835_cprman.c
46
@@ -XXX,XX +XXX,XX @@
47
48
/* PLL */
49
50
+static bool pll_is_locked(const CprmanPllState *pll)
51
+{
52
+ return !FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PWRDN)
53
+ && !FIELD_EX32(*pll->reg_cm, CM_PLLx, ANARST);
54
+}
31
+
55
+
32
VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0
56
static void pll_update(CprmanPllState *pll)
33
57
{
34
+ VRINTP 1111 001 11 . 11 .. 10 .... 0 1111 . . 0 .... @2misc
58
- clock_update(pll->out, 0);
59
+ uint64_t freq, ndiv, fdiv, pdiv;
35
+
60
+
36
VRECPE 1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc
61
+ if (!pll_is_locked(pll)) {
37
VRSQRTE 1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc
62
+ clock_update(pll->out, 0);
38
VRECPE_F 1111 001 11 . 11 .. 11 .... 0 1010 . . 0 .... @2misc
63
+ return;
39
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/translate-neon.inc.c
42
+++ b/target/arm/translate-neon.inc.c
43
@@ -XXX,XX +XXX,XX @@ DO_FP_CMP0(VCGE0_F, gen_helper_neon_cge_f32, FWD)
44
DO_FP_CMP0(VCEQ0_F, gen_helper_neon_ceq_f32, FWD)
45
DO_FP_CMP0(VCLE0_F, gen_helper_neon_cge_f32, REV)
46
DO_FP_CMP0(VCLT0_F, gen_helper_neon_cgt_f32, REV)
47
+
48
+static bool do_vrint(DisasContext *s, arg_2misc *a, int rmode)
49
+{
50
+ /*
51
+ * Handle a VRINT* operation by iterating 32 bits at a time,
52
+ * with a specified rounding mode in operation.
53
+ */
54
+ int pass;
55
+ TCGv_ptr fpst;
56
+ TCGv_i32 tcg_rmode;
57
+
58
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
59
+ !arm_dc_feature(s, ARM_FEATURE_V8)) {
60
+ return false;
61
+ }
64
+ }
62
+
65
+
63
+ /* UNDEF accesses to D16-D31 if they don't exist. */
66
+ pdiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PDIV);
64
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
67
+
65
+ ((a->vd | a->vm) & 0x10)) {
68
+ if (!pdiv) {
66
+ return false;
69
+ clock_update(pll->out, 0);
70
+ return;
67
+ }
71
+ }
68
+
72
+
69
+ if (a->size != 2) {
73
+ ndiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, NDIV);
70
+ /* TODO: FP16 will be the size == 1 case */
74
+ fdiv = FIELD_EX32(*pll->reg_a2w_frac, A2W_PLLx_FRAC, FRAC);
71
+ return false;
75
+
76
+ if (pll->reg_a2w_ana[1] & pll->prediv_mask) {
77
+ /* The prescaler doubles the parent frequency */
78
+ ndiv *= 2;
79
+ fdiv *= 2;
72
+ }
80
+ }
73
+
81
+
74
+ if ((a->vd | a->vm) & a->q) {
82
+ /*
75
+ return false;
83
+ * We have a multiplier with an integer part (ndiv) and a fractional part
84
+ * (fdiv), and a divider (pdiv).
85
+ */
86
+ freq = clock_get_hz(pll->xosc_in) *
87
+ ((ndiv << R_A2W_PLLx_FRAC_FRAC_LENGTH) + fdiv);
88
+ freq /= pdiv;
89
+ freq >>= R_A2W_PLLx_FRAC_FRAC_LENGTH;
90
+
91
+ clock_update_hz(pll->out, freq);
92
}
93
94
static void pll_xosc_update(void *opaque)
95
@@ -XXX,XX +XXX,XX @@ static const TypeInfo cprman_pll_info = {
96
97
/* CPRMAN "top level" model */
98
99
+static uint32_t get_cm_lock(const BCM2835CprmanState *s)
100
+{
101
+ static const int CM_LOCK_MAPPING[CPRMAN_NUM_PLL] = {
102
+ [CPRMAN_PLLA] = R_CM_LOCK_FLOCKA_SHIFT,
103
+ [CPRMAN_PLLC] = R_CM_LOCK_FLOCKC_SHIFT,
104
+ [CPRMAN_PLLD] = R_CM_LOCK_FLOCKD_SHIFT,
105
+ [CPRMAN_PLLH] = R_CM_LOCK_FLOCKH_SHIFT,
106
+ [CPRMAN_PLLB] = R_CM_LOCK_FLOCKB_SHIFT,
107
+ };
108
+
109
+ uint32_t r = 0;
110
+ size_t i;
111
+
112
+ for (i = 0; i < CPRMAN_NUM_PLL; i++) {
113
+ r |= pll_is_locked(&s->plls[i]) << CM_LOCK_MAPPING[i];
76
+ }
114
+ }
77
+
115
+
78
+ if (!vfp_access_check(s)) {
116
+ return r;
79
+ return true;
80
+ }
81
+
82
+ fpst = get_fpstatus_ptr(1);
83
+ tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
84
+ gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env);
85
+ for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
86
+ TCGv_i32 tmp = neon_load_reg(a->vm, pass);
87
+ gen_helper_rints(tmp, tmp, fpst);
88
+ neon_store_reg(a->vd, pass, tmp);
89
+ }
90
+ gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env);
91
+ tcg_temp_free_i32(tcg_rmode);
92
+ tcg_temp_free_ptr(fpst);
93
+
94
+ return true;
95
+}
117
+}
96
+
118
+
97
+#define DO_VRINT(INSN, RMODE) \
119
static uint64_t cprman_read(void *opaque, hwaddr offset,
98
+ static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
120
unsigned size)
99
+ { \
121
{
100
+ return do_vrint(s, a, RMODE); \
122
@@ -XXX,XX +XXX,XX @@ static uint64_t cprman_read(void *opaque, hwaddr offset,
101
+ }
123
size_t idx = offset / sizeof(uint32_t);
124
125
switch (idx) {
126
+ case R_CM_LOCK:
127
+ r = get_cm_lock(s);
128
+ break;
102
+
129
+
103
+DO_VRINT(VRINTN, FPROUNDING_TIEEVEN)
130
default:
104
+DO_VRINT(VRINTA, FPROUNDING_TIEAWAY)
131
r = s->regs[idx];
105
+DO_VRINT(VRINTZ, FPROUNDING_ZERO)
132
}
106
+DO_VRINT(VRINTM, FPROUNDING_NEGINF)
107
+DO_VRINT(VRINTP, FPROUNDING_POSINF)
108
diff --git a/target/arm/translate.c b/target/arm/translate.c
109
index XXXXXXX..XXXXXXX 100644
110
--- a/target/arm/translate.c
111
+++ b/target/arm/translate.c
112
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
113
case NEON_2RM_VCEQ0_F:
114
case NEON_2RM_VCLE0_F:
115
case NEON_2RM_VCLT0_F:
116
+ case NEON_2RM_VRINTN:
117
+ case NEON_2RM_VRINTA:
118
+ case NEON_2RM_VRINTM:
119
+ case NEON_2RM_VRINTP:
120
+ case NEON_2RM_VRINTZ:
121
/* handled by decodetree */
122
return 1;
123
case NEON_2RM_VTRN:
124
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
125
}
126
neon_store_reg(rm, pass, tmp2);
127
break;
128
- case NEON_2RM_VRINTN:
129
- case NEON_2RM_VRINTA:
130
- case NEON_2RM_VRINTM:
131
- case NEON_2RM_VRINTP:
132
- case NEON_2RM_VRINTZ:
133
- {
134
- TCGv_i32 tcg_rmode;
135
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
136
- int rmode;
137
-
138
- if (op == NEON_2RM_VRINTZ) {
139
- rmode = FPROUNDING_ZERO;
140
- } else {
141
- rmode = fp_decode_rm[((op & 0x6) >> 1) ^ 1];
142
- }
143
-
144
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
145
- gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
146
- cpu_env);
147
- gen_helper_rints(tmp, tmp, fpstatus);
148
- gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
149
- cpu_env);
150
- tcg_temp_free_ptr(fpstatus);
151
- tcg_temp_free_i32(tcg_rmode);
152
- break;
153
- }
154
case NEON_2RM_VCVTAU:
155
case NEON_2RM_VCVTAS:
156
case NEON_2RM_VCVTNU:
157
--
133
--
158
2.20.1
134
2.20.1
159
135
160
136
diff view generated by jsdifflib
1
From: David CARLIER <devnexen@gmail.com>
1
From: Luc Michel <luc@lmichel.fr>
2
2
3
From 3025a0ce3fdf7d3559fc35a52c659f635f5c750c Mon Sep 17 00:00:00 2001
3
PLLs are composed of multiple channels. Each channel outputs one clock
4
From: David Carlier <devnexen@gmail.com>
4
signal. They are modeled as one device taking the PLL generated clock as
5
Date: Tue, 26 May 2020 21:35:27 +0100
5
input, and outputting a new clock.
6
Subject: [PATCH] util/oslib-posix : qemu_init_exec_dir implementation for Mac
6
7
7
A channel shares the CM register with its parent PLL, and has its own
8
Using dyld API to get the full path of the current process.
8
A2W_CTRL register. A write to the CM register will trigger an update of
9
9
the PLL and all its channels, while a write to an A2W_CTRL channel
10
Signed-off-by: David Carlier <devnexen@gmail.com>
10
register will update the required channel only.
11
Message-id: CA+XhMqxwC10XHVs4Z-JfE0-WLAU3ztDuU9QKVi31mjr59HWCxg@mail.gmail.com
11
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Signed-off-by: Luc Michel <luc@lmichel.fr>
15
Tested-by: Guenter Roeck <linux@roeck-us.net>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
17
---
15
util/oslib-posix.c | 15 +++++++++++++++
18
include/hw/misc/bcm2835_cprman.h | 44 ++++++
16
1 file changed, 15 insertions(+)
19
include/hw/misc/bcm2835_cprman_internals.h | 146 +++++++++++++++++++
17
20
hw/misc/bcm2835_cprman.c | 155 +++++++++++++++++++--
18
diff --git a/util/oslib-posix.c b/util/oslib-posix.c
21
3 files changed, 337 insertions(+), 8 deletions(-)
22
23
diff --git a/include/hw/misc/bcm2835_cprman.h b/include/hw/misc/bcm2835_cprman.h
19
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
20
--- a/util/oslib-posix.c
25
--- a/include/hw/misc/bcm2835_cprman.h
21
+++ b/util/oslib-posix.c
26
+++ b/include/hw/misc/bcm2835_cprman.h
27
@@ -XXX,XX +XXX,XX @@ typedef enum CprmanPll {
28
CPRMAN_NUM_PLL
29
} CprmanPll;
30
31
+typedef enum CprmanPllChannel {
32
+ CPRMAN_PLLA_CHANNEL_DSI0 = 0,
33
+ CPRMAN_PLLA_CHANNEL_CORE,
34
+ CPRMAN_PLLA_CHANNEL_PER,
35
+ CPRMAN_PLLA_CHANNEL_CCP2,
36
+
37
+ CPRMAN_PLLC_CHANNEL_CORE2,
38
+ CPRMAN_PLLC_CHANNEL_CORE1,
39
+ CPRMAN_PLLC_CHANNEL_PER,
40
+ CPRMAN_PLLC_CHANNEL_CORE0,
41
+
42
+ CPRMAN_PLLD_CHANNEL_DSI0,
43
+ CPRMAN_PLLD_CHANNEL_CORE,
44
+ CPRMAN_PLLD_CHANNEL_PER,
45
+ CPRMAN_PLLD_CHANNEL_DSI1,
46
+
47
+ CPRMAN_PLLH_CHANNEL_AUX,
48
+ CPRMAN_PLLH_CHANNEL_RCAL,
49
+ CPRMAN_PLLH_CHANNEL_PIX,
50
+
51
+ CPRMAN_PLLB_CHANNEL_ARM,
52
+
53
+ CPRMAN_NUM_PLL_CHANNEL,
54
+} CprmanPllChannel;
55
+
56
typedef struct CprmanPllState {
57
/*< private >*/
58
DeviceState parent_obj;
59
@@ -XXX,XX +XXX,XX @@ typedef struct CprmanPllState {
60
Clock *out;
61
} CprmanPllState;
62
63
+typedef struct CprmanPllChannelState {
64
+ /*< private >*/
65
+ DeviceState parent_obj;
66
+
67
+ /*< public >*/
68
+ CprmanPllChannel id;
69
+ CprmanPll parent;
70
+
71
+ uint32_t *reg_cm;
72
+ uint32_t hold_mask;
73
+ uint32_t load_mask;
74
+ uint32_t *reg_a2w_ctrl;
75
+ int fixed_divider;
76
+
77
+ Clock *pll_in;
78
+ Clock *out;
79
+} CprmanPllChannelState;
80
+
81
struct BCM2835CprmanState {
82
/*< private >*/
83
SysBusDevice parent_obj;
84
@@ -XXX,XX +XXX,XX @@ struct BCM2835CprmanState {
85
MemoryRegion iomem;
86
87
CprmanPllState plls[CPRMAN_NUM_PLL];
88
+ CprmanPllChannelState channels[CPRMAN_NUM_PLL_CHANNEL];
89
90
uint32_t regs[CPRMAN_NUM_REGS];
91
uint32_t xosc_freq;
92
diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/bcm2835_cprman_internals.h
93
index XXXXXXX..XXXXXXX 100644
94
--- a/include/hw/misc/bcm2835_cprman_internals.h
95
+++ b/include/hw/misc/bcm2835_cprman_internals.h
22
@@ -XXX,XX +XXX,XX @@
96
@@ -XXX,XX +XXX,XX @@
23
#include <lwp.h>
97
#include "hw/misc/bcm2835_cprman.h"
98
99
#define TYPE_CPRMAN_PLL "bcm2835-cprman-pll"
100
+#define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel"
101
102
DECLARE_INSTANCE_CHECKER(CprmanPllState, CPRMAN_PLL,
103
TYPE_CPRMAN_PLL)
104
+DECLARE_INSTANCE_CHECKER(CprmanPllChannelState, CPRMAN_PLL_CHANNEL,
105
+ TYPE_CPRMAN_PLL_CHANNEL)
106
107
/* Register map */
108
109
@@ -XXX,XX +XXX,XX @@ REG32(A2W_PLLD_FRAC, 0x1240)
110
REG32(A2W_PLLH_FRAC, 0x1260)
111
REG32(A2W_PLLB_FRAC, 0x12e0)
112
113
+/* PLL channels */
114
+REG32(A2W_PLLA_DSI0, 0x1300)
115
+ FIELD(A2W_PLLx_CHANNELy, DIV, 0, 8)
116
+ FIELD(A2W_PLLx_CHANNELy, DISABLE, 8, 1)
117
+REG32(A2W_PLLA_CORE, 0x1400)
118
+REG32(A2W_PLLA_PER, 0x1500)
119
+REG32(A2W_PLLA_CCP2, 0x1600)
120
+
121
+REG32(A2W_PLLC_CORE2, 0x1320)
122
+REG32(A2W_PLLC_CORE1, 0x1420)
123
+REG32(A2W_PLLC_PER, 0x1520)
124
+REG32(A2W_PLLC_CORE0, 0x1620)
125
+
126
+REG32(A2W_PLLD_DSI0, 0x1340)
127
+REG32(A2W_PLLD_CORE, 0x1440)
128
+REG32(A2W_PLLD_PER, 0x1540)
129
+REG32(A2W_PLLD_DSI1, 0x1640)
130
+
131
+REG32(A2W_PLLH_AUX, 0x1360)
132
+REG32(A2W_PLLH_RCAL, 0x1460)
133
+REG32(A2W_PLLH_PIX, 0x1560)
134
+REG32(A2W_PLLH_STS, 0x1660)
135
+
136
+REG32(A2W_PLLB_ARM, 0x13e0)
137
+
138
/* misc registers */
139
REG32(CM_LOCK, 0x114)
140
FIELD(CM_LOCK, FLOCKH, 12, 1)
141
@@ -XXX,XX +XXX,XX @@ static inline void set_pll_init_info(BCM2835CprmanState *s,
142
pll->reg_a2w_frac = &s->regs[PLL_INIT_INFO[id].a2w_frac_offset];
143
}
144
145
+
146
+/* PLL channel init info */
147
+typedef struct PLLChannelInitInfo {
148
+ const char *name;
149
+ CprmanPll parent;
150
+ size_t cm_offset;
151
+ uint32_t cm_hold_mask;
152
+ uint32_t cm_load_mask;
153
+ size_t a2w_ctrl_offset;
154
+ unsigned int fixed_divider;
155
+} PLLChannelInitInfo;
156
+
157
+#define FILL_PLL_CHANNEL_INIT_INFO_common(pll_, channel_) \
158
+ .parent = CPRMAN_ ## pll_, \
159
+ .cm_offset = R_CM_ ## pll_, \
160
+ .cm_load_mask = R_CM_ ## pll_ ## _ ## LOAD ## channel_ ## _MASK, \
161
+ .a2w_ctrl_offset = R_A2W_ ## pll_ ## _ ## channel_
162
+
163
+#define FILL_PLL_CHANNEL_INIT_INFO(pll_, channel_) \
164
+ FILL_PLL_CHANNEL_INIT_INFO_common(pll_, channel_), \
165
+ .cm_hold_mask = R_CM_ ## pll_ ## _ ## HOLD ## channel_ ## _MASK, \
166
+ .fixed_divider = 1
167
+
168
+#define FILL_PLL_CHANNEL_INIT_INFO_nohold(pll_, channel_) \
169
+ FILL_PLL_CHANNEL_INIT_INFO_common(pll_, channel_), \
170
+ .cm_hold_mask = 0
171
+
172
+static PLLChannelInitInfo PLL_CHANNEL_INIT_INFO[] = {
173
+ [CPRMAN_PLLA_CHANNEL_DSI0] = {
174
+ .name = "plla-dsi0",
175
+ FILL_PLL_CHANNEL_INIT_INFO(PLLA, DSI0),
176
+ },
177
+ [CPRMAN_PLLA_CHANNEL_CORE] = {
178
+ .name = "plla-core",
179
+ FILL_PLL_CHANNEL_INIT_INFO(PLLA, CORE),
180
+ },
181
+ [CPRMAN_PLLA_CHANNEL_PER] = {
182
+ .name = "plla-per",
183
+ FILL_PLL_CHANNEL_INIT_INFO(PLLA, PER),
184
+ },
185
+ [CPRMAN_PLLA_CHANNEL_CCP2] = {
186
+ .name = "plla-ccp2",
187
+ FILL_PLL_CHANNEL_INIT_INFO(PLLA, CCP2),
188
+ },
189
+
190
+ [CPRMAN_PLLC_CHANNEL_CORE2] = {
191
+ .name = "pllc-core2",
192
+ FILL_PLL_CHANNEL_INIT_INFO(PLLC, CORE2),
193
+ },
194
+ [CPRMAN_PLLC_CHANNEL_CORE1] = {
195
+ .name = "pllc-core1",
196
+ FILL_PLL_CHANNEL_INIT_INFO(PLLC, CORE1),
197
+ },
198
+ [CPRMAN_PLLC_CHANNEL_PER] = {
199
+ .name = "pllc-per",
200
+ FILL_PLL_CHANNEL_INIT_INFO(PLLC, PER),
201
+ },
202
+ [CPRMAN_PLLC_CHANNEL_CORE0] = {
203
+ .name = "pllc-core0",
204
+ FILL_PLL_CHANNEL_INIT_INFO(PLLC, CORE0),
205
+ },
206
+
207
+ [CPRMAN_PLLD_CHANNEL_DSI0] = {
208
+ .name = "plld-dsi0",
209
+ FILL_PLL_CHANNEL_INIT_INFO(PLLD, DSI0),
210
+ },
211
+ [CPRMAN_PLLD_CHANNEL_CORE] = {
212
+ .name = "plld-core",
213
+ FILL_PLL_CHANNEL_INIT_INFO(PLLD, CORE),
214
+ },
215
+ [CPRMAN_PLLD_CHANNEL_PER] = {
216
+ .name = "plld-per",
217
+ FILL_PLL_CHANNEL_INIT_INFO(PLLD, PER),
218
+ },
219
+ [CPRMAN_PLLD_CHANNEL_DSI1] = {
220
+ .name = "plld-dsi1",
221
+ FILL_PLL_CHANNEL_INIT_INFO(PLLD, DSI1),
222
+ },
223
+
224
+ [CPRMAN_PLLH_CHANNEL_AUX] = {
225
+ .name = "pllh-aux",
226
+ .fixed_divider = 1,
227
+ FILL_PLL_CHANNEL_INIT_INFO_nohold(PLLH, AUX),
228
+ },
229
+ [CPRMAN_PLLH_CHANNEL_RCAL] = {
230
+ .name = "pllh-rcal",
231
+ .fixed_divider = 10,
232
+ FILL_PLL_CHANNEL_INIT_INFO_nohold(PLLH, RCAL),
233
+ },
234
+ [CPRMAN_PLLH_CHANNEL_PIX] = {
235
+ .name = "pllh-pix",
236
+ .fixed_divider = 10,
237
+ FILL_PLL_CHANNEL_INIT_INFO_nohold(PLLH, PIX),
238
+ },
239
+
240
+ [CPRMAN_PLLB_CHANNEL_ARM] = {
241
+ .name = "pllb-arm",
242
+ FILL_PLL_CHANNEL_INIT_INFO(PLLB, ARM),
243
+ },
244
+};
245
+
246
+#undef FILL_PLL_CHANNEL_INIT_INFO_nohold
247
+#undef FILL_PLL_CHANNEL_INIT_INFO
248
+#undef FILL_PLL_CHANNEL_INIT_INFO_common
249
+
250
+static inline void set_pll_channel_init_info(BCM2835CprmanState *s,
251
+ CprmanPllChannelState *channel,
252
+ CprmanPllChannel id)
253
+{
254
+ channel->id = id;
255
+ channel->parent = PLL_CHANNEL_INIT_INFO[id].parent;
256
+ channel->reg_cm = &s->regs[PLL_CHANNEL_INIT_INFO[id].cm_offset];
257
+ channel->hold_mask = PLL_CHANNEL_INIT_INFO[id].cm_hold_mask;
258
+ channel->load_mask = PLL_CHANNEL_INIT_INFO[id].cm_load_mask;
259
+ channel->reg_a2w_ctrl = &s->regs[PLL_CHANNEL_INIT_INFO[id].a2w_ctrl_offset];
260
+ channel->fixed_divider = PLL_CHANNEL_INIT_INFO[id].fixed_divider;
261
+}
262
+
24
#endif
263
#endif
25
264
diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c
26
+#ifdef __APPLE__
265
index XXXXXXX..XXXXXXX 100644
27
+#include <mach-o/dyld.h>
266
--- a/hw/misc/bcm2835_cprman.c
28
+#endif
267
+++ b/hw/misc/bcm2835_cprman.c
29
+
268
@@ -XXX,XX +XXX,XX @@ static const TypeInfo cprman_pll_info = {
30
#include "qemu/mmap-alloc.h"
269
};
31
270
32
#ifdef CONFIG_DEBUG_STACK_USAGE
271
33
@@ -XXX,XX +XXX,XX @@ void qemu_init_exec_dir(const char *argv0)
272
+/* PLL channel */
34
p = buf;
273
+
274
+static void pll_channel_update(CprmanPllChannelState *channel)
275
+{
276
+ clock_update(channel->out, 0);
277
+}
278
+
279
+/* Update a PLL and all its channels */
280
+static void pll_update_all_channels(BCM2835CprmanState *s,
281
+ CprmanPllState *pll)
282
+{
283
+ size_t i;
284
+
285
+ pll_update(pll);
286
+
287
+ for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
288
+ CprmanPllChannelState *channel = &s->channels[i];
289
+ if (channel->parent == pll->id) {
290
+ pll_channel_update(channel);
291
+ }
292
+ }
293
+}
294
+
295
+static void pll_channel_pll_in_update(void *opaque)
296
+{
297
+ pll_channel_update(CPRMAN_PLL_CHANNEL(opaque));
298
+}
299
+
300
+static void pll_channel_init(Object *obj)
301
+{
302
+ CprmanPllChannelState *s = CPRMAN_PLL_CHANNEL(obj);
303
+
304
+ s->pll_in = qdev_init_clock_in(DEVICE(s), "pll-in",
305
+ pll_channel_pll_in_update, s);
306
+ s->out = qdev_init_clock_out(DEVICE(s), "out");
307
+}
308
+
309
+static const VMStateDescription pll_channel_vmstate = {
310
+ .name = TYPE_CPRMAN_PLL_CHANNEL,
311
+ .version_id = 1,
312
+ .minimum_version_id = 1,
313
+ .fields = (VMStateField[]) {
314
+ VMSTATE_CLOCK(pll_in, CprmanPllChannelState),
315
+ VMSTATE_END_OF_LIST()
316
+ }
317
+};
318
+
319
+static void pll_channel_class_init(ObjectClass *klass, void *data)
320
+{
321
+ DeviceClass *dc = DEVICE_CLASS(klass);
322
+
323
+ dc->vmsd = &pll_channel_vmstate;
324
+}
325
+
326
+static const TypeInfo cprman_pll_channel_info = {
327
+ .name = TYPE_CPRMAN_PLL_CHANNEL,
328
+ .parent = TYPE_DEVICE,
329
+ .instance_size = sizeof(CprmanPllChannelState),
330
+ .class_init = pll_channel_class_init,
331
+ .instance_init = pll_channel_init,
332
+};
333
+
334
+
335
/* CPRMAN "top level" model */
336
337
static uint32_t get_cm_lock(const BCM2835CprmanState *s)
338
@@ -XXX,XX +XXX,XX @@ static uint64_t cprman_read(void *opaque, hwaddr offset,
339
return r;
340
}
341
342
-#define CASE_PLL_REGS(pll_) \
343
- case R_CM_ ## pll_: \
344
+static inline void update_pll_and_channels_from_cm(BCM2835CprmanState *s,
345
+ size_t idx)
346
+{
347
+ size_t i;
348
+
349
+ for (i = 0; i < CPRMAN_NUM_PLL; i++) {
350
+ if (PLL_INIT_INFO[i].cm_offset == idx) {
351
+ pll_update_all_channels(s, &s->plls[i]);
352
+ return;
353
+ }
354
+ }
355
+}
356
+
357
+static inline void update_channel_from_a2w(BCM2835CprmanState *s, size_t idx)
358
+{
359
+ size_t i;
360
+
361
+ for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
362
+ if (PLL_CHANNEL_INIT_INFO[i].a2w_ctrl_offset == idx) {
363
+ pll_channel_update(&s->channels[i]);
364
+ return;
365
+ }
366
+ }
367
+}
368
+
369
+#define CASE_PLL_A2W_REGS(pll_) \
370
case R_A2W_ ## pll_ ## _CTRL: \
371
case R_A2W_ ## pll_ ## _ANA0: \
372
case R_A2W_ ## pll_ ## _ANA1: \
373
@@ -XXX,XX +XXX,XX @@ static void cprman_write(void *opaque, hwaddr offset,
374
s->regs[idx] = value;
375
376
switch (idx) {
377
- CASE_PLL_REGS(PLLA) :
378
+ case R_CM_PLLA ... R_CM_PLLH:
379
+ case R_CM_PLLB:
380
+ /*
381
+ * A given CM_PLLx register is shared by both the PLL and the channels
382
+ * of this PLL.
383
+ */
384
+ update_pll_and_channels_from_cm(s, idx);
385
+ break;
386
+
387
+ CASE_PLL_A2W_REGS(PLLA) :
388
pll_update(&s->plls[CPRMAN_PLLA]);
389
break;
390
391
- CASE_PLL_REGS(PLLC) :
392
+ CASE_PLL_A2W_REGS(PLLC) :
393
pll_update(&s->plls[CPRMAN_PLLC]);
394
break;
395
396
- CASE_PLL_REGS(PLLD) :
397
+ CASE_PLL_A2W_REGS(PLLD) :
398
pll_update(&s->plls[CPRMAN_PLLD]);
399
break;
400
401
- CASE_PLL_REGS(PLLH) :
402
+ CASE_PLL_A2W_REGS(PLLH) :
403
pll_update(&s->plls[CPRMAN_PLLH]);
404
break;
405
406
- CASE_PLL_REGS(PLLB) :
407
+ CASE_PLL_A2W_REGS(PLLB) :
408
pll_update(&s->plls[CPRMAN_PLLB]);
409
break;
410
+
411
+ case R_A2W_PLLA_DSI0:
412
+ case R_A2W_PLLA_CORE:
413
+ case R_A2W_PLLA_PER:
414
+ case R_A2W_PLLA_CCP2:
415
+ case R_A2W_PLLC_CORE2:
416
+ case R_A2W_PLLC_CORE1:
417
+ case R_A2W_PLLC_PER:
418
+ case R_A2W_PLLC_CORE0:
419
+ case R_A2W_PLLD_DSI0:
420
+ case R_A2W_PLLD_CORE:
421
+ case R_A2W_PLLD_PER:
422
+ case R_A2W_PLLD_DSI1:
423
+ case R_A2W_PLLH_AUX:
424
+ case R_A2W_PLLH_RCAL:
425
+ case R_A2W_PLLH_PIX:
426
+ case R_A2W_PLLB_ARM:
427
+ update_channel_from_a2w(s, idx);
428
+ break;
429
}
430
}
431
432
-#undef CASE_PLL_REGS
433
+#undef CASE_PLL_A2W_REGS
434
435
static const MemoryRegionOps cprman_ops = {
436
.read = cprman_read,
437
@@ -XXX,XX +XXX,XX @@ static void cprman_reset(DeviceState *dev)
438
device_cold_reset(DEVICE(&s->plls[i]));
439
}
440
441
+ for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
442
+ device_cold_reset(DEVICE(&s->channels[i]));
443
+ }
444
+
445
clock_update_hz(s->xosc, s->xosc_freq);
446
}
447
448
@@ -XXX,XX +XXX,XX @@ static void cprman_init(Object *obj)
449
set_pll_init_info(s, &s->plls[i], i);
450
}
451
452
+ for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
453
+ object_initialize_child(obj, PLL_CHANNEL_INIT_INFO[i].name,
454
+ &s->channels[i],
455
+ TYPE_CPRMAN_PLL_CHANNEL);
456
+ set_pll_channel_init_info(s, &s->channels[i], i);
457
+ }
458
+
459
s->xosc = clock_new(obj, "xosc");
460
461
memory_region_init_io(&s->iomem, obj, &cprman_ops,
462
@@ -XXX,XX +XXX,XX @@ static void cprman_realize(DeviceState *dev, Error **errp)
463
return;
35
}
464
}
36
}
465
}
37
+#elif defined(__APPLE__)
466
+
38
+ {
467
+ for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
39
+ char fpath[PATH_MAX];
468
+ CprmanPllChannelState *channel = &s->channels[i];
40
+ uint32_t len = sizeof(fpath);
469
+ CprmanPll parent = PLL_CHANNEL_INIT_INFO[i].parent;
41
+ if (_NSGetExecutablePath(fpath, &len) == 0) {
470
+ Clock *parent_clk = s->plls[parent].out;
42
+ p = realpath(fpath, buf);
471
+
43
+ if (!p) {
472
+ clock_set_source(channel->pll_in, parent_clk);
44
+ return;
473
+
45
+ }
474
+ if (!qdev_realize(DEVICE(channel), NULL, errp)) {
475
+ return;
46
+ }
476
+ }
47
+ }
477
+ }
48
#endif
478
}
49
/* If we don't have any way of figuring out the actual executable
479
50
location then try argv[0]. */
480
static const VMStateDescription cprman_vmstate = {
481
@@ -XXX,XX +XXX,XX @@ static void cprman_register_types(void)
482
{
483
type_register_static(&cprman_info);
484
type_register_static(&cprman_pll_info);
485
+ type_register_static(&cprman_pll_channel_info);
486
}
487
488
type_init(cprman_register_types);
51
--
489
--
52
2.20.1
490
2.20.1
53
491
54
492
diff view generated by jsdifflib
1
Convert the Neon VTRN insn to decodetree. This is the last insn in the
1
From: Luc Michel <luc@lmichel.fr>
2
Neon data-processing group, so we can remove all the now-unused old
3
decoder framework.
4
2
5
It's possible that there's a more efficient implementation of
3
A PLL channel is able to further divide the generated PLL frequency.
6
VTRN, but for this conversion we just copy the existing approach.
4
The divider is given in the CTRL_A2W register. Some channels have an
5
additional fixed divider which is always applied to the signal.
7
6
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Luc Michel <luc@lmichel.fr>
10
Tested-by: Guenter Roeck <linux@roeck-us.net>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200616170844.13318-21-peter.maydell@linaro.org
11
---
12
---
12
target/arm/neon-dp.decode | 2 +-
13
hw/misc/bcm2835_cprman.c | 33 ++++++++++++++++++++++++++++++++-
13
target/arm/translate-neon.inc.c | 90 ++++++++
14
1 file changed, 32 insertions(+), 1 deletion(-)
14
target/arm/translate.c | 363 +-------------------------------
15
3 files changed, 93 insertions(+), 362 deletions(-)
16
15
17
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
16
diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c
18
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/neon-dp.decode
18
--- a/hw/misc/bcm2835_cprman.c
20
+++ b/target/arm/neon-dp.decode
19
+++ b/hw/misc/bcm2835_cprman.c
21
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
20
@@ -XXX,XX +XXX,XX @@ static const TypeInfo cprman_pll_info = {
22
VNEG_F 1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc
21
23
22
/* PLL channel */
24
VSWP 1111 001 11 . 11 .. 10 .... 0 0000 . . 0 .... @2misc
23
25
-
24
+static bool pll_channel_is_enabled(CprmanPllChannelState *channel)
26
+ VTRN 1111 001 11 . 11 .. 10 .... 0 0001 . . 0 .... @2misc
27
VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc
28
VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc
29
30
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/translate-neon.inc.c
33
+++ b/target/arm/translate-neon.inc.c
34
@@ -XXX,XX +XXX,XX @@ static bool trans_VSWP(DisasContext *s, arg_2misc *a)
35
36
return true;
37
}
38
+static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1)
39
+{
25
+{
40
+ TCGv_i32 rd, tmp;
26
+ /*
41
+
27
+ * XXX I'm not sure of the purpose of the LOAD field. The Linux driver does
42
+ rd = tcg_temp_new_i32();
28
+ * not set it when enabling the channel, but does clear it when disabling
43
+ tmp = tcg_temp_new_i32();
29
+ * it.
44
+
30
+ */
45
+ tcg_gen_shli_i32(rd, t0, 8);
31
+ return !FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DISABLE)
46
+ tcg_gen_andi_i32(rd, rd, 0xff00ff00);
32
+ && !(*channel->reg_cm & channel->hold_mask);
47
+ tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
48
+ tcg_gen_or_i32(rd, rd, tmp);
49
+
50
+ tcg_gen_shri_i32(t1, t1, 8);
51
+ tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
52
+ tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
53
+ tcg_gen_or_i32(t1, t1, tmp);
54
+ tcg_gen_mov_i32(t0, rd);
55
+
56
+ tcg_temp_free_i32(tmp);
57
+ tcg_temp_free_i32(rd);
58
+}
33
+}
59
+
34
+
60
+static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
35
static void pll_channel_update(CprmanPllChannelState *channel)
61
+{
36
{
62
+ TCGv_i32 rd, tmp;
37
- clock_update(channel->out, 0);
38
+ uint64_t freq, div;
63
+
39
+
64
+ rd = tcg_temp_new_i32();
40
+ if (!pll_channel_is_enabled(channel)) {
65
+ tmp = tcg_temp_new_i32();
41
+ clock_update(channel->out, 0);
66
+
42
+ return;
67
+ tcg_gen_shli_i32(rd, t0, 16);
68
+ tcg_gen_andi_i32(tmp, t1, 0xffff);
69
+ tcg_gen_or_i32(rd, rd, tmp);
70
+ tcg_gen_shri_i32(t1, t1, 16);
71
+ tcg_gen_andi_i32(tmp, t0, 0xffff0000);
72
+ tcg_gen_or_i32(t1, t1, tmp);
73
+ tcg_gen_mov_i32(t0, rd);
74
+
75
+ tcg_temp_free_i32(tmp);
76
+ tcg_temp_free_i32(rd);
77
+}
78
+
79
+static bool trans_VTRN(DisasContext *s, arg_2misc *a)
80
+{
81
+ TCGv_i32 tmp, tmp2;
82
+ int pass;
83
+
84
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
85
+ return false;
86
+ }
43
+ }
87
+
44
+
88
+ /* UNDEF accesses to D16-D31 if they don't exist. */
45
+ div = FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DIV);
89
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
46
+
90
+ ((a->vd | a->vm) & 0x10)) {
47
+ if (!div) {
91
+ return false;
48
+ /*
49
+ * It seems that when the divider value is 0, it is considered as
50
+ * being maximum by the hardware (see the Linux driver).
51
+ */
52
+ div = R_A2W_PLLx_CHANNELy_DIV_MASK;
92
+ }
53
+ }
93
+
54
+
94
+ if ((a->vd | a->vm) & a->q) {
55
+ /* Some channels have an additional fixed divider */
95
+ return false;
56
+ freq = clock_get_hz(channel->pll_in) / (div * channel->fixed_divider);
96
+ }
97
+
57
+
98
+ if (a->size == 3) {
58
+ clock_update_hz(channel->out, freq);
99
+ return false;
100
+ }
101
+
102
+ if (!vfp_access_check(s)) {
103
+ return true;
104
+ }
105
+
106
+ if (a->size == 2) {
107
+ for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) {
108
+ tmp = neon_load_reg(a->vm, pass);
109
+ tmp2 = neon_load_reg(a->vd, pass + 1);
110
+ neon_store_reg(a->vm, pass, tmp2);
111
+ neon_store_reg(a->vd, pass + 1, tmp);
112
+ }
113
+ } else {
114
+ for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
115
+ tmp = neon_load_reg(a->vm, pass);
116
+ tmp2 = neon_load_reg(a->vd, pass);
117
+ if (a->size == 0) {
118
+ gen_neon_trn_u8(tmp, tmp2);
119
+ } else {
120
+ gen_neon_trn_u16(tmp, tmp2);
121
+ }
122
+ neon_store_reg(a->vm, pass, tmp2);
123
+ neon_store_reg(a->vd, pass, tmp);
124
+ }
125
+ }
126
+ return true;
127
+}
128
diff --git a/target/arm/translate.c b/target/arm/translate.c
129
index XXXXXXX..XXXXXXX 100644
130
--- a/target/arm/translate.c
131
+++ b/target/arm/translate.c
132
@@ -XXX,XX +XXX,XX @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc)
133
gen_rfe(s, pc, load_cpu_field(spsr));
134
}
59
}
135
60
136
-static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1)
61
/* Update a PLL and all its channels */
137
-{
138
- TCGv_i32 rd, tmp;
139
-
140
- rd = tcg_temp_new_i32();
141
- tmp = tcg_temp_new_i32();
142
-
143
- tcg_gen_shli_i32(rd, t0, 8);
144
- tcg_gen_andi_i32(rd, rd, 0xff00ff00);
145
- tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
146
- tcg_gen_or_i32(rd, rd, tmp);
147
-
148
- tcg_gen_shri_i32(t1, t1, 8);
149
- tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
150
- tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
151
- tcg_gen_or_i32(t1, t1, tmp);
152
- tcg_gen_mov_i32(t0, rd);
153
-
154
- tcg_temp_free_i32(tmp);
155
- tcg_temp_free_i32(rd);
156
-}
157
-
158
-static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
159
-{
160
- TCGv_i32 rd, tmp;
161
-
162
- rd = tcg_temp_new_i32();
163
- tmp = tcg_temp_new_i32();
164
-
165
- tcg_gen_shli_i32(rd, t0, 16);
166
- tcg_gen_andi_i32(tmp, t1, 0xffff);
167
- tcg_gen_or_i32(rd, rd, tmp);
168
- tcg_gen_shri_i32(t1, t1, 16);
169
- tcg_gen_andi_i32(tmp, t0, 0xffff0000);
170
- tcg_gen_or_i32(t1, t1, tmp);
171
- tcg_gen_mov_i32(t0, rd);
172
-
173
- tcg_temp_free_i32(tmp);
174
- tcg_temp_free_i32(rd);
175
-}
176
-
177
-/* Symbolic constants for op fields for Neon 2-register miscellaneous.
178
- * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B
179
- * table A7-13.
180
- */
181
-#define NEON_2RM_VREV64 0
182
-#define NEON_2RM_VREV32 1
183
-#define NEON_2RM_VREV16 2
184
-#define NEON_2RM_VPADDL 4
185
-#define NEON_2RM_VPADDL_U 5
186
-#define NEON_2RM_AESE 6 /* Includes AESD */
187
-#define NEON_2RM_AESMC 7 /* Includes AESIMC */
188
-#define NEON_2RM_VCLS 8
189
-#define NEON_2RM_VCLZ 9
190
-#define NEON_2RM_VCNT 10
191
-#define NEON_2RM_VMVN 11
192
-#define NEON_2RM_VPADAL 12
193
-#define NEON_2RM_VPADAL_U 13
194
-#define NEON_2RM_VQABS 14
195
-#define NEON_2RM_VQNEG 15
196
-#define NEON_2RM_VCGT0 16
197
-#define NEON_2RM_VCGE0 17
198
-#define NEON_2RM_VCEQ0 18
199
-#define NEON_2RM_VCLE0 19
200
-#define NEON_2RM_VCLT0 20
201
-#define NEON_2RM_SHA1H 21
202
-#define NEON_2RM_VABS 22
203
-#define NEON_2RM_VNEG 23
204
-#define NEON_2RM_VCGT0_F 24
205
-#define NEON_2RM_VCGE0_F 25
206
-#define NEON_2RM_VCEQ0_F 26
207
-#define NEON_2RM_VCLE0_F 27
208
-#define NEON_2RM_VCLT0_F 28
209
-#define NEON_2RM_VABS_F 30
210
-#define NEON_2RM_VNEG_F 31
211
-#define NEON_2RM_VSWP 32
212
-#define NEON_2RM_VTRN 33
213
-#define NEON_2RM_VUZP 34
214
-#define NEON_2RM_VZIP 35
215
-#define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
216
-#define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
217
-#define NEON_2RM_VSHLL 38
218
-#define NEON_2RM_SHA1SU1 39 /* Includes SHA256SU0 */
219
-#define NEON_2RM_VRINTN 40
220
-#define NEON_2RM_VRINTX 41
221
-#define NEON_2RM_VRINTA 42
222
-#define NEON_2RM_VRINTZ 43
223
-#define NEON_2RM_VCVT_F16_F32 44
224
-#define NEON_2RM_VRINTM 45
225
-#define NEON_2RM_VCVT_F32_F16 46
226
-#define NEON_2RM_VRINTP 47
227
-#define NEON_2RM_VCVTAU 48
228
-#define NEON_2RM_VCVTAS 49
229
-#define NEON_2RM_VCVTNU 50
230
-#define NEON_2RM_VCVTNS 51
231
-#define NEON_2RM_VCVTPU 52
232
-#define NEON_2RM_VCVTPS 53
233
-#define NEON_2RM_VCVTMU 54
234
-#define NEON_2RM_VCVTMS 55
235
-#define NEON_2RM_VRECPE 56
236
-#define NEON_2RM_VRSQRTE 57
237
-#define NEON_2RM_VRECPE_F 58
238
-#define NEON_2RM_VRSQRTE_F 59
239
-#define NEON_2RM_VCVT_FS 60
240
-#define NEON_2RM_VCVT_FU 61
241
-#define NEON_2RM_VCVT_SF 62
242
-#define NEON_2RM_VCVT_UF 63
243
-
244
-/* Each entry in this array has bit n set if the insn allows
245
- * size value n (otherwise it will UNDEF). Since unallocated
246
- * op values will have no bits set they always UNDEF.
247
- */
248
-static const uint8_t neon_2rm_sizes[] = {
249
- [NEON_2RM_VREV64] = 0x7,
250
- [NEON_2RM_VREV32] = 0x3,
251
- [NEON_2RM_VREV16] = 0x1,
252
- [NEON_2RM_VPADDL] = 0x7,
253
- [NEON_2RM_VPADDL_U] = 0x7,
254
- [NEON_2RM_AESE] = 0x1,
255
- [NEON_2RM_AESMC] = 0x1,
256
- [NEON_2RM_VCLS] = 0x7,
257
- [NEON_2RM_VCLZ] = 0x7,
258
- [NEON_2RM_VCNT] = 0x1,
259
- [NEON_2RM_VMVN] = 0x1,
260
- [NEON_2RM_VPADAL] = 0x7,
261
- [NEON_2RM_VPADAL_U] = 0x7,
262
- [NEON_2RM_VQABS] = 0x7,
263
- [NEON_2RM_VQNEG] = 0x7,
264
- [NEON_2RM_VCGT0] = 0x7,
265
- [NEON_2RM_VCGE0] = 0x7,
266
- [NEON_2RM_VCEQ0] = 0x7,
267
- [NEON_2RM_VCLE0] = 0x7,
268
- [NEON_2RM_VCLT0] = 0x7,
269
- [NEON_2RM_SHA1H] = 0x4,
270
- [NEON_2RM_VABS] = 0x7,
271
- [NEON_2RM_VNEG] = 0x7,
272
- [NEON_2RM_VCGT0_F] = 0x4,
273
- [NEON_2RM_VCGE0_F] = 0x4,
274
- [NEON_2RM_VCEQ0_F] = 0x4,
275
- [NEON_2RM_VCLE0_F] = 0x4,
276
- [NEON_2RM_VCLT0_F] = 0x4,
277
- [NEON_2RM_VABS_F] = 0x4,
278
- [NEON_2RM_VNEG_F] = 0x4,
279
- [NEON_2RM_VSWP] = 0x1,
280
- [NEON_2RM_VTRN] = 0x7,
281
- [NEON_2RM_VUZP] = 0x7,
282
- [NEON_2RM_VZIP] = 0x7,
283
- [NEON_2RM_VMOVN] = 0x7,
284
- [NEON_2RM_VQMOVN] = 0x7,
285
- [NEON_2RM_VSHLL] = 0x7,
286
- [NEON_2RM_SHA1SU1] = 0x4,
287
- [NEON_2RM_VRINTN] = 0x4,
288
- [NEON_2RM_VRINTX] = 0x4,
289
- [NEON_2RM_VRINTA] = 0x4,
290
- [NEON_2RM_VRINTZ] = 0x4,
291
- [NEON_2RM_VCVT_F16_F32] = 0x2,
292
- [NEON_2RM_VRINTM] = 0x4,
293
- [NEON_2RM_VCVT_F32_F16] = 0x2,
294
- [NEON_2RM_VRINTP] = 0x4,
295
- [NEON_2RM_VCVTAU] = 0x4,
296
- [NEON_2RM_VCVTAS] = 0x4,
297
- [NEON_2RM_VCVTNU] = 0x4,
298
- [NEON_2RM_VCVTNS] = 0x4,
299
- [NEON_2RM_VCVTPU] = 0x4,
300
- [NEON_2RM_VCVTPS] = 0x4,
301
- [NEON_2RM_VCVTMU] = 0x4,
302
- [NEON_2RM_VCVTMS] = 0x4,
303
- [NEON_2RM_VRECPE] = 0x4,
304
- [NEON_2RM_VRSQRTE] = 0x4,
305
- [NEON_2RM_VRECPE_F] = 0x4,
306
- [NEON_2RM_VRSQRTE_F] = 0x4,
307
- [NEON_2RM_VCVT_FS] = 0x4,
308
- [NEON_2RM_VCVT_FU] = 0x4,
309
- [NEON_2RM_VCVT_SF] = 0x4,
310
- [NEON_2RM_VCVT_UF] = 0x4,
311
-};
312
-
313
static void gen_gvec_fn3_qc(uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_ofs,
314
uint32_t opr_sz, uint32_t max_sz,
315
gen_helper_gvec_3_ptr *fn)
316
@@ -XXX,XX +XXX,XX @@ void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
317
tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]);
318
}
319
320
-/* Translate a NEON data processing instruction. Return nonzero if the
321
- instruction is invalid.
322
- We process data in a mixture of 32-bit and 64-bit chunks.
323
- Mostly we use 32-bit chunks so we can use normal scalar instructions. */
324
-
325
-static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
326
-{
327
- int op;
328
- int q;
329
- int rd, rm;
330
- int size;
331
- int pass;
332
- int u;
333
- TCGv_i32 tmp, tmp2;
334
-
335
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
336
- return 1;
337
- }
338
-
339
- /* FIXME: this access check should not take precedence over UNDEF
340
- * for invalid encodings; we will generate incorrect syndrome information
341
- * for attempts to execute invalid vfp/neon encodings with FP disabled.
342
- */
343
- if (s->fp_excp_el) {
344
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
345
- syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
346
- return 0;
347
- }
348
-
349
- if (!s->vfp_enabled)
350
- return 1;
351
- q = (insn & (1 << 6)) != 0;
352
- u = (insn >> 24) & 1;
353
- VFP_DREG_D(rd, insn);
354
- VFP_DREG_M(rm, insn);
355
- size = (insn >> 20) & 3;
356
-
357
- if ((insn & (1 << 23)) == 0) {
358
- /* Three register same length: handled by decodetree */
359
- return 1;
360
- } else if (insn & (1 << 4)) {
361
- /* Two registers and shift or reg and imm: handled by decodetree */
362
- return 1;
363
- } else { /* (insn & 0x00800010 == 0x00800000) */
364
- if (size != 3) {
365
- /*
366
- * Three registers of different lengths, or two registers and
367
- * a scalar: handled by decodetree
368
- */
369
- return 1;
370
- } else { /* size == 3 */
371
- if (!u) {
372
- /* Extract: handled by decodetree */
373
- return 1;
374
- } else if ((insn & (1 << 11)) == 0) {
375
- /* Two register misc. */
376
- op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
377
- size = (insn >> 18) & 3;
378
- /* UNDEF for unknown op values and bad op-size combinations */
379
- if ((neon_2rm_sizes[op] & (1 << size)) == 0) {
380
- return 1;
381
- }
382
- if (q && ((rm | rd) & 1)) {
383
- return 1;
384
- }
385
- switch (op) {
386
- case NEON_2RM_VREV64:
387
- case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U:
388
- case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U:
389
- case NEON_2RM_VUZP:
390
- case NEON_2RM_VZIP:
391
- case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN:
392
- case NEON_2RM_VSHLL:
393
- case NEON_2RM_VCVT_F16_F32:
394
- case NEON_2RM_VCVT_F32_F16:
395
- case NEON_2RM_VMVN:
396
- case NEON_2RM_VNEG:
397
- case NEON_2RM_VABS:
398
- case NEON_2RM_VCEQ0:
399
- case NEON_2RM_VCGT0:
400
- case NEON_2RM_VCLE0:
401
- case NEON_2RM_VCGE0:
402
- case NEON_2RM_VCLT0:
403
- case NEON_2RM_AESE: case NEON_2RM_AESMC:
404
- case NEON_2RM_SHA1H:
405
- case NEON_2RM_SHA1SU1:
406
- case NEON_2RM_VREV32:
407
- case NEON_2RM_VREV16:
408
- case NEON_2RM_VCLS:
409
- case NEON_2RM_VCLZ:
410
- case NEON_2RM_VCNT:
411
- case NEON_2RM_VABS_F:
412
- case NEON_2RM_VNEG_F:
413
- case NEON_2RM_VRECPE:
414
- case NEON_2RM_VRSQRTE:
415
- case NEON_2RM_VQABS:
416
- case NEON_2RM_VQNEG:
417
- case NEON_2RM_VRECPE_F:
418
- case NEON_2RM_VRSQRTE_F:
419
- case NEON_2RM_VCVT_FS:
420
- case NEON_2RM_VCVT_FU:
421
- case NEON_2RM_VCVT_SF:
422
- case NEON_2RM_VCVT_UF:
423
- case NEON_2RM_VRINTX:
424
- case NEON_2RM_VCGT0_F:
425
- case NEON_2RM_VCGE0_F:
426
- case NEON_2RM_VCEQ0_F:
427
- case NEON_2RM_VCLE0_F:
428
- case NEON_2RM_VCLT0_F:
429
- case NEON_2RM_VRINTN:
430
- case NEON_2RM_VRINTA:
431
- case NEON_2RM_VRINTM:
432
- case NEON_2RM_VRINTP:
433
- case NEON_2RM_VRINTZ:
434
- case NEON_2RM_VCVTAU:
435
- case NEON_2RM_VCVTAS:
436
- case NEON_2RM_VCVTNU:
437
- case NEON_2RM_VCVTNS:
438
- case NEON_2RM_VCVTPU:
439
- case NEON_2RM_VCVTPS:
440
- case NEON_2RM_VCVTMU:
441
- case NEON_2RM_VCVTMS:
442
- case NEON_2RM_VSWP:
443
- /* handled by decodetree */
444
- return 1;
445
- case NEON_2RM_VTRN:
446
- if (size == 2) {
447
- int n;
448
- for (n = 0; n < (q ? 4 : 2); n += 2) {
449
- tmp = neon_load_reg(rm, n);
450
- tmp2 = neon_load_reg(rd, n + 1);
451
- neon_store_reg(rm, n, tmp2);
452
- neon_store_reg(rd, n + 1, tmp);
453
- }
454
- } else {
455
- goto elementwise;
456
- }
457
- break;
458
-
459
- default:
460
- elementwise:
461
- for (pass = 0; pass < (q ? 4 : 2); pass++) {
462
- tmp = neon_load_reg(rm, pass);
463
- switch (op) {
464
- case NEON_2RM_VTRN:
465
- tmp2 = neon_load_reg(rd, pass);
466
- switch (size) {
467
- case 0: gen_neon_trn_u8(tmp, tmp2); break;
468
- case 1: gen_neon_trn_u16(tmp, tmp2); break;
469
- default: abort();
470
- }
471
- neon_store_reg(rm, pass, tmp2);
472
- break;
473
- default:
474
- /* Reserved op values were caught by the
475
- * neon_2rm_sizes[] check earlier.
476
- */
477
- abort();
478
- }
479
- neon_store_reg(rd, pass, tmp);
480
- }
481
- break;
482
- }
483
- } else {
484
- /* VTBL, VTBX, VDUP: handled by decodetree */
485
- return 1;
486
- }
487
- }
488
- }
489
- return 0;
490
-}
491
-
492
static int disas_coproc_insn(DisasContext *s, uint32_t insn)
493
{
494
int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
495
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
496
}
497
/* fall back to legacy decoder */
498
499
- if (((insn >> 25) & 7) == 1) {
500
- /* NEON Data processing. */
501
- if (disas_neon_data_insn(s, insn)) {
502
- goto illegal_op;
503
- }
504
- return;
505
- }
506
if ((insn & 0x0e000f00) == 0x0c000100) {
507
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
508
/* iWMMXt register transfer. */
509
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
510
break;
511
}
512
if (((insn >> 24) & 3) == 3) {
513
- /* Translate into the equivalent ARM encoding. */
514
- insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
515
- if (disas_neon_data_insn(s, insn)) {
516
- goto illegal_op;
517
- }
518
+ /* Neon DP, but failed disas_neon_dp() */
519
+ goto illegal_op;
520
} else if (((insn >> 8) & 0xe) == 10) {
521
/* VFP, but failed disas_vfp. */
522
goto illegal_op;
523
--
62
--
524
2.20.1
63
2.20.1
525
64
526
65
diff view generated by jsdifflib
1
From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
1
From: Luc Michel <luc@lmichel.fr>
2
2
3
This adds support for memory(pc-dimm) hot remove on arm/virt that
3
The clock multiplexers are the last clock stage in the CPRMAN. Each mux
4
uses acpi ged device.
4
outputs one clock signal that goes out of the CPRMAN to the SoC
5
5
peripherals.
6
NVDIMM hot removal is not yet supported.
6
7
7
Each mux has at most 10 sources. The sources 0 to 3 are common to all
8
Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
8
muxes. They are:
9
Message-id: 20200622124157.20360-1-shameerali.kolothum.thodi@huawei.com
9
0. ground (no clock signal)
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
1. the main oscillator (xosc)
11
Tested-by: Eric Auger <eric.auger@redhat.com>
11
2. "test debug 0" clock
12
3. "test debug 1" clock
13
14
Test debug 0 and 1 are actual clock muxes that can be used as sources to
15
other muxes (for debug purpose).
16
17
Sources 4 to 9 are mux specific and can be unpopulated (grounded). Those
18
sources are fed by the PLL channels outputs.
19
20
One corner case exists for DSI0E and DSI0P muxes. They have their source
21
number 4 connected to an intermediate multiplexer that can select
22
between PLLA-DSI0 and PLLD-DSI0 channel. This multiplexer is called
23
DSI0HSCK and is not a clock mux as such. It is really a simple mux from
24
the hardware point of view (see https://elinux.org/The_Undocumented_Pi).
25
This mux is not implemented in this commit.
26
27
Note that there is some muxes for which sources are unknown (because of
28
a lack of documentation). For those cases all the sources are connected
29
to ground in this implementation.
30
31
Each clock mux output is exported by the CPRMAN at the qdev level,
32
adding the suffix '-out' to the mux name to form the output clock name.
33
(E.g. the 'uart' mux sees its output exported as 'uart-out' at the
34
CPRMAN level.)
35
36
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
37
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
38
Signed-off-by: Luc Michel <luc@lmichel.fr>
39
Tested-by: Guenter Roeck <linux@roeck-us.net>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
40
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
41
---
14
hw/acpi/generic_event_device.c | 29 ++++++++++++++++
42
include/hw/misc/bcm2835_cprman.h | 85 +++++
15
hw/arm/virt.c | 62 ++++++++++++++++++++++++++++++++--
43
include/hw/misc/bcm2835_cprman_internals.h | 422 +++++++++++++++++++++
16
2 files changed, 89 insertions(+), 2 deletions(-)
44
hw/misc/bcm2835_cprman.c | 151 ++++++++
17
45
3 files changed, 658 insertions(+)
18
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
46
47
diff --git a/include/hw/misc/bcm2835_cprman.h b/include/hw/misc/bcm2835_cprman.h
19
index XXXXXXX..XXXXXXX 100644
48
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/acpi/generic_event_device.c
49
--- a/include/hw/misc/bcm2835_cprman.h
21
+++ b/hw/acpi/generic_event_device.c
50
+++ b/include/hw/misc/bcm2835_cprman.h
22
@@ -XXX,XX +XXX,XX @@ static void acpi_ged_device_plug_cb(HotplugHandler *hotplug_dev,
51
@@ -XXX,XX +XXX,XX @@ typedef enum CprmanPllChannel {
52
CPRMAN_PLLB_CHANNEL_ARM,
53
54
CPRMAN_NUM_PLL_CHANNEL,
55
+
56
+ /* Special values used when connecting clock sources to clocks */
57
+ CPRMAN_CLOCK_SRC_NORMAL = -1,
58
+ CPRMAN_CLOCK_SRC_FORCE_GROUND = -2,
59
+ CPRMAN_CLOCK_SRC_DSI0HSCK = -3,
60
} CprmanPllChannel;
61
62
+typedef enum CprmanClockMux {
63
+ CPRMAN_CLOCK_GNRIC,
64
+ CPRMAN_CLOCK_VPU,
65
+ CPRMAN_CLOCK_SYS,
66
+ CPRMAN_CLOCK_PERIA,
67
+ CPRMAN_CLOCK_PERII,
68
+ CPRMAN_CLOCK_H264,
69
+ CPRMAN_CLOCK_ISP,
70
+ CPRMAN_CLOCK_V3D,
71
+ CPRMAN_CLOCK_CAM0,
72
+ CPRMAN_CLOCK_CAM1,
73
+ CPRMAN_CLOCK_CCP2,
74
+ CPRMAN_CLOCK_DSI0E,
75
+ CPRMAN_CLOCK_DSI0P,
76
+ CPRMAN_CLOCK_DPI,
77
+ CPRMAN_CLOCK_GP0,
78
+ CPRMAN_CLOCK_GP1,
79
+ CPRMAN_CLOCK_GP2,
80
+ CPRMAN_CLOCK_HSM,
81
+ CPRMAN_CLOCK_OTP,
82
+ CPRMAN_CLOCK_PCM,
83
+ CPRMAN_CLOCK_PWM,
84
+ CPRMAN_CLOCK_SLIM,
85
+ CPRMAN_CLOCK_SMI,
86
+ CPRMAN_CLOCK_TEC,
87
+ CPRMAN_CLOCK_TD0,
88
+ CPRMAN_CLOCK_TD1,
89
+ CPRMAN_CLOCK_TSENS,
90
+ CPRMAN_CLOCK_TIMER,
91
+ CPRMAN_CLOCK_UART,
92
+ CPRMAN_CLOCK_VEC,
93
+ CPRMAN_CLOCK_PULSE,
94
+ CPRMAN_CLOCK_SDC,
95
+ CPRMAN_CLOCK_ARM,
96
+ CPRMAN_CLOCK_AVEO,
97
+ CPRMAN_CLOCK_EMMC,
98
+ CPRMAN_CLOCK_EMMC2,
99
+
100
+ CPRMAN_NUM_CLOCK_MUX
101
+} CprmanClockMux;
102
+
103
+typedef enum CprmanClockMuxSource {
104
+ CPRMAN_CLOCK_SRC_GND = 0,
105
+ CPRMAN_CLOCK_SRC_XOSC,
106
+ CPRMAN_CLOCK_SRC_TD0,
107
+ CPRMAN_CLOCK_SRC_TD1,
108
+ CPRMAN_CLOCK_SRC_PLLA,
109
+ CPRMAN_CLOCK_SRC_PLLC,
110
+ CPRMAN_CLOCK_SRC_PLLD,
111
+ CPRMAN_CLOCK_SRC_PLLH,
112
+ CPRMAN_CLOCK_SRC_PLLC_CORE1,
113
+ CPRMAN_CLOCK_SRC_PLLC_CORE2,
114
+
115
+ CPRMAN_NUM_CLOCK_MUX_SRC
116
+} CprmanClockMuxSource;
117
+
118
typedef struct CprmanPllState {
119
/*< private >*/
120
DeviceState parent_obj;
121
@@ -XXX,XX +XXX,XX @@ typedef struct CprmanPllChannelState {
122
Clock *out;
123
} CprmanPllChannelState;
124
125
+typedef struct CprmanClockMuxState {
126
+ /*< private >*/
127
+ DeviceState parent_obj;
128
+
129
+ /*< public >*/
130
+ CprmanClockMux id;
131
+
132
+ uint32_t *reg_ctl;
133
+ uint32_t *reg_div;
134
+ int int_bits;
135
+ int frac_bits;
136
+
137
+ Clock *srcs[CPRMAN_NUM_CLOCK_MUX_SRC];
138
+ Clock *out;
139
+
140
+ /*
141
+ * Used by clock srcs update callback to retrieve both the clock and the
142
+ * source number.
143
+ */
144
+ struct CprmanClockMuxState *backref[CPRMAN_NUM_CLOCK_MUX_SRC];
145
+} CprmanClockMuxState;
146
+
147
struct BCM2835CprmanState {
148
/*< private >*/
149
SysBusDevice parent_obj;
150
@@ -XXX,XX +XXX,XX @@ struct BCM2835CprmanState {
151
152
CprmanPllState plls[CPRMAN_NUM_PLL];
153
CprmanPllChannelState channels[CPRMAN_NUM_PLL_CHANNEL];
154
+ CprmanClockMuxState clock_muxes[CPRMAN_NUM_CLOCK_MUX];
155
156
uint32_t regs[CPRMAN_NUM_REGS];
157
uint32_t xosc_freq;
158
159
Clock *xosc;
160
+ Clock *gnd;
161
};
162
163
#endif
164
diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/bcm2835_cprman_internals.h
165
index XXXXXXX..XXXXXXX 100644
166
--- a/include/hw/misc/bcm2835_cprman_internals.h
167
+++ b/include/hw/misc/bcm2835_cprman_internals.h
168
@@ -XXX,XX +XXX,XX @@
169
170
#define TYPE_CPRMAN_PLL "bcm2835-cprman-pll"
171
#define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel"
172
+#define TYPE_CPRMAN_CLOCK_MUX "bcm2835-cprman-clock-mux"
173
174
DECLARE_INSTANCE_CHECKER(CprmanPllState, CPRMAN_PLL,
175
TYPE_CPRMAN_PLL)
176
DECLARE_INSTANCE_CHECKER(CprmanPllChannelState, CPRMAN_PLL_CHANNEL,
177
TYPE_CPRMAN_PLL_CHANNEL)
178
+DECLARE_INSTANCE_CHECKER(CprmanClockMuxState, CPRMAN_CLOCK_MUX,
179
+ TYPE_CPRMAN_CLOCK_MUX)
180
181
/* Register map */
182
183
@@ -XXX,XX +XXX,XX @@ REG32(A2W_PLLH_STS, 0x1660)
184
185
REG32(A2W_PLLB_ARM, 0x13e0)
186
187
+/* Clock muxes */
188
+REG32(CM_GNRICCTL, 0x000)
189
+ FIELD(CM_CLOCKx_CTL, SRC, 0, 4)
190
+ FIELD(CM_CLOCKx_CTL, ENABLE, 4, 1)
191
+ FIELD(CM_CLOCKx_CTL, KILL, 5, 1)
192
+ FIELD(CM_CLOCKx_CTL, GATE, 6, 1)
193
+ FIELD(CM_CLOCKx_CTL, BUSY, 7, 1)
194
+ FIELD(CM_CLOCKx_CTL, BUSYD, 8, 1)
195
+ FIELD(CM_CLOCKx_CTL, MASH, 9, 2)
196
+ FIELD(CM_CLOCKx_CTL, FLIP, 11, 1)
197
+REG32(CM_GNRICDIV, 0x004)
198
+ FIELD(CM_CLOCKx_DIV, FRAC, 0, 12)
199
+REG32(CM_VPUCTL, 0x008)
200
+REG32(CM_VPUDIV, 0x00c)
201
+REG32(CM_SYSCTL, 0x010)
202
+REG32(CM_SYSDIV, 0x014)
203
+REG32(CM_PERIACTL, 0x018)
204
+REG32(CM_PERIADIV, 0x01c)
205
+REG32(CM_PERIICTL, 0x020)
206
+REG32(CM_PERIIDIV, 0x024)
207
+REG32(CM_H264CTL, 0x028)
208
+REG32(CM_H264DIV, 0x02c)
209
+REG32(CM_ISPCTL, 0x030)
210
+REG32(CM_ISPDIV, 0x034)
211
+REG32(CM_V3DCTL, 0x038)
212
+REG32(CM_V3DDIV, 0x03c)
213
+REG32(CM_CAM0CTL, 0x040)
214
+REG32(CM_CAM0DIV, 0x044)
215
+REG32(CM_CAM1CTL, 0x048)
216
+REG32(CM_CAM1DIV, 0x04c)
217
+REG32(CM_CCP2CTL, 0x050)
218
+REG32(CM_CCP2DIV, 0x054)
219
+REG32(CM_DSI0ECTL, 0x058)
220
+REG32(CM_DSI0EDIV, 0x05c)
221
+REG32(CM_DSI0PCTL, 0x060)
222
+REG32(CM_DSI0PDIV, 0x064)
223
+REG32(CM_DPICTL, 0x068)
224
+REG32(CM_DPIDIV, 0x06c)
225
+REG32(CM_GP0CTL, 0x070)
226
+REG32(CM_GP0DIV, 0x074)
227
+REG32(CM_GP1CTL, 0x078)
228
+REG32(CM_GP1DIV, 0x07c)
229
+REG32(CM_GP2CTL, 0x080)
230
+REG32(CM_GP2DIV, 0x084)
231
+REG32(CM_HSMCTL, 0x088)
232
+REG32(CM_HSMDIV, 0x08c)
233
+REG32(CM_OTPCTL, 0x090)
234
+REG32(CM_OTPDIV, 0x094)
235
+REG32(CM_PCMCTL, 0x098)
236
+REG32(CM_PCMDIV, 0x09c)
237
+REG32(CM_PWMCTL, 0x0a0)
238
+REG32(CM_PWMDIV, 0x0a4)
239
+REG32(CM_SLIMCTL, 0x0a8)
240
+REG32(CM_SLIMDIV, 0x0ac)
241
+REG32(CM_SMICTL, 0x0b0)
242
+REG32(CM_SMIDIV, 0x0b4)
243
+REG32(CM_TCNTCTL, 0x0c0)
244
+REG32(CM_TCNTCNT, 0x0c4)
245
+REG32(CM_TECCTL, 0x0c8)
246
+REG32(CM_TECDIV, 0x0cc)
247
+REG32(CM_TD0CTL, 0x0d0)
248
+REG32(CM_TD0DIV, 0x0d4)
249
+REG32(CM_TD1CTL, 0x0d8)
250
+REG32(CM_TD1DIV, 0x0dc)
251
+REG32(CM_TSENSCTL, 0x0e0)
252
+REG32(CM_TSENSDIV, 0x0e4)
253
+REG32(CM_TIMERCTL, 0x0e8)
254
+REG32(CM_TIMERDIV, 0x0ec)
255
+REG32(CM_UARTCTL, 0x0f0)
256
+REG32(CM_UARTDIV, 0x0f4)
257
+REG32(CM_VECCTL, 0x0f8)
258
+REG32(CM_VECDIV, 0x0fc)
259
+REG32(CM_PULSECTL, 0x190)
260
+REG32(CM_PULSEDIV, 0x194)
261
+REG32(CM_SDCCTL, 0x1a8)
262
+REG32(CM_SDCDIV, 0x1ac)
263
+REG32(CM_ARMCTL, 0x1b0)
264
+REG32(CM_AVEOCTL, 0x1b8)
265
+REG32(CM_AVEODIV, 0x1bc)
266
+REG32(CM_EMMCCTL, 0x1c0)
267
+REG32(CM_EMMCDIV, 0x1c4)
268
+REG32(CM_EMMC2CTL, 0x1d0)
269
+REG32(CM_EMMC2DIV, 0x1d4)
270
+
271
/* misc registers */
272
REG32(CM_LOCK, 0x114)
273
FIELD(CM_LOCK, FLOCKH, 12, 1)
274
@@ -XXX,XX +XXX,XX @@ static inline void set_pll_channel_init_info(BCM2835CprmanState *s,
275
channel->fixed_divider = PLL_CHANNEL_INIT_INFO[id].fixed_divider;
276
}
277
278
+/* Clock mux init info */
279
+typedef struct ClockMuxInitInfo {
280
+ const char *name;
281
+ size_t cm_offset; /* cm_offset[0]->CM_CTL, cm_offset[1]->CM_DIV */
282
+ int int_bits;
283
+ int frac_bits;
284
+
285
+ CprmanPllChannel src_mapping[CPRMAN_NUM_CLOCK_MUX_SRC];
286
+} ClockMuxInitInfo;
287
+
288
+/*
289
+ * Each clock mux can have up to 10 sources. Sources 0 to 3 are always the
290
+ * same (ground, xosc, td0, td1). Sources 4 to 9 are mux specific, and are not
291
+ * always populated. The following macros catch all those cases.
292
+ */
293
+
294
+/* Unknown mapping. Connect everything to ground */
295
+#define SRC_MAPPING_INFO_unknown \
296
+ .src_mapping = { \
297
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* gnd */ \
298
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* xosc */ \
299
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* test debug 0 */ \
300
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* test debug 1 */ \
301
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll a */ \
302
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c */ \
303
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll d */ \
304
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll h */ \
305
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c, core1 */ \
306
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c, core2 */ \
307
+ }
308
+
309
+/* Only the oscillator and the two test debug clocks */
310
+#define SRC_MAPPING_INFO_xosc \
311
+ .src_mapping = { \
312
+ CPRMAN_CLOCK_SRC_NORMAL, \
313
+ CPRMAN_CLOCK_SRC_NORMAL, \
314
+ CPRMAN_CLOCK_SRC_NORMAL, \
315
+ CPRMAN_CLOCK_SRC_NORMAL, \
316
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
317
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
318
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
319
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
320
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
321
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
322
+ }
323
+
324
+/* All the PLL "core" channels */
325
+#define SRC_MAPPING_INFO_core \
326
+ .src_mapping = { \
327
+ CPRMAN_CLOCK_SRC_NORMAL, \
328
+ CPRMAN_CLOCK_SRC_NORMAL, \
329
+ CPRMAN_CLOCK_SRC_NORMAL, \
330
+ CPRMAN_CLOCK_SRC_NORMAL, \
331
+ CPRMAN_PLLA_CHANNEL_CORE, \
332
+ CPRMAN_PLLC_CHANNEL_CORE0, \
333
+ CPRMAN_PLLD_CHANNEL_CORE, \
334
+ CPRMAN_PLLH_CHANNEL_AUX, \
335
+ CPRMAN_PLLC_CHANNEL_CORE1, \
336
+ CPRMAN_PLLC_CHANNEL_CORE2, \
337
+ }
338
+
339
+/* All the PLL "per" channels */
340
+#define SRC_MAPPING_INFO_periph \
341
+ .src_mapping = { \
342
+ CPRMAN_CLOCK_SRC_NORMAL, \
343
+ CPRMAN_CLOCK_SRC_NORMAL, \
344
+ CPRMAN_CLOCK_SRC_NORMAL, \
345
+ CPRMAN_CLOCK_SRC_NORMAL, \
346
+ CPRMAN_PLLA_CHANNEL_PER, \
347
+ CPRMAN_PLLC_CHANNEL_PER, \
348
+ CPRMAN_PLLD_CHANNEL_PER, \
349
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
350
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
351
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
352
+ }
353
+
354
+/*
355
+ * The DSI0 channels. This one got an intermediate mux between the PLL channels
356
+ * and the clock input.
357
+ */
358
+#define SRC_MAPPING_INFO_dsi0 \
359
+ .src_mapping = { \
360
+ CPRMAN_CLOCK_SRC_NORMAL, \
361
+ CPRMAN_CLOCK_SRC_NORMAL, \
362
+ CPRMAN_CLOCK_SRC_NORMAL, \
363
+ CPRMAN_CLOCK_SRC_NORMAL, \
364
+ CPRMAN_CLOCK_SRC_DSI0HSCK, \
365
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
366
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
367
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
368
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
369
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
370
+ }
371
+
372
+/* The DSI1 channel */
373
+#define SRC_MAPPING_INFO_dsi1 \
374
+ .src_mapping = { \
375
+ CPRMAN_CLOCK_SRC_NORMAL, \
376
+ CPRMAN_CLOCK_SRC_NORMAL, \
377
+ CPRMAN_CLOCK_SRC_NORMAL, \
378
+ CPRMAN_CLOCK_SRC_NORMAL, \
379
+ CPRMAN_PLLD_CHANNEL_DSI1, \
380
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
381
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
382
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
383
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
384
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
385
+ }
386
+
387
+#define FILL_CLOCK_MUX_SRC_MAPPING_INIT_INFO(kind_) \
388
+ SRC_MAPPING_INFO_ ## kind_
389
+
390
+#define FILL_CLOCK_MUX_INIT_INFO(clock_, kind_) \
391
+ .cm_offset = R_CM_ ## clock_ ## CTL, \
392
+ FILL_CLOCK_MUX_SRC_MAPPING_INIT_INFO(kind_)
393
+
394
+static ClockMuxInitInfo CLOCK_MUX_INIT_INFO[] = {
395
+ [CPRMAN_CLOCK_GNRIC] = {
396
+ .name = "gnric",
397
+ FILL_CLOCK_MUX_INIT_INFO(GNRIC, unknown),
398
+ },
399
+ [CPRMAN_CLOCK_VPU] = {
400
+ .name = "vpu",
401
+ .int_bits = 12,
402
+ .frac_bits = 8,
403
+ FILL_CLOCK_MUX_INIT_INFO(VPU, core),
404
+ },
405
+ [CPRMAN_CLOCK_SYS] = {
406
+ .name = "sys",
407
+ FILL_CLOCK_MUX_INIT_INFO(SYS, unknown),
408
+ },
409
+ [CPRMAN_CLOCK_PERIA] = {
410
+ .name = "peria",
411
+ FILL_CLOCK_MUX_INIT_INFO(PERIA, unknown),
412
+ },
413
+ [CPRMAN_CLOCK_PERII] = {
414
+ .name = "perii",
415
+ FILL_CLOCK_MUX_INIT_INFO(PERII, unknown),
416
+ },
417
+ [CPRMAN_CLOCK_H264] = {
418
+ .name = "h264",
419
+ .int_bits = 4,
420
+ .frac_bits = 8,
421
+ FILL_CLOCK_MUX_INIT_INFO(H264, core),
422
+ },
423
+ [CPRMAN_CLOCK_ISP] = {
424
+ .name = "isp",
425
+ .int_bits = 4,
426
+ .frac_bits = 8,
427
+ FILL_CLOCK_MUX_INIT_INFO(ISP, core),
428
+ },
429
+ [CPRMAN_CLOCK_V3D] = {
430
+ .name = "v3d",
431
+ FILL_CLOCK_MUX_INIT_INFO(V3D, core),
432
+ },
433
+ [CPRMAN_CLOCK_CAM0] = {
434
+ .name = "cam0",
435
+ .int_bits = 4,
436
+ .frac_bits = 8,
437
+ FILL_CLOCK_MUX_INIT_INFO(CAM0, periph),
438
+ },
439
+ [CPRMAN_CLOCK_CAM1] = {
440
+ .name = "cam1",
441
+ .int_bits = 4,
442
+ .frac_bits = 8,
443
+ FILL_CLOCK_MUX_INIT_INFO(CAM1, periph),
444
+ },
445
+ [CPRMAN_CLOCK_CCP2] = {
446
+ .name = "ccp2",
447
+ FILL_CLOCK_MUX_INIT_INFO(CCP2, unknown),
448
+ },
449
+ [CPRMAN_CLOCK_DSI0E] = {
450
+ .name = "dsi0e",
451
+ .int_bits = 4,
452
+ .frac_bits = 8,
453
+ FILL_CLOCK_MUX_INIT_INFO(DSI0E, dsi0),
454
+ },
455
+ [CPRMAN_CLOCK_DSI0P] = {
456
+ .name = "dsi0p",
457
+ .int_bits = 0,
458
+ .frac_bits = 0,
459
+ FILL_CLOCK_MUX_INIT_INFO(DSI0P, dsi0),
460
+ },
461
+ [CPRMAN_CLOCK_DPI] = {
462
+ .name = "dpi",
463
+ .int_bits = 4,
464
+ .frac_bits = 8,
465
+ FILL_CLOCK_MUX_INIT_INFO(DPI, periph),
466
+ },
467
+ [CPRMAN_CLOCK_GP0] = {
468
+ .name = "gp0",
469
+ .int_bits = 12,
470
+ .frac_bits = 12,
471
+ FILL_CLOCK_MUX_INIT_INFO(GP0, periph),
472
+ },
473
+ [CPRMAN_CLOCK_GP1] = {
474
+ .name = "gp1",
475
+ .int_bits = 12,
476
+ .frac_bits = 12,
477
+ FILL_CLOCK_MUX_INIT_INFO(GP1, periph),
478
+ },
479
+ [CPRMAN_CLOCK_GP2] = {
480
+ .name = "gp2",
481
+ .int_bits = 12,
482
+ .frac_bits = 12,
483
+ FILL_CLOCK_MUX_INIT_INFO(GP2, periph),
484
+ },
485
+ [CPRMAN_CLOCK_HSM] = {
486
+ .name = "hsm",
487
+ .int_bits = 4,
488
+ .frac_bits = 8,
489
+ FILL_CLOCK_MUX_INIT_INFO(HSM, periph),
490
+ },
491
+ [CPRMAN_CLOCK_OTP] = {
492
+ .name = "otp",
493
+ .int_bits = 4,
494
+ .frac_bits = 0,
495
+ FILL_CLOCK_MUX_INIT_INFO(OTP, xosc),
496
+ },
497
+ [CPRMAN_CLOCK_PCM] = {
498
+ .name = "pcm",
499
+ .int_bits = 12,
500
+ .frac_bits = 12,
501
+ FILL_CLOCK_MUX_INIT_INFO(PCM, periph),
502
+ },
503
+ [CPRMAN_CLOCK_PWM] = {
504
+ .name = "pwm",
505
+ .int_bits = 12,
506
+ .frac_bits = 12,
507
+ FILL_CLOCK_MUX_INIT_INFO(PWM, periph),
508
+ },
509
+ [CPRMAN_CLOCK_SLIM] = {
510
+ .name = "slim",
511
+ .int_bits = 12,
512
+ .frac_bits = 12,
513
+ FILL_CLOCK_MUX_INIT_INFO(SLIM, periph),
514
+ },
515
+ [CPRMAN_CLOCK_SMI] = {
516
+ .name = "smi",
517
+ .int_bits = 4,
518
+ .frac_bits = 8,
519
+ FILL_CLOCK_MUX_INIT_INFO(SMI, periph),
520
+ },
521
+ [CPRMAN_CLOCK_TEC] = {
522
+ .name = "tec",
523
+ .int_bits = 6,
524
+ .frac_bits = 0,
525
+ FILL_CLOCK_MUX_INIT_INFO(TEC, xosc),
526
+ },
527
+ [CPRMAN_CLOCK_TD0] = {
528
+ .name = "td0",
529
+ FILL_CLOCK_MUX_INIT_INFO(TD0, unknown),
530
+ },
531
+ [CPRMAN_CLOCK_TD1] = {
532
+ .name = "td1",
533
+ FILL_CLOCK_MUX_INIT_INFO(TD1, unknown),
534
+ },
535
+ [CPRMAN_CLOCK_TSENS] = {
536
+ .name = "tsens",
537
+ .int_bits = 5,
538
+ .frac_bits = 0,
539
+ FILL_CLOCK_MUX_INIT_INFO(TSENS, xosc),
540
+ },
541
+ [CPRMAN_CLOCK_TIMER] = {
542
+ .name = "timer",
543
+ .int_bits = 6,
544
+ .frac_bits = 12,
545
+ FILL_CLOCK_MUX_INIT_INFO(TIMER, xosc),
546
+ },
547
+ [CPRMAN_CLOCK_UART] = {
548
+ .name = "uart",
549
+ .int_bits = 10,
550
+ .frac_bits = 12,
551
+ FILL_CLOCK_MUX_INIT_INFO(UART, periph),
552
+ },
553
+ [CPRMAN_CLOCK_VEC] = {
554
+ .name = "vec",
555
+ .int_bits = 4,
556
+ .frac_bits = 0,
557
+ FILL_CLOCK_MUX_INIT_INFO(VEC, periph),
558
+ },
559
+ [CPRMAN_CLOCK_PULSE] = {
560
+ .name = "pulse",
561
+ FILL_CLOCK_MUX_INIT_INFO(PULSE, xosc),
562
+ },
563
+ [CPRMAN_CLOCK_SDC] = {
564
+ .name = "sdram",
565
+ .int_bits = 6,
566
+ .frac_bits = 0,
567
+ FILL_CLOCK_MUX_INIT_INFO(SDC, core),
568
+ },
569
+ [CPRMAN_CLOCK_ARM] = {
570
+ .name = "arm",
571
+ FILL_CLOCK_MUX_INIT_INFO(ARM, unknown),
572
+ },
573
+ [CPRMAN_CLOCK_AVEO] = {
574
+ .name = "aveo",
575
+ .int_bits = 4,
576
+ .frac_bits = 0,
577
+ FILL_CLOCK_MUX_INIT_INFO(AVEO, periph),
578
+ },
579
+ [CPRMAN_CLOCK_EMMC] = {
580
+ .name = "emmc",
581
+ .int_bits = 4,
582
+ .frac_bits = 8,
583
+ FILL_CLOCK_MUX_INIT_INFO(EMMC, periph),
584
+ },
585
+ [CPRMAN_CLOCK_EMMC2] = {
586
+ .name = "emmc2",
587
+ .int_bits = 4,
588
+ .frac_bits = 8,
589
+ FILL_CLOCK_MUX_INIT_INFO(EMMC2, unknown),
590
+ },
591
+};
592
+
593
+#undef FILL_CLOCK_MUX_INIT_INFO
594
+#undef FILL_CLOCK_MUX_SRC_MAPPING_INIT_INFO
595
+#undef SRC_MAPPING_INFO_dsi1
596
+#undef SRC_MAPPING_INFO_dsi0
597
+#undef SRC_MAPPING_INFO_periph
598
+#undef SRC_MAPPING_INFO_core
599
+#undef SRC_MAPPING_INFO_xosc
600
+#undef SRC_MAPPING_INFO_unknown
601
+
602
+static inline void set_clock_mux_init_info(BCM2835CprmanState *s,
603
+ CprmanClockMuxState *mux,
604
+ CprmanClockMux id)
605
+{
606
+ mux->id = id;
607
+ mux->reg_ctl = &s->regs[CLOCK_MUX_INIT_INFO[id].cm_offset];
608
+ mux->reg_div = &s->regs[CLOCK_MUX_INIT_INFO[id].cm_offset + 1];
609
+ mux->int_bits = CLOCK_MUX_INIT_INFO[id].int_bits;
610
+ mux->frac_bits = CLOCK_MUX_INIT_INFO[id].frac_bits;
611
+}
612
+
613
#endif
614
diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c
615
index XXXXXXX..XXXXXXX 100644
616
--- a/hw/misc/bcm2835_cprman.c
617
+++ b/hw/misc/bcm2835_cprman.c
618
@@ -XXX,XX +XXX,XX @@
619
*
620
* The page at https://elinux.org/The_Undocumented_Pi gives the actual clock
621
* tree configuration.
622
+ *
623
+ * The CPRMAN exposes clock outputs with the name of the clock mux suffixed
624
+ * with "-out" (e.g. "uart-out", "h264-out", ...).
625
*/
626
627
#include "qemu/osdep.h"
628
@@ -XXX,XX +XXX,XX @@ static const TypeInfo cprman_pll_channel_info = {
629
};
630
631
632
+/* clock mux */
633
+
634
+static void clock_mux_update(CprmanClockMuxState *mux)
635
+{
636
+ clock_update(mux->out, 0);
637
+}
638
+
639
+static void clock_mux_src_update(void *opaque)
640
+{
641
+ CprmanClockMuxState **backref = opaque;
642
+ CprmanClockMuxState *s = *backref;
643
+
644
+ clock_mux_update(s);
645
+}
646
+
647
+static void clock_mux_init(Object *obj)
648
+{
649
+ CprmanClockMuxState *s = CPRMAN_CLOCK_MUX(obj);
650
+ size_t i;
651
+
652
+ for (i = 0; i < CPRMAN_NUM_CLOCK_MUX_SRC; i++) {
653
+ char *name = g_strdup_printf("srcs[%zu]", i);
654
+ s->backref[i] = s;
655
+ s->srcs[i] = qdev_init_clock_in(DEVICE(s), name,
656
+ clock_mux_src_update,
657
+ &s->backref[i]);
658
+ g_free(name);
659
+ }
660
+
661
+ s->out = qdev_init_clock_out(DEVICE(s), "out");
662
+}
663
+
664
+static const VMStateDescription clock_mux_vmstate = {
665
+ .name = TYPE_CPRMAN_CLOCK_MUX,
666
+ .version_id = 1,
667
+ .minimum_version_id = 1,
668
+ .fields = (VMStateField[]) {
669
+ VMSTATE_ARRAY_CLOCK(srcs, CprmanClockMuxState,
670
+ CPRMAN_NUM_CLOCK_MUX_SRC),
671
+ VMSTATE_END_OF_LIST()
672
+ }
673
+};
674
+
675
+static void clock_mux_class_init(ObjectClass *klass, void *data)
676
+{
677
+ DeviceClass *dc = DEVICE_CLASS(klass);
678
+
679
+ dc->vmsd = &clock_mux_vmstate;
680
+}
681
+
682
+static const TypeInfo cprman_clock_mux_info = {
683
+ .name = TYPE_CPRMAN_CLOCK_MUX,
684
+ .parent = TYPE_DEVICE,
685
+ .instance_size = sizeof(CprmanClockMuxState),
686
+ .class_init = clock_mux_class_init,
687
+ .instance_init = clock_mux_init,
688
+};
689
+
690
+
691
/* CPRMAN "top level" model */
692
693
static uint32_t get_cm_lock(const BCM2835CprmanState *s)
694
@@ -XXX,XX +XXX,XX @@ static inline void update_channel_from_a2w(BCM2835CprmanState *s, size_t idx)
23
}
695
}
24
}
696
}
25
697
26
+static void acpi_ged_unplug_request_cb(HotplugHandler *hotplug_dev,
698
+static inline void update_mux_from_cm(BCM2835CprmanState *s, size_t idx)
27
+ DeviceState *dev, Error **errp)
28
+{
699
+{
29
+ AcpiGedState *s = ACPI_GED(hotplug_dev);
700
+ size_t i;
30
+
701
+
31
+ if ((object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) &&
702
+ for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
32
+ !(object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)))) {
703
+ if ((CLOCK_MUX_INIT_INFO[i].cm_offset == idx) ||
33
+ acpi_memory_unplug_request_cb(hotplug_dev, &s->memhp_state, dev, errp);
704
+ (CLOCK_MUX_INIT_INFO[i].cm_offset + 4 == idx)) {
34
+ } else {
705
+ /* matches CM_CTL or CM_DIV mux register */
35
+ error_setg(errp, "acpi: device unplug request for unsupported device"
706
+ clock_mux_update(&s->clock_muxes[i]);
36
+ " type: %s", object_get_typename(OBJECT(dev)));
707
+ return;
708
+ }
37
+ }
709
+ }
38
+}
710
+}
39
+
711
+
40
+static void acpi_ged_unplug_cb(HotplugHandler *hotplug_dev,
712
#define CASE_PLL_A2W_REGS(pll_) \
41
+ DeviceState *dev, Error **errp)
713
case R_A2W_ ## pll_ ## _CTRL: \
42
+{
714
case R_A2W_ ## pll_ ## _ANA0: \
43
+ AcpiGedState *s = ACPI_GED(hotplug_dev);
715
@@ -XXX,XX +XXX,XX @@ static void cprman_write(void *opaque, hwaddr offset,
44
+
716
case R_A2W_PLLB_ARM:
45
+ if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
717
update_channel_from_a2w(s, idx);
46
+ acpi_memory_unplug_cb(&s->memhp_state, dev, errp);
718
break;
47
+ } else {
719
+
48
+ error_setg(errp, "acpi: device unplug for unsupported device"
720
+ case R_CM_GNRICCTL ... R_CM_SMIDIV:
49
+ " type: %s", object_get_typename(OBJECT(dev)));
721
+ case R_CM_TCNTCNT ... R_CM_VECDIV:
50
+ }
722
+ case R_CM_PULSECTL ... R_CM_PULSEDIV:
51
+}
723
+ case R_CM_SDCCTL ... R_CM_ARMCTL:
52
+
724
+ case R_CM_AVEOCTL ... R_CM_EMMCDIV:
53
static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
725
+ case R_CM_EMMC2CTL ... R_CM_EMMC2DIV:
54
{
726
+ update_mux_from_cm(s, idx);
55
AcpiGedState *s = ACPI_GED(adev);
727
+ break;
56
@@ -XXX,XX +XXX,XX @@ static void acpi_ged_class_init(ObjectClass *class, void *data)
57
dc->vmsd = &vmstate_acpi_ged;
58
59
hc->plug = acpi_ged_device_plug_cb;
60
+ hc->unplug_request = acpi_ged_unplug_request_cb;
61
+ hc->unplug = acpi_ged_unplug_cb;
62
63
adevc->send_event = acpi_ged_send_event;
64
}
65
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/hw/arm/virt.c
68
+++ b/hw/arm/virt.c
69
@@ -XXX,XX +XXX,XX @@ static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
70
}
728
}
71
}
729
}
72
730
73
+static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
731
@@ -XXX,XX +XXX,XX @@ static void cprman_reset(DeviceState *dev)
74
+ DeviceState *dev, Error **errp)
732
device_cold_reset(DEVICE(&s->channels[i]));
733
}
734
735
+ for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
736
+ device_cold_reset(DEVICE(&s->clock_muxes[i]));
737
+ }
738
+
739
clock_update_hz(s->xosc, s->xosc_freq);
740
}
741
742
@@ -XXX,XX +XXX,XX @@ static void cprman_init(Object *obj)
743
set_pll_channel_init_info(s, &s->channels[i], i);
744
}
745
746
+ for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
747
+ char *alias;
748
+
749
+ object_initialize_child(obj, CLOCK_MUX_INIT_INFO[i].name,
750
+ &s->clock_muxes[i],
751
+ TYPE_CPRMAN_CLOCK_MUX);
752
+ set_clock_mux_init_info(s, &s->clock_muxes[i], i);
753
+
754
+ /* Expose muxes output as CPRMAN outputs */
755
+ alias = g_strdup_printf("%s-out", CLOCK_MUX_INIT_INFO[i].name);
756
+ qdev_alias_clock(DEVICE(&s->clock_muxes[i]), "out", DEVICE(obj), alias);
757
+ g_free(alias);
758
+ }
759
+
760
s->xosc = clock_new(obj, "xosc");
761
+ s->gnd = clock_new(obj, "gnd");
762
+
763
+ clock_set(s->gnd, 0);
764
765
memory_region_init_io(&s->iomem, obj, &cprman_ops,
766
s, "bcm2835-cprman", 0x2000);
767
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
768
}
769
770
+static void connect_mux_sources(BCM2835CprmanState *s,
771
+ CprmanClockMuxState *mux,
772
+ const CprmanPllChannel *clk_mapping)
75
+{
773
+{
76
+ VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
774
+ size_t i;
77
+ Error *local_err = NULL;
775
+ Clock *td0 = s->clock_muxes[CPRMAN_CLOCK_TD0].out;
78
+
776
+ Clock *td1 = s->clock_muxes[CPRMAN_CLOCK_TD1].out;
79
+ if (!vms->acpi_dev) {
777
+
80
+ error_setg(&local_err,
778
+ /* For sources from 0 to 3. Source 4 to 9 are mux specific */
81
+ "memory hotplug is not enabled: missing acpi-ged device");
779
+ Clock * const CLK_SRC_MAPPING[] = {
82
+ goto out;
780
+ [CPRMAN_CLOCK_SRC_GND] = s->gnd,
83
+ }
781
+ [CPRMAN_CLOCK_SRC_XOSC] = s->xosc,
84
+
782
+ [CPRMAN_CLOCK_SRC_TD0] = td0,
85
+ if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
783
+ [CPRMAN_CLOCK_SRC_TD1] = td1,
86
+ error_setg(&local_err,
784
+ };
87
+ "nvdimm device hot unplug is not supported yet.");
785
+
88
+ goto out;
786
+ for (i = 0; i < CPRMAN_NUM_CLOCK_MUX_SRC; i++) {
89
+ }
787
+ CprmanPllChannel mapping = clk_mapping[i];
90
+
788
+ Clock *src;
91
+ hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
789
+
92
+ &local_err);
790
+ if (mapping == CPRMAN_CLOCK_SRC_FORCE_GROUND) {
93
+out:
791
+ src = s->gnd;
94
+ error_propagate(errp, local_err);
792
+ } else if (mapping == CPRMAN_CLOCK_SRC_DSI0HSCK) {
793
+ src = s->gnd; /* TODO */
794
+ } else if (i < CPRMAN_CLOCK_SRC_PLLA) {
795
+ src = CLK_SRC_MAPPING[i];
796
+ } else {
797
+ src = s->channels[mapping].out;
798
+ }
799
+
800
+ clock_set_source(mux->srcs[i], src);
801
+ }
95
+}
802
+}
96
+
803
+
97
+static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
804
static void cprman_realize(DeviceState *dev, Error **errp)
98
+ DeviceState *dev, Error **errp)
99
+{
100
+ VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
101
+ Error *local_err = NULL;
102
+
103
+ hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
104
+ if (local_err) {
105
+ goto out;
106
+ }
107
+
108
+ pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
109
+ qdev_unrealize(dev);
110
+
111
+out:
112
+ error_propagate(errp, local_err);
113
+}
114
+
115
static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
116
DeviceState *dev, Error **errp)
117
{
805
{
118
- error_setg(errp, "device unplug request for unsupported device"
806
BCM2835CprmanState *s = CPRMAN(dev);
119
- " type: %s", object_get_typename(OBJECT(dev)));
807
@@ -XXX,XX +XXX,XX @@ static void cprman_realize(DeviceState *dev, Error **errp)
120
+ if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
808
return;
121
+ virt_dimm_unplug_request(hotplug_dev, dev, errp);
809
}
122
+ } else {
810
}
123
+ error_setg(errp, "device unplug request for unsupported device"
811
+
124
+ " type: %s", object_get_typename(OBJECT(dev)));
812
+ for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
125
+ }
813
+ CprmanClockMuxState *clock_mux = &s->clock_muxes[i];
126
+}
814
+
127
+
815
+ connect_mux_sources(s, clock_mux, CLOCK_MUX_INIT_INFO[i].src_mapping);
128
+static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
816
+
129
+ DeviceState *dev, Error **errp)
817
+ if (!qdev_realize(DEVICE(clock_mux), NULL, errp)) {
130
+{
818
+ return;
131
+ if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
819
+ }
132
+ virt_dimm_unplug(hotplug_dev, dev, errp);
133
+ } else {
134
+ error_setg(errp, "virt: device unplug for unsupported device"
135
+ " type: %s", object_get_typename(OBJECT(dev)));
136
+ }
820
+ }
137
}
821
}
138
822
139
static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
823
static const VMStateDescription cprman_vmstate = {
140
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
824
@@ -XXX,XX +XXX,XX @@ static void cprman_register_types(void)
141
hc->pre_plug = virt_machine_device_pre_plug_cb;
825
type_register_static(&cprman_info);
142
hc->plug = virt_machine_device_plug_cb;
826
type_register_static(&cprman_pll_info);
143
hc->unplug_request = virt_machine_device_unplug_request_cb;
827
type_register_static(&cprman_pll_channel_info);
144
+ hc->unplug = virt_machine_device_unplug_cb;
828
+ type_register_static(&cprman_clock_mux_info);
145
mc->numa_mem_supported = true;
829
}
146
mc->nvdimm_supported = true;
830
147
mc->auto_enable_numa_with_memhp = true;
831
type_init(cprman_register_types);
148
--
832
--
149
2.20.1
833
2.20.1
150
834
151
835
diff view generated by jsdifflib
1
Convert the Neon-2-reg misc crypto ops (AESE, AESMC, SHA1H, SHA1SU1)
1
From: Luc Michel <luc@lmichel.fr>
2
to decodetree.
3
2
3
A clock mux can be configured to select one of its 10 sources through
4
the CM_CTL register. It also embeds yet another clock divider, composed
5
of an integer part and a fractional part. The number of bits of each
6
part is mux dependent.
7
8
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Luc Michel <luc@lmichel.fr>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Tested-by: Guenter Roeck <linux@roeck-us.net>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200616170844.13318-9-peter.maydell@linaro.org
7
---
13
---
8
target/arm/neon-dp.decode | 12 ++++++++
14
hw/misc/bcm2835_cprman.c | 53 +++++++++++++++++++++++++++++++++++++++-
9
target/arm/translate-neon.inc.c | 42 ++++++++++++++++++++++++++
15
1 file changed, 52 insertions(+), 1 deletion(-)
10
target/arm/translate.c | 52 +++------------------------------
11
3 files changed, 58 insertions(+), 48 deletions(-)
12
16
13
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
17
diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c
14
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/neon-dp.decode
19
--- a/hw/misc/bcm2835_cprman.c
16
+++ b/target/arm/neon-dp.decode
20
+++ b/hw/misc/bcm2835_cprman.c
17
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
21
@@ -XXX,XX +XXX,XX @@ static const TypeInfo cprman_pll_channel_info = {
18
&2misc vm=%vm_dp vd=%vd_dp
22
19
@2misc_q0 .... ... .. . .. size:2 .. .... . .... . . . .... \
23
/* clock mux */
20
&2misc vm=%vm_dp vd=%vd_dp q=0
24
21
+ @2misc_q1 .... ... .. . .. size:2 .. .... . .... . . . .... \
25
+static bool clock_mux_is_enabled(CprmanClockMuxState *mux)
22
+ &2misc vm=%vm_dp vd=%vd_dp q=1
26
+{
23
27
+ return FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, ENABLE);
24
VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc
28
+}
25
26
VPADDL_S 1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc
27
VPADDL_U 1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc
28
29
+ AESE 1111 001 11 . 11 .. 00 .... 0 0110 0 . 0 .... @2misc_q1
30
+ AESD 1111 001 11 . 11 .. 00 .... 0 0110 1 . 0 .... @2misc_q1
31
+ AESMC 1111 001 11 . 11 .. 00 .... 0 0111 0 . 0 .... @2misc_q1
32
+ AESIMC 1111 001 11 . 11 .. 00 .... 0 0111 1 . 0 .... @2misc_q1
33
+
29
+
34
VMVN 1111 001 11 . 11 .. 00 .... 0 1011 . . 0 .... @2misc
30
static void clock_mux_update(CprmanClockMuxState *mux)
35
31
{
36
VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc
32
- clock_update(mux->out, 0);
37
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
33
+ uint64_t freq;
38
VCLE0 1111 001 11 . 11 .. 01 .... 0 0011 . . 0 .... @2misc
34
+ uint32_t div, src = FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, SRC);
39
VCLT0 1111 001 11 . 11 .. 01 .... 0 0100 . . 0 .... @2misc
35
+ bool enabled = clock_mux_is_enabled(mux);
40
41
+ SHA1H 1111 001 11 . 11 .. 01 .... 0 0101 1 . 0 .... @2misc_q1
42
+
36
+
43
VABS 1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc
37
+ *mux->reg_ctl = FIELD_DP32(*mux->reg_ctl, CM_CLOCKx_CTL, BUSY, enabled);
44
VNEG 1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc
45
46
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
47
48
VSHLL 1111 001 11 . 11 .. 10 .... 0 0110 0 . 0 .... @2misc_q0
49
50
+ SHA1SU1 1111 001 11 . 11 .. 10 .... 0 0111 0 . 0 .... @2misc_q1
51
+ SHA256SU0 1111 001 11 . 11 .. 10 .... 0 0111 1 . 0 .... @2misc_q1
52
+
38
+
53
VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0
39
+ if (!enabled) {
54
VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0
40
+ clock_update(mux->out, 0);
55
]
41
+ return;
56
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/target/arm/translate-neon.inc.c
59
+++ b/target/arm/translate-neon.inc.c
60
@@ -XXX,XX +XXX,XX @@ static bool trans_VMVN(DisasContext *s, arg_2misc *a)
61
}
62
return do_2misc_vec(s, a, tcg_gen_gvec_not);
63
}
64
+
65
+#define WRAP_2M_3_OOL_FN(WRAPNAME, FUNC, DATA) \
66
+ static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \
67
+ uint32_t rm_ofs, uint32_t oprsz, \
68
+ uint32_t maxsz) \
69
+ { \
70
+ tcg_gen_gvec_3_ool(rd_ofs, rd_ofs, rm_ofs, oprsz, maxsz, \
71
+ DATA, FUNC); \
72
+ }
42
+ }
73
+
43
+
74
+#define WRAP_2M_2_OOL_FN(WRAPNAME, FUNC, DATA) \
44
+ freq = clock_get_hz(mux->srcs[src]);
75
+ static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \
45
+
76
+ uint32_t rm_ofs, uint32_t oprsz, \
46
+ if (mux->int_bits == 0 && mux->frac_bits == 0) {
77
+ uint32_t maxsz) \
47
+ clock_update_hz(mux->out, freq);
78
+ { \
48
+ return;
79
+ tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, oprsz, maxsz, DATA, FUNC); \
80
+ }
49
+ }
81
+
50
+
82
+WRAP_2M_3_OOL_FN(gen_AESE, gen_helper_crypto_aese, 0)
51
+ /*
83
+WRAP_2M_3_OOL_FN(gen_AESD, gen_helper_crypto_aese, 1)
52
+ * The divider has an integer and a fractional part. The size of each part
84
+WRAP_2M_2_OOL_FN(gen_AESMC, gen_helper_crypto_aesmc, 0)
53
+ * varies with the muxes (int_bits and frac_bits). Both parts are
85
+WRAP_2M_2_OOL_FN(gen_AESIMC, gen_helper_crypto_aesmc, 1)
54
+ * concatenated, with the integer part always starting at bit 12.
86
+WRAP_2M_2_OOL_FN(gen_SHA1H, gen_helper_crypto_sha1h, 0)
55
+ *
87
+WRAP_2M_2_OOL_FN(gen_SHA1SU1, gen_helper_crypto_sha1su1, 0)
56
+ * 31 12 11 0
88
+WRAP_2M_2_OOL_FN(gen_SHA256SU0, gen_helper_crypto_sha256su0, 0)
57
+ * ------------------------------
58
+ * CM_DIV | | int | frac | |
59
+ * ------------------------------
60
+ * <-----> <------>
61
+ * int_bits frac_bits
62
+ */
63
+ div = extract32(*mux->reg_div,
64
+ R_CM_CLOCKx_DIV_FRAC_LENGTH - mux->frac_bits,
65
+ mux->int_bits + mux->frac_bits);
89
+
66
+
90
+#define DO_2M_CRYPTO(INSN, FEATURE, SIZE) \
67
+ if (!div) {
91
+ static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
68
+ clock_update(mux->out, 0);
92
+ { \
69
+ return;
93
+ if (!dc_isar_feature(FEATURE, s) || a->size != SIZE) { \
94
+ return false; \
95
+ } \
96
+ return do_2misc_vec(s, a, gen_##INSN); \
97
+ }
70
+ }
98
+
71
+
99
+DO_2M_CRYPTO(AESE, aa32_aes, 0)
72
+ freq = muldiv64(freq, 1 << mux->frac_bits, div);
100
+DO_2M_CRYPTO(AESD, aa32_aes, 0)
73
+
101
+DO_2M_CRYPTO(AESMC, aa32_aes, 0)
74
+ clock_update_hz(mux->out, freq);
102
+DO_2M_CRYPTO(AESIMC, aa32_aes, 0)
75
}
103
+DO_2M_CRYPTO(SHA1H, aa32_sha1, 2)
76
104
+DO_2M_CRYPTO(SHA1SU1, aa32_sha1, 2)
77
static void clock_mux_src_update(void *opaque)
105
+DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2)
106
diff --git a/target/arm/translate.c b/target/arm/translate.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/translate.c
109
+++ b/target/arm/translate.c
110
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
111
{
78
{
112
int op;
79
CprmanClockMuxState **backref = opaque;
113
int q;
80
CprmanClockMuxState *s = *backref;
114
- int rd, rm, rd_ofs, rm_ofs;
81
+ CprmanClockMuxSource src = backref - s->backref;
115
+ int rd, rm;
82
+
116
int size;
83
+ if (FIELD_EX32(*s->reg_ctl, CM_CLOCKx_CTL, SRC) != src) {
117
int pass;
84
+ return;
118
int u;
85
+ }
119
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
86
120
VFP_DREG_D(rd, insn);
87
clock_mux_update(s);
121
VFP_DREG_M(rm, insn);
88
}
122
size = (insn >> 20) & 3;
123
- rd_ofs = neon_reg_offset(rd, 0);
124
- rm_ofs = neon_reg_offset(rm, 0);
125
126
if ((insn & (1 << 23)) == 0) {
127
/* Three register same length: handled by decodetree */
128
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
129
case NEON_2RM_VCLE0:
130
case NEON_2RM_VCGE0:
131
case NEON_2RM_VCLT0:
132
+ case NEON_2RM_AESE: case NEON_2RM_AESMC:
133
+ case NEON_2RM_SHA1H:
134
+ case NEON_2RM_SHA1SU1:
135
/* handled by decodetree */
136
return 1;
137
case NEON_2RM_VTRN:
138
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
139
goto elementwise;
140
}
141
break;
142
- case NEON_2RM_AESE: case NEON_2RM_AESMC:
143
- if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) {
144
- return 1;
145
- }
146
- /*
147
- * Bit 6 is the lowest opcode bit; it distinguishes
148
- * between encryption (AESE/AESMC) and decryption
149
- * (AESD/AESIMC).
150
- */
151
- if (op == NEON_2RM_AESE) {
152
- tcg_gen_gvec_3_ool(vfp_reg_offset(true, rd),
153
- vfp_reg_offset(true, rd),
154
- vfp_reg_offset(true, rm),
155
- 16, 16, extract32(insn, 6, 1),
156
- gen_helper_crypto_aese);
157
- } else {
158
- tcg_gen_gvec_2_ool(vfp_reg_offset(true, rd),
159
- vfp_reg_offset(true, rm),
160
- 16, 16, extract32(insn, 6, 1),
161
- gen_helper_crypto_aesmc);
162
- }
163
- break;
164
- case NEON_2RM_SHA1H:
165
- if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) {
166
- return 1;
167
- }
168
- tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0,
169
- gen_helper_crypto_sha1h);
170
- break;
171
- case NEON_2RM_SHA1SU1:
172
- if ((rm | rd) & 1) {
173
- return 1;
174
- }
175
- /* bit 6 (q): set -> SHA256SU0, cleared -> SHA1SU1 */
176
- if (q) {
177
- if (!dc_isar_feature(aa32_sha2, s)) {
178
- return 1;
179
- }
180
- } else if (!dc_isar_feature(aa32_sha1, s)) {
181
- return 1;
182
- }
183
- tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0,
184
- q ? gen_helper_crypto_sha256su0
185
- : gen_helper_crypto_sha1su1);
186
- break;
187
188
default:
189
elementwise:
190
--
89
--
191
2.20.1
90
2.20.1
192
91
193
92
diff view generated by jsdifflib
1
Convert the Neon narrowing moves VMQNV, VQMOVN, VQMOVUN in the 2-reg-misc
1
From: Luc Michel <luc@lmichel.fr>
2
group to decodetree.
2
3
3
This simple mux sits between the PLL channels and the DSI0E and DSI0P
4
clock muxes. This mux selects between PLLA-DSI0 and PLLD-DSI0 channel
5
and outputs the selected signal to source number 4 of DSI0E/P clock
6
muxes. It is controlled by the cm_dsi0hsck register.
7
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Signed-off-by: Luc Michel <luc@lmichel.fr>
11
Tested-by: Guenter Roeck <linux@roeck-us.net>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200616170844.13318-5-peter.maydell@linaro.org
7
---
13
---
8
target/arm/neon-dp.decode | 9 ++++
14
include/hw/misc/bcm2835_cprman.h | 15 +++++
9
target/arm/translate-neon.inc.c | 59 ++++++++++++++++++++++++
15
include/hw/misc/bcm2835_cprman_internals.h | 6 ++
10
target/arm/translate.c | 81 +--------------------------------
16
hw/misc/bcm2835_cprman.c | 74 +++++++++++++++++++++-
11
3 files changed, 70 insertions(+), 79 deletions(-)
17
3 files changed, 94 insertions(+), 1 deletion(-)
12
18
13
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
19
diff --git a/include/hw/misc/bcm2835_cprman.h b/include/hw/misc/bcm2835_cprman.h
14
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/neon-dp.decode
21
--- a/include/hw/misc/bcm2835_cprman.h
16
+++ b/target/arm/neon-dp.decode
22
+++ b/include/hw/misc/bcm2835_cprman.h
17
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
23
@@ -XXX,XX +XXX,XX @@ typedef struct CprmanClockMuxState {
18
24
struct CprmanClockMuxState *backref[CPRMAN_NUM_CLOCK_MUX_SRC];
19
@2misc .... ... .. . .. size:2 .. .... . .... q:1 . . .... \
25
} CprmanClockMuxState;
20
&2misc vm=%vm_dp vd=%vd_dp
26
21
+ @2misc_q0 .... ... .. . .. size:2 .. .... . .... . . . .... \
27
+typedef struct CprmanDsi0HsckMuxState {
22
+ &2misc vm=%vm_dp vd=%vd_dp q=0
28
+ /*< private >*/
23
29
+ DeviceState parent_obj;
24
VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc
30
+
25
31
+ /*< public >*/
26
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
32
+ CprmanClockMux id;
27
33
+
28
VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc
34
+ uint32_t *reg_cm;
29
VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc
35
+
30
+
36
+ Clock *plla_in;
31
+ VMOVN 1111 001 11 . 11 .. 10 .... 0 0100 0 . 0 .... @2misc_q0
37
+ Clock *plld_in;
32
+ # VQMOVUN: unsigned result (source is always signed)
38
+ Clock *out;
33
+ VQMOVUN 1111 001 11 . 11 .. 10 .... 0 0100 1 . 0 .... @2misc_q0
39
+} CprmanDsi0HsckMuxState;
34
+ # VQMOVN: signed result, source may be signed (_S) or unsigned (_U)
40
+
35
+ VQMOVN_S 1111 001 11 . 11 .. 10 .... 0 0101 0 . 0 .... @2misc_q0
41
struct BCM2835CprmanState {
36
+ VQMOVN_U 1111 001 11 . 11 .. 10 .... 0 0101 1 . 0 .... @2misc_q0
42
/*< private >*/
37
]
43
SysBusDevice parent_obj;
38
44
@@ -XXX,XX +XXX,XX @@ struct BCM2835CprmanState {
39
# Subgroup for size != 0b11
45
CprmanPllState plls[CPRMAN_NUM_PLL];
40
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
46
CprmanPllChannelState channels[CPRMAN_NUM_PLL_CHANNEL];
47
CprmanClockMuxState clock_muxes[CPRMAN_NUM_CLOCK_MUX];
48
+ CprmanDsi0HsckMuxState dsi0hsck_mux;
49
50
uint32_t regs[CPRMAN_NUM_REGS];
51
uint32_t xosc_freq;
52
diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/bcm2835_cprman_internals.h
41
index XXXXXXX..XXXXXXX 100644
53
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/translate-neon.inc.c
54
--- a/include/hw/misc/bcm2835_cprman_internals.h
43
+++ b/target/arm/translate-neon.inc.c
55
+++ b/include/hw/misc/bcm2835_cprman_internals.h
44
@@ -XXX,XX +XXX,XX @@ static bool trans_VZIP(DisasContext *s, arg_2misc *a)
56
@@ -XXX,XX +XXX,XX @@
45
};
57
#define TYPE_CPRMAN_PLL "bcm2835-cprman-pll"
46
return do_zip_uzp(s, a, fn[a->q][a->size]);
58
#define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel"
59
#define TYPE_CPRMAN_CLOCK_MUX "bcm2835-cprman-clock-mux"
60
+#define TYPE_CPRMAN_DSI0HSCK_MUX "bcm2835-cprman-dsi0hsck-mux"
61
62
DECLARE_INSTANCE_CHECKER(CprmanPllState, CPRMAN_PLL,
63
TYPE_CPRMAN_PLL)
64
@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(CprmanPllChannelState, CPRMAN_PLL_CHANNEL,
65
TYPE_CPRMAN_PLL_CHANNEL)
66
DECLARE_INSTANCE_CHECKER(CprmanClockMuxState, CPRMAN_CLOCK_MUX,
67
TYPE_CPRMAN_CLOCK_MUX)
68
+DECLARE_INSTANCE_CHECKER(CprmanDsi0HsckMuxState, CPRMAN_DSI0HSCK_MUX,
69
+ TYPE_CPRMAN_DSI0HSCK_MUX)
70
71
/* Register map */
72
73
@@ -XXX,XX +XXX,XX @@ REG32(CM_LOCK, 0x114)
74
FIELD(CM_LOCK, FLOCKB, 9, 1)
75
FIELD(CM_LOCK, FLOCKA, 8, 1)
76
77
+REG32(CM_DSI0HSCK, 0x120)
78
+ FIELD(CM_DSI0HSCK, SELPLLD, 0, 1)
79
+
80
/*
81
* This field is common to all registers. Each register write value must match
82
* the CPRMAN_PASSWORD magic value in its 8 MSB.
83
diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c
84
index XXXXXXX..XXXXXXX 100644
85
--- a/hw/misc/bcm2835_cprman.c
86
+++ b/hw/misc/bcm2835_cprman.c
87
@@ -XXX,XX +XXX,XX @@ static const TypeInfo cprman_clock_mux_info = {
88
};
89
90
91
+/* DSI0HSCK mux */
92
+
93
+static void dsi0hsck_mux_update(CprmanDsi0HsckMuxState *s)
94
+{
95
+ bool src_is_plld = FIELD_EX32(*s->reg_cm, CM_DSI0HSCK, SELPLLD);
96
+ Clock *src = src_is_plld ? s->plld_in : s->plla_in;
97
+
98
+ clock_update(s->out, clock_get(src));
99
+}
100
+
101
+static void dsi0hsck_mux_in_update(void *opaque)
102
+{
103
+ dsi0hsck_mux_update(CPRMAN_DSI0HSCK_MUX(opaque));
104
+}
105
+
106
+static void dsi0hsck_mux_init(Object *obj)
107
+{
108
+ CprmanDsi0HsckMuxState *s = CPRMAN_DSI0HSCK_MUX(obj);
109
+ DeviceState *dev = DEVICE(obj);
110
+
111
+ s->plla_in = qdev_init_clock_in(dev, "plla-in", dsi0hsck_mux_in_update, s);
112
+ s->plld_in = qdev_init_clock_in(dev, "plld-in", dsi0hsck_mux_in_update, s);
113
+ s->out = qdev_init_clock_out(DEVICE(s), "out");
114
+}
115
+
116
+static const VMStateDescription dsi0hsck_mux_vmstate = {
117
+ .name = TYPE_CPRMAN_DSI0HSCK_MUX,
118
+ .version_id = 1,
119
+ .minimum_version_id = 1,
120
+ .fields = (VMStateField[]) {
121
+ VMSTATE_CLOCK(plla_in, CprmanDsi0HsckMuxState),
122
+ VMSTATE_CLOCK(plld_in, CprmanDsi0HsckMuxState),
123
+ VMSTATE_END_OF_LIST()
124
+ }
125
+};
126
+
127
+static void dsi0hsck_mux_class_init(ObjectClass *klass, void *data)
128
+{
129
+ DeviceClass *dc = DEVICE_CLASS(klass);
130
+
131
+ dc->vmsd = &dsi0hsck_mux_vmstate;
132
+}
133
+
134
+static const TypeInfo cprman_dsi0hsck_mux_info = {
135
+ .name = TYPE_CPRMAN_DSI0HSCK_MUX,
136
+ .parent = TYPE_DEVICE,
137
+ .instance_size = sizeof(CprmanDsi0HsckMuxState),
138
+ .class_init = dsi0hsck_mux_class_init,
139
+ .instance_init = dsi0hsck_mux_init,
140
+};
141
+
142
+
143
/* CPRMAN "top level" model */
144
145
static uint32_t get_cm_lock(const BCM2835CprmanState *s)
146
@@ -XXX,XX +XXX,XX @@ static void cprman_write(void *opaque, hwaddr offset,
147
case R_CM_EMMC2CTL ... R_CM_EMMC2DIV:
148
update_mux_from_cm(s, idx);
149
break;
150
+
151
+ case R_CM_DSI0HSCK:
152
+ dsi0hsck_mux_update(&s->dsi0hsck_mux);
153
+ break;
154
}
47
}
155
}
48
+
156
49
+static bool do_vmovn(DisasContext *s, arg_2misc *a,
157
@@ -XXX,XX +XXX,XX @@ static void cprman_reset(DeviceState *dev)
50
+ NeonGenNarrowEnvFn *narrowfn)
158
device_cold_reset(DEVICE(&s->channels[i]));
51
+{
159
}
52
+ TCGv_i64 rm;
160
53
+ TCGv_i32 rd0, rd1;
161
+ device_cold_reset(DEVICE(&s->dsi0hsck_mux));
54
+
162
+
55
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
163
for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
56
+ return false;
164
device_cold_reset(DEVICE(&s->clock_muxes[i]));
165
}
166
@@ -XXX,XX +XXX,XX @@ static void cprman_init(Object *obj)
167
set_pll_channel_init_info(s, &s->channels[i], i);
168
}
169
170
+ object_initialize_child(obj, "dsi0hsck-mux",
171
+ &s->dsi0hsck_mux, TYPE_CPRMAN_DSI0HSCK_MUX);
172
+ s->dsi0hsck_mux.reg_cm = &s->regs[R_CM_DSI0HSCK];
173
+
174
for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
175
char *alias;
176
177
@@ -XXX,XX +XXX,XX @@ static void connect_mux_sources(BCM2835CprmanState *s,
178
if (mapping == CPRMAN_CLOCK_SRC_FORCE_GROUND) {
179
src = s->gnd;
180
} else if (mapping == CPRMAN_CLOCK_SRC_DSI0HSCK) {
181
- src = s->gnd; /* TODO */
182
+ src = s->dsi0hsck_mux.out;
183
} else if (i < CPRMAN_CLOCK_SRC_PLLA) {
184
src = CLK_SRC_MAPPING[i];
185
} else {
186
@@ -XXX,XX +XXX,XX @@ static void cprman_realize(DeviceState *dev, Error **errp)
187
}
188
}
189
190
+ clock_set_source(s->dsi0hsck_mux.plla_in,
191
+ s->channels[CPRMAN_PLLA_CHANNEL_DSI0].out);
192
+ clock_set_source(s->dsi0hsck_mux.plld_in,
193
+ s->channels[CPRMAN_PLLD_CHANNEL_DSI0].out);
194
+
195
+ if (!qdev_realize(DEVICE(&s->dsi0hsck_mux), NULL, errp)) {
196
+ return;
57
+ }
197
+ }
58
+
198
+
59
+ /* UNDEF accesses to D16-D31 if they don't exist. */
199
for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
60
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
200
CprmanClockMuxState *clock_mux = &s->clock_muxes[i];
61
+ ((a->vd | a->vm) & 0x10)) {
201
62
+ return false;
202
@@ -XXX,XX +XXX,XX @@ static void cprman_register_types(void)
63
+ }
203
type_register_static(&cprman_pll_info);
64
+
204
type_register_static(&cprman_pll_channel_info);
65
+ if (a->vm & 1) {
205
type_register_static(&cprman_clock_mux_info);
66
+ return false;
206
+ type_register_static(&cprman_dsi0hsck_mux_info);
67
+ }
68
+
69
+ if (!narrowfn) {
70
+ return false;
71
+ }
72
+
73
+ if (!vfp_access_check(s)) {
74
+ return true;
75
+ }
76
+
77
+ rm = tcg_temp_new_i64();
78
+ rd0 = tcg_temp_new_i32();
79
+ rd1 = tcg_temp_new_i32();
80
+
81
+ neon_load_reg64(rm, a->vm);
82
+ narrowfn(rd0, cpu_env, rm);
83
+ neon_load_reg64(rm, a->vm + 1);
84
+ narrowfn(rd1, cpu_env, rm);
85
+ neon_store_reg(a->vd, 0, rd0);
86
+ neon_store_reg(a->vd, 1, rd1);
87
+ tcg_temp_free_i64(rm);
88
+ return true;
89
+}
90
+
91
+#define DO_VMOVN(INSN, FUNC) \
92
+ static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
93
+ { \
94
+ static NeonGenNarrowEnvFn * const narrowfn[] = { \
95
+ FUNC##8, \
96
+ FUNC##16, \
97
+ FUNC##32, \
98
+ NULL, \
99
+ }; \
100
+ return do_vmovn(s, a, narrowfn[a->size]); \
101
+ }
102
+
103
+DO_VMOVN(VMOVN, gen_neon_narrow_u)
104
+DO_VMOVN(VQMOVUN, gen_helper_neon_unarrow_sat)
105
+DO_VMOVN(VQMOVN_S, gen_helper_neon_narrow_sat_s)
106
+DO_VMOVN(VQMOVN_U, gen_helper_neon_narrow_sat_u)
107
diff --git a/target/arm/translate.c b/target/arm/translate.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/target/arm/translate.c
110
+++ b/target/arm/translate.c
111
@@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
112
tcg_temp_free_i32(rd);
113
}
207
}
114
208
115
-static inline void gen_neon_narrow(int size, TCGv_i32 dest, TCGv_i64 src)
209
type_init(cprman_register_types);
116
-{
117
- switch (size) {
118
- case 0: gen_helper_neon_narrow_u8(dest, src); break;
119
- case 1: gen_helper_neon_narrow_u16(dest, src); break;
120
- case 2: tcg_gen_extrl_i64_i32(dest, src); break;
121
- default: abort();
122
- }
123
-}
124
-
125
-static inline void gen_neon_narrow_sats(int size, TCGv_i32 dest, TCGv_i64 src)
126
-{
127
- switch (size) {
128
- case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break;
129
- case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break;
130
- case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break;
131
- default: abort();
132
- }
133
-}
134
-
135
-static inline void gen_neon_narrow_satu(int size, TCGv_i32 dest, TCGv_i64 src)
136
-{
137
- switch (size) {
138
- case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break;
139
- case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break;
140
- case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break;
141
- default: abort();
142
- }
143
-}
144
-
145
-static inline void gen_neon_unarrow_sats(int size, TCGv_i32 dest, TCGv_i64 src)
146
-{
147
- switch (size) {
148
- case 0: gen_helper_neon_unarrow_sat8(dest, cpu_env, src); break;
149
- case 1: gen_helper_neon_unarrow_sat16(dest, cpu_env, src); break;
150
- case 2: gen_helper_neon_unarrow_sat32(dest, cpu_env, src); break;
151
- default: abort();
152
- }
153
-}
154
-
155
static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u)
156
{
157
if (u) {
158
@@ -XXX,XX +XXX,XX @@ static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u)
159
tcg_temp_free_i32(src);
160
}
161
162
-static void gen_neon_narrow_op(int op, int u, int size,
163
- TCGv_i32 dest, TCGv_i64 src)
164
-{
165
- if (op) {
166
- if (u) {
167
- gen_neon_unarrow_sats(size, dest, src);
168
- } else {
169
- gen_neon_narrow(size, dest, src);
170
- }
171
- } else {
172
- if (u) {
173
- gen_neon_narrow_satu(size, dest, src);
174
- } else {
175
- gen_neon_narrow_sats(size, dest, src);
176
- }
177
- }
178
-}
179
-
180
/* Symbolic constants for op fields for Neon 2-register miscellaneous.
181
* The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B
182
* table A7-13.
183
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
184
!arm_dc_feature(s, ARM_FEATURE_V8)) {
185
return 1;
186
}
187
- if ((op != NEON_2RM_VMOVN && op != NEON_2RM_VQMOVN) &&
188
- q && ((rm | rd) & 1)) {
189
+ if (q && ((rm | rd) & 1)) {
190
return 1;
191
}
192
switch (op) {
193
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
194
case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U:
195
case NEON_2RM_VUZP:
196
case NEON_2RM_VZIP:
197
+ case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN:
198
/* handled by decodetree */
199
return 1;
200
case NEON_2RM_VTRN:
201
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
202
goto elementwise;
203
}
204
break;
205
- case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN:
206
- /* also VQMOVUN; op field and mnemonics don't line up */
207
- if (rm & 1) {
208
- return 1;
209
- }
210
- tmp2 = NULL;
211
- for (pass = 0; pass < 2; pass++) {
212
- neon_load_reg64(cpu_V0, rm + pass);
213
- tmp = tcg_temp_new_i32();
214
- gen_neon_narrow_op(op == NEON_2RM_VMOVN, q, size,
215
- tmp, cpu_V0);
216
- if (pass == 0) {
217
- tmp2 = tmp;
218
- } else {
219
- neon_store_reg(rd, 0, tmp2);
220
- neon_store_reg(rd, 1, tmp);
221
- }
222
- }
223
- break;
224
case NEON_2RM_VSHLL:
225
if (q || (rd & 1)) {
226
return 1;
227
--
210
--
228
2.20.1
211
2.20.1
229
212
230
213
diff view generated by jsdifflib
1
Convert the remaining ops in the Neon 2-reg-misc group which
1
From: Luc Michel <luc@lmichel.fr>
2
can be implemented simply with our do_2misc() helper.
2
3
3
Those reset values have been extracted from a Raspberry Pi 3 model B
4
v1.2, using the 2020-08-20 version of raspios. The dump was done using
5
the debugfs interface of the CPRMAN driver in Linux (under
6
'/sys/kernel/debug/clk'). Each exposed clock tree stage (PLLs, channels
7
and muxes) can be observed by reading the 'regdump' file (e.g.
8
'plla/regdump').
9
10
Those values are set by the Raspberry Pi firmware at boot time (Linux
11
expects them to be set when it boots up).
12
13
Some stages are not exposed by the Linux driver (e.g. the PLL B). For
14
those, the reset values are unknown and left to 0 which implies a
15
disabled output.
16
17
Once booted in QEMU, the final clock tree is very similar to the one
18
visible on real hardware. The differences come from some unimplemented
19
devices for which the driver simply disable the corresponding clock.
20
21
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
22
Signed-off-by: Luc Michel <luc@lmichel.fr>
23
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
24
Tested-by: Guenter Roeck <linux@roeck-us.net>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200616170844.13318-14-peter.maydell@linaro.org
7
---
26
---
8
target/arm/neon-dp.decode | 10 +++++
27
include/hw/misc/bcm2835_cprman_internals.h | 269 +++++++++++++++++++++
9
target/arm/translate-neon.inc.c | 69 +++++++++++++++++++++++++++++++++
28
hw/misc/bcm2835_cprman.c | 31 +++
10
target/arm/translate.c | 38 ++++--------------
29
2 files changed, 300 insertions(+)
11
3 files changed, 86 insertions(+), 31 deletions(-)
30
12
31
diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/bcm2835_cprman_internals.h
13
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
14
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/neon-dp.decode
33
--- a/include/hw/misc/bcm2835_cprman_internals.h
16
+++ b/target/arm/neon-dp.decode
34
+++ b/include/hw/misc/bcm2835_cprman_internals.h
17
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
35
@@ -XXX,XX +XXX,XX @@ static inline void set_clock_mux_init_info(BCM2835CprmanState *s,
18
AESMC 1111 001 11 . 11 .. 00 .... 0 0111 0 . 0 .... @2misc_q1
36
mux->frac_bits = CLOCK_MUX_INIT_INFO[id].frac_bits;
19
AESIMC 1111 001 11 . 11 .. 00 .... 0 0111 1 . 0 .... @2misc_q1
37
}
20
38
21
+ VCLS 1111 001 11 . 11 .. 00 .... 0 1000 . . 0 .... @2misc
39
+
22
+ VCLZ 1111 001 11 . 11 .. 00 .... 0 1001 . . 0 .... @2misc
40
+/*
23
+ VCNT 1111 001 11 . 11 .. 00 .... 0 1010 . . 0 .... @2misc
41
+ * Object reset info
24
+
42
+ * Those values have been dumped from a Raspberry Pi 3 Model B v1.2 using the
25
VMVN 1111 001 11 . 11 .. 00 .... 0 1011 . . 0 .... @2misc
43
+ * clk debugfs interface in Linux.
26
44
+ */
27
VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc
45
+typedef struct PLLResetInfo {
28
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
46
+ uint32_t cm;
29
VABS 1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc
47
+ uint32_t a2w_ctrl;
30
VNEG 1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc
48
+ uint32_t a2w_ana[4];
31
49
+ uint32_t a2w_frac;
32
+ VABS_F 1111 001 11 . 11 .. 01 .... 0 1110 . . 0 .... @2misc
50
+} PLLResetInfo;
33
+ VNEG_F 1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc
51
+
34
+
52
+static const PLLResetInfo PLL_RESET_INFO[] = {
35
VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc
53
+ [CPRMAN_PLLA] = {
36
VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc
54
+ .cm = 0x0000008a,
37
55
+ .a2w_ctrl = 0x0002103a,
38
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
56
+ .a2w_frac = 0x00098000,
39
57
+ .a2w_ana = { 0x00000000, 0x00144000, 0x00000000, 0x00000100 }
40
VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0
58
+ },
41
VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0
59
+
42
+
60
+ [CPRMAN_PLLC] = {
43
+ VRECPE 1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc
61
+ .cm = 0x00000228,
44
+ VRSQRTE 1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc
62
+ .a2w_ctrl = 0x0002103e,
45
]
63
+ .a2w_frac = 0x00080000,
46
64
+ .a2w_ana = { 0x00000000, 0x00144000, 0x00000000, 0x00000100 }
47
# Subgroup for size != 0b11
65
+ },
48
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
66
+
67
+ [CPRMAN_PLLD] = {
68
+ .cm = 0x0000020a,
69
+ .a2w_ctrl = 0x00021034,
70
+ .a2w_frac = 0x00015556,
71
+ .a2w_ana = { 0x00000000, 0x00144000, 0x00000000, 0x00000100 }
72
+ },
73
+
74
+ [CPRMAN_PLLH] = {
75
+ .cm = 0x00000000,
76
+ .a2w_ctrl = 0x0002102d,
77
+ .a2w_frac = 0x00000000,
78
+ .a2w_ana = { 0x00900000, 0x0000000c, 0x00000000, 0x00000000 }
79
+ },
80
+
81
+ [CPRMAN_PLLB] = {
82
+ /* unknown */
83
+ .cm = 0x00000000,
84
+ .a2w_ctrl = 0x00000000,
85
+ .a2w_frac = 0x00000000,
86
+ .a2w_ana = { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
87
+ }
88
+};
89
+
90
+typedef struct PLLChannelResetInfo {
91
+ /*
92
+ * Even though a PLL channel has a CM register, it shares it with its
93
+ * parent PLL. The parent already takes care of the reset value.
94
+ */
95
+ uint32_t a2w_ctrl;
96
+} PLLChannelResetInfo;
97
+
98
+static const PLLChannelResetInfo PLL_CHANNEL_RESET_INFO[] = {
99
+ [CPRMAN_PLLA_CHANNEL_DSI0] = { .a2w_ctrl = 0x00000100 },
100
+ [CPRMAN_PLLA_CHANNEL_CORE] = { .a2w_ctrl = 0x00000003 },
101
+ [CPRMAN_PLLA_CHANNEL_PER] = { .a2w_ctrl = 0x00000000 }, /* unknown */
102
+ [CPRMAN_PLLA_CHANNEL_CCP2] = { .a2w_ctrl = 0x00000100 },
103
+
104
+ [CPRMAN_PLLC_CHANNEL_CORE2] = { .a2w_ctrl = 0x00000100 },
105
+ [CPRMAN_PLLC_CHANNEL_CORE1] = { .a2w_ctrl = 0x00000100 },
106
+ [CPRMAN_PLLC_CHANNEL_PER] = { .a2w_ctrl = 0x00000002 },
107
+ [CPRMAN_PLLC_CHANNEL_CORE0] = { .a2w_ctrl = 0x00000002 },
108
+
109
+ [CPRMAN_PLLD_CHANNEL_DSI0] = { .a2w_ctrl = 0x00000100 },
110
+ [CPRMAN_PLLD_CHANNEL_CORE] = { .a2w_ctrl = 0x00000004 },
111
+ [CPRMAN_PLLD_CHANNEL_PER] = { .a2w_ctrl = 0x00000004 },
112
+ [CPRMAN_PLLD_CHANNEL_DSI1] = { .a2w_ctrl = 0x00000100 },
113
+
114
+ [CPRMAN_PLLH_CHANNEL_AUX] = { .a2w_ctrl = 0x00000004 },
115
+ [CPRMAN_PLLH_CHANNEL_RCAL] = { .a2w_ctrl = 0x00000000 },
116
+ [CPRMAN_PLLH_CHANNEL_PIX] = { .a2w_ctrl = 0x00000000 },
117
+
118
+ [CPRMAN_PLLB_CHANNEL_ARM] = { .a2w_ctrl = 0x00000000 }, /* unknown */
119
+};
120
+
121
+typedef struct ClockMuxResetInfo {
122
+ uint32_t cm_ctl;
123
+ uint32_t cm_div;
124
+} ClockMuxResetInfo;
125
+
126
+static const ClockMuxResetInfo CLOCK_MUX_RESET_INFO[] = {
127
+ [CPRMAN_CLOCK_GNRIC] = {
128
+ .cm_ctl = 0, /* unknown */
129
+ .cm_div = 0
130
+ },
131
+
132
+ [CPRMAN_CLOCK_VPU] = {
133
+ .cm_ctl = 0x00000245,
134
+ .cm_div = 0x00003000,
135
+ },
136
+
137
+ [CPRMAN_CLOCK_SYS] = {
138
+ .cm_ctl = 0, /* unknown */
139
+ .cm_div = 0
140
+ },
141
+
142
+ [CPRMAN_CLOCK_PERIA] = {
143
+ .cm_ctl = 0, /* unknown */
144
+ .cm_div = 0
145
+ },
146
+
147
+ [CPRMAN_CLOCK_PERII] = {
148
+ .cm_ctl = 0, /* unknown */
149
+ .cm_div = 0
150
+ },
151
+
152
+ [CPRMAN_CLOCK_H264] = {
153
+ .cm_ctl = 0x00000244,
154
+ .cm_div = 0x00003000,
155
+ },
156
+
157
+ [CPRMAN_CLOCK_ISP] = {
158
+ .cm_ctl = 0x00000244,
159
+ .cm_div = 0x00003000,
160
+ },
161
+
162
+ [CPRMAN_CLOCK_V3D] = {
163
+ .cm_ctl = 0, /* unknown */
164
+ .cm_div = 0
165
+ },
166
+
167
+ [CPRMAN_CLOCK_CAM0] = {
168
+ .cm_ctl = 0x00000000,
169
+ .cm_div = 0x00000000,
170
+ },
171
+
172
+ [CPRMAN_CLOCK_CAM1] = {
173
+ .cm_ctl = 0x00000000,
174
+ .cm_div = 0x00000000,
175
+ },
176
+
177
+ [CPRMAN_CLOCK_CCP2] = {
178
+ .cm_ctl = 0, /* unknown */
179
+ .cm_div = 0
180
+ },
181
+
182
+ [CPRMAN_CLOCK_DSI0E] = {
183
+ .cm_ctl = 0x00000000,
184
+ .cm_div = 0x00000000,
185
+ },
186
+
187
+ [CPRMAN_CLOCK_DSI0P] = {
188
+ .cm_ctl = 0x00000000,
189
+ .cm_div = 0x00000000,
190
+ },
191
+
192
+ [CPRMAN_CLOCK_DPI] = {
193
+ .cm_ctl = 0x00000000,
194
+ .cm_div = 0x00000000,
195
+ },
196
+
197
+ [CPRMAN_CLOCK_GP0] = {
198
+ .cm_ctl = 0x00000200,
199
+ .cm_div = 0x00000000,
200
+ },
201
+
202
+ [CPRMAN_CLOCK_GP1] = {
203
+ .cm_ctl = 0x00000096,
204
+ .cm_div = 0x00014000,
205
+ },
206
+
207
+ [CPRMAN_CLOCK_GP2] = {
208
+ .cm_ctl = 0x00000291,
209
+ .cm_div = 0x00249f00,
210
+ },
211
+
212
+ [CPRMAN_CLOCK_HSM] = {
213
+ .cm_ctl = 0x00000000,
214
+ .cm_div = 0x00000000,
215
+ },
216
+
217
+ [CPRMAN_CLOCK_OTP] = {
218
+ .cm_ctl = 0x00000091,
219
+ .cm_div = 0x00004000,
220
+ },
221
+
222
+ [CPRMAN_CLOCK_PCM] = {
223
+ .cm_ctl = 0x00000200,
224
+ .cm_div = 0x00000000,
225
+ },
226
+
227
+ [CPRMAN_CLOCK_PWM] = {
228
+ .cm_ctl = 0x00000200,
229
+ .cm_div = 0x00000000,
230
+ },
231
+
232
+ [CPRMAN_CLOCK_SLIM] = {
233
+ .cm_ctl = 0x00000200,
234
+ .cm_div = 0x00000000,
235
+ },
236
+
237
+ [CPRMAN_CLOCK_SMI] = {
238
+ .cm_ctl = 0x00000000,
239
+ .cm_div = 0x00000000,
240
+ },
241
+
242
+ [CPRMAN_CLOCK_TEC] = {
243
+ .cm_ctl = 0x00000000,
244
+ .cm_div = 0x00000000,
245
+ },
246
+
247
+ [CPRMAN_CLOCK_TD0] = {
248
+ .cm_ctl = 0, /* unknown */
249
+ .cm_div = 0
250
+ },
251
+
252
+ [CPRMAN_CLOCK_TD1] = {
253
+ .cm_ctl = 0, /* unknown */
254
+ .cm_div = 0
255
+ },
256
+
257
+ [CPRMAN_CLOCK_TSENS] = {
258
+ .cm_ctl = 0x00000091,
259
+ .cm_div = 0x0000a000,
260
+ },
261
+
262
+ [CPRMAN_CLOCK_TIMER] = {
263
+ .cm_ctl = 0x00000291,
264
+ .cm_div = 0x00013333,
265
+ },
266
+
267
+ [CPRMAN_CLOCK_UART] = {
268
+ .cm_ctl = 0x00000296,
269
+ .cm_div = 0x0000a6ab,
270
+ },
271
+
272
+ [CPRMAN_CLOCK_VEC] = {
273
+ .cm_ctl = 0x00000097,
274
+ .cm_div = 0x00002000,
275
+ },
276
+
277
+ [CPRMAN_CLOCK_PULSE] = {
278
+ .cm_ctl = 0, /* unknown */
279
+ .cm_div = 0
280
+ },
281
+
282
+ [CPRMAN_CLOCK_SDC] = {
283
+ .cm_ctl = 0x00004006,
284
+ .cm_div = 0x00003000,
285
+ },
286
+
287
+ [CPRMAN_CLOCK_ARM] = {
288
+ .cm_ctl = 0, /* unknown */
289
+ .cm_div = 0
290
+ },
291
+
292
+ [CPRMAN_CLOCK_AVEO] = {
293
+ .cm_ctl = 0x00000000,
294
+ .cm_div = 0x00000000,
295
+ },
296
+
297
+ [CPRMAN_CLOCK_EMMC] = {
298
+ .cm_ctl = 0x00000295,
299
+ .cm_div = 0x00006000,
300
+ },
301
+
302
+ [CPRMAN_CLOCK_EMMC2] = {
303
+ .cm_ctl = 0, /* unknown */
304
+ .cm_div = 0
305
+ },
306
+};
307
+
308
#endif
309
diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c
49
index XXXXXXX..XXXXXXX 100644
310
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/translate-neon.inc.c
311
--- a/hw/misc/bcm2835_cprman.c
51
+++ b/target/arm/translate-neon.inc.c
312
+++ b/hw/misc/bcm2835_cprman.c
52
@@ -XXX,XX +XXX,XX @@ static bool trans_VREV16(DisasContext *s, arg_2misc *a)
313
@@ -XXX,XX +XXX,XX @@
53
}
314
54
return do_2misc(s, a, gen_rev16);
315
/* PLL */
55
}
316
56
+
317
+static void pll_reset(DeviceState *dev)
57
+static bool trans_VCLS(DisasContext *s, arg_2misc *a)
58
+{
318
+{
59
+ static NeonGenOneOpFn * const fn[] = {
319
+ CprmanPllState *s = CPRMAN_PLL(dev);
60
+ gen_helper_neon_cls_s8,
320
+ const PLLResetInfo *info = &PLL_RESET_INFO[s->id];
61
+ gen_helper_neon_cls_s16,
321
+
62
+ gen_helper_neon_cls_s32,
322
+ *s->reg_cm = info->cm;
63
+ NULL,
323
+ *s->reg_a2w_ctrl = info->a2w_ctrl;
64
+ };
324
+ memcpy(s->reg_a2w_ana, info->a2w_ana, sizeof(info->a2w_ana));
65
+ return do_2misc(s, a, fn[a->size]);
325
+ *s->reg_a2w_frac = info->a2w_frac;
66
+}
326
+}
67
+
327
+
68
+static void do_VCLZ_32(TCGv_i32 rd, TCGv_i32 rm)
328
static bool pll_is_locked(const CprmanPllState *pll)
329
{
330
return !FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PWRDN)
331
@@ -XXX,XX +XXX,XX @@ static void pll_class_init(ObjectClass *klass, void *data)
332
{
333
DeviceClass *dc = DEVICE_CLASS(klass);
334
335
+ dc->reset = pll_reset;
336
dc->vmsd = &pll_vmstate;
337
}
338
339
@@ -XXX,XX +XXX,XX @@ static const TypeInfo cprman_pll_info = {
340
341
/* PLL channel */
342
343
+static void pll_channel_reset(DeviceState *dev)
69
+{
344
+{
70
+ tcg_gen_clzi_i32(rd, rm, 32);
345
+ CprmanPllChannelState *s = CPRMAN_PLL_CHANNEL(dev);
346
+ const PLLChannelResetInfo *info = &PLL_CHANNEL_RESET_INFO[s->id];
347
+
348
+ *s->reg_a2w_ctrl = info->a2w_ctrl;
71
+}
349
+}
72
+
350
+
73
+static bool trans_VCLZ(DisasContext *s, arg_2misc *a)
351
static bool pll_channel_is_enabled(CprmanPllChannelState *channel)
352
{
353
/*
354
@@ -XXX,XX +XXX,XX @@ static void pll_channel_class_init(ObjectClass *klass, void *data)
355
{
356
DeviceClass *dc = DEVICE_CLASS(klass);
357
358
+ dc->reset = pll_channel_reset;
359
dc->vmsd = &pll_channel_vmstate;
360
}
361
362
@@ -XXX,XX +XXX,XX @@ static void clock_mux_src_update(void *opaque)
363
clock_mux_update(s);
364
}
365
366
+static void clock_mux_reset(DeviceState *dev)
74
+{
367
+{
75
+ static NeonGenOneOpFn * const fn[] = {
368
+ CprmanClockMuxState *clock = CPRMAN_CLOCK_MUX(dev);
76
+ gen_helper_neon_clz_u8,
369
+ const ClockMuxResetInfo *info = &CLOCK_MUX_RESET_INFO[clock->id];
77
+ gen_helper_neon_clz_u16,
370
+
78
+ do_VCLZ_32,
371
+ *clock->reg_ctl = info->cm_ctl;
79
+ NULL,
372
+ *clock->reg_div = info->cm_div;
80
+ };
81
+ return do_2misc(s, a, fn[a->size]);
82
+}
373
+}
83
+
374
+
84
+static bool trans_VCNT(DisasContext *s, arg_2misc *a)
375
static void clock_mux_init(Object *obj)
85
+{
376
{
86
+ if (a->size != 0) {
377
CprmanClockMuxState *s = CPRMAN_CLOCK_MUX(obj);
87
+ return false;
378
@@ -XXX,XX +XXX,XX @@ static void clock_mux_class_init(ObjectClass *klass, void *data)
88
+ }
379
{
89
+ return do_2misc(s, a, gen_helper_neon_cnt_u8);
380
DeviceClass *dc = DEVICE_CLASS(klass);
90
+}
381
91
+
382
+ dc->reset = clock_mux_reset;
92
+static bool trans_VABS_F(DisasContext *s, arg_2misc *a)
383
dc->vmsd = &clock_mux_vmstate;
93
+{
384
}
94
+ if (a->size != 2) {
385
95
+ return false;
96
+ }
97
+ /* TODO: FP16 : size == 1 */
98
+ return do_2misc(s, a, gen_helper_vfp_abss);
99
+}
100
+
101
+static bool trans_VNEG_F(DisasContext *s, arg_2misc *a)
102
+{
103
+ if (a->size != 2) {
104
+ return false;
105
+ }
106
+ /* TODO: FP16 : size == 1 */
107
+ return do_2misc(s, a, gen_helper_vfp_negs);
108
+}
109
+
110
+static bool trans_VRECPE(DisasContext *s, arg_2misc *a)
111
+{
112
+ if (a->size != 2) {
113
+ return false;
114
+ }
115
+ return do_2misc(s, a, gen_helper_recpe_u32);
116
+}
117
+
118
+static bool trans_VRSQRTE(DisasContext *s, arg_2misc *a)
119
+{
120
+ if (a->size != 2) {
121
+ return false;
122
+ }
123
+ return do_2misc(s, a, gen_helper_rsqrte_u32);
124
+}
125
diff --git a/target/arm/translate.c b/target/arm/translate.c
126
index XXXXXXX..XXXXXXX 100644
127
--- a/target/arm/translate.c
128
+++ b/target/arm/translate.c
129
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
130
case NEON_2RM_SHA1SU1:
131
case NEON_2RM_VREV32:
132
case NEON_2RM_VREV16:
133
+ case NEON_2RM_VCLS:
134
+ case NEON_2RM_VCLZ:
135
+ case NEON_2RM_VCNT:
136
+ case NEON_2RM_VABS_F:
137
+ case NEON_2RM_VNEG_F:
138
+ case NEON_2RM_VRECPE:
139
+ case NEON_2RM_VRSQRTE:
140
/* handled by decodetree */
141
return 1;
142
case NEON_2RM_VTRN:
143
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
144
for (pass = 0; pass < (q ? 4 : 2); pass++) {
145
tmp = neon_load_reg(rm, pass);
146
switch (op) {
147
- case NEON_2RM_VCLS:
148
- switch (size) {
149
- case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
150
- case 1: gen_helper_neon_cls_s16(tmp, tmp); break;
151
- case 2: gen_helper_neon_cls_s32(tmp, tmp); break;
152
- default: abort();
153
- }
154
- break;
155
- case NEON_2RM_VCLZ:
156
- switch (size) {
157
- case 0: gen_helper_neon_clz_u8(tmp, tmp); break;
158
- case 1: gen_helper_neon_clz_u16(tmp, tmp); break;
159
- case 2: tcg_gen_clzi_i32(tmp, tmp, 32); break;
160
- default: abort();
161
- }
162
- break;
163
- case NEON_2RM_VCNT:
164
- gen_helper_neon_cnt_u8(tmp, tmp);
165
- break;
166
case NEON_2RM_VQABS:
167
switch (size) {
168
case 0:
169
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
170
tcg_temp_free_ptr(fpstatus);
171
break;
172
}
173
- case NEON_2RM_VABS_F:
174
- gen_helper_vfp_abss(tmp, tmp);
175
- break;
176
- case NEON_2RM_VNEG_F:
177
- gen_helper_vfp_negs(tmp, tmp);
178
- break;
179
case NEON_2RM_VSWP:
180
tmp2 = neon_load_reg(rd, pass);
181
neon_store_reg(rm, pass, tmp2);
182
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
183
tcg_temp_free_ptr(fpst);
184
break;
185
}
186
- case NEON_2RM_VRECPE:
187
- gen_helper_recpe_u32(tmp, tmp);
188
- break;
189
- case NEON_2RM_VRSQRTE:
190
- gen_helper_rsqrte_u32(tmp, tmp);
191
- break;
192
case NEON_2RM_VRECPE_F:
193
{
194
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
195
--
386
--
196
2.20.1
387
2.20.1
197
388
198
389
diff view generated by jsdifflib
1
Convert the pairwise ops VPADDL and VPADAL in the 2-reg-misc grouping
1
From: Luc Michel <luc@lmichel.fr>
2
to decodetree.
3
2
4
At this point we can get rid of the weird CPU_V001 #define that was
3
Add a clock input to the PL011 UART so we can compute the current baud
5
used to avoid having to explicitly list all the arguments being
4
rate and trace it. This is intended for developers who wish to use QEMU
6
passed to some TCG gen/helper functions.
5
to e.g. debug their firmware or to figure out the baud rate configured
6
by an unknown/closed source binary.
7
7
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Luc Michel <luc@lmichel.fr>
10
Tested-by: Guenter Roeck <linux@roeck-us.net>
11
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200616170844.13318-3-peter.maydell@linaro.org
11
---
13
---
12
target/arm/neon-dp.decode | 6 ++
14
include/hw/char/pl011.h | 1 +
13
target/arm/translate-neon.inc.c | 149 ++++++++++++++++++++++++++++++++
15
hw/char/pl011.c | 45 +++++++++++++++++++++++++++++++++++++++++
14
target/arm/translate.c | 35 +-------
16
hw/char/trace-events | 1 +
15
3 files changed, 157 insertions(+), 33 deletions(-)
17
3 files changed, 47 insertions(+)
16
18
17
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
19
diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h
18
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/neon-dp.decode
21
--- a/include/hw/char/pl011.h
20
+++ b/target/arm/neon-dp.decode
22
+++ b/include/hw/char/pl011.h
21
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
23
@@ -XXX,XX +XXX,XX @@ struct PL011State {
22
&2misc vm=%vm_dp vd=%vd_dp
24
int read_trigger;
23
25
CharBackend chr;
24
VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc
26
qemu_irq irq[6];
27
+ Clock *clk;
28
const unsigned char *id;
29
};
30
31
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/char/pl011.c
34
+++ b/hw/char/pl011.c
35
@@ -XXX,XX +XXX,XX @@
36
#include "hw/char/pl011.h"
37
#include "hw/irq.h"
38
#include "hw/sysbus.h"
39
+#include "hw/qdev-clock.h"
40
#include "migration/vmstate.h"
41
#include "chardev/char-fe.h"
42
#include "qemu/log.h"
43
@@ -XXX,XX +XXX,XX @@ static void pl011_set_read_trigger(PL011State *s)
44
s->read_trigger = 1;
45
}
46
47
+static unsigned int pl011_get_baudrate(const PL011State *s)
48
+{
49
+ uint64_t clk;
25
+
50
+
26
+ VPADDL_S 1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc
51
+ if (s->fbrd == 0) {
27
+ VPADDL_U 1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc
52
+ return 0;
28
+
29
+ VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc
30
+ VPADAL_U 1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc
31
]
32
33
# Subgroup for size != 0b11
34
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/translate-neon.inc.c
37
+++ b/target/arm/translate-neon.inc.c
38
@@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
39
}
40
return true;
41
}
42
+
43
+static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a,
44
+ NeonGenWidenFn *widenfn,
45
+ NeonGenTwo64OpFn *opfn,
46
+ NeonGenTwo64OpFn *accfn)
47
+{
48
+ /*
49
+ * Pairwise long operations: widen both halves of the pair,
50
+ * combine the pairs with the opfn, and then possibly accumulate
51
+ * into the destination with the accfn.
52
+ */
53
+ int pass;
54
+
55
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
56
+ return false;
57
+ }
53
+ }
58
+
54
+
59
+ /* UNDEF accesses to D16-D31 if they don't exist. */
55
+ clk = clock_get_hz(s->clk);
60
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
56
+ return (clk / ((s->ibrd << 6) + s->fbrd)) << 2;
61
+ ((a->vd | a->vm) & 0x10)) {
62
+ return false;
63
+ }
64
+
65
+ if ((a->vd | a->vm) & a->q) {
66
+ return false;
67
+ }
68
+
69
+ if (!widenfn) {
70
+ return false;
71
+ }
72
+
73
+ if (!vfp_access_check(s)) {
74
+ return true;
75
+ }
76
+
77
+ for (pass = 0; pass < a->q + 1; pass++) {
78
+ TCGv_i32 tmp;
79
+ TCGv_i64 rm0_64, rm1_64, rd_64;
80
+
81
+ rm0_64 = tcg_temp_new_i64();
82
+ rm1_64 = tcg_temp_new_i64();
83
+ rd_64 = tcg_temp_new_i64();
84
+ tmp = neon_load_reg(a->vm, pass * 2);
85
+ widenfn(rm0_64, tmp);
86
+ tcg_temp_free_i32(tmp);
87
+ tmp = neon_load_reg(a->vm, pass * 2 + 1);
88
+ widenfn(rm1_64, tmp);
89
+ tcg_temp_free_i32(tmp);
90
+ opfn(rd_64, rm0_64, rm1_64);
91
+ tcg_temp_free_i64(rm0_64);
92
+ tcg_temp_free_i64(rm1_64);
93
+
94
+ if (accfn) {
95
+ TCGv_i64 tmp64 = tcg_temp_new_i64();
96
+ neon_load_reg64(tmp64, a->vd + pass);
97
+ accfn(rd_64, tmp64, rd_64);
98
+ tcg_temp_free_i64(tmp64);
99
+ }
100
+ neon_store_reg64(rd_64, a->vd + pass);
101
+ tcg_temp_free_i64(rd_64);
102
+ }
103
+ return true;
104
+}
57
+}
105
+
58
+
106
+static bool trans_VPADDL_S(DisasContext *s, arg_2misc *a)
59
+static void pl011_trace_baudrate_change(const PL011State *s)
107
+{
60
+{
108
+ static NeonGenWidenFn * const widenfn[] = {
61
+ trace_pl011_baudrate_change(pl011_get_baudrate(s),
109
+ gen_helper_neon_widen_s8,
62
+ clock_get_hz(s->clk),
110
+ gen_helper_neon_widen_s16,
63
+ s->ibrd, s->fbrd);
111
+ tcg_gen_ext_i32_i64,
112
+ NULL,
113
+ };
114
+ static NeonGenTwo64OpFn * const opfn[] = {
115
+ gen_helper_neon_paddl_u16,
116
+ gen_helper_neon_paddl_u32,
117
+ tcg_gen_add_i64,
118
+ NULL,
119
+ };
120
+
121
+ return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL);
122
+}
64
+}
123
+
65
+
124
+static bool trans_VPADDL_U(DisasContext *s, arg_2misc *a)
66
static void pl011_write(void *opaque, hwaddr offset,
67
uint64_t value, unsigned size)
68
{
69
@@ -XXX,XX +XXX,XX @@ static void pl011_write(void *opaque, hwaddr offset,
70
break;
71
case 9: /* UARTIBRD */
72
s->ibrd = value;
73
+ pl011_trace_baudrate_change(s);
74
break;
75
case 10: /* UARTFBRD */
76
s->fbrd = value;
77
+ pl011_trace_baudrate_change(s);
78
break;
79
case 11: /* UARTLCR_H */
80
/* Reset the FIFO state on FIFO enable or disable */
81
@@ -XXX,XX +XXX,XX @@ static void pl011_event(void *opaque, QEMUChrEvent event)
82
pl011_put_fifo(opaque, 0x400);
83
}
84
85
+static void pl011_clock_update(void *opaque)
125
+{
86
+{
126
+ static NeonGenWidenFn * const widenfn[] = {
87
+ PL011State *s = PL011(opaque);
127
+ gen_helper_neon_widen_u8,
128
+ gen_helper_neon_widen_u16,
129
+ tcg_gen_extu_i32_i64,
130
+ NULL,
131
+ };
132
+ static NeonGenTwo64OpFn * const opfn[] = {
133
+ gen_helper_neon_paddl_u16,
134
+ gen_helper_neon_paddl_u32,
135
+ tcg_gen_add_i64,
136
+ NULL,
137
+ };
138
+
88
+
139
+ return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL);
89
+ pl011_trace_baudrate_change(s);
140
+}
90
+}
141
+
91
+
142
+static bool trans_VPADAL_S(DisasContext *s, arg_2misc *a)
92
static const MemoryRegionOps pl011_ops = {
143
+{
93
.read = pl011_read,
144
+ static NeonGenWidenFn * const widenfn[] = {
94
.write = pl011_write,
145
+ gen_helper_neon_widen_s8,
95
.endianness = DEVICE_NATIVE_ENDIAN,
146
+ gen_helper_neon_widen_s16,
96
};
147
+ tcg_gen_ext_i32_i64,
97
148
+ NULL,
98
+static const VMStateDescription vmstate_pl011_clock = {
149
+ };
99
+ .name = "pl011/clock",
150
+ static NeonGenTwo64OpFn * const opfn[] = {
100
+ .version_id = 1,
151
+ gen_helper_neon_paddl_u16,
101
+ .minimum_version_id = 1,
152
+ gen_helper_neon_paddl_u32,
102
+ .fields = (VMStateField[]) {
153
+ tcg_gen_add_i64,
103
+ VMSTATE_CLOCK(clk, PL011State),
154
+ NULL,
104
+ VMSTATE_END_OF_LIST()
155
+ };
105
+ }
156
+ static NeonGenTwo64OpFn * const accfn[] = {
106
+};
157
+ gen_helper_neon_addl_u16,
158
+ gen_helper_neon_addl_u32,
159
+ tcg_gen_add_i64,
160
+ NULL,
161
+ };
162
+
107
+
163
+ return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size],
108
static const VMStateDescription vmstate_pl011 = {
164
+ accfn[a->size]);
109
.name = "pl011",
165
+}
110
.version_id = 2,
111
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl011 = {
112
VMSTATE_INT32(read_count, PL011State),
113
VMSTATE_INT32(read_trigger, PL011State),
114
VMSTATE_END_OF_LIST()
115
+ },
116
+ .subsections = (const VMStateDescription * []) {
117
+ &vmstate_pl011_clock,
118
+ NULL
119
}
120
};
121
122
@@ -XXX,XX +XXX,XX @@ static void pl011_init(Object *obj)
123
sysbus_init_irq(sbd, &s->irq[i]);
124
}
125
126
+ s->clk = qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, s);
166
+
127
+
167
+static bool trans_VPADAL_U(DisasContext *s, arg_2misc *a)
128
s->read_trigger = 1;
168
+{
129
s->ifl = 0x12;
169
+ static NeonGenWidenFn * const widenfn[] = {
130
s->cr = 0x300;
170
+ gen_helper_neon_widen_u8,
131
diff --git a/hw/char/trace-events b/hw/char/trace-events
171
+ gen_helper_neon_widen_u16,
172
+ tcg_gen_extu_i32_i64,
173
+ NULL,
174
+ };
175
+ static NeonGenTwo64OpFn * const opfn[] = {
176
+ gen_helper_neon_paddl_u16,
177
+ gen_helper_neon_paddl_u32,
178
+ tcg_gen_add_i64,
179
+ NULL,
180
+ };
181
+ static NeonGenTwo64OpFn * const accfn[] = {
182
+ gen_helper_neon_addl_u16,
183
+ gen_helper_neon_addl_u32,
184
+ tcg_gen_add_i64,
185
+ NULL,
186
+ };
187
+
188
+ return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size],
189
+ accfn[a->size]);
190
+}
191
diff --git a/target/arm/translate.c b/target/arm/translate.c
192
index XXXXXXX..XXXXXXX 100644
132
index XXXXXXX..XXXXXXX 100644
193
--- a/target/arm/translate.c
133
--- a/hw/char/trace-events
194
+++ b/target/arm/translate.c
134
+++ b/hw/char/trace-events
195
@@ -XXX,XX +XXX,XX @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc)
135
@@ -XXX,XX +XXX,XX @@ pl011_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
196
gen_rfe(s, pc, load_cpu_field(spsr));
136
pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_count %d returning %d"
197
}
137
pl011_put_fifo(uint32_t c, int read_count) "new char 0x%x read_count now %d"
198
138
pl011_put_fifo_full(void) "FIFO now full, RXFF set"
199
-#define CPU_V001 cpu_V0, cpu_V0, cpu_V1
139
+pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd, uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd: %" PRIu32 ")"
200
-
140
201
static int gen_neon_unzip(int rd, int rm, int size, int q)
141
# cmsdk-apb-uart.c
202
{
142
cmsdk_apb_uart_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB UART read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
203
TCGv_ptr pd, pm;
204
@@ -XXX,XX +XXX,XX @@ static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u)
205
tcg_temp_free_i32(src);
206
}
207
208
-static inline void gen_neon_addl(int size)
209
-{
210
- switch (size) {
211
- case 0: gen_helper_neon_addl_u16(CPU_V001); break;
212
- case 1: gen_helper_neon_addl_u32(CPU_V001); break;
213
- case 2: tcg_gen_add_i64(CPU_V001); break;
214
- default: abort();
215
- }
216
-}
217
-
218
static void gen_neon_narrow_op(int op, int u, int size,
219
TCGv_i32 dest, TCGv_i64 src)
220
{
221
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
222
}
223
switch (op) {
224
case NEON_2RM_VREV64:
225
- /* handled by decodetree */
226
- return 1;
227
case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U:
228
case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U:
229
- for (pass = 0; pass < q + 1; pass++) {
230
- tmp = neon_load_reg(rm, pass * 2);
231
- gen_neon_widen(cpu_V0, tmp, size, op & 1);
232
- tmp = neon_load_reg(rm, pass * 2 + 1);
233
- gen_neon_widen(cpu_V1, tmp, size, op & 1);
234
- switch (size) {
235
- case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
236
- case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
237
- case 2: tcg_gen_add_i64(CPU_V001); break;
238
- default: abort();
239
- }
240
- if (op >= NEON_2RM_VPADAL) {
241
- /* Accumulate. */
242
- neon_load_reg64(cpu_V1, rd + pass);
243
- gen_neon_addl(size);
244
- }
245
- neon_store_reg64(cpu_V0, rd + pass);
246
- }
247
- break;
248
+ /* handled by decodetree */
249
+ return 1;
250
case NEON_2RM_VTRN:
251
if (size == 2) {
252
int n;
253
--
143
--
254
2.20.1
144
2.20.1
255
145
256
146
diff view generated by jsdifflib
1
Convert the fp-compare-with-zero insns in the Neon 2-reg-misc group to
1
From: Luc Michel <luc@lmichel.fr>
2
decodetree.
3
2
3
Connect the 'uart-out' clock from the CPRMAN to the PL011 instance.
4
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Luc Michel <luc@lmichel.fr>
7
Tested-by: Guenter Roeck <linux@roeck-us.net>
8
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200616170844.13318-17-peter.maydell@linaro.org
7
---
10
---
8
target/arm/neon-dp.decode | 6 ++++
11
hw/arm/bcm2835_peripherals.c | 2 ++
9
target/arm/translate-neon.inc.c | 28 ++++++++++++++++++
12
1 file changed, 2 insertions(+)
10
target/arm/translate.c | 50 ++++-----------------------------
11
3 files changed, 39 insertions(+), 45 deletions(-)
12
13
13
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
14
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/neon-dp.decode
16
--- a/hw/arm/bcm2835_peripherals.c
16
+++ b/target/arm/neon-dp.decode
17
+++ b/hw/arm/bcm2835_peripherals.c
17
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
18
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
18
VABS 1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc
19
VNEG 1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc
20
21
+ VCGT0_F 1111 001 11 . 11 .. 01 .... 0 1000 . . 0 .... @2misc
22
+ VCGE0_F 1111 001 11 . 11 .. 01 .... 0 1001 . . 0 .... @2misc
23
+ VCEQ0_F 1111 001 11 . 11 .. 01 .... 0 1010 . . 0 .... @2misc
24
+ VCLE0_F 1111 001 11 . 11 .. 01 .... 0 1011 . . 0 .... @2misc
25
+ VCLT0_F 1111 001 11 . 11 .. 01 .... 0 1100 . . 0 .... @2misc
26
+
27
VABS_F 1111 001 11 . 11 .. 01 .... 0 1110 . . 0 .... @2misc
28
VNEG_F 1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc
29
30
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/translate-neon.inc.c
33
+++ b/target/arm/translate-neon.inc.c
34
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX(DisasContext *s, arg_2misc *a)
35
}
19
}
36
return do_2misc_fp(s, a, gen_helper_rints_exact);
20
memory_region_add_subregion(&s->peri_mr, CPRMAN_OFFSET,
37
}
21
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cprman), 0));
38
+
22
+ qdev_connect_clock_in(DEVICE(&s->uart0), "clk",
39
+#define WRAP_FP_CMP0_FWD(WRAPNAME, FUNC) \
23
+ qdev_get_clock_out(DEVICE(&s->cprman), "uart-out"));
40
+ static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \
24
41
+ { \
25
memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET,
42
+ TCGv_i32 zero = tcg_const_i32(0); \
26
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0));
43
+ FUNC(d, m, zero, fpst); \
44
+ tcg_temp_free_i32(zero); \
45
+ }
46
+#define WRAP_FP_CMP0_REV(WRAPNAME, FUNC) \
47
+ static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \
48
+ { \
49
+ TCGv_i32 zero = tcg_const_i32(0); \
50
+ FUNC(d, zero, m, fpst); \
51
+ tcg_temp_free_i32(zero); \
52
+ }
53
+
54
+#define DO_FP_CMP0(INSN, FUNC, REV) \
55
+ WRAP_FP_CMP0_##REV(gen_##INSN, FUNC) \
56
+ static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
57
+ { \
58
+ return do_2misc_fp(s, a, gen_##INSN); \
59
+ }
60
+
61
+DO_FP_CMP0(VCGT0_F, gen_helper_neon_cgt_f32, FWD)
62
+DO_FP_CMP0(VCGE0_F, gen_helper_neon_cge_f32, FWD)
63
+DO_FP_CMP0(VCEQ0_F, gen_helper_neon_ceq_f32, FWD)
64
+DO_FP_CMP0(VCLE0_F, gen_helper_neon_cge_f32, REV)
65
+DO_FP_CMP0(VCLT0_F, gen_helper_neon_cgt_f32, REV)
66
diff --git a/target/arm/translate.c b/target/arm/translate.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/arm/translate.c
69
+++ b/target/arm/translate.c
70
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
71
case NEON_2RM_VCVT_SF:
72
case NEON_2RM_VCVT_UF:
73
case NEON_2RM_VRINTX:
74
+ case NEON_2RM_VCGT0_F:
75
+ case NEON_2RM_VCGE0_F:
76
+ case NEON_2RM_VCEQ0_F:
77
+ case NEON_2RM_VCLE0_F:
78
+ case NEON_2RM_VCLT0_F:
79
/* handled by decodetree */
80
return 1;
81
case NEON_2RM_VTRN:
82
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
83
for (pass = 0; pass < (q ? 4 : 2); pass++) {
84
tmp = neon_load_reg(rm, pass);
85
switch (op) {
86
- case NEON_2RM_VCGT0_F:
87
- {
88
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
89
- tmp2 = tcg_const_i32(0);
90
- gen_helper_neon_cgt_f32(tmp, tmp, tmp2, fpstatus);
91
- tcg_temp_free_i32(tmp2);
92
- tcg_temp_free_ptr(fpstatus);
93
- break;
94
- }
95
- case NEON_2RM_VCGE0_F:
96
- {
97
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
98
- tmp2 = tcg_const_i32(0);
99
- gen_helper_neon_cge_f32(tmp, tmp, tmp2, fpstatus);
100
- tcg_temp_free_i32(tmp2);
101
- tcg_temp_free_ptr(fpstatus);
102
- break;
103
- }
104
- case NEON_2RM_VCEQ0_F:
105
- {
106
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
107
- tmp2 = tcg_const_i32(0);
108
- gen_helper_neon_ceq_f32(tmp, tmp, tmp2, fpstatus);
109
- tcg_temp_free_i32(tmp2);
110
- tcg_temp_free_ptr(fpstatus);
111
- break;
112
- }
113
- case NEON_2RM_VCLE0_F:
114
- {
115
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
116
- tmp2 = tcg_const_i32(0);
117
- gen_helper_neon_cge_f32(tmp, tmp2, tmp, fpstatus);
118
- tcg_temp_free_i32(tmp2);
119
- tcg_temp_free_ptr(fpstatus);
120
- break;
121
- }
122
- case NEON_2RM_VCLT0_F:
123
- {
124
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
125
- tmp2 = tcg_const_i32(0);
126
- gen_helper_neon_cgt_f32(tmp, tmp2, tmp, fpstatus);
127
- tcg_temp_free_i32(tmp2);
128
- tcg_temp_free_ptr(fpstatus);
129
- break;
130
- }
131
case NEON_2RM_VSWP:
132
tmp2 = neon_load_reg(rd, pass);
133
neon_store_reg(rm, pass, tmp2);
134
--
27
--
135
2.20.1
28
2.20.1
136
29
137
30
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Shashi Mallela <shashi.mallela@linaro.org>
2
2
3
From 'Application Note AN385', chapter 3.9, SPI:
3
Generic watchdog device model implementation as per ARM SBSA v6.0
4
4
5
The SMM implements five PL022 SPI modules.
5
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
6
6
Message-id: 20201027015927.29495-2-shashi.mallela@linaro.org
7
Two pairs of modules share the same OR-gated IRQ.
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20200617072539.32686-12-f4bug@amsat.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
9
---
14
hw/arm/mps2.c | 24 ++++++++++++++++++++++++
10
include/hw/watchdog/sbsa_gwdt.h | 79 +++++++++
15
hw/arm/Kconfig | 6 +++---
11
hw/watchdog/sbsa_gwdt.c | 293 ++++++++++++++++++++++++++++++++
16
2 files changed, 27 insertions(+), 3 deletions(-)
12
hw/arm/Kconfig | 1 +
13
hw/watchdog/Kconfig | 3 +
14
hw/watchdog/meson.build | 1 +
15
5 files changed, 377 insertions(+)
16
create mode 100644 include/hw/watchdog/sbsa_gwdt.h
17
create mode 100644 hw/watchdog/sbsa_gwdt.c
17
18
18
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
19
diff --git a/include/hw/watchdog/sbsa_gwdt.h b/include/hw/watchdog/sbsa_gwdt.h
19
index XXXXXXX..XXXXXXX 100644
20
new file mode 100644
20
--- a/hw/arm/mps2.c
21
index XXXXXXX..XXXXXXX
21
+++ b/hw/arm/mps2.c
22
--- /dev/null
23
+++ b/include/hw/watchdog/sbsa_gwdt.h
22
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@
23
#include "hw/timer/cmsdk-apb-dualtimer.h"
25
+/*
24
#include "hw/misc/mps2-scc.h"
26
+ * Copyright (c) 2020 Linaro Limited
25
#include "hw/misc/mps2-fpgaio.h"
27
+ *
26
+#include "hw/ssi/pl022.h"
28
+ * Authors:
27
#include "hw/net/lan9118.h"
29
+ * Shashi Mallela <shashi.mallela@linaro.org>
28
#include "net/net.h"
30
+ *
29
#include "hw/watchdog/cmsdk-apb-watchdog.h"
31
+ * This work is licensed under the terms of the GNU GPL, version 2 or (at your
30
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
32
+ * option) any later version. See the COPYING file in the top-level directory.
31
qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", 25000000);
33
+ *
32
sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
34
+ */
33
sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0x40028000);
35
+
34
+ sysbus_create_simple(TYPE_PL022, 0x40025000, /* External ADC */
36
+#ifndef WDT_SBSA_GWDT_H
35
+ qdev_get_gpio_in(armv7m, 22));
37
+#define WDT_SBSA_GWDT_H
36
+ for (i = 0; i < 2; i++) {
38
+
37
+ static const int spi_irqno[] = {11, 24};
39
+#include "qemu/bitops.h"
38
+ static const hwaddr spibase[] = {0x40020000, /* APB */
40
+#include "hw/sysbus.h"
39
+ 0x40021000, /* LCD */
41
+#include "hw/irq.h"
40
+ 0x40026000, /* Shield0 */
42
+
41
+ 0x40027000}; /* Shield1 */
43
+#define TYPE_WDT_SBSA "sbsa_gwdt"
42
+ DeviceState *orgate_dev;
44
+#define SBSA_GWDT(obj) \
43
+ Object *orgate;
45
+ OBJECT_CHECK(SBSA_GWDTState, (obj), TYPE_WDT_SBSA)
44
+ int j;
46
+#define SBSA_GWDT_CLASS(klass) \
45
+
47
+ OBJECT_CLASS_CHECK(SBSA_GWDTClass, (klass), TYPE_WDT_SBSA)
46
+ orgate = object_new(TYPE_OR_IRQ);
48
+#define SBSA_GWDT_GET_CLASS(obj) \
47
+ object_property_set_int(orgate, 2, "num-lines", &error_fatal);
49
+ OBJECT_GET_CLASS(SBSA_GWDTClass, (obj), TYPE_WDT_SBSA)
48
+ orgate_dev = DEVICE(orgate);
50
+
49
+ qdev_realize(orgate_dev, NULL, &error_fatal);
51
+/* SBSA Generic Watchdog register definitions */
50
+ qdev_connect_gpio_out(orgate_dev, 0,
52
+/* refresh frame */
51
+ qdev_get_gpio_in(armv7m, spi_irqno[i]));
53
+#define SBSA_GWDT_WRR 0x000
52
+ for (j = 0; j < 2; j++) {
54
+
53
+ sysbus_create_simple(TYPE_PL022, spibase[2 * i + j],
55
+/* control frame */
54
+ qdev_get_gpio_in(orgate_dev, j));
56
+#define SBSA_GWDT_WCS 0x000
57
+#define SBSA_GWDT_WOR 0x008
58
+#define SBSA_GWDT_WORU 0x00C
59
+#define SBSA_GWDT_WCV 0x010
60
+#define SBSA_GWDT_WCVU 0x014
61
+
62
+/* Watchdog Interface Identification Register */
63
+#define SBSA_GWDT_W_IIDR 0xFCC
64
+
65
+/* Watchdog Control and Status Register Bits */
66
+#define SBSA_GWDT_WCS_EN BIT(0)
67
+#define SBSA_GWDT_WCS_WS0 BIT(1)
68
+#define SBSA_GWDT_WCS_WS1 BIT(2)
69
+
70
+#define SBSA_GWDT_WOR_MASK 0x0000FFFF
71
+
72
+/*
73
+ * Watchdog Interface Identification Register definition
74
+ * considering JEP106 code for ARM in Bits [11:0]
75
+ */
76
+#define SBSA_GWDT_ID 0x1043B
77
+
78
+/* 2 Separate memory regions for each of refresh & control register frames */
79
+#define SBSA_GWDT_RMMIO_SIZE 0x1000
80
+#define SBSA_GWDT_CMMIO_SIZE 0x1000
81
+
82
+#define SBSA_TIMER_FREQ 62500000 /* Hz */
83
+
84
+typedef struct SBSA_GWDTState {
85
+ /* <private> */
86
+ SysBusDevice parent_obj;
87
+
88
+ /*< public >*/
89
+ MemoryRegion rmmio;
90
+ MemoryRegion cmmio;
91
+ qemu_irq irq;
92
+
93
+ QEMUTimer *timer;
94
+
95
+ uint32_t id;
96
+ uint32_t wcs;
97
+ uint32_t worl;
98
+ uint32_t woru;
99
+ uint32_t wcvl;
100
+ uint32_t wcvu;
101
+} SBSA_GWDTState;
102
+
103
+#endif /* WDT_SBSA_GWDT_H */
104
diff --git a/hw/watchdog/sbsa_gwdt.c b/hw/watchdog/sbsa_gwdt.c
105
new file mode 100644
106
index XXXXXXX..XXXXXXX
107
--- /dev/null
108
+++ b/hw/watchdog/sbsa_gwdt.c
109
@@ -XXX,XX +XXX,XX @@
110
+/*
111
+ * Generic watchdog device model for SBSA
112
+ *
113
+ * The watchdog device has been implemented as revision 1 variant of
114
+ * the ARM SBSA specification v6.0
115
+ * (https://developer.arm.com/documentation/den0029/d?lang=en)
116
+ *
117
+ * Copyright Linaro.org 2020
118
+ *
119
+ * Authors:
120
+ * Shashi Mallela <shashi.mallela@linaro.org>
121
+ *
122
+ * This work is licensed under the terms of the GNU GPL, version 2 or (at your
123
+ * option) any later version. See the COPYING file in the top-level directory.
124
+ *
125
+ */
126
+
127
+#include "qemu/osdep.h"
128
+#include "sysemu/reset.h"
129
+#include "sysemu/watchdog.h"
130
+#include "hw/watchdog/sbsa_gwdt.h"
131
+#include "qemu/timer.h"
132
+#include "migration/vmstate.h"
133
+#include "qemu/log.h"
134
+#include "qemu/module.h"
135
+
136
+static WatchdogTimerModel model = {
137
+ .wdt_name = TYPE_WDT_SBSA,
138
+ .wdt_description = "SBSA-compliant generic watchdog device",
139
+};
140
+
141
+static const VMStateDescription vmstate_sbsa_gwdt = {
142
+ .name = "sbsa-gwdt",
143
+ .version_id = 1,
144
+ .minimum_version_id = 1,
145
+ .fields = (VMStateField[]) {
146
+ VMSTATE_TIMER_PTR(timer, SBSA_GWDTState),
147
+ VMSTATE_UINT32(wcs, SBSA_GWDTState),
148
+ VMSTATE_UINT32(worl, SBSA_GWDTState),
149
+ VMSTATE_UINT32(woru, SBSA_GWDTState),
150
+ VMSTATE_UINT32(wcvl, SBSA_GWDTState),
151
+ VMSTATE_UINT32(wcvu, SBSA_GWDTState),
152
+ VMSTATE_END_OF_LIST()
153
+ }
154
+};
155
+
156
+typedef enum WdtRefreshType {
157
+ EXPLICIT_REFRESH = 0,
158
+ TIMEOUT_REFRESH = 1,
159
+} WdtRefreshType;
160
+
161
+static uint64_t sbsa_gwdt_rread(void *opaque, hwaddr addr, unsigned int size)
162
+{
163
+ SBSA_GWDTState *s = SBSA_GWDT(opaque);
164
+ uint32_t ret = 0;
165
+
166
+ switch (addr) {
167
+ case SBSA_GWDT_WRR:
168
+ /* watch refresh read has no effect and returns 0 */
169
+ ret = 0;
170
+ break;
171
+ case SBSA_GWDT_W_IIDR:
172
+ ret = s->id;
173
+ break;
174
+ default:
175
+ qemu_log_mask(LOG_GUEST_ERROR, "bad address in refresh frame read :"
176
+ " 0x%x\n", (int)addr);
177
+ }
178
+ return ret;
179
+}
180
+
181
+static uint64_t sbsa_gwdt_read(void *opaque, hwaddr addr, unsigned int size)
182
+{
183
+ SBSA_GWDTState *s = SBSA_GWDT(opaque);
184
+ uint32_t ret = 0;
185
+
186
+ switch (addr) {
187
+ case SBSA_GWDT_WCS:
188
+ ret = s->wcs;
189
+ break;
190
+ case SBSA_GWDT_WOR:
191
+ ret = s->worl;
192
+ break;
193
+ case SBSA_GWDT_WORU:
194
+ ret = s->woru;
195
+ break;
196
+ case SBSA_GWDT_WCV:
197
+ ret = s->wcvl;
198
+ break;
199
+ case SBSA_GWDT_WCVU:
200
+ ret = s->wcvu;
201
+ break;
202
+ case SBSA_GWDT_W_IIDR:
203
+ ret = s->id;
204
+ break;
205
+ default:
206
+ qemu_log_mask(LOG_GUEST_ERROR, "bad address in control frame read :"
207
+ " 0x%x\n", (int)addr);
208
+ }
209
+ return ret;
210
+}
211
+
212
+static void sbsa_gwdt_update_timer(SBSA_GWDTState *s, WdtRefreshType rtype)
213
+{
214
+ uint64_t timeout = 0;
215
+
216
+ timer_del(s->timer);
217
+
218
+ if (s->wcs & SBSA_GWDT_WCS_EN) {
219
+ /*
220
+ * Extract the upper 16 bits from woru & 32 bits from worl
221
+ * registers to construct the 48 bit offset value
222
+ */
223
+ timeout = s->woru;
224
+ timeout <<= 32;
225
+ timeout |= s->worl;
226
+ timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, SBSA_TIMER_FREQ);
227
+ timeout += qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
228
+
229
+ if ((rtype == EXPLICIT_REFRESH) || ((rtype == TIMEOUT_REFRESH) &&
230
+ (!(s->wcs & SBSA_GWDT_WCS_WS0)))) {
231
+ /* store the current timeout value into compare registers */
232
+ s->wcvu = timeout >> 32;
233
+ s->wcvl = timeout;
55
+ }
234
+ }
56
+ }
235
+ timer_mod(s->timer, timeout);
57
236
+ }
58
/* In hardware this is a LAN9220; the LAN9118 is software compatible
237
+}
59
* except that it doesn't support the checksum-offload feature.
238
+
239
+static void sbsa_gwdt_rwrite(void *opaque, hwaddr offset, uint64_t data,
240
+ unsigned size) {
241
+ SBSA_GWDTState *s = SBSA_GWDT(opaque);
242
+
243
+ if (offset == SBSA_GWDT_WRR) {
244
+ s->wcs &= ~(SBSA_GWDT_WCS_WS0 | SBSA_GWDT_WCS_WS1);
245
+
246
+ sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH);
247
+ } else {
248
+ qemu_log_mask(LOG_GUEST_ERROR, "bad address in refresh frame write :"
249
+ " 0x%x\n", (int)offset);
250
+ }
251
+}
252
+
253
+static void sbsa_gwdt_write(void *opaque, hwaddr offset, uint64_t data,
254
+ unsigned size) {
255
+ SBSA_GWDTState *s = SBSA_GWDT(opaque);
256
+
257
+ switch (offset) {
258
+ case SBSA_GWDT_WCS:
259
+ s->wcs = data & SBSA_GWDT_WCS_EN;
260
+ qemu_set_irq(s->irq, 0);
261
+ sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH);
262
+ break;
263
+
264
+ case SBSA_GWDT_WOR:
265
+ s->worl = data;
266
+ s->wcs &= ~(SBSA_GWDT_WCS_WS0 | SBSA_GWDT_WCS_WS1);
267
+ qemu_set_irq(s->irq, 0);
268
+ sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH);
269
+ break;
270
+
271
+ case SBSA_GWDT_WORU:
272
+ s->woru = data & SBSA_GWDT_WOR_MASK;
273
+ s->wcs &= ~(SBSA_GWDT_WCS_WS0 | SBSA_GWDT_WCS_WS1);
274
+ qemu_set_irq(s->irq, 0);
275
+ sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH);
276
+ break;
277
+
278
+ case SBSA_GWDT_WCV:
279
+ s->wcvl = data;
280
+ break;
281
+
282
+ case SBSA_GWDT_WCVU:
283
+ s->wcvu = data;
284
+ break;
285
+
286
+ default:
287
+ qemu_log_mask(LOG_GUEST_ERROR, "bad address in control frame write :"
288
+ " 0x%x\n", (int)offset);
289
+ }
290
+ return;
291
+}
292
+
293
+static void wdt_sbsa_gwdt_reset(DeviceState *dev)
294
+{
295
+ SBSA_GWDTState *s = SBSA_GWDT(dev);
296
+
297
+ timer_del(s->timer);
298
+
299
+ s->wcs = 0;
300
+ s->wcvl = 0;
301
+ s->wcvu = 0;
302
+ s->worl = 0;
303
+ s->woru = 0;
304
+ s->id = SBSA_GWDT_ID;
305
+}
306
+
307
+static void sbsa_gwdt_timer_sysinterrupt(void *opaque)
308
+{
309
+ SBSA_GWDTState *s = SBSA_GWDT(opaque);
310
+
311
+ if (!(s->wcs & SBSA_GWDT_WCS_WS0)) {
312
+ s->wcs |= SBSA_GWDT_WCS_WS0;
313
+ sbsa_gwdt_update_timer(s, TIMEOUT_REFRESH);
314
+ qemu_set_irq(s->irq, 1);
315
+ } else {
316
+ s->wcs |= SBSA_GWDT_WCS_WS1;
317
+ qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n");
318
+ /*
319
+ * Reset the watchdog only if the guest gets notified about
320
+ * expiry. watchdog_perform_action() may temporarily relinquish
321
+ * the BQL; reset before triggering the action to avoid races with
322
+ * sbsa_gwdt instructions.
323
+ */
324
+ switch (get_watchdog_action()) {
325
+ case WATCHDOG_ACTION_DEBUG:
326
+ case WATCHDOG_ACTION_NONE:
327
+ case WATCHDOG_ACTION_PAUSE:
328
+ break;
329
+ default:
330
+ wdt_sbsa_gwdt_reset(DEVICE(s));
331
+ }
332
+ watchdog_perform_action();
333
+ }
334
+}
335
+
336
+static const MemoryRegionOps sbsa_gwdt_rops = {
337
+ .read = sbsa_gwdt_rread,
338
+ .write = sbsa_gwdt_rwrite,
339
+ .endianness = DEVICE_LITTLE_ENDIAN,
340
+ .valid.min_access_size = 4,
341
+ .valid.max_access_size = 4,
342
+ .valid.unaligned = false,
343
+};
344
+
345
+static const MemoryRegionOps sbsa_gwdt_ops = {
346
+ .read = sbsa_gwdt_read,
347
+ .write = sbsa_gwdt_write,
348
+ .endianness = DEVICE_LITTLE_ENDIAN,
349
+ .valid.min_access_size = 4,
350
+ .valid.max_access_size = 4,
351
+ .valid.unaligned = false,
352
+};
353
+
354
+static void wdt_sbsa_gwdt_realize(DeviceState *dev, Error **errp)
355
+{
356
+ SBSA_GWDTState *s = SBSA_GWDT(dev);
357
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
358
+
359
+ memory_region_init_io(&s->rmmio, OBJECT(dev),
360
+ &sbsa_gwdt_rops, s,
361
+ "sbsa_gwdt.refresh",
362
+ SBSA_GWDT_RMMIO_SIZE);
363
+
364
+ memory_region_init_io(&s->cmmio, OBJECT(dev),
365
+ &sbsa_gwdt_ops, s,
366
+ "sbsa_gwdt.control",
367
+ SBSA_GWDT_CMMIO_SIZE);
368
+
369
+ sysbus_init_mmio(sbd, &s->rmmio);
370
+ sysbus_init_mmio(sbd, &s->cmmio);
371
+
372
+ sysbus_init_irq(sbd, &s->irq);
373
+
374
+ s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sbsa_gwdt_timer_sysinterrupt,
375
+ dev);
376
+}
377
+
378
+static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data)
379
+{
380
+ DeviceClass *dc = DEVICE_CLASS(klass);
381
+
382
+ dc->realize = wdt_sbsa_gwdt_realize;
383
+ dc->reset = wdt_sbsa_gwdt_reset;
384
+ dc->hotpluggable = false;
385
+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
386
+ dc->vmsd = &vmstate_sbsa_gwdt;
387
+}
388
+
389
+static const TypeInfo wdt_sbsa_gwdt_info = {
390
+ .class_init = wdt_sbsa_gwdt_class_init,
391
+ .parent = TYPE_SYS_BUS_DEVICE,
392
+ .name = TYPE_WDT_SBSA,
393
+ .instance_size = sizeof(SBSA_GWDTState),
394
+};
395
+
396
+static void wdt_sbsa_gwdt_register_types(void)
397
+{
398
+ watchdog_add_model(&model);
399
+ type_register_static(&wdt_sbsa_gwdt_info);
400
+}
401
+
402
+type_init(wdt_sbsa_gwdt_register_types)
60
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
403
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
61
index XXXXXXX..XXXXXXX 100644
404
index XXXXXXX..XXXXXXX 100644
62
--- a/hw/arm/Kconfig
405
--- a/hw/arm/Kconfig
63
+++ b/hw/arm/Kconfig
406
+++ b/hw/arm/Kconfig
64
@@ -XXX,XX +XXX,XX @@ config HIGHBANK
407
@@ -XXX,XX +XXX,XX @@ config SBSA_REF
65
select ARM_TIMER # sp804
66
select ARM_V7M
67
select PL011 # UART
68
- select PL022 # Serial port
69
+ select PL022 # SPI
70
select PL031 # RTC
408
select PL031 # RTC
71
select PL061 # GPIO
409
select PL061 # GPIO
72
select PL310 # cache controller
410
select USB_EHCI_SYSBUS
73
@@ -XXX,XX +XXX,XX @@ config STELLARIS
411
+ select WDT_SBSA
74
select CMSDK_APB_WATCHDOG
412
75
select I2C
413
config SABRELITE
76
select PL011 # UART
414
bool
77
- select PL022 # Serial port
415
diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig
78
+ select PL022 # SPI
416
index XXXXXXX..XXXXXXX 100644
79
select PL061 # GPIO
417
--- a/hw/watchdog/Kconfig
80
select SSD0303 # OLED display
418
+++ b/hw/watchdog/Kconfig
81
select SSD0323 # OLED display
419
@@ -XXX,XX +XXX,XX @@ config WDT_DIAG288
82
@@ -XXX,XX +XXX,XX @@ config MPS2
420
83
select MPS2_FPGAIO
421
config WDT_IMX2
84
select MPS2_SCC
422
bool
85
select OR_IRQ
423
+
86
- select PL022 # Serial port
424
+config WDT_SBSA
87
+ select PL022 # SPI
425
+ bool
88
select PL080 # DMA controller
426
diff --git a/hw/watchdog/meson.build b/hw/watchdog/meson.build
89
select SPLIT_IRQ
427
index XXXXXXX..XXXXXXX 100644
90
select UNIMP
428
--- a/hw/watchdog/meson.build
429
+++ b/hw/watchdog/meson.build
430
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_WDT_IB700', if_true: files('wdt_ib700.c'))
431
softmmu_ss.add(when: 'CONFIG_WDT_DIAG288', if_true: files('wdt_diag288.c'))
432
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('wdt_aspeed.c'))
433
softmmu_ss.add(when: 'CONFIG_WDT_IMX2', if_true: files('wdt_imx2.c'))
434
+softmmu_ss.add(when: 'CONFIG_WDT_SBSA', if_true: files('sbsa_gwdt.c'))
91
--
435
--
92
2.20.1
436
2.20.1
93
437
94
438
diff view generated by jsdifflib
1
Convert the Neon VQABS and VQNEG insns to decodetree.
1
From: Shashi Mallela <shashi.mallela@linaro.org>
2
Since these are the only ones which need cpu_env passing to
3
the helper, we wrap the helper rather than creating a whole
4
new do_2misc_env() function.
5
2
3
Included the newly implemented SBSA generic watchdog device model into
4
SBSA platform
5
6
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20201027015927.29495-3-shashi.mallela@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200616170844.13318-15-peter.maydell@linaro.org
9
---
10
---
10
target/arm/neon-dp.decode | 3 +++
11
hw/arm/sbsa-ref.c | 23 +++++++++++++++++++++++
11
target/arm/translate-neon.inc.c | 35 +++++++++++++++++++++++++++++++++
12
1 file changed, 23 insertions(+)
12
target/arm/translate.c | 30 ++--------------------------
13
3 files changed, 40 insertions(+), 28 deletions(-)
14
13
15
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
14
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/neon-dp.decode
16
--- a/hw/arm/sbsa-ref.c
18
+++ b/target/arm/neon-dp.decode
17
+++ b/hw/arm/sbsa-ref.c
19
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
18
@@ -XXX,XX +XXX,XX @@
20
VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc
19
#include "hw/qdev-properties.h"
21
VPADAL_U 1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc
20
#include "hw/usb.h"
22
21
#include "hw/char/pl011.h"
23
+ VQABS 1111 001 11 . 11 .. 00 .... 0 1110 . . 0 .... @2misc
22
+#include "hw/watchdog/sbsa_gwdt.h"
24
+ VQNEG 1111 001 11 . 11 .. 00 .... 0 1111 . . 0 .... @2misc
23
#include "net/net.h"
24
#include "qom/object.h"
25
26
@@ -XXX,XX +XXX,XX @@ enum {
27
SBSA_GIC_DIST,
28
SBSA_GIC_REDIST,
29
SBSA_SECURE_EC,
30
+ SBSA_GWDT,
31
+ SBSA_GWDT_REFRESH,
32
+ SBSA_GWDT_CONTROL,
33
SBSA_SMMU,
34
SBSA_UART,
35
SBSA_RTC,
36
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry sbsa_ref_memmap[] = {
37
[SBSA_GIC_DIST] = { 0x40060000, 0x00010000 },
38
[SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 },
39
[SBSA_SECURE_EC] = { 0x50000000, 0x00001000 },
40
+ [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 },
41
+ [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 },
42
[SBSA_UART] = { 0x60000000, 0x00001000 },
43
[SBSA_RTC] = { 0x60010000, 0x00001000 },
44
[SBSA_GPIO] = { 0x60020000, 0x00001000 },
45
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
46
[SBSA_AHCI] = 10,
47
[SBSA_EHCI] = 11,
48
[SBSA_SMMU] = 12, /* ... to 15 */
49
+ [SBSA_GWDT] = 16,
50
};
51
52
static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
53
@@ -XXX,XX +XXX,XX @@ static void create_rtc(const SBSAMachineState *sms)
54
sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq));
55
}
56
57
+static void create_wdt(const SBSAMachineState *sms)
58
+{
59
+ hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base;
60
+ hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base;
61
+ DeviceState *dev = qdev_new(TYPE_WDT_SBSA);
62
+ SysBusDevice *s = SYS_BUS_DEVICE(dev);
63
+ int irq = sbsa_ref_irqmap[SBSA_GWDT];
25
+
64
+
26
VCGT0 1111 001 11 . 11 .. 01 .... 0 0000 . . 0 .... @2misc
65
+ sysbus_realize_and_unref(s, &error_fatal);
27
VCGE0 1111 001 11 . 11 .. 01 .... 0 0001 . . 0 .... @2misc
66
+ sysbus_mmio_map(s, 0, rbase);
28
VCEQ0 1111 001 11 . 11 .. 01 .... 0 0010 . . 0 .... @2misc
67
+ sysbus_mmio_map(s, 1, cbase);
29
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
68
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/translate-neon.inc.c
32
+++ b/target/arm/translate-neon.inc.c
33
@@ -XXX,XX +XXX,XX @@ static bool trans_VRSQRTE(DisasContext *s, arg_2misc *a)
34
}
35
return do_2misc(s, a, gen_helper_rsqrte_u32);
36
}
37
+
38
+#define WRAP_1OP_ENV_FN(WRAPNAME, FUNC) \
39
+ static void WRAPNAME(TCGv_i32 d, TCGv_i32 m) \
40
+ { \
41
+ FUNC(d, cpu_env, m); \
42
+ }
43
+
44
+WRAP_1OP_ENV_FN(gen_VQABS_s8, gen_helper_neon_qabs_s8)
45
+WRAP_1OP_ENV_FN(gen_VQABS_s16, gen_helper_neon_qabs_s16)
46
+WRAP_1OP_ENV_FN(gen_VQABS_s32, gen_helper_neon_qabs_s32)
47
+WRAP_1OP_ENV_FN(gen_VQNEG_s8, gen_helper_neon_qneg_s8)
48
+WRAP_1OP_ENV_FN(gen_VQNEG_s16, gen_helper_neon_qneg_s16)
49
+WRAP_1OP_ENV_FN(gen_VQNEG_s32, gen_helper_neon_qneg_s32)
50
+
51
+static bool trans_VQABS(DisasContext *s, arg_2misc *a)
52
+{
53
+ static NeonGenOneOpFn * const fn[] = {
54
+ gen_VQABS_s8,
55
+ gen_VQABS_s16,
56
+ gen_VQABS_s32,
57
+ NULL,
58
+ };
59
+ return do_2misc(s, a, fn[a->size]);
60
+}
69
+}
61
+
70
+
62
+static bool trans_VQNEG(DisasContext *s, arg_2misc *a)
71
static DeviceState *gpio_key_dev;
63
+{
72
static void sbsa_ref_powerdown_req(Notifier *n, void *opaque)
64
+ static NeonGenOneOpFn * const fn[] = {
73
{
65
+ gen_VQNEG_s8,
74
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
66
+ gen_VQNEG_s16,
75
67
+ gen_VQNEG_s32,
76
create_rtc(sms);
68
+ NULL,
77
69
+ };
78
+ create_wdt(sms);
70
+ return do_2misc(s, a, fn[a->size]);
79
+
71
+}
80
create_gpio(sms);
72
diff --git a/target/arm/translate.c b/target/arm/translate.c
81
73
index XXXXXXX..XXXXXXX 100644
82
create_ahci(sms);
74
--- a/target/arm/translate.c
75
+++ b/target/arm/translate.c
76
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
77
case NEON_2RM_VNEG_F:
78
case NEON_2RM_VRECPE:
79
case NEON_2RM_VRSQRTE:
80
+ case NEON_2RM_VQABS:
81
+ case NEON_2RM_VQNEG:
82
/* handled by decodetree */
83
return 1;
84
case NEON_2RM_VTRN:
85
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
86
for (pass = 0; pass < (q ? 4 : 2); pass++) {
87
tmp = neon_load_reg(rm, pass);
88
switch (op) {
89
- case NEON_2RM_VQABS:
90
- switch (size) {
91
- case 0:
92
- gen_helper_neon_qabs_s8(tmp, cpu_env, tmp);
93
- break;
94
- case 1:
95
- gen_helper_neon_qabs_s16(tmp, cpu_env, tmp);
96
- break;
97
- case 2:
98
- gen_helper_neon_qabs_s32(tmp, cpu_env, tmp);
99
- break;
100
- default: abort();
101
- }
102
- break;
103
- case NEON_2RM_VQNEG:
104
- switch (size) {
105
- case 0:
106
- gen_helper_neon_qneg_s8(tmp, cpu_env, tmp);
107
- break;
108
- case 1:
109
- gen_helper_neon_qneg_s16(tmp, cpu_env, tmp);
110
- break;
111
- case 2:
112
- gen_helper_neon_qneg_s32(tmp, cpu_env, tmp);
113
- break;
114
- default: abort();
115
- }
116
- break;
117
case NEON_2RM_VCGT0_F:
118
{
119
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
120
--
83
--
121
2.20.1
84
2.20.1
122
85
123
86
diff view generated by jsdifflib
1
The NeonGenOneOpFn typedef breaks with the pattern of the other
1
In ptimer_reload(), we call the callback function provided by the
2
NeonGen*Fn typedefs, because it is a TCGv_i64 -> TCGv_i64 operation
2
timer device that is using the ptimer. This callback might disable
3
but it does not have '64' in its name. Rename it to NeonGenOne64OpFn,
3
the ptimer. The code mostly handles this correctly, except that
4
so that the old name is available for a TCGv_i32 -> TCGv_i32 operation
4
we'll still print the warning about "Timer with delta zero,
5
(which we will need in a subsequent commit).
5
disabling" if the now-disabled timer happened to be set such that it
6
would fire again immediately if it were enabled (eg because the
7
limit/reload value is zero).
8
9
Suppress the spurious warning message and the unnecessary
10
repeat-deletion of the underlying timer in this case.
6
11
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20200616170844.13318-10-peter.maydell@linaro.org
14
Message-id: 20201015151829.14656-2-peter.maydell@linaro.org
10
---
15
---
11
target/arm/translate.h | 2 +-
16
hw/core/ptimer.c | 4 ++++
12
target/arm/translate-a64.c | 4 ++--
17
1 file changed, 4 insertions(+)
13
2 files changed, 3 insertions(+), 3 deletions(-)
14
18
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
19
diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c
16
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.h
21
--- a/hw/core/ptimer.c
18
+++ b/target/arm/translate.h
22
+++ b/hw/core/ptimer.c
19
@@ -XXX,XX +XXX,XX @@ typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
23
@@ -XXX,XX +XXX,XX @@ static void ptimer_reload(ptimer_state *s, int delta_adjust)
20
typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
24
}
21
typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
25
22
typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
26
if (delta == 0) {
23
-typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
27
+ if (s->enabled == 0) {
24
+typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
28
+ /* trigger callback disabled the timer already */
25
typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
29
+ return;
26
typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
30
+ }
27
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
31
if (!qtest_enabled()) {
28
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
32
fprintf(stderr, "Timer with delta zero, disabling\n");
29
index XXXXXXX..XXXXXXX 100644
33
}
30
--- a/target/arm/translate-a64.c
31
+++ b/target/arm/translate-a64.c
32
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
33
} else {
34
for (pass = 0; pass < maxpass; pass++) {
35
TCGv_i64 tcg_op = tcg_temp_new_i64();
36
- NeonGenOneOpFn *genfn;
37
- static NeonGenOneOpFn * const fns[2][2] = {
38
+ NeonGenOne64OpFn *genfn;
39
+ static NeonGenOne64OpFn * const fns[2][2] = {
40
{ gen_helper_neon_addlp_s8, gen_helper_neon_addlp_u8 },
41
{ gen_helper_neon_addlp_s16, gen_helper_neon_addlp_u16 },
42
};
43
--
34
--
44
2.20.1
35
2.20.1
45
36
46
37
diff view generated by jsdifflib
1
Convert the Neon insns in the 2-reg-misc group which are
1
The armv7m systick timer is a 24-bit decrementing, wrap-on-zero,
2
VCVT between f32 and f16 to decodetree.
2
clear-on-write counter. Our current implementation has various
3
bugs and dubious workarounds in it (for instance see
4
https://bugs.launchpad.net/qemu/+bug/1872237).
5
6
We have an implementation of a simple decrementing counter
7
and we put a lot of effort into making sure it handles the
8
interesting corner cases (like "spend a cycle at 0 before
9
reloading") -- ptimer.
10
11
Rewrite the systick timer to use a ptimer rather than
12
a raw QEMU timer.
13
14
Unfortunately this is a migration compatibility break,
15
which will affect all M-profile boards.
16
17
Among other bugs, this fixes
18
https://bugs.launchpad.net/qemu/+bug/1872237 :
19
now writes to SYST_CVR when the timer is enabled correctly
20
do nothing; when the timer is enabled via SYST_CSR.ENABLE,
21
the ptimer code will (because of POLICY_NO_IMMEDIATE_RELOAD)
22
arrange that after one timer tick the counter is reloaded
23
from SYST_RVR and then counts down from there, as the
24
architecture requires.
3
25
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
27
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-id: 20200616170844.13318-7-peter.maydell@linaro.org
28
Message-id: 20201015151829.14656-3-peter.maydell@linaro.org
7
---
29
---
8
target/arm/neon-dp.decode | 3 ++
30
include/hw/timer/armv7m_systick.h | 3 +-
9
target/arm/translate-neon.inc.c | 96 +++++++++++++++++++++++++++++++++
31
hw/timer/armv7m_systick.c | 124 +++++++++++++-----------------
10
target/arm/translate.c | 65 ++--------------------
32
2 files changed, 54 insertions(+), 73 deletions(-)
11
3 files changed, 102 insertions(+), 62 deletions(-)
33
12
34
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
13
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
14
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/neon-dp.decode
36
--- a/include/hw/timer/armv7m_systick.h
16
+++ b/target/arm/neon-dp.decode
37
+++ b/include/hw/timer/armv7m_systick.h
17
@@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
38
@@ -XXX,XX +XXX,XX @@
18
VQMOVN_U 1111 001 11 . 11 .. 10 .... 0 0101 1 . 0 .... @2misc_q0
39
19
40
#include "hw/sysbus.h"
20
VSHLL 1111 001 11 . 11 .. 10 .... 0 0110 0 . 0 .... @2misc_q0
41
#include "qom/object.h"
42
+#include "hw/ptimer.h"
43
44
#define TYPE_SYSTICK "armv7m_systick"
45
46
@@ -XXX,XX +XXX,XX @@ struct SysTickState {
47
uint32_t control;
48
uint32_t reload;
49
int64_t tick;
50
- QEMUTimer *timer;
51
+ ptimer_state *ptimer;
52
MemoryRegion iomem;
53
qemu_irq irq;
54
};
55
diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/timer/armv7m_systick.c
58
+++ b/hw/timer/armv7m_systick.c
59
@@ -XXX,XX +XXX,XX @@ static inline int64_t systick_scale(SysTickState *s)
60
}
61
}
62
63
-static void systick_reload(SysTickState *s, int reset)
64
-{
65
- /* The Cortex-M3 Devices Generic User Guide says that "When the
66
- * ENABLE bit is set to 1, the counter loads the RELOAD value from the
67
- * SYST RVR register and then counts down". So, we need to check the
68
- * ENABLE bit before reloading the value.
69
- */
70
- trace_systick_reload();
71
-
72
- if ((s->control & SYSTICK_ENABLE) == 0) {
73
- return;
74
- }
75
-
76
- if (reset) {
77
- s->tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
78
- }
79
- s->tick += (s->reload + 1) * systick_scale(s);
80
- timer_mod(s->timer, s->tick);
81
-}
82
-
83
static void systick_timer_tick(void *opaque)
84
{
85
SysTickState *s = (SysTickState *)opaque;
86
@@ -XXX,XX +XXX,XX @@ static void systick_timer_tick(void *opaque)
87
/* Tell the NVIC to pend the SysTick exception */
88
qemu_irq_pulse(s->irq);
89
}
90
- if (s->reload == 0) {
91
- s->control &= ~SYSTICK_ENABLE;
92
- } else {
93
- systick_reload(s, 0);
94
+ if (ptimer_get_limit(s->ptimer) == 0) {
95
+ /*
96
+ * Timer expiry with SYST_RVR zero disables the timer
97
+ * (but doesn't clear SYST_CSR.ENABLE)
98
+ */
99
+ ptimer_stop(s->ptimer);
100
}
101
}
102
103
@@ -XXX,XX +XXX,XX @@ static MemTxResult systick_read(void *opaque, hwaddr addr, uint64_t *data,
104
s->control &= ~SYSTICK_COUNTFLAG;
105
break;
106
case 0x4: /* SysTick Reload Value. */
107
- val = s->reload;
108
+ val = ptimer_get_limit(s->ptimer);
109
break;
110
case 0x8: /* SysTick Current Value. */
111
- {
112
- int64_t t;
113
-
114
- if ((s->control & SYSTICK_ENABLE) == 0) {
115
- val = 0;
116
- break;
117
- }
118
- t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
119
- if (t >= s->tick) {
120
- val = 0;
121
- break;
122
- }
123
- val = ((s->tick - (t + 1)) / systick_scale(s)) + 1;
124
- /* The interrupt in triggered when the timer reaches zero.
125
- However the counter is not reloaded until the next clock
126
- tick. This is a hack to return zero during the first tick. */
127
- if (val > s->reload) {
128
- val = 0;
129
- }
130
+ val = ptimer_get_count(s->ptimer);
131
break;
132
- }
133
case 0xc: /* SysTick Calibration Value. */
134
val = 10000;
135
break;
136
@@ -XXX,XX +XXX,XX @@ static MemTxResult systick_write(void *opaque, hwaddr addr,
137
switch (addr) {
138
case 0x0: /* SysTick Control and Status. */
139
{
140
- uint32_t oldval = s->control;
141
+ uint32_t oldval;
142
143
+ ptimer_transaction_begin(s->ptimer);
144
+ oldval = s->control;
145
s->control &= 0xfffffff8;
146
s->control |= value & 7;
21
+
147
+
22
+ VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0
148
if ((oldval ^ value) & SYSTICK_ENABLE) {
23
+ VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0
149
- int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
24
]
150
if (value & SYSTICK_ENABLE) {
25
151
- if (s->tick) {
26
# Subgroup for size != 0b11
152
- s->tick += now;
27
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
153
- timer_mod(s->timer, s->tick);
28
index XXXXXXX..XXXXXXX 100644
154
- } else {
29
--- a/target/arm/translate-neon.inc.c
155
- systick_reload(s, 1);
30
+++ b/target/arm/translate-neon.inc.c
31
@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a)
32
tcg_temp_free_i32(rm1);
33
return true;
34
}
35
+
36
+static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a)
37
+{
38
+ TCGv_ptr fpst;
39
+ TCGv_i32 ahp, tmp, tmp2, tmp3;
40
+
41
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
42
+ !dc_isar_feature(aa32_fp16_spconv, s)) {
43
+ return false;
44
+ }
45
+
46
+ /* UNDEF accesses to D16-D31 if they don't exist. */
47
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
48
+ ((a->vd | a->vm) & 0x10)) {
49
+ return false;
50
+ }
51
+
52
+ if ((a->vm & 1) || (a->size != 1)) {
53
+ return false;
54
+ }
55
+
56
+ if (!vfp_access_check(s)) {
57
+ return true;
58
+ }
59
+
60
+ fpst = get_fpstatus_ptr(true);
61
+ ahp = get_ahp_flag();
62
+ tmp = neon_load_reg(a->vm, 0);
63
+ gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
64
+ tmp2 = neon_load_reg(a->vm, 1);
65
+ gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp);
66
+ tcg_gen_shli_i32(tmp2, tmp2, 16);
67
+ tcg_gen_or_i32(tmp2, tmp2, tmp);
68
+ tcg_temp_free_i32(tmp);
69
+ tmp = neon_load_reg(a->vm, 2);
70
+ gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
71
+ tmp3 = neon_load_reg(a->vm, 3);
72
+ neon_store_reg(a->vd, 0, tmp2);
73
+ gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp);
74
+ tcg_gen_shli_i32(tmp3, tmp3, 16);
75
+ tcg_gen_or_i32(tmp3, tmp3, tmp);
76
+ neon_store_reg(a->vd, 1, tmp3);
77
+ tcg_temp_free_i32(tmp);
78
+ tcg_temp_free_i32(ahp);
79
+ tcg_temp_free_ptr(fpst);
80
+
81
+ return true;
82
+}
83
+
84
+static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a)
85
+{
86
+ TCGv_ptr fpst;
87
+ TCGv_i32 ahp, tmp, tmp2, tmp3;
88
+
89
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
90
+ !dc_isar_feature(aa32_fp16_spconv, s)) {
91
+ return false;
92
+ }
93
+
94
+ /* UNDEF accesses to D16-D31 if they don't exist. */
95
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
96
+ ((a->vd | a->vm) & 0x10)) {
97
+ return false;
98
+ }
99
+
100
+ if ((a->vd & 1) || (a->size != 1)) {
101
+ return false;
102
+ }
103
+
104
+ if (!vfp_access_check(s)) {
105
+ return true;
106
+ }
107
+
108
+ fpst = get_fpstatus_ptr(true);
109
+ ahp = get_ahp_flag();
110
+ tmp3 = tcg_temp_new_i32();
111
+ tmp = neon_load_reg(a->vm, 0);
112
+ tmp2 = neon_load_reg(a->vm, 1);
113
+ tcg_gen_ext16u_i32(tmp3, tmp);
114
+ gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
115
+ neon_store_reg(a->vd, 0, tmp3);
116
+ tcg_gen_shri_i32(tmp, tmp, 16);
117
+ gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp);
118
+ neon_store_reg(a->vd, 1, tmp);
119
+ tmp3 = tcg_temp_new_i32();
120
+ tcg_gen_ext16u_i32(tmp3, tmp2);
121
+ gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
122
+ neon_store_reg(a->vd, 2, tmp3);
123
+ tcg_gen_shri_i32(tmp2, tmp2, 16);
124
+ gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp);
125
+ neon_store_reg(a->vd, 3, tmp2);
126
+ tcg_temp_free_i32(ahp);
127
+ tcg_temp_free_ptr(fpst);
128
+
129
+ return true;
130
+}
131
diff --git a/target/arm/translate.c b/target/arm/translate.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/target/arm/translate.c
134
+++ b/target/arm/translate.c
135
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
136
int pass;
137
int u;
138
int vec_size;
139
- TCGv_i32 tmp, tmp2, tmp3;
140
+ TCGv_i32 tmp, tmp2;
141
142
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
143
return 1;
144
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
145
case NEON_2RM_VZIP:
146
case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN:
147
case NEON_2RM_VSHLL:
148
+ case NEON_2RM_VCVT_F16_F32:
149
+ case NEON_2RM_VCVT_F32_F16:
150
/* handled by decodetree */
151
return 1;
152
case NEON_2RM_VTRN:
153
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
154
goto elementwise;
155
}
156
break;
157
- case NEON_2RM_VCVT_F16_F32:
158
- {
159
- TCGv_ptr fpst;
160
- TCGv_i32 ahp;
161
-
162
- if (!dc_isar_feature(aa32_fp16_spconv, s) ||
163
- q || (rm & 1)) {
164
- return 1;
165
- }
166
- fpst = get_fpstatus_ptr(true);
167
- ahp = get_ahp_flag();
168
- tmp = neon_load_reg(rm, 0);
169
- gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
170
- tmp2 = neon_load_reg(rm, 1);
171
- gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp);
172
- tcg_gen_shli_i32(tmp2, tmp2, 16);
173
- tcg_gen_or_i32(tmp2, tmp2, tmp);
174
- tcg_temp_free_i32(tmp);
175
- tmp = neon_load_reg(rm, 2);
176
- gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
177
- tmp3 = neon_load_reg(rm, 3);
178
- neon_store_reg(rd, 0, tmp2);
179
- gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp);
180
- tcg_gen_shli_i32(tmp3, tmp3, 16);
181
- tcg_gen_or_i32(tmp3, tmp3, tmp);
182
- neon_store_reg(rd, 1, tmp3);
183
- tcg_temp_free_i32(tmp);
184
- tcg_temp_free_i32(ahp);
185
- tcg_temp_free_ptr(fpst);
186
- break;
187
- }
156
- }
188
- case NEON_2RM_VCVT_F32_F16:
157
+ /*
189
- {
158
+ * Always reload the period in case board code has
190
- TCGv_ptr fpst;
159
+ * changed system_clock_scale. If we ever replace that
191
- TCGv_i32 ahp;
160
+ * global with a more sensible API then we might be able
192
- if (!dc_isar_feature(aa32_fp16_spconv, s) ||
161
+ * to set the period only when it actually changes.
193
- q || (rd & 1)) {
162
+ */
194
- return 1;
163
+ ptimer_set_period(s->ptimer, systick_scale(s));
195
- }
164
+ ptimer_run(s->ptimer, 0);
196
- fpst = get_fpstatus_ptr(true);
165
} else {
197
- ahp = get_ahp_flag();
166
- timer_del(s->timer);
198
- tmp3 = tcg_temp_new_i32();
167
- s->tick -= now;
199
- tmp = neon_load_reg(rm, 0);
168
- if (s->tick < 0) {
200
- tmp2 = neon_load_reg(rm, 1);
169
- s->tick = 0;
201
- tcg_gen_ext16u_i32(tmp3, tmp);
202
- gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
203
- neon_store_reg(rd, 0, tmp3);
204
- tcg_gen_shri_i32(tmp, tmp, 16);
205
- gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp);
206
- neon_store_reg(rd, 1, tmp);
207
- tmp3 = tcg_temp_new_i32();
208
- tcg_gen_ext16u_i32(tmp3, tmp2);
209
- gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
210
- neon_store_reg(rd, 2, tmp3);
211
- tcg_gen_shri_i32(tmp2, tmp2, 16);
212
- gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp);
213
- neon_store_reg(rd, 3, tmp2);
214
- tcg_temp_free_i32(ahp);
215
- tcg_temp_free_ptr(fpst);
216
- break;
217
- }
170
- }
218
case NEON_2RM_AESE: case NEON_2RM_AESMC:
171
+ ptimer_stop(s->ptimer);
219
if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) {
172
}
220
return 1;
173
} else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
174
- /* This is a hack. Force the timer to be reloaded
175
- when the reference clock is changed. */
176
- systick_reload(s, 1);
177
+ ptimer_set_period(s->ptimer, systick_scale(s));
178
}
179
+ ptimer_transaction_commit(s->ptimer);
180
break;
181
}
182
case 0x4: /* SysTick Reload Value. */
183
- s->reload = value;
184
+ ptimer_transaction_begin(s->ptimer);
185
+ ptimer_set_limit(s->ptimer, value & 0xffffff, 0);
186
+ ptimer_transaction_commit(s->ptimer);
187
break;
188
- case 0x8: /* SysTick Current Value. Writes reload the timer. */
189
- systick_reload(s, 1);
190
+ case 0x8: /* SysTick Current Value. */
191
+ /*
192
+ * Writing any value clears SYST_CVR to zero and clears
193
+ * SYST_CSR.COUNTFLAG. The counter will then reload from SYST_RVR
194
+ * on the next clock edge unless SYST_RVR is zero.
195
+ */
196
+ ptimer_transaction_begin(s->ptimer);
197
+ if (ptimer_get_limit(s->ptimer) == 0) {
198
+ ptimer_stop(s->ptimer);
199
+ }
200
+ ptimer_set_count(s->ptimer, 0);
201
s->control &= ~SYSTICK_COUNTFLAG;
202
+ ptimer_transaction_commit(s->ptimer);
203
break;
204
default:
205
qemu_log_mask(LOG_GUEST_ERROR,
206
@@ -XXX,XX +XXX,XX @@ static void systick_reset(DeviceState *dev)
207
*/
208
assert(system_clock_scale != 0);
209
210
+ ptimer_transaction_begin(s->ptimer);
211
s->control = 0;
212
- s->reload = 0;
213
- s->tick = 0;
214
- timer_del(s->timer);
215
+ ptimer_stop(s->ptimer);
216
+ ptimer_set_count(s->ptimer, 0);
217
+ ptimer_set_limit(s->ptimer, 0, 0);
218
+ ptimer_set_period(s->ptimer, systick_scale(s));
219
+ ptimer_transaction_commit(s->ptimer);
220
}
221
222
static void systick_instance_init(Object *obj)
223
@@ -XXX,XX +XXX,XX @@ static void systick_instance_init(Object *obj)
224
static void systick_realize(DeviceState *dev, Error **errp)
225
{
226
SysTickState *s = SYSTICK(dev);
227
- s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
228
+ s->ptimer = ptimer_init(systick_timer_tick, s,
229
+ PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
230
+ PTIMER_POLICY_NO_COUNTER_ROUND_DOWN |
231
+ PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
232
+ PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
233
}
234
235
static const VMStateDescription vmstate_systick = {
236
.name = "armv7m_systick",
237
- .version_id = 1,
238
- .minimum_version_id = 1,
239
+ .version_id = 2,
240
+ .minimum_version_id = 2,
241
.fields = (VMStateField[]) {
242
VMSTATE_UINT32(control, SysTickState),
243
- VMSTATE_UINT32(reload, SysTickState),
244
VMSTATE_INT64(tick, SysTickState),
245
- VMSTATE_TIMER_PTR(timer, SysTickState),
246
+ VMSTATE_PTIMER(ptimer, SysTickState),
247
VMSTATE_END_OF_LIST()
248
}
249
};
221
--
250
--
222
2.20.1
251
2.20.1
223
252
224
253
diff view generated by jsdifflib