Series comparison

-[PULL 00/42] target-arm queue
+[PULL 00/29] target-arm queue
-The following changes since commit 61fee7f45955cd0bf9b79be9fa9c7ebabb5e6a85:
+Arm queue; some of the simpler stuff, things other have reviewed (thanks!), etc.
-  Merge remote-tracking branch 'remotes/philmd-gitlab/tags/acceptance-testing-20200622' into staging (2020-06-22 20:50:10 +0100)
+-- PMM
 The following changes since commit 5d2f557b47dfbf8f23277a5bdd8473d4607c681a:
   Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200605-pull-request' into staging (2020-06-05 13:53:05 +0100)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200623
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200605
-for you to fetch changes up to 539533b85fbd269f777bed931de8ccae1dd837e9:
+for you to fetch changes up to 2c35a39eda0b16c2ed85c94cec204bf5efb97812:
-  arm/virt: Add memory hot remove support (2020-06-23 11:39:48 +0100)
+  target/arm: Convert Neon one-register-and-immediate insns to decodetree (2020-06-05 17:23:10 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * util/oslib-posix : qemu_init_exec_dir implementation for Mac
+ hw/ssi/imx_spi: Handle tx burst lengths other than 8 correctly
- * target/arm: Last parts of neon decodetree conversion
+ hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()
- * hw/arm/virt: Add 5.0 HW compat props
+ hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()
- * hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status
+ target/arm: Convert crypto insns to gvec
- * mps2: Add CMSDK APB watchdog, FPGAIO block, S2I devices and I2C devices
+ hw/adc/stm32f2xx_adc: Correct memory region size and access size
- * mps2: Add some unimplemented-device stubs for audio and GPIO
+ tests/acceptance: Add a boot test for the xlnx-versal-virt machine
- * mps2-tz: Use the ARM SBCon two-wire serial bus interface
+ docs/system: Document Aspeed boards
- * target/arm: Check supported KVM features globally (not per vCPU)
+ raspi: Add model of the USB controller
- * tests/qtest/arm-cpu-features: Add feature setting tests
+ target/arm: Convert 2-reg-and-shift and 1-reg-imm Neon insns to decodetree
  * arm/virt: Add memory hot remove support
 ----------------------------------------------------------------
-Andrew Jones (2):
+Cédric Le Goater (1):
-      hw/arm/virt: Add 5.0 HW compat props
+      docs/system: Document Aspeed boards
       tests/qtest/arm-cpu-features: Add feature setting tests
-David CARLIER (1):
+Eden Mikitas (2):
-      util/oslib-posix : qemu_init_exec_dir implementation for Mac
+      hw/ssi/imx_spi: changed while statement to prevent underflow
       hw/ssi/imx_spi: Removed unnecessary cast of rx data received from slave
-Peter Maydell (23):
+Paul Zimmerman (7):
-      target/arm: Convert Neon 2-reg-misc VREV64 to decodetree
+      raspi: add BCM2835 SOC MPHI emulation
-      target/arm: Convert Neon 2-reg-misc pairwise ops to decodetree
+      dwc-hsotg (dwc2) USB host controller register definitions
-      target/arm: Convert VZIP, VUZP to decodetree
+      dwc-hsotg (dwc2) USB host controller state definitions
-      target/arm: Convert Neon narrowing moves to decodetree
+      dwc-hsotg (dwc2) USB host controller emulation
-      target/arm: Convert Neon 2-reg-misc VSHLL to decodetree
+      usb: add short-packet handling to usb-storage driver
-      target/arm: Convert Neon VCVT f16/f32 insns to decodetree
+      wire in the dwc-hsotg (dwc2) USB host controller emulation
-      target/arm: Convert vectorised 2-reg-misc Neon ops to decodetree
+      raspi2 acceptance test: add test for dwc-hsotg (dwc2) USB host
       target/arm: Convert Neon 2-reg-misc crypto operations to decodetree
       target/arm: Rename NeonGenOneOpFn to NeonGenOne64OpFn
       target/arm: Fix capitalization in NeonGenTwo{Single, Double}OPFn typedefs
       target/arm: Make gen_swap_half() take separate src and dest
       target/arm: Convert Neon 2-reg-misc VREV32 and VREV16 to decodetree
       target/arm: Convert remaining simple 2-reg-misc Neon ops
       target/arm: Convert Neon VQABS, VQNEG to decodetree
       target/arm: Convert simple fp Neon 2-reg-misc insns
       target/arm: Convert Neon 2-reg-misc fp-compare-with-zero insns to decodetree
       target/arm: Convert Neon 2-reg-misc VRINT insns to decodetree
       target/arm: Convert Neon 2-reg-misc VCVT insns to decodetree
       target/arm: Convert Neon VSWP to decodetree
       target/arm: Convert Neon VTRN to decodetree
       target/arm: Move some functions used only in translate-neon.inc.c to that file
       target/arm: Remove unnecessary gen_io_end() calls
       target/arm: Remove dead code relating to SABA and UABA
-Philippe Mathieu-Daudé (15):
+Peter Maydell (9):
-      hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status
+      target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree
-      hw/i2c/versatile_i2c: Add definitions for register addresses
+      target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree
-      hw/i2c/versatile_i2c: Add SCL/SDA definitions
+      target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree
-      hw/i2c: Add header for ARM SBCon two-wire serial bus interface
+      target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree
-      hw/arm: Use TYPE_VERSATILE_I2C instead of hardcoded string
+      target/arm: Convert Neon narrowing shifts with op==8 to decodetree
-      hw/arm/mps2: Document CMSDK/FPGA APB subsystem sections
+      target/arm: Convert Neon narrowing shifts with op==9 to decodetree
-      hw/arm/mps2: Rename CMSDK AHB peripheral region
+      target/arm: Convert Neon VSHLL, VMOVL to decodetree
-      hw/arm/mps2: Add CMSDK APB watchdog device
+      target/arm: Convert VCVT fixed-point ops to decodetree
-      hw/arm/mps2: Add CMSDK AHB GPIO peripherals as unimplemented devices
+      target/arm: Convert Neon one-register-and-immediate insns to decodetree
       hw/arm/mps2: Map the FPGA I/O block
       hw/arm/mps2: Add SPI devices
       hw/arm/mps2: Add I2C devices
       hw/arm/mps2: Add audio I2S interface as unimplemented device
       hw/arm/mps2-tz: Use the ARM SBCon two-wire serial bus interface
       target/arm: Check supported KVM features globally (not per vCPU)
-Shameer Kolothum (1):
+Philippe Mathieu-Daudé (3):
-      arm/virt: Add memory hot remove support
+      hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()
       hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()
       hw/adc/stm32f2xx_adc: Correct memory region size and access size
- include/hw/i2c/arm_sbcon_i2c.h   |   35 ++
+Richard Henderson (6):
- target/arm/cpu.h                 |    2 +-
+      target/arm: Convert aes and sm4 to gvec helpers
- target/arm/kvm_arm.h             |   21 +-
+      target/arm: Convert rax1 to gvec helpers
- target/arm/translate.h           |    8 +-
+      target/arm: Convert sha512 and sm3 to gvec helpers
- target/arm/neon-dp.decode        |  106 ++++
+      target/arm: Convert sha1 and sha256 to gvec helpers
- hw/acpi/generic_event_device.c   |   29 +
+      target/arm: Split helper_crypto_sha1_3reg
- hw/arm/mps2-tz.c                 |   23 +-
+      target/arm: Split helper_crypto_sm3tt
  hw/arm/mps2.c                    |   65 ++-
  hw/arm/realview.c                |    3 +-
  hw/arm/versatilepb.c             |    3 +-
  hw/arm/vexpress.c                |    3 +-
  hw/arm/virt.c                    |   63 +-
  hw/i2c/versatile_i2c.c           |   38 +-
  hw/watchdog/cmsdk-apb-watchdog.c |    1 +
  target/arm/cpu.c                 |    2 +-
  target/arm/cpu64.c               |   10 +-
  target/arm/kvm.c                 |    4 +-
  target/arm/kvm64.c               |   14 +-
  target/arm/translate-a64.c       |   20 +-
  target/arm/translate-neon.inc.c  | 1191 +++++++++++++++++++++++++++++++++++++-
  target/arm/translate-vfp.inc.c   |    7 +-
  target/arm/translate.c           | 1064 +---------------------------------
  tests/qtest/arm-cpu-features.c   |   38 +-
  util/oslib-posix.c               |   15 +
  MAINTAINERS                      |    1 +
  hw/arm/Kconfig                   |    8 +-
  hw/watchdog/trace-events         |    1 +
 files changed, 1624 insertions(+), 1151 deletions(-)
  create mode 100644 include/hw/i2c/arm_sbcon_i2c.h
+Thomas Huth (1):
+      tests/acceptance: Add a boot test for the xlnx-versal-virt machine
+ docs/system/arm/aspeed.rst             |   85 ++
+ docs/system/target-arm.rst             |    1 +
+ hw/usb/hcd-dwc2.h                      |  190 +++++
+ include/hw/arm/bcm2835_peripherals.h   |    5 +-
+ include/hw/misc/bcm2835_mphi.h         |   44 +
+ include/hw/usb/dwc2-regs.h             |  899 ++++++++++++++++++++
+ target/arm/helper.h                    |   45 +-
+ target/arm/translate-a64.h             |    3 +
+ target/arm/vec_internal.h              |   33 +
+ target/arm/neon-dp.decode              |  214 ++++-
+ hw/adc/stm32f2xx_adc.c                 |    4 +-
+ hw/arm/bcm2835_peripherals.c           |   38 +-
+ hw/arm/pxa2xx.c                        |   66 +-
+ hw/input/pxa2xx_keypad.c               |   10 +-
+ hw/misc/bcm2835_mphi.c                 |  191 +++++
+ hw/ssi/imx_spi.c                       |    4 +-
+ hw/usb/dev-storage.c                   |   15 +-
+ hw/usb/hcd-dwc2.c                      | 1417 ++++++++++++++++++++++++++++++++
+ target/arm/crypto_helper.c             |  267 ++++--
+ target/arm/translate-a64.c             |  198 ++---
+ target/arm/translate-neon.inc.c        |  796 ++++++++++++++----
+ target/arm/translate.c                 |  539 +-----------
+ target/arm/vec_helper.c                |   12 +-
+ hw/misc/Makefile.objs                  |    1 +
+ hw/usb/Kconfig                         |    5 +
+ hw/usb/Makefile.objs                   |    1 +
+ hw/usb/trace-events                    |   50 ++
+ tests/acceptance/boot_linux_console.py |   35 +-
+files changed, 4258 insertions(+), 910 deletions(-)
+ create mode 100644 docs/system/arm/aspeed.rst
+ create mode 100644 hw/usb/hcd-dwc2.h
+ create mode 100644 include/hw/misc/bcm2835_mphi.h
+ create mode 100644 include/hw/usb/dwc2-regs.h
+ create mode 100644 target/arm/vec_internal.h
+ create mode 100644 hw/misc/bcm2835_mphi.c
+ create mode 100644 hw/usb/hcd-dwc2.c

-[PULL 01/42] hw/arm/virt: Add 5.0 HW compat props
+Deleted patch
-From: Andrew Jones <drjones@redhat.com>
-Cc: Cornelia Huck <cohuck@redhat.com>
-Signed-off-by: Andrew Jones <drjones@redhat.com>
-Reviewed-by: Cornelia Huck <cohuck@redhat.com>
-Message-id: 20200616140803.25515-1-drjones@redhat.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/arm/virt.c | 1 +
-file changed, 1 insertion(+)
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
-+++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 1)
- static void virt_machine_5_0_options(MachineClass *mc)
- {
-     virt_machine_5_1_options(mc);
-+    compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
- }
- DEFINE_VIRT_MACHINE(5, 0)
---
-.20.1

-[PULL 02/42] util/oslib-posix : qemu_init_exec_dir implementation for Mac
+Deleted patch
-From: David CARLIER <devnexen@gmail.com>
-From 3025a0ce3fdf7d3559fc35a52c659f635f5c750c Mon Sep 17 00:00:00 2001
-From: David Carlier <devnexen@gmail.com>
-Date: Tue, 26 May 2020 21:35:27 +0100
-Subject: [PATCH] util/oslib-posix : qemu_init_exec_dir implementation for Mac
-Using dyld API to get the full path of the current process.
-Signed-off-by: David Carlier <devnexen@gmail.com>
-Message-id: CA+XhMqxwC10XHVs4Z-JfE0-WLAU3ztDuU9QKVi31mjr59HWCxg@mail.gmail.com
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- util/oslib-posix.c | 15 +++++++++++++++
-file changed, 15 insertions(+)
-diff --git a/util/oslib-posix.c b/util/oslib-posix.c
-index XXXXXXX..XXXXXXX 100644
---- a/util/oslib-posix.c
-+++ b/util/oslib-posix.c
-@@ -XXX,XX +XXX,XX @@
- #include <lwp.h>
- #endif
-+#ifdef __APPLE__
-+#include <mach-o/dyld.h>
-+#endif
-+
- #include "qemu/mmap-alloc.h"
- #ifdef CONFIG_DEBUG_STACK_USAGE
-@@ -XXX,XX +XXX,XX @@ void qemu_init_exec_dir(const char *argv0)
-             p = buf;
-         }
-     }
-+#elif defined(__APPLE__)
-+    {
-+        char fpath[PATH_MAX];
-+        uint32_t len = sizeof(fpath);
-+        if (_NSGetExecutablePath(fpath, &len) == 0) {
-+            p = realpath(fpath, buf);
-+            if (!p) {
-+                return;
-+            }
-+        }
-+    }
- #endif
-     /* If we don't have any way of figuring out the actual executable
-        location then try argv[0].  */
---
-.20.1

-[PULL 39/42] hw/arm/mps2-tz: Use the ARM SBCon two-wire serial bus interface
+[PULL 01/29] hw/ssi/imx_spi: changed while statement to prevent underflow
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Eden Mikitas <e.mikitas@gmail.com>
-From 'Application Note AN521', chapter 4.7:
+The while statement in question only checked if tx_burst is not 0.
 tx_burst is a signed int, which is assigned the value put by the
 guest driver in ECSPI_CONREG. The burst length can be anywhere
 between 1 and 4096, and since tx_burst is always decremented by 8
 it could possibly underflow, causing an infinite loop.
-  The SMM implements four SBCon serial modules:
+Signed-off-by: Eden Mikitas <e.mikitas@gmail.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
   One SBCon module for use by the Color LCD touch interface.
   One SBCon module to configure the audio controller.
   Two general purpose SBCon modules, that connect to the
   Expansion headers J7 and J8, are intended for use with the
   V2C-Shield1 which provide an I2C interface on the headers.
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20200617072539.32686-15-f4bug@amsat.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/mps2-tz.c | 23 ++++++++++++++++++-----
+ hw/ssi/imx_spi.c | 2 +-
-file changed, 18 insertions(+), 5 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
+diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/mps2-tz.c
+--- a/hw/ssi/imx_spi.c
-+++ b/hw/arm/mps2-tz.c
++++ b/hw/ssi/imx_spi.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
- #include "hw/arm/armsse.h"
- #include "hw/dma/pl080.h"
+         rx = 0;
- #include "hw/ssi/pl022.h"
-+#include "hw/i2c/arm_sbcon_i2c.h"
+-        while (tx_burst) {
- #include "hw/net/lan9118.h"
++        while (tx_burst > 0) {
- #include "net/net.h"
+             uint8_t byte = tx & 0xff;
- #include "hw/core/split-irq.h"
-@@ -XXX,XX +XXX,XX @@ typedef struct {
+             DPRINTF("writing 0x%02x\n", (uint32_t)byte);
      TZPPC ppc[5];
      TZMPC ssram_mpc[3];
      PL022State spi[5];
 -    UnimplementedDeviceState i2c[4];
 +    ArmSbconI2CState i2c[4];
      UnimplementedDeviceState i2s_audio;
      UnimplementedDeviceState gpio[4];
      UnimplementedDeviceState gfx;
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque,
      return sysbus_mmio_get_region(s, 0);
  }
 +static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque,
 +                              const char *name, hwaddr size)
 +{
 +    ArmSbconI2CState *i2c = opaque;
 +    SysBusDevice *s;
 +
 +    object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C);
 +    s = SYS_BUS_DEVICE(i2c);
 +    sysbus_realize(s, &error_fatal);
 +    return sysbus_mmio_get_region(s, 0);
 +}
 +
  static void mps2tz_common_init(MachineState *machine)
  {
      MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine);
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
                  { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 },
                  { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 },
                  { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 },
 -                { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 },
 -                { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 },
 -                { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 },
 -                { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 },
 +                { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 },
 +                { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 },
 +                { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 },
 +                { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000 },
              },
          }, {
              .name = "apb_ppcexp2",
 --
 .20.1

-[PULL 38/42] hw/arm/mps2: Add audio I2S interface as unimplemented device
+[PULL 02/29] hw/ssi/imx_spi: Removed unnecessary cast of rx data received from slave
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Eden Mikitas <e.mikitas@gmail.com>
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+When inserting the value retrieved (rx) from the spi slave, rx is pushed to
-Message-id: 20200617072539.32686-14-f4bug@amsat.org
+rx_fifo after being cast to uint8_t. rx_fifo is a fifo32, and the rx
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+register the driver uses is also 32 bit. This zeroes the 24 most
 significant bits of rx. This proved problematic with devices that expect to
 use the whole 32 bits of the rx register.
 Signed-off-by: Eden Mikitas <e.mikitas@gmail.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/mps2.c | 1 +
+ hw/ssi/imx_spi.c | 2 +-
-file changed, 1 insertion(+)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
+diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/mps2.c
+--- a/hw/ssi/imx_spi.c
-+++ b/hw/arm/mps2.c
++++ b/hw/ssi/imx_spi.c
-@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
-x4002a000};   /* Shield1 */
+         if (fifo32_is_full(&s->rx_fifo)) {
-         sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL);
+             s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RO;
-     }
+         } else {
-+    create_unimplemented_device("i2s", 0x40024000, 0x400);
+-            fifo32_push(&s->rx_fifo, (uint8_t)rx);
++            fifo32_push(&s->rx_fifo, rx);
-     /* In hardware this is a LAN9220; the LAN9118 is software compatible
+         }
-      * except that it doesn't support the checksum-offload feature.
          if (s->burst_length <= 0) {
 --
 .20.1

-[PULL 30/42] hw/arm: Use TYPE_VERSATILE_I2C instead of hardcoded string
+[PULL 03/29] hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()
 From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-By using the TYPE_* definitions for devices, we can:
+hw_error() calls exit(). This a bit overkill when we can log
- - quickly find where devices are used with 'git-grep'
+the accesses as unimplemented or guest error.
- - easily rename a device (one-line change).
 When fuzzing the devices, we don't want the whole process to
 exit. Replace some hw_error() calls by qemu_log_mask()
 (missed in commit 5a0001ec7e).
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20200617072539.32686-6-f4bug@amsat.org
+Message-id: 20200525114123.21317-2-f4bug@amsat.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/realview.c    | 3 ++-
+ hw/input/pxa2xx_keypad.c | 10 +++++++---
- hw/arm/versatilepb.c | 3 ++-
+file changed, 7 insertions(+), 3 deletions(-)
  hw/arm/vexpress.c    | 3 ++-
 files changed, 6 insertions(+), 3 deletions(-)
-diff --git a/hw/arm/realview.c b/hw/arm/realview.c
+diff --git a/hw/input/pxa2xx_keypad.c b/hw/input/pxa2xx_keypad.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/realview.c
+--- a/hw/input/pxa2xx_keypad.c
-+++ b/hw/arm/realview.c
++++ b/hw/input/pxa2xx_keypad.c
 @@ -XXX,XX +XXX,XX @@
- #include "hw/cpu/a9mpcore.h"
+  */
- #include "hw/intc/realview_gic.h"
  #include "qemu/osdep.h"
 -#include "hw/hw.h"
 +#include "qemu/log.h"
  #include "hw/irq.h"
-+#include "hw/i2c/arm_sbcon_i2c.h"
+ #include "migration/vmstate.h"
+ #include "hw/arm/pxa.h"
- #define SMP_BOOT_ADDR 0xe0000000
+@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_keypad_read(void *opaque, hwaddr offset,
- #define SMP_BOOTREG_ADDR 0x10000030
+         return s->kpkdi;
-@@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine,
+         break;
-         }
+     default:
 -        hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
 +                      __func__, offset);
      }
--    dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
+     return 0;
-+    dev = sysbus_create_simple(TYPE_VERSATILE_I2C, 0x10002000, NULL);
+@@ -XXX,XX +XXX,XX @@ static void pxa2xx_keypad_write(void *opaque, hwaddr offset,
-     i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
+         break;
-     i2c_create_slave(i2c, "ds1338", 0x68);
+     default:
-diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
+-        hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
-index XXXXXXX..XXXXXXX 100644
++        qemu_log_mask(LOG_GUEST_ERROR,
---- a/hw/arm/versatilepb.c
++                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
-+++ b/hw/arm/versatilepb.c
++                      __func__, offset);
-@@ -XXX,XX +XXX,XX @@
+     }
- #include "sysemu/sysemu.h"
+ }
  #include "hw/pci/pci.h"
  #include "hw/i2c/i2c.h"
 +#include "hw/i2c/arm_sbcon_i2c.h"
  #include "hw/irq.h"
  #include "hw/boards.h"
  #include "exec/address-spaces.h"
@@ -XXX,XX +XXX,XX @@ static void versatile_init(MachineState *machine, int board_id)
      /* Add PL031 Real Time Clock. */
      sysbus_create_simple("pl031", 0x101e8000, pic[10]);
 -    dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
 +    dev = sysbus_create_simple(TYPE_VERSATILE_I2C, 0x10002000, NULL);
      i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
      i2c_create_slave(i2c, "ds1338", 0x68);
 diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/vexpress.c
 +++ b/hw/arm/vexpress.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/char/pl011.h"
  #include "hw/cpu/a9mpcore.h"
  #include "hw/cpu/a15mpcore.h"
 +#include "hw/i2c/arm_sbcon_i2c.h"
  #define VEXPRESS_BOARD_ID 0x8e0
  #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
      sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
      sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
 -    dev = sysbus_create_simple("versatile_i2c", map[VE_SERIALDVI], NULL);
 +    dev = sysbus_create_simple(TYPE_VERSATILE_I2C, map[VE_SERIALDVI], NULL);
      i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
      i2c_create_slave(i2c, "sii9022", 0x39);
 --
 .20.1

-[PULL 37/42] hw/arm/mps2: Add I2C devices
+[PULL 04/29] hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()
 From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-From 'Application Note AN385', chapter 3.14:
+Replace printf() calls by qemu_log_mask(), which is disabled
+by default. This avoid flooding the terminal when fuzzing the
-  The SMM implements a simple SBCon interface based on I2C.
+device.
 There are 4 SBCon interfaces on the FPGA APB subsystem.
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20200617072539.32686-13-f4bug@amsat.org
+Message-id: 20200525114123.21317-3-f4bug@amsat.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/mps2.c  | 8 ++++++++
+ hw/arm/pxa2xx.c | 66 ++++++++++++++++++++++++++++++++++++-------------
- hw/arm/Kconfig | 1 +
+file changed, 49 insertions(+), 17 deletions(-)
-files changed, 9 insertions(+)
+diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
 diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/mps2.c
+--- a/hw/arm/pxa2xx.c
-+++ b/hw/arm/mps2.c
++++ b/hw/arm/pxa2xx.c
 @@ -XXX,XX +XXX,XX @@
- #include "hw/misc/mps2-scc.h"
+ #include "sysemu/blockdev.h"
- #include "hw/misc/mps2-fpgaio.h"
+ #include "sysemu/qtest.h"
- #include "hw/ssi/pl022.h"
+ #include "qemu/cutils.h"
-+#include "hw/i2c/arm_sbcon_i2c.h"
++#include "qemu/log.h"
- #include "hw/net/lan9118.h"
- #include "net/net.h"
+ static struct {
- #include "hw/watchdog/cmsdk-apb-watchdog.h"
+     hwaddr io_base;
-@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
-                                  qdev_get_gpio_in(orgate_dev, j));
+         return s->pm_regs[addr >> 2];
-         }
+     default:
-     }
+     fail:
-+    for (i = 0; i < 4; i++) {
+-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
-+        static const hwaddr i2cbase[] = {0x40022000,    /* Touch */
++        qemu_log_mask(LOG_GUEST_ERROR,
-+                                         0x40023000,    /* Audio */
++                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
-+                                         0x40029000,    /* Shield0 */
++                      __func__, addr);
-+                                         0x4002a000};   /* Shield1 */
+         break;
-+        sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL);
+     }
-+    }
+     return 0;
+@@ -XXX,XX +XXX,XX @@ static void pxa2xx_pm_write(void *opaque, hwaddr addr,
-     /* In hardware this is a LAN9220; the LAN9118 is software compatible
+             s->pm_regs[addr >> 2] = value;
-      * except that it doesn't support the checksum-offload feature.
+             break;
-diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
+         }
-index XXXXXXX..XXXXXXX 100644
+-
---- a/hw/arm/Kconfig
+-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
-+++ b/hw/arm/Kconfig
++        qemu_log_mask(LOG_GUEST_ERROR,
-@@ -XXX,XX +XXX,XX @@ config MPS2
++                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
-     select SPLIT_IRQ
++                      __func__, addr);
-     select UNIMP
+         break;
-     select CMSDK_APB_WATCHDOG
+     }
-+    select VERSATILE_I2C
+ }
+@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
- config FSL_IMX7
+         return s->cm_regs[CCCR >> 2] | (3 << 28);
-     bool
      default:
 -        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
 +                      __func__, addr);
          break;
      }
      return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_cm_write(void *opaque, hwaddr addr,
          break;
      default:
 -        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
 +                      __func__, addr);
          break;
      }
  }
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
              return s->mm_regs[addr >> 2];
          /* fall through */
      default:
 -        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
 +                      __func__, addr);
          break;
      }
      return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_mm_write(void *opaque, hwaddr addr,
          }
      default:
 -        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
 +                      __func__, addr);
          break;
      }
  }
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
      case SSACD:
          return s->ssacd;
      default:
 -        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
 +                      __func__, addr);
          break;
      }
      return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
          break;
      default:
 -        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
 +                      __func__, addr);
          break;
      }
  }
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
          else
              return s->last_swcr;
      default:
 -        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
 +                      __func__, addr);
          break;
      }
      return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
          break;
      default:
 -        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
 +                      __func__, addr);
      }
  }
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
              s->ibmr = 0;
          return s->ibmr;
      default:
 -        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
 +                      __func__, addr);
          break;
      }
      return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
          break;
      default:
 -        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
 +                      __func__, addr);
      }
  }
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
          }
          return 0;
      default:
 -        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
 +                      __func__, addr);
          break;
      }
      return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
          }
          break;
      default:
 -        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
 +                      __func__, addr);
      }
  }
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
      case ICFOR:
          return s->rx_len;
      default:
 -        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
 +                      __func__, addr);
          break;
      }
      return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_fir_write(void *opaque, hwaddr addr,
      case ICFOR:
          break;
      default:
 -        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
 +                      __func__, addr);
      }
  }
 --
 .20.1

-[PULL 40/42] target/arm: Check supported KVM features globally (not per vCPU)
+[PULL 05/29] target/arm: Convert aes and sm4 to gvec helpers
-From: Philippe Mathieu-Daudé <philmd@redhat.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Since commit d70c996df23f, when enabling the PMU we get:
+With this conversion, we will be able to use the same helpers
+with sve.  In particular, pass 3 vector parameters for the
-  $ qemu-system-aarch64 -cpu host,pmu=on -M virt,accel=kvm,gic-version=3
+-operand operations; for advsimd the destination register
-  Segmentation fault (core dumped)
+is also an input.
-  Thread 1 "qemu-system-aar" received signal SIGSEGV, Segmentation fault.
+This also fixes a bug in which we failed to clear the high bits
-x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at accel/kvm/kvm-all.c:2588
+of the SVE register after an AdvSIMD operation.
-ret = ioctl(s->fd, type, arg);
-  (gdb) bt
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-  #0  0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at accel/kvm/kvm-all.c:2588
+Message-id: 20200514212831.31248-2-richard.henderson@linaro.org
-  #1  0x0000aaaaaae31568 in kvm_check_extension (s=0x0, extension=126) at accel/kvm/kvm-all.c:916
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
   #2  0x0000aaaaaafce254 in kvm_arm_pmu_supported (cpu=0xaaaaac214ab0) at target/arm/kvm.c:213
   #3  0x0000aaaaaafc0f94 in arm_set_pmu (obj=0xaaaaac214ab0, value=true, errp=0xffffffffe438) at target/arm/cpu.c:1111
   #4  0x0000aaaaab5533ac in property_set_bool (obj=0xaaaaac214ab0, v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", opaque=0xaaaaac222730, errp=0xffffffffe438) at qom/object.c:2170
   #5  0x0000aaaaab5512f0 in object_property_set (obj=0xaaaaac214ab0, v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at qom/object.c:1328
   #6  0x0000aaaaab551e10 in object_property_parse (obj=0xaaaaac214ab0, string=0xaaaaac11b4c0 "on", name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at qom/object.c:1561
   #7  0x0000aaaaab54ee8c in object_apply_global_props (obj=0xaaaaac214ab0, props=0xaaaaac018e20, errp=0xaaaaabd6fd88 <error_fatal>) at qom/object.c:407
   #8  0x0000aaaaab1dd5a4 in qdev_prop_set_globals (dev=0xaaaaac214ab0) at hw/core/qdev-properties.c:1218
   #9  0x0000aaaaab1d9fac in device_post_init (obj=0xaaaaac214ab0) at hw/core/qdev.c:1050
   ...
   #15 0x0000aaaaab54f310 in object_initialize_with_type (obj=0xaaaaac214ab0, size=52208, type=0xaaaaabe237f0) at qom/object.c:512
   #16 0x0000aaaaab54fa24 in object_new_with_type (type=0xaaaaabe237f0) at qom/object.c:687
   #17 0x0000aaaaab54fa80 in object_new (typename=0xaaaaabe23970 "host-arm-cpu") at qom/object.c:702
   #18 0x0000aaaaaaf04a74 in machvirt_init (machine=0xaaaaac0a8550) at hw/arm/virt.c:1770
   #19 0x0000aaaaab1e8720 in machine_run_board_init (machine=0xaaaaac0a8550) at hw/core/machine.c:1138
   #20 0x0000aaaaaaf95394 in qemu_init (argc=5, argv=0xffffffffea58, envp=0xffffffffea88) at softmmu/vl.c:4348
   #21 0x0000aaaaaada3f74 in main (argc=<optimized out>, argv=<optimized out>, envp=<optimized out>) at softmmu/main.c:48
 This is because in frame #2, cpu->kvm_state is still NULL
 (the vCPU is not yet realized).
 KVM has a hard requirement of all cores supporting the same
 feature set. We only need to check if the accelerator supports
 a feature, not each vCPU individually.
 Fix by removing the 'CPUState *cpu' argument from the
 kvm_arm_<FEATURE>_supported() functions.
 Fixes: d70c996df23f ('Use CPUState::kvm_state in kvm_arm_pmu_supported')
 Reported-by: Haibo Xu <haibo.xu@linaro.org>
 Reviewed-by: Andrew Jones <drjones@redhat.com>
 Acked-by: Paolo Bonzini <pbonzini@redhat.com>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/kvm_arm.h | 21 +++++++++------------
+ target/arm/helper.h        |  6 ++--
- target/arm/cpu.c     |  2 +-
+ target/arm/vec_internal.h  | 33 +++++++++++++++++
- target/arm/cpu64.c   | 10 +++++-----
+ target/arm/crypto_helper.c | 72 +++++++++++++++++++++++++++-----------
- target/arm/kvm.c     |  4 ++--
+ target/arm/translate-a64.c | 55 ++++++++++++++++++-----------
- target/arm/kvm64.c   | 14 +++++---------
+ target/arm/translate.c     | 27 +++++++-------
-files changed, 22 insertions(+), 29 deletions(-)
+ target/arm/vec_helper.c    | 12 +------
+files changed, 138 insertions(+), 67 deletions(-)
-diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
+ create mode 100644 target/arm/vec_internal.h
 diff --git a/target/arm/helper.h b/target/arm/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/kvm_arm.h
+--- a/target/arm/helper.h
-+++ b/target/arm/kvm_arm.h
++++ b/target/arm/helper.h
-@@ -XXX,XX +XXX,XX @@ void kvm_arm_add_vcpu_properties(Object *obj);
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(neon_qzip8, TCG_CALL_NO_RWG, void, ptr, ptr)
+ DEF_HELPER_FLAGS_2(neon_qzip16, TCG_CALL_NO_RWG, void, ptr, ptr)
- /**
+ DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr)
-  * kvm_arm_aarch32_supported:
-- * @cs: CPUState
+-DEF_HELPER_FLAGS_3(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
-  *
++DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-- * Returns: true if the KVM VCPU can enable AArch32 mode
+ DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
-+ * Returns: true if KVM can enable AArch32 mode
-  * and false otherwise.
+ DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32, i32)
  DEF_HELPER_FLAGS_3(crypto_sm3partw1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
  DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
 -DEF_HELPER_FLAGS_2(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr)
 -DEF_HELPER_FLAGS_3(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
 +DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
  DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
  DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
 diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/arm/vec_internal.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * ARM AdvSIMD / SVE Vector Helpers
 + *
 + * Copyright (c) 2020 Linaro
 + *
 + * This library is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU Lesser General Public
 + * License as published by the Free Software Foundation; either
 + * version 2 of the License, or (at your option) any later version.
 + *
 + * This library is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 + * Lesser General Public License for more details.
 + *
 + * You should have received a copy of the GNU Lesser General Public
 + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#ifndef TARGET_ARM_VEC_INTERNALS_H
 +#define TARGET_ARM_VEC_INTERNALS_H
 +
 +static inline void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
 +{
 +    uint64_t *d = vd + opr_sz;
 +    uintptr_t i;
 +
 +    for (i = opr_sz; i < max_sz; i += 8) {
 +        *d++ = 0;
 +    }
 +}
 +
 +#endif /* TARGET_ARM_VEC_INTERNALS_H */
 diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/crypto_helper.c
 +++ b/target/arm/crypto_helper.c
@@ -XXX,XX +XXX,XX @@
  #include "cpu.h"
  #include "exec/helper-proto.h"
 +#include "tcg/tcg-gvec-desc.h"
  #include "crypto/aes.h"
 +#include "vec_internal.h"
  union CRYPTO_STATE {
      uint8_t    bytes[16];
@@ -XXX,XX +XXX,XX @@ union CRYPTO_STATE {
  #define CR_ST_WORD(state, i)   (state.words[i])
  #endif
 -void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt)
 +static void do_crypto_aese(uint64_t *rd, uint64_t *rn,
 +                           uint64_t *rm, bool decrypt)
  {
      static uint8_t const * const sbox[2] = { AES_sbox, AES_isbox };
      static uint8_t const * const shift[2] = { AES_shifts, AES_ishifts };
 -    uint64_t *rd = vd;
 -    uint64_t *rm = vm;
      union CRYPTO_STATE rk = { .l = { rm[0], rm[1] } };
 -    union CRYPTO_STATE st = { .l = { rd[0], rd[1] } };
 +    union CRYPTO_STATE st = { .l = { rn[0], rn[1] } };
      int i;
 -    assert(decrypt < 2);
 -
      /* xor state vector with round key */
      rk.l[0] ^= st.l[0];
      rk.l[1] ^= st.l[1];
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt)
      rd[1] = st.l[1];
  }
 -void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)
 +void HELPER(crypto_aese)(void *vd, void *vn, void *vm, uint32_t desc)
 +{
 +    intptr_t i, opr_sz = simd_oprsz(desc);
 +    bool decrypt = simd_data(desc);
 +
 +    for (i = 0; i < opr_sz; i += 16) {
 +        do_crypto_aese(vd + i, vn + i, vm + i, decrypt);
 +    }
 +    clear_tail(vd, opr_sz, simd_maxsz(desc));
 +}
 +
 +static void do_crypto_aesmc(uint64_t *rd, uint64_t *rm, bool decrypt)
  {
      static uint32_t const mc[][256] = { {
          /* MixColumns lookup table */
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)
 xbe805d9f, 0xb58d5491, 0xa89a4f83, 0xa397468d,
      } };
 -    uint64_t *rd = vd;
 -    uint64_t *rm = vm;
      union CRYPTO_STATE st = { .l = { rm[0], rm[1] } };
      int i;
 -    assert(decrypt < 2);
 -
      for (i = 0; i < 16; i += 4) {
          CR_ST_WORD(st, i >> 2) =
              mc[decrypt][CR_ST_BYTE(st, i)] ^
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)
      rd[1] = st.l[1];
  }
 +void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t desc)
 +{
 +    intptr_t i, opr_sz = simd_oprsz(desc);
 +    bool decrypt = simd_data(desc);
 +
 +    for (i = 0; i < opr_sz; i += 16) {
 +        do_crypto_aesmc(vd + i, vm + i, decrypt);
 +    }
 +    clear_tail(vd, opr_sz, simd_maxsz(desc));
 +}
 +
  /*
   * SHA-1 logical functions
   */
--bool kvm_arm_aarch32_supported(CPUState *cs);
+@@ -XXX,XX +XXX,XX @@ static uint8_t const sm4_sbox[] = {
-+bool kvm_arm_aarch32_supported(void);
+x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
+ };
- /**
-  * kvm_arm_pmu_supported:
+-void HELPER(crypto_sm4e)(void *vd, void *vn)
-- * @cs: CPUState
++static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
   *
 - * Returns: true if the KVM VCPU can enable its PMU
 + * Returns: true if KVM can enable the PMU
   * and false otherwise.
   */
 -bool kvm_arm_pmu_supported(CPUState *cs);
 +bool kvm_arm_pmu_supported(void);
  /**
   * kvm_arm_sve_supported:
 - * @cs: CPUState
   *
 - * Returns true if the KVM VCPU can enable SVE and false otherwise.
 + * Returns true if KVM can enable SVE and false otherwise.
   */
 -bool kvm_arm_sve_supported(CPUState *cs);
 +bool kvm_arm_sve_supported(void);
  /**
   * kvm_arm_get_max_vm_ipa_size:
@@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
  static inline void kvm_arm_add_vcpu_properties(Object *obj) {}
 -static inline bool kvm_arm_aarch32_supported(CPUState *cs)
 +static inline bool kvm_arm_aarch32_supported(void)
  {
-     return false;
+-    uint64_t *rd = vd;
- }
+-    uint64_t *rn = vn;
+-    union CRYPTO_STATE d = { .l = { rd[0], rd[1] } };
--static inline bool kvm_arm_pmu_supported(CPUState *cs)
+-    union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };
-+static inline bool kvm_arm_pmu_supported(void)
++    union CRYPTO_STATE d = { .l = { rn[0], rn[1] } };
 +    union CRYPTO_STATE n = { .l = { rm[0], rm[1] } };
      uint32_t t, i;
      for (i = 0; i < 4; i++) {
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4e)(void *vd, void *vn)
      rd[1] = d.l[1];
  }
 -void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm)
 +void HELPER(crypto_sm4e)(void *vd, void *vn, void *vm, uint32_t desc)
 +{
 +    intptr_t i, opr_sz = simd_oprsz(desc);
 +
 +    for (i = 0; i < opr_sz; i += 16) {
 +        do_crypto_sm4e(vd + i, vn + i, vm + i);
 +    }
 +    clear_tail(vd, opr_sz, simd_maxsz(desc));
 +}
 +
 +static void do_crypto_sm4ekey(uint64_t *rd, uint64_t *rn, uint64_t *rm)
  {
-     return false;
+-    uint64_t *rd = vd;
- }
+-    uint64_t *rn = vn;
+-    uint64_t *rm = vm;
--static inline bool kvm_arm_sve_supported(CPUState *cs)
+     union CRYPTO_STATE d;
-+static inline bool kvm_arm_sve_supported(void)
+     union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };
- {
+     union CRYPTO_STATE m = { .l = { rm[0], rm[1] } };
-     return false;
+@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm)
- }
+     rd[0] = d.l[0];
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+     rd[1] = d.l[1];
  }
 +
 +void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm, uint32_t desc)
 +{
 +    intptr_t i, opr_sz = simd_oprsz(desc);
 +
 +    for (i = 0; i < opr_sz; i += 16) {
 +        do_crypto_sm4ekey(vd + i, vn + i, vm + i);
 +    }
 +    clear_tail(vd, opr_sz, simd_maxsz(desc));
 +}
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/target/arm/translate-a64.c
-+++ b/target/arm/cpu.c
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void arm_set_pmu(Object *obj, bool value, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void gen_gvec_fn4(DisasContext *s, bool is_q, int rd, int rn, int rm,
-     ARMCPU *cpu = ARM_CPU(obj);
+             is_q ? 16 : 8, vec_full_reg_size(s));
+ }
-     if (value) {
--        if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu))) {
++/* Expand a 2-operand operation using an out-of-line helper.  */
-+        if (kvm_enabled() && !kvm_arm_pmu_supported()) {
++static void gen_gvec_op2_ool(DisasContext *s, bool is_q, int rd,
-             error_setg(errp, "'pmu' feature not supported by KVM on this host");
++                             int rn, int data, gen_helper_gvec_2 *fn)
-             return;
++{
-         }
++    tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
++                       vec_full_reg_offset(s, rn),
-index XXXXXXX..XXXXXXX 100644
++                       is_q ? 16 : 8, vec_full_reg_size(s), data, fn);
---- a/target/arm/cpu64.c
++}
-+++ b/target/arm/cpu64.c
++
-@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
+ /* Expand a 3-operand operation using an out-of-line helper.  */
+ static void gen_gvec_op3_ool(DisasContext *s, bool is_q, int rd,
-     /* Collect the set of vector lengths supported by KVM. */
+                              int rn, int rm, int data, gen_helper_gvec_3 *fn)
-     bitmap_zero(kvm_supported, ARM_MAX_VQ);
+@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
--    if (kvm_enabled() && kvm_arm_sve_supported(CPU(cpu))) {
+     int rn = extract32(insn, 5, 5);
-+    if (kvm_enabled() && kvm_arm_sve_supported()) {
+     int rd = extract32(insn, 0, 5);
-         kvm_arm_sve_get_vls(CPU(cpu), kvm_supported);
+     int decrypt;
-     } else if (kvm_enabled()) {
+-    TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
-         assert(!cpu_isar_feature(aa64_sve, cpu));
+-    TCGv_i32 tcg_decrypt;
-@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
+-    CryptoThreeOpIntFn *genfn;
 +    gen_helper_gvec_2 *genfn2 = NULL;
 +    gen_helper_gvec_3 *genfn3 = NULL;
      if (!dc_isar_feature(aa64_aes, s) || size != 0) {
          unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
      switch (opcode) {
      case 0x4: /* AESE */
          decrypt = 0;
 -        genfn = gen_helper_crypto_aese;
 +        genfn3 = gen_helper_crypto_aese;
          break;
      case 0x6: /* AESMC */
          decrypt = 0;
 -        genfn = gen_helper_crypto_aesmc;
 +        genfn2 = gen_helper_crypto_aesmc;
          break;
      case 0x5: /* AESD */
          decrypt = 1;
 -        genfn = gen_helper_crypto_aese;
 +        genfn3 = gen_helper_crypto_aese;
          break;
      case 0x7: /* AESIMC */
          decrypt = 1;
 -        genfn = gen_helper_crypto_aesmc;
 +        genfn2 = gen_helper_crypto_aesmc;
          break;
      default:
          unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
      if (!fp_access_check(s)) {
          return;
      }
+-
--    if (kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
+-    tcg_rd_ptr = vec_full_reg_ptr(s, rd);
-+    if (kvm_enabled() && !kvm_arm_sve_supported()) {
+-    tcg_rn_ptr = vec_full_reg_ptr(s, rn);
-         error_setg(errp, "cannot set sve-max-vq");
+-    tcg_decrypt = tcg_const_i32(decrypt);
-         error_append_hint(errp, "SVE not supported by KVM on this host\n");
+-
-         return;
+-    genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_decrypt);
-@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name,
+-
 -    tcg_temp_free_ptr(tcg_rd_ptr);
 -    tcg_temp_free_ptr(tcg_rn_ptr);
 -    tcg_temp_free_i32(tcg_decrypt);
 +    if (genfn2) {
 +        gen_gvec_op2_ool(s, true, rd, rn, decrypt, genfn2);
 +    } else {
 +        gen_gvec_op3_ool(s, true, rd, rd, rn, decrypt, genfn3);
 +    }
  }
  /* Crypto three-reg SHA
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
      int rn = extract32(insn, 5, 5);
      int rd = extract32(insn, 0, 5);
      bool feature;
 -    CryptoThreeOpFn *genfn;
 +    CryptoThreeOpFn *genfn = NULL;
 +    gen_helper_gvec_3 *oolfn = NULL;
      if (o == 0) {
          switch (opcode) {
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
              break;
          case 2: /* SM4EKEY */
              feature = dc_isar_feature(aa64_sm4, s);
 -            genfn = gen_helper_crypto_sm4ekey;
 +            oolfn = gen_helper_crypto_sm4ekey;
              break;
          default:
              unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
          return;
      }
--    if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
++    if (oolfn) {
-+    if (value && kvm_enabled() && !kvm_arm_sve_supported()) {
++        gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn);
-         error_setg(errp, "cannot enable %s", name);
++        return;
-         error_append_hint(errp, "SVE not supported by KVM on this host\n");
++    }
-         return;
++
-@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
+     if (genfn) {
          TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
      TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
      bool feature;
      CryptoTwoOpFn *genfn;
 +    gen_helper_gvec_3 *oolfn = NULL;
      switch (opcode) {
      case 0: /* SHA512SU0 */
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
          break;
      case 1: /* SM4E */
          feature = dc_isar_feature(aa64_sm4, s);
 -        genfn = gen_helper_crypto_sm4e;
 +        oolfn = gen_helper_crypto_sm4e;
          break;
      default:
          unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
          return;
      }
--    if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
++    if (oolfn) {
-+    if (value && kvm_enabled() && !kvm_arm_sve_supported()) {
++        gen_gvec_op3_ool(s, true, rd, rd, rn, 0, oolfn);
-         error_setg(errp, "'sve' feature not supported by KVM on this host");
++        return;
-         return;
++    }
-     }
++
-@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
+     tcg_rd_ptr = vec_full_reg_ptr(s, rd);
-      * uniform execution state like do_interrupt.
+     tcg_rn_ptr = vec_full_reg_ptr(s, rn);
-      */
-     if (value == false) {
+diff --git a/target/arm/translate.c b/target/arm/translate.c
 -        if (!kvm_enabled() || !kvm_arm_aarch32_supported(CPU(cpu))) {
 +        if (!kvm_enabled() || !kvm_arm_aarch32_supported()) {
              error_setg(errp, "'aarch64' feature cannot be disabled "
                               "unless KVM is enabled and 32-bit EL1 "
                               "is supported");
 diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/kvm.c
+--- a/target/arm/translate.c
-+++ b/target/arm/kvm.c
++++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ void kvm_arm_add_vcpu_properties(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-     }
+                     if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) {
- }
+                         return 1;
+                     }
--bool kvm_arm_pmu_supported(CPUState *cpu)
+-                    ptr1 = vfp_reg_ptr(true, rd);
-+bool kvm_arm_pmu_supported(void)
+-                    ptr2 = vfp_reg_ptr(true, rm);
- {
+-
--    return kvm_check_extension(cpu->kvm_state, KVM_CAP_ARM_PMU_V3);
+-                     /* Bit 6 is the lowest opcode bit; it distinguishes between
-+    return kvm_check_extension(kvm_state, KVM_CAP_ARM_PMU_V3);
+-                      * encryption (AESE/AESMC) and decryption (AESD/AESIMC)
- }
+-                      */
+-                    tmp3 = tcg_const_i32(extract32(insn, 6, 1));
- int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
+-
-diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
++                    /*
 +                     * Bit 6 is the lowest opcode bit; it distinguishes
 +                     * between encryption (AESE/AESMC) and decryption
 +                     * (AESD/AESIMC).
 +                     */
                      if (op == NEON_2RM_AESE) {
 -                        gen_helper_crypto_aese(ptr1, ptr2, tmp3);
 +                        tcg_gen_gvec_3_ool(vfp_reg_offset(true, rd),
 +                                           vfp_reg_offset(true, rd),
 +                                           vfp_reg_offset(true, rm),
 +                                           16, 16, extract32(insn, 6, 1),
 +                                           gen_helper_crypto_aese);
                      } else {
 -                        gen_helper_crypto_aesmc(ptr1, ptr2, tmp3);
 +                        tcg_gen_gvec_2_ool(vfp_reg_offset(true, rd),
 +                                           vfp_reg_offset(true, rm),
 +                                           16, 16, extract32(insn, 6, 1),
 +                                           gen_helper_crypto_aesmc);
                      }
 -                    tcg_temp_free_ptr(ptr1);
 -                    tcg_temp_free_ptr(ptr2);
 -                    tcg_temp_free_i32(tmp3);
                      break;
                  case NEON_2RM_SHA1H:
                      if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) {
 diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/kvm64.c
+--- a/target/arm/vec_helper.c
-+++ b/target/arm/kvm64.c
++++ b/target/arm/vec_helper.c
-@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
+@@ -XXX,XX +XXX,XX @@
-     return true;
+ #include "exec/helper-proto.h"
- }
+ #include "tcg/tcg-gvec-desc.h"
+ #include "fpu/softfloat.h"
--bool kvm_arm_aarch32_supported(CPUState *cpu)
+-
-+bool kvm_arm_aarch32_supported(void)
++#include "vec_internal.h"
- {
--    KVMState *s = KVM_STATE(current_accel());
+ /* Note that vector data is stored in host-endian 64-bit chunks,
--
+    so addressing units smaller than that needs a host-endian fixup.  */
--    return kvm_check_extension(s, KVM_CAP_ARM_EL1_32BIT);
+@@ -XXX,XX +XXX,XX @@
-+    return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT);
+ #define H4(x)  (x)
- }
+ #endif
--bool kvm_arm_sve_supported(CPUState *cpu)
+-static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
-+bool kvm_arm_sve_supported(void)
+-{
- {
+-    uint64_t *d = vd + opr_sz;
--    KVMState *s = KVM_STATE(current_accel());
+-    uintptr_t i;
 -
--    return kvm_check_extension(s, KVM_CAP_ARM_SVE);
+-    for (i = opr_sz; i < max_sz; i += 8) {
-+    return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE);
+-        *d++ = 0;
- }
+-    }
+-}
- QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1);
+-
-@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
+ /* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
-         env->features &= ~(1ULL << ARM_FEATURE_PMU);
+ static int16_t inl_qrdmlah_s16(int16_t src1, int16_t src2,
-     }
+                                int16_t src3, uint32_t *sat)
      if (cpu_isar_feature(aa64_sve, cpu)) {
 -        assert(kvm_arm_sve_supported(cs));
 +        assert(kvm_arm_sve_supported());
          cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE;
      }
 --
 .20.1

-[PULL 12/42] target/arm: Fix capitalization in NeonGenTwo{Single, Double}OPFn typedefs
+[PULL 06/29] target/arm: Convert rax1 to gvec helpers
-All the other typedefs like these spell "Op" with a lowercase 'p';
+From: Richard Henderson <richard.henderson@linaro.org>
 remane the NeonGenTwoSingleOPFn and NeonGenTwoDoubleOPFn typedefs to
 match.
+With this conversion, we will be able to use the same helpers
+with sve.  This also fixes a bug in which we failed to clear
+the high bits of the SVE register after an AdvSIMD operation.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20200514212831.31248-3-richard.henderson@linaro.org
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-11-peter.maydell@linaro.org
 ---
- target/arm/translate.h          | 4 ++--
+ target/arm/helper.h        |  2 ++
- target/arm/translate-a64.c      | 4 ++--
+ target/arm/translate-a64.h |  3 ++
- target/arm/translate-neon.inc.c | 2 +-
+ target/arm/crypto_helper.c | 11 +++++++
-files changed, 5 insertions(+), 5 deletions(-)
+ target/arm/translate-a64.c | 59 ++++++++++++++++++++------------------
 files changed, 47 insertions(+), 28 deletions(-)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
+diff --git a/target/arm/helper.h b/target/arm/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
+--- a/target/arm/helper.h
-+++ b/target/arm/translate.h
++++ b/target/arm/helper.h
-@@ -XXX,XX +XXX,XX @@ typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
- typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
+ DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
- typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
+ DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
- typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
--typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
++DEF_HELPER_FLAGS_4(crypto_rax1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
--typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
++
-+typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
+ DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
-+typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
+ DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
- typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
- typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
+diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
- typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
+index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.h
 +++ b/target/arm/translate-a64.h
@@ -XXX,XX +XXX,XX @@ static inline int vec_full_reg_size(DisasContext *s)
  bool disas_sve(DisasContext *, uint32_t);
 +void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 +                   uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 +
  #endif /* TARGET_ARM_TRANSLATE_A64_H */
 diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/crypto_helper.c
 +++ b/target/arm/crypto_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm, uint32_t desc)
      }
      clear_tail(vd, opr_sz, simd_maxsz(desc));
  }
 +
 +void HELPER(crypto_rax1)(void *vd, void *vn, void *vm, uint32_t desc)
 +{
 +    intptr_t i, opr_sz = simd_oprsz(desc);
 +    uint64_t *d = vd, *n = vn, *m = vm;
 +
 +    for (i = 0; i < opr_sz / 8; ++i) {
 +        d[i] = n[i] ^ rol64(m[i], 1);
 +    }
 +    clear_tail(vd, opr_sz, simd_maxsz(desc));
 +}
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
+@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
-         TCGv_i64 tcg_op = tcg_temp_new_i64();
+     tcg_temp_free_ptr(tcg_rn_ptr);
          TCGv_i64 tcg_zero = tcg_const_i64(0);
          TCGv_i64 tcg_res = tcg_temp_new_i64();
 -        NeonGenTwoDoubleOPFn *genfn;
 +        NeonGenTwoDoubleOpFn *genfn;
          bool swap = false;
          int pass;
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
          TCGv_i32 tcg_op = tcg_temp_new_i32();
          TCGv_i32 tcg_zero = tcg_const_i32(0);
          TCGv_i32 tcg_res = tcg_temp_new_i32();
 -        NeonGenTwoSingleOPFn *genfn;
 +        NeonGenTwoSingleOpFn *genfn;
          bool swap = false;
          int pass, maxpasses;
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.inc.c
 +++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a)
  }
- static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
++static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
--                      NeonGenTwoSingleOPFn *fn)
++{
-+                      NeonGenTwoSingleOpFn *fn)
++    tcg_gen_rotli_i64(d, m, 1);
- {
++    tcg_gen_xor_i64(d, d, n);
-     /* FP operations in 2-reg-and-shift group */
++}
-     TCGv_i32 tmp, shiftv;
++
 +static void gen_rax1_vec(unsigned vece, TCGv_vec d, TCGv_vec n, TCGv_vec m)
 +{
 +    tcg_gen_rotli_vec(vece, d, m, 1);
 +    tcg_gen_xor_vec(vece, d, d, n);
 +}
 +
 +void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 +                   uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz)
 +{
 +    static const TCGOpcode vecop_list[] = { INDEX_op_rotli_vec, 0 };
 +    static const GVecGen3 op = {
 +        .fni8 = gen_rax1_i64,
 +        .fniv = gen_rax1_vec,
 +        .opt_opc = vecop_list,
 +        .fno = gen_helper_crypto_rax1,
 +        .vece = MO_64,
 +    };
 +    tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &op);
 +}
 +
  /* Crypto three-reg SHA512
   *  31                   21 20  16 15  14  13 12  11  10  9    5 4    0
   * +-----------------------+------+---+---+-----+--------+------+------+
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
      bool feature;
      CryptoThreeOpFn *genfn = NULL;
      gen_helper_gvec_3 *oolfn = NULL;
 +    GVecGen3Fn *gvecfn = NULL;
      if (o == 0) {
          switch (opcode) {
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
              break;
          case 3: /* RAX1 */
              feature = dc_isar_feature(aa64_sha3, s);
 -            genfn = NULL;
 +            gvecfn = gen_gvec_rax1;
              break;
          default:
              g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
      if (oolfn) {
          gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn);
 -        return;
 -    }
 -
 -    if (genfn) {
 +    } else if (gvecfn) {
 +        gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64);
 +    } else {
          TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
          tcg_rd_ptr = vec_full_reg_ptr(s, rd);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
          tcg_temp_free_ptr(tcg_rd_ptr);
          tcg_temp_free_ptr(tcg_rn_ptr);
          tcg_temp_free_ptr(tcg_rm_ptr);
 -    } else {
 -        TCGv_i64 tcg_op1, tcg_op2, tcg_res[2];
 -        int pass;
 -
 -        tcg_op1 = tcg_temp_new_i64();
 -        tcg_op2 = tcg_temp_new_i64();
 -        tcg_res[0] = tcg_temp_new_i64();
 -        tcg_res[1] = tcg_temp_new_i64();
 -
 -        for (pass = 0; pass < 2; pass++) {
 -            read_vec_element(s, tcg_op1, rn, pass, MO_64);
 -            read_vec_element(s, tcg_op2, rm, pass, MO_64);
 -
 -            tcg_gen_rotli_i64(tcg_res[pass], tcg_op2, 1);
 -            tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
 -        }
 -        write_vec_element(s, tcg_res[0], rd, 0, MO_64);
 -        write_vec_element(s, tcg_res[1], rd, 1, MO_64);
 -
 -        tcg_temp_free_i64(tcg_op1);
 -        tcg_temp_free_i64(tcg_op2);
 -        tcg_temp_free_i64(tcg_res[0]);
 -        tcg_temp_free_i64(tcg_res[1]);
      }
  }
 --
 .20.1

-[PULL 27/42] hw/i2c/versatile_i2c: Add definitions for register addresses
+[PULL 07/29] target/arm: Convert sha512 and sm3 to gvec helpers
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Richard Henderson <richard.henderson@linaro.org>
-Use self-explicit definitions instead of magic values.
+Do not yet convert the helpers to loop over opr_sz, but the
+descriptor allows the vector tail to be cleared.  Which fixes
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+an existing bug vs SVE.
-Message-id: 20200617072539.32686-3-f4bug@amsat.org
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20200514212831.31248-4-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/i2c/versatile_i2c.c | 14 ++++++++++----
+ target/arm/helper.h        | 15 +++++++-----
-file changed, 10 insertions(+), 4 deletions(-)
+ target/arm/crypto_helper.c | 37 +++++++++++++++++++++++-----
+ target/arm/translate-a64.c | 50 ++++++++++++--------------------------
-diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
+files changed, 55 insertions(+), 47 deletions(-)
 diff --git a/target/arm/helper.h b/target/arm/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/i2c/versatile_i2c.c
+--- a/target/arm/helper.h
-+++ b/hw/i2c/versatile_i2c.c
++++ b/target/arm/helper.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
- #include "qemu/osdep.h"
+ DEF_HELPER_FLAGS_2(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr)
- #include "hw/sysbus.h"
+ DEF_HELPER_FLAGS_3(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
- #include "hw/i2c/bitbang_i2c.h"
-+#include "hw/registerfields.h"
+-DEF_HELPER_FLAGS_3(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
- #include "qemu/log.h"
+-DEF_HELPER_FLAGS_3(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
- #include "qemu/module.h"
+-DEF_HELPER_FLAGS_2(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr)
+-DEF_HELPER_FLAGS_3(crypto_sha512su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
-@@ -XXX,XX +XXX,XX @@ typedef struct VersatileI2CState {
++DEF_HELPER_FLAGS_4(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-     int in;
++DEF_HELPER_FLAGS_4(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
- } VersatileI2CState;
++DEF_HELPER_FLAGS_3(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
++DEF_HELPER_FLAGS_4(crypto_sha512su1, TCG_CALL_NO_RWG,
-+REG32(CONTROL_GET, 0)
++                   void, ptr, ptr, ptr, i32)
-+REG32(CONTROL_SET, 0)
-+REG32(CONTROL_CLR, 4)
+ DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32, i32)
-+
+-DEF_HELPER_FLAGS_3(crypto_sm3partw1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
- static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
+-DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
-                                    unsigned size)
++DEF_HELPER_FLAGS_4(crypto_sm3partw1, TCG_CALL_NO_RWG,
- {
++                   void, ptr, ptr, ptr, i32)
-     VersatileI2CState *s = (VersatileI2CState *)opaque;
++DEF_HELPER_FLAGS_4(crypto_sm3partw2, TCG_CALL_NO_RWG,
++                   void, ptr, ptr, ptr, i32)
--    if (offset == 0) {
-+    switch (offset) {
+ DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-+    case A_CONTROL_SET:
+ DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-         return (s->out & 1) | (s->in << 1);
+diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
--    } else {
+index XXXXXXX..XXXXXXX 100644
-+    default:
+--- a/target/arm/crypto_helper.c
-         qemu_log_mask(LOG_GUEST_ERROR,
++++ b/target/arm/crypto_helper.c
-                       "%s: Bad offset 0x%x\n", __func__, (int)offset);
+@@ -XXX,XX +XXX,XX @@ union CRYPTO_STATE {
-         return -1;
+ #define CR_ST_WORD(state, i)   (state.words[i])
-@@ -XXX,XX +XXX,XX @@ static void versatile_i2c_write(void *opaque, hwaddr offset,
+ #endif
-     VersatileI2CState *s = (VersatileI2CState *)opaque;
++/*
-     switch (offset) {
++ * The caller has not been converted to full gvec, and so only
--    case 0:
++ * modifies the low 16 bytes of the vector register.
-+    case A_CONTROL_SET:
++ */
-         s->out |= value & 3;
++static void clear_tail_16(void *vd, uint32_t desc)
 +{
 +    int opr_sz = simd_oprsz(desc);
 +    int max_sz = simd_maxsz(desc);
 +
 +    assert(opr_sz == 16);
 +    clear_tail(vd, opr_sz, max_sz);
 +}
 +
  static void do_crypto_aese(uint64_t *rd, uint64_t *rn,
                             uint64_t *rm, bool decrypt)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t s1_512(uint64_t x)
      return ror64(x, 19) ^ ror64(x, 61) ^ (x >> 6);
  }
 -void HELPER(crypto_sha512h)(void *vd, void *vn, void *vm)
 +void HELPER(crypto_sha512h)(void *vd, void *vn, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512h)(void *vd, void *vn, void *vm)
      rd[0] = d0;
      rd[1] = d1;
 +
 +    clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sha512h2)(void *vd, void *vn, void *vm)
 +void HELPER(crypto_sha512h2)(void *vd, void *vn, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512h2)(void *vd, void *vn, void *vm)
      rd[0] = d0;
      rd[1] = d1;
 +
 +    clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sha512su0)(void *vd, void *vn)
 +void HELPER(crypto_sha512su0)(void *vd, void *vn, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512su0)(void *vd, void *vn)
      rd[0] = d0;
      rd[1] = d1;
 +
 +    clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sha512su1)(void *vd, void *vn, void *vm)
 +void HELPER(crypto_sha512su1)(void *vd, void *vn, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512su1)(void *vd, void *vn, void *vm)
      rd[0] += s1_512(rn[0]) + rm[0];
      rd[1] += s1_512(rn[1]) + rm[1];
 +
 +    clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sm3partw1)(void *vd, void *vn, void *vm)
 +void HELPER(crypto_sm3partw1)(void *vd, void *vn, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3partw1)(void *vd, void *vn, void *vm)
      rd[0] = d.l[0];
      rd[1] = d.l[1];
 +
 +    clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm)
 +void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm)
      rd[0] = d.l[0];
      rd[1] = d.l[1];
 +
 +    clear_tail_16(vd, desc);
  }
  void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2,
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
      int rn = extract32(insn, 5, 5);
      int rd = extract32(insn, 0, 5);
      bool feature;
 -    CryptoThreeOpFn *genfn = NULL;
      gen_helper_gvec_3 *oolfn = NULL;
      GVecGen3Fn *gvecfn = NULL;
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
          switch (opcode) {
          case 0: /* SHA512H */
              feature = dc_isar_feature(aa64_sha512, s);
 -            genfn = gen_helper_crypto_sha512h;
 +            oolfn = gen_helper_crypto_sha512h;
              break;
          case 1: /* SHA512H2 */
              feature = dc_isar_feature(aa64_sha512, s);
 -            genfn = gen_helper_crypto_sha512h2;
 +            oolfn = gen_helper_crypto_sha512h2;
              break;
          case 2: /* SHA512SU1 */
              feature = dc_isar_feature(aa64_sha512, s);
 -            genfn = gen_helper_crypto_sha512su1;
 +            oolfn = gen_helper_crypto_sha512su1;
              break;
          case 3: /* RAX1 */
              feature = dc_isar_feature(aa64_sha3, s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
          switch (opcode) {
          case 0: /* SM3PARTW1 */
              feature = dc_isar_feature(aa64_sm3, s);
 -            genfn = gen_helper_crypto_sm3partw1;
 +            oolfn = gen_helper_crypto_sm3partw1;
              break;
          case 1: /* SM3PARTW2 */
              feature = dc_isar_feature(aa64_sm3, s);
 -            genfn = gen_helper_crypto_sm3partw2;
 +            oolfn = gen_helper_crypto_sm3partw2;
              break;
          case 2: /* SM4EKEY */
              feature = dc_isar_feature(aa64_sm4, s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
      if (oolfn) {
          gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn);
 -    } else if (gvecfn) {
 -        gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64);
      } else {
 -        TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
 -
 -        tcg_rd_ptr = vec_full_reg_ptr(s, rd);
 -        tcg_rn_ptr = vec_full_reg_ptr(s, rn);
 -        tcg_rm_ptr = vec_full_reg_ptr(s, rm);
 -
 -        genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr);
 -
 -        tcg_temp_free_ptr(tcg_rd_ptr);
 -        tcg_temp_free_ptr(tcg_rn_ptr);
 -        tcg_temp_free_ptr(tcg_rm_ptr);
 +        gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64);
      }
  }
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
      int opcode = extract32(insn, 10, 2);
      int rn = extract32(insn, 5, 5);
      int rd = extract32(insn, 0, 5);
 -    TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
      bool feature;
 -    CryptoTwoOpFn *genfn;
 -    gen_helper_gvec_3 *oolfn = NULL;
      switch (opcode) {
      case 0: /* SHA512SU0 */
          feature = dc_isar_feature(aa64_sha512, s);
 -        genfn = gen_helper_crypto_sha512su0;
          break;
--    case 4:
+     case 1: /* SM4E */
-+    case A_CONTROL_CLR:
+         feature = dc_isar_feature(aa64_sm4, s);
-         s->out &= ~value;
+-        oolfn = gen_helper_crypto_sm4e;
          break;
      default:
+         unallocated_encoding(s);
+@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
+         return;
+     }
+-    if (oolfn) {
+-        gen_gvec_op3_ool(s, true, rd, rd, rn, 0, oolfn);
+-        return;
++    switch (opcode) {
++    case 0: /* SHA512SU0 */
++        gen_gvec_op2_ool(s, true, rd, rn, 0, gen_helper_crypto_sha512su0);
++        break;
++    case 1: /* SM4E */
++        gen_gvec_op3_ool(s, true, rd, rd, rn, 0, gen_helper_crypto_sm4e);
++        break;
++    default:
++        g_assert_not_reached();
+     }
+-
+-    tcg_rd_ptr = vec_full_reg_ptr(s, rd);
+-    tcg_rn_ptr = vec_full_reg_ptr(s, rn);
+-
+-    genfn(tcg_rd_ptr, tcg_rn_ptr);
+-
+-    tcg_temp_free_ptr(tcg_rd_ptr);
+-    tcg_temp_free_ptr(tcg_rn_ptr);
+ }
+ /* Crypto four-register
 --
 .20.1

-[PULL 21/42] target/arm: Convert Neon VSWP to decodetree
+[PULL 08/29] target/arm: Convert sha1 and sha256 to gvec helpers
-Convert the Neon VSWP insn to decodetree. Since the new implementation
+From: Richard Henderson <richard.henderson@linaro.org>
 doesn't have to share a pass-loop with the other 2-reg-misc operations
 we can implement the swap with 64-bit accesses rather than 32-bits
 (which brings us into line with the pseudocode and is more efficient).
+Do not yet convert the helpers to loop over opr_sz, but the
+descriptor allows the vector tail to be cleared.  Which fixes
+an existing bug vs SVE.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20200514212831.31248-5-richard.henderson@linaro.org
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-20-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       |  2 ++
+ target/arm/helper.h             |  12 ++--
- target/arm/translate-neon.inc.c | 41 +++++++++++++++++++++++++++++++++
+ target/arm/neon-dp.decode       |  12 ++--
- target/arm/translate.c          |  5 +---
+ target/arm/crypto_helper.c      |  24 +++++--
-files changed, 44 insertions(+), 4 deletions(-)
+ target/arm/translate-a64.c      |  34 ++++-----
  target/arm/translate-neon.inc.c | 124 +++++---------------------------
  target/arm/translate.c          |  24 ++-----
 files changed, 67 insertions(+), 163 deletions(-)
+diff --git a/target/arm/helper.h b/target/arm/helper.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.h
++++ b/target/arm/helper.h
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+ DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+ DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+-DEF_HELPER_FLAGS_2(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr)
+-DEF_HELPER_FLAGS_2(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr)
++DEF_HELPER_FLAGS_3(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
++DEF_HELPER_FLAGS_3(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+-DEF_HELPER_FLAGS_3(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
+-DEF_HELPER_FLAGS_3(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
+-DEF_HELPER_FLAGS_2(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr)
+-DEF_HELPER_FLAGS_3(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
++DEF_HELPER_FLAGS_4(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
++DEF_HELPER_FLAGS_4(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
++DEF_HELPER_FLAGS_3(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
++DEF_HELPER_FLAGS_4(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+ DEF_HELPER_FLAGS_4(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+ DEF_HELPER_FLAGS_4(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/neon-dp.decode
 +++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
+@@ -XXX,XX +XXX,XX @@ VPADD_3s         1111 001 0 0 . .. .... .... 1011 . . . 1 .... @3same_q0
-     VABS_F       1111 001 11 . 11 .. 01 .... 0 1110 . . 0 .... @2misc
-     VNEG_F       1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc
+ VQRDMLAH_3s      1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
-+    VSWP         1111 001 11 . 11 .. 10 .... 0 0000 . . 0 .... @2misc
++@3same_crypto    .... .... .... .... .... .... .... .... \
-+
++                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 q=1
-     VUZP         1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc
++
-     VZIP         1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc
+ SHA1_3s          1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \
+                  vm=%vm_dp vn=%vn_dp vd=%vd_dp
 -SHA256H_3s       1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... \
 -                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
 -SHA256H2_3s      1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... \
 -                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
 -SHA256SU1_3s     1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... \
 -                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
 +SHA256H_3s       1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
 +SHA256H2_3s      1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
 +SHA256SU1_3s     1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
  VFMA_fp_3s       1111 001 0 0 . 0 . .... .... 1100 ... 1 .... @3same_fp
  VFMS_fp_3s       1111 001 0 0 . 1 . .... .... 1100 ... 1 .... @3same_fp
 diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/crypto_helper.c
 +++ b/target/arm/crypto_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha1_3reg)(void *vd, void *vn, void *vm, uint32_t op)
      rd[1] = d.l[1];
  }
 -void HELPER(crypto_sha1h)(void *vd, void *vm)
 +void HELPER(crypto_sha1h)(void *vd, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rm = vm;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha1h)(void *vd, void *vm)
      rd[0] = m.l[0];
      rd[1] = m.l[1];
 +
 +    clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sha1su1)(void *vd, void *vm)
 +void HELPER(crypto_sha1su1)(void *vd, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rm = vm;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha1su1)(void *vd, void *vm)
      rd[0] = d.l[0];
      rd[1] = d.l[1];
 +
 +    clear_tail_16(vd, desc);
  }
  /*
@@ -XXX,XX +XXX,XX @@ static uint32_t s1(uint32_t x)
      return ror32(x, 17) ^ ror32(x, 19) ^ (x >> 10);
  }
 -void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm)
 +void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm)
      rd[0] = d.l[0];
      rd[1] = d.l[1];
 +
 +    clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm)
 +void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm)
      rd[0] = d.l[0];
      rd[1] = d.l[1];
 +
 +    clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sha256su0)(void *vd, void *vm)
 +void HELPER(crypto_sha256su0)(void *vd, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rm = vm;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256su0)(void *vd, void *vm)
      rd[0] = d.l[0];
      rd[1] = d.l[1];
 +
 +    clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm)
 +void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm)
      rd[0] = d.l[0];
      rd[1] = d.l[1];
 +
 +    clear_tail_16(vd, desc);
  }
  /*
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
      int rm = extract32(insn, 16, 5);
      int rn = extract32(insn, 5, 5);
      int rd = extract32(insn, 0, 5);
 -    CryptoThreeOpFn *genfn;
 -    TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
 +    gen_helper_gvec_3 *genfn;
      bool feature;
      if (size != 0) {
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
          return;
      }
 -    tcg_rd_ptr = vec_full_reg_ptr(s, rd);
 -    tcg_rn_ptr = vec_full_reg_ptr(s, rn);
 -    tcg_rm_ptr = vec_full_reg_ptr(s, rm);
 -
      if (genfn) {
 -        genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr);
 +        gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn);
      } else {
          TCGv_i32 tcg_opcode = tcg_const_i32(opcode);
 +        TCGv_ptr tcg_rd_ptr = vec_full_reg_ptr(s, rd);
 +        TCGv_ptr tcg_rn_ptr = vec_full_reg_ptr(s, rn);
 +        TCGv_ptr tcg_rm_ptr = vec_full_reg_ptr(s, rm);
          gen_helper_crypto_sha1_3reg(tcg_rd_ptr, tcg_rn_ptr,
                                      tcg_rm_ptr, tcg_opcode);
 -        tcg_temp_free_i32(tcg_opcode);
 -    }
 -    tcg_temp_free_ptr(tcg_rd_ptr);
 -    tcg_temp_free_ptr(tcg_rn_ptr);
 -    tcg_temp_free_ptr(tcg_rm_ptr);
 +        tcg_temp_free_i32(tcg_opcode);
 +        tcg_temp_free_ptr(tcg_rd_ptr);
 +        tcg_temp_free_ptr(tcg_rn_ptr);
 +        tcg_temp_free_ptr(tcg_rm_ptr);
 +    }
  }
  /* Crypto two-reg SHA
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
      int opcode = extract32(insn, 12, 5);
      int rn = extract32(insn, 5, 5);
      int rd = extract32(insn, 0, 5);
 -    CryptoTwoOpFn *genfn;
 +    gen_helper_gvec_2 *genfn;
      bool feature;
 -    TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
      if (size != 0) {
          unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
      if (!fp_access_check(s)) {
          return;
      }
 -
 -    tcg_rd_ptr = vec_full_reg_ptr(s, rd);
 -    tcg_rn_ptr = vec_full_reg_ptr(s, rn);
 -
 -    genfn(tcg_rd_ptr, tcg_rn_ptr);
 -
 -    tcg_temp_free_ptr(tcg_rd_ptr);
 -    tcg_temp_free_ptr(tcg_rn_ptr);
 +    gen_gvec_op2_ool(s, true, rd, rn, 0, genfn);
  }
  static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.inc.c
 +++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ DO_VCVT(VCVTPU, FPROUNDING_POSINF, false)
+@@ -XXX,XX +XXX,XX @@ DO_3SAME_CMP(VCGE_S, TCG_COND_GE)
- DO_VCVT(VCVTPS, FPROUNDING_POSINF, true)
+ DO_3SAME_CMP(VCGE_U, TCG_COND_GEU)
- DO_VCVT(VCVTMU, FPROUNDING_NEGINF, false)
+ DO_3SAME_CMP(VCEQ, TCG_COND_EQ)
- DO_VCVT(VCVTMS, FPROUNDING_NEGINF, true)
-+
+-static void gen_VMUL_p_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
-+static bool trans_VSWP(DisasContext *s, arg_2misc *a)
+-                           uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)
-+{
+-{
-+    TCGv_i64 rm, rd;
+-    tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz,
-+    int pass;
+-                       0, gen_helper_gvec_pmul_b);
-+
+-}
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
++#define WRAP_OOL_FN(WRAPNAME, FUNC)                                        \
-+        return false;
++    static void WRAPNAME(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,  \
 +                         uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)  \
 +    {                                                                      \
 +        tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, 0, FUNC); \
 +    }
 +
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
++WRAP_OOL_FN(gen_VMUL_p_3s, gen_helper_gvec_pmul_b)
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        ((a->vd | a->vm) & 0x10)) {
+ static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
-+        return false;
+ {
-+    }
+@@ -XXX,XX +XXX,XX @@ static bool trans_SHA1_3s(DisasContext *s, arg_SHA1_3s *a)
-+
+     return true;
-+    if (a->size != 0) {
+ }
-+        return false;
-+    }
+-static bool trans_SHA256H_3s(DisasContext *s, arg_SHA256H_3s *a)
-+
+-{
-+    if ((a->vd | a->vm) & a->q) {
+-    TCGv_ptr ptr1, ptr2, ptr3;
-+        return false;
+-
-+    }
+-    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
-+
+-        !dc_isar_feature(aa32_sha2, s)) {
-+    if (!vfp_access_check(s)) {
+-        return false;
-+        return true;
++#define DO_SHA2(NAME, FUNC)                                             \
-+    }
++    WRAP_OOL_FN(gen_##NAME##_3s, FUNC)                                  \
-+
++    static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a)        \
-+    rm = tcg_temp_new_i64();
++    {                                                                   \
-+    rd = tcg_temp_new_i64();
++        if (!dc_isar_feature(aa32_sha2, s)) {                           \
-+    for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
++            return false;                                               \
-+        neon_load_reg64(rm, a->vm + pass);
++        }                                                               \
-+        neon_load_reg64(rd, a->vd + pass);
++        return do_3same(s, a, gen_##NAME##_3s);                         \
-+        neon_store_reg64(rm, a->vd + pass);
+     }
-+        neon_store_reg64(rd, a->vm + pass);
-+    }
+-    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    tcg_temp_free_i64(rm);
+-    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+    tcg_temp_free_i64(rd);
+-        ((a->vd | a->vn | a->vm) & 0x10)) {
-+
+-        return false;
-+    return true;
+-    }
-+}
+-
 -    if ((a->vn | a->vm | a->vd) & 1) {
 -        return false;
 -    }
 -
 -    if (!vfp_access_check(s)) {
 -        return true;
 -    }
 -
 -    ptr1 = vfp_reg_ptr(true, a->vd);
 -    ptr2 = vfp_reg_ptr(true, a->vn);
 -    ptr3 = vfp_reg_ptr(true, a->vm);
 -    gen_helper_crypto_sha256h(ptr1, ptr2, ptr3);
 -    tcg_temp_free_ptr(ptr1);
 -    tcg_temp_free_ptr(ptr2);
 -    tcg_temp_free_ptr(ptr3);
 -
 -    return true;
 -}
 -
 -static bool trans_SHA256H2_3s(DisasContext *s, arg_SHA256H2_3s *a)
 -{
 -    TCGv_ptr ptr1, ptr2, ptr3;
 -
 -    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
 -        !dc_isar_feature(aa32_sha2, s)) {
 -        return false;
 -    }
 -
 -    /* UNDEF accesses to D16-D31 if they don't exist. */
 -    if (!dc_isar_feature(aa32_simd_r32, s) &&
 -        ((a->vd | a->vn | a->vm) & 0x10)) {
 -        return false;
 -    }
 -
 -    if ((a->vn | a->vm | a->vd) & 1) {
 -        return false;
 -    }
 -
 -    if (!vfp_access_check(s)) {
 -        return true;
 -    }
 -
 -    ptr1 = vfp_reg_ptr(true, a->vd);
 -    ptr2 = vfp_reg_ptr(true, a->vn);
 -    ptr3 = vfp_reg_ptr(true, a->vm);
 -    gen_helper_crypto_sha256h2(ptr1, ptr2, ptr3);
 -    tcg_temp_free_ptr(ptr1);
 -    tcg_temp_free_ptr(ptr2);
 -    tcg_temp_free_ptr(ptr3);
 -
 -    return true;
 -}
 -
 -static bool trans_SHA256SU1_3s(DisasContext *s, arg_SHA256SU1_3s *a)
 -{
 -    TCGv_ptr ptr1, ptr2, ptr3;
 -
 -    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
 -        !dc_isar_feature(aa32_sha2, s)) {
 -        return false;
 -    }
 -
 -    /* UNDEF accesses to D16-D31 if they don't exist. */
 -    if (!dc_isar_feature(aa32_simd_r32, s) &&
 -        ((a->vd | a->vn | a->vm) & 0x10)) {
 -        return false;
 -    }
 -
 -    if ((a->vn | a->vm | a->vd) & 1) {
 -        return false;
 -    }
 -
 -    if (!vfp_access_check(s)) {
 -        return true;
 -    }
 -
 -    ptr1 = vfp_reg_ptr(true, a->vd);
 -    ptr2 = vfp_reg_ptr(true, a->vn);
 -    ptr3 = vfp_reg_ptr(true, a->vm);
 -    gen_helper_crypto_sha256su1(ptr1, ptr2, ptr3);
 -    tcg_temp_free_ptr(ptr1);
 -    tcg_temp_free_ptr(ptr2);
 -    tcg_temp_free_ptr(ptr3);
 -
 -    return true;
 -}
 +DO_SHA2(SHA256H, gen_helper_crypto_sha256h)
 +DO_SHA2(SHA256H2, gen_helper_crypto_sha256h2)
 +DO_SHA2(SHA256SU1, gen_helper_crypto_sha256su1)
  #define DO_3SAME_64(INSN, FUNC)                                         \
      static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
 @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                 case NEON_2RM_VCVTPS:
+     int vec_size;
-                 case NEON_2RM_VCVTMU:
+     uint32_t imm;
-                 case NEON_2RM_VCVTMS:
+     TCGv_i32 tmp, tmp2, tmp3, tmp4, tmp5;
-+                case NEON_2RM_VSWP:
+-    TCGv_ptr ptr1, ptr2;
-                     /* handled by decodetree */
++    TCGv_ptr ptr1;
-                     return 1;
+     TCGv_i64 tmp64;
-                 case NEON_2RM_VTRN:
      if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
 @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                     for (pass = 0; pass < (q ? 4 : 2); pass++) {
+                     if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) {
-                         tmp = neon_load_reg(rm, pass);
+                         return 1;
-                         switch (op) {
+                     }
--                        case NEON_2RM_VSWP:
+-                    ptr1 = vfp_reg_ptr(true, rd);
--                            tmp2 = neon_load_reg(rd, pass);
+-                    ptr2 = vfp_reg_ptr(true, rm);
--                            neon_store_reg(rm, pass, tmp2);
+-
--                            break;
+-                    gen_helper_crypto_sha1h(ptr1, ptr2);
-                         case NEON_2RM_VTRN:
+-
-                             tmp2 = neon_load_reg(rd, pass);
+-                    tcg_temp_free_ptr(ptr1);
-                             switch (size) {
+-                    tcg_temp_free_ptr(ptr2);
 +                    tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0,
 +                                       gen_helper_crypto_sha1h);
                      break;
                  case NEON_2RM_SHA1SU1:
                      if ((rm | rd) & 1) {
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                      } else if (!dc_isar_feature(aa32_sha1, s)) {
                          return 1;
                      }
 -                    ptr1 = vfp_reg_ptr(true, rd);
 -                    ptr2 = vfp_reg_ptr(true, rm);
 -                    if (q) {
 -                        gen_helper_crypto_sha256su0(ptr1, ptr2);
 -                    } else {
 -                        gen_helper_crypto_sha1su1(ptr1, ptr2);
 -                    }
 -                    tcg_temp_free_ptr(ptr1);
 -                    tcg_temp_free_ptr(ptr2);
 +                    tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0,
 +                                       q ? gen_helper_crypto_sha256su0
 +                                       : gen_helper_crypto_sha1su1);
                      break;
 -
                  case NEON_2RM_VMVN:
                      tcg_gen_gvec_not(0, rd_ofs, rm_ofs, vec_size, vec_size);
                      break;
 --
 .20.1

-[PULL 03/42] target/arm: Convert Neon 2-reg-misc VREV64 to decodetree
+[PULL 09/29] target/arm: Split helper_crypto_sha1_3reg
-Convert the Neon VREV64 insn from the 2-reg-misc grouping to decodetree.
+From: Richard Henderson <richard.henderson@linaro.org>
 Rather than passing an opcode to a helper, fully decode the
 operation at translate time.  Use clear_tail_16 to zap the
 balance of the SVE register with the AdvSIMD write.
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20200514212831.31248-6-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-2-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       | 12 ++++++++
+ target/arm/helper.h             |  5 +-
- target/arm/translate-neon.inc.c | 50 +++++++++++++++++++++++++++++++++
+ target/arm/neon-dp.decode       |  6 +-
- target/arm/translate.c          | 24 ++--------------
+ target/arm/crypto_helper.c      | 99 +++++++++++++++++++++------------
-files changed, 64 insertions(+), 22 deletions(-)
+ target/arm/translate-a64.c      | 29 ++++------
+ target/arm/translate-neon.inc.c | 46 ++++-----------
 files changed, 93 insertions(+), 92 deletions(-)
 diff --git a/target/arm/helper.h b/target/arm/helper.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.h
 +++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr)
  DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
  DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 -DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(crypto_sha1su0, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(crypto_sha1c, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(crypto_sha1p, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(crypto_sha1m, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
  DEF_HELPER_FLAGS_3(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
  DEF_HELPER_FLAGS_3(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/neon-dp.decode
 +++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
+@@ -XXX,XX +XXX,XX @@ VQRDMLAH_3s      1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
-                  vm=%vm_dp vd=%vd_dp size=1
+ @3same_crypto    .... .... .... .... .... .... .... .... \
-     VDUP_scalar  1111 001 1 1 . 11 index:1 100 .... 11 000 q:1 . 0 .... \
+                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 q=1
-                  vm=%vm_dp vd=%vd_dp size=2
-+
+-SHA1_3s          1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \
-+    ##################################################################
+-                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
-+    # 2-reg-misc grouping:
++SHA1C_3s         1111 001 0 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
-+    # 1111 001 11 D 11 size:2 opc1:2 Vd:4 0 opc2:4 q:1 M 0 Vm:4
++SHA1P_3s         1111 001 0 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
-+    ##################################################################
++SHA1M_3s         1111 001 0 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
-+
++SHA1SU0_3s       1111 001 0 0 . 11 .... .... 1100 . 1 . 0 .... @3same_crypto
-+    &2misc vd vm q size
+ SHA256H_3s       1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
-+
+ SHA256H2_3s      1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
-+    @2misc       .... ... .. . .. size:2 .. .... . .... q:1 . . .... \
+ SHA256SU1_3s     1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
-+                 &2misc vm=%vm_dp vd=%vd_dp
+diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
-+
+index XXXXXXX..XXXXXXX 100644
-+    VREV64       1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc
+--- a/target/arm/crypto_helper.c
-   ]
++++ b/target/arm/crypto_helper.c
+@@ -XXX,XX +XXX,XX @@ union CRYPTO_STATE {
-   # Subgroup for size != 0b11
+ };
  #ifdef HOST_WORDS_BIGENDIAN
 -#define CR_ST_BYTE(state, i)   (state.bytes[(15 - (i)) ^ 8])
 -#define CR_ST_WORD(state, i)   (state.words[(3 - (i)) ^ 2])
 +#define CR_ST_BYTE(state, i)   ((state).bytes[(15 - (i)) ^ 8])
 +#define CR_ST_WORD(state, i)   ((state).words[(3 - (i)) ^ 2])
  #else
 -#define CR_ST_BYTE(state, i)   (state.bytes[i])
 -#define CR_ST_WORD(state, i)   (state.words[i])
 +#define CR_ST_BYTE(state, i)   ((state).bytes[i])
 +#define CR_ST_WORD(state, i)   ((state).words[i])
  #endif
  /*
@@ -XXX,XX +XXX,XX @@ static uint32_t maj(uint32_t x, uint32_t y, uint32_t z)
      return (x & y) | ((x | y) & z);
  }
 -void HELPER(crypto_sha1_3reg)(void *vd, void *vn, void *vm, uint32_t op)
 +void HELPER(crypto_sha1su0)(void *vd, void *vn, void *vm, uint32_t desc)
 +{
 +    uint64_t *d = vd, *n = vn, *m = vm;
 +    uint64_t d0, d1;
 +
 +    d0 = d[1] ^ d[0] ^ m[0];
 +    d1 = n[0] ^ d[1] ^ m[1];
 +    d[0] = d0;
 +    d[1] = d1;
 +
 +    clear_tail_16(vd, desc);
 +}
 +
 +static inline void crypto_sha1_3reg(uint64_t *rd, uint64_t *rn,
 +                                    uint64_t *rm, uint32_t desc,
 +                                    uint32_t (*fn)(union CRYPTO_STATE *d))
  {
 -    uint64_t *rd = vd;
 -    uint64_t *rn = vn;
 -    uint64_t *rm = vm;
      union CRYPTO_STATE d = { .l = { rd[0], rd[1] } };
      union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };
      union CRYPTO_STATE m = { .l = { rm[0], rm[1] } };
 +    int i;
 -    if (op == 3) { /* sha1su0 */
 -        d.l[0] ^= d.l[1] ^ m.l[0];
 -        d.l[1] ^= n.l[0] ^ m.l[1];
 -    } else {
 -        int i;
 +    for (i = 0; i < 4; i++) {
 +        uint32_t t = fn(&d);
 -        for (i = 0; i < 4; i++) {
 -            uint32_t t;
 +        t += rol32(CR_ST_WORD(d, 0), 5) + CR_ST_WORD(n, 0)
 +             + CR_ST_WORD(m, i);
 -            switch (op) {
 -            case 0: /* sha1c */
 -                t = cho(CR_ST_WORD(d, 1), CR_ST_WORD(d, 2), CR_ST_WORD(d, 3));
 -                break;
 -            case 1: /* sha1p */
 -                t = par(CR_ST_WORD(d, 1), CR_ST_WORD(d, 2), CR_ST_WORD(d, 3));
 -                break;
 -            case 2: /* sha1m */
 -                t = maj(CR_ST_WORD(d, 1), CR_ST_WORD(d, 2), CR_ST_WORD(d, 3));
 -                break;
 -            default:
 -                g_assert_not_reached();
 -            }
 -            t += rol32(CR_ST_WORD(d, 0), 5) + CR_ST_WORD(n, 0)
 -                 + CR_ST_WORD(m, i);
 -
 -            CR_ST_WORD(n, 0) = CR_ST_WORD(d, 3);
 -            CR_ST_WORD(d, 3) = CR_ST_WORD(d, 2);
 -            CR_ST_WORD(d, 2) = ror32(CR_ST_WORD(d, 1), 2);
 -            CR_ST_WORD(d, 1) = CR_ST_WORD(d, 0);
 -            CR_ST_WORD(d, 0) = t;
 -        }
 +        CR_ST_WORD(n, 0) = CR_ST_WORD(d, 3);
 +        CR_ST_WORD(d, 3) = CR_ST_WORD(d, 2);
 +        CR_ST_WORD(d, 2) = ror32(CR_ST_WORD(d, 1), 2);
 +        CR_ST_WORD(d, 1) = CR_ST_WORD(d, 0);
 +        CR_ST_WORD(d, 0) = t;
      }
      rd[0] = d.l[0];
      rd[1] = d.l[1];
 +
 +    clear_tail_16(rd, desc);
 +}
 +
 +static uint32_t do_sha1c(union CRYPTO_STATE *d)
 +{
 +    return cho(CR_ST_WORD(*d, 1), CR_ST_WORD(*d, 2), CR_ST_WORD(*d, 3));
 +}
 +
 +void HELPER(crypto_sha1c)(void *vd, void *vn, void *vm, uint32_t desc)
 +{
 +    crypto_sha1_3reg(vd, vn, vm, desc, do_sha1c);
 +}
 +
 +static uint32_t do_sha1p(union CRYPTO_STATE *d)
 +{
 +    return par(CR_ST_WORD(*d, 1), CR_ST_WORD(*d, 2), CR_ST_WORD(*d, 3));
 +}
 +
 +void HELPER(crypto_sha1p)(void *vd, void *vn, void *vm, uint32_t desc)
 +{
 +    crypto_sha1_3reg(vd, vn, vm, desc, do_sha1p);
 +}
 +
 +static uint32_t do_sha1m(union CRYPTO_STATE *d)
 +{
 +    return maj(CR_ST_WORD(*d, 1), CR_ST_WORD(*d, 2), CR_ST_WORD(*d, 3));
 +}
 +
 +void HELPER(crypto_sha1m)(void *vd, void *vn, void *vm, uint32_t desc)
 +{
 +    crypto_sha1_3reg(vd, vn, vm, desc, do_sha1m);
  }
  void HELPER(crypto_sha1h)(void *vd, void *vm, uint32_t desc)
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
      switch (opcode) {
      case 0: /* SHA1C */
 +        genfn = gen_helper_crypto_sha1c;
 +        feature = dc_isar_feature(aa64_sha1, s);
 +        break;
      case 1: /* SHA1P */
 +        genfn = gen_helper_crypto_sha1p;
 +        feature = dc_isar_feature(aa64_sha1, s);
 +        break;
      case 2: /* SHA1M */
 +        genfn = gen_helper_crypto_sha1m;
 +        feature = dc_isar_feature(aa64_sha1, s);
 +        break;
      case 3: /* SHA1SU0 */
 -        genfn = NULL;
 +        genfn = gen_helper_crypto_sha1su0;
          feature = dc_isar_feature(aa64_sha1, s);
          break;
      case 4: /* SHA256H */
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
      if (!fp_access_check(s)) {
          return;
      }
 -
 -    if (genfn) {
 -        gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn);
 -    } else {
 -        TCGv_i32 tcg_opcode = tcg_const_i32(opcode);
 -        TCGv_ptr tcg_rd_ptr = vec_full_reg_ptr(s, rd);
 -        TCGv_ptr tcg_rn_ptr = vec_full_reg_ptr(s, rn);
 -        TCGv_ptr tcg_rm_ptr = vec_full_reg_ptr(s, rm);
 -
 -        gen_helper_crypto_sha1_3reg(tcg_rd_ptr, tcg_rn_ptr,
 -                                    tcg_rm_ptr, tcg_opcode);
 -
 -        tcg_temp_free_i32(tcg_opcode);
 -        tcg_temp_free_ptr(tcg_rd_ptr);
 -        tcg_temp_free_ptr(tcg_rn_ptr);
 -        tcg_temp_free_ptr(tcg_rm_ptr);
 -    }
 +    gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn);
  }
  /* Crypto two-reg SHA
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.inc.c
 +++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
+@@ -XXX,XX +XXX,XX @@ static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
-                          a->q ? 16 : 8, a->q ? 16 : 8);
+ DO_VQRDMLAH(VQRDMLAH, gen_gvec_sqrdmlah_qc)
-     return true;
+ DO_VQRDMLAH(VQRDMLSH, gen_gvec_sqrdmlsh_qc)
- }
-+
+-static bool trans_SHA1_3s(DisasContext *s, arg_SHA1_3s *a)
-+static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
+-{
-+{
+-    TCGv_ptr ptr1, ptr2, ptr3;
-+    int pass, half;
+-    TCGv_i32 tmp;
-+
+-
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+-    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
-+        return false;
+-        !dc_isar_feature(aa32_sha1, s)) {
-+    }
+-        return false;
-+
++#define DO_SHA1(NAME, FUNC)                                             \
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
++    WRAP_OOL_FN(gen_##NAME##_3s, FUNC)                                  \
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
++    static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a)        \
-+        ((a->vd | a->vm) & 0x10)) {
++    {                                                                   \
-+        return false;
++        if (!dc_isar_feature(aa32_sha1, s)) {                           \
-+    }
++            return false;                                               \
-+
++        }                                                               \
-+    if ((a->vd | a->vm) & a->q) {
++        return do_3same(s, a, gen_##NAME##_3s);                         \
-+        return false;
+     }
-+    }
-+
+-    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (a->size == 3) {
+-    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        return false;
+-        ((a->vd | a->vn | a->vm) & 0x10)) {
-+    }
+-        return false;
-+
+-    }
-+    if (!vfp_access_check(s)) {
+-
-+        return true;
+-    if ((a->vn | a->vm | a->vd) & 1) {
-+    }
+-        return false;
-+
+-    }
-+    for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
+-
-+        TCGv_i32 tmp[2];
+-    if (!vfp_access_check(s)) {
-+
+-        return true;
-+        for (half = 0; half < 2; half++) {
+-    }
-+            tmp[half] = neon_load_reg(a->vm, pass * 2 + half);
+-
-+            switch (a->size) {
+-    ptr1 = vfp_reg_ptr(true, a->vd);
-+            case 0:
+-    ptr2 = vfp_reg_ptr(true, a->vn);
-+                tcg_gen_bswap32_i32(tmp[half], tmp[half]);
+-    ptr3 = vfp_reg_ptr(true, a->vm);
-+                break;
+-    tmp = tcg_const_i32(a->optype);
-+            case 1:
+-    gen_helper_crypto_sha1_3reg(ptr1, ptr2, ptr3, tmp);
-+                gen_swap_half(tmp[half]);
+-    tcg_temp_free_i32(tmp);
-+                break;
+-    tcg_temp_free_ptr(ptr1);
-+            case 2:
+-    tcg_temp_free_ptr(ptr2);
-+                break;
+-    tcg_temp_free_ptr(ptr3);
-+            default:
+-
-+                g_assert_not_reached();
+-    return true;
-+            }
+-}
-+        }
++DO_SHA1(SHA1C, gen_helper_crypto_sha1c)
-+        neon_store_reg(a->vd, pass * 2, tmp[1]);
++DO_SHA1(SHA1P, gen_helper_crypto_sha1p)
-+        neon_store_reg(a->vd, pass * 2 + 1, tmp[0]);
++DO_SHA1(SHA1M, gen_helper_crypto_sha1m)
-+    }
++DO_SHA1(SHA1SU0, gen_helper_crypto_sha1su0)
-+    return true;
-+}
+ #define DO_SHA2(NAME, FUNC)                                             \
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+     WRAP_OOL_FN(gen_##NAME##_3s, FUNC)                                  \
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                  }
                  switch (op) {
                  case NEON_2RM_VREV64:
 -                    for (pass = 0; pass < (q ? 2 : 1); pass++) {
 -                        tmp = neon_load_reg(rm, pass * 2);
 -                        tmp2 = neon_load_reg(rm, pass * 2 + 1);
 -                        switch (size) {
 -                        case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
 -                        case 1: gen_swap_half(tmp); break;
 -                        case 2: /* no-op */ break;
 -                        default: abort();
 -                        }
 -                        neon_store_reg(rd, pass * 2 + 1, tmp);
 -                        if (size == 2) {
 -                            neon_store_reg(rd, pass * 2, tmp2);
 -                        } else {
 -                            switch (size) {
 -                            case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
 -                            case 1: gen_swap_half(tmp2); break;
 -                            default: abort();
 -                            }
 -                            neon_store_reg(rd, pass * 2, tmp2);
 -                        }
 -                    }
 -                    break;
 +                    /* handled by decodetree */
 +                    return 1;
                  case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U:
                  case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U:
                      for (pass = 0; pass < q + 1; pass++) {
 --
 .20.1

-[PULL 41/42] tests/qtest/arm-cpu-features: Add feature setting tests
+[PULL 10/29] target/arm: Split helper_crypto_sm3tt
-From: Andrew Jones <drjones@redhat.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Some cpu features may be enabled and disabled for all configurations
+Rather than passing an opcode to a helper, fully decode the
-that support the feature. Let's test that.
+operation at translate time.  Use clear_tail_16 to zap the
 balance of the SVE register with the AdvSIMD write.
-A recent regression[*] inspired adding these tests.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20200514212831.31248-7-richard.henderson@linaro.org
 [*] '-cpu host,pmu=on' caused a segfault
 Signed-off-by: Andrew Jones <drjones@redhat.com>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20200623090622.30365-2-philmd@redhat.com
 Message-Id: <20200623082310.17577-1-drjones@redhat.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- tests/qtest/arm-cpu-features.c | 38 ++++++++++++++++++++++++++++++----
+ target/arm/helper.h        |  5 ++++-
-file changed, 34 insertions(+), 4 deletions(-)
+ target/arm/crypto_helper.c | 24 ++++++++++++++++++------
  target/arm/translate-a64.c | 21 +++++----------------
 files changed, 27 insertions(+), 23 deletions(-)
-diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
+diff --git a/target/arm/helper.h b/target/arm/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/tests/qtest/arm-cpu-features.c
+--- a/target/arm/helper.h
-+++ b/tests/qtest/arm-cpu-features.c
++++ b/target/arm/helper.h
-@@ -XXX,XX +XXX,XX @@ static bool resp_get_feature(QDict *resp, const char *feature)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
-     qobject_unref(_resp);                                              \
+ DEF_HELPER_FLAGS_4(crypto_sha512su1, TCG_CALL_NO_RWG,
- })
+                    void, ptr, ptr, ptr, i32)
--#define assert_feature(qts, cpu_type, feature, expected_value)         \
+-DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32, i32)
-+#define resp_assert_feature(resp, feature, expected_value)             \
++DEF_HELPER_FLAGS_4(crypto_sm3tt1a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
- ({                                                                     \
++DEF_HELPER_FLAGS_4(crypto_sm3tt1b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
--    QDict *_resp, *_props;                                             \
++DEF_HELPER_FLAGS_4(crypto_sm3tt2a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-+    QDict *_props;                                                     \
++DEF_HELPER_FLAGS_4(crypto_sm3tt2b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-                                                                        \
+ DEF_HELPER_FLAGS_4(crypto_sm3partw1, TCG_CALL_NO_RWG,
--    _resp = do_query_no_props(qts, cpu_type);                          \
+                    void, ptr, ptr, ptr, i32)
-     g_assert(_resp);                                                   \
+ DEF_HELPER_FLAGS_4(crypto_sm3partw2, TCG_CALL_NO_RWG,
-     g_assert(resp_has_props(_resp));                                   \
+diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
-     _props = resp_get_props(_resp);                                    \
+index XXXXXXX..XXXXXXX 100644
-     g_assert(qdict_get(_props, feature));                              \
+--- a/target/arm/crypto_helper.c
-     g_assert(qdict_get_bool(_props, feature) == (expected_value));     \
++++ b/target/arm/crypto_helper.c
-+})
+@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm, uint32_t desc)
      clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2,
 -                          uint32_t opcode)
 +static inline void QEMU_ALWAYS_INLINE
 +crypto_sm3tt(uint64_t *rd, uint64_t *rn, uint64_t *rm,
 +             uint32_t desc, uint32_t opcode)
  {
 -    uint64_t *rd = vd;
 -    uint64_t *rn = vn;
 -    uint64_t *rm = vm;
      union CRYPTO_STATE d = { .l = { rd[0], rd[1] } };
      union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };
      union CRYPTO_STATE m = { .l = { rm[0], rm[1] } };
 +    uint32_t imm2 = simd_data(desc);
      uint32_t t;
      assert(imm2 < 4);
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2,
          /* SM3TT2B */
          t = cho(CR_ST_WORD(d, 3), CR_ST_WORD(d, 2), CR_ST_WORD(d, 1));
      } else {
 -        g_assert_not_reached();
 +        qemu_build_not_reached();
      }
      t += CR_ST_WORD(d, 0) + CR_ST_WORD(m, imm2);
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2,
      rd[0] = d.l[0];
      rd[1] = d.l[1];
 +
-+#define assert_feature(qts, cpu_type, feature, expected_value)         \
++    clear_tail_16(rd, desc);
-+({                                                                     \
+ }
-+    QDict *_resp;                                                      \
-+                                                                       \
++#define DO_SM3TT(NAME, OPCODE) \
-+    _resp = do_query_no_props(qts, cpu_type);                          \
++    void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
-+    g_assert(_resp);                                                   \
++    { crypto_sm3tt(vd, vn, vm, desc, OPCODE); }
 +    resp_assert_feature(_resp, feature, expected_value);               \
 +    qobject_unref(_resp);                                              \
 +})
 +
-+#define assert_set_feature(qts, cpu_type, feature, value)              \
++DO_SM3TT(crypto_sm3tt1a, 0)
-+({                                                                     \
++DO_SM3TT(crypto_sm3tt1b, 1)
-+    const char *_fmt = (value) ? "{ %s: true }" : "{ %s: false }";     \
++DO_SM3TT(crypto_sm3tt2a, 2)
-+    QDict *_resp;                                                      \
++DO_SM3TT(crypto_sm3tt2b, 3)
 +                                                                       \
 +    _resp = do_query(qts, cpu_type, _fmt, feature);                    \
 +    g_assert(_resp);                                                   \
 +    resp_assert_feature(_resp, feature, value);                        \
      qobject_unref(_resp);                                              \
  })
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
      assert_error(qts, "host", "The CPU type 'host' requires KVM", NULL);
      /* Test expected feature presence/absence for some cpu types */
 -    assert_has_feature_enabled(qts, "max", "pmu");
      assert_has_feature_enabled(qts, "cortex-a15", "pmu");
      assert_has_not_feature(qts, "cortex-a15", "aarch64");
 +    /* Enabling and disabling pmu should always work. */
 +    assert_has_feature_enabled(qts, "max", "pmu");
 +    assert_set_feature(qts, "max", "pmu", false);
 +    assert_set_feature(qts, "max", "pmu", true);
 +
-     assert_has_not_feature(qts, "max", "kvm-no-adjvtime");
++#undef DO_SM3TT
++
-     if (g_str_equal(qtest_get_arch(), "aarch64")) {
+ static uint8_t const sm4_sbox[] = {
-@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
+xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
 x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_xar(DisasContext *s, uint32_t insn)
   */
  static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn)
  {
 +    static gen_helper_gvec_3 * const fns[4] = {
 +        gen_helper_crypto_sm3tt1a, gen_helper_crypto_sm3tt1b,
 +        gen_helper_crypto_sm3tt2a, gen_helper_crypto_sm3tt2b,
 +    };
      int opcode = extract32(insn, 10, 2);
      int imm2 = extract32(insn, 12, 2);
      int rm = extract32(insn, 16, 5);
      int rn = extract32(insn, 5, 5);
      int rd = extract32(insn, 0, 5);
 -    TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
 -    TCGv_i32 tcg_imm2, tcg_opcode;
      if (!dc_isar_feature(aa64_sm3, s)) {
          unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn)
          return;
      }
-+    /* Enabling and disabling kvm-no-adjvtime should always work. */
+-    tcg_rd_ptr = vec_full_reg_ptr(s, rd);
-     assert_has_feature_disabled(qts, "host", "kvm-no-adjvtime");
+-    tcg_rn_ptr = vec_full_reg_ptr(s, rn);
-+    assert_set_feature(qts, "host", "kvm-no-adjvtime", true);
+-    tcg_rm_ptr = vec_full_reg_ptr(s, rm);
-+    assert_set_feature(qts, "host", "kvm-no-adjvtime", false);
+-    tcg_imm2   = tcg_const_i32(imm2);
+-    tcg_opcode = tcg_const_i32(opcode);
-     if (g_str_equal(qtest_get_arch(), "aarch64")) {
+-
-         bool kvm_supports_sve;
+-    gen_helper_crypto_sm3tt(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr, tcg_imm2,
-@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
+-                            tcg_opcode);
-         char *error;
+-
+-    tcg_temp_free_ptr(tcg_rd_ptr);
-         assert_has_feature_enabled(qts, "host", "aarch64");
+-    tcg_temp_free_ptr(tcg_rn_ptr);
-+
+-    tcg_temp_free_ptr(tcg_rm_ptr);
-+        /* Enabling and disabling pmu should always work. */
+-    tcg_temp_free_i32(tcg_imm2);
-         assert_has_feature_enabled(qts, "host", "pmu");
+-    tcg_temp_free_i32(tcg_opcode);
-+        assert_set_feature(qts, "host", "pmu", false);
++    gen_gvec_op3_ool(s, true, rd, rn, rm, imm2, fns[opcode]);
-+        assert_set_feature(qts, "host", "pmu", true);
+ }
-         assert_error(qts, "cortex-a15",
+ /* C3.6 Data processing - SIMD, inc Crypto
              "We cannot guarantee the CPU type 'cortex-a15' works "
 --
 .20.1

-[PULL 32/42] hw/arm/mps2: Rename CMSDK AHB peripheral region
+[PULL 11/29] hw/adc/stm32f2xx_adc: Correct memory region size and access size
 From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-To differenciate with the CMSDK APB peripheral region,
+The ADC region size is 256B, split as:
-rename this region 'CMSDK AHB peripheral region'.
+ - [0x00 - 0x4f] defined
  - [0x50 - 0xff] reserved
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+All registers are 32-bit (thus when the datasheet mentions the
 last defined register is 0x4c, it means its address range is
 x4c .. 0x4f.
 This model implementation is also 32-bit. Set MemoryRegionOps
 'impl' fields.
 See:
   'RM0033 Reference manual Rev 8', Table 10.13.18 "ADC register map".
 Reported-by: Seth Kintigh <skintigh@gmail.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20200617072539.32686-8-f4bug@amsat.org
+Message-id: 20200603055915.17678-1-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/mps2.c | 3 ++-
+ hw/adc/stm32f2xx_adc.c | 4 +++-
-file changed, 2 insertions(+), 1 deletion(-)
+file changed, 3 insertions(+), 1 deletion(-)
-diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
+diff --git a/hw/adc/stm32f2xx_adc.c b/hw/adc/stm32f2xx_adc.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/mps2.c
+--- a/hw/adc/stm32f2xx_adc.c
-+++ b/hw/arm/mps2.c
++++ b/hw/adc/stm32f2xx_adc.c
-@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps stm32f2xx_adc_ops = {
-      */
+     .read = stm32f2xx_adc_read,
-     create_unimplemented_device("CMSDK APB peripheral region @0x40000000",
+     .write = stm32f2xx_adc_write,
-x40000000, 0x00010000);
+     .endianness = DEVICE_NATIVE_ENDIAN,
--    create_unimplemented_device("CMSDK peripheral region @0x40010000",
++    .impl.min_access_size = 4,
-+    create_unimplemented_device("CMSDK AHB peripheral region @0x40010000",
++    .impl.max_access_size = 4,
-x40010000, 0x00010000);
+ };
-     create_unimplemented_device("Extra peripheral region @0x40020000",
-x40020000, 0x00010000);
+ static const VMStateDescription vmstate_stm32f2xx_adc = {
-+
+@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_adc_init(Object *obj)
-     create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000);
+     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
-     create_unimplemented_device("VGA", 0x41000000, 0x0200000);
      memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s,
 -                          TYPE_STM32F2XX_ADC, 0xFF);
 +                          TYPE_STM32F2XX_ADC, 0x100);
      sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
  }
 --
 .20.1

-[PULL 36/42] hw/arm/mps2: Add SPI devices
+[PULL 12/29] tests/acceptance: Add a boot test for the xlnx-versal-virt machine
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Thomas Huth <thuth@redhat.com>
-From 'Application Note AN385', chapter 3.9, SPI:
+As described by Edgar here:
-  The SMM implements five PL022 SPI modules.
+ https://www.mail-archive.com/qemu-devel@nongnu.org/msg605124.html
-Two pairs of modules share the same OR-gated IRQ.
+we can use the Ubuntu kernel for testing the xlnx-versal-virt machine.
 So let's add a boot test for this now.
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 20200617072539.32686-12-f4bug@amsat.org
+Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Thomas Huth <thuth@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 Message-id: 20200525141237.15243-1-thuth@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/mps2.c  | 24 ++++++++++++++++++++++++
+ tests/acceptance/boot_linux_console.py | 26 ++++++++++++++++++++++++++
- hw/arm/Kconfig |  6 +++---
+file changed, 26 insertions(+)
 files changed, 27 insertions(+), 3 deletions(-)
-diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
+diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/mps2.c
+--- a/tests/acceptance/boot_linux_console.py
-+++ b/hw/arm/mps2.c
++++ b/tests/acceptance/boot_linux_console.py
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(LinuxKernelTest):
- #include "hw/timer/cmsdk-apb-dualtimer.h"
+         console_pattern = 'Kernel command line: %s' % kernel_command_line
- #include "hw/misc/mps2-scc.h"
+         self.wait_for_console_pattern(console_pattern)
- #include "hw/misc/mps2-fpgaio.h"
-+#include "hw/ssi/pl022.h"
++    def test_aarch64_xlnx_versal_virt(self):
- #include "hw/net/lan9118.h"
++        """
- #include "net/net.h"
++        :avocado: tags=arch:aarch64
- #include "hw/watchdog/cmsdk-apb-watchdog.h"
++        :avocado: tags=machine:xlnx-versal-virt
-@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
++        :avocado: tags=device:pl011
-     qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", 25000000);
++        :avocado: tags=device:arm_gicv3
-     sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
++        """
-     sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0x40028000);
++        kernel_url = ('http://ports.ubuntu.com/ubuntu-ports/dists/'
-+    sysbus_create_simple(TYPE_PL022, 0x40025000,        /* External ADC */
++                      'bionic-updates/main/installer-arm64/current/images/'
-+                         qdev_get_gpio_in(armv7m, 22));
++                      'netboot/ubuntu-installer/arm64/linux')
-+    for (i = 0; i < 2; i++) {
++        kernel_hash = '5bfc54cf7ed8157d93f6e5b0241e727b6dc22c50'
-+        static const int spi_irqno[] = {11, 24};
++        kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
 +        static const hwaddr spibase[] = {0x40020000,    /* APB */
 +                                         0x40021000,    /* LCD */
 +                                         0x40026000,    /* Shield0 */
 +                                         0x40027000};   /* Shield1 */
 +        DeviceState *orgate_dev;
 +        Object *orgate;
 +        int j;
 +
-+        orgate = object_new(TYPE_OR_IRQ);
++        initrd_url = ('http://ports.ubuntu.com/ubuntu-ports/dists/'
-+        object_property_set_int(orgate, 2, "num-lines", &error_fatal);
++                      'bionic-updates/main/installer-arm64/current/images/'
-+        orgate_dev = DEVICE(orgate);
++                      'netboot/ubuntu-installer/arm64/initrd.gz')
-+        qdev_realize(orgate_dev, NULL, &error_fatal);
++        initrd_hash = 'd385d3e88d53e2004c5d43cbe668b458a094f772'
-+        qdev_connect_gpio_out(orgate_dev, 0,
++        initrd_path = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
-+                              qdev_get_gpio_in(armv7m, spi_irqno[i]));
++
-+        for (j = 0; j < 2; j++) {
++        self.vm.set_console()
-+            sysbus_create_simple(TYPE_PL022, spibase[2 * i + j],
++        self.vm.add_args('-m', '2G',
-+                                 qdev_get_gpio_in(orgate_dev, j));
++                         '-kernel', kernel_path,
-+        }
++                         '-initrd', initrd_path)
-+    }
++        self.vm.launch()
++        self.wait_for_console_pattern('Checked W+X mappings: passed')
-     /* In hardware this is a LAN9220; the LAN9118 is software compatible
++
-      * except that it doesn't support the checksum-offload feature.
+     def test_arm_virt(self):
-diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
+         """
-index XXXXXXX..XXXXXXX 100644
+         :avocado: tags=arch:arm
 --- a/hw/arm/Kconfig
 +++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config HIGHBANK
      select ARM_TIMER # sp804
      select ARM_V7M
      select PL011 # UART
 -    select PL022 # Serial port
 +    select PL022 # SPI
      select PL031 # RTC
      select PL061 # GPIO
      select PL310 # cache controller
@@ -XXX,XX +XXX,XX @@ config STELLARIS
      select CMSDK_APB_WATCHDOG
      select I2C
      select PL011 # UART
 -    select PL022 # Serial port
 +    select PL022 # SPI
      select PL061 # GPIO
      select SSD0303 # OLED display
      select SSD0323 # OLED display
@@ -XXX,XX +XXX,XX @@ config MPS2
      select MPS2_FPGAIO
      select MPS2_SCC
      select OR_IRQ
 -    select PL022    # Serial port
 +    select PL022    # SPI
      select PL080    # DMA controller
      select SPLIT_IRQ
      select UNIMP
 --
 .20.1

-[PULL 35/42] hw/arm/mps2: Map the FPGA I/O block
+[PULL 13/29] docs/system: Document Aspeed boards
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Cédric Le Goater <clg@kaod.org>
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Cédric Le Goater <clg@kaod.org>
-Message-id: 20200617072539.32686-11-f4bug@amsat.org
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20200602135050.593692-1-clg@kaod.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/mps2.c | 9 +++++++++
+ docs/system/arm/aspeed.rst | 85 ++++++++++++++++++++++++++++++++++++++
-file changed, 9 insertions(+)
+ docs/system/target-arm.rst |  1 +
 files changed, 86 insertions(+)
  create mode 100644 docs/system/arm/aspeed.rst
-diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
+diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/docs/system/arm/aspeed.rst
@@ -XXX,XX +XXX,XX @@
 +Aspeed family boards (``*-bmc``, ``ast2500-evb``, ``ast2600-evb``)
 +==================================================================
 +
 +The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
 +Aspeed evaluation boards. They are based on different releases of the
 +Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the
 +AST2500 with an ARM1176JZS CPU (800MHz) and more recently the AST2600
 +with dual cores ARM Cortex A7 CPUs (1.2GHz).
 +
 +The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C,
 +etc.
 +
 +AST2400 SoC based machines :
 +
 +- ``palmetto-bmc``         OpenPOWER Palmetto POWER8 BMC
 +
 +AST2500 SoC based machines :
 +
 +- ``ast2500-evb``          Aspeed AST2500 Evaluation board
 +- ``romulus-bmc``          OpenPOWER Romulus POWER9 BMC
 +- ``witherspoon-bmc``      OpenPOWER Witherspoon POWER9 BMC
 +- ``sonorapass-bmc``       OCP SonoraPass BMC
 +- ``swift-bmc``            OpenPOWER Swift BMC POWER9
 +
 +AST2600 SoC based machines :
 +
 +- ``ast2600-evb``          Aspeed AST2600 Evaluation board (Cortex A7)
 +- ``tacoma-bmc``           OpenPOWER Witherspoon POWER9 AST2600 BMC
 +
 +Supported devices
 +-----------------
 +
 + * SMP (for the AST2600 Cortex-A7)
 + * Interrupt Controller (VIC)
 + * Timer Controller
 + * RTC Controller
 + * I2C Controller
 + * System Control Unit (SCU)
 + * SRAM mapping
 + * X-DMA Controller (basic interface)
 + * Static Memory Controller (SMC or FMC) - Only SPI Flash support
 + * SPI Memory Controller
 + * USB 2.0 Controller
 + * SD/MMC storage controllers
 + * SDRAM controller (dummy interface for basic settings and training)
 + * Watchdog Controller
 + * GPIO Controller (Master only)
 + * UART
 + * Ethernet controllers
 +
 +
 +Missing devices
 +---------------
 +
 + * Coprocessor support
 + * ADC (out of tree implementation)
 + * PWM and Fan Controller
 + * LPC Bus Controller
 + * Slave GPIO Controller
 + * Super I/O Controller
 + * Hash/Crypto Engine
 + * PCI-Express 1 Controller
 + * Graphic Display Controller
 + * PECI Controller
 + * MCTP Controller
 + * Mailbox Controller
 + * Virtual UART
 + * eSPI Controller
 + * I3C Controller
 +
 +Boot options
 +------------
 +
 +The Aspeed machines can be started using the -kernel option to load a
 +Linux kernel or from a firmare image which can be downloaded from the
 +OpenPOWER jenkins :
 +
 +   https://openpower.xyz/
 +
 +The image should be attached as an MTD drive. Run :
 +
 +.. code-block:: bash
 +
 +  $ qemu-system-arm -M romulus-bmc -nic user \
 +    -drive file=flash-romulus,format=raw,if=mtd -nographic
 diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/mps2.c
+--- a/docs/system/target-arm.rst
-+++ b/hw/arm/mps2.c
++++ b/docs/system/target-arm.rst
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
- #include "hw/timer/cmsdk-apb-timer.h"
+    arm/realview
- #include "hw/timer/cmsdk-apb-dualtimer.h"
+    arm/versatile
- #include "hw/misc/mps2-scc.h"
+    arm/vexpress
-+#include "hw/misc/mps2-fpgaio.h"
++   arm/aspeed
- #include "hw/net/lan9118.h"
+    arm/musicpal
- #include "net/net.h"
+    arm/nseries
-+#include "hw/watchdog/cmsdk-apb-watchdog.h"
+    arm/orangepi
  typedef enum MPS2FPGAType {
      FPGA_AN385,
@@ -XXX,XX +XXX,XX @@ typedef struct {
      MemoryRegion sram;
      /* FPGA APB subsystem */
      MPS2SCC scc;
 +    MPS2FPGAIO fpgaio;
      /* CMSDK APB subsystem */
      CMSDKAPBDualTimer dualtimer;
 +    CMSDKAPBWatchdog watchdog;
  } MPS2MachineState;
  #define TYPE_MPS2_MACHINE "mps2"
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
      qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
      sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
      sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000);
 +    object_initialize_child(OBJECT(mms), "fpgaio",
 +                            &mms->fpgaio, TYPE_MPS2_FPGAIO);
 +    qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", 25000000);
 +    sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0x40028000);
      /* In hardware this is a LAN9220; the LAN9118 is software compatible
       * except that it doesn't support the checksum-offload feature.
 --
 .20.1

-[PULL 28/42] hw/i2c/versatile_i2c: Add SCL/SDA definitions
+[PULL 14/29] raspi: add BCM2835 SOC MPHI emulation
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Paul Zimmerman <pauldzim@gmail.com>
-Use self-explicit definitions instead of magic values.
+Add BCM2835 SOC MPHI (Message-based Parallel Host Interface)
+emulation. It is very basic, only providing the FIQ interrupt
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+needed to allow the dwc-otg USB host controller driver in the
-Message-id: 20200617072539.32686-4-f4bug@amsat.org
+Raspbian kernel to function.
 Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
 Acked-by: Philippe Mathieu-Daude <f4bug@amsat.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20200520235349.21215-2-pauldzim@gmail.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/i2c/versatile_i2c.c | 7 +++++--
+ include/hw/arm/bcm2835_peripherals.h |   2 +
-file changed, 5 insertions(+), 2 deletions(-)
+ include/hw/misc/bcm2835_mphi.h       |  44 ++++++
+ hw/arm/bcm2835_peripherals.c         |  17 +++
-diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
+ hw/misc/bcm2835_mphi.c               | 191 +++++++++++++++++++++++++++
  hw/misc/Makefile.objs                |   1 +
 files changed, 255 insertions(+)
  create mode 100644 include/hw/misc/bcm2835_mphi.h
  create mode 100644 hw/misc/bcm2835_mphi.c
 diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/i2c/versatile_i2c.c
+--- a/include/hw/arm/bcm2835_peripherals.h
-+++ b/hw/i2c/versatile_i2c.c
++++ b/include/hw/arm/bcm2835_peripherals.h
-@@ -XXX,XX +XXX,XX @@ REG32(CONTROL_GET, 0)
+@@ -XXX,XX +XXX,XX @@
- REG32(CONTROL_SET, 0)
+ #include "hw/misc/bcm2835_property.h"
- REG32(CONTROL_CLR, 4)
+ #include "hw/misc/bcm2835_rng.h"
+ #include "hw/misc/bcm2835_mbox.h"
-+#define SCL BIT(0)
++#include "hw/misc/bcm2835_mphi.h"
-+#define SDA BIT(1)
+ #include "hw/misc/bcm2835_thermal.h"
-+
+ #include "hw/sd/sdhci.h"
- static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
+ #include "hw/sd/bcm2835_sdhost.h"
-                                    unsigned size)
+@@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState {
- {
+     qemu_irq irq, fiq;
-@@ -XXX,XX +XXX,XX @@ static void versatile_i2c_write(void *opaque, hwaddr offset,
-         qemu_log_mask(LOG_GUEST_ERROR,
+     BCM2835SystemTimerState systmr;
-                       "%s: Bad offset 0x%x\n", __func__, (int)offset);
++    BCM2835MphiState mphi;
-     }
+     UnimplementedDeviceState armtmr;
--    bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0);
+     UnimplementedDeviceState cprman;
--    s->in = bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0);
+     UnimplementedDeviceState a2w;
-+    bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SCL, (s->out & SCL) != 0);
+diff --git a/include/hw/misc/bcm2835_mphi.h b/include/hw/misc/bcm2835_mphi.h
-+    s->in = bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SDA, (s->out & SDA) != 0);
+new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/misc/bcm2835_mphi.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * BCM2835 SOC MPHI state definitions
 + *
 + * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
 + *
 + * This program is free software; you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License as published by
 + * the Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 + * GNU General Public License for more details.
 + */
 +
 +#ifndef HW_MISC_BCM2835_MPHI_H
 +#define HW_MISC_BCM2835_MPHI_H
 +
 +#include "hw/irq.h"
 +#include "hw/sysbus.h"
 +
 +#define MPHI_MMIO_SIZE      0x1000
 +
 +typedef struct BCM2835MphiState BCM2835MphiState;
 +
 +struct BCM2835MphiState {
 +    SysBusDevice parent_obj;
 +    qemu_irq irq;
 +    MemoryRegion iomem;
 +
 +    uint32_t outdda;
 +    uint32_t outddb;
 +    uint32_t ctrl;
 +    uint32_t intstat;
 +    uint32_t swirq;
 +};
 +
 +#define TYPE_BCM2835_MPHI   "bcm2835-mphi"
 +
 +#define BCM2835_MPHI(obj) \
 +    OBJECT_CHECK(BCM2835MphiState, (obj), TYPE_BCM2835_MPHI)
 +
 +#endif
 diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/bcm2835_peripherals.c
 +++ b/hw/arm/bcm2835_peripherals.c
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
                                     OBJECT(&s->sdhci.sdbus));
      object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost",
                                     OBJECT(&s->sdhost.sdbus));
 +
 +    /* Mphi */
 +    sysbus_init_child_obj(obj, "mphi", &s->mphi, sizeof(s->mphi),
 +                          TYPE_BCM2835_MPHI);
  }
- static const MemoryRegionOps versatile_i2c_ops = {
+ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
      object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus");
 +    /* Mphi */
 +    object_property_set_bool(OBJECT(&s->mphi), true, "realized", &err);
 +    if (err) {
 +        error_propagate(errp, err);
 +        return;
 +    }
 +
 +    memory_region_add_subregion(&s->peri_mr, MPHI_OFFSET,
 +                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mphi), 0));
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->mphi), 0,
 +        qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
 +                               INTERRUPT_HOSTPORT));
 +
      create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
      create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
      create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
 diff --git a/hw/misc/bcm2835_mphi.c b/hw/misc/bcm2835_mphi.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/bcm2835_mphi.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * BCM2835 SOC MPHI emulation
 + *
 + * Very basic emulation, only providing the FIQ interrupt needed to
 + * allow the dwc-otg USB host controller driver in the Raspbian kernel
 + * to function.
 + *
 + * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
 + *
 + * This program is free software; you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License as published by
 + * the Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 + * GNU General Public License for more details.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qapi/error.h"
 +#include "hw/misc/bcm2835_mphi.h"
 +#include "migration/vmstate.h"
 +#include "qemu/error-report.h"
 +#include "qemu/log.h"
 +#include "qemu/main-loop.h"
 +
 +static inline void mphi_raise_irq(BCM2835MphiState *s)
 +{
 +    qemu_set_irq(s->irq, 1);
 +}
 +
 +static inline void mphi_lower_irq(BCM2835MphiState *s)
 +{
 +    qemu_set_irq(s->irq, 0);
 +}
 +
 +static uint64_t mphi_reg_read(void *ptr, hwaddr addr, unsigned size)
 +{
 +    BCM2835MphiState *s = ptr;
 +    uint32_t val = 0;
 +
 +    switch (addr) {
 +    case 0x28:  /* outdda */
 +        val = s->outdda;
 +        break;
 +    case 0x2c:  /* outddb */
 +        val = s->outddb;
 +        break;
 +    case 0x4c:  /* ctrl */
 +        val = s->ctrl;
 +        val |= 1 << 17;
 +        break;
 +    case 0x50:  /* intstat */
 +        val = s->intstat;
 +        break;
 +    case 0x1f0: /* swirq_set */
 +        val = s->swirq;
 +        break;
 +    case 0x1f4: /* swirq_clr */
 +        val = s->swirq;
 +        break;
 +    default:
 +        qemu_log_mask(LOG_UNIMP, "read from unknown register");
 +        break;
 +    }
 +
 +    return val;
 +}
 +
 +static void mphi_reg_write(void *ptr, hwaddr addr, uint64_t val, unsigned size)
 +{
 +    BCM2835MphiState *s = ptr;
 +    int do_irq = 0;
 +
 +    switch (addr) {
 +    case 0x28:  /* outdda */
 +        s->outdda = val;
 +        break;
 +    case 0x2c:  /* outddb */
 +        s->outddb = val;
 +        if (val & (1 << 29)) {
 +            do_irq = 1;
 +        }
 +        break;
 +    case 0x4c:  /* ctrl */
 +        s->ctrl = val;
 +        if (val & (1 << 16)) {
 +            do_irq = -1;
 +        }
 +        break;
 +    case 0x50:  /* intstat */
 +        s->intstat = val;
 +        if (val & ((1 << 16) | (1 << 29))) {
 +            do_irq = -1;
 +        }
 +        break;
 +    case 0x1f0: /* swirq_set */
 +        s->swirq |= val;
 +        do_irq = 1;
 +        break;
 +    case 0x1f4: /* swirq_clr */
 +        s->swirq &= ~val;
 +        do_irq = -1;
 +        break;
 +    default:
 +        qemu_log_mask(LOG_UNIMP, "write to unknown register");
 +        return;
 +    }
 +
 +    if (do_irq > 0) {
 +        mphi_raise_irq(s);
 +    } else if (do_irq < 0) {
 +        mphi_lower_irq(s);
 +    }
 +}
 +
 +static const MemoryRegionOps mphi_mmio_ops = {
 +    .read = mphi_reg_read,
 +    .write = mphi_reg_write,
 +    .impl.min_access_size = 4,
 +    .impl.max_access_size = 4,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +};
 +
 +static void mphi_reset(DeviceState *dev)
 +{
 +    BCM2835MphiState *s = BCM2835_MPHI(dev);
 +
 +    s->outdda = 0;
 +    s->outddb = 0;
 +    s->ctrl = 0;
 +    s->intstat = 0;
 +    s->swirq = 0;
 +}
 +
 +static void mphi_realize(DeviceState *dev, Error **errp)
 +{
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 +    BCM2835MphiState *s = BCM2835_MPHI(dev);
 +
 +    sysbus_init_irq(sbd, &s->irq);
 +}
 +
 +static void mphi_init(Object *obj)
 +{
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 +    BCM2835MphiState *s = BCM2835_MPHI(obj);
 +
 +    memory_region_init_io(&s->iomem, obj, &mphi_mmio_ops, s, "mphi", MPHI_MMIO_SIZE);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +}
 +
 +const VMStateDescription vmstate_mphi_state = {
 +    .name = "mphi",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32(outdda, BCM2835MphiState),
 +        VMSTATE_UINT32(outddb, BCM2835MphiState),
 +        VMSTATE_UINT32(ctrl, BCM2835MphiState),
 +        VMSTATE_UINT32(intstat, BCM2835MphiState),
 +        VMSTATE_UINT32(swirq, BCM2835MphiState),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static void mphi_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->realize = mphi_realize;
 +    dc->reset = mphi_reset;
 +    dc->vmsd = &vmstate_mphi_state;
 +}
 +
 +static const TypeInfo bcm2835_mphi_type_info = {
 +    .name          = TYPE_BCM2835_MPHI,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(BCM2835MphiState),
 +    .instance_init = mphi_init,
 +    .class_init    = mphi_class_init,
 +};
 +
 +static void bcm2835_mphi_register_types(void)
 +{
 +    type_register_static(&bcm2835_mphi_type_info);
 +}
 +
 +type_init(bcm2835_mphi_register_types)
 diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/Makefile.objs
 +++ b/hw/misc/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_OMAP) += omap_l4.o
  common-obj-$(CONFIG_OMAP) += omap_sdrc.o
  common-obj-$(CONFIG_OMAP) += omap_tap.o
  common-obj-$(CONFIG_RASPI) += bcm2835_mbox.o
 +common-obj-$(CONFIG_RASPI) += bcm2835_mphi.o
  common-obj-$(CONFIG_RASPI) += bcm2835_property.o
  common-obj-$(CONFIG_RASPI) += bcm2835_rng.o
  common-obj-$(CONFIG_RASPI) += bcm2835_thermal.o
 --
 .20.1

-[PULL 33/42] hw/arm/mps2: Add CMSDK APB watchdog device
+[PULL 15/29] dwc-hsotg (dwc2) USB host controller register definitions
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Paul Zimmerman <pauldzim@gmail.com>
-We already model the CMSDK APB watchdog device, let's use it!
+Import the dwc-hsotg (dwc2) register definitions file from the
 Linux kernel. This is a copy of drivers/usb/dwc2/hw.h from the
 mainline Linux kernel, the only changes being to the header, and
 two instances of 'u32' changed to 'uint32_t' to allow it to
 compile. Checkpatch throws a boatload of errors due to the tab
 indentation, but I would rather import it as-is than reformat it.
-Suggested-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20200520235349.21215-3-pauldzim@gmail.com
 Message-id: 20200617072539.32686-9-f4bug@amsat.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/mps2.c  | 7 +++++++
+ include/hw/usb/dwc2-regs.h | 899 +++++++++++++++++++++++++++++++++++++
- hw/arm/Kconfig | 1 +
+file changed, 899 insertions(+)
-files changed, 8 insertions(+)
+ create mode 100644 include/hw/usb/dwc2-regs.h
-diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
+diff --git a/include/hw/usb/dwc2-regs.h b/include/hw/usb/dwc2-regs.h
-index XXXXXXX..XXXXXXX 100644
+new file mode 100644
---- a/hw/arm/mps2.c
+index XXXXXXX..XXXXXXX
-+++ b/hw/arm/mps2.c
+--- /dev/null
-@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
++++ b/include/hw/usb/dwc2-regs.h
-     sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
+@@ -XXX,XX +XXX,XX @@
-                        qdev_get_gpio_in(armv7m, 10));
++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-     sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
++/*
-+    object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
++ * Imported from the Linux kernel file drivers/usb/dwc2/hw.h, commit
-+                            TYPE_CMSDK_APB_WATCHDOG);
++ * a89bae709b3492b478480a2c9734e7e9393b279c ("usb: dwc2: Move
-+    qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ);
++ * UTMI_PHY_DATA defines closer")
-+    sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
++ *
-+    sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
++ * hw.h - DesignWare HS OTG Controller hardware definitions
-+                       qdev_get_gpio_in_named(armv7m, "NMI", 0));
++ *
-+    sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0x40008000);
++ * Copyright 2004-2013 Synopsys, Inc.
++ *
-     /* FPGA APB subsystem */
++ * Redistribution and use in source and binary forms, with or without
-     object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
++ * modification, are permitted provided that the following conditions
-diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
++ * are met:
-index XXXXXXX..XXXXXXX 100644
++ * 1. Redistributions of source code must retain the above copyright
---- a/hw/arm/Kconfig
++ *    notice, this list of conditions, and the following disclaimer,
-+++ b/hw/arm/Kconfig
++ *    without modification.
-@@ -XXX,XX +XXX,XX @@ config MPS2
++ * 2. Redistributions in binary form must reproduce the above copyright
-     select PL080    # DMA controller
++ *    notice, this list of conditions and the following disclaimer in the
-     select SPLIT_IRQ
++ *    documentation and/or other materials provided with the distribution.
-     select UNIMP
++ * 3. The names of the above-listed copyright holders may not be used
-+    select CMSDK_APB_WATCHDOG
++ *    to endorse or promote products derived from this software without
++ *    specific prior written permission.
- config FSL_IMX7
++ *
-     bool
++ * ALTERNATIVELY, this software may be distributed under the terms of the
 + * GNU General Public License ("GPL") as published by the Free Software
 + * Foundation; either version 2 of the License, or (at your option) any
 + * later version.
 + *
 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 + */
 +
 +#ifndef __DWC2_HW_H__
 +#define __DWC2_HW_H__
 +
 +#define HSOTG_REG(x)    (x)
 +
 +#define GOTGCTL                HSOTG_REG(0x000)
 +#define GOTGCTL_CHIRPEN            BIT(27)
 +#define GOTGCTL_MULT_VALID_BC_MASK    (0x1f << 22)
 +#define GOTGCTL_MULT_VALID_BC_SHIFT    22
 +#define GOTGCTL_OTGVER            BIT(20)
 +#define GOTGCTL_BSESVLD            BIT(19)
 +#define GOTGCTL_ASESVLD            BIT(18)
 +#define GOTGCTL_DBNC_SHORT        BIT(17)
 +#define GOTGCTL_CONID_B            BIT(16)
 +#define GOTGCTL_DBNCE_FLTR_BYPASS    BIT(15)
 +#define GOTGCTL_DEVHNPEN        BIT(11)
 +#define GOTGCTL_HSTSETHNPEN        BIT(10)
 +#define GOTGCTL_HNPREQ            BIT(9)
 +#define GOTGCTL_HSTNEGSCS        BIT(8)
 +#define GOTGCTL_SESREQ            BIT(1)
 +#define GOTGCTL_SESREQSCS        BIT(0)
 +
 +#define GOTGINT                HSOTG_REG(0x004)
 +#define GOTGINT_DBNCE_DONE        BIT(19)
 +#define GOTGINT_A_DEV_TOUT_CHG        BIT(18)
 +#define GOTGINT_HST_NEG_DET        BIT(17)
 +#define GOTGINT_HST_NEG_SUC_STS_CHNG    BIT(9)
 +#define GOTGINT_SES_REQ_SUC_STS_CHNG    BIT(8)
 +#define GOTGINT_SES_END_DET        BIT(2)
 +
 +#define GAHBCFG                HSOTG_REG(0x008)
 +#define GAHBCFG_AHB_SINGLE        BIT(23)
 +#define GAHBCFG_NOTI_ALL_DMA_WRIT    BIT(22)
 +#define GAHBCFG_REM_MEM_SUPP        BIT(21)
 +#define GAHBCFG_P_TXF_EMP_LVL        BIT(8)
 +#define GAHBCFG_NP_TXF_EMP_LVL        BIT(7)
 +#define GAHBCFG_DMA_EN            BIT(5)
 +#define GAHBCFG_HBSTLEN_MASK        (0xf << 1)
 +#define GAHBCFG_HBSTLEN_SHIFT        1
 +#define GAHBCFG_HBSTLEN_SINGLE        0
 +#define GAHBCFG_HBSTLEN_INCR        1
 +#define GAHBCFG_HBSTLEN_INCR4        3
 +#define GAHBCFG_HBSTLEN_INCR8        5
 +#define GAHBCFG_HBSTLEN_INCR16        7
 +#define GAHBCFG_GLBL_INTR_EN        BIT(0)
 +#define GAHBCFG_CTRL_MASK        (GAHBCFG_P_TXF_EMP_LVL | \
 +                     GAHBCFG_NP_TXF_EMP_LVL | \
 +                     GAHBCFG_DMA_EN | \
 +                     GAHBCFG_GLBL_INTR_EN)
 +
 +#define GUSBCFG                HSOTG_REG(0x00C)
 +#define GUSBCFG_FORCEDEVMODE        BIT(30)
 +#define GUSBCFG_FORCEHOSTMODE        BIT(29)
 +#define GUSBCFG_TXENDDELAY        BIT(28)
 +#define GUSBCFG_ICTRAFFICPULLREMOVE    BIT(27)
 +#define GUSBCFG_ICUSBCAP        BIT(26)
 +#define GUSBCFG_ULPI_INT_PROT_DIS    BIT(25)
 +#define GUSBCFG_INDICATORPASSTHROUGH    BIT(24)
 +#define GUSBCFG_INDICATORCOMPLEMENT    BIT(23)
 +#define GUSBCFG_TERMSELDLPULSE        BIT(22)
 +#define GUSBCFG_ULPI_INT_VBUS_IND    BIT(21)
 +#define GUSBCFG_ULPI_EXT_VBUS_DRV    BIT(20)
 +#define GUSBCFG_ULPI_CLK_SUSP_M        BIT(19)
 +#define GUSBCFG_ULPI_AUTO_RES        BIT(18)
 +#define GUSBCFG_ULPI_FS_LS        BIT(17)
 +#define GUSBCFG_OTG_UTMI_FS_SEL        BIT(16)
 +#define GUSBCFG_PHY_LP_CLK_SEL        BIT(15)
 +#define GUSBCFG_USBTRDTIM_MASK        (0xf << 10)
 +#define GUSBCFG_USBTRDTIM_SHIFT        10
 +#define GUSBCFG_HNPCAP            BIT(9)
 +#define GUSBCFG_SRPCAP            BIT(8)
 +#define GUSBCFG_DDRSEL            BIT(7)
 +#define GUSBCFG_PHYSEL            BIT(6)
 +#define GUSBCFG_FSINTF            BIT(5)
 +#define GUSBCFG_ULPI_UTMI_SEL        BIT(4)
 +#define GUSBCFG_PHYIF16            BIT(3)
 +#define GUSBCFG_PHYIF8            (0 << 3)
 +#define GUSBCFG_TOUTCAL_MASK        (0x7 << 0)
 +#define GUSBCFG_TOUTCAL_SHIFT        0
 +#define GUSBCFG_TOUTCAL_LIMIT        0x7
 +#define GUSBCFG_TOUTCAL(_x)        ((_x) << 0)
 +
 +#define GRSTCTL                HSOTG_REG(0x010)
 +#define GRSTCTL_AHBIDLE            BIT(31)
 +#define GRSTCTL_DMAREQ            BIT(30)
 +#define GRSTCTL_TXFNUM_MASK        (0x1f << 6)
 +#define GRSTCTL_TXFNUM_SHIFT        6
 +#define GRSTCTL_TXFNUM_LIMIT        0x1f
 +#define GRSTCTL_TXFNUM(_x)        ((_x) << 6)
 +#define GRSTCTL_TXFFLSH            BIT(5)
 +#define GRSTCTL_RXFFLSH            BIT(4)
 +#define GRSTCTL_IN_TKNQ_FLSH        BIT(3)
 +#define GRSTCTL_FRMCNTRRST        BIT(2)
 +#define GRSTCTL_HSFTRST            BIT(1)
 +#define GRSTCTL_CSFTRST            BIT(0)
 +
 +#define GINTSTS                HSOTG_REG(0x014)
 +#define GINTMSK                HSOTG_REG(0x018)
 +#define GINTSTS_WKUPINT            BIT(31)
 +#define GINTSTS_SESSREQINT        BIT(30)
 +#define GINTSTS_DISCONNINT        BIT(29)
 +#define GINTSTS_CONIDSTSCHNG        BIT(28)
 +#define GINTSTS_LPMTRANRCVD        BIT(27)
 +#define GINTSTS_PTXFEMP            BIT(26)
 +#define GINTSTS_HCHINT            BIT(25)
 +#define GINTSTS_PRTINT            BIT(24)
 +#define GINTSTS_RESETDET        BIT(23)
 +#define GINTSTS_FET_SUSP        BIT(22)
 +#define GINTSTS_INCOMPL_IP        BIT(21)
 +#define GINTSTS_INCOMPL_SOOUT        BIT(21)
 +#define GINTSTS_INCOMPL_SOIN        BIT(20)
 +#define GINTSTS_OEPINT            BIT(19)
 +#define GINTSTS_IEPINT            BIT(18)
 +#define GINTSTS_EPMIS            BIT(17)
 +#define GINTSTS_RESTOREDONE        BIT(16)
 +#define GINTSTS_EOPF            BIT(15)
 +#define GINTSTS_ISOUTDROP        BIT(14)
 +#define GINTSTS_ENUMDONE        BIT(13)
 +#define GINTSTS_USBRST            BIT(12)
 +#define GINTSTS_USBSUSP            BIT(11)
 +#define GINTSTS_ERLYSUSP        BIT(10)
 +#define GINTSTS_I2CINT            BIT(9)
 +#define GINTSTS_ULPI_CK_INT        BIT(8)
 +#define GINTSTS_GOUTNAKEFF        BIT(7)
 +#define GINTSTS_GINNAKEFF        BIT(6)
 +#define GINTSTS_NPTXFEMP        BIT(5)
 +#define GINTSTS_RXFLVL            BIT(4)
 +#define GINTSTS_SOF            BIT(3)
 +#define GINTSTS_OTGINT            BIT(2)
 +#define GINTSTS_MODEMIS            BIT(1)
 +#define GINTSTS_CURMODE_HOST        BIT(0)
 +
 +#define GRXSTSR                HSOTG_REG(0x01C)
 +#define GRXSTSP                HSOTG_REG(0x020)
 +#define GRXSTS_FN_MASK            (0x7f << 25)
 +#define GRXSTS_FN_SHIFT            25
 +#define GRXSTS_PKTSTS_MASK        (0xf << 17)
 +#define GRXSTS_PKTSTS_SHIFT        17
 +#define GRXSTS_PKTSTS_GLOBALOUTNAK    1
 +#define GRXSTS_PKTSTS_OUTRX        2
 +#define GRXSTS_PKTSTS_HCHIN        2
 +#define GRXSTS_PKTSTS_OUTDONE        3
 +#define GRXSTS_PKTSTS_HCHIN_XFER_COMP    3
 +#define GRXSTS_PKTSTS_SETUPDONE        4
 +#define GRXSTS_PKTSTS_DATATOGGLEERR    5
 +#define GRXSTS_PKTSTS_SETUPRX        6
 +#define GRXSTS_PKTSTS_HCHHALTED        7
 +#define GRXSTS_HCHNUM_MASK        (0xf << 0)
 +#define GRXSTS_HCHNUM_SHIFT        0
 +#define GRXSTS_DPID_MASK        (0x3 << 15)
 +#define GRXSTS_DPID_SHIFT        15
 +#define GRXSTS_BYTECNT_MASK        (0x7ff << 4)
 +#define GRXSTS_BYTECNT_SHIFT        4
 +#define GRXSTS_EPNUM_MASK        (0xf << 0)
 +#define GRXSTS_EPNUM_SHIFT        0
 +
 +#define GRXFSIZ                HSOTG_REG(0x024)
 +#define GRXFSIZ_DEPTH_MASK        (0xffff << 0)
 +#define GRXFSIZ_DEPTH_SHIFT        0
 +
 +#define GNPTXFSIZ            HSOTG_REG(0x028)
 +/* Use FIFOSIZE_* constants to access this register */
 +
 +#define GNPTXSTS            HSOTG_REG(0x02C)
 +#define GNPTXSTS_NP_TXQ_TOP_MASK        (0x7f << 24)
 +#define GNPTXSTS_NP_TXQ_TOP_SHIFT        24
 +#define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK        (0xff << 16)
 +#define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT        16
 +#define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v)    (((_v) >> 16) & 0xff)
 +#define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK        (0xffff << 0)
 +#define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT        0
 +#define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v)    (((_v) >> 0) & 0xffff)
 +
 +#define GI2CCTL                HSOTG_REG(0x0030)
 +#define GI2CCTL_BSYDNE            BIT(31)
 +#define GI2CCTL_RW            BIT(30)
 +#define GI2CCTL_I2CDATSE0        BIT(28)
 +#define GI2CCTL_I2CDEVADDR_MASK        (0x3 << 26)
 +#define GI2CCTL_I2CDEVADDR_SHIFT    26
 +#define GI2CCTL_I2CSUSPCTL        BIT(25)
 +#define GI2CCTL_ACK            BIT(24)
 +#define GI2CCTL_I2CEN            BIT(23)
 +#define GI2CCTL_ADDR_MASK        (0x7f << 16)
 +#define GI2CCTL_ADDR_SHIFT        16
 +#define GI2CCTL_REGADDR_MASK        (0xff << 8)
 +#define GI2CCTL_REGADDR_SHIFT        8
 +#define GI2CCTL_RWDATA_MASK        (0xff << 0)
 +#define GI2CCTL_RWDATA_SHIFT        0
 +
 +#define GPVNDCTL            HSOTG_REG(0x0034)
 +#define GGPIO                HSOTG_REG(0x0038)
 +#define GGPIO_STM32_OTG_GCCFG_PWRDWN    BIT(16)
 +
 +#define GUID                HSOTG_REG(0x003c)
 +#define GSNPSID                HSOTG_REG(0x0040)
 +#define GHWCFG1                HSOTG_REG(0x0044)
 +#define GSNPSID_ID_MASK            GENMASK(31, 16)
 +
 +#define GHWCFG2                HSOTG_REG(0x0048)
 +#define GHWCFG2_OTG_ENABLE_IC_USB        BIT(31)
 +#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK        (0x1f << 26)
 +#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT        26
 +#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK    (0x3 << 24)
 +#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT    24
 +#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK    (0x3 << 22)
 +#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT    22
 +#define GHWCFG2_MULTI_PROC_INT            BIT(20)
 +#define GHWCFG2_DYNAMIC_FIFO            BIT(19)
 +#define GHWCFG2_PERIO_EP_SUPPORTED        BIT(18)
 +#define GHWCFG2_NUM_HOST_CHAN_MASK        (0xf << 14)
 +#define GHWCFG2_NUM_HOST_CHAN_SHIFT        14
 +#define GHWCFG2_NUM_DEV_EP_MASK            (0xf << 10)
 +#define GHWCFG2_NUM_DEV_EP_SHIFT        10
 +#define GHWCFG2_FS_PHY_TYPE_MASK        (0x3 << 8)
 +#define GHWCFG2_FS_PHY_TYPE_SHIFT        8
 +#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED    0
 +#define GHWCFG2_FS_PHY_TYPE_DEDICATED        1
 +#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI        2
 +#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI        3
 +#define GHWCFG2_HS_PHY_TYPE_MASK        (0x3 << 6)
 +#define GHWCFG2_HS_PHY_TYPE_SHIFT        6
 +#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED    0
 +#define GHWCFG2_HS_PHY_TYPE_UTMI        1
 +#define GHWCFG2_HS_PHY_TYPE_ULPI        2
 +#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI        3
 +#define GHWCFG2_POINT2POINT            BIT(5)
 +#define GHWCFG2_ARCHITECTURE_MASK        (0x3 << 3)
 +#define GHWCFG2_ARCHITECTURE_SHIFT        3
 +#define GHWCFG2_SLAVE_ONLY_ARCH            0
 +#define GHWCFG2_EXT_DMA_ARCH            1
 +#define GHWCFG2_INT_DMA_ARCH            2
 +#define GHWCFG2_OP_MODE_MASK            (0x7 << 0)
 +#define GHWCFG2_OP_MODE_SHIFT            0
 +#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE        0
 +#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE    1
 +#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE    2
 +#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE    3
 +#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE    4
 +#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST    5
 +#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST    6
 +#define GHWCFG2_OP_MODE_UNDEFINED        7
 +
 +#define GHWCFG3                HSOTG_REG(0x004c)
 +#define GHWCFG3_DFIFO_DEPTH_MASK        (0xffff << 16)
 +#define GHWCFG3_DFIFO_DEPTH_SHIFT        16
 +#define GHWCFG3_OTG_LPM_EN            BIT(15)
 +#define GHWCFG3_BC_SUPPORT            BIT(14)
 +#define GHWCFG3_OTG_ENABLE_HSIC            BIT(13)
 +#define GHWCFG3_ADP_SUPP            BIT(12)
 +#define GHWCFG3_SYNCH_RESET_TYPE        BIT(11)
 +#define GHWCFG3_OPTIONAL_FEATURES        BIT(10)
 +#define GHWCFG3_VENDOR_CTRL_IF            BIT(9)
 +#define GHWCFG3_I2C                BIT(8)
 +#define GHWCFG3_OTG_FUNC            BIT(7)
 +#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK    (0x7 << 4)
 +#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT    4
 +#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK    (0xf << 0)
 +#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT    0
 +
 +#define GHWCFG4                HSOTG_REG(0x0050)
 +#define GHWCFG4_DESC_DMA_DYN            BIT(31)
 +#define GHWCFG4_DESC_DMA            BIT(30)
 +#define GHWCFG4_NUM_IN_EPS_MASK            (0xf << 26)
 +#define GHWCFG4_NUM_IN_EPS_SHIFT        26
 +#define GHWCFG4_DED_FIFO_EN            BIT(25)
 +#define GHWCFG4_DED_FIFO_SHIFT        25
 +#define GHWCFG4_SESSION_END_FILT_EN        BIT(24)
 +#define GHWCFG4_B_VALID_FILT_EN            BIT(23)
 +#define GHWCFG4_A_VALID_FILT_EN            BIT(22)
 +#define GHWCFG4_VBUS_VALID_FILT_EN        BIT(21)
 +#define GHWCFG4_IDDIG_FILT_EN            BIT(20)
 +#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK    (0xf << 16)
 +#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT    16
 +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK    (0x3 << 14)
 +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT    14
 +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8        0
 +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16        1
 +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16    2
 +#define GHWCFG4_ACG_SUPPORTED            BIT(12)
 +#define GHWCFG4_IPG_ISOC_SUPPORTED        BIT(11)
 +#define GHWCFG4_SERVICE_INTERVAL_SUPPORTED      BIT(10)
 +#define GHWCFG4_XHIBER                BIT(7)
 +#define GHWCFG4_HIBER                BIT(6)
 +#define GHWCFG4_MIN_AHB_FREQ            BIT(5)
 +#define GHWCFG4_POWER_OPTIMIZ            BIT(4)
 +#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK    (0xf << 0)
 +#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT    0
 +
 +#define GLPMCFG                HSOTG_REG(0x0054)
 +#define GLPMCFG_INVSELHSIC        BIT(31)
 +#define GLPMCFG_HSICCON            BIT(30)
 +#define GLPMCFG_RSTRSLPSTS        BIT(29)
 +#define GLPMCFG_ENBESL            BIT(28)
 +#define GLPMCFG_LPM_RETRYCNT_STS_MASK    (0x7 << 25)
 +#define GLPMCFG_LPM_RETRYCNT_STS_SHIFT    25
 +#define GLPMCFG_SNDLPM            BIT(24)
 +#define GLPMCFG_RETRY_CNT_MASK        (0x7 << 21)
 +#define GLPMCFG_RETRY_CNT_SHIFT        21
 +#define GLPMCFG_LPM_REJECT_CTRL_CONTROL    BIT(21)
 +#define GLPMCFG_LPM_ACCEPT_CTRL_ISOC    BIT(22)
 +#define GLPMCFG_LPM_CHNL_INDX_MASK    (0xf << 17)
 +#define GLPMCFG_LPM_CHNL_INDX_SHIFT    17
 +#define GLPMCFG_L1RESUMEOK        BIT(16)
 +#define GLPMCFG_SLPSTS            BIT(15)
 +#define GLPMCFG_COREL1RES_MASK        (0x3 << 13)
 +#define GLPMCFG_COREL1RES_SHIFT        13
 +#define GLPMCFG_HIRD_THRES_MASK        (0x1f << 8)
 +#define GLPMCFG_HIRD_THRES_SHIFT    8
 +#define GLPMCFG_HIRD_THRES_EN        (0x10 << 8)
 +#define GLPMCFG_ENBLSLPM        BIT(7)
 +#define GLPMCFG_BREMOTEWAKE        BIT(6)
 +#define GLPMCFG_HIRD_MASK        (0xf << 2)
 +#define GLPMCFG_HIRD_SHIFT        2
 +#define GLPMCFG_APPL1RES        BIT(1)
 +#define GLPMCFG_LPMCAP            BIT(0)
 +
 +#define GPWRDN                HSOTG_REG(0x0058)
 +#define GPWRDN_MULT_VAL_ID_BC_MASK    (0x1f << 24)
 +#define GPWRDN_MULT_VAL_ID_BC_SHIFT    24
 +#define GPWRDN_ADP_INT            BIT(23)
 +#define GPWRDN_BSESSVLD            BIT(22)
 +#define GPWRDN_IDSTS            BIT(21)
 +#define GPWRDN_LINESTATE_MASK        (0x3 << 19)
 +#define GPWRDN_LINESTATE_SHIFT        19
 +#define GPWRDN_STS_CHGINT_MSK        BIT(18)
 +#define GPWRDN_STS_CHGINT        BIT(17)
 +#define GPWRDN_SRP_DET_MSK        BIT(16)
 +#define GPWRDN_SRP_DET            BIT(15)
 +#define GPWRDN_CONNECT_DET_MSK        BIT(14)
 +#define GPWRDN_CONNECT_DET        BIT(13)
 +#define GPWRDN_DISCONN_DET_MSK        BIT(12)
 +#define GPWRDN_DISCONN_DET        BIT(11)
 +#define GPWRDN_RST_DET_MSK        BIT(10)
 +#define GPWRDN_RST_DET            BIT(9)
 +#define GPWRDN_LNSTSCHG_MSK        BIT(8)
 +#define GPWRDN_LNSTSCHG            BIT(7)
 +#define GPWRDN_DIS_VBUS            BIT(6)
 +#define GPWRDN_PWRDNSWTCH        BIT(5)
 +#define GPWRDN_PWRDNRSTN        BIT(4)
 +#define GPWRDN_PWRDNCLMP        BIT(3)
 +#define GPWRDN_RESTORE            BIT(2)
 +#define GPWRDN_PMUACTV            BIT(1)
 +#define GPWRDN_PMUINTSEL        BIT(0)
 +
 +#define GDFIFOCFG            HSOTG_REG(0x005c)
 +#define GDFIFOCFG_EPINFOBASE_MASK    (0xffff << 16)
 +#define GDFIFOCFG_EPINFOBASE_SHIFT    16
 +#define GDFIFOCFG_GDFIFOCFG_MASK    (0xffff << 0)
 +#define GDFIFOCFG_GDFIFOCFG_SHIFT    0
 +
 +#define ADPCTL                HSOTG_REG(0x0060)
 +#define ADPCTL_AR_MASK            (0x3 << 27)
 +#define ADPCTL_AR_SHIFT            27
 +#define ADPCTL_ADP_TMOUT_INT_MSK    BIT(26)
 +#define ADPCTL_ADP_SNS_INT_MSK        BIT(25)
 +#define ADPCTL_ADP_PRB_INT_MSK        BIT(24)
 +#define ADPCTL_ADP_TMOUT_INT        BIT(23)
 +#define ADPCTL_ADP_SNS_INT        BIT(22)
 +#define ADPCTL_ADP_PRB_INT        BIT(21)
 +#define ADPCTL_ADPENA            BIT(20)
 +#define ADPCTL_ADPRES            BIT(19)
 +#define ADPCTL_ENASNS            BIT(18)
 +#define ADPCTL_ENAPRB            BIT(17)
 +#define ADPCTL_RTIM_MASK        (0x7ff << 6)
 +#define ADPCTL_RTIM_SHIFT        6
 +#define ADPCTL_PRB_PER_MASK        (0x3 << 4)
 +#define ADPCTL_PRB_PER_SHIFT        4
 +#define ADPCTL_PRB_DELTA_MASK        (0x3 << 2)
 +#define ADPCTL_PRB_DELTA_SHIFT        2
 +#define ADPCTL_PRB_DSCHRG_MASK        (0x3 << 0)
 +#define ADPCTL_PRB_DSCHRG_SHIFT        0
 +
 +#define GREFCLK                    HSOTG_REG(0x0064)
 +#define GREFCLK_REFCLKPER_MASK            (0x1ffff << 15)
 +#define GREFCLK_REFCLKPER_SHIFT            15
 +#define GREFCLK_REF_CLK_MODE            BIT(14)
 +#define GREFCLK_SOF_CNT_WKUP_ALERT_MASK        (0x3ff)
 +#define GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT    0
 +
 +#define GINTMSK2            HSOTG_REG(0x0068)
 +#define GINTMSK2_WKUP_ALERT_INT_MSK    BIT(0)
 +
 +#define GINTSTS2            HSOTG_REG(0x006c)
 +#define GINTSTS2_WKUP_ALERT_INT        BIT(0)
 +
 +#define HPTXFSIZ            HSOTG_REG(0x100)
 +/* Use FIFOSIZE_* constants to access this register */
 +
 +#define DPTXFSIZN(_a)            HSOTG_REG(0x104 + (((_a) - 1) * 4))
 +/* Use FIFOSIZE_* constants to access this register */
 +
 +/* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
 +#define FIFOSIZE_DEPTH_MASK        (0xffff << 16)
 +#define FIFOSIZE_DEPTH_SHIFT        16
 +#define FIFOSIZE_STARTADDR_MASK        (0xffff << 0)
 +#define FIFOSIZE_STARTADDR_SHIFT    0
 +#define FIFOSIZE_DEPTH_GET(_x)        (((_x) >> 16) & 0xffff)
 +
 +/* Device mode registers */
 +
 +#define DCFG                HSOTG_REG(0x800)
 +#define DCFG_DESCDMA_EN            BIT(23)
 +#define DCFG_EPMISCNT_MASK        (0x1f << 18)
 +#define DCFG_EPMISCNT_SHIFT        18
 +#define DCFG_EPMISCNT_LIMIT        0x1f
 +#define DCFG_EPMISCNT(_x)        ((_x) << 18)
 +#define DCFG_IPG_ISOC_SUPPORDED        BIT(17)
 +#define DCFG_PERFRINT_MASK        (0x3 << 11)
 +#define DCFG_PERFRINT_SHIFT        11
 +#define DCFG_PERFRINT_LIMIT        0x3
 +#define DCFG_PERFRINT(_x)        ((_x) << 11)
 +#define DCFG_DEVADDR_MASK        (0x7f << 4)
 +#define DCFG_DEVADDR_SHIFT        4
 +#define DCFG_DEVADDR_LIMIT        0x7f
 +#define DCFG_DEVADDR(_x)        ((_x) << 4)
 +#define DCFG_NZ_STS_OUT_HSHK        BIT(2)
 +#define DCFG_DEVSPD_MASK        (0x3 << 0)
 +#define DCFG_DEVSPD_SHIFT        0
 +#define DCFG_DEVSPD_HS            0
 +#define DCFG_DEVSPD_FS            1
 +#define DCFG_DEVSPD_LS            2
 +#define DCFG_DEVSPD_FS48        3
 +
 +#define DCTL                HSOTG_REG(0x804)
 +#define DCTL_SERVICE_INTERVAL_SUPPORTED BIT(19)
 +#define DCTL_PWRONPRGDONE        BIT(11)
 +#define DCTL_CGOUTNAK            BIT(10)
 +#define DCTL_SGOUTNAK            BIT(9)
 +#define DCTL_CGNPINNAK            BIT(8)
 +#define DCTL_SGNPINNAK            BIT(7)
 +#define DCTL_TSTCTL_MASK        (0x7 << 4)
 +#define DCTL_TSTCTL_SHIFT        4
 +#define DCTL_GOUTNAKSTS            BIT(3)
 +#define DCTL_GNPINNAKSTS        BIT(2)
 +#define DCTL_SFTDISCON            BIT(1)
 +#define DCTL_RMTWKUPSIG            BIT(0)
 +
 +#define DSTS                HSOTG_REG(0x808)
 +#define DSTS_SOFFN_MASK            (0x3fff << 8)
 +#define DSTS_SOFFN_SHIFT        8
 +#define DSTS_SOFFN_LIMIT        0x3fff
 +#define DSTS_SOFFN(_x)            ((_x) << 8)
 +#define DSTS_ERRATICERR            BIT(3)
 +#define DSTS_ENUMSPD_MASK        (0x3 << 1)
 +#define DSTS_ENUMSPD_SHIFT        1
 +#define DSTS_ENUMSPD_HS            0
 +#define DSTS_ENUMSPD_FS            1
 +#define DSTS_ENUMSPD_LS            2
 +#define DSTS_ENUMSPD_FS48        3
 +#define DSTS_SUSPSTS            BIT(0)
 +
 +#define DIEPMSK                HSOTG_REG(0x810)
 +#define DIEPMSK_NAKMSK            BIT(13)
 +#define DIEPMSK_BNAININTRMSK        BIT(9)
 +#define DIEPMSK_TXFIFOUNDRNMSK        BIT(8)
 +#define DIEPMSK_TXFIFOEMPTY        BIT(7)
 +#define DIEPMSK_INEPNAKEFFMSK        BIT(6)
 +#define DIEPMSK_INTKNEPMISMSK        BIT(5)
 +#define DIEPMSK_INTKNTXFEMPMSK        BIT(4)
 +#define DIEPMSK_TIMEOUTMSK        BIT(3)
 +#define DIEPMSK_AHBERRMSK        BIT(2)
 +#define DIEPMSK_EPDISBLDMSK        BIT(1)
 +#define DIEPMSK_XFERCOMPLMSK        BIT(0)
 +
 +#define DOEPMSK                HSOTG_REG(0x814)
 +#define DOEPMSK_BNAMSK            BIT(9)
 +#define DOEPMSK_BACK2BACKSETUP        BIT(6)
 +#define DOEPMSK_STSPHSERCVDMSK        BIT(5)
 +#define DOEPMSK_OUTTKNEPDISMSK        BIT(4)
 +#define DOEPMSK_SETUPMSK        BIT(3)
 +#define DOEPMSK_AHBERRMSK        BIT(2)
 +#define DOEPMSK_EPDISBLDMSK        BIT(1)
 +#define DOEPMSK_XFERCOMPLMSK        BIT(0)
 +
 +#define DAINT                HSOTG_REG(0x818)
 +#define DAINTMSK            HSOTG_REG(0x81C)
 +#define DAINT_OUTEP_SHIFT        16
 +#define DAINT_OUTEP(_x)            (1 << ((_x) + 16))
 +#define DAINT_INEP(_x)            (1 << (_x))
 +
 +#define DTKNQR1                HSOTG_REG(0x820)
 +#define DTKNQR2                HSOTG_REG(0x824)
 +#define DTKNQR3                HSOTG_REG(0x830)
 +#define DTKNQR4                HSOTG_REG(0x834)
 +#define DIEPEMPMSK            HSOTG_REG(0x834)
 +
 +#define DVBUSDIS            HSOTG_REG(0x828)
 +#define DVBUSPULSE            HSOTG_REG(0x82C)
 +
 +#define DIEPCTL0            HSOTG_REG(0x900)
 +#define DIEPCTL(_a)            HSOTG_REG(0x900 + ((_a) * 0x20))
 +
 +#define DOEPCTL0            HSOTG_REG(0xB00)
 +#define DOEPCTL(_a)            HSOTG_REG(0xB00 + ((_a) * 0x20))
 +
 +/* EP0 specialness:
 + * bits[29..28] - reserved (no SetD0PID, SetD1PID)
 + * bits[25..22] - should always be zero, this isn't a periodic endpoint
 + * bits[10..0]  - MPS setting different for EP0
 + */
 +#define D0EPCTL_MPS_MASK        (0x3 << 0)
 +#define D0EPCTL_MPS_SHIFT        0
 +#define D0EPCTL_MPS_64            0
 +#define D0EPCTL_MPS_32            1
 +#define D0EPCTL_MPS_16            2
 +#define D0EPCTL_MPS_8            3
 +
 +#define DXEPCTL_EPENA            BIT(31)
 +#define DXEPCTL_EPDIS            BIT(30)
 +#define DXEPCTL_SETD1PID        BIT(29)
 +#define DXEPCTL_SETODDFR        BIT(29)
 +#define DXEPCTL_SETD0PID        BIT(28)
 +#define DXEPCTL_SETEVENFR        BIT(28)
 +#define DXEPCTL_SNAK            BIT(27)
 +#define DXEPCTL_CNAK            BIT(26)
 +#define DXEPCTL_TXFNUM_MASK        (0xf << 22)
 +#define DXEPCTL_TXFNUM_SHIFT        22
 +#define DXEPCTL_TXFNUM_LIMIT        0xf
 +#define DXEPCTL_TXFNUM(_x)        ((_x) << 22)
 +#define DXEPCTL_STALL            BIT(21)
 +#define DXEPCTL_SNP            BIT(20)
 +#define DXEPCTL_EPTYPE_MASK        (0x3 << 18)
 +#define DXEPCTL_EPTYPE_CONTROL        (0x0 << 18)
 +#define DXEPCTL_EPTYPE_ISO        (0x1 << 18)
 +#define DXEPCTL_EPTYPE_BULK        (0x2 << 18)
 +#define DXEPCTL_EPTYPE_INTERRUPT    (0x3 << 18)
 +
 +#define DXEPCTL_NAKSTS            BIT(17)
 +#define DXEPCTL_DPID            BIT(16)
 +#define DXEPCTL_EOFRNUM            BIT(16)
 +#define DXEPCTL_USBACTEP        BIT(15)
 +#define DXEPCTL_NEXTEP_MASK        (0xf << 11)
 +#define DXEPCTL_NEXTEP_SHIFT        11
 +#define DXEPCTL_NEXTEP_LIMIT        0xf
 +#define DXEPCTL_NEXTEP(_x)        ((_x) << 11)
 +#define DXEPCTL_MPS_MASK        (0x7ff << 0)
 +#define DXEPCTL_MPS_SHIFT        0
 +#define DXEPCTL_MPS_LIMIT        0x7ff
 +#define DXEPCTL_MPS(_x)            ((_x) << 0)
 +
 +#define DIEPINT(_a)            HSOTG_REG(0x908 + ((_a) * 0x20))
 +#define DOEPINT(_a)            HSOTG_REG(0xB08 + ((_a) * 0x20))
 +#define DXEPINT_SETUP_RCVD        BIT(15)
 +#define DXEPINT_NYETINTRPT        BIT(14)
 +#define DXEPINT_NAKINTRPT        BIT(13)
 +#define DXEPINT_BBLEERRINTRPT        BIT(12)
 +#define DXEPINT_PKTDRPSTS        BIT(11)
 +#define DXEPINT_BNAINTR            BIT(9)
 +#define DXEPINT_TXFIFOUNDRN        BIT(8)
 +#define DXEPINT_OUTPKTERR        BIT(8)
 +#define DXEPINT_TXFEMP            BIT(7)
 +#define DXEPINT_INEPNAKEFF        BIT(6)
 +#define DXEPINT_BACK2BACKSETUP        BIT(6)
 +#define DXEPINT_INTKNEPMIS        BIT(5)
 +#define DXEPINT_STSPHSERCVD        BIT(5)
 +#define DXEPINT_INTKNTXFEMP        BIT(4)
 +#define DXEPINT_OUTTKNEPDIS        BIT(4)
 +#define DXEPINT_TIMEOUT            BIT(3)
 +#define DXEPINT_SETUP            BIT(3)
 +#define DXEPINT_AHBERR            BIT(2)
 +#define DXEPINT_EPDISBLD        BIT(1)
 +#define DXEPINT_XFERCOMPL        BIT(0)
 +
 +#define DIEPTSIZ0            HSOTG_REG(0x910)
 +#define DIEPTSIZ0_PKTCNT_MASK        (0x3 << 19)
 +#define DIEPTSIZ0_PKTCNT_SHIFT        19
 +#define DIEPTSIZ0_PKTCNT_LIMIT        0x3
 +#define DIEPTSIZ0_PKTCNT(_x)        ((_x) << 19)
 +#define DIEPTSIZ0_XFERSIZE_MASK        (0x7f << 0)
 +#define DIEPTSIZ0_XFERSIZE_SHIFT    0
 +#define DIEPTSIZ0_XFERSIZE_LIMIT    0x7f
 +#define DIEPTSIZ0_XFERSIZE(_x)        ((_x) << 0)
 +
 +#define DOEPTSIZ0            HSOTG_REG(0xB10)
 +#define DOEPTSIZ0_SUPCNT_MASK        (0x3 << 29)
 +#define DOEPTSIZ0_SUPCNT_SHIFT        29
 +#define DOEPTSIZ0_SUPCNT_LIMIT        0x3
 +#define DOEPTSIZ0_SUPCNT(_x)        ((_x) << 29)
 +#define DOEPTSIZ0_PKTCNT        BIT(19)
 +#define DOEPTSIZ0_XFERSIZE_MASK        (0x7f << 0)
 +#define DOEPTSIZ0_XFERSIZE_SHIFT    0
 +
 +#define DIEPTSIZ(_a)            HSOTG_REG(0x910 + ((_a) * 0x20))
 +#define DOEPTSIZ(_a)            HSOTG_REG(0xB10 + ((_a) * 0x20))
 +#define DXEPTSIZ_MC_MASK        (0x3 << 29)
 +#define DXEPTSIZ_MC_SHIFT        29
 +#define DXEPTSIZ_MC_LIMIT        0x3
 +#define DXEPTSIZ_MC(_x)            ((_x) << 29)
 +#define DXEPTSIZ_PKTCNT_MASK        (0x3ff << 19)
 +#define DXEPTSIZ_PKTCNT_SHIFT        19
 +#define DXEPTSIZ_PKTCNT_LIMIT        0x3ff
 +#define DXEPTSIZ_PKTCNT_GET(_v)        (((_v) >> 19) & 0x3ff)
 +#define DXEPTSIZ_PKTCNT(_x)        ((_x) << 19)
 +#define DXEPTSIZ_XFERSIZE_MASK        (0x7ffff << 0)
 +#define DXEPTSIZ_XFERSIZE_SHIFT        0
 +#define DXEPTSIZ_XFERSIZE_LIMIT        0x7ffff
 +#define DXEPTSIZ_XFERSIZE_GET(_v)    (((_v) >> 0) & 0x7ffff)
 +#define DXEPTSIZ_XFERSIZE(_x)        ((_x) << 0)
 +
 +#define DIEPDMA(_a)            HSOTG_REG(0x914 + ((_a) * 0x20))
 +#define DOEPDMA(_a)            HSOTG_REG(0xB14 + ((_a) * 0x20))
 +
 +#define DTXFSTS(_a)            HSOTG_REG(0x918 + ((_a) * 0x20))
 +
 +#define PCGCTL                HSOTG_REG(0x0e00)
 +#define PCGCTL_IF_DEV_MODE        BIT(31)
 +#define PCGCTL_P2HD_PRT_SPD_MASK    (0x3 << 29)
 +#define PCGCTL_P2HD_PRT_SPD_SHIFT    29
 +#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK    (0x3 << 27)
 +#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT    27
 +#define PCGCTL_MAC_DEV_ADDR_MASK    (0x7f << 20)
 +#define PCGCTL_MAC_DEV_ADDR_SHIFT    20
 +#define PCGCTL_MAX_TERMSEL        BIT(19)
 +#define PCGCTL_MAX_XCVRSELECT_MASK    (0x3 << 17)
 +#define PCGCTL_MAX_XCVRSELECT_SHIFT    17
 +#define PCGCTL_PORT_POWER        BIT(16)
 +#define PCGCTL_PRT_CLK_SEL_MASK        (0x3 << 14)
 +#define PCGCTL_PRT_CLK_SEL_SHIFT    14
 +#define PCGCTL_ESS_REG_RESTORED        BIT(13)
 +#define PCGCTL_EXTND_HIBER_SWITCH    BIT(12)
 +#define PCGCTL_EXTND_HIBER_PWRCLMP    BIT(11)
 +#define PCGCTL_ENBL_EXTND_HIBER        BIT(10)
 +#define PCGCTL_RESTOREMODE        BIT(9)
 +#define PCGCTL_RESETAFTSUSP        BIT(8)
 +#define PCGCTL_DEEP_SLEEP        BIT(7)
 +#define PCGCTL_PHY_IN_SLEEP        BIT(6)
 +#define PCGCTL_ENBL_SLEEP_GATING    BIT(5)
 +#define PCGCTL_RSTPDWNMODULE        BIT(3)
 +#define PCGCTL_PWRCLMP            BIT(2)
 +#define PCGCTL_GATEHCLK            BIT(1)
 +#define PCGCTL_STOPPCLK            BIT(0)
 +
 +#define PCGCCTL1                        HSOTG_REG(0xe04)
 +#define PCGCCTL1_TIMER                  (0x3 << 1)
 +#define PCGCCTL1_GATEEN                 BIT(0)
 +
 +#define EPFIFO(_a)            HSOTG_REG(0x1000 + ((_a) * 0x1000))
 +
 +/* Host Mode Registers */
 +
 +#define HCFG                HSOTG_REG(0x0400)
 +#define HCFG_MODECHTIMEN        BIT(31)
 +#define HCFG_PERSCHEDENA        BIT(26)
 +#define HCFG_FRLISTEN_MASK        (0x3 << 24)
 +#define HCFG_FRLISTEN_SHIFT        24
 +#define HCFG_FRLISTEN_8                (0 << 24)
 +#define FRLISTEN_8_SIZE                8
 +#define HCFG_FRLISTEN_16            BIT(24)
 +#define FRLISTEN_16_SIZE            16
 +#define HCFG_FRLISTEN_32            (2 << 24)
 +#define FRLISTEN_32_SIZE            32
 +#define HCFG_FRLISTEN_64            (3 << 24)
 +#define FRLISTEN_64_SIZE            64
 +#define HCFG_DESCDMA            BIT(23)
 +#define HCFG_RESVALID_MASK        (0xff << 8)
 +#define HCFG_RESVALID_SHIFT        8
 +#define HCFG_ENA32KHZ            BIT(7)
 +#define HCFG_FSLSSUPP            BIT(2)
 +#define HCFG_FSLSPCLKSEL_MASK        (0x3 << 0)
 +#define HCFG_FSLSPCLKSEL_SHIFT        0
 +#define HCFG_FSLSPCLKSEL_30_60_MHZ    0
 +#define HCFG_FSLSPCLKSEL_48_MHZ        1
 +#define HCFG_FSLSPCLKSEL_6_MHZ        2
 +
 +#define HFIR                HSOTG_REG(0x0404)
 +#define HFIR_FRINT_MASK            (0xffff << 0)
 +#define HFIR_FRINT_SHIFT        0
 +#define HFIR_RLDCTRL            BIT(16)
 +
 +#define HFNUM                HSOTG_REG(0x0408)
 +#define HFNUM_FRREM_MASK        (0xffff << 16)
 +#define HFNUM_FRREM_SHIFT        16
 +#define HFNUM_FRNUM_MASK        (0xffff << 0)
 +#define HFNUM_FRNUM_SHIFT        0
 +#define HFNUM_MAX_FRNUM            0x3fff
 +
 +#define HPTXSTS                HSOTG_REG(0x0410)
 +#define TXSTS_QTOP_ODD            BIT(31)
 +#define TXSTS_QTOP_CHNEP_MASK        (0xf << 27)
 +#define TXSTS_QTOP_CHNEP_SHIFT        27
 +#define TXSTS_QTOP_TOKEN_MASK        (0x3 << 25)
 +#define TXSTS_QTOP_TOKEN_SHIFT        25
 +#define TXSTS_QTOP_TERMINATE        BIT(24)
 +#define TXSTS_QSPCAVAIL_MASK        (0xff << 16)
 +#define TXSTS_QSPCAVAIL_SHIFT        16
 +#define TXSTS_FSPCAVAIL_MASK        (0xffff << 0)
 +#define TXSTS_FSPCAVAIL_SHIFT        0
 +
 +#define HAINT                HSOTG_REG(0x0414)
 +#define HAINTMSK            HSOTG_REG(0x0418)
 +#define HFLBADDR            HSOTG_REG(0x041c)
 +
 +#define HPRT0                HSOTG_REG(0x0440)
 +#define HPRT0_SPD_MASK            (0x3 << 17)
 +#define HPRT0_SPD_SHIFT            17
 +#define HPRT0_SPD_HIGH_SPEED        0
 +#define HPRT0_SPD_FULL_SPEED        1
 +#define HPRT0_SPD_LOW_SPEED        2
 +#define HPRT0_TSTCTL_MASK        (0xf << 13)
 +#define HPRT0_TSTCTL_SHIFT        13
 +#define HPRT0_PWR            BIT(12)
 +#define HPRT0_LNSTS_MASK        (0x3 << 10)
 +#define HPRT0_LNSTS_SHIFT        10
 +#define HPRT0_RST            BIT(8)
 +#define HPRT0_SUSP            BIT(7)
 +#define HPRT0_RES            BIT(6)
 +#define HPRT0_OVRCURRCHG        BIT(5)
 +#define HPRT0_OVRCURRACT        BIT(4)
 +#define HPRT0_ENACHG            BIT(3)
 +#define HPRT0_ENA            BIT(2)
 +#define HPRT0_CONNDET            BIT(1)
 +#define HPRT0_CONNSTS            BIT(0)
 +
 +#define HCCHAR(_ch)            HSOTG_REG(0x0500 + 0x20 * (_ch))
 +#define HCCHAR_CHENA            BIT(31)
 +#define HCCHAR_CHDIS            BIT(30)
 +#define HCCHAR_ODDFRM            BIT(29)
 +#define HCCHAR_DEVADDR_MASK        (0x7f << 22)
 +#define HCCHAR_DEVADDR_SHIFT        22
 +#define HCCHAR_MULTICNT_MASK        (0x3 << 20)
 +#define HCCHAR_MULTICNT_SHIFT        20
 +#define HCCHAR_EPTYPE_MASK        (0x3 << 18)
 +#define HCCHAR_EPTYPE_SHIFT        18
 +#define HCCHAR_LSPDDEV            BIT(17)
 +#define HCCHAR_EPDIR            BIT(15)
 +#define HCCHAR_EPNUM_MASK        (0xf << 11)
 +#define HCCHAR_EPNUM_SHIFT        11
 +#define HCCHAR_MPS_MASK            (0x7ff << 0)
 +#define HCCHAR_MPS_SHIFT        0
 +
 +#define HCSPLT(_ch)            HSOTG_REG(0x0504 + 0x20 * (_ch))
 +#define HCSPLT_SPLTENA            BIT(31)
 +#define HCSPLT_COMPSPLT            BIT(16)
 +#define HCSPLT_XACTPOS_MASK        (0x3 << 14)
 +#define HCSPLT_XACTPOS_SHIFT        14
 +#define HCSPLT_XACTPOS_MID        0
 +#define HCSPLT_XACTPOS_END        1
 +#define HCSPLT_XACTPOS_BEGIN        2
 +#define HCSPLT_XACTPOS_ALL        3
 +#define HCSPLT_HUBADDR_MASK        (0x7f << 7)
 +#define HCSPLT_HUBADDR_SHIFT        7
 +#define HCSPLT_PRTADDR_MASK        (0x7f << 0)
 +#define HCSPLT_PRTADDR_SHIFT        0
 +
 +#define HCINT(_ch)            HSOTG_REG(0x0508 + 0x20 * (_ch))
 +#define HCINTMSK(_ch)            HSOTG_REG(0x050c + 0x20 * (_ch))
 +#define HCINTMSK_RESERVED14_31        (0x3ffff << 14)
 +#define HCINTMSK_FRM_LIST_ROLL        BIT(13)
 +#define HCINTMSK_XCS_XACT        BIT(12)
 +#define HCINTMSK_BNA            BIT(11)
 +#define HCINTMSK_DATATGLERR        BIT(10)
 +#define HCINTMSK_FRMOVRUN        BIT(9)
 +#define HCINTMSK_BBLERR            BIT(8)
 +#define HCINTMSK_XACTERR        BIT(7)
 +#define HCINTMSK_NYET            BIT(6)
 +#define HCINTMSK_ACK            BIT(5)
 +#define HCINTMSK_NAK            BIT(4)
 +#define HCINTMSK_STALL            BIT(3)
 +#define HCINTMSK_AHBERR            BIT(2)
 +#define HCINTMSK_CHHLTD            BIT(1)
 +#define HCINTMSK_XFERCOMPL        BIT(0)
 +
 +#define HCTSIZ(_ch)            HSOTG_REG(0x0510 + 0x20 * (_ch))
 +#define TSIZ_DOPNG            BIT(31)
 +#define TSIZ_SC_MC_PID_MASK        (0x3 << 29)
 +#define TSIZ_SC_MC_PID_SHIFT        29
 +#define TSIZ_SC_MC_PID_DATA0        0
 +#define TSIZ_SC_MC_PID_DATA2        1
 +#define TSIZ_SC_MC_PID_DATA1        2
 +#define TSIZ_SC_MC_PID_MDATA        3
 +#define TSIZ_SC_MC_PID_SETUP        3
 +#define TSIZ_PKTCNT_MASK        (0x3ff << 19)
 +#define TSIZ_PKTCNT_SHIFT        19
 +#define TSIZ_NTD_MASK            (0xff << 8)
 +#define TSIZ_NTD_SHIFT            8
 +#define TSIZ_SCHINFO_MASK        (0xff << 0)
 +#define TSIZ_SCHINFO_SHIFT        0
 +#define TSIZ_XFERSIZE_MASK        (0x7ffff << 0)
 +#define TSIZ_XFERSIZE_SHIFT        0
 +
 +#define HCDMA(_ch)            HSOTG_REG(0x0514 + 0x20 * (_ch))
 +
 +#define HCDMAB(_ch)            HSOTG_REG(0x051c + 0x20 * (_ch))
 +
 +#define HCFIFO(_ch)            HSOTG_REG(0x1000 + 0x1000 * (_ch))
 +
 +/**
 + * struct dwc2_dma_desc - DMA descriptor structure,
 + * used for both host and gadget modes
 + *
 + * @status: DMA descriptor status quadlet
 + * @buf:    DMA descriptor data buffer pointer
 + *
 + * DMA Descriptor structure contains two quadlets:
 + * Status quadlet and Data buffer pointer.
 + */
 +struct dwc2_dma_desc {
 +    uint32_t status;
 +    uint32_t buf;
 +} __packed;
 +
 +/* Host Mode DMA descriptor status quadlet */
 +
 +#define HOST_DMA_A            BIT(31)
 +#define HOST_DMA_STS_MASK        (0x3 << 28)
 +#define HOST_DMA_STS_SHIFT        28
 +#define HOST_DMA_STS_PKTERR        BIT(28)
 +#define HOST_DMA_EOL            BIT(26)
 +#define HOST_DMA_IOC            BIT(25)
 +#define HOST_DMA_SUP            BIT(24)
 +#define HOST_DMA_ALT_QTD        BIT(23)
 +#define HOST_DMA_QTD_OFFSET_MASK    (0x3f << 17)
 +#define HOST_DMA_QTD_OFFSET_SHIFT    17
 +#define HOST_DMA_ISOC_NBYTES_MASK    (0xfff << 0)
 +#define HOST_DMA_ISOC_NBYTES_SHIFT    0
 +#define HOST_DMA_NBYTES_MASK        (0x1ffff << 0)
 +#define HOST_DMA_NBYTES_SHIFT        0
 +#define HOST_DMA_NBYTES_LIMIT        131071
 +
 +/* Device Mode DMA descriptor status quadlet */
 +
 +#define DEV_DMA_BUFF_STS_MASK        (0x3 << 30)
 +#define DEV_DMA_BUFF_STS_SHIFT        30
 +#define DEV_DMA_BUFF_STS_HREADY        0
 +#define DEV_DMA_BUFF_STS_DMABUSY    1
 +#define DEV_DMA_BUFF_STS_DMADONE    2
 +#define DEV_DMA_BUFF_STS_HBUSY        3
 +#define DEV_DMA_STS_MASK        (0x3 << 28)
 +#define DEV_DMA_STS_SHIFT        28
 +#define DEV_DMA_STS_SUCC        0
 +#define DEV_DMA_STS_BUFF_FLUSH        1
 +#define DEV_DMA_STS_BUFF_ERR        3
 +#define DEV_DMA_L            BIT(27)
 +#define DEV_DMA_SHORT            BIT(26)
 +#define DEV_DMA_IOC            BIT(25)
 +#define DEV_DMA_SR            BIT(24)
 +#define DEV_DMA_MTRF            BIT(23)
 +#define DEV_DMA_ISOC_PID_MASK        (0x3 << 23)
 +#define DEV_DMA_ISOC_PID_SHIFT        23
 +#define DEV_DMA_ISOC_PID_DATA0        0
 +#define DEV_DMA_ISOC_PID_DATA2        1
 +#define DEV_DMA_ISOC_PID_DATA1        2
 +#define DEV_DMA_ISOC_PID_MDATA        3
 +#define DEV_DMA_ISOC_FRNUM_MASK        (0x7ff << 12)
 +#define DEV_DMA_ISOC_FRNUM_SHIFT    12
 +#define DEV_DMA_ISOC_TX_NBYTES_MASK    (0xfff << 0)
 +#define DEV_DMA_ISOC_TX_NBYTES_LIMIT    0xfff
 +#define DEV_DMA_ISOC_RX_NBYTES_MASK    (0x7ff << 0)
 +#define DEV_DMA_ISOC_RX_NBYTES_LIMIT    0x7ff
 +#define DEV_DMA_ISOC_NBYTES_SHIFT    0
 +#define DEV_DMA_NBYTES_MASK        (0xffff << 0)
 +#define DEV_DMA_NBYTES_SHIFT        0
 +#define DEV_DMA_NBYTES_LIMIT        0xffff
 +
 +#define MAX_DMA_DESC_NUM_GENERIC    64
 +#define MAX_DMA_DESC_NUM_HS_ISOC    256
 +
 +#endif /* __DWC2_HW_H__ */
 --
 .20.1

-[PULL 29/42] hw/i2c: Add header for ARM SBCon two-wire serial bus interface
+[PULL 16/29] dwc-hsotg (dwc2) USB host controller state definitions
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Paul Zimmerman <pauldzim@gmail.com>
-'ARM SBCon two-wire serial bus interface' is the official
+Add the dwc-hsotg (dwc2) USB host controller state definitions.
-name describing the pair of registers used to bitbanging
+Mostly based on hw/usb/hcd-ehci.h.
-I2C in the Versatile boards.
+Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
-Make the private VersatileI2CState structure as public
+Message-id: 20200520235349.21215-4-pauldzim@gmail.com
 ArmSbconI2CState.
 Add the TYPE_ARM_SBCON_I2C, alias to our current
 TYPE_VERSATILE_I2C model.
 Rename the memory region description as 'arm_sbcon_i2c'.
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20200617072539.32686-5-f4bug@amsat.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/i2c/arm_sbcon_i2c.h | 35 ++++++++++++++++++++++++++++++++++
+ hw/usb/hcd-dwc2.h | 190 ++++++++++++++++++++++++++++++++++++++++++++++
- hw/i2c/versatile_i2c.c         | 17 +++++------------
+file changed, 190 insertions(+)
- MAINTAINERS                    |  1 +
+ create mode 100644 hw/usb/hcd-dwc2.h
-files changed, 41 insertions(+), 12 deletions(-)
- create mode 100644 include/hw/i2c/arm_sbcon_i2c.h
+diff --git a/hw/usb/hcd-dwc2.h b/hw/usb/hcd-dwc2.h
 diff --git a/include/hw/i2c/arm_sbcon_i2c.h b/include/hw/i2c/arm_sbcon_i2c.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/include/hw/i2c/arm_sbcon_i2c.h
++++ b/hw/usb/hcd-dwc2.h
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * ARM SBCon two-wire serial bus interface (I2C bitbang)
++ * dwc-hsotg (dwc2) USB host controller state definitions
-+ *   a.k.a.
++ *
-+ * ARM Versatile I2C controller
++ * Based on hw/usb/hcd-ehci.h
 + *
-+ * Copyright (c) 2006-2007 CodeSourcery.
++ * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
-+ * Copyright (c) 2012 Oskar Andero <oskar.andero@gmail.com>
++ *
-+ * Copyright (C) 2020 Philippe Mathieu-Daudé <f4bug@amsat.org>
++ * This program is free software; you can redistribute it and/or modify
-+ *
++ * it under the terms of the GNU General Public License as published by
-+ * SPDX-License-Identifier: GPL-2.0-or-later
++ * the Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 + * GNU General Public License for more details.
 + */
-+#ifndef HW_I2C_ARM_SBCON_H
++
-+#define HW_I2C_ARM_SBCON_H
++#ifndef HW_USB_DWC2_H
-+
++#define HW_USB_DWC2_H
 +
 +#include "qemu/timer.h"
 +#include "hw/irq.h"
 +#include "hw/sysbus.h"
-+#include "hw/i2c/bitbang_i2c.h"
++#include "hw/usb.h"
-+
++#include "sysemu/dma.h"
-+#define TYPE_VERSATILE_I2C "versatile_i2c"
++
-+#define TYPE_ARM_SBCON_I2C TYPE_VERSATILE_I2C
++#define DWC2_MMIO_SIZE      0x11000
 +
-+#define ARM_SBCON_I2C(obj) \
++#define DWC2_NB_CHAN        8       /* Number of host channels */
-+    OBJECT_CHECK(ArmSbconI2CState, (obj), TYPE_ARM_SBCON_I2C)
++#define DWC2_MAX_XFER_SIZE  65536   /* Max transfer size expected in HCTSIZ */
 +
-+typedef struct ArmSbconI2CState {
++typedef struct DWC2Packet DWC2Packet;
 +typedef struct DWC2State DWC2State;
 +typedef struct DWC2Class DWC2Class;
 +
 +enum async_state {
 +    DWC2_ASYNC_NONE = 0,
 +    DWC2_ASYNC_INITIALIZED,
 +    DWC2_ASYNC_INFLIGHT,
 +    DWC2_ASYNC_FINISHED,
 +};
 +
 +struct DWC2Packet {
 +    USBPacket packet;
 +    uint32_t devadr;
 +    uint32_t epnum;
 +    uint32_t epdir;
 +    uint32_t mps;
 +    uint32_t pid;
 +    uint32_t index;
 +    uint32_t pcnt;
 +    uint32_t len;
 +    int32_t async;
 +    bool small;
 +    bool needs_service;
 +};
 +
 +struct DWC2State {
 +    /*< private >*/
 +    SysBusDevice parent_obj;
++
 +    /*< public >*/
-+
++    USBBus bus;
-+    MemoryRegion iomem;
++    qemu_irq irq;
-+    bitbang_i2c_interface bitbang;
++    MemoryRegion *dma_mr;
-+    int out;
++    AddressSpace dma_as;
-+    int in;
++    MemoryRegion container;
-+} ArmSbconI2CState;
++    MemoryRegion hsotg;
-+
++    MemoryRegion fifos;
-+#endif /* HW_I2C_ARM_SBCON_H */
++
-diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
++    union {
-index XXXXXXX..XXXXXXX 100644
++#define DWC2_GLBREG_SIZE    0x70
---- a/hw/i2c/versatile_i2c.c
++        uint32_t glbreg[DWC2_GLBREG_SIZE / sizeof(uint32_t)];
-+++ b/hw/i2c/versatile_i2c.c
++        struct {
-@@ -XXX,XX +XXX,XX @@
++            uint32_t gotgctl;       /* 00 */
- /*
++            uint32_t gotgint;       /* 04 */
-- * ARM Versatile I2C controller
++            uint32_t gahbcfg;       /* 08 */
-+ * ARM SBCon two-wire serial bus interface (I2C bitbang)
++            uint32_t gusbcfg;       /* 0c */
-+ * a.k.a. ARM Versatile I2C controller
++            uint32_t grstctl;       /* 10 */
-  *
++            uint32_t gintsts;       /* 14 */
-  * Copyright (c) 2006-2007 CodeSourcery.
++            uint32_t gintmsk;       /* 18 */
-  * Copyright (c) 2012 Oskar Andero <oskar.andero@gmail.com>
++            uint32_t grxstsr;       /* 1c */
-@@ -XXX,XX +XXX,XX @@
++            uint32_t grxstsp;       /* 20 */
-  */
++            uint32_t grxfsiz;       /* 24 */
++            uint32_t gnptxfsiz;     /* 28 */
- #include "qemu/osdep.h"
++            uint32_t gnptxsts;      /* 2c */
--#include "hw/sysbus.h"
++            uint32_t gi2cctl;       /* 30 */
--#include "hw/i2c/bitbang_i2c.h"
++            uint32_t gpvndctl;      /* 34 */
-+#include "hw/i2c/arm_sbcon_i2c.h"
++            uint32_t ggpio;         /* 38 */
- #include "hw/registerfields.h"
++            uint32_t guid;          /* 3c */
- #include "qemu/log.h"
++            uint32_t gsnpsid;       /* 40 */
- #include "qemu/module.h"
++            uint32_t ghwcfg1;       /* 44 */
++            uint32_t ghwcfg2;       /* 48 */
--#define TYPE_VERSATILE_I2C "versatile_i2c"
++            uint32_t ghwcfg3;       /* 4c */
- #define VERSATILE_I2C(obj) \
++            uint32_t ghwcfg4;       /* 50 */
-     OBJECT_CHECK(VersatileI2CState, (obj), TYPE_VERSATILE_I2C)
++            uint32_t glpmcfg;       /* 54 */
++            uint32_t gpwrdn;        /* 58 */
--typedef struct VersatileI2CState {
++            uint32_t gdfifocfg;     /* 5c */
--    SysBusDevice parent_obj;
++            uint32_t gadpctl;       /* 60 */
-+typedef ArmSbconI2CState VersatileI2CState;
++            uint32_t grefclk;       /* 64 */
++            uint32_t gintmsk2;      /* 68 */
--    MemoryRegion iomem;
++            uint32_t gintsts2;      /* 6c */
--    bitbang_i2c_interface bitbang;
++        };
--    int out;
++    };
--    int in;
++
--} VersatileI2CState;
++    union {
++#define DWC2_FSZREG_SIZE    0x04
- REG32(CONTROL_GET, 0)
++        uint32_t fszreg[DWC2_FSZREG_SIZE / sizeof(uint32_t)];
- REG32(CONTROL_SET, 0)
++        struct {
-@@ -XXX,XX +XXX,XX @@ static void versatile_i2c_init(Object *obj)
++            uint32_t hptxfsiz;      /* 100 */
-     bus = i2c_init_bus(dev, "i2c");
++        };
-     bitbang_i2c_init(&s->bitbang, bus);
++    };
-     memory_region_init_io(&s->iomem, obj, &versatile_i2c_ops, s,
++
--                          "versatile_i2c", 0x1000);
++    union {
-+                          "arm_sbcon_i2c", 0x1000);
++#define DWC2_HREG0_SIZE     0x44
-     sysbus_init_mmio(sbd, &s->iomem);
++        uint32_t hreg0[DWC2_HREG0_SIZE / sizeof(uint32_t)];
- }
++        struct {
++            uint32_t hcfg;          /* 400 */
-diff --git a/MAINTAINERS b/MAINTAINERS
++            uint32_t hfir;          /* 404 */
-index XXXXXXX..XXXXXXX 100644
++            uint32_t hfnum;         /* 408 */
---- a/MAINTAINERS
++            uint32_t rsvd0;         /* 40c */
-+++ b/MAINTAINERS
++            uint32_t hptxsts;       /* 410 */
-@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
++            uint32_t haint;         /* 414 */
- L: qemu-arm@nongnu.org
++            uint32_t haintmsk;      /* 418 */
- S: Maintained
++            uint32_t hflbaddr;      /* 41c */
- F: hw/*/versatile*
++            uint32_t rsvd1[8];      /* 420-43c */
-+F: include/hw/i2c/arm_sbcon_i2c.h
++            uint32_t hprt0;         /* 440 */
- F: hw/misc/arm_sysctl.c
++        };
- F: docs/system/arm/versatile.rst
++    };
++
 +#define DWC2_HREG1_SIZE     (0x20 * DWC2_NB_CHAN)
 +    uint32_t hreg1[DWC2_HREG1_SIZE / sizeof(uint32_t)];
 +
 +#define hcchar(_ch)     hreg1[((_ch) << 3) + 0] /* 500, 520, ... */
 +#define hcsplt(_ch)     hreg1[((_ch) << 3) + 1] /* 504, 524, ... */
 +#define hcint(_ch)      hreg1[((_ch) << 3) + 2] /* 508, 528, ... */
 +#define hcintmsk(_ch)   hreg1[((_ch) << 3) + 3] /* 50c, 52c, ... */
 +#define hctsiz(_ch)     hreg1[((_ch) << 3) + 4] /* 510, 530, ... */
 +#define hcdma(_ch)      hreg1[((_ch) << 3) + 5] /* 514, 534, ... */
 +#define hcdmab(_ch)     hreg1[((_ch) << 3) + 7] /* 51c, 53c, ... */
 +
 +    union {
 +#define DWC2_PCGREG_SIZE    0x08
 +        uint32_t pcgreg[DWC2_PCGREG_SIZE / sizeof(uint32_t)];
 +        struct {
 +            uint32_t pcgctl;        /* e00 */
 +            uint32_t pcgcctl1;      /* e04 */
 +        };
 +    };
 +
 +    /* TODO - implement FIFO registers for slave mode */
 +#define DWC2_HFIFO_SIZE     (0x1000 * DWC2_NB_CHAN)
 +
 +    /*
 +     *  Internal state
 +     */
 +    QEMUTimer *eof_timer;
 +    QEMUTimer *frame_timer;
 +    QEMUBH *async_bh;
 +    int64_t sof_time;
 +    int64_t usb_frame_time;
 +    int64_t usb_bit_time;
 +    uint32_t usb_version;
 +    uint16_t frame_number;
 +    uint16_t fi;
 +    uint16_t next_chan;
 +    bool working;
 +    USBPort uport;
 +    DWC2Packet packet[DWC2_NB_CHAN];                   /* one packet per chan */
 +    uint8_t usb_buf[DWC2_NB_CHAN][DWC2_MAX_XFER_SIZE]; /* one buffer per chan */
 +};
 +
 +struct DWC2Class {
 +    /*< private >*/
 +    SysBusDeviceClass parent_class;
 +    ResettablePhases parent_phases;
 +
 +    /*< public >*/
 +};
 +
 +#define TYPE_DWC2_USB   "dwc2-usb"
 +#define DWC2_USB(obj) \
 +    OBJECT_CHECK(DWC2State, (obj), TYPE_DWC2_USB)
 +#define DWC2_CLASS(klass) \
 +    OBJECT_CLASS_CHECK(DWC2Class, (klass), TYPE_DWC2_USB)
 +#define DWC2_GET_CLASS(obj) \
 +    OBJECT_GET_CLASS(DWC2Class, (obj), TYPE_DWC2_USB)
 +
 +#endif
 --
 .20.1

-[PULL 23/42] target/arm: Move some functions used only in translate-neon.inc.c to that file
+[PULL 17/29] dwc-hsotg (dwc2) USB host controller emulation
-The functions neon_element_offset(), neon_load_element(),
+From: Paul Zimmerman <pauldzim@gmail.com>
 neon_load_element64(), neon_store_element() and
 neon_store_element64() are used only in the translate-neon.inc.c
 file, so move their definitions there.
-Since the .inc.c file is #included in translate.c this doesn't make
+Add the dwc-hsotg (dwc2) USB host controller emulation code.
-much difference currently, but it's a more logical place to put the
+Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c.
 functions and it might be helpful if we ever decide to try to make
 the .inc.c files genuinely separate compilation units.
+Note that to use this with the dwc-otg driver in the Raspbian
+kernel, you must pass the option "dwc_otg.fiq_fsm_enable=0" on
+the kernel command line.
+Emulation of slave mode and of descriptor-DMA mode has not been
+implemented yet. These modes are seldom used.
+I have used some on-line sources of information while developing
+this emulation, including:
+http://www.capital-micro.com/PDF/CME-M7_Family_User_Guide_EN.pdf
+which has a pretty complete description of the controller starting
+on page 370.
+https://sourceforge.net/p/wive-ng/wive-ng-mt/ci/master/tree/docs/DataSheets/RT3050_5x_V2.0_081408_0902.pdf
+which has a description of the controller registers starting on
+page 130.
+Thanks to Felippe Mathieu-Daude for providing a cleaner method
+of implementing the memory regions for the controller registers.
+Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
+Message-id: 20200520235349.21215-5-pauldzim@gmail.com
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-22-peter.maydell@linaro.org
 ---
- target/arm/translate-neon.inc.c | 101 ++++++++++++++++++++++++++++++++
+ hw/usb/hcd-dwc2.c    | 1417 ++++++++++++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 101 --------------------------------
+ hw/usb/Kconfig       |    5 +
-files changed, 101 insertions(+), 101 deletions(-)
+ hw/usb/Makefile.objs |    1 +
  hw/usb/trace-events  |   50 ++
 files changed, 1473 insertions(+)
  create mode 100644 hw/usb/hcd-dwc2.c
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
+diff --git a/hw/usb/hcd-dwc2.c b/hw/usb/hcd-dwc2.c
-index XXXXXXX..XXXXXXX 100644
+new file mode 100644
---- a/target/arm/translate-neon.inc.c
+index XXXXXXX..XXXXXXX
-+++ b/target/arm/translate-neon.inc.c
+--- /dev/null
-@@ -XXX,XX +XXX,XX @@ static inline int rsub_8(DisasContext *s, int x)
++++ b/hw/usb/hcd-dwc2.c
- #include "decode-neon-ls.inc.c"
+@@ -XXX,XX +XXX,XX @@
- #include "decode-neon-shared.inc.c"
++/*
++ * dwc-hsotg (dwc2) USB host controller emulation
-+/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
++ *
-+ * where 0 is the least significant end of the register.
++ * Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c
 + *
 + * Note that to use this emulation with the dwc-otg driver in the
 + * Raspbian kernel, you must pass the option "dwc_otg.fiq_fsm_enable=0"
 + * on the kernel command line.
 + *
 + * Some useful documentation used to develop this emulation can be
 + * found online (as of April 2020) at:
 + *
 + * http://www.capital-micro.com/PDF/CME-M7_Family_User_Guide_EN.pdf
 + * which has a pretty complete description of the controller starting
 + * on page 370.
 + *
 + * https://sourceforge.net/p/wive-ng/wive-ng-mt/ci/master/tree/docs/DataSheets/RT3050_5x_V2.0_081408_0902.pdf
 + * which has a description of the controller registers starting on
 + * page 130.
 + *
 + * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
 + *
 + * This program is free software; you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License as published by
 + * the Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 + * GNU General Public License for more details.
 + */
-+static inline long
++
-+neon_element_offset(int reg, int element, MemOp size)
++#include "qemu/osdep.h"
-+{
++#include "qemu/units.h"
-+    int element_size = 1 << size;
++#include "qapi/error.h"
-+    int ofs = element * element_size;
++#include "hw/usb/dwc2-regs.h"
-+#ifdef HOST_WORDS_BIGENDIAN
++#include "hw/usb/hcd-dwc2.h"
-+    /* Calculate the offset assuming fully little-endian,
++#include "migration/vmstate.h"
-+     * then XOR to account for the order of the 8-byte units.
++#include "trace.h"
 +#include "qemu/log.h"
 +#include "qemu/error-report.h"
 +#include "qemu/main-loop.h"
 +#include "hw/qdev-properties.h"
 +
 +#define USB_HZ_FS       12000000
 +#define USB_HZ_HS       96000000
 +#define USB_FRMINTVL    12000
 +
 +/* nifty macros from Arnon's EHCI version  */
 +#define get_field(data, field) \
 +    (((data) & field##_MASK) >> field##_SHIFT)
 +
 +#define set_field(data, newval, field) do { \
 +    uint32_t val = *(data); \
 +    val &= ~field##_MASK; \
 +    val |= ((newval) << field##_SHIFT) & field##_MASK; \
 +    *(data) = val; \
 +} while (0)
 +
 +#define get_bit(data, bitmask) \
 +    (!!((data) & (bitmask)))
 +
 +/* update irq line */
 +static inline void dwc2_update_irq(DWC2State *s)
 +{
 +    static int oldlevel;
 +    int level = 0;
 +
 +    if ((s->gintsts & s->gintmsk) && (s->gahbcfg & GAHBCFG_GLBL_INTR_EN)) {
 +        level = 1;
 +    }
 +    if (level != oldlevel) {
 +        oldlevel = level;
 +        trace_usb_dwc2_update_irq(level);
 +        qemu_set_irq(s->irq, level);
 +    }
 +}
 +
 +/* flag interrupt condition */
 +static inline void dwc2_raise_global_irq(DWC2State *s, uint32_t intr)
 +{
 +    if (!(s->gintsts & intr)) {
 +        s->gintsts |= intr;
 +        trace_usb_dwc2_raise_global_irq(intr);
 +        dwc2_update_irq(s);
 +    }
 +}
 +
 +static inline void dwc2_lower_global_irq(DWC2State *s, uint32_t intr)
 +{
 +    if (s->gintsts & intr) {
 +        s->gintsts &= ~intr;
 +        trace_usb_dwc2_lower_global_irq(intr);
 +        dwc2_update_irq(s);
 +    }
 +}
 +
 +static inline void dwc2_raise_host_irq(DWC2State *s, uint32_t host_intr)
 +{
 +    if (!(s->haint & host_intr)) {
 +        s->haint |= host_intr;
 +        s->haint &= 0xffff;
 +        trace_usb_dwc2_raise_host_irq(host_intr);
 +        if (s->haint & s->haintmsk) {
 +            dwc2_raise_global_irq(s, GINTSTS_HCHINT);
 +        }
 +    }
 +}
 +
 +static inline void dwc2_lower_host_irq(DWC2State *s, uint32_t host_intr)
 +{
 +    if (s->haint & host_intr) {
 +        s->haint &= ~host_intr;
 +        trace_usb_dwc2_lower_host_irq(host_intr);
 +        if (!(s->haint & s->haintmsk)) {
 +            dwc2_lower_global_irq(s, GINTSTS_HCHINT);
 +        }
 +    }
 +}
 +
 +static inline void dwc2_update_hc_irq(DWC2State *s, int index)
 +{
 +    uint32_t host_intr = 1 << (index >> 3);
 +
 +    if (s->hreg1[index + 2] & s->hreg1[index + 3]) {
 +        dwc2_raise_host_irq(s, host_intr);
 +    } else {
 +        dwc2_lower_host_irq(s, host_intr);
 +    }
 +}
 +
 +/* set a timer for EOF */
 +static void dwc2_eof_timer(DWC2State *s)
 +{
 +    timer_mod(s->eof_timer, s->sof_time + s->usb_frame_time);
 +}
 +
 +/* Set a timer for EOF and generate SOF event */
 +static void dwc2_sof(DWC2State *s)
 +{
 +    s->sof_time += s->usb_frame_time;
 +    trace_usb_dwc2_sof(s->sof_time);
 +    dwc2_eof_timer(s);
 +    dwc2_raise_global_irq(s, GINTSTS_SOF);
 +}
 +
 +/* Do frame processing on frame boundary */
 +static void dwc2_frame_boundary(void *opaque)
 +{
 +    DWC2State *s = opaque;
 +    int64_t now;
 +    uint16_t frcnt;
 +
 +    now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 +
 +    /* Frame boundary, so do EOF stuff here */
 +
 +    /* Increment frame number */
 +    frcnt = (uint16_t)((now - s->sof_time) / s->fi);
 +    s->frame_number = (s->frame_number + frcnt) & 0xffff;
 +    s->hfnum = s->frame_number & HFNUM_MAX_FRNUM;
 +
 +    /* Do SOF stuff here */
 +    dwc2_sof(s);
 +}
 +
 +/* Start sending SOF tokens on the USB bus */
 +static void dwc2_bus_start(DWC2State *s)
 +{
 +    trace_usb_dwc2_bus_start();
 +    s->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 +    dwc2_eof_timer(s);
 +}
 +
 +/* Stop sending SOF tokens on the USB bus */
 +static void dwc2_bus_stop(DWC2State *s)
 +{
 +    trace_usb_dwc2_bus_stop();
 +    timer_del(s->eof_timer);
 +}
 +
 +static USBDevice *dwc2_find_device(DWC2State *s, uint8_t addr)
 +{
 +    USBDevice *dev;
 +
 +    trace_usb_dwc2_find_device(addr);
 +
 +    if (!(s->hprt0 & HPRT0_ENA)) {
 +        trace_usb_dwc2_port_disabled(0);
 +    } else {
 +        dev = usb_find_device(&s->uport, addr);
 +        if (dev != NULL) {
 +            trace_usb_dwc2_device_found(0);
 +            return dev;
 +        }
 +    }
 +
 +    trace_usb_dwc2_device_not_found();
 +    return NULL;
 +}
 +
 +static const char *pstatus[] = {
 +    "USB_RET_SUCCESS", "USB_RET_NODEV", "USB_RET_NAK", "USB_RET_STALL",
 +    "USB_RET_BABBLE", "USB_RET_IOERROR", "USB_RET_ASYNC",
 +    "USB_RET_ADD_TO_QUEUE", "USB_RET_REMOVE_FROM_QUEUE"
 +};
 +
 +static uint32_t pintr[] = {
 +    HCINTMSK_XFERCOMPL, HCINTMSK_XACTERR, HCINTMSK_NAK, HCINTMSK_STALL,
 +    HCINTMSK_BBLERR, HCINTMSK_XACTERR, HCINTMSK_XACTERR, HCINTMSK_XACTERR,
 +    HCINTMSK_XACTERR
 +};
 +
 +static const char *types[] = {
 +    "Ctrl", "Isoc", "Bulk", "Intr"
 +};
 +
 +static const char *dirs[] = {
 +    "Out", "In"
 +};
 +
 +static void dwc2_handle_packet(DWC2State *s, uint32_t devadr, USBDevice *dev,
 +                               USBEndpoint *ep, uint32_t index, bool send)
 +{
 +    DWC2Packet *p;
 +    uint32_t hcchar = s->hreg1[index];
 +    uint32_t hctsiz = s->hreg1[index + 4];
 +    uint32_t hcdma = s->hreg1[index + 5];
 +    uint32_t chan, epnum, epdir, eptype, mps, pid, pcnt, len, tlen, intr = 0;
 +    uint32_t tpcnt, stsidx, actual = 0;
 +    bool do_intr = false, done = false;
 +
 +    epnum = get_field(hcchar, HCCHAR_EPNUM);
 +    epdir = get_bit(hcchar, HCCHAR_EPDIR);
 +    eptype = get_field(hcchar, HCCHAR_EPTYPE);
 +    mps = get_field(hcchar, HCCHAR_MPS);
 +    pid = get_field(hctsiz, TSIZ_SC_MC_PID);
 +    pcnt = get_field(hctsiz, TSIZ_PKTCNT);
 +    len = get_field(hctsiz, TSIZ_XFERSIZE);
 +    assert(len <= DWC2_MAX_XFER_SIZE);
 +    chan = index >> 3;
 +    p = &s->packet[chan];
 +
 +    trace_usb_dwc2_handle_packet(chan, dev, &p->packet, epnum, types[eptype],
 +                                 dirs[epdir], mps, len, pcnt);
 +
 +    if (eptype == USB_ENDPOINT_XFER_CONTROL && pid == TSIZ_SC_MC_PID_SETUP) {
 +        pid = USB_TOKEN_SETUP;
 +    } else {
 +        pid = epdir ? USB_TOKEN_IN : USB_TOKEN_OUT;
 +    }
 +
 +    if (send) {
 +        tlen = len;
 +        if (p->small) {
 +            if (tlen > mps) {
 +                tlen = mps;
 +            }
 +        }
 +
 +        if (pid != USB_TOKEN_IN) {
 +            trace_usb_dwc2_memory_read(hcdma, tlen);
 +            if (dma_memory_read(&s->dma_as, hcdma,
 +                                s->usb_buf[chan], tlen) != MEMTX_OK) {
 +                qemu_log_mask(LOG_GUEST_ERROR, "%s: dma_memory_read failed\n",
 +                              __func__);
 +            }
 +        }
 +
 +        usb_packet_init(&p->packet);
 +        usb_packet_setup(&p->packet, pid, ep, 0, hcdma,
 +                         pid != USB_TOKEN_IN, true);
 +        usb_packet_addbuf(&p->packet, s->usb_buf[chan], tlen);
 +        p->async = DWC2_ASYNC_NONE;
 +        usb_handle_packet(dev, &p->packet);
 +    } else {
 +        tlen = p->len;
 +    }
 +
 +    stsidx = -p->packet.status;
 +    assert(stsidx < sizeof(pstatus) / sizeof(*pstatus));
 +    actual = p->packet.actual_length;
 +    trace_usb_dwc2_packet_status(pstatus[stsidx], actual);
 +
 +babble:
 +    if (p->packet.status != USB_RET_SUCCESS &&
 +            p->packet.status != USB_RET_NAK &&
 +            p->packet.status != USB_RET_STALL &&
 +            p->packet.status != USB_RET_ASYNC) {
 +        trace_usb_dwc2_packet_error(pstatus[stsidx]);
 +    }
 +
 +    if (p->packet.status == USB_RET_ASYNC) {
 +        trace_usb_dwc2_async_packet(&p->packet, chan, dev, epnum,
 +                                    dirs[epdir], tlen);
 +        usb_device_flush_ep_queue(dev, ep);
 +        assert(p->async != DWC2_ASYNC_INFLIGHT);
 +        p->devadr = devadr;
 +        p->epnum = epnum;
 +        p->epdir = epdir;
 +        p->mps = mps;
 +        p->pid = pid;
 +        p->index = index;
 +        p->pcnt = pcnt;
 +        p->len = tlen;
 +        p->async = DWC2_ASYNC_INFLIGHT;
 +        p->needs_service = false;
 +        return;
 +    }
 +
 +    if (p->packet.status == USB_RET_SUCCESS) {
 +        if (actual > tlen) {
 +            p->packet.status = USB_RET_BABBLE;
 +            goto babble;
 +        }
 +
 +        if (pid == USB_TOKEN_IN) {
 +            trace_usb_dwc2_memory_write(hcdma, actual);
 +            if (dma_memory_write(&s->dma_as, hcdma, s->usb_buf[chan],
 +                                 actual) != MEMTX_OK) {
 +                qemu_log_mask(LOG_GUEST_ERROR, "%s: dma_memory_write failed\n",
 +                              __func__);
 +            }
 +        }
 +
 +        tpcnt = actual / mps;
 +        if (actual % mps) {
 +            tpcnt++;
 +            if (pid == USB_TOKEN_IN) {
 +                done = true;
 +            }
 +        }
 +
 +        pcnt -= tpcnt < pcnt ? tpcnt : pcnt;
 +        set_field(&hctsiz, pcnt, TSIZ_PKTCNT);
 +        len -= actual < len ? actual : len;
 +        set_field(&hctsiz, len, TSIZ_XFERSIZE);
 +        s->hreg1[index + 4] = hctsiz;
 +        hcdma += actual;
 +        s->hreg1[index + 5] = hcdma;
 +
 +        if (!pcnt || len == 0 || actual == 0) {
 +            done = true;
 +        }
 +    } else {
 +        intr |= pintr[stsidx];
 +        if (p->packet.status == USB_RET_NAK &&
 +            (eptype == USB_ENDPOINT_XFER_CONTROL ||
 +             eptype == USB_ENDPOINT_XFER_BULK)) {
 +            /*
 +             * for ctrl/bulk, automatically retry on NAK,
 +             * but send the interrupt anyway
 +             */
 +            intr &= ~HCINTMSK_RESERVED14_31;
 +            s->hreg1[index + 2] |= intr;
 +            do_intr = true;
 +        } else {
 +            intr |= HCINTMSK_CHHLTD;
 +            done = true;
 +        }
 +    }
 +
 +    usb_packet_cleanup(&p->packet);
 +
 +    if (done) {
 +        hcchar &= ~HCCHAR_CHENA;
 +        s->hreg1[index] = hcchar;
 +        if (!(intr & HCINTMSK_CHHLTD)) {
 +            intr |= HCINTMSK_CHHLTD | HCINTMSK_XFERCOMPL;
 +        }
 +        intr &= ~HCINTMSK_RESERVED14_31;
 +        s->hreg1[index + 2] |= intr;
 +        p->needs_service = false;
 +        trace_usb_dwc2_packet_done(pstatus[stsidx], actual, len, pcnt);
 +        dwc2_update_hc_irq(s, index);
 +        return;
 +    }
 +
 +    p->devadr = devadr;
 +    p->epnum = epnum;
 +    p->epdir = epdir;
 +    p->mps = mps;
 +    p->pid = pid;
 +    p->index = index;
 +    p->pcnt = pcnt;
 +    p->len = len;
 +    p->needs_service = true;
 +    trace_usb_dwc2_packet_next(pstatus[stsidx], len, pcnt);
 +    if (do_intr) {
 +        dwc2_update_hc_irq(s, index);
 +    }
 +}
 +
 +/* Attach or detach a device on root hub */
 +
 +static const char *speeds[] = {
 +    "low", "full", "high"
 +};
 +
 +static void dwc2_attach(USBPort *port)
 +{
 +    DWC2State *s = port->opaque;
 +    int hispd = 0;
 +
 +    trace_usb_dwc2_attach(port);
 +    assert(port->index == 0);
 +
 +    if (!port->dev || !port->dev->attached) {
 +        return;
 +    }
 +
 +    assert(port->dev->speed <= USB_SPEED_HIGH);
 +    trace_usb_dwc2_attach_speed(speeds[port->dev->speed]);
 +    s->hprt0 &= ~HPRT0_SPD_MASK;
 +
 +    switch (port->dev->speed) {
 +    case USB_SPEED_LOW:
 +        s->hprt0 |= HPRT0_SPD_LOW_SPEED << HPRT0_SPD_SHIFT;
 +        break;
 +    case USB_SPEED_FULL:
 +        s->hprt0 |= HPRT0_SPD_FULL_SPEED << HPRT0_SPD_SHIFT;
 +        break;
 +    case USB_SPEED_HIGH:
 +        s->hprt0 |= HPRT0_SPD_HIGH_SPEED << HPRT0_SPD_SHIFT;
 +        hispd = 1;
 +        break;
 +    }
 +
 +    if (hispd) {
 +        s->usb_frame_time = NANOSECONDS_PER_SECOND / 8000;        /* 125000 */
 +        if (NANOSECONDS_PER_SECOND >= USB_HZ_HS) {
 +            s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_HS; /* 10.4 */
 +        } else {
 +            s->usb_bit_time = 1;
 +        }
 +    } else {
 +        s->usb_frame_time = NANOSECONDS_PER_SECOND / 1000;        /* 1000000 */
 +        if (NANOSECONDS_PER_SECOND >= USB_HZ_FS) {
 +            s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_FS; /* 83.3 */
 +        } else {
 +            s->usb_bit_time = 1;
 +        }
 +    }
 +
 +    s->fi = USB_FRMINTVL - 1;
 +    s->hprt0 |= HPRT0_CONNDET | HPRT0_CONNSTS;
 +
 +    dwc2_bus_start(s);
 +    dwc2_raise_global_irq(s, GINTSTS_PRTINT);
 +}
 +
 +static void dwc2_detach(USBPort *port)
 +{
 +    DWC2State *s = port->opaque;
 +
 +    trace_usb_dwc2_detach(port);
 +    assert(port->index == 0);
 +
 +    dwc2_bus_stop(s);
 +
 +    s->hprt0 &= ~(HPRT0_SPD_MASK | HPRT0_SUSP | HPRT0_ENA | HPRT0_CONNSTS);
 +    s->hprt0 |= HPRT0_CONNDET | HPRT0_ENACHG;
 +
 +    dwc2_raise_global_irq(s, GINTSTS_PRTINT);
 +}
 +
 +static void dwc2_child_detach(USBPort *port, USBDevice *child)
 +{
 +    trace_usb_dwc2_child_detach(port, child);
 +    assert(port->index == 0);
 +}
 +
 +static void dwc2_wakeup(USBPort *port)
 +{
 +    DWC2State *s = port->opaque;
 +
 +    trace_usb_dwc2_wakeup(port);
 +    assert(port->index == 0);
 +
 +    if (s->hprt0 & HPRT0_SUSP) {
 +        s->hprt0 |= HPRT0_RES;
 +        dwc2_raise_global_irq(s, GINTSTS_PRTINT);
 +    }
 +
 +    qemu_bh_schedule(s->async_bh);
 +}
 +
 +static void dwc2_async_packet_complete(USBPort *port, USBPacket *packet)
 +{
 +    DWC2State *s = port->opaque;
 +    DWC2Packet *p;
 +    USBDevice *dev;
 +    USBEndpoint *ep;
 +
 +    assert(port->index == 0);
 +    p = container_of(packet, DWC2Packet, packet);
 +    dev = dwc2_find_device(s, p->devadr);
 +    ep = usb_ep_get(dev, p->pid, p->epnum);
 +    trace_usb_dwc2_async_packet_complete(port, packet, p->index >> 3, dev,
 +                                         p->epnum, dirs[p->epdir], p->len);
 +    assert(p->async == DWC2_ASYNC_INFLIGHT);
 +
 +    if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
 +        usb_cancel_packet(packet);
 +        usb_packet_cleanup(packet);
 +        return;
 +    }
 +
 +    dwc2_handle_packet(s, p->devadr, dev, ep, p->index, false);
 +
 +    p->async = DWC2_ASYNC_FINISHED;
 +    qemu_bh_schedule(s->async_bh);
 +}
 +
 +static USBPortOps dwc2_port_ops = {
 +    .attach = dwc2_attach,
 +    .detach = dwc2_detach,
 +    .child_detach = dwc2_child_detach,
 +    .wakeup = dwc2_wakeup,
 +    .complete = dwc2_async_packet_complete,
 +};
 +
 +static uint32_t dwc2_get_frame_remaining(DWC2State *s)
 +{
 +    uint32_t fr = 0;
 +    int64_t tks;
 +
 +    tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->sof_time;
 +    if (tks < 0) {
 +        tks = 0;
 +    }
 +
 +    /* avoid muldiv if possible */
 +    if (tks >= s->usb_frame_time) {
 +        goto out;
 +    }
 +    if (tks < s->usb_bit_time) {
 +        fr = s->fi;
 +        goto out;
 +    }
 +
 +    /* tks = number of ns since SOF, divided by 83 (fs) or 10 (hs) */
 +    tks = tks / s->usb_bit_time;
 +    if (tks >= (int64_t)s->fi) {
 +        goto out;
 +    }
 +
 +    /* remaining = frame interval minus tks */
 +    fr = (uint32_t)((int64_t)s->fi - tks);
 +
 +out:
 +    return fr;
 +}
 +
 +static void dwc2_work_bh(void *opaque)
 +{
 +    DWC2State *s = opaque;
 +    DWC2Packet *p;
 +    USBDevice *dev;
 +    USBEndpoint *ep;
 +    int64_t t_now, expire_time;
 +    int chan;
 +    bool found = false;
 +
 +    trace_usb_dwc2_work_bh();
 +    if (s->working) {
 +        return;
 +    }
 +    s->working = true;
 +
 +    t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 +    chan = s->next_chan;
 +
 +    do {
 +        p = &s->packet[chan];
 +        if (p->needs_service) {
 +            dev = dwc2_find_device(s, p->devadr);
 +            ep = usb_ep_get(dev, p->pid, p->epnum);
 +            trace_usb_dwc2_work_bh_service(s->next_chan, chan, dev, p->epnum);
 +            dwc2_handle_packet(s, p->devadr, dev, ep, p->index, true);
 +            found = true;
 +        }
 +        if (++chan == DWC2_NB_CHAN) {
 +            chan = 0;
 +        }
 +        if (found) {
 +            s->next_chan = chan;
 +            trace_usb_dwc2_work_bh_next(chan);
 +        }
 +    } while (chan != s->next_chan);
 +
 +    if (found) {
 +        expire_time = t_now + NANOSECONDS_PER_SECOND / 4000;
 +        timer_mod(s->frame_timer, expire_time);
 +    }
 +    s->working = false;
 +}
 +
 +static void dwc2_enable_chan(DWC2State *s,  uint32_t index)
 +{
 +    USBDevice *dev;
 +    USBEndpoint *ep;
 +    uint32_t hcchar;
 +    uint32_t hctsiz;
 +    uint32_t devadr, epnum, epdir, eptype, pid, len;
 +    DWC2Packet *p;
 +
 +    assert((index >> 3) < DWC2_NB_CHAN);
 +    p = &s->packet[index >> 3];
 +    hcchar = s->hreg1[index];
 +    hctsiz = s->hreg1[index + 4];
 +    devadr = get_field(hcchar, HCCHAR_DEVADDR);
 +    epnum = get_field(hcchar, HCCHAR_EPNUM);
 +    epdir = get_bit(hcchar, HCCHAR_EPDIR);
 +    eptype = get_field(hcchar, HCCHAR_EPTYPE);
 +    pid = get_field(hctsiz, TSIZ_SC_MC_PID);
 +    len = get_field(hctsiz, TSIZ_XFERSIZE);
 +
 +    dev = dwc2_find_device(s, devadr);
 +
 +    trace_usb_dwc2_enable_chan(index >> 3, dev, &p->packet, epnum);
 +    if (dev == NULL) {
 +        return;
 +    }
 +
 +    if (eptype == USB_ENDPOINT_XFER_CONTROL && pid == TSIZ_SC_MC_PID_SETUP) {
 +        pid = USB_TOKEN_SETUP;
 +    } else {
 +        pid = epdir ? USB_TOKEN_IN : USB_TOKEN_OUT;
 +    }
 +
 +    ep = usb_ep_get(dev, pid, epnum);
 +
 +    /*
 +     * Hack: Networking doesn't like us delivering large transfers, it kind
 +     * of works but the latency is horrible. So if the transfer is <= the mtu
 +     * size, we take that as a hint that this might be a network transfer,
 +     * and do the transfer packet-by-packet.
 +     */
-+    if (element_size < 8) {
++    if (len > 1536) {
-+        ofs ^= 8 - element_size;
++        p->small = false;
-+    }
++    } else {
-+#endif
++        p->small = true;
-+    return neon_reg_offset(reg, 0) + ofs;
++    }
-+}
++
-+
++    dwc2_handle_packet(s, devadr, dev, ep, index, true);
-+static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
++    qemu_bh_schedule(s->async_bh);
-+{
++}
-+    long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
++
-+
++static const char *glbregnm[] = {
-+    switch (mop) {
++    "GOTGCTL  ", "GOTGINT  ", "GAHBCFG  ", "GUSBCFG  ", "GRSTCTL  ",
-+    case MO_UB:
++    "GINTSTS  ", "GINTMSK  ", "GRXSTSR  ", "GRXSTSP  ", "GRXFSIZ  ",
-+        tcg_gen_ld8u_i32(var, cpu_env, offset);
++    "GNPTXFSIZ", "GNPTXSTS ", "GI2CCTL  ", "GPVNDCTL ", "GGPIO    ",
-+        break;
++    "GUID     ", "GSNPSID  ", "GHWCFG1  ", "GHWCFG2  ", "GHWCFG3  ",
-+    case MO_UW:
++    "GHWCFG4  ", "GLPMCFG  ", "GPWRDN   ", "GDFIFOCFG", "GADPCTL  ",
-+        tcg_gen_ld16u_i32(var, cpu_env, offset);
++    "GREFCLK  ", "GINTMSK2 ", "GINTSTS2 "
-+        break;
++};
-+    case MO_UL:
++
-+        tcg_gen_ld_i32(var, cpu_env, offset);
++static uint64_t dwc2_glbreg_read(void *ptr, hwaddr addr, int index,
 +                                 unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    uint32_t val;
 +
 +    assert(addr <= GINTSTS2);
 +    val = s->glbreg[index];
 +
 +    switch (addr) {
 +    case GRSTCTL:
 +        /* clear any self-clearing bits that were set */
 +        val &= ~(GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH | GRSTCTL_IN_TKNQ_FLSH |
 +                 GRSTCTL_FRMCNTRRST | GRSTCTL_HSFTRST | GRSTCTL_CSFTRST);
 +        s->glbreg[index] = val;
 +        break;
 +    default:
 +        break;
 +    }
 +
 +    trace_usb_dwc2_glbreg_read(addr, glbregnm[index], val);
 +    return val;
 +}
 +
 +static void dwc2_glbreg_write(void *ptr, hwaddr addr, int index, uint64_t val,
 +                              unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    uint64_t orig = val;
 +    uint32_t *mmio;
 +    uint32_t old;
 +    int iflg = 0;
 +
 +    assert(addr <= GINTSTS2);
 +    mmio = &s->glbreg[index];
 +    old = *mmio;
 +
 +    switch (addr) {
 +    case GOTGCTL:
 +        /* don't allow setting of read-only bits */
 +        val &= ~(GOTGCTL_MULT_VALID_BC_MASK | GOTGCTL_BSESVLD |
 +                 GOTGCTL_ASESVLD | GOTGCTL_DBNC_SHORT | GOTGCTL_CONID_B |
 +                 GOTGCTL_HSTNEGSCS | GOTGCTL_SESREQSCS);
 +        /* don't allow clearing of read-only bits */
 +        val |= old & (GOTGCTL_MULT_VALID_BC_MASK | GOTGCTL_BSESVLD |
 +                      GOTGCTL_ASESVLD | GOTGCTL_DBNC_SHORT | GOTGCTL_CONID_B |
 +                      GOTGCTL_HSTNEGSCS | GOTGCTL_SESREQSCS);
 +        break;
 +    case GAHBCFG:
 +        if ((val & GAHBCFG_GLBL_INTR_EN) && !(old & GAHBCFG_GLBL_INTR_EN)) {
 +            iflg = 1;
 +        }
 +        break;
 +    case GRSTCTL:
 +        val |= GRSTCTL_AHBIDLE;
 +        val &= ~GRSTCTL_DMAREQ;
 +        if (!(old & GRSTCTL_TXFFLSH) && (val & GRSTCTL_TXFFLSH)) {
 +                /* TODO - TX fifo flush */
 +            qemu_log_mask(LOG_UNIMP, "Tx FIFO flush not implemented\n");
 +        }
 +        if (!(old & GRSTCTL_RXFFLSH) && (val & GRSTCTL_RXFFLSH)) {
 +                /* TODO - RX fifo flush */
 +            qemu_log_mask(LOG_UNIMP, "Rx FIFO flush not implemented\n");
 +        }
 +        if (!(old & GRSTCTL_IN_TKNQ_FLSH) && (val & GRSTCTL_IN_TKNQ_FLSH)) {
 +                /* TODO - device IN token queue flush */
 +            qemu_log_mask(LOG_UNIMP, "Token queue flush not implemented\n");
 +        }
 +        if (!(old & GRSTCTL_FRMCNTRRST) && (val & GRSTCTL_FRMCNTRRST)) {
 +                /* TODO - host frame counter reset */
 +            qemu_log_mask(LOG_UNIMP, "Frame counter reset not implemented\n");
 +        }
 +        if (!(old & GRSTCTL_HSFTRST) && (val & GRSTCTL_HSFTRST)) {
 +                /* TODO - host soft reset */
 +            qemu_log_mask(LOG_UNIMP, "Host soft reset not implemented\n");
 +        }
 +        if (!(old & GRSTCTL_CSFTRST) && (val & GRSTCTL_CSFTRST)) {
 +                /* TODO - core soft reset */
 +            qemu_log_mask(LOG_UNIMP, "Core soft reset not implemented\n");
 +        }
 +        /* don't allow clearing of self-clearing bits */
 +        val |= old & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH |
 +                      GRSTCTL_IN_TKNQ_FLSH | GRSTCTL_FRMCNTRRST |
 +                      GRSTCTL_HSFTRST | GRSTCTL_CSFTRST);
 +        break;
 +    case GINTSTS:
 +        /* clear the write-1-to-clear bits */
 +        val |= ~old;
 +        val = ~val;
 +        /* don't allow clearing of read-only bits */
 +        val |= old & (GINTSTS_PTXFEMP | GINTSTS_HCHINT | GINTSTS_PRTINT |
 +                      GINTSTS_OEPINT | GINTSTS_IEPINT | GINTSTS_GOUTNAKEFF |
 +                      GINTSTS_GINNAKEFF | GINTSTS_NPTXFEMP | GINTSTS_RXFLVL |
 +                      GINTSTS_OTGINT | GINTSTS_CURMODE_HOST);
 +        iflg = 1;
 +        break;
 +    case GINTMSK:
 +        iflg = 1;
 +        break;
 +    default:
 +        break;
 +    }
 +
 +    trace_usb_dwc2_glbreg_write(addr, glbregnm[index], orig, old, val);
 +    *mmio = val;
 +
 +    if (iflg) {
 +        dwc2_update_irq(s);
 +    }
 +}
 +
 +static uint64_t dwc2_fszreg_read(void *ptr, hwaddr addr, int index,
 +                                 unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    uint32_t val;
 +
 +    assert(addr == HPTXFSIZ);
 +    val = s->fszreg[index];
 +
 +    trace_usb_dwc2_fszreg_read(addr, val);
 +    return val;
 +}
 +
 +static void dwc2_fszreg_write(void *ptr, hwaddr addr, int index, uint64_t val,
 +                              unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    uint64_t orig = val;
 +    uint32_t *mmio;
 +    uint32_t old;
 +
 +    assert(addr == HPTXFSIZ);
 +    mmio = &s->fszreg[index];
 +    old = *mmio;
 +
 +    trace_usb_dwc2_fszreg_write(addr, orig, old, val);
 +    *mmio = val;
 +}
 +
 +static const char *hreg0nm[] = {
 +    "HCFG     ", "HFIR     ", "HFNUM    ", "<rsvd>   ", "HPTXSTS  ",
 +    "HAINT    ", "HAINTMSK ", "HFLBADDR ", "<rsvd>   ", "<rsvd>   ",
 +    "<rsvd>   ", "<rsvd>   ", "<rsvd>   ", "<rsvd>   ", "<rsvd>   ",
 +    "<rsvd>   ", "HPRT0    "
 +};
 +
 +static uint64_t dwc2_hreg0_read(void *ptr, hwaddr addr, int index,
 +                                unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    uint32_t val;
 +
 +    assert(addr >= HCFG && addr <= HPRT0);
 +    val = s->hreg0[index];
 +
 +    switch (addr) {
 +    case HFNUM:
 +        val = (dwc2_get_frame_remaining(s) << HFNUM_FRREM_SHIFT) |
 +              (s->hfnum << HFNUM_FRNUM_SHIFT);
 +        break;
 +    default:
 +        break;
 +    }
 +
 +    trace_usb_dwc2_hreg0_read(addr, hreg0nm[index], val);
 +    return val;
 +}
 +
 +static void dwc2_hreg0_write(void *ptr, hwaddr addr, int index, uint64_t val,
 +                             unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    USBDevice *dev = s->uport.dev;
 +    uint64_t orig = val;
 +    uint32_t *mmio;
 +    uint32_t tval, told, old;
 +    int prst = 0;
 +    int iflg = 0;
 +
 +    assert(addr >= HCFG && addr <= HPRT0);
 +    mmio = &s->hreg0[index];
 +    old = *mmio;
 +
 +    switch (addr) {
 +    case HFIR:
 +        break;
 +    case HFNUM:
 +    case HPTXSTS:
 +    case HAINT:
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: write to read-only register\n",
 +                      __func__);
 +        return;
 +    case HAINTMSK:
 +        val &= 0xffff;
 +        break;
 +    case HPRT0:
 +        /* don't allow clearing of read-only bits */
 +        val |= old & (HPRT0_SPD_MASK | HPRT0_LNSTS_MASK | HPRT0_OVRCURRACT |
 +                      HPRT0_CONNSTS);
 +        /* don't allow clearing of self-clearing bits */
 +        val |= old & (HPRT0_SUSP | HPRT0_RES);
 +        /* don't allow setting of self-setting bits */
 +        if (!(old & HPRT0_ENA) && (val & HPRT0_ENA)) {
 +            val &= ~HPRT0_ENA;
 +        }
 +        /* clear the write-1-to-clear bits */
 +        tval = val & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
 +                      HPRT0_CONNDET);
 +        told = old & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
 +                      HPRT0_CONNDET);
 +        tval |= ~told;
 +        tval = ~tval;
 +        tval &= (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
 +                 HPRT0_CONNDET);
 +        val &= ~(HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
 +                 HPRT0_CONNDET);
 +        val |= tval;
 +        if (!(val & HPRT0_RST) && (old & HPRT0_RST)) {
 +            if (dev && dev->attached) {
 +                val |= HPRT0_ENA | HPRT0_ENACHG;
 +                prst = 1;
 +            }
 +        }
 +        if (val & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_CONNDET)) {
 +            iflg = 1;
 +        } else {
 +            iflg = -1;
 +        }
 +        break;
 +    default:
 +        break;
 +    }
 +
 +    if (prst) {
 +        trace_usb_dwc2_hreg0_write(addr, hreg0nm[index], orig, old,
 +                                   val & ~HPRT0_CONNDET);
 +        trace_usb_dwc2_hreg0_action("call usb_port_reset");
 +        usb_port_reset(&s->uport);
 +        val &= ~HPRT0_CONNDET;
 +    } else {
 +        trace_usb_dwc2_hreg0_write(addr, hreg0nm[index], orig, old, val);
 +    }
 +
 +    *mmio = val;
 +
 +    if (iflg > 0) {
 +        trace_usb_dwc2_hreg0_action("enable PRTINT");
 +        dwc2_raise_global_irq(s, GINTSTS_PRTINT);
 +    } else if (iflg < 0) {
 +        trace_usb_dwc2_hreg0_action("disable PRTINT");
 +        dwc2_lower_global_irq(s, GINTSTS_PRTINT);
 +    }
 +}
 +
 +static const char *hreg1nm[] = {
 +    "HCCHAR  ", "HCSPLT  ", "HCINT   ", "HCINTMSK", "HCTSIZ  ", "HCDMA   ",
 +    "<rsvd>  ", "HCDMAB  "
 +};
 +
 +static uint64_t dwc2_hreg1_read(void *ptr, hwaddr addr, int index,
 +                                unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    uint32_t val;
 +
 +    assert(addr >= HCCHAR(0) && addr <= HCDMAB(DWC2_NB_CHAN - 1));
 +    val = s->hreg1[index];
 +
 +    trace_usb_dwc2_hreg1_read(addr, hreg1nm[index & 7], addr >> 5, val);
 +    return val;
 +}
 +
 +static void dwc2_hreg1_write(void *ptr, hwaddr addr, int index, uint64_t val,
 +                             unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    uint64_t orig = val;
 +    uint32_t *mmio;
 +    uint32_t old;
 +    int iflg = 0;
 +    int enflg = 0;
 +    int disflg = 0;
 +
 +    assert(addr >= HCCHAR(0) && addr <= HCDMAB(DWC2_NB_CHAN - 1));
 +    mmio = &s->hreg1[index];
 +    old = *mmio;
 +
 +    switch (HSOTG_REG(0x500) + (addr & 0x1c)) {
 +    case HCCHAR(0):
 +        if ((val & HCCHAR_CHDIS) && !(old & HCCHAR_CHDIS)) {
 +            val &= ~(HCCHAR_CHENA | HCCHAR_CHDIS);
 +            disflg = 1;
 +        } else {
 +            val |= old & HCCHAR_CHDIS;
 +            if ((val & HCCHAR_CHENA) && !(old & HCCHAR_CHENA)) {
 +                val &= ~HCCHAR_CHDIS;
 +                enflg = 1;
 +            } else {
 +                val |= old & HCCHAR_CHENA;
 +            }
 +        }
 +        break;
 +    case HCINT(0):
 +        /* clear the write-1-to-clear bits */
 +        val |= ~old;
 +        val = ~val;
 +        val &= ~HCINTMSK_RESERVED14_31;
 +        iflg = 1;
 +        break;
 +    case HCINTMSK(0):
 +        val &= ~HCINTMSK_RESERVED14_31;
 +        iflg = 1;
 +        break;
 +    case HCDMAB(0):
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: write to read-only register\n",
 +                      __func__);
 +        return;
 +    default:
 +        break;
 +    }
 +
 +    trace_usb_dwc2_hreg1_write(addr, hreg1nm[index & 7], index >> 3, orig,
 +                               old, val);
 +    *mmio = val;
 +
 +    if (disflg) {
 +        /* set ChHltd in HCINT */
 +        s->hreg1[(index & ~7) + 2] |= HCINTMSK_CHHLTD;
 +        iflg = 1;
 +    }
 +
 +    if (enflg) {
 +        dwc2_enable_chan(s, index & ~7);
 +    }
 +
 +    if (iflg) {
 +        dwc2_update_hc_irq(s, index & ~7);
 +    }
 +}
 +
 +static const char *pcgregnm[] = {
 +        "PCGCTL   ", "PCGCCTL1 "
 +};
 +
 +static uint64_t dwc2_pcgreg_read(void *ptr, hwaddr addr, int index,
 +                                 unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    uint32_t val;
 +
 +    assert(addr >= PCGCTL && addr <= PCGCCTL1);
 +    val = s->pcgreg[index];
 +
 +    trace_usb_dwc2_pcgreg_read(addr, pcgregnm[index], val);
 +    return val;
 +}
 +
 +static void dwc2_pcgreg_write(void *ptr, hwaddr addr, int index,
 +                              uint64_t val, unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    uint64_t orig = val;
 +    uint32_t *mmio;
 +    uint32_t old;
 +
 +    assert(addr >= PCGCTL && addr <= PCGCCTL1);
 +    mmio = &s->pcgreg[index];
 +    old = *mmio;
 +
 +    trace_usb_dwc2_pcgreg_write(addr, pcgregnm[index], orig, old, val);
 +    *mmio = val;
 +}
 +
 +static uint64_t dwc2_hsotg_read(void *ptr, hwaddr addr, unsigned size)
 +{
 +    uint64_t val;
 +
 +    switch (addr) {
 +    case HSOTG_REG(0x000) ... HSOTG_REG(0x0fc):
 +        val = dwc2_glbreg_read(ptr, addr, (addr - HSOTG_REG(0x000)) >> 2, size);
 +        break;
 +    case HSOTG_REG(0x100):
 +        val = dwc2_fszreg_read(ptr, addr, (addr - HSOTG_REG(0x100)) >> 2, size);
 +        break;
 +    case HSOTG_REG(0x104) ... HSOTG_REG(0x3fc):
 +        /* Gadget-mode registers, just return 0 for now */
 +        val = 0;
 +        break;
 +    case HSOTG_REG(0x400) ... HSOTG_REG(0x4fc):
 +        val = dwc2_hreg0_read(ptr, addr, (addr - HSOTG_REG(0x400)) >> 2, size);
 +        break;
 +    case HSOTG_REG(0x500) ... HSOTG_REG(0x7fc):
 +        val = dwc2_hreg1_read(ptr, addr, (addr - HSOTG_REG(0x500)) >> 2, size);
 +        break;
 +    case HSOTG_REG(0x800) ... HSOTG_REG(0xdfc):
 +        /* Gadget-mode registers, just return 0 for now */
 +        val = 0;
 +        break;
 +    case HSOTG_REG(0xe00) ... HSOTG_REG(0xffc):
 +        val = dwc2_pcgreg_read(ptr, addr, (addr - HSOTG_REG(0xe00)) >> 2, size);
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
-+}
++
-+
++    return val;
-+static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop)
++}
-+{
++
-+    long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
++static void dwc2_hsotg_write(void *ptr, hwaddr addr, uint64_t val,
-+
++                             unsigned size)
-+    switch (mop) {
++{
-+    case MO_UB:
++    switch (addr) {
-+        tcg_gen_ld8u_i64(var, cpu_env, offset);
++    case HSOTG_REG(0x000) ... HSOTG_REG(0x0fc):
-+        break;
++        dwc2_glbreg_write(ptr, addr, (addr - HSOTG_REG(0x000)) >> 2, val, size);
-+    case MO_UW:
++        break;
-+        tcg_gen_ld16u_i64(var, cpu_env, offset);
++    case HSOTG_REG(0x100):
-+        break;
++        dwc2_fszreg_write(ptr, addr, (addr - HSOTG_REG(0x100)) >> 2, val, size);
-+    case MO_UL:
++        break;
-+        tcg_gen_ld32u_i64(var, cpu_env, offset);
++    case HSOTG_REG(0x104) ... HSOTG_REG(0x3fc):
-+        break;
++        /* Gadget-mode registers, do nothing for now */
-+    case MO_Q:
++        break;
-+        tcg_gen_ld_i64(var, cpu_env, offset);
++    case HSOTG_REG(0x400) ... HSOTG_REG(0x4fc):
 +        dwc2_hreg0_write(ptr, addr, (addr - HSOTG_REG(0x400)) >> 2, val, size);
 +        break;
 +    case HSOTG_REG(0x500) ... HSOTG_REG(0x7fc):
 +        dwc2_hreg1_write(ptr, addr, (addr - HSOTG_REG(0x500)) >> 2, val, size);
 +        break;
 +    case HSOTG_REG(0x800) ... HSOTG_REG(0xdfc):
 +        /* Gadget-mode registers, do nothing for now */
 +        break;
 +    case HSOTG_REG(0xe00) ... HSOTG_REG(0xffc):
 +        dwc2_pcgreg_write(ptr, addr, (addr - HSOTG_REG(0xe00)) >> 2, val, size);
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
-+static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var)
++static const MemoryRegionOps dwc2_mmio_hsotg_ops = {
-+{
++    .read = dwc2_hsotg_read,
-+    long offset = neon_element_offset(reg, ele, size);
++    .write = dwc2_hsotg_write,
-+
++    .impl.min_access_size = 4,
-+    switch (size) {
++    .impl.max_access_size = 4,
-+    case MO_8:
++    .endianness = DEVICE_LITTLE_ENDIAN,
-+        tcg_gen_st8_i32(var, cpu_env, offset);
++};
-+        break;
++
-+    case MO_16:
++static uint64_t dwc2_hreg2_read(void *ptr, hwaddr addr, unsigned size)
-+        tcg_gen_st16_i32(var, cpu_env, offset);
++{
-+        break;
++    /* TODO - implement FIFOs to support slave mode */
-+    case MO_32:
++    trace_usb_dwc2_hreg2_read(addr, addr >> 12, 0);
-+        tcg_gen_st_i32(var, cpu_env, offset);
++    qemu_log_mask(LOG_UNIMP, "FIFO read not implemented\n");
-+        break;
++    return 0;
-+    default:
++}
-+        g_assert_not_reached();
++
-+    }
++static void dwc2_hreg2_write(void *ptr, hwaddr addr, uint64_t val,
-+}
++                             unsigned size)
-+
++{
-+static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var)
++    uint64_t orig = val;
-+{
++
-+    long offset = neon_element_offset(reg, ele, size);
++    /* TODO - implement FIFOs to support slave mode */
-+
++    trace_usb_dwc2_hreg2_write(addr, addr >> 12, orig, 0, val);
-+    switch (size) {
++    qemu_log_mask(LOG_UNIMP, "FIFO write not implemented\n");
-+    case MO_8:
++}
-+        tcg_gen_st8_i64(var, cpu_env, offset);
++
-+        break;
++static const MemoryRegionOps dwc2_mmio_hreg2_ops = {
-+    case MO_16:
++    .read = dwc2_hreg2_read,
-+        tcg_gen_st16_i64(var, cpu_env, offset);
++    .write = dwc2_hreg2_write,
-+        break;
++    .impl.min_access_size = 4,
-+    case MO_32:
++    .impl.max_access_size = 4,
-+        tcg_gen_st32_i64(var, cpu_env, offset);
++    .endianness = DEVICE_LITTLE_ENDIAN,
-+        break;
++};
-+    case MO_64:
++
-+        tcg_gen_st_i64(var, cpu_env, offset);
++static void dwc2_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
-+        break;
++                                 unsigned int stream)
-+    default:
++{
-+        g_assert_not_reached();
++    DWC2State *s = container_of(bus, DWC2State, bus);
-+    }
++
-+}
++    trace_usb_dwc2_wakeup_endpoint(ep, stream);
 +
- static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
++    /* TODO - do something here? */
- {
++    qemu_bh_schedule(s->async_bh);
-     int opr_sz;
++}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
++
 +static USBBusOps dwc2_bus_ops = {
 +    .wakeup_endpoint = dwc2_wakeup_endpoint,
 +};
 +
 +static void dwc2_work_timer(void *opaque)
 +{
 +    DWC2State *s = opaque;
 +
 +    trace_usb_dwc2_work_timer();
 +    qemu_bh_schedule(s->async_bh);
 +}
 +
 +static void dwc2_reset_enter(Object *obj, ResetType type)
 +{
 +    DWC2Class *c = DWC2_GET_CLASS(obj);
 +    DWC2State *s = DWC2_USB(obj);
 +    int i;
 +
 +    trace_usb_dwc2_reset_enter();
 +
 +    if (c->parent_phases.enter) {
 +        c->parent_phases.enter(obj, type);
 +    }
 +
 +    timer_del(s->frame_timer);
 +    qemu_bh_cancel(s->async_bh);
 +
 +    if (s->uport.dev && s->uport.dev->attached) {
 +        usb_detach(&s->uport);
 +    }
 +
 +    dwc2_bus_stop(s);
 +
 +    s->gotgctl = GOTGCTL_BSESVLD | GOTGCTL_ASESVLD | GOTGCTL_CONID_B;
 +    s->gotgint = 0;
 +    s->gahbcfg = 0;
 +    s->gusbcfg = 5 << GUSBCFG_USBTRDTIM_SHIFT;
 +    s->grstctl = GRSTCTL_AHBIDLE;
 +    s->gintsts = GINTSTS_CONIDSTSCHNG | GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP |
 +                 GINTSTS_CURMODE_HOST;
 +    s->gintmsk = 0;
 +    s->grxstsr = 0;
 +    s->grxstsp = 0;
 +    s->grxfsiz = 1024;
 +    s->gnptxfsiz = 1024 << FIFOSIZE_DEPTH_SHIFT;
 +    s->gnptxsts = (4 << FIFOSIZE_DEPTH_SHIFT) | 1024;
 +    s->gi2cctl = GI2CCTL_I2CDATSE0 | GI2CCTL_ACK;
 +    s->gpvndctl = 0;
 +    s->ggpio = 0;
 +    s->guid = 0;
 +    s->gsnpsid = 0x4f54294a;
 +    s->ghwcfg1 = 0;
 +    s->ghwcfg2 = (8 << GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT) |
 +                 (4 << GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT) |
 +                 (4 << GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT) |
 +                 GHWCFG2_DYNAMIC_FIFO |
 +                 GHWCFG2_PERIO_EP_SUPPORTED |
 +                 ((DWC2_NB_CHAN - 1) << GHWCFG2_NUM_HOST_CHAN_SHIFT) |
 +                 (GHWCFG2_INT_DMA_ARCH << GHWCFG2_ARCHITECTURE_SHIFT) |
 +                 (GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST << GHWCFG2_OP_MODE_SHIFT);
 +    s->ghwcfg3 = (4096 << GHWCFG3_DFIFO_DEPTH_SHIFT) |
 +                 (4 << GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT) |
 +                 (4 << GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT);
 +    s->ghwcfg4 = 0;
 +    s->glpmcfg = 0;
 +    s->gpwrdn = GPWRDN_PWRDNRSTN;
 +    s->gdfifocfg = 0;
 +    s->gadpctl = 0;
 +    s->grefclk = 0;
 +    s->gintmsk2 = 0;
 +    s->gintsts2 = 0;
 +
 +    s->hptxfsiz = 500 << FIFOSIZE_DEPTH_SHIFT;
 +
 +    s->hcfg = 2 << HCFG_RESVALID_SHIFT;
 +    s->hfir = 60000;
 +    s->hfnum = 0x3fff;
 +    s->hptxsts = (16 << TXSTS_QSPCAVAIL_SHIFT) | 32768;
 +    s->haint = 0;
 +    s->haintmsk = 0;
 +    s->hprt0 = 0;
 +
 +    memset(s->hreg1, 0, sizeof(s->hreg1));
 +    memset(s->pcgreg, 0, sizeof(s->pcgreg));
 +
 +    s->sof_time = 0;
 +    s->frame_number = 0;
 +    s->fi = USB_FRMINTVL - 1;
 +    s->next_chan = 0;
 +    s->working = false;
 +
 +    for (i = 0; i < DWC2_NB_CHAN; i++) {
 +        s->packet[i].needs_service = false;
 +    }
 +}
 +
 +static void dwc2_reset_hold(Object *obj)
 +{
 +    DWC2Class *c = DWC2_GET_CLASS(obj);
 +    DWC2State *s = DWC2_USB(obj);
 +
 +    trace_usb_dwc2_reset_hold();
 +
 +    if (c->parent_phases.hold) {
 +        c->parent_phases.hold(obj);
 +    }
 +
 +    dwc2_update_irq(s);
 +}
 +
 +static void dwc2_reset_exit(Object *obj)
 +{
 +    DWC2Class *c = DWC2_GET_CLASS(obj);
 +    DWC2State *s = DWC2_USB(obj);
 +
 +    trace_usb_dwc2_reset_exit();
 +
 +    if (c->parent_phases.exit) {
 +        c->parent_phases.exit(obj);
 +    }
 +
 +    s->hprt0 = HPRT0_PWR;
 +    if (s->uport.dev && s->uport.dev->attached) {
 +        usb_attach(&s->uport);
 +        usb_device_reset(s->uport.dev);
 +    }
 +}
 +
 +static void dwc2_realize(DeviceState *dev, Error **errp)
 +{
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 +    DWC2State *s = DWC2_USB(dev);
 +    Object *obj;
 +    Error *err = NULL;
 +
 +    obj = object_property_get_link(OBJECT(dev), "dma-mr", &err);
 +    if (err) {
 +        error_setg(errp, "dwc2: required dma-mr link not found: %s",
 +                   error_get_pretty(err));
 +        return;
 +    }
 +    assert(obj != NULL);
 +
 +    s->dma_mr = MEMORY_REGION(obj);
 +    address_space_init(&s->dma_as, s->dma_mr, "dwc2");
 +
 +    usb_bus_new(&s->bus, sizeof(s->bus), &dwc2_bus_ops, dev);
 +    usb_register_port(&s->bus, &s->uport, s, 0, &dwc2_port_ops,
 +                      USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL |
 +                      (s->usb_version == 2 ? USB_SPEED_MASK_HIGH : 0));
 +    s->uport.dev = 0;
 +
 +    s->usb_frame_time = NANOSECONDS_PER_SECOND / 1000;          /* 1000000 */
 +    if (NANOSECONDS_PER_SECOND >= USB_HZ_FS) {
 +        s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_FS;   /* 83.3 */
 +    } else {
 +        s->usb_bit_time = 1;
 +    }
 +
 +    s->fi = USB_FRMINTVL - 1;
 +    s->eof_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, dwc2_frame_boundary, s);
 +    s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, dwc2_work_timer, s);
 +    s->async_bh = qemu_bh_new(dwc2_work_bh, s);
 +
 +    sysbus_init_irq(sbd, &s->irq);
 +}
 +
 +static void dwc2_init(Object *obj)
 +{
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 +    DWC2State *s = DWC2_USB(obj);
 +
 +    memory_region_init(&s->container, obj, "dwc2", DWC2_MMIO_SIZE);
 +    sysbus_init_mmio(sbd, &s->container);
 +
 +    memory_region_init_io(&s->hsotg, obj, &dwc2_mmio_hsotg_ops, s,
 +                          "dwc2-io", 4 * KiB);
 +    memory_region_add_subregion(&s->container, 0x0000, &s->hsotg);
 +
 +    memory_region_init_io(&s->fifos, obj, &dwc2_mmio_hreg2_ops, s,
 +                          "dwc2-fifo", 64 * KiB);
 +    memory_region_add_subregion(&s->container, 0x1000, &s->fifos);
 +}
 +
 +static const VMStateDescription vmstate_dwc2_state_packet = {
 +    .name = "dwc2/packet",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32(devadr, DWC2Packet),
 +        VMSTATE_UINT32(epnum, DWC2Packet),
 +        VMSTATE_UINT32(epdir, DWC2Packet),
 +        VMSTATE_UINT32(mps, DWC2Packet),
 +        VMSTATE_UINT32(pid, DWC2Packet),
 +        VMSTATE_UINT32(index, DWC2Packet),
 +        VMSTATE_UINT32(pcnt, DWC2Packet),
 +        VMSTATE_UINT32(len, DWC2Packet),
 +        VMSTATE_INT32(async, DWC2Packet),
 +        VMSTATE_BOOL(small, DWC2Packet),
 +        VMSTATE_BOOL(needs_service, DWC2Packet),
 +        VMSTATE_END_OF_LIST()
 +    },
 +};
 +
 +const VMStateDescription vmstate_dwc2_state = {
 +    .name = "dwc2",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(glbreg, DWC2State,
 +                             DWC2_GLBREG_SIZE / sizeof(uint32_t)),
 +        VMSTATE_UINT32_ARRAY(fszreg, DWC2State,
 +                             DWC2_FSZREG_SIZE / sizeof(uint32_t)),
 +        VMSTATE_UINT32_ARRAY(hreg0, DWC2State,
 +                             DWC2_HREG0_SIZE / sizeof(uint32_t)),
 +        VMSTATE_UINT32_ARRAY(hreg1, DWC2State,
 +                             DWC2_HREG1_SIZE / sizeof(uint32_t)),
 +        VMSTATE_UINT32_ARRAY(pcgreg, DWC2State,
 +                             DWC2_PCGREG_SIZE / sizeof(uint32_t)),
 +
 +        VMSTATE_TIMER_PTR(eof_timer, DWC2State),
 +        VMSTATE_TIMER_PTR(frame_timer, DWC2State),
 +        VMSTATE_INT64(sof_time, DWC2State),
 +        VMSTATE_INT64(usb_frame_time, DWC2State),
 +        VMSTATE_INT64(usb_bit_time, DWC2State),
 +        VMSTATE_UINT32(usb_version, DWC2State),
 +        VMSTATE_UINT16(frame_number, DWC2State),
 +        VMSTATE_UINT16(fi, DWC2State),
 +        VMSTATE_UINT16(next_chan, DWC2State),
 +        VMSTATE_BOOL(working, DWC2State),
 +
 +        VMSTATE_STRUCT_ARRAY(packet, DWC2State, DWC2_NB_CHAN, 1,
 +                             vmstate_dwc2_state_packet, DWC2Packet),
 +        VMSTATE_UINT8_2DARRAY(usb_buf, DWC2State, DWC2_NB_CHAN,
 +                              DWC2_MAX_XFER_SIZE),
 +
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static Property dwc2_usb_properties[] = {
 +    DEFINE_PROP_UINT32("usb_version", DWC2State, usb_version, 2),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void dwc2_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +    DWC2Class *c = DWC2_CLASS(klass);
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
 +
 +    dc->realize = dwc2_realize;
 +    dc->vmsd = &vmstate_dwc2_state;
 +    set_bit(DEVICE_CATEGORY_USB, dc->categories);
 +    device_class_set_props(dc, dwc2_usb_properties);
 +    resettable_class_set_parent_phases(rc, dwc2_reset_enter, dwc2_reset_hold,
 +                                       dwc2_reset_exit, &c->parent_phases);
 +}
 +
 +static const TypeInfo dwc2_usb_type_info = {
 +    .name          = TYPE_DWC2_USB,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(DWC2State),
 +    .instance_init = dwc2_init,
 +    .class_size    = sizeof(DWC2Class),
 +    .class_init    = dwc2_class_init,
 +};
 +
 +static void dwc2_usb_register_types(void)
 +{
 +    type_register_static(&dwc2_usb_type_info);
 +}
 +
 +type_init(dwc2_usb_register_types)
 diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/hw/usb/Kconfig
-+++ b/target/arm/translate.c
++++ b/hw/usb/Kconfig
-@@ -XXX,XX +XXX,XX @@ neon_reg_offset (int reg, int n)
+@@ -XXX,XX +XXX,XX @@ config USB_MUSB
-     return vfp_reg_offset(0, sreg);
+     bool
- }
+     select USB
--/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
++config USB_DWC2
-- * where 0 is the least significant end of the register.
++    bool
-- */
++    default y
--static inline long
++    select USB
--neon_element_offset(int reg, int element, MemOp size)
++
--{
+ config TUSB6010
--    int element_size = 1 << size;
+     bool
--    int ofs = element * element_size;
+     select USB_MUSB
--#ifdef HOST_WORDS_BIGENDIAN
+diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs
--    /* Calculate the offset assuming fully little-endian,
+index XXXXXXX..XXXXXXX 100644
--     * then XOR to account for the order of the 8-byte units.
+--- a/hw/usb/Makefile.objs
--     */
++++ b/hw/usb/Makefile.objs
--    if (element_size < 8) {
+@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_USB_EHCI_SYSBUS) += hcd-ehci-sysbus.o
--        ofs ^= 8 - element_size;
+ common-obj-$(CONFIG_USB_XHCI) += hcd-xhci.o
--    }
+ common-obj-$(CONFIG_USB_XHCI_NEC) += hcd-xhci-nec.o
--#endif
+ common-obj-$(CONFIG_USB_MUSB) += hcd-musb.o
--    return neon_reg_offset(reg, 0) + ofs;
++common-obj-$(CONFIG_USB_DWC2) += hcd-dwc2.o
--}
--
+ common-obj-$(CONFIG_TUSB6010) += tusb6010.o
- static TCGv_i32 neon_load_reg(int reg, int pass)
+ common-obj-$(CONFIG_IMX)      += chipidea.o
- {
+diff --git a/hw/usb/trace-events b/hw/usb/trace-events
-     TCGv_i32 tmp = tcg_temp_new_i32();
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ static TCGv_i32 neon_load_reg(int reg, int pass)
+--- a/hw/usb/trace-events
-     return tmp;
++++ b/hw/usb/trace-events
- }
+@@ -XXX,XX +XXX,XX @@ usb_xhci_xfer_error(void *xfer, uint32_t ret) "%p: ret %d"
+ usb_xhci_unimplemented(const char *item, int nr) "%s (0x%x)"
--static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
+ usb_xhci_enforced_limit(const char *item) "%s"
--{
--    long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
++# hcd-dwc2.c
--
++usb_dwc2_update_irq(uint32_t level) "level=%d"
--    switch (mop) {
++usb_dwc2_raise_global_irq(uint32_t intr) "0x%08x"
--    case MO_UB:
++usb_dwc2_lower_global_irq(uint32_t intr) "0x%08x"
--        tcg_gen_ld8u_i32(var, cpu_env, offset);
++usb_dwc2_raise_host_irq(uint32_t intr) "0x%04x"
--        break;
++usb_dwc2_lower_host_irq(uint32_t intr) "0x%04x"
--    case MO_UW:
++usb_dwc2_sof(int64_t next) "next SOF %" PRId64
--        tcg_gen_ld16u_i32(var, cpu_env, offset);
++usb_dwc2_bus_start(void) "start SOFs"
--        break;
++usb_dwc2_bus_stop(void) "stop SOFs"
--    case MO_UL:
++usb_dwc2_find_device(uint8_t addr) "%d"
--        tcg_gen_ld_i32(var, cpu_env, offset);
++usb_dwc2_port_disabled(uint32_t pnum) "port %d disabled"
--        break;
++usb_dwc2_device_found(uint32_t pnum) "device found on port %d"
--    default:
++usb_dwc2_device_not_found(void) "device not found"
--        g_assert_not_reached();
++usb_dwc2_handle_packet(uint32_t chan, void *dev, void *pkt, uint32_t ep, const char *type, const char *dir, uint32_t mps, uint32_t len, uint32_t pcnt) "ch %d dev %p pkt %p ep %d type %s dir %s mps %d len %d pcnt %d"
--    }
++usb_dwc2_memory_read(uint32_t addr, uint32_t len) "addr %d len %d"
--}
++usb_dwc2_packet_status(const char *status, uint32_t len) "status %s len %d"
--
++usb_dwc2_packet_error(const char *status) "ERROR %s"
--static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop)
++usb_dwc2_async_packet(void *pkt, uint32_t chan, void *dev, uint32_t ep, const char *dir, uint32_t len) "pkt %p ch %d dev %p ep %d %s len %d"
--{
++usb_dwc2_memory_write(uint32_t addr, uint32_t len) "addr %d len %d"
--    long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
++usb_dwc2_packet_done(const char *status, uint32_t actual, uint32_t len, uint32_t pcnt) "status %s actual %d len %d pcnt %d"
--
++usb_dwc2_packet_next(const char *status, uint32_t len, uint32_t pcnt) "status %s len %d pcnt %d"
--    switch (mop) {
++usb_dwc2_attach(void *port) "port %p"
--    case MO_UB:
++usb_dwc2_attach_speed(const char *speed) "%s-speed device attached"
--        tcg_gen_ld8u_i64(var, cpu_env, offset);
++usb_dwc2_detach(void *port) "port %p"
--        break;
++usb_dwc2_child_detach(void *port, void *child) "port %p child %p"
--    case MO_UW:
++usb_dwc2_wakeup(void *port) "port %p"
--        tcg_gen_ld16u_i64(var, cpu_env, offset);
++usb_dwc2_async_packet_complete(void *port, void *pkt, uint32_t chan, void *dev, uint32_t ep, const char *dir, uint32_t len) "port %p packet %p ch %d dev %p ep %d %s len %d"
--        break;
++usb_dwc2_work_bh(void) ""
--    case MO_UL:
++usb_dwc2_work_bh_service(uint32_t first, uint32_t current, void *dev, uint32_t ep) "first %d servicing %d dev %p ep %d"
--        tcg_gen_ld32u_i64(var, cpu_env, offset);
++usb_dwc2_work_bh_next(uint32_t chan) "next %d"
--        break;
++usb_dwc2_enable_chan(uint32_t chan, void *dev, void *pkt, uint32_t ep) "ch %d dev %p pkt %p ep %d"
--    case MO_Q:
++usb_dwc2_glbreg_read(uint64_t addr, const char *reg, uint32_t val) " 0x%04" PRIx64 " %s val 0x%08x"
--        tcg_gen_ld_i64(var, cpu_env, offset);
++usb_dwc2_glbreg_write(uint64_t addr, const char *reg, uint64_t val, uint32_t old, uint64_t result) "0x%04" PRIx64 " %s val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
--        break;
++usb_dwc2_fszreg_read(uint64_t addr, uint32_t val) " 0x%04" PRIx64 " HPTXFSIZ  val 0x%08x"
--    default:
++usb_dwc2_fszreg_write(uint64_t addr, uint64_t val, uint32_t old, uint64_t result) "0x%04" PRIx64 " HPTXFSIZ  val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
--        g_assert_not_reached();
++usb_dwc2_hreg0_read(uint64_t addr, const char *reg, uint32_t val) "  0x%04" PRIx64 " %s val 0x%08x"
--    }
++usb_dwc2_hreg0_write(uint64_t addr, const char *reg, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " %s val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
--}
++usb_dwc2_hreg1_read(uint64_t addr, const char *reg, uint64_t chan, uint32_t val) "  0x%04" PRIx64 " %s%" PRId64 " val 0x%08x"
--
++usb_dwc2_hreg1_write(uint64_t addr, const char *reg, uint64_t chan, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " %s%" PRId64 " val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
- static void neon_store_reg(int reg, int pass, TCGv_i32 var)
++usb_dwc2_pcgreg_read(uint64_t addr, const char *reg, uint32_t val) " 0x%04" PRIx64 " %s val 0x%08x"
- {
++usb_dwc2_pcgreg_write(uint64_t addr, const char *reg, uint64_t val, uint32_t old, uint64_t result) "0x%04" PRIx64 " %s val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
-     tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
++usb_dwc2_hreg2_read(uint64_t addr, uint64_t fifo, uint32_t val) "  0x%04" PRIx64 " FIFO%" PRId64 "     val 0x%08x"
-     tcg_temp_free_i32(var);
++usb_dwc2_hreg2_write(uint64_t addr, uint64_t fifo, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " FIFO%" PRId64 "     val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
- }
++usb_dwc2_hreg0_action(const char *s) "%s"
++usb_dwc2_wakeup_endpoint(void *ep, uint32_t stream) "endp %p stream %d"
--static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var)
++usb_dwc2_work_timer(void) ""
--{
++usb_dwc2_reset_enter(void) "=== RESET enter ==="
--    long offset = neon_element_offset(reg, ele, size);
++usb_dwc2_reset_hold(void) "=== RESET hold ==="
--
++usb_dwc2_reset_exit(void) "=== RESET exit ==="
--    switch (size) {
++
--    case MO_8:
+ # desc.c
--        tcg_gen_st8_i32(var, cpu_env, offset);
+ usb_desc_device(int addr, int len, int ret) "dev %d query device, len %d, ret %d"
--        break;
+ usb_desc_device_qualifier(int addr, int len, int ret) "dev %d query device qualifier, len %d, ret %d"
 -    case MO_16:
 -        tcg_gen_st16_i32(var, cpu_env, offset);
 -        break;
 -    case MO_32:
 -        tcg_gen_st_i32(var, cpu_env, offset);
 -        break;
 -    default:
 -        g_assert_not_reached();
 -    }
 -}
 -
 -static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var)
 -{
 -    long offset = neon_element_offset(reg, ele, size);
 -
 -    switch (size) {
 -    case MO_8:
 -        tcg_gen_st8_i64(var, cpu_env, offset);
 -        break;
 -    case MO_16:
 -        tcg_gen_st16_i64(var, cpu_env, offset);
 -        break;
 -    case MO_32:
 -        tcg_gen_st32_i64(var, cpu_env, offset);
 -        break;
 -    case MO_64:
 -        tcg_gen_st_i64(var, cpu_env, offset);
 -        break;
 -    default:
 -        g_assert_not_reached();
 -    }
 -}
 -
  static inline void neon_load_reg64(TCGv_i64 var, int reg)
  {
      tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
 --
 .20.1

-[PULL 34/42] hw/arm/mps2: Add CMSDK AHB GPIO peripherals as unimplemented devices
+[PULL 18/29] usb: add short-packet handling to usb-storage driver
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Paul Zimmerman <pauldzim@gmail.com>
-Register the GPIO peripherals as unimplemented to better
+The dwc-hsotg (dwc2) USB host depends on a short packet to
-follow their accesses, for example booting Zephyr:
+indicate the end of an IN transfer. The usb-storage driver
 currently doesn't provide this, so fix it.
-  ----------------
+I have tested this change rather extensively using a PC
-  IN: arm_mps2_pinmux_init
+emulation with xhci, ehci, and uhci controllers, and have
-x00001160:  f64f 0231  movw     r2, #0xf831
+not observed any regressions.
 x00001164:  4b06       ldr      r3, [pc, #0x18]
 x00001166:  2000       movs     r0, #0
 x00001168:  619a       str      r2, [r3, #0x18]
 x0000116a:  f24c 426f  movw     r2, #0xc46f
 x0000116e:  f503 5380  add.w    r3, r3, #0x1000
 x00001172:  619a       str      r2, [r3, #0x18]
 x00001174:  f44f 529e  mov.w    r2, #0x13c0
 x00001178:  f503 5380  add.w    r3, r3, #0x1000
 x0000117c:  619a       str      r2, [r3, #0x18]
 x0000117e:  4770       bx       lr
   cmsdk-ahb-gpio: unimplemented device write (size 4, value 0xf831, offset 0x18)
   cmsdk-ahb-gpio: unimplemented device write (size 4, value 0xc46f, offset 0x18)
   cmsdk-ahb-gpio: unimplemented device write (size 4, value 0x13c0, offset 0x18)
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20200520235349.21215-6-pauldzim@gmail.com
 Message-id: 20200617072539.32686-10-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/mps2.c | 8 ++++++--
+ hw/usb/dev-storage.c | 15 ++++++++++++++-
-file changed, 6 insertions(+), 2 deletions(-)
+file changed, 14 insertions(+), 1 deletion(-)
-diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
+diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/mps2.c
+--- a/hw/usb/dev-storage.c
-+++ b/hw/arm/mps2.c
++++ b/hw/usb/dev-storage.c
-@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ static void usb_msd_copy_data(MSDState *s, USBPacket *p)
-     MemoryRegion *system_memory = get_system_memory();
+     usb_packet_copy(p, scsi_req_get_buf(s->req) + s->scsi_off, len);
-     MachineClass *mc = MACHINE_GET_CLASS(machine);
+     s->scsi_len -= len;
-     DeviceState *armv7m, *sccdev;
+     s->scsi_off += len;
-+    int i;
++    if (len > s->data_len) {
++        len = s->data_len;
      if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
          error_report("This board can only be used with CPU %s",
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
           */
          Object *orgate;
          DeviceState *orgate_dev;
 -        int i;
          orgate = object_new(TYPE_OR_IRQ);
          object_property_set_int(orgate, 6, "num-lines", &error_fatal);
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
           */
          Object *orgate;
          DeviceState *orgate_dev;
 -        int i;
          orgate = object_new(TYPE_OR_IRQ);
          object_property_set_int(orgate, 10, "num-lines", &error_fatal);
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
      default:
          g_assert_not_reached();
      }
 +    for (i = 0; i < 4; i++) {
 +        static const hwaddr gpiobase[] = {0x40010000, 0x40011000,
 +                                          0x40012000, 0x40013000};
 +        create_unimplemented_device("cmsdk-ahb-gpio", gpiobase[i], 0x1000);
 +    }
+     s->data_len -= len;
-     /* CMSDK APB subsystem */
+     if (s->scsi_len == 0 || s->data_len == 0) {
-     cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
+         scsi_req_continue(s->req);
@@ -XXX,XX +XXX,XX @@ static void usb_msd_command_complete(SCSIRequest *req, uint32_t status, size_t r
              if (s->data_len) {
                  int len = (p->iov.size - p->actual_length);
                  usb_packet_skip(p, len);
 +                if (len > s->data_len) {
 +                    len = s->data_len;
 +                }
                  s->data_len -= len;
              }
              if (s->data_len == 0) {
@@ -XXX,XX +XXX,XX @@ static void usb_msd_handle_data(USBDevice *dev, USBPacket *p)
                  int len = p->iov.size - p->actual_length;
                  if (len) {
                      usb_packet_skip(p, len);
 +                    if (len > s->data_len) {
 +                        len = s->data_len;
 +                    }
                      s->data_len -= len;
                      if (s->data_len == 0) {
                          s->mode = USB_MSDM_CSW;
@@ -XXX,XX +XXX,XX @@ static void usb_msd_handle_data(USBDevice *dev, USBPacket *p)
                  int len = p->iov.size - p->actual_length;
                  if (len) {
                      usb_packet_skip(p, len);
 +                    if (len > s->data_len) {
 +                        len = s->data_len;
 +                    }
                      s->data_len -= len;
                      if (s->data_len == 0) {
                          s->mode = USB_MSDM_CSW;
                      }
                  }
              }
 -            if (p->actual_length < p->iov.size) {
 +            if (p->actual_length < p->iov.size && (p->short_not_ok ||
 +                    s->scsi_len >= p->ep->max_packet_size)) {
                  DPRINTF("Deferring packet %p [wait data-in]\n", p);
                  s->packet = p;
                  p->status = USB_RET_ASYNC;
 --
 .20.1

-[PULL 42/42] arm/virt: Add memory hot remove support
+[PULL 19/29] wire in the dwc-hsotg (dwc2) USB host controller emulation
-From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
+From: Paul Zimmerman <pauldzim@gmail.com>
-This adds support for memory(pc-dimm) hot remove on arm/virt that
+Wire the dwc-hsotg (dwc2) emulation into Qemu
 uses acpi ged device.
-NVDIMM hot removal is not yet supported.
+Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
+Reviewed-by: Philippe Mathieu-Daude <f4bug@amsat.org>
-Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
+Message-id: 20200520235349.21215-7-pauldzim@gmail.com
 Message-id: 20200622124157.20360-1-shameerali.kolothum.thodi@huawei.com
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Tested-by: Eric Auger <eric.auger@redhat.com>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/acpi/generic_event_device.c | 29 ++++++++++++++++
+ include/hw/arm/bcm2835_peripherals.h |  3 ++-
- hw/arm/virt.c                  | 62 ++++++++++++++++++++++++++++++++--
+ hw/arm/bcm2835_peripherals.c         | 21 ++++++++++++++++++++-
-files changed, 89 insertions(+), 2 deletions(-)
+files changed, 22 insertions(+), 2 deletions(-)
-diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
+diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/acpi/generic_event_device.c
+--- a/include/hw/arm/bcm2835_peripherals.h
-+++ b/hw/acpi/generic_event_device.c
++++ b/include/hw/arm/bcm2835_peripherals.h
-@@ -XXX,XX +XXX,XX @@ static void acpi_ged_device_plug_cb(HotplugHandler *hotplug_dev,
+@@ -XXX,XX +XXX,XX @@
-     }
+ #include "hw/sd/bcm2835_sdhost.h"
  #include "hw/gpio/bcm2835_gpio.h"
  #include "hw/timer/bcm2835_systmr.h"
 +#include "hw/usb/hcd-dwc2.h"
  #include "hw/misc/unimp.h"
  #define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState {
      UnimplementedDeviceState ave0;
      UnimplementedDeviceState bscsl;
      UnimplementedDeviceState smi;
 -    UnimplementedDeviceState dwc2;
 +    DWC2State dwc2;
      UnimplementedDeviceState sdramc;
  } BCM2835PeripheralState;
 diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/bcm2835_peripherals.c
 +++ b/hw/arm/bcm2835_peripherals.c
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
      /* Mphi */
      sysbus_init_child_obj(obj, "mphi", &s->mphi, sizeof(s->mphi),
                            TYPE_BCM2835_MPHI);
 +
 +    /* DWC2 */
 +    sysbus_init_child_obj(obj, "dwc2", &s->dwc2, sizeof(s->dwc2),
 +                          TYPE_DWC2_USB);
 +
 +    object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
 +                                   OBJECT(&s->gpu_bus_mr));
  }
-+static void acpi_ged_unplug_request_cb(HotplugHandler *hotplug_dev,
+ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
-+                                       DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
-+{
+         qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
-+    AcpiGedState *s = ACPI_GED(hotplug_dev);
+                                INTERRUPT_HOSTPORT));
-+
-+    if ((object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) &&
++    /* DWC2 */
-+                       !(object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)))) {
++    object_property_set_bool(OBJECT(&s->dwc2), true, "realized", &err);
-+        acpi_memory_unplug_request_cb(hotplug_dev, &s->memhp_state, dev, errp);
++    if (err) {
-+    } else {
++        error_propagate(errp, err);
-+        error_setg(errp, "acpi: device unplug request for unsupported device"
++        return;
 +                   " type: %s", object_get_typename(OBJECT(dev)));
 +    }
 +}
 +
 +static void acpi_ged_unplug_cb(HotplugHandler *hotplug_dev,
 +                               DeviceState *dev, Error **errp)
 +{
 +    AcpiGedState *s = ACPI_GED(hotplug_dev);
 +
 +    if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 +        acpi_memory_unplug_cb(&s->memhp_state, dev, errp);
 +    } else {
 +        error_setg(errp, "acpi: device unplug for unsupported device"
 +                   " type: %s", object_get_typename(OBJECT(dev)));
 +    }
 +}
 +
  static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
  {
      AcpiGedState *s = ACPI_GED(adev);
@@ -XXX,XX +XXX,XX @@ static void acpi_ged_class_init(ObjectClass *class, void *data)
      dc->vmsd = &vmstate_acpi_ged;
      hc->plug = acpi_ged_device_plug_cb;
 +    hc->unplug_request = acpi_ged_unplug_request_cb;
 +    hc->unplug = acpi_ged_unplug_cb;
      adevc->send_event = acpi_ged_send_event;
  }
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
      }
  }
 +static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
 +                                     DeviceState *dev, Error **errp)
 +{
 +    VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
 +    Error *local_err = NULL;
 +
 +    if (!vms->acpi_dev) {
 +        error_setg(&local_err,
 +                   "memory hotplug is not enabled: missing acpi-ged device");
 +        goto out;
 +    }
 +
-+    if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
++    memory_region_add_subregion(&s->peri_mr, USB_OTG_OFFSET,
-+        error_setg(&local_err,
++                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dwc2), 0));
-+                   "nvdimm device hot unplug is not supported yet.");
++    sysbus_connect_irq(SYS_BUS_DEVICE(&s->dwc2), 0,
-+        goto out;
++        qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
-+    }
++                               INTERRUPT_USB));
 +
-+    hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
+     create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
-+                                   &local_err);
+     create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
-+out:
+     create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
-+    error_propagate(errp, local_err);
+@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
-+}
+     create_unimp(s, &s->otp, "bcm2835-otp", OTP_OFFSET, 0x80);
-+
+     create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000);
-+static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
+     create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000);
-+                             DeviceState *dev, Error **errp)
+-    create_unimp(s, &s->dwc2, "dwc-usb2", USB_OTG_OFFSET, 0x1000);
-+{
+     create_unimp(s, &s->sdramc, "bcm2835-sdramc", SDRAMC_OFFSET, 0x100);
 +    VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
 +    Error *local_err = NULL;
 +
 +    hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
 +    if (local_err) {
 +        goto out;
 +    }
 +
 +    pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
 +    qdev_unrealize(dev);
 +
 +out:
 +    error_propagate(errp, local_err);
 +}
 +
  static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
                                            DeviceState *dev, Error **errp)
  {
 -    error_setg(errp, "device unplug request for unsupported device"
 -               " type: %s", object_get_typename(OBJECT(dev)));
 +    if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 +        virt_dimm_unplug_request(hotplug_dev, dev, errp);
 +    } else {
 +        error_setg(errp, "device unplug request for unsupported device"
 +                   " type: %s", object_get_typename(OBJECT(dev)));
 +    }
 +}
 +
 +static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
 +                                          DeviceState *dev, Error **errp)
 +{
 +    if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 +        virt_dimm_unplug(hotplug_dev, dev, errp);
 +    } else {
 +        error_setg(errp, "virt: device unplug for unsupported device"
 +                   " type: %s", object_get_typename(OBJECT(dev)));
 +    }
  }
- static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
-     hc->pre_plug = virt_machine_device_pre_plug_cb;
-     hc->plug = virt_machine_device_plug_cb;
-     hc->unplug_request = virt_machine_device_unplug_request_cb;
-+    hc->unplug = virt_machine_device_unplug_cb;
-     mc->numa_mem_supported = true;
-     mc->nvdimm_supported = true;
-     mc->auto_enable_numa_with_memhp = true;
 --
 .20.1

-[PULL 31/42] hw/arm/mps2: Document CMSDK/FPGA APB subsystem sections
+[PULL 20/29] raspi2 acceptance test: add test for dwc-hsotg (dwc2) USB host
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Paul Zimmerman <pauldzim@gmail.com>
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Add a check for functional dwc-hsotg (dwc2) USB host emulation to
-Message-id: 20200617072539.32686-7-f4bug@amsat.org
+the Raspi 2 acceptance test
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
 Reviewed-by: Philippe Mathieu-Daude <f4bug@amsat.org>
 Message-id: 20200520235349.21215-8-pauldzim@gmail.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/mps2.c | 5 ++++-
+ tests/acceptance/boot_linux_console.py | 9 +++++++--
-file changed, 4 insertions(+), 1 deletion(-)
+file changed, 7 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
+diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/mps2.c
+--- a/tests/acceptance/boot_linux_console.py
-+++ b/hw/arm/mps2.c
++++ b/tests/acceptance/boot_linux_console.py
-@@ -XXX,XX +XXX,XX @@ typedef struct {
+@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(LinuxKernelTest):
-     MemoryRegion blockram_m2;
-     MemoryRegion blockram_m3;
+         self.vm.set_console()
-     MemoryRegion sram;
+         kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
-+    /* FPGA APB subsystem */
+-                               serial_kernel_cmdline[uart_id])
-     MPS2SCC scc;
++                               serial_kernel_cmdline[uart_id] +
-+    /* CMSDK APB subsystem */
++                               ' root=/dev/mmcblk0p2 rootwait ' +
-     CMSDKAPBDualTimer dualtimer;
++                               'dwc_otg.fiq_fsm_enable=0')
- } MPS2MachineState;
+         self.vm.add_args('-kernel', kernel_path,
+                          '-dtb', dtb_path,
-@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
+-                         '-append', kernel_command_line)
-         g_assert_not_reached();
++                         '-append', kernel_command_line,
-     }
++                         '-device', 'usb-kbd')
+         self.vm.launch()
-+    /* CMSDK APB subsystem */
+         console_pattern = 'Kernel command line: %s' % kernel_command_line
-     cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
+         self.wait_for_console_pattern(console_pattern)
-     cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ);
++        console_pattern = 'Product: QEMU USB Keyboard'
--
++        self.wait_for_console_pattern(console_pattern)
-     object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
-                             TYPE_CMSDK_APB_DUALTIMER);
+     def test_arm_raspi2_uart0(self):
-     qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
+         """
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
                         qdev_get_gpio_in(armv7m, 10));
      sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
 +    /* FPGA APB subsystem */
      object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
      sccdev = DEVICE(&mms->scc);
      qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
 --
 .20.1

-[PULL 09/42] target/arm: Convert vectorised 2-reg-misc Neon ops to decodetree
+[PULL 21/29] target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree
-Convert to decodetree the insns in the Neon 2-reg-misc grouping which
+Convert the VSHL and VSLI insns from the Neon 2-registers-and-a-shift
-we implement using gvec.
+group to decodetree.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-8-peter.maydell@linaro.org
+Message-id: 20200522145520.6778-2-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       | 11 +++++++
+ target/arm/neon-dp.decode       | 25 ++++++++++++++++++++++
- target/arm/translate-neon.inc.c | 55 +++++++++++++++++++++++++++++++++
+ target/arm/translate-neon.inc.c | 38 +++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 35 +++++----------------
+ target/arm/translate.c          | 18 +++++++---------
-files changed, 74 insertions(+), 27 deletions(-)
+files changed, 71 insertions(+), 10 deletions(-)
 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/neon-dp.decode
 +++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
+@@ -XXX,XX +XXX,XX @@ VRECPS_fp_3s     1111 001 0 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
-     VPADDL_S     1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc
+ VRSQRTS_fp_3s    1111 001 0 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
-     VPADDL_U     1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc
+ VMAXNM_fp_3s     1111 001 1 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
+ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
 +    VMVN         1111 001 11 . 11 .. 00 .... 0 1011 . . 0 .... @2misc
 +
-     VPADAL_S     1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc
++######################################################################
-     VPADAL_U     1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc
++# 2-reg-and-shift grouping:
++# 1111 001 U 1 D immH:3 immL:3 Vd:4 opc:4 L Q M 1 Vm:4
-+    VCGT0        1111 001 11 . 11 .. 01 .... 0 0000 . . 0 .... @2misc
++######################################################################
-+    VCGE0        1111 001 11 . 11 .. 01 .... 0 0001 . . 0 .... @2misc
++&2reg_shift vm vd q shift size
 +    VCEQ0        1111 001 11 . 11 .. 01 .... 0 0010 . . 0 .... @2misc
 +    VCLE0        1111 001 11 . 11 .. 01 .... 0 0011 . . 0 .... @2misc
 +    VCLT0        1111 001 11 . 11 .. 01 .... 0 0100 . . 0 .... @2misc
 +
-+    VABS         1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc
++@2reg_shl_d      .... ... . . . shift:6      .... .... 1 q:1 . . .... \
-+    VNEG         1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc
++                 &2reg_shift vm=%vm_dp vd=%vd_dp size=3
 +@2reg_shl_s      .... ... . . . 1 shift:5    .... .... 0 q:1 . . .... \
 +                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2
 +@2reg_shl_h      .... ... . . . 01 shift:4   .... .... 0 q:1 . . .... \
 +                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1
 +@2reg_shl_b      .... ... . . . 001 shift:3  .... .... 0 q:1 . . .... \
 +                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0
 +
-     VUZP         1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc
++VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
-     VZIP         1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc
++VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
++VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
 +VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
 +
 +VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
 +VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
 +VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
 +VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.inc.c
 +++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a)
+@@ -XXX,XX +XXX,XX @@ static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn)
+ DO_3S_FP_PAIR(VPADD, gen_helper_vfp_adds)
-     return true;
+ DO_3S_FP_PAIR(VPMAX, gen_helper_vfp_maxs)
- }
+ DO_3S_FP_PAIR(VPMIN, gen_helper_vfp_mins)
 +
-+static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn)
++static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
 +{
++    /* Handle a 2-reg-shift insn which can be vectorized. */
 +    int vec_size = a->q ? 16 : 8;
 +    int rd_ofs = neon_reg_offset(a->vd, 0);
 +    int rm_ofs = neon_reg_offset(a->vm, 0);
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
 ...
 +    if (!dc_isar_feature(aa32_simd_r32, s) &&
 +        ((a->vd | a->vm) & 0x10)) {
 +        return false;
 +    }
 +
-+    if (a->size == 3) {
++    if ((a->vm | a->vd) & a->q) {
 +        return false;
 +    }
 +
 +    if ((a->vd | a->vm) & a->q) {
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
-+    fn(a->size, rd_ofs, rm_ofs, vec_size, vec_size);
++    fn(a->size, rd_ofs, rm_ofs, a->shift, vec_size, vec_size);
 +
 +    return true;
 +}
 +
-+#define DO_2MISC_VEC(INSN, FN)                                  \
++#define DO_2SH(INSN, FUNC)                                              \
-+    static bool trans_##INSN(DisasContext *s, arg_2misc *a)     \
++    static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a)  \
-+    {                                                           \
++    {                                                                   \
-+        return do_2misc_vec(s, a, FN);                          \
++        return do_vector_2sh(s, a, FUNC);                               \
-+    }
++    }                                                                   \
 +
-+DO_2MISC_VEC(VNEG, tcg_gen_gvec_neg)
++DO_2SH(VSHL, tcg_gen_gvec_shli)
-+DO_2MISC_VEC(VABS, tcg_gen_gvec_abs)
++DO_2SH(VSLI, gen_gvec_sli)
 +DO_2MISC_VEC(VCEQ0, gen_gvec_ceq0)
 +DO_2MISC_VEC(VCGT0, gen_gvec_cgt0)
 +DO_2MISC_VEC(VCLE0, gen_gvec_cle0)
 +DO_2MISC_VEC(VCGE0, gen_gvec_cge0)
 +DO_2MISC_VEC(VCLT0, gen_gvec_clt0)
 +
 +static bool trans_VMVN(DisasContext *s, arg_2misc *a)
 +{
 +    if (a->size != 0) {
 +        return false;
 +    }
 +    return do_2misc_vec(s, a, tcg_gen_gvec_not);
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
 @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-     int size;
+         if ((insn & 0x00380080) != 0) {
-     int pass;
+             /* Two registers and shift.  */
-     int u;
+             op = (insn >> 8) & 0xf;
--    int vec_size;
++
-     TCGv_i32 tmp, tmp2;
++            switch (op) {
++            case 5: /* VSHL, VSLI */
-     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
++                return 1; /* handled by decodetree */
 +            default:
 +                break;
 +            }
 +
              if (insn & (1 << 7)) {
                  /* 64-bit shift. */
                  if (op > 7) {
 @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-     VFP_DREG_D(rd, insn);
+                     gen_gvec_sri(size, rd_ofs, rm_ofs, shift,
-     VFP_DREG_M(rm, insn);
+                                  vec_size, vec_size);
-     size = (insn >> 20) & 3;
+                     return 0;
 -    vec_size = q ? 16 : 8;
      rd_ofs = neon_reg_offset(rd, 0);
      rm_ofs = neon_reg_offset(rm, 0);
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                  case NEON_2RM_VSHLL:
                  case NEON_2RM_VCVT_F16_F32:
                  case NEON_2RM_VCVT_F32_F16:
 +                case NEON_2RM_VMVN:
 +                case NEON_2RM_VNEG:
 +                case NEON_2RM_VABS:
 +                case NEON_2RM_VCEQ0:
 +                case NEON_2RM_VCGT0:
 +                case NEON_2RM_VCLE0:
 +                case NEON_2RM_VCGE0:
 +                case NEON_2RM_VCLT0:
                      /* handled by decodetree */
                      return 1;
                  case NEON_2RM_VTRN:
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                                         q ? gen_helper_crypto_sha256su0
                                         : gen_helper_crypto_sha1su1);
                      break;
 -                case NEON_2RM_VMVN:
 -                    tcg_gen_gvec_not(0, rd_ofs, rm_ofs, vec_size, vec_size);
 -                    break;
 -                case NEON_2RM_VNEG:
 -                    tcg_gen_gvec_neg(size, rd_ofs, rm_ofs, vec_size, vec_size);
 -                    break;
 -                case NEON_2RM_VABS:
 -                    tcg_gen_gvec_abs(size, rd_ofs, rm_ofs, vec_size, vec_size);
 -                    break;
 -
--                case NEON_2RM_VCEQ0:
+-                case 5: /* VSHL, VSLI */
--                    gen_gvec_ceq0(size, rd_ofs, rm_ofs, vec_size, vec_size);
+-                    if (u) { /* VSLI */
--                    break;
+-                        gen_gvec_sli(size, rd_ofs, rm_ofs, shift,
--                case NEON_2RM_VCGT0:
+-                                     vec_size, vec_size);
--                    gen_gvec_cgt0(size, rd_ofs, rm_ofs, vec_size, vec_size);
+-                    } else { /* VSHL */
--                    break;
+-                        tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift,
--                case NEON_2RM_VCLE0:
+-                                          vec_size, vec_size);
--                    gen_gvec_cle0(size, rd_ofs, rm_ofs, vec_size, vec_size);
+-                    }
--                    break;
+-                    return 0;
--                case NEON_2RM_VCGE0:
+                 }
--                    gen_gvec_cge0(size, rd_ofs, rm_ofs, vec_size, vec_size);
--                    break;
+                 if (size == 3) {
 -                case NEON_2RM_VCLT0:
 -                    gen_gvec_clt0(size, rd_ofs, rm_ofs, vec_size, vec_size);
 -                    break;
                  default:
                  elementwise:
 --
 .20.1

-[PULL 15/42] target/arm: Convert remaining simple 2-reg-misc Neon ops
+[PULL 22/29] target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree
-Convert the remaining ops in the Neon 2-reg-misc group which
+Convert the VSHR 2-reg-shift insns to decodetree.
-can be implemented simply with our do_2misc() helper.
 Note that unlike the legacy decoder, we present the right shift
 amount to the trans_ function as a positive integer.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-14-peter.maydell@linaro.org
+Message-id: 20200522145520.6778-3-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       | 10 +++++
+ target/arm/neon-dp.decode       | 25 ++++++++++++++++++++
- target/arm/translate-neon.inc.c | 69 +++++++++++++++++++++++++++++++++
+ target/arm/translate-neon.inc.c | 41 +++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 38 ++++--------------
+ target/arm/translate.c          | 21 +----------------
-files changed, 86 insertions(+), 31 deletions(-)
+files changed, 67 insertions(+), 20 deletions(-)
 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/neon-dp.decode
 +++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
+@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
-     AESMC        1111 001 11 . 11 .. 00 .... 0 0111 0 . 0 .... @2misc_q1
+ ######################################################################
-     AESIMC       1111 001 11 . 11 .. 00 .... 0 0111 1 . 0 .... @2misc_q1
+ &2reg_shift vm vd q shift size
-+    VCLS         1111 001 11 . 11 .. 00 .... 0 1000 . . 0 .... @2misc
++# Right shifts are encoded as N - shift, where N is the element size in bits.
-+    VCLZ         1111 001 11 . 11 .. 00 .... 0 1001 . . 0 .... @2misc
++%neon_rshift_i6  16:6 !function=rsub_64
-+    VCNT         1111 001 11 . 11 .. 00 .... 0 1010 . . 0 .... @2misc
++%neon_rshift_i5  16:5 !function=rsub_32
 +%neon_rshift_i4  16:4 !function=rsub_16
 +%neon_rshift_i3  16:3 !function=rsub_8
 +
-     VMVN         1111 001 11 . 11 .. 00 .... 0 1011 . . 0 .... @2misc
++@2reg_shr_d      .... ... . . . ......  .... .... 1 q:1 . . .... \
++                 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 shift=%neon_rshift_i6
-     VPADAL_S     1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc
++@2reg_shr_s      .... ... . . . 1 ..... .... .... 0 q:1 . . .... \
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
++                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
-     VABS         1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc
++@2reg_shr_h      .... ... . . . 01 .... .... .... 0 q:1 . . .... \
-     VNEG         1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc
++                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4
++@2reg_shr_b      .... ... . . . 001 ... .... .... 0 q:1 . . .... \
-+    VABS_F       1111 001 11 . 11 .. 01 .... 0 1110 . . 0 .... @2misc
++                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i3
 +    VNEG_F       1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc
 +
-     VUZP         1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc
+ @2reg_shl_d      .... ... . . . shift:6      .... .... 1 q:1 . . .... \
-     VZIP         1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc
+                  &2reg_shift vm=%vm_dp vd=%vd_dp size=3
+ @2reg_shl_s      .... ... . . . 1 shift:5    .... .... 0 q:1 . . .... \
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
+@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
+ @2reg_shl_b      .... ... . . . 001 shift:3  .... .... 0 q:1 . . .... \
-     VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0
+                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0
-     VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0
 +VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
 +VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
 +VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
 +VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
 +
-+    VRECPE       1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc
++VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
-+    VRSQRTE      1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc
++VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
-   ]
++VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
++VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
-   # Subgroup for size != 0b11
++
  VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
  VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
  VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.inc.c
 +++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VREV16(DisasContext *s, arg_2misc *a)
+@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
-     }
+     return x + 1;
      return do_2misc(s, a, gen_rev16);
  }
-+
-+static bool trans_VCLS(DisasContext *s, arg_2misc *a)
++static inline int rsub_64(DisasContext *s, int x)
 +{
-+    static NeonGenOneOpFn * const fn[] = {
++    return 64 - x;
 +        gen_helper_neon_cls_s8,
 +        gen_helper_neon_cls_s16,
 +        gen_helper_neon_cls_s32,
 +        NULL,
 +    };
 +    return do_2misc(s, a, fn[a->size]);
 +}
 +
-+static void do_VCLZ_32(TCGv_i32 rd, TCGv_i32 rm)
++static inline int rsub_32(DisasContext *s, int x)
 +{
-+    tcg_gen_clzi_i32(rd, rm, 32);
++    return 32 - x;
 +}
 +static inline int rsub_16(DisasContext *s, int x)
 +{
 +    return 16 - x;
 +}
 +static inline int rsub_8(DisasContext *s, int x)
 +{
 +    return 8 - x;
 +}
 +
-+static bool trans_VCLZ(DisasContext *s, arg_2misc *a)
+ /* Include the generated Neon decoder */
  #include "decode-neon-dp.inc.c"
  #include "decode-neon-ls.inc.c"
@@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
  DO_2SH(VSHL, tcg_gen_gvec_shli)
  DO_2SH(VSLI, gen_gvec_sli)
 +
 +static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a)
 +{
-+    static NeonGenOneOpFn * const fn[] = {
++    /* Signed shift out of range results in all-sign-bits */
-+        gen_helper_neon_clz_u8,
++    a->shift = MIN(a->shift, (8 << a->size) - 1);
-+        gen_helper_neon_clz_u16,
++    return do_vector_2sh(s, a, tcg_gen_gvec_sari);
 +        do_VCLZ_32,
 +        NULL,
 +    };
 +    return do_2misc(s, a, fn[a->size]);
 +}
 +
-+static bool trans_VCNT(DisasContext *s, arg_2misc *a)
++static void gen_zero_rd_2sh(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 +                            int64_t shift, uint32_t oprsz, uint32_t maxsz)
 +{
-+    if (a->size != 0) {
++    tcg_gen_gvec_dup_imm(vece, rd_ofs, oprsz, maxsz, 0);
 +        return false;
 +    }
 +    return do_2misc(s, a, gen_helper_neon_cnt_u8);
 +}
 +
-+static bool trans_VABS_F(DisasContext *s, arg_2misc *a)
++static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a)
 +{
-+    if (a->size != 2) {
++    /* Shift out of range is architecturally valid and results in zero. */
-+        return false;
++    if (a->shift >= (8 << a->size)) {
 +        return do_vector_2sh(s, a, gen_zero_rd_2sh);
 +    } else {
 +        return do_vector_2sh(s, a, tcg_gen_gvec_shri);
 +    }
-+    /* TODO: FP16 : size == 1 */
-+    return do_2misc(s, a, gen_helper_vfp_abss);
-+}
-+
-+static bool trans_VNEG_F(DisasContext *s, arg_2misc *a)
-+{
-+    if (a->size != 2) {
-+        return false;
-+    }
-+    /* TODO: FP16 : size == 1 */
-+    return do_2misc(s, a, gen_helper_vfp_negs);
-+}
-+
-+static bool trans_VRECPE(DisasContext *s, arg_2misc *a)
-+{
-+    if (a->size != 2) {
-+        return false;
-+    }
-+    return do_2misc(s, a, gen_helper_recpe_u32);
-+}
-+
-+static bool trans_VRSQRTE(DisasContext *s, arg_2misc *a)
-+{
-+    if (a->size != 2) {
-+        return false;
-+    }
-+    return do_2misc(s, a, gen_helper_rsqrte_u32);
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
 @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                 case NEON_2RM_SHA1SU1:
+             op = (insn >> 8) & 0xf;
-                 case NEON_2RM_VREV32:
-                 case NEON_2RM_VREV16:
+             switch (op) {
-+                case NEON_2RM_VCLS:
++            case 0: /* VSHR */
-+                case NEON_2RM_VCLZ:
+             case 5: /* VSHL, VSLI */
-+                case NEON_2RM_VCNT:
+                 return 1; /* handled by decodetree */
-+                case NEON_2RM_VABS_F:
+             default:
 +                case NEON_2RM_VNEG_F:
 +                case NEON_2RM_VRECPE:
 +                case NEON_2RM_VRSQRTE:
                      /* handled by decodetree */
                      return 1;
                  case NEON_2RM_VTRN:
 @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                     for (pass = 0; pass < (q ? 4 : 2); pass++) {
+                 }
-                         tmp = neon_load_reg(rm, pass);
-                         switch (op) {
+                 switch (op) {
--                        case NEON_2RM_VCLS:
+-                case 0:  /* VSHR */
--                            switch (size) {
+-                    /* Right shift comes here negative.  */
--                            case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
+-                    shift = -shift;
--                            case 1: gen_helper_neon_cls_s16(tmp, tmp); break;
+-                    /* Shifts larger than the element size are architecturally
--                            case 2: gen_helper_neon_cls_s32(tmp, tmp); break;
+-                     * valid.  Unsigned results in all zeros; signed results
--                            default: abort();
+-                     * in all sign bits.
--                            }
+-                     */
--                            break;
+-                    if (!u) {
--                        case NEON_2RM_VCLZ:
+-                        tcg_gen_gvec_sari(size, rd_ofs, rm_ofs,
--                            switch (size) {
+-                                          MIN(shift, (8 << size) - 1),
--                            case 0: gen_helper_neon_clz_u8(tmp, tmp); break;
+-                                          vec_size, vec_size);
--                            case 1: gen_helper_neon_clz_u16(tmp, tmp); break;
+-                    } else if (shift >= 8 << size) {
--                            case 2: tcg_gen_clzi_i32(tmp, tmp, 32); break;
+-                        tcg_gen_gvec_dup_imm(MO_8, rd_ofs, vec_size,
--                            default: abort();
+-                                             vec_size, 0);
--                            }
+-                    } else {
--                            break;
+-                        tcg_gen_gvec_shri(size, rd_ofs, rm_ofs, shift,
--                        case NEON_2RM_VCNT:
+-                                          vec_size, vec_size);
--                            gen_helper_neon_cnt_u8(tmp, tmp);
+-                    }
--                            break;
+-                    return 0;
-                         case NEON_2RM_VQABS:
+-
-                             switch (size) {
+                 case 1:  /* VSRA */
-                             case 0:
+                     /* Right shift comes here negative.  */
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
+                     shift = -shift;
                              tcg_temp_free_ptr(fpstatus);
                              break;
                          }
 -                        case NEON_2RM_VABS_F:
 -                            gen_helper_vfp_abss(tmp, tmp);
 -                            break;
 -                        case NEON_2RM_VNEG_F:
 -                            gen_helper_vfp_negs(tmp, tmp);
 -                            break;
                          case NEON_2RM_VSWP:
                              tmp2 = neon_load_reg(rd, pass);
                              neon_store_reg(rm, pass, tmp2);
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                              tcg_temp_free_ptr(fpst);
                              break;
                          }
 -                        case NEON_2RM_VRECPE:
 -                            gen_helper_recpe_u32(tmp, tmp);
 -                            break;
 -                        case NEON_2RM_VRSQRTE:
 -                            gen_helper_rsqrte_u32(tmp, tmp);
 -                            break;
                          case NEON_2RM_VRECPE_F:
                          {
                              TCGv_ptr fpstatus = get_fpstatus_ptr(1);
 --
 .20.1

-[PULL 10/42] target/arm: Convert Neon 2-reg-misc crypto operations to decodetree
+[PULL 23/29] target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree
-Convert the Neon-2-reg misc crypto ops (AESE, AESMC, SHA1H, SHA1SU1)
+Convert the VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree.
-to decodetree.
+(These are the last instructions in the group that are vectorized;
 the rest all require looping over each element.)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-9-peter.maydell@linaro.org
+Message-id: 20200522145520.6778-4-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       | 12 ++++++++
+ target/arm/neon-dp.decode       | 35 ++++++++++++++++++++++
- target/arm/translate-neon.inc.c | 42 ++++++++++++++++++++++++++
+ target/arm/translate-neon.inc.c |  7 +++++
  target/arm/translate.c          | 52 +++------------------------------
-files changed, 58 insertions(+), 48 deletions(-)
+files changed, 46 insertions(+), 48 deletions(-)
 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/neon-dp.decode
 +++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
+@@ -XXX,XX +XXX,XX @@ VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
-                  &2misc vm=%vm_dp vd=%vd_dp
+ VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
-     @2misc_q0    .... ... .. . .. size:2 .. .... . .... . . . .... \
+ VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
-                  &2misc vm=%vm_dp vd=%vd_dp q=0
-+    @2misc_q1    .... ... .. . .. size:2 .. .... . .... . . . .... \
++VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
-+                 &2misc vm=%vm_dp vd=%vd_dp q=1
++VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
++VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
-     VREV64       1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc
++VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
      VPADDL_S     1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc
      VPADDL_U     1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc
 +    AESE         1111 001 11 . 11 .. 00 .... 0 0110 0 . 0 .... @2misc_q1
 +    AESD         1111 001 11 . 11 .. 00 .... 0 0110 1 . 0 .... @2misc_q1
 +    AESMC        1111 001 11 . 11 .. 00 .... 0 0111 0 . 0 .... @2misc_q1
 +    AESIMC       1111 001 11 . 11 .. 00 .... 0 0111 1 . 0 .... @2misc_q1
 +
-     VMVN         1111 001 11 . 11 .. 00 .... 0 1011 . . 0 .... @2misc
++VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
++VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
-     VPADAL_S     1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc
++VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
++VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
      VCLE0        1111 001 11 . 11 .. 01 .... 0 0011 . . 0 .... @2misc
      VCLT0        1111 001 11 . 11 .. 01 .... 0 0100 . . 0 .... @2misc
 +    SHA1H        1111 001 11 . 11 .. 01 .... 0 0101 1 . 0 .... @2misc_q1
 +
-     VABS         1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc
++VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
-     VNEG         1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc
++VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
++VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
++VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
      VSHLL        1111 001 11 . 11 .. 10 .... 0 0110 0 . 0 .... @2misc_q0
 +    SHA1SU1      1111 001 11 . 11 .. 10 .... 0 0111 0 . 0 .... @2misc_q1
 +    SHA256SU0    1111 001 11 . 11 .. 10 .... 0 0111 1 . 0 .... @2misc_q1
 +
-     VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0
++VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
-     VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0
++VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
-   ]
++VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
 +VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
 +
 +VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
 +VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
 +VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
 +VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
 +
 +VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
 +VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
 +VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
 +VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
 +
 +VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_d
 +VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_s
 +VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_h
 +VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_b
 +
  VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
  VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
  VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.inc.c
 +++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VMVN(DisasContext *s, arg_2misc *a)
+@@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
-     }
-     return do_2misc_vec(s, a, tcg_gen_gvec_not);
+ DO_2SH(VSHL, tcg_gen_gvec_shli)
- }
+ DO_2SH(VSLI, gen_gvec_sli)
-+
++DO_2SH(VSRI, gen_gvec_sri)
-+#define WRAP_2M_3_OOL_FN(WRAPNAME, FUNC, DATA)                          \
++DO_2SH(VSRA_S, gen_gvec_ssra)
-+    static void WRAPNAME(unsigned vece, uint32_t rd_ofs,                \
++DO_2SH(VSRA_U, gen_gvec_usra)
-+                         uint32_t rm_ofs, uint32_t oprsz,               \
++DO_2SH(VRSHR_S, gen_gvec_srshr)
-+                         uint32_t maxsz)                                \
++DO_2SH(VRSHR_U, gen_gvec_urshr)
-+    {                                                                   \
++DO_2SH(VRSRA_S, gen_gvec_srsra)
-+        tcg_gen_gvec_3_ool(rd_ofs, rd_ofs, rm_ofs, oprsz, maxsz,        \
++DO_2SH(VRSRA_U, gen_gvec_ursra)
-+                           DATA, FUNC);                                 \
-+    }
+ static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a)
-+
+ {
 +#define WRAP_2M_2_OOL_FN(WRAPNAME, FUNC, DATA)                          \
 +    static void WRAPNAME(unsigned vece, uint32_t rd_ofs,                \
 +                         uint32_t rm_ofs, uint32_t oprsz,               \
 +                         uint32_t maxsz)                                \
 +    {                                                                   \
 +        tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, oprsz, maxsz, DATA, FUNC);   \
 +    }
 +
 +WRAP_2M_3_OOL_FN(gen_AESE, gen_helper_crypto_aese, 0)
 +WRAP_2M_3_OOL_FN(gen_AESD, gen_helper_crypto_aese, 1)
 +WRAP_2M_2_OOL_FN(gen_AESMC, gen_helper_crypto_aesmc, 0)
 +WRAP_2M_2_OOL_FN(gen_AESIMC, gen_helper_crypto_aesmc, 1)
 +WRAP_2M_2_OOL_FN(gen_SHA1H, gen_helper_crypto_sha1h, 0)
 +WRAP_2M_2_OOL_FN(gen_SHA1SU1, gen_helper_crypto_sha1su1, 0)
 +WRAP_2M_2_OOL_FN(gen_SHA256SU0, gen_helper_crypto_sha256su0, 0)
 +
 +#define DO_2M_CRYPTO(INSN, FEATURE, SIZE)                       \
 +    static bool trans_##INSN(DisasContext *s, arg_2misc *a)     \
 +    {                                                           \
 +        if (!dc_isar_feature(FEATURE, s) || a->size != SIZE) {  \
 +            return false;                                       \
 +        }                                                       \
 +        return do_2misc_vec(s, a, gen_##INSN);                  \
 +    }
 +
 +DO_2M_CRYPTO(AESE, aa32_aes, 0)
 +DO_2M_CRYPTO(AESD, aa32_aes, 0)
 +DO_2M_CRYPTO(AESMC, aa32_aes, 0)
 +DO_2M_CRYPTO(AESIMC, aa32_aes, 0)
 +DO_2M_CRYPTO(SHA1H, aa32_sha1, 2)
 +DO_2M_CRYPTO(SHA1SU1, aa32_sha1, 2)
 +DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2)
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
 @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
- {
-     int op;
+             switch (op) {
-     int q;
+             case 0: /* VSHR */
--    int rd, rm, rd_ofs, rm_ofs;
++            case 1: /* VSRA */
-+    int rd, rm;
++            case 2: /* VRSHR */
-     int size;
++            case 3: /* VRSRA */
-     int pass;
++            case 4: /* VSRI */
-     int u;
+             case 5: /* VSHL, VSLI */
                  return 1; /* handled by decodetree */
              default:
 @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-     VFP_DREG_D(rd, insn);
+                     shift = shift - (1 << (size + 3));
-     VFP_DREG_M(rm, insn);
+                 }
-     size = (insn >> 20) & 3;
--    rd_ofs = neon_reg_offset(rd, 0);
+-                switch (op) {
--    rm_ofs = neon_reg_offset(rm, 0);
+-                case 1:  /* VSRA */
+-                    /* Right shift comes here negative.  */
-     if ((insn & (1 << 23)) == 0) {
+-                    shift = -shift;
-         /* Three register same length: handled by decodetree */
+-                    if (u) {
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
+-                        gen_gvec_usra(size, rd_ofs, rm_ofs, shift,
-                 case NEON_2RM_VCLE0:
+-                                      vec_size, vec_size);
-                 case NEON_2RM_VCGE0:
+-                    } else {
-                 case NEON_2RM_VCLT0:
+-                        gen_gvec_ssra(size, rd_ofs, rm_ofs, shift,
-+                case NEON_2RM_AESE: case NEON_2RM_AESMC:
+-                                      vec_size, vec_size);
-+                case NEON_2RM_SHA1H:
+-                    }
-+                case NEON_2RM_SHA1SU1:
+-                    return 0;
-                     /* handled by decodetree */
+-
-                     return 1;
+-                case 2: /* VRSHR */
-                 case NEON_2RM_VTRN:
+-                    /* Right shift comes here negative.  */
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
+-                    shift = -shift;
-                         goto elementwise;
+-                    if (u) {
-                     }
+-                        gen_gvec_urshr(size, rd_ofs, rm_ofs, shift,
-                     break;
+-                                       vec_size, vec_size);
--                case NEON_2RM_AESE: case NEON_2RM_AESMC:
+-                    } else {
--                    if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) {
+-                        gen_gvec_srshr(size, rd_ofs, rm_ofs, shift,
 -                                       vec_size, vec_size);
 -                    }
 -                    return 0;
 -
 -                case 3: /* VRSRA */
 -                    /* Right shift comes here negative.  */
 -                    shift = -shift;
 -                    if (u) {
 -                        gen_gvec_ursra(size, rd_ofs, rm_ofs, shift,
 -                                       vec_size, vec_size);
 -                    } else {
 -                        gen_gvec_srsra(size, rd_ofs, rm_ofs, shift,
 -                                       vec_size, vec_size);
 -                    }
 -                    return 0;
 -
 -                case 4: /* VSRI */
 -                    if (!u) {
 -                        return 1;
 -                    }
--                    /*
+-                    /* Right shift comes here negative.  */
--                     * Bit 6 is the lowest opcode bit; it distinguishes
+-                    shift = -shift;
--                     * between encryption (AESE/AESMC) and decryption
+-                    gen_gvec_sri(size, rd_ofs, rm_ofs, shift,
--                     * (AESD/AESIMC).
+-                                 vec_size, vec_size);
--                     */
+-                    return 0;
--                    if (op == NEON_2RM_AESE) {
+-                }
--                        tcg_gen_gvec_3_ool(vfp_reg_offset(true, rd),
+-
--                                           vfp_reg_offset(true, rd),
+                 if (size == 3) {
--                                           vfp_reg_offset(true, rm),
+                     count = q + 1;
--                                           16, 16, extract32(insn, 6, 1),
+                 } else {
 -                                           gen_helper_crypto_aese);
 -                    } else {
 -                        tcg_gen_gvec_2_ool(vfp_reg_offset(true, rd),
 -                                           vfp_reg_offset(true, rm),
 -                                           16, 16, extract32(insn, 6, 1),
 -                                           gen_helper_crypto_aesmc);
 -                    }
 -                    break;
 -                case NEON_2RM_SHA1H:
 -                    if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) {
 -                        return 1;
 -                    }
 -                    tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0,
 -                                       gen_helper_crypto_sha1h);
 -                    break;
 -                case NEON_2RM_SHA1SU1:
 -                    if ((rm | rd) & 1) {
 -                            return 1;
 -                    }
 -                    /* bit 6 (q): set -> SHA256SU0, cleared -> SHA1SU1 */
 -                    if (q) {
 -                        if (!dc_isar_feature(aa32_sha2, s)) {
 -                            return 1;
 -                        }
 -                    } else if (!dc_isar_feature(aa32_sha1, s)) {
 -                        return 1;
 -                    }
 -                    tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0,
 -                                       q ? gen_helper_crypto_sha256su0
 -                                       : gen_helper_crypto_sha1su1);
 -                    break;
                  default:
                  elementwise:
 --
 .20.1

-[PULL 22/42] target/arm: Convert Neon VTRN to decodetree
+[PULL 24/29] target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree
-Convert the Neon VTRN insn to decodetree. This is the last insn in the
+Convert the VQSHLU and QVSHL 2-reg-shift insns to decodetree.
-Neon data-processing group, so we can remove all the now-unused old
+These are the last of the simple shift-by-immediate insns.
 decoder framework.
 It's possible that there's a more efficient implementation of
 VTRN, but for this conversion we just copy the existing approach.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-21-peter.maydell@linaro.org
+Message-id: 20200522145520.6778-5-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       |   2 +-
+ target/arm/neon-dp.decode       |  15 +++++
- target/arm/translate-neon.inc.c |  90 ++++++++
+ target/arm/translate-neon.inc.c | 108 +++++++++++++++++++++++++++++++
- target/arm/translate.c          | 363 +-------------------------------
+ target/arm/translate.c          | 110 +-------------------------------
-files changed, 93 insertions(+), 362 deletions(-)
+files changed, 126 insertions(+), 107 deletions(-)
 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/neon-dp.decode
 +++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
+@@ -XXX,XX +XXX,XX @@ VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
-     VNEG_F       1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc
+ VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
+ VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
-     VSWP         1111 001 11 . 11 .. 10 .... 0 0000 . . 0 .... @2misc
+ VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
--
++
-+    VTRN         1111 001 11 . 11 .. 10 .... 0 0001 . . 0 .... @2misc
++VQSHLU_64_2sh    1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_d
-     VUZP         1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc
++VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_s
-     VZIP         1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc
++VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_h
++VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_b
 +
 +VQSHL_S_64_2sh   1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
 +VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
 +VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
 +VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
 +
 +VQSHL_U_64_2sh   1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
 +VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
 +VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
 +VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.inc.c
 +++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VSWP(DisasContext *s, arg_2misc *a)
+@@ -XXX,XX +XXX,XX @@ static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a)
+         return do_vector_2sh(s, a, tcg_gen_gvec_shri);
-     return true;
+     }
  }
-+static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1)
++
 +static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a,
 +                             NeonGenTwo64OpEnvFn *fn)
 +{
-+    TCGv_i32 rd, tmp;
++    /*
-+
++     * 2-reg-and-shift operations, size == 3 case, where the
-+    rd = tcg_temp_new_i32();
++     * function needs to be passed cpu_env.
-+    tmp = tcg_temp_new_i32();
++     */
-+
++    TCGv_i64 constimm;
 +    tcg_gen_shli_i32(rd, t0, 8);
 +    tcg_gen_andi_i32(rd, rd, 0xff00ff00);
 +    tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
 +    tcg_gen_or_i32(rd, rd, tmp);
 +
 +    tcg_gen_shri_i32(t1, t1, 8);
 +    tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
 +    tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
 +    tcg_gen_or_i32(t1, t1, tmp);
 +    tcg_gen_mov_i32(t0, rd);
 +
 +    tcg_temp_free_i32(tmp);
 +    tcg_temp_free_i32(rd);
 +}
 +
 +static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
 +{
 +    TCGv_i32 rd, tmp;
 +
 +    rd = tcg_temp_new_i32();
 +    tmp = tcg_temp_new_i32();
 +
 +    tcg_gen_shli_i32(rd, t0, 16);
 +    tcg_gen_andi_i32(tmp, t1, 0xffff);
 +    tcg_gen_or_i32(rd, rd, tmp);
 +    tcg_gen_shri_i32(t1, t1, 16);
 +    tcg_gen_andi_i32(tmp, t0, 0xffff0000);
 +    tcg_gen_or_i32(t1, t1, tmp);
 +    tcg_gen_mov_i32(t0, rd);
 +
 +    tcg_temp_free_i32(tmp);
 +    tcg_temp_free_i32(rd);
 +}
 +
 +static bool trans_VTRN(DisasContext *s, arg_2misc *a)
 +{
 +    TCGv_i32 tmp, tmp2;
 +    int pass;
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
 +        return false;
 +    }
 ...
 +    if (!dc_isar_feature(aa32_simd_r32, s) &&
 +        ((a->vd | a->vm) & 0x10)) {
 +        return false;
 +    }
 +
-+    if ((a->vd | a->vm) & a->q) {
++    if ((a->vm | a->vd) & a->q) {
 +        return false;
 +    }
 +
 +    if (a->size == 3) {
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
-+    if (a->size == 2) {
++    /*
-+        for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) {
++     * To avoid excessive duplication of ops we implement shift
-+            tmp = neon_load_reg(a->vm, pass);
++     * by immediate using the variable shift operations.
-+            tmp2 = neon_load_reg(a->vd, pass + 1);
++     */
-+            neon_store_reg(a->vm, pass, tmp2);
++    constimm = tcg_const_i64(dup_const(a->size, a->shift));
-+            neon_store_reg(a->vd, pass + 1, tmp);
++
-+        }
++    for (pass = 0; pass < a->q + 1; pass++) {
-+    } else {
++        TCGv_i64 tmp = tcg_temp_new_i64();
-+        for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
++
-+            tmp = neon_load_reg(a->vm, pass);
++        neon_load_reg64(tmp, a->vm + pass);
-+            tmp2 = neon_load_reg(a->vd, pass);
++        fn(tmp, cpu_env, tmp, constimm);
-+            if (a->size == 0) {
++        neon_store_reg64(tmp, a->vd + pass);
-+                gen_neon_trn_u8(tmp, tmp2);
++    }
-+            } else {
++    tcg_temp_free_i64(constimm);
 +                gen_neon_trn_u16(tmp, tmp2);
 +            }
 +            neon_store_reg(a->vm, pass, tmp2);
 +            neon_store_reg(a->vd, pass, tmp);
 +        }
 +    }
 +    return true;
 +}
++
++static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
++                             NeonGenTwoOpEnvFn *fn)
++{
++    /*
++     * 2-reg-and-shift operations, size < 3 case, where the
++     * helper needs to be passed cpu_env.
++     */
++    TCGv_i32 constimm;
++    int pass;
++
++    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
++        return false;
++    }
++
++    /* UNDEF accesses to D16-D31 if they don't exist. */
++    if (!dc_isar_feature(aa32_simd_r32, s) &&
++        ((a->vd | a->vm) & 0x10)) {
++        return false;
++    }
++
++    if ((a->vm | a->vd) & a->q) {
++        return false;
++    }
++
++    if (!vfp_access_check(s)) {
++        return true;
++    }
++
++    /*
++     * To avoid excessive duplication of ops we implement shift
++     * by immediate using the variable shift operations.
++     */
++    constimm = tcg_const_i32(dup_const(a->size, a->shift));
++
++    for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
++        TCGv_i32 tmp = neon_load_reg(a->vm, pass);
++        fn(tmp, cpu_env, tmp, constimm);
++        neon_store_reg(a->vd, pass, tmp);
++    }
++    tcg_temp_free_i32(constimm);
++    return true;
++}
++
++#define DO_2SHIFT_ENV(INSN, FUNC)                                       \
++    static bool trans_##INSN##_64_2sh(DisasContext *s, arg_2reg_shift *a) \
++    {                                                                   \
++        return do_2shift_env_64(s, a, gen_helper_neon_##FUNC##64);      \
++    }                                                                   \
++    static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a)  \
++    {                                                                   \
++        static NeonGenTwoOpEnvFn * const fns[] = {                      \
++            gen_helper_neon_##FUNC##8,                                  \
++            gen_helper_neon_##FUNC##16,                                 \
++            gen_helper_neon_##FUNC##32,                                 \
++        };                                                              \
++        assert(a->size < ARRAY_SIZE(fns));                              \
++        return do_2shift_env_32(s, a, fns[a->size]);                    \
++    }
++
++DO_2SHIFT_ENV(VQSHLU, qshlu_s)
++DO_2SHIFT_ENV(VQSHL_U, qshl_u)
++DO_2SHIFT_ENV(VQSHL_S, qshl_s)
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc)
+@@ -XXX,XX +XXX,XX @@ static inline void gen_neon_rsb(int size, TCGv_i32 t0, TCGv_i32 t1)
-     gen_rfe(s, pc, load_cpu_field(spsr));
+     }
  }
--static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1)
+-#define GEN_NEON_INTEGER_OP_ENV(name) do { \
--{
+-    switch ((size << 1) | u) { \
--    TCGv_i32 rd, tmp;
+-    case 0: \
--
+-        gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
--    rd = tcg_temp_new_i32();
+-        break; \
--    tmp = tcg_temp_new_i32();
+-    case 1: \
--
+-        gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
--    tcg_gen_shli_i32(rd, t0, 8);
+-        break; \
--    tcg_gen_andi_i32(rd, rd, 0xff00ff00);
+-    case 2: \
--    tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
+-        gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
--    tcg_gen_or_i32(rd, rd, tmp);
+-        break; \
--
+-    case 3: \
--    tcg_gen_shri_i32(t1, t1, 8);
+-        gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
--    tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
+-        break; \
--    tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
+-    case 4: \
--    tcg_gen_or_i32(t1, t1, tmp);
+-        gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
--    tcg_gen_mov_i32(t0, rd);
+-        break; \
--
+-    case 5: \
--    tcg_temp_free_i32(tmp);
+-        gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
--    tcg_temp_free_i32(rd);
+-        break; \
--}
+-    default: return 1; \
--
+-    }} while (0)
--static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
+-
--{
+ static TCGv_i32 neon_load_scratch(int scratch)
--    TCGv_i32 rd, tmp;
+ {
--
+     TCGv_i32 tmp = tcg_temp_new_i32();
--    rd = tcg_temp_new_i32();
+@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
--    tmp = tcg_temp_new_i32();
+     int size;
--
+     int shift;
--    tcg_gen_shli_i32(rd, t0, 16);
+     int pass;
--    tcg_gen_andi_i32(tmp, t1, 0xffff);
+-    int count;
--    tcg_gen_or_i32(rd, rd, tmp);
+     int u;
--    tcg_gen_shri_i32(t1, t1, 16);
+     int vec_size;
--    tcg_gen_andi_i32(tmp, t0, 0xffff0000);
+     uint32_t imm;
--    tcg_gen_or_i32(t1, t1, tmp);
+@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
--    tcg_gen_mov_i32(t0, rd);
+             case 3: /* VRSRA */
--
+             case 4: /* VSRI */
--    tcg_temp_free_i32(tmp);
+             case 5: /* VSHL, VSLI */
--    tcg_temp_free_i32(rd);
++            case 6: /* VQSHLU */
--}
++            case 7: /* VQSHL */
--
+                 return 1; /* handled by decodetree */
--/* Symbolic constants for op fields for Neon 2-register miscellaneous.
+             default:
-- * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B
+                 break;
-- * table A7-13.
+@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-- */
+                     size--;
--#define NEON_2RM_VREV64 0
+             }
--#define NEON_2RM_VREV32 1
+             shift = (insn >> 16) & ((1 << (3 + size)) - 1);
--#define NEON_2RM_VREV16 2
+-            if (op < 8) {
--#define NEON_2RM_VPADDL 4
+-                /* Shift by immediate:
--#define NEON_2RM_VPADDL_U 5
+-                   VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU.  */
--#define NEON_2RM_AESE 6 /* Includes AESD */
+-                if (q && ((rd | rm) & 1)) {
 -#define NEON_2RM_AESMC 7 /* Includes AESIMC */
 -#define NEON_2RM_VCLS 8
 -#define NEON_2RM_VCLZ 9
 -#define NEON_2RM_VCNT 10
 -#define NEON_2RM_VMVN 11
 -#define NEON_2RM_VPADAL 12
 -#define NEON_2RM_VPADAL_U 13
 -#define NEON_2RM_VQABS 14
 -#define NEON_2RM_VQNEG 15
 -#define NEON_2RM_VCGT0 16
 -#define NEON_2RM_VCGE0 17
 -#define NEON_2RM_VCEQ0 18
 -#define NEON_2RM_VCLE0 19
 -#define NEON_2RM_VCLT0 20
 -#define NEON_2RM_SHA1H 21
 -#define NEON_2RM_VABS 22
 -#define NEON_2RM_VNEG 23
 -#define NEON_2RM_VCGT0_F 24
 -#define NEON_2RM_VCGE0_F 25
 -#define NEON_2RM_VCEQ0_F 26
 -#define NEON_2RM_VCLE0_F 27
 -#define NEON_2RM_VCLT0_F 28
 -#define NEON_2RM_VABS_F 30
 -#define NEON_2RM_VNEG_F 31
 -#define NEON_2RM_VSWP 32
 -#define NEON_2RM_VTRN 33
 -#define NEON_2RM_VUZP 34
 -#define NEON_2RM_VZIP 35
 -#define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
 -#define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
 -#define NEON_2RM_VSHLL 38
 -#define NEON_2RM_SHA1SU1 39 /* Includes SHA256SU0 */
 -#define NEON_2RM_VRINTN 40
 -#define NEON_2RM_VRINTX 41
 -#define NEON_2RM_VRINTA 42
 -#define NEON_2RM_VRINTZ 43
 -#define NEON_2RM_VCVT_F16_F32 44
 -#define NEON_2RM_VRINTM 45
 -#define NEON_2RM_VCVT_F32_F16 46
 -#define NEON_2RM_VRINTP 47
 -#define NEON_2RM_VCVTAU 48
 -#define NEON_2RM_VCVTAS 49
 -#define NEON_2RM_VCVTNU 50
 -#define NEON_2RM_VCVTNS 51
 -#define NEON_2RM_VCVTPU 52
 -#define NEON_2RM_VCVTPS 53
 -#define NEON_2RM_VCVTMU 54
 -#define NEON_2RM_VCVTMS 55
 -#define NEON_2RM_VRECPE 56
 -#define NEON_2RM_VRSQRTE 57
 -#define NEON_2RM_VRECPE_F 58
 -#define NEON_2RM_VRSQRTE_F 59
 -#define NEON_2RM_VCVT_FS 60
 -#define NEON_2RM_VCVT_FU 61
 -#define NEON_2RM_VCVT_SF 62
 -#define NEON_2RM_VCVT_UF 63
 -
 -/* Each entry in this array has bit n set if the insn allows
 - * size value n (otherwise it will UNDEF). Since unallocated
 - * op values will have no bits set they always UNDEF.
 - */
 -static const uint8_t neon_2rm_sizes[] = {
 -    [NEON_2RM_VREV64] = 0x7,
 -    [NEON_2RM_VREV32] = 0x3,
 -    [NEON_2RM_VREV16] = 0x1,
 -    [NEON_2RM_VPADDL] = 0x7,
 -    [NEON_2RM_VPADDL_U] = 0x7,
 -    [NEON_2RM_AESE] = 0x1,
 -    [NEON_2RM_AESMC] = 0x1,
 -    [NEON_2RM_VCLS] = 0x7,
 -    [NEON_2RM_VCLZ] = 0x7,
 -    [NEON_2RM_VCNT] = 0x1,
 -    [NEON_2RM_VMVN] = 0x1,
 -    [NEON_2RM_VPADAL] = 0x7,
 -    [NEON_2RM_VPADAL_U] = 0x7,
 -    [NEON_2RM_VQABS] = 0x7,
 -    [NEON_2RM_VQNEG] = 0x7,
 -    [NEON_2RM_VCGT0] = 0x7,
 -    [NEON_2RM_VCGE0] = 0x7,
 -    [NEON_2RM_VCEQ0] = 0x7,
 -    [NEON_2RM_VCLE0] = 0x7,
 -    [NEON_2RM_VCLT0] = 0x7,
 -    [NEON_2RM_SHA1H] = 0x4,
 -    [NEON_2RM_VABS] = 0x7,
 -    [NEON_2RM_VNEG] = 0x7,
 -    [NEON_2RM_VCGT0_F] = 0x4,
 -    [NEON_2RM_VCGE0_F] = 0x4,
 -    [NEON_2RM_VCEQ0_F] = 0x4,
 -    [NEON_2RM_VCLE0_F] = 0x4,
 -    [NEON_2RM_VCLT0_F] = 0x4,
 -    [NEON_2RM_VABS_F] = 0x4,
 -    [NEON_2RM_VNEG_F] = 0x4,
 -    [NEON_2RM_VSWP] = 0x1,
 -    [NEON_2RM_VTRN] = 0x7,
 -    [NEON_2RM_VUZP] = 0x7,
 -    [NEON_2RM_VZIP] = 0x7,
 -    [NEON_2RM_VMOVN] = 0x7,
 -    [NEON_2RM_VQMOVN] = 0x7,
 -    [NEON_2RM_VSHLL] = 0x7,
 -    [NEON_2RM_SHA1SU1] = 0x4,
 -    [NEON_2RM_VRINTN] = 0x4,
 -    [NEON_2RM_VRINTX] = 0x4,
 -    [NEON_2RM_VRINTA] = 0x4,
 -    [NEON_2RM_VRINTZ] = 0x4,
 -    [NEON_2RM_VCVT_F16_F32] = 0x2,
 -    [NEON_2RM_VRINTM] = 0x4,
 -    [NEON_2RM_VCVT_F32_F16] = 0x2,
 -    [NEON_2RM_VRINTP] = 0x4,
 -    [NEON_2RM_VCVTAU] = 0x4,
 -    [NEON_2RM_VCVTAS] = 0x4,
 -    [NEON_2RM_VCVTNU] = 0x4,
 -    [NEON_2RM_VCVTNS] = 0x4,
 -    [NEON_2RM_VCVTPU] = 0x4,
 -    [NEON_2RM_VCVTPS] = 0x4,
 -    [NEON_2RM_VCVTMU] = 0x4,
 -    [NEON_2RM_VCVTMS] = 0x4,
 -    [NEON_2RM_VRECPE] = 0x4,
 -    [NEON_2RM_VRSQRTE] = 0x4,
 -    [NEON_2RM_VRECPE_F] = 0x4,
 -    [NEON_2RM_VRSQRTE_F] = 0x4,
 -    [NEON_2RM_VCVT_FS] = 0x4,
 -    [NEON_2RM_VCVT_FU] = 0x4,
 -    [NEON_2RM_VCVT_SF] = 0x4,
 -    [NEON_2RM_VCVT_UF] = 0x4,
 -};
 -
  static void gen_gvec_fn3_qc(uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_ofs,
                              uint32_t opr_sz, uint32_t max_sz,
                              gen_helper_gvec_3_ptr *fn)
@@ -XXX,XX +XXX,XX @@ void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
      tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]);
  }
 -/* Translate a NEON data processing instruction.  Return nonzero if the
 -   instruction is invalid.
 -   We process data in a mixture of 32-bit and 64-bit chunks.
 -   Mostly we use 32-bit chunks so we can use normal scalar instructions.  */
 -
 -static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
 -{
 -    int op;
 -    int q;
 -    int rd, rm;
 -    int size;
 -    int pass;
 -    int u;
 -    TCGv_i32 tmp, tmp2;
 -
 -    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
 -        return 1;
 -    }
 -
 -    /* FIXME: this access check should not take precedence over UNDEF
 -     * for invalid encodings; we will generate incorrect syndrome information
 -     * for attempts to execute invalid vfp/neon encodings with FP disabled.
 -     */
 -    if (s->fp_excp_el) {
 -        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
 -                           syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
 -        return 0;
 -    }
 -
 -    if (!s->vfp_enabled)
 -      return 1;
 -    q = (insn & (1 << 6)) != 0;
 -    u = (insn >> 24) & 1;
 -    VFP_DREG_D(rd, insn);
 -    VFP_DREG_M(rm, insn);
 -    size = (insn >> 20) & 3;
 -
 -    if ((insn & (1 << 23)) == 0) {
 -        /* Three register same length: handled by decodetree */
 -        return 1;
 -    } else if (insn & (1 << 4)) {
 -        /* Two registers and shift or reg and imm: handled by decodetree */
 -        return 1;
 -    } else { /* (insn & 0x00800010 == 0x00800000) */
 -        if (size != 3) {
 -            /*
 -             * Three registers of different lengths, or two registers and
 -             * a scalar: handled by decodetree
 -             */
 -            return 1;
 -        } else { /* size == 3 */
 -            if (!u) {
 -                /* Extract: handled by decodetree */
 -                return 1;
 -            } else if ((insn & (1 << 11)) == 0) {
 -                /* Two register misc.  */
 -                op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
 -                size = (insn >> 18) & 3;
 -                /* UNDEF for unknown op values and bad op-size combinations */
 -                if ((neon_2rm_sizes[op] & (1 << size)) == 0) {
 -                    return 1;
 -                }
--                if (q && ((rm | rd) & 1)) {
+-                if (!u && (op == 4 || op == 6)) {
 -                    return 1;
 -                }
--                switch (op) {
+-                /* Right shifts are encoded as N - shift, where N is the
--                case NEON_2RM_VREV64:
+-                   element size in bits.  */
--                case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U:
+-                if (op <= 4) {
--                case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U:
+-                    shift = shift - (1 << (size + 3));
--                case NEON_2RM_VUZP:
+-                }
--                case NEON_2RM_VZIP:
+-
--                case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN:
+-                if (size == 3) {
--                case NEON_2RM_VSHLL:
+-                    count = q + 1;
--                case NEON_2RM_VCVT_F16_F32:
+-                } else {
--                case NEON_2RM_VCVT_F32_F16:
+-                    count = q ? 4: 2;
--                case NEON_2RM_VMVN:
+-                }
--                case NEON_2RM_VNEG:
+-
--                case NEON_2RM_VABS:
+-                /* To avoid excessive duplication of ops we implement shift
--                case NEON_2RM_VCEQ0:
+-                 * by immediate using the variable shift operations.
--                case NEON_2RM_VCGT0:
+-                  */
--                case NEON_2RM_VCLE0:
+-                imm = dup_const(size, shift);
--                case NEON_2RM_VCGE0:
+-
--                case NEON_2RM_VCLT0:
+-                for (pass = 0; pass < count; pass++) {
--                case NEON_2RM_AESE: case NEON_2RM_AESMC:
+-                    if (size == 3) {
--                case NEON_2RM_SHA1H:
+-                        neon_load_reg64(cpu_V0, rm + pass);
--                case NEON_2RM_SHA1SU1:
+-                        tcg_gen_movi_i64(cpu_V1, imm);
--                case NEON_2RM_VREV32:
+-                        switch (op) {
--                case NEON_2RM_VREV16:
+-                        case 6: /* VQSHLU */
--                case NEON_2RM_VCLS:
+-                            gen_helper_neon_qshlu_s64(cpu_V0, cpu_env,
--                case NEON_2RM_VCLZ:
+-                                                      cpu_V0, cpu_V1);
--                case NEON_2RM_VCNT:
+-                            break;
--                case NEON_2RM_VABS_F:
+-                        case 7: /* VQSHL */
--                case NEON_2RM_VNEG_F:
+-                            if (u) {
--                case NEON_2RM_VRECPE:
+-                                gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
--                case NEON_2RM_VRSQRTE:
+-                                                         cpu_V0, cpu_V1);
--                case NEON_2RM_VQABS:
+-                            } else {
--                case NEON_2RM_VQNEG:
+-                                gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
--                case NEON_2RM_VRECPE_F:
+-                                                         cpu_V0, cpu_V1);
--                case NEON_2RM_VRSQRTE_F:
+-                            }
--                case NEON_2RM_VCVT_FS:
+-                            break;
--                case NEON_2RM_VCVT_FU:
+-                        default:
--                case NEON_2RM_VCVT_SF:
+-                            g_assert_not_reached();
 -                case NEON_2RM_VCVT_UF:
 -                case NEON_2RM_VRINTX:
 -                case NEON_2RM_VCGT0_F:
 -                case NEON_2RM_VCGE0_F:
 -                case NEON_2RM_VCEQ0_F:
 -                case NEON_2RM_VCLE0_F:
 -                case NEON_2RM_VCLT0_F:
 -                case NEON_2RM_VRINTN:
 -                case NEON_2RM_VRINTA:
 -                case NEON_2RM_VRINTM:
 -                case NEON_2RM_VRINTP:
 -                case NEON_2RM_VRINTZ:
 -                case NEON_2RM_VCVTAU:
 -                case NEON_2RM_VCVTAS:
 -                case NEON_2RM_VCVTNU:
 -                case NEON_2RM_VCVTNS:
 -                case NEON_2RM_VCVTPU:
 -                case NEON_2RM_VCVTPS:
 -                case NEON_2RM_VCVTMU:
 -                case NEON_2RM_VCVTMS:
 -                case NEON_2RM_VSWP:
 -                    /* handled by decodetree */
 -                    return 1;
 -                case NEON_2RM_VTRN:
 -                    if (size == 2) {
 -                        int n;
 -                        for (n = 0; n < (q ? 4 : 2); n += 2) {
 -                            tmp = neon_load_reg(rm, n);
 -                            tmp2 = neon_load_reg(rd, n + 1);
 -                            neon_store_reg(rm, n, tmp2);
 -                            neon_store_reg(rd, n + 1, tmp);
 -                        }
--                    } else {
+-                        neon_store_reg64(cpu_V0, rd + pass);
--                        goto elementwise;
+-                    } else { /* size < 3 */
--                    }
+-                        /* Operands in T0 and T1.  */
 -                    break;
 -
 -                default:
 -                elementwise:
 -                    for (pass = 0; pass < (q ? 4 : 2); pass++) {
 -                        tmp = neon_load_reg(rm, pass);
+-                        tmp2 = tcg_temp_new_i32();
+-                        tcg_gen_movi_i32(tmp2, imm);
 -                        switch (op) {
--                        case NEON_2RM_VTRN:
+-                        case 6: /* VQSHLU */
 -                            tmp2 = neon_load_reg(rd, pass);
 -                            switch (size) {
--                            case 0: gen_neon_trn_u8(tmp, tmp2); break;
+-                            case 0:
--                            case 1: gen_neon_trn_u16(tmp, tmp2); break;
+-                                gen_helper_neon_qshlu_s8(tmp, cpu_env,
--                            default: abort();
+-                                                         tmp, tmp2);
 -                                break;
 -                            case 1:
 -                                gen_helper_neon_qshlu_s16(tmp, cpu_env,
 -                                                          tmp, tmp2);
 -                                break;
 -                            case 2:
 -                                gen_helper_neon_qshlu_s32(tmp, cpu_env,
 -                                                          tmp, tmp2);
 -                                break;
 -                            default:
 -                                abort();
 -                            }
--                            neon_store_reg(rm, pass, tmp2);
+-                            break;
 -                        case 7: /* VQSHL */
 -                            GEN_NEON_INTEGER_OP_ENV(qshl);
 -                            break;
 -                        default:
--                            /* Reserved op values were caught by the
+-                            g_assert_not_reached();
 -                             * neon_2rm_sizes[] check earlier.
 -                             */
 -                            abort();
 -                        }
+-                        tcg_temp_free_i32(tmp2);
 -                        neon_store_reg(rd, pass, tmp);
 -                    }
--                    break;
+-                } /* for pass */
--                }
+-            } else if (op < 10) {
--            } else {
++            if (op < 10) {
--                /* VTBL, VTBX, VDUP: handled by decodetree */
+                 /* Shift by immediate and narrow:
--                return 1;
+                    VSHRN, VRSHRN, VQSHRN, VQRSHRN.  */
--            }
+                 int input_unsigned = (op == 8) ? !u : u;
 -        }
 -    }
 -    return 0;
 -}
 -
  static int disas_coproc_insn(DisasContext *s, uint32_t insn)
  {
      int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
          }
          /* fall back to legacy decoder */
 -        if (((insn >> 25) & 7) == 1) {
 -            /* NEON Data processing.  */
 -            if (disas_neon_data_insn(s, insn)) {
 -                goto illegal_op;
 -            }
 -            return;
 -        }
          if ((insn & 0x0e000f00) == 0x0c000100) {
              if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
                  /* iWMMXt register transfer.  */
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
              break;
          }
          if (((insn >> 24) & 3) == 3) {
 -            /* Translate into the equivalent ARM encoding.  */
 -            insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
 -            if (disas_neon_data_insn(s, insn)) {
 -                goto illegal_op;
 -            }
 +            /* Neon DP, but failed disas_neon_dp() */
 +            goto illegal_op;
          } else if (((insn >> 8) & 0xe) == 10) {
              /* VFP, but failed disas_vfp.  */
              goto illegal_op;
 --
 .20.1

-[PULL 08/42] target/arm: Convert Neon VCVT f16/f32 insns to decodetree
+[PULL 25/29] target/arm: Convert Neon narrowing shifts with op==8 to decodetree
-Convert the Neon insns in the 2-reg-misc group which are
+Convert the Neon narrowing shifts where op==8 to decodetree:
-VCVT between f32 and f16 to decodetree.
+ * VSHRN
  * VRSHRN
  * VQSHRUN
  * VQRSHRUN
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-7-peter.maydell@linaro.org
+Message-id: 20200522145520.6778-6-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       |  3 ++
+ target/arm/neon-dp.decode       |  27 ++++++
- target/arm/translate-neon.inc.c | 96 +++++++++++++++++++++++++++++++++
+ target/arm/translate-neon.inc.c | 167 ++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 65 ++--------------------
+ target/arm/translate.c          |   1 +
-files changed, 102 insertions(+), 62 deletions(-)
+files changed, 195 insertions(+)
 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/neon-dp.decode
 +++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
+@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
-     VQMOVN_U     1111 001 11 . 11 .. 10 .... 0 0101 1 . 0 .... @2misc_q0
+ @2reg_shl_b      .... ... . . . 001 shift:3  .... .... 0 q:1 . . .... \
+                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0
-     VSHLL        1111 001 11 . 11 .. 10 .... 0 0110 0 . 0 .... @2misc_q0
-+
++# Narrowing right shifts: here the Q bit is part of the opcode decode
-+    VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0
++@2reg_shrn_d     .... ... . . . 1 ..... .... .... 0 . . . .... \
-+    VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0
++                 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 q=0 \
-   ]
++                 shift=%neon_rshift_i5
++@2reg_shrn_s     .... ... . . . 01 .... .... .... 0 . . . .... \
-   # Subgroup for size != 0b11
++                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0 \
 +                 shift=%neon_rshift_i4
 +@2reg_shrn_h     .... ... . . . 001 ... .... .... 0 . . . .... \
 +                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 \
 +                 shift=%neon_rshift_i3
 +
  VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
  VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
  VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
@@ -XXX,XX +XXX,XX @@ VQSHL_U_64_2sh   1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
  VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
  VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
  VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
 +
 +VSHRN_64_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
 +VSHRN_32_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
 +VSHRN_16_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
 +
 +VRSHRN_64_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
 +VRSHRN_32_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
 +VRSHRN_16_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
 +
 +VQSHRUN_64_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
 +VQSHRUN_32_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
 +VQSHRUN_16_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
 +
 +VQRSHRUN_64_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
 +VQRSHRUN_32_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
 +VQRSHRUN_16_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.inc.c
 +++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a)
+@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
-     tcg_temp_free_i32(rm1);
+ DO_2SHIFT_ENV(VQSHLU, qshlu_s)
-     return true;
+ DO_2SHIFT_ENV(VQSHL_U, qshl_u)
- }
+ DO_2SHIFT_ENV(VQSHL_S, qshl_s)
 +
-+static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a)
++static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
-+{
++                                NeonGenTwo64OpFn *shiftfn,
-+    TCGv_ptr fpst;
++                                NeonGenNarrowEnvFn *narrowfn)
-+    TCGv_i32 ahp, tmp, tmp2, tmp3;
++{
-+
++    /* 2-reg-and-shift narrowing-shift operations, size == 3 case */
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
++    TCGv_i64 constimm, rm1, rm2;
-+        !dc_isar_feature(aa32_fp16_spconv, s)) {
++    TCGv_i32 rd;
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
 +        return false;
 +    }
 +
 +    /* UNDEF accesses to D16-D31 if they don't exist. */
 +    if (!dc_isar_feature(aa32_simd_r32, s) &&
 +        ((a->vd | a->vm) & 0x10)) {
 +        return false;
 +    }
 +
-+    if ((a->vm & 1) || (a->size != 1)) {
++    if (a->vm & 1) {
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
-+    fpst = get_fpstatus_ptr(true);
++    /*
-+    ahp = get_ahp_flag();
++     * This is always a right shift, and the shiftfn is always a
-+    tmp = neon_load_reg(a->vm, 0);
++     * left-shift helper, which thus needs the negated shift count.
-+    gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
++     */
-+    tmp2 = neon_load_reg(a->vm, 1);
++    constimm = tcg_const_i64(-a->shift);
-+    gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp);
++    rm1 = tcg_temp_new_i64();
-+    tcg_gen_shli_i32(tmp2, tmp2, 16);
++    rm2 = tcg_temp_new_i64();
-+    tcg_gen_or_i32(tmp2, tmp2, tmp);
++
-+    tcg_temp_free_i32(tmp);
++    /* Load both inputs first to avoid potential overwrite if rm == rd */
-+    tmp = neon_load_reg(a->vm, 2);
++    neon_load_reg64(rm1, a->vm);
-+    gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
++    neon_load_reg64(rm2, a->vm + 1);
-+    tmp3 = neon_load_reg(a->vm, 3);
++
-+    neon_store_reg(a->vd, 0, tmp2);
++    shiftfn(rm1, rm1, constimm);
-+    gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp);
++    rd = tcg_temp_new_i32();
-+    tcg_gen_shli_i32(tmp3, tmp3, 16);
++    narrowfn(rd, cpu_env, rm1);
-+    tcg_gen_or_i32(tmp3, tmp3, tmp);
++    neon_store_reg(a->vd, 0, rd);
-+    neon_store_reg(a->vd, 1, tmp3);
++
-+    tcg_temp_free_i32(tmp);
++    shiftfn(rm2, rm2, constimm);
-+    tcg_temp_free_i32(ahp);
++    rd = tcg_temp_new_i32();
-+    tcg_temp_free_ptr(fpst);
++    narrowfn(rd, cpu_env, rm2);
 +    neon_store_reg(a->vd, 1, rd);
 +
 +    tcg_temp_free_i64(rm1);
 +    tcg_temp_free_i64(rm2);
 +    tcg_temp_free_i64(constimm);
 +
 +    return true;
 +}
 +
-+static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a)
++static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
-+{
++                                NeonGenTwoOpFn *shiftfn,
-+    TCGv_ptr fpst;
++                                NeonGenNarrowEnvFn *narrowfn)
-+    TCGv_i32 ahp, tmp, tmp2, tmp3;
++{
-+
++    /* 2-reg-and-shift narrowing-shift operations, size < 3 case */
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
++    TCGv_i32 constimm, rm1, rm2, rm3, rm4;
-+        !dc_isar_feature(aa32_fp16_spconv, s)) {
++    TCGv_i64 rtmp;
 +    uint32_t imm;
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
 +        return false;
 +    }
 +
 +    /* UNDEF accesses to D16-D31 if they don't exist. */
 +    if (!dc_isar_feature(aa32_simd_r32, s) &&
 +        ((a->vd | a->vm) & 0x10)) {
 +        return false;
 +    }
 +
-+    if ((a->vd & 1) || (a->size != 1)) {
++    if (a->vm & 1) {
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
-+    fpst = get_fpstatus_ptr(true);
++    /*
-+    ahp = get_ahp_flag();
++     * This is always a right shift, and the shiftfn is always a
-+    tmp3 = tcg_temp_new_i32();
++     * left-shift helper, which thus needs the negated shift count
-+    tmp = neon_load_reg(a->vm, 0);
++     * duplicated into each lane of the immediate value.
-+    tmp2 = neon_load_reg(a->vm, 1);
++     */
-+    tcg_gen_ext16u_i32(tmp3, tmp);
++    if (a->size == 1) {
-+    gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
++        imm = (uint16_t)(-a->shift);
-+    neon_store_reg(a->vd, 0, tmp3);
++        imm |= imm << 16;
-+    tcg_gen_shri_i32(tmp, tmp, 16);
++    } else {
-+    gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp);
++        /* size == 2 */
-+    neon_store_reg(a->vd, 1, tmp);
++        imm = -a->shift;
-+    tmp3 = tcg_temp_new_i32();
++    }
-+    tcg_gen_ext16u_i32(tmp3, tmp2);
++    constimm = tcg_const_i32(imm);
-+    gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
++
-+    neon_store_reg(a->vd, 2, tmp3);
++    /* Load all inputs first to avoid potential overwrite */
-+    tcg_gen_shri_i32(tmp2, tmp2, 16);
++    rm1 = neon_load_reg(a->vm, 0);
-+    gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp);
++    rm2 = neon_load_reg(a->vm, 1);
-+    neon_store_reg(a->vd, 3, tmp2);
++    rm3 = neon_load_reg(a->vm + 1, 0);
-+    tcg_temp_free_i32(ahp);
++    rm4 = neon_load_reg(a->vm + 1, 1);
-+    tcg_temp_free_ptr(fpst);
++    rtmp = tcg_temp_new_i64();
 +
 +    shiftfn(rm1, rm1, constimm);
 +    shiftfn(rm2, rm2, constimm);
 +
 +    tcg_gen_concat_i32_i64(rtmp, rm1, rm2);
 +    tcg_temp_free_i32(rm2);
 +
 +    narrowfn(rm1, cpu_env, rtmp);
 +    neon_store_reg(a->vd, 0, rm1);
 +
 +    shiftfn(rm3, rm3, constimm);
 +    shiftfn(rm4, rm4, constimm);
 +    tcg_temp_free_i32(constimm);
 +
 +    tcg_gen_concat_i32_i64(rtmp, rm3, rm4);
 +    tcg_temp_free_i32(rm4);
 +
 +    narrowfn(rm3, cpu_env, rtmp);
 +    tcg_temp_free_i64(rtmp);
 +    neon_store_reg(a->vd, 1, rm3);
 +    return true;
 +}
++
++#define DO_2SN_64(INSN, FUNC, NARROWFUNC)                               \
++    static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a)  \
++    {                                                                   \
++        return do_2shift_narrow_64(s, a, FUNC, NARROWFUNC);             \
++    }
++#define DO_2SN_32(INSN, FUNC, NARROWFUNC)                               \
++    static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a)  \
++    {                                                                   \
++        return do_2shift_narrow_32(s, a, FUNC, NARROWFUNC);             \
++    }
++
++static void gen_neon_narrow_u32(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
++{
++    tcg_gen_extrl_i64_i32(dest, src);
++}
++
++static void gen_neon_narrow_u16(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
++{
++    gen_helper_neon_narrow_u16(dest, src);
++}
++
++static void gen_neon_narrow_u8(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
++{
++    gen_helper_neon_narrow_u8(dest, src);
++}
++
++DO_2SN_64(VSHRN_64, gen_ushl_i64, gen_neon_narrow_u32)
++DO_2SN_32(VSHRN_32, gen_ushl_i32, gen_neon_narrow_u16)
++DO_2SN_32(VSHRN_16, gen_helper_neon_shl_u16, gen_neon_narrow_u8)
++
++DO_2SN_64(VRSHRN_64, gen_helper_neon_rshl_u64, gen_neon_narrow_u32)
++DO_2SN_32(VRSHRN_32, gen_helper_neon_rshl_u32, gen_neon_narrow_u16)
++DO_2SN_32(VRSHRN_16, gen_helper_neon_rshl_u16, gen_neon_narrow_u8)
++
++DO_2SN_64(VQSHRUN_64, gen_sshl_i64, gen_helper_neon_unarrow_sat32)
++DO_2SN_32(VQSHRUN_32, gen_sshl_i32, gen_helper_neon_unarrow_sat16)
++DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat8)
++
++DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_sat32)
++DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_sat16)
++DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_sat8)
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
 @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-     int pass;
+             case 5: /* VSHL, VSLI */
-     int u;
+             case 6: /* VQSHLU */
-     int vec_size;
+             case 7: /* VQSHL */
--    TCGv_i32 tmp, tmp2, tmp3;
++            case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
-+    TCGv_i32 tmp, tmp2;
+                 return 1; /* handled by decodetree */
+             default:
-     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+                 break;
          return 1;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                  case NEON_2RM_VZIP:
                  case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN:
                  case NEON_2RM_VSHLL:
 +                case NEON_2RM_VCVT_F16_F32:
 +                case NEON_2RM_VCVT_F32_F16:
                      /* handled by decodetree */
                      return 1;
                  case NEON_2RM_VTRN:
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                          goto elementwise;
                      }
                      break;
 -                case NEON_2RM_VCVT_F16_F32:
 -                {
 -                    TCGv_ptr fpst;
 -                    TCGv_i32 ahp;
 -
 -                    if (!dc_isar_feature(aa32_fp16_spconv, s) ||
 -                        q || (rm & 1)) {
 -                        return 1;
 -                    }
 -                    fpst = get_fpstatus_ptr(true);
 -                    ahp = get_ahp_flag();
 -                    tmp = neon_load_reg(rm, 0);
 -                    gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
 -                    tmp2 = neon_load_reg(rm, 1);
 -                    gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp);
 -                    tcg_gen_shli_i32(tmp2, tmp2, 16);
 -                    tcg_gen_or_i32(tmp2, tmp2, tmp);
 -                    tcg_temp_free_i32(tmp);
 -                    tmp = neon_load_reg(rm, 2);
 -                    gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
 -                    tmp3 = neon_load_reg(rm, 3);
 -                    neon_store_reg(rd, 0, tmp2);
 -                    gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp);
 -                    tcg_gen_shli_i32(tmp3, tmp3, 16);
 -                    tcg_gen_or_i32(tmp3, tmp3, tmp);
 -                    neon_store_reg(rd, 1, tmp3);
 -                    tcg_temp_free_i32(tmp);
 -                    tcg_temp_free_i32(ahp);
 -                    tcg_temp_free_ptr(fpst);
 -                    break;
 -                }
 -                case NEON_2RM_VCVT_F32_F16:
 -                {
 -                    TCGv_ptr fpst;
 -                    TCGv_i32 ahp;
 -                    if (!dc_isar_feature(aa32_fp16_spconv, s) ||
 -                        q || (rd & 1)) {
 -                        return 1;
 -                    }
 -                    fpst = get_fpstatus_ptr(true);
 -                    ahp = get_ahp_flag();
 -                    tmp3 = tcg_temp_new_i32();
 -                    tmp = neon_load_reg(rm, 0);
 -                    tmp2 = neon_load_reg(rm, 1);
 -                    tcg_gen_ext16u_i32(tmp3, tmp);
 -                    gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
 -                    neon_store_reg(rd, 0, tmp3);
 -                    tcg_gen_shri_i32(tmp, tmp, 16);
 -                    gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp);
 -                    neon_store_reg(rd, 1, tmp);
 -                    tmp3 = tcg_temp_new_i32();
 -                    tcg_gen_ext16u_i32(tmp3, tmp2);
 -                    gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
 -                    neon_store_reg(rd, 2, tmp3);
 -                    tcg_gen_shri_i32(tmp2, tmp2, 16);
 -                    gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp);
 -                    neon_store_reg(rd, 3, tmp2);
 -                    tcg_temp_free_i32(ahp);
 -                    tcg_temp_free_ptr(fpst);
 -                    break;
 -                }
                  case NEON_2RM_AESE: case NEON_2RM_AESMC:
                      if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) {
                          return 1;
 --
 .20.1

-[PULL 06/42] target/arm: Convert Neon narrowing moves to decodetree
+[PULL 26/29] target/arm: Convert Neon narrowing shifts with op==9 to decodetree
-Convert the Neon narrowing moves VMQNV, VQMOVN, VQMOVUN in the 2-reg-misc
+Convert the remaining Neon narrowing shifts to decodetree:
-group to decodetree.
+  * VQSHRN
   * VQRSHRN
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-5-peter.maydell@linaro.org
+Message-id: 20200522145520.6778-7-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       |  9 ++++
+ target/arm/neon-dp.decode       |  20 ++++++
- target/arm/translate-neon.inc.c | 59 ++++++++++++++++++++++++
+ target/arm/translate-neon.inc.c |  15 +++++
- target/arm/translate.c          | 81 +--------------------------------
+ target/arm/translate.c          | 110 +-------------------------------
-files changed, 70 insertions(+), 79 deletions(-)
+files changed, 37 insertions(+), 108 deletions(-)
 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/neon-dp.decode
 +++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
+@@ -XXX,XX +XXX,XX @@ VQSHRUN_16_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
+ VQRSHRUN_64_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
-     @2misc       .... ... .. . .. size:2 .. .... . .... q:1 . . .... \
+ VQRSHRUN_32_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
-                  &2misc vm=%vm_dp vd=%vd_dp
+ VQRSHRUN_16_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
-+    @2misc_q0    .... ... .. . .. size:2 .. .... . .... . . . .... \
++
-+                 &2misc vm=%vm_dp vd=%vd_dp q=0
++# VQSHRN with signed input
++VQSHRN_S64_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
-     VREV64       1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc
++VQSHRN_S32_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
++VQSHRN_S16_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
++
++# VQRSHRN with signed input
-     VUZP         1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc
++VQRSHRN_S64_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
-     VZIP         1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc
++VQRSHRN_S32_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
-+
++VQRSHRN_S16_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
-+    VMOVN        1111 001 11 . 11 .. 10 .... 0 0100 0 . 0 .... @2misc_q0
++
-+    # VQMOVUN: unsigned result (source is always signed)
++# VQSHRN with unsigned input
-+    VQMOVUN      1111 001 11 . 11 .. 10 .... 0 0100 1 . 0 .... @2misc_q0
++VQSHRN_U64_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
-+    # VQMOVN: signed result, source may be signed (_S) or unsigned (_U)
++VQSHRN_U32_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
-+    VQMOVN_S     1111 001 11 . 11 .. 10 .... 0 0101 0 . 0 .... @2misc_q0
++VQSHRN_U16_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
-+    VQMOVN_U     1111 001 11 . 11 .. 10 .... 0 0101 1 . 0 .... @2misc_q0
++
-   ]
++# VQRSHRN with unsigned input
++VQRSHRN_U64_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
-   # Subgroup for size != 0b11
++VQRSHRN_U32_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
 +VQRSHRN_U16_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.inc.c
 +++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VZIP(DisasContext *s, arg_2misc *a)
+@@ -XXX,XX +XXX,XX @@ DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat8)
-     };
+ DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_sat32)
-     return do_zip_uzp(s, a, fn[a->q][a->size]);
+ DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_sat16)
- }
+ DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_sat8)
-+
++DO_2SN_64(VQSHRN_S64, gen_sshl_i64, gen_helper_neon_narrow_sat_s32)
-+static bool do_vmovn(DisasContext *s, arg_2misc *a,
++DO_2SN_32(VQSHRN_S32, gen_sshl_i32, gen_helper_neon_narrow_sat_s16)
-+                     NeonGenNarrowEnvFn *narrowfn)
++DO_2SN_32(VQSHRN_S16, gen_helper_neon_shl_s16, gen_helper_neon_narrow_sat_s8)
-+{
++
-+    TCGv_i64 rm;
++DO_2SN_64(VQRSHRN_S64, gen_helper_neon_rshl_s64, gen_helper_neon_narrow_sat_s32)
-+    TCGv_i32 rd0, rd1;
++DO_2SN_32(VQRSHRN_S32, gen_helper_neon_rshl_s32, gen_helper_neon_narrow_sat_s16)
-+
++DO_2SN_32(VQRSHRN_S16, gen_helper_neon_rshl_s16, gen_helper_neon_narrow_sat_s8)
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
++
-+        return false;
++DO_2SN_64(VQSHRN_U64, gen_ushl_i64, gen_helper_neon_narrow_sat_u32)
-+    }
++DO_2SN_32(VQSHRN_U32, gen_ushl_i32, gen_helper_neon_narrow_sat_u16)
-+
++DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_u8)
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
++
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
++DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sat_u32)
-+        ((a->vd | a->vm) & 0x10)) {
++DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sat_u16)
-+        return false;
++DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sat_u8)
 +    }
 +
 +    if (a->vm & 1) {
 +        return false;
 +    }
 +
 +    if (!narrowfn) {
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    rm = tcg_temp_new_i64();
 +    rd0 = tcg_temp_new_i32();
 +    rd1 = tcg_temp_new_i32();
 +
 +    neon_load_reg64(rm, a->vm);
 +    narrowfn(rd0, cpu_env, rm);
 +    neon_load_reg64(rm, a->vm + 1);
 +    narrowfn(rd1, cpu_env, rm);
 +    neon_store_reg(a->vd, 0, rd0);
 +    neon_store_reg(a->vd, 1, rd1);
 +    tcg_temp_free_i64(rm);
 +    return true;
 +}
 +
 +#define DO_VMOVN(INSN, FUNC)                                    \
 +    static bool trans_##INSN(DisasContext *s, arg_2misc *a)     \
 +    {                                                           \
 +        static NeonGenNarrowEnvFn * const narrowfn[] = {        \
 +            FUNC##8,                                            \
 +            FUNC##16,                                           \
 +            FUNC##32,                                           \
 +            NULL,                                               \
 +        };                                                      \
 +        return do_vmovn(s, a, narrowfn[a->size]);               \
 +    }
 +
 +DO_VMOVN(VMOVN, gen_neon_narrow_u)
 +DO_VMOVN(VQMOVUN, gen_helper_neon_unarrow_sat)
 +DO_VMOVN(VQMOVN_S, gen_helper_neon_narrow_sat_s)
 +DO_VMOVN(VQMOVN_U, gen_helper_neon_narrow_sat_u)
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
+@@ -XXX,XX +XXX,XX @@ static inline void gen_neon_unarrow_sats(int size, TCGv_i32 dest, TCGv_i64 src)
-     tcg_temp_free_i32(rd);
+     }
  }
--static inline void gen_neon_narrow(int size, TCGv_i32 dest, TCGv_i64 src)
+-static inline void gen_neon_shift_narrow(int size, TCGv_i32 var, TCGv_i32 shift,
 -                                         int q, int u)
 -{
--    switch (size) {
+-    if (q) {
--    case 0: gen_helper_neon_narrow_u8(dest, src); break;
+-        if (u) {
--    case 1: gen_helper_neon_narrow_u16(dest, src); break;
+-            switch (size) {
--    case 2: tcg_gen_extrl_i64_i32(dest, src); break;
+-            case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
--    default: abort();
+-            case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
--    }
+-            default: abort();
--}
+-            }
--
+-        } else {
--static inline void gen_neon_narrow_sats(int size, TCGv_i32 dest, TCGv_i64 src)
+-            switch (size) {
--{
+-            case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
--    switch (size) {
+-            case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
--    case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break;
+-            default: abort();
--    case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break;
+-            }
--    case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break;
+-        }
--    default: abort();
+-    } else {
--    }
+-        if (u) {
--}
+-            switch (size) {
--
+-            case 1: gen_helper_neon_shl_u16(var, var, shift); break;
--static inline void gen_neon_narrow_satu(int size, TCGv_i32 dest, TCGv_i64 src)
+-            case 2: gen_ushl_i32(var, var, shift); break;
--{
+-            default: abort();
--    switch (size) {
+-            }
--    case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break;
+-        } else {
--    case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break;
+-            switch (size) {
--    case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break;
+-            case 1: gen_helper_neon_shl_s16(var, var, shift); break;
--    default: abort();
+-            case 2: gen_sshl_i32(var, var, shift); break;
--    }
+-            default: abort();
--}
+-            }
--
+-        }
 -static inline void gen_neon_unarrow_sats(int size, TCGv_i32 dest, TCGv_i64 src)
 -{
 -    switch (size) {
 -    case 0: gen_helper_neon_unarrow_sat8(dest, cpu_env, src); break;
 -    case 1: gen_helper_neon_unarrow_sat16(dest, cpu_env, src); break;
 -    case 2: gen_helper_neon_unarrow_sat32(dest, cpu_env, src); break;
 -    default: abort();
 -    }
 -}
 -
  static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u)
  {
      if (u) {
-@@ -XXX,XX +XXX,XX @@ static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u)
-     tcg_temp_free_i32(src);
- }
--static void gen_neon_narrow_op(int op, int u, int size,
--                               TCGv_i32 dest, TCGv_i64 src)
--{
--    if (op) {
--        if (u) {
--            gen_neon_unarrow_sats(size, dest, src);
--        } else {
--            gen_neon_narrow(size, dest, src);
--        }
--    } else {
--        if (u) {
--            gen_neon_narrow_satu(size, dest, src);
--        } else {
--            gen_neon_narrow_sats(size, dest, src);
--        }
--    }
--}
--
- /* Symbolic constants for op fields for Neon 2-register miscellaneous.
-  * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B
-  * table A7-13.
 @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                     !arm_dc_feature(s, ARM_FEATURE_V8)) {
+             case 6: /* VQSHLU */
              case 7: /* VQSHL */
              case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
 +            case 9: /* VQSHRN, VQRSHRN */
                  return 1; /* handled by decodetree */
              default:
                  break;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                      size--;
              }
              shift = (insn >> 16) & ((1 << (3 + size)) - 1);
 -            if (op < 10) {
 -                /* Shift by immediate and narrow:
 -                   VSHRN, VRSHRN, VQSHRN, VQRSHRN.  */
 -                int input_unsigned = (op == 8) ? !u : u;
 -                if (rm & 1) {
 -                    return 1;
 -                }
 -                shift = shift - (1 << (size + 3));
 -                size++;
 -                if (size == 3) {
 -                    tmp64 = tcg_const_i64(shift);
 -                    neon_load_reg64(cpu_V0, rm);
 -                    neon_load_reg64(cpu_V1, rm + 1);
 -                    for (pass = 0; pass < 2; pass++) {
 -                        TCGv_i64 in;
 -                        if (pass == 0) {
 -                            in = cpu_V0;
 -                        } else {
 -                            in = cpu_V1;
 -                        }
 -                        if (q) {
 -                            if (input_unsigned) {
 -                                gen_helper_neon_rshl_u64(cpu_V0, in, tmp64);
 -                            } else {
 -                                gen_helper_neon_rshl_s64(cpu_V0, in, tmp64);
 -                            }
 -                        } else {
 -                            if (input_unsigned) {
 -                                gen_ushl_i64(cpu_V0, in, tmp64);
 -                            } else {
 -                                gen_sshl_i64(cpu_V0, in, tmp64);
 -                            }
 -                        }
 -                        tmp = tcg_temp_new_i32();
 -                        gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
 -                        neon_store_reg(rd, pass, tmp);
 -                    } /* for pass */
 -                    tcg_temp_free_i64(tmp64);
 -                } else {
 -                    if (size == 1) {
 -                        imm = (uint16_t)shift;
 -                        imm |= imm << 16;
 -                    } else {
 -                        /* size == 2 */
 -                        imm = (uint32_t)shift;
 -                    }
 -                    tmp2 = tcg_const_i32(imm);
 -                    tmp4 = neon_load_reg(rm + 1, 0);
 -                    tmp5 = neon_load_reg(rm + 1, 1);
 -                    for (pass = 0; pass < 2; pass++) {
 -                        if (pass == 0) {
 -                            tmp = neon_load_reg(rm, 0);
 -                        } else {
 -                            tmp = tmp4;
 -                        }
 -                        gen_neon_shift_narrow(size, tmp, tmp2, q,
 -                                              input_unsigned);
 -                        if (pass == 0) {
 -                            tmp3 = neon_load_reg(rm, 1);
 -                        } else {
 -                            tmp3 = tmp5;
 -                        }
 -                        gen_neon_shift_narrow(size, tmp3, tmp2, q,
 -                                              input_unsigned);
 -                        tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
 -                        tcg_temp_free_i32(tmp);
 -                        tcg_temp_free_i32(tmp3);
 -                        tmp = tcg_temp_new_i32();
 -                        gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
 -                        neon_store_reg(rd, pass, tmp);
 -                    } /* for pass */
 -                    tcg_temp_free_i32(tmp2);
 -                }
 -            } else if (op == 10) {
 +            if (op == 10) {
                  /* VSHLL, VMOVL */
                  if (q || (rd & 1)) {
                      return 1;
-                 }
--                if ((op != NEON_2RM_VMOVN && op != NEON_2RM_VQMOVN) &&
--                    q && ((rm | rd) & 1)) {
-+                if (q && ((rm | rd) & 1)) {
-                     return 1;
-                 }
-                 switch (op) {
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                 case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U:
-                 case NEON_2RM_VUZP:
-                 case NEON_2RM_VZIP:
-+                case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN:
-                     /* handled by decodetree */
-                     return 1;
-                 case NEON_2RM_VTRN:
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                         goto elementwise;
-                     }
-                     break;
--                case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN:
--                    /* also VQMOVUN; op field and mnemonics don't line up */
--                    if (rm & 1) {
--                        return 1;
--                    }
--                    tmp2 = NULL;
--                    for (pass = 0; pass < 2; pass++) {
--                        neon_load_reg64(cpu_V0, rm + pass);
--                        tmp = tcg_temp_new_i32();
--                        gen_neon_narrow_op(op == NEON_2RM_VMOVN, q, size,
--                                           tmp, cpu_V0);
--                        if (pass == 0) {
--                            tmp2 = tmp;
--                        } else {
--                            neon_store_reg(rd, 0, tmp2);
--                            neon_store_reg(rd, 1, tmp);
--                        }
--                    }
--                    break;
-                 case NEON_2RM_VSHLL:
-                     if (q || (rd & 1)) {
-                         return 1;
 --
 .20.1

-[PULL 04/42] target/arm: Convert Neon 2-reg-misc pairwise ops to decodetree
+[PULL 27/29] target/arm: Convert Neon VSHLL, VMOVL to decodetree
-Convert the pairwise ops VPADDL and VPADAL in the 2-reg-misc grouping
+Convert the VSHLL and VMOVL insns from the 2-reg-shift group
-to decodetree.
+to decodetree. Since the loop always has two passes, we unroll
+it to avoid the awkward reassignment of one TCGv to another.
 At this point we can get rid of the weird CPU_V001 #define that was
 used to avoid having to explicitly list all the arguments being
 passed to some TCG gen/helper functions.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-3-peter.maydell@linaro.org
+Message-id: 20200522145520.6778-8-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       |   6 ++
+ target/arm/neon-dp.decode       | 16 +++++++
- target/arm/translate-neon.inc.c | 149 ++++++++++++++++++++++++++++++++
+ target/arm/translate-neon.inc.c | 81 +++++++++++++++++++++++++++++++++
- target/arm/translate.c          |  35 +-------
+ target/arm/translate.c          | 46 +------------------
-files changed, 157 insertions(+), 33 deletions(-)
+files changed, 99 insertions(+), 44 deletions(-)
 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/neon-dp.decode
 +++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
+@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
-                  &2misc vm=%vm_dp vd=%vd_dp
+                  &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 \
+                  shift=%neon_rshift_i3
-     VREV64       1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc
-+
++# Long left shifts: again Q is part of opcode decode
-+    VPADDL_S     1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc
++@2reg_shll_s     .... ... . . . 1 shift:5    .... .... 0 . . . .... \
-+    VPADDL_U     1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc
++                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0
-+
++@2reg_shll_h     .... ... . . . 01 shift:4   .... .... 0 . . . .... \
-+    VPADAL_S     1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc
++                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0
-+    VPADAL_U     1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc
++@2reg_shll_b     .... ... . . . 001 shift:3  .... .... 0 . . . .... \
-   ]
++                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
++
-   # Subgroup for size != 0b11
+ VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
  VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
  VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
@@ -XXX,XX +XXX,XX @@ VQSHRN_U16_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
  VQRSHRN_U64_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
  VQRSHRN_U32_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
  VQRSHRN_U16_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
 +
 +VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
 +VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
 +VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
 +
 +VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
 +VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
 +VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.inc.c
 +++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
+@@ -XXX,XX +XXX,XX @@ DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_u8)
-     }
+ DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sat_u32)
-     return true;
+ DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sat_u16)
- }
+ DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sat_u8)
 +
-+static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a,
++static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
-+                              NeonGenWidenFn *widenfn,
++                         NeonGenWidenFn *widenfn, bool u)
 +                              NeonGenTwo64OpFn *opfn,
 +                              NeonGenTwo64OpFn *accfn)
 +{
-+    /*
++    TCGv_i64 tmp;
-+     * Pairwise long operations: widen both halves of the pair,
++    TCGv_i32 rm0, rm1;
-+     * combine the pairs with the opfn, and then possibly accumulate
++    uint64_t widen_mask = 0;
 +     * into the destination with the accfn.
 +     */
 +    int pass;
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
 +        return false;
 +    }
 +
 +    /* UNDEF accesses to D16-D31 if they don't exist. */
 +    if (!dc_isar_feature(aa32_simd_r32, s) &&
 +        ((a->vd | a->vm) & 0x10)) {
 +        return false;
 +    }
 +
-+    if ((a->vd | a->vm) & a->q) {
++    if (a->vd & 1) {
 +        return false;
 +    }
 +
 +    if (!widenfn) {
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
-+    for (pass = 0; pass < a->q + 1; pass++) {
++    /*
-+        TCGv_i32 tmp;
++     * This is a widen-and-shift operation. The shift is always less
-+        TCGv_i64 rm0_64, rm1_64, rd_64;
++     * than the width of the source type, so after widening the input
-+
++     * vector we can simply shift the whole 64-bit widened register,
-+        rm0_64 = tcg_temp_new_i64();
++     * and then clear the potential overflow bits resulting from left
-+        rm1_64 = tcg_temp_new_i64();
++     * bits of the narrow input appearing as right bits of the left
-+        rd_64 = tcg_temp_new_i64();
++     * neighbour narrow input. Calculate a mask of bits to clear.
-+        tmp = neon_load_reg(a->vm, pass * 2);
++     */
-+        widenfn(rm0_64, tmp);
++    if ((a->shift != 0) && (a->size < 2 || u)) {
-+        tcg_temp_free_i32(tmp);
++        int esize = 8 << a->size;
-+        tmp = neon_load_reg(a->vm, pass * 2 + 1);
++        widen_mask = MAKE_64BIT_MASK(0, esize);
-+        widenfn(rm1_64, tmp);
++        widen_mask >>= esize - a->shift;
-+        tcg_temp_free_i32(tmp);
++        widen_mask = dup_const(a->size + 1, widen_mask);
-+        opfn(rd_64, rm0_64, rm1_64);
++    }
-+        tcg_temp_free_i64(rm0_64);
++
-+        tcg_temp_free_i64(rm1_64);
++    rm0 = neon_load_reg(a->vm, 0);
-+
++    rm1 = neon_load_reg(a->vm, 1);
-+        if (accfn) {
++    tmp = tcg_temp_new_i64();
-+            TCGv_i64 tmp64 = tcg_temp_new_i64();
++
-+            neon_load_reg64(tmp64, a->vd + pass);
++    widenfn(tmp, rm0);
-+            accfn(rd_64, tmp64, rd_64);
++    if (a->shift != 0) {
-+            tcg_temp_free_i64(tmp64);
++        tcg_gen_shli_i64(tmp, tmp, a->shift);
-+        }
++        tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
-+        neon_store_reg64(rd_64, a->vd + pass);
++    }
-+        tcg_temp_free_i64(rd_64);
++    neon_store_reg64(tmp, a->vd);
-+    }
++
 +    widenfn(tmp, rm1);
 +    if (a->shift != 0) {
 +        tcg_gen_shli_i64(tmp, tmp, a->shift);
 +        tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
 +    }
 +    neon_store_reg64(tmp, a->vd + 1);
 +    tcg_temp_free_i64(tmp);
 +    return true;
 +}
 +
-+static bool trans_VPADDL_S(DisasContext *s, arg_2misc *a)
++static bool trans_VSHLL_S_2sh(DisasContext *s, arg_2reg_shift *a)
 +{
-+    static NeonGenWidenFn * const widenfn[] = {
++    NeonGenWidenFn *widenfn[] = {
 +        gen_helper_neon_widen_s8,
 +        gen_helper_neon_widen_s16,
 +        tcg_gen_ext_i32_i64,
-+        NULL,
 +    };
-+    static NeonGenTwo64OpFn * const opfn[] = {
++    return do_vshll_2sh(s, a, widenfn[a->size], false);
 +        gen_helper_neon_paddl_u16,
 +        gen_helper_neon_paddl_u32,
 +        tcg_gen_add_i64,
 +        NULL,
 +    };
 +
 +    return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL);
 +}
 +
-+static bool trans_VPADDL_U(DisasContext *s, arg_2misc *a)
++static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a)
 +{
-+    static NeonGenWidenFn * const widenfn[] = {
++    NeonGenWidenFn *widenfn[] = {
 +        gen_helper_neon_widen_u8,
 +        gen_helper_neon_widen_u16,
 +        tcg_gen_extu_i32_i64,
-+        NULL,
 +    };
-+    static NeonGenTwo64OpFn * const opfn[] = {
++    return do_vshll_2sh(s, a, widenfn[a->size], true);
 +        gen_helper_neon_paddl_u16,
 +        gen_helper_neon_paddl_u32,
 +        tcg_gen_add_i64,
 +        NULL,
 +    };
 +
 +    return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL);
 +}
 +
 +static bool trans_VPADAL_S(DisasContext *s, arg_2misc *a)
 +{
 +    static NeonGenWidenFn * const widenfn[] = {
 +        gen_helper_neon_widen_s8,
 +        gen_helper_neon_widen_s16,
 +        tcg_gen_ext_i32_i64,
 +        NULL,
 +    };
 +    static NeonGenTwo64OpFn * const opfn[] = {
 +        gen_helper_neon_paddl_u16,
 +        gen_helper_neon_paddl_u32,
 +        tcg_gen_add_i64,
 +        NULL,
 +    };
 +    static NeonGenTwo64OpFn * const accfn[] = {
 +        gen_helper_neon_addl_u16,
 +        gen_helper_neon_addl_u32,
 +        tcg_gen_add_i64,
 +        NULL,
 +    };
 +
 +    return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size],
 +                             accfn[a->size]);
 +}
 +
 +static bool trans_VPADAL_U(DisasContext *s, arg_2misc *a)
 +{
 +    static NeonGenWidenFn * const widenfn[] = {
 +        gen_helper_neon_widen_u8,
 +        gen_helper_neon_widen_u16,
 +        tcg_gen_extu_i32_i64,
 +        NULL,
 +    };
 +    static NeonGenTwo64OpFn * const opfn[] = {
 +        gen_helper_neon_paddl_u16,
 +        gen_helper_neon_paddl_u32,
 +        tcg_gen_add_i64,
 +        NULL,
 +    };
 +    static NeonGenTwo64OpFn * const accfn[] = {
 +        gen_helper_neon_addl_u16,
 +        gen_helper_neon_addl_u32,
 +        tcg_gen_add_i64,
 +        NULL,
 +    };
 +
 +    return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size],
 +                             accfn[a->size]);
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc)
+@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-     gen_rfe(s, pc, load_cpu_field(spsr));
+             case 7: /* VQSHL */
- }
+             case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
+             case 9: /* VQSHRN, VQRSHRN */
--#define CPU_V001 cpu_V0, cpu_V0, cpu_V1
++            case 10: /* VSHLL, including VMOVL */
                  return 1; /* handled by decodetree */
              default:
                  break;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                      size--;
              }
              shift = (insn >> 16) & ((1 << (3 + size)) - 1);
 -            if (op == 10) {
 -                /* VSHLL, VMOVL */
 -                if (q || (rd & 1)) {
 -                    return 1;
 -                }
 -                tmp = neon_load_reg(rm, 0);
 -                tmp2 = neon_load_reg(rm, 1);
 -                for (pass = 0; pass < 2; pass++) {
 -                    if (pass == 1)
 -                        tmp = tmp2;
 -
- static int gen_neon_unzip(int rd, int rm, int size, int q)
+-                    gen_neon_widen(cpu_V0, tmp, size, u);
  {
      TCGv_ptr pd, pm;
@@ -XXX,XX +XXX,XX @@ static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u)
      tcg_temp_free_i32(src);
  }
 -static inline void gen_neon_addl(int size)
 -{
 -    switch (size) {
 -    case 0: gen_helper_neon_addl_u16(CPU_V001); break;
 -    case 1: gen_helper_neon_addl_u32(CPU_V001); break;
 -    case 2: tcg_gen_add_i64(CPU_V001); break;
 -    default: abort();
 -    }
 -}
 -
- static void gen_neon_narrow_op(int op, int u, int size,
+-                    if (shift != 0) {
-                                TCGv_i32 dest, TCGv_i64 src)
+-                        /* The shift is less than the width of the source
- {
+-                           type, so we can just shift the whole register.  */
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
+-                        tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
-                 }
+-                        /* Widen the result of shift: we need to clear
-                 switch (op) {
+-                         * the potential overflow bits resulting from
-                 case NEON_2RM_VREV64:
+-                         * left bits of the narrow input appearing as
--                    /* handled by decodetree */
+-                         * right bits of left the neighbour narrow
--                    return 1;
+-                         * input.  */
-                 case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U:
+-                        if (size < 2 || !u) {
-                 case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U:
+-                            uint64_t imm64;
--                    for (pass = 0; pass < q + 1; pass++) {
+-                            if (size == 0) {
--                        tmp = neon_load_reg(rm, pass * 2);
+-                                imm = (0xffu >> (8 - shift));
--                        gen_neon_widen(cpu_V0, tmp, size, op & 1);
+-                                imm |= imm << 16;
--                        tmp = neon_load_reg(rm, pass * 2 + 1);
+-                            } else if (size == 1) {
--                        gen_neon_widen(cpu_V1, tmp, size, op & 1);
+-                                imm = 0xffff >> (16 - shift);
--                        switch (size) {
+-                            } else {
--                        case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
+-                                /* size == 2 */
--                        case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
+-                                imm = 0xffffffff >> (32 - shift);
--                        case 2: tcg_gen_add_i64(CPU_V001); break;
+-                            }
--                        default: abort();
+-                            if (size < 2) {
 -                                imm64 = imm | (((uint64_t)imm) << 32);
 -                            } else {
 -                                imm64 = imm;
 -                            }
 -                            tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64);
 -                        }
--                        if (op >= NEON_2RM_VPADAL) {
--                            /* Accumulate.  */
--                            neon_load_reg64(cpu_V1, rd + pass);
--                            gen_neon_addl(size);
--                        }
--                        neon_store_reg64(cpu_V0, rd + pass);
 -                    }
--                    break;
+-                    neon_store_reg64(cpu_V0, rd + pass);
-+                    /* handled by decodetree */
+-                }
-+                    return 1;
+-            } else if (op >= 14) {
-                 case NEON_2RM_VTRN:
++            if (op >= 14) {
-                     if (size == 2) {
+                 /* VCVT fixed-point.  */
-                         int n;
+                 TCGv_ptr fpst;
                  TCGv_i32 shiftv;
 --
 .20.1

-[PULL 17/42] target/arm: Convert simple fp Neon 2-reg-misc insns
+[PULL 28/29] target/arm: Convert VCVT fixed-point ops to decodetree
-Convert the Neon 2-reg-misc insns which are implemented with
+Convert the VCVT fixed-point conversion operations in the
-simple calls to functions that take the input, output and
+Neon 2-regs-and-shift group to decodetree.
 fpstatus pointer.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-16-peter.maydell@linaro.org
+Message-id: 20200522145520.6778-9-peter.maydell@linaro.org
 ---
- target/arm/translate.h          |  1 +
+ target/arm/neon-dp.decode       | 11 +++++
- target/arm/neon-dp.decode       |  8 +++++
+ target/arm/translate-neon.inc.c | 49 +++++++++++++++++++++
- target/arm/translate-neon.inc.c | 62 +++++++++++++++++++++++++++++++++
+ target/arm/translate.c          | 75 +--------------------------------
- target/arm/translate.c          | 56 ++++-------------------------
+files changed, 62 insertions(+), 73 deletions(-)
 files changed, 78 insertions(+), 49 deletions(-)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
-+++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
- typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
- typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
- typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
-+typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr);
- typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
- typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
- typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/neon-dp.decode
 +++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
+@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
-     SHA1SU1      1111 001 11 . 11 .. 10 .... 0 0111 0 . 0 .... @2misc_q1
+ @2reg_shll_b     .... ... . . . 001 shift:3  .... .... 0 . . . .... \
-     SHA256SU0    1111 001 11 . 11 .. 10 .... 0 0111 1 . 0 .... @2misc_q1
+                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
-+    VRINTX       1111 001 11 . 11 .. 10 .... 0 1001 . . 0 .... @2misc
++# We use size=0 for fp32 and size=1 for fp16 to match the 3-same encodings.
 +@2reg_vcvt       .... ... . . . 1 ..... .... .... . q:1 . . .... \
 +                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i5
 +
-     VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0
+ VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
-     VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0
+ VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
+ VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
-     VRECPE       1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc
+@@ -XXX,XX +XXX,XX @@ VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
-     VRSQRTE      1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc
+ VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
-+    VRECPE_F     1111 001 11 . 11 .. 11 .... 0 1010 . . 0 .... @2misc
+ VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
-+    VRSQRTE_F    1111 001 11 . 11 .. 11 .... 0 1011 . . 0 .... @2misc
+ VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
-+    VCVT_FS      1111 001 11 . 11 .. 11 .... 0 1100 . . 0 .... @2misc
++
-+    VCVT_FU      1111 001 11 . 11 .. 11 .... 0 1101 . . 0 .... @2misc
++# VCVT fixed<->float conversions
-+    VCVT_SF      1111 001 11 . 11 .. 11 .... 0 1110 . . 0 .... @2misc
++# TODO: FP16 fixed<->float conversions are opc==0b1100 and 0b1101
-+    VCVT_UF      1111 001 11 . 11 .. 11 .... 0 1111 . . 0 .... @2misc
++VCVT_SF_2sh      1111 001 0 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
-   ]
++VCVT_UF_2sh      1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
++VCVT_FS_2sh      1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
-   # Subgroup for size != 0b11
++VCVT_FU_2sh      1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.inc.c
 +++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VQNEG(DisasContext *s, arg_2misc *a)
+@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a)
      };
-     return do_2misc(s, a, fn[a->size]);
+     return do_vshll_2sh(s, a, widenfn[a->size], true);
  }
 +
-+static bool do_2misc_fp(DisasContext *s, arg_2misc *a,
++static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
-+                        NeonGenOneSingleOpFn *fn)
++                      NeonGenTwoSingleOPFn *fn)
 +{
++    /* FP operations in 2-reg-and-shift group */
++    TCGv_i32 tmp, shiftv;
++    TCGv_ptr fpstatus;
 +    int pass;
-+    TCGv_ptr fpst;
 +
-+    /* Handle a 2-reg-misc operation by iterating 32 bits at a time */
 +    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
 +        return false;
 +    }
 +
 +    /* UNDEF accesses to D16-D31 if they don't exist. */
 +    if (!dc_isar_feature(aa32_simd_r32, s) &&
 +        ((a->vd | a->vm) & 0x10)) {
 +        return false;
 +    }
 +
-+    if (a->size != 2) {
++    if ((a->vm | a->vd) & a->q) {
 +        /* TODO: FP16 will be the size == 1 case */
 +        return false;
 +    }
 +
 +    if ((a->vd | a->vm) & a->q) {
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
-+    fpst = get_fpstatus_ptr(1);
++    fpstatus = get_fpstatus_ptr(1);
 +    shiftv = tcg_const_i32(a->shift);
 +    for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
-+        TCGv_i32 tmp = neon_load_reg(a->vm, pass);
++        tmp = neon_load_reg(a->vm, pass);
-+        fn(tmp, tmp, fpst);
++        fn(tmp, tmp, shiftv, fpstatus);
 +        neon_store_reg(a->vd, pass, tmp);
 +    }
-+    tcg_temp_free_ptr(fpst);
++    tcg_temp_free_ptr(fpstatus);
-+
++    tcg_temp_free_i32(shiftv);
 +    return true;
 +}
 +
-+#define DO_2MISC_FP(INSN, FUNC)                                 \
++#define DO_FP_2SH(INSN, FUNC)                                           \
-+    static bool trans_##INSN(DisasContext *s, arg_2misc *a)     \
++    static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a)  \
-+    {                                                           \
++    {                                                                   \
-+        return do_2misc_fp(s, a, FUNC);                         \
++        return do_fp_2sh(s, a, FUNC);                                   \
 +    }
 +
-+DO_2MISC_FP(VRECPE_F, gen_helper_recpe_f32)
++DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos)
-+DO_2MISC_FP(VRSQRTE_F, gen_helper_rsqrte_f32)
++DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos)
-+DO_2MISC_FP(VCVT_FS, gen_helper_vfp_sitos)
++DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero)
-+DO_2MISC_FP(VCVT_FU, gen_helper_vfp_uitos)
++DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero)
 +DO_2MISC_FP(VCVT_SF, gen_helper_vfp_tosizs)
 +DO_2MISC_FP(VCVT_UF, gen_helper_vfp_touizs)
 +
 +static bool trans_VRINTX(DisasContext *s, arg_2misc *a)
 +{
 +    if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
 +        return false;
 +    }
 +    return do_2misc_fp(s, a, gen_helper_rints_exact);
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
 @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                 case NEON_2RM_VRSQRTE:
+     int q;
-                 case NEON_2RM_VQABS:
+     int rd, rn, rm, rd_ofs, rn_ofs, rm_ofs;
-                 case NEON_2RM_VQNEG:
+     int size;
-+                case NEON_2RM_VRECPE_F:
+-    int shift;
-+                case NEON_2RM_VRSQRTE_F:
+     int pass;
-+                case NEON_2RM_VCVT_FS:
+     int u;
-+                case NEON_2RM_VCVT_FU:
+     int vec_size;
 +                case NEON_2RM_VCVT_SF:
 +                case NEON_2RM_VCVT_UF:
 +                case NEON_2RM_VRINTX:
                      /* handled by decodetree */
                      return 1;
                  case NEON_2RM_VTRN:
 @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                             tcg_temp_free_i32(tcg_rmode);
+         return 1;
-                             break;
+     } else if (insn & (1 << 4)) {
-                         }
+         if ((insn & 0x00380080) != 0) {
--                        case NEON_2RM_VRINTX:
+-            /* Two registers and shift.  */
--                        {
+-            op = (insn >> 8) & 0xf;
--                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+-
--                            gen_helper_rints_exact(tmp, tmp, fpstatus);
+-            switch (op) {
--                            tcg_temp_free_ptr(fpstatus);
+-            case 0: /* VSHR */
--                            break;
+-            case 1: /* VSRA */
--                        }
+-            case 2: /* VRSHR */
-                         case NEON_2RM_VCVTAU:
+-            case 3: /* VRSRA */
-                         case NEON_2RM_VCVTAS:
+-            case 4: /* VSRI */
-                         case NEON_2RM_VCVTNU:
+-            case 5: /* VSHL, VSLI */
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
+-            case 6: /* VQSHLU */
-                             tcg_temp_free_ptr(fpst);
+-            case 7: /* VQSHL */
-                             break;
+-            case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
-                         }
+-            case 9: /* VQSHRN, VQRSHRN */
--                        case NEON_2RM_VRECPE_F:
+-            case 10: /* VSHLL, including VMOVL */
--                        {
+-                return 1; /* handled by decodetree */
--                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+-            default:
--                            gen_helper_recpe_f32(tmp, tmp, fpstatus);
+-                break;
--                            tcg_temp_free_ptr(fpstatus);
+-            }
--                            break;
+-
--                        }
+-            if (insn & (1 << 7)) {
--                        case NEON_2RM_VRSQRTE_F:
+-                /* 64-bit shift. */
--                        {
+-                if (op > 7) {
--                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+-                    return 1;
--                            gen_helper_rsqrte_f32(tmp, tmp, fpstatus);
+-                }
--                            tcg_temp_free_ptr(fpstatus);
+-                size = 3;
--                            break;
+-            } else {
--                        }
+-                size = 2;
--                        case NEON_2RM_VCVT_FS: /* VCVT.F32.S32 */
+-                while ((insn & (1 << (size + 19))) == 0)
--                        {
+-                    size--;
--                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+-            }
--                            gen_helper_vfp_sitos(tmp, tmp, fpstatus);
+-            shift = (insn >> 16) & ((1 << (3 + size)) - 1);
--                            tcg_temp_free_ptr(fpstatus);
+-            if (op >= 14) {
--                            break;
+-                /* VCVT fixed-point.  */
--                        }
+-                TCGv_ptr fpst;
--                        case NEON_2RM_VCVT_FU: /* VCVT.F32.U32 */
+-                TCGv_i32 shiftv;
--                        {
+-                VFPGenFixPointFn *fn;
--                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+-
--                            gen_helper_vfp_uitos(tmp, tmp, fpstatus);
+-                if (!(insn & (1 << 21)) || (q && ((rd | rm) & 1))) {
--                            tcg_temp_free_ptr(fpstatus);
+-                    return 1;
--                            break;
+-                }
--                        }
+-
--                        case NEON_2RM_VCVT_SF: /* VCVT.S32.F32 */
+-                if (!(op & 1)) {
--                        {
+-                    if (u) {
--                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+-                        fn = gen_helper_vfp_ultos;
--                            gen_helper_vfp_tosizs(tmp, tmp, fpstatus);
+-                    } else {
--                            tcg_temp_free_ptr(fpstatus);
+-                        fn = gen_helper_vfp_sltos;
--                            break;
+-                    }
--                        }
+-                } else {
--                        case NEON_2RM_VCVT_UF: /* VCVT.U32.F32 */
+-                    if (u) {
--                        {
+-                        fn = gen_helper_vfp_touls_round_to_zero;
--                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+-                    } else {
--                            gen_helper_vfp_touizs(tmp, tmp, fpstatus);
+-                        fn = gen_helper_vfp_tosls_round_to_zero;
--                            tcg_temp_free_ptr(fpstatus);
+-                    }
--                            break;
+-                }
--                        }
+-
-                         default:
+-                /* We have already masked out the must-be-1 top bit of imm6,
-                             /* Reserved op values were caught by the
+-                 * hence this 32-shift where the ARM ARM has 64-imm6.
-                              * neon_2rm_sizes[] check earlier.
+-                 */
 -                shift = 32 - shift;
 -                fpst = get_fpstatus_ptr(1);
 -                shiftv = tcg_const_i32(shift);
 -                for (pass = 0; pass < (q ? 4 : 2); pass++) {
 -                    TCGv_i32 tmpf = neon_load_reg(rm, pass);
 -                    fn(tmpf, tmpf, shiftv, fpst);
 -                    neon_store_reg(rd, pass, tmpf);
 -                }
 -                tcg_temp_free_ptr(fpst);
 -                tcg_temp_free_i32(shiftv);
 -            } else {
 -                return 1;
 -            }
 +            /* Two registers and shift: handled by decodetree */
 +            return 1;
          } else { /* (insn & 0x00380080) == 0 */
              int invert, reg_ofs, vec_size;
 --
 .20.1

-[PULL 05/42] target/arm: Convert VZIP, VUZP to decodetree
+[PULL 29/29] target/arm: Convert Neon one-register-and-immediate insns to decodetree
-Convert the Neon VZIP and VUZP insns in the 2-reg-misc group to
+Convert the insns in the one-register-and-immediate group to decodetree.
-decodetree.
 In the new decode, our asimd_imm_const() function returns a 64-bit value
 rather than a 32-bit one, which means we don't need to treat cmode=14 op=1
 as a special case in the decoder (it is the only encoding where the two
 halves of the 64-bit value are different).
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-4-peter.maydell@linaro.org
+Message-id: 20200522145520.6778-10-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       |  3 ++
+ target/arm/neon-dp.decode       |  22 ++++++
- target/arm/translate-neon.inc.c | 74 ++++++++++++++++++++++++++
+ target/arm/translate-neon.inc.c | 118 ++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 92 +--------------------------------
+ target/arm/translate.c          | 101 +--------------------------
-files changed, 79 insertions(+), 90 deletions(-)
+files changed, 142 insertions(+), 99 deletions(-)
 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/neon-dp.decode
 +++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
+@@ -XXX,XX +XXX,XX @@ VCVT_SF_2sh      1111 001 0 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
+ VCVT_UF_2sh      1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
-     VPADAL_S     1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc
+ VCVT_FS_2sh      1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
-     VPADAL_U     1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc
+ VCVT_FU_2sh      1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
 +
-+    VUZP         1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc
++######################################################################
-+    VZIP         1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc
++# 1-reg-and-modified-immediate grouping:
-   ]
++# 1111 001 i 1 D 000 imm:3 Vd:4 cmode:4 0 Q op 1 Vm:4
++######################################################################
-   # Subgroup for size != 0b11
++
 +&1reg_imm        vd q imm cmode op
 +
 +%asimd_imm_value 24:1 16:3 0:4
 +
 +@1reg_imm        .... ... . . . ... ... .... .... . q:1 . . .... \
 +                 &1reg_imm imm=%asimd_imm_value vd=%vd_dp
 +
 +# The cmode/op bits here decode VORR/VBIC/VMOV/VMNV, but
 +# not in a way we can conveniently represent in decodetree without
 +# a lot of repetition:
 +# VORR: op=0, (cmode & 1) && cmode < 12
 +# VBIC: op=1, (cmode & 1) && cmode < 12
 +# VMOV: everything else
 +# So we have a single decode line and check the cmode/op in the
 +# trans function.
 +Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.inc.c
 +++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VPADAL_U(DisasContext *s, arg_2misc *a)
+@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos)
-     return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size],
+ DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos)
-                              accfn[a->size]);
+ DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero)
- }
+ DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero)
 +
-+typedef void ZipFn(TCGv_ptr, TCGv_ptr);
++static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
-+
++{
-+static bool do_zip_uzp(DisasContext *s, arg_2misc *a,
++    /*
-+                       ZipFn *fn)
++     * Expand the encoded constant.
-+{
++     * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
-+    TCGv_ptr pd, pm;
++     * We choose to not special-case this and will behave as if a
 +     * valid constant encoding of 0 had been given.
 +     * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
 +     */
 +    switch (cmode) {
 +    case 0: case 1:
 +        /* no-op */
 +        break;
 +    case 2: case 3:
 +        imm <<= 8;
 +        break;
 +    case 4: case 5:
 +        imm <<= 16;
 +        break;
 +    case 6: case 7:
 +        imm <<= 24;
 +        break;
 +    case 8: case 9:
 +        imm |= imm << 16;
 +        break;
 +    case 10: case 11:
 +        imm = (imm << 8) | (imm << 24);
 +        break;
 +    case 12:
 +        imm = (imm << 8) | 0xff;
 +        break;
 +    case 13:
 +        imm = (imm << 16) | 0xffff;
 +        break;
 +    case 14:
 +        if (op) {
 +            /*
 +             * This is the only case where the top and bottom 32 bits
 +             * of the encoded constant differ.
 +             */
 +            uint64_t imm64 = 0;
 +            int n;
 +
 +            for (n = 0; n < 8; n++) {
 +                if (imm & (1 << n)) {
 +                    imm64 |= (0xffULL << (n * 8));
 +                }
 +            }
 +            return imm64;
 +        }
 +        imm |= (imm << 8) | (imm << 16) | (imm << 24);
 +        break;
 +    case 15:
 +        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
 +            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
 +        break;
 +    }
 +    if (op) {
 +        imm = ~imm;
 +    }
 +    return dup_const(MO_32, imm);
 +}
 +
 +static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
 +                        GVecGen2iFn *fn)
 +{
 +    uint64_t imm;
 +    int reg_ofs, vec_size;
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
 +        return false;
 +    }
 +
 +    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
++    if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
 +        ((a->vd | a->vm) & 0x10)) {
 +        return false;
 +    }
 +
-+    if ((a->vd | a->vm) & a->q) {
++    if (a->vd & a->q) {
 +        return false;
 +    }
 +
 +    if (!fn) {
 +        /* Bad size or size/q combination */
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
-+    pd = vfp_reg_ptr(true, a->vd);
++    reg_ofs = neon_reg_offset(a->vd, 0);
-+    pm = vfp_reg_ptr(true, a->vm);
++    vec_size = a->q ? 16 : 8;
-+    fn(pd, pm);
++    imm = asimd_imm_const(a->imm, a->cmode, a->op);
-+    tcg_temp_free_ptr(pd);
++
-+    tcg_temp_free_ptr(pm);
++    fn(MO_64, reg_ofs, reg_ofs, imm, vec_size, vec_size);
 +    return true;
 +}
 +
-+static bool trans_VUZP(DisasContext *s, arg_2misc *a)
++static void gen_VMOV_1r(unsigned vece, uint32_t dofs, uint32_t aofs,
-+{
++                        int64_t c, uint32_t oprsz, uint32_t maxsz)
-+    static ZipFn * const fn[2][4] = {
++{
-+        {
++    tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, c);
-+            gen_helper_neon_unzip8,
++}
-+            gen_helper_neon_unzip16,
++
-+            NULL,
++static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a)
-+            NULL,
++{
-+        }, {
++    /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
-+            gen_helper_neon_qunzip8,
++    GVecGen2iFn *fn;
-+            gen_helper_neon_qunzip16,
++
-+            gen_helper_neon_qunzip32,
++    if ((a->cmode & 1) && a->cmode < 12) {
-+            NULL,
++        /* for op=1, the imm will be inverted, so BIC becomes AND. */
 +        fn = a->op ? tcg_gen_gvec_andi : tcg_gen_gvec_ori;
 +    } else {
 +        /* There is one unallocated cmode/op combination in this space */
 +        if (a->cmode == 15 && a->op == 1) {
 +            return false;
 +        }
-+    };
++        fn = gen_VMOV_1r;
-+    return do_zip_uzp(s, a, fn[a->q][a->size]);
++    }
-+}
++    return do_1reg_imm(s, a, fn);
 +
 +static bool trans_VZIP(DisasContext *s, arg_2misc *a)
 +{
 +    static ZipFn * const fn[2][4] = {
 +        {
 +            gen_helper_neon_zip8,
 +            gen_helper_neon_zip16,
 +            NULL,
 +            NULL,
 +        }, {
 +            gen_helper_neon_qzip8,
 +            gen_helper_neon_qzip16,
 +            gen_helper_neon_qzip32,
 +            NULL,
 +        }
 +    };
 +    return do_zip_uzp(s, a, fn[a->q][a->size]);
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc)
+@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-     gen_rfe(s, pc, load_cpu_field(spsr));
+         /* Three register same length: handled by decodetree */
- }
+         return 1;
+     } else if (insn & (1 << 4)) {
--static int gen_neon_unzip(int rd, int rm, int size, int q)
+-        if ((insn & 0x00380080) != 0) {
--{
+-            /* Two registers and shift: handled by decodetree */
--    TCGv_ptr pd, pm;
+-            return 1;
--
+-        } else { /* (insn & 0x00380080) == 0 */
--    if (!q && size == 2) {
+-            int invert, reg_ofs, vec_size;
--        return 1;
+-
--    }
+-            if (q && (rd & 1)) {
--    pd = vfp_reg_ptr(true, rd);
+-                return 1;
--    pm = vfp_reg_ptr(true, rm);
+-            }
--    if (q) {
+-
--        switch (size) {
+-            op = (insn >> 8) & 0xf;
--        case 0:
+-            /* One register and immediate.  */
--            gen_helper_neon_qunzip8(pd, pm);
+-            imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
--            break;
+-            invert = (insn & (1 << 5)) != 0;
--        case 1:
+-            /* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
--            gen_helper_neon_qunzip16(pd, pm);
+-             * We choose to not special-case this and will behave as if a
--            break;
+-             * valid constant encoding of 0 had been given.
--        case 2:
+-             */
--            gen_helper_neon_qunzip32(pd, pm);
+-            switch (op) {
--            break;
+-            case 0: case 1:
--        default:
+-                /* no-op */
--            abort();
+-                break;
 -            case 2: case 3:
 -                imm <<= 8;
 -                break;
 -            case 4: case 5:
 -                imm <<= 16;
 -                break;
 -            case 6: case 7:
 -                imm <<= 24;
 -                break;
 -            case 8: case 9:
 -                imm |= imm << 16;
 -                break;
 -            case 10: case 11:
 -                imm = (imm << 8) | (imm << 24);
 -                break;
 -            case 12:
 -                imm = (imm << 8) | 0xff;
 -                break;
 -            case 13:
 -                imm = (imm << 16) | 0xffff;
 -                break;
 -            case 14:
 -                imm |= (imm << 8) | (imm << 16) | (imm << 24);
 -                if (invert) {
 -                    imm = ~imm;
 -                }
 -                break;
 -            case 15:
 -                if (invert) {
 -                    return 1;
 -                }
 -                imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
 -                      | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
 -                break;
 -            }
 -            if (invert) {
 -                imm = ~imm;
 -            }
 -
 -            reg_ofs = neon_reg_offset(rd, 0);
 -            vec_size = q ? 16 : 8;
 -
 -            if (op & 1 && op < 12) {
 -                if (invert) {
 -                    /* The immediate value has already been inverted,
 -                     * so BIC becomes AND.
 -                     */
 -                    tcg_gen_gvec_andi(MO_32, reg_ofs, reg_ofs, imm,
 -                                      vec_size, vec_size);
 -                } else {
 -                    tcg_gen_gvec_ori(MO_32, reg_ofs, reg_ofs, imm,
 -                                     vec_size, vec_size);
 -                }
 -            } else {
 -                /* VMOV, VMVN.  */
 -                if (op == 14 && invert) {
 -                    TCGv_i64 t64 = tcg_temp_new_i64();
 -
 -                    for (pass = 0; pass <= q; ++pass) {
 -                        uint64_t val = 0;
 -                        int n;
 -
 -                        for (n = 0; n < 8; n++) {
 -                            if (imm & (1 << (n + pass * 8))) {
 -                                val |= 0xffull << (n * 8);
 -                            }
 -                        }
 -                        tcg_gen_movi_i64(t64, val);
 -                        neon_store_reg64(t64, rd + pass);
 -                    }
 -                    tcg_temp_free_i64(t64);
 -                } else {
 -                    tcg_gen_gvec_dup_imm(MO_32, reg_ofs, vec_size,
 -                                         vec_size, imm);
 -                }
 -            }
 -        }
--    } else {
++        /* Two registers and shift or reg and imm: handled by decodetree */
--        switch (size) {
++        return 1;
--        case 0:
+     } else { /* (insn & 0x00800010 == 0x00800000) */
--            gen_helper_neon_unzip8(pd, pm);
+         if (size != 3) {
--            break;
+             op = (insn >> 8) & 0xf;
 -        case 1:
 -            gen_helper_neon_unzip16(pd, pm);
 -            break;
 -        default:
 -            abort();
 -        }
 -    }
 -    tcg_temp_free_ptr(pd);
 -    tcg_temp_free_ptr(pm);
 -    return 0;
 -}
 -
 -static int gen_neon_zip(int rd, int rm, int size, int q)
 -{
 -    TCGv_ptr pd, pm;
 -
 -    if (!q && size == 2) {
 -        return 1;
 -    }
 -    pd = vfp_reg_ptr(true, rd);
 -    pm = vfp_reg_ptr(true, rm);
 -    if (q) {
 -        switch (size) {
 -        case 0:
 -            gen_helper_neon_qzip8(pd, pm);
 -            break;
 -        case 1:
 -            gen_helper_neon_qzip16(pd, pm);
 -            break;
 -        case 2:
 -            gen_helper_neon_qzip32(pd, pm);
 -            break;
 -        default:
 -            abort();
 -        }
 -    } else {
 -        switch (size) {
 -        case 0:
 -            gen_helper_neon_zip8(pd, pm);
 -            break;
 -        case 1:
 -            gen_helper_neon_zip16(pd, pm);
 -            break;
 -        default:
 -            abort();
 -        }
 -    }
 -    tcg_temp_free_ptr(pd);
 -    tcg_temp_free_ptr(pm);
 -    return 0;
 -}
 -
  static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1)
  {
      TCGv_i32 rd, tmp;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                  case NEON_2RM_VREV64:
                  case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U:
                  case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U:
 +                case NEON_2RM_VUZP:
 +                case NEON_2RM_VZIP:
                      /* handled by decodetree */
                      return 1;
                  case NEON_2RM_VTRN:
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                          goto elementwise;
                      }
                      break;
 -                case NEON_2RM_VUZP:
 -                    if (gen_neon_unzip(rd, rm, size, q)) {
 -                        return 1;
 -                    }
 -                    break;
 -                case NEON_2RM_VZIP:
 -                    if (gen_neon_zip(rd, rm, size, q)) {
 -                        return 1;
 -                    }
 -                    break;
                  case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN:
                      /* also VQMOVUN; op field and mnemonics don't line up */
                      if (rm & 1) {
 --
 .20.1

-[PULL 07/42] target/arm: Convert Neon 2-reg-misc VSHLL to decodetree
+Deleted patch
-Convert the VSHLL insn in the 2-reg-misc Neon group to decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-6-peter.maydell@linaro.org
----
- target/arm/neon-dp.decode       |  2 ++
- target/arm/translate-neon.inc.c | 52 +++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 35 +---------------------
-files changed, 55 insertions(+), 34 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
-+++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
-     # VQMOVN: signed result, source may be signed (_S) or unsigned (_U)
-     VQMOVN_S     1111 001 11 . 11 .. 10 .... 0 0101 0 . 0 .... @2misc_q0
-     VQMOVN_U     1111 001 11 . 11 .. 10 .... 0 0101 1 . 0 .... @2misc_q0
-+
-+    VSHLL        1111 001 11 . 11 .. 10 .... 0 0110 0 . 0 .... @2misc_q0
-   ]
-   # Subgroup for size != 0b11
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ DO_VMOVN(VMOVN, gen_neon_narrow_u)
- DO_VMOVN(VQMOVUN, gen_helper_neon_unarrow_sat)
- DO_VMOVN(VQMOVN_S, gen_helper_neon_narrow_sat_s)
- DO_VMOVN(VQMOVN_U, gen_helper_neon_narrow_sat_u)
-+
-+static bool trans_VSHLL(DisasContext *s, arg_2misc *a)
-+{
-+    TCGv_i32 rm0, rm1;
-+    TCGv_i64 rd;
-+    static NeonGenWidenFn * const widenfns[] = {
-+        gen_helper_neon_widen_u8,
-+        gen_helper_neon_widen_u16,
-+        tcg_gen_extu_i32_i64,
-+        NULL,
-+    };
-+    NeonGenWidenFn *widenfn = widenfns[a->size];
-+
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        ((a->vd | a->vm) & 0x10)) {
-+        return false;
-+    }
-+
-+    if (a->vd & 1) {
-+        return false;
-+    }
-+
-+    if (!widenfn) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    rd = tcg_temp_new_i64();
-+
-+    rm0 = neon_load_reg(a->vm, 0);
-+    rm1 = neon_load_reg(a->vm, 1);
-+
-+    widenfn(rd, rm0);
-+    tcg_gen_shli_i64(rd, rd, 8 << a->size);
-+    neon_store_reg64(rd, a->vd);
-+    widenfn(rd, rm1);
-+    tcg_gen_shli_i64(rd, rd, 8 << a->size);
-+    neon_store_reg64(rd, a->vd + 1);
-+
-+    tcg_temp_free_i64(rd);
-+    tcg_temp_free_i32(rm0);
-+    tcg_temp_free_i32(rm1);
-+    return true;
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
-     tcg_temp_free_i32(rd);
- }
--static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u)
--{
--    if (u) {
--        switch (size) {
--        case 0: gen_helper_neon_widen_u8(dest, src); break;
--        case 1: gen_helper_neon_widen_u16(dest, src); break;
--        case 2: tcg_gen_extu_i32_i64(dest, src); break;
--        default: abort();
--        }
--    } else {
--        switch (size) {
--        case 0: gen_helper_neon_widen_s8(dest, src); break;
--        case 1: gen_helper_neon_widen_s16(dest, src); break;
--        case 2: tcg_gen_ext_i32_i64(dest, src); break;
--        default: abort();
--        }
--    }
--    tcg_temp_free_i32(src);
--}
--
- /* Symbolic constants for op fields for Neon 2-register miscellaneous.
-  * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B
-  * table A7-13.
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                 case NEON_2RM_VUZP:
-                 case NEON_2RM_VZIP:
-                 case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN:
-+                case NEON_2RM_VSHLL:
-                     /* handled by decodetree */
-                     return 1;
-                 case NEON_2RM_VTRN:
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                         goto elementwise;
-                     }
-                     break;
--                case NEON_2RM_VSHLL:
--                    if (q || (rd & 1)) {
--                        return 1;
--                    }
--                    tmp = neon_load_reg(rm, 0);
--                    tmp2 = neon_load_reg(rm, 1);
--                    for (pass = 0; pass < 2; pass++) {
--                        if (pass == 1)
--                            tmp = tmp2;
--                        gen_neon_widen(cpu_V0, tmp, size, 1);
--                        tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size);
--                        neon_store_reg64(cpu_V0, rd + pass);
--                    }
--                    break;
-                 case NEON_2RM_VCVT_F16_F32:
-                 {
-                     TCGv_ptr fpst;
---
-.20.1

-[PULL 11/42] target/arm: Rename NeonGenOneOpFn to NeonGenOne64OpFn
+Deleted patch
-The NeonGenOneOpFn typedef breaks with the pattern of the other
-NeonGen*Fn typedefs, because it is a TCGv_i64 -> TCGv_i64 operation
-but it does not have '64' in its name. Rename it to NeonGenOne64OpFn,
-so that the old name is available for a TCGv_i32 -> TCGv_i32 operation
-(which we will need in a subsequent commit).
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-10-peter.maydell@linaro.org
----
- target/arm/translate.h     | 2 +-
- target/arm/translate-a64.c | 4 ++--
-files changed, 3 insertions(+), 3 deletions(-)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
-+++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
- typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
- typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
- typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
--typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
-+typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
- typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
- typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
- typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
-     } else {
-         for (pass = 0; pass < maxpass; pass++) {
-             TCGv_i64 tcg_op = tcg_temp_new_i64();
--            NeonGenOneOpFn *genfn;
--            static NeonGenOneOpFn * const fns[2][2] = {
-+            NeonGenOne64OpFn *genfn;
-+            static NeonGenOne64OpFn * const fns[2][2] = {
-                 { gen_helper_neon_addlp_s8,  gen_helper_neon_addlp_u8 },
-                 { gen_helper_neon_addlp_s16,  gen_helper_neon_addlp_u16 },
-             };
---
-.20.1

-[PULL 13/42] target/arm: Make gen_swap_half() take separate src and dest
+Deleted patch
-Make gen_swap_half() take a source and destination TCGv_i32 rather
-than modifying the input TCGv_i32; we're going to want to be able to
-use it with the more flexible function signature, and this also
-brings it into line with other functions like gen_rev16() and
-gen_revsh().
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-12-peter.maydell@linaro.org
----
- target/arm/translate-neon.inc.c |  2 +-
- target/arm/translate.c          | 10 +++++-----
-files changed, 6 insertions(+), 6 deletions(-)
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
-                 tcg_gen_bswap32_i32(tmp[half], tmp[half]);
-                 break;
-             case 1:
--                gen_swap_half(tmp[half]);
-+                gen_swap_half(tmp[half], tmp[half]);
-                 break;
-             case 2:
-                 break;
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_revsh(TCGv_i32 dest, TCGv_i32 var)
- }
- /* Swap low and high halfwords.  */
--static void gen_swap_half(TCGv_i32 var)
-+static void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
- {
--    tcg_gen_rotri_i32(var, var, 16);
-+    tcg_gen_rotri_i32(dest, var, 16);
- }
- /* Dual 16-bit add.  Result placed in t0 and t1 is marked as dead.
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                         case NEON_2RM_VREV32:
-                             switch (size) {
-                             case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
--                            case 1: gen_swap_half(tmp); break;
-+                            case 1: gen_swap_half(tmp, tmp); break;
-                             default: abort();
-                             }
-                             break;
-@@ -XXX,XX +XXX,XX @@ static bool op_smlad(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub)
-     t1 = load_reg(s, a->rn);
-     t2 = load_reg(s, a->rm);
-     if (m_swap) {
--        gen_swap_half(t2);
-+        gen_swap_half(t2, t2);
-     }
-     gen_smul_dual(t1, t2);
-@@ -XXX,XX +XXX,XX @@ static bool op_smlald(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub)
-     t1 = load_reg(s, a->rn);
-     t2 = load_reg(s, a->rm);
-     if (m_swap) {
--        gen_swap_half(t2);
-+        gen_swap_half(t2, t2);
-     }
-     gen_smul_dual(t1, t2);
---
-.20.1

-[PULL 14/42] target/arm: Convert Neon 2-reg-misc VREV32 and VREV16 to decodetree
+Deleted patch
-Convert the VREV32 and VREV16 insns in the Neon 2-reg-misc group
-to decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-13-peter.maydell@linaro.org
----
- target/arm/translate.h          |  1 +
- target/arm/neon-dp.decode       |  2 ++
- target/arm/translate-neon.inc.c | 55 +++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 12 ++-----
-files changed, 60 insertions(+), 10 deletions(-)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
-+++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
-                         uint32_t, uint32_t, uint32_t);
- /* Function prototype for gen_ functions for calling Neon helpers */
-+typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32);
- typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
- typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
- typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
-+++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
-                  &2misc vm=%vm_dp vd=%vd_dp q=1
-     VREV64       1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc
-+    VREV32       1111 001 11 . 11 .. 00 .... 0 0001 . . 0 .... @2misc
-+    VREV16       1111 001 11 . 11 .. 00 .... 0 0010 . . 0 .... @2misc
-     VPADDL_S     1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc
-     VPADDL_U     1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ DO_2M_CRYPTO(AESIMC, aa32_aes, 0)
- DO_2M_CRYPTO(SHA1H, aa32_sha1, 2)
- DO_2M_CRYPTO(SHA1SU1, aa32_sha1, 2)
- DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2)
-+
-+static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn)
-+{
-+    int pass;
-+
-+    /* Handle a 2-reg-misc operation by iterating 32 bits at a time */
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        ((a->vd | a->vm) & 0x10)) {
-+        return false;
-+    }
-+
-+    if (!fn) {
-+        return false;
-+    }
-+
-+    if ((a->vd | a->vm) & a->q) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
-+        TCGv_i32 tmp = neon_load_reg(a->vm, pass);
-+        fn(tmp, tmp);
-+        neon_store_reg(a->vd, pass, tmp);
-+    }
-+
-+    return true;
-+}
-+
-+static bool trans_VREV32(DisasContext *s, arg_2misc *a)
-+{
-+    static NeonGenOneOpFn * const fn[] = {
-+        tcg_gen_bswap32_i32,
-+        gen_swap_half,
-+        NULL,
-+        NULL,
-+    };
-+    return do_2misc(s, a, fn[a->size]);
-+}
-+
-+static bool trans_VREV16(DisasContext *s, arg_2misc *a)
-+{
-+    if (a->size != 0) {
-+        return false;
-+    }
-+    return do_2misc(s, a, gen_rev16);
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                 case NEON_2RM_AESE: case NEON_2RM_AESMC:
-                 case NEON_2RM_SHA1H:
-                 case NEON_2RM_SHA1SU1:
-+                case NEON_2RM_VREV32:
-+                case NEON_2RM_VREV16:
-                     /* handled by decodetree */
-                     return 1;
-                 case NEON_2RM_VTRN:
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                     for (pass = 0; pass < (q ? 4 : 2); pass++) {
-                         tmp = neon_load_reg(rm, pass);
-                         switch (op) {
--                        case NEON_2RM_VREV32:
--                            switch (size) {
--                            case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
--                            case 1: gen_swap_half(tmp, tmp); break;
--                            default: abort();
--                            }
--                            break;
--                        case NEON_2RM_VREV16:
--                            gen_rev16(tmp, tmp);
--                            break;
-                         case NEON_2RM_VCLS:
-                             switch (size) {
-                             case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
---
-.20.1

-[PULL 16/42] target/arm: Convert Neon VQABS, VQNEG to decodetree
+Deleted patch
-Convert the Neon VQABS and VQNEG insns to decodetree.
-Since these are the only ones which need cpu_env passing to
-the helper, we wrap the helper rather than creating a whole
-new do_2misc_env() function.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-15-peter.maydell@linaro.org
----
- target/arm/neon-dp.decode       |  3 +++
- target/arm/translate-neon.inc.c | 35 +++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 30 ++--------------------------
-files changed, 40 insertions(+), 28 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
-+++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
-     VPADAL_S     1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc
-     VPADAL_U     1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc
-+    VQABS        1111 001 11 . 11 .. 00 .... 0 1110 . . 0 .... @2misc
-+    VQNEG        1111 001 11 . 11 .. 00 .... 0 1111 . . 0 .... @2misc
-+
-     VCGT0        1111 001 11 . 11 .. 01 .... 0 0000 . . 0 .... @2misc
-     VCGE0        1111 001 11 . 11 .. 01 .... 0 0001 . . 0 .... @2misc
-     VCEQ0        1111 001 11 . 11 .. 01 .... 0 0010 . . 0 .... @2misc
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VRSQRTE(DisasContext *s, arg_2misc *a)
-     }
-     return do_2misc(s, a, gen_helper_rsqrte_u32);
- }
-+
-+#define WRAP_1OP_ENV_FN(WRAPNAME, FUNC) \
-+    static void WRAPNAME(TCGv_i32 d, TCGv_i32 m)        \
-+    {                                                   \
-+        FUNC(d, cpu_env, m);                            \
-+    }
-+
-+WRAP_1OP_ENV_FN(gen_VQABS_s8, gen_helper_neon_qabs_s8)
-+WRAP_1OP_ENV_FN(gen_VQABS_s16, gen_helper_neon_qabs_s16)
-+WRAP_1OP_ENV_FN(gen_VQABS_s32, gen_helper_neon_qabs_s32)
-+WRAP_1OP_ENV_FN(gen_VQNEG_s8, gen_helper_neon_qneg_s8)
-+WRAP_1OP_ENV_FN(gen_VQNEG_s16, gen_helper_neon_qneg_s16)
-+WRAP_1OP_ENV_FN(gen_VQNEG_s32, gen_helper_neon_qneg_s32)
-+
-+static bool trans_VQABS(DisasContext *s, arg_2misc *a)
-+{
-+    static NeonGenOneOpFn * const fn[] = {
-+        gen_VQABS_s8,
-+        gen_VQABS_s16,
-+        gen_VQABS_s32,
-+        NULL,
-+    };
-+    return do_2misc(s, a, fn[a->size]);
-+}
-+
-+static bool trans_VQNEG(DisasContext *s, arg_2misc *a)
-+{
-+    static NeonGenOneOpFn * const fn[] = {
-+        gen_VQNEG_s8,
-+        gen_VQNEG_s16,
-+        gen_VQNEG_s32,
-+        NULL,
-+    };
-+    return do_2misc(s, a, fn[a->size]);
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                 case NEON_2RM_VNEG_F:
-                 case NEON_2RM_VRECPE:
-                 case NEON_2RM_VRSQRTE:
-+                case NEON_2RM_VQABS:
-+                case NEON_2RM_VQNEG:
-                     /* handled by decodetree */
-                     return 1;
-                 case NEON_2RM_VTRN:
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                     for (pass = 0; pass < (q ? 4 : 2); pass++) {
-                         tmp = neon_load_reg(rm, pass);
-                         switch (op) {
--                        case NEON_2RM_VQABS:
--                            switch (size) {
--                            case 0:
--                                gen_helper_neon_qabs_s8(tmp, cpu_env, tmp);
--                                break;
--                            case 1:
--                                gen_helper_neon_qabs_s16(tmp, cpu_env, tmp);
--                                break;
--                            case 2:
--                                gen_helper_neon_qabs_s32(tmp, cpu_env, tmp);
--                                break;
--                            default: abort();
--                            }
--                            break;
--                        case NEON_2RM_VQNEG:
--                            switch (size) {
--                            case 0:
--                                gen_helper_neon_qneg_s8(tmp, cpu_env, tmp);
--                                break;
--                            case 1:
--                                gen_helper_neon_qneg_s16(tmp, cpu_env, tmp);
--                                break;
--                            case 2:
--                                gen_helper_neon_qneg_s32(tmp, cpu_env, tmp);
--                                break;
--                            default: abort();
--                            }
--                            break;
-                         case NEON_2RM_VCGT0_F:
-                         {
-                             TCGv_ptr fpstatus = get_fpstatus_ptr(1);
---
-.20.1

-[PULL 18/42] target/arm: Convert Neon 2-reg-misc fp-compare-with-zero insns to decodetree
+Deleted patch
-Convert the fp-compare-with-zero insns in the Neon 2-reg-misc group to
-decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-17-peter.maydell@linaro.org
----
- target/arm/neon-dp.decode       |  6 ++++
- target/arm/translate-neon.inc.c | 28 ++++++++++++++++++
- target/arm/translate.c          | 50 ++++-----------------------------
-files changed, 39 insertions(+), 45 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
-+++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
-     VABS         1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc
-     VNEG         1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc
-+    VCGT0_F      1111 001 11 . 11 .. 01 .... 0 1000 . . 0 .... @2misc
-+    VCGE0_F      1111 001 11 . 11 .. 01 .... 0 1001 . . 0 .... @2misc
-+    VCEQ0_F      1111 001 11 . 11 .. 01 .... 0 1010 . . 0 .... @2misc
-+    VCLE0_F      1111 001 11 . 11 .. 01 .... 0 1011 . . 0 .... @2misc
-+    VCLT0_F      1111 001 11 . 11 .. 01 .... 0 1100 . . 0 .... @2misc
-+
-     VABS_F       1111 001 11 . 11 .. 01 .... 0 1110 . . 0 .... @2misc
-     VNEG_F       1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX(DisasContext *s, arg_2misc *a)
-     }
-     return do_2misc_fp(s, a, gen_helper_rints_exact);
- }
-+
-+#define WRAP_FP_CMP0_FWD(WRAPNAME, FUNC)                        \
-+    static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \
-+    {                                                           \
-+        TCGv_i32 zero = tcg_const_i32(0);                       \
-+        FUNC(d, m, zero, fpst);                                 \
-+        tcg_temp_free_i32(zero);                                \
-+    }
-+#define WRAP_FP_CMP0_REV(WRAPNAME, FUNC)                        \
-+    static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \
-+    {                                                           \
-+        TCGv_i32 zero = tcg_const_i32(0);                       \
-+        FUNC(d, zero, m, fpst);                                 \
-+        tcg_temp_free_i32(zero);                                \
-+    }
-+
-+#define DO_FP_CMP0(INSN, FUNC, REV)                             \
-+    WRAP_FP_CMP0_##REV(gen_##INSN, FUNC)                        \
-+    static bool trans_##INSN(DisasContext *s, arg_2misc *a)     \
-+    {                                                           \
-+        return do_2misc_fp(s, a, gen_##INSN);                   \
-+    }
-+
-+DO_FP_CMP0(VCGT0_F, gen_helper_neon_cgt_f32, FWD)
-+DO_FP_CMP0(VCGE0_F, gen_helper_neon_cge_f32, FWD)
-+DO_FP_CMP0(VCEQ0_F, gen_helper_neon_ceq_f32, FWD)
-+DO_FP_CMP0(VCLE0_F, gen_helper_neon_cge_f32, REV)
-+DO_FP_CMP0(VCLT0_F, gen_helper_neon_cgt_f32, REV)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                 case NEON_2RM_VCVT_SF:
-                 case NEON_2RM_VCVT_UF:
-                 case NEON_2RM_VRINTX:
-+                case NEON_2RM_VCGT0_F:
-+                case NEON_2RM_VCGE0_F:
-+                case NEON_2RM_VCEQ0_F:
-+                case NEON_2RM_VCLE0_F:
-+                case NEON_2RM_VCLT0_F:
-                     /* handled by decodetree */
-                     return 1;
-                 case NEON_2RM_VTRN:
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                     for (pass = 0; pass < (q ? 4 : 2); pass++) {
-                         tmp = neon_load_reg(rm, pass);
-                         switch (op) {
--                        case NEON_2RM_VCGT0_F:
--                        {
--                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
--                            tmp2 = tcg_const_i32(0);
--                            gen_helper_neon_cgt_f32(tmp, tmp, tmp2, fpstatus);
--                            tcg_temp_free_i32(tmp2);
--                            tcg_temp_free_ptr(fpstatus);
--                            break;
--                        }
--                        case NEON_2RM_VCGE0_F:
--                        {
--                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
--                            tmp2 = tcg_const_i32(0);
--                            gen_helper_neon_cge_f32(tmp, tmp, tmp2, fpstatus);
--                            tcg_temp_free_i32(tmp2);
--                            tcg_temp_free_ptr(fpstatus);
--                            break;
--                        }
--                        case NEON_2RM_VCEQ0_F:
--                        {
--                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
--                            tmp2 = tcg_const_i32(0);
--                            gen_helper_neon_ceq_f32(tmp, tmp, tmp2, fpstatus);
--                            tcg_temp_free_i32(tmp2);
--                            tcg_temp_free_ptr(fpstatus);
--                            break;
--                        }
--                        case NEON_2RM_VCLE0_F:
--                        {
--                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
--                            tmp2 = tcg_const_i32(0);
--                            gen_helper_neon_cge_f32(tmp, tmp2, tmp, fpstatus);
--                            tcg_temp_free_i32(tmp2);
--                            tcg_temp_free_ptr(fpstatus);
--                            break;
--                        }
--                        case NEON_2RM_VCLT0_F:
--                        {
--                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
--                            tmp2 = tcg_const_i32(0);
--                            gen_helper_neon_cgt_f32(tmp, tmp2, tmp, fpstatus);
--                            tcg_temp_free_i32(tmp2);
--                            tcg_temp_free_ptr(fpstatus);
--                            break;
--                        }
-                         case NEON_2RM_VSWP:
-                             tmp2 = neon_load_reg(rd, pass);
-                             neon_store_reg(rm, pass, tmp2);
---
-.20.1

-[PULL 19/42] target/arm: Convert Neon 2-reg-misc VRINT insns to decodetree
+Deleted patch
-Convert the Neon 2-reg-misc VRINT insns to decodetree.
-Giving these insns their own do_vrint() function allows us
-to change the rounding mode just once at the start and end
-rather than doing it for every element in the vector.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-18-peter.maydell@linaro.org
----
- target/arm/neon-dp.decode       |  8 +++++
- target/arm/translate-neon.inc.c | 61 +++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 31 +++--------------
-files changed, 74 insertions(+), 26 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
-+++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
-     SHA1SU1      1111 001 11 . 11 .. 10 .... 0 0111 0 . 0 .... @2misc_q1
-     SHA256SU0    1111 001 11 . 11 .. 10 .... 0 0111 1 . 0 .... @2misc_q1
-+    VRINTN       1111 001 11 . 11 .. 10 .... 0 1000 . . 0 .... @2misc
-     VRINTX       1111 001 11 . 11 .. 10 .... 0 1001 . . 0 .... @2misc
-+    VRINTA       1111 001 11 . 11 .. 10 .... 0 1010 . . 0 .... @2misc
-+    VRINTZ       1111 001 11 . 11 .. 10 .... 0 1011 . . 0 .... @2misc
-     VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0
-+
-+    VRINTM       1111 001 11 . 11 .. 10 .... 0 1101 . . 0 .... @2misc
-+
-     VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0
-+    VRINTP       1111 001 11 . 11 .. 10 .... 0 1111 . . 0 .... @2misc
-+
-     VRECPE       1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc
-     VRSQRTE      1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc
-     VRECPE_F     1111 001 11 . 11 .. 11 .... 0 1010 . . 0 .... @2misc
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ DO_FP_CMP0(VCGE0_F, gen_helper_neon_cge_f32, FWD)
- DO_FP_CMP0(VCEQ0_F, gen_helper_neon_ceq_f32, FWD)
- DO_FP_CMP0(VCLE0_F, gen_helper_neon_cge_f32, REV)
- DO_FP_CMP0(VCLT0_F, gen_helper_neon_cgt_f32, REV)
-+
-+static bool do_vrint(DisasContext *s, arg_2misc *a, int rmode)
-+{
-+    /*
-+     * Handle a VRINT* operation by iterating 32 bits at a time,
-+     * with a specified rounding mode in operation.
-+     */
-+    int pass;
-+    TCGv_ptr fpst;
-+    TCGv_i32 tcg_rmode;
-+
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
-+        !arm_dc_feature(s, ARM_FEATURE_V8)) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        ((a->vd | a->vm) & 0x10)) {
-+        return false;
-+    }
-+
-+    if (a->size != 2) {
-+        /* TODO: FP16 will be the size == 1 case */
-+        return false;
-+    }
-+
-+    if ((a->vd | a->vm) & a->q) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    fpst = get_fpstatus_ptr(1);
-+    tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
-+    gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env);
-+    for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
-+        TCGv_i32 tmp = neon_load_reg(a->vm, pass);
-+        gen_helper_rints(tmp, tmp, fpst);
-+        neon_store_reg(a->vd, pass, tmp);
-+    }
-+    gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env);
-+    tcg_temp_free_i32(tcg_rmode);
-+    tcg_temp_free_ptr(fpst);
-+
-+    return true;
-+}
-+
-+#define DO_VRINT(INSN, RMODE)                                   \
-+    static bool trans_##INSN(DisasContext *s, arg_2misc *a)     \
-+    {                                                           \
-+        return do_vrint(s, a, RMODE);                           \
-+    }
-+
-+DO_VRINT(VRINTN, FPROUNDING_TIEEVEN)
-+DO_VRINT(VRINTA, FPROUNDING_TIEAWAY)
-+DO_VRINT(VRINTZ, FPROUNDING_ZERO)
-+DO_VRINT(VRINTM, FPROUNDING_NEGINF)
-+DO_VRINT(VRINTP, FPROUNDING_POSINF)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                 case NEON_2RM_VCEQ0_F:
-                 case NEON_2RM_VCLE0_F:
-                 case NEON_2RM_VCLT0_F:
-+                case NEON_2RM_VRINTN:
-+                case NEON_2RM_VRINTA:
-+                case NEON_2RM_VRINTM:
-+                case NEON_2RM_VRINTP:
-+                case NEON_2RM_VRINTZ:
-                     /* handled by decodetree */
-                     return 1;
-                 case NEON_2RM_VTRN:
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                             }
-                             neon_store_reg(rm, pass, tmp2);
-                             break;
--                        case NEON_2RM_VRINTN:
--                        case NEON_2RM_VRINTA:
--                        case NEON_2RM_VRINTM:
--                        case NEON_2RM_VRINTP:
--                        case NEON_2RM_VRINTZ:
--                        {
--                            TCGv_i32 tcg_rmode;
--                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
--                            int rmode;
--
--                            if (op == NEON_2RM_VRINTZ) {
--                                rmode = FPROUNDING_ZERO;
--                            } else {
--                                rmode = fp_decode_rm[((op & 0x6) >> 1) ^ 1];
--                            }
--
--                            tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
--                            gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
--                                                      cpu_env);
--                            gen_helper_rints(tmp, tmp, fpstatus);
--                            gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
--                                                      cpu_env);
--                            tcg_temp_free_ptr(fpstatus);
--                            tcg_temp_free_i32(tcg_rmode);
--                            break;
--                        }
-                         case NEON_2RM_VCVTAU:
-                         case NEON_2RM_VCVTAS:
-                         case NEON_2RM_VCVTNU:
---
-.20.1

-[PULL 20/42] target/arm: Convert Neon 2-reg-misc VCVT insns to decodetree
+Deleted patch
-Convert the VCVT instructions in the 2-reg-misc grouping to
-decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200616170844.13318-19-peter.maydell@linaro.org
----
- target/arm/neon-dp.decode       |  9 +++++
- target/arm/translate-neon.inc.c | 70 +++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 70 ++++-----------------------------
-files changed, 87 insertions(+), 62 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
-+++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
-     VRINTP       1111 001 11 . 11 .. 10 .... 0 1111 . . 0 .... @2misc
-+    VCVTAS       1111 001 11 . 11 .. 11 .... 0 0000 . . 0 .... @2misc
-+    VCVTAU       1111 001 11 . 11 .. 11 .... 0 0001 . . 0 .... @2misc
-+    VCVTNS       1111 001 11 . 11 .. 11 .... 0 0010 . . 0 .... @2misc
-+    VCVTNU       1111 001 11 . 11 .. 11 .... 0 0011 . . 0 .... @2misc
-+    VCVTPS       1111 001 11 . 11 .. 11 .... 0 0100 . . 0 .... @2misc
-+    VCVTPU       1111 001 11 . 11 .. 11 .... 0 0101 . . 0 .... @2misc
-+    VCVTMS       1111 001 11 . 11 .. 11 .... 0 0110 . . 0 .... @2misc
-+    VCVTMU       1111 001 11 . 11 .. 11 .... 0 0111 . . 0 .... @2misc
-+
-     VRECPE       1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc
-     VRSQRTE      1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc
-     VRECPE_F     1111 001 11 . 11 .. 11 .... 0 1010 . . 0 .... @2misc
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ DO_VRINT(VRINTA, FPROUNDING_TIEAWAY)
- DO_VRINT(VRINTZ, FPROUNDING_ZERO)
- DO_VRINT(VRINTM, FPROUNDING_NEGINF)
- DO_VRINT(VRINTP, FPROUNDING_POSINF)
-+
-+static bool do_vcvt(DisasContext *s, arg_2misc *a, int rmode, bool is_signed)
-+{
-+    /*
-+     * Handle a VCVT* operation by iterating 32 bits at a time,
-+     * with a specified rounding mode in operation.
-+     */
-+    int pass;
-+    TCGv_ptr fpst;
-+    TCGv_i32 tcg_rmode, tcg_shift;
-+
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
-+        !arm_dc_feature(s, ARM_FEATURE_V8)) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        ((a->vd | a->vm) & 0x10)) {
-+        return false;
-+    }
-+
-+    if (a->size != 2) {
-+        /* TODO: FP16 will be the size == 1 case */
-+        return false;
-+    }
-+
-+    if ((a->vd | a->vm) & a->q) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    fpst = get_fpstatus_ptr(1);
-+    tcg_shift = tcg_const_i32(0);
-+    tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
-+    gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env);
-+    for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
-+        TCGv_i32 tmp = neon_load_reg(a->vm, pass);
-+        if (is_signed) {
-+            gen_helper_vfp_tosls(tmp, tmp, tcg_shift, fpst);
-+        } else {
-+            gen_helper_vfp_touls(tmp, tmp, tcg_shift, fpst);
-+        }
-+        neon_store_reg(a->vd, pass, tmp);
-+    }
-+    gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env);
-+    tcg_temp_free_i32(tcg_rmode);
-+    tcg_temp_free_i32(tcg_shift);
-+    tcg_temp_free_ptr(fpst);
-+
-+    return true;
-+}
-+
-+#define DO_VCVT(INSN, RMODE, SIGNED)                            \
-+    static bool trans_##INSN(DisasContext *s, arg_2misc *a)     \
-+    {                                                           \
-+        return do_vcvt(s, a, RMODE, SIGNED);                    \
-+    }
-+
-+DO_VCVT(VCVTAU, FPROUNDING_TIEAWAY, false)
-+DO_VCVT(VCVTAS, FPROUNDING_TIEAWAY, true)
-+DO_VCVT(VCVTNU, FPROUNDING_TIEEVEN, false)
-+DO_VCVT(VCVTNS, FPROUNDING_TIEEVEN, true)
-+DO_VCVT(VCVTPU, FPROUNDING_POSINF, false)
-+DO_VCVT(VCVTPS, FPROUNDING_POSINF, true)
-+DO_VCVT(VCVTMU, FPROUNDING_NEGINF, false)
-+DO_VCVT(VCVTMS, FPROUNDING_NEGINF, true)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
- #define NEON_2RM_VCVT_SF 62
- #define NEON_2RM_VCVT_UF 63
--static bool neon_2rm_is_v8_op(int op)
--{
--    /* Return true if this neon 2reg-misc op is ARMv8 and up */
--    switch (op) {
--    case NEON_2RM_VRINTN:
--    case NEON_2RM_VRINTA:
--    case NEON_2RM_VRINTM:
--    case NEON_2RM_VRINTP:
--    case NEON_2RM_VRINTZ:
--    case NEON_2RM_VRINTX:
--    case NEON_2RM_VCVTAU:
--    case NEON_2RM_VCVTAS:
--    case NEON_2RM_VCVTNU:
--    case NEON_2RM_VCVTNS:
--    case NEON_2RM_VCVTPU:
--    case NEON_2RM_VCVTPS:
--    case NEON_2RM_VCVTMU:
--    case NEON_2RM_VCVTMS:
--        return true;
--    default:
--        return false;
--    }
--}
--
- /* Each entry in this array has bit n set if the insn allows
-  * size value n (otherwise it will UNDEF). Since unallocated
-  * op values will have no bits set they always UNDEF.
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                 if ((neon_2rm_sizes[op] & (1 << size)) == 0) {
-                     return 1;
-                 }
--                if (neon_2rm_is_v8_op(op) &&
--                    !arm_dc_feature(s, ARM_FEATURE_V8)) {
--                    return 1;
--                }
-                 if (q && ((rm | rd) & 1)) {
-                     return 1;
-                 }
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                 case NEON_2RM_VRINTM:
-                 case NEON_2RM_VRINTP:
-                 case NEON_2RM_VRINTZ:
-+                case NEON_2RM_VCVTAU:
-+                case NEON_2RM_VCVTAS:
-+                case NEON_2RM_VCVTNU:
-+                case NEON_2RM_VCVTNS:
-+                case NEON_2RM_VCVTPU:
-+                case NEON_2RM_VCVTPS:
-+                case NEON_2RM_VCVTMU:
-+                case NEON_2RM_VCVTMS:
-                     /* handled by decodetree */
-                     return 1;
-                 case NEON_2RM_VTRN:
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                             }
-                             neon_store_reg(rm, pass, tmp2);
-                             break;
--                        case NEON_2RM_VCVTAU:
--                        case NEON_2RM_VCVTAS:
--                        case NEON_2RM_VCVTNU:
--                        case NEON_2RM_VCVTNS:
--                        case NEON_2RM_VCVTPU:
--                        case NEON_2RM_VCVTPS:
--                        case NEON_2RM_VCVTMU:
--                        case NEON_2RM_VCVTMS:
--                        {
--                            bool is_signed = !extract32(insn, 7, 1);
--                            TCGv_ptr fpst = get_fpstatus_ptr(1);
--                            TCGv_i32 tcg_rmode, tcg_shift;
--                            int rmode = fp_decode_rm[extract32(insn, 8, 2)];
--
--                            tcg_shift = tcg_const_i32(0);
--                            tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
--                            gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
--                                                      cpu_env);
--
--                            if (is_signed) {
--                                gen_helper_vfp_tosls(tmp, tmp,
--                                                     tcg_shift, fpst);
--                            } else {
--                                gen_helper_vfp_touls(tmp, tmp,
--                                                     tcg_shift, fpst);
--                            }
--
--                            gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
--                                                      cpu_env);
--                            tcg_temp_free_i32(tcg_rmode);
--                            tcg_temp_free_i32(tcg_shift);
--                            tcg_temp_free_ptr(fpst);
--                            break;
--                        }
-                         default:
-                             /* Reserved op values were caught by the
-                              * neon_2rm_sizes[] check earlier.
---
-.20.1

-[PULL 24/42] target/arm: Remove unnecessary gen_io_end() calls
+Deleted patch
-Since commit ba3e7926691ed3 it has been unnecessary for target code
-to call gen_io_end() after an IO instruction in icount mode; it is
-sufficient to call gen_io_start() before it and to force the end of
-the TB.
-Many now-unnecessary calls to gen_io_end() were removed in commit
-e9b10c6491153b, but some were missed or accidentally added later.
-Remove unneeded calls from the arm target:
- * the call in the handling of exception-return-via-LDM is
-   unnecessary, and the code is already forcing end-of-TB
- * the call in the VFP access check code is more complicated:
-   we weren't ending the TB, so we need to add the code to
-   force that by setting DISAS_UPDATE
- * the doc comment for ARM_CP_IO doesn't need to mention
-   gen_io_end() any more
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru>
-Message-id: 20200619170324.12093-1-peter.maydell@linaro.org
----
- target/arm/cpu.h               | 2 +-
- target/arm/translate-vfp.inc.c | 7 +++----
- target/arm/translate.c         | 3 ---
-files changed, 4 insertions(+), 8 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
-  * migration or KVM state synchronization. (Typically this is for "registers"
-  * which are actually used as instructions for cache maintenance and so on.)
-  * IO indicates that this register does I/O and therefore its accesses
-- * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
-+ * need to be marked with gen_io_start() and also end the TB. In particular,
-  * registers which implement clocks or timers require this.
-  * RAISES_EXC is for when the read or write hook might raise an exception;
-  * the generated code will synchronize the CPU state before calling the hook
-diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-vfp.inc.c
-+++ b/target/arm/translate-vfp.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
-         if (s->v7m_lspact) {
-             /*
-              * Lazy state saving affects external memory and also the NVIC,
--             * so we must mark it as an IO operation for icount.
-+             * so we must mark it as an IO operation for icount (and cause
-+             * this to be the last insn in the TB).
-              */
-             if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
-+                s->base.is_jmp = DISAS_UPDATE;
-                 gen_io_start();
-             }
-             gen_helper_v7m_preserve_fp_state(cpu_env);
--            if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
--                gen_io_end();
--            }
-             /*
-              * If the preserve_fp_state helper doesn't throw an exception
-              * then it will clear LSPACT; we don't need to repeat this for
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
-             gen_io_start();
-         }
-         gen_helper_cpsr_write_eret(cpu_env, tmp);
--        if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
--            gen_io_end();
--        }
-         tcg_temp_free_i32(tmp);
-         /* Must exit loop to check un-masked IRQs */
-         s->base.is_jmp = DISAS_EXIT;
---
-.20.1

-[PULL 25/42] target/arm: Remove dead code relating to SABA and UABA
+Deleted patch
-In commit cfdb2c0c95ae9205b0 ("target/arm: Vectorize SABA/UABA") we
-replaced the old handling of SABA/UABA with a vectorized implementation
-which returns early rather than falling into the loop-ever-elements
-code. We forgot to delete the part of the old looping code that
-did the accumulate step, and Coverity correctly warns (CID 1428955)
-that this code is now dead. Delete it.
-Fixes: cfdb2c0c95ae9205b0
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200619171547.29780-1-peter.maydell@linaro.org
----
- target/arm/translate-a64.c | 12 ------------
-file changed, 12 deletions(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
-                 genfn(tcg_res, tcg_op1, tcg_op2);
-             }
--            if (opcode == 0xf) {
--                /* SABA, UABA: accumulating ops */
--                static NeonGenTwoOpFn * const fns[3] = {
--                    gen_helper_neon_add_u8,
--                    gen_helper_neon_add_u16,
--                    tcg_gen_add_i32,
--                };
--
--                read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);
--                fns[size](tcg_res, tcg_op1, tcg_res);
--            }
--
-             write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
-             tcg_temp_free_i32(tcg_res);
---
-.20.1

-[PULL 26/42] hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status
+Deleted patch
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Add a trace event to see when a guest disable/enable the watchdog.
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20200617072539.32686-2-f4bug@amsat.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/watchdog/cmsdk-apb-watchdog.c | 1 +
- hw/watchdog/trace-events         | 1 +
-files changed, 2 insertions(+)
-diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/watchdog/cmsdk-apb-watchdog.c
-+++ b/hw/watchdog/cmsdk-apb-watchdog.c
-@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset,
-         break;
-     case A_WDOGLOCK:
-         s->lock = (value != WDOG_UNLOCK_VALUE);
-+        trace_cmsdk_apb_watchdog_lock(s->lock);
-         break;
-     case A_WDOGITCR:
-         if (s->is_luminary) {
-diff --git a/hw/watchdog/trace-events b/hw/watchdog/trace-events
-index XXXXXXX..XXXXXXX 100644
---- a/hw/watchdog/trace-events
-+++ b/hw/watchdog/trace-events
-@@ -XXX,XX +XXX,XX @@
- cmsdk_apb_watchdog_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
- cmsdk_apb_watchdog_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
- cmsdk_apb_watchdog_reset(void) "CMSDK APB watchdog: reset"
-+cmsdk_apb_watchdog_lock(uint32_t lock) "CMSDK APB watchdog: lock %" PRIu32
---
-.20.1

The following changes since commit 61fee7f45955cd0bf9b79be9fa9c7ebabb5e6a85:

Merge remote-tracking branch 'remotes/philmd-gitlab/tags/acceptance-testing-20200622' into staging (2020-06-22 20:50:10 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200623

for you to fetch changes up to 539533b85fbd269f777bed931de8ccae1dd837e9:

arm/virt: Add memory hot remove support (2020-06-23 11:39:48 +0100)

----------------------------------------------------------------
target-arm queue:
 * util/oslib-posix : qemu_init_exec_dir implementation for Mac
 * target/arm: Last parts of neon decodetree conversion
 * hw/arm/virt: Add 5.0 HW compat props
 * hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status
 * mps2: Add CMSDK APB watchdog, FPGAIO block, S2I devices and I2C devices
 * mps2: Add some unimplemented-device stubs for audio and GPIO
 * mps2-tz: Use the ARM SBCon two-wire serial bus interface
 * target/arm: Check supported KVM features globally (not per vCPU)
 * tests/qtest/arm-cpu-features: Add feature setting tests
 * arm/virt: Add memory hot remove support

----------------------------------------------------------------
Andrew Jones (2):
      hw/arm/virt: Add 5.0 HW compat props
      tests/qtest/arm-cpu-features: Add feature setting tests

David CARLIER (1):
      util/oslib-posix : qemu_init_exec_dir implementation for Mac

Peter Maydell (23):
      target/arm: Convert Neon 2-reg-misc VREV64 to decodetree
      target/arm: Convert Neon 2-reg-misc pairwise ops to decodetree
      target/arm: Convert VZIP, VUZP to decodetree
      target/arm: Convert Neon narrowing moves to decodetree
      target/arm: Convert Neon 2-reg-misc VSHLL to decodetree
      target/arm: Convert Neon VCVT f16/f32 insns to decodetree
      target/arm: Convert vectorised 2-reg-misc Neon ops to decodetree
      target/arm: Convert Neon 2-reg-misc crypto operations to decodetree
      target/arm: Rename NeonGenOneOpFn to NeonGenOne64OpFn
      target/arm: Fix capitalization in NeonGenTwo{Single, Double}OPFn typedefs
      target/arm: Make gen_swap_half() take separate src and dest
      target/arm: Convert Neon 2-reg-misc VREV32 and VREV16 to decodetree
      target/arm: Convert remaining simple 2-reg-misc Neon ops
      target/arm: Convert Neon VQABS, VQNEG to decodetree
      target/arm: Convert simple fp Neon 2-reg-misc insns
      target/arm: Convert Neon 2-reg-misc fp-compare-with-zero insns to decodetree
      target/arm: Convert Neon 2-reg-misc VRINT insns to decodetree
      target/arm: Convert Neon 2-reg-misc VCVT insns to decodetree
      target/arm: Convert Neon VSWP to decodetree
      target/arm: Convert Neon VTRN to decodetree
      target/arm: Move some functions used only in translate-neon.inc.c to that file
      target/arm: Remove unnecessary gen_io_end() calls
      target/arm: Remove dead code relating to SABA and UABA

Philippe Mathieu-Daudé (15):
      hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status
      hw/i2c/versatile_i2c: Add definitions for register addresses
      hw/i2c/versatile_i2c: Add SCL/SDA definitions
      hw/i2c: Add header for ARM SBCon two-wire serial bus interface
      hw/arm: Use TYPE_VERSATILE_I2C instead of hardcoded string
      hw/arm/mps2: Document CMSDK/FPGA APB subsystem sections
      hw/arm/mps2: Rename CMSDK AHB peripheral region
      hw/arm/mps2: Add CMSDK APB watchdog device
      hw/arm/mps2: Add CMSDK AHB GPIO peripherals as unimplemented devices
      hw/arm/mps2: Map the FPGA I/O block
      hw/arm/mps2: Add SPI devices
      hw/arm/mps2: Add I2C devices
      hw/arm/mps2: Add audio I2S interface as unimplemented device
      hw/arm/mps2-tz: Use the ARM SBCon two-wire serial bus interface
      target/arm: Check supported KVM features globally (not per vCPU)

Shameer Kolothum (1):
      arm/virt: Add memory hot remove support

From: David CARLIER <devnexen@gmail.com>

From 3025a0ce3fdf7d3559fc35a52c659f635f5c750c Mon Sep 17 00:00:00 2001
From: David Carlier <devnexen@gmail.com>
Date: Tue, 26 May 2020 21:35:27 +0100
Subject: [PATCH] util/oslib-posix : qemu_init_exec_dir implementation for Mac

Using dyld API to get the full path of the current process.

Signed-off-by: David Carlier <devnexen@gmail.com>
Message-id: CA+XhMqxwC10XHVs4Z-JfE0-WLAU3ztDuU9QKVi31mjr59HWCxg@mail.gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 util/oslib-posix.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/util/oslib-posix.c b/util/oslib-posix.c
index XXXXXXX..XXXXXXX 100644
--- a/util/oslib-posix.c
+++ b/util/oslib-posix.c
@@ -XXX,XX +XXX,XX @@
 #include <lwp.h>
 #endif
 
+#ifdef __APPLE__
+#include <mach-o/dyld.h>
+#endif
+
 #include "qemu/mmap-alloc.h"
 
 #ifdef CONFIG_DEBUG_STACK_USAGE
@@ -XXX,XX +XXX,XX @@ void qemu_init_exec_dir(const char *argv0)
             p = buf;
         }
     }
+#elif defined(__APPLE__)
+    {
+        char fpath[PATH_MAX];
+        uint32_t len = sizeof(fpath);
+        if (_NSGetExecutablePath(fpath, &len) == 0) {
+            p = realpath(fpath, buf);
+            if (!p) {
+                return;
+            }
+        }
+    }
 #endif
     /* If we don't have any way of figuring out the actual executable
        location then try argv[0].  */
-- 
2.20.1

Convert the Neon VREV64 insn from the 2-reg-misc grouping to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-2-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 12 ++++++++
 target/arm/translate-neon.inc.c | 50 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 24 ++--------------
 3 files changed, 64 insertions(+), 22 deletions(-)

Convert the pairwise ops VPADDL and VPADAL in the 2-reg-misc grouping
to decodetree.

At this point we can get rid of the weird CPU_V001 #define that was
used to avoid having to explicitly list all the arguments being
passed to some TCG gen/helper functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-3-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |   6 ++
 target/arm/translate-neon.inc.c | 149 ++++++++++++++++++++++++++++++++
 target/arm/translate.c          |  35 +-------
 3 files changed, 157 insertions(+), 33 deletions(-)

Convert the Neon VZIP and VUZP insns in the 2-reg-misc group to
decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-4-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  3 ++
 target/arm/translate-neon.inc.c | 74 ++++++++++++++++++++++++++
 target/arm/translate.c          | 92 +--------------------------------
 3 files changed, 79 insertions(+), 90 deletions(-)

Convert the Neon narrowing moves VMQNV, VQMOVN, VQMOVUN in the 2-reg-misc
group to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-5-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  9 ++++
 target/arm/translate-neon.inc.c | 59 ++++++++++++++++++++++++
 target/arm/translate.c          | 81 +--------------------------------
 3 files changed, 70 insertions(+), 79 deletions(-)

Convert the VSHLL insn in the 2-reg-misc Neon group to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-6-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  2 ++
 target/arm/translate-neon.inc.c | 52 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 35 +---------------------
 3 files changed, 55 insertions(+), 34 deletions(-)

Convert the Neon insns in the 2-reg-misc group which are
VCVT between f32 and f16 to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-7-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  3 ++
 target/arm/translate-neon.inc.c | 96 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 65 ++--------------------
 3 files changed, 102 insertions(+), 62 deletions(-)

Convert to decodetree the insns in the Neon 2-reg-misc grouping which
we implement using gvec.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-8-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 11 +++++++
 target/arm/translate-neon.inc.c | 55 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 35 +++++----------------
 3 files changed, 74 insertions(+), 27 deletions(-)

Convert the Neon-2-reg misc crypto ops (AESE, AESMC, SHA1H, SHA1SU1)
to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-9-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 12 ++++++++
 target/arm/translate-neon.inc.c | 42 ++++++++++++++++++++++++++
 target/arm/translate.c          | 52 +++------------------------------
 3 files changed, 58 insertions(+), 48 deletions(-)

The NeonGenOneOpFn typedef breaks with the pattern of the other
NeonGen*Fn typedefs, because it is a TCGv_i64 -> TCGv_i64 operation
but it does not have '64' in its name. Rename it to NeonGenOne64OpFn,
so that the old name is available for a TCGv_i32 -> TCGv_i32 operation
(which we will need in a subsequent commit).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-10-peter.maydell@linaro.org
---
 target/arm/translate.h     | 2 +-
 target/arm/translate-a64.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

All the other typedefs like these spell "Op" with a lowercase 'p';
remane the NeonGenTwoSingleOPFn and NeonGenTwoDoubleOPFn typedefs to
match.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-11-peter.maydell@linaro.org
---
 target/arm/translate.h          | 4 ++--
 target/arm/translate-a64.c      | 4 ++--
 target/arm/translate-neon.inc.c | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

Make gen_swap_half() take a source and destination TCGv_i32 rather
than modifying the input TCGv_i32; we're going to want to be able to
use it with the more flexible function signature, and this also
brings it into line with other functions like gen_rev16() and
gen_revsh().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-12-peter.maydell@linaro.org
---
 target/arm/translate-neon.inc.c |  2 +-
 target/arm/translate.c          | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
                 tcg_gen_bswap32_i32(tmp[half], tmp[half]);
                 break;
             case 1:
-                gen_swap_half(tmp[half]);
+                gen_swap_half(tmp[half], tmp[half]);
                 break;
             case 2:
                 break;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_revsh(TCGv_i32 dest, TCGv_i32 var)
 }
 
 /* Swap low and high halfwords.  */
-static void gen_swap_half(TCGv_i32 var)
+static void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
 {
-    tcg_gen_rotri_i32(var, var, 16);
+    tcg_gen_rotri_i32(dest, var, 16);
 }
 
 /* Dual 16-bit add.  Result placed in t0 and t1 is marked as dead.
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                         case NEON_2RM_VREV32:
                             switch (size) {
                             case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
-                            case 1: gen_swap_half(tmp); break;
+                            case 1: gen_swap_half(tmp, tmp); break;
                             default: abort();
                             }
                             break;
@@ -XXX,XX +XXX,XX @@ static bool op_smlad(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub)
     t1 = load_reg(s, a->rn);
     t2 = load_reg(s, a->rm);
     if (m_swap) {
-        gen_swap_half(t2);
+        gen_swap_half(t2, t2);
     }
     gen_smul_dual(t1, t2);
 
@@ -XXX,XX +XXX,XX @@ static bool op_smlald(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub)
     t1 = load_reg(s, a->rn);
     t2 = load_reg(s, a->rm);
     if (m_swap) {
-        gen_swap_half(t2);
+        gen_swap_half(t2, t2);
     }
     gen_smul_dual(t1, t2);
 
-- 
2.20.1

Convert the VREV32 and VREV16 insns in the Neon 2-reg-misc group
to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-13-peter.maydell@linaro.org
---
 target/arm/translate.h          |  1 +
 target/arm/neon-dp.decode       |  2 ++
 target/arm/translate-neon.inc.c | 55 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 12 ++-----
 4 files changed, 60 insertions(+), 10 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
                         uint32_t, uint32_t, uint32_t);
 
 /* Function prototype for gen_ functions for calling Neon helpers */
+typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32);
 typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
                  &2misc vm=%vm_dp vd=%vd_dp q=1
 
     VREV64       1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc
+    VREV32       1111 001 11 . 11 .. 00 .... 0 0001 . . 0 .... @2misc
+    VREV16       1111 001 11 . 11 .. 00 .... 0 0010 . . 0 .... @2misc
 
     VPADDL_S     1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc
     VPADDL_U     1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ DO_2M_CRYPTO(AESIMC, aa32_aes, 0)
 DO_2M_CRYPTO(SHA1H, aa32_sha1, 2)
 DO_2M_CRYPTO(SHA1SU1, aa32_sha1, 2)
 DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2)
+
+static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn)
+{
+    int pass;
+
+    /* Handle a 2-reg-misc operation by iterating 32 bits at a time */
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if (!fn) {
+        return false;
+    }
+
+    if ((a->vd | a->vm) & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
+        TCGv_i32 tmp = neon_load_reg(a->vm, pass);
+        fn(tmp, tmp);
+        neon_store_reg(a->vd, pass, tmp);
+    }
+
+    return true;
+}
+
+static bool trans_VREV32(DisasContext *s, arg_2misc *a)
+{
+    static NeonGenOneOpFn * const fn[] = {
+        tcg_gen_bswap32_i32,
+        gen_swap_half,
+        NULL,
+        NULL,
+    };
+    return do_2misc(s, a, fn[a->size]);
+}
+
+static bool trans_VREV16(DisasContext *s, arg_2misc *a)
+{
+    if (a->size != 0) {
+        return false;
+    }
+    return do_2misc(s, a, gen_rev16);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                 case NEON_2RM_AESE: case NEON_2RM_AESMC:
                 case NEON_2RM_SHA1H:
                 case NEON_2RM_SHA1SU1:
+                case NEON_2RM_VREV32:
+                case NEON_2RM_VREV16:
                     /* handled by decodetree */
                     return 1;
                 case NEON_2RM_VTRN:
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     for (pass = 0; pass < (q ? 4 : 2); pass++) {
                         tmp = neon_load_reg(rm, pass);
                         switch (op) {
-                        case NEON_2RM_VREV32:
-                            switch (size) {
-                            case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
-                            case 1: gen_swap_half(tmp, tmp); break;
-                            default: abort();
-                            }
-                            break;
-                        case NEON_2RM_VREV16:
-                            gen_rev16(tmp, tmp);
-                            break;
                         case NEON_2RM_VCLS:
                             switch (size) {
                             case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
-- 
2.20.1

Convert the remaining ops in the Neon 2-reg-misc group which
can be implemented simply with our do_2misc() helper.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-14-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 10 +++++
 target/arm/translate-neon.inc.c | 69 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 38 ++++--------------
 3 files changed, 86 insertions(+), 31 deletions(-)

Convert the Neon VQABS and VQNEG insns to decodetree.
Since these are the only ones which need cpu_env passing to
the helper, we wrap the helper rather than creating a whole
new do_2misc_env() function.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-15-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  3 +++
 target/arm/translate-neon.inc.c | 35 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 30 ++--------------------------
 3 files changed, 40 insertions(+), 28 deletions(-)

Convert the Neon 2-reg-misc insns which are implemented with
simple calls to functions that take the input, output and
fpstatus pointer.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-16-peter.maydell@linaro.org
---
 target/arm/translate.h          |  1 +
 target/arm/neon-dp.decode       |  8 +++++
 target/arm/translate-neon.inc.c | 62 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 56 ++++-------------------------
 4 files changed, 78 insertions(+), 49 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
 typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
 typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
+typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr);
 typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
 typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
 typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
     SHA1SU1      1111 001 11 . 11 .. 10 .... 0 0111 0 . 0 .... @2misc_q1
     SHA256SU0    1111 001 11 . 11 .. 10 .... 0 0111 1 . 0 .... @2misc_q1
 
+    VRINTX       1111 001 11 . 11 .. 10 .... 0 1001 . . 0 .... @2misc
+
     VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0
     VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0
 
     VRECPE       1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc
     VRSQRTE      1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc
+    VRECPE_F     1111 001 11 . 11 .. 11 .... 0 1010 . . 0 .... @2misc
+    VRSQRTE_F    1111 001 11 . 11 .. 11 .... 0 1011 . . 0 .... @2misc
+    VCVT_FS      1111 001 11 . 11 .. 11 .... 0 1100 . . 0 .... @2misc
+    VCVT_FU      1111 001 11 . 11 .. 11 .... 0 1101 . . 0 .... @2misc
+    VCVT_SF      1111 001 11 . 11 .. 11 .... 0 1110 . . 0 .... @2misc
+    VCVT_UF      1111 001 11 . 11 .. 11 .... 0 1111 . . 0 .... @2misc
   ]
 
   # Subgroup for size != 0b11
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VQNEG(DisasContext *s, arg_2misc *a)
     };
     return do_2misc(s, a, fn[a->size]);
 }
+
+static bool do_2misc_fp(DisasContext *s, arg_2misc *a,
+                        NeonGenOneSingleOpFn *fn)
+{
+    int pass;
+    TCGv_ptr fpst;
+
+    /* Handle a 2-reg-misc operation by iterating 32 bits at a time */
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if (a->size != 2) {
+        /* TODO: FP16 will be the size == 1 case */
+        return false;
+    }
+
+    if ((a->vd | a->vm) & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    fpst = get_fpstatus_ptr(1);
+    for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
+        TCGv_i32 tmp = neon_load_reg(a->vm, pass);
+        fn(tmp, tmp, fpst);
+        neon_store_reg(a->vd, pass, tmp);
+    }
+    tcg_temp_free_ptr(fpst);
+
+    return true;
+}
+
+#define DO_2MISC_FP(INSN, FUNC)                                 \
+    static bool trans_##INSN(DisasContext *s, arg_2misc *a)     \
+    {                                                           \
+        return do_2misc_fp(s, a, FUNC);                         \
+    }
+
+DO_2MISC_FP(VRECPE_F, gen_helper_recpe_f32)
+DO_2MISC_FP(VRSQRTE_F, gen_helper_rsqrte_f32)
+DO_2MISC_FP(VCVT_FS, gen_helper_vfp_sitos)
+DO_2MISC_FP(VCVT_FU, gen_helper_vfp_uitos)
+DO_2MISC_FP(VCVT_SF, gen_helper_vfp_tosizs)
+DO_2MISC_FP(VCVT_UF, gen_helper_vfp_touizs)
+
+static bool trans_VRINTX(DisasContext *s, arg_2misc *a)
+{
+    if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
+        return false;
+    }
+    return do_2misc_fp(s, a, gen_helper_rints_exact);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                 case NEON_2RM_VRSQRTE:
                 case NEON_2RM_VQABS:
                 case NEON_2RM_VQNEG:
+                case NEON_2RM_VRECPE_F:
+                case NEON_2RM_VRSQRTE_F:
+                case NEON_2RM_VCVT_FS:
+                case NEON_2RM_VCVT_FU:
+                case NEON_2RM_VCVT_SF:
+                case NEON_2RM_VCVT_UF:
+                case NEON_2RM_VRINTX:
                     /* handled by decodetree */
                     return 1;
                 case NEON_2RM_VTRN:
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                             tcg_temp_free_i32(tcg_rmode);
                             break;
                         }
-                        case NEON_2RM_VRINTX:
-                        {
-                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
-                            gen_helper_rints_exact(tmp, tmp, fpstatus);
-                            tcg_temp_free_ptr(fpstatus);
-                            break;
-                        }
                         case NEON_2RM_VCVTAU:
                         case NEON_2RM_VCVTAS:
                         case NEON_2RM_VCVTNU:
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                             tcg_temp_free_ptr(fpst);
                             break;
                         }
-                        case NEON_2RM_VRECPE_F:
-                        {
-                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
-                            gen_helper_recpe_f32(tmp, tmp, fpstatus);
-                            tcg_temp_free_ptr(fpstatus);
-                            break;
-                        }
-                        case NEON_2RM_VRSQRTE_F:
-                        {
-                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
-                            gen_helper_rsqrte_f32(tmp, tmp, fpstatus);
-                            tcg_temp_free_ptr(fpstatus);
-                            break;
-                        }
-                        case NEON_2RM_VCVT_FS: /* VCVT.F32.S32 */
-                        {
-                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
-                            gen_helper_vfp_sitos(tmp, tmp, fpstatus);
-                            tcg_temp_free_ptr(fpstatus);
-                            break;
-                        }
-                        case NEON_2RM_VCVT_FU: /* VCVT.F32.U32 */
-                        {
-                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
-                            gen_helper_vfp_uitos(tmp, tmp, fpstatus);
-                            tcg_temp_free_ptr(fpstatus);
-                            break;
-                        }
-                        case NEON_2RM_VCVT_SF: /* VCVT.S32.F32 */
-                        {
-                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
-                            gen_helper_vfp_tosizs(tmp, tmp, fpstatus);
-                            tcg_temp_free_ptr(fpstatus);
-                            break;
-                        }
-                        case NEON_2RM_VCVT_UF: /* VCVT.U32.F32 */
-                        {
-                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
-                            gen_helper_vfp_touizs(tmp, tmp, fpstatus);
-                            tcg_temp_free_ptr(fpstatus);
-                            break;
-                        }
                         default:
                             /* Reserved op values were caught by the
                              * neon_2rm_sizes[] check earlier.
-- 
2.20.1

Convert the fp-compare-with-zero insns in the Neon 2-reg-misc group to
decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-17-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  6 ++++
 target/arm/translate-neon.inc.c | 28 ++++++++++++++++++
 target/arm/translate.c          | 50 ++++-----------------------------
 3 files changed, 39 insertions(+), 45 deletions(-)

Convert the Neon 2-reg-misc VRINT insns to decodetree.
Giving these insns their own do_vrint() function allows us
to change the rounding mode just once at the start and end
rather than doing it for every element in the vector.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-18-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  8 +++++
 target/arm/translate-neon.inc.c | 61 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 31 +++--------------
 3 files changed, 74 insertions(+), 26 deletions(-)

Convert the VCVT instructions in the 2-reg-misc grouping to
decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-19-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  9 +++++
 target/arm/translate-neon.inc.c | 70 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 70 ++++-----------------------------
 3 files changed, 87 insertions(+), 62 deletions(-)

Convert the Neon VSWP insn to decodetree. Since the new implementation
doesn't have to share a pass-loop with the other 2-reg-misc operations
we can implement the swap with 64-bit accesses rather than 32-bits
(which brings us into line with the pseudocode and is more efficient).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-20-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  2 ++
 target/arm/translate-neon.inc.c | 41 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          |  5 +---
 3 files changed, 44 insertions(+), 4 deletions(-)

Convert the Neon VTRN insn to decodetree. This is the last insn in the
Neon data-processing group, so we can remove all the now-unused old
decoder framework.

It's possible that there's a more efficient implementation of
VTRN, but for this conversion we just copy the existing approach.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-21-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |   2 +-
 target/arm/translate-neon.inc.c |  90 ++++++++
 target/arm/translate.c          | 363 +-------------------------------
 3 files changed, 93 insertions(+), 362 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
     VNEG_F       1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc
 
     VSWP         1111 001 11 . 11 .. 10 .... 0 0000 . . 0 .... @2misc
-
+    VTRN         1111 001 11 . 11 .. 10 .... 0 0001 . . 0 .... @2misc
     VUZP         1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc
     VZIP         1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc
 
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VSWP(DisasContext *s, arg_2misc *a)
 
     return true;
 }
+static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1)
+{
+    TCGv_i32 rd, tmp;
+
+    rd = tcg_temp_new_i32();
+    tmp = tcg_temp_new_i32();
+
+    tcg_gen_shli_i32(rd, t0, 8);
+    tcg_gen_andi_i32(rd, rd, 0xff00ff00);
+    tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
+    tcg_gen_or_i32(rd, rd, tmp);
+
+    tcg_gen_shri_i32(t1, t1, 8);
+    tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
+    tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
+    tcg_gen_or_i32(t1, t1, tmp);
+    tcg_gen_mov_i32(t0, rd);
+
+    tcg_temp_free_i32(tmp);
+    tcg_temp_free_i32(rd);
+}
+
+static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
+{
+    TCGv_i32 rd, tmp;
+
+    rd = tcg_temp_new_i32();
+    tmp = tcg_temp_new_i32();
+
+    tcg_gen_shli_i32(rd, t0, 16);
+    tcg_gen_andi_i32(tmp, t1, 0xffff);
+    tcg_gen_or_i32(rd, rd, tmp);
+    tcg_gen_shri_i32(t1, t1, 16);
+    tcg_gen_andi_i32(tmp, t0, 0xffff0000);
+    tcg_gen_or_i32(t1, t1, tmp);
+    tcg_gen_mov_i32(t0, rd);
+
+    tcg_temp_free_i32(tmp);
+    tcg_temp_free_i32(rd);
+}
+
+static bool trans_VTRN(DisasContext *s, arg_2misc *a)
+{
+    TCGv_i32 tmp, tmp2;
+    int pass;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if ((a->vd | a->vm) & a->q) {
+        return false;
+    }
+
+    if (a->size == 3) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    if (a->size == 2) {
+        for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) {
+            tmp = neon_load_reg(a->vm, pass);
+            tmp2 = neon_load_reg(a->vd, pass + 1);
+            neon_store_reg(a->vm, pass, tmp2);
+            neon_store_reg(a->vd, pass + 1, tmp);
+        }
+    } else {
+        for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
+            tmp = neon_load_reg(a->vm, pass);
+            tmp2 = neon_load_reg(a->vd, pass);
+            if (a->size == 0) {
+                gen_neon_trn_u8(tmp, tmp2);
+            } else {
+                gen_neon_trn_u16(tmp, tmp2);
+            }
+            neon_store_reg(a->vm, pass, tmp2);
+            neon_store_reg(a->vd, pass, tmp);
+        }
+    }
+    return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc)
     gen_rfe(s, pc, load_cpu_field(spsr));
 }
 
-static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1)
-{
-    TCGv_i32 rd, tmp;
-
-    rd = tcg_temp_new_i32();
-    tmp = tcg_temp_new_i32();
-
-    tcg_gen_shli_i32(rd, t0, 8);
-    tcg_gen_andi_i32(rd, rd, 0xff00ff00);
-    tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
-    tcg_gen_or_i32(rd, rd, tmp);
-
-    tcg_gen_shri_i32(t1, t1, 8);
-    tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
-    tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
-    tcg_gen_or_i32(t1, t1, tmp);
-    tcg_gen_mov_i32(t0, rd);
-
-    tcg_temp_free_i32(tmp);
-    tcg_temp_free_i32(rd);
-}
-
-static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
-{
-    TCGv_i32 rd, tmp;
-
-    rd = tcg_temp_new_i32();
-    tmp = tcg_temp_new_i32();
-
-    tcg_gen_shli_i32(rd, t0, 16);
-    tcg_gen_andi_i32(tmp, t1, 0xffff);
-    tcg_gen_or_i32(rd, rd, tmp);
-    tcg_gen_shri_i32(t1, t1, 16);
-    tcg_gen_andi_i32(tmp, t0, 0xffff0000);
-    tcg_gen_or_i32(t1, t1, tmp);
-    tcg_gen_mov_i32(t0, rd);
-
-    tcg_temp_free_i32(tmp);
-    tcg_temp_free_i32(rd);
-}
-
-/* Symbolic constants for op fields for Neon 2-register miscellaneous.
- * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B
- * table A7-13.
- */
-#define NEON_2RM_VREV64 0
-#define NEON_2RM_VREV32 1
-#define NEON_2RM_VREV16 2
-#define NEON_2RM_VPADDL 4
-#define NEON_2RM_VPADDL_U 5
-#define NEON_2RM_AESE 6 /* Includes AESD */
-#define NEON_2RM_AESMC 7 /* Includes AESIMC */
-#define NEON_2RM_VCLS 8
-#define NEON_2RM_VCLZ 9
-#define NEON_2RM_VCNT 10
-#define NEON_2RM_VMVN 11
-#define NEON_2RM_VPADAL 12
-#define NEON_2RM_VPADAL_U 13
-#define NEON_2RM_VQABS 14
-#define NEON_2RM_VQNEG 15
-#define NEON_2RM_VCGT0 16
-#define NEON_2RM_VCGE0 17
-#define NEON_2RM_VCEQ0 18
-#define NEON_2RM_VCLE0 19
-#define NEON_2RM_VCLT0 20
-#define NEON_2RM_SHA1H 21
-#define NEON_2RM_VABS 22
-#define NEON_2RM_VNEG 23
-#define NEON_2RM_VCGT0_F 24
-#define NEON_2RM_VCGE0_F 25
-#define NEON_2RM_VCEQ0_F 26
-#define NEON_2RM_VCLE0_F 27
-#define NEON_2RM_VCLT0_F 28
-#define NEON_2RM_VABS_F 30
-#define NEON_2RM_VNEG_F 31
-#define NEON_2RM_VSWP 32
-#define NEON_2RM_VTRN 33
-#define NEON_2RM_VUZP 34
-#define NEON_2RM_VZIP 35
-#define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
-#define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
-#define NEON_2RM_VSHLL 38
-#define NEON_2RM_SHA1SU1 39 /* Includes SHA256SU0 */
-#define NEON_2RM_VRINTN 40
-#define NEON_2RM_VRINTX 41
-#define NEON_2RM_VRINTA 42
-#define NEON_2RM_VRINTZ 43
-#define NEON_2RM_VCVT_F16_F32 44
-#define NEON_2RM_VRINTM 45
-#define NEON_2RM_VCVT_F32_F16 46
-#define NEON_2RM_VRINTP 47
-#define NEON_2RM_VCVTAU 48
-#define NEON_2RM_VCVTAS 49
-#define NEON_2RM_VCVTNU 50
-#define NEON_2RM_VCVTNS 51
-#define NEON_2RM_VCVTPU 52
-#define NEON_2RM_VCVTPS 53
-#define NEON_2RM_VCVTMU 54
-#define NEON_2RM_VCVTMS 55
-#define NEON_2RM_VRECPE 56
-#define NEON_2RM_VRSQRTE 57
-#define NEON_2RM_VRECPE_F 58
-#define NEON_2RM_VRSQRTE_F 59
-#define NEON_2RM_VCVT_FS 60
-#define NEON_2RM_VCVT_FU 61
-#define NEON_2RM_VCVT_SF 62
-#define NEON_2RM_VCVT_UF 63
-
-/* Each entry in this array has bit n set if the insn allows
- * size value n (otherwise it will UNDEF). Since unallocated
- * op values will have no bits set they always UNDEF.
- */
-static const uint8_t neon_2rm_sizes[] = {
-    [NEON_2RM_VREV64] = 0x7,
-    [NEON_2RM_VREV32] = 0x3,
-    [NEON_2RM_VREV16] = 0x1,
-    [NEON_2RM_VPADDL] = 0x7,
-    [NEON_2RM_VPADDL_U] = 0x7,
-    [NEON_2RM_AESE] = 0x1,
-    [NEON_2RM_AESMC] = 0x1,
-    [NEON_2RM_VCLS] = 0x7,
-    [NEON_2RM_VCLZ] = 0x7,
-    [NEON_2RM_VCNT] = 0x1,
-    [NEON_2RM_VMVN] = 0x1,
-    [NEON_2RM_VPADAL] = 0x7,
-    [NEON_2RM_VPADAL_U] = 0x7,
-    [NEON_2RM_VQABS] = 0x7,
-    [NEON_2RM_VQNEG] = 0x7,
-    [NEON_2RM_VCGT0] = 0x7,
-    [NEON_2RM_VCGE0] = 0x7,
-    [NEON_2RM_VCEQ0] = 0x7,
-    [NEON_2RM_VCLE0] = 0x7,
-    [NEON_2RM_VCLT0] = 0x7,
-    [NEON_2RM_SHA1H] = 0x4,
-    [NEON_2RM_VABS] = 0x7,
-    [NEON_2RM_VNEG] = 0x7,
-    [NEON_2RM_VCGT0_F] = 0x4,
-    [NEON_2RM_VCGE0_F] = 0x4,
-    [NEON_2RM_VCEQ0_F] = 0x4,
-    [NEON_2RM_VCLE0_F] = 0x4,
-    [NEON_2RM_VCLT0_F] = 0x4,
-    [NEON_2RM_VABS_F] = 0x4,
-    [NEON_2RM_VNEG_F] = 0x4,
-    [NEON_2RM_VSWP] = 0x1,
-    [NEON_2RM_VTRN] = 0x7,
-    [NEON_2RM_VUZP] = 0x7,
-    [NEON_2RM_VZIP] = 0x7,
-    [NEON_2RM_VMOVN] = 0x7,
-    [NEON_2RM_VQMOVN] = 0x7,
-    [NEON_2RM_VSHLL] = 0x7,
-    [NEON_2RM_SHA1SU1] = 0x4,
-    [NEON_2RM_VRINTN] = 0x4,
-    [NEON_2RM_VRINTX] = 0x4,
-    [NEON_2RM_VRINTA] = 0x4,
-    [NEON_2RM_VRINTZ] = 0x4,
-    [NEON_2RM_VCVT_F16_F32] = 0x2,
-    [NEON_2RM_VRINTM] = 0x4,
-    [NEON_2RM_VCVT_F32_F16] = 0x2,
-    [NEON_2RM_VRINTP] = 0x4,
-    [NEON_2RM_VCVTAU] = 0x4,
-    [NEON_2RM_VCVTAS] = 0x4,
-    [NEON_2RM_VCVTNU] = 0x4,
-    [NEON_2RM_VCVTNS] = 0x4,
-    [NEON_2RM_VCVTPU] = 0x4,
-    [NEON_2RM_VCVTPS] = 0x4,
-    [NEON_2RM_VCVTMU] = 0x4,
-    [NEON_2RM_VCVTMS] = 0x4,
-    [NEON_2RM_VRECPE] = 0x4,
-    [NEON_2RM_VRSQRTE] = 0x4,
-    [NEON_2RM_VRECPE_F] = 0x4,
-    [NEON_2RM_VRSQRTE_F] = 0x4,
-    [NEON_2RM_VCVT_FS] = 0x4,
-    [NEON_2RM_VCVT_FU] = 0x4,
-    [NEON_2RM_VCVT_SF] = 0x4,
-    [NEON_2RM_VCVT_UF] = 0x4,
-};
-
 static void gen_gvec_fn3_qc(uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_ofs,
                             uint32_t opr_sz, uint32_t max_sz,
                             gen_helper_gvec_3_ptr *fn)
@@ -XXX,XX +XXX,XX @@ void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
     tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]);
 }
 
-/* Translate a NEON data processing instruction.  Return nonzero if the
-   instruction is invalid.
-   We process data in a mixture of 32-bit and 64-bit chunks.
-   Mostly we use 32-bit chunks so we can use normal scalar instructions.  */
-
-static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-{
-    int op;
-    int q;
-    int rd, rm;
-    int size;
-    int pass;
-    int u;
-    TCGv_i32 tmp, tmp2;
-
-    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-        return 1;
-    }
-
-    /* FIXME: this access check should not take precedence over UNDEF
-     * for invalid encodings; we will generate incorrect syndrome information
-     * for attempts to execute invalid vfp/neon encodings with FP disabled.
-     */
-    if (s->fp_excp_el) {
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-                           syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
-        return 0;
-    }
-
-    if (!s->vfp_enabled)
-      return 1;
-    q = (insn & (1 << 6)) != 0;
-    u = (insn >> 24) & 1;
-    VFP_DREG_D(rd, insn);
-    VFP_DREG_M(rm, insn);
-    size = (insn >> 20) & 3;
-
-    if ((insn & (1 << 23)) == 0) {
-        /* Three register same length: handled by decodetree */
-        return 1;
-    } else if (insn & (1 << 4)) {
-        /* Two registers and shift or reg and imm: handled by decodetree */
-        return 1;
-    } else { /* (insn & 0x00800010 == 0x00800000) */
-        if (size != 3) {
-            /*
-             * Three registers of different lengths, or two registers and
-             * a scalar: handled by decodetree
-             */
-            return 1;
-        } else { /* size == 3 */
-            if (!u) {
-                /* Extract: handled by decodetree */
-                return 1;
-            } else if ((insn & (1 << 11)) == 0) {
-                /* Two register misc.  */
-                op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
-                size = (insn >> 18) & 3;
-                /* UNDEF for unknown op values and bad op-size combinations */
-                if ((neon_2rm_sizes[op] & (1 << size)) == 0) {
-                    return 1;
-                }
-                if (q && ((rm | rd) & 1)) {
-                    return 1;
-                }
-                switch (op) {
-                case NEON_2RM_VREV64:
-                case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U:
-                case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U:
-                case NEON_2RM_VUZP:
-                case NEON_2RM_VZIP:
-                case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN:
-                case NEON_2RM_VSHLL:
-                case NEON_2RM_VCVT_F16_F32:
-                case NEON_2RM_VCVT_F32_F16:
-                case NEON_2RM_VMVN:
-                case NEON_2RM_VNEG:
-                case NEON_2RM_VABS:
-                case NEON_2RM_VCEQ0:
-                case NEON_2RM_VCGT0:
-                case NEON_2RM_VCLE0:
-                case NEON_2RM_VCGE0:
-                case NEON_2RM_VCLT0:
-                case NEON_2RM_AESE: case NEON_2RM_AESMC:
-                case NEON_2RM_SHA1H:
-                case NEON_2RM_SHA1SU1:
-                case NEON_2RM_VREV32:
-                case NEON_2RM_VREV16:
-                case NEON_2RM_VCLS:
-                case NEON_2RM_VCLZ:
-                case NEON_2RM_VCNT:
-                case NEON_2RM_VABS_F:
-                case NEON_2RM_VNEG_F:
-                case NEON_2RM_VRECPE:
-                case NEON_2RM_VRSQRTE:
-                case NEON_2RM_VQABS:
-                case NEON_2RM_VQNEG:
-                case NEON_2RM_VRECPE_F:
-                case NEON_2RM_VRSQRTE_F:
-                case NEON_2RM_VCVT_FS:
-                case NEON_2RM_VCVT_FU:
-                case NEON_2RM_VCVT_SF:
-                case NEON_2RM_VCVT_UF:
-                case NEON_2RM_VRINTX:
-                case NEON_2RM_VCGT0_F:
-                case NEON_2RM_VCGE0_F:
-                case NEON_2RM_VCEQ0_F:
-                case NEON_2RM_VCLE0_F:
-                case NEON_2RM_VCLT0_F:
-                case NEON_2RM_VRINTN:
-                case NEON_2RM_VRINTA:
-                case NEON_2RM_VRINTM:
-                case NEON_2RM_VRINTP:
-                case NEON_2RM_VRINTZ:
-                case NEON_2RM_VCVTAU:
-                case NEON_2RM_VCVTAS:
-                case NEON_2RM_VCVTNU:
-                case NEON_2RM_VCVTNS:
-                case NEON_2RM_VCVTPU:
-                case NEON_2RM_VCVTPS:
-                case NEON_2RM_VCVTMU:
-                case NEON_2RM_VCVTMS:
-                case NEON_2RM_VSWP:
-                    /* handled by decodetree */
-                    return 1;
-                case NEON_2RM_VTRN:
-                    if (size == 2) {
-                        int n;
-                        for (n = 0; n < (q ? 4 : 2); n += 2) {
-                            tmp = neon_load_reg(rm, n);
-                            tmp2 = neon_load_reg(rd, n + 1);
-                            neon_store_reg(rm, n, tmp2);
-                            neon_store_reg(rd, n + 1, tmp);
-                        }
-                    } else {
-                        goto elementwise;
-                    }
-                    break;
-
-                default:
-                elementwise:
-                    for (pass = 0; pass < (q ? 4 : 2); pass++) {
-                        tmp = neon_load_reg(rm, pass);
-                        switch (op) {
-                        case NEON_2RM_VTRN:
-                            tmp2 = neon_load_reg(rd, pass);
-                            switch (size) {
-                            case 0: gen_neon_trn_u8(tmp, tmp2); break;
-                            case 1: gen_neon_trn_u16(tmp, tmp2); break;
-                            default: abort();
-                            }
-                            neon_store_reg(rm, pass, tmp2);
-                            break;
-                        default:
-                            /* Reserved op values were caught by the
-                             * neon_2rm_sizes[] check earlier.
-                             */
-                            abort();
-                        }
-                        neon_store_reg(rd, pass, tmp);
-                    }
-                    break;
-                }
-            } else {
-                /* VTBL, VTBX, VDUP: handled by decodetree */
-                return 1;
-            }
-        }
-    }
-    return 0;
-}
-
 static int disas_coproc_insn(DisasContext *s, uint32_t insn)
 {
     int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
         }
         /* fall back to legacy decoder */
 
-        if (((insn >> 25) & 7) == 1) {
-            /* NEON Data processing.  */
-            if (disas_neon_data_insn(s, insn)) {
-                goto illegal_op;
-            }
-            return;
-        }
         if ((insn & 0x0e000f00) == 0x0c000100) {
             if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
                 /* iWMMXt register transfer.  */
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
             break;
         }
         if (((insn >> 24) & 3) == 3) {
-            /* Translate into the equivalent ARM encoding.  */
-            insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
-            if (disas_neon_data_insn(s, insn)) {
-                goto illegal_op;
-            }
+            /* Neon DP, but failed disas_neon_dp() */
+            goto illegal_op;
         } else if (((insn >> 8) & 0xe) == 10) {
             /* VFP, but failed disas_vfp.  */
             goto illegal_op;
-- 
2.20.1

The functions neon_element_offset(), neon_load_element(),
neon_load_element64(), neon_store_element() and
neon_store_element64() are used only in the translate-neon.inc.c
file, so move their definitions there.

Since the .inc.c file is #included in translate.c this doesn't make
much difference currently, but it's a more logical place to put the
functions and it might be helpful if we ever decide to try to make
the .inc.c files genuinely separate compilation units.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-22-peter.maydell@linaro.org
---
 target/arm/translate-neon.inc.c | 101 ++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 101 --------------------------------
 2 files changed, 101 insertions(+), 101 deletions(-)

diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static inline int rsub_8(DisasContext *s, int x)
 #include "decode-neon-ls.inc.c"
 #include "decode-neon-shared.inc.c"
 
+/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
+ * where 0 is the least significant end of the register.
+ */
+static inline long
+neon_element_offset(int reg, int element, MemOp size)
+{
+    int element_size = 1 << size;
+    int ofs = element * element_size;
+#ifdef HOST_WORDS_BIGENDIAN
+    /* Calculate the offset assuming fully little-endian,
+     * then XOR to account for the order of the 8-byte units.
+     */
+    if (element_size < 8) {
+        ofs ^= 8 - element_size;
+    }
+#endif
+    return neon_reg_offset(reg, 0) + ofs;
+}
+
+static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
+{
+    long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
+
+    switch (mop) {
+    case MO_UB:
+        tcg_gen_ld8u_i32(var, cpu_env, offset);
+        break;
+    case MO_UW:
+        tcg_gen_ld16u_i32(var, cpu_env, offset);
+        break;
+    case MO_UL:
+        tcg_gen_ld_i32(var, cpu_env, offset);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop)
+{
+    long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
+
+    switch (mop) {
+    case MO_UB:
+        tcg_gen_ld8u_i64(var, cpu_env, offset);
+        break;
+    case MO_UW:
+        tcg_gen_ld16u_i64(var, cpu_env, offset);
+        break;
+    case MO_UL:
+        tcg_gen_ld32u_i64(var, cpu_env, offset);
+        break;
+    case MO_Q:
+        tcg_gen_ld_i64(var, cpu_env, offset);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var)
+{
+    long offset = neon_element_offset(reg, ele, size);
+
+    switch (size) {
+    case MO_8:
+        tcg_gen_st8_i32(var, cpu_env, offset);
+        break;
+    case MO_16:
+        tcg_gen_st16_i32(var, cpu_env, offset);
+        break;
+    case MO_32:
+        tcg_gen_st_i32(var, cpu_env, offset);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var)
+{
+    long offset = neon_element_offset(reg, ele, size);
+
+    switch (size) {
+    case MO_8:
+        tcg_gen_st8_i64(var, cpu_env, offset);
+        break;
+    case MO_16:
+        tcg_gen_st16_i64(var, cpu_env, offset);
+        break;
+    case MO_32:
+        tcg_gen_st32_i64(var, cpu_env, offset);
+        break;
+    case MO_64:
+        tcg_gen_st_i64(var, cpu_env, offset);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
 static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
 {
     int opr_sz;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ neon_reg_offset (int reg, int n)
     return vfp_reg_offset(0, sreg);
 }
 
-/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
- * where 0 is the least significant end of the register.
- */
-static inline long
-neon_element_offset(int reg, int element, MemOp size)
-{
-    int element_size = 1 << size;
-    int ofs = element * element_size;
-#ifdef HOST_WORDS_BIGENDIAN
-    /* Calculate the offset assuming fully little-endian,
-     * then XOR to account for the order of the 8-byte units.
-     */
-    if (element_size < 8) {
-        ofs ^= 8 - element_size;
-    }
-#endif
-    return neon_reg_offset(reg, 0) + ofs;
-}
-
 static TCGv_i32 neon_load_reg(int reg, int pass)
 {
     TCGv_i32 tmp = tcg_temp_new_i32();
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 neon_load_reg(int reg, int pass)
     return tmp;
 }
 
-static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
-{
-    long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
-
-    switch (mop) {
-    case MO_UB:
-        tcg_gen_ld8u_i32(var, cpu_env, offset);
-        break;
-    case MO_UW:
-        tcg_gen_ld16u_i32(var, cpu_env, offset);
-        break;
-    case MO_UL:
-        tcg_gen_ld_i32(var, cpu_env, offset);
-        break;
-    default:
-        g_assert_not_reached();
-    }
-}
-
-static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop)
-{
-    long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
-
-    switch (mop) {
-    case MO_UB:
-        tcg_gen_ld8u_i64(var, cpu_env, offset);
-        break;
-    case MO_UW:
-        tcg_gen_ld16u_i64(var, cpu_env, offset);
-        break;
-    case MO_UL:
-        tcg_gen_ld32u_i64(var, cpu_env, offset);
-        break;
-    case MO_Q:
-        tcg_gen_ld_i64(var, cpu_env, offset);
-        break;
-    default:
-        g_assert_not_reached();
-    }
-}
-
 static void neon_store_reg(int reg, int pass, TCGv_i32 var)
 {
     tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
     tcg_temp_free_i32(var);
 }
 
-static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var)
-{
-    long offset = neon_element_offset(reg, ele, size);
-
-    switch (size) {
-    case MO_8:
-        tcg_gen_st8_i32(var, cpu_env, offset);
-        break;
-    case MO_16:
-        tcg_gen_st16_i32(var, cpu_env, offset);
-        break;
-    case MO_32:
-        tcg_gen_st_i32(var, cpu_env, offset);
-        break;
-    default:
-        g_assert_not_reached();
-    }
-}
-
-static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var)
-{
-    long offset = neon_element_offset(reg, ele, size);
-
-    switch (size) {
-    case MO_8:
-        tcg_gen_st8_i64(var, cpu_env, offset);
-        break;
-    case MO_16:
-        tcg_gen_st16_i64(var, cpu_env, offset);
-        break;
-    case MO_32:
-        tcg_gen_st32_i64(var, cpu_env, offset);
-        break;
-    case MO_64:
-        tcg_gen_st_i64(var, cpu_env, offset);
-        break;
-    default:
-        g_assert_not_reached();
-    }
-}
-
 static inline void neon_load_reg64(TCGv_i64 var, int reg)
 {
     tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
-- 
2.20.1

Since commit ba3e7926691ed3 it has been unnecessary for target code
to call gen_io_end() after an IO instruction in icount mode; it is
sufficient to call gen_io_start() before it and to force the end of
the TB.

Many now-unnecessary calls to gen_io_end() were removed in commit
9e9b10c6491153b, but some were missed or accidentally added later.
Remove unneeded calls from the arm target:

* the call in the handling of exception-return-via-LDM is
   unnecessary, and the code is already forcing end-of-TB
 * the call in the VFP access check code is more complicated:
   we weren't ending the TB, so we need to add the code to
   force that by setting DISAS_UPDATE
 * the doc comment for ARM_CP_IO doesn't need to mention
   gen_io_end() any more

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru>
Message-id: 20200619170324.12093-1-peter.maydell@linaro.org
---
 target/arm/cpu.h               | 2 +-
 target/arm/translate-vfp.inc.c | 7 +++----
 target/arm/translate.c         | 3 ---
 3 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
  * migration or KVM state synchronization. (Typically this is for "registers"
  * which are actually used as instructions for cache maintenance and so on.)
  * IO indicates that this register does I/O and therefore its accesses
- * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
+ * need to be marked with gen_io_start() and also end the TB. In particular,
  * registers which implement clocks or timers require this.
  * RAISES_EXC is for when the read or write hook might raise an exception;
  * the generated code will synchronize the CPU state before calling the hook
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
         if (s->v7m_lspact) {
             /*
              * Lazy state saving affects external memory and also the NVIC,
-             * so we must mark it as an IO operation for icount.
+             * so we must mark it as an IO operation for icount (and cause
+             * this to be the last insn in the TB).
              */
             if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+                s->base.is_jmp = DISAS_UPDATE;
                 gen_io_start();
             }
             gen_helper_v7m_preserve_fp_state(cpu_env);
-            if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
-                gen_io_end();
-            }
             /*
              * If the preserve_fp_state helper doesn't throw an exception
              * then it will clear LSPACT; we don't need to repeat this for
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
             gen_io_start();
         }
         gen_helper_cpsr_write_eret(cpu_env, tmp);
-        if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
-            gen_io_end();
-        }
         tcg_temp_free_i32(tmp);
         /* Must exit loop to check un-masked IRQs */
         s->base.is_jmp = DISAS_EXIT;
-- 
2.20.1

In commit cfdb2c0c95ae9205b0 ("target/arm: Vectorize SABA/UABA") we
replaced the old handling of SABA/UABA with a vectorized implementation
which returns early rather than falling into the loop-ever-elements
code. We forgot to delete the part of the old looping code that
did the accumulate step, and Coverity correctly warns (CID 1428955)
that this code is now dead. Delete it.

Fixes: cfdb2c0c95ae9205b0
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200619171547.29780-1-peter.maydell@linaro.org
---
 target/arm/translate-a64.c | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
                 genfn(tcg_res, tcg_op1, tcg_op2);
             }
 
-            if (opcode == 0xf) {
-                /* SABA, UABA: accumulating ops */
-                static NeonGenTwoOpFn * const fns[3] = {
-                    gen_helper_neon_add_u8,
-                    gen_helper_neon_add_u16,
-                    tcg_gen_add_i32,
-                };
-
-                read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);
-                fns[size](tcg_res, tcg_op1, tcg_res);
-            }
-
             write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
 
             tcg_temp_free_i32(tcg_res);
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Add a trace event to see when a guest disable/enable the watchdog.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-2-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/watchdog/cmsdk-apb-watchdog.c | 1 +
 hw/watchdog/trace-events         | 1 +
 2 files changed, 2 insertions(+)

diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/watchdog/cmsdk-apb-watchdog.c
+++ b/hw/watchdog/cmsdk-apb-watchdog.c
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset,
         break;
     case A_WDOGLOCK:
         s->lock = (value != WDOG_UNLOCK_VALUE);
+        trace_cmsdk_apb_watchdog_lock(s->lock);
         break;
     case A_WDOGITCR:
         if (s->is_luminary) {
diff --git a/hw/watchdog/trace-events b/hw/watchdog/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/watchdog/trace-events
+++ b/hw/watchdog/trace-events
@@ -XXX,XX +XXX,XX @@
 cmsdk_apb_watchdog_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 cmsdk_apb_watchdog_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 cmsdk_apb_watchdog_reset(void) "CMSDK APB watchdog: reset"
+cmsdk_apb_watchdog_lock(uint32_t lock) "CMSDK APB watchdog: lock %" PRIu32
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Use self-explicit definitions instead of magic values.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-3-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/i2c/versatile_i2c.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/versatile_i2c.c
+++ b/hw/i2c/versatile_i2c.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "hw/sysbus.h"
 #include "hw/i2c/bitbang_i2c.h"
+#include "hw/registerfields.h"
 #include "qemu/log.h"
 #include "qemu/module.h"
 
@@ -XXX,XX +XXX,XX @@ typedef struct VersatileI2CState {
     int in;
 } VersatileI2CState;
 
+REG32(CONTROL_GET, 0)
+REG32(CONTROL_SET, 0)
+REG32(CONTROL_CLR, 4)
+
 static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
                                    unsigned size)
 {
     VersatileI2CState *s = (VersatileI2CState *)opaque;
 
-    if (offset == 0) {
+    switch (offset) {
+    case A_CONTROL_SET:
         return (s->out & 1) | (s->in << 1);
-    } else {
+    default:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: Bad offset 0x%x\n", __func__, (int)offset);
         return -1;
@@ -XXX,XX +XXX,XX @@ static void versatile_i2c_write(void *opaque, hwaddr offset,
     VersatileI2CState *s = (VersatileI2CState *)opaque;
 
     switch (offset) {
-    case 0:
+    case A_CONTROL_SET:
         s->out |= value & 3;
         break;
-    case 4:
+    case A_CONTROL_CLR:
         s->out &= ~value;
         break;
     default:
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Use self-explicit definitions instead of magic values.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-4-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/i2c/versatile_i2c.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/versatile_i2c.c
+++ b/hw/i2c/versatile_i2c.c
@@ -XXX,XX +XXX,XX @@ REG32(CONTROL_GET, 0)
 REG32(CONTROL_SET, 0)
 REG32(CONTROL_CLR, 4)
 
+#define SCL BIT(0)
+#define SDA BIT(1)
+
 static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
                                    unsigned size)
 {
@@ -XXX,XX +XXX,XX @@ static void versatile_i2c_write(void *opaque, hwaddr offset,
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: Bad offset 0x%x\n", __func__, (int)offset);
     }
-    bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0);
-    s->in = bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0);
+    bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SCL, (s->out & SCL) != 0);
+    s->in = bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SDA, (s->out & SDA) != 0);
 }
 
 static const MemoryRegionOps versatile_i2c_ops = {
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

'ARM SBCon two-wire serial bus interface' is the official
name describing the pair of registers used to bitbanging
I2C in the Versatile boards.

Make the private VersatileI2CState structure as public
ArmSbconI2CState.
Add the TYPE_ARM_SBCON_I2C, alias to our current
TYPE_VERSATILE_I2C model.
Rename the memory region description as 'arm_sbcon_i2c'.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-5-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/i2c/arm_sbcon_i2c.h | 35 ++++++++++++++++++++++++++++++++++
 hw/i2c/versatile_i2c.c         | 17 +++++------------
 MAINTAINERS                    |  1 +
 3 files changed, 41 insertions(+), 12 deletions(-)
 create mode 100644 include/hw/i2c/arm_sbcon_i2c.h

diff --git a/include/hw/i2c/arm_sbcon_i2c.h b/include/hw/i2c/arm_sbcon_i2c.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/i2c/arm_sbcon_i2c.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * ARM SBCon two-wire serial bus interface (I2C bitbang)
+ *   a.k.a.
+ * ARM Versatile I2C controller
+ *
+ * Copyright (c) 2006-2007 CodeSourcery.
+ * Copyright (c) 2012 Oskar Andero <oskar.andero@gmail.com>
+ * Copyright (C) 2020 Philippe Mathieu-Daudé <f4bug@amsat.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef HW_I2C_ARM_SBCON_H
+#define HW_I2C_ARM_SBCON_H
+
+#include "hw/sysbus.h"
+#include "hw/i2c/bitbang_i2c.h"
+
+#define TYPE_VERSATILE_I2C "versatile_i2c"
+#define TYPE_ARM_SBCON_I2C TYPE_VERSATILE_I2C
+
+#define ARM_SBCON_I2C(obj) \
+    OBJECT_CHECK(ArmSbconI2CState, (obj), TYPE_ARM_SBCON_I2C)
+
+typedef struct ArmSbconI2CState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+    /*< public >*/
+
+    MemoryRegion iomem;
+    bitbang_i2c_interface bitbang;
+    int out;
+    int in;
+} ArmSbconI2CState;
+
+#endif /* HW_I2C_ARM_SBCON_H */
diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/versatile_i2c.c
+++ b/hw/i2c/versatile_i2c.c
@@ -XXX,XX +XXX,XX @@
 /*
- * ARM Versatile I2C controller
+ * ARM SBCon two-wire serial bus interface (I2C bitbang)
+ * a.k.a. ARM Versatile I2C controller
  *
  * Copyright (c) 2006-2007 CodeSourcery.
  * Copyright (c) 2012 Oskar Andero <oskar.andero@gmail.com>
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
-#include "hw/sysbus.h"
-#include "hw/i2c/bitbang_i2c.h"
+#include "hw/i2c/arm_sbcon_i2c.h"
 #include "hw/registerfields.h"
 #include "qemu/log.h"
 #include "qemu/module.h"
 
-#define TYPE_VERSATILE_I2C "versatile_i2c"
 #define VERSATILE_I2C(obj) \
     OBJECT_CHECK(VersatileI2CState, (obj), TYPE_VERSATILE_I2C)
 
-typedef struct VersatileI2CState {
-    SysBusDevice parent_obj;
+typedef ArmSbconI2CState VersatileI2CState;
 
-    MemoryRegion iomem;
-    bitbang_i2c_interface bitbang;
-    int out;
-    int in;
-} VersatileI2CState;
 
 REG32(CONTROL_GET, 0)
 REG32(CONTROL_SET, 0)
@@ -XXX,XX +XXX,XX @@ static void versatile_i2c_init(Object *obj)
     bus = i2c_init_bus(dev, "i2c");
     bitbang_i2c_init(&s->bitbang, bus);
     memory_region_init_io(&s->iomem, obj, &versatile_i2c_ops, s,
-                          "versatile_i2c", 0x1000);
+                          "arm_sbcon_i2c", 0x1000);
     sysbus_init_mmio(sbd, &s->iomem);
 }
 
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/*/versatile*
+F: include/hw/i2c/arm_sbcon_i2c.h
 F: hw/misc/arm_sysctl.c
 F: docs/system/arm/versatile.rst
 
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

By using the TYPE_* definitions for devices, we can:
 - quickly find where devices are used with 'git-grep'
 - easily rename a device (one-line change).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-6-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/realview.c    | 3 ++-
 hw/arm/versatilepb.c | 3 ++-
 hw/arm/vexpress.c    | 3 ++-
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/cpu/a9mpcore.h"
 #include "hw/intc/realview_gic.h"
 #include "hw/irq.h"
+#include "hw/i2c/arm_sbcon_i2c.h"
 
 #define SMP_BOOT_ADDR 0xe0000000
 #define SMP_BOOTREG_ADDR 0x10000030
@@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine,
         }
     }
 
-    dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
+    dev = sysbus_create_simple(TYPE_VERSATILE_I2C, 0x10002000, NULL);
     i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
     i2c_create_slave(i2c, "ds1338", 0x68);
 
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/sysemu.h"
 #include "hw/pci/pci.h"
 #include "hw/i2c/i2c.h"
+#include "hw/i2c/arm_sbcon_i2c.h"
 #include "hw/irq.h"
 #include "hw/boards.h"
 #include "exec/address-spaces.h"
@@ -XXX,XX +XXX,XX @@ static void versatile_init(MachineState *machine, int board_id)
     /* Add PL031 Real Time Clock. */
     sysbus_create_simple("pl031", 0x101e8000, pic[10]);
 
-    dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
+    dev = sysbus_create_simple(TYPE_VERSATILE_I2C, 0x10002000, NULL);
     i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
     i2c_create_slave(i2c, "ds1338", 0x68);
 
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/char/pl011.h"
 #include "hw/cpu/a9mpcore.h"
 #include "hw/cpu/a15mpcore.h"
+#include "hw/i2c/arm_sbcon_i2c.h"
 
 #define VEXPRESS_BOARD_ID 0x8e0
 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
 
-    dev = sysbus_create_simple("versatile_i2c", map[VE_SERIALDVI], NULL);
+    dev = sysbus_create_simple(TYPE_VERSATILE_I2C, map[VE_SERIALDVI], NULL);
     i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
     i2c_create_slave(i2c, "sii9022", 0x39);
 
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-7-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/mps2.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
     MemoryRegion blockram_m2;
     MemoryRegion blockram_m3;
     MemoryRegion sram;
+    /* FPGA APB subsystem */
     MPS2SCC scc;
+    /* CMSDK APB subsystem */
     CMSDKAPBDualTimer dualtimer;
 } MPS2MachineState;
 
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
         g_assert_not_reached();
     }
 
+    /* CMSDK APB subsystem */
     cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
     cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ);
-
     object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
                             TYPE_CMSDK_APB_DUALTIMER);
     qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
                        qdev_get_gpio_in(armv7m, 10));
     sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
 
+    /* FPGA APB subsystem */
     object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
     sccdev = DEVICE(&mms->scc);
     qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

To differenciate with the CMSDK APB peripheral region,
rename this region 'CMSDK AHB peripheral region'.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-8-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/mps2.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
      */
     create_unimplemented_device("CMSDK APB peripheral region @0x40000000",
                                 0x40000000, 0x00010000);
-    create_unimplemented_device("CMSDK peripheral region @0x40010000",
+    create_unimplemented_device("CMSDK AHB peripheral region @0x40010000",
                                 0x40010000, 0x00010000);
     create_unimplemented_device("Extra peripheral region @0x40020000",
                                 0x40020000, 0x00010000);
+
     create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000);
     create_unimplemented_device("VGA", 0x41000000, 0x0200000);
 
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

We already model the CMSDK APB watchdog device, let's use it!

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-9-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/mps2.c  | 7 +++++++
 hw/arm/Kconfig | 1 +
 2 files changed, 8 insertions(+)

diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
     sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
                        qdev_get_gpio_in(armv7m, 10));
     sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
+    object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
+                            TYPE_CMSDK_APB_WATCHDOG);
+    qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ);
+    sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
+                       qdev_get_gpio_in_named(armv7m, "NMI", 0));
+    sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0x40008000);
 
     /* FPGA APB subsystem */
     object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config MPS2
     select PL080    # DMA controller
     select SPLIT_IRQ
     select UNIMP
+    select CMSDK_APB_WATCHDOG
 
 config FSL_IMX7
     bool
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

----------------
  IN: arm_mps2_pinmux_init
  0x00001160:  f64f 0231  movw     r2, #0xf831
  0x00001164:  4b06       ldr      r3, [pc, #0x18]
  0x00001166:  2000       movs     r0, #0
  0x00001168:  619a       str      r2, [r3, #0x18]
  0x0000116a:  f24c 426f  movw     r2, #0xc46f
  0x0000116e:  f503 5380  add.w    r3, r3, #0x1000
  0x00001172:  619a       str      r2, [r3, #0x18]
  0x00001174:  f44f 529e  mov.w    r2, #0x13c0
  0x00001178:  f503 5380  add.w    r3, r3, #0x1000
  0x0000117c:  619a       str      r2, [r3, #0x18]
  0x0000117e:  4770       bx       lr
  cmsdk-ahb-gpio: unimplemented device write (size 4, value 0xf831, offset 0x18)
  cmsdk-ahb-gpio: unimplemented device write (size 4, value 0xc46f, offset 0x18)
  cmsdk-ahb-gpio: unimplemented device write (size 4, value 0x13c0, offset 0x18)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-10-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/mps2.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
     MemoryRegion *system_memory = get_system_memory();
     MachineClass *mc = MACHINE_GET_CLASS(machine);
     DeviceState *armv7m, *sccdev;
+    int i;
 
     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
         error_report("This board can only be used with CPU %s",
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
          */
         Object *orgate;
         DeviceState *orgate_dev;
-        int i;
 
         orgate = object_new(TYPE_OR_IRQ);
         object_property_set_int(orgate, 6, "num-lines", &error_fatal);
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
          */
         Object *orgate;
         DeviceState *orgate_dev;
-        int i;
 
         orgate = object_new(TYPE_OR_IRQ);
         object_property_set_int(orgate, 10, "num-lines", &error_fatal);
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
     default:
         g_assert_not_reached();
     }
+    for (i = 0; i < 4; i++) {
+        static const hwaddr gpiobase[] = {0x40010000, 0x40011000,
+                                          0x40012000, 0x40013000};
+        create_unimplemented_device("cmsdk-ahb-gpio", gpiobase[i], 0x1000);
+    }
 
     /* CMSDK APB subsystem */
     cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-11-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/mps2.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/timer/cmsdk-apb-timer.h"
 #include "hw/timer/cmsdk-apb-dualtimer.h"
 #include "hw/misc/mps2-scc.h"
+#include "hw/misc/mps2-fpgaio.h"
 #include "hw/net/lan9118.h"
 #include "net/net.h"
+#include "hw/watchdog/cmsdk-apb-watchdog.h"
 
 typedef enum MPS2FPGAType {
     FPGA_AN385,
@@ -XXX,XX +XXX,XX @@ typedef struct {
     MemoryRegion sram;
     /* FPGA APB subsystem */
     MPS2SCC scc;
+    MPS2FPGAIO fpgaio;
     /* CMSDK APB subsystem */
     CMSDKAPBDualTimer dualtimer;
+    CMSDKAPBWatchdog watchdog;
 } MPS2MachineState;
 
 #define TYPE_MPS2_MACHINE "mps2"
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
     qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
     sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000);
+    object_initialize_child(OBJECT(mms), "fpgaio",
+                            &mms->fpgaio, TYPE_MPS2_FPGAIO);
+    qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", 25000000);
+    sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0x40028000);
 
     /* In hardware this is a LAN9220; the LAN9118 is software compatible
      * except that it doesn't support the checksum-offload feature.
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

From 'Application Note AN385', chapter 3.9, SPI:

The SMM implements five PL022 SPI modules.

Two pairs of modules share the same OR-gated IRQ.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-12-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/mps2.c  | 24 ++++++++++++++++++++++++
 hw/arm/Kconfig |  6 +++---
 2 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/timer/cmsdk-apb-dualtimer.h"
 #include "hw/misc/mps2-scc.h"
 #include "hw/misc/mps2-fpgaio.h"
+#include "hw/ssi/pl022.h"
 #include "hw/net/lan9118.h"
 #include "net/net.h"
 #include "hw/watchdog/cmsdk-apb-watchdog.h"
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
     qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", 25000000);
     sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0x40028000);
+    sysbus_create_simple(TYPE_PL022, 0x40025000,        /* External ADC */
+                         qdev_get_gpio_in(armv7m, 22));
+    for (i = 0; i < 2; i++) {
+        static const int spi_irqno[] = {11, 24};
+        static const hwaddr spibase[] = {0x40020000,    /* APB */
+                                         0x40021000,    /* LCD */
+                                         0x40026000,    /* Shield0 */
+                                         0x40027000};   /* Shield1 */
+        DeviceState *orgate_dev;
+        Object *orgate;
+        int j;
+
+        orgate = object_new(TYPE_OR_IRQ);
+        object_property_set_int(orgate, 2, "num-lines", &error_fatal);
+        orgate_dev = DEVICE(orgate);
+        qdev_realize(orgate_dev, NULL, &error_fatal);
+        qdev_connect_gpio_out(orgate_dev, 0,
+                              qdev_get_gpio_in(armv7m, spi_irqno[i]));
+        for (j = 0; j < 2; j++) {
+            sysbus_create_simple(TYPE_PL022, spibase[2 * i + j],
+                                 qdev_get_gpio_in(orgate_dev, j));
+        }
+    }
 
     /* In hardware this is a LAN9220; the LAN9118 is software compatible
      * except that it doesn't support the checksum-offload feature.
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config HIGHBANK
     select ARM_TIMER # sp804
     select ARM_V7M
     select PL011 # UART
-    select PL022 # Serial port
+    select PL022 # SPI
     select PL031 # RTC
     select PL061 # GPIO
     select PL310 # cache controller
@@ -XXX,XX +XXX,XX @@ config STELLARIS
     select CMSDK_APB_WATCHDOG
     select I2C
     select PL011 # UART
-    select PL022 # Serial port
+    select PL022 # SPI
     select PL061 # GPIO
     select SSD0303 # OLED display
     select SSD0323 # OLED display
@@ -XXX,XX +XXX,XX @@ config MPS2
     select MPS2_FPGAIO
     select MPS2_SCC
     select OR_IRQ
-    select PL022    # Serial port
+    select PL022    # SPI
     select PL080    # DMA controller
     select SPLIT_IRQ
     select UNIMP
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

From 'Application Note AN385', chapter 3.14:

The SMM implements a simple SBCon interface based on I2C.

There are 4 SBCon interfaces on the FPGA APB subsystem.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-13-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/mps2.c  | 8 ++++++++
 hw/arm/Kconfig | 1 +
 2 files changed, 9 insertions(+)

diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/mps2-scc.h"
 #include "hw/misc/mps2-fpgaio.h"
 #include "hw/ssi/pl022.h"
+#include "hw/i2c/arm_sbcon_i2c.h"
 #include "hw/net/lan9118.h"
 #include "net/net.h"
 #include "hw/watchdog/cmsdk-apb-watchdog.h"
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
                                  qdev_get_gpio_in(orgate_dev, j));
         }
     }
+    for (i = 0; i < 4; i++) {
+        static const hwaddr i2cbase[] = {0x40022000,    /* Touch */
+                                         0x40023000,    /* Audio */
+                                         0x40029000,    /* Shield0 */
+                                         0x4002a000};   /* Shield1 */
+        sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL);
+    }
 
     /* In hardware this is a LAN9220; the LAN9118 is software compatible
      * except that it doesn't support the checksum-offload feature.
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config MPS2
     select SPLIT_IRQ
     select UNIMP
     select CMSDK_APB_WATCHDOG
+    select VERSATILE_I2C
 
 config FSL_IMX7
     bool
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

From 'Application Note AN521', chapter 4.7:

The SMM implements four SBCon serial modules:

One SBCon module for use by the Color LCD touch interface.
  One SBCon module to configure the audio controller.
  Two general purpose SBCon modules, that connect to the
  Expansion headers J7 and J8, are intended for use with the
  V2C-Shield1 which provide an I2C interface on the headers.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-15-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/mps2-tz.c | 23 ++++++++++++++++++-----
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/armsse.h"
 #include "hw/dma/pl080.h"
 #include "hw/ssi/pl022.h"
+#include "hw/i2c/arm_sbcon_i2c.h"
 #include "hw/net/lan9118.h"
 #include "net/net.h"
 #include "hw/core/split-irq.h"
@@ -XXX,XX +XXX,XX @@ typedef struct {
     TZPPC ppc[5];
     TZMPC ssram_mpc[3];
     PL022State spi[5];
-    UnimplementedDeviceState i2c[4];
+    ArmSbconI2CState i2c[4];
     UnimplementedDeviceState i2s_audio;
     UnimplementedDeviceState gpio[4];
     UnimplementedDeviceState gfx;
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque,
     return sysbus_mmio_get_region(s, 0);
 }
 
+static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque,
+                              const char *name, hwaddr size)
+{
+    ArmSbconI2CState *i2c = opaque;
+    SysBusDevice *s;
+
+    object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C);
+    s = SYS_BUS_DEVICE(i2c);
+    sysbus_realize(s, &error_fatal);
+    return sysbus_mmio_get_region(s, 0);
+}
+
 static void mps2tz_common_init(MachineState *machine)
 {
     MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine);
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
                 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 },
                 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 },
                 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 },
-                { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 },
-                { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 },
-                { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 },
-                { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 },
+                { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 },
+                { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 },
+                { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 },
+                { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000 },
             },
         }, {
             .name = "apb_ppcexp2",
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

Since commit d70c996df23f, when enabling the PMU we get:

$ qemu-system-aarch64 -cpu host,pmu=on -M virt,accel=kvm,gic-version=3
  Segmentation fault (core dumped)

Thread 1 "qemu-system-aar" received signal SIGSEGV, Segmentation fault.
  0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at accel/kvm/kvm-all.c:2588
  2588        ret = ioctl(s->fd, type, arg);
  (gdb) bt
  #0  0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at accel/kvm/kvm-all.c:2588
  #1  0x0000aaaaaae31568 in kvm_check_extension (s=0x0, extension=126) at accel/kvm/kvm-all.c:916
  #2  0x0000aaaaaafce254 in kvm_arm_pmu_supported (cpu=0xaaaaac214ab0) at target/arm/kvm.c:213
  #3  0x0000aaaaaafc0f94 in arm_set_pmu (obj=0xaaaaac214ab0, value=true, errp=0xffffffffe438) at target/arm/cpu.c:1111
  #4  0x0000aaaaab5533ac in property_set_bool (obj=0xaaaaac214ab0, v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", opaque=0xaaaaac222730, errp=0xffffffffe438) at qom/object.c:2170
  #5  0x0000aaaaab5512f0 in object_property_set (obj=0xaaaaac214ab0, v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at qom/object.c:1328
  #6  0x0000aaaaab551e10 in object_property_parse (obj=0xaaaaac214ab0, string=0xaaaaac11b4c0 "on", name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at qom/object.c:1561
  #7  0x0000aaaaab54ee8c in object_apply_global_props (obj=0xaaaaac214ab0, props=0xaaaaac018e20, errp=0xaaaaabd6fd88 <error_fatal>) at qom/object.c:407
  #8  0x0000aaaaab1dd5a4 in qdev_prop_set_globals (dev=0xaaaaac214ab0) at hw/core/qdev-properties.c:1218
  #9  0x0000aaaaab1d9fac in device_post_init (obj=0xaaaaac214ab0) at hw/core/qdev.c:1050
  ...
  #15 0x0000aaaaab54f310 in object_initialize_with_type (obj=0xaaaaac214ab0, size=52208, type=0xaaaaabe237f0) at qom/object.c:512
  #16 0x0000aaaaab54fa24 in object_new_with_type (type=0xaaaaabe237f0) at qom/object.c:687
  #17 0x0000aaaaab54fa80 in object_new (typename=0xaaaaabe23970 "host-arm-cpu") at qom/object.c:702
  #18 0x0000aaaaaaf04a74 in machvirt_init (machine=0xaaaaac0a8550) at hw/arm/virt.c:1770
  #19 0x0000aaaaab1e8720 in machine_run_board_init (machine=0xaaaaac0a8550) at hw/core/machine.c:1138
  #20 0x0000aaaaaaf95394 in qemu_init (argc=5, argv=0xffffffffea58, envp=0xffffffffea88) at softmmu/vl.c:4348
  #21 0x0000aaaaaada3f74 in main (argc=<optimized out>, argv=<optimized out>, envp=<optimized out>) at softmmu/main.c:48

This is because in frame #2, cpu->kvm_state is still NULL
(the vCPU is not yet realized).

KVM has a hard requirement of all cores supporting the same
feature set. We only need to check if the accelerator supports
a feature, not each vCPU individually.

Fix by removing the 'CPUState *cpu' argument from the
kvm_arm_<FEATURE>_supported() functions.

Fixes: d70c996df23f ('Use CPUState::kvm_state in kvm_arm_pmu_supported')
Reported-by: Haibo Xu <haibo.xu@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm_arm.h | 21 +++++++++------------
 target/arm/cpu.c     |  2 +-
 target/arm/cpu64.c   | 10 +++++-----
 target/arm/kvm.c     |  4 ++--
 target/arm/kvm64.c   | 14 +++++---------
 5 files changed, 22 insertions(+), 29 deletions(-)

diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@ void kvm_arm_add_vcpu_properties(Object *obj);
 
 /**
  * kvm_arm_aarch32_supported:
- * @cs: CPUState
  *
- * Returns: true if the KVM VCPU can enable AArch32 mode
+ * Returns: true if KVM can enable AArch32 mode
  * and false otherwise.
  */
-bool kvm_arm_aarch32_supported(CPUState *cs);
+bool kvm_arm_aarch32_supported(void);
 
 /**
  * kvm_arm_pmu_supported:
- * @cs: CPUState
  *
- * Returns: true if the KVM VCPU can enable its PMU
+ * Returns: true if KVM can enable the PMU
  * and false otherwise.
  */
-bool kvm_arm_pmu_supported(CPUState *cs);
+bool kvm_arm_pmu_supported(void);
 
 /**
  * kvm_arm_sve_supported:
- * @cs: CPUState
  *
- * Returns true if the KVM VCPU can enable SVE and false otherwise.
+ * Returns true if KVM can enable SVE and false otherwise.
  */
-bool kvm_arm_sve_supported(CPUState *cs);
+bool kvm_arm_sve_supported(void);
 
 /**
  * kvm_arm_get_max_vm_ipa_size:
@@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
 
 static inline void kvm_arm_add_vcpu_properties(Object *obj) {}
 
-static inline bool kvm_arm_aarch32_supported(CPUState *cs)
+static inline bool kvm_arm_aarch32_supported(void)
 {
     return false;
 }
 
-static inline bool kvm_arm_pmu_supported(CPUState *cs)
+static inline bool kvm_arm_pmu_supported(void)
 {
     return false;
 }
 
-static inline bool kvm_arm_sve_supported(CPUState *cs)
+static inline bool kvm_arm_sve_supported(void)
 {
     return false;
 }
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_set_pmu(Object *obj, bool value, Error **errp)
     ARMCPU *cpu = ARM_CPU(obj);
 
     if (value) {
-        if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu))) {
+        if (kvm_enabled() && !kvm_arm_pmu_supported()) {
             error_setg(errp, "'pmu' feature not supported by KVM on this host");
             return;
         }
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
 
     /* Collect the set of vector lengths supported by KVM. */
     bitmap_zero(kvm_supported, ARM_MAX_VQ);
-    if (kvm_enabled() && kvm_arm_sve_supported(CPU(cpu))) {
+    if (kvm_enabled() && kvm_arm_sve_supported()) {
         kvm_arm_sve_get_vls(CPU(cpu), kvm_supported);
     } else if (kvm_enabled()) {
         assert(!cpu_isar_feature(aa64_sve, cpu));
@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
         return;
     }
 
-    if (kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
+    if (kvm_enabled() && !kvm_arm_sve_supported()) {
         error_setg(errp, "cannot set sve-max-vq");
         error_append_hint(errp, "SVE not supported by KVM on this host\n");
         return;
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name,
         return;
     }
 
-    if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
+    if (value && kvm_enabled() && !kvm_arm_sve_supported()) {
         error_setg(errp, "cannot enable %s", name);
         error_append_hint(errp, "SVE not supported by KVM on this host\n");
         return;
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
         return;
     }
 
-    if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
+    if (value && kvm_enabled() && !kvm_arm_sve_supported()) {
         error_setg(errp, "'sve' feature not supported by KVM on this host");
         return;
     }
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
      * uniform execution state like do_interrupt.
      */
     if (value == false) {
-        if (!kvm_enabled() || !kvm_arm_aarch32_supported(CPU(cpu))) {
+        if (!kvm_enabled() || !kvm_arm_aarch32_supported()) {
             error_setg(errp, "'aarch64' feature cannot be disabled "
                              "unless KVM is enabled and 32-bit EL1 "
                              "is supported");
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ void kvm_arm_add_vcpu_properties(Object *obj)
     }
 }
 
-bool kvm_arm_pmu_supported(CPUState *cpu)
+bool kvm_arm_pmu_supported(void)
 {
-    return kvm_check_extension(cpu->kvm_state, KVM_CAP_ARM_PMU_V3);
+    return kvm_check_extension(kvm_state, KVM_CAP_ARM_PMU_V3);
 }
 
 int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
     return true;
 }
 
-bool kvm_arm_aarch32_supported(CPUState *cpu)
+bool kvm_arm_aarch32_supported(void)
 {
-    KVMState *s = KVM_STATE(current_accel());
-
-    return kvm_check_extension(s, KVM_CAP_ARM_EL1_32BIT);
+    return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT);
 }
 
-bool kvm_arm_sve_supported(CPUState *cpu)
+bool kvm_arm_sve_supported(void)
 {
-    KVMState *s = KVM_STATE(current_accel());
-
-    return kvm_check_extension(s, KVM_CAP_ARM_SVE);
+    return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE);
 }
 
 QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1);
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
         env->features &= ~(1ULL << ARM_FEATURE_PMU);
     }
     if (cpu_isar_feature(aa64_sve, cpu)) {
-        assert(kvm_arm_sve_supported(cs));
+        assert(kvm_arm_sve_supported());
         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE;
     }
 
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Some cpu features may be enabled and disabled for all configurations
that support the feature. Let's test that.

A recent regression[*] inspired adding these tests.

[*] '-cpu host,pmu=on' caused a segfault

Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200623090622.30365-2-philmd@redhat.com
Message-Id: <20200623082310.17577-1-drjones@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/arm-cpu-features.c | 38 ++++++++++++++++++++++++++++++----
 1 file changed, 34 insertions(+), 4 deletions(-)

diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static bool resp_get_feature(QDict *resp, const char *feature)
     qobject_unref(_resp);                                              \
 })
 
-#define assert_feature(qts, cpu_type, feature, expected_value)         \
+#define resp_assert_feature(resp, feature, expected_value)             \
 ({                                                                     \
-    QDict *_resp, *_props;                                             \
+    QDict *_props;                                                     \
                                                                        \
-    _resp = do_query_no_props(qts, cpu_type);                          \
     g_assert(_resp);                                                   \
     g_assert(resp_has_props(_resp));                                   \
     _props = resp_get_props(_resp);                                    \
     g_assert(qdict_get(_props, feature));                              \
     g_assert(qdict_get_bool(_props, feature) == (expected_value));     \
+})
+
+#define assert_feature(qts, cpu_type, feature, expected_value)         \
+({                                                                     \
+    QDict *_resp;                                                      \
+                                                                       \
+    _resp = do_query_no_props(qts, cpu_type);                          \
+    g_assert(_resp);                                                   \
+    resp_assert_feature(_resp, feature, expected_value);               \
+    qobject_unref(_resp);                                              \
+})
+
+#define assert_set_feature(qts, cpu_type, feature, value)              \
+({                                                                     \
+    const char *_fmt = (value) ? "{ %s: true }" : "{ %s: false }";     \
+    QDict *_resp;                                                      \
+                                                                       \
+    _resp = do_query(qts, cpu_type, _fmt, feature);                    \
+    g_assert(_resp);                                                   \
+    resp_assert_feature(_resp, feature, value);                        \
     qobject_unref(_resp);                                              \
 })
 
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
     assert_error(qts, "host", "The CPU type 'host' requires KVM", NULL);
 
     /* Test expected feature presence/absence for some cpu types */
-    assert_has_feature_enabled(qts, "max", "pmu");
     assert_has_feature_enabled(qts, "cortex-a15", "pmu");
     assert_has_not_feature(qts, "cortex-a15", "aarch64");
 
+    /* Enabling and disabling pmu should always work. */
+    assert_has_feature_enabled(qts, "max", "pmu");
+    assert_set_feature(qts, "max", "pmu", false);
+    assert_set_feature(qts, "max", "pmu", true);
+
     assert_has_not_feature(qts, "max", "kvm-no-adjvtime");
 
     if (g_str_equal(qtest_get_arch(), "aarch64")) {
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
         return;
     }
 
+    /* Enabling and disabling kvm-no-adjvtime should always work. */
     assert_has_feature_disabled(qts, "host", "kvm-no-adjvtime");
+    assert_set_feature(qts, "host", "kvm-no-adjvtime", true);
+    assert_set_feature(qts, "host", "kvm-no-adjvtime", false);
 
     if (g_str_equal(qtest_get_arch(), "aarch64")) {
         bool kvm_supports_sve;
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
         char *error;
 
         assert_has_feature_enabled(qts, "host", "aarch64");
+
+        /* Enabling and disabling pmu should always work. */
         assert_has_feature_enabled(qts, "host", "pmu");
+        assert_set_feature(qts, "host", "pmu", false);
+        assert_set_feature(qts, "host", "pmu", true);
 
         assert_error(qts, "cortex-a15",
             "We cannot guarantee the CPU type 'cortex-a15' works "
-- 
2.20.1

From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

This adds support for memory(pc-dimm) hot remove on arm/virt that
uses acpi ged device.

NVDIMM hot removal is not yet supported.

Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Message-id: 20200622124157.20360-1-shameerali.kolothum.thodi@huawei.com
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/acpi/generic_event_device.c | 29 ++++++++++++++++
 hw/arm/virt.c                  | 62 ++++++++++++++++++++++++++++++++--
 2 files changed, 89 insertions(+), 2 deletions(-)

diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/acpi/generic_event_device.c
+++ b/hw/acpi/generic_event_device.c
@@ -XXX,XX +XXX,XX @@ static void acpi_ged_device_plug_cb(HotplugHandler *hotplug_dev,
     }
 }
 
+static void acpi_ged_unplug_request_cb(HotplugHandler *hotplug_dev,
+                                       DeviceState *dev, Error **errp)
+{
+    AcpiGedState *s = ACPI_GED(hotplug_dev);
+
+    if ((object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) &&
+                       !(object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)))) {
+        acpi_memory_unplug_request_cb(hotplug_dev, &s->memhp_state, dev, errp);
+    } else {
+        error_setg(errp, "acpi: device unplug request for unsupported device"
+                   " type: %s", object_get_typename(OBJECT(dev)));
+    }
+}
+
+static void acpi_ged_unplug_cb(HotplugHandler *hotplug_dev,
+                               DeviceState *dev, Error **errp)
+{
+    AcpiGedState *s = ACPI_GED(hotplug_dev);
+
+    if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
+        acpi_memory_unplug_cb(&s->memhp_state, dev, errp);
+    } else {
+        error_setg(errp, "acpi: device unplug for unsupported device"
+                   " type: %s", object_get_typename(OBJECT(dev)));
+    }
+}
+
 static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
 {
     AcpiGedState *s = ACPI_GED(adev);
@@ -XXX,XX +XXX,XX @@ static void acpi_ged_class_init(ObjectClass *class, void *data)
     dc->vmsd = &vmstate_acpi_ged;
 
     hc->plug = acpi_ged_device_plug_cb;
+    hc->unplug_request = acpi_ged_unplug_request_cb;
+    hc->unplug = acpi_ged_unplug_cb;
 
     adevc->send_event = acpi_ged_send_event;
 }
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
     }
 }
 
+static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
+                                     DeviceState *dev, Error **errp)
+{
+    VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
+    Error *local_err = NULL;
+
+    if (!vms->acpi_dev) {
+        error_setg(&local_err,
+                   "memory hotplug is not enabled: missing acpi-ged device");
+        goto out;
+    }
+
+    if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
+        error_setg(&local_err,
+                   "nvdimm device hot unplug is not supported yet.");
+        goto out;
+    }
+
+    hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
+                                   &local_err);
+out:
+    error_propagate(errp, local_err);
+}
+
+static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
+                             DeviceState *dev, Error **errp)
+{
+    VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
+    Error *local_err = NULL;
+
+    hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
+    if (local_err) {
+        goto out;
+    }
+
+    pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
+    qdev_unrealize(dev);
+
+out:
+    error_propagate(errp, local_err);
+}
+
 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
                                           DeviceState *dev, Error **errp)
 {
-    error_setg(errp, "device unplug request for unsupported device"
-               " type: %s", object_get_typename(OBJECT(dev)));
+    if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
+        virt_dimm_unplug_request(hotplug_dev, dev, errp);
+    } else {
+        error_setg(errp, "device unplug request for unsupported device"
+                   " type: %s", object_get_typename(OBJECT(dev)));
+    }
+}
+
+static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
+                                          DeviceState *dev, Error **errp)
+{
+    if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
+        virt_dimm_unplug(hotplug_dev, dev, errp);
+    } else {
+        error_setg(errp, "virt: device unplug for unsupported device"
+                   " type: %s", object_get_typename(OBJECT(dev)));
+    }
 }
 
 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     hc->pre_plug = virt_machine_device_pre_plug_cb;
     hc->plug = virt_machine_device_plug_cb;
     hc->unplug_request = virt_machine_device_unplug_request_cb;
+    hc->unplug = virt_machine_device_unplug_cb;
     mc->numa_mem_supported = true;
     mc->nvdimm_supported = true;
     mc->auto_enable_numa_with_memhp = true;
-- 
2.20.1

Arm queue; some of the simpler stuff, things other have reviewed (thanks!), etc.

-- PMM

The following changes since commit 5d2f557b47dfbf8f23277a5bdd8473d4607c681a:

Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200605-pull-request' into staging (2020-06-05 13:53:05 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200605

for you to fetch changes up to 2c35a39eda0b16c2ed85c94cec204bf5efb97812:

target/arm: Convert Neon one-register-and-immediate insns to decodetree (2020-06-05 17:23:10 +0100)

----------------------------------------------------------------
target-arm queue:
 hw/ssi/imx_spi: Handle tx burst lengths other than 8 correctly
 hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()
 hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()
 target/arm: Convert crypto insns to gvec
 hw/adc/stm32f2xx_adc: Correct memory region size and access size
 tests/acceptance: Add a boot test for the xlnx-versal-virt machine
 docs/system: Document Aspeed boards
 raspi: Add model of the USB controller
 target/arm: Convert 2-reg-and-shift and 1-reg-imm Neon insns to decodetree

----------------------------------------------------------------
Cédric Le Goater (1):
      docs/system: Document Aspeed boards

Eden Mikitas (2):
      hw/ssi/imx_spi: changed while statement to prevent underflow
      hw/ssi/imx_spi: Removed unnecessary cast of rx data received from slave

Paul Zimmerman (7):
      raspi: add BCM2835 SOC MPHI emulation
      dwc-hsotg (dwc2) USB host controller register definitions
      dwc-hsotg (dwc2) USB host controller state definitions
      dwc-hsotg (dwc2) USB host controller emulation
      usb: add short-packet handling to usb-storage driver
      wire in the dwc-hsotg (dwc2) USB host controller emulation
      raspi2 acceptance test: add test for dwc-hsotg (dwc2) USB host

Peter Maydell (9):
      target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree
      target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree
      target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree
      target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree
      target/arm: Convert Neon narrowing shifts with op==8 to decodetree
      target/arm: Convert Neon narrowing shifts with op==9 to decodetree
      target/arm: Convert Neon VSHLL, VMOVL to decodetree
      target/arm: Convert VCVT fixed-point ops to decodetree
      target/arm: Convert Neon one-register-and-immediate insns to decodetree

Philippe Mathieu-Daudé (3):
      hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()
      hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()
      hw/adc/stm32f2xx_adc: Correct memory region size and access size

Richard Henderson (6):
      target/arm: Convert aes and sm4 to gvec helpers
      target/arm: Convert rax1 to gvec helpers
      target/arm: Convert sha512 and sm3 to gvec helpers
      target/arm: Convert sha1 and sha256 to gvec helpers
      target/arm: Split helper_crypto_sha1_3reg
      target/arm: Split helper_crypto_sm3tt

Thomas Huth (1):
      tests/acceptance: Add a boot test for the xlnx-versal-virt machine

docs/system/arm/aspeed.rst             |   85 ++
 docs/system/target-arm.rst             |    1 +
 hw/usb/hcd-dwc2.h                      |  190 +++++
 include/hw/arm/bcm2835_peripherals.h   |    5 +-
 include/hw/misc/bcm2835_mphi.h         |   44 +
 include/hw/usb/dwc2-regs.h             |  899 ++++++++++++++++++++
 target/arm/helper.h                    |   45 +-
 target/arm/translate-a64.h             |    3 +
 target/arm/vec_internal.h              |   33 +
 target/arm/neon-dp.decode              |  214 ++++-
 hw/adc/stm32f2xx_adc.c                 |    4 +-
 hw/arm/bcm2835_peripherals.c           |   38 +-
 hw/arm/pxa2xx.c                        |   66 +-
 hw/input/pxa2xx_keypad.c               |   10 +-
 hw/misc/bcm2835_mphi.c                 |  191 +++++
 hw/ssi/imx_spi.c                       |    4 +-
 hw/usb/dev-storage.c                   |   15 +-
 hw/usb/hcd-dwc2.c                      | 1417 ++++++++++++++++++++++++++++++++
 target/arm/crypto_helper.c             |  267 ++++--
 target/arm/translate-a64.c             |  198 ++---
 target/arm/translate-neon.inc.c        |  796 ++++++++++++++----
 target/arm/translate.c                 |  539 +-----------
 target/arm/vec_helper.c                |   12 +-
 hw/misc/Makefile.objs                  |    1 +
 hw/usb/Kconfig                         |    5 +
 hw/usb/Makefile.objs                   |    1 +
 hw/usb/trace-events                    |   50 ++
 tests/acceptance/boot_linux_console.py |   35 +-
 28 files changed, 4258 insertions(+), 910 deletions(-)
 create mode 100644 docs/system/arm/aspeed.rst
 create mode 100644 hw/usb/hcd-dwc2.h
 create mode 100644 include/hw/misc/bcm2835_mphi.h
 create mode 100644 include/hw/usb/dwc2-regs.h
 create mode 100644 target/arm/vec_internal.h
 create mode 100644 hw/misc/bcm2835_mphi.c
 create mode 100644 hw/usb/hcd-dwc2.c

From: Eden Mikitas <e.mikitas@gmail.com>

When inserting the value retrieved (rx) from the spi slave, rx is pushed to
rx_fifo after being cast to uint8_t. rx_fifo is a fifo32, and the rx
register the driver uses is also 32 bit. This zeroes the 24 most
significant bits of rx. This proved problematic with devices that expect to
use the whole 32 bits of the rx register.

Signed-off-by: Eden Mikitas <e.mikitas@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/ssi/imx_spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
         if (fifo32_is_full(&s->rx_fifo)) {
             s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RO;
         } else {
-            fifo32_push(&s->rx_fifo, (uint8_t)rx);
+            fifo32_push(&s->rx_fifo, rx);
         }
 
         if (s->burst_length <= 0) {
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

hw_error() calls exit(). This a bit overkill when we can log
the accesses as unimplemented or guest error.

When fuzzing the devices, we don't want the whole process to
exit. Replace some hw_error() calls by qemu_log_mask()
(missed in commit 5a0001ec7e).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200525114123.21317-2-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/input/pxa2xx_keypad.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/input/pxa2xx_keypad.c b/hw/input/pxa2xx_keypad.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/input/pxa2xx_keypad.c
+++ b/hw/input/pxa2xx_keypad.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
-#include "hw/hw.h"
+#include "qemu/log.h"
 #include "hw/irq.h"
 #include "migration/vmstate.h"
 #include "hw/arm/pxa.h"
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_keypad_read(void *opaque, hwaddr offset,
         return s->kpkdi;
         break;
     default:
-        hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+                      __func__, offset);
     }
 
     return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_keypad_write(void *opaque, hwaddr offset,
         break;
 
     default:
-        hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+                      __func__, offset);
     }
 }
 
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Replace printf() calls by qemu_log_mask(), which is disabled
by default. This avoid flooding the terminal when fuzzing the
device.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200525114123.21317-3-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/pxa2xx.c | 66 ++++++++++++++++++++++++++++++++++++-------------
 1 file changed, 49 insertions(+), 17 deletions(-)

diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/blockdev.h"
 #include "sysemu/qtest.h"
 #include "qemu/cutils.h"
+#include "qemu/log.h"
 
 static struct {
     hwaddr io_base;
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
         return s->pm_regs[addr >> 2];
     default:
     fail:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_pm_write(void *opaque, hwaddr addr,
             s->pm_regs[addr >> 2] = value;
             break;
         }
-
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
         return s->cm_regs[CCCR >> 2] | (3 << 28);
 
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_cm_write(void *opaque, hwaddr addr,
         break;
 
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
             return s->mm_regs[addr >> 2];
         /* fall through */
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_mm_write(void *opaque, hwaddr addr,
         }
 
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
     case SSACD:
         return s->ssacd;
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
         break;
 
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
         else
             return s->last_swcr;
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
         break;
 
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
             s->ibmr = 0;
         return s->ibmr;
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
         break;
 
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
         }
         return 0;
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
         }
         break;
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
     case ICFOR:
         return s->rx_len;
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_fir_write(void *opaque, hwaddr addr,
     case ICFOR:
         break;
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
     }
 }
 
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

With this conversion, we will be able to use the same helpers
with sve.  In particular, pass 3 vector parameters for the
3-operand operations; for advsimd the destination register
is also an input.

This also fixes a bug in which we failed to clear the high bits
of the SVE register after an AdvSIMD operation.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h        |  6 ++--
 target/arm/vec_internal.h  | 33 +++++++++++++++++
 target/arm/crypto_helper.c | 72 +++++++++++++++++++++++++++-----------
 target/arm/translate-a64.c | 55 ++++++++++++++++++-----------
 target/arm/translate.c     | 27 +++++++-------
 target/arm/vec_helper.c    | 12 +------
 6 files changed, 138 insertions(+), 67 deletions(-)
 create mode 100644 target/arm/vec_internal.h

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(neon_qzip8, TCG_CALL_NO_RWG, void, ptr, ptr)
 DEF_HELPER_FLAGS_2(neon_qzip16, TCG_CALL_NO_RWG, void, ptr, ptr)
 DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr)
 
-DEF_HELPER_FLAGS_3(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 
 DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32, i32)
 DEF_HELPER_FLAGS_3(crypto_sm3partw1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
 DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
 
-DEF_HELPER_FLAGS_2(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr)
-DEF_HELPER_FLAGS_3(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 
 DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
 DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/vec_internal.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * ARM AdvSIMD / SVE Vector Helpers
+ *
+ * Copyright (c) 2020 Linaro
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARM_VEC_INTERNALS_H
+#define TARGET_ARM_VEC_INTERNALS_H
+
+static inline void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
+{
+    uint64_t *d = vd + opr_sz;
+    uintptr_t i;
+
+    for (i = opr_sz; i < max_sz; i += 8) {
+        *d++ = 0;
+    }
+}
+
+#endif /* TARGET_ARM_VEC_INTERNALS_H */
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/crypto_helper.c
+++ b/target/arm/crypto_helper.c
@@ -XXX,XX +XXX,XX @@
 
 #include "cpu.h"
 #include "exec/helper-proto.h"
+#include "tcg/tcg-gvec-desc.h"
 #include "crypto/aes.h"
+#include "vec_internal.h"
 
 union CRYPTO_STATE {
     uint8_t    bytes[16];
@@ -XXX,XX +XXX,XX @@ union CRYPTO_STATE {
 #define CR_ST_WORD(state, i)   (state.words[i])
 #endif
 
-void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt)
+static void do_crypto_aese(uint64_t *rd, uint64_t *rn,
+                           uint64_t *rm, bool decrypt)
 {
     static uint8_t const * const sbox[2] = { AES_sbox, AES_isbox };
     static uint8_t const * const shift[2] = { AES_shifts, AES_ishifts };
-    uint64_t *rd = vd;
-    uint64_t *rm = vm;
     union CRYPTO_STATE rk = { .l = { rm[0], rm[1] } };
-    union CRYPTO_STATE st = { .l = { rd[0], rd[1] } };
+    union CRYPTO_STATE st = { .l = { rn[0], rn[1] } };
     int i;
 
-    assert(decrypt < 2);
-
     /* xor state vector with round key */
     rk.l[0] ^= st.l[0];
     rk.l[1] ^= st.l[1];
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt)
     rd[1] = st.l[1];
 }
 
-void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)
+void HELPER(crypto_aese)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+    intptr_t i, opr_sz = simd_oprsz(desc);
+    bool decrypt = simd_data(desc);
+
+    for (i = 0; i < opr_sz; i += 16) {
+        do_crypto_aese(vd + i, vn + i, vm + i, decrypt);
+    }
+    clear_tail(vd, opr_sz, simd_maxsz(desc));
+}
+
+static void do_crypto_aesmc(uint64_t *rd, uint64_t *rm, bool decrypt)
 {
     static uint32_t const mc[][256] = { {
         /* MixColumns lookup table */
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)
         0xbe805d9f, 0xb58d5491, 0xa89a4f83, 0xa397468d,
     } };
 
-    uint64_t *rd = vd;
-    uint64_t *rm = vm;
     union CRYPTO_STATE st = { .l = { rm[0], rm[1] } };
     int i;
 
-    assert(decrypt < 2);
-
     for (i = 0; i < 16; i += 4) {
         CR_ST_WORD(st, i >> 2) =
             mc[decrypt][CR_ST_BYTE(st, i)] ^
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)
     rd[1] = st.l[1];
 }
 
+void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t desc)
+{
+    intptr_t i, opr_sz = simd_oprsz(desc);
+    bool decrypt = simd_data(desc);
+
+    for (i = 0; i < opr_sz; i += 16) {
+        do_crypto_aesmc(vd + i, vm + i, decrypt);
+    }
+    clear_tail(vd, opr_sz, simd_maxsz(desc));
+}
+
 /*
  * SHA-1 logical functions
  */
@@ -XXX,XX +XXX,XX @@ static uint8_t const sm4_sbox[] = {
     0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
 };
 
-void HELPER(crypto_sm4e)(void *vd, void *vn)
+static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
 {
-    uint64_t *rd = vd;
-    uint64_t *rn = vn;
-    union CRYPTO_STATE d = { .l = { rd[0], rd[1] } };
-    union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };
+    union CRYPTO_STATE d = { .l = { rn[0], rn[1] } };
+    union CRYPTO_STATE n = { .l = { rm[0], rm[1] } };
     uint32_t t, i;
 
     for (i = 0; i < 4; i++) {
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4e)(void *vd, void *vn)
     rd[1] = d.l[1];
 }
 
-void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm)
+void HELPER(crypto_sm4e)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+    intptr_t i, opr_sz = simd_oprsz(desc);
+
+    for (i = 0; i < opr_sz; i += 16) {
+        do_crypto_sm4e(vd + i, vn + i, vm + i);
+    }
+    clear_tail(vd, opr_sz, simd_maxsz(desc));
+}
+
+static void do_crypto_sm4ekey(uint64_t *rd, uint64_t *rn, uint64_t *rm)
 {
-    uint64_t *rd = vd;
-    uint64_t *rn = vn;
-    uint64_t *rm = vm;
     union CRYPTO_STATE d;
     union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };
     union CRYPTO_STATE m = { .l = { rm[0], rm[1] } };
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm)
     rd[0] = d.l[0];
     rd[1] = d.l[1];
 }
+
+void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm, uint32_t desc)
+{
+    intptr_t i, opr_sz = simd_oprsz(desc);
+
+    for (i = 0; i < opr_sz; i += 16) {
+        do_crypto_sm4ekey(vd + i, vn + i, vm + i);
+    }
+    clear_tail(vd, opr_sz, simd_maxsz(desc));
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void gen_gvec_fn4(DisasContext *s, bool is_q, int rd, int rn, int rm,
             is_q ? 16 : 8, vec_full_reg_size(s));
 }
 
+/* Expand a 2-operand operation using an out-of-line helper.  */
+static void gen_gvec_op2_ool(DisasContext *s, bool is_q, int rd,
+                             int rn, int data, gen_helper_gvec_2 *fn)
+{
+    tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
+                       vec_full_reg_offset(s, rn),
+                       is_q ? 16 : 8, vec_full_reg_size(s), data, fn);
+}
+
 /* Expand a 3-operand operation using an out-of-line helper.  */
 static void gen_gvec_op3_ool(DisasContext *s, bool is_q, int rd,
                              int rn, int rm, int data, gen_helper_gvec_3 *fn)
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
     int rn = extract32(insn, 5, 5);
     int rd = extract32(insn, 0, 5);
     int decrypt;
-    TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
-    TCGv_i32 tcg_decrypt;
-    CryptoThreeOpIntFn *genfn;
+    gen_helper_gvec_2 *genfn2 = NULL;
+    gen_helper_gvec_3 *genfn3 = NULL;
 
     if (!dc_isar_feature(aa64_aes, s) || size != 0) {
         unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
     switch (opcode) {
     case 0x4: /* AESE */
         decrypt = 0;
-        genfn = gen_helper_crypto_aese;
+        genfn3 = gen_helper_crypto_aese;
         break;
     case 0x6: /* AESMC */
         decrypt = 0;
-        genfn = gen_helper_crypto_aesmc;
+        genfn2 = gen_helper_crypto_aesmc;
         break;
     case 0x5: /* AESD */
         decrypt = 1;
-        genfn = gen_helper_crypto_aese;
+        genfn3 = gen_helper_crypto_aese;
         break;
     case 0x7: /* AESIMC */
         decrypt = 1;
-        genfn = gen_helper_crypto_aesmc;
+        genfn2 = gen_helper_crypto_aesmc;
         break;
     default:
         unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
     if (!fp_access_check(s)) {
         return;
     }
-
-    tcg_rd_ptr = vec_full_reg_ptr(s, rd);
-    tcg_rn_ptr = vec_full_reg_ptr(s, rn);
-    tcg_decrypt = tcg_const_i32(decrypt);
-
-    genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_decrypt);
-
-    tcg_temp_free_ptr(tcg_rd_ptr);
-    tcg_temp_free_ptr(tcg_rn_ptr);
-    tcg_temp_free_i32(tcg_decrypt);
+    if (genfn2) {
+        gen_gvec_op2_ool(s, true, rd, rn, decrypt, genfn2);
+    } else {
+        gen_gvec_op3_ool(s, true, rd, rd, rn, decrypt, genfn3);
+    }
 }
 
 /* Crypto three-reg SHA
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
     int rn = extract32(insn, 5, 5);
     int rd = extract32(insn, 0, 5);
     bool feature;
-    CryptoThreeOpFn *genfn;
+    CryptoThreeOpFn *genfn = NULL;
+    gen_helper_gvec_3 *oolfn = NULL;
 
     if (o == 0) {
         switch (opcode) {
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
             break;
         case 2: /* SM4EKEY */
             feature = dc_isar_feature(aa64_sm4, s);
-            genfn = gen_helper_crypto_sm4ekey;
+            oolfn = gen_helper_crypto_sm4ekey;
             break;
         default:
             unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
         return;
     }
 
+    if (oolfn) {
+        gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn);
+        return;
+    }
+
     if (genfn) {
         TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
 
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
     TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
     bool feature;
     CryptoTwoOpFn *genfn;
+    gen_helper_gvec_3 *oolfn = NULL;
 
     switch (opcode) {
     case 0: /* SHA512SU0 */
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
         break;
     case 1: /* SM4E */
         feature = dc_isar_feature(aa64_sm4, s);
-        genfn = gen_helper_crypto_sm4e;
+        oolfn = gen_helper_crypto_sm4e;
         break;
     default:
         unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
         return;
     }
 
+    if (oolfn) {
+        gen_gvec_op3_ool(s, true, rd, rd, rn, 0, oolfn);
+        return;
+    }
+
     tcg_rd_ptr = vec_full_reg_ptr(s, rd);
     tcg_rn_ptr = vec_full_reg_ptr(s, rn);
 
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) {
                         return 1;
                     }
-                    ptr1 = vfp_reg_ptr(true, rd);
-                    ptr2 = vfp_reg_ptr(true, rm);
-
-                     /* Bit 6 is the lowest opcode bit; it distinguishes between
-                      * encryption (AESE/AESMC) and decryption (AESD/AESIMC)
-                      */
-                    tmp3 = tcg_const_i32(extract32(insn, 6, 1));
-
+                    /*
+                     * Bit 6 is the lowest opcode bit; it distinguishes
+                     * between encryption (AESE/AESMC) and decryption
+                     * (AESD/AESIMC).
+                     */
                     if (op == NEON_2RM_AESE) {
-                        gen_helper_crypto_aese(ptr1, ptr2, tmp3);
+                        tcg_gen_gvec_3_ool(vfp_reg_offset(true, rd),
+                                           vfp_reg_offset(true, rd),
+                                           vfp_reg_offset(true, rm),
+                                           16, 16, extract32(insn, 6, 1),
+                                           gen_helper_crypto_aese);
                     } else {
-                        gen_helper_crypto_aesmc(ptr1, ptr2, tmp3);
+                        tcg_gen_gvec_2_ool(vfp_reg_offset(true, rd),
+                                           vfp_reg_offset(true, rm),
+                                           16, 16, extract32(insn, 6, 1),
+                                           gen_helper_crypto_aesmc);
                     }
-                    tcg_temp_free_ptr(ptr1);
-                    tcg_temp_free_ptr(ptr2);
-                    tcg_temp_free_i32(tmp3);
                     break;
                 case NEON_2RM_SHA1H:
                     if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) {
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-proto.h"
 #include "tcg/tcg-gvec-desc.h"
 #include "fpu/softfloat.h"
-
+#include "vec_internal.h"
 
 /* Note that vector data is stored in host-endian 64-bit chunks,
    so addressing units smaller than that needs a host-endian fixup.  */
@@ -XXX,XX +XXX,XX @@
 #define H4(x)  (x)
 #endif
 
-static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
-{
-    uint64_t *d = vd + opr_sz;
-    uintptr_t i;
-
-    for (i = opr_sz; i < max_sz; i += 8) {
-        *d++ = 0;
-    }
-}
-
 /* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
 static int16_t inl_qrdmlah_s16(int16_t src1, int16_t src2,
                                int16_t src3, uint32_t *sat)
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

With this conversion, we will be able to use the same helpers
with sve.  This also fixes a bug in which we failed to clear
the high bits of the SVE register after an AdvSIMD operation.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h        |  2 ++
 target/arm/translate-a64.h |  3 ++
 target/arm/crypto_helper.c | 11 +++++++
 target/arm/translate-a64.c | 59 ++++++++++++++++++++------------------
 4 files changed, 47 insertions(+), 28 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Do not yet convert the helpers to loop over opr_sz, but the
descriptor allows the vector tail to be cleared.  Which fixes
an existing bug vs SVE.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h        | 15 +++++++-----
 target/arm/crypto_helper.c | 37 +++++++++++++++++++++++-----
 target/arm/translate-a64.c | 50 ++++++++++++--------------------------
 3 files changed, 55 insertions(+), 47 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Do not yet convert the helpers to loop over opr_sz, but the
descriptor allows the vector tail to be cleared.  Which fixes
an existing bug vs SVE.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h             |  12 ++--
 target/arm/neon-dp.decode       |  12 ++--
 target/arm/crypto_helper.c      |  24 +++++--
 target/arm/translate-a64.c      |  34 ++++-----
 target/arm/translate-neon.inc.c | 124 +++++---------------------------
 target/arm/translate.c          |  24 ++-----
 6 files changed, 67 insertions(+), 163 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 
 DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-DEF_HELPER_FLAGS_2(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr)
-DEF_HELPER_FLAGS_2(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr)
+DEF_HELPER_FLAGS_3(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 
-DEF_HELPER_FLAGS_3(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
-DEF_HELPER_FLAGS_3(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
-DEF_HELPER_FLAGS_2(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr)
-DEF_HELPER_FLAGS_3(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 
 DEF_HELPER_FLAGS_4(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VPADD_3s         1111 001 0 0 . .. .... .... 1011 . . . 1 .... @3same_q0
 
 VQRDMLAH_3s      1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
 
+@3same_crypto    .... .... .... .... .... .... .... .... \
+                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 q=1
+
 SHA1_3s          1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \
                  vm=%vm_dp vn=%vn_dp vd=%vd_dp
-SHA256H_3s       1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... \
-                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
-SHA256H2_3s      1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... \
-                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
-SHA256SU1_3s     1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... \
-                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
+SHA256H_3s       1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
+SHA256H2_3s      1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
+SHA256SU1_3s     1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
 
 VFMA_fp_3s       1111 001 0 0 . 0 . .... .... 1100 ... 1 .... @3same_fp
 VFMS_fp_3s       1111 001 0 0 . 1 . .... .... 1100 ... 1 .... @3same_fp
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/crypto_helper.c
+++ b/target/arm/crypto_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha1_3reg)(void *vd, void *vn, void *vm, uint32_t op)
     rd[1] = d.l[1];
 }
 
-void HELPER(crypto_sha1h)(void *vd, void *vm)
+void HELPER(crypto_sha1h)(void *vd, void *vm, uint32_t desc)
 {
     uint64_t *rd = vd;
     uint64_t *rm = vm;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha1h)(void *vd, void *vm)
 
     rd[0] = m.l[0];
     rd[1] = m.l[1];
+
+    clear_tail_16(vd, desc);
 }
 
-void HELPER(crypto_sha1su1)(void *vd, void *vm)
+void HELPER(crypto_sha1su1)(void *vd, void *vm, uint32_t desc)
 {
     uint64_t *rd = vd;
     uint64_t *rm = vm;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha1su1)(void *vd, void *vm)
 
     rd[0] = d.l[0];
     rd[1] = d.l[1];
+
+    clear_tail_16(vd, desc);
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static uint32_t s1(uint32_t x)
     return ror32(x, 17) ^ ror32(x, 19) ^ (x >> 10);
 }
 
-void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm)
+void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm, uint32_t desc)
 {
     uint64_t *rd = vd;
     uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm)
 
     rd[0] = d.l[0];
     rd[1] = d.l[1];
+
+    clear_tail_16(vd, desc);
 }
 
-void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm)
+void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm, uint32_t desc)
 {
     uint64_t *rd = vd;
     uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm)
 
     rd[0] = d.l[0];
     rd[1] = d.l[1];
+
+    clear_tail_16(vd, desc);
 }
 
-void HELPER(crypto_sha256su0)(void *vd, void *vm)
+void HELPER(crypto_sha256su0)(void *vd, void *vm, uint32_t desc)
 {
     uint64_t *rd = vd;
     uint64_t *rm = vm;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256su0)(void *vd, void *vm)
 
     rd[0] = d.l[0];
     rd[1] = d.l[1];
+
+    clear_tail_16(vd, desc);
 }
 
-void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm)
+void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm, uint32_t desc)
 {
     uint64_t *rd = vd;
     uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm)
 
     rd[0] = d.l[0];
     rd[1] = d.l[1];
+
+    clear_tail_16(vd, desc);
 }
 
 /*
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
     int rm = extract32(insn, 16, 5);
     int rn = extract32(insn, 5, 5);
     int rd = extract32(insn, 0, 5);
-    CryptoThreeOpFn *genfn;
-    TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
+    gen_helper_gvec_3 *genfn;
     bool feature;
 
     if (size != 0) {
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
         return;
     }
 
-    tcg_rd_ptr = vec_full_reg_ptr(s, rd);
-    tcg_rn_ptr = vec_full_reg_ptr(s, rn);
-    tcg_rm_ptr = vec_full_reg_ptr(s, rm);
-
     if (genfn) {
-        genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr);
+        gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn);
     } else {
         TCGv_i32 tcg_opcode = tcg_const_i32(opcode);
+        TCGv_ptr tcg_rd_ptr = vec_full_reg_ptr(s, rd);
+        TCGv_ptr tcg_rn_ptr = vec_full_reg_ptr(s, rn);
+        TCGv_ptr tcg_rm_ptr = vec_full_reg_ptr(s, rm);
 
         gen_helper_crypto_sha1_3reg(tcg_rd_ptr, tcg_rn_ptr,
                                     tcg_rm_ptr, tcg_opcode);
-        tcg_temp_free_i32(tcg_opcode);
-    }
 
-    tcg_temp_free_ptr(tcg_rd_ptr);
-    tcg_temp_free_ptr(tcg_rn_ptr);
-    tcg_temp_free_ptr(tcg_rm_ptr);
+        tcg_temp_free_i32(tcg_opcode);
+        tcg_temp_free_ptr(tcg_rd_ptr);
+        tcg_temp_free_ptr(tcg_rn_ptr);
+        tcg_temp_free_ptr(tcg_rm_ptr);
+    }
 }
 
 /* Crypto two-reg SHA
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
     int opcode = extract32(insn, 12, 5);
     int rn = extract32(insn, 5, 5);
     int rd = extract32(insn, 0, 5);
-    CryptoTwoOpFn *genfn;
+    gen_helper_gvec_2 *genfn;
     bool feature;
-    TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
 
     if (size != 0) {
         unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
     if (!fp_access_check(s)) {
         return;
     }
-
-    tcg_rd_ptr = vec_full_reg_ptr(s, rd);
-    tcg_rn_ptr = vec_full_reg_ptr(s, rn);
-
-    genfn(tcg_rd_ptr, tcg_rn_ptr);
-
-    tcg_temp_free_ptr(tcg_rd_ptr);
-    tcg_temp_free_ptr(tcg_rn_ptr);
+    gen_gvec_op2_ool(s, true, rd, rn, 0, genfn);
 }
 
 static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ DO_3SAME_CMP(VCGE_S, TCG_COND_GE)
 DO_3SAME_CMP(VCGE_U, TCG_COND_GEU)
 DO_3SAME_CMP(VCEQ, TCG_COND_EQ)
 
-static void gen_VMUL_p_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
-                           uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)
-{
-    tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz,
-                       0, gen_helper_gvec_pmul_b);
-}
+#define WRAP_OOL_FN(WRAPNAME, FUNC)                                        \
+    static void WRAPNAME(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,  \
+                         uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)  \
+    {                                                                      \
+        tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, 0, FUNC); \
+    }
+
+WRAP_OOL_FN(gen_VMUL_p_3s, gen_helper_gvec_pmul_b)
 
 static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
 {
@@ -XXX,XX +XXX,XX @@ static bool trans_SHA1_3s(DisasContext *s, arg_SHA1_3s *a)
     return true;
 }
 
-static bool trans_SHA256H_3s(DisasContext *s, arg_SHA256H_3s *a)
-{
-    TCGv_ptr ptr1, ptr2, ptr3;
-
-    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
-        !dc_isar_feature(aa32_sha2, s)) {
-        return false;
+#define DO_SHA2(NAME, FUNC)                                             \
+    WRAP_OOL_FN(gen_##NAME##_3s, FUNC)                                  \
+    static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a)        \
+    {                                                                   \
+        if (!dc_isar_feature(aa32_sha2, s)) {                           \
+            return false;                                               \
+        }                                                               \
+        return do_3same(s, a, gen_##NAME##_3s);                         \
     }
 
-    /* UNDEF accesses to D16-D31 if they don't exist. */
-    if (!dc_isar_feature(aa32_simd_r32, s) &&
-        ((a->vd | a->vn | a->vm) & 0x10)) {
-        return false;
-    }
-
-    if ((a->vn | a->vm | a->vd) & 1) {
-        return false;
-    }
-
-    if (!vfp_access_check(s)) {
-        return true;
-    }
-
-    ptr1 = vfp_reg_ptr(true, a->vd);
-    ptr2 = vfp_reg_ptr(true, a->vn);
-    ptr3 = vfp_reg_ptr(true, a->vm);
-    gen_helper_crypto_sha256h(ptr1, ptr2, ptr3);
-    tcg_temp_free_ptr(ptr1);
-    tcg_temp_free_ptr(ptr2);
-    tcg_temp_free_ptr(ptr3);
-
-    return true;
-}
-
-static bool trans_SHA256H2_3s(DisasContext *s, arg_SHA256H2_3s *a)
-{
-    TCGv_ptr ptr1, ptr2, ptr3;
-
-    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
-        !dc_isar_feature(aa32_sha2, s)) {
-        return false;
-    }
-
-    /* UNDEF accesses to D16-D31 if they don't exist. */
-    if (!dc_isar_feature(aa32_simd_r32, s) &&
-        ((a->vd | a->vn | a->vm) & 0x10)) {
-        return false;
-    }
-
-    if ((a->vn | a->vm | a->vd) & 1) {
-        return false;
-    }
-
-    if (!vfp_access_check(s)) {
-        return true;
-    }
-
-    ptr1 = vfp_reg_ptr(true, a->vd);
-    ptr2 = vfp_reg_ptr(true, a->vn);
-    ptr3 = vfp_reg_ptr(true, a->vm);
-    gen_helper_crypto_sha256h2(ptr1, ptr2, ptr3);
-    tcg_temp_free_ptr(ptr1);
-    tcg_temp_free_ptr(ptr2);
-    tcg_temp_free_ptr(ptr3);
-
-    return true;
-}
-
-static bool trans_SHA256SU1_3s(DisasContext *s, arg_SHA256SU1_3s *a)
-{
-    TCGv_ptr ptr1, ptr2, ptr3;
-
-    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
-        !dc_isar_feature(aa32_sha2, s)) {
-        return false;
-    }
-
-    /* UNDEF accesses to D16-D31 if they don't exist. */
-    if (!dc_isar_feature(aa32_simd_r32, s) &&
-        ((a->vd | a->vn | a->vm) & 0x10)) {
-        return false;
-    }
-
-    if ((a->vn | a->vm | a->vd) & 1) {
-        return false;
-    }
-
-    if (!vfp_access_check(s)) {
-        return true;
-    }
-
-    ptr1 = vfp_reg_ptr(true, a->vd);
-    ptr2 = vfp_reg_ptr(true, a->vn);
-    ptr3 = vfp_reg_ptr(true, a->vm);
-    gen_helper_crypto_sha256su1(ptr1, ptr2, ptr3);
-    tcg_temp_free_ptr(ptr1);
-    tcg_temp_free_ptr(ptr2);
-    tcg_temp_free_ptr(ptr3);
-
-    return true;
-}
+DO_SHA2(SHA256H, gen_helper_crypto_sha256h)
+DO_SHA2(SHA256H2, gen_helper_crypto_sha256h2)
+DO_SHA2(SHA256SU1, gen_helper_crypto_sha256su1)
 
 #define DO_3SAME_64(INSN, FUNC)                                         \
     static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
     int vec_size;
     uint32_t imm;
     TCGv_i32 tmp, tmp2, tmp3, tmp4, tmp5;
-    TCGv_ptr ptr1, ptr2;
+    TCGv_ptr ptr1;
     TCGv_i64 tmp64;
 
     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) {
                         return 1;
                     }
-                    ptr1 = vfp_reg_ptr(true, rd);
-                    ptr2 = vfp_reg_ptr(true, rm);
-
-                    gen_helper_crypto_sha1h(ptr1, ptr2);
-
-                    tcg_temp_free_ptr(ptr1);
-                    tcg_temp_free_ptr(ptr2);
+                    tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0,
+                                       gen_helper_crypto_sha1h);
                     break;
                 case NEON_2RM_SHA1SU1:
                     if ((rm | rd) & 1) {
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     } else if (!dc_isar_feature(aa32_sha1, s)) {
                         return 1;
                     }
-                    ptr1 = vfp_reg_ptr(true, rd);
-                    ptr2 = vfp_reg_ptr(true, rm);
-                    if (q) {
-                        gen_helper_crypto_sha256su0(ptr1, ptr2);
-                    } else {
-                        gen_helper_crypto_sha1su1(ptr1, ptr2);
-                    }
-                    tcg_temp_free_ptr(ptr1);
-                    tcg_temp_free_ptr(ptr2);
+                    tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0,
+                                       q ? gen_helper_crypto_sha256su0
+                                       : gen_helper_crypto_sha1su1);
                     break;
-
                 case NEON_2RM_VMVN:
                     tcg_gen_gvec_not(0, rd_ofs, rm_ofs, vec_size, vec_size);
                     break;
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Rather than passing an opcode to a helper, fully decode the
operation at translate time.  Use clear_tail_16 to zap the
balance of the SVE register with the AdvSIMD write.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-6-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h             |  5 +-
 target/arm/neon-dp.decode       |  6 +-
 target/arm/crypto_helper.c      | 99 +++++++++++++++++++++------------
 target/arm/translate-a64.c      | 29 ++++------
 target/arm/translate-neon.inc.c | 46 ++++-----------
 5 files changed, 93 insertions(+), 92 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Rather than passing an opcode to a helper, fully decode the
operation at translate time.  Use clear_tail_16 to zap the
balance of the SVE register with the AdvSIMD write.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-7-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h        |  5 ++++-
 target/arm/crypto_helper.c | 24 ++++++++++++++++++------
 target/arm/translate-a64.c | 21 +++++----------------
 3 files changed, 27 insertions(+), 23 deletions(-)

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The ADC region size is 256B, split as:
 - [0x00 - 0x4f] defined
 - [0x50 - 0xff] reserved

All registers are 32-bit (thus when the datasheet mentions the
last defined register is 0x4c, it means its address range is
0x4c .. 0x4f.

This model implementation is also 32-bit. Set MemoryRegionOps
'impl' fields.

See:
  'RM0033 Reference manual Rev 8', Table 10.13.18 "ADC register map".

Reported-by: Seth Kintigh <skintigh@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200603055915.17678-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/adc/stm32f2xx_adc.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/adc/stm32f2xx_adc.c b/hw/adc/stm32f2xx_adc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/adc/stm32f2xx_adc.c
+++ b/hw/adc/stm32f2xx_adc.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps stm32f2xx_adc_ops = {
     .read = stm32f2xx_adc_read,
     .write = stm32f2xx_adc_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
 };
 
 static const VMStateDescription vmstate_stm32f2xx_adc = {
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_adc_init(Object *obj)
     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 
     memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s,
-                          TYPE_STM32F2XX_ADC, 0xFF);
+                          TYPE_STM32F2XX_ADC, 0x100);
     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 }
 
-- 
2.20.1

From: Thomas Huth <thuth@redhat.com>

As described by Edgar here:

https://www.mail-archive.com/qemu-devel@nongnu.org/msg605124.html

we can use the Ubuntu kernel for testing the xlnx-versal-virt machine.
So let's add a boot test for this now.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20200525141237.15243-1-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/acceptance/boot_linux_console.py | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(LinuxKernelTest):
         console_pattern = 'Kernel command line: %s' % kernel_command_line
         self.wait_for_console_pattern(console_pattern)
 
+    def test_aarch64_xlnx_versal_virt(self):
+        """
+        :avocado: tags=arch:aarch64
+        :avocado: tags=machine:xlnx-versal-virt
+        :avocado: tags=device:pl011
+        :avocado: tags=device:arm_gicv3
+        """
+        kernel_url = ('http://ports.ubuntu.com/ubuntu-ports/dists/'
+                      'bionic-updates/main/installer-arm64/current/images/'
+                      'netboot/ubuntu-installer/arm64/linux')
+        kernel_hash = '5bfc54cf7ed8157d93f6e5b0241e727b6dc22c50'
+        kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+
+        initrd_url = ('http://ports.ubuntu.com/ubuntu-ports/dists/'
+                      'bionic-updates/main/installer-arm64/current/images/'
+                      'netboot/ubuntu-installer/arm64/initrd.gz')
+        initrd_hash = 'd385d3e88d53e2004c5d43cbe668b458a094f772'
+        initrd_path = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
+
+        self.vm.set_console()
+        self.vm.add_args('-m', '2G',
+                         '-kernel', kernel_path,
+                         '-initrd', initrd_path)
+        self.vm.launch()
+        self.wait_for_console_pattern('Checked W+X mappings: passed')
+
     def test_arm_virt(self):
         """
         :avocado: tags=arch:arm
-- 
2.20.1

From: Cédric Le Goater <clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200602135050.593692-1-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/aspeed.rst | 85 ++++++++++++++++++++++++++++++++++++++
 docs/system/target-arm.rst |  1 +
 2 files changed, 86 insertions(+)
 create mode 100644 docs/system/arm/aspeed.rst

diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/arm/aspeed.rst
@@ -XXX,XX +XXX,XX @@
+Aspeed family boards (``*-bmc``, ``ast2500-evb``, ``ast2600-evb``)
+==================================================================
+
+The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
+Aspeed evaluation boards. They are based on different releases of the
+Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the
+AST2500 with an ARM1176JZS CPU (800MHz) and more recently the AST2600
+with dual cores ARM Cortex A7 CPUs (1.2GHz).
+
+The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C,
+etc.
+
+AST2400 SoC based machines :
+
+- ``palmetto-bmc``         OpenPOWER Palmetto POWER8 BMC
+
+AST2500 SoC based machines :
+
+- ``ast2500-evb``          Aspeed AST2500 Evaluation board
+- ``romulus-bmc``          OpenPOWER Romulus POWER9 BMC
+- ``witherspoon-bmc``      OpenPOWER Witherspoon POWER9 BMC
+- ``sonorapass-bmc``       OCP SonoraPass BMC
+- ``swift-bmc``            OpenPOWER Swift BMC POWER9
+
+AST2600 SoC based machines :
+
+- ``ast2600-evb``          Aspeed AST2600 Evaluation board (Cortex A7)
+- ``tacoma-bmc``           OpenPOWER Witherspoon POWER9 AST2600 BMC
+
+Supported devices
+-----------------
+
+ * SMP (for the AST2600 Cortex-A7)
+ * Interrupt Controller (VIC)
+ * Timer Controller
+ * RTC Controller
+ * I2C Controller
+ * System Control Unit (SCU)
+ * SRAM mapping
+ * X-DMA Controller (basic interface)
+ * Static Memory Controller (SMC or FMC) - Only SPI Flash support
+ * SPI Memory Controller
+ * USB 2.0 Controller
+ * SD/MMC storage controllers
+ * SDRAM controller (dummy interface for basic settings and training)
+ * Watchdog Controller
+ * GPIO Controller (Master only)
+ * UART
+ * Ethernet controllers
+
+
+Missing devices
+---------------
+
+ * Coprocessor support
+ * ADC (out of tree implementation)
+ * PWM and Fan Controller
+ * LPC Bus Controller
+ * Slave GPIO Controller
+ * Super I/O Controller
+ * Hash/Crypto Engine
+ * PCI-Express 1 Controller
+ * Graphic Display Controller
+ * PECI Controller
+ * MCTP Controller
+ * Mailbox Controller
+ * Virtual UART
+ * eSPI Controller
+ * I3C Controller
+
+Boot options
+------------
+
+The Aspeed machines can be started using the -kernel option to load a
+Linux kernel or from a firmare image which can be downloaded from the
+OpenPOWER jenkins :
+
+   https://openpower.xyz/
+
+The image should be attached as an MTD drive. Run :
+
+.. code-block:: bash
+
+  $ qemu-system-arm -M romulus-bmc -nic user \
+	-drive file=flash-romulus,format=raw,if=mtd -nographic
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
    arm/realview
    arm/versatile
    arm/vexpress
+   arm/aspeed
    arm/musicpal
    arm/nseries
    arm/orangepi
-- 
2.20.1

From: Paul Zimmerman <pauldzim@gmail.com>

Add BCM2835 SOC MPHI (Message-based Parallel Host Interface)
emulation. It is very basic, only providing the FIQ interrupt
needed to allow the dwc-otg USB host controller driver in the
Raspbian kernel to function.

Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Acked-by: Philippe Mathieu-Daude <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200520235349.21215-2-pauldzim@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/bcm2835_peripherals.h |   2 +
 include/hw/misc/bcm2835_mphi.h       |  44 ++++++
 hw/arm/bcm2835_peripherals.c         |  17 +++
 hw/misc/bcm2835_mphi.c               | 191 +++++++++++++++++++++++++++
 hw/misc/Makefile.objs                |   1 +
 5 files changed, 255 insertions(+)
 create mode 100644 include/hw/misc/bcm2835_mphi.h
 create mode 100644 hw/misc/bcm2835_mphi.c

diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2835_peripherals.h
+++ b/include/hw/arm/bcm2835_peripherals.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/bcm2835_property.h"
 #include "hw/misc/bcm2835_rng.h"
 #include "hw/misc/bcm2835_mbox.h"
+#include "hw/misc/bcm2835_mphi.h"
 #include "hw/misc/bcm2835_thermal.h"
 #include "hw/sd/sdhci.h"
 #include "hw/sd/bcm2835_sdhost.h"
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState {
     qemu_irq irq, fiq;
 
     BCM2835SystemTimerState systmr;
+    BCM2835MphiState mphi;
     UnimplementedDeviceState armtmr;
     UnimplementedDeviceState cprman;
     UnimplementedDeviceState a2w;
diff --git a/include/hw/misc/bcm2835_mphi.h b/include/hw/misc/bcm2835_mphi.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/bcm2835_mphi.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * BCM2835 SOC MPHI state definitions
+ *
+ * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef HW_MISC_BCM2835_MPHI_H
+#define HW_MISC_BCM2835_MPHI_H
+
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+
+#define MPHI_MMIO_SIZE      0x1000
+
+typedef struct BCM2835MphiState BCM2835MphiState;
+
+struct BCM2835MphiState {
+    SysBusDevice parent_obj;
+    qemu_irq irq;
+    MemoryRegion iomem;
+
+    uint32_t outdda;
+    uint32_t outddb;
+    uint32_t ctrl;
+    uint32_t intstat;
+    uint32_t swirq;
+};
+
+#define TYPE_BCM2835_MPHI   "bcm2835-mphi"
+
+#define BCM2835_MPHI(obj) \
+    OBJECT_CHECK(BCM2835MphiState, (obj), TYPE_BCM2835_MPHI)
+
+#endif
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2835_peripherals.c
+++ b/hw/arm/bcm2835_peripherals.c
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
                                    OBJECT(&s->sdhci.sdbus));
     object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost",
                                    OBJECT(&s->sdhost.sdbus));
+
+    /* Mphi */
+    sysbus_init_child_obj(obj, "mphi", &s->mphi, sizeof(s->mphi),
+                          TYPE_BCM2835_MPHI);
 }
 
 static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
 
     object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus");
 
+    /* Mphi */
+    object_property_set_bool(OBJECT(&s->mphi), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+
+    memory_region_add_subregion(&s->peri_mr, MPHI_OFFSET,
+                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mphi), 0));
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->mphi), 0,
+        qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
+                               INTERRUPT_HOSTPORT));
+
     create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
     create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
     create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
diff --git a/hw/misc/bcm2835_mphi.c b/hw/misc/bcm2835_mphi.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/bcm2835_mphi.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * BCM2835 SOC MPHI emulation
+ *
+ * Very basic emulation, only providing the FIQ interrupt needed to
+ * allow the dwc-otg USB host controller driver in the Raspbian kernel
+ * to function.
+ *
+ * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/misc/bcm2835_mphi.h"
+#include "migration/vmstate.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/main-loop.h"
+
+static inline void mphi_raise_irq(BCM2835MphiState *s)
+{
+    qemu_set_irq(s->irq, 1);
+}
+
+static inline void mphi_lower_irq(BCM2835MphiState *s)
+{
+    qemu_set_irq(s->irq, 0);
+}
+
+static uint64_t mphi_reg_read(void *ptr, hwaddr addr, unsigned size)
+{
+    BCM2835MphiState *s = ptr;
+    uint32_t val = 0;
+
+    switch (addr) {
+    case 0x28:  /* outdda */
+        val = s->outdda;
+        break;
+    case 0x2c:  /* outddb */
+        val = s->outddb;
+        break;
+    case 0x4c:  /* ctrl */
+        val = s->ctrl;
+        val |= 1 << 17;
+        break;
+    case 0x50:  /* intstat */
+        val = s->intstat;
+        break;
+    case 0x1f0: /* swirq_set */
+        val = s->swirq;
+        break;
+    case 0x1f4: /* swirq_clr */
+        val = s->swirq;
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "read from unknown register");
+        break;
+    }
+
+    return val;
+}
+
+static void mphi_reg_write(void *ptr, hwaddr addr, uint64_t val, unsigned size)
+{
+    BCM2835MphiState *s = ptr;
+    int do_irq = 0;
+
+    switch (addr) {
+    case 0x28:  /* outdda */
+        s->outdda = val;
+        break;
+    case 0x2c:  /* outddb */
+        s->outddb = val;
+        if (val & (1 << 29)) {
+            do_irq = 1;
+        }
+        break;
+    case 0x4c:  /* ctrl */
+        s->ctrl = val;
+        if (val & (1 << 16)) {
+            do_irq = -1;
+        }
+        break;
+    case 0x50:  /* intstat */
+        s->intstat = val;
+        if (val & ((1 << 16) | (1 << 29))) {
+            do_irq = -1;
+        }
+        break;
+    case 0x1f0: /* swirq_set */
+        s->swirq |= val;
+        do_irq = 1;
+        break;
+    case 0x1f4: /* swirq_clr */
+        s->swirq &= ~val;
+        do_irq = -1;
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "write to unknown register");
+        return;
+    }
+
+    if (do_irq > 0) {
+        mphi_raise_irq(s);
+    } else if (do_irq < 0) {
+        mphi_lower_irq(s);
+    }
+}
+
+static const MemoryRegionOps mphi_mmio_ops = {
+    .read = mphi_reg_read,
+    .write = mphi_reg_write,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void mphi_reset(DeviceState *dev)
+{
+    BCM2835MphiState *s = BCM2835_MPHI(dev);
+
+    s->outdda = 0;
+    s->outddb = 0;
+    s->ctrl = 0;
+    s->intstat = 0;
+    s->swirq = 0;
+}
+
+static void mphi_realize(DeviceState *dev, Error **errp)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+    BCM2835MphiState *s = BCM2835_MPHI(dev);
+
+    sysbus_init_irq(sbd, &s->irq);
+}
+
+static void mphi_init(Object *obj)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    BCM2835MphiState *s = BCM2835_MPHI(obj);
+
+    memory_region_init_io(&s->iomem, obj, &mphi_mmio_ops, s, "mphi", MPHI_MMIO_SIZE);
+    sysbus_init_mmio(sbd, &s->iomem);
+}
+
+const VMStateDescription vmstate_mphi_state = {
+    .name = "mphi",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(outdda, BCM2835MphiState),
+        VMSTATE_UINT32(outddb, BCM2835MphiState),
+        VMSTATE_UINT32(ctrl, BCM2835MphiState),
+        VMSTATE_UINT32(intstat, BCM2835MphiState),
+        VMSTATE_UINT32(swirq, BCM2835MphiState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void mphi_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = mphi_realize;
+    dc->reset = mphi_reset;
+    dc->vmsd = &vmstate_mphi_state;
+}
+
+static const TypeInfo bcm2835_mphi_type_info = {
+    .name          = TYPE_BCM2835_MPHI,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(BCM2835MphiState),
+    .instance_init = mphi_init,
+    .class_init    = mphi_class_init,
+};
+
+static void bcm2835_mphi_register_types(void)
+{
+    type_register_static(&bcm2835_mphi_type_info);
+}
+
+type_init(bcm2835_mphi_register_types)
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_OMAP) += omap_l4.o
 common-obj-$(CONFIG_OMAP) += omap_sdrc.o
 common-obj-$(CONFIG_OMAP) += omap_tap.o
 common-obj-$(CONFIG_RASPI) += bcm2835_mbox.o
+common-obj-$(CONFIG_RASPI) += bcm2835_mphi.o
 common-obj-$(CONFIG_RASPI) += bcm2835_property.o
 common-obj-$(CONFIG_RASPI) += bcm2835_rng.o
 common-obj-$(CONFIG_RASPI) += bcm2835_thermal.o
-- 
2.20.1

From: Paul Zimmerman <pauldzim@gmail.com>

Import the dwc-hsotg (dwc2) register definitions file from the
Linux kernel. This is a copy of drivers/usb/dwc2/hw.h from the
mainline Linux kernel, the only changes being to the header, and
two instances of 'u32' changed to 'uint32_t' to allow it to
compile. Checkpatch throws a boatload of errors due to the tab
indentation, but I would rather import it as-is than reformat it.

Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Message-id: 20200520235349.21215-3-pauldzim@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/usb/dwc2-regs.h | 899 +++++++++++++++++++++++++++++++++++++
 1 file changed, 899 insertions(+)
 create mode 100644 include/hw/usb/dwc2-regs.h

diff --git a/include/hw/usb/dwc2-regs.h b/include/hw/usb/dwc2-regs.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/usb/dwc2-regs.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Imported from the Linux kernel file drivers/usb/dwc2/hw.h, commit
+ * a89bae709b3492b478480a2c9734e7e9393b279c ("usb: dwc2: Move
+ * UTMI_PHY_DATA defines closer")
+ *
+ * hw.h - DesignWare HS OTG Controller hardware definitions
+ *
+ * Copyright 2004-2013 Synopsys, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The names of the above-listed copyright holders may not be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __DWC2_HW_H__
+#define __DWC2_HW_H__
+
+#define HSOTG_REG(x)	(x)
+
+#define GOTGCTL				HSOTG_REG(0x000)
+#define GOTGCTL_CHIRPEN			BIT(27)
+#define GOTGCTL_MULT_VALID_BC_MASK	(0x1f << 22)
+#define GOTGCTL_MULT_VALID_BC_SHIFT	22
+#define GOTGCTL_OTGVER			BIT(20)
+#define GOTGCTL_BSESVLD			BIT(19)
+#define GOTGCTL_ASESVLD			BIT(18)
+#define GOTGCTL_DBNC_SHORT		BIT(17)
+#define GOTGCTL_CONID_B			BIT(16)
+#define GOTGCTL_DBNCE_FLTR_BYPASS	BIT(15)
+#define GOTGCTL_DEVHNPEN		BIT(11)
+#define GOTGCTL_HSTSETHNPEN		BIT(10)
+#define GOTGCTL_HNPREQ			BIT(9)
+#define GOTGCTL_HSTNEGSCS		BIT(8)
+#define GOTGCTL_SESREQ			BIT(1)
+#define GOTGCTL_SESREQSCS		BIT(0)
+
+#define GOTGINT				HSOTG_REG(0x004)
+#define GOTGINT_DBNCE_DONE		BIT(19)
+#define GOTGINT_A_DEV_TOUT_CHG		BIT(18)
+#define GOTGINT_HST_NEG_DET		BIT(17)
+#define GOTGINT_HST_NEG_SUC_STS_CHNG	BIT(9)
+#define GOTGINT_SES_REQ_SUC_STS_CHNG	BIT(8)
+#define GOTGINT_SES_END_DET		BIT(2)
+
+#define GAHBCFG				HSOTG_REG(0x008)
+#define GAHBCFG_AHB_SINGLE		BIT(23)
+#define GAHBCFG_NOTI_ALL_DMA_WRIT	BIT(22)
+#define GAHBCFG_REM_MEM_SUPP		BIT(21)
+#define GAHBCFG_P_TXF_EMP_LVL		BIT(8)
+#define GAHBCFG_NP_TXF_EMP_LVL		BIT(7)
+#define GAHBCFG_DMA_EN			BIT(5)
+#define GAHBCFG_HBSTLEN_MASK		(0xf << 1)
+#define GAHBCFG_HBSTLEN_SHIFT		1
+#define GAHBCFG_HBSTLEN_SINGLE		0
+#define GAHBCFG_HBSTLEN_INCR		1
+#define GAHBCFG_HBSTLEN_INCR4		3
+#define GAHBCFG_HBSTLEN_INCR8		5
+#define GAHBCFG_HBSTLEN_INCR16		7
+#define GAHBCFG_GLBL_INTR_EN		BIT(0)
+#define GAHBCFG_CTRL_MASK		(GAHBCFG_P_TXF_EMP_LVL | \
+					 GAHBCFG_NP_TXF_EMP_LVL | \
+					 GAHBCFG_DMA_EN | \
+					 GAHBCFG_GLBL_INTR_EN)
+
+#define GUSBCFG				HSOTG_REG(0x00C)
+#define GUSBCFG_FORCEDEVMODE		BIT(30)
+#define GUSBCFG_FORCEHOSTMODE		BIT(29)
+#define GUSBCFG_TXENDDELAY		BIT(28)
+#define GUSBCFG_ICTRAFFICPULLREMOVE	BIT(27)
+#define GUSBCFG_ICUSBCAP		BIT(26)
+#define GUSBCFG_ULPI_INT_PROT_DIS	BIT(25)
+#define GUSBCFG_INDICATORPASSTHROUGH	BIT(24)
+#define GUSBCFG_INDICATORCOMPLEMENT	BIT(23)
+#define GUSBCFG_TERMSELDLPULSE		BIT(22)
+#define GUSBCFG_ULPI_INT_VBUS_IND	BIT(21)
+#define GUSBCFG_ULPI_EXT_VBUS_DRV	BIT(20)
+#define GUSBCFG_ULPI_CLK_SUSP_M		BIT(19)
+#define GUSBCFG_ULPI_AUTO_RES		BIT(18)
+#define GUSBCFG_ULPI_FS_LS		BIT(17)
+#define GUSBCFG_OTG_UTMI_FS_SEL		BIT(16)
+#define GUSBCFG_PHY_LP_CLK_SEL		BIT(15)
+#define GUSBCFG_USBTRDTIM_MASK		(0xf << 10)
+#define GUSBCFG_USBTRDTIM_SHIFT		10
+#define GUSBCFG_HNPCAP			BIT(9)
+#define GUSBCFG_SRPCAP			BIT(8)
+#define GUSBCFG_DDRSEL			BIT(7)
+#define GUSBCFG_PHYSEL			BIT(6)
+#define GUSBCFG_FSINTF			BIT(5)
+#define GUSBCFG_ULPI_UTMI_SEL		BIT(4)
+#define GUSBCFG_PHYIF16			BIT(3)
+#define GUSBCFG_PHYIF8			(0 << 3)
+#define GUSBCFG_TOUTCAL_MASK		(0x7 << 0)
+#define GUSBCFG_TOUTCAL_SHIFT		0
+#define GUSBCFG_TOUTCAL_LIMIT		0x7
+#define GUSBCFG_TOUTCAL(_x)		((_x) << 0)
+
+#define GRSTCTL				HSOTG_REG(0x010)
+#define GRSTCTL_AHBIDLE			BIT(31)
+#define GRSTCTL_DMAREQ			BIT(30)
+#define GRSTCTL_TXFNUM_MASK		(0x1f << 6)
+#define GRSTCTL_TXFNUM_SHIFT		6
+#define GRSTCTL_TXFNUM_LIMIT		0x1f
+#define GRSTCTL_TXFNUM(_x)		((_x) << 6)
+#define GRSTCTL_TXFFLSH			BIT(5)
+#define GRSTCTL_RXFFLSH			BIT(4)
+#define GRSTCTL_IN_TKNQ_FLSH		BIT(3)
+#define GRSTCTL_FRMCNTRRST		BIT(2)
+#define GRSTCTL_HSFTRST			BIT(1)
+#define GRSTCTL_CSFTRST			BIT(0)
+
+#define GINTSTS				HSOTG_REG(0x014)
+#define GINTMSK				HSOTG_REG(0x018)
+#define GINTSTS_WKUPINT			BIT(31)
+#define GINTSTS_SESSREQINT		BIT(30)
+#define GINTSTS_DISCONNINT		BIT(29)
+#define GINTSTS_CONIDSTSCHNG		BIT(28)
+#define GINTSTS_LPMTRANRCVD		BIT(27)
+#define GINTSTS_PTXFEMP			BIT(26)
+#define GINTSTS_HCHINT			BIT(25)
+#define GINTSTS_PRTINT			BIT(24)
+#define GINTSTS_RESETDET		BIT(23)
+#define GINTSTS_FET_SUSP		BIT(22)
+#define GINTSTS_INCOMPL_IP		BIT(21)
+#define GINTSTS_INCOMPL_SOOUT		BIT(21)
+#define GINTSTS_INCOMPL_SOIN		BIT(20)
+#define GINTSTS_OEPINT			BIT(19)
+#define GINTSTS_IEPINT			BIT(18)
+#define GINTSTS_EPMIS			BIT(17)
+#define GINTSTS_RESTOREDONE		BIT(16)
+#define GINTSTS_EOPF			BIT(15)
+#define GINTSTS_ISOUTDROP		BIT(14)
+#define GINTSTS_ENUMDONE		BIT(13)
+#define GINTSTS_USBRST			BIT(12)
+#define GINTSTS_USBSUSP			BIT(11)
+#define GINTSTS_ERLYSUSP		BIT(10)
+#define GINTSTS_I2CINT			BIT(9)
+#define GINTSTS_ULPI_CK_INT		BIT(8)
+#define GINTSTS_GOUTNAKEFF		BIT(7)
+#define GINTSTS_GINNAKEFF		BIT(6)
+#define GINTSTS_NPTXFEMP		BIT(5)
+#define GINTSTS_RXFLVL			BIT(4)
+#define GINTSTS_SOF			BIT(3)
+#define GINTSTS_OTGINT			BIT(2)
+#define GINTSTS_MODEMIS			BIT(1)
+#define GINTSTS_CURMODE_HOST		BIT(0)
+
+#define GRXSTSR				HSOTG_REG(0x01C)
+#define GRXSTSP				HSOTG_REG(0x020)
+#define GRXSTS_FN_MASK			(0x7f << 25)
+#define GRXSTS_FN_SHIFT			25
+#define GRXSTS_PKTSTS_MASK		(0xf << 17)
+#define GRXSTS_PKTSTS_SHIFT		17
+#define GRXSTS_PKTSTS_GLOBALOUTNAK	1
+#define GRXSTS_PKTSTS_OUTRX		2
+#define GRXSTS_PKTSTS_HCHIN		2
+#define GRXSTS_PKTSTS_OUTDONE		3
+#define GRXSTS_PKTSTS_HCHIN_XFER_COMP	3
+#define GRXSTS_PKTSTS_SETUPDONE		4
+#define GRXSTS_PKTSTS_DATATOGGLEERR	5
+#define GRXSTS_PKTSTS_SETUPRX		6
+#define GRXSTS_PKTSTS_HCHHALTED		7
+#define GRXSTS_HCHNUM_MASK		(0xf << 0)
+#define GRXSTS_HCHNUM_SHIFT		0
+#define GRXSTS_DPID_MASK		(0x3 << 15)
+#define GRXSTS_DPID_SHIFT		15
+#define GRXSTS_BYTECNT_MASK		(0x7ff << 4)
+#define GRXSTS_BYTECNT_SHIFT		4
+#define GRXSTS_EPNUM_MASK		(0xf << 0)
+#define GRXSTS_EPNUM_SHIFT		0
+
+#define GRXFSIZ				HSOTG_REG(0x024)
+#define GRXFSIZ_DEPTH_MASK		(0xffff << 0)
+#define GRXFSIZ_DEPTH_SHIFT		0
+
+#define GNPTXFSIZ			HSOTG_REG(0x028)
+/* Use FIFOSIZE_* constants to access this register */
+
+#define GNPTXSTS			HSOTG_REG(0x02C)
+#define GNPTXSTS_NP_TXQ_TOP_MASK		(0x7f << 24)
+#define GNPTXSTS_NP_TXQ_TOP_SHIFT		24
+#define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK		(0xff << 16)
+#define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT		16
+#define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v)	(((_v) >> 16) & 0xff)
+#define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK		(0xffff << 0)
+#define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT		0
+#define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v)	(((_v) >> 0) & 0xffff)
+
+#define GI2CCTL				HSOTG_REG(0x0030)
+#define GI2CCTL_BSYDNE			BIT(31)
+#define GI2CCTL_RW			BIT(30)
+#define GI2CCTL_I2CDATSE0		BIT(28)
+#define GI2CCTL_I2CDEVADDR_MASK		(0x3 << 26)
+#define GI2CCTL_I2CDEVADDR_SHIFT	26
+#define GI2CCTL_I2CSUSPCTL		BIT(25)
+#define GI2CCTL_ACK			BIT(24)
+#define GI2CCTL_I2CEN			BIT(23)
+#define GI2CCTL_ADDR_MASK		(0x7f << 16)
+#define GI2CCTL_ADDR_SHIFT		16
+#define GI2CCTL_REGADDR_MASK		(0xff << 8)
+#define GI2CCTL_REGADDR_SHIFT		8
+#define GI2CCTL_RWDATA_MASK		(0xff << 0)
+#define GI2CCTL_RWDATA_SHIFT		0
+
+#define GPVNDCTL			HSOTG_REG(0x0034)
+#define GGPIO				HSOTG_REG(0x0038)
+#define GGPIO_STM32_OTG_GCCFG_PWRDWN	BIT(16)
+
+#define GUID				HSOTG_REG(0x003c)
+#define GSNPSID				HSOTG_REG(0x0040)
+#define GHWCFG1				HSOTG_REG(0x0044)
+#define GSNPSID_ID_MASK			GENMASK(31, 16)
+
+#define GHWCFG2				HSOTG_REG(0x0048)
+#define GHWCFG2_OTG_ENABLE_IC_USB		BIT(31)
+#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK		(0x1f << 26)
+#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT		26
+#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK	(0x3 << 24)
+#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT	24
+#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK	(0x3 << 22)
+#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT	22
+#define GHWCFG2_MULTI_PROC_INT			BIT(20)
+#define GHWCFG2_DYNAMIC_FIFO			BIT(19)
+#define GHWCFG2_PERIO_EP_SUPPORTED		BIT(18)
+#define GHWCFG2_NUM_HOST_CHAN_MASK		(0xf << 14)
+#define GHWCFG2_NUM_HOST_CHAN_SHIFT		14
+#define GHWCFG2_NUM_DEV_EP_MASK			(0xf << 10)
+#define GHWCFG2_NUM_DEV_EP_SHIFT		10
+#define GHWCFG2_FS_PHY_TYPE_MASK		(0x3 << 8)
+#define GHWCFG2_FS_PHY_TYPE_SHIFT		8
+#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED	0
+#define GHWCFG2_FS_PHY_TYPE_DEDICATED		1
+#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI		2
+#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI		3
+#define GHWCFG2_HS_PHY_TYPE_MASK		(0x3 << 6)
+#define GHWCFG2_HS_PHY_TYPE_SHIFT		6
+#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED	0
+#define GHWCFG2_HS_PHY_TYPE_UTMI		1
+#define GHWCFG2_HS_PHY_TYPE_ULPI		2
+#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI		3
+#define GHWCFG2_POINT2POINT			BIT(5)
+#define GHWCFG2_ARCHITECTURE_MASK		(0x3 << 3)
+#define GHWCFG2_ARCHITECTURE_SHIFT		3
+#define GHWCFG2_SLAVE_ONLY_ARCH			0
+#define GHWCFG2_EXT_DMA_ARCH			1
+#define GHWCFG2_INT_DMA_ARCH			2
+#define GHWCFG2_OP_MODE_MASK			(0x7 << 0)
+#define GHWCFG2_OP_MODE_SHIFT			0
+#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE		0
+#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE	1
+#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE	2
+#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE	3
+#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE	4
+#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST	5
+#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST	6
+#define GHWCFG2_OP_MODE_UNDEFINED		7
+
+#define GHWCFG3				HSOTG_REG(0x004c)
+#define GHWCFG3_DFIFO_DEPTH_MASK		(0xffff << 16)
+#define GHWCFG3_DFIFO_DEPTH_SHIFT		16
+#define GHWCFG3_OTG_LPM_EN			BIT(15)
+#define GHWCFG3_BC_SUPPORT			BIT(14)
+#define GHWCFG3_OTG_ENABLE_HSIC			BIT(13)
+#define GHWCFG3_ADP_SUPP			BIT(12)
+#define GHWCFG3_SYNCH_RESET_TYPE		BIT(11)
+#define GHWCFG3_OPTIONAL_FEATURES		BIT(10)
+#define GHWCFG3_VENDOR_CTRL_IF			BIT(9)
+#define GHWCFG3_I2C				BIT(8)
+#define GHWCFG3_OTG_FUNC			BIT(7)
+#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK	(0x7 << 4)
+#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT	4
+#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK	(0xf << 0)
+#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT	0
+
+#define GHWCFG4				HSOTG_REG(0x0050)
+#define GHWCFG4_DESC_DMA_DYN			BIT(31)
+#define GHWCFG4_DESC_DMA			BIT(30)
+#define GHWCFG4_NUM_IN_EPS_MASK			(0xf << 26)
+#define GHWCFG4_NUM_IN_EPS_SHIFT		26
+#define GHWCFG4_DED_FIFO_EN			BIT(25)
+#define GHWCFG4_DED_FIFO_SHIFT		25
+#define GHWCFG4_SESSION_END_FILT_EN		BIT(24)
+#define GHWCFG4_B_VALID_FILT_EN			BIT(23)
+#define GHWCFG4_A_VALID_FILT_EN			BIT(22)
+#define GHWCFG4_VBUS_VALID_FILT_EN		BIT(21)
+#define GHWCFG4_IDDIG_FILT_EN			BIT(20)
+#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK	(0xf << 16)
+#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT	16
+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK	(0x3 << 14)
+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT	14
+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8		0
+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16		1
+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16	2
+#define GHWCFG4_ACG_SUPPORTED			BIT(12)
+#define GHWCFG4_IPG_ISOC_SUPPORTED		BIT(11)
+#define GHWCFG4_SERVICE_INTERVAL_SUPPORTED      BIT(10)
+#define GHWCFG4_XHIBER				BIT(7)
+#define GHWCFG4_HIBER				BIT(6)
+#define GHWCFG4_MIN_AHB_FREQ			BIT(5)
+#define GHWCFG4_POWER_OPTIMIZ			BIT(4)
+#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK	(0xf << 0)
+#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT	0
+
+#define GLPMCFG				HSOTG_REG(0x0054)
+#define GLPMCFG_INVSELHSIC		BIT(31)
+#define GLPMCFG_HSICCON			BIT(30)
+#define GLPMCFG_RSTRSLPSTS		BIT(29)
+#define GLPMCFG_ENBESL			BIT(28)
+#define GLPMCFG_LPM_RETRYCNT_STS_MASK	(0x7 << 25)
+#define GLPMCFG_LPM_RETRYCNT_STS_SHIFT	25
+#define GLPMCFG_SNDLPM			BIT(24)
+#define GLPMCFG_RETRY_CNT_MASK		(0x7 << 21)
+#define GLPMCFG_RETRY_CNT_SHIFT		21
+#define GLPMCFG_LPM_REJECT_CTRL_CONTROL	BIT(21)
+#define GLPMCFG_LPM_ACCEPT_CTRL_ISOC	BIT(22)
+#define GLPMCFG_LPM_CHNL_INDX_MASK	(0xf << 17)
+#define GLPMCFG_LPM_CHNL_INDX_SHIFT	17
+#define GLPMCFG_L1RESUMEOK		BIT(16)
+#define GLPMCFG_SLPSTS			BIT(15)
+#define GLPMCFG_COREL1RES_MASK		(0x3 << 13)
+#define GLPMCFG_COREL1RES_SHIFT		13
+#define GLPMCFG_HIRD_THRES_MASK		(0x1f << 8)
+#define GLPMCFG_HIRD_THRES_SHIFT	8
+#define GLPMCFG_HIRD_THRES_EN		(0x10 << 8)
+#define GLPMCFG_ENBLSLPM		BIT(7)
+#define GLPMCFG_BREMOTEWAKE		BIT(6)
+#define GLPMCFG_HIRD_MASK		(0xf << 2)
+#define GLPMCFG_HIRD_SHIFT		2
+#define GLPMCFG_APPL1RES		BIT(1)
+#define GLPMCFG_LPMCAP			BIT(0)
+
+#define GPWRDN				HSOTG_REG(0x0058)
+#define GPWRDN_MULT_VAL_ID_BC_MASK	(0x1f << 24)
+#define GPWRDN_MULT_VAL_ID_BC_SHIFT	24
+#define GPWRDN_ADP_INT			BIT(23)
+#define GPWRDN_BSESSVLD			BIT(22)
+#define GPWRDN_IDSTS			BIT(21)
+#define GPWRDN_LINESTATE_MASK		(0x3 << 19)
+#define GPWRDN_LINESTATE_SHIFT		19
+#define GPWRDN_STS_CHGINT_MSK		BIT(18)
+#define GPWRDN_STS_CHGINT		BIT(17)
+#define GPWRDN_SRP_DET_MSK		BIT(16)
+#define GPWRDN_SRP_DET			BIT(15)
+#define GPWRDN_CONNECT_DET_MSK		BIT(14)
+#define GPWRDN_CONNECT_DET		BIT(13)
+#define GPWRDN_DISCONN_DET_MSK		BIT(12)
+#define GPWRDN_DISCONN_DET		BIT(11)
+#define GPWRDN_RST_DET_MSK		BIT(10)
+#define GPWRDN_RST_DET			BIT(9)
+#define GPWRDN_LNSTSCHG_MSK		BIT(8)
+#define GPWRDN_LNSTSCHG			BIT(7)
+#define GPWRDN_DIS_VBUS			BIT(6)
+#define GPWRDN_PWRDNSWTCH		BIT(5)
+#define GPWRDN_PWRDNRSTN		BIT(4)
+#define GPWRDN_PWRDNCLMP		BIT(3)
+#define GPWRDN_RESTORE			BIT(2)
+#define GPWRDN_PMUACTV			BIT(1)
+#define GPWRDN_PMUINTSEL		BIT(0)
+
+#define GDFIFOCFG			HSOTG_REG(0x005c)
+#define GDFIFOCFG_EPINFOBASE_MASK	(0xffff << 16)
+#define GDFIFOCFG_EPINFOBASE_SHIFT	16
+#define GDFIFOCFG_GDFIFOCFG_MASK	(0xffff << 0)
+#define GDFIFOCFG_GDFIFOCFG_SHIFT	0
+
+#define ADPCTL				HSOTG_REG(0x0060)
+#define ADPCTL_AR_MASK			(0x3 << 27)
+#define ADPCTL_AR_SHIFT			27
+#define ADPCTL_ADP_TMOUT_INT_MSK	BIT(26)
+#define ADPCTL_ADP_SNS_INT_MSK		BIT(25)
+#define ADPCTL_ADP_PRB_INT_MSK		BIT(24)
+#define ADPCTL_ADP_TMOUT_INT		BIT(23)
+#define ADPCTL_ADP_SNS_INT		BIT(22)
+#define ADPCTL_ADP_PRB_INT		BIT(21)
+#define ADPCTL_ADPENA			BIT(20)
+#define ADPCTL_ADPRES			BIT(19)
+#define ADPCTL_ENASNS			BIT(18)
+#define ADPCTL_ENAPRB			BIT(17)
+#define ADPCTL_RTIM_MASK		(0x7ff << 6)
+#define ADPCTL_RTIM_SHIFT		6
+#define ADPCTL_PRB_PER_MASK		(0x3 << 4)
+#define ADPCTL_PRB_PER_SHIFT		4
+#define ADPCTL_PRB_DELTA_MASK		(0x3 << 2)
+#define ADPCTL_PRB_DELTA_SHIFT		2
+#define ADPCTL_PRB_DSCHRG_MASK		(0x3 << 0)
+#define ADPCTL_PRB_DSCHRG_SHIFT		0
+
+#define GREFCLK				    HSOTG_REG(0x0064)
+#define GREFCLK_REFCLKPER_MASK		    (0x1ffff << 15)
+#define GREFCLK_REFCLKPER_SHIFT		    15
+#define GREFCLK_REF_CLK_MODE		    BIT(14)
+#define GREFCLK_SOF_CNT_WKUP_ALERT_MASK	    (0x3ff)
+#define GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT    0
+
+#define GINTMSK2			HSOTG_REG(0x0068)
+#define GINTMSK2_WKUP_ALERT_INT_MSK	BIT(0)
+
+#define GINTSTS2			HSOTG_REG(0x006c)
+#define GINTSTS2_WKUP_ALERT_INT		BIT(0)
+
+#define HPTXFSIZ			HSOTG_REG(0x100)
+/* Use FIFOSIZE_* constants to access this register */
+
+#define DPTXFSIZN(_a)			HSOTG_REG(0x104 + (((_a) - 1) * 4))
+/* Use FIFOSIZE_* constants to access this register */
+
+/* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
+#define FIFOSIZE_DEPTH_MASK		(0xffff << 16)
+#define FIFOSIZE_DEPTH_SHIFT		16
+#define FIFOSIZE_STARTADDR_MASK		(0xffff << 0)
+#define FIFOSIZE_STARTADDR_SHIFT	0
+#define FIFOSIZE_DEPTH_GET(_x)		(((_x) >> 16) & 0xffff)
+
+/* Device mode registers */
+
+#define DCFG				HSOTG_REG(0x800)
+#define DCFG_DESCDMA_EN			BIT(23)
+#define DCFG_EPMISCNT_MASK		(0x1f << 18)
+#define DCFG_EPMISCNT_SHIFT		18
+#define DCFG_EPMISCNT_LIMIT		0x1f
+#define DCFG_EPMISCNT(_x)		((_x) << 18)
+#define DCFG_IPG_ISOC_SUPPORDED		BIT(17)
+#define DCFG_PERFRINT_MASK		(0x3 << 11)
+#define DCFG_PERFRINT_SHIFT		11
+#define DCFG_PERFRINT_LIMIT		0x3
+#define DCFG_PERFRINT(_x)		((_x) << 11)
+#define DCFG_DEVADDR_MASK		(0x7f << 4)
+#define DCFG_DEVADDR_SHIFT		4
+#define DCFG_DEVADDR_LIMIT		0x7f
+#define DCFG_DEVADDR(_x)		((_x) << 4)
+#define DCFG_NZ_STS_OUT_HSHK		BIT(2)
+#define DCFG_DEVSPD_MASK		(0x3 << 0)
+#define DCFG_DEVSPD_SHIFT		0
+#define DCFG_DEVSPD_HS			0
+#define DCFG_DEVSPD_FS			1
+#define DCFG_DEVSPD_LS			2
+#define DCFG_DEVSPD_FS48		3
+
+#define DCTL				HSOTG_REG(0x804)
+#define DCTL_SERVICE_INTERVAL_SUPPORTED BIT(19)
+#define DCTL_PWRONPRGDONE		BIT(11)
+#define DCTL_CGOUTNAK			BIT(10)
+#define DCTL_SGOUTNAK			BIT(9)
+#define DCTL_CGNPINNAK			BIT(8)
+#define DCTL_SGNPINNAK			BIT(7)
+#define DCTL_TSTCTL_MASK		(0x7 << 4)
+#define DCTL_TSTCTL_SHIFT		4
+#define DCTL_GOUTNAKSTS			BIT(3)
+#define DCTL_GNPINNAKSTS		BIT(2)
+#define DCTL_SFTDISCON			BIT(1)
+#define DCTL_RMTWKUPSIG			BIT(0)
+
+#define DSTS				HSOTG_REG(0x808)
+#define DSTS_SOFFN_MASK			(0x3fff << 8)
+#define DSTS_SOFFN_SHIFT		8
+#define DSTS_SOFFN_LIMIT		0x3fff
+#define DSTS_SOFFN(_x)			((_x) << 8)
+#define DSTS_ERRATICERR			BIT(3)
+#define DSTS_ENUMSPD_MASK		(0x3 << 1)
+#define DSTS_ENUMSPD_SHIFT		1
+#define DSTS_ENUMSPD_HS			0
+#define DSTS_ENUMSPD_FS			1
+#define DSTS_ENUMSPD_LS			2
+#define DSTS_ENUMSPD_FS48		3
+#define DSTS_SUSPSTS			BIT(0)
+
+#define DIEPMSK				HSOTG_REG(0x810)
+#define DIEPMSK_NAKMSK			BIT(13)
+#define DIEPMSK_BNAININTRMSK		BIT(9)
+#define DIEPMSK_TXFIFOUNDRNMSK		BIT(8)
+#define DIEPMSK_TXFIFOEMPTY		BIT(7)
+#define DIEPMSK_INEPNAKEFFMSK		BIT(6)
+#define DIEPMSK_INTKNEPMISMSK		BIT(5)
+#define DIEPMSK_INTKNTXFEMPMSK		BIT(4)
+#define DIEPMSK_TIMEOUTMSK		BIT(3)
+#define DIEPMSK_AHBERRMSK		BIT(2)
+#define DIEPMSK_EPDISBLDMSK		BIT(1)
+#define DIEPMSK_XFERCOMPLMSK		BIT(0)
+
+#define DOEPMSK				HSOTG_REG(0x814)
+#define DOEPMSK_BNAMSK			BIT(9)
+#define DOEPMSK_BACK2BACKSETUP		BIT(6)
+#define DOEPMSK_STSPHSERCVDMSK		BIT(5)
+#define DOEPMSK_OUTTKNEPDISMSK		BIT(4)
+#define DOEPMSK_SETUPMSK		BIT(3)
+#define DOEPMSK_AHBERRMSK		BIT(2)
+#define DOEPMSK_EPDISBLDMSK		BIT(1)
+#define DOEPMSK_XFERCOMPLMSK		BIT(0)
+
+#define DAINT				HSOTG_REG(0x818)
+#define DAINTMSK			HSOTG_REG(0x81C)
+#define DAINT_OUTEP_SHIFT		16
+#define DAINT_OUTEP(_x)			(1 << ((_x) + 16))
+#define DAINT_INEP(_x)			(1 << (_x))
+
+#define DTKNQR1				HSOTG_REG(0x820)
+#define DTKNQR2				HSOTG_REG(0x824)
+#define DTKNQR3				HSOTG_REG(0x830)
+#define DTKNQR4				HSOTG_REG(0x834)
+#define DIEPEMPMSK			HSOTG_REG(0x834)
+
+#define DVBUSDIS			HSOTG_REG(0x828)
+#define DVBUSPULSE			HSOTG_REG(0x82C)
+
+#define DIEPCTL0			HSOTG_REG(0x900)
+#define DIEPCTL(_a)			HSOTG_REG(0x900 + ((_a) * 0x20))
+
+#define DOEPCTL0			HSOTG_REG(0xB00)
+#define DOEPCTL(_a)			HSOTG_REG(0xB00 + ((_a) * 0x20))
+
+/* EP0 specialness:
+ * bits[29..28] - reserved (no SetD0PID, SetD1PID)
+ * bits[25..22] - should always be zero, this isn't a periodic endpoint
+ * bits[10..0]  - MPS setting different for EP0
+ */
+#define D0EPCTL_MPS_MASK		(0x3 << 0)
+#define D0EPCTL_MPS_SHIFT		0
+#define D0EPCTL_MPS_64			0
+#define D0EPCTL_MPS_32			1
+#define D0EPCTL_MPS_16			2
+#define D0EPCTL_MPS_8			3
+
+#define DXEPCTL_EPENA			BIT(31)
+#define DXEPCTL_EPDIS			BIT(30)
+#define DXEPCTL_SETD1PID		BIT(29)
+#define DXEPCTL_SETODDFR		BIT(29)
+#define DXEPCTL_SETD0PID		BIT(28)
+#define DXEPCTL_SETEVENFR		BIT(28)
+#define DXEPCTL_SNAK			BIT(27)
+#define DXEPCTL_CNAK			BIT(26)
+#define DXEPCTL_TXFNUM_MASK		(0xf << 22)
+#define DXEPCTL_TXFNUM_SHIFT		22
+#define DXEPCTL_TXFNUM_LIMIT		0xf
+#define DXEPCTL_TXFNUM(_x)		((_x) << 22)
+#define DXEPCTL_STALL			BIT(21)
+#define DXEPCTL_SNP			BIT(20)
+#define DXEPCTL_EPTYPE_MASK		(0x3 << 18)
+#define DXEPCTL_EPTYPE_CONTROL		(0x0 << 18)
+#define DXEPCTL_EPTYPE_ISO		(0x1 << 18)
+#define DXEPCTL_EPTYPE_BULK		(0x2 << 18)
+#define DXEPCTL_EPTYPE_INTERRUPT	(0x3 << 18)
+
+#define DXEPCTL_NAKSTS			BIT(17)
+#define DXEPCTL_DPID			BIT(16)
+#define DXEPCTL_EOFRNUM			BIT(16)
+#define DXEPCTL_USBACTEP		BIT(15)
+#define DXEPCTL_NEXTEP_MASK		(0xf << 11)
+#define DXEPCTL_NEXTEP_SHIFT		11
+#define DXEPCTL_NEXTEP_LIMIT		0xf
+#define DXEPCTL_NEXTEP(_x)		((_x) << 11)
+#define DXEPCTL_MPS_MASK		(0x7ff << 0)
+#define DXEPCTL_MPS_SHIFT		0
+#define DXEPCTL_MPS_LIMIT		0x7ff
+#define DXEPCTL_MPS(_x)			((_x) << 0)
+
+#define DIEPINT(_a)			HSOTG_REG(0x908 + ((_a) * 0x20))
+#define DOEPINT(_a)			HSOTG_REG(0xB08 + ((_a) * 0x20))
+#define DXEPINT_SETUP_RCVD		BIT(15)
+#define DXEPINT_NYETINTRPT		BIT(14)
+#define DXEPINT_NAKINTRPT		BIT(13)
+#define DXEPINT_BBLEERRINTRPT		BIT(12)
+#define DXEPINT_PKTDRPSTS		BIT(11)
+#define DXEPINT_BNAINTR			BIT(9)
+#define DXEPINT_TXFIFOUNDRN		BIT(8)
+#define DXEPINT_OUTPKTERR		BIT(8)
+#define DXEPINT_TXFEMP			BIT(7)
+#define DXEPINT_INEPNAKEFF		BIT(6)
+#define DXEPINT_BACK2BACKSETUP		BIT(6)
+#define DXEPINT_INTKNEPMIS		BIT(5)
+#define DXEPINT_STSPHSERCVD		BIT(5)
+#define DXEPINT_INTKNTXFEMP		BIT(4)
+#define DXEPINT_OUTTKNEPDIS		BIT(4)
+#define DXEPINT_TIMEOUT			BIT(3)
+#define DXEPINT_SETUP			BIT(3)
+#define DXEPINT_AHBERR			BIT(2)
+#define DXEPINT_EPDISBLD		BIT(1)
+#define DXEPINT_XFERCOMPL		BIT(0)
+
+#define DIEPTSIZ0			HSOTG_REG(0x910)
+#define DIEPTSIZ0_PKTCNT_MASK		(0x3 << 19)
+#define DIEPTSIZ0_PKTCNT_SHIFT		19
+#define DIEPTSIZ0_PKTCNT_LIMIT		0x3
+#define DIEPTSIZ0_PKTCNT(_x)		((_x) << 19)
+#define DIEPTSIZ0_XFERSIZE_MASK		(0x7f << 0)
+#define DIEPTSIZ0_XFERSIZE_SHIFT	0
+#define DIEPTSIZ0_XFERSIZE_LIMIT	0x7f
+#define DIEPTSIZ0_XFERSIZE(_x)		((_x) << 0)
+
+#define DOEPTSIZ0			HSOTG_REG(0xB10)
+#define DOEPTSIZ0_SUPCNT_MASK		(0x3 << 29)
+#define DOEPTSIZ0_SUPCNT_SHIFT		29
+#define DOEPTSIZ0_SUPCNT_LIMIT		0x3
+#define DOEPTSIZ0_SUPCNT(_x)		((_x) << 29)
+#define DOEPTSIZ0_PKTCNT		BIT(19)
+#define DOEPTSIZ0_XFERSIZE_MASK		(0x7f << 0)
+#define DOEPTSIZ0_XFERSIZE_SHIFT	0
+
+#define DIEPTSIZ(_a)			HSOTG_REG(0x910 + ((_a) * 0x20))
+#define DOEPTSIZ(_a)			HSOTG_REG(0xB10 + ((_a) * 0x20))
+#define DXEPTSIZ_MC_MASK		(0x3 << 29)
+#define DXEPTSIZ_MC_SHIFT		29
+#define DXEPTSIZ_MC_LIMIT		0x3
+#define DXEPTSIZ_MC(_x)			((_x) << 29)
+#define DXEPTSIZ_PKTCNT_MASK		(0x3ff << 19)
+#define DXEPTSIZ_PKTCNT_SHIFT		19
+#define DXEPTSIZ_PKTCNT_LIMIT		0x3ff
+#define DXEPTSIZ_PKTCNT_GET(_v)		(((_v) >> 19) & 0x3ff)
+#define DXEPTSIZ_PKTCNT(_x)		((_x) << 19)
+#define DXEPTSIZ_XFERSIZE_MASK		(0x7ffff << 0)
+#define DXEPTSIZ_XFERSIZE_SHIFT		0
+#define DXEPTSIZ_XFERSIZE_LIMIT		0x7ffff
+#define DXEPTSIZ_XFERSIZE_GET(_v)	(((_v) >> 0) & 0x7ffff)
+#define DXEPTSIZ_XFERSIZE(_x)		((_x) << 0)
+
+#define DIEPDMA(_a)			HSOTG_REG(0x914 + ((_a) * 0x20))
+#define DOEPDMA(_a)			HSOTG_REG(0xB14 + ((_a) * 0x20))
+
+#define DTXFSTS(_a)			HSOTG_REG(0x918 + ((_a) * 0x20))
+
+#define PCGCTL				HSOTG_REG(0x0e00)
+#define PCGCTL_IF_DEV_MODE		BIT(31)
+#define PCGCTL_P2HD_PRT_SPD_MASK	(0x3 << 29)
+#define PCGCTL_P2HD_PRT_SPD_SHIFT	29
+#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK	(0x3 << 27)
+#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT	27
+#define PCGCTL_MAC_DEV_ADDR_MASK	(0x7f << 20)
+#define PCGCTL_MAC_DEV_ADDR_SHIFT	20
+#define PCGCTL_MAX_TERMSEL		BIT(19)
+#define PCGCTL_MAX_XCVRSELECT_MASK	(0x3 << 17)
+#define PCGCTL_MAX_XCVRSELECT_SHIFT	17
+#define PCGCTL_PORT_POWER		BIT(16)
+#define PCGCTL_PRT_CLK_SEL_MASK		(0x3 << 14)
+#define PCGCTL_PRT_CLK_SEL_SHIFT	14
+#define PCGCTL_ESS_REG_RESTORED		BIT(13)
+#define PCGCTL_EXTND_HIBER_SWITCH	BIT(12)
+#define PCGCTL_EXTND_HIBER_PWRCLMP	BIT(11)
+#define PCGCTL_ENBL_EXTND_HIBER		BIT(10)
+#define PCGCTL_RESTOREMODE		BIT(9)
+#define PCGCTL_RESETAFTSUSP		BIT(8)
+#define PCGCTL_DEEP_SLEEP		BIT(7)
+#define PCGCTL_PHY_IN_SLEEP		BIT(6)
+#define PCGCTL_ENBL_SLEEP_GATING	BIT(5)
+#define PCGCTL_RSTPDWNMODULE		BIT(3)
+#define PCGCTL_PWRCLMP			BIT(2)
+#define PCGCTL_GATEHCLK			BIT(1)
+#define PCGCTL_STOPPCLK			BIT(0)
+
+#define PCGCCTL1                        HSOTG_REG(0xe04)
+#define PCGCCTL1_TIMER                  (0x3 << 1)
+#define PCGCCTL1_GATEEN                 BIT(0)
+
+#define EPFIFO(_a)			HSOTG_REG(0x1000 + ((_a) * 0x1000))
+
+/* Host Mode Registers */
+
+#define HCFG				HSOTG_REG(0x0400)
+#define HCFG_MODECHTIMEN		BIT(31)
+#define HCFG_PERSCHEDENA		BIT(26)
+#define HCFG_FRLISTEN_MASK		(0x3 << 24)
+#define HCFG_FRLISTEN_SHIFT		24
+#define HCFG_FRLISTEN_8				(0 << 24)
+#define FRLISTEN_8_SIZE				8
+#define HCFG_FRLISTEN_16			BIT(24)
+#define FRLISTEN_16_SIZE			16
+#define HCFG_FRLISTEN_32			(2 << 24)
+#define FRLISTEN_32_SIZE			32
+#define HCFG_FRLISTEN_64			(3 << 24)
+#define FRLISTEN_64_SIZE			64
+#define HCFG_DESCDMA			BIT(23)
+#define HCFG_RESVALID_MASK		(0xff << 8)
+#define HCFG_RESVALID_SHIFT		8
+#define HCFG_ENA32KHZ			BIT(7)
+#define HCFG_FSLSSUPP			BIT(2)
+#define HCFG_FSLSPCLKSEL_MASK		(0x3 << 0)
+#define HCFG_FSLSPCLKSEL_SHIFT		0
+#define HCFG_FSLSPCLKSEL_30_60_MHZ	0
+#define HCFG_FSLSPCLKSEL_48_MHZ		1
+#define HCFG_FSLSPCLKSEL_6_MHZ		2
+
+#define HFIR				HSOTG_REG(0x0404)
+#define HFIR_FRINT_MASK			(0xffff << 0)
+#define HFIR_FRINT_SHIFT		0
+#define HFIR_RLDCTRL			BIT(16)
+
+#define HFNUM				HSOTG_REG(0x0408)
+#define HFNUM_FRREM_MASK		(0xffff << 16)
+#define HFNUM_FRREM_SHIFT		16
+#define HFNUM_FRNUM_MASK		(0xffff << 0)
+#define HFNUM_FRNUM_SHIFT		0
+#define HFNUM_MAX_FRNUM			0x3fff
+
+#define HPTXSTS				HSOTG_REG(0x0410)
+#define TXSTS_QTOP_ODD			BIT(31)
+#define TXSTS_QTOP_CHNEP_MASK		(0xf << 27)
+#define TXSTS_QTOP_CHNEP_SHIFT		27
+#define TXSTS_QTOP_TOKEN_MASK		(0x3 << 25)
+#define TXSTS_QTOP_TOKEN_SHIFT		25
+#define TXSTS_QTOP_TERMINATE		BIT(24)
+#define TXSTS_QSPCAVAIL_MASK		(0xff << 16)
+#define TXSTS_QSPCAVAIL_SHIFT		16
+#define TXSTS_FSPCAVAIL_MASK		(0xffff << 0)
+#define TXSTS_FSPCAVAIL_SHIFT		0
+
+#define HAINT				HSOTG_REG(0x0414)
+#define HAINTMSK			HSOTG_REG(0x0418)
+#define HFLBADDR			HSOTG_REG(0x041c)
+
+#define HPRT0				HSOTG_REG(0x0440)
+#define HPRT0_SPD_MASK			(0x3 << 17)
+#define HPRT0_SPD_SHIFT			17
+#define HPRT0_SPD_HIGH_SPEED		0
+#define HPRT0_SPD_FULL_SPEED		1
+#define HPRT0_SPD_LOW_SPEED		2
+#define HPRT0_TSTCTL_MASK		(0xf << 13)
+#define HPRT0_TSTCTL_SHIFT		13
+#define HPRT0_PWR			BIT(12)
+#define HPRT0_LNSTS_MASK		(0x3 << 10)
+#define HPRT0_LNSTS_SHIFT		10
+#define HPRT0_RST			BIT(8)
+#define HPRT0_SUSP			BIT(7)
+#define HPRT0_RES			BIT(6)
+#define HPRT0_OVRCURRCHG		BIT(5)
+#define HPRT0_OVRCURRACT		BIT(4)
+#define HPRT0_ENACHG			BIT(3)
+#define HPRT0_ENA			BIT(2)
+#define HPRT0_CONNDET			BIT(1)
+#define HPRT0_CONNSTS			BIT(0)
+
+#define HCCHAR(_ch)			HSOTG_REG(0x0500 + 0x20 * (_ch))
+#define HCCHAR_CHENA			BIT(31)
+#define HCCHAR_CHDIS			BIT(30)
+#define HCCHAR_ODDFRM			BIT(29)
+#define HCCHAR_DEVADDR_MASK		(0x7f << 22)
+#define HCCHAR_DEVADDR_SHIFT		22
+#define HCCHAR_MULTICNT_MASK		(0x3 << 20)
+#define HCCHAR_MULTICNT_SHIFT		20
+#define HCCHAR_EPTYPE_MASK		(0x3 << 18)
+#define HCCHAR_EPTYPE_SHIFT		18
+#define HCCHAR_LSPDDEV			BIT(17)
+#define HCCHAR_EPDIR			BIT(15)
+#define HCCHAR_EPNUM_MASK		(0xf << 11)
+#define HCCHAR_EPNUM_SHIFT		11
+#define HCCHAR_MPS_MASK			(0x7ff << 0)
+#define HCCHAR_MPS_SHIFT		0
+
+#define HCSPLT(_ch)			HSOTG_REG(0x0504 + 0x20 * (_ch))
+#define HCSPLT_SPLTENA			BIT(31)
+#define HCSPLT_COMPSPLT			BIT(16)
+#define HCSPLT_XACTPOS_MASK		(0x3 << 14)
+#define HCSPLT_XACTPOS_SHIFT		14
+#define HCSPLT_XACTPOS_MID		0
+#define HCSPLT_XACTPOS_END		1
+#define HCSPLT_XACTPOS_BEGIN		2
+#define HCSPLT_XACTPOS_ALL		3
+#define HCSPLT_HUBADDR_MASK		(0x7f << 7)
+#define HCSPLT_HUBADDR_SHIFT		7
+#define HCSPLT_PRTADDR_MASK		(0x7f << 0)
+#define HCSPLT_PRTADDR_SHIFT		0
+
+#define HCINT(_ch)			HSOTG_REG(0x0508 + 0x20 * (_ch))
+#define HCINTMSK(_ch)			HSOTG_REG(0x050c + 0x20 * (_ch))
+#define HCINTMSK_RESERVED14_31		(0x3ffff << 14)
+#define HCINTMSK_FRM_LIST_ROLL		BIT(13)
+#define HCINTMSK_XCS_XACT		BIT(12)
+#define HCINTMSK_BNA			BIT(11)
+#define HCINTMSK_DATATGLERR		BIT(10)
+#define HCINTMSK_FRMOVRUN		BIT(9)
+#define HCINTMSK_BBLERR			BIT(8)
+#define HCINTMSK_XACTERR		BIT(7)
+#define HCINTMSK_NYET			BIT(6)
+#define HCINTMSK_ACK			BIT(5)
+#define HCINTMSK_NAK			BIT(4)
+#define HCINTMSK_STALL			BIT(3)
+#define HCINTMSK_AHBERR			BIT(2)
+#define HCINTMSK_CHHLTD			BIT(1)
+#define HCINTMSK_XFERCOMPL		BIT(0)
+
+#define HCTSIZ(_ch)			HSOTG_REG(0x0510 + 0x20 * (_ch))
+#define TSIZ_DOPNG			BIT(31)
+#define TSIZ_SC_MC_PID_MASK		(0x3 << 29)
+#define TSIZ_SC_MC_PID_SHIFT		29
+#define TSIZ_SC_MC_PID_DATA0		0
+#define TSIZ_SC_MC_PID_DATA2		1
+#define TSIZ_SC_MC_PID_DATA1		2
+#define TSIZ_SC_MC_PID_MDATA		3
+#define TSIZ_SC_MC_PID_SETUP		3
+#define TSIZ_PKTCNT_MASK		(0x3ff << 19)
+#define TSIZ_PKTCNT_SHIFT		19
+#define TSIZ_NTD_MASK			(0xff << 8)
+#define TSIZ_NTD_SHIFT			8
+#define TSIZ_SCHINFO_MASK		(0xff << 0)
+#define TSIZ_SCHINFO_SHIFT		0
+#define TSIZ_XFERSIZE_MASK		(0x7ffff << 0)
+#define TSIZ_XFERSIZE_SHIFT		0
+
+#define HCDMA(_ch)			HSOTG_REG(0x0514 + 0x20 * (_ch))
+
+#define HCDMAB(_ch)			HSOTG_REG(0x051c + 0x20 * (_ch))
+
+#define HCFIFO(_ch)			HSOTG_REG(0x1000 + 0x1000 * (_ch))
+
+/**
+ * struct dwc2_dma_desc - DMA descriptor structure,
+ * used for both host and gadget modes
+ *
+ * @status: DMA descriptor status quadlet
+ * @buf:    DMA descriptor data buffer pointer
+ *
+ * DMA Descriptor structure contains two quadlets:
+ * Status quadlet and Data buffer pointer.
+ */
+struct dwc2_dma_desc {
+	uint32_t status;
+	uint32_t buf;
+} __packed;
+
+/* Host Mode DMA descriptor status quadlet */
+
+#define HOST_DMA_A			BIT(31)
+#define HOST_DMA_STS_MASK		(0x3 << 28)
+#define HOST_DMA_STS_SHIFT		28
+#define HOST_DMA_STS_PKTERR		BIT(28)
+#define HOST_DMA_EOL			BIT(26)
+#define HOST_DMA_IOC			BIT(25)
+#define HOST_DMA_SUP			BIT(24)
+#define HOST_DMA_ALT_QTD		BIT(23)
+#define HOST_DMA_QTD_OFFSET_MASK	(0x3f << 17)
+#define HOST_DMA_QTD_OFFSET_SHIFT	17
+#define HOST_DMA_ISOC_NBYTES_MASK	(0xfff << 0)
+#define HOST_DMA_ISOC_NBYTES_SHIFT	0
+#define HOST_DMA_NBYTES_MASK		(0x1ffff << 0)
+#define HOST_DMA_NBYTES_SHIFT		0
+#define HOST_DMA_NBYTES_LIMIT		131071
+
+/* Device Mode DMA descriptor status quadlet */
+
+#define DEV_DMA_BUFF_STS_MASK		(0x3 << 30)
+#define DEV_DMA_BUFF_STS_SHIFT		30
+#define DEV_DMA_BUFF_STS_HREADY		0
+#define DEV_DMA_BUFF_STS_DMABUSY	1
+#define DEV_DMA_BUFF_STS_DMADONE	2
+#define DEV_DMA_BUFF_STS_HBUSY		3
+#define DEV_DMA_STS_MASK		(0x3 << 28)
+#define DEV_DMA_STS_SHIFT		28
+#define DEV_DMA_STS_SUCC		0
+#define DEV_DMA_STS_BUFF_FLUSH		1
+#define DEV_DMA_STS_BUFF_ERR		3
+#define DEV_DMA_L			BIT(27)
+#define DEV_DMA_SHORT			BIT(26)
+#define DEV_DMA_IOC			BIT(25)
+#define DEV_DMA_SR			BIT(24)
+#define DEV_DMA_MTRF			BIT(23)
+#define DEV_DMA_ISOC_PID_MASK		(0x3 << 23)
+#define DEV_DMA_ISOC_PID_SHIFT		23
+#define DEV_DMA_ISOC_PID_DATA0		0
+#define DEV_DMA_ISOC_PID_DATA2		1
+#define DEV_DMA_ISOC_PID_DATA1		2
+#define DEV_DMA_ISOC_PID_MDATA		3
+#define DEV_DMA_ISOC_FRNUM_MASK		(0x7ff << 12)
+#define DEV_DMA_ISOC_FRNUM_SHIFT	12
+#define DEV_DMA_ISOC_TX_NBYTES_MASK	(0xfff << 0)
+#define DEV_DMA_ISOC_TX_NBYTES_LIMIT	0xfff
+#define DEV_DMA_ISOC_RX_NBYTES_MASK	(0x7ff << 0)
+#define DEV_DMA_ISOC_RX_NBYTES_LIMIT	0x7ff
+#define DEV_DMA_ISOC_NBYTES_SHIFT	0
+#define DEV_DMA_NBYTES_MASK		(0xffff << 0)
+#define DEV_DMA_NBYTES_SHIFT		0
+#define DEV_DMA_NBYTES_LIMIT		0xffff
+
+#define MAX_DMA_DESC_NUM_GENERIC	64
+#define MAX_DMA_DESC_NUM_HS_ISOC	256
+
+#endif /* __DWC2_HW_H__ */
-- 
2.20.1

From: Paul Zimmerman <pauldzim@gmail.com>

Add the dwc-hsotg (dwc2) USB host controller state definitions.
Mostly based on hw/usb/hcd-ehci.h.

Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Message-id: 20200520235349.21215-4-pauldzim@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/usb/hcd-dwc2.h | 190 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 190 insertions(+)
 create mode 100644 hw/usb/hcd-dwc2.h

diff --git a/hw/usb/hcd-dwc2.h b/hw/usb/hcd-dwc2.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/usb/hcd-dwc2.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * dwc-hsotg (dwc2) USB host controller state definitions
+ *
+ * Based on hw/usb/hcd-ehci.h
+ *
+ * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef HW_USB_DWC2_H
+#define HW_USB_DWC2_H
+
+#include "qemu/timer.h"
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "hw/usb.h"
+#include "sysemu/dma.h"
+
+#define DWC2_MMIO_SIZE      0x11000
+
+#define DWC2_NB_CHAN        8       /* Number of host channels */
+#define DWC2_MAX_XFER_SIZE  65536   /* Max transfer size expected in HCTSIZ */
+
+typedef struct DWC2Packet DWC2Packet;
+typedef struct DWC2State DWC2State;
+typedef struct DWC2Class DWC2Class;
+
+enum async_state {
+    DWC2_ASYNC_NONE = 0,
+    DWC2_ASYNC_INITIALIZED,
+    DWC2_ASYNC_INFLIGHT,
+    DWC2_ASYNC_FINISHED,
+};
+
+struct DWC2Packet {
+    USBPacket packet;
+    uint32_t devadr;
+    uint32_t epnum;
+    uint32_t epdir;
+    uint32_t mps;
+    uint32_t pid;
+    uint32_t index;
+    uint32_t pcnt;
+    uint32_t len;
+    int32_t async;
+    bool small;
+    bool needs_service;
+};
+
+struct DWC2State {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
+    USBBus bus;
+    qemu_irq irq;
+    MemoryRegion *dma_mr;
+    AddressSpace dma_as;
+    MemoryRegion container;
+    MemoryRegion hsotg;
+    MemoryRegion fifos;
+
+    union {
+#define DWC2_GLBREG_SIZE    0x70
+        uint32_t glbreg[DWC2_GLBREG_SIZE / sizeof(uint32_t)];
+        struct {
+            uint32_t gotgctl;       /* 00 */
+            uint32_t gotgint;       /* 04 */
+            uint32_t gahbcfg;       /* 08 */
+            uint32_t gusbcfg;       /* 0c */
+            uint32_t grstctl;       /* 10 */
+            uint32_t gintsts;       /* 14 */
+            uint32_t gintmsk;       /* 18 */
+            uint32_t grxstsr;       /* 1c */
+            uint32_t grxstsp;       /* 20 */
+            uint32_t grxfsiz;       /* 24 */
+            uint32_t gnptxfsiz;     /* 28 */
+            uint32_t gnptxsts;      /* 2c */
+            uint32_t gi2cctl;       /* 30 */
+            uint32_t gpvndctl;      /* 34 */
+            uint32_t ggpio;         /* 38 */
+            uint32_t guid;          /* 3c */
+            uint32_t gsnpsid;       /* 40 */
+            uint32_t ghwcfg1;       /* 44 */
+            uint32_t ghwcfg2;       /* 48 */
+            uint32_t ghwcfg3;       /* 4c */
+            uint32_t ghwcfg4;       /* 50 */
+            uint32_t glpmcfg;       /* 54 */
+            uint32_t gpwrdn;        /* 58 */
+            uint32_t gdfifocfg;     /* 5c */
+            uint32_t gadpctl;       /* 60 */
+            uint32_t grefclk;       /* 64 */
+            uint32_t gintmsk2;      /* 68 */
+            uint32_t gintsts2;      /* 6c */
+        };
+    };
+
+    union {
+#define DWC2_FSZREG_SIZE    0x04
+        uint32_t fszreg[DWC2_FSZREG_SIZE / sizeof(uint32_t)];
+        struct {
+            uint32_t hptxfsiz;      /* 100 */
+        };
+    };
+
+    union {
+#define DWC2_HREG0_SIZE     0x44
+        uint32_t hreg0[DWC2_HREG0_SIZE / sizeof(uint32_t)];
+        struct {
+            uint32_t hcfg;          /* 400 */
+            uint32_t hfir;          /* 404 */
+            uint32_t hfnum;         /* 408 */
+            uint32_t rsvd0;         /* 40c */
+            uint32_t hptxsts;       /* 410 */
+            uint32_t haint;         /* 414 */
+            uint32_t haintmsk;      /* 418 */
+            uint32_t hflbaddr;      /* 41c */
+            uint32_t rsvd1[8];      /* 420-43c */
+            uint32_t hprt0;         /* 440 */
+        };
+    };
+
+#define DWC2_HREG1_SIZE     (0x20 * DWC2_NB_CHAN)
+    uint32_t hreg1[DWC2_HREG1_SIZE / sizeof(uint32_t)];
+
+#define hcchar(_ch)     hreg1[((_ch) << 3) + 0] /* 500, 520, ... */
+#define hcsplt(_ch)     hreg1[((_ch) << 3) + 1] /* 504, 524, ... */
+#define hcint(_ch)      hreg1[((_ch) << 3) + 2] /* 508, 528, ... */
+#define hcintmsk(_ch)   hreg1[((_ch) << 3) + 3] /* 50c, 52c, ... */
+#define hctsiz(_ch)     hreg1[((_ch) << 3) + 4] /* 510, 530, ... */
+#define hcdma(_ch)      hreg1[((_ch) << 3) + 5] /* 514, 534, ... */
+#define hcdmab(_ch)     hreg1[((_ch) << 3) + 7] /* 51c, 53c, ... */
+
+    union {
+#define DWC2_PCGREG_SIZE    0x08
+        uint32_t pcgreg[DWC2_PCGREG_SIZE / sizeof(uint32_t)];
+        struct {
+            uint32_t pcgctl;        /* e00 */
+            uint32_t pcgcctl1;      /* e04 */
+        };
+    };
+
+    /* TODO - implement FIFO registers for slave mode */
+#define DWC2_HFIFO_SIZE     (0x1000 * DWC2_NB_CHAN)
+
+    /*
+     *  Internal state
+     */
+    QEMUTimer *eof_timer;
+    QEMUTimer *frame_timer;
+    QEMUBH *async_bh;
+    int64_t sof_time;
+    int64_t usb_frame_time;
+    int64_t usb_bit_time;
+    uint32_t usb_version;
+    uint16_t frame_number;
+    uint16_t fi;
+    uint16_t next_chan;
+    bool working;
+    USBPort uport;
+    DWC2Packet packet[DWC2_NB_CHAN];                   /* one packet per chan */
+    uint8_t usb_buf[DWC2_NB_CHAN][DWC2_MAX_XFER_SIZE]; /* one buffer per chan */
+};
+
+struct DWC2Class {
+    /*< private >*/
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+
+    /*< public >*/
+};
+
+#define TYPE_DWC2_USB   "dwc2-usb"
+#define DWC2_USB(obj) \
+    OBJECT_CHECK(DWC2State, (obj), TYPE_DWC2_USB)
+#define DWC2_CLASS(klass) \
+    OBJECT_CLASS_CHECK(DWC2Class, (klass), TYPE_DWC2_USB)
+#define DWC2_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(DWC2Class, (obj), TYPE_DWC2_USB)
+
+#endif
-- 
2.20.1

From: Paul Zimmerman <pauldzim@gmail.com>

Add the dwc-hsotg (dwc2) USB host controller emulation code.
Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c.

Note that to use this with the dwc-otg driver in the Raspbian
kernel, you must pass the option "dwc_otg.fiq_fsm_enable=0" on
the kernel command line.

Emulation of slave mode and of descriptor-DMA mode has not been
implemented yet. These modes are seldom used.

I have used some on-line sources of information while developing
this emulation, including:

http://www.capital-micro.com/PDF/CME-M7_Family_User_Guide_EN.pdf
which has a pretty complete description of the controller starting
on page 370.

https://sourceforge.net/p/wive-ng/wive-ng-mt/ci/master/tree/docs/DataSheets/RT3050_5x_V2.0_081408_0902.pdf
which has a description of the controller registers starting on
page 130.

Thanks to Felippe Mathieu-Daude for providing a cleaner method
of implementing the memory regions for the controller registers.

Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Message-id: 20200520235349.21215-5-pauldzim@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/usb/hcd-dwc2.c    | 1417 ++++++++++++++++++++++++++++++++++++++++++
 hw/usb/Kconfig       |    5 +
 hw/usb/Makefile.objs |    1 +
 hw/usb/trace-events  |   50 ++
 4 files changed, 1473 insertions(+)
 create mode 100644 hw/usb/hcd-dwc2.c

diff --git a/hw/usb/hcd-dwc2.c b/hw/usb/hcd-dwc2.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/usb/hcd-dwc2.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * dwc-hsotg (dwc2) USB host controller emulation
+ *
+ * Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c
+ *
+ * Note that to use this emulation with the dwc-otg driver in the
+ * Raspbian kernel, you must pass the option "dwc_otg.fiq_fsm_enable=0"
+ * on the kernel command line.
+ *
+ * Some useful documentation used to develop this emulation can be
+ * found online (as of April 2020) at:
+ *
+ * http://www.capital-micro.com/PDF/CME-M7_Family_User_Guide_EN.pdf
+ * which has a pretty complete description of the controller starting
+ * on page 370.
+ *
+ * https://sourceforge.net/p/wive-ng/wive-ng-mt/ci/master/tree/docs/DataSheets/RT3050_5x_V2.0_081408_0902.pdf
+ * which has a description of the controller registers starting on
+ * page 130.
+ *
+ * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qapi/error.h"
+#include "hw/usb/dwc2-regs.h"
+#include "hw/usb/hcd-dwc2.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
+#include "hw/qdev-properties.h"
+
+#define USB_HZ_FS       12000000
+#define USB_HZ_HS       96000000
+#define USB_FRMINTVL    12000
+
+/* nifty macros from Arnon's EHCI version  */
+#define get_field(data, field) \
+    (((data) & field##_MASK) >> field##_SHIFT)
+
+#define set_field(data, newval, field) do { \
+    uint32_t val = *(data); \
+    val &= ~field##_MASK; \
+    val |= ((newval) << field##_SHIFT) & field##_MASK; \
+    *(data) = val; \
+} while (0)
+
+#define get_bit(data, bitmask) \
+    (!!((data) & (bitmask)))
+
+/* update irq line */
+static inline void dwc2_update_irq(DWC2State *s)
+{
+    static int oldlevel;
+    int level = 0;
+
+    if ((s->gintsts & s->gintmsk) && (s->gahbcfg & GAHBCFG_GLBL_INTR_EN)) {
+        level = 1;
+    }
+    if (level != oldlevel) {
+        oldlevel = level;
+        trace_usb_dwc2_update_irq(level);
+        qemu_set_irq(s->irq, level);
+    }
+}
+
+/* flag interrupt condition */
+static inline void dwc2_raise_global_irq(DWC2State *s, uint32_t intr)
+{
+    if (!(s->gintsts & intr)) {
+        s->gintsts |= intr;
+        trace_usb_dwc2_raise_global_irq(intr);
+        dwc2_update_irq(s);
+    }
+}
+
+static inline void dwc2_lower_global_irq(DWC2State *s, uint32_t intr)
+{
+    if (s->gintsts & intr) {
+        s->gintsts &= ~intr;
+        trace_usb_dwc2_lower_global_irq(intr);
+        dwc2_update_irq(s);
+    }
+}
+
+static inline void dwc2_raise_host_irq(DWC2State *s, uint32_t host_intr)
+{
+    if (!(s->haint & host_intr)) {
+        s->haint |= host_intr;
+        s->haint &= 0xffff;
+        trace_usb_dwc2_raise_host_irq(host_intr);
+        if (s->haint & s->haintmsk) {
+            dwc2_raise_global_irq(s, GINTSTS_HCHINT);
+        }
+    }
+}
+
+static inline void dwc2_lower_host_irq(DWC2State *s, uint32_t host_intr)
+{
+    if (s->haint & host_intr) {
+        s->haint &= ~host_intr;
+        trace_usb_dwc2_lower_host_irq(host_intr);
+        if (!(s->haint & s->haintmsk)) {
+            dwc2_lower_global_irq(s, GINTSTS_HCHINT);
+        }
+    }
+}
+
+static inline void dwc2_update_hc_irq(DWC2State *s, int index)
+{
+    uint32_t host_intr = 1 << (index >> 3);
+
+    if (s->hreg1[index + 2] & s->hreg1[index + 3]) {
+        dwc2_raise_host_irq(s, host_intr);
+    } else {
+        dwc2_lower_host_irq(s, host_intr);
+    }
+}
+
+/* set a timer for EOF */
+static void dwc2_eof_timer(DWC2State *s)
+{
+    timer_mod(s->eof_timer, s->sof_time + s->usb_frame_time);
+}
+
+/* Set a timer for EOF and generate SOF event */
+static void dwc2_sof(DWC2State *s)
+{
+    s->sof_time += s->usb_frame_time;
+    trace_usb_dwc2_sof(s->sof_time);
+    dwc2_eof_timer(s);
+    dwc2_raise_global_irq(s, GINTSTS_SOF);
+}
+
+/* Do frame processing on frame boundary */
+static void dwc2_frame_boundary(void *opaque)
+{
+    DWC2State *s = opaque;
+    int64_t now;
+    uint16_t frcnt;
+
+    now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+
+    /* Frame boundary, so do EOF stuff here */
+
+    /* Increment frame number */
+    frcnt = (uint16_t)((now - s->sof_time) / s->fi);
+    s->frame_number = (s->frame_number + frcnt) & 0xffff;
+    s->hfnum = s->frame_number & HFNUM_MAX_FRNUM;
+
+    /* Do SOF stuff here */
+    dwc2_sof(s);
+}
+
+/* Start sending SOF tokens on the USB bus */
+static void dwc2_bus_start(DWC2State *s)
+{
+    trace_usb_dwc2_bus_start();
+    s->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+    dwc2_eof_timer(s);
+}
+
+/* Stop sending SOF tokens on the USB bus */
+static void dwc2_bus_stop(DWC2State *s)
+{
+    trace_usb_dwc2_bus_stop();
+    timer_del(s->eof_timer);
+}
+
+static USBDevice *dwc2_find_device(DWC2State *s, uint8_t addr)
+{
+    USBDevice *dev;
+
+    trace_usb_dwc2_find_device(addr);
+
+    if (!(s->hprt0 & HPRT0_ENA)) {
+        trace_usb_dwc2_port_disabled(0);
+    } else {
+        dev = usb_find_device(&s->uport, addr);
+        if (dev != NULL) {
+            trace_usb_dwc2_device_found(0);
+            return dev;
+        }
+    }
+
+    trace_usb_dwc2_device_not_found();
+    return NULL;
+}
+
+static const char *pstatus[] = {
+    "USB_RET_SUCCESS", "USB_RET_NODEV", "USB_RET_NAK", "USB_RET_STALL",
+    "USB_RET_BABBLE", "USB_RET_IOERROR", "USB_RET_ASYNC",
+    "USB_RET_ADD_TO_QUEUE", "USB_RET_REMOVE_FROM_QUEUE"
+};
+
+static uint32_t pintr[] = {
+    HCINTMSK_XFERCOMPL, HCINTMSK_XACTERR, HCINTMSK_NAK, HCINTMSK_STALL,
+    HCINTMSK_BBLERR, HCINTMSK_XACTERR, HCINTMSK_XACTERR, HCINTMSK_XACTERR,
+    HCINTMSK_XACTERR
+};
+
+static const char *types[] = {
+    "Ctrl", "Isoc", "Bulk", "Intr"
+};
+
+static const char *dirs[] = {
+    "Out", "In"
+};
+
+static void dwc2_handle_packet(DWC2State *s, uint32_t devadr, USBDevice *dev,
+                               USBEndpoint *ep, uint32_t index, bool send)
+{
+    DWC2Packet *p;
+    uint32_t hcchar = s->hreg1[index];
+    uint32_t hctsiz = s->hreg1[index + 4];
+    uint32_t hcdma = s->hreg1[index + 5];
+    uint32_t chan, epnum, epdir, eptype, mps, pid, pcnt, len, tlen, intr = 0;
+    uint32_t tpcnt, stsidx, actual = 0;
+    bool do_intr = false, done = false;
+
+    epnum = get_field(hcchar, HCCHAR_EPNUM);
+    epdir = get_bit(hcchar, HCCHAR_EPDIR);
+    eptype = get_field(hcchar, HCCHAR_EPTYPE);
+    mps = get_field(hcchar, HCCHAR_MPS);
+    pid = get_field(hctsiz, TSIZ_SC_MC_PID);
+    pcnt = get_field(hctsiz, TSIZ_PKTCNT);
+    len = get_field(hctsiz, TSIZ_XFERSIZE);
+    assert(len <= DWC2_MAX_XFER_SIZE);
+    chan = index >> 3;
+    p = &s->packet[chan];
+
+    trace_usb_dwc2_handle_packet(chan, dev, &p->packet, epnum, types[eptype],
+                                 dirs[epdir], mps, len, pcnt);
+
+    if (eptype == USB_ENDPOINT_XFER_CONTROL && pid == TSIZ_SC_MC_PID_SETUP) {
+        pid = USB_TOKEN_SETUP;
+    } else {
+        pid = epdir ? USB_TOKEN_IN : USB_TOKEN_OUT;
+    }
+
+    if (send) {
+        tlen = len;
+        if (p->small) {
+            if (tlen > mps) {
+                tlen = mps;
+            }
+        }
+
+        if (pid != USB_TOKEN_IN) {
+            trace_usb_dwc2_memory_read(hcdma, tlen);
+            if (dma_memory_read(&s->dma_as, hcdma,
+                                s->usb_buf[chan], tlen) != MEMTX_OK) {
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: dma_memory_read failed\n",
+                              __func__);
+            }
+        }
+
+        usb_packet_init(&p->packet);
+        usb_packet_setup(&p->packet, pid, ep, 0, hcdma,
+                         pid != USB_TOKEN_IN, true);
+        usb_packet_addbuf(&p->packet, s->usb_buf[chan], tlen);
+        p->async = DWC2_ASYNC_NONE;
+        usb_handle_packet(dev, &p->packet);
+    } else {
+        tlen = p->len;
+    }
+
+    stsidx = -p->packet.status;
+    assert(stsidx < sizeof(pstatus) / sizeof(*pstatus));
+    actual = p->packet.actual_length;
+    trace_usb_dwc2_packet_status(pstatus[stsidx], actual);
+
+babble:
+    if (p->packet.status != USB_RET_SUCCESS &&
+            p->packet.status != USB_RET_NAK &&
+            p->packet.status != USB_RET_STALL &&
+            p->packet.status != USB_RET_ASYNC) {
+        trace_usb_dwc2_packet_error(pstatus[stsidx]);
+    }
+
+    if (p->packet.status == USB_RET_ASYNC) {
+        trace_usb_dwc2_async_packet(&p->packet, chan, dev, epnum,
+                                    dirs[epdir], tlen);
+        usb_device_flush_ep_queue(dev, ep);
+        assert(p->async != DWC2_ASYNC_INFLIGHT);
+        p->devadr = devadr;
+        p->epnum = epnum;
+        p->epdir = epdir;
+        p->mps = mps;
+        p->pid = pid;
+        p->index = index;
+        p->pcnt = pcnt;
+        p->len = tlen;
+        p->async = DWC2_ASYNC_INFLIGHT;
+        p->needs_service = false;
+        return;
+    }
+
+    if (p->packet.status == USB_RET_SUCCESS) {
+        if (actual > tlen) {
+            p->packet.status = USB_RET_BABBLE;
+            goto babble;
+        }
+
+        if (pid == USB_TOKEN_IN) {
+            trace_usb_dwc2_memory_write(hcdma, actual);
+            if (dma_memory_write(&s->dma_as, hcdma, s->usb_buf[chan],
+                                 actual) != MEMTX_OK) {
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: dma_memory_write failed\n",
+                              __func__);
+            }
+        }
+
+        tpcnt = actual / mps;
+        if (actual % mps) {
+            tpcnt++;
+            if (pid == USB_TOKEN_IN) {
+                done = true;
+            }
+        }
+
+        pcnt -= tpcnt < pcnt ? tpcnt : pcnt;
+        set_field(&hctsiz, pcnt, TSIZ_PKTCNT);
+        len -= actual < len ? actual : len;
+        set_field(&hctsiz, len, TSIZ_XFERSIZE);
+        s->hreg1[index + 4] = hctsiz;
+        hcdma += actual;
+        s->hreg1[index + 5] = hcdma;
+
+        if (!pcnt || len == 0 || actual == 0) {
+            done = true;
+        }
+    } else {
+        intr |= pintr[stsidx];
+        if (p->packet.status == USB_RET_NAK &&
+            (eptype == USB_ENDPOINT_XFER_CONTROL ||
+             eptype == USB_ENDPOINT_XFER_BULK)) {
+            /*
+             * for ctrl/bulk, automatically retry on NAK,
+             * but send the interrupt anyway
+             */
+            intr &= ~HCINTMSK_RESERVED14_31;
+            s->hreg1[index + 2] |= intr;
+            do_intr = true;
+        } else {
+            intr |= HCINTMSK_CHHLTD;
+            done = true;
+        }
+    }
+
+    usb_packet_cleanup(&p->packet);
+
+    if (done) {
+        hcchar &= ~HCCHAR_CHENA;
+        s->hreg1[index] = hcchar;
+        if (!(intr & HCINTMSK_CHHLTD)) {
+            intr |= HCINTMSK_CHHLTD | HCINTMSK_XFERCOMPL;
+        }
+        intr &= ~HCINTMSK_RESERVED14_31;
+        s->hreg1[index + 2] |= intr;
+        p->needs_service = false;
+        trace_usb_dwc2_packet_done(pstatus[stsidx], actual, len, pcnt);
+        dwc2_update_hc_irq(s, index);
+        return;
+    }
+
+    p->devadr = devadr;
+    p->epnum = epnum;
+    p->epdir = epdir;
+    p->mps = mps;
+    p->pid = pid;
+    p->index = index;
+    p->pcnt = pcnt;
+    p->len = len;
+    p->needs_service = true;
+    trace_usb_dwc2_packet_next(pstatus[stsidx], len, pcnt);
+    if (do_intr) {
+        dwc2_update_hc_irq(s, index);
+    }
+}
+
+/* Attach or detach a device on root hub */
+
+static const char *speeds[] = {
+    "low", "full", "high"
+};
+
+static void dwc2_attach(USBPort *port)
+{
+    DWC2State *s = port->opaque;
+    int hispd = 0;
+
+    trace_usb_dwc2_attach(port);
+    assert(port->index == 0);
+
+    if (!port->dev || !port->dev->attached) {
+        return;
+    }
+
+    assert(port->dev->speed <= USB_SPEED_HIGH);
+    trace_usb_dwc2_attach_speed(speeds[port->dev->speed]);
+    s->hprt0 &= ~HPRT0_SPD_MASK;
+
+    switch (port->dev->speed) {
+    case USB_SPEED_LOW:
+        s->hprt0 |= HPRT0_SPD_LOW_SPEED << HPRT0_SPD_SHIFT;
+        break;
+    case USB_SPEED_FULL:
+        s->hprt0 |= HPRT0_SPD_FULL_SPEED << HPRT0_SPD_SHIFT;
+        break;
+    case USB_SPEED_HIGH:
+        s->hprt0 |= HPRT0_SPD_HIGH_SPEED << HPRT0_SPD_SHIFT;
+        hispd = 1;
+        break;
+    }
+
+    if (hispd) {
+        s->usb_frame_time = NANOSECONDS_PER_SECOND / 8000;        /* 125000 */
+        if (NANOSECONDS_PER_SECOND >= USB_HZ_HS) {
+            s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_HS; /* 10.4 */
+        } else {
+            s->usb_bit_time = 1;
+        }
+    } else {
+        s->usb_frame_time = NANOSECONDS_PER_SECOND / 1000;        /* 1000000 */
+        if (NANOSECONDS_PER_SECOND >= USB_HZ_FS) {
+            s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_FS; /* 83.3 */
+        } else {
+            s->usb_bit_time = 1;
+        }
+    }
+
+    s->fi = USB_FRMINTVL - 1;
+    s->hprt0 |= HPRT0_CONNDET | HPRT0_CONNSTS;
+
+    dwc2_bus_start(s);
+    dwc2_raise_global_irq(s, GINTSTS_PRTINT);
+}
+
+static void dwc2_detach(USBPort *port)
+{
+    DWC2State *s = port->opaque;
+
+    trace_usb_dwc2_detach(port);
+    assert(port->index == 0);
+
+    dwc2_bus_stop(s);
+
+    s->hprt0 &= ~(HPRT0_SPD_MASK | HPRT0_SUSP | HPRT0_ENA | HPRT0_CONNSTS);
+    s->hprt0 |= HPRT0_CONNDET | HPRT0_ENACHG;
+
+    dwc2_raise_global_irq(s, GINTSTS_PRTINT);
+}
+
+static void dwc2_child_detach(USBPort *port, USBDevice *child)
+{
+    trace_usb_dwc2_child_detach(port, child);
+    assert(port->index == 0);
+}
+
+static void dwc2_wakeup(USBPort *port)
+{
+    DWC2State *s = port->opaque;
+
+    trace_usb_dwc2_wakeup(port);
+    assert(port->index == 0);
+
+    if (s->hprt0 & HPRT0_SUSP) {
+        s->hprt0 |= HPRT0_RES;
+        dwc2_raise_global_irq(s, GINTSTS_PRTINT);
+    }
+
+    qemu_bh_schedule(s->async_bh);
+}
+
+static void dwc2_async_packet_complete(USBPort *port, USBPacket *packet)
+{
+    DWC2State *s = port->opaque;
+    DWC2Packet *p;
+    USBDevice *dev;
+    USBEndpoint *ep;
+
+    assert(port->index == 0);
+    p = container_of(packet, DWC2Packet, packet);
+    dev = dwc2_find_device(s, p->devadr);
+    ep = usb_ep_get(dev, p->pid, p->epnum);
+    trace_usb_dwc2_async_packet_complete(port, packet, p->index >> 3, dev,
+                                         p->epnum, dirs[p->epdir], p->len);
+    assert(p->async == DWC2_ASYNC_INFLIGHT);
+
+    if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
+        usb_cancel_packet(packet);
+        usb_packet_cleanup(packet);
+        return;
+    }
+
+    dwc2_handle_packet(s, p->devadr, dev, ep, p->index, false);
+
+    p->async = DWC2_ASYNC_FINISHED;
+    qemu_bh_schedule(s->async_bh);
+}
+
+static USBPortOps dwc2_port_ops = {
+    .attach = dwc2_attach,
+    .detach = dwc2_detach,
+    .child_detach = dwc2_child_detach,
+    .wakeup = dwc2_wakeup,
+    .complete = dwc2_async_packet_complete,
+};
+
+static uint32_t dwc2_get_frame_remaining(DWC2State *s)
+{
+    uint32_t fr = 0;
+    int64_t tks;
+
+    tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->sof_time;
+    if (tks < 0) {
+        tks = 0;
+    }
+
+    /* avoid muldiv if possible */
+    if (tks >= s->usb_frame_time) {
+        goto out;
+    }
+    if (tks < s->usb_bit_time) {
+        fr = s->fi;
+        goto out;
+    }
+
+    /* tks = number of ns since SOF, divided by 83 (fs) or 10 (hs) */
+    tks = tks / s->usb_bit_time;
+    if (tks >= (int64_t)s->fi) {
+        goto out;
+    }
+
+    /* remaining = frame interval minus tks */
+    fr = (uint32_t)((int64_t)s->fi - tks);
+
+out:
+    return fr;
+}
+
+static void dwc2_work_bh(void *opaque)
+{
+    DWC2State *s = opaque;
+    DWC2Packet *p;
+    USBDevice *dev;
+    USBEndpoint *ep;
+    int64_t t_now, expire_time;
+    int chan;
+    bool found = false;
+
+    trace_usb_dwc2_work_bh();
+    if (s->working) {
+        return;
+    }
+    s->working = true;
+
+    t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+    chan = s->next_chan;
+
+    do {
+        p = &s->packet[chan];
+        if (p->needs_service) {
+            dev = dwc2_find_device(s, p->devadr);
+            ep = usb_ep_get(dev, p->pid, p->epnum);
+            trace_usb_dwc2_work_bh_service(s->next_chan, chan, dev, p->epnum);
+            dwc2_handle_packet(s, p->devadr, dev, ep, p->index, true);
+            found = true;
+        }
+        if (++chan == DWC2_NB_CHAN) {
+            chan = 0;
+        }
+        if (found) {
+            s->next_chan = chan;
+            trace_usb_dwc2_work_bh_next(chan);
+        }
+    } while (chan != s->next_chan);
+
+    if (found) {
+        expire_time = t_now + NANOSECONDS_PER_SECOND / 4000;
+        timer_mod(s->frame_timer, expire_time);
+    }
+    s->working = false;
+}
+
+static void dwc2_enable_chan(DWC2State *s,  uint32_t index)
+{
+    USBDevice *dev;
+    USBEndpoint *ep;
+    uint32_t hcchar;
+    uint32_t hctsiz;
+    uint32_t devadr, epnum, epdir, eptype, pid, len;
+    DWC2Packet *p;
+
+    assert((index >> 3) < DWC2_NB_CHAN);
+    p = &s->packet[index >> 3];
+    hcchar = s->hreg1[index];
+    hctsiz = s->hreg1[index + 4];
+    devadr = get_field(hcchar, HCCHAR_DEVADDR);
+    epnum = get_field(hcchar, HCCHAR_EPNUM);
+    epdir = get_bit(hcchar, HCCHAR_EPDIR);
+    eptype = get_field(hcchar, HCCHAR_EPTYPE);
+    pid = get_field(hctsiz, TSIZ_SC_MC_PID);
+    len = get_field(hctsiz, TSIZ_XFERSIZE);
+
+    dev = dwc2_find_device(s, devadr);
+
+    trace_usb_dwc2_enable_chan(index >> 3, dev, &p->packet, epnum);
+    if (dev == NULL) {
+        return;
+    }
+
+    if (eptype == USB_ENDPOINT_XFER_CONTROL && pid == TSIZ_SC_MC_PID_SETUP) {
+        pid = USB_TOKEN_SETUP;
+    } else {
+        pid = epdir ? USB_TOKEN_IN : USB_TOKEN_OUT;
+    }
+
+    ep = usb_ep_get(dev, pid, epnum);
+
+    /*
+     * Hack: Networking doesn't like us delivering large transfers, it kind
+     * of works but the latency is horrible. So if the transfer is <= the mtu
+     * size, we take that as a hint that this might be a network transfer,
+     * and do the transfer packet-by-packet.
+     */
+    if (len > 1536) {
+        p->small = false;
+    } else {
+        p->small = true;
+    }
+
+    dwc2_handle_packet(s, devadr, dev, ep, index, true);
+    qemu_bh_schedule(s->async_bh);
+}
+
+static const char *glbregnm[] = {
+    "GOTGCTL  ", "GOTGINT  ", "GAHBCFG  ", "GUSBCFG  ", "GRSTCTL  ",
+    "GINTSTS  ", "GINTMSK  ", "GRXSTSR  ", "GRXSTSP  ", "GRXFSIZ  ",
+    "GNPTXFSIZ", "GNPTXSTS ", "GI2CCTL  ", "GPVNDCTL ", "GGPIO    ",
+    "GUID     ", "GSNPSID  ", "GHWCFG1  ", "GHWCFG2  ", "GHWCFG3  ",
+    "GHWCFG4  ", "GLPMCFG  ", "GPWRDN   ", "GDFIFOCFG", "GADPCTL  ",
+    "GREFCLK  ", "GINTMSK2 ", "GINTSTS2 "
+};
+
+static uint64_t dwc2_glbreg_read(void *ptr, hwaddr addr, int index,
+                                 unsigned size)
+{
+    DWC2State *s = ptr;
+    uint32_t val;
+
+    assert(addr <= GINTSTS2);
+    val = s->glbreg[index];
+
+    switch (addr) {
+    case GRSTCTL:
+        /* clear any self-clearing bits that were set */
+        val &= ~(GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH | GRSTCTL_IN_TKNQ_FLSH |
+                 GRSTCTL_FRMCNTRRST | GRSTCTL_HSFTRST | GRSTCTL_CSFTRST);
+        s->glbreg[index] = val;
+        break;
+    default:
+        break;
+    }
+
+    trace_usb_dwc2_glbreg_read(addr, glbregnm[index], val);
+    return val;
+}
+
+static void dwc2_glbreg_write(void *ptr, hwaddr addr, int index, uint64_t val,
+                              unsigned size)
+{
+    DWC2State *s = ptr;
+    uint64_t orig = val;
+    uint32_t *mmio;
+    uint32_t old;
+    int iflg = 0;
+
+    assert(addr <= GINTSTS2);
+    mmio = &s->glbreg[index];
+    old = *mmio;
+
+    switch (addr) {
+    case GOTGCTL:
+        /* don't allow setting of read-only bits */
+        val &= ~(GOTGCTL_MULT_VALID_BC_MASK | GOTGCTL_BSESVLD |
+                 GOTGCTL_ASESVLD | GOTGCTL_DBNC_SHORT | GOTGCTL_CONID_B |
+                 GOTGCTL_HSTNEGSCS | GOTGCTL_SESREQSCS);
+        /* don't allow clearing of read-only bits */
+        val |= old & (GOTGCTL_MULT_VALID_BC_MASK | GOTGCTL_BSESVLD |
+                      GOTGCTL_ASESVLD | GOTGCTL_DBNC_SHORT | GOTGCTL_CONID_B |
+                      GOTGCTL_HSTNEGSCS | GOTGCTL_SESREQSCS);
+        break;
+    case GAHBCFG:
+        if ((val & GAHBCFG_GLBL_INTR_EN) && !(old & GAHBCFG_GLBL_INTR_EN)) {
+            iflg = 1;
+        }
+        break;
+    case GRSTCTL:
+        val |= GRSTCTL_AHBIDLE;
+        val &= ~GRSTCTL_DMAREQ;
+        if (!(old & GRSTCTL_TXFFLSH) && (val & GRSTCTL_TXFFLSH)) {
+                /* TODO - TX fifo flush */
+            qemu_log_mask(LOG_UNIMP, "Tx FIFO flush not implemented\n");
+        }
+        if (!(old & GRSTCTL_RXFFLSH) && (val & GRSTCTL_RXFFLSH)) {
+                /* TODO - RX fifo flush */
+            qemu_log_mask(LOG_UNIMP, "Rx FIFO flush not implemented\n");
+        }
+        if (!(old & GRSTCTL_IN_TKNQ_FLSH) && (val & GRSTCTL_IN_TKNQ_FLSH)) {
+                /* TODO - device IN token queue flush */
+            qemu_log_mask(LOG_UNIMP, "Token queue flush not implemented\n");
+        }
+        if (!(old & GRSTCTL_FRMCNTRRST) && (val & GRSTCTL_FRMCNTRRST)) {
+                /* TODO - host frame counter reset */
+            qemu_log_mask(LOG_UNIMP, "Frame counter reset not implemented\n");
+        }
+        if (!(old & GRSTCTL_HSFTRST) && (val & GRSTCTL_HSFTRST)) {
+                /* TODO - host soft reset */
+            qemu_log_mask(LOG_UNIMP, "Host soft reset not implemented\n");
+        }
+        if (!(old & GRSTCTL_CSFTRST) && (val & GRSTCTL_CSFTRST)) {
+                /* TODO - core soft reset */
+            qemu_log_mask(LOG_UNIMP, "Core soft reset not implemented\n");
+        }
+        /* don't allow clearing of self-clearing bits */
+        val |= old & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH |
+                      GRSTCTL_IN_TKNQ_FLSH | GRSTCTL_FRMCNTRRST |
+                      GRSTCTL_HSFTRST | GRSTCTL_CSFTRST);
+        break;
+    case GINTSTS:
+        /* clear the write-1-to-clear bits */
+        val |= ~old;
+        val = ~val;
+        /* don't allow clearing of read-only bits */
+        val |= old & (GINTSTS_PTXFEMP | GINTSTS_HCHINT | GINTSTS_PRTINT |
+                      GINTSTS_OEPINT | GINTSTS_IEPINT | GINTSTS_GOUTNAKEFF |
+                      GINTSTS_GINNAKEFF | GINTSTS_NPTXFEMP | GINTSTS_RXFLVL |
+                      GINTSTS_OTGINT | GINTSTS_CURMODE_HOST);
+        iflg = 1;
+        break;
+    case GINTMSK:
+        iflg = 1;
+        break;
+    default:
+        break;
+    }
+
+    trace_usb_dwc2_glbreg_write(addr, glbregnm[index], orig, old, val);
+    *mmio = val;
+
+    if (iflg) {
+        dwc2_update_irq(s);
+    }
+}
+
+static uint64_t dwc2_fszreg_read(void *ptr, hwaddr addr, int index,
+                                 unsigned size)
+{
+    DWC2State *s = ptr;
+    uint32_t val;
+
+    assert(addr == HPTXFSIZ);
+    val = s->fszreg[index];
+
+    trace_usb_dwc2_fszreg_read(addr, val);
+    return val;
+}
+
+static void dwc2_fszreg_write(void *ptr, hwaddr addr, int index, uint64_t val,
+                              unsigned size)
+{
+    DWC2State *s = ptr;
+    uint64_t orig = val;
+    uint32_t *mmio;
+    uint32_t old;
+
+    assert(addr == HPTXFSIZ);
+    mmio = &s->fszreg[index];
+    old = *mmio;
+
+    trace_usb_dwc2_fszreg_write(addr, orig, old, val);
+    *mmio = val;
+}
+
+static const char *hreg0nm[] = {
+    "HCFG     ", "HFIR     ", "HFNUM    ", "<rsvd>   ", "HPTXSTS  ",
+    "HAINT    ", "HAINTMSK ", "HFLBADDR ", "<rsvd>   ", "<rsvd>   ",
+    "<rsvd>   ", "<rsvd>   ", "<rsvd>   ", "<rsvd>   ", "<rsvd>   ",
+    "<rsvd>   ", "HPRT0    "
+};
+
+static uint64_t dwc2_hreg0_read(void *ptr, hwaddr addr, int index,
+                                unsigned size)
+{
+    DWC2State *s = ptr;
+    uint32_t val;
+
+    assert(addr >= HCFG && addr <= HPRT0);
+    val = s->hreg0[index];
+
+    switch (addr) {
+    case HFNUM:
+        val = (dwc2_get_frame_remaining(s) << HFNUM_FRREM_SHIFT) |
+              (s->hfnum << HFNUM_FRNUM_SHIFT);
+        break;
+    default:
+        break;
+    }
+
+    trace_usb_dwc2_hreg0_read(addr, hreg0nm[index], val);
+    return val;
+}
+
+static void dwc2_hreg0_write(void *ptr, hwaddr addr, int index, uint64_t val,
+                             unsigned size)
+{
+    DWC2State *s = ptr;
+    USBDevice *dev = s->uport.dev;
+    uint64_t orig = val;
+    uint32_t *mmio;
+    uint32_t tval, told, old;
+    int prst = 0;
+    int iflg = 0;
+
+    assert(addr >= HCFG && addr <= HPRT0);
+    mmio = &s->hreg0[index];
+    old = *mmio;
+
+    switch (addr) {
+    case HFIR:
+        break;
+    case HFNUM:
+    case HPTXSTS:
+    case HAINT:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: write to read-only register\n",
+                      __func__);
+        return;
+    case HAINTMSK:
+        val &= 0xffff;
+        break;
+    case HPRT0:
+        /* don't allow clearing of read-only bits */
+        val |= old & (HPRT0_SPD_MASK | HPRT0_LNSTS_MASK | HPRT0_OVRCURRACT |
+                      HPRT0_CONNSTS);
+        /* don't allow clearing of self-clearing bits */
+        val |= old & (HPRT0_SUSP | HPRT0_RES);
+        /* don't allow setting of self-setting bits */
+        if (!(old & HPRT0_ENA) && (val & HPRT0_ENA)) {
+            val &= ~HPRT0_ENA;
+        }
+        /* clear the write-1-to-clear bits */
+        tval = val & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
+                      HPRT0_CONNDET);
+        told = old & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
+                      HPRT0_CONNDET);
+        tval |= ~told;
+        tval = ~tval;
+        tval &= (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
+                 HPRT0_CONNDET);
+        val &= ~(HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
+                 HPRT0_CONNDET);
+        val |= tval;
+        if (!(val & HPRT0_RST) && (old & HPRT0_RST)) {
+            if (dev && dev->attached) {
+                val |= HPRT0_ENA | HPRT0_ENACHG;
+                prst = 1;
+            }
+        }
+        if (val & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_CONNDET)) {
+            iflg = 1;
+        } else {
+            iflg = -1;
+        }
+        break;
+    default:
+        break;
+    }
+
+    if (prst) {
+        trace_usb_dwc2_hreg0_write(addr, hreg0nm[index], orig, old,
+                                   val & ~HPRT0_CONNDET);
+        trace_usb_dwc2_hreg0_action("call usb_port_reset");
+        usb_port_reset(&s->uport);
+        val &= ~HPRT0_CONNDET;
+    } else {
+        trace_usb_dwc2_hreg0_write(addr, hreg0nm[index], orig, old, val);
+    }
+
+    *mmio = val;
+
+    if (iflg > 0) {
+        trace_usb_dwc2_hreg0_action("enable PRTINT");
+        dwc2_raise_global_irq(s, GINTSTS_PRTINT);
+    } else if (iflg < 0) {
+        trace_usb_dwc2_hreg0_action("disable PRTINT");
+        dwc2_lower_global_irq(s, GINTSTS_PRTINT);
+    }
+}
+
+static const char *hreg1nm[] = {
+    "HCCHAR  ", "HCSPLT  ", "HCINT   ", "HCINTMSK", "HCTSIZ  ", "HCDMA   ",
+    "<rsvd>  ", "HCDMAB  "
+};
+
+static uint64_t dwc2_hreg1_read(void *ptr, hwaddr addr, int index,
+                                unsigned size)
+{
+    DWC2State *s = ptr;
+    uint32_t val;
+
+    assert(addr >= HCCHAR(0) && addr <= HCDMAB(DWC2_NB_CHAN - 1));
+    val = s->hreg1[index];
+
+    trace_usb_dwc2_hreg1_read(addr, hreg1nm[index & 7], addr >> 5, val);
+    return val;
+}
+
+static void dwc2_hreg1_write(void *ptr, hwaddr addr, int index, uint64_t val,
+                             unsigned size)
+{
+    DWC2State *s = ptr;
+    uint64_t orig = val;
+    uint32_t *mmio;
+    uint32_t old;
+    int iflg = 0;
+    int enflg = 0;
+    int disflg = 0;
+
+    assert(addr >= HCCHAR(0) && addr <= HCDMAB(DWC2_NB_CHAN - 1));
+    mmio = &s->hreg1[index];
+    old = *mmio;
+
+    switch (HSOTG_REG(0x500) + (addr & 0x1c)) {
+    case HCCHAR(0):
+        if ((val & HCCHAR_CHDIS) && !(old & HCCHAR_CHDIS)) {
+            val &= ~(HCCHAR_CHENA | HCCHAR_CHDIS);
+            disflg = 1;
+        } else {
+            val |= old & HCCHAR_CHDIS;
+            if ((val & HCCHAR_CHENA) && !(old & HCCHAR_CHENA)) {
+                val &= ~HCCHAR_CHDIS;
+                enflg = 1;
+            } else {
+                val |= old & HCCHAR_CHENA;
+            }
+        }
+        break;
+    case HCINT(0):
+        /* clear the write-1-to-clear bits */
+        val |= ~old;
+        val = ~val;
+        val &= ~HCINTMSK_RESERVED14_31;
+        iflg = 1;
+        break;
+    case HCINTMSK(0):
+        val &= ~HCINTMSK_RESERVED14_31;
+        iflg = 1;
+        break;
+    case HCDMAB(0):
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: write to read-only register\n",
+                      __func__);
+        return;
+    default:
+        break;
+    }
+
+    trace_usb_dwc2_hreg1_write(addr, hreg1nm[index & 7], index >> 3, orig,
+                               old, val);
+    *mmio = val;
+
+    if (disflg) {
+        /* set ChHltd in HCINT */
+        s->hreg1[(index & ~7) + 2] |= HCINTMSK_CHHLTD;
+        iflg = 1;
+    }
+
+    if (enflg) {
+        dwc2_enable_chan(s, index & ~7);
+    }
+
+    if (iflg) {
+        dwc2_update_hc_irq(s, index & ~7);
+    }
+}
+
+static const char *pcgregnm[] = {
+        "PCGCTL   ", "PCGCCTL1 "
+};
+
+static uint64_t dwc2_pcgreg_read(void *ptr, hwaddr addr, int index,
+                                 unsigned size)
+{
+    DWC2State *s = ptr;
+    uint32_t val;
+
+    assert(addr >= PCGCTL && addr <= PCGCCTL1);
+    val = s->pcgreg[index];
+
+    trace_usb_dwc2_pcgreg_read(addr, pcgregnm[index], val);
+    return val;
+}
+
+static void dwc2_pcgreg_write(void *ptr, hwaddr addr, int index,
+                              uint64_t val, unsigned size)
+{
+    DWC2State *s = ptr;
+    uint64_t orig = val;
+    uint32_t *mmio;
+    uint32_t old;
+
+    assert(addr >= PCGCTL && addr <= PCGCCTL1);
+    mmio = &s->pcgreg[index];
+    old = *mmio;
+
+    trace_usb_dwc2_pcgreg_write(addr, pcgregnm[index], orig, old, val);
+    *mmio = val;
+}
+
+static uint64_t dwc2_hsotg_read(void *ptr, hwaddr addr, unsigned size)
+{
+    uint64_t val;
+
+    switch (addr) {
+    case HSOTG_REG(0x000) ... HSOTG_REG(0x0fc):
+        val = dwc2_glbreg_read(ptr, addr, (addr - HSOTG_REG(0x000)) >> 2, size);
+        break;
+    case HSOTG_REG(0x100):
+        val = dwc2_fszreg_read(ptr, addr, (addr - HSOTG_REG(0x100)) >> 2, size);
+        break;
+    case HSOTG_REG(0x104) ... HSOTG_REG(0x3fc):
+        /* Gadget-mode registers, just return 0 for now */
+        val = 0;
+        break;
+    case HSOTG_REG(0x400) ... HSOTG_REG(0x4fc):
+        val = dwc2_hreg0_read(ptr, addr, (addr - HSOTG_REG(0x400)) >> 2, size);
+        break;
+    case HSOTG_REG(0x500) ... HSOTG_REG(0x7fc):
+        val = dwc2_hreg1_read(ptr, addr, (addr - HSOTG_REG(0x500)) >> 2, size);
+        break;
+    case HSOTG_REG(0x800) ... HSOTG_REG(0xdfc):
+        /* Gadget-mode registers, just return 0 for now */
+        val = 0;
+        break;
+    case HSOTG_REG(0xe00) ... HSOTG_REG(0xffc):
+        val = dwc2_pcgreg_read(ptr, addr, (addr - HSOTG_REG(0xe00)) >> 2, size);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    return val;
+}
+
+static void dwc2_hsotg_write(void *ptr, hwaddr addr, uint64_t val,
+                             unsigned size)
+{
+    switch (addr) {
+    case HSOTG_REG(0x000) ... HSOTG_REG(0x0fc):
+        dwc2_glbreg_write(ptr, addr, (addr - HSOTG_REG(0x000)) >> 2, val, size);
+        break;
+    case HSOTG_REG(0x100):
+        dwc2_fszreg_write(ptr, addr, (addr - HSOTG_REG(0x100)) >> 2, val, size);
+        break;
+    case HSOTG_REG(0x104) ... HSOTG_REG(0x3fc):
+        /* Gadget-mode registers, do nothing for now */
+        break;
+    case HSOTG_REG(0x400) ... HSOTG_REG(0x4fc):
+        dwc2_hreg0_write(ptr, addr, (addr - HSOTG_REG(0x400)) >> 2, val, size);
+        break;
+    case HSOTG_REG(0x500) ... HSOTG_REG(0x7fc):
+        dwc2_hreg1_write(ptr, addr, (addr - HSOTG_REG(0x500)) >> 2, val, size);
+        break;
+    case HSOTG_REG(0x800) ... HSOTG_REG(0xdfc):
+        /* Gadget-mode registers, do nothing for now */
+        break;
+    case HSOTG_REG(0xe00) ... HSOTG_REG(0xffc):
+        dwc2_pcgreg_write(ptr, addr, (addr - HSOTG_REG(0xe00)) >> 2, val, size);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static const MemoryRegionOps dwc2_mmio_hsotg_ops = {
+    .read = dwc2_hsotg_read,
+    .write = dwc2_hsotg_write,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static uint64_t dwc2_hreg2_read(void *ptr, hwaddr addr, unsigned size)
+{
+    /* TODO - implement FIFOs to support slave mode */
+    trace_usb_dwc2_hreg2_read(addr, addr >> 12, 0);
+    qemu_log_mask(LOG_UNIMP, "FIFO read not implemented\n");
+    return 0;
+}
+
+static void dwc2_hreg2_write(void *ptr, hwaddr addr, uint64_t val,
+                             unsigned size)
+{
+    uint64_t orig = val;
+
+    /* TODO - implement FIFOs to support slave mode */
+    trace_usb_dwc2_hreg2_write(addr, addr >> 12, orig, 0, val);
+    qemu_log_mask(LOG_UNIMP, "FIFO write not implemented\n");
+}
+
+static const MemoryRegionOps dwc2_mmio_hreg2_ops = {
+    .read = dwc2_hreg2_read,
+    .write = dwc2_hreg2_write,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void dwc2_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
+                                 unsigned int stream)
+{
+    DWC2State *s = container_of(bus, DWC2State, bus);
+
+    trace_usb_dwc2_wakeup_endpoint(ep, stream);
+
+    /* TODO - do something here? */
+    qemu_bh_schedule(s->async_bh);
+}
+
+static USBBusOps dwc2_bus_ops = {
+    .wakeup_endpoint = dwc2_wakeup_endpoint,
+};
+
+static void dwc2_work_timer(void *opaque)
+{
+    DWC2State *s = opaque;
+
+    trace_usb_dwc2_work_timer();
+    qemu_bh_schedule(s->async_bh);
+}
+
+static void dwc2_reset_enter(Object *obj, ResetType type)
+{
+    DWC2Class *c = DWC2_GET_CLASS(obj);
+    DWC2State *s = DWC2_USB(obj);
+    int i;
+
+    trace_usb_dwc2_reset_enter();
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    timer_del(s->frame_timer);
+    qemu_bh_cancel(s->async_bh);
+
+    if (s->uport.dev && s->uport.dev->attached) {
+        usb_detach(&s->uport);
+    }
+
+    dwc2_bus_stop(s);
+
+    s->gotgctl = GOTGCTL_BSESVLD | GOTGCTL_ASESVLD | GOTGCTL_CONID_B;
+    s->gotgint = 0;
+    s->gahbcfg = 0;
+    s->gusbcfg = 5 << GUSBCFG_USBTRDTIM_SHIFT;
+    s->grstctl = GRSTCTL_AHBIDLE;
+    s->gintsts = GINTSTS_CONIDSTSCHNG | GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP |
+                 GINTSTS_CURMODE_HOST;
+    s->gintmsk = 0;
+    s->grxstsr = 0;
+    s->grxstsp = 0;
+    s->grxfsiz = 1024;
+    s->gnptxfsiz = 1024 << FIFOSIZE_DEPTH_SHIFT;
+    s->gnptxsts = (4 << FIFOSIZE_DEPTH_SHIFT) | 1024;
+    s->gi2cctl = GI2CCTL_I2CDATSE0 | GI2CCTL_ACK;
+    s->gpvndctl = 0;
+    s->ggpio = 0;
+    s->guid = 0;
+    s->gsnpsid = 0x4f54294a;
+    s->ghwcfg1 = 0;
+    s->ghwcfg2 = (8 << GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT) |
+                 (4 << GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT) |
+                 (4 << GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT) |
+                 GHWCFG2_DYNAMIC_FIFO |
+                 GHWCFG2_PERIO_EP_SUPPORTED |
+                 ((DWC2_NB_CHAN - 1) << GHWCFG2_NUM_HOST_CHAN_SHIFT) |
+                 (GHWCFG2_INT_DMA_ARCH << GHWCFG2_ARCHITECTURE_SHIFT) |
+                 (GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST << GHWCFG2_OP_MODE_SHIFT);
+    s->ghwcfg3 = (4096 << GHWCFG3_DFIFO_DEPTH_SHIFT) |
+                 (4 << GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT) |
+                 (4 << GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT);
+    s->ghwcfg4 = 0;
+    s->glpmcfg = 0;
+    s->gpwrdn = GPWRDN_PWRDNRSTN;
+    s->gdfifocfg = 0;
+    s->gadpctl = 0;
+    s->grefclk = 0;
+    s->gintmsk2 = 0;
+    s->gintsts2 = 0;
+
+    s->hptxfsiz = 500 << FIFOSIZE_DEPTH_SHIFT;
+
+    s->hcfg = 2 << HCFG_RESVALID_SHIFT;
+    s->hfir = 60000;
+    s->hfnum = 0x3fff;
+    s->hptxsts = (16 << TXSTS_QSPCAVAIL_SHIFT) | 32768;
+    s->haint = 0;
+    s->haintmsk = 0;
+    s->hprt0 = 0;
+
+    memset(s->hreg1, 0, sizeof(s->hreg1));
+    memset(s->pcgreg, 0, sizeof(s->pcgreg));
+
+    s->sof_time = 0;
+    s->frame_number = 0;
+    s->fi = USB_FRMINTVL - 1;
+    s->next_chan = 0;
+    s->working = false;
+
+    for (i = 0; i < DWC2_NB_CHAN; i++) {
+        s->packet[i].needs_service = false;
+    }
+}
+
+static void dwc2_reset_hold(Object *obj)
+{
+    DWC2Class *c = DWC2_GET_CLASS(obj);
+    DWC2State *s = DWC2_USB(obj);
+
+    trace_usb_dwc2_reset_hold();
+
+    if (c->parent_phases.hold) {
+        c->parent_phases.hold(obj);
+    }
+
+    dwc2_update_irq(s);
+}
+
+static void dwc2_reset_exit(Object *obj)
+{
+    DWC2Class *c = DWC2_GET_CLASS(obj);
+    DWC2State *s = DWC2_USB(obj);
+
+    trace_usb_dwc2_reset_exit();
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj);
+    }
+
+    s->hprt0 = HPRT0_PWR;
+    if (s->uport.dev && s->uport.dev->attached) {
+        usb_attach(&s->uport);
+        usb_device_reset(s->uport.dev);
+    }
+}
+
+static void dwc2_realize(DeviceState *dev, Error **errp)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+    DWC2State *s = DWC2_USB(dev);
+    Object *obj;
+    Error *err = NULL;
+
+    obj = object_property_get_link(OBJECT(dev), "dma-mr", &err);
+    if (err) {
+        error_setg(errp, "dwc2: required dma-mr link not found: %s",
+                   error_get_pretty(err));
+        return;
+    }
+    assert(obj != NULL);
+
+    s->dma_mr = MEMORY_REGION(obj);
+    address_space_init(&s->dma_as, s->dma_mr, "dwc2");
+
+    usb_bus_new(&s->bus, sizeof(s->bus), &dwc2_bus_ops, dev);
+    usb_register_port(&s->bus, &s->uport, s, 0, &dwc2_port_ops,
+                      USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL |
+                      (s->usb_version == 2 ? USB_SPEED_MASK_HIGH : 0));
+    s->uport.dev = 0;
+
+    s->usb_frame_time = NANOSECONDS_PER_SECOND / 1000;          /* 1000000 */
+    if (NANOSECONDS_PER_SECOND >= USB_HZ_FS) {
+        s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_FS;   /* 83.3 */
+    } else {
+        s->usb_bit_time = 1;
+    }
+
+    s->fi = USB_FRMINTVL - 1;
+    s->eof_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, dwc2_frame_boundary, s);
+    s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, dwc2_work_timer, s);
+    s->async_bh = qemu_bh_new(dwc2_work_bh, s);
+
+    sysbus_init_irq(sbd, &s->irq);
+}
+
+static void dwc2_init(Object *obj)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    DWC2State *s = DWC2_USB(obj);
+
+    memory_region_init(&s->container, obj, "dwc2", DWC2_MMIO_SIZE);
+    sysbus_init_mmio(sbd, &s->container);
+
+    memory_region_init_io(&s->hsotg, obj, &dwc2_mmio_hsotg_ops, s,
+                          "dwc2-io", 4 * KiB);
+    memory_region_add_subregion(&s->container, 0x0000, &s->hsotg);
+
+    memory_region_init_io(&s->fifos, obj, &dwc2_mmio_hreg2_ops, s,
+                          "dwc2-fifo", 64 * KiB);
+    memory_region_add_subregion(&s->container, 0x1000, &s->fifos);
+}
+
+static const VMStateDescription vmstate_dwc2_state_packet = {
+    .name = "dwc2/packet",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(devadr, DWC2Packet),
+        VMSTATE_UINT32(epnum, DWC2Packet),
+        VMSTATE_UINT32(epdir, DWC2Packet),
+        VMSTATE_UINT32(mps, DWC2Packet),
+        VMSTATE_UINT32(pid, DWC2Packet),
+        VMSTATE_UINT32(index, DWC2Packet),
+        VMSTATE_UINT32(pcnt, DWC2Packet),
+        VMSTATE_UINT32(len, DWC2Packet),
+        VMSTATE_INT32(async, DWC2Packet),
+        VMSTATE_BOOL(small, DWC2Packet),
+        VMSTATE_BOOL(needs_service, DWC2Packet),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+const VMStateDescription vmstate_dwc2_state = {
+    .name = "dwc2",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(glbreg, DWC2State,
+                             DWC2_GLBREG_SIZE / sizeof(uint32_t)),
+        VMSTATE_UINT32_ARRAY(fszreg, DWC2State,
+                             DWC2_FSZREG_SIZE / sizeof(uint32_t)),
+        VMSTATE_UINT32_ARRAY(hreg0, DWC2State,
+                             DWC2_HREG0_SIZE / sizeof(uint32_t)),
+        VMSTATE_UINT32_ARRAY(hreg1, DWC2State,
+                             DWC2_HREG1_SIZE / sizeof(uint32_t)),
+        VMSTATE_UINT32_ARRAY(pcgreg, DWC2State,
+                             DWC2_PCGREG_SIZE / sizeof(uint32_t)),
+
+        VMSTATE_TIMER_PTR(eof_timer, DWC2State),
+        VMSTATE_TIMER_PTR(frame_timer, DWC2State),
+        VMSTATE_INT64(sof_time, DWC2State),
+        VMSTATE_INT64(usb_frame_time, DWC2State),
+        VMSTATE_INT64(usb_bit_time, DWC2State),
+        VMSTATE_UINT32(usb_version, DWC2State),
+        VMSTATE_UINT16(frame_number, DWC2State),
+        VMSTATE_UINT16(fi, DWC2State),
+        VMSTATE_UINT16(next_chan, DWC2State),
+        VMSTATE_BOOL(working, DWC2State),
+
+        VMSTATE_STRUCT_ARRAY(packet, DWC2State, DWC2_NB_CHAN, 1,
+                             vmstate_dwc2_state_packet, DWC2Packet),
+        VMSTATE_UINT8_2DARRAY(usb_buf, DWC2State, DWC2_NB_CHAN,
+                              DWC2_MAX_XFER_SIZE),
+
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static Property dwc2_usb_properties[] = {
+    DEFINE_PROP_UINT32("usb_version", DWC2State, usb_version, 2),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void dwc2_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    DWC2Class *c = DWC2_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+    dc->realize = dwc2_realize;
+    dc->vmsd = &vmstate_dwc2_state;
+    set_bit(DEVICE_CATEGORY_USB, dc->categories);
+    device_class_set_props(dc, dwc2_usb_properties);
+    resettable_class_set_parent_phases(rc, dwc2_reset_enter, dwc2_reset_hold,
+                                       dwc2_reset_exit, &c->parent_phases);
+}
+
+static const TypeInfo dwc2_usb_type_info = {
+    .name          = TYPE_DWC2_USB,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(DWC2State),
+    .instance_init = dwc2_init,
+    .class_size    = sizeof(DWC2Class),
+    .class_init    = dwc2_class_init,
+};
+
+static void dwc2_usb_register_types(void)
+{
+    type_register_static(&dwc2_usb_type_info);
+}
+
+type_init(dwc2_usb_register_types)
diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/usb/Kconfig
+++ b/hw/usb/Kconfig
@@ -XXX,XX +XXX,XX @@ config USB_MUSB
     bool
     select USB
 
+config USB_DWC2
+    bool
+    default y
+    select USB
+
 config TUSB6010
     bool
     select USB_MUSB
diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/usb/Makefile.objs
+++ b/hw/usb/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_USB_EHCI_SYSBUS) += hcd-ehci-sysbus.o
 common-obj-$(CONFIG_USB_XHCI) += hcd-xhci.o
 common-obj-$(CONFIG_USB_XHCI_NEC) += hcd-xhci-nec.o
 common-obj-$(CONFIG_USB_MUSB) += hcd-musb.o
+common-obj-$(CONFIG_USB_DWC2) += hcd-dwc2.o
 
 common-obj-$(CONFIG_TUSB6010) += tusb6010.o
 common-obj-$(CONFIG_IMX)      += chipidea.o
diff --git a/hw/usb/trace-events b/hw/usb/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/usb/trace-events
+++ b/hw/usb/trace-events
@@ -XXX,XX +XXX,XX @@ usb_xhci_xfer_error(void *xfer, uint32_t ret) "%p: ret %d"
 usb_xhci_unimplemented(const char *item, int nr) "%s (0x%x)"
 usb_xhci_enforced_limit(const char *item) "%s"
 
+# hcd-dwc2.c
+usb_dwc2_update_irq(uint32_t level) "level=%d"
+usb_dwc2_raise_global_irq(uint32_t intr) "0x%08x"
+usb_dwc2_lower_global_irq(uint32_t intr) "0x%08x"
+usb_dwc2_raise_host_irq(uint32_t intr) "0x%04x"
+usb_dwc2_lower_host_irq(uint32_t intr) "0x%04x"
+usb_dwc2_sof(int64_t next) "next SOF %" PRId64
+usb_dwc2_bus_start(void) "start SOFs"
+usb_dwc2_bus_stop(void) "stop SOFs"
+usb_dwc2_find_device(uint8_t addr) "%d"
+usb_dwc2_port_disabled(uint32_t pnum) "port %d disabled"
+usb_dwc2_device_found(uint32_t pnum) "device found on port %d"
+usb_dwc2_device_not_found(void) "device not found"
+usb_dwc2_handle_packet(uint32_t chan, void *dev, void *pkt, uint32_t ep, const char *type, const char *dir, uint32_t mps, uint32_t len, uint32_t pcnt) "ch %d dev %p pkt %p ep %d type %s dir %s mps %d len %d pcnt %d"
+usb_dwc2_memory_read(uint32_t addr, uint32_t len) "addr %d len %d"
+usb_dwc2_packet_status(const char *status, uint32_t len) "status %s len %d"
+usb_dwc2_packet_error(const char *status) "ERROR %s"
+usb_dwc2_async_packet(void *pkt, uint32_t chan, void *dev, uint32_t ep, const char *dir, uint32_t len) "pkt %p ch %d dev %p ep %d %s len %d"
+usb_dwc2_memory_write(uint32_t addr, uint32_t len) "addr %d len %d"
+usb_dwc2_packet_done(const char *status, uint32_t actual, uint32_t len, uint32_t pcnt) "status %s actual %d len %d pcnt %d"
+usb_dwc2_packet_next(const char *status, uint32_t len, uint32_t pcnt) "status %s len %d pcnt %d"
+usb_dwc2_attach(void *port) "port %p"
+usb_dwc2_attach_speed(const char *speed) "%s-speed device attached"
+usb_dwc2_detach(void *port) "port %p"
+usb_dwc2_child_detach(void *port, void *child) "port %p child %p"
+usb_dwc2_wakeup(void *port) "port %p"
+usb_dwc2_async_packet_complete(void *port, void *pkt, uint32_t chan, void *dev, uint32_t ep, const char *dir, uint32_t len) "port %p packet %p ch %d dev %p ep %d %s len %d"
+usb_dwc2_work_bh(void) ""
+usb_dwc2_work_bh_service(uint32_t first, uint32_t current, void *dev, uint32_t ep) "first %d servicing %d dev %p ep %d"
+usb_dwc2_work_bh_next(uint32_t chan) "next %d"
+usb_dwc2_enable_chan(uint32_t chan, void *dev, void *pkt, uint32_t ep) "ch %d dev %p pkt %p ep %d"
+usb_dwc2_glbreg_read(uint64_t addr, const char *reg, uint32_t val) " 0x%04" PRIx64 " %s val 0x%08x"
+usb_dwc2_glbreg_write(uint64_t addr, const char *reg, uint64_t val, uint32_t old, uint64_t result) "0x%04" PRIx64 " %s val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
+usb_dwc2_fszreg_read(uint64_t addr, uint32_t val) " 0x%04" PRIx64 " HPTXFSIZ  val 0x%08x"
+usb_dwc2_fszreg_write(uint64_t addr, uint64_t val, uint32_t old, uint64_t result) "0x%04" PRIx64 " HPTXFSIZ  val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
+usb_dwc2_hreg0_read(uint64_t addr, const char *reg, uint32_t val) "  0x%04" PRIx64 " %s val 0x%08x"
+usb_dwc2_hreg0_write(uint64_t addr, const char *reg, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " %s val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
+usb_dwc2_hreg1_read(uint64_t addr, const char *reg, uint64_t chan, uint32_t val) "  0x%04" PRIx64 " %s%" PRId64 " val 0x%08x"
+usb_dwc2_hreg1_write(uint64_t addr, const char *reg, uint64_t chan, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " %s%" PRId64 " val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
+usb_dwc2_pcgreg_read(uint64_t addr, const char *reg, uint32_t val) " 0x%04" PRIx64 " %s val 0x%08x"
+usb_dwc2_pcgreg_write(uint64_t addr, const char *reg, uint64_t val, uint32_t old, uint64_t result) "0x%04" PRIx64 " %s val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
+usb_dwc2_hreg2_read(uint64_t addr, uint64_t fifo, uint32_t val) "  0x%04" PRIx64 " FIFO%" PRId64 "     val 0x%08x"
+usb_dwc2_hreg2_write(uint64_t addr, uint64_t fifo, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " FIFO%" PRId64 "     val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
+usb_dwc2_hreg0_action(const char *s) "%s"
+usb_dwc2_wakeup_endpoint(void *ep, uint32_t stream) "endp %p stream %d"
+usb_dwc2_work_timer(void) ""
+usb_dwc2_reset_enter(void) "=== RESET enter ==="
+usb_dwc2_reset_hold(void) "=== RESET hold ==="
+usb_dwc2_reset_exit(void) "=== RESET exit ==="
+
 # desc.c
 usb_desc_device(int addr, int len, int ret) "dev %d query device, len %d, ret %d"
 usb_desc_device_qualifier(int addr, int len, int ret) "dev %d query device qualifier, len %d, ret %d"
-- 
2.20.1

From: Paul Zimmerman <pauldzim@gmail.com>

The dwc-hsotg (dwc2) USB host depends on a short packet to
indicate the end of an IN transfer. The usb-storage driver
currently doesn't provide this, so fix it.

I have tested this change rather extensively using a PC
emulation with xhci, ehci, and uhci controllers, and have
not observed any regressions.

Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Message-id: 20200520235349.21215-6-pauldzim@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/usb/dev-storage.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/usb/dev-storage.c
+++ b/hw/usb/dev-storage.c
@@ -XXX,XX +XXX,XX @@ static void usb_msd_copy_data(MSDState *s, USBPacket *p)
     usb_packet_copy(p, scsi_req_get_buf(s->req) + s->scsi_off, len);
     s->scsi_len -= len;
     s->scsi_off += len;
+    if (len > s->data_len) {
+        len = s->data_len;
+    }
     s->data_len -= len;
     if (s->scsi_len == 0 || s->data_len == 0) {
         scsi_req_continue(s->req);
@@ -XXX,XX +XXX,XX @@ static void usb_msd_command_complete(SCSIRequest *req, uint32_t status, size_t r
             if (s->data_len) {
                 int len = (p->iov.size - p->actual_length);
                 usb_packet_skip(p, len);
+                if (len > s->data_len) {
+                    len = s->data_len;
+                }
                 s->data_len -= len;
             }
             if (s->data_len == 0) {
@@ -XXX,XX +XXX,XX @@ static void usb_msd_handle_data(USBDevice *dev, USBPacket *p)
                 int len = p->iov.size - p->actual_length;
                 if (len) {
                     usb_packet_skip(p, len);
+                    if (len > s->data_len) {
+                        len = s->data_len;
+                    }
                     s->data_len -= len;
                     if (s->data_len == 0) {
                         s->mode = USB_MSDM_CSW;
@@ -XXX,XX +XXX,XX @@ static void usb_msd_handle_data(USBDevice *dev, USBPacket *p)
                 int len = p->iov.size - p->actual_length;
                 if (len) {
                     usb_packet_skip(p, len);
+                    if (len > s->data_len) {
+                        len = s->data_len;
+                    }
                     s->data_len -= len;
                     if (s->data_len == 0) {
                         s->mode = USB_MSDM_CSW;
                     }
                 }
             }
-            if (p->actual_length < p->iov.size) {
+            if (p->actual_length < p->iov.size && (p->short_not_ok ||
+                    s->scsi_len >= p->ep->max_packet_size)) {
                 DPRINTF("Deferring packet %p [wait data-in]\n", p);
                 s->packet = p;
                 p->status = USB_RET_ASYNC;
-- 
2.20.1

From: Paul Zimmerman <pauldzim@gmail.com>

Wire the dwc-hsotg (dwc2) emulation into Qemu

Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Reviewed-by: Philippe Mathieu-Daude <f4bug@amsat.org>
Message-id: 20200520235349.21215-7-pauldzim@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/bcm2835_peripherals.h |  3 ++-
 hw/arm/bcm2835_peripherals.c         | 21 ++++++++++++++++++++-
 2 files changed, 22 insertions(+), 2 deletions(-)

From: Paul Zimmerman <pauldzim@gmail.com>

Add a check for functional dwc-hsotg (dwc2) USB host emulation to
the Raspi 2 acceptance test

Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Reviewed-by: Philippe Mathieu-Daude <f4bug@amsat.org>
Message-id: 20200520235349.21215-8-pauldzim@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/acceptance/boot_linux_console.py | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(LinuxKernelTest):
 
         self.vm.set_console()
         kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
-                               serial_kernel_cmdline[uart_id])
+                               serial_kernel_cmdline[uart_id] +
+                               ' root=/dev/mmcblk0p2 rootwait ' +
+                               'dwc_otg.fiq_fsm_enable=0')
         self.vm.add_args('-kernel', kernel_path,
                          '-dtb', dtb_path,
-                         '-append', kernel_command_line)
+                         '-append', kernel_command_line,
+                         '-device', 'usb-kbd')
         self.vm.launch()
         console_pattern = 'Kernel command line: %s' % kernel_command_line
         self.wait_for_console_pattern(console_pattern)
+        console_pattern = 'Product: QEMU USB Keyboard'
+        self.wait_for_console_pattern(console_pattern)
 
     def test_arm_raspi2_uart0(self):
         """
-- 
2.20.1

Convert the VSHL and VSLI insns from the Neon 2-registers-and-a-shift
group to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-2-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 25 ++++++++++++++++++++++
 target/arm/translate-neon.inc.c | 38 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 18 +++++++---------
 3 files changed, 71 insertions(+), 10 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VRECPS_fp_3s     1111 001 0 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
 VRSQRTS_fp_3s    1111 001 0 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
 VMAXNM_fp_3s     1111 001 1 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
 VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
+
+######################################################################
+# 2-reg-and-shift grouping:
+# 1111 001 U 1 D immH:3 immL:3 Vd:4 opc:4 L Q M 1 Vm:4
+######################################################################
+&2reg_shift vm vd q shift size
+
+@2reg_shl_d      .... ... . . . shift:6      .... .... 1 q:1 . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=3
+@2reg_shl_s      .... ... . . . 1 shift:5    .... .... 0 q:1 . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2
+@2reg_shl_h      .... ... . . . 01 shift:4   .... .... 0 q:1 . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1
+@2reg_shl_b      .... ... . . . 001 shift:3  .... .... 0 q:1 . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0
+
+VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
+VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
+VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
+VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
+
+VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
+VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
+VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
+VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn)
 DO_3S_FP_PAIR(VPADD, gen_helper_vfp_adds)
 DO_3S_FP_PAIR(VPMAX, gen_helper_vfp_maxs)
 DO_3S_FP_PAIR(VPMIN, gen_helper_vfp_mins)
+
+static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
+{
+    /* Handle a 2-reg-shift insn which can be vectorized. */
+    int vec_size = a->q ? 16 : 8;
+    int rd_ofs = neon_reg_offset(a->vd, 0);
+    int rm_ofs = neon_reg_offset(a->vm, 0);
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if ((a->vm | a->vd) & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    fn(a->size, rd_ofs, rm_ofs, a->shift, vec_size, vec_size);
+    return true;
+}
+
+#define DO_2SH(INSN, FUNC)                                              \
+    static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a)  \
+    {                                                                   \
+        return do_vector_2sh(s, a, FUNC);                               \
+    }                                                                   \
+
+DO_2SH(VSHL, tcg_gen_gvec_shli)
+DO_2SH(VSLI, gen_gvec_sli)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
         if ((insn & 0x00380080) != 0) {
             /* Two registers and shift.  */
             op = (insn >> 8) & 0xf;
+
+            switch (op) {
+            case 5: /* VSHL, VSLI */
+                return 1; /* handled by decodetree */
+            default:
+                break;
+            }
+
             if (insn & (1 << 7)) {
                 /* 64-bit shift. */
                 if (op > 7) {
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     gen_gvec_sri(size, rd_ofs, rm_ofs, shift,
                                  vec_size, vec_size);
                     return 0;
-
-                case 5: /* VSHL, VSLI */
-                    if (u) { /* VSLI */
-                        gen_gvec_sli(size, rd_ofs, rm_ofs, shift,
-                                     vec_size, vec_size);
-                    } else { /* VSHL */
-                        tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift,
-                                          vec_size, vec_size);
-                    }
-                    return 0;
                 }
 
                 if (size == 3) {
-- 
2.20.1

Convert the VSHR 2-reg-shift insns to decodetree.

Note that unlike the legacy decoder, we present the right shift
amount to the trans_ function as a positive integer.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-3-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 25 ++++++++++++++++++++
 target/arm/translate-neon.inc.c | 41 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 21 +----------------
 3 files changed, 67 insertions(+), 20 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
 ######################################################################
 &2reg_shift vm vd q shift size
 
+# Right shifts are encoded as N - shift, where N is the element size in bits.
+%neon_rshift_i6  16:6 !function=rsub_64
+%neon_rshift_i5  16:5 !function=rsub_32
+%neon_rshift_i4  16:4 !function=rsub_16
+%neon_rshift_i3  16:3 !function=rsub_8
+
+@2reg_shr_d      .... ... . . . ......  .... .... 1 q:1 . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 shift=%neon_rshift_i6
+@2reg_shr_s      .... ... . . . 1 ..... .... .... 0 q:1 . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
+@2reg_shr_h      .... ... . . . 01 .... .... .... 0 q:1 . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4
+@2reg_shr_b      .... ... . . . 001 ... .... .... 0 q:1 . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i3
+
 @2reg_shl_d      .... ... . . . shift:6      .... .... 1 q:1 . . .... \
                  &2reg_shift vm=%vm_dp vd=%vd_dp size=3
 @2reg_shl_s      .... ... . . . 1 shift:5    .... .... 0 q:1 . . .... \
@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
 @2reg_shl_b      .... ... . . . 001 shift:3  .... .... 0 q:1 . . .... \
                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0
 
+VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
+VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
+VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
+VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
+
+VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
+VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
+VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
+VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
+
 VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
 VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
 VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
     return x + 1;
 }
 
+static inline int rsub_64(DisasContext *s, int x)
+{
+    return 64 - x;
+}
+
+static inline int rsub_32(DisasContext *s, int x)
+{
+    return 32 - x;
+}
+static inline int rsub_16(DisasContext *s, int x)
+{
+    return 16 - x;
+}
+static inline int rsub_8(DisasContext *s, int x)
+{
+    return 8 - x;
+}
+
 /* Include the generated Neon decoder */
 #include "decode-neon-dp.inc.c"
 #include "decode-neon-ls.inc.c"
@@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
 
 DO_2SH(VSHL, tcg_gen_gvec_shli)
 DO_2SH(VSLI, gen_gvec_sli)
+
+static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a)
+{
+    /* Signed shift out of range results in all-sign-bits */
+    a->shift = MIN(a->shift, (8 << a->size) - 1);
+    return do_vector_2sh(s, a, tcg_gen_gvec_sari);
+}
+
+static void gen_zero_rd_2sh(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
+                            int64_t shift, uint32_t oprsz, uint32_t maxsz)
+{
+    tcg_gen_gvec_dup_imm(vece, rd_ofs, oprsz, maxsz, 0);
+}
+
+static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a)
+{
+    /* Shift out of range is architecturally valid and results in zero. */
+    if (a->shift >= (8 << a->size)) {
+        return do_vector_2sh(s, a, gen_zero_rd_2sh);
+    } else {
+        return do_vector_2sh(s, a, tcg_gen_gvec_shri);
+    }
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             op = (insn >> 8) & 0xf;
 
             switch (op) {
+            case 0: /* VSHR */
             case 5: /* VSHL, VSLI */
                 return 1; /* handled by decodetree */
             default:
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                 }
 
                 switch (op) {
-                case 0:  /* VSHR */
-                    /* Right shift comes here negative.  */
-                    shift = -shift;
-                    /* Shifts larger than the element size are architecturally
-                     * valid.  Unsigned results in all zeros; signed results
-                     * in all sign bits.
-                     */
-                    if (!u) {
-                        tcg_gen_gvec_sari(size, rd_ofs, rm_ofs,
-                                          MIN(shift, (8 << size) - 1),
-                                          vec_size, vec_size);
-                    } else if (shift >= 8 << size) {
-                        tcg_gen_gvec_dup_imm(MO_8, rd_ofs, vec_size,
-                                             vec_size, 0);
-                    } else {
-                        tcg_gen_gvec_shri(size, rd_ofs, rm_ofs, shift,
-                                          vec_size, vec_size);
-                    }
-                    return 0;
-
                 case 1:  /* VSRA */
                     /* Right shift comes here negative.  */
                     shift = -shift;
-- 
2.20.1

Convert the VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree.
(These are the last instructions in the group that are vectorized;
the rest all require looping over each element.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-4-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 35 ++++++++++++++++++++++
 target/arm/translate-neon.inc.c |  7 +++++
 target/arm/translate.c          | 52 +++------------------------------
 3 files changed, 46 insertions(+), 48 deletions(-)

Convert the VQSHLU and QVSHL 2-reg-shift insns to decodetree.
These are the last of the simple shift-by-immediate insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-5-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  15 +++++
 target/arm/translate-neon.inc.c | 108 +++++++++++++++++++++++++++++++
 target/arm/translate.c          | 110 +-------------------------------
 3 files changed, 126 insertions(+), 107 deletions(-)

Convert the Neon narrowing shifts where op==8 to decodetree:
 * VSHRN
 * VRSHRN
 * VQSHRUN
 * VQRSHRUN

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-6-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  27 ++++++
 target/arm/translate-neon.inc.c | 167 ++++++++++++++++++++++++++++++++
 target/arm/translate.c          |   1 +
 3 files changed, 195 insertions(+)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
 @2reg_shl_b      .... ... . . . 001 shift:3  .... .... 0 q:1 . . .... \
                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0
 
+# Narrowing right shifts: here the Q bit is part of the opcode decode
+@2reg_shrn_d     .... ... . . . 1 ..... .... .... 0 . . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 q=0 \
+                 shift=%neon_rshift_i5
+@2reg_shrn_s     .... ... . . . 01 .... .... .... 0 . . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0 \
+                 shift=%neon_rshift_i4
+@2reg_shrn_h     .... ... . . . 001 ... .... .... 0 . . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 \
+                 shift=%neon_rshift_i3
+
 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
@@ -XXX,XX +XXX,XX @@ VQSHL_U_64_2sh   1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
 VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
 VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
 VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
+
+VSHRN_64_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
+VSHRN_32_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
+VSHRN_16_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
+
+VRSHRN_64_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
+VRSHRN_32_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
+VRSHRN_16_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
+
+VQSHRUN_64_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
+VQSHRUN_32_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
+VQSHRUN_16_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
+
+VQRSHRUN_64_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
+VQRSHRUN_32_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
+VQRSHRUN_16_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
 DO_2SHIFT_ENV(VQSHLU, qshlu_s)
 DO_2SHIFT_ENV(VQSHL_U, qshl_u)
 DO_2SHIFT_ENV(VQSHL_S, qshl_s)
+
+static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
+                                NeonGenTwo64OpFn *shiftfn,
+                                NeonGenNarrowEnvFn *narrowfn)
+{
+    /* 2-reg-and-shift narrowing-shift operations, size == 3 case */
+    TCGv_i64 constimm, rm1, rm2;
+    TCGv_i32 rd;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if (a->vm & 1) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    /*
+     * This is always a right shift, and the shiftfn is always a
+     * left-shift helper, which thus needs the negated shift count.
+     */
+    constimm = tcg_const_i64(-a->shift);
+    rm1 = tcg_temp_new_i64();
+    rm2 = tcg_temp_new_i64();
+
+    /* Load both inputs first to avoid potential overwrite if rm == rd */
+    neon_load_reg64(rm1, a->vm);
+    neon_load_reg64(rm2, a->vm + 1);
+
+    shiftfn(rm1, rm1, constimm);
+    rd = tcg_temp_new_i32();
+    narrowfn(rd, cpu_env, rm1);
+    neon_store_reg(a->vd, 0, rd);
+
+    shiftfn(rm2, rm2, constimm);
+    rd = tcg_temp_new_i32();
+    narrowfn(rd, cpu_env, rm2);
+    neon_store_reg(a->vd, 1, rd);
+
+    tcg_temp_free_i64(rm1);
+    tcg_temp_free_i64(rm2);
+    tcg_temp_free_i64(constimm);
+
+    return true;
+}
+
+static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
+                                NeonGenTwoOpFn *shiftfn,
+                                NeonGenNarrowEnvFn *narrowfn)
+{
+    /* 2-reg-and-shift narrowing-shift operations, size < 3 case */
+    TCGv_i32 constimm, rm1, rm2, rm3, rm4;
+    TCGv_i64 rtmp;
+    uint32_t imm;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if (a->vm & 1) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    /*
+     * This is always a right shift, and the shiftfn is always a
+     * left-shift helper, which thus needs the negated shift count
+     * duplicated into each lane of the immediate value.
+     */
+    if (a->size == 1) {
+        imm = (uint16_t)(-a->shift);
+        imm |= imm << 16;
+    } else {
+        /* size == 2 */
+        imm = -a->shift;
+    }
+    constimm = tcg_const_i32(imm);
+
+    /* Load all inputs first to avoid potential overwrite */
+    rm1 = neon_load_reg(a->vm, 0);
+    rm2 = neon_load_reg(a->vm, 1);
+    rm3 = neon_load_reg(a->vm + 1, 0);
+    rm4 = neon_load_reg(a->vm + 1, 1);
+    rtmp = tcg_temp_new_i64();
+
+    shiftfn(rm1, rm1, constimm);
+    shiftfn(rm2, rm2, constimm);
+
+    tcg_gen_concat_i32_i64(rtmp, rm1, rm2);
+    tcg_temp_free_i32(rm2);
+
+    narrowfn(rm1, cpu_env, rtmp);
+    neon_store_reg(a->vd, 0, rm1);
+
+    shiftfn(rm3, rm3, constimm);
+    shiftfn(rm4, rm4, constimm);
+    tcg_temp_free_i32(constimm);
+
+    tcg_gen_concat_i32_i64(rtmp, rm3, rm4);
+    tcg_temp_free_i32(rm4);
+
+    narrowfn(rm3, cpu_env, rtmp);
+    tcg_temp_free_i64(rtmp);
+    neon_store_reg(a->vd, 1, rm3);
+    return true;
+}
+
+#define DO_2SN_64(INSN, FUNC, NARROWFUNC)                               \
+    static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a)  \
+    {                                                                   \
+        return do_2shift_narrow_64(s, a, FUNC, NARROWFUNC);             \
+    }
+#define DO_2SN_32(INSN, FUNC, NARROWFUNC)                               \
+    static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a)  \
+    {                                                                   \
+        return do_2shift_narrow_32(s, a, FUNC, NARROWFUNC);             \
+    }
+
+static void gen_neon_narrow_u32(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
+{
+    tcg_gen_extrl_i64_i32(dest, src);
+}
+
+static void gen_neon_narrow_u16(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
+{
+    gen_helper_neon_narrow_u16(dest, src);
+}
+
+static void gen_neon_narrow_u8(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
+{
+    gen_helper_neon_narrow_u8(dest, src);
+}
+
+DO_2SN_64(VSHRN_64, gen_ushl_i64, gen_neon_narrow_u32)
+DO_2SN_32(VSHRN_32, gen_ushl_i32, gen_neon_narrow_u16)
+DO_2SN_32(VSHRN_16, gen_helper_neon_shl_u16, gen_neon_narrow_u8)
+
+DO_2SN_64(VRSHRN_64, gen_helper_neon_rshl_u64, gen_neon_narrow_u32)
+DO_2SN_32(VRSHRN_32, gen_helper_neon_rshl_u32, gen_neon_narrow_u16)
+DO_2SN_32(VRSHRN_16, gen_helper_neon_rshl_u16, gen_neon_narrow_u8)
+
+DO_2SN_64(VQSHRUN_64, gen_sshl_i64, gen_helper_neon_unarrow_sat32)
+DO_2SN_32(VQSHRUN_32, gen_sshl_i32, gen_helper_neon_unarrow_sat16)
+DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat8)
+
+DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_sat32)
+DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_sat16)
+DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_sat8)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             case 5: /* VSHL, VSLI */
             case 6: /* VQSHLU */
             case 7: /* VQSHL */
+            case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
                 return 1; /* handled by decodetree */
             default:
                 break;
-- 
2.20.1

Convert the remaining Neon narrowing shifts to decodetree:
  * VQSHRN
  * VQRSHRN

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-7-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  20 ++++++
 target/arm/translate-neon.inc.c |  15 +++++
 target/arm/translate.c          | 110 +-------------------------------
 3 files changed, 37 insertions(+), 108 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VQSHRUN_16_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
 VQRSHRUN_64_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
 VQRSHRUN_32_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
 VQRSHRUN_16_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
+
+# VQSHRN with signed input
+VQSHRN_S64_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
+VQSHRN_S32_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
+VQSHRN_S16_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
+
+# VQRSHRN with signed input
+VQRSHRN_S64_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
+VQRSHRN_S32_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
+VQRSHRN_S16_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
+
+# VQSHRN with unsigned input
+VQSHRN_U64_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
+VQSHRN_U32_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
+VQSHRN_U16_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
+
+# VQRSHRN with unsigned input
+VQRSHRN_U64_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
+VQRSHRN_U32_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
+VQRSHRN_U16_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat8)
 DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_sat32)
 DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_sat16)
 DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_sat8)
+DO_2SN_64(VQSHRN_S64, gen_sshl_i64, gen_helper_neon_narrow_sat_s32)
+DO_2SN_32(VQSHRN_S32, gen_sshl_i32, gen_helper_neon_narrow_sat_s16)
+DO_2SN_32(VQSHRN_S16, gen_helper_neon_shl_s16, gen_helper_neon_narrow_sat_s8)
+
+DO_2SN_64(VQRSHRN_S64, gen_helper_neon_rshl_s64, gen_helper_neon_narrow_sat_s32)
+DO_2SN_32(VQRSHRN_S32, gen_helper_neon_rshl_s32, gen_helper_neon_narrow_sat_s16)
+DO_2SN_32(VQRSHRN_S16, gen_helper_neon_rshl_s16, gen_helper_neon_narrow_sat_s8)
+
+DO_2SN_64(VQSHRN_U64, gen_ushl_i64, gen_helper_neon_narrow_sat_u32)
+DO_2SN_32(VQSHRN_U32, gen_ushl_i32, gen_helper_neon_narrow_sat_u16)
+DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_u8)
+
+DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sat_u32)
+DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sat_u16)
+DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sat_u8)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_neon_unarrow_sats(int size, TCGv_i32 dest, TCGv_i64 src)
     }
 }
 
-static inline void gen_neon_shift_narrow(int size, TCGv_i32 var, TCGv_i32 shift,
-                                         int q, int u)
-{
-    if (q) {
-        if (u) {
-            switch (size) {
-            case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
-            case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
-            default: abort();
-            }
-        } else {
-            switch (size) {
-            case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
-            case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
-            default: abort();
-            }
-        }
-    } else {
-        if (u) {
-            switch (size) {
-            case 1: gen_helper_neon_shl_u16(var, var, shift); break;
-            case 2: gen_ushl_i32(var, var, shift); break;
-            default: abort();
-            }
-        } else {
-            switch (size) {
-            case 1: gen_helper_neon_shl_s16(var, var, shift); break;
-            case 2: gen_sshl_i32(var, var, shift); break;
-            default: abort();
-            }
-        }
-    }
-}
-
 static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u)
 {
     if (u) {
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             case 6: /* VQSHLU */
             case 7: /* VQSHL */
             case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
+            case 9: /* VQSHRN, VQRSHRN */
                 return 1; /* handled by decodetree */
             default:
                 break;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     size--;
             }
             shift = (insn >> 16) & ((1 << (3 + size)) - 1);
-            if (op < 10) {
-                /* Shift by immediate and narrow:
-                   VSHRN, VRSHRN, VQSHRN, VQRSHRN.  */
-                int input_unsigned = (op == 8) ? !u : u;
-                if (rm & 1) {
-                    return 1;
-                }
-                shift = shift - (1 << (size + 3));
-                size++;
-                if (size == 3) {
-                    tmp64 = tcg_const_i64(shift);
-                    neon_load_reg64(cpu_V0, rm);
-                    neon_load_reg64(cpu_V1, rm + 1);
-                    for (pass = 0; pass < 2; pass++) {
-                        TCGv_i64 in;
-                        if (pass == 0) {
-                            in = cpu_V0;
-                        } else {
-                            in = cpu_V1;
-                        }
-                        if (q) {
-                            if (input_unsigned) {
-                                gen_helper_neon_rshl_u64(cpu_V0, in, tmp64);
-                            } else {
-                                gen_helper_neon_rshl_s64(cpu_V0, in, tmp64);
-                            }
-                        } else {
-                            if (input_unsigned) {
-                                gen_ushl_i64(cpu_V0, in, tmp64);
-                            } else {
-                                gen_sshl_i64(cpu_V0, in, tmp64);
-                            }
-                        }
-                        tmp = tcg_temp_new_i32();
-                        gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
-                        neon_store_reg(rd, pass, tmp);
-                    } /* for pass */
-                    tcg_temp_free_i64(tmp64);
-                } else {
-                    if (size == 1) {
-                        imm = (uint16_t)shift;
-                        imm |= imm << 16;
-                    } else {
-                        /* size == 2 */
-                        imm = (uint32_t)shift;
-                    }
-                    tmp2 = tcg_const_i32(imm);
-                    tmp4 = neon_load_reg(rm + 1, 0);
-                    tmp5 = neon_load_reg(rm + 1, 1);
-                    for (pass = 0; pass < 2; pass++) {
-                        if (pass == 0) {
-                            tmp = neon_load_reg(rm, 0);
-                        } else {
-                            tmp = tmp4;
-                        }
-                        gen_neon_shift_narrow(size, tmp, tmp2, q,
-                                              input_unsigned);
-                        if (pass == 0) {
-                            tmp3 = neon_load_reg(rm, 1);
-                        } else {
-                            tmp3 = tmp5;
-                        }
-                        gen_neon_shift_narrow(size, tmp3, tmp2, q,
-                                              input_unsigned);
-                        tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
-                        tcg_temp_free_i32(tmp);
-                        tcg_temp_free_i32(tmp3);
-                        tmp = tcg_temp_new_i32();
-                        gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
-                        neon_store_reg(rd, pass, tmp);
-                    } /* for pass */
-                    tcg_temp_free_i32(tmp2);
-                }
-            } else if (op == 10) {
+            if (op == 10) {
                 /* VSHLL, VMOVL */
                 if (q || (rd & 1)) {
                     return 1;
-- 
2.20.1

Convert the VSHLL and VMOVL insns from the 2-reg-shift group
to decodetree. Since the loop always has two passes, we unroll
it to avoid the awkward reassignment of one TCGv to another.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-8-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 16 +++++++
 target/arm/translate-neon.inc.c | 81 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 46 +------------------
 3 files changed, 99 insertions(+), 44 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
                  &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 \
                  shift=%neon_rshift_i3
 
+# Long left shifts: again Q is part of opcode decode
+@2reg_shll_s     .... ... . . . 1 shift:5    .... .... 0 . . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0
+@2reg_shll_h     .... ... . . . 01 shift:4   .... .... 0 . . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0
+@2reg_shll_b     .... ... . . . 001 shift:3  .... .... 0 . . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
+
 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
@@ -XXX,XX +XXX,XX @@ VQSHRN_U16_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
 VQRSHRN_U64_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
 VQRSHRN_U32_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
 VQRSHRN_U16_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
+
+VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
+VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
+VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
+
+VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
+VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
+VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_u8)
 DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sat_u32)
 DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sat_u16)
 DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sat_u8)
+
+static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
+                         NeonGenWidenFn *widenfn, bool u)
+{
+    TCGv_i64 tmp;
+    TCGv_i32 rm0, rm1;
+    uint64_t widen_mask = 0;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if (a->vd & 1) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    /*
+     * This is a widen-and-shift operation. The shift is always less
+     * than the width of the source type, so after widening the input
+     * vector we can simply shift the whole 64-bit widened register,
+     * and then clear the potential overflow bits resulting from left
+     * bits of the narrow input appearing as right bits of the left
+     * neighbour narrow input. Calculate a mask of bits to clear.
+     */
+    if ((a->shift != 0) && (a->size < 2 || u)) {
+        int esize = 8 << a->size;
+        widen_mask = MAKE_64BIT_MASK(0, esize);
+        widen_mask >>= esize - a->shift;
+        widen_mask = dup_const(a->size + 1, widen_mask);
+    }
+
+    rm0 = neon_load_reg(a->vm, 0);
+    rm1 = neon_load_reg(a->vm, 1);
+    tmp = tcg_temp_new_i64();
+
+    widenfn(tmp, rm0);
+    if (a->shift != 0) {
+        tcg_gen_shli_i64(tmp, tmp, a->shift);
+        tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
+    }
+    neon_store_reg64(tmp, a->vd);
+
+    widenfn(tmp, rm1);
+    if (a->shift != 0) {
+        tcg_gen_shli_i64(tmp, tmp, a->shift);
+        tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
+    }
+    neon_store_reg64(tmp, a->vd + 1);
+    tcg_temp_free_i64(tmp);
+    return true;
+}
+
+static bool trans_VSHLL_S_2sh(DisasContext *s, arg_2reg_shift *a)
+{
+    NeonGenWidenFn *widenfn[] = {
+        gen_helper_neon_widen_s8,
+        gen_helper_neon_widen_s16,
+        tcg_gen_ext_i32_i64,
+    };
+    return do_vshll_2sh(s, a, widenfn[a->size], false);
+}
+
+static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a)
+{
+    NeonGenWidenFn *widenfn[] = {
+        gen_helper_neon_widen_u8,
+        gen_helper_neon_widen_u16,
+        tcg_gen_extu_i32_i64,
+    };
+    return do_vshll_2sh(s, a, widenfn[a->size], true);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             case 7: /* VQSHL */
             case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
             case 9: /* VQSHRN, VQRSHRN */
+            case 10: /* VSHLL, including VMOVL */
                 return 1; /* handled by decodetree */
             default:
                 break;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     size--;
             }
             shift = (insn >> 16) & ((1 << (3 + size)) - 1);
-            if (op == 10) {
-                /* VSHLL, VMOVL */
-                if (q || (rd & 1)) {
-                    return 1;
-                }
-                tmp = neon_load_reg(rm, 0);
-                tmp2 = neon_load_reg(rm, 1);
-                for (pass = 0; pass < 2; pass++) {
-                    if (pass == 1)
-                        tmp = tmp2;
-
-                    gen_neon_widen(cpu_V0, tmp, size, u);
-
-                    if (shift != 0) {
-                        /* The shift is less than the width of the source
-                           type, so we can just shift the whole register.  */
-                        tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
-                        /* Widen the result of shift: we need to clear
-                         * the potential overflow bits resulting from
-                         * left bits of the narrow input appearing as
-                         * right bits of left the neighbour narrow
-                         * input.  */
-                        if (size < 2 || !u) {
-                            uint64_t imm64;
-                            if (size == 0) {
-                                imm = (0xffu >> (8 - shift));
-                                imm |= imm << 16;
-                            } else if (size == 1) {
-                                imm = 0xffff >> (16 - shift);
-                            } else {
-                                /* size == 2 */
-                                imm = 0xffffffff >> (32 - shift);
-                            }
-                            if (size < 2) {
-                                imm64 = imm | (((uint64_t)imm) << 32);
-                            } else {
-                                imm64 = imm;
-                            }
-                            tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64);
-                        }
-                    }
-                    neon_store_reg64(cpu_V0, rd + pass);
-                }
-            } else if (op >= 14) {
+            if (op >= 14) {
                 /* VCVT fixed-point.  */
                 TCGv_ptr fpst;
                 TCGv_i32 shiftv;
-- 
2.20.1

Convert the VCVT fixed-point conversion operations in the
Neon 2-regs-and-shift group to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-9-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 11 +++++
 target/arm/translate-neon.inc.c | 49 +++++++++++++++++++++
 target/arm/translate.c          | 75 +--------------------------------
 3 files changed, 62 insertions(+), 73 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
 @2reg_shll_b     .... ... . . . 001 shift:3  .... .... 0 . . . .... \
                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
 
+# We use size=0 for fp32 and size=1 for fp16 to match the 3-same encodings.
+@2reg_vcvt       .... ... . . . 1 ..... .... .... . q:1 . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i5
+
 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
@@ -XXX,XX +XXX,XX @@ VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
 VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
 VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
 VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
+
+# VCVT fixed<->float conversions
+# TODO: FP16 fixed<->float conversions are opc==0b1100 and 0b1101
+VCVT_SF_2sh      1111 001 0 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
+VCVT_UF_2sh      1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
+VCVT_FS_2sh      1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
+VCVT_FU_2sh      1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a)
     };
     return do_vshll_2sh(s, a, widenfn[a->size], true);
 }
+
+static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
+                      NeonGenTwoSingleOPFn *fn)
+{
+    /* FP operations in 2-reg-and-shift group */
+    TCGv_i32 tmp, shiftv;
+    TCGv_ptr fpstatus;
+    int pass;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if ((a->vm | a->vd) & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    fpstatus = get_fpstatus_ptr(1);
+    shiftv = tcg_const_i32(a->shift);
+    for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
+        tmp = neon_load_reg(a->vm, pass);
+        fn(tmp, tmp, shiftv, fpstatus);
+        neon_store_reg(a->vd, pass, tmp);
+    }
+    tcg_temp_free_ptr(fpstatus);
+    tcg_temp_free_i32(shiftv);
+    return true;
+}
+
+#define DO_FP_2SH(INSN, FUNC)                                           \
+    static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a)  \
+    {                                                                   \
+        return do_fp_2sh(s, a, FUNC);                                   \
+    }
+
+DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos)
+DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos)
+DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero)
+DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
     int q;
     int rd, rn, rm, rd_ofs, rn_ofs, rm_ofs;
     int size;
-    int shift;
     int pass;
     int u;
     int vec_size;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
         return 1;
     } else if (insn & (1 << 4)) {
         if ((insn & 0x00380080) != 0) {
-            /* Two registers and shift.  */
-            op = (insn >> 8) & 0xf;
-
-            switch (op) {
-            case 0: /* VSHR */
-            case 1: /* VSRA */
-            case 2: /* VRSHR */
-            case 3: /* VRSRA */
-            case 4: /* VSRI */
-            case 5: /* VSHL, VSLI */
-            case 6: /* VQSHLU */
-            case 7: /* VQSHL */
-            case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
-            case 9: /* VQSHRN, VQRSHRN */
-            case 10: /* VSHLL, including VMOVL */
-                return 1; /* handled by decodetree */
-            default:
-                break;
-            }
-
-            if (insn & (1 << 7)) {
-                /* 64-bit shift. */
-                if (op > 7) {
-                    return 1;
-                }
-                size = 3;
-            } else {
-                size = 2;
-                while ((insn & (1 << (size + 19))) == 0)
-                    size--;
-            }
-            shift = (insn >> 16) & ((1 << (3 + size)) - 1);
-            if (op >= 14) {
-                /* VCVT fixed-point.  */
-                TCGv_ptr fpst;
-                TCGv_i32 shiftv;
-                VFPGenFixPointFn *fn;
-
-                if (!(insn & (1 << 21)) || (q && ((rd | rm) & 1))) {
-                    return 1;
-                }
-
-                if (!(op & 1)) {
-                    if (u) {
-                        fn = gen_helper_vfp_ultos;
-                    } else {
-                        fn = gen_helper_vfp_sltos;
-                    }
-                } else {
-                    if (u) {
-                        fn = gen_helper_vfp_touls_round_to_zero;
-                    } else {
-                        fn = gen_helper_vfp_tosls_round_to_zero;
-                    }
-                }
-
-                /* We have already masked out the must-be-1 top bit of imm6,
-                 * hence this 32-shift where the ARM ARM has 64-imm6.
-                 */
-                shift = 32 - shift;
-                fpst = get_fpstatus_ptr(1);
-                shiftv = tcg_const_i32(shift);
-                for (pass = 0; pass < (q ? 4 : 2); pass++) {
-                    TCGv_i32 tmpf = neon_load_reg(rm, pass);
-                    fn(tmpf, tmpf, shiftv, fpst);
-                    neon_store_reg(rd, pass, tmpf);
-                }
-                tcg_temp_free_ptr(fpst);
-                tcg_temp_free_i32(shiftv);
-            } else {
-                return 1;
-            }
+            /* Two registers and shift: handled by decodetree */
+            return 1;
         } else { /* (insn & 0x00380080) == 0 */
             int invert, reg_ofs, vec_size;
 
-- 
2.20.1

Convert the insns in the one-register-and-immediate group to decodetree.

In the new decode, our asimd_imm_const() function returns a 64-bit value
rather than a 32-bit one, which means we don't need to treat cmode=14 op=1
as a special case in the decoder (it is the only encoding where the two
halves of the 64-bit value are different).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-10-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  22 ++++++
 target/arm/translate-neon.inc.c | 118 ++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 101 +--------------------------
 3 files changed, 142 insertions(+), 99 deletions(-)