1 | Mostly my decodetree stuff, but also some patches for various | 1 | Hi; here's the first target-arm pullreq for the 7.0 cycle. |
---|---|---|---|
2 | smaller bugs/features from others. | ||
3 | 2 | ||
4 | thanks | 3 | thanks |
5 | -- PMM | 4 | -- PMM |
6 | 5 | ||
7 | The following changes since commit 53550e81e2cafe7c03a39526b95cd21b5194d9b1: | 6 | The following changes since commit 76b56fdfc9fa43ec6e5986aee33f108c6c6a511e: |
8 | 7 | ||
9 | Merge remote-tracking branch 'remotes/berrange/tags/qcrypto-next-pull-request' into staging (2020-06-15 16:36:34 +0100) | 8 | Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2021-12-14 12:46:18 -0800) |
10 | 9 | ||
11 | are available in the Git repository at: | 10 | are available in the Git repository at: |
12 | 11 | ||
13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200616 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211215 |
14 | 13 | ||
15 | for you to fetch changes up to 64b397417a26509bcdff44ab94356a35c7901c79: | 14 | for you to fetch changes up to aed176558806674d030a8305d989d4e6a5073359: |
16 | 15 | ||
17 | hw: arm: Set vendor property for IMX SDHCI emulations (2020-06-16 10:32:29 +0100) | 16 | tests/acpi: add expected blob for VIOT test on virt machine (2021-12-15 10:35:26 +0000) |
18 | 17 | ||
19 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
20 | * hw: arm: Set vendor property for IMX SDHCI emulations | 19 | target-arm queue: |
21 | * sd: sdhci: Implement basic vendor specific register support | 20 | * ITS: error reporting cleanup |
22 | * hw/net/imx_fec: Convert debug fprintf() to trace events | 21 | * aspeed: improve documentation |
23 | * target/arm/cpu: adjust virtual time for all KVM arm cpus | 22 | * Fix STM32F2XX USART data register readout |
24 | * Implement configurable descriptor size in ftgmac100 | 23 | * allow emulated GICv3 to be disabled in non-TCG builds |
25 | * hw/misc/imx6ul_ccm: Implement non writable bits in CCM registers | 24 | * fix exception priority for singlestep, misaligned PC, bp, etc |
26 | * target/arm: More Neon decodetree conversion work | 25 | * Correct calculation of tlb range invalidate length |
26 | * npcm7xx_emc: fix missing queue_flush | ||
27 | * virt: Add VIOT ACPI table for virtio-iommu | ||
28 | * target/i386: Use assert() to sanity-check b1 in SSE decode | ||
29 | * Don't include qemu-common unnecessarily | ||
27 | 30 | ||
28 | ---------------------------------------------------------------- | 31 | ---------------------------------------------------------------- |
29 | Erik Smit (1): | 32 | Alex Bennée (1): |
30 | Implement configurable descriptor size in ftgmac100 | 33 | hw/intc: clean-up error reporting for failed ITS cmd |
31 | 34 | ||
32 | Guenter Roeck (2): | 35 | Jean-Philippe Brucker (8): |
33 | sd: sdhci: Implement basic vendor specific register support | 36 | hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu |
34 | hw: arm: Set vendor property for IMX SDHCI emulations | 37 | hw/arm/virt: Remove device tree restriction for virtio-iommu |
38 | hw/arm/virt: Reject instantiation of multiple IOMMUs | ||
39 | hw/arm/virt: Use object_property_set instead of qdev_prop_set | ||
40 | tests/acpi: allow updates of VIOT expected data files | ||
41 | tests/acpi: add test case for VIOT | ||
42 | tests/acpi: add expected blobs for VIOT test on q35 machine | ||
43 | tests/acpi: add expected blob for VIOT test on virt machine | ||
35 | 44 | ||
36 | Jean-Christophe Dubois (2): | 45 | Joel Stanley (4): |
37 | hw/misc/imx6ul_ccm: Implement non writable bits in CCM registers | 46 | docs: aspeed: Add new boards |
38 | hw/net/imx_fec: Convert debug fprintf() to trace events | 47 | docs: aspeed: Update OpenBMC image URL |
48 | docs: aspeed: Give an example of booting a kernel | ||
49 | docs: aspeed: ADC is now modelled | ||
39 | 50 | ||
40 | Peter Maydell (17): | 51 | Olivier Hériveaux (1): |
41 | target/arm: Fix missing temp frees in do_vshll_2sh | 52 | Fix STM32F2XX USART data register readout |
42 | target/arm: Convert Neon 3-reg-diff prewidening ops to decodetree | ||
43 | target/arm: Convert Neon 3-reg-diff narrowing ops to decodetree | ||
44 | target/arm: Convert Neon 3-reg-diff VABAL, VABDL to decodetree | ||
45 | target/arm: Convert Neon 3-reg-diff long multiplies | ||
46 | target/arm: Convert Neon 3-reg-diff saturating doubling multiplies | ||
47 | target/arm: Convert Neon 3-reg-diff polynomial VMULL | ||
48 | target/arm: Add 'static' and 'const' annotations to VSHLL function arrays | ||
49 | target/arm: Add missing TCG temp free in do_2shift_env_64() | ||
50 | target/arm: Convert Neon 2-reg-scalar integer multiplies to decodetree | ||
51 | target/arm: Convert Neon 2-reg-scalar float multiplies to decodetree | ||
52 | target/arm: Convert Neon 2-reg-scalar VQDMULH, VQRDMULH to decodetree | ||
53 | target/arm: Convert Neon 2-reg-scalar VQRDMLAH, VQRDMLSH to decodetree | ||
54 | target/arm: Convert Neon 2-reg-scalar long multiplies to decodetree | ||
55 | target/arm: Convert Neon VEXT to decodetree | ||
56 | target/arm: Convert Neon VTBL, VTBX to decodetree | ||
57 | target/arm: Convert Neon VDUP (scalar) to decodetree | ||
58 | 53 | ||
59 | fangying (1): | 54 | Patrick Venture (1): |
60 | target/arm/cpu: adjust virtual time for all KVM arm cpus | 55 | hw/net: npcm7xx_emc fix missing queue_flush |
61 | 56 | ||
62 | hw/sd/sdhci-internal.h | 5 + | 57 | Peter Maydell (6): |
63 | include/hw/sd/sdhci.h | 5 + | 58 | target/i386: Use assert() to sanity-check b1 in SSE decode |
64 | target/arm/translate.h | 1 + | 59 | include/hw/i386: Don't include qemu-common.h in .h files |
65 | target/arm/neon-dp.decode | 130 +++++ | 60 | target/hexagon/cpu.h: don't include qemu-common.h |
66 | hw/arm/fsl-imx25.c | 6 + | 61 | target/rx/cpu.h: Don't include qemu-common.h |
67 | hw/arm/fsl-imx6.c | 6 + | 62 | hw/arm: Don't include qemu-common.h unnecessarily |
68 | hw/arm/fsl-imx6ul.c | 2 + | 63 | target/arm: Correct calculation of tlb range invalidate length |
69 | hw/arm/fsl-imx7.c | 2 + | ||
70 | hw/misc/imx6ul_ccm.c | 76 ++- | ||
71 | hw/net/ftgmac100.c | 26 +- | ||
72 | hw/net/imx_fec.c | 106 ++-- | ||
73 | hw/sd/sdhci.c | 18 +- | ||
74 | target/arm/cpu.c | 6 +- | ||
75 | target/arm/cpu64.c | 1 - | ||
76 | target/arm/kvm.c | 21 +- | ||
77 | target/arm/translate-neon.inc.c | 1148 ++++++++++++++++++++++++++++++++++++++- | ||
78 | target/arm/translate.c | 684 +---------------------- | ||
79 | hw/net/trace-events | 18 + | ||
80 | 18 files changed, 1495 insertions(+), 766 deletions(-) | ||
81 | 64 | ||
65 | Philippe Mathieu-Daudé (2): | ||
66 | hw/intc/arm_gicv3: Extract gicv3_set_gicv3state from arm_gicv3_cpuif.c | ||
67 | hw/intc/arm_gicv3: Introduce CONFIG_ARM_GIC_TCG Kconfig selector | ||
68 | |||
69 | Richard Henderson (10): | ||
70 | target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn | ||
71 | target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn | ||
72 | target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn | ||
73 | target/arm: Split arm_pre_translate_insn | ||
74 | target/arm: Advance pc for arch single-step exception | ||
75 | target/arm: Split compute_fsr_fsc out of arm_deliver_fault | ||
76 | target/arm: Take an exception if PC is misaligned | ||
77 | target/arm: Assert thumb pc is aligned | ||
78 | target/arm: Suppress bp for exceptions with more priority | ||
79 | tests/tcg: Add arm and aarch64 pc alignment tests | ||
80 | |||
81 | docs/system/arm/aspeed.rst | 26 ++++++++++++---- | ||
82 | include/hw/i386/microvm.h | 1 - | ||
83 | include/hw/i386/x86.h | 1 - | ||
84 | target/arm/helper.h | 1 + | ||
85 | target/arm/syndrome.h | 5 +++ | ||
86 | target/hexagon/cpu.h | 1 - | ||
87 | target/rx/cpu.h | 1 - | ||
88 | hw/arm/boot.c | 1 - | ||
89 | hw/arm/digic_boards.c | 1 - | ||
90 | hw/arm/highbank.c | 1 - | ||
91 | hw/arm/npcm7xx_boards.c | 1 - | ||
92 | hw/arm/sbsa-ref.c | 1 - | ||
93 | hw/arm/stm32f405_soc.c | 1 - | ||
94 | hw/arm/vexpress.c | 1 - | ||
95 | hw/arm/virt-acpi-build.c | 7 +++++ | ||
96 | hw/arm/virt.c | 21 ++++++------- | ||
97 | hw/char/stm32f2xx_usart.c | 3 +- | ||
98 | hw/intc/arm_gicv3.c | 2 +- | ||
99 | hw/intc/arm_gicv3_cpuif.c | 10 +----- | ||
100 | hw/intc/arm_gicv3_cpuif_common.c | 22 +++++++++++++ | ||
101 | hw/intc/arm_gicv3_its.c | 39 +++++++++++++++-------- | ||
102 | hw/net/npcm7xx_emc.c | 18 +++++------ | ||
103 | hw/virtio/virtio-iommu-pci.c | 12 ++------ | ||
104 | linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++------------ | ||
105 | linux-user/hexagon/cpu_loop.c | 1 + | ||
106 | target/arm/debug_helper.c | 23 ++++++++++++++ | ||
107 | target/arm/gdbstub.c | 9 ++++-- | ||
108 | target/arm/helper.c | 6 ++-- | ||
109 | target/arm/machine.c | 10 ++++++ | ||
110 | target/arm/tlb_helper.c | 63 ++++++++++++++++++++++++++++---------- | ||
111 | target/arm/translate-a64.c | 23 ++++++++++++-- | ||
112 | target/arm/translate.c | 58 ++++++++++++++++++++++++++--------- | ||
113 | target/i386/tcg/translate.c | 12 ++------ | ||
114 | tests/qtest/bios-tables-test.c | 38 +++++++++++++++++++++++ | ||
115 | tests/tcg/aarch64/pcalign-a64.c | 37 ++++++++++++++++++++++ | ||
116 | tests/tcg/arm/pcalign-a32.c | 46 ++++++++++++++++++++++++++++ | ||
117 | hw/arm/Kconfig | 1 + | ||
118 | hw/intc/Kconfig | 5 +++ | ||
119 | hw/intc/meson.build | 11 ++++--- | ||
120 | tests/data/acpi/q35/DSDT.viot | Bin 0 -> 9398 bytes | ||
121 | tests/data/acpi/q35/VIOT.viot | Bin 0 -> 112 bytes | ||
122 | tests/data/acpi/virt/VIOT | Bin 0 -> 88 bytes | ||
123 | tests/tcg/aarch64/Makefile.target | 4 +-- | ||
124 | tests/tcg/arm/Makefile.target | 4 +++ | ||
125 | 44 files changed, 429 insertions(+), 145 deletions(-) | ||
126 | create mode 100644 hw/intc/arm_gicv3_cpuif_common.c | ||
127 | create mode 100644 tests/tcg/aarch64/pcalign-a64.c | ||
128 | create mode 100644 tests/tcg/arm/pcalign-a32.c | ||
129 | create mode 100644 tests/data/acpi/q35/DSDT.viot | ||
130 | create mode 100644 tests/data/acpi/q35/VIOT.viot | ||
131 | create mode 100644 tests/data/acpi/virt/VIOT | ||
132 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Alex Bennée <alex.bennee@linaro.org> | ||
1 | 2 | ||
3 | While trying to debug a GIC ITS failure I saw some guest errors that | ||
4 | had poor formatting as well as leaving me confused as to what failed. | ||
5 | As most of the checks aren't possible without a valid dte split that | ||
6 | check apart and then check the other conditions in steps. This avoids | ||
7 | us relying on undefined data. | ||
8 | |||
9 | I still get a failure with the current kvm-unit-tests but at least I | ||
10 | know (partially) why now: | ||
11 | |||
12 | Exception return from AArch64 EL1 to AArch64 EL1 PC 0x40080588 | ||
13 | PASS: gicv3: its-trigger: inv/invall: dev2/eventid=20 now triggers an LPI | ||
14 | ITS: MAPD devid=2 size = 0x8 itt=0x40430000 valid=0 | ||
15 | INT dev_id=2 event_id=20 | ||
16 | process_its_cmd: invalid command attributes: invalid dte: 0 for 2 (MEM_TX: 0) | ||
17 | PASS: gicv3: its-trigger: mapd valid=false: no LPI after device unmap | ||
18 | SUMMARY: 6 tests, 1 unexpected failures | ||
19 | |||
20 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
21 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
22 | Message-id: 20211112170454.3158925-1-alex.bennee@linaro.org | ||
23 | Cc: Shashi Mallela <shashi.mallela@linaro.org> | ||
24 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
26 | --- | ||
27 | hw/intc/arm_gicv3_its.c | 39 +++++++++++++++++++++++++++------------ | ||
28 | 1 file changed, 27 insertions(+), 12 deletions(-) | ||
29 | |||
30 | diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/hw/intc/arm_gicv3_its.c | ||
33 | +++ b/hw/intc/arm_gicv3_its.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static bool process_its_cmd(GICv3ITSState *s, uint64_t value, uint32_t offset, | ||
35 | if (res != MEMTX_OK) { | ||
36 | return result; | ||
37 | } | ||
38 | + } else { | ||
39 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
40 | + "%s: invalid command attributes: " | ||
41 | + "invalid dte: %"PRIx64" for %d (MEM_TX: %d)\n", | ||
42 | + __func__, dte, devid, res); | ||
43 | + return result; | ||
44 | } | ||
45 | |||
46 | - if ((devid > s->dt.maxids.max_devids) || !dte_valid || !ite_valid || | ||
47 | - !cte_valid || (eventid > max_eventid)) { | ||
48 | + | ||
49 | + /* | ||
50 | + * In this implementation, in case of guest errors we ignore the | ||
51 | + * command and move onto the next command in the queue. | ||
52 | + */ | ||
53 | + if (devid > s->dt.maxids.max_devids) { | ||
54 | qemu_log_mask(LOG_GUEST_ERROR, | ||
55 | - "%s: invalid command attributes " | ||
56 | - "devid %d or eventid %d or invalid dte %d or" | ||
57 | - "invalid cte %d or invalid ite %d\n", | ||
58 | - __func__, devid, eventid, dte_valid, cte_valid, | ||
59 | - ite_valid); | ||
60 | - /* | ||
61 | - * in this implementation, in case of error | ||
62 | - * we ignore this command and move onto the next | ||
63 | - * command in the queue | ||
64 | - */ | ||
65 | + "%s: invalid command attributes: devid %d>%d", | ||
66 | + __func__, devid, s->dt.maxids.max_devids); | ||
67 | + | ||
68 | + } else if (!dte_valid || !ite_valid || !cte_valid) { | ||
69 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
70 | + "%s: invalid command attributes: " | ||
71 | + "dte: %s, ite: %s, cte: %s\n", | ||
72 | + __func__, | ||
73 | + dte_valid ? "valid" : "invalid", | ||
74 | + ite_valid ? "valid" : "invalid", | ||
75 | + cte_valid ? "valid" : "invalid"); | ||
76 | + } else if (eventid > max_eventid) { | ||
77 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
78 | + "%s: invalid command attributes: eventid %d > %d\n", | ||
79 | + __func__, eventid, max_eventid); | ||
80 | } else { | ||
81 | /* | ||
82 | * Current implementation only supports rdbase == procnum | ||
83 | -- | ||
84 | 2.25.1 | ||
85 | |||
86 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Joel Stanley <joel@jms.id.au> | ||
1 | 2 | ||
3 | Add X11, FP5280G2, G220A, Rainier and Fuji. Mention that Swift will be | ||
4 | removed in v7.0. | ||
5 | |||
6 | Signed-off-by: Joel Stanley <joel@jms.id.au> | ||
7 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
8 | Message-id: 20211117065752.330632-2-joel@jms.id.au | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | docs/system/arm/aspeed.rst | 7 ++++++- | ||
12 | 1 file changed, 6 insertions(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/docs/system/arm/aspeed.rst | ||
17 | +++ b/docs/system/arm/aspeed.rst | ||
18 | @@ -XXX,XX +XXX,XX @@ AST2400 SoC based machines : | ||
19 | |||
20 | - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC | ||
21 | - ``quanta-q71l-bmc`` OpenBMC Quanta BMC | ||
22 | +- ``supermicrox11-bmc`` Supermicro X11 BMC | ||
23 | |||
24 | AST2500 SoC based machines : | ||
25 | |||
26 | @@ -XXX,XX +XXX,XX @@ AST2500 SoC based machines : | ||
27 | - ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC | ||
28 | - ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC | ||
29 | - ``sonorapass-bmc`` OCP SonoraPass BMC | ||
30 | -- ``swift-bmc`` OpenPOWER Swift BMC POWER9 | ||
31 | +- ``swift-bmc`` OpenPOWER Swift BMC POWER9 (to be removed in v7.0) | ||
32 | +- ``fp5280g2-bmc`` Inspur FP5280G2 BMC | ||
33 | +- ``g220a-bmc`` Bytedance G220A BMC | ||
34 | |||
35 | AST2600 SoC based machines : | ||
36 | |||
37 | - ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex-A7) | ||
38 | - ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC | ||
39 | +- ``rainier-bmc`` IBM Rainier POWER10 BMC | ||
40 | +- ``fuji-bmc`` Facebook Fuji BMC | ||
41 | |||
42 | Supported devices | ||
43 | ----------------- | ||
44 | -- | ||
45 | 2.25.1 | ||
46 | |||
47 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Joel Stanley <joel@jms.id.au> | ||
1 | 2 | ||
3 | This is the latest URL for the OpenBMC CI. The old URL still works, but | ||
4 | redirects. | ||
5 | |||
6 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
7 | Signed-off-by: Joel Stanley <joel@jms.id.au> | ||
8 | Message-id: 20211117065752.330632-3-joel@jms.id.au | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | docs/system/arm/aspeed.rst | 2 +- | ||
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/docs/system/arm/aspeed.rst | ||
17 | +++ b/docs/system/arm/aspeed.rst | ||
18 | @@ -XXX,XX +XXX,XX @@ The Aspeed machines can be started using the ``-kernel`` option to | ||
19 | load a Linux kernel or from a firmware. Images can be downloaded from | ||
20 | the OpenBMC jenkins : | ||
21 | |||
22 | - https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/distro=ubuntu,label=docker-builder | ||
23 | + https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/ | ||
24 | |||
25 | or directly from the OpenBMC GitHub release repository : | ||
26 | |||
27 | -- | ||
28 | 2.25.1 | ||
29 | |||
30 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Joel Stanley <joel@jms.id.au> | ||
1 | 2 | ||
3 | A common use case for the ASPEED machine is to boot a Linux kernel. | ||
4 | Provide a full example command line. | ||
5 | |||
6 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
7 | Signed-off-by: Joel Stanley <joel@jms.id.au> | ||
8 | Message-id: 20211117065752.330632-4-joel@jms.id.au | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | docs/system/arm/aspeed.rst | 15 ++++++++++++--- | ||
12 | 1 file changed, 12 insertions(+), 3 deletions(-) | ||
13 | |||
14 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/docs/system/arm/aspeed.rst | ||
17 | +++ b/docs/system/arm/aspeed.rst | ||
18 | @@ -XXX,XX +XXX,XX @@ Missing devices | ||
19 | Boot options | ||
20 | ------------ | ||
21 | |||
22 | -The Aspeed machines can be started using the ``-kernel`` option to | ||
23 | -load a Linux kernel or from a firmware. Images can be downloaded from | ||
24 | -the OpenBMC jenkins : | ||
25 | +The Aspeed machines can be started using the ``-kernel`` and ``-dtb`` options | ||
26 | +to load a Linux kernel or from a firmware. Images can be downloaded from the | ||
27 | +OpenBMC jenkins : | ||
28 | |||
29 | https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/ | ||
30 | |||
31 | @@ -XXX,XX +XXX,XX @@ or directly from the OpenBMC GitHub release repository : | ||
32 | |||
33 | https://github.com/openbmc/openbmc/releases | ||
34 | |||
35 | +To boot a kernel directly from a Linux build tree: | ||
36 | + | ||
37 | +.. code-block:: bash | ||
38 | + | ||
39 | + $ qemu-system-arm -M ast2600-evb -nographic \ | ||
40 | + -kernel arch/arm/boot/zImage \ | ||
41 | + -dtb arch/arm/boot/dts/aspeed-ast2600-evb.dtb \ | ||
42 | + -initrd rootfs.cpio | ||
43 | + | ||
44 | The image should be attached as an MTD drive. Run : | ||
45 | |||
46 | .. code-block:: bash | ||
47 | -- | ||
48 | 2.25.1 | ||
49 | |||
50 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Joel Stanley <joel@jms.id.au> | ||
1 | 2 | ||
3 | Move it to the supported list. | ||
4 | |||
5 | Signed-off-by: Joel Stanley <joel@jms.id.au> | ||
6 | Message-id: 20211117065752.330632-5-joel@jms.id.au | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | --- | ||
9 | docs/system/arm/aspeed.rst | 2 +- | ||
10 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
11 | |||
12 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/docs/system/arm/aspeed.rst | ||
15 | +++ b/docs/system/arm/aspeed.rst | ||
16 | @@ -XXX,XX +XXX,XX @@ Supported devices | ||
17 | * Front LEDs (PCA9552 on I2C bus) | ||
18 | * LPC Peripheral Controller (a subset of subdevices are supported) | ||
19 | * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA | ||
20 | + * ADC | ||
21 | |||
22 | |||
23 | Missing devices | ||
24 | --------------- | ||
25 | |||
26 | * Coprocessor support | ||
27 | - * ADC (out of tree implementation) | ||
28 | * PWM and Fan Controller | ||
29 | * Slave GPIO Controller | ||
30 | * Super I/O Controller | ||
31 | -- | ||
32 | 2.25.1 | ||
33 | |||
34 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Olivier Hériveaux <olivier.heriveaux@ledger.fr> | ||
1 | 2 | ||
3 | Fix issue where the data register may be overwritten by next character | ||
4 | reception before being read and returned. | ||
5 | |||
6 | Signed-off-by: Olivier Hériveaux <olivier.heriveaux@ledger.fr> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
9 | Message-id: 20211128120723.4053-1-olivier.heriveaux@ledger.fr | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/char/stm32f2xx_usart.c | 3 ++- | ||
13 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
14 | |||
15 | diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/char/stm32f2xx_usart.c | ||
18 | +++ b/hw/char/stm32f2xx_usart.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr, | ||
20 | return retvalue; | ||
21 | case USART_DR: | ||
22 | DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr); | ||
23 | + retvalue = s->usart_dr & 0x3FF; | ||
24 | s->usart_sr &= ~USART_SR_RXNE; | ||
25 | qemu_chr_fe_accept_input(&s->chr); | ||
26 | qemu_set_irq(s->irq, 0); | ||
27 | - return s->usart_dr & 0x3FF; | ||
28 | + return retvalue; | ||
29 | case USART_BRR: | ||
30 | return s->usart_brr; | ||
31 | case USART_CR1: | ||
32 | -- | ||
33 | 2.25.1 | ||
34 | |||
35 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
1 | 2 | ||
3 | gicv3_set_gicv3state() is used by arm_gicv3_common.c in | ||
4 | arm_gicv3_common_realize(). Since we want to restrict | ||
5 | arm_gicv3_cpuif.c to TCG, extract gicv3_set_gicv3state() | ||
6 | to a new file. Add this file to the meson 'specific' | ||
7 | source set, since it needs access to "cpu.h". | ||
8 | |||
9 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Message-id: 20211115223619.2599282-2-philmd@redhat.com | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | hw/intc/arm_gicv3_cpuif.c | 10 +--------- | ||
15 | hw/intc/arm_gicv3_cpuif_common.c | 22 ++++++++++++++++++++++ | ||
16 | hw/intc/meson.build | 1 + | ||
17 | 3 files changed, 24 insertions(+), 9 deletions(-) | ||
18 | create mode 100644 hw/intc/arm_gicv3_cpuif_common.c | ||
19 | |||
20 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/hw/intc/arm_gicv3_cpuif.c | ||
23 | +++ b/hw/intc/arm_gicv3_cpuif.c | ||
24 | @@ -XXX,XX +XXX,XX @@ | ||
25 | /* | ||
26 | - * ARM Generic Interrupt Controller v3 | ||
27 | + * ARM Generic Interrupt Controller v3 (emulation) | ||
28 | * | ||
29 | * Copyright (c) 2016 Linaro Limited | ||
30 | * Written by Peter Maydell | ||
31 | @@ -XXX,XX +XXX,XX @@ | ||
32 | #include "hw/irq.h" | ||
33 | #include "cpu.h" | ||
34 | |||
35 | -void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) | ||
36 | -{ | ||
37 | - ARMCPU *arm_cpu = ARM_CPU(cpu); | ||
38 | - CPUARMState *env = &arm_cpu->env; | ||
39 | - | ||
40 | - env->gicv3state = (void *)s; | ||
41 | -}; | ||
42 | - | ||
43 | static GICv3CPUState *icc_cs_from_env(CPUARMState *env) | ||
44 | { | ||
45 | return env->gicv3state; | ||
46 | diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/intc/arm_gicv3_cpuif_common.c | ||
47 | new file mode 100644 | ||
48 | index XXXXXXX..XXXXXXX | ||
49 | --- /dev/null | ||
50 | +++ b/hw/intc/arm_gicv3_cpuif_common.c | ||
51 | @@ -XXX,XX +XXX,XX @@ | ||
52 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ | ||
53 | +/* | ||
54 | + * ARM Generic Interrupt Controller v3 | ||
55 | + * | ||
56 | + * Copyright (c) 2016 Linaro Limited | ||
57 | + * Written by Peter Maydell | ||
58 | + * | ||
59 | + * This code is licensed under the GPL, version 2 or (at your option) | ||
60 | + * any later version. | ||
61 | + */ | ||
62 | + | ||
63 | +#include "qemu/osdep.h" | ||
64 | +#include "gicv3_internal.h" | ||
65 | +#include "cpu.h" | ||
66 | + | ||
67 | +void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) | ||
68 | +{ | ||
69 | + ARMCPU *arm_cpu = ARM_CPU(cpu); | ||
70 | + CPUARMState *env = &arm_cpu->env; | ||
71 | + | ||
72 | + env->gicv3state = (void *)s; | ||
73 | +}; | ||
74 | diff --git a/hw/intc/meson.build b/hw/intc/meson.build | ||
75 | index XXXXXXX..XXXXXXX 100644 | ||
76 | --- a/hw/intc/meson.build | ||
77 | +++ b/hw/intc/meson.build | ||
78 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in | ||
79 | |||
80 | specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c')) | ||
81 | specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c')) | ||
82 | +specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c')) | ||
83 | specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c')) | ||
84 | specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c')) | ||
85 | specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) | ||
86 | -- | ||
87 | 2.25.1 | ||
88 | |||
89 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
1 | 2 | ||
3 | The TYPE_ARM_GICV3 device is an emulated one. When using | ||
4 | KVM, it is recommended to use the TYPE_KVM_ARM_GICV3 device | ||
5 | (which uses in-kernel support). | ||
6 | |||
7 | When using --with-devices-FOO, it is possible to build a | ||
8 | binary with a specific set of devices. When this binary is | ||
9 | restricted to KVM accelerator, the TYPE_ARM_GICV3 device is | ||
10 | irrelevant, and it is desirable to remove it from the binary. | ||
11 | |||
12 | Therefore introduce the CONFIG_ARM_GIC_TCG Kconfig selector | ||
13 | which select the files required to have the TYPE_ARM_GICV3 | ||
14 | device, but also allowing to de-select this device. | ||
15 | |||
16 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Message-id: 20211115223619.2599282-3-philmd@redhat.com | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
20 | --- | ||
21 | hw/intc/arm_gicv3.c | 2 +- | ||
22 | hw/intc/Kconfig | 5 +++++ | ||
23 | hw/intc/meson.build | 10 ++++++---- | ||
24 | 3 files changed, 12 insertions(+), 5 deletions(-) | ||
25 | |||
26 | diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/hw/intc/arm_gicv3.c | ||
29 | +++ b/hw/intc/arm_gicv3.c | ||
30 | @@ -XXX,XX +XXX,XX @@ | ||
31 | /* | ||
32 | - * ARM Generic Interrupt Controller v3 | ||
33 | + * ARM Generic Interrupt Controller v3 (emulation) | ||
34 | * | ||
35 | * Copyright (c) 2015 Huawei. | ||
36 | * Copyright (c) 2016 Linaro Limited | ||
37 | diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/hw/intc/Kconfig | ||
40 | +++ b/hw/intc/Kconfig | ||
41 | @@ -XXX,XX +XXX,XX @@ config APIC | ||
42 | select MSI_NONBROKEN | ||
43 | select I8259 | ||
44 | |||
45 | +config ARM_GIC_TCG | ||
46 | + bool | ||
47 | + default y | ||
48 | + depends on ARM_GIC && TCG | ||
49 | + | ||
50 | config ARM_GIC_KVM | ||
51 | bool | ||
52 | default y | ||
53 | diff --git a/hw/intc/meson.build b/hw/intc/meson.build | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/hw/intc/meson.build | ||
56 | +++ b/hw/intc/meson.build | ||
57 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files( | ||
58 | 'arm_gic.c', | ||
59 | 'arm_gic_common.c', | ||
60 | 'arm_gicv2m.c', | ||
61 | - 'arm_gicv3.c', | ||
62 | 'arm_gicv3_common.c', | ||
63 | - 'arm_gicv3_dist.c', | ||
64 | 'arm_gicv3_its_common.c', | ||
65 | - 'arm_gicv3_redist.c', | ||
66 | +)) | ||
67 | +softmmu_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files( | ||
68 | + 'arm_gicv3.c', | ||
69 | + 'arm_gicv3_dist.c', | ||
70 | 'arm_gicv3_its.c', | ||
71 | + 'arm_gicv3_redist.c', | ||
72 | )) | ||
73 | softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c')) | ||
74 | softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c')) | ||
75 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in | ||
76 | specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c')) | ||
77 | specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c')) | ||
78 | specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c')) | ||
79 | -specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c')) | ||
80 | +specific_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files('arm_gicv3_cpuif.c')) | ||
81 | specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c')) | ||
82 | specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) | ||
83 | specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) | ||
84 | -- | ||
85 | 2.25.1 | ||
86 | |||
87 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | --- | ||
7 | target/arm/translate-a64.c | 7 ++++--- | ||
8 | 1 file changed, 4 insertions(+), 3 deletions(-) | ||
9 | |||
10 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/arm/translate-a64.c | ||
13 | +++ b/target/arm/translate-a64.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
15 | { | ||
16 | DisasContext *s = container_of(dcbase, DisasContext, base); | ||
17 | CPUARMState *env = cpu->env_ptr; | ||
18 | + uint64_t pc = s->base.pc_next; | ||
19 | uint32_t insn; | ||
20 | |||
21 | if (s->ss_active && !s->pstate_ss) { | ||
22 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
23 | return; | ||
24 | } | ||
25 | |||
26 | - s->pc_curr = s->base.pc_next; | ||
27 | - insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b); | ||
28 | + s->pc_curr = pc; | ||
29 | + insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b); | ||
30 | s->insn = insn; | ||
31 | - s->base.pc_next += 4; | ||
32 | + s->base.pc_next = pc + 4; | ||
33 | |||
34 | s->fp_access_checked = false; | ||
35 | s->sve_access_checked = false; | ||
36 | -- | ||
37 | 2.25.1 | ||
38 | |||
39 | diff view generated by jsdifflib |
1 | Convert the Neon VDUP (scalar) insn to decodetree. (Note that we | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | can't call this just "VDUP" as we used that already in vfp.decode for | ||
3 | the "VDUP (general purpose register" insn.) | ||
4 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | --- | 6 | --- |
8 | target/arm/neon-dp.decode | 7 +++++++ | 7 | target/arm/translate.c | 9 +++++---- |
9 | target/arm/translate-neon.inc.c | 26 ++++++++++++++++++++++++++ | 8 | 1 file changed, 5 insertions(+), 4 deletions(-) |
10 | target/arm/translate.c | 25 +------------------------ | ||
11 | 3 files changed, 34 insertions(+), 24 deletions(-) | ||
12 | 9 | ||
13 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/neon-dp.decode | ||
16 | +++ b/target/arm/neon-dp.decode | ||
17 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
18 | |||
19 | VTBL 1111 001 1 1 . 11 .... .... 10 len:2 . op:1 . 0 .... \ | ||
20 | vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
21 | + | ||
22 | + VDUP_scalar 1111 001 1 1 . 11 index:3 1 .... 11 000 q:1 . 0 .... \ | ||
23 | + vm=%vm_dp vd=%vd_dp size=0 | ||
24 | + VDUP_scalar 1111 001 1 1 . 11 index:2 10 .... 11 000 q:1 . 0 .... \ | ||
25 | + vm=%vm_dp vd=%vd_dp size=1 | ||
26 | + VDUP_scalar 1111 001 1 1 . 11 index:1 100 .... 11 000 q:1 . 0 .... \ | ||
27 | + vm=%vm_dp vd=%vd_dp size=2 | ||
28 | ] | ||
29 | |||
30 | # Subgroup for size != 0b11 | ||
31 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/target/arm/translate-neon.inc.c | ||
34 | +++ b/target/arm/translate-neon.inc.c | ||
35 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
36 | tcg_temp_free_i32(tmp); | ||
37 | return true; | ||
38 | } | ||
39 | + | ||
40 | +static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a) | ||
41 | +{ | ||
42 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
43 | + return false; | ||
44 | + } | ||
45 | + | ||
46 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
47 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
48 | + ((a->vd | a->vm) & 0x10)) { | ||
49 | + return false; | ||
50 | + } | ||
51 | + | ||
52 | + if (a->vd & a->q) { | ||
53 | + return false; | ||
54 | + } | ||
55 | + | ||
56 | + if (!vfp_access_check(s)) { | ||
57 | + return true; | ||
58 | + } | ||
59 | + | ||
60 | + tcg_gen_gvec_dup_mem(a->size, neon_reg_offset(a->vd, 0), | ||
61 | + neon_element_offset(a->vm, a->index, a->size), | ||
62 | + a->q ? 16 : 8, a->q ? 16 : 8); | ||
63 | + return true; | ||
64 | +} | ||
65 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 10 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
66 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
67 | --- a/target/arm/translate.c | 12 | --- a/target/arm/translate.c |
68 | +++ b/target/arm/translate.c | 13 | +++ b/target/arm/translate.c |
69 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 14 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
70 | } | 15 | { |
71 | break; | 16 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
72 | } | 17 | CPUARMState *env = cpu->env_ptr; |
73 | - } else if ((insn & (1 << 10)) == 0) { | 18 | + uint32_t pc = dc->base.pc_next; |
74 | - /* VTBL, VTBX: handled by decodetree */ | 19 | unsigned int insn; |
75 | - return 1; | 20 | |
76 | - } else if ((insn & 0x380) == 0) { | 21 | if (arm_pre_translate_insn(dc)) { |
77 | - /* VDUP */ | 22 | - dc->base.pc_next += 4; |
78 | - int element; | 23 | + dc->base.pc_next = pc + 4; |
79 | - MemOp size; | 24 | return; |
80 | - | 25 | } |
81 | - if ((insn & (7 << 16)) == 0 || (q && (rd & 1))) { | 26 | |
82 | - return 1; | 27 | - dc->pc_curr = dc->base.pc_next; |
83 | - } | 28 | - insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); |
84 | - if (insn & (1 << 16)) { | 29 | + dc->pc_curr = pc; |
85 | - size = MO_8; | 30 | + insn = arm_ldl_code(env, &dc->base, pc, dc->sctlr_b); |
86 | - element = (insn >> 17) & 7; | 31 | dc->insn = insn; |
87 | - } else if (insn & (1 << 17)) { | 32 | - dc->base.pc_next += 4; |
88 | - size = MO_16; | 33 | + dc->base.pc_next = pc + 4; |
89 | - element = (insn >> 18) & 3; | 34 | disas_arm_insn(dc, insn); |
90 | - } else { | 35 | |
91 | - size = MO_32; | 36 | arm_post_translate_insn(dc); |
92 | - element = (insn >> 19) & 1; | ||
93 | - } | ||
94 | - tcg_gen_gvec_dup_mem(size, neon_reg_offset(rd, 0), | ||
95 | - neon_element_offset(rm, element, size), | ||
96 | - q ? 16 : 8, q ? 16 : 8); | ||
97 | } else { | ||
98 | + /* VTBL, VTBX, VDUP: handled by decodetree */ | ||
99 | return 1; | ||
100 | } | ||
101 | } | ||
102 | -- | 37 | -- |
103 | 2.20.1 | 38 | 2.25.1 |
104 | 39 | ||
105 | 40 | diff view generated by jsdifflib |
1 | Convert the Neon VTBL, VTBX instructions to decodetree. The actual | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | implementation of the insn is copied across to the new trans function | ||
3 | unchanged except for renaming 'tmp5' to 'tmp4'. | ||
4 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | --- | 6 | --- |
8 | target/arm/neon-dp.decode | 3 ++ | 7 | target/arm/translate.c | 16 ++++++++-------- |
9 | target/arm/translate-neon.inc.c | 56 +++++++++++++++++++++++++++++++++ | 8 | 1 file changed, 8 insertions(+), 8 deletions(-) |
10 | target/arm/translate.c | 41 +++--------------------- | ||
11 | 3 files changed, 63 insertions(+), 37 deletions(-) | ||
12 | 9 | ||
13 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/neon-dp.decode | ||
16 | +++ b/target/arm/neon-dp.decode | ||
17 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
18 | ################################################################## | ||
19 | VEXT 1111 001 0 1 . 11 .... .... imm:4 . q:1 . 0 .... \ | ||
20 | vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
21 | + | ||
22 | + VTBL 1111 001 1 1 . 11 .... .... 10 len:2 . op:1 . 0 .... \ | ||
23 | + vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
24 | ] | ||
25 | |||
26 | # Subgroup for size != 0b11 | ||
27 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/translate-neon.inc.c | ||
30 | +++ b/target/arm/translate-neon.inc.c | ||
31 | @@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) | ||
32 | } | ||
33 | return true; | ||
34 | } | ||
35 | + | ||
36 | +static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
37 | +{ | ||
38 | + int n; | ||
39 | + TCGv_i32 tmp, tmp2, tmp3, tmp4; | ||
40 | + TCGv_ptr ptr1; | ||
41 | + | ||
42 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
43 | + return false; | ||
44 | + } | ||
45 | + | ||
46 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
47 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
48 | + ((a->vd | a->vn | a->vm) & 0x10)) { | ||
49 | + return false; | ||
50 | + } | ||
51 | + | ||
52 | + if (!vfp_access_check(s)) { | ||
53 | + return true; | ||
54 | + } | ||
55 | + | ||
56 | + n = a->len + 1; | ||
57 | + if ((a->vn + n) > 32) { | ||
58 | + /* | ||
59 | + * This is UNPREDICTABLE; we choose to UNDEF to avoid the | ||
60 | + * helper function running off the end of the register file. | ||
61 | + */ | ||
62 | + return false; | ||
63 | + } | ||
64 | + n <<= 3; | ||
65 | + if (a->op) { | ||
66 | + tmp = neon_load_reg(a->vd, 0); | ||
67 | + } else { | ||
68 | + tmp = tcg_temp_new_i32(); | ||
69 | + tcg_gen_movi_i32(tmp, 0); | ||
70 | + } | ||
71 | + tmp2 = neon_load_reg(a->vm, 0); | ||
72 | + ptr1 = vfp_reg_ptr(true, a->vn); | ||
73 | + tmp4 = tcg_const_i32(n); | ||
74 | + gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4); | ||
75 | + tcg_temp_free_i32(tmp); | ||
76 | + if (a->op) { | ||
77 | + tmp = neon_load_reg(a->vd, 1); | ||
78 | + } else { | ||
79 | + tmp = tcg_temp_new_i32(); | ||
80 | + tcg_gen_movi_i32(tmp, 0); | ||
81 | + } | ||
82 | + tmp3 = neon_load_reg(a->vm, 1); | ||
83 | + gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4); | ||
84 | + tcg_temp_free_i32(tmp4); | ||
85 | + tcg_temp_free_ptr(ptr1); | ||
86 | + neon_store_reg(a->vd, 0, tmp2); | ||
87 | + neon_store_reg(a->vd, 1, tmp3); | ||
88 | + tcg_temp_free_i32(tmp); | ||
89 | + return true; | ||
90 | +} | ||
91 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 10 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
92 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
93 | --- a/target/arm/translate.c | 12 | --- a/target/arm/translate.c |
94 | +++ b/target/arm/translate.c | 13 | +++ b/target/arm/translate.c |
95 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 14 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
96 | { | 15 | { |
97 | int op; | 16 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
98 | int q; | 17 | CPUARMState *env = cpu->env_ptr; |
99 | - int rd, rn, rm, rd_ofs, rm_ofs; | 18 | + uint32_t pc = dc->base.pc_next; |
100 | + int rd, rm, rd_ofs, rm_ofs; | 19 | uint32_t insn; |
101 | int size; | 20 | bool is_16bit; |
102 | int pass; | 21 | |
103 | int u; | 22 | if (arm_pre_translate_insn(dc)) { |
104 | int vec_size; | 23 | - dc->base.pc_next += 2; |
105 | - TCGv_i32 tmp, tmp2, tmp3, tmp5; | 24 | + dc->base.pc_next = pc + 2; |
106 | - TCGv_ptr ptr1; | 25 | return; |
107 | + TCGv_i32 tmp, tmp2, tmp3; | 26 | } |
108 | 27 | ||
109 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | 28 | - dc->pc_curr = dc->base.pc_next; |
110 | return 1; | 29 | - insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); |
111 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 30 | + dc->pc_curr = pc; |
112 | q = (insn & (1 << 6)) != 0; | 31 | + insn = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b); |
113 | u = (insn >> 24) & 1; | 32 | is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn); |
114 | VFP_DREG_D(rd, insn); | 33 | - dc->base.pc_next += 2; |
115 | - VFP_DREG_N(rn, insn); | 34 | + pc += 2; |
116 | VFP_DREG_M(rm, insn); | 35 | if (!is_16bit) { |
117 | size = (insn >> 20) & 3; | 36 | - uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next, |
118 | vec_size = q ? 16 : 8; | 37 | - dc->sctlr_b); |
119 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 38 | - |
120 | break; | 39 | + uint32_t insn2 = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b); |
121 | } | 40 | insn = insn << 16 | insn2; |
122 | } else if ((insn & (1 << 10)) == 0) { | 41 | - dc->base.pc_next += 2; |
123 | - /* VTBL, VTBX. */ | 42 | + pc += 2; |
124 | - int n = ((insn >> 8) & 3) + 1; | 43 | } |
125 | - if ((rn + n) > 32) { | 44 | + dc->base.pc_next = pc; |
126 | - /* This is UNPREDICTABLE; we choose to UNDEF to avoid the | 45 | dc->insn = insn; |
127 | - * helper function running off the end of the register file. | 46 | |
128 | - */ | 47 | if (dc->pstate_il) { |
129 | - return 1; | ||
130 | - } | ||
131 | - n <<= 3; | ||
132 | - if (insn & (1 << 6)) { | ||
133 | - tmp = neon_load_reg(rd, 0); | ||
134 | - } else { | ||
135 | - tmp = tcg_temp_new_i32(); | ||
136 | - tcg_gen_movi_i32(tmp, 0); | ||
137 | - } | ||
138 | - tmp2 = neon_load_reg(rm, 0); | ||
139 | - ptr1 = vfp_reg_ptr(true, rn); | ||
140 | - tmp5 = tcg_const_i32(n); | ||
141 | - gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp5); | ||
142 | - tcg_temp_free_i32(tmp); | ||
143 | - if (insn & (1 << 6)) { | ||
144 | - tmp = neon_load_reg(rd, 1); | ||
145 | - } else { | ||
146 | - tmp = tcg_temp_new_i32(); | ||
147 | - tcg_gen_movi_i32(tmp, 0); | ||
148 | - } | ||
149 | - tmp3 = neon_load_reg(rm, 1); | ||
150 | - gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp5); | ||
151 | - tcg_temp_free_i32(tmp5); | ||
152 | - tcg_temp_free_ptr(ptr1); | ||
153 | - neon_store_reg(rd, 0, tmp2); | ||
154 | - neon_store_reg(rd, 1, tmp3); | ||
155 | - tcg_temp_free_i32(tmp); | ||
156 | + /* VTBL, VTBX: handled by decodetree */ | ||
157 | + return 1; | ||
158 | } else if ((insn & 0x380) == 0) { | ||
159 | /* VDUP */ | ||
160 | int element; | ||
161 | -- | 48 | -- |
162 | 2.20.1 | 49 | 2.25.1 |
163 | 50 | ||
164 | 51 | diff view generated by jsdifflib |
1 | Convert the Neon 2-reg-scalar long multiplies to decodetree. | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | These are the last instructions in the group. | ||
3 | 2 | ||
3 | Create arm_check_ss_active and arm_check_kernelpage. | ||
4 | |||
5 | Reverse the order of the tests. While it doesn't matter in practice, | ||
6 | because only user-only has a kernel page and user-only never sets | ||
7 | ss_active, ss_active has priority over execution exceptions and it | ||
8 | is best to keep them in the proper order. | ||
9 | |||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | 13 | --- |
7 | target/arm/neon-dp.decode | 18 ++++ | 14 | target/arm/translate.c | 10 +++++++--- |
8 | target/arm/translate-neon.inc.c | 163 ++++++++++++++++++++++++++++ | 15 | 1 file changed, 7 insertions(+), 3 deletions(-) |
9 | target/arm/translate.c | 182 ++------------------------------ | ||
10 | 3 files changed, 187 insertions(+), 176 deletions(-) | ||
11 | 16 | ||
12 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/neon-dp.decode | ||
15 | +++ b/target/arm/neon-dp.decode | ||
16 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
17 | |||
18 | @2scalar .... ... q:1 . . size:2 .... .... .... . . . . .... \ | ||
19 | &2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
20 | + # For the 'long' ops the Q bit is part of insn decode | ||
21 | + @2scalar_q0 .... ... . . . size:2 .... .... .... . . . . .... \ | ||
22 | + &2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0 | ||
23 | |||
24 | VMLA_2sc 1111 001 . 1 . .. .... .... 0000 . 1 . 0 .... @2scalar | ||
25 | VMLA_F_2sc 1111 001 . 1 . .. .... .... 0001 . 1 . 0 .... @2scalar | ||
26 | |||
27 | + VMLAL_S_2sc 1111 001 0 1 . .. .... .... 0010 . 1 . 0 .... @2scalar_q0 | ||
28 | + VMLAL_U_2sc 1111 001 1 1 . .. .... .... 0010 . 1 . 0 .... @2scalar_q0 | ||
29 | + | ||
30 | + VQDMLAL_2sc 1111 001 0 1 . .. .... .... 0011 . 1 . 0 .... @2scalar_q0 | ||
31 | + | ||
32 | VMLS_2sc 1111 001 . 1 . .. .... .... 0100 . 1 . 0 .... @2scalar | ||
33 | VMLS_F_2sc 1111 001 . 1 . .. .... .... 0101 . 1 . 0 .... @2scalar | ||
34 | |||
35 | + VMLSL_S_2sc 1111 001 0 1 . .. .... .... 0110 . 1 . 0 .... @2scalar_q0 | ||
36 | + VMLSL_U_2sc 1111 001 1 1 . .. .... .... 0110 . 1 . 0 .... @2scalar_q0 | ||
37 | + | ||
38 | + VQDMLSL_2sc 1111 001 0 1 . .. .... .... 0111 . 1 . 0 .... @2scalar_q0 | ||
39 | + | ||
40 | VMUL_2sc 1111 001 . 1 . .. .... .... 1000 . 1 . 0 .... @2scalar | ||
41 | VMUL_F_2sc 1111 001 . 1 . .. .... .... 1001 . 1 . 0 .... @2scalar | ||
42 | |||
43 | + VMULL_S_2sc 1111 001 0 1 . .. .... .... 1010 . 1 . 0 .... @2scalar_q0 | ||
44 | + VMULL_U_2sc 1111 001 1 1 . .. .... .... 1010 . 1 . 0 .... @2scalar_q0 | ||
45 | + | ||
46 | + VQDMULL_2sc 1111 001 0 1 . .. .... .... 1011 . 1 . 0 .... @2scalar_q0 | ||
47 | + | ||
48 | VQDMULH_2sc 1111 001 . 1 . .. .... .... 1100 . 1 . 0 .... @2scalar | ||
49 | VQRDMULH_2sc 1111 001 . 1 . .. .... .... 1101 . 1 . 0 .... @2scalar | ||
50 | |||
51 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
52 | index XXXXXXX..XXXXXXX 100644 | ||
53 | --- a/target/arm/translate-neon.inc.c | ||
54 | +++ b/target/arm/translate-neon.inc.c | ||
55 | @@ -XXX,XX +XXX,XX @@ static bool trans_VQRDMLSH_2sc(DisasContext *s, arg_2scalar *a) | ||
56 | }; | ||
57 | return do_vqrdmlah_2sc(s, a, opfn[a->size]); | ||
58 | } | ||
59 | + | ||
60 | +static bool do_2scalar_long(DisasContext *s, arg_2scalar *a, | ||
61 | + NeonGenTwoOpWidenFn *opfn, | ||
62 | + NeonGenTwo64OpFn *accfn) | ||
63 | +{ | ||
64 | + /* | ||
65 | + * Two registers and a scalar, long operations: perform an | ||
66 | + * operation on the input elements and the scalar which produces | ||
67 | + * a double-width result, and then possibly perform an accumulation | ||
68 | + * operation of that result into the destination. | ||
69 | + */ | ||
70 | + TCGv_i32 scalar, rn; | ||
71 | + TCGv_i64 rn0_64, rn1_64; | ||
72 | + | ||
73 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
74 | + return false; | ||
75 | + } | ||
76 | + | ||
77 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
78 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
79 | + ((a->vd | a->vn | a->vm) & 0x10)) { | ||
80 | + return false; | ||
81 | + } | ||
82 | + | ||
83 | + if (!opfn) { | ||
84 | + /* Bad size (including size == 3, which is a different insn group) */ | ||
85 | + return false; | ||
86 | + } | ||
87 | + | ||
88 | + if (a->vd & 1) { | ||
89 | + return false; | ||
90 | + } | ||
91 | + | ||
92 | + if (!vfp_access_check(s)) { | ||
93 | + return true; | ||
94 | + } | ||
95 | + | ||
96 | + scalar = neon_get_scalar(a->size, a->vm); | ||
97 | + | ||
98 | + /* Load all inputs before writing any outputs, in case of overlap */ | ||
99 | + rn = neon_load_reg(a->vn, 0); | ||
100 | + rn0_64 = tcg_temp_new_i64(); | ||
101 | + opfn(rn0_64, rn, scalar); | ||
102 | + tcg_temp_free_i32(rn); | ||
103 | + | ||
104 | + rn = neon_load_reg(a->vn, 1); | ||
105 | + rn1_64 = tcg_temp_new_i64(); | ||
106 | + opfn(rn1_64, rn, scalar); | ||
107 | + tcg_temp_free_i32(rn); | ||
108 | + tcg_temp_free_i32(scalar); | ||
109 | + | ||
110 | + if (accfn) { | ||
111 | + TCGv_i64 t64 = tcg_temp_new_i64(); | ||
112 | + neon_load_reg64(t64, a->vd); | ||
113 | + accfn(t64, t64, rn0_64); | ||
114 | + neon_store_reg64(t64, a->vd); | ||
115 | + neon_load_reg64(t64, a->vd + 1); | ||
116 | + accfn(t64, t64, rn1_64); | ||
117 | + neon_store_reg64(t64, a->vd + 1); | ||
118 | + tcg_temp_free_i64(t64); | ||
119 | + } else { | ||
120 | + neon_store_reg64(rn0_64, a->vd); | ||
121 | + neon_store_reg64(rn1_64, a->vd + 1); | ||
122 | + } | ||
123 | + tcg_temp_free_i64(rn0_64); | ||
124 | + tcg_temp_free_i64(rn1_64); | ||
125 | + return true; | ||
126 | +} | ||
127 | + | ||
128 | +static bool trans_VMULL_S_2sc(DisasContext *s, arg_2scalar *a) | ||
129 | +{ | ||
130 | + static NeonGenTwoOpWidenFn * const opfn[] = { | ||
131 | + NULL, | ||
132 | + gen_helper_neon_mull_s16, | ||
133 | + gen_mull_s32, | ||
134 | + NULL, | ||
135 | + }; | ||
136 | + | ||
137 | + return do_2scalar_long(s, a, opfn[a->size], NULL); | ||
138 | +} | ||
139 | + | ||
140 | +static bool trans_VMULL_U_2sc(DisasContext *s, arg_2scalar *a) | ||
141 | +{ | ||
142 | + static NeonGenTwoOpWidenFn * const opfn[] = { | ||
143 | + NULL, | ||
144 | + gen_helper_neon_mull_u16, | ||
145 | + gen_mull_u32, | ||
146 | + NULL, | ||
147 | + }; | ||
148 | + | ||
149 | + return do_2scalar_long(s, a, opfn[a->size], NULL); | ||
150 | +} | ||
151 | + | ||
152 | +#define DO_VMLAL_2SC(INSN, MULL, ACC) \ | ||
153 | + static bool trans_##INSN##_2sc(DisasContext *s, arg_2scalar *a) \ | ||
154 | + { \ | ||
155 | + static NeonGenTwoOpWidenFn * const opfn[] = { \ | ||
156 | + NULL, \ | ||
157 | + gen_helper_neon_##MULL##16, \ | ||
158 | + gen_##MULL##32, \ | ||
159 | + NULL, \ | ||
160 | + }; \ | ||
161 | + static NeonGenTwo64OpFn * const accfn[] = { \ | ||
162 | + NULL, \ | ||
163 | + gen_helper_neon_##ACC##l_u32, \ | ||
164 | + tcg_gen_##ACC##_i64, \ | ||
165 | + NULL, \ | ||
166 | + }; \ | ||
167 | + return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]); \ | ||
168 | + } | ||
169 | + | ||
170 | +DO_VMLAL_2SC(VMLAL_S, mull_s, add) | ||
171 | +DO_VMLAL_2SC(VMLAL_U, mull_u, add) | ||
172 | +DO_VMLAL_2SC(VMLSL_S, mull_s, sub) | ||
173 | +DO_VMLAL_2SC(VMLSL_U, mull_u, sub) | ||
174 | + | ||
175 | +static bool trans_VQDMULL_2sc(DisasContext *s, arg_2scalar *a) | ||
176 | +{ | ||
177 | + static NeonGenTwoOpWidenFn * const opfn[] = { | ||
178 | + NULL, | ||
179 | + gen_VQDMULL_16, | ||
180 | + gen_VQDMULL_32, | ||
181 | + NULL, | ||
182 | + }; | ||
183 | + | ||
184 | + return do_2scalar_long(s, a, opfn[a->size], NULL); | ||
185 | +} | ||
186 | + | ||
187 | +static bool trans_VQDMLAL_2sc(DisasContext *s, arg_2scalar *a) | ||
188 | +{ | ||
189 | + static NeonGenTwoOpWidenFn * const opfn[] = { | ||
190 | + NULL, | ||
191 | + gen_VQDMULL_16, | ||
192 | + gen_VQDMULL_32, | ||
193 | + NULL, | ||
194 | + }; | ||
195 | + static NeonGenTwo64OpFn * const accfn[] = { | ||
196 | + NULL, | ||
197 | + gen_VQDMLAL_acc_16, | ||
198 | + gen_VQDMLAL_acc_32, | ||
199 | + NULL, | ||
200 | + }; | ||
201 | + | ||
202 | + return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]); | ||
203 | +} | ||
204 | + | ||
205 | +static bool trans_VQDMLSL_2sc(DisasContext *s, arg_2scalar *a) | ||
206 | +{ | ||
207 | + static NeonGenTwoOpWidenFn * const opfn[] = { | ||
208 | + NULL, | ||
209 | + gen_VQDMULL_16, | ||
210 | + gen_VQDMULL_32, | ||
211 | + NULL, | ||
212 | + }; | ||
213 | + static NeonGenTwo64OpFn * const accfn[] = { | ||
214 | + NULL, | ||
215 | + gen_VQDMLSL_acc_16, | ||
216 | + gen_VQDMLSL_acc_32, | ||
217 | + NULL, | ||
218 | + }; | ||
219 | + | ||
220 | + return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]); | ||
221 | +} | ||
222 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 17 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
223 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
224 | --- a/target/arm/translate.c | 19 | --- a/target/arm/translate.c |
225 | +++ b/target/arm/translate.c | 20 | +++ b/target/arm/translate.c |
226 | @@ -XXX,XX +XXX,XX @@ static void gen_revsh(TCGv_i32 dest, TCGv_i32 var) | 21 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) |
227 | tcg_gen_ext16s_i32(dest, var); | 22 | dc->insn_start = tcg_last_op(); |
228 | } | 23 | } |
229 | 24 | ||
230 | -/* 32x32->64 multiply. Marks inputs as dead. */ | 25 | -static bool arm_pre_translate_insn(DisasContext *dc) |
231 | -static TCGv_i64 gen_mulu_i64_i32(TCGv_i32 a, TCGv_i32 b) | 26 | +static bool arm_check_kernelpage(DisasContext *dc) |
232 | -{ | ||
233 | - TCGv_i32 lo = tcg_temp_new_i32(); | ||
234 | - TCGv_i32 hi = tcg_temp_new_i32(); | ||
235 | - TCGv_i64 ret; | ||
236 | - | ||
237 | - tcg_gen_mulu2_i32(lo, hi, a, b); | ||
238 | - tcg_temp_free_i32(a); | ||
239 | - tcg_temp_free_i32(b); | ||
240 | - | ||
241 | - ret = tcg_temp_new_i64(); | ||
242 | - tcg_gen_concat_i32_i64(ret, lo, hi); | ||
243 | - tcg_temp_free_i32(lo); | ||
244 | - tcg_temp_free_i32(hi); | ||
245 | - | ||
246 | - return ret; | ||
247 | -} | ||
248 | - | ||
249 | -static TCGv_i64 gen_muls_i64_i32(TCGv_i32 a, TCGv_i32 b) | ||
250 | -{ | ||
251 | - TCGv_i32 lo = tcg_temp_new_i32(); | ||
252 | - TCGv_i32 hi = tcg_temp_new_i32(); | ||
253 | - TCGv_i64 ret; | ||
254 | - | ||
255 | - tcg_gen_muls2_i32(lo, hi, a, b); | ||
256 | - tcg_temp_free_i32(a); | ||
257 | - tcg_temp_free_i32(b); | ||
258 | - | ||
259 | - ret = tcg_temp_new_i64(); | ||
260 | - tcg_gen_concat_i32_i64(ret, lo, hi); | ||
261 | - tcg_temp_free_i32(lo); | ||
262 | - tcg_temp_free_i32(hi); | ||
263 | - | ||
264 | - return ret; | ||
265 | -} | ||
266 | - | ||
267 | /* Swap low and high halfwords. */ | ||
268 | static void gen_swap_half(TCGv_i32 var) | ||
269 | { | 27 | { |
270 | @@ -XXX,XX +XXX,XX @@ static inline void gen_neon_addl(int size) | 28 | #ifdef CONFIG_USER_ONLY |
29 | /* Intercept jump to the magic kernel page. */ | ||
30 | @@ -XXX,XX +XXX,XX @@ static bool arm_pre_translate_insn(DisasContext *dc) | ||
31 | return true; | ||
271 | } | 32 | } |
272 | } | 33 | #endif |
273 | 34 | + return false; | |
274 | -static inline void gen_neon_negl(TCGv_i64 var, int size) | 35 | +} |
275 | -{ | 36 | |
276 | - switch (size) { | 37 | +static bool arm_check_ss_active(DisasContext *dc) |
277 | - case 0: gen_helper_neon_negl_u16(var, var); break; | 38 | +{ |
278 | - case 1: gen_helper_neon_negl_u32(var, var); break; | 39 | if (dc->ss_active && !dc->pstate_ss) { |
279 | - case 2: | 40 | /* Singlestep state is Active-pending. |
280 | - tcg_gen_neg_i64(var, var); | 41 | * If we're in this state at the start of a TB then either |
281 | - break; | 42 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
282 | - default: abort(); | 43 | uint32_t pc = dc->base.pc_next; |
283 | - } | 44 | unsigned int insn; |
284 | -} | 45 | |
285 | - | 46 | - if (arm_pre_translate_insn(dc)) { |
286 | -static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size) | 47 | + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { |
287 | -{ | 48 | dc->base.pc_next = pc + 4; |
288 | - switch (size) { | 49 | return; |
289 | - case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break; | 50 | } |
290 | - case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break; | 51 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
291 | - default: abort(); | 52 | uint32_t insn; |
292 | - } | 53 | bool is_16bit; |
293 | -} | 54 | |
294 | - | 55 | - if (arm_pre_translate_insn(dc)) { |
295 | -static inline void gen_neon_mull(TCGv_i64 dest, TCGv_i32 a, TCGv_i32 b, | 56 | + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { |
296 | - int size, int u) | 57 | dc->base.pc_next = pc + 2; |
297 | -{ | 58 | return; |
298 | - TCGv_i64 tmp; | 59 | } |
299 | - | ||
300 | - switch ((size << 1) | u) { | ||
301 | - case 0: gen_helper_neon_mull_s8(dest, a, b); break; | ||
302 | - case 1: gen_helper_neon_mull_u8(dest, a, b); break; | ||
303 | - case 2: gen_helper_neon_mull_s16(dest, a, b); break; | ||
304 | - case 3: gen_helper_neon_mull_u16(dest, a, b); break; | ||
305 | - case 4: | ||
306 | - tmp = gen_muls_i64_i32(a, b); | ||
307 | - tcg_gen_mov_i64(dest, tmp); | ||
308 | - tcg_temp_free_i64(tmp); | ||
309 | - break; | ||
310 | - case 5: | ||
311 | - tmp = gen_mulu_i64_i32(a, b); | ||
312 | - tcg_gen_mov_i64(dest, tmp); | ||
313 | - tcg_temp_free_i64(tmp); | ||
314 | - break; | ||
315 | - default: abort(); | ||
316 | - } | ||
317 | - | ||
318 | - /* gen_helper_neon_mull_[su]{8|16} do not free their parameters. | ||
319 | - Don't forget to clean them now. */ | ||
320 | - if (size < 2) { | ||
321 | - tcg_temp_free_i32(a); | ||
322 | - tcg_temp_free_i32(b); | ||
323 | - } | ||
324 | -} | ||
325 | - | ||
326 | static void gen_neon_narrow_op(int op, int u, int size, | ||
327 | TCGv_i32 dest, TCGv_i64 src) | ||
328 | { | ||
329 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
330 | int u; | ||
331 | int vec_size; | ||
332 | uint32_t imm; | ||
333 | - TCGv_i32 tmp, tmp2, tmp3, tmp4, tmp5; | ||
334 | + TCGv_i32 tmp, tmp2, tmp3, tmp5; | ||
335 | TCGv_ptr ptr1; | ||
336 | TCGv_i64 tmp64; | ||
337 | |||
338 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
339 | return 1; | ||
340 | } else { /* (insn & 0x00800010 == 0x00800000) */ | ||
341 | if (size != 3) { | ||
342 | - op = (insn >> 8) & 0xf; | ||
343 | - if ((insn & (1 << 6)) == 0) { | ||
344 | - /* Three registers of different lengths: handled by decodetree */ | ||
345 | - return 1; | ||
346 | - } else { | ||
347 | - /* Two registers and a scalar. NB that for ops of this form | ||
348 | - * the ARM ARM labels bit 24 as Q, but it is in our variable | ||
349 | - * 'u', not 'q'. | ||
350 | - */ | ||
351 | - if (size == 0) { | ||
352 | - return 1; | ||
353 | - } | ||
354 | - switch (op) { | ||
355 | - case 0: /* Integer VMLA scalar */ | ||
356 | - case 4: /* Integer VMLS scalar */ | ||
357 | - case 8: /* Integer VMUL scalar */ | ||
358 | - case 1: /* Float VMLA scalar */ | ||
359 | - case 5: /* Floating point VMLS scalar */ | ||
360 | - case 9: /* Floating point VMUL scalar */ | ||
361 | - case 12: /* VQDMULH scalar */ | ||
362 | - case 13: /* VQRDMULH scalar */ | ||
363 | - case 14: /* VQRDMLAH scalar */ | ||
364 | - case 15: /* VQRDMLSH scalar */ | ||
365 | - return 1; /* handled by decodetree */ | ||
366 | - | ||
367 | - case 3: /* VQDMLAL scalar */ | ||
368 | - case 7: /* VQDMLSL scalar */ | ||
369 | - case 11: /* VQDMULL scalar */ | ||
370 | - if (u == 1) { | ||
371 | - return 1; | ||
372 | - } | ||
373 | - /* fall through */ | ||
374 | - case 2: /* VMLAL sclar */ | ||
375 | - case 6: /* VMLSL scalar */ | ||
376 | - case 10: /* VMULL scalar */ | ||
377 | - if (rd & 1) { | ||
378 | - return 1; | ||
379 | - } | ||
380 | - tmp2 = neon_get_scalar(size, rm); | ||
381 | - /* We need a copy of tmp2 because gen_neon_mull | ||
382 | - * deletes it during pass 0. */ | ||
383 | - tmp4 = tcg_temp_new_i32(); | ||
384 | - tcg_gen_mov_i32(tmp4, tmp2); | ||
385 | - tmp3 = neon_load_reg(rn, 1); | ||
386 | - | ||
387 | - for (pass = 0; pass < 2; pass++) { | ||
388 | - if (pass == 0) { | ||
389 | - tmp = neon_load_reg(rn, 0); | ||
390 | - } else { | ||
391 | - tmp = tmp3; | ||
392 | - tmp2 = tmp4; | ||
393 | - } | ||
394 | - gen_neon_mull(cpu_V0, tmp, tmp2, size, u); | ||
395 | - if (op != 11) { | ||
396 | - neon_load_reg64(cpu_V1, rd + pass); | ||
397 | - } | ||
398 | - switch (op) { | ||
399 | - case 6: | ||
400 | - gen_neon_negl(cpu_V0, size); | ||
401 | - /* Fall through */ | ||
402 | - case 2: | ||
403 | - gen_neon_addl(size); | ||
404 | - break; | ||
405 | - case 3: case 7: | ||
406 | - gen_neon_addl_saturate(cpu_V0, cpu_V0, size); | ||
407 | - if (op == 7) { | ||
408 | - gen_neon_negl(cpu_V0, size); | ||
409 | - } | ||
410 | - gen_neon_addl_saturate(cpu_V0, cpu_V1, size); | ||
411 | - break; | ||
412 | - case 10: | ||
413 | - /* no-op */ | ||
414 | - break; | ||
415 | - case 11: | ||
416 | - gen_neon_addl_saturate(cpu_V0, cpu_V0, size); | ||
417 | - break; | ||
418 | - default: | ||
419 | - abort(); | ||
420 | - } | ||
421 | - neon_store_reg64(cpu_V0, rd + pass); | ||
422 | - } | ||
423 | - break; | ||
424 | - default: | ||
425 | - g_assert_not_reached(); | ||
426 | - } | ||
427 | - } | ||
428 | + /* | ||
429 | + * Three registers of different lengths, or two registers and | ||
430 | + * a scalar: handled by decodetree | ||
431 | + */ | ||
432 | + return 1; | ||
433 | } else { /* size == 3 */ | ||
434 | if (!u) { | ||
435 | /* Extract. */ | ||
436 | -- | 60 | -- |
437 | 2.20.1 | 61 | 2.25.1 |
438 | 62 | ||
439 | 63 | diff view generated by jsdifflib |
1 | From: Erik Smit <erik.lucas.smit@gmail.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The hardware supports configurable descriptor sizes, configured in the DBLAC | 3 | The size of the code covered by a TranslationBlock cannot be 0; |
4 | register. | 4 | this is checked via assert in tb_gen_code. |
5 | 5 | ||
6 | Most drivers use the default 4 word descriptor, which is currently hardcoded, | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | but Aspeed SDK configures 8 words to store extra data. | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | |||
9 | Signed-off-by: Erik Smit <erik.lucas.smit@gmail.com> | ||
10 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
11 | [PMM: removed unnecessary parens] | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 9 | --- |
14 | hw/net/ftgmac100.c | 26 ++++++++++++++++++++++++-- | 10 | target/arm/translate-a64.c | 1 + |
15 | 1 file changed, 24 insertions(+), 2 deletions(-) | 11 | 1 file changed, 1 insertion(+) |
16 | 12 | ||
17 | diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c | 13 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
18 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/net/ftgmac100.c | 15 | --- a/target/arm/translate-a64.c |
20 | +++ b/hw/net/ftgmac100.c | 16 | +++ b/target/arm/translate-a64.c |
21 | @@ -XXX,XX +XXX,XX @@ | 17 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
22 | #define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) >> 8) & 0xf) | 18 | assert(s->base.num_insns == 1); |
23 | #define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) | 19 | gen_swstep_exception(s, 0, 0); |
24 | 20 | s->base.is_jmp = DISAS_NORETURN; | |
25 | +/* | 21 | + s->base.pc_next = pc + 4; |
26 | + * DMA burst length and arbitration control register | 22 | return; |
27 | + */ | ||
28 | +#define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) >> 8) & 0x3) | ||
29 | +#define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) >> 10) & 0x3) | ||
30 | +#define FTGMAC100_DBLAC_RXDES_SIZE(x) ((((x) >> 12) & 0xf) * 8) | ||
31 | +#define FTGMAC100_DBLAC_TXDES_SIZE(x) ((((x) >> 16) & 0xf) * 8) | ||
32 | +#define FTGMAC100_DBLAC_IFG_CNT(x) (((x) >> 20) & 0x7) | ||
33 | +#define FTGMAC100_DBLAC_IFG_INC (1 << 23) | ||
34 | + | ||
35 | /* | ||
36 | * PHY control register | ||
37 | */ | ||
38 | @@ -XXX,XX +XXX,XX @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring, | ||
39 | if (bd.des0 & s->txdes0_edotr) { | ||
40 | addr = tx_ring; | ||
41 | } else { | ||
42 | - addr += sizeof(FTGMAC100Desc); | ||
43 | + addr += FTGMAC100_DBLAC_TXDES_SIZE(s->dblac); | ||
44 | } | ||
45 | } | 23 | } |
46 | 24 | ||
47 | @@ -XXX,XX +XXX,XX @@ static void ftgmac100_write(void *opaque, hwaddr addr, | ||
48 | s->phydata = value & 0xffff; | ||
49 | break; | ||
50 | case FTGMAC100_DBLAC: /* DMA Burst Length and Arbitration Control */ | ||
51 | + if (FTGMAC100_DBLAC_TXDES_SIZE(s->dblac) < sizeof(FTGMAC100Desc)) { | ||
52 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
53 | + "%s: transmit descriptor too small : %d bytes\n", | ||
54 | + __func__, FTGMAC100_DBLAC_TXDES_SIZE(s->dblac)); | ||
55 | + break; | ||
56 | + } | ||
57 | + if (FTGMAC100_DBLAC_RXDES_SIZE(s->dblac) < sizeof(FTGMAC100Desc)) { | ||
58 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
59 | + "%s: receive descriptor too small : %d bytes\n", | ||
60 | + __func__, FTGMAC100_DBLAC_RXDES_SIZE(s->dblac)); | ||
61 | + break; | ||
62 | + } | ||
63 | s->dblac = value; | ||
64 | break; | ||
65 | case FTGMAC100_REVR: /* Feature Register */ | ||
66 | @@ -XXX,XX +XXX,XX @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf, | ||
67 | if (bd.des0 & s->rxdes0_edorr) { | ||
68 | addr = s->rx_ring; | ||
69 | } else { | ||
70 | - addr += sizeof(FTGMAC100Desc); | ||
71 | + addr += FTGMAC100_DBLAC_RXDES_SIZE(s->dblac); | ||
72 | } | ||
73 | } | ||
74 | s->rx_descriptor = addr; | ||
75 | -- | 25 | -- |
76 | 2.20.1 | 26 | 2.25.1 |
77 | 27 | ||
78 | 28 | diff view generated by jsdifflib |
1 | Convert the VQRDMLAH and VQRDMLSH insns in the 2-reg-scalar | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | group to decodetree. | ||
3 | 2 | ||
3 | We will reuse this section of arm_deliver_fault for | ||
4 | raising pc alignment faults. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | 9 | --- |
7 | target/arm/neon-dp.decode | 3 ++ | 10 | target/arm/tlb_helper.c | 45 +++++++++++++++++++++++++---------------- |
8 | target/arm/translate-neon.inc.c | 74 +++++++++++++++++++++++++++++++++ | 11 | 1 file changed, 28 insertions(+), 17 deletions(-) |
9 | target/arm/translate.c | 38 +---------------- | ||
10 | 3 files changed, 79 insertions(+), 36 deletions(-) | ||
11 | 12 | ||
12 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | 13 | diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c |
13 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/neon-dp.decode | 15 | --- a/target/arm/tlb_helper.c |
15 | +++ b/target/arm/neon-dp.decode | 16 | +++ b/target/arm/tlb_helper.c |
16 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | 17 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, |
17 | 18 | return syn; | |
18 | VQDMULH_2sc 1111 001 . 1 . .. .... .... 1100 . 1 . 0 .... @2scalar | ||
19 | VQRDMULH_2sc 1111 001 . 1 . .. .... .... 1101 . 1 . 0 .... @2scalar | ||
20 | + | ||
21 | + VQRDMLAH_2sc 1111 001 . 1 . .. .... .... 1110 . 1 . 0 .... @2scalar | ||
22 | + VQRDMLSH_2sc 1111 001 . 1 . .. .... .... 1111 . 1 . 0 .... @2scalar | ||
23 | ] | ||
24 | } | 19 | } |
25 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | 20 | |
26 | index XXXXXXX..XXXXXXX 100644 | 21 | -static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, |
27 | --- a/target/arm/translate-neon.inc.c | 22 | - MMUAccessType access_type, |
28 | +++ b/target/arm/translate-neon.inc.c | 23 | - int mmu_idx, ARMMMUFaultInfo *fi) |
29 | @@ -XXX,XX +XXX,XX @@ static bool trans_VQRDMULH_2sc(DisasContext *s, arg_2scalar *a) | 24 | +static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi, |
30 | 25 | + int target_el, int mmu_idx, uint32_t *ret_fsc) | |
31 | return do_2scalar(s, a, opfn[a->size], NULL); | 26 | { |
32 | } | 27 | - CPUARMState *env = &cpu->env; |
33 | + | 28 | - int target_el; |
34 | +static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a, | 29 | - bool same_el; |
35 | + NeonGenThreeOpEnvFn *opfn) | 30 | - uint32_t syn, exc, fsr, fsc; |
36 | +{ | 31 | ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); |
37 | + /* | 32 | - |
38 | + * VQRDMLAH/VQRDMLSH: this is like do_2scalar, but the opfn | 33 | - target_el = exception_target_el(env); |
39 | + * performs a kind of fused op-then-accumulate using a helper | 34 | - if (fi->stage2) { |
40 | + * function that takes all of rd, rn and the scalar at once. | 35 | - target_el = 2; |
41 | + */ | 36 | - env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; |
42 | + TCGv_i32 scalar; | 37 | - if (arm_is_secure_below_el3(env) && fi->s1ns) { |
43 | + int pass; | 38 | - env->cp15.hpfar_el2 |= HPFAR_NS; |
44 | + | 39 | - } |
45 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | 40 | - } |
46 | + return false; | 41 | - same_el = (arm_current_el(env) == target_el); |
47 | + } | 42 | + uint32_t fsr, fsc; |
48 | + | 43 | |
49 | + if (!dc_isar_feature(aa32_rdm, s)) { | 44 | if (target_el == 2 || arm_el_is_aa64(env, target_el) || |
50 | + return false; | 45 | arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { |
51 | + } | 46 | @@ -XXX,XX +XXX,XX @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, |
52 | + | 47 | fsc = 0x3f; |
53 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | 48 | } |
54 | + if (!dc_isar_feature(aa32_simd_r32, s) && | 49 | |
55 | + ((a->vd | a->vn | a->vm) & 0x10)) { | 50 | + *ret_fsc = fsc; |
56 | + return false; | 51 | + return fsr; |
57 | + } | ||
58 | + | ||
59 | + if (!opfn) { | ||
60 | + /* Bad size (including size == 3, which is a different insn group) */ | ||
61 | + return false; | ||
62 | + } | ||
63 | + | ||
64 | + if (a->q && ((a->vd | a->vn) & 1)) { | ||
65 | + return false; | ||
66 | + } | ||
67 | + | ||
68 | + if (!vfp_access_check(s)) { | ||
69 | + return true; | ||
70 | + } | ||
71 | + | ||
72 | + scalar = neon_get_scalar(a->size, a->vm); | ||
73 | + | ||
74 | + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
75 | + TCGv_i32 rn = neon_load_reg(a->vn, pass); | ||
76 | + TCGv_i32 rd = neon_load_reg(a->vd, pass); | ||
77 | + opfn(rd, cpu_env, rn, scalar, rd); | ||
78 | + tcg_temp_free_i32(rn); | ||
79 | + neon_store_reg(a->vd, pass, rd); | ||
80 | + } | ||
81 | + tcg_temp_free_i32(scalar); | ||
82 | + | ||
83 | + return true; | ||
84 | +} | 52 | +} |
85 | + | 53 | + |
86 | +static bool trans_VQRDMLAH_2sc(DisasContext *s, arg_2scalar *a) | 54 | +static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, |
55 | + MMUAccessType access_type, | ||
56 | + int mmu_idx, ARMMMUFaultInfo *fi) | ||
87 | +{ | 57 | +{ |
88 | + static NeonGenThreeOpEnvFn *opfn[] = { | 58 | + CPUARMState *env = &cpu->env; |
89 | + NULL, | 59 | + int target_el; |
90 | + gen_helper_neon_qrdmlah_s16, | 60 | + bool same_el; |
91 | + gen_helper_neon_qrdmlah_s32, | 61 | + uint32_t syn, exc, fsr, fsc; |
92 | + NULL, | ||
93 | + }; | ||
94 | + return do_vqrdmlah_2sc(s, a, opfn[a->size]); | ||
95 | +} | ||
96 | + | 62 | + |
97 | +static bool trans_VQRDMLSH_2sc(DisasContext *s, arg_2scalar *a) | 63 | + target_el = exception_target_el(env); |
98 | +{ | 64 | + if (fi->stage2) { |
99 | + static NeonGenThreeOpEnvFn *opfn[] = { | 65 | + target_el = 2; |
100 | + NULL, | 66 | + env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; |
101 | + gen_helper_neon_qrdmlsh_s16, | 67 | + if (arm_is_secure_below_el3(env) && fi->s1ns) { |
102 | + gen_helper_neon_qrdmlsh_s32, | 68 | + env->cp15.hpfar_el2 |= HPFAR_NS; |
103 | + NULL, | 69 | + } |
104 | + }; | 70 | + } |
105 | + return do_vqrdmlah_2sc(s, a, opfn[a->size]); | 71 | + same_el = (arm_current_el(env) == target_el); |
106 | +} | 72 | + |
107 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 73 | + fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); |
108 | index XXXXXXX..XXXXXXX 100644 | 74 | + |
109 | --- a/target/arm/translate.c | 75 | if (access_type == MMU_INST_FETCH) { |
110 | +++ b/target/arm/translate.c | 76 | syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); |
111 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 77 | exc = EXCP_PREFETCH_ABORT; |
112 | case 9: /* Floating point VMUL scalar */ | ||
113 | case 12: /* VQDMULH scalar */ | ||
114 | case 13: /* VQRDMULH scalar */ | ||
115 | + case 14: /* VQRDMLAH scalar */ | ||
116 | + case 15: /* VQRDMLSH scalar */ | ||
117 | return 1; /* handled by decodetree */ | ||
118 | |||
119 | case 3: /* VQDMLAL scalar */ | ||
120 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
121 | neon_store_reg64(cpu_V0, rd + pass); | ||
122 | } | ||
123 | break; | ||
124 | - case 14: /* VQRDMLAH scalar */ | ||
125 | - case 15: /* VQRDMLSH scalar */ | ||
126 | - { | ||
127 | - NeonGenThreeOpEnvFn *fn; | ||
128 | - | ||
129 | - if (!dc_isar_feature(aa32_rdm, s)) { | ||
130 | - return 1; | ||
131 | - } | ||
132 | - if (u && ((rd | rn) & 1)) { | ||
133 | - return 1; | ||
134 | - } | ||
135 | - if (op == 14) { | ||
136 | - if (size == 1) { | ||
137 | - fn = gen_helper_neon_qrdmlah_s16; | ||
138 | - } else { | ||
139 | - fn = gen_helper_neon_qrdmlah_s32; | ||
140 | - } | ||
141 | - } else { | ||
142 | - if (size == 1) { | ||
143 | - fn = gen_helper_neon_qrdmlsh_s16; | ||
144 | - } else { | ||
145 | - fn = gen_helper_neon_qrdmlsh_s32; | ||
146 | - } | ||
147 | - } | ||
148 | - | ||
149 | - tmp2 = neon_get_scalar(size, rm); | ||
150 | - for (pass = 0; pass < (u ? 4 : 2); pass++) { | ||
151 | - tmp = neon_load_reg(rn, pass); | ||
152 | - tmp3 = neon_load_reg(rd, pass); | ||
153 | - fn(tmp, cpu_env, tmp, tmp2, tmp3); | ||
154 | - tcg_temp_free_i32(tmp3); | ||
155 | - neon_store_reg(rd, pass, tmp); | ||
156 | - } | ||
157 | - tcg_temp_free_i32(tmp2); | ||
158 | - } | ||
159 | - break; | ||
160 | default: | ||
161 | g_assert_not_reached(); | ||
162 | } | ||
163 | -- | 78 | -- |
164 | 2.20.1 | 79 | 2.25.1 |
165 | 80 | ||
166 | 81 | diff view generated by jsdifflib |
1 | Convert the Neon 3-reg-diff insns VQDMULL, VQDMLAL and VQDMLSL: | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | these are all saturating doubling long multiplies with a possible | 2 | |
3 | accumulate step. | 3 | For A64, any input to an indirect branch can cause this. |
4 | 4 | ||
5 | These are the last insns in the group which use the pass-over-each | 5 | For A32, many indirect branch paths force the branch to be aligned, |
6 | elements loop, so we can delete that code. | 6 | but BXWritePC does not. This includes the BX instruction but also |
7 | 7 | other interworking changes to PC. Prior to v8, this case is UNDEFINED. | |
8 | With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an | ||
9 | exception or force align the PC. | ||
10 | |||
11 | We choose to raise an exception because we have the infrastructure, | ||
12 | it makes the generated code for gen_bx simpler, and it has the | ||
13 | possibility of catching more guest bugs. | ||
14 | |||
15 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | --- | 18 | --- |
11 | target/arm/neon-dp.decode | 6 +++ | 19 | target/arm/helper.h | 1 + |
12 | target/arm/translate-neon.inc.c | 82 +++++++++++++++++++++++++++++++++ | 20 | target/arm/syndrome.h | 5 ++++ |
13 | target/arm/translate.c | 59 ++---------------------- | 21 | linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++++++--------------- |
14 | 3 files changed, 92 insertions(+), 55 deletions(-) | 22 | target/arm/tlb_helper.c | 18 ++++++++++++++ |
15 | 23 | target/arm/translate-a64.c | 15 ++++++++++++ | |
16 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | 24 | target/arm/translate.c | 22 ++++++++++++++++- |
17 | index XXXXXXX..XXXXXXX 100644 | 25 | 6 files changed, 87 insertions(+), 20 deletions(-) |
18 | --- a/target/arm/neon-dp.decode | 26 | |
19 | +++ b/target/arm/neon-dp.decode | 27 | diff --git a/target/arm/helper.h b/target/arm/helper.h |
20 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | 28 | index XXXXXXX..XXXXXXX 100644 |
21 | VMLAL_S_3d 1111 001 0 1 . .. .... .... 1000 . 0 . 0 .... @3diff | 29 | --- a/target/arm/helper.h |
22 | VMLAL_U_3d 1111 001 1 1 . .. .... .... 1000 . 0 . 0 .... @3diff | 30 | +++ b/target/arm/helper.h |
23 | 31 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, | |
24 | + VQDMLAL_3d 1111 001 0 1 . .. .... .... 1001 . 0 . 0 .... @3diff | 32 | DEF_HELPER_2(exception_internal, void, env, i32) |
25 | + | 33 | DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32) |
26 | VMLSL_S_3d 1111 001 0 1 . .. .... .... 1010 . 0 . 0 .... @3diff | 34 | DEF_HELPER_2(exception_bkpt_insn, void, env, i32) |
27 | VMLSL_U_3d 1111 001 1 1 . .. .... .... 1010 . 0 . 0 .... @3diff | 35 | +DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) |
28 | 36 | DEF_HELPER_1(setend, void, env) | |
29 | + VQDMLSL_3d 1111 001 0 1 . .. .... .... 1011 . 0 . 0 .... @3diff | 37 | DEF_HELPER_2(wfi, void, env, i32) |
30 | + | 38 | DEF_HELPER_1(wfe, void, env) |
31 | VMULL_S_3d 1111 001 0 1 . .. .... .... 1100 . 0 . 0 .... @3diff | 39 | diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h |
32 | VMULL_U_3d 1111 001 1 1 . .. .... .... 1100 . 0 . 0 .... @3diff | 40 | index XXXXXXX..XXXXXXX 100644 |
33 | + | 41 | --- a/target/arm/syndrome.h |
34 | + VQDMULL_3d 1111 001 0 1 . .. .... .... 1101 . 0 . 0 .... @3diff | 42 | +++ b/target/arm/syndrome.h |
35 | ] | 43 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_illegalstate(void) |
44 | return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; | ||
36 | } | 45 | } |
37 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | 46 | |
38 | index XXXXXXX..XXXXXXX 100644 | 47 | +static inline uint32_t syn_pcalignment(void) |
39 | --- a/target/arm/translate-neon.inc.c | ||
40 | +++ b/target/arm/translate-neon.inc.c | ||
41 | @@ -XXX,XX +XXX,XX @@ DO_VMLAL(VMLAL_S,mull_s,add) | ||
42 | DO_VMLAL(VMLAL_U,mull_u,add) | ||
43 | DO_VMLAL(VMLSL_S,mull_s,sub) | ||
44 | DO_VMLAL(VMLSL_U,mull_u,sub) | ||
45 | + | ||
46 | +static void gen_VQDMULL_16(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) | ||
47 | +{ | 48 | +{ |
48 | + gen_helper_neon_mull_s16(rd, rn, rm); | 49 | + return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; |
49 | + gen_helper_neon_addl_saturate_s32(rd, cpu_env, rd, rd); | ||
50 | +} | 50 | +} |
51 | + | 51 | + |
52 | +static void gen_VQDMULL_32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) | 52 | #endif /* TARGET_ARM_SYNDROME_H */ |
53 | diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/linux-user/aarch64/cpu_loop.c | ||
56 | +++ b/linux-user/aarch64/cpu_loop.c | ||
57 | @@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env) | ||
58 | break; | ||
59 | case EXCP_PREFETCH_ABORT: | ||
60 | case EXCP_DATA_ABORT: | ||
61 | - /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */ | ||
62 | ec = syn_get_ec(env->exception.syndrome); | ||
63 | - assert(ec == EC_DATAABORT || ec == EC_INSNABORT); | ||
64 | - | ||
65 | - /* Both EC have the same format for FSC, or close enough. */ | ||
66 | - fsc = extract32(env->exception.syndrome, 0, 6); | ||
67 | - switch (fsc) { | ||
68 | - case 0x04 ... 0x07: /* Translation fault, level {0-3} */ | ||
69 | - si_signo = TARGET_SIGSEGV; | ||
70 | - si_code = TARGET_SEGV_MAPERR; | ||
71 | + switch (ec) { | ||
72 | + case EC_DATAABORT: | ||
73 | + case EC_INSNABORT: | ||
74 | + /* Both EC have the same format for FSC, or close enough. */ | ||
75 | + fsc = extract32(env->exception.syndrome, 0, 6); | ||
76 | + switch (fsc) { | ||
77 | + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ | ||
78 | + si_signo = TARGET_SIGSEGV; | ||
79 | + si_code = TARGET_SEGV_MAPERR; | ||
80 | + break; | ||
81 | + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ | ||
82 | + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ | ||
83 | + si_signo = TARGET_SIGSEGV; | ||
84 | + si_code = TARGET_SEGV_ACCERR; | ||
85 | + break; | ||
86 | + case 0x11: /* Synchronous Tag Check Fault */ | ||
87 | + si_signo = TARGET_SIGSEGV; | ||
88 | + si_code = TARGET_SEGV_MTESERR; | ||
89 | + break; | ||
90 | + case 0x21: /* Alignment fault */ | ||
91 | + si_signo = TARGET_SIGBUS; | ||
92 | + si_code = TARGET_BUS_ADRALN; | ||
93 | + break; | ||
94 | + default: | ||
95 | + g_assert_not_reached(); | ||
96 | + } | ||
97 | break; | ||
98 | - case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ | ||
99 | - case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ | ||
100 | - si_signo = TARGET_SIGSEGV; | ||
101 | - si_code = TARGET_SEGV_ACCERR; | ||
102 | - break; | ||
103 | - case 0x11: /* Synchronous Tag Check Fault */ | ||
104 | - si_signo = TARGET_SIGSEGV; | ||
105 | - si_code = TARGET_SEGV_MTESERR; | ||
106 | - break; | ||
107 | - case 0x21: /* Alignment fault */ | ||
108 | + case EC_PCALIGNMENT: | ||
109 | si_signo = TARGET_SIGBUS; | ||
110 | si_code = TARGET_BUS_ADRALN; | ||
111 | break; | ||
112 | diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c | ||
113 | index XXXXXXX..XXXXXXX 100644 | ||
114 | --- a/target/arm/tlb_helper.c | ||
115 | +++ b/target/arm/tlb_helper.c | ||
116 | @@ -XXX,XX +XXX,XX @@ | ||
117 | #include "cpu.h" | ||
118 | #include "internals.h" | ||
119 | #include "exec/exec-all.h" | ||
120 | +#include "exec/helper-proto.h" | ||
121 | |||
122 | static inline uint32_t merge_syn_data_abort(uint32_t template_syn, | ||
123 | unsigned int target_el, | ||
124 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, | ||
125 | arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); | ||
126 | } | ||
127 | |||
128 | +void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) | ||
53 | +{ | 129 | +{ |
54 | + gen_mull_s32(rd, rn, rm); | 130 | + ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; |
55 | + gen_helper_neon_addl_saturate_s64(rd, cpu_env, rd, rd); | 131 | + int target_el = exception_target_el(env); |
132 | + int mmu_idx = cpu_mmu_index(env, true); | ||
133 | + uint32_t fsc; | ||
134 | + | ||
135 | + env->exception.vaddress = pc; | ||
136 | + | ||
137 | + /* | ||
138 | + * Note that the fsc is not applicable to this exception, | ||
139 | + * since any syndrome is pcalignment not insn_abort. | ||
140 | + */ | ||
141 | + env->exception.fsr = compute_fsr_fsc(env, &fi, target_el, mmu_idx, &fsc); | ||
142 | + raise_exception(env, EXCP_PREFETCH_ABORT, syn_pcalignment(), target_el); | ||
56 | +} | 143 | +} |
57 | + | 144 | + |
58 | +static bool trans_VQDMULL_3d(DisasContext *s, arg_3diff *a) | 145 | #if !defined(CONFIG_USER_ONLY) |
59 | +{ | 146 | |
60 | + static NeonGenTwoOpWidenFn * const opfn[] = { | 147 | /* |
61 | + NULL, | 148 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
62 | + gen_VQDMULL_16, | 149 | index XXXXXXX..XXXXXXX 100644 |
63 | + gen_VQDMULL_32, | 150 | --- a/target/arm/translate-a64.c |
64 | + NULL, | 151 | +++ b/target/arm/translate-a64.c |
65 | + }; | 152 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
66 | + | 153 | uint64_t pc = s->base.pc_next; |
67 | + return do_long_3d(s, a, opfn[a->size], NULL); | 154 | uint32_t insn; |
68 | +} | 155 | |
69 | + | 156 | + /* Singlestep exceptions have the highest priority. */ |
70 | +static void gen_VQDMLAL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) | 157 | if (s->ss_active && !s->pstate_ss) { |
71 | +{ | 158 | /* Singlestep state is Active-pending. |
72 | + gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm); | 159 | * If we're in this state at the start of a TB then either |
73 | +} | 160 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
74 | + | 161 | return; |
75 | +static void gen_VQDMLAL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) | 162 | } |
76 | +{ | 163 | |
77 | + gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm); | 164 | + if (pc & 3) { |
78 | +} | 165 | + /* |
79 | + | 166 | + * PC alignment fault. This has priority over the instruction abort |
80 | +static bool trans_VQDMLAL_3d(DisasContext *s, arg_3diff *a) | 167 | + * that we would receive from a translation fault via arm_ldl_code. |
81 | +{ | 168 | + * This should only be possible after an indirect branch, at the |
82 | + static NeonGenTwoOpWidenFn * const opfn[] = { | 169 | + * start of the TB. |
83 | + NULL, | 170 | + */ |
84 | + gen_VQDMULL_16, | 171 | + assert(s->base.num_insns == 1); |
85 | + gen_VQDMULL_32, | 172 | + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); |
86 | + NULL, | 173 | + s->base.is_jmp = DISAS_NORETURN; |
87 | + }; | 174 | + s->base.pc_next = QEMU_ALIGN_UP(pc, 4); |
88 | + static NeonGenTwo64OpFn * const accfn[] = { | 175 | + return; |
89 | + NULL, | 176 | + } |
90 | + gen_VQDMLAL_acc_16, | 177 | + |
91 | + gen_VQDMLAL_acc_32, | 178 | s->pc_curr = pc; |
92 | + NULL, | 179 | insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b); |
93 | + }; | 180 | s->insn = insn; |
94 | + | ||
95 | + return do_long_3d(s, a, opfn[a->size], accfn[a->size]); | ||
96 | +} | ||
97 | + | ||
98 | +static void gen_VQDMLSL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) | ||
99 | +{ | ||
100 | + gen_helper_neon_negl_u32(rm, rm); | ||
101 | + gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm); | ||
102 | +} | ||
103 | + | ||
104 | +static void gen_VQDMLSL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) | ||
105 | +{ | ||
106 | + tcg_gen_neg_i64(rm, rm); | ||
107 | + gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm); | ||
108 | +} | ||
109 | + | ||
110 | +static bool trans_VQDMLSL_3d(DisasContext *s, arg_3diff *a) | ||
111 | +{ | ||
112 | + static NeonGenTwoOpWidenFn * const opfn[] = { | ||
113 | + NULL, | ||
114 | + gen_VQDMULL_16, | ||
115 | + gen_VQDMULL_32, | ||
116 | + NULL, | ||
117 | + }; | ||
118 | + static NeonGenTwo64OpFn * const accfn[] = { | ||
119 | + NULL, | ||
120 | + gen_VQDMLSL_acc_16, | ||
121 | + gen_VQDMLSL_acc_32, | ||
122 | + NULL, | ||
123 | + }; | ||
124 | + | ||
125 | + return do_long_3d(s, a, opfn[a->size], accfn[a->size]); | ||
126 | +} | ||
127 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 181 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
128 | index XXXXXXX..XXXXXXX 100644 | 182 | index XXXXXXX..XXXXXXX 100644 |
129 | --- a/target/arm/translate.c | 183 | --- a/target/arm/translate.c |
130 | +++ b/target/arm/translate.c | 184 | +++ b/target/arm/translate.c |
131 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 185 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
132 | {0, 0, 0, 7}, /* VSUBHN: handled by decodetree */ | 186 | uint32_t pc = dc->base.pc_next; |
133 | {0, 0, 0, 7}, /* VABDL */ | 187 | unsigned int insn; |
134 | {0, 0, 0, 7}, /* VMLAL */ | 188 | |
135 | - {0, 0, 0, 9}, /* VQDMLAL */ | 189 | - if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { |
136 | + {0, 0, 0, 7}, /* VQDMLAL */ | 190 | + /* Singlestep exceptions have the highest priority. */ |
137 | {0, 0, 0, 7}, /* VMLSL */ | 191 | + if (arm_check_ss_active(dc)) { |
138 | - {0, 0, 0, 9}, /* VQDMLSL */ | 192 | + dc->base.pc_next = pc + 4; |
139 | + {0, 0, 0, 7}, /* VQDMLSL */ | 193 | + return; |
140 | {0, 0, 0, 7}, /* Integer VMULL */ | 194 | + } |
141 | - {0, 0, 0, 9}, /* VQDMULL */ | 195 | + |
142 | + {0, 0, 0, 7}, /* VQDMULL */ | 196 | + if (pc & 3) { |
143 | {0, 0, 0, 0xa}, /* Polynomial VMULL */ | 197 | + /* |
144 | {0, 0, 0, 7}, /* Reserved: always UNDEF */ | 198 | + * PC alignment fault. This has priority over the instruction abort |
145 | }; | 199 | + * that we would receive from a translation fault via arm_ldl_code |
146 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 200 | + * (or the execution of the kernelpage entrypoint). This should only |
147 | } | 201 | + * be possible after an indirect branch, at the start of the TB. |
148 | return 0; | 202 | + */ |
149 | } | 203 | + assert(dc->base.num_insns == 1); |
150 | - | 204 | + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); |
151 | - /* Avoid overlapping operands. Wide source operands are | 205 | + dc->base.is_jmp = DISAS_NORETURN; |
152 | - always aligned so will never overlap with wide | 206 | + dc->base.pc_next = QEMU_ALIGN_UP(pc, 4); |
153 | - destinations in problematic ways. */ | 207 | + return; |
154 | - if (rd == rm) { | 208 | + } |
155 | - tmp = neon_load_reg(rm, 1); | 209 | + |
156 | - neon_store_scratch(2, tmp); | 210 | + if (arm_check_kernelpage(dc)) { |
157 | - } else if (rd == rn) { | 211 | dc->base.pc_next = pc + 4; |
158 | - tmp = neon_load_reg(rn, 1); | 212 | return; |
159 | - neon_store_scratch(2, tmp); | 213 | } |
160 | - } | ||
161 | - tmp3 = NULL; | ||
162 | - for (pass = 0; pass < 2; pass++) { | ||
163 | - if (pass == 1 && rd == rn) { | ||
164 | - tmp = neon_load_scratch(2); | ||
165 | - } else { | ||
166 | - tmp = neon_load_reg(rn, pass); | ||
167 | - } | ||
168 | - if (pass == 1 && rd == rm) { | ||
169 | - tmp2 = neon_load_scratch(2); | ||
170 | - } else { | ||
171 | - tmp2 = neon_load_reg(rm, pass); | ||
172 | - } | ||
173 | - switch (op) { | ||
174 | - case 9: case 11: case 13: | ||
175 | - /* VQDMLAL, VQDMLSL, VQDMULL */ | ||
176 | - gen_neon_mull(cpu_V0, tmp, tmp2, size, u); | ||
177 | - break; | ||
178 | - default: /* 15 is RESERVED: caught earlier */ | ||
179 | - abort(); | ||
180 | - } | ||
181 | - if (op == 13) { | ||
182 | - /* VQDMULL */ | ||
183 | - gen_neon_addl_saturate(cpu_V0, cpu_V0, size); | ||
184 | - neon_store_reg64(cpu_V0, rd + pass); | ||
185 | - } else { | ||
186 | - /* Accumulate. */ | ||
187 | - neon_load_reg64(cpu_V1, rd + pass); | ||
188 | - switch (op) { | ||
189 | - case 9: case 11: /* VQDMLAL, VQDMLSL */ | ||
190 | - gen_neon_addl_saturate(cpu_V0, cpu_V0, size); | ||
191 | - if (op == 11) { | ||
192 | - gen_neon_negl(cpu_V0, size); | ||
193 | - } | ||
194 | - gen_neon_addl_saturate(cpu_V0, cpu_V1, size); | ||
195 | - break; | ||
196 | - default: | ||
197 | - abort(); | ||
198 | - } | ||
199 | - neon_store_reg64(cpu_V0, rd + pass); | ||
200 | - } | ||
201 | - } | ||
202 | + abort(); /* all others handled by decodetree */ | ||
203 | } else { | ||
204 | /* Two registers and a scalar. NB that for ops of this form | ||
205 | * the ARM ARM labels bit 24 as Q, but it is in our variable | ||
206 | -- | 214 | -- |
207 | 2.20.1 | 215 | 2.25.1 |
208 | 216 | ||
209 | 217 | diff view generated by jsdifflib |
1 | Convert the Neon VEXT insn to decodetree. Rather than keeping the | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | old implementation which used fixed temporaries cpu_V0 and cpu_V1 | ||
3 | and did the extraction with by-hand shift and logic ops, we use | ||
4 | the TCG extract2 insn. | ||
5 | 2 | ||
6 | We don't need to special case 0 or 8 immediates any more as the | 3 | Misaligned thumb PC is architecturally impossible. |
7 | optimizer is smart enough to throw away the dead code. | 4 | Assert is better than proceeding, in case we've missed |
5 | something somewhere. | ||
8 | 6 | ||
7 | Expand a comment about aligning the pc in gdbstub. | ||
8 | Fail an incoming migrate if a thumb pc is misaligned. | ||
9 | |||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | --- | 13 | --- |
12 | target/arm/neon-dp.decode | 8 +++- | 14 | target/arm/gdbstub.c | 9 +++++++-- |
13 | target/arm/translate-neon.inc.c | 76 +++++++++++++++++++++++++++++++++ | 15 | target/arm/machine.c | 10 ++++++++++ |
14 | target/arm/translate.c | 58 +------------------------ | 16 | target/arm/translate.c | 3 +++ |
15 | 3 files changed, 85 insertions(+), 57 deletions(-) | 17 | 3 files changed, 20 insertions(+), 2 deletions(-) |
16 | 18 | ||
17 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | 19 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c |
18 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/neon-dp.decode | 21 | --- a/target/arm/gdbstub.c |
20 | +++ b/target/arm/neon-dp.decode | 22 | +++ b/target/arm/gdbstub.c |
21 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | 23 | @@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) |
22 | # return false for size==3. | 24 | |
23 | ###################################################################### | 25 | tmp = ldl_p(mem_buf); |
24 | { | 26 | |
25 | - # 0b11 subgroup will go here | 27 | - /* Mask out low bit of PC to workaround gdb bugs. This will probably |
26 | + [ | 28 | - cause problems if we ever implement the Jazelle DBX extensions. */ |
27 | + ################################################################## | 29 | + /* |
28 | + # Miscellaneous size=0b11 insns | 30 | + * Mask out low bits of PC to workaround gdb bugs. |
29 | + ################################################################## | 31 | + * This avoids an assert in thumb_tr_translate_insn, because it is |
30 | + VEXT 1111 001 0 1 . 11 .... .... imm:4 . q:1 . 0 .... \ | 32 | + * architecturally impossible to misalign the pc. |
31 | + vm=%vm_dp vn=%vn_dp vd=%vd_dp | 33 | + * This will probably cause problems if we ever implement the |
32 | + ] | 34 | + * Jazelle DBX extensions. |
33 | 35 | + */ | |
34 | # Subgroup for size != 0b11 | 36 | if (n == 15) { |
35 | [ | 37 | tmp &= ~1; |
36 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | 38 | } |
39 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | 40 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/target/arm/translate-neon.inc.c | 41 | --- a/target/arm/machine.c |
39 | +++ b/target/arm/translate-neon.inc.c | 42 | +++ b/target/arm/machine.c |
40 | @@ -XXX,XX +XXX,XX @@ static bool trans_VQDMLSL_2sc(DisasContext *s, arg_2scalar *a) | 43 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) |
41 | 44 | return -1; | |
42 | return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]); | 45 | } |
43 | } | 46 | } |
44 | + | 47 | + |
45 | +static bool trans_VEXT(DisasContext *s, arg_VEXT *a) | 48 | + /* |
46 | +{ | 49 | + * Misaligned thumb pc is architecturally impossible. |
47 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | 50 | + * We have an assert in thumb_tr_translate_insn to verify this. |
48 | + return false; | 51 | + * Fail an incoming migrate to avoid this assert. |
52 | + */ | ||
53 | + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { | ||
54 | + return -1; | ||
49 | + } | 55 | + } |
50 | + | 56 | + |
51 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | 57 | if (!kvm_enabled()) { |
52 | + if (!dc_isar_feature(aa32_simd_r32, s) && | 58 | pmu_op_finish(&cpu->env); |
53 | + ((a->vd | a->vn | a->vm) & 0x10)) { | 59 | } |
54 | + return false; | ||
55 | + } | ||
56 | + | ||
57 | + if ((a->vn | a->vm | a->vd) & a->q) { | ||
58 | + return false; | ||
59 | + } | ||
60 | + | ||
61 | + if (a->imm > 7 && !a->q) { | ||
62 | + return false; | ||
63 | + } | ||
64 | + | ||
65 | + if (!vfp_access_check(s)) { | ||
66 | + return true; | ||
67 | + } | ||
68 | + | ||
69 | + if (!a->q) { | ||
70 | + /* Extract 64 bits from <Vm:Vn> */ | ||
71 | + TCGv_i64 left, right, dest; | ||
72 | + | ||
73 | + left = tcg_temp_new_i64(); | ||
74 | + right = tcg_temp_new_i64(); | ||
75 | + dest = tcg_temp_new_i64(); | ||
76 | + | ||
77 | + neon_load_reg64(right, a->vn); | ||
78 | + neon_load_reg64(left, a->vm); | ||
79 | + tcg_gen_extract2_i64(dest, right, left, a->imm * 8); | ||
80 | + neon_store_reg64(dest, a->vd); | ||
81 | + | ||
82 | + tcg_temp_free_i64(left); | ||
83 | + tcg_temp_free_i64(right); | ||
84 | + tcg_temp_free_i64(dest); | ||
85 | + } else { | ||
86 | + /* Extract 128 bits from <Vm+1:Vm:Vn+1:Vn> */ | ||
87 | + TCGv_i64 left, middle, right, destleft, destright; | ||
88 | + | ||
89 | + left = tcg_temp_new_i64(); | ||
90 | + middle = tcg_temp_new_i64(); | ||
91 | + right = tcg_temp_new_i64(); | ||
92 | + destleft = tcg_temp_new_i64(); | ||
93 | + destright = tcg_temp_new_i64(); | ||
94 | + | ||
95 | + if (a->imm < 8) { | ||
96 | + neon_load_reg64(right, a->vn); | ||
97 | + neon_load_reg64(middle, a->vn + 1); | ||
98 | + tcg_gen_extract2_i64(destright, right, middle, a->imm * 8); | ||
99 | + neon_load_reg64(left, a->vm); | ||
100 | + tcg_gen_extract2_i64(destleft, middle, left, a->imm * 8); | ||
101 | + } else { | ||
102 | + neon_load_reg64(right, a->vn + 1); | ||
103 | + neon_load_reg64(middle, a->vm); | ||
104 | + tcg_gen_extract2_i64(destright, right, middle, (a->imm - 8) * 8); | ||
105 | + neon_load_reg64(left, a->vm + 1); | ||
106 | + tcg_gen_extract2_i64(destleft, middle, left, (a->imm - 8) * 8); | ||
107 | + } | ||
108 | + | ||
109 | + neon_store_reg64(destright, a->vd); | ||
110 | + neon_store_reg64(destleft, a->vd + 1); | ||
111 | + | ||
112 | + tcg_temp_free_i64(destright); | ||
113 | + tcg_temp_free_i64(destleft); | ||
114 | + tcg_temp_free_i64(right); | ||
115 | + tcg_temp_free_i64(middle); | ||
116 | + tcg_temp_free_i64(left); | ||
117 | + } | ||
118 | + return true; | ||
119 | +} | ||
120 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 60 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
121 | index XXXXXXX..XXXXXXX 100644 | 61 | index XXXXXXX..XXXXXXX 100644 |
122 | --- a/target/arm/translate.c | 62 | --- a/target/arm/translate.c |
123 | +++ b/target/arm/translate.c | 63 | +++ b/target/arm/translate.c |
124 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 64 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
125 | int pass; | 65 | uint32_t insn; |
126 | int u; | 66 | bool is_16bit; |
127 | int vec_size; | 67 | |
128 | - uint32_t imm; | 68 | + /* Misaligned thumb PC is architecturally impossible. */ |
129 | TCGv_i32 tmp, tmp2, tmp3, tmp5; | 69 | + assert((dc->base.pc_next & 1) == 0); |
130 | TCGv_ptr ptr1; | 70 | + |
131 | - TCGv_i64 tmp64; | 71 | if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { |
132 | 72 | dc->base.pc_next = pc + 2; | |
133 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | 73 | return; |
134 | return 1; | ||
135 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
136 | return 1; | ||
137 | } else { /* size == 3 */ | ||
138 | if (!u) { | ||
139 | - /* Extract. */ | ||
140 | - imm = (insn >> 8) & 0xf; | ||
141 | - | ||
142 | - if (imm > 7 && !q) | ||
143 | - return 1; | ||
144 | - | ||
145 | - if (q && ((rd | rn | rm) & 1)) { | ||
146 | - return 1; | ||
147 | - } | ||
148 | - | ||
149 | - if (imm == 0) { | ||
150 | - neon_load_reg64(cpu_V0, rn); | ||
151 | - if (q) { | ||
152 | - neon_load_reg64(cpu_V1, rn + 1); | ||
153 | - } | ||
154 | - } else if (imm == 8) { | ||
155 | - neon_load_reg64(cpu_V0, rn + 1); | ||
156 | - if (q) { | ||
157 | - neon_load_reg64(cpu_V1, rm); | ||
158 | - } | ||
159 | - } else if (q) { | ||
160 | - tmp64 = tcg_temp_new_i64(); | ||
161 | - if (imm < 8) { | ||
162 | - neon_load_reg64(cpu_V0, rn); | ||
163 | - neon_load_reg64(tmp64, rn + 1); | ||
164 | - } else { | ||
165 | - neon_load_reg64(cpu_V0, rn + 1); | ||
166 | - neon_load_reg64(tmp64, rm); | ||
167 | - } | ||
168 | - tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8); | ||
169 | - tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8)); | ||
170 | - tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); | ||
171 | - if (imm < 8) { | ||
172 | - neon_load_reg64(cpu_V1, rm); | ||
173 | - } else { | ||
174 | - neon_load_reg64(cpu_V1, rm + 1); | ||
175 | - imm -= 8; | ||
176 | - } | ||
177 | - tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8)); | ||
178 | - tcg_gen_shri_i64(tmp64, tmp64, imm * 8); | ||
179 | - tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64); | ||
180 | - tcg_temp_free_i64(tmp64); | ||
181 | - } else { | ||
182 | - /* BUGFIX */ | ||
183 | - neon_load_reg64(cpu_V0, rn); | ||
184 | - tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8); | ||
185 | - neon_load_reg64(cpu_V1, rm); | ||
186 | - tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8)); | ||
187 | - tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); | ||
188 | - } | ||
189 | - neon_store_reg64(cpu_V0, rd); | ||
190 | - if (q) { | ||
191 | - neon_store_reg64(cpu_V1, rd + 1); | ||
192 | - } | ||
193 | + /* Extract: handled by decodetree */ | ||
194 | + return 1; | ||
195 | } else if ((insn & (1 << 11)) == 0) { | ||
196 | /* Two register misc. */ | ||
197 | op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf); | ||
198 | -- | 74 | -- |
199 | 2.20.1 | 75 | 2.25.1 |
200 | 76 | ||
201 | 77 | diff view generated by jsdifflib |
1 | Convert the VMLA, VMLS and VMUL insns in the Neon "2 registers and a | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | scalar" group to decodetree. These are 32x32->32 operations where | ||
3 | one of the inputs is the scalar, followed by a possible accumulate | ||
4 | operation of the 32-bit result. | ||
5 | 2 | ||
6 | The refactoring removes some of the oddities of the old decoder: | 3 | Both single-step and pc alignment faults have priority over |
7 | * operands to the operation and accumulation were often | 4 | breakpoint exceptions. |
8 | reversed (taking advantage of the fact that most of these ops | ||
9 | are commutative); the new code follows the pseudocode order | ||
10 | * the Q bit in the insn was in a local variable 'u'; in the | ||
11 | new code it is decoded into a->q | ||
12 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | --- | 9 | --- |
16 | target/arm/neon-dp.decode | 15 ++++ | 10 | target/arm/debug_helper.c | 23 +++++++++++++++++++++++ |
17 | target/arm/translate-neon.inc.c | 133 ++++++++++++++++++++++++++++++++ | 11 | 1 file changed, 23 insertions(+) |
18 | target/arm/translate.c | 77 ++---------------- | ||
19 | 3 files changed, 154 insertions(+), 71 deletions(-) | ||
20 | 12 | ||
21 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | 13 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c |
22 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/target/arm/neon-dp.decode | 15 | --- a/target/arm/debug_helper.c |
24 | +++ b/target/arm/neon-dp.decode | 16 | +++ b/target/arm/debug_helper.c |
25 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | 17 | @@ -XXX,XX +XXX,XX @@ bool arm_debug_check_breakpoint(CPUState *cs) |
26 | VQDMULL_3d 1111 001 0 1 . .. .... .... 1101 . 0 . 0 .... @3diff | 18 | { |
27 | 19 | ARMCPU *cpu = ARM_CPU(cs); | |
28 | VMULL_P_3d 1111 001 0 1 . .. .... .... 1110 . 0 . 0 .... @3diff | 20 | CPUARMState *env = &cpu->env; |
29 | + | 21 | + target_ulong pc; |
30 | + ################################################################## | 22 | int n; |
31 | + # 2-regs-plus-scalar grouping: | 23 | |
32 | + # 1111 001 Q 1 D sz!=11 Vn:4 Vd:4 opc:4 N 1 M 0 Vm:4 | 24 | /* |
33 | + ################################################################## | 25 | @@ -XXX,XX +XXX,XX @@ bool arm_debug_check_breakpoint(CPUState *cs) |
34 | + &2scalar vm vn vd size q | 26 | return false; |
35 | + | 27 | } |
36 | + @2scalar .... ... q:1 . . size:2 .... .... .... . . . . .... \ | 28 | |
37 | + &2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
38 | + | ||
39 | + VMLA_2sc 1111 001 . 1 . .. .... .... 0000 . 1 . 0 .... @2scalar | ||
40 | + | ||
41 | + VMLS_2sc 1111 001 . 1 . .. .... .... 0100 . 1 . 0 .... @2scalar | ||
42 | + | ||
43 | + VMUL_2sc 1111 001 . 1 . .. .... .... 1000 . 1 . 0 .... @2scalar | ||
44 | ] | ||
45 | } | ||
46 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/translate-neon.inc.c | ||
49 | +++ b/target/arm/translate-neon.inc.c | ||
50 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a) | ||
51 | 16, 16, 0, fn_gvec); | ||
52 | return true; | ||
53 | } | ||
54 | + | ||
55 | +static void gen_neon_dup_low16(TCGv_i32 var) | ||
56 | +{ | ||
57 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
58 | + tcg_gen_ext16u_i32(var, var); | ||
59 | + tcg_gen_shli_i32(tmp, var, 16); | ||
60 | + tcg_gen_or_i32(var, var, tmp); | ||
61 | + tcg_temp_free_i32(tmp); | ||
62 | +} | ||
63 | + | ||
64 | +static void gen_neon_dup_high16(TCGv_i32 var) | ||
65 | +{ | ||
66 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
67 | + tcg_gen_andi_i32(var, var, 0xffff0000); | ||
68 | + tcg_gen_shri_i32(tmp, var, 16); | ||
69 | + tcg_gen_or_i32(var, var, tmp); | ||
70 | + tcg_temp_free_i32(tmp); | ||
71 | +} | ||
72 | + | ||
73 | +static inline TCGv_i32 neon_get_scalar(int size, int reg) | ||
74 | +{ | ||
75 | + TCGv_i32 tmp; | ||
76 | + if (size == 1) { | ||
77 | + tmp = neon_load_reg(reg & 7, reg >> 4); | ||
78 | + if (reg & 8) { | ||
79 | + gen_neon_dup_high16(tmp); | ||
80 | + } else { | ||
81 | + gen_neon_dup_low16(tmp); | ||
82 | + } | ||
83 | + } else { | ||
84 | + tmp = neon_load_reg(reg & 15, reg >> 4); | ||
85 | + } | ||
86 | + return tmp; | ||
87 | +} | ||
88 | + | ||
89 | +static bool do_2scalar(DisasContext *s, arg_2scalar *a, | ||
90 | + NeonGenTwoOpFn *opfn, NeonGenTwoOpFn *accfn) | ||
91 | +{ | ||
92 | + /* | 29 | + /* |
93 | + * Two registers and a scalar: perform an operation between | 30 | + * Single-step exceptions have priority over breakpoint exceptions. |
94 | + * the input elements and the scalar, and then possibly | 31 | + * If single-step state is active-pending, suppress the bp. |
95 | + * perform an accumulation operation of that result into the | ||
96 | + * destination. | ||
97 | + */ | 32 | + */ |
98 | + TCGv_i32 scalar; | 33 | + if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) { |
99 | + int pass; | ||
100 | + | ||
101 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
102 | + return false; | 34 | + return false; |
103 | + } | 35 | + } |
104 | + | 36 | + |
105 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | 37 | + /* |
106 | + if (!dc_isar_feature(aa32_simd_r32, s) && | 38 | + * PC alignment faults have priority over breakpoint exceptions. |
107 | + ((a->vd | a->vn | a->vm) & 0x10)) { | 39 | + */ |
40 | + pc = is_a64(env) ? env->pc : env->regs[15]; | ||
41 | + if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) { | ||
108 | + return false; | 42 | + return false; |
109 | + } | 43 | + } |
110 | + | 44 | + |
111 | + if (!opfn) { | 45 | + /* |
112 | + /* Bad size (including size == 3, which is a different insn group) */ | 46 | + * Instruction aborts have priority over breakpoint exceptions. |
113 | + return false; | 47 | + * TODO: We would need to look up the page for PC and verify that |
114 | + } | 48 | + * it is present and executable. |
49 | + */ | ||
115 | + | 50 | + |
116 | + if (a->q && ((a->vd | a->vn) & 1)) { | 51 | for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { |
117 | + return false; | 52 | if (bp_wp_matches(cpu, n, false)) { |
118 | + } | 53 | return true; |
119 | + | ||
120 | + if (!vfp_access_check(s)) { | ||
121 | + return true; | ||
122 | + } | ||
123 | + | ||
124 | + scalar = neon_get_scalar(a->size, a->vm); | ||
125 | + | ||
126 | + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
127 | + TCGv_i32 tmp = neon_load_reg(a->vn, pass); | ||
128 | + opfn(tmp, tmp, scalar); | ||
129 | + if (accfn) { | ||
130 | + TCGv_i32 rd = neon_load_reg(a->vd, pass); | ||
131 | + accfn(tmp, rd, tmp); | ||
132 | + tcg_temp_free_i32(rd); | ||
133 | + } | ||
134 | + neon_store_reg(a->vd, pass, tmp); | ||
135 | + } | ||
136 | + tcg_temp_free_i32(scalar); | ||
137 | + return true; | ||
138 | +} | ||
139 | + | ||
140 | +static bool trans_VMUL_2sc(DisasContext *s, arg_2scalar *a) | ||
141 | +{ | ||
142 | + static NeonGenTwoOpFn * const opfn[] = { | ||
143 | + NULL, | ||
144 | + gen_helper_neon_mul_u16, | ||
145 | + tcg_gen_mul_i32, | ||
146 | + NULL, | ||
147 | + }; | ||
148 | + | ||
149 | + return do_2scalar(s, a, opfn[a->size], NULL); | ||
150 | +} | ||
151 | + | ||
152 | +static bool trans_VMLA_2sc(DisasContext *s, arg_2scalar *a) | ||
153 | +{ | ||
154 | + static NeonGenTwoOpFn * const opfn[] = { | ||
155 | + NULL, | ||
156 | + gen_helper_neon_mul_u16, | ||
157 | + tcg_gen_mul_i32, | ||
158 | + NULL, | ||
159 | + }; | ||
160 | + static NeonGenTwoOpFn * const accfn[] = { | ||
161 | + NULL, | ||
162 | + gen_helper_neon_add_u16, | ||
163 | + tcg_gen_add_i32, | ||
164 | + NULL, | ||
165 | + }; | ||
166 | + | ||
167 | + return do_2scalar(s, a, opfn[a->size], accfn[a->size]); | ||
168 | +} | ||
169 | + | ||
170 | +static bool trans_VMLS_2sc(DisasContext *s, arg_2scalar *a) | ||
171 | +{ | ||
172 | + static NeonGenTwoOpFn * const opfn[] = { | ||
173 | + NULL, | ||
174 | + gen_helper_neon_mul_u16, | ||
175 | + tcg_gen_mul_i32, | ||
176 | + NULL, | ||
177 | + }; | ||
178 | + static NeonGenTwoOpFn * const accfn[] = { | ||
179 | + NULL, | ||
180 | + gen_helper_neon_sub_u16, | ||
181 | + tcg_gen_sub_i32, | ||
182 | + NULL, | ||
183 | + }; | ||
184 | + | ||
185 | + return do_2scalar(s, a, opfn[a->size], accfn[a->size]); | ||
186 | +} | ||
187 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
188 | index XXXXXXX..XXXXXXX 100644 | ||
189 | --- a/target/arm/translate.c | ||
190 | +++ b/target/arm/translate.c | ||
191 | @@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn) | ||
192 | #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7) | ||
193 | #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5) | ||
194 | |||
195 | -static void gen_neon_dup_low16(TCGv_i32 var) | ||
196 | -{ | ||
197 | - TCGv_i32 tmp = tcg_temp_new_i32(); | ||
198 | - tcg_gen_ext16u_i32(var, var); | ||
199 | - tcg_gen_shli_i32(tmp, var, 16); | ||
200 | - tcg_gen_or_i32(var, var, tmp); | ||
201 | - tcg_temp_free_i32(tmp); | ||
202 | -} | ||
203 | - | ||
204 | -static void gen_neon_dup_high16(TCGv_i32 var) | ||
205 | -{ | ||
206 | - TCGv_i32 tmp = tcg_temp_new_i32(); | ||
207 | - tcg_gen_andi_i32(var, var, 0xffff0000); | ||
208 | - tcg_gen_shri_i32(tmp, var, 16); | ||
209 | - tcg_gen_or_i32(var, var, tmp); | ||
210 | - tcg_temp_free_i32(tmp); | ||
211 | -} | ||
212 | - | ||
213 | static inline bool use_goto_tb(DisasContext *s, target_ulong dest) | ||
214 | { | ||
215 | #ifndef CONFIG_USER_ONLY | ||
216 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc) | ||
217 | |||
218 | #define CPU_V001 cpu_V0, cpu_V0, cpu_V1 | ||
219 | |||
220 | -static inline void gen_neon_add(int size, TCGv_i32 t0, TCGv_i32 t1) | ||
221 | -{ | ||
222 | - switch (size) { | ||
223 | - case 0: gen_helper_neon_add_u8(t0, t0, t1); break; | ||
224 | - case 1: gen_helper_neon_add_u16(t0, t0, t1); break; | ||
225 | - case 2: tcg_gen_add_i32(t0, t0, t1); break; | ||
226 | - default: abort(); | ||
227 | - } | ||
228 | -} | ||
229 | - | ||
230 | -static inline void gen_neon_rsb(int size, TCGv_i32 t0, TCGv_i32 t1) | ||
231 | -{ | ||
232 | - switch (size) { | ||
233 | - case 0: gen_helper_neon_sub_u8(t0, t1, t0); break; | ||
234 | - case 1: gen_helper_neon_sub_u16(t0, t1, t0); break; | ||
235 | - case 2: tcg_gen_sub_i32(t0, t1, t0); break; | ||
236 | - default: return; | ||
237 | - } | ||
238 | -} | ||
239 | - | ||
240 | static TCGv_i32 neon_load_scratch(int scratch) | ||
241 | { | ||
242 | TCGv_i32 tmp = tcg_temp_new_i32(); | ||
243 | @@ -XXX,XX +XXX,XX @@ static void neon_store_scratch(int scratch, TCGv_i32 var) | ||
244 | tcg_temp_free_i32(var); | ||
245 | } | ||
246 | |||
247 | -static inline TCGv_i32 neon_get_scalar(int size, int reg) | ||
248 | -{ | ||
249 | - TCGv_i32 tmp; | ||
250 | - if (size == 1) { | ||
251 | - tmp = neon_load_reg(reg & 7, reg >> 4); | ||
252 | - if (reg & 8) { | ||
253 | - gen_neon_dup_high16(tmp); | ||
254 | - } else { | ||
255 | - gen_neon_dup_low16(tmp); | ||
256 | - } | ||
257 | - } else { | ||
258 | - tmp = neon_load_reg(reg & 15, reg >> 4); | ||
259 | - } | ||
260 | - return tmp; | ||
261 | -} | ||
262 | - | ||
263 | static int gen_neon_unzip(int rd, int rm, int size, int q) | ||
264 | { | ||
265 | TCGv_ptr pd, pm; | ||
266 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
267 | return 1; | ||
268 | } | ||
269 | switch (op) { | ||
270 | + case 0: /* Integer VMLA scalar */ | ||
271 | + case 4: /* Integer VMLS scalar */ | ||
272 | + case 8: /* Integer VMUL scalar */ | ||
273 | + return 1; /* handled by decodetree */ | ||
274 | + | ||
275 | case 1: /* Float VMLA scalar */ | ||
276 | case 5: /* Floating point VMLS scalar */ | ||
277 | case 9: /* Floating point VMUL scalar */ | ||
278 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
279 | return 1; | ||
280 | } | ||
281 | /* fall through */ | ||
282 | - case 0: /* Integer VMLA scalar */ | ||
283 | - case 4: /* Integer VMLS scalar */ | ||
284 | - case 8: /* Integer VMUL scalar */ | ||
285 | case 12: /* VQDMULH scalar */ | ||
286 | case 13: /* VQRDMULH scalar */ | ||
287 | if (u && ((rd | rn) & 1)) { | ||
288 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
289 | } else { | ||
290 | gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2); | ||
291 | } | ||
292 | - } else if (op & 1) { | ||
293 | + } else { | ||
294 | TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
295 | gen_helper_vfp_muls(tmp, tmp, tmp2, fpstatus); | ||
296 | tcg_temp_free_ptr(fpstatus); | ||
297 | - } else { | ||
298 | - switch (size) { | ||
299 | - case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break; | ||
300 | - case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break; | ||
301 | - case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break; | ||
302 | - default: abort(); | ||
303 | - } | ||
304 | } | ||
305 | tcg_temp_free_i32(tmp2); | ||
306 | if (op < 8) { | ||
307 | /* Accumulate. */ | ||
308 | tmp2 = neon_load_reg(rd, pass); | ||
309 | switch (op) { | ||
310 | - case 0: | ||
311 | - gen_neon_add(size, tmp, tmp2); | ||
312 | - break; | ||
313 | case 1: | ||
314 | { | ||
315 | TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
316 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
317 | tcg_temp_free_ptr(fpstatus); | ||
318 | break; | ||
319 | } | ||
320 | - case 4: | ||
321 | - gen_neon_rsb(size, tmp, tmp2); | ||
322 | - break; | ||
323 | case 5: | ||
324 | { | ||
325 | TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
326 | -- | 54 | -- |
327 | 2.20.1 | 55 | 2.25.1 |
328 | 56 | ||
329 | 57 | diff view generated by jsdifflib |
1 | Convert the Neon 3-reg-diff insns VMULL, VMLAL and VMLSL; these perform | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | a 32x32->64 multiply with possible accumulate. | ||
3 | 2 | ||
4 | Note that for VMLSL we do the accumulate directly with a subtraction | 3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | rather than doing a negate-then-add as the old code did. | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | --- | ||
7 | tests/tcg/aarch64/pcalign-a64.c | 37 +++++++++++++++++++++++++ | ||
8 | tests/tcg/arm/pcalign-a32.c | 46 +++++++++++++++++++++++++++++++ | ||
9 | tests/tcg/aarch64/Makefile.target | 4 +-- | ||
10 | tests/tcg/arm/Makefile.target | 4 +++ | ||
11 | 4 files changed, 89 insertions(+), 2 deletions(-) | ||
12 | create mode 100644 tests/tcg/aarch64/pcalign-a64.c | ||
13 | create mode 100644 tests/tcg/arm/pcalign-a32.c | ||
6 | 14 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | diff --git a/tests/tcg/aarch64/pcalign-a64.c b/tests/tcg/aarch64/pcalign-a64.c |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 16 | new file mode 100644 |
9 | --- | 17 | index XXXXXXX..XXXXXXX |
10 | target/arm/neon-dp.decode | 9 +++++ | 18 | --- /dev/null |
11 | target/arm/translate-neon.inc.c | 71 +++++++++++++++++++++++++++++++++ | 19 | +++ b/tests/tcg/aarch64/pcalign-a64.c |
12 | target/arm/translate.c | 21 +++------- | 20 | @@ -XXX,XX +XXX,XX @@ |
13 | 3 files changed, 86 insertions(+), 15 deletions(-) | 21 | +/* Test PC misalignment exception */ |
14 | |||
15 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/neon-dp.decode | ||
18 | +++ b/target/arm/neon-dp.decode | ||
19 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
20 | |||
21 | VABDL_S_3d 1111 001 0 1 . .. .... .... 0111 . 0 . 0 .... @3diff | ||
22 | VABDL_U_3d 1111 001 1 1 . .. .... .... 0111 . 0 . 0 .... @3diff | ||
23 | + | 22 | + |
24 | + VMLAL_S_3d 1111 001 0 1 . .. .... .... 1000 . 0 . 0 .... @3diff | 23 | +#include <assert.h> |
25 | + VMLAL_U_3d 1111 001 1 1 . .. .... .... 1000 . 0 . 0 .... @3diff | 24 | +#include <signal.h> |
25 | +#include <stdlib.h> | ||
26 | +#include <stdio.h> | ||
26 | + | 27 | + |
27 | + VMLSL_S_3d 1111 001 0 1 . .. .... .... 1010 . 0 . 0 .... @3diff | 28 | +static void *expected; |
28 | + VMLSL_U_3d 1111 001 1 1 . .. .... .... 1010 . 0 . 0 .... @3diff | ||
29 | + | 29 | + |
30 | + VMULL_S_3d 1111 001 0 1 . .. .... .... 1100 . 0 . 0 .... @3diff | 30 | +static void sigbus(int sig, siginfo_t *info, void *vuc) |
31 | + VMULL_U_3d 1111 001 1 1 . .. .... .... 1100 . 0 . 0 .... @3diff | ||
32 | ] | ||
33 | } | ||
34 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/target/arm/translate-neon.inc.c | ||
37 | +++ b/target/arm/translate-neon.inc.c | ||
38 | @@ -XXX,XX +XXX,XX @@ static bool trans_VABAL_U_3d(DisasContext *s, arg_3diff *a) | ||
39 | |||
40 | return do_long_3d(s, a, opfn[a->size], addfn[a->size]); | ||
41 | } | ||
42 | + | ||
43 | +static void gen_mull_s32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) | ||
44 | +{ | 31 | +{ |
45 | + TCGv_i32 lo = tcg_temp_new_i32(); | 32 | + assert(info->si_code == BUS_ADRALN); |
46 | + TCGv_i32 hi = tcg_temp_new_i32(); | 33 | + assert(info->si_addr == expected); |
47 | + | 34 | + exit(EXIT_SUCCESS); |
48 | + tcg_gen_muls2_i32(lo, hi, rn, rm); | ||
49 | + tcg_gen_concat_i32_i64(rd, lo, hi); | ||
50 | + | ||
51 | + tcg_temp_free_i32(lo); | ||
52 | + tcg_temp_free_i32(hi); | ||
53 | +} | 35 | +} |
54 | + | 36 | + |
55 | +static void gen_mull_u32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) | 37 | +int main() |
56 | +{ | 38 | +{ |
57 | + TCGv_i32 lo = tcg_temp_new_i32(); | 39 | + void *tmp; |
58 | + TCGv_i32 hi = tcg_temp_new_i32(); | ||
59 | + | 40 | + |
60 | + tcg_gen_mulu2_i32(lo, hi, rn, rm); | 41 | + struct sigaction sa = { |
61 | + tcg_gen_concat_i32_i64(rd, lo, hi); | 42 | + .sa_sigaction = sigbus, |
43 | + .sa_flags = SA_SIGINFO | ||
44 | + }; | ||
62 | + | 45 | + |
63 | + tcg_temp_free_i32(lo); | 46 | + if (sigaction(SIGBUS, &sa, NULL) < 0) { |
64 | + tcg_temp_free_i32(hi); | 47 | + perror("sigaction"); |
48 | + return EXIT_FAILURE; | ||
49 | + } | ||
50 | + | ||
51 | + asm volatile("adr %0, 1f + 1\n\t" | ||
52 | + "str %0, %1\n\t" | ||
53 | + "br %0\n" | ||
54 | + "1:" | ||
55 | + : "=&r"(tmp), "=m"(expected)); | ||
56 | + abort(); | ||
57 | +} | ||
58 | diff --git a/tests/tcg/arm/pcalign-a32.c b/tests/tcg/arm/pcalign-a32.c | ||
59 | new file mode 100644 | ||
60 | index XXXXXXX..XXXXXXX | ||
61 | --- /dev/null | ||
62 | +++ b/tests/tcg/arm/pcalign-a32.c | ||
63 | @@ -XXX,XX +XXX,XX @@ | ||
64 | +/* Test PC misalignment exception */ | ||
65 | + | ||
66 | +#ifdef __thumb__ | ||
67 | +#error "This test must be compiled for ARM" | ||
68 | +#endif | ||
69 | + | ||
70 | +#include <assert.h> | ||
71 | +#include <signal.h> | ||
72 | +#include <stdlib.h> | ||
73 | +#include <stdio.h> | ||
74 | + | ||
75 | +static void *expected; | ||
76 | + | ||
77 | +static void sigbus(int sig, siginfo_t *info, void *vuc) | ||
78 | +{ | ||
79 | + assert(info->si_code == BUS_ADRALN); | ||
80 | + assert(info->si_addr == expected); | ||
81 | + exit(EXIT_SUCCESS); | ||
65 | +} | 82 | +} |
66 | + | 83 | + |
67 | +static bool trans_VMULL_S_3d(DisasContext *s, arg_3diff *a) | 84 | +int main() |
68 | +{ | 85 | +{ |
69 | + static NeonGenTwoOpWidenFn * const opfn[] = { | 86 | + void *tmp; |
70 | + gen_helper_neon_mull_s8, | 87 | + |
71 | + gen_helper_neon_mull_s16, | 88 | + struct sigaction sa = { |
72 | + gen_mull_s32, | 89 | + .sa_sigaction = sigbus, |
73 | + NULL, | 90 | + .sa_flags = SA_SIGINFO |
74 | + }; | 91 | + }; |
75 | + | 92 | + |
76 | + return do_long_3d(s, a, opfn[a->size], NULL); | 93 | + if (sigaction(SIGBUS, &sa, NULL) < 0) { |
77 | +} | 94 | + perror("sigaction"); |
78 | + | 95 | + return EXIT_FAILURE; |
79 | +static bool trans_VMULL_U_3d(DisasContext *s, arg_3diff *a) | ||
80 | +{ | ||
81 | + static NeonGenTwoOpWidenFn * const opfn[] = { | ||
82 | + gen_helper_neon_mull_u8, | ||
83 | + gen_helper_neon_mull_u16, | ||
84 | + gen_mull_u32, | ||
85 | + NULL, | ||
86 | + }; | ||
87 | + | ||
88 | + return do_long_3d(s, a, opfn[a->size], NULL); | ||
89 | +} | ||
90 | + | ||
91 | +#define DO_VMLAL(INSN,MULL,ACC) \ | ||
92 | + static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ | ||
93 | + { \ | ||
94 | + static NeonGenTwoOpWidenFn * const opfn[] = { \ | ||
95 | + gen_helper_neon_##MULL##8, \ | ||
96 | + gen_helper_neon_##MULL##16, \ | ||
97 | + gen_##MULL##32, \ | ||
98 | + NULL, \ | ||
99 | + }; \ | ||
100 | + static NeonGenTwo64OpFn * const accfn[] = { \ | ||
101 | + gen_helper_neon_##ACC##l_u16, \ | ||
102 | + gen_helper_neon_##ACC##l_u32, \ | ||
103 | + tcg_gen_##ACC##_i64, \ | ||
104 | + NULL, \ | ||
105 | + }; \ | ||
106 | + return do_long_3d(s, a, opfn[a->size], accfn[a->size]); \ | ||
107 | + } | 96 | + } |
108 | + | 97 | + |
109 | +DO_VMLAL(VMLAL_S,mull_s,add) | 98 | + asm volatile("adr %0, 1f + 2\n\t" |
110 | +DO_VMLAL(VMLAL_U,mull_u,add) | 99 | + "str %0, %1\n\t" |
111 | +DO_VMLAL(VMLSL_S,mull_s,sub) | 100 | + "bx %0\n" |
112 | +DO_VMLAL(VMLSL_U,mull_u,sub) | 101 | + "1:" |
113 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 102 | + : "=&r"(tmp), "=m"(expected)); |
103 | + | ||
104 | + /* | ||
105 | + * From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns | ||
106 | + * the address or not. If so, we can legitimately fall through. | ||
107 | + */ | ||
108 | + return EXIT_SUCCESS; | ||
109 | +} | ||
110 | diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target | ||
114 | index XXXXXXX..XXXXXXX 100644 | 111 | index XXXXXXX..XXXXXXX 100644 |
115 | --- a/target/arm/translate.c | 112 | --- a/tests/tcg/aarch64/Makefile.target |
116 | +++ b/target/arm/translate.c | 113 | +++ b/tests/tcg/aarch64/Makefile.target |
117 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 114 | @@ -XXX,XX +XXX,XX @@ VPATH += $(ARM_SRC) |
118 | {0, 0, 0, 7}, /* VABAL */ | 115 | AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64 |
119 | {0, 0, 0, 7}, /* VSUBHN: handled by decodetree */ | 116 | VPATH += $(AARCH64_SRC) |
120 | {0, 0, 0, 7}, /* VABDL */ | 117 | |
121 | - {0, 0, 0, 0}, /* VMLAL */ | 118 | -# Float-convert Tests |
122 | + {0, 0, 0, 7}, /* VMLAL */ | 119 | -AARCH64_TESTS=fcvt |
123 | {0, 0, 0, 9}, /* VQDMLAL */ | 120 | +# Base architecture tests |
124 | - {0, 0, 0, 0}, /* VMLSL */ | 121 | +AARCH64_TESTS=fcvt pcalign-a64 |
125 | + {0, 0, 0, 7}, /* VMLSL */ | 122 | |
126 | {0, 0, 0, 9}, /* VQDMLSL */ | 123 | fcvt: LDFLAGS+=-lm |
127 | - {0, 0, 0, 0}, /* Integer VMULL */ | 124 | |
128 | + {0, 0, 0, 7}, /* Integer VMULL */ | 125 | diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target |
129 | {0, 0, 0, 9}, /* VQDMULL */ | 126 | index XXXXXXX..XXXXXXX 100644 |
130 | {0, 0, 0, 0xa}, /* Polynomial VMULL */ | 127 | --- a/tests/tcg/arm/Makefile.target |
131 | {0, 0, 0, 7}, /* Reserved: always UNDEF */ | 128 | +++ b/tests/tcg/arm/Makefile.target |
132 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 129 | @@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt |
133 | tmp2 = neon_load_reg(rm, pass); | 130 | $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") |
134 | } | 131 | $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) |
135 | switch (op) { | 132 | |
136 | - case 8: case 9: case 10: case 11: case 12: case 13: | 133 | +# PC alignment test |
137 | - /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */ | 134 | +ARM_TESTS += pcalign-a32 |
138 | + case 9: case 11: case 13: | 135 | +pcalign-a32: CFLAGS+=-marm |
139 | + /* VQDMLAL, VQDMLSL, VQDMULL */ | 136 | + |
140 | gen_neon_mull(cpu_V0, tmp, tmp2, size, u); | 137 | ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y) |
141 | break; | 138 | |
142 | default: /* 15 is RESERVED: caught earlier */ | 139 | # Semihosting smoke test for linux-user |
143 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
144 | /* VQDMULL */ | ||
145 | gen_neon_addl_saturate(cpu_V0, cpu_V0, size); | ||
146 | neon_store_reg64(cpu_V0, rd + pass); | ||
147 | - } else if (op == 5 || (op >= 8 && op <= 11)) { | ||
148 | + } else { | ||
149 | /* Accumulate. */ | ||
150 | neon_load_reg64(cpu_V1, rd + pass); | ||
151 | switch (op) { | ||
152 | - case 10: /* VMLSL */ | ||
153 | - gen_neon_negl(cpu_V0, size); | ||
154 | - /* Fall through */ | ||
155 | - case 8: /* VABAL, VMLAL */ | ||
156 | - gen_neon_addl(size); | ||
157 | - break; | ||
158 | case 9: case 11: /* VQDMLAL, VQDMLSL */ | ||
159 | gen_neon_addl_saturate(cpu_V0, cpu_V0, size); | ||
160 | if (op == 11) { | ||
161 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
162 | abort(); | ||
163 | } | ||
164 | neon_store_reg64(cpu_V0, rd + pass); | ||
165 | - } else { | ||
166 | - /* Write back the result. */ | ||
167 | - neon_store_reg64(cpu_V0, rd + pass); | ||
168 | } | ||
169 | } | ||
170 | } else { | ||
171 | -- | 140 | -- |
172 | 2.20.1 | 141 | 2.25.1 |
173 | 142 | ||
174 | 143 | diff view generated by jsdifflib |
1 | In commit 37bfce81b10450071 we accidentally introduced a leak of a TCG | 1 | In the SSE decode function gen_sse(), we combine a byte |
---|---|---|---|
2 | temporary in do_2shift_env_64(); free it. | 2 | 'b' and a value 'b1' which can be [0..3], and switch on them: |
3 | b |= (b1 << 8); | ||
4 | switch (b) { | ||
5 | ... | ||
6 | default: | ||
7 | unknown_op: | ||
8 | gen_unknown_opcode(env, s); | ||
9 | return; | ||
10 | } | ||
3 | 11 | ||
12 | In three cases inside this switch, we were then also checking for | ||
13 | "if (b1 >= 2) { goto unknown_op; }". | ||
14 | However, this can never happen, because the 'case' values in each place | ||
15 | are 0x0nn or 0x1nn and the switch will have directed the b1 == (2, 3) | ||
16 | cases to the default already. | ||
17 | |||
18 | This check was added in commit c045af25a52e9 in 2010; the added code | ||
19 | was unnecessary then as well, and was apparently intended only to | ||
20 | ensure that we never accidentally ended up indexing off the end | ||
21 | of an sse_op_table with only 2 entries as a result of future bugs | ||
22 | in the decode logic. | ||
23 | |||
24 | Change the checks to assert() instead, and make sure they're always | ||
25 | immediately before the array access they are protecting. | ||
26 | |||
27 | Fixes: Coverity CID 1460207 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 28 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 29 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | --- | 30 | --- |
7 | target/arm/translate-neon.inc.c | 1 + | 31 | target/i386/tcg/translate.c | 12 +++--------- |
8 | 1 file changed, 1 insertion(+) | 32 | 1 file changed, 3 insertions(+), 9 deletions(-) |
9 | 33 | ||
10 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | 34 | diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c |
11 | index XXXXXXX..XXXXXXX 100644 | 35 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/target/arm/translate-neon.inc.c | 36 | --- a/target/i386/tcg/translate.c |
13 | +++ b/target/arm/translate-neon.inc.c | 37 | +++ b/target/i386/tcg/translate.c |
14 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a, | 38 | @@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, |
15 | neon_load_reg64(tmp, a->vm + pass); | 39 | case 0x171: /* shift xmm, im */ |
16 | fn(tmp, cpu_env, tmp, constimm); | 40 | case 0x172: |
17 | neon_store_reg64(tmp, a->vd + pass); | 41 | case 0x173: |
18 | + tcg_temp_free_i64(tmp); | 42 | - if (b1 >= 2) { |
19 | } | 43 | - goto unknown_op; |
20 | tcg_temp_free_i64(constimm); | 44 | - } |
21 | return true; | 45 | val = x86_ldub_code(env, s); |
46 | if (is_xmm) { | ||
47 | tcg_gen_movi_tl(s->T0, val); | ||
48 | @@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, | ||
49 | offsetof(CPUX86State, mmx_t0.MMX_L(1))); | ||
50 | op1_offset = offsetof(CPUX86State,mmx_t0); | ||
51 | } | ||
52 | + assert(b1 < 2); | ||
53 | sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 + | ||
54 | (((modrm >> 3)) & 7)][b1]; | ||
55 | if (!sse_fn_epp) { | ||
56 | @@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, | ||
57 | rm = modrm & 7; | ||
58 | reg = ((modrm >> 3) & 7) | REX_R(s); | ||
59 | mod = (modrm >> 6) & 3; | ||
60 | - if (b1 >= 2) { | ||
61 | - goto unknown_op; | ||
62 | - } | ||
63 | |||
64 | + assert(b1 < 2); | ||
65 | sse_fn_epp = sse_op_table6[b].op[b1]; | ||
66 | if (!sse_fn_epp) { | ||
67 | goto unknown_op; | ||
68 | @@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, | ||
69 | rm = modrm & 7; | ||
70 | reg = ((modrm >> 3) & 7) | REX_R(s); | ||
71 | mod = (modrm >> 6) & 3; | ||
72 | - if (b1 >= 2) { | ||
73 | - goto unknown_op; | ||
74 | - } | ||
75 | |||
76 | + assert(b1 < 2); | ||
77 | sse_fn_eppi = sse_op_table7[b].op[b1]; | ||
78 | if (!sse_fn_eppi) { | ||
79 | goto unknown_op; | ||
22 | -- | 80 | -- |
23 | 2.20.1 | 81 | 2.25.1 |
24 | 82 | ||
25 | 83 | diff view generated by jsdifflib |
1 | Convert the VQDMULH and VQRDMULH insns in the 2-reg-scalar group | 1 | The qemu-common.h header is not supposed to be included from any |
---|---|---|---|
2 | to decodetree. | 2 | other header files, only from .c files (as documented in a comment at |
3 | the start of it). | ||
4 | |||
5 | include/hw/i386/x86.h and include/hw/i386/microvm.h break this rule. | ||
6 | In fact, the include is not required at all, so we can just drop it | ||
7 | from both files. | ||
3 | 8 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
12 | Message-id: 20211129200510.1233037-2-peter.maydell@linaro.org | ||
6 | --- | 13 | --- |
7 | target/arm/neon-dp.decode | 3 +++ | 14 | include/hw/i386/microvm.h | 1 - |
8 | target/arm/translate-neon.inc.c | 29 +++++++++++++++++++++++ | 15 | include/hw/i386/x86.h | 1 - |
9 | target/arm/translate.c | 42 ++------------------------------- | 16 | 2 files changed, 2 deletions(-) |
10 | 3 files changed, 34 insertions(+), 40 deletions(-) | ||
11 | 17 | ||
12 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | 18 | diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h |
13 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/neon-dp.decode | 20 | --- a/include/hw/i386/microvm.h |
15 | +++ b/target/arm/neon-dp.decode | 21 | +++ b/include/hw/i386/microvm.h |
16 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | 22 | @@ -XXX,XX +XXX,XX @@ |
17 | 23 | #ifndef HW_I386_MICROVM_H | |
18 | VMUL_2sc 1111 001 . 1 . .. .... .... 1000 . 1 . 0 .... @2scalar | 24 | #define HW_I386_MICROVM_H |
19 | VMUL_F_2sc 1111 001 . 1 . .. .... .... 1001 . 1 . 0 .... @2scalar | 25 | |
20 | + | 26 | -#include "qemu-common.h" |
21 | + VQDMULH_2sc 1111 001 . 1 . .. .... .... 1100 . 1 . 0 .... @2scalar | 27 | #include "exec/hwaddr.h" |
22 | + VQRDMULH_2sc 1111 001 . 1 . .. .... .... 1101 . 1 . 0 .... @2scalar | 28 | #include "qemu/notify.h" |
23 | ] | 29 | |
24 | } | 30 | diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h |
25 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
26 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/target/arm/translate-neon.inc.c | 32 | --- a/include/hw/i386/x86.h |
28 | +++ b/target/arm/translate-neon.inc.c | 33 | +++ b/include/hw/i386/x86.h |
29 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMLS_F_2sc(DisasContext *s, arg_2scalar *a) | 34 | @@ -XXX,XX +XXX,XX @@ |
30 | 35 | #ifndef HW_I386_X86_H | |
31 | return do_2scalar(s, a, opfn[a->size], accfn[a->size]); | 36 | #define HW_I386_X86_H |
32 | } | 37 | |
33 | + | 38 | -#include "qemu-common.h" |
34 | +WRAP_ENV_FN(gen_VQDMULH_16, gen_helper_neon_qdmulh_s16) | 39 | #include "exec/hwaddr.h" |
35 | +WRAP_ENV_FN(gen_VQDMULH_32, gen_helper_neon_qdmulh_s32) | 40 | #include "qemu/notify.h" |
36 | +WRAP_ENV_FN(gen_VQRDMULH_16, gen_helper_neon_qrdmulh_s16) | 41 | |
37 | +WRAP_ENV_FN(gen_VQRDMULH_32, gen_helper_neon_qrdmulh_s32) | ||
38 | + | ||
39 | +static bool trans_VQDMULH_2sc(DisasContext *s, arg_2scalar *a) | ||
40 | +{ | ||
41 | + static NeonGenTwoOpFn * const opfn[] = { | ||
42 | + NULL, | ||
43 | + gen_VQDMULH_16, | ||
44 | + gen_VQDMULH_32, | ||
45 | + NULL, | ||
46 | + }; | ||
47 | + | ||
48 | + return do_2scalar(s, a, opfn[a->size], NULL); | ||
49 | +} | ||
50 | + | ||
51 | +static bool trans_VQRDMULH_2sc(DisasContext *s, arg_2scalar *a) | ||
52 | +{ | ||
53 | + static NeonGenTwoOpFn * const opfn[] = { | ||
54 | + NULL, | ||
55 | + gen_VQRDMULH_16, | ||
56 | + gen_VQRDMULH_32, | ||
57 | + NULL, | ||
58 | + }; | ||
59 | + | ||
60 | + return do_2scalar(s, a, opfn[a->size], NULL); | ||
61 | +} | ||
62 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
63 | index XXXXXXX..XXXXXXX 100644 | ||
64 | --- a/target/arm/translate.c | ||
65 | +++ b/target/arm/translate.c | ||
66 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc) | ||
67 | |||
68 | #define CPU_V001 cpu_V0, cpu_V0, cpu_V1 | ||
69 | |||
70 | -static TCGv_i32 neon_load_scratch(int scratch) | ||
71 | -{ | ||
72 | - TCGv_i32 tmp = tcg_temp_new_i32(); | ||
73 | - tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch])); | ||
74 | - return tmp; | ||
75 | -} | ||
76 | - | ||
77 | -static void neon_store_scratch(int scratch, TCGv_i32 var) | ||
78 | -{ | ||
79 | - tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch])); | ||
80 | - tcg_temp_free_i32(var); | ||
81 | -} | ||
82 | - | ||
83 | static int gen_neon_unzip(int rd, int rm, int size, int q) | ||
84 | { | ||
85 | TCGv_ptr pd, pm; | ||
86 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
87 | case 1: /* Float VMLA scalar */ | ||
88 | case 5: /* Floating point VMLS scalar */ | ||
89 | case 9: /* Floating point VMUL scalar */ | ||
90 | - return 1; /* handled by decodetree */ | ||
91 | - | ||
92 | case 12: /* VQDMULH scalar */ | ||
93 | case 13: /* VQRDMULH scalar */ | ||
94 | - if (u && ((rd | rn) & 1)) { | ||
95 | - return 1; | ||
96 | - } | ||
97 | - tmp = neon_get_scalar(size, rm); | ||
98 | - neon_store_scratch(0, tmp); | ||
99 | - for (pass = 0; pass < (u ? 4 : 2); pass++) { | ||
100 | - tmp = neon_load_scratch(0); | ||
101 | - tmp2 = neon_load_reg(rn, pass); | ||
102 | - if (op == 12) { | ||
103 | - if (size == 1) { | ||
104 | - gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2); | ||
105 | - } else { | ||
106 | - gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2); | ||
107 | - } | ||
108 | - } else { | ||
109 | - if (size == 1) { | ||
110 | - gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2); | ||
111 | - } else { | ||
112 | - gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2); | ||
113 | - } | ||
114 | - } | ||
115 | - tcg_temp_free_i32(tmp2); | ||
116 | - neon_store_reg(rd, pass, tmp); | ||
117 | - } | ||
118 | - break; | ||
119 | + return 1; /* handled by decodetree */ | ||
120 | + | ||
121 | case 3: /* VQDMLAL scalar */ | ||
122 | case 7: /* VQDMLSL scalar */ | ||
123 | case 11: /* VQDMULL scalar */ | ||
124 | -- | 42 | -- |
125 | 2.20.1 | 43 | 2.25.1 |
126 | 44 | ||
127 | 45 | diff view generated by jsdifflib |
1 | Mark the arrays of function pointers in trans_VSHLL_S_2sh() and | 1 | The qemu-common.h header is not supposed to be included from any |
---|---|---|---|
2 | trans_VSHLL_U_2sh() as both 'static' and 'const'. | 2 | other header files, only from .c files (as documented in a comment at |
3 | the start of it). | ||
4 | |||
5 | Move the include to linux-user/hexagon/cpu_loop.c, which needs it for | ||
6 | the declaration of cpu_exec_step_atomic(). | ||
3 | 7 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> | ||
12 | Message-id: 20211129200510.1233037-3-peter.maydell@linaro.org | ||
6 | --- | 13 | --- |
7 | target/arm/translate-neon.inc.c | 4 ++-- | 14 | target/hexagon/cpu.h | 1 - |
8 | 1 file changed, 2 insertions(+), 2 deletions(-) | 15 | linux-user/hexagon/cpu_loop.c | 1 + |
16 | 2 files changed, 1 insertion(+), 1 deletion(-) | ||
9 | 17 | ||
10 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | 18 | diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h |
11 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/target/arm/translate-neon.inc.c | 20 | --- a/target/hexagon/cpu.h |
13 | +++ b/target/arm/translate-neon.inc.c | 21 | +++ b/target/hexagon/cpu.h |
14 | @@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, | 22 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUHexagonState CPUHexagonState; |
15 | 23 | ||
16 | static bool trans_VSHLL_S_2sh(DisasContext *s, arg_2reg_shift *a) | 24 | #include "fpu/softfloat-types.h" |
17 | { | 25 | |
18 | - NeonGenWidenFn *widenfn[] = { | 26 | -#include "qemu-common.h" |
19 | + static NeonGenWidenFn * const widenfn[] = { | 27 | #include "exec/cpu-defs.h" |
20 | gen_helper_neon_widen_s8, | 28 | #include "hex_regs.h" |
21 | gen_helper_neon_widen_s16, | 29 | #include "mmvec/mmvec.h" |
22 | tcg_gen_ext_i32_i64, | 30 | diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c |
23 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL_S_2sh(DisasContext *s, arg_2reg_shift *a) | 31 | index XXXXXXX..XXXXXXX 100644 |
24 | 32 | --- a/linux-user/hexagon/cpu_loop.c | |
25 | static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a) | 33 | +++ b/linux-user/hexagon/cpu_loop.c |
26 | { | 34 | @@ -XXX,XX +XXX,XX @@ |
27 | - NeonGenWidenFn *widenfn[] = { | 35 | */ |
28 | + static NeonGenWidenFn * const widenfn[] = { | 36 | |
29 | gen_helper_neon_widen_u8, | 37 | #include "qemu/osdep.h" |
30 | gen_helper_neon_widen_u16, | 38 | +#include "qemu-common.h" |
31 | tcg_gen_extu_i32_i64, | 39 | #include "qemu.h" |
40 | #include "user-internals.h" | ||
41 | #include "cpu_loop-common.h" | ||
32 | -- | 42 | -- |
33 | 2.20.1 | 43 | 2.25.1 |
34 | 44 | ||
35 | 45 | diff view generated by jsdifflib |
1 | Convert the Neon 3-reg-diff insn polynomial VMULL. This is the last | 1 | The qemu-common.h header is not supposed to be included from any |
---|---|---|---|
2 | insn in this group to be converted. | 2 | other header files, only from .c files (as documented in a comment at |
3 | the start of it). | ||
4 | |||
5 | Nothing actually relies on target/rx/cpu.h including it, so we can | ||
6 | just drop the include. | ||
3 | 7 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> | ||
12 | Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> | ||
13 | Message-id: 20211129200510.1233037-4-peter.maydell@linaro.org | ||
6 | --- | 14 | --- |
7 | target/arm/neon-dp.decode | 2 ++ | 15 | target/rx/cpu.h | 1 - |
8 | target/arm/translate-neon.inc.c | 43 +++++++++++++++++++++++ | 16 | 1 file changed, 1 deletion(-) |
9 | target/arm/translate.c | 60 ++------------------------------- | ||
10 | 3 files changed, 48 insertions(+), 57 deletions(-) | ||
11 | 17 | ||
12 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | 18 | diff --git a/target/rx/cpu.h b/target/rx/cpu.h |
13 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/neon-dp.decode | 20 | --- a/target/rx/cpu.h |
15 | +++ b/target/arm/neon-dp.decode | 21 | +++ b/target/rx/cpu.h |
16 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | 22 | @@ -XXX,XX +XXX,XX @@ |
17 | VMULL_U_3d 1111 001 1 1 . .. .... .... 1100 . 0 . 0 .... @3diff | 23 | #define RX_CPU_H |
18 | 24 | ||
19 | VQDMULL_3d 1111 001 0 1 . .. .... .... 1101 . 0 . 0 .... @3diff | 25 | #include "qemu/bitops.h" |
20 | + | 26 | -#include "qemu-common.h" |
21 | + VMULL_P_3d 1111 001 0 1 . .. .... .... 1110 . 0 . 0 .... @3diff | 27 | #include "hw/registerfields.h" |
22 | ] | 28 | #include "cpu-qom.h" |
23 | } | 29 | |
24 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/target/arm/translate-neon.inc.c | ||
27 | +++ b/target/arm/translate-neon.inc.c | ||
28 | @@ -XXX,XX +XXX,XX @@ static bool trans_VQDMLSL_3d(DisasContext *s, arg_3diff *a) | ||
29 | |||
30 | return do_long_3d(s, a, opfn[a->size], accfn[a->size]); | ||
31 | } | ||
32 | + | ||
33 | +static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a) | ||
34 | +{ | ||
35 | + gen_helper_gvec_3 *fn_gvec; | ||
36 | + | ||
37 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
38 | + return false; | ||
39 | + } | ||
40 | + | ||
41 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
42 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
43 | + ((a->vd | a->vn | a->vm) & 0x10)) { | ||
44 | + return false; | ||
45 | + } | ||
46 | + | ||
47 | + if (a->vd & 1) { | ||
48 | + return false; | ||
49 | + } | ||
50 | + | ||
51 | + switch (a->size) { | ||
52 | + case 0: | ||
53 | + fn_gvec = gen_helper_neon_pmull_h; | ||
54 | + break; | ||
55 | + case 2: | ||
56 | + if (!dc_isar_feature(aa32_pmull, s)) { | ||
57 | + return false; | ||
58 | + } | ||
59 | + fn_gvec = gen_helper_gvec_pmull_q; | ||
60 | + break; | ||
61 | + default: | ||
62 | + return false; | ||
63 | + } | ||
64 | + | ||
65 | + if (!vfp_access_check(s)) { | ||
66 | + return true; | ||
67 | + } | ||
68 | + | ||
69 | + tcg_gen_gvec_3_ool(neon_reg_offset(a->vd, 0), | ||
70 | + neon_reg_offset(a->vn, 0), | ||
71 | + neon_reg_offset(a->vm, 0), | ||
72 | + 16, 16, 0, fn_gvec); | ||
73 | + return true; | ||
74 | +} | ||
75 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
76 | index XXXXXXX..XXXXXXX 100644 | ||
77 | --- a/target/arm/translate.c | ||
78 | +++ b/target/arm/translate.c | ||
79 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
80 | { | ||
81 | int op; | ||
82 | int q; | ||
83 | - int rd, rn, rm, rd_ofs, rn_ofs, rm_ofs; | ||
84 | + int rd, rn, rm, rd_ofs, rm_ofs; | ||
85 | int size; | ||
86 | int pass; | ||
87 | int u; | ||
88 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
89 | size = (insn >> 20) & 3; | ||
90 | vec_size = q ? 16 : 8; | ||
91 | rd_ofs = neon_reg_offset(rd, 0); | ||
92 | - rn_ofs = neon_reg_offset(rn, 0); | ||
93 | rm_ofs = neon_reg_offset(rm, 0); | ||
94 | |||
95 | if ((insn & (1 << 23)) == 0) { | ||
96 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
97 | if (size != 3) { | ||
98 | op = (insn >> 8) & 0xf; | ||
99 | if ((insn & (1 << 6)) == 0) { | ||
100 | - /* Three registers of different lengths. */ | ||
101 | - /* undefreq: bit 0 : UNDEF if size == 0 | ||
102 | - * bit 1 : UNDEF if size == 1 | ||
103 | - * bit 2 : UNDEF if size == 2 | ||
104 | - * bit 3 : UNDEF if U == 1 | ||
105 | - * Note that [2:0] set implies 'always UNDEF' | ||
106 | - */ | ||
107 | - int undefreq; | ||
108 | - /* prewiden, src1_wide, src2_wide, undefreq */ | ||
109 | - static const int neon_3reg_wide[16][4] = { | ||
110 | - {0, 0, 0, 7}, /* VADDL: handled by decodetree */ | ||
111 | - {0, 0, 0, 7}, /* VADDW: handled by decodetree */ | ||
112 | - {0, 0, 0, 7}, /* VSUBL: handled by decodetree */ | ||
113 | - {0, 0, 0, 7}, /* VSUBW: handled by decodetree */ | ||
114 | - {0, 0, 0, 7}, /* VADDHN: handled by decodetree */ | ||
115 | - {0, 0, 0, 7}, /* VABAL */ | ||
116 | - {0, 0, 0, 7}, /* VSUBHN: handled by decodetree */ | ||
117 | - {0, 0, 0, 7}, /* VABDL */ | ||
118 | - {0, 0, 0, 7}, /* VMLAL */ | ||
119 | - {0, 0, 0, 7}, /* VQDMLAL */ | ||
120 | - {0, 0, 0, 7}, /* VMLSL */ | ||
121 | - {0, 0, 0, 7}, /* VQDMLSL */ | ||
122 | - {0, 0, 0, 7}, /* Integer VMULL */ | ||
123 | - {0, 0, 0, 7}, /* VQDMULL */ | ||
124 | - {0, 0, 0, 0xa}, /* Polynomial VMULL */ | ||
125 | - {0, 0, 0, 7}, /* Reserved: always UNDEF */ | ||
126 | - }; | ||
127 | - | ||
128 | - undefreq = neon_3reg_wide[op][3]; | ||
129 | - | ||
130 | - if ((undefreq & (1 << size)) || | ||
131 | - ((undefreq & 8) && u)) { | ||
132 | - return 1; | ||
133 | - } | ||
134 | - if (rd & 1) { | ||
135 | - return 1; | ||
136 | - } | ||
137 | - | ||
138 | - /* Handle polynomial VMULL in a single pass. */ | ||
139 | - if (op == 14) { | ||
140 | - if (size == 0) { | ||
141 | - /* VMULL.P8 */ | ||
142 | - tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, 16, 16, | ||
143 | - 0, gen_helper_neon_pmull_h); | ||
144 | - } else { | ||
145 | - /* VMULL.P64 */ | ||
146 | - if (!dc_isar_feature(aa32_pmull, s)) { | ||
147 | - return 1; | ||
148 | - } | ||
149 | - tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, 16, 16, | ||
150 | - 0, gen_helper_gvec_pmull_q); | ||
151 | - } | ||
152 | - return 0; | ||
153 | - } | ||
154 | - abort(); /* all others handled by decodetree */ | ||
155 | + /* Three registers of different lengths: handled by decodetree */ | ||
156 | + return 1; | ||
157 | } else { | ||
158 | /* Two registers and a scalar. NB that for ops of this form | ||
159 | * the ARM ARM labels bit 24 as Q, but it is in our variable | ||
160 | -- | 30 | -- |
161 | 2.20.1 | 31 | 2.25.1 |
162 | 32 | ||
163 | 33 | diff view generated by jsdifflib |
1 | The widenfn() in do_vshll_2sh() does not free the input 32-bit | 1 | A lot of C files in hw/arm include qemu-common.h when they don't |
---|---|---|---|
2 | TCGv, so we need to do this in the calling code. | 2 | need anything from it. Drop the include lines. |
3 | |||
4 | omap1.c, pxa2xx.c and strongarm.c retain the include because they | ||
5 | use it for the prototype of qemu_get_timedate(). | ||
3 | 6 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
10 | Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> | ||
11 | Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> | ||
12 | Message-id: 20211129200510.1233037-5-peter.maydell@linaro.org | ||
7 | --- | 13 | --- |
8 | target/arm/translate-neon.inc.c | 2 ++ | 14 | hw/arm/boot.c | 1 - |
9 | 1 file changed, 2 insertions(+) | 15 | hw/arm/digic_boards.c | 1 - |
16 | hw/arm/highbank.c | 1 - | ||
17 | hw/arm/npcm7xx_boards.c | 1 - | ||
18 | hw/arm/sbsa-ref.c | 1 - | ||
19 | hw/arm/stm32f405_soc.c | 1 - | ||
20 | hw/arm/vexpress.c | 1 - | ||
21 | hw/arm/virt.c | 1 - | ||
22 | 8 files changed, 8 deletions(-) | ||
10 | 23 | ||
11 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | 24 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c |
12 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate-neon.inc.c | 26 | --- a/hw/arm/boot.c |
14 | +++ b/target/arm/translate-neon.inc.c | 27 | +++ b/hw/arm/boot.c |
15 | @@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, | 28 | @@ -XXX,XX +XXX,XX @@ |
16 | tmp = tcg_temp_new_i64(); | 29 | */ |
17 | 30 | ||
18 | widenfn(tmp, rm0); | 31 | #include "qemu/osdep.h" |
19 | + tcg_temp_free_i32(rm0); | 32 | -#include "qemu-common.h" |
20 | if (a->shift != 0) { | 33 | #include "qemu/datadir.h" |
21 | tcg_gen_shli_i64(tmp, tmp, a->shift); | 34 | #include "qemu/error-report.h" |
22 | tcg_gen_andi_i64(tmp, tmp, ~widen_mask); | 35 | #include "qapi/error.h" |
23 | @@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, | 36 | diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c |
24 | neon_store_reg64(tmp, a->vd); | 37 | index XXXXXXX..XXXXXXX 100644 |
25 | 38 | --- a/hw/arm/digic_boards.c | |
26 | widenfn(tmp, rm1); | 39 | +++ b/hw/arm/digic_boards.c |
27 | + tcg_temp_free_i32(rm1); | 40 | @@ -XXX,XX +XXX,XX @@ |
28 | if (a->shift != 0) { | 41 | |
29 | tcg_gen_shli_i64(tmp, tmp, a->shift); | 42 | #include "qemu/osdep.h" |
30 | tcg_gen_andi_i64(tmp, tmp, ~widen_mask); | 43 | #include "qapi/error.h" |
44 | -#include "qemu-common.h" | ||
45 | #include "qemu/datadir.h" | ||
46 | #include "hw/boards.h" | ||
47 | #include "qemu/error-report.h" | ||
48 | diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/hw/arm/highbank.c | ||
51 | +++ b/hw/arm/highbank.c | ||
52 | @@ -XXX,XX +XXX,XX @@ | ||
53 | */ | ||
54 | |||
55 | #include "qemu/osdep.h" | ||
56 | -#include "qemu-common.h" | ||
57 | #include "qemu/datadir.h" | ||
58 | #include "qapi/error.h" | ||
59 | #include "hw/sysbus.h" | ||
60 | diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c | ||
61 | index XXXXXXX..XXXXXXX 100644 | ||
62 | --- a/hw/arm/npcm7xx_boards.c | ||
63 | +++ b/hw/arm/npcm7xx_boards.c | ||
64 | @@ -XXX,XX +XXX,XX @@ | ||
65 | #include "hw/qdev-core.h" | ||
66 | #include "hw/qdev-properties.h" | ||
67 | #include "qapi/error.h" | ||
68 | -#include "qemu-common.h" | ||
69 | #include "qemu/datadir.h" | ||
70 | #include "qemu/units.h" | ||
71 | #include "sysemu/blockdev.h" | ||
72 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/hw/arm/sbsa-ref.c | ||
75 | +++ b/hw/arm/sbsa-ref.c | ||
76 | @@ -XXX,XX +XXX,XX @@ | ||
77 | */ | ||
78 | |||
79 | #include "qemu/osdep.h" | ||
80 | -#include "qemu-common.h" | ||
81 | #include "qemu/datadir.h" | ||
82 | #include "qapi/error.h" | ||
83 | #include "qemu/error-report.h" | ||
84 | diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c | ||
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/hw/arm/stm32f405_soc.c | ||
87 | +++ b/hw/arm/stm32f405_soc.c | ||
88 | @@ -XXX,XX +XXX,XX @@ | ||
89 | |||
90 | #include "qemu/osdep.h" | ||
91 | #include "qapi/error.h" | ||
92 | -#include "qemu-common.h" | ||
93 | #include "exec/address-spaces.h" | ||
94 | #include "sysemu/sysemu.h" | ||
95 | #include "hw/arm/stm32f405_soc.h" | ||
96 | diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c | ||
97 | index XXXXXXX..XXXXXXX 100644 | ||
98 | --- a/hw/arm/vexpress.c | ||
99 | +++ b/hw/arm/vexpress.c | ||
100 | @@ -XXX,XX +XXX,XX @@ | ||
101 | |||
102 | #include "qemu/osdep.h" | ||
103 | #include "qapi/error.h" | ||
104 | -#include "qemu-common.h" | ||
105 | #include "qemu/datadir.h" | ||
106 | #include "cpu.h" | ||
107 | #include "hw/sysbus.h" | ||
108 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
109 | index XXXXXXX..XXXXXXX 100644 | ||
110 | --- a/hw/arm/virt.c | ||
111 | +++ b/hw/arm/virt.c | ||
112 | @@ -XXX,XX +XXX,XX @@ | ||
113 | */ | ||
114 | |||
115 | #include "qemu/osdep.h" | ||
116 | -#include "qemu-common.h" | ||
117 | #include "qemu/datadir.h" | ||
118 | #include "qemu/units.h" | ||
119 | #include "qemu/option.h" | ||
31 | -- | 120 | -- |
32 | 2.20.1 | 121 | 2.25.1 |
33 | 122 | ||
34 | 123 | diff view generated by jsdifflib |
1 | Convert the Neon 3-reg-diff insns VABAL and VABDL to decodetree. | 1 | The calculation of the length of TLB range invalidate operations |
---|---|---|---|
2 | Like almost all the remaining insns in this group, these are | 2 | in tlbi_aa64_range_get_length() is incorrect in two ways: |
3 | a combination of a two-input operation which returns a double width | 3 | * the NUM field is 5 bits, but we read only 4 bits |
4 | result and then a possible accumulation of that double width | 4 | * we miscalculate the page_shift value, because of an |
5 | result into the destination. | 5 | off-by-one error: |
6 | TG 0b00 is invalid | ||
7 | TG 0b01 is 4K granule size == 4096 == 2^12 | ||
8 | TG 0b10 is 16K granule size == 16384 == 2^14 | ||
9 | TG 0b11 is 64K granule size == 65536 == 2^16 | ||
10 | so page_shift should be (TG - 1) * 2 + 12 | ||
6 | 11 | ||
12 | Thanks to the bug report submitter Cha HyunSoo for identifying | ||
13 | both these errors. | ||
14 | |||
15 | Fixes: 84940ed82552d3c ("target/arm: Add support for FEAT_TLBIRANGE") | ||
16 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/734 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
19 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
20 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
21 | Message-id: 20211130173257.1274194-1-peter.maydell@linaro.org | ||
9 | --- | 22 | --- |
10 | target/arm/translate.h | 1 + | 23 | target/arm/helper.c | 6 +++--- |
11 | target/arm/neon-dp.decode | 6 ++ | 24 | 1 file changed, 3 insertions(+), 3 deletions(-) |
12 | target/arm/translate-neon.inc.c | 132 ++++++++++++++++++++++++++++++++ | ||
13 | target/arm/translate.c | 31 +------- | ||
14 | 4 files changed, 142 insertions(+), 28 deletions(-) | ||
15 | 25 | ||
16 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 26 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
17 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/translate.h | 28 | --- a/target/arm/helper.c |
19 | +++ b/target/arm/translate.h | 29 | +++ b/target/arm/helper.c |
20 | @@ -XXX,XX +XXX,XX @@ typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); | 30 | @@ -XXX,XX +XXX,XX @@ static uint64_t tlbi_aa64_range_get_length(CPUARMState *env, |
21 | typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); | 31 | uint64_t exponent; |
22 | typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64); | 32 | uint64_t length; |
23 | typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); | 33 | |
24 | +typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32); | 34 | - num = extract64(value, 39, 4); |
25 | typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); | 35 | + num = extract64(value, 39, 5); |
26 | typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); | 36 | scale = extract64(value, 44, 2); |
27 | typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); | 37 | page_size_granule = extract64(value, 46, 2); |
28 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | 38 | |
29 | index XXXXXXX..XXXXXXX 100644 | 39 | - page_shift = page_size_granule * 2 + 12; |
30 | --- a/target/arm/neon-dp.decode | 40 | - |
31 | +++ b/target/arm/neon-dp.decode | 41 | if (page_size_granule == 0) { |
32 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | 42 | qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", |
33 | VADDHN_3d 1111 001 0 1 . .. .... .... 0100 . 0 . 0 .... @3diff | 43 | page_size_granule); |
34 | VRADDHN_3d 1111 001 1 1 . .. .... .... 0100 . 0 . 0 .... @3diff | 44 | return 0; |
35 | 45 | } | |
36 | + VABAL_S_3d 1111 001 0 1 . .. .... .... 0101 . 0 . 0 .... @3diff | 46 | |
37 | + VABAL_U_3d 1111 001 1 1 . .. .... .... 0101 . 0 . 0 .... @3diff | 47 | + page_shift = (page_size_granule - 1) * 2 + 12; |
38 | + | 48 | + |
39 | VSUBHN_3d 1111 001 0 1 . .. .... .... 0110 . 0 . 0 .... @3diff | 49 | exponent = (5 * scale) + 1; |
40 | VRSUBHN_3d 1111 001 1 1 . .. .... .... 0110 . 0 . 0 .... @3diff | 50 | length = (num + 1) << (exponent + page_shift); |
41 | + | 51 | |
42 | + VABDL_S_3d 1111 001 0 1 . .. .... .... 0111 . 0 . 0 .... @3diff | ||
43 | + VABDL_U_3d 1111 001 1 1 . .. .... .... 0111 . 0 . 0 .... @3diff | ||
44 | ] | ||
45 | } | ||
46 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/translate-neon.inc.c | ||
49 | +++ b/target/arm/translate-neon.inc.c | ||
50 | @@ -XXX,XX +XXX,XX @@ DO_NARROW_3D(VADDHN, add, narrow, tcg_gen_extrh_i64_i32) | ||
51 | DO_NARROW_3D(VSUBHN, sub, narrow, tcg_gen_extrh_i64_i32) | ||
52 | DO_NARROW_3D(VRADDHN, add, narrow_round, gen_narrow_round_high_u32) | ||
53 | DO_NARROW_3D(VRSUBHN, sub, narrow_round, gen_narrow_round_high_u32) | ||
54 | + | ||
55 | +static bool do_long_3d(DisasContext *s, arg_3diff *a, | ||
56 | + NeonGenTwoOpWidenFn *opfn, | ||
57 | + NeonGenTwo64OpFn *accfn) | ||
58 | +{ | ||
59 | + /* | ||
60 | + * 3-regs different lengths, long operations. | ||
61 | + * These perform an operation on two inputs that returns a double-width | ||
62 | + * result, and then possibly perform an accumulation operation of | ||
63 | + * that result into the double-width destination. | ||
64 | + */ | ||
65 | + TCGv_i64 rd0, rd1, tmp; | ||
66 | + TCGv_i32 rn, rm; | ||
67 | + | ||
68 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
69 | + return false; | ||
70 | + } | ||
71 | + | ||
72 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
73 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
74 | + ((a->vd | a->vn | a->vm) & 0x10)) { | ||
75 | + return false; | ||
76 | + } | ||
77 | + | ||
78 | + if (!opfn) { | ||
79 | + /* size == 3 case, which is an entirely different insn group */ | ||
80 | + return false; | ||
81 | + } | ||
82 | + | ||
83 | + if (a->vd & 1) { | ||
84 | + return false; | ||
85 | + } | ||
86 | + | ||
87 | + if (!vfp_access_check(s)) { | ||
88 | + return true; | ||
89 | + } | ||
90 | + | ||
91 | + rd0 = tcg_temp_new_i64(); | ||
92 | + rd1 = tcg_temp_new_i64(); | ||
93 | + | ||
94 | + rn = neon_load_reg(a->vn, 0); | ||
95 | + rm = neon_load_reg(a->vm, 0); | ||
96 | + opfn(rd0, rn, rm); | ||
97 | + tcg_temp_free_i32(rn); | ||
98 | + tcg_temp_free_i32(rm); | ||
99 | + | ||
100 | + rn = neon_load_reg(a->vn, 1); | ||
101 | + rm = neon_load_reg(a->vm, 1); | ||
102 | + opfn(rd1, rn, rm); | ||
103 | + tcg_temp_free_i32(rn); | ||
104 | + tcg_temp_free_i32(rm); | ||
105 | + | ||
106 | + /* Don't store results until after all loads: they might overlap */ | ||
107 | + if (accfn) { | ||
108 | + tmp = tcg_temp_new_i64(); | ||
109 | + neon_load_reg64(tmp, a->vd); | ||
110 | + accfn(tmp, tmp, rd0); | ||
111 | + neon_store_reg64(tmp, a->vd); | ||
112 | + neon_load_reg64(tmp, a->vd + 1); | ||
113 | + accfn(tmp, tmp, rd1); | ||
114 | + neon_store_reg64(tmp, a->vd + 1); | ||
115 | + tcg_temp_free_i64(tmp); | ||
116 | + } else { | ||
117 | + neon_store_reg64(rd0, a->vd); | ||
118 | + neon_store_reg64(rd1, a->vd + 1); | ||
119 | + } | ||
120 | + | ||
121 | + tcg_temp_free_i64(rd0); | ||
122 | + tcg_temp_free_i64(rd1); | ||
123 | + | ||
124 | + return true; | ||
125 | +} | ||
126 | + | ||
127 | +static bool trans_VABDL_S_3d(DisasContext *s, arg_3diff *a) | ||
128 | +{ | ||
129 | + static NeonGenTwoOpWidenFn * const opfn[] = { | ||
130 | + gen_helper_neon_abdl_s16, | ||
131 | + gen_helper_neon_abdl_s32, | ||
132 | + gen_helper_neon_abdl_s64, | ||
133 | + NULL, | ||
134 | + }; | ||
135 | + | ||
136 | + return do_long_3d(s, a, opfn[a->size], NULL); | ||
137 | +} | ||
138 | + | ||
139 | +static bool trans_VABDL_U_3d(DisasContext *s, arg_3diff *a) | ||
140 | +{ | ||
141 | + static NeonGenTwoOpWidenFn * const opfn[] = { | ||
142 | + gen_helper_neon_abdl_u16, | ||
143 | + gen_helper_neon_abdl_u32, | ||
144 | + gen_helper_neon_abdl_u64, | ||
145 | + NULL, | ||
146 | + }; | ||
147 | + | ||
148 | + return do_long_3d(s, a, opfn[a->size], NULL); | ||
149 | +} | ||
150 | + | ||
151 | +static bool trans_VABAL_S_3d(DisasContext *s, arg_3diff *a) | ||
152 | +{ | ||
153 | + static NeonGenTwoOpWidenFn * const opfn[] = { | ||
154 | + gen_helper_neon_abdl_s16, | ||
155 | + gen_helper_neon_abdl_s32, | ||
156 | + gen_helper_neon_abdl_s64, | ||
157 | + NULL, | ||
158 | + }; | ||
159 | + static NeonGenTwo64OpFn * const addfn[] = { | ||
160 | + gen_helper_neon_addl_u16, | ||
161 | + gen_helper_neon_addl_u32, | ||
162 | + tcg_gen_add_i64, | ||
163 | + NULL, | ||
164 | + }; | ||
165 | + | ||
166 | + return do_long_3d(s, a, opfn[a->size], addfn[a->size]); | ||
167 | +} | ||
168 | + | ||
169 | +static bool trans_VABAL_U_3d(DisasContext *s, arg_3diff *a) | ||
170 | +{ | ||
171 | + static NeonGenTwoOpWidenFn * const opfn[] = { | ||
172 | + gen_helper_neon_abdl_u16, | ||
173 | + gen_helper_neon_abdl_u32, | ||
174 | + gen_helper_neon_abdl_u64, | ||
175 | + NULL, | ||
176 | + }; | ||
177 | + static NeonGenTwo64OpFn * const addfn[] = { | ||
178 | + gen_helper_neon_addl_u16, | ||
179 | + gen_helper_neon_addl_u32, | ||
180 | + tcg_gen_add_i64, | ||
181 | + NULL, | ||
182 | + }; | ||
183 | + | ||
184 | + return do_long_3d(s, a, opfn[a->size], addfn[a->size]); | ||
185 | +} | ||
186 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
187 | index XXXXXXX..XXXXXXX 100644 | ||
188 | --- a/target/arm/translate.c | ||
189 | +++ b/target/arm/translate.c | ||
190 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
191 | {0, 0, 0, 7}, /* VSUBL: handled by decodetree */ | ||
192 | {0, 0, 0, 7}, /* VSUBW: handled by decodetree */ | ||
193 | {0, 0, 0, 7}, /* VADDHN: handled by decodetree */ | ||
194 | - {0, 0, 0, 0}, /* VABAL */ | ||
195 | + {0, 0, 0, 7}, /* VABAL */ | ||
196 | {0, 0, 0, 7}, /* VSUBHN: handled by decodetree */ | ||
197 | - {0, 0, 0, 0}, /* VABDL */ | ||
198 | + {0, 0, 0, 7}, /* VABDL */ | ||
199 | {0, 0, 0, 0}, /* VMLAL */ | ||
200 | {0, 0, 0, 9}, /* VQDMLAL */ | ||
201 | {0, 0, 0, 0}, /* VMLSL */ | ||
202 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
203 | tmp2 = neon_load_reg(rm, pass); | ||
204 | } | ||
205 | switch (op) { | ||
206 | - case 5: case 7: /* VABAL, VABDL */ | ||
207 | - switch ((size << 1) | u) { | ||
208 | - case 0: | ||
209 | - gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2); | ||
210 | - break; | ||
211 | - case 1: | ||
212 | - gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2); | ||
213 | - break; | ||
214 | - case 2: | ||
215 | - gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2); | ||
216 | - break; | ||
217 | - case 3: | ||
218 | - gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2); | ||
219 | - break; | ||
220 | - case 4: | ||
221 | - gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2); | ||
222 | - break; | ||
223 | - case 5: | ||
224 | - gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2); | ||
225 | - break; | ||
226 | - default: abort(); | ||
227 | - } | ||
228 | - tcg_temp_free_i32(tmp2); | ||
229 | - tcg_temp_free_i32(tmp); | ||
230 | - break; | ||
231 | case 8: case 9: case 10: case 11: case 12: case 13: | ||
232 | /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */ | ||
233 | gen_neon_mull(cpu_V0, tmp, tmp2, size, u); | ||
234 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
235 | case 10: /* VMLSL */ | ||
236 | gen_neon_negl(cpu_V0, size); | ||
237 | /* Fall through */ | ||
238 | - case 5: case 8: /* VABAL, VMLAL */ | ||
239 | + case 8: /* VABAL, VMLAL */ | ||
240 | gen_neon_addl(size); | ||
241 | break; | ||
242 | case 9: case 11: /* VQDMLAL, VQDMLSL */ | ||
243 | -- | 52 | -- |
244 | 2.20.1 | 53 | 2.25.1 |
245 | 54 | ||
246 | 55 | diff view generated by jsdifflib |
1 | Convert the narrow-to-high-half insns VADDHN, VSUBHN, VRADDHN, | 1 | From: Patrick Venture <venture@google.com> |
---|---|---|---|
2 | VRSUBHN in the Neon 3-registers-different-lengths group to | ||
3 | decodetree. | ||
4 | 2 | ||
3 | The rx_active boolean change to true should always trigger a try_read | ||
4 | call that flushes the queue. | ||
5 | |||
6 | Signed-off-by: Patrick Venture <venture@google.com> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Message-id: 20211203221002.1719306-1-venture@google.com | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | --- | 10 | --- |
8 | target/arm/neon-dp.decode | 6 +++ | 11 | hw/net/npcm7xx_emc.c | 18 ++++++++---------- |
9 | target/arm/translate-neon.inc.c | 87 +++++++++++++++++++++++++++++++ | 12 | 1 file changed, 8 insertions(+), 10 deletions(-) |
10 | target/arm/translate.c | 91 ++++----------------------------- | ||
11 | 3 files changed, 104 insertions(+), 80 deletions(-) | ||
12 | 13 | ||
13 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | 14 | diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c |
14 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/neon-dp.decode | 16 | --- a/hw/net/npcm7xx_emc.c |
16 | +++ b/target/arm/neon-dp.decode | 17 | +++ b/hw/net/npcm7xx_emc.c |
17 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | 18 | @@ -XXX,XX +XXX,XX @@ static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t mista_flag) |
18 | 19 | emc_set_mista(emc, mista_flag); | |
19 | VSUBW_S_3d 1111 001 0 1 . .. .... .... 0011 . 0 . 0 .... @3diff | ||
20 | VSUBW_U_3d 1111 001 1 1 . .. .... .... 0011 . 0 . 0 .... @3diff | ||
21 | + | ||
22 | + VADDHN_3d 1111 001 0 1 . .. .... .... 0100 . 0 . 0 .... @3diff | ||
23 | + VRADDHN_3d 1111 001 1 1 . .. .... .... 0100 . 0 . 0 .... @3diff | ||
24 | + | ||
25 | + VSUBHN_3d 1111 001 0 1 . .. .... .... 0110 . 0 . 0 .... @3diff | ||
26 | + VRSUBHN_3d 1111 001 1 1 . .. .... .... 0110 . 0 . 0 .... @3diff | ||
27 | ] | ||
28 | } | 20 | } |
29 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | 21 | |
30 | index XXXXXXX..XXXXXXX 100644 | 22 | +static void emc_enable_rx_and_flush(NPCM7xxEMCState *emc) |
31 | --- a/target/arm/translate-neon.inc.c | ||
32 | +++ b/target/arm/translate-neon.inc.c | ||
33 | @@ -XXX,XX +XXX,XX @@ DO_PREWIDEN(VADDW_S, s, ext, add, true) | ||
34 | DO_PREWIDEN(VADDW_U, u, extu, add, true) | ||
35 | DO_PREWIDEN(VSUBW_S, s, ext, sub, true) | ||
36 | DO_PREWIDEN(VSUBW_U, u, extu, sub, true) | ||
37 | + | ||
38 | +static bool do_narrow_3d(DisasContext *s, arg_3diff *a, | ||
39 | + NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn) | ||
40 | +{ | 23 | +{ |
41 | + /* 3-regs different lengths, narrowing (VADDHN/VSUBHN/VRADDHN/VRSUBHN) */ | 24 | + emc->rx_active = true; |
42 | + TCGv_i64 rn_64, rm_64; | 25 | + qemu_flush_queued_packets(qemu_get_queue(emc->nic)); |
43 | + TCGv_i32 rd0, rd1; | ||
44 | + | ||
45 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
46 | + return false; | ||
47 | + } | ||
48 | + | ||
49 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
50 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
51 | + ((a->vd | a->vn | a->vm) & 0x10)) { | ||
52 | + return false; | ||
53 | + } | ||
54 | + | ||
55 | + if (!opfn || !narrowfn) { | ||
56 | + /* size == 3 case, which is an entirely different insn group */ | ||
57 | + return false; | ||
58 | + } | ||
59 | + | ||
60 | + if ((a->vn | a->vm) & 1) { | ||
61 | + return false; | ||
62 | + } | ||
63 | + | ||
64 | + if (!vfp_access_check(s)) { | ||
65 | + return true; | ||
66 | + } | ||
67 | + | ||
68 | + rn_64 = tcg_temp_new_i64(); | ||
69 | + rm_64 = tcg_temp_new_i64(); | ||
70 | + rd0 = tcg_temp_new_i32(); | ||
71 | + rd1 = tcg_temp_new_i32(); | ||
72 | + | ||
73 | + neon_load_reg64(rn_64, a->vn); | ||
74 | + neon_load_reg64(rm_64, a->vm); | ||
75 | + | ||
76 | + opfn(rn_64, rn_64, rm_64); | ||
77 | + | ||
78 | + narrowfn(rd0, rn_64); | ||
79 | + | ||
80 | + neon_load_reg64(rn_64, a->vn + 1); | ||
81 | + neon_load_reg64(rm_64, a->vm + 1); | ||
82 | + | ||
83 | + opfn(rn_64, rn_64, rm_64); | ||
84 | + | ||
85 | + narrowfn(rd1, rn_64); | ||
86 | + | ||
87 | + neon_store_reg(a->vd, 0, rd0); | ||
88 | + neon_store_reg(a->vd, 1, rd1); | ||
89 | + | ||
90 | + tcg_temp_free_i64(rn_64); | ||
91 | + tcg_temp_free_i64(rm_64); | ||
92 | + | ||
93 | + return true; | ||
94 | +} | 26 | +} |
95 | + | 27 | + |
96 | +#define DO_NARROW_3D(INSN, OP, NARROWTYPE, EXTOP) \ | 28 | static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc, |
97 | + static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ | 29 | const NPCM7xxEMCTxDesc *tx_desc, |
98 | + { \ | 30 | uint32_t desc_addr) |
99 | + static NeonGenTwo64OpFn * const addfn[] = { \ | 31 | @@ -XXX,XX +XXX,XX @@ static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t len1) |
100 | + gen_helper_neon_##OP##l_u16, \ | 32 | return len; |
101 | + gen_helper_neon_##OP##l_u32, \ | ||
102 | + tcg_gen_##OP##_i64, \ | ||
103 | + NULL, \ | ||
104 | + }; \ | ||
105 | + static NeonGenNarrowFn * const narrowfn[] = { \ | ||
106 | + gen_helper_neon_##NARROWTYPE##_high_u8, \ | ||
107 | + gen_helper_neon_##NARROWTYPE##_high_u16, \ | ||
108 | + EXTOP, \ | ||
109 | + NULL, \ | ||
110 | + }; \ | ||
111 | + return do_narrow_3d(s, a, addfn[a->size], narrowfn[a->size]); \ | ||
112 | + } | ||
113 | + | ||
114 | +static void gen_narrow_round_high_u32(TCGv_i32 rd, TCGv_i64 rn) | ||
115 | +{ | ||
116 | + tcg_gen_addi_i64(rn, rn, 1u << 31); | ||
117 | + tcg_gen_extrh_i64_i32(rd, rn); | ||
118 | +} | ||
119 | + | ||
120 | +DO_NARROW_3D(VADDHN, add, narrow, tcg_gen_extrh_i64_i32) | ||
121 | +DO_NARROW_3D(VSUBHN, sub, narrow, tcg_gen_extrh_i64_i32) | ||
122 | +DO_NARROW_3D(VRADDHN, add, narrow_round, gen_narrow_round_high_u32) | ||
123 | +DO_NARROW_3D(VRSUBHN, sub, narrow_round, gen_narrow_round_high_u32) | ||
124 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
125 | index XXXXXXX..XXXXXXX 100644 | ||
126 | --- a/target/arm/translate.c | ||
127 | +++ b/target/arm/translate.c | ||
128 | @@ -XXX,XX +XXX,XX @@ static inline void gen_neon_addl(int size) | ||
129 | } | ||
130 | } | 33 | } |
131 | 34 | ||
132 | -static inline void gen_neon_subl(int size) | 35 | -static void emc_try_receive_next_packet(NPCM7xxEMCState *emc) |
133 | -{ | 36 | -{ |
134 | - switch (size) { | 37 | - if (emc_can_receive(qemu_get_queue(emc->nic))) { |
135 | - case 0: gen_helper_neon_subl_u16(CPU_V001); break; | 38 | - qemu_flush_queued_packets(qemu_get_queue(emc->nic)); |
136 | - case 1: gen_helper_neon_subl_u32(CPU_V001); break; | ||
137 | - case 2: tcg_gen_sub_i64(CPU_V001); break; | ||
138 | - default: abort(); | ||
139 | - } | 39 | - } |
140 | -} | 40 | -} |
141 | - | 41 | - |
142 | static inline void gen_neon_negl(TCGv_i64 var, int size) | 42 | static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned size) |
143 | { | 43 | { |
144 | switch (size) { | 44 | NPCM7xxEMCState *emc = opaque; |
145 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 45 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset, |
146 | op = (insn >> 8) & 0xf; | 46 | emc->regs[REG_MGSTA] |= REG_MGSTA_RXHA; |
147 | if ((insn & (1 << 6)) == 0) { | 47 | } |
148 | /* Three registers of different lengths. */ | 48 | if (value & REG_MCMDR_RXON) { |
149 | - int src1_wide; | 49 | - emc->rx_active = true; |
150 | - int src2_wide; | 50 | + emc_enable_rx_and_flush(emc); |
151 | /* undefreq: bit 0 : UNDEF if size == 0 | 51 | } else { |
152 | * bit 1 : UNDEF if size == 1 | 52 | emc_halt_rx(emc, 0); |
153 | * bit 2 : UNDEF if size == 2 | 53 | } |
154 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 54 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset, |
155 | {0, 0, 0, 7}, /* VADDW: handled by decodetree */ | 55 | break; |
156 | {0, 0, 0, 7}, /* VSUBL: handled by decodetree */ | 56 | case REG_RSDR: |
157 | {0, 0, 0, 7}, /* VSUBW: handled by decodetree */ | 57 | if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) { |
158 | - {0, 1, 1, 0}, /* VADDHN */ | 58 | - emc->rx_active = true; |
159 | + {0, 0, 0, 7}, /* VADDHN: handled by decodetree */ | 59 | - emc_try_receive_next_packet(emc); |
160 | {0, 0, 0, 0}, /* VABAL */ | 60 | + emc_enable_rx_and_flush(emc); |
161 | - {0, 1, 1, 0}, /* VSUBHN */ | 61 | } |
162 | + {0, 0, 0, 7}, /* VSUBHN: handled by decodetree */ | 62 | break; |
163 | {0, 0, 0, 0}, /* VABDL */ | 63 | case REG_MIIDA: |
164 | {0, 0, 0, 0}, /* VMLAL */ | ||
165 | {0, 0, 0, 9}, /* VQDMLAL */ | ||
166 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
167 | {0, 0, 0, 7}, /* Reserved: always UNDEF */ | ||
168 | }; | ||
169 | |||
170 | - src1_wide = neon_3reg_wide[op][1]; | ||
171 | - src2_wide = neon_3reg_wide[op][2]; | ||
172 | undefreq = neon_3reg_wide[op][3]; | ||
173 | |||
174 | if ((undefreq & (1 << size)) || | ||
175 | ((undefreq & 8) && u)) { | ||
176 | return 1; | ||
177 | } | ||
178 | - if ((src1_wide && (rn & 1)) || | ||
179 | - (src2_wide && (rm & 1)) || | ||
180 | - (!src2_wide && (rd & 1))) { | ||
181 | + if (rd & 1) { | ||
182 | return 1; | ||
183 | } | ||
184 | |||
185 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
186 | /* Avoid overlapping operands. Wide source operands are | ||
187 | always aligned so will never overlap with wide | ||
188 | destinations in problematic ways. */ | ||
189 | - if (rd == rm && !src2_wide) { | ||
190 | + if (rd == rm) { | ||
191 | tmp = neon_load_reg(rm, 1); | ||
192 | neon_store_scratch(2, tmp); | ||
193 | - } else if (rd == rn && !src1_wide) { | ||
194 | + } else if (rd == rn) { | ||
195 | tmp = neon_load_reg(rn, 1); | ||
196 | neon_store_scratch(2, tmp); | ||
197 | } | ||
198 | tmp3 = NULL; | ||
199 | for (pass = 0; pass < 2; pass++) { | ||
200 | - if (src1_wide) { | ||
201 | - neon_load_reg64(cpu_V0, rn + pass); | ||
202 | - tmp = NULL; | ||
203 | + if (pass == 1 && rd == rn) { | ||
204 | + tmp = neon_load_scratch(2); | ||
205 | } else { | ||
206 | - if (pass == 1 && rd == rn) { | ||
207 | - tmp = neon_load_scratch(2); | ||
208 | - } else { | ||
209 | - tmp = neon_load_reg(rn, pass); | ||
210 | - } | ||
211 | + tmp = neon_load_reg(rn, pass); | ||
212 | } | ||
213 | - if (src2_wide) { | ||
214 | - neon_load_reg64(cpu_V1, rm + pass); | ||
215 | - tmp2 = NULL; | ||
216 | + if (pass == 1 && rd == rm) { | ||
217 | + tmp2 = neon_load_scratch(2); | ||
218 | } else { | ||
219 | - if (pass == 1 && rd == rm) { | ||
220 | - tmp2 = neon_load_scratch(2); | ||
221 | - } else { | ||
222 | - tmp2 = neon_load_reg(rm, pass); | ||
223 | - } | ||
224 | + tmp2 = neon_load_reg(rm, pass); | ||
225 | } | ||
226 | switch (op) { | ||
227 | - case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */ | ||
228 | - gen_neon_addl(size); | ||
229 | - break; | ||
230 | - case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */ | ||
231 | - gen_neon_subl(size); | ||
232 | - break; | ||
233 | case 5: case 7: /* VABAL, VABDL */ | ||
234 | switch ((size << 1) | u) { | ||
235 | case 0: | ||
236 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
237 | abort(); | ||
238 | } | ||
239 | neon_store_reg64(cpu_V0, rd + pass); | ||
240 | - } else if (op == 4 || op == 6) { | ||
241 | - /* Narrowing operation. */ | ||
242 | - tmp = tcg_temp_new_i32(); | ||
243 | - if (!u) { | ||
244 | - switch (size) { | ||
245 | - case 0: | ||
246 | - gen_helper_neon_narrow_high_u8(tmp, cpu_V0); | ||
247 | - break; | ||
248 | - case 1: | ||
249 | - gen_helper_neon_narrow_high_u16(tmp, cpu_V0); | ||
250 | - break; | ||
251 | - case 2: | ||
252 | - tcg_gen_extrh_i64_i32(tmp, cpu_V0); | ||
253 | - break; | ||
254 | - default: abort(); | ||
255 | - } | ||
256 | - } else { | ||
257 | - switch (size) { | ||
258 | - case 0: | ||
259 | - gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0); | ||
260 | - break; | ||
261 | - case 1: | ||
262 | - gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0); | ||
263 | - break; | ||
264 | - case 2: | ||
265 | - tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31); | ||
266 | - tcg_gen_extrh_i64_i32(tmp, cpu_V0); | ||
267 | - break; | ||
268 | - default: abort(); | ||
269 | - } | ||
270 | - } | ||
271 | - if (pass == 0) { | ||
272 | - tmp3 = tmp; | ||
273 | - } else { | ||
274 | - neon_store_reg(rd, 0, tmp3); | ||
275 | - neon_store_reg(rd, 1, tmp); | ||
276 | - } | ||
277 | } else { | ||
278 | /* Write back the result. */ | ||
279 | neon_store_reg64(cpu_V0, rd + pass); | ||
280 | -- | 64 | -- |
281 | 2.20.1 | 65 | 2.25.1 |
282 | 66 | ||
283 | 67 | diff view generated by jsdifflib |
1 | Convert the "pre-widening" insns VADDL, VSUBL, VADDW and VSUBW | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | in the Neon 3-registers-different-lengths group to decodetree. | ||
3 | These insns work by widening one or both inputs to double their | ||
4 | size, performing an add or subtract at the doubled size and | ||
5 | then storing the double-size result. | ||
6 | 2 | ||
7 | As usual, rather than copying the loop of the original decoder | 3 | When a virtio-iommu is instantiated, describe it using the ACPI VIOT |
8 | (which needs awkward code to avoid problems when source and | 4 | table. |
9 | destination registers overlap) we just unroll the two passes. | ||
10 | 5 | ||
6 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
7 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
8 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
9 | Message-id: 20211210170415.583179-2-jean-philippe@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | --- | 11 | --- |
14 | target/arm/neon-dp.decode | 43 +++++++++++++ | 12 | hw/arm/virt-acpi-build.c | 7 +++++++ |
15 | target/arm/translate-neon.inc.c | 104 ++++++++++++++++++++++++++++++++ | 13 | hw/arm/Kconfig | 1 + |
16 | target/arm/translate.c | 16 ++--- | 14 | 2 files changed, 8 insertions(+) |
17 | 3 files changed, 151 insertions(+), 12 deletions(-) | ||
18 | 15 | ||
19 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | 16 | diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c |
20 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/neon-dp.decode | 18 | --- a/hw/arm/virt-acpi-build.c |
22 | +++ b/target/arm/neon-dp.decode | 19 | +++ b/hw/arm/virt-acpi-build.c |
23 | @@ -XXX,XX +XXX,XX @@ VCVT_FU_2sh 1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt | 20 | @@ -XXX,XX +XXX,XX @@ |
24 | # So we have a single decode line and check the cmode/op in the | 21 | #include "kvm_arm.h" |
25 | # trans function. | 22 | #include "migration/vmstate.h" |
26 | Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | 23 | #include "hw/acpi/ghes.h" |
27 | + | 24 | +#include "hw/acpi/viot.h" |
28 | +###################################################################### | 25 | |
29 | +# Within the "two registers, or three registers of different lengths" | 26 | #define ARM_SPI_BASE 32 |
30 | +# grouping ([23,4]=0b10), bits [21:20] are either part of the opcode | 27 | |
31 | +# decode: 0b11 for VEXT, two-reg-misc, VTBL, and duplicate-scalar; | 28 | @@ -XXX,XX +XXX,XX @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) |
32 | +# or they are a size field for the three-reg-different-lengths and | ||
33 | +# two-reg-and-scalar insn groups (where size cannot be 0b11). This | ||
34 | +# is slightly awkward for decodetree: we handle it with this | ||
35 | +# non-exclusive group which contains within it two exclusive groups: | ||
36 | +# one for the size=0b11 patterns, and one for the size-not-0b11 | ||
37 | +# patterns. This allows us to check that none of the insns within | ||
38 | +# each subgroup accidentally overlap each other. Note that all the | ||
39 | +# trans functions for the size-not-0b11 patterns must check and | ||
40 | +# return false for size==3. | ||
41 | +###################################################################### | ||
42 | +{ | ||
43 | + # 0b11 subgroup will go here | ||
44 | + | ||
45 | + # Subgroup for size != 0b11 | ||
46 | + [ | ||
47 | + ################################################################## | ||
48 | + # 3-reg-different-length grouping: | ||
49 | + # 1111 001 U 1 D sz!=11 Vn:4 Vd:4 opc:4 N 0 M 0 Vm:4 | ||
50 | + ################################################################## | ||
51 | + | ||
52 | + &3diff vm vn vd size | ||
53 | + | ||
54 | + @3diff .... ... . . . size:2 .... .... .... . . . . .... \ | ||
55 | + &3diff vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
56 | + | ||
57 | + VADDL_S_3d 1111 001 0 1 . .. .... .... 0000 . 0 . 0 .... @3diff | ||
58 | + VADDL_U_3d 1111 001 1 1 . .. .... .... 0000 . 0 . 0 .... @3diff | ||
59 | + | ||
60 | + VADDW_S_3d 1111 001 0 1 . .. .... .... 0001 . 0 . 0 .... @3diff | ||
61 | + VADDW_U_3d 1111 001 1 1 . .. .... .... 0001 . 0 . 0 .... @3diff | ||
62 | + | ||
63 | + VSUBL_S_3d 1111 001 0 1 . .. .... .... 0010 . 0 . 0 .... @3diff | ||
64 | + VSUBL_U_3d 1111 001 1 1 . .. .... .... 0010 . 0 . 0 .... @3diff | ||
65 | + | ||
66 | + VSUBW_S_3d 1111 001 0 1 . .. .... .... 0011 . 0 . 0 .... @3diff | ||
67 | + VSUBW_U_3d 1111 001 1 1 . .. .... .... 0011 . 0 . 0 .... @3diff | ||
68 | + ] | ||
69 | +} | ||
70 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
71 | index XXXXXXX..XXXXXXX 100644 | ||
72 | --- a/target/arm/translate-neon.inc.c | ||
73 | +++ b/target/arm/translate-neon.inc.c | ||
74 | @@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a) | ||
75 | } | 29 | } |
76 | return do_1reg_imm(s, a, fn); | 30 | #endif |
77 | } | 31 | |
78 | + | 32 | + if (vms->iommu == VIRT_IOMMU_VIRTIO) { |
79 | +static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | 33 | + acpi_add_table(table_offsets, tables_blob); |
80 | + NeonGenWidenFn *widenfn, | 34 | + build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf, |
81 | + NeonGenTwo64OpFn *opfn, | 35 | + vms->oem_id, vms->oem_table_id); |
82 | + bool src1_wide) | ||
83 | +{ | ||
84 | + /* 3-regs different lengths, prewidening case (VADDL/VSUBL/VAADW/VSUBW) */ | ||
85 | + TCGv_i64 rn0_64, rn1_64, rm_64; | ||
86 | + TCGv_i32 rm; | ||
87 | + | ||
88 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
89 | + return false; | ||
90 | + } | 36 | + } |
91 | + | 37 | + |
92 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | 38 | /* XSDT is pointed to by RSDP */ |
93 | + if (!dc_isar_feature(aa32_simd_r32, s) && | 39 | xsdt = tables_blob->len; |
94 | + ((a->vd | a->vn | a->vm) & 0x10)) { | 40 | build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, |
95 | + return false; | 41 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig |
96 | + } | ||
97 | + | ||
98 | + if (!widenfn || !opfn) { | ||
99 | + /* size == 3 case, which is an entirely different insn group */ | ||
100 | + return false; | ||
101 | + } | ||
102 | + | ||
103 | + if ((a->vd & 1) || (src1_wide && (a->vn & 1))) { | ||
104 | + return false; | ||
105 | + } | ||
106 | + | ||
107 | + if (!vfp_access_check(s)) { | ||
108 | + return true; | ||
109 | + } | ||
110 | + | ||
111 | + rn0_64 = tcg_temp_new_i64(); | ||
112 | + rn1_64 = tcg_temp_new_i64(); | ||
113 | + rm_64 = tcg_temp_new_i64(); | ||
114 | + | ||
115 | + if (src1_wide) { | ||
116 | + neon_load_reg64(rn0_64, a->vn); | ||
117 | + } else { | ||
118 | + TCGv_i32 tmp = neon_load_reg(a->vn, 0); | ||
119 | + widenfn(rn0_64, tmp); | ||
120 | + tcg_temp_free_i32(tmp); | ||
121 | + } | ||
122 | + rm = neon_load_reg(a->vm, 0); | ||
123 | + | ||
124 | + widenfn(rm_64, rm); | ||
125 | + tcg_temp_free_i32(rm); | ||
126 | + opfn(rn0_64, rn0_64, rm_64); | ||
127 | + | ||
128 | + /* | ||
129 | + * Load second pass inputs before storing the first pass result, to | ||
130 | + * avoid incorrect results if a narrow input overlaps with the result. | ||
131 | + */ | ||
132 | + if (src1_wide) { | ||
133 | + neon_load_reg64(rn1_64, a->vn + 1); | ||
134 | + } else { | ||
135 | + TCGv_i32 tmp = neon_load_reg(a->vn, 1); | ||
136 | + widenfn(rn1_64, tmp); | ||
137 | + tcg_temp_free_i32(tmp); | ||
138 | + } | ||
139 | + rm = neon_load_reg(a->vm, 1); | ||
140 | + | ||
141 | + neon_store_reg64(rn0_64, a->vd); | ||
142 | + | ||
143 | + widenfn(rm_64, rm); | ||
144 | + tcg_temp_free_i32(rm); | ||
145 | + opfn(rn1_64, rn1_64, rm_64); | ||
146 | + neon_store_reg64(rn1_64, a->vd + 1); | ||
147 | + | ||
148 | + tcg_temp_free_i64(rn0_64); | ||
149 | + tcg_temp_free_i64(rn1_64); | ||
150 | + tcg_temp_free_i64(rm_64); | ||
151 | + | ||
152 | + return true; | ||
153 | +} | ||
154 | + | ||
155 | +#define DO_PREWIDEN(INSN, S, EXT, OP, SRC1WIDE) \ | ||
156 | + static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ | ||
157 | + { \ | ||
158 | + static NeonGenWidenFn * const widenfn[] = { \ | ||
159 | + gen_helper_neon_widen_##S##8, \ | ||
160 | + gen_helper_neon_widen_##S##16, \ | ||
161 | + tcg_gen_##EXT##_i32_i64, \ | ||
162 | + NULL, \ | ||
163 | + }; \ | ||
164 | + static NeonGenTwo64OpFn * const addfn[] = { \ | ||
165 | + gen_helper_neon_##OP##l_u16, \ | ||
166 | + gen_helper_neon_##OP##l_u32, \ | ||
167 | + tcg_gen_##OP##_i64, \ | ||
168 | + NULL, \ | ||
169 | + }; \ | ||
170 | + return do_prewiden_3d(s, a, widenfn[a->size], \ | ||
171 | + addfn[a->size], SRC1WIDE); \ | ||
172 | + } | ||
173 | + | ||
174 | +DO_PREWIDEN(VADDL_S, s, ext, add, false) | ||
175 | +DO_PREWIDEN(VADDL_U, u, extu, add, false) | ||
176 | +DO_PREWIDEN(VSUBL_S, s, ext, sub, false) | ||
177 | +DO_PREWIDEN(VSUBL_U, u, extu, sub, false) | ||
178 | +DO_PREWIDEN(VADDW_S, s, ext, add, true) | ||
179 | +DO_PREWIDEN(VADDW_U, u, extu, add, true) | ||
180 | +DO_PREWIDEN(VSUBW_S, s, ext, sub, true) | ||
181 | +DO_PREWIDEN(VSUBW_U, u, extu, sub, true) | ||
182 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
183 | index XXXXXXX..XXXXXXX 100644 | 42 | index XXXXXXX..XXXXXXX 100644 |
184 | --- a/target/arm/translate.c | 43 | --- a/hw/arm/Kconfig |
185 | +++ b/target/arm/translate.c | 44 | +++ b/hw/arm/Kconfig |
186 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 45 | @@ -XXX,XX +XXX,XX @@ config ARM_VIRT |
187 | /* Three registers of different lengths. */ | 46 | select DIMM |
188 | int src1_wide; | 47 | select ACPI_HW_REDUCED |
189 | int src2_wide; | 48 | select ACPI_APEI |
190 | - int prewiden; | 49 | + select ACPI_VIOT |
191 | /* undefreq: bit 0 : UNDEF if size == 0 | 50 | |
192 | * bit 1 : UNDEF if size == 1 | 51 | config CHEETAH |
193 | * bit 2 : UNDEF if size == 2 | 52 | bool |
194 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
195 | int undefreq; | ||
196 | /* prewiden, src1_wide, src2_wide, undefreq */ | ||
197 | static const int neon_3reg_wide[16][4] = { | ||
198 | - {1, 0, 0, 0}, /* VADDL */ | ||
199 | - {1, 1, 0, 0}, /* VADDW */ | ||
200 | - {1, 0, 0, 0}, /* VSUBL */ | ||
201 | - {1, 1, 0, 0}, /* VSUBW */ | ||
202 | + {0, 0, 0, 7}, /* VADDL: handled by decodetree */ | ||
203 | + {0, 0, 0, 7}, /* VADDW: handled by decodetree */ | ||
204 | + {0, 0, 0, 7}, /* VSUBL: handled by decodetree */ | ||
205 | + {0, 0, 0, 7}, /* VSUBW: handled by decodetree */ | ||
206 | {0, 1, 1, 0}, /* VADDHN */ | ||
207 | {0, 0, 0, 0}, /* VABAL */ | ||
208 | {0, 1, 1, 0}, /* VSUBHN */ | ||
209 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
210 | {0, 0, 0, 7}, /* Reserved: always UNDEF */ | ||
211 | }; | ||
212 | |||
213 | - prewiden = neon_3reg_wide[op][0]; | ||
214 | src1_wide = neon_3reg_wide[op][1]; | ||
215 | src2_wide = neon_3reg_wide[op][2]; | ||
216 | undefreq = neon_3reg_wide[op][3]; | ||
217 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
218 | } else { | ||
219 | tmp = neon_load_reg(rn, pass); | ||
220 | } | ||
221 | - if (prewiden) { | ||
222 | - gen_neon_widen(cpu_V0, tmp, size, u); | ||
223 | - } | ||
224 | } | ||
225 | if (src2_wide) { | ||
226 | neon_load_reg64(cpu_V1, rm + pass); | ||
227 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
228 | } else { | ||
229 | tmp2 = neon_load_reg(rm, pass); | ||
230 | } | ||
231 | - if (prewiden) { | ||
232 | - gen_neon_widen(cpu_V1, tmp2, size, u); | ||
233 | - } | ||
234 | } | ||
235 | switch (op) { | ||
236 | case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */ | ||
237 | -- | 53 | -- |
238 | 2.20.1 | 54 | 2.25.1 |
239 | 55 | ||
240 | 56 | diff view generated by jsdifflib |
1 | From: fangying <fangying1@huawei.com> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Virtual time adjustment was implemented for virt-5.0 machine type, | 3 | virtio-iommu is now supported with ACPI VIOT as well as device tree. |
4 | but the cpu property was enabled only for host-passthrough and max | 4 | Remove the restriction that prevents from instantiating a virtio-iommu |
5 | cpu model. Let's add it for any KVM arm cpu which has the generic | 5 | device under ACPI. |
6 | timer feature enabled. | ||
7 | 6 | ||
8 | Signed-off-by: Ying Fang <fangying1@huawei.com> | 7 | Acked-by: Igor Mammedov <imammedo@redhat.com> |
9 | Reviewed-by: Andrew Jones <drjones@redhat.com> | 8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
10 | Message-id: 20200608121243.2076-1-fangying1@huawei.com | 9 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> |
11 | [PMM: minor commit message tweak, removed inaccurate | 10 | Message-id: 20211210170415.583179-3-jean-philippe@linaro.org |
12 | suggested-by tag] | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 12 | --- |
15 | target/arm/cpu.c | 6 ++++-- | 13 | hw/arm/virt.c | 10 ++-------- |
16 | target/arm/cpu64.c | 1 - | 14 | hw/virtio/virtio-iommu-pci.c | 12 ++---------- |
17 | target/arm/kvm.c | 21 +++++++++++---------- | 15 | 2 files changed, 4 insertions(+), 18 deletions(-) |
18 | 3 files changed, 15 insertions(+), 13 deletions(-) | ||
19 | 16 | ||
20 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 17 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
21 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/target/arm/cpu.c | 19 | --- a/hw/arm/virt.c |
23 | +++ b/target/arm/cpu.c | 20 | +++ b/hw/arm/virt.c |
24 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj) | 21 | @@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, |
25 | if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { | 22 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
26 | qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); | 23 | |
24 | if (device_is_dynamic_sysbus(mc, dev) || | ||
25 | - (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) { | ||
26 | + object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || | ||
27 | + object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { | ||
28 | return HOTPLUG_HANDLER(machine); | ||
27 | } | 29 | } |
28 | + | 30 | - if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { |
29 | + if (kvm_enabled()) { | 31 | - VirtMachineState *vms = VIRT_MACHINE(machine); |
30 | + kvm_arm_add_vcpu_properties(obj); | 32 | - |
31 | + } | 33 | - if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) { |
34 | - return HOTPLUG_HANDLER(machine); | ||
35 | - } | ||
36 | - } | ||
37 | return NULL; | ||
32 | } | 38 | } |
33 | 39 | ||
34 | static void arm_cpu_finalizefn(Object *obj) | 40 | diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c |
35 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | 41 | index XXXXXXX..XXXXXXX 100644 |
36 | 42 | --- a/hw/virtio/virtio-iommu-pci.c | |
37 | if (kvm_enabled()) { | 43 | +++ b/hw/virtio/virtio-iommu-pci.c |
38 | kvm_arm_set_cpu_features_from_host(cpu); | 44 | @@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) |
39 | - kvm_arm_add_vcpu_properties(obj); | 45 | VirtIOIOMMU *s = VIRTIO_IOMMU(vdev); |
40 | } else { | 46 | |
41 | cortex_a15_initfn(obj); | 47 | if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) { |
42 | 48 | - MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); | |
43 | @@ -XXX,XX +XXX,XX @@ static void arm_host_initfn(Object *obj) | 49 | - |
44 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | 50 | - error_setg(errp, |
45 | aarch64_add_sve_properties(obj); | 51 | - "%s machine fails to create iommu-map device tree bindings", |
52 | - mc->name); | ||
53 | - error_append_hint(errp, | ||
54 | - "Check your machine implements a hotplug handler " | ||
55 | - "for the virtio-iommu-pci device\n"); | ||
56 | - error_append_hint(errp, "Check the guest is booted without FW or with " | ||
57 | - "-no-acpi\n"); | ||
58 | + error_setg(errp, "Check your machine implements a hotplug handler " | ||
59 | + "for the virtio-iommu-pci device"); | ||
60 | return; | ||
46 | } | 61 | } |
47 | - kvm_arm_add_vcpu_properties(obj); | 62 | for (int i = 0; i < s->nb_reserved_regions; i++) { |
48 | arm_cpu_post_init(obj); | ||
49 | } | ||
50 | |||
51 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
52 | index XXXXXXX..XXXXXXX 100644 | ||
53 | --- a/target/arm/cpu64.c | ||
54 | +++ b/target/arm/cpu64.c | ||
55 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
56 | |||
57 | if (kvm_enabled()) { | ||
58 | kvm_arm_set_cpu_features_from_host(cpu); | ||
59 | - kvm_arm_add_vcpu_properties(obj); | ||
60 | } else { | ||
61 | uint64_t t; | ||
62 | uint32_t u; | ||
63 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | ||
64 | index XXXXXXX..XXXXXXX 100644 | ||
65 | --- a/target/arm/kvm.c | ||
66 | +++ b/target/arm/kvm.c | ||
67 | @@ -XXX,XX +XXX,XX @@ static void kvm_no_adjvtime_set(Object *obj, bool value, Error **errp) | ||
68 | /* KVM VCPU properties should be prefixed with "kvm-". */ | ||
69 | void kvm_arm_add_vcpu_properties(Object *obj) | ||
70 | { | ||
71 | - if (!kvm_enabled()) { | ||
72 | - return; | ||
73 | - } | ||
74 | + ARMCPU *cpu = ARM_CPU(obj); | ||
75 | + CPUARMState *env = &cpu->env; | ||
76 | |||
77 | - ARM_CPU(obj)->kvm_adjvtime = true; | ||
78 | - object_property_add_bool(obj, "kvm-no-adjvtime", kvm_no_adjvtime_get, | ||
79 | - kvm_no_adjvtime_set); | ||
80 | - object_property_set_description(obj, "kvm-no-adjvtime", | ||
81 | - "Set on to disable the adjustment of " | ||
82 | - "the virtual counter. VM stopped time " | ||
83 | - "will be counted."); | ||
84 | + if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { | ||
85 | + cpu->kvm_adjvtime = true; | ||
86 | + object_property_add_bool(obj, "kvm-no-adjvtime", kvm_no_adjvtime_get, | ||
87 | + kvm_no_adjvtime_set); | ||
88 | + object_property_set_description(obj, "kvm-no-adjvtime", | ||
89 | + "Set on to disable the adjustment of " | ||
90 | + "the virtual counter. VM stopped time " | ||
91 | + "will be counted."); | ||
92 | + } | ||
93 | } | ||
94 | |||
95 | bool kvm_arm_pmu_supported(CPUState *cpu) | ||
96 | -- | 63 | -- |
97 | 2.20.1 | 64 | 2.25.1 |
98 | 65 | ||
99 | 66 | diff view generated by jsdifflib |
1 | From: Guenter Roeck <linux@roeck-us.net> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Set vendor property to IMX to enable IMX specific functionality | 3 | We do not support instantiating multiple IOMMUs. Before adding a |
4 | in sdhci code. | 4 | virtio-iommu, check that no other IOMMU is present. This will detect |
5 | both "iommu=smmuv3" machine parameter and another virtio-iommu instance. | ||
5 | 6 | ||
6 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 7 | Fixes: 70e89132c9 ("hw/arm/virt: Add the virtio-iommu device tree mappings") |
7 | Signed-off-by: Guenter Roeck <linux@roeck-us.net> | 8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 9 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> |
9 | Message-id: 20200603145258.195920-3-linux@roeck-us.net | 10 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> |
11 | Message-id: 20211210170415.583179-4-jean-philippe@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 13 | --- |
12 | hw/arm/fsl-imx25.c | 6 ++++++ | 14 | hw/arm/virt.c | 5 +++++ |
13 | hw/arm/fsl-imx6.c | 6 ++++++ | 15 | 1 file changed, 5 insertions(+) |
14 | hw/arm/fsl-imx6ul.c | 2 ++ | ||
15 | hw/arm/fsl-imx7.c | 2 ++ | ||
16 | 4 files changed, 16 insertions(+) | ||
17 | 16 | ||
18 | diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c | 17 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
19 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/hw/arm/fsl-imx25.c | 19 | --- a/hw/arm/virt.c |
21 | +++ b/hw/arm/fsl-imx25.c | 20 | +++ b/hw/arm/virt.c |
22 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) | 21 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, |
23 | &err); | 22 | hwaddr db_start = 0, db_end = 0; |
24 | object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES, | 23 | char *resv_prop_str; |
25 | "capareg", &err); | 24 | |
26 | + object_property_set_uint(OBJECT(&s->esdhc[i]), SDHCI_VENDOR_IMX, | 25 | + if (vms->iommu != VIRT_IOMMU_NONE) { |
27 | + "vendor", &err); | 26 | + error_setg(errp, "virt machine does not support multiple IOMMUs"); |
28 | + if (err) { | ||
29 | + error_propagate(errp, err); | ||
30 | + return; | 27 | + return; |
31 | + } | 28 | + } |
32 | object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err); | 29 | + |
33 | if (err) { | 30 | switch (vms->msi_controller) { |
34 | error_propagate(errp, err); | 31 | case VIRT_MSI_CTRL_NONE: |
35 | diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c | 32 | return; |
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/hw/arm/fsl-imx6.c | ||
38 | +++ b/hw/arm/fsl-imx6.c | ||
39 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) | ||
40 | &err); | ||
41 | object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES, | ||
42 | "capareg", &err); | ||
43 | + object_property_set_uint(OBJECT(&s->esdhc[i]), SDHCI_VENDOR_IMX, | ||
44 | + "vendor", &err); | ||
45 | + if (err) { | ||
46 | + error_propagate(errp, err); | ||
47 | + return; | ||
48 | + } | ||
49 | object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err); | ||
50 | if (err) { | ||
51 | error_propagate(errp, err); | ||
52 | diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/hw/arm/fsl-imx6ul.c | ||
55 | +++ b/hw/arm/fsl-imx6ul.c | ||
56 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
57 | FSL_IMX6UL_USDHC2_IRQ, | ||
58 | }; | ||
59 | |||
60 | + object_property_set_uint(OBJECT(&s->usdhc[i]), SDHCI_VENDOR_IMX, | ||
61 | + "vendor", &error_abort); | ||
62 | object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized", | ||
63 | &error_abort); | ||
64 | |||
65 | diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c | ||
66 | index XXXXXXX..XXXXXXX 100644 | ||
67 | --- a/hw/arm/fsl-imx7.c | ||
68 | +++ b/hw/arm/fsl-imx7.c | ||
69 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
70 | FSL_IMX7_USDHC3_IRQ, | ||
71 | }; | ||
72 | |||
73 | + object_property_set_uint(OBJECT(&s->usdhc[i]), SDHCI_VENDOR_IMX, | ||
74 | + "vendor", &error_abort); | ||
75 | object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized", | ||
76 | &error_abort); | ||
77 | |||
78 | -- | 33 | -- |
79 | 2.20.1 | 34 | 2.25.1 |
80 | 35 | ||
81 | 36 | diff view generated by jsdifflib |
1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Some bits of the CCM registers are non writable. | 3 | To propagate errors to the caller of the pre_plug callback, use the |
4 | object_poperty_set*() functions directly instead of the qdev_prop_set*() | ||
5 | helpers. | ||
4 | 6 | ||
5 | This was left undone in the initial commit (all bits of registers were | 7 | Suggested-by: Igor Mammedov <imammedo@redhat.com> |
6 | writable). | 8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
7 | 9 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | |
8 | This patch adds the required code to protect the non writable bits. | 10 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> |
9 | 11 | Message-id: 20211210170415.583179-5-jean-philippe@linaro.org | |
10 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
11 | Message-id: 20200608133508.550046-1-jcd@tribudubois.net | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 13 | --- |
15 | hw/misc/imx6ul_ccm.c | 76 ++++++++++++++++++++++++++++++++++++-------- | 14 | hw/arm/virt.c | 5 +++-- |
16 | 1 file changed, 63 insertions(+), 13 deletions(-) | 15 | 1 file changed, 3 insertions(+), 2 deletions(-) |
17 | 16 | ||
18 | diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c | 17 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
19 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/hw/misc/imx6ul_ccm.c | 19 | --- a/hw/arm/virt.c |
21 | +++ b/hw/misc/imx6ul_ccm.c | 20 | +++ b/hw/arm/virt.c |
22 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, |
23 | 22 | db_start, db_end, | |
24 | #include "trace.h" | 23 | VIRTIO_IOMMU_RESV_MEM_T_MSI); |
25 | 24 | ||
26 | +static const uint32_t ccm_mask[CCM_MAX] = { | 25 | - qdev_prop_set_uint32(dev, "len-reserved-regions", 1); |
27 | + [CCM_CCR] = 0xf01fef80, | 26 | - qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str); |
28 | + [CCM_CCDR] = 0xfffeffff, | 27 | + object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); |
29 | + [CCM_CSR] = 0xffffffff, | 28 | + object_property_set_str(OBJECT(dev), "reserved-regions[0]", |
30 | + [CCM_CCSR] = 0xfffffef2, | 29 | + resv_prop_str, errp); |
31 | + [CCM_CACRR] = 0xfffffff8, | 30 | g_free(resv_prop_str); |
32 | + [CCM_CBCDR] = 0xc1f8e000, | ||
33 | + [CCM_CBCMR] = 0xfc03cfff, | ||
34 | + [CCM_CSCMR1] = 0x80700000, | ||
35 | + [CCM_CSCMR2] = 0xe01ff003, | ||
36 | + [CCM_CSCDR1] = 0xfe00c780, | ||
37 | + [CCM_CS1CDR] = 0xfe00fe00, | ||
38 | + [CCM_CS2CDR] = 0xf8007000, | ||
39 | + [CCM_CDCDR] = 0xf00fffff, | ||
40 | + [CCM_CHSCCDR] = 0xfffc01ff, | ||
41 | + [CCM_CSCDR2] = 0xfe0001ff, | ||
42 | + [CCM_CSCDR3] = 0xffffc1ff, | ||
43 | + [CCM_CDHIPR] = 0xffffffff, | ||
44 | + [CCM_CTOR] = 0x00000000, | ||
45 | + [CCM_CLPCR] = 0xf39ff01c, | ||
46 | + [CCM_CISR] = 0xfb85ffbe, | ||
47 | + [CCM_CIMR] = 0xfb85ffbf, | ||
48 | + [CCM_CCOSR] = 0xfe00fe00, | ||
49 | + [CCM_CGPR] = 0xfffc3fea, | ||
50 | + [CCM_CCGR0] = 0x00000000, | ||
51 | + [CCM_CCGR1] = 0x00000000, | ||
52 | + [CCM_CCGR2] = 0x00000000, | ||
53 | + [CCM_CCGR3] = 0x00000000, | ||
54 | + [CCM_CCGR4] = 0x00000000, | ||
55 | + [CCM_CCGR5] = 0x00000000, | ||
56 | + [CCM_CCGR6] = 0x00000000, | ||
57 | + [CCM_CMEOR] = 0xafffff1f, | ||
58 | +}; | ||
59 | + | ||
60 | +static const uint32_t analog_mask[CCM_ANALOG_MAX] = { | ||
61 | + [CCM_ANALOG_PLL_ARM] = 0xfff60f80, | ||
62 | + [CCM_ANALOG_PLL_USB1] = 0xfffe0fbc, | ||
63 | + [CCM_ANALOG_PLL_USB2] = 0xfffe0fbc, | ||
64 | + [CCM_ANALOG_PLL_SYS] = 0xfffa0ffe, | ||
65 | + [CCM_ANALOG_PLL_SYS_SS] = 0x00000000, | ||
66 | + [CCM_ANALOG_PLL_SYS_NUM] = 0xc0000000, | ||
67 | + [CCM_ANALOG_PLL_SYS_DENOM] = 0xc0000000, | ||
68 | + [CCM_ANALOG_PLL_AUDIO] = 0xffe20f80, | ||
69 | + [CCM_ANALOG_PLL_AUDIO_NUM] = 0xc0000000, | ||
70 | + [CCM_ANALOG_PLL_AUDIO_DENOM] = 0xc0000000, | ||
71 | + [CCM_ANALOG_PLL_VIDEO] = 0xffe20f80, | ||
72 | + [CCM_ANALOG_PLL_VIDEO_NUM] = 0xc0000000, | ||
73 | + [CCM_ANALOG_PLL_VIDEO_DENOM] = 0xc0000000, | ||
74 | + [CCM_ANALOG_PLL_ENET] = 0xffc20ff0, | ||
75 | + [CCM_ANALOG_PFD_480] = 0x40404040, | ||
76 | + [CCM_ANALOG_PFD_528] = 0x40404040, | ||
77 | + [PMU_MISC0] = 0x01fe8306, | ||
78 | + [PMU_MISC1] = 0x07fcede0, | ||
79 | + [PMU_MISC2] = 0x005f5f5f, | ||
80 | +}; | ||
81 | + | ||
82 | static const char *imx6ul_ccm_reg_name(uint32_t reg) | ||
83 | { | ||
84 | static char unknown[20]; | ||
85 | @@ -XXX,XX +XXX,XX @@ static void imx6ul_ccm_write(void *opaque, hwaddr offset, uint64_t value, | ||
86 | |||
87 | trace_ccm_write_reg(imx6ul_ccm_reg_name(index), (uint32_t)value); | ||
88 | |||
89 | - /* | ||
90 | - * We will do a better implementation later. In particular some bits | ||
91 | - * cannot be written to. | ||
92 | - */ | ||
93 | - s->ccm[index] = (uint32_t)value; | ||
94 | + s->ccm[index] = (s->ccm[index] & ccm_mask[index]) | | ||
95 | + ((uint32_t)value & ~ccm_mask[index]); | ||
96 | } | ||
97 | |||
98 | static uint64_t imx6ul_analog_read(void *opaque, hwaddr offset, unsigned size) | ||
99 | @@ -XXX,XX +XXX,XX @@ static void imx6ul_analog_write(void *opaque, hwaddr offset, uint64_t value, | ||
100 | * the REG_NAME register. So we change the value of the | ||
101 | * REG_NAME register, setting bits passed in the value. | ||
102 | */ | ||
103 | - s->analog[index - 1] |= value; | ||
104 | + s->analog[index - 1] |= (value & ~analog_mask[index - 1]); | ||
105 | break; | ||
106 | case CCM_ANALOG_PLL_ARM_CLR: | ||
107 | case CCM_ANALOG_PLL_USB1_CLR: | ||
108 | @@ -XXX,XX +XXX,XX @@ static void imx6ul_analog_write(void *opaque, hwaddr offset, uint64_t value, | ||
109 | * the REG_NAME register. So we change the value of the | ||
110 | * REG_NAME register, unsetting bits passed in the value. | ||
111 | */ | ||
112 | - s->analog[index - 2] &= ~value; | ||
113 | + s->analog[index - 2] &= ~(value & ~analog_mask[index - 2]); | ||
114 | break; | ||
115 | case CCM_ANALOG_PLL_ARM_TOG: | ||
116 | case CCM_ANALOG_PLL_USB1_TOG: | ||
117 | @@ -XXX,XX +XXX,XX @@ static void imx6ul_analog_write(void *opaque, hwaddr offset, uint64_t value, | ||
118 | * the REG_NAME register. So we change the value of the | ||
119 | * REG_NAME register, toggling bits passed in the value. | ||
120 | */ | ||
121 | - s->analog[index - 3] ^= value; | ||
122 | + s->analog[index - 3] ^= (value & ~analog_mask[index - 3]); | ||
123 | break; | ||
124 | default: | ||
125 | - /* | ||
126 | - * We will do a better implementation later. In particular some bits | ||
127 | - * cannot be written to. | ||
128 | - */ | ||
129 | - s->analog[index] = value; | ||
130 | + s->analog[index] = (s->analog[index] & analog_mask[index]) | | ||
131 | + (value & ~analog_mask[index]); | ||
132 | break; | ||
133 | } | 31 | } |
134 | } | 32 | } |
135 | -- | 33 | -- |
136 | 2.20.1 | 34 | 2.25.1 |
137 | 35 | ||
138 | 36 | diff view generated by jsdifflib |
1 | From: Guenter Roeck <linux@roeck-us.net> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The Linux kernel's IMX code now uses vendor specific commands. | 3 | Create empty data files and allow updates for the upcoming VIOT tests. |
4 | This results in endless warnings when booting the Linux kernel. | ||
5 | 4 | ||
6 | sdhci-esdhc-imx 2194000.usdhc: esdhc_wait_for_card_clock_gate_off: | 5 | Acked-by: Igor Mammedov <imammedo@redhat.com> |
7 | card clock still not gate off in 100us!. | 6 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
8 | 7 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | |
9 | Implement support for the vendor specific command implemented in IMX hardware | 8 | Message-id: 20211210170415.583179-6-jean-philippe@linaro.org |
10 | to be able to avoid this warning. | ||
11 | |||
12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
13 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
14 | Signed-off-by: Guenter Roeck <linux@roeck-us.net> | ||
15 | Message-id: 20200603145258.195920-2-linux@roeck-us.net | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 10 | --- |
18 | hw/sd/sdhci-internal.h | 5 +++++ | 11 | tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ |
19 | include/hw/sd/sdhci.h | 5 +++++ | 12 | tests/data/acpi/q35/DSDT.viot | 0 |
20 | hw/sd/sdhci.c | 18 +++++++++++++++++- | 13 | tests/data/acpi/q35/VIOT.viot | 0 |
21 | 3 files changed, 27 insertions(+), 1 deletion(-) | 14 | tests/data/acpi/virt/VIOT | 0 |
15 | 4 files changed, 3 insertions(+) | ||
16 | create mode 100644 tests/data/acpi/q35/DSDT.viot | ||
17 | create mode 100644 tests/data/acpi/q35/VIOT.viot | ||
18 | create mode 100644 tests/data/acpi/virt/VIOT | ||
22 | 19 | ||
23 | diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h | 20 | diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h |
24 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/hw/sd/sdhci-internal.h | 22 | --- a/tests/qtest/bios-tables-test-allowed-diff.h |
26 | +++ b/hw/sd/sdhci-internal.h | 23 | +++ b/tests/qtest/bios-tables-test-allowed-diff.h |
27 | @@ -XXX,XX +XXX,XX @@ | 24 | @@ -1 +1,4 @@ |
28 | #define SDHC_CMD_INHIBIT 0x00000001 | 25 | /* List of comma-separated changed AML files to ignore */ |
29 | #define SDHC_DATA_INHIBIT 0x00000002 | 26 | +"tests/data/acpi/virt/VIOT", |
30 | #define SDHC_DAT_LINE_ACTIVE 0x00000004 | 27 | +"tests/data/acpi/q35/DSDT.viot", |
31 | +#define SDHC_IMX_CLOCK_GATE_OFF 0x00000080 | 28 | +"tests/data/acpi/q35/VIOT.viot", |
32 | #define SDHC_DOING_WRITE 0x00000100 | 29 | diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot |
33 | #define SDHC_DOING_READ 0x00000200 | 30 | new file mode 100644 |
34 | #define SDHC_SPACE_AVAILABLE 0x00000400 | 31 | index XXXXXXX..XXXXXXX |
35 | @@ -XXX,XX +XXX,XX @@ extern const VMStateDescription sdhci_vmstate; | 32 | diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot |
36 | 33 | new file mode 100644 | |
37 | 34 | index XXXXXXX..XXXXXXX | |
38 | #define ESDHC_MIX_CTRL 0x48 | 35 | diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT |
39 | + | 36 | new file mode 100644 |
40 | #define ESDHC_VENDOR_SPEC 0xc0 | 37 | index XXXXXXX..XXXXXXX |
41 | +#define ESDHC_IMX_FRC_SDCLK_ON (1 << 8) | ||
42 | + | ||
43 | #define ESDHC_DLL_CTRL 0x60 | ||
44 | |||
45 | #define ESDHC_TUNING_CTRL 0xcc | ||
46 | @@ -XXX,XX +XXX,XX @@ extern const VMStateDescription sdhci_vmstate; | ||
47 | #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \ | ||
48 | DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \ | ||
49 | DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \ | ||
50 | + DEFINE_PROP_UINT8("vendor", _state, vendor, SDHCI_VENDOR_NONE), \ | ||
51 | \ | ||
52 | /* Capabilities registers provide information on supported | ||
53 | * features of this specific host controller implementation */ \ | ||
54 | diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/include/hw/sd/sdhci.h | ||
57 | +++ b/include/hw/sd/sdhci.h | ||
58 | @@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState { | ||
59 | uint16_t acmd12errsts; /* Auto CMD12 error status register */ | ||
60 | uint16_t hostctl2; /* Host Control 2 */ | ||
61 | uint64_t admasysaddr; /* ADMA System Address Register */ | ||
62 | + uint16_t vendor_spec; /* Vendor specific register */ | ||
63 | |||
64 | /* Read-only registers */ | ||
65 | uint64_t capareg; /* Capabilities Register */ | ||
66 | @@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState { | ||
67 | uint32_t quirks; | ||
68 | uint8_t sd_spec_version; | ||
69 | uint8_t uhs_mode; | ||
70 | + uint8_t vendor; /* For vendor specific functionality */ | ||
71 | } SDHCIState; | ||
72 | |||
73 | +#define SDHCI_VENDOR_NONE 0 | ||
74 | +#define SDHCI_VENDOR_IMX 1 | ||
75 | + | ||
76 | /* | ||
77 | * Controller does not provide transfer-complete interrupt when not | ||
78 | * busy. | ||
79 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | ||
80 | index XXXXXXX..XXXXXXX 100644 | ||
81 | --- a/hw/sd/sdhci.c | ||
82 | +++ b/hw/sd/sdhci.c | ||
83 | @@ -XXX,XX +XXX,XX @@ static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) | ||
84 | } | ||
85 | break; | ||
86 | |||
87 | + case ESDHC_VENDOR_SPEC: | ||
88 | + ret = s->vendor_spec; | ||
89 | + break; | ||
90 | case ESDHC_DLL_CTRL: | ||
91 | case ESDHC_TUNE_CTRL_STATUS: | ||
92 | case ESDHC_UNDOCUMENTED_REG27: | ||
93 | case ESDHC_TUNING_CTRL: | ||
94 | - case ESDHC_VENDOR_SPEC: | ||
95 | case ESDHC_MIX_CTRL: | ||
96 | case ESDHC_WTMK_LVL: | ||
97 | ret = 0; | ||
98 | @@ -XXX,XX +XXX,XX @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) | ||
99 | case ESDHC_UNDOCUMENTED_REG27: | ||
100 | case ESDHC_TUNING_CTRL: | ||
101 | case ESDHC_WTMK_LVL: | ||
102 | + break; | ||
103 | + | ||
104 | case ESDHC_VENDOR_SPEC: | ||
105 | + s->vendor_spec = value; | ||
106 | + switch (s->vendor) { | ||
107 | + case SDHCI_VENDOR_IMX: | ||
108 | + if (value & ESDHC_IMX_FRC_SDCLK_ON) { | ||
109 | + s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF; | ||
110 | + } else { | ||
111 | + s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF; | ||
112 | + } | ||
113 | + break; | ||
114 | + default: | ||
115 | + break; | ||
116 | + } | ||
117 | break; | ||
118 | |||
119 | case SDHC_HOSTCTL: | ||
120 | -- | 38 | -- |
121 | 2.20.1 | 39 | 2.25.1 |
122 | 40 | ||
123 | 41 | diff view generated by jsdifflib |
1 | Convert the float versions of VMLA, VMLS and VMUL in the Neon | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2-reg-scalar group to decodetree. | ||
3 | 2 | ||
3 | Add two test cases for VIOT, one on the q35 machine and the other on | ||
4 | virt. To test complex topologies the q35 test has two PCIe buses that | ||
5 | bypass the IOMMU (and are therefore not described by VIOT), and two | ||
6 | buses that are translated by virtio-iommu. | ||
7 | |||
8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
9 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
10 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
11 | Message-id: 20211210170415.583179-7-jean-philippe@linaro.org | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | --- | 13 | --- |
6 | As noted in the comment on the WRAP_FP_FN macro, we could have | 14 | tests/qtest/bios-tables-test.c | 38 ++++++++++++++++++++++++++++++++++ |
7 | had a do_2scalar_fp() function, but for 3 insns it seemed | 15 | 1 file changed, 38 insertions(+) |
8 | simpler to just do the wrapping to get hold of the fpstatus ptr. | ||
9 | (These are the only fp insns in the group.) | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | --- | ||
12 | target/arm/neon-dp.decode | 3 ++ | ||
13 | target/arm/translate-neon.inc.c | 65 +++++++++++++++++++++++++++++++++ | ||
14 | target/arm/translate.c | 37 ++----------------- | ||
15 | 3 files changed, 71 insertions(+), 34 deletions(-) | ||
16 | 16 | ||
17 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | 17 | diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c |
18 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/neon-dp.decode | 19 | --- a/tests/qtest/bios-tables-test.c |
20 | +++ b/target/arm/neon-dp.decode | 20 | +++ b/tests/qtest/bios-tables-test.c |
21 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | 21 | @@ -XXX,XX +XXX,XX @@ static void test_acpi_virt_tcg(void) |
22 | &2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp | 22 | free_test_data(&data); |
23 | |||
24 | VMLA_2sc 1111 001 . 1 . .. .... .... 0000 . 1 . 0 .... @2scalar | ||
25 | + VMLA_F_2sc 1111 001 . 1 . .. .... .... 0001 . 1 . 0 .... @2scalar | ||
26 | |||
27 | VMLS_2sc 1111 001 . 1 . .. .... .... 0100 . 1 . 0 .... @2scalar | ||
28 | + VMLS_F_2sc 1111 001 . 1 . .. .... .... 0101 . 1 . 0 .... @2scalar | ||
29 | |||
30 | VMUL_2sc 1111 001 . 1 . .. .... .... 1000 . 1 . 0 .... @2scalar | ||
31 | + VMUL_F_2sc 1111 001 . 1 . .. .... .... 1001 . 1 . 0 .... @2scalar | ||
32 | ] | ||
33 | } | 23 | } |
34 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | 24 | |
35 | index XXXXXXX..XXXXXXX 100644 | 25 | +static void test_acpi_q35_viot(void) |
36 | --- a/target/arm/translate-neon.inc.c | ||
37 | +++ b/target/arm/translate-neon.inc.c | ||
38 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMLS_2sc(DisasContext *s, arg_2scalar *a) | ||
39 | |||
40 | return do_2scalar(s, a, opfn[a->size], accfn[a->size]); | ||
41 | } | ||
42 | + | ||
43 | +/* | ||
44 | + * Rather than have a float-specific version of do_2scalar just for | ||
45 | + * three insns, we wrap a NeonGenTwoSingleOpFn to turn it into | ||
46 | + * a NeonGenTwoOpFn. | ||
47 | + */ | ||
48 | +#define WRAP_FP_FN(WRAPNAME, FUNC) \ | ||
49 | + static void WRAPNAME(TCGv_i32 rd, TCGv_i32 rn, TCGv_i32 rm) \ | ||
50 | + { \ | ||
51 | + TCGv_ptr fpstatus = get_fpstatus_ptr(1); \ | ||
52 | + FUNC(rd, rn, rm, fpstatus); \ | ||
53 | + tcg_temp_free_ptr(fpstatus); \ | ||
54 | + } | ||
55 | + | ||
56 | +WRAP_FP_FN(gen_VMUL_F_mul, gen_helper_vfp_muls) | ||
57 | +WRAP_FP_FN(gen_VMUL_F_add, gen_helper_vfp_adds) | ||
58 | +WRAP_FP_FN(gen_VMUL_F_sub, gen_helper_vfp_subs) | ||
59 | + | ||
60 | +static bool trans_VMUL_F_2sc(DisasContext *s, arg_2scalar *a) | ||
61 | +{ | 26 | +{ |
62 | + static NeonGenTwoOpFn * const opfn[] = { | 27 | + test_data data = { |
63 | + NULL, | 28 | + .machine = MACHINE_Q35, |
64 | + NULL, /* TODO: fp16 support */ | 29 | + .variant = ".viot", |
65 | + gen_VMUL_F_mul, | ||
66 | + NULL, | ||
67 | + }; | 30 | + }; |
68 | + | 31 | + |
69 | + return do_2scalar(s, a, opfn[a->size], NULL); | 32 | + /* |
33 | + * To keep things interesting, two buses bypass the IOMMU. | ||
34 | + * VIOT should only describes the other two buses. | ||
35 | + */ | ||
36 | + test_acpi_one("-machine default_bus_bypass_iommu=on " | ||
37 | + "-device virtio-iommu-pci " | ||
38 | + "-device pxb-pcie,bus_nr=0x10,id=pcie.100,bus=pcie.0 " | ||
39 | + "-device pxb-pcie,bus_nr=0x20,id=pcie.200,bus=pcie.0,bypass_iommu=on " | ||
40 | + "-device pxb-pcie,bus_nr=0x30,id=pcie.300,bus=pcie.0", | ||
41 | + &data); | ||
42 | + free_test_data(&data); | ||
70 | +} | 43 | +} |
71 | + | 44 | + |
72 | +static bool trans_VMLA_F_2sc(DisasContext *s, arg_2scalar *a) | 45 | +static void test_acpi_virt_viot(void) |
73 | +{ | 46 | +{ |
74 | + static NeonGenTwoOpFn * const opfn[] = { | 47 | + test_data data = { |
75 | + NULL, | 48 | + .machine = "virt", |
76 | + NULL, /* TODO: fp16 support */ | 49 | + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd", |
77 | + gen_VMUL_F_mul, | 50 | + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd", |
78 | + NULL, | 51 | + .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2", |
79 | + }; | 52 | + .ram_start = 0x40000000ULL, |
80 | + static NeonGenTwoOpFn * const accfn[] = { | 53 | + .scan_len = 128ULL * 1024 * 1024, |
81 | + NULL, | ||
82 | + NULL, /* TODO: fp16 support */ | ||
83 | + gen_VMUL_F_add, | ||
84 | + NULL, | ||
85 | + }; | 54 | + }; |
86 | + | 55 | + |
87 | + return do_2scalar(s, a, opfn[a->size], accfn[a->size]); | 56 | + test_acpi_one("-cpu cortex-a57 " |
57 | + "-device virtio-iommu-pci", &data); | ||
58 | + free_test_data(&data); | ||
88 | +} | 59 | +} |
89 | + | 60 | + |
90 | +static bool trans_VMLS_F_2sc(DisasContext *s, arg_2scalar *a) | 61 | static void test_oem_fields(test_data *data) |
91 | +{ | 62 | { |
92 | + static NeonGenTwoOpFn * const opfn[] = { | 63 | int i; |
93 | + NULL, | 64 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[]) |
94 | + NULL, /* TODO: fp16 support */ | 65 | qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xapic); |
95 | + gen_VMUL_F_mul, | 66 | qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar); |
96 | + NULL, | 67 | } |
97 | + }; | 68 | + qtest_add_func("acpi/q35/viot", test_acpi_q35_viot); |
98 | + static NeonGenTwoOpFn * const accfn[] = { | 69 | } else if (strcmp(arch, "aarch64") == 0) { |
99 | + NULL, | 70 | if (has_tcg) { |
100 | + NULL, /* TODO: fp16 support */ | 71 | qtest_add_func("acpi/virt", test_acpi_virt_tcg); |
101 | + gen_VMUL_F_sub, | 72 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[]) |
102 | + NULL, | 73 | qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp); |
103 | + }; | 74 | qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb); |
104 | + | 75 | qtest_add_func("acpi/virt/oem-fields", test_acpi_oem_fields_virt); |
105 | + return do_2scalar(s, a, opfn[a->size], accfn[a->size]); | 76 | + qtest_add_func("acpi/virt/viot", test_acpi_virt_viot); |
106 | +} | 77 | } |
107 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 78 | } |
108 | index XXXXXXX..XXXXXXX 100644 | 79 | ret = g_test_run(); |
109 | --- a/target/arm/translate.c | ||
110 | +++ b/target/arm/translate.c | ||
111 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
112 | case 0: /* Integer VMLA scalar */ | ||
113 | case 4: /* Integer VMLS scalar */ | ||
114 | case 8: /* Integer VMUL scalar */ | ||
115 | - return 1; /* handled by decodetree */ | ||
116 | - | ||
117 | case 1: /* Float VMLA scalar */ | ||
118 | case 5: /* Floating point VMLS scalar */ | ||
119 | case 9: /* Floating point VMUL scalar */ | ||
120 | - if (size == 1) { | ||
121 | - return 1; | ||
122 | - } | ||
123 | - /* fall through */ | ||
124 | + return 1; /* handled by decodetree */ | ||
125 | + | ||
126 | case 12: /* VQDMULH scalar */ | ||
127 | case 13: /* VQRDMULH scalar */ | ||
128 | if (u && ((rd | rn) & 1)) { | ||
129 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
130 | } else { | ||
131 | gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2); | ||
132 | } | ||
133 | - } else if (op == 13) { | ||
134 | + } else { | ||
135 | if (size == 1) { | ||
136 | gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2); | ||
137 | } else { | ||
138 | gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2); | ||
139 | } | ||
140 | - } else { | ||
141 | - TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
142 | - gen_helper_vfp_muls(tmp, tmp, tmp2, fpstatus); | ||
143 | - tcg_temp_free_ptr(fpstatus); | ||
144 | } | ||
145 | tcg_temp_free_i32(tmp2); | ||
146 | - if (op < 8) { | ||
147 | - /* Accumulate. */ | ||
148 | - tmp2 = neon_load_reg(rd, pass); | ||
149 | - switch (op) { | ||
150 | - case 1: | ||
151 | - { | ||
152 | - TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
153 | - gen_helper_vfp_adds(tmp, tmp, tmp2, fpstatus); | ||
154 | - tcg_temp_free_ptr(fpstatus); | ||
155 | - break; | ||
156 | - } | ||
157 | - case 5: | ||
158 | - { | ||
159 | - TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
160 | - gen_helper_vfp_subs(tmp, tmp2, tmp, fpstatus); | ||
161 | - tcg_temp_free_ptr(fpstatus); | ||
162 | - break; | ||
163 | - } | ||
164 | - default: | ||
165 | - abort(); | ||
166 | - } | ||
167 | - tcg_temp_free_i32(tmp2); | ||
168 | - } | ||
169 | neon_store_reg(rd, pass, tmp); | ||
170 | } | ||
171 | break; | ||
172 | -- | 80 | -- |
173 | 2.20.1 | 81 | 2.25.1 |
174 | 82 | ||
175 | 83 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> | |
2 | |||
3 | Add expected blobs of the VIOT and DSDT table for the VIOT test on the | ||
4 | q35 machine. | ||
5 | |||
6 | Since the test instantiates a virtio device and two PCIe expander | ||
7 | bridges, DSDT.viot has more blocks than the base DSDT. | ||
8 | |||
9 | The VIOT table generated for the q35 test is: | ||
10 | |||
11 | [000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table] | ||
12 | [004h 0004 4] Table Length : 00000070 | ||
13 | [008h 0008 1] Revision : 00 | ||
14 | [009h 0009 1] Checksum : 3D | ||
15 | [00Ah 0010 6] Oem ID : "BOCHS " | ||
16 | [010h 0016 8] Oem Table ID : "BXPC " | ||
17 | [018h 0024 4] Oem Revision : 00000001 | ||
18 | [01Ch 0028 4] Asl Compiler ID : "BXPC" | ||
19 | [020h 0032 4] Asl Compiler Revision : 00000001 | ||
20 | |||
21 | [024h 0036 2] Node count : 0003 | ||
22 | [026h 0038 2] Node offset : 0030 | ||
23 | [028h 0040 8] Reserved : 0000000000000000 | ||
24 | |||
25 | [030h 0048 1] Type : 03 [VirtIO-PCI IOMMU] | ||
26 | [031h 0049 1] Reserved : 00 | ||
27 | [032h 0050 2] Length : 0010 | ||
28 | |||
29 | [034h 0052 2] PCI Segment : 0000 | ||
30 | [036h 0054 2] PCI BDF number : 0010 | ||
31 | [038h 0056 8] Reserved : 0000000000000000 | ||
32 | |||
33 | [040h 0064 1] Type : 01 [PCI Range] | ||
34 | [041h 0065 1] Reserved : 00 | ||
35 | [042h 0066 2] Length : 0018 | ||
36 | |||
37 | [044h 0068 4] Endpoint start : 00003000 | ||
38 | [048h 0072 2] PCI Segment start : 0000 | ||
39 | [04Ah 0074 2] PCI Segment end : 0000 | ||
40 | [04Ch 0076 2] PCI BDF start : 3000 | ||
41 | [04Eh 0078 2] PCI BDF end : 30FF | ||
42 | [050h 0080 2] Output node : 0030 | ||
43 | [052h 0082 6] Reserved : 000000000000 | ||
44 | |||
45 | [058h 0088 1] Type : 01 [PCI Range] | ||
46 | [059h 0089 1] Reserved : 00 | ||
47 | [05Ah 0090 2] Length : 0018 | ||
48 | |||
49 | [05Ch 0092 4] Endpoint start : 00001000 | ||
50 | [060h 0096 2] PCI Segment start : 0000 | ||
51 | [062h 0098 2] PCI Segment end : 0000 | ||
52 | [064h 0100 2] PCI BDF start : 1000 | ||
53 | [066h 0102 2] PCI BDF end : 10FF | ||
54 | [068h 0104 2] Output node : 0030 | ||
55 | [06Ah 0106 6] Reserved : 000000000000 | ||
56 | |||
57 | And the DSDT diff is: | ||
58 | |||
59 | @@ -XXX,XX +XXX,XX @@ | ||
60 | * | ||
61 | * Disassembling to symbolic ASL+ operators | ||
62 | * | ||
63 | - * Disassembly of tests/data/acpi/q35/DSDT, Fri Dec 10 15:03:08 2021 | ||
64 | + * Disassembly of /tmp/aml-H9Y5D1, Fri Dec 10 15:02:27 2021 | ||
65 | * | ||
66 | * Original Table Header: | ||
67 | * Signature "DSDT" | ||
68 | - * Length 0x00002061 (8289) | ||
69 | + * Length 0x000024B6 (9398) | ||
70 | * Revision 0x01 **** 32-bit table (V1), no 64-bit math support | ||
71 | - * Checksum 0xFA | ||
72 | + * Checksum 0xA7 | ||
73 | * OEM ID "BOCHS " | ||
74 | * OEM Table ID "BXPC " | ||
75 | * OEM Revision 0x00000001 (1) | ||
76 | @@ -XXX,XX +XXX,XX @@ | ||
77 | } | ||
78 | } | ||
79 | |||
80 | + Scope (\_SB) | ||
81 | + { | ||
82 | + Device (PC30) | ||
83 | + { | ||
84 | + Name (_UID, 0x30) // _UID: Unique ID | ||
85 | + Name (_BBN, 0x30) // _BBN: BIOS Bus Number | ||
86 | + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID | ||
87 | + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID | ||
88 | + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities | ||
89 | + { | ||
90 | + CreateDWordField (Arg3, Zero, CDW1) | ||
91 | + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) | ||
92 | + { | ||
93 | + CreateDWordField (Arg3, 0x04, CDW2) | ||
94 | + CreateDWordField (Arg3, 0x08, CDW3) | ||
95 | + Local0 = CDW3 /* \_SB_.PC30._OSC.CDW3 */ | ||
96 | + Local0 &= 0x1F | ||
97 | + If ((Arg1 != One)) | ||
98 | + { | ||
99 | + CDW1 |= 0x08 | ||
100 | + } | ||
101 | + | ||
102 | + If ((CDW3 != Local0)) | ||
103 | + { | ||
104 | + CDW1 |= 0x10 | ||
105 | + } | ||
106 | + | ||
107 | + CDW3 = Local0 | ||
108 | + } | ||
109 | + Else | ||
110 | + { | ||
111 | + CDW1 |= 0x04 | ||
112 | + } | ||
113 | + | ||
114 | + Return (Arg3) | ||
115 | + } | ||
116 | + | ||
117 | + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table | ||
118 | + { | ||
119 | + Local0 = Package (0x80){} | ||
120 | + Local1 = Zero | ||
121 | + While ((Local1 < 0x80)) | ||
122 | + { | ||
123 | + Local2 = (Local1 >> 0x02) | ||
124 | + Local3 = ((Local1 + Local2) & 0x03) | ||
125 | + If ((Local3 == Zero)) | ||
126 | + { | ||
127 | + Local4 = Package (0x04) | ||
128 | + { | ||
129 | + Zero, | ||
130 | + Zero, | ||
131 | + LNKD, | ||
132 | + Zero | ||
133 | + } | ||
134 | + } | ||
135 | + | ||
136 | + If ((Local3 == One)) | ||
137 | + { | ||
138 | + Local4 = Package (0x04) | ||
139 | + { | ||
140 | + Zero, | ||
141 | + Zero, | ||
142 | + LNKA, | ||
143 | + Zero | ||
144 | + } | ||
145 | + } | ||
146 | + | ||
147 | + If ((Local3 == 0x02)) | ||
148 | + { | ||
149 | + Local4 = Package (0x04) | ||
150 | + { | ||
151 | + Zero, | ||
152 | + Zero, | ||
153 | + LNKB, | ||
154 | + Zero | ||
155 | + } | ||
156 | + } | ||
157 | + | ||
158 | + If ((Local3 == 0x03)) | ||
159 | + { | ||
160 | + Local4 = Package (0x04) | ||
161 | + { | ||
162 | + Zero, | ||
163 | + Zero, | ||
164 | + LNKC, | ||
165 | + Zero | ||
166 | + } | ||
167 | + } | ||
168 | + | ||
169 | + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) | ||
170 | + Local4 [One] = (Local1 & 0x03) | ||
171 | + Local0 [Local1] = Local4 | ||
172 | + Local1++ | ||
173 | + } | ||
174 | + | ||
175 | + Return (Local0) | ||
176 | + } | ||
177 | + | ||
178 | + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings | ||
179 | + { | ||
180 | + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, | ||
181 | + 0x0000, // Granularity | ||
182 | + 0x0030, // Range Minimum | ||
183 | + 0x0030, // Range Maximum | ||
184 | + 0x0000, // Translation Offset | ||
185 | + 0x0001, // Length | ||
186 | + ,, ) | ||
187 | + }) | ||
188 | + } | ||
189 | + } | ||
190 | + | ||
191 | + Scope (\_SB) | ||
192 | + { | ||
193 | + Device (PC20) | ||
194 | + { | ||
195 | + Name (_UID, 0x20) // _UID: Unique ID | ||
196 | + Name (_BBN, 0x20) // _BBN: BIOS Bus Number | ||
197 | + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID | ||
198 | + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID | ||
199 | + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities | ||
200 | + { | ||
201 | + CreateDWordField (Arg3, Zero, CDW1) | ||
202 | + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) | ||
203 | + { | ||
204 | + CreateDWordField (Arg3, 0x04, CDW2) | ||
205 | + CreateDWordField (Arg3, 0x08, CDW3) | ||
206 | + Local0 = CDW3 /* \_SB_.PC20._OSC.CDW3 */ | ||
207 | + Local0 &= 0x1F | ||
208 | + If ((Arg1 != One)) | ||
209 | + { | ||
210 | + CDW1 |= 0x08 | ||
211 | + } | ||
212 | + | ||
213 | + If ((CDW3 != Local0)) | ||
214 | + { | ||
215 | + CDW1 |= 0x10 | ||
216 | + } | ||
217 | + | ||
218 | + CDW3 = Local0 | ||
219 | + } | ||
220 | + Else | ||
221 | + { | ||
222 | + CDW1 |= 0x04 | ||
223 | + } | ||
224 | + | ||
225 | + Return (Arg3) | ||
226 | + } | ||
227 | + | ||
228 | + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table | ||
229 | + { | ||
230 | + Local0 = Package (0x80){} | ||
231 | + Local1 = Zero | ||
232 | + While ((Local1 < 0x80)) | ||
233 | + { | ||
234 | + Local2 = (Local1 >> 0x02) | ||
235 | + Local3 = ((Local1 + Local2) & 0x03) | ||
236 | + If ((Local3 == Zero)) | ||
237 | + { | ||
238 | + Local4 = Package (0x04) | ||
239 | + { | ||
240 | + Zero, | ||
241 | + Zero, | ||
242 | + LNKD, | ||
243 | + Zero | ||
244 | + } | ||
245 | + } | ||
246 | + | ||
247 | + If ((Local3 == One)) | ||
248 | + { | ||
249 | + Local4 = Package (0x04) | ||
250 | + { | ||
251 | + Zero, | ||
252 | + Zero, | ||
253 | + LNKA, | ||
254 | + Zero | ||
255 | + } | ||
256 | + } | ||
257 | + | ||
258 | + If ((Local3 == 0x02)) | ||
259 | + { | ||
260 | + Local4 = Package (0x04) | ||
261 | + { | ||
262 | + Zero, | ||
263 | + Zero, | ||
264 | + LNKB, | ||
265 | + Zero | ||
266 | + } | ||
267 | + } | ||
268 | + | ||
269 | + If ((Local3 == 0x03)) | ||
270 | + { | ||
271 | + Local4 = Package (0x04) | ||
272 | + { | ||
273 | + Zero, | ||
274 | + Zero, | ||
275 | + LNKC, | ||
276 | + Zero | ||
277 | + } | ||
278 | + } | ||
279 | + | ||
280 | + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) | ||
281 | + Local4 [One] = (Local1 & 0x03) | ||
282 | + Local0 [Local1] = Local4 | ||
283 | + Local1++ | ||
284 | + } | ||
285 | + | ||
286 | + Return (Local0) | ||
287 | + } | ||
288 | + | ||
289 | + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings | ||
290 | + { | ||
291 | + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, | ||
292 | + 0x0000, // Granularity | ||
293 | + 0x0020, // Range Minimum | ||
294 | + 0x0020, // Range Maximum | ||
295 | + 0x0000, // Translation Offset | ||
296 | + 0x0001, // Length | ||
297 | + ,, ) | ||
298 | + }) | ||
299 | + } | ||
300 | + } | ||
301 | + | ||
302 | + Scope (\_SB) | ||
303 | + { | ||
304 | + Device (PC10) | ||
305 | + { | ||
306 | + Name (_UID, 0x10) // _UID: Unique ID | ||
307 | + Name (_BBN, 0x10) // _BBN: BIOS Bus Number | ||
308 | + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID | ||
309 | + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID | ||
310 | + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities | ||
311 | + { | ||
312 | + CreateDWordField (Arg3, Zero, CDW1) | ||
313 | + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) | ||
314 | + { | ||
315 | + CreateDWordField (Arg3, 0x04, CDW2) | ||
316 | + CreateDWordField (Arg3, 0x08, CDW3) | ||
317 | + Local0 = CDW3 /* \_SB_.PC10._OSC.CDW3 */ | ||
318 | + Local0 &= 0x1F | ||
319 | + If ((Arg1 != One)) | ||
320 | + { | ||
321 | + CDW1 |= 0x08 | ||
322 | + } | ||
323 | + | ||
324 | + If ((CDW3 != Local0)) | ||
325 | + { | ||
326 | + CDW1 |= 0x10 | ||
327 | + } | ||
328 | + | ||
329 | + CDW3 = Local0 | ||
330 | + } | ||
331 | + Else | ||
332 | + { | ||
333 | + CDW1 |= 0x04 | ||
334 | + } | ||
335 | + | ||
336 | + Return (Arg3) | ||
337 | + } | ||
338 | + | ||
339 | + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table | ||
340 | + { | ||
341 | + Local0 = Package (0x80){} | ||
342 | + Local1 = Zero | ||
343 | + While ((Local1 < 0x80)) | ||
344 | + { | ||
345 | + Local2 = (Local1 >> 0x02) | ||
346 | + Local3 = ((Local1 + Local2) & 0x03) | ||
347 | + If ((Local3 == Zero)) | ||
348 | + { | ||
349 | + Local4 = Package (0x04) | ||
350 | + { | ||
351 | + Zero, | ||
352 | + Zero, | ||
353 | + LNKD, | ||
354 | + Zero | ||
355 | + } | ||
356 | + } | ||
357 | + | ||
358 | + If ((Local3 == One)) | ||
359 | + { | ||
360 | + Local4 = Package (0x04) | ||
361 | + { | ||
362 | + Zero, | ||
363 | + Zero, | ||
364 | + LNKA, | ||
365 | + Zero | ||
366 | + } | ||
367 | + } | ||
368 | + | ||
369 | + If ((Local3 == 0x02)) | ||
370 | + { | ||
371 | + Local4 = Package (0x04) | ||
372 | + { | ||
373 | + Zero, | ||
374 | + Zero, | ||
375 | + LNKB, | ||
376 | + Zero | ||
377 | + } | ||
378 | + } | ||
379 | + | ||
380 | + If ((Local3 == 0x03)) | ||
381 | + { | ||
382 | + Local4 = Package (0x04) | ||
383 | + { | ||
384 | + Zero, | ||
385 | + Zero, | ||
386 | + LNKC, | ||
387 | + Zero | ||
388 | + } | ||
389 | + } | ||
390 | + | ||
391 | + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) | ||
392 | + Local4 [One] = (Local1 & 0x03) | ||
393 | + Local0 [Local1] = Local4 | ||
394 | + Local1++ | ||
395 | + } | ||
396 | + | ||
397 | + Return (Local0) | ||
398 | + } | ||
399 | + | ||
400 | + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings | ||
401 | + { | ||
402 | + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, | ||
403 | + 0x0000, // Granularity | ||
404 | + 0x0010, // Range Minimum | ||
405 | + 0x0010, // Range Maximum | ||
406 | + 0x0000, // Translation Offset | ||
407 | + 0x0001, // Length | ||
408 | + ,, ) | ||
409 | + }) | ||
410 | + } | ||
411 | + } | ||
412 | + | ||
413 | Scope (\_SB.PCI0) | ||
414 | { | ||
415 | Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings | ||
416 | @@ -XXX,XX +XXX,XX @@ | ||
417 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, | ||
418 | 0x0000, // Granularity | ||
419 | 0x0000, // Range Minimum | ||
420 | - 0x00FF, // Range Maximum | ||
421 | + 0x000F, // Range Maximum | ||
422 | 0x0000, // Translation Offset | ||
423 | - 0x0100, // Length | ||
424 | + 0x0010, // Length | ||
425 | ,, ) | ||
426 | IO (Decode16, | ||
427 | 0x0CF8, // Range Minimum | ||
428 | @@ -XXX,XX +XXX,XX @@ | ||
429 | } | ||
430 | } | ||
431 | |||
432 | + Device (S10) | ||
433 | + { | ||
434 | + Name (_ADR, 0x00020000) // _ADR: Address | ||
435 | + } | ||
436 | + | ||
437 | + Device (S18) | ||
438 | + { | ||
439 | + Name (_ADR, 0x00030000) // _ADR: Address | ||
440 | + } | ||
441 | + | ||
442 | + Device (S20) | ||
443 | + { | ||
444 | + Name (_ADR, 0x00040000) // _ADR: Address | ||
445 | + } | ||
446 | + | ||
447 | + Device (S28) | ||
448 | + { | ||
449 | + Name (_ADR, 0x00050000) // _ADR: Address | ||
450 | + } | ||
451 | + | ||
452 | Method (PCNT, 0, NotSerialized) | ||
453 | { | ||
454 | } | ||
455 | |||
456 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
457 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
458 | Message-id: 20211210170415.583179-8-jean-philippe@linaro.org | ||
459 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
460 | --- | ||
461 | tests/qtest/bios-tables-test-allowed-diff.h | 2 -- | ||
462 | tests/data/acpi/q35/DSDT.viot | Bin 0 -> 9398 bytes | ||
463 | tests/data/acpi/q35/VIOT.viot | Bin 0 -> 112 bytes | ||
464 | 3 files changed, 2 deletions(-) | ||
465 | |||
466 | diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h | ||
467 | index XXXXXXX..XXXXXXX 100644 | ||
468 | --- a/tests/qtest/bios-tables-test-allowed-diff.h | ||
469 | +++ b/tests/qtest/bios-tables-test-allowed-diff.h | ||
470 | @@ -XXX,XX +XXX,XX @@ | ||
471 | /* List of comma-separated changed AML files to ignore */ | ||
472 | "tests/data/acpi/virt/VIOT", | ||
473 | -"tests/data/acpi/q35/DSDT.viot", | ||
474 | -"tests/data/acpi/q35/VIOT.viot", | ||
475 | diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot | ||
476 | index XXXXXXX..XXXXXXX 100644 | ||
477 | GIT binary patch | ||
478 | literal 9398 | ||
479 | zcmeHNO>7&-8J*>iv|O&FB}G~Oi$yp||57BBoWHhc5OS9yDTx$CQgH$r;8Idr*-4Q_ | ||
480 | z5(9Az1F`}niVsB-)<KW7p`g9Br(A2Gm-gmc1N78GFS!;)e2V(MnH_0{q<{#yMgn&C | ||
481 | zn|*J-d9yqFhO_H6z19~`FlPL*u<DkZ*}|)JH;X@mF-FI<cPg<fti9tEN*yB^i5czN | ||
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484 | zeLZ*n<<Bm^n}6`jfBx#u8&(W}1?)}iF9o#mZ~E2+zwdn7yK3AbIzKnxpZ>JRPm3~# | ||
485 | z&ICS{+_OayRW-l=Mtk=~uaS3o8z<_udd|(wqg`&JnVPfCe>BUOO`Su3e>pff_^UW% | ||
486 | z&JE^NO`)=Amg~iqRB1pPscP?(>#ZuY8GHCmlEvD$9g3%4Db~Dfz2SATnddvrR-Oe^ | ||
487 | z;s;dJec!hnzi)ri^I6YN9vtkm{^TdUF8h7gX8-<Qe4p)GQ=)AtYx2VcwdLVAEXEjG | ||
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494 | zvT@rUu>DljxJ?^&Z?-?vyJn3C>3D=qux{Y*bs5|5n)Qmi$TD^Zdn4GU$ocJS2Hh-< | ||
495 | z`xPI^^+v0nUVdjMos8k`WGl7hA`{03ju%<lrgAHSpd^DRf-*}_#Ly0mB!LSfVgWcQ | ||
496 | z&T$@~G9)JI=hz5m0vkrel+Xy{Oh7pkAu-V!j*W7rY(bO}Q$nMH2`FbGB&N)QaV4<4 | ||
497 | zo)~9JXiP9=;}NPl<C@MmXG&;XFlFNrsyfFsonxFSp<}vEgsRSQP3O3#b6nSnP}ON_ | ||
498 | zI!#Tdsp~|j>ckUB>FI=~GokB5sOq#dotCE4(sd$KbtW~PNlj-`*NIToiD#j5J#9^= | ||
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500 | zn$DD_Go|Z9sOn5>I@6lYw5}7Os&iV?Ij!lO)^#FOb!If38BJ$K*NIToIiu;E(R9w} | ||
501 | zIuWWmPiZ<&X*y5oIuWWmF_XaEC!a&Jn$B5WCqh-{X-(&8P3LJ{Cqh-{8P3dyPr@^t | ||
502 | zSqL9?X9Uwd3W@23*s~h*tj0X6GZCuHa~kuU#yqDp5vt7d8uPryJg+kms?5hU=3^T3 | ||
503 | zF`bD}WnSP+=`t5MQ$FJ_2&Q~+BP6E0f^%BVIW6a$o)e+SX~IDBih-7z6{O~7YTy`& | ||
504 | zLjy&Cv?7QikV#>n0>>@MV8oK`Gmun34-FKdlm-J8SZSaNlnhir4-FI{S|bfqV8e)V | ||
505 | zss<{chX#reE#g=hsKAC%sF6d-Km}BWs!kZFsFpKfpbC@>6rprQGEjt4Ck#|zITHq| | ||
506 | zK*>M_l;<P^MJRQ`Kn0dFVW0|>3{*fllMEE0)CmI>Sk8ojDo`>|0p(0GP=xY&!axO< | ||
507 | zGhv_#lnhirIg<<&q0|Wj6<E%MfhtfkPyyvkGEjt4Ck#|zITHq|K*>M_lrzad5lWpf | ||
508 | zP=V!47^ngz0~JutBm+e#b;3XemNQ|X3X}{~Ksl2P6rt1!0~J`#gn=qhGEf2KOfpb} | ||
509 | zQYQ>lU^x>8szAv=1(Y+%KoLrvFi?TzOc<yFB?A>u&LjgxD0RX>1(q{mpbC@>R6seC | ||
510 | z3>2Z%2?G^a&V+#~P%=;f<xDbAgi<FARA4z12C6{GKn0XD$v_cGoiI>=<xCi;0wn_# | ||
511 | zP|hR+MJRQ`Kn0dFVW0|>3{*fllMEE0)CmI>Sk8ojDo`>|0p(0GP=rz^3{+q_69%e4 | ||
512 | z$v_2^Gs!>^N}VuJf#pmXr~)Me6;RG314Srx!axxz28u{EP=u<1B2)}iVZuNaCK;&0 | ||
513 | zBm-5LFi?dF167!0pbC==RAItE6($T+VUmF=Ofpb~2?JG_Fi?d_2C6X0Kouqo6p_5T | ||
514 | zFi=FeV!SiSKoR0H$dH(_Z(*Q_WZ%L-5y`$K14StNmJAdjmWs}HV4<vU_xO+1efmLq | ||
515 | zZ;W>N_U)fP6Qy6Nw5mbt9Y(#emWSi66=>tq#xoh#Ue=0qyhxi8ZOUe5y0V7VfPUhp | ||
516 | zwX=;ymc+i5%sg9Ja~lZ&8oAV@mHc>&CHP9v4R(jhtT?un;O4e9#pno)Xkh7OWgK&a | ||
517 | zyj=3Iv0OuoK_;5rOr5f(Kb~ZXDBO+V`OWYo#_C08imwChQxnjdd?wZLDou8aj;$SD | ||
518 | zGDYiA3<$Tu<JnHL(KPOChi#zrR32t83}naR$+ym4P_h?z_5#|cW-nw$XD_sOtE62l | ||
519 | zrD3@*)NVyiklt0&yF9%+klsBey&I<Y2E<!f(E8TuJte)z(|ZHyy<^gQVfx}=`q&B5 | ||
520 | z7nSryp1wGczIaUfVwiq$Fn#<4=@*ssi#+|}K>EdF(l3VTOM~ghPLRH&q%ZOGrGfON | ||
521 | zW73zx^yR_y<0nX8R??Sw`tm^f@-gYlNFSp|*<gA{q?Zp5Oe-+l#rmyYmKozi9y=P> | ||
522 | zVReJU*h=ZuVXiS$ohTbw-O#v9>(yZbGE|)?8(H1ZIKvV!jWa0>vy!3eMA^vdhQ>`s | ||
523 | zuMSg{q3T50$m)j1!HixV<}X9liL#N^4c*tL^y)CF8LCc{jjV3yKAqL8!%SzWI#H%q | ||
524 | z=bSrQ&)%JCRttF5g4Zf`6l?y@>PzD7MA^D>wBlcH6r1ucwJ<p0O%rZ?JzIY3-QdmZ | ||
525 | zzs|n>`a5r3e|z)wcUaqS>nqFQ-8x}eCF4u`OWUxqst-@1rSmUs%WmKP5e0dcb?e2N | ||
526 | z;Z|x*!);VwF|Yuhqs^khqOM!@u*jY!WYldISF(V6`BoNd&6Qfk3>X#SuD^7J>p_D= | ||
527 | zBPa51y^_n#=cpOt#Zf$ya$Ae9Mfz56n|<i!a=ELS@)%a{^NIH3SDuN<R~sah1km#P | ||
528 | zU@?*f%<rG=4W1wgfi;C?_n|W@%lm$&8YfvNOJodIg&IcIpIJQRHr<+ej11GQ6)&eF | ||
529 | z2Lam*jIH}#y0>KnY%4JQfOYS$*uU%f#@$U6`N8I3N-lV?5ErFCdv~xDmu2(wexld4 | ||
530 | z4v^;aVAT2k6GJ^m*FD(Wqc(Qg^)6a<?}h$zLoj}4;PP!+(O{@!a1y-hoAhF_7!z+6 | ||
531 | zslpAmNtYbjHrw-~#SPVk_FUf>-Obg6yV`8o$8_`PyJe_;bY5_EMBfBfWU!Q=*9HsG | ||
532 | z%_Cda{@_Krr!oHVhv9+y+T5qR8zZ2aZ>5r!$*|f$^U%yBUYfR&B!+EYy_PwL!BeUi | ||
533 | zJH^}r3r9Q+B)X@Z)fk=P13w&7x#wBtXTZ)g>WITPg5r&pQc!nmyrmk#S(>>b9xnNr | ||
534 | zx_b#v9Xv-Y><Wb%?S^0Xe&<)bbKl_=Z|3C$tf|F<bYzE*mfHB;uC)`q-?buaBe?l? | ||
535 | zcLTpK*k<49Z32`K?|nSBMFqxTK^_IE-li2fEGdK~(ZdoKBl6ab4a;Hler#`xvEXJG | ||
536 | zb?<E%EZExfX>jcOVhS*0rS~RS1dA#xhkv@Nct@#q?LyeKS<$uFec!bw>{@uu$gZ6a | ||
537 | zyVen1i{1BKd%~`D7|m$;U0a<I*3I7%^N%N%lGYdU_GS!gaR8T$NA@GzFi~z`l7hdl | ||
538 | zarZy6590|88pi(1zq;V(>38zM0sT&<zX;R5$1w3;`_JMG`;&I&0Y23DMx1%@(w(R9 | ||
539 | z4M$j;D5J+Gy%fijRQsctzFKf&cv|BAz#YLq3CZJWDdtL4u1u1|mkdcUp7|sxJC+?Y | ||
540 | z_@@s`v3j}Q7*z>6X~cwUxUL8G1KT)_XTp!KAbs;vCp{K3&~_X@+ew=-D}v`2MbFV0 | ||
541 | zQsVsL=rXi-pI*G|iiz;VTCutgUs)hDzV1+4?8KcoP3xROf<M%qC6lgVdpFt4<-|uM | ||
542 | z=#rl_b1#YjSIl6Toj2z_hOZcKupkdE(LozC(fN=FY(x|sk)ym|;Rq2E1xJWD%Z!ol | ||
543 | Gu>S+TT-130 | ||
544 | |||
545 | literal 0 | ||
546 | HcmV?d00001 | ||
547 | |||
548 | diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot | ||
549 | index XXXXXXX..XXXXXXX 100644 | ||
550 | GIT binary patch | ||
551 | literal 112 | ||
552 | zcmWIZ^baXu00LVle`k+i1*eDrX9XZ&1PX!JAex!M0Hgv8m>C3sGzdcgBZCA3T-xBj | ||
553 | Q0Zb)W9Hva*zW_`e0M!8s0RR91 | ||
554 | |||
555 | literal 0 | ||
556 | HcmV?d00001 | ||
557 | |||
558 | -- | ||
559 | 2.25.1 | ||
560 | |||
561 | diff view generated by jsdifflib |
1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> | 3 | The VIOT blob contains the following: |
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 4 | |
5 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | [000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table] |
6 | [PMD: Fixed 32-bit format string using PRIx32/PRIx64] | 6 | [004h 0004 4] Table Length : 00000058 |
7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 7 | [008h 0008 1] Revision : 00 |
8 | [009h 0009 1] Checksum : 66 | ||
9 | [00Ah 0010 6] Oem ID : "BOCHS " | ||
10 | [010h 0016 8] Oem Table ID : "BXPC " | ||
11 | [018h 0024 4] Oem Revision : 00000001 | ||
12 | [01Ch 0028 4] Asl Compiler ID : "BXPC" | ||
13 | [020h 0032 4] Asl Compiler Revision : 00000001 | ||
14 | |||
15 | [024h 0036 2] Node count : 0002 | ||
16 | [026h 0038 2] Node offset : 0030 | ||
17 | [028h 0040 8] Reserved : 0000000000000000 | ||
18 | |||
19 | [030h 0048 1] Type : 03 [VirtIO-PCI IOMMU] | ||
20 | [031h 0049 1] Reserved : 00 | ||
21 | [032h 0050 2] Length : 0010 | ||
22 | |||
23 | [034h 0052 2] PCI Segment : 0000 | ||
24 | [036h 0054 2] PCI BDF number : 0008 | ||
25 | [038h 0056 8] Reserved : 0000000000000000 | ||
26 | |||
27 | [040h 0064 1] Type : 01 [PCI Range] | ||
28 | [041h 0065 1] Reserved : 00 | ||
29 | [042h 0066 2] Length : 0018 | ||
30 | |||
31 | [044h 0068 4] Endpoint start : 00000000 | ||
32 | [048h 0072 2] PCI Segment start : 0000 | ||
33 | [04Ah 0074 2] PCI Segment end : 0000 | ||
34 | [04Ch 0076 2] PCI BDF start : 0000 | ||
35 | [04Eh 0078 2] PCI BDF end : 00FF | ||
36 | [050h 0080 2] Output node : 0030 | ||
37 | [052h 0082 6] Reserved : 000000000000 | ||
38 | |||
39 | Acked-by: Ani Sinha <ani@anisinha.ca> | ||
40 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
41 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
42 | Message-id: 20211210170415.583179-9-jean-philippe@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 43 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 44 | --- |
10 | hw/net/imx_fec.c | 106 +++++++++++++++++++------------------------- | 45 | tests/qtest/bios-tables-test-allowed-diff.h | 1 - |
11 | hw/net/trace-events | 18 ++++++++ | 46 | tests/data/acpi/virt/VIOT | Bin 0 -> 88 bytes |
12 | 2 files changed, 63 insertions(+), 61 deletions(-) | 47 | 2 files changed, 1 deletion(-) |
13 | 48 | ||
14 | diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c | 49 | diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h |
15 | index XXXXXXX..XXXXXXX 100644 | 50 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/net/imx_fec.c | 51 | --- a/tests/qtest/bios-tables-test-allowed-diff.h |
17 | +++ b/hw/net/imx_fec.c | 52 | +++ b/tests/qtest/bios-tables-test-allowed-diff.h |
18 | @@ -XXX,XX +XXX,XX @@ | 53 | @@ -1,2 +1 @@ |
19 | #include "qemu/module.h" | 54 | /* List of comma-separated changed AML files to ignore */ |
20 | #include "net/checksum.h" | 55 | -"tests/data/acpi/virt/VIOT", |
21 | #include "net/eth.h" | 56 | diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT |
22 | +#include "trace.h" | ||
23 | |||
24 | /* For crc32 */ | ||
25 | #include <zlib.h> | ||
26 | |||
27 | -#ifndef DEBUG_IMX_FEC | ||
28 | -#define DEBUG_IMX_FEC 0 | ||
29 | -#endif | ||
30 | - | ||
31 | -#define FEC_PRINTF(fmt, args...) \ | ||
32 | - do { \ | ||
33 | - if (DEBUG_IMX_FEC) { \ | ||
34 | - fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_FEC, \ | ||
35 | - __func__, ##args); \ | ||
36 | - } \ | ||
37 | - } while (0) | ||
38 | - | ||
39 | -#ifndef DEBUG_IMX_PHY | ||
40 | -#define DEBUG_IMX_PHY 0 | ||
41 | -#endif | ||
42 | - | ||
43 | -#define PHY_PRINTF(fmt, args...) \ | ||
44 | - do { \ | ||
45 | - if (DEBUG_IMX_PHY) { \ | ||
46 | - fprintf(stderr, "[%s.phy]%s: " fmt , TYPE_IMX_FEC, \ | ||
47 | - __func__, ##args); \ | ||
48 | - } \ | ||
49 | - } while (0) | ||
50 | - | ||
51 | #define IMX_MAX_DESC 1024 | ||
52 | |||
53 | static const char *imx_default_reg_name(IMXFECState *s, uint32_t index) | ||
54 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_update(IMXFECState *s); | ||
55 | * For now we don't handle any GPIO/interrupt line, so the OS will | ||
56 | * have to poll for the PHY status. | ||
57 | */ | ||
58 | -static void phy_update_irq(IMXFECState *s) | ||
59 | +static void imx_phy_update_irq(IMXFECState *s) | ||
60 | { | ||
61 | imx_eth_update(s); | ||
62 | } | ||
63 | |||
64 | -static void phy_update_link(IMXFECState *s) | ||
65 | +static void imx_phy_update_link(IMXFECState *s) | ||
66 | { | ||
67 | /* Autonegotiation status mirrors link status. */ | ||
68 | if (qemu_get_queue(s->nic)->link_down) { | ||
69 | - PHY_PRINTF("link is down\n"); | ||
70 | + trace_imx_phy_update_link("down"); | ||
71 | s->phy_status &= ~0x0024; | ||
72 | s->phy_int |= PHY_INT_DOWN; | ||
73 | } else { | ||
74 | - PHY_PRINTF("link is up\n"); | ||
75 | + trace_imx_phy_update_link("up"); | ||
76 | s->phy_status |= 0x0024; | ||
77 | s->phy_int |= PHY_INT_ENERGYON; | ||
78 | s->phy_int |= PHY_INT_AUTONEG_COMPLETE; | ||
79 | } | ||
80 | - phy_update_irq(s); | ||
81 | + imx_phy_update_irq(s); | ||
82 | } | ||
83 | |||
84 | static void imx_eth_set_link(NetClientState *nc) | ||
85 | { | ||
86 | - phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc))); | ||
87 | + imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc))); | ||
88 | } | ||
89 | |||
90 | -static void phy_reset(IMXFECState *s) | ||
91 | +static void imx_phy_reset(IMXFECState *s) | ||
92 | { | ||
93 | + trace_imx_phy_reset(); | ||
94 | + | ||
95 | s->phy_status = 0x7809; | ||
96 | s->phy_control = 0x3000; | ||
97 | s->phy_advertise = 0x01e1; | ||
98 | s->phy_int_mask = 0; | ||
99 | s->phy_int = 0; | ||
100 | - phy_update_link(s); | ||
101 | + imx_phy_update_link(s); | ||
102 | } | ||
103 | |||
104 | -static uint32_t do_phy_read(IMXFECState *s, int reg) | ||
105 | +static uint32_t imx_phy_read(IMXFECState *s, int reg) | ||
106 | { | ||
107 | uint32_t val; | ||
108 | |||
109 | @@ -XXX,XX +XXX,XX @@ static uint32_t do_phy_read(IMXFECState *s, int reg) | ||
110 | case 29: /* Interrupt source. */ | ||
111 | val = s->phy_int; | ||
112 | s->phy_int = 0; | ||
113 | - phy_update_irq(s); | ||
114 | + imx_phy_update_irq(s); | ||
115 | break; | ||
116 | case 30: /* Interrupt mask */ | ||
117 | val = s->phy_int_mask; | ||
118 | @@ -XXX,XX +XXX,XX @@ static uint32_t do_phy_read(IMXFECState *s, int reg) | ||
119 | break; | ||
120 | } | ||
121 | |||
122 | - PHY_PRINTF("read 0x%04x @ %d\n", val, reg); | ||
123 | + trace_imx_phy_read(val, reg); | ||
124 | |||
125 | return val; | ||
126 | } | ||
127 | |||
128 | -static void do_phy_write(IMXFECState *s, int reg, uint32_t val) | ||
129 | +static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) | ||
130 | { | ||
131 | - PHY_PRINTF("write 0x%04x @ %d\n", val, reg); | ||
132 | + trace_imx_phy_write(val, reg); | ||
133 | |||
134 | if (reg > 31) { | ||
135 | /* we only advertise one phy */ | ||
136 | @@ -XXX,XX +XXX,XX @@ static void do_phy_write(IMXFECState *s, int reg, uint32_t val) | ||
137 | switch (reg) { | ||
138 | case 0: /* Basic Control */ | ||
139 | if (val & 0x8000) { | ||
140 | - phy_reset(s); | ||
141 | + imx_phy_reset(s); | ||
142 | } else { | ||
143 | s->phy_control = val & 0x7980; | ||
144 | /* Complete autonegotiation immediately. */ | ||
145 | @@ -XXX,XX +XXX,XX @@ static void do_phy_write(IMXFECState *s, int reg, uint32_t val) | ||
146 | break; | ||
147 | case 30: /* Interrupt mask */ | ||
148 | s->phy_int_mask = val & 0xff; | ||
149 | - phy_update_irq(s); | ||
150 | + imx_phy_update_irq(s); | ||
151 | break; | ||
152 | case 17: | ||
153 | case 18: | ||
154 | @@ -XXX,XX +XXX,XX @@ static void do_phy_write(IMXFECState *s, int reg, uint32_t val) | ||
155 | static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr) | ||
156 | { | ||
157 | dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd)); | ||
158 | + | ||
159 | + trace_imx_fec_read_bd(addr, bd->flags, bd->length, bd->data); | ||
160 | } | ||
161 | |||
162 | static void imx_fec_write_bd(IMXFECBufDesc *bd, dma_addr_t addr) | ||
163 | @@ -XXX,XX +XXX,XX @@ static void imx_fec_write_bd(IMXFECBufDesc *bd, dma_addr_t addr) | ||
164 | static void imx_enet_read_bd(IMXENETBufDesc *bd, dma_addr_t addr) | ||
165 | { | ||
166 | dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd)); | ||
167 | + | ||
168 | + trace_imx_enet_read_bd(addr, bd->flags, bd->length, bd->data, | ||
169 | + bd->option, bd->status); | ||
170 | } | ||
171 | |||
172 | static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr) | ||
173 | @@ -XXX,XX +XXX,XX @@ static void imx_fec_do_tx(IMXFECState *s) | ||
174 | int len; | ||
175 | |||
176 | imx_fec_read_bd(&bd, addr); | ||
177 | - FEC_PRINTF("tx_bd %x flags %04x len %d data %08x\n", | ||
178 | - addr, bd.flags, bd.length, bd.data); | ||
179 | if ((bd.flags & ENET_BD_R) == 0) { | ||
180 | + | ||
181 | /* Run out of descriptors to transmit. */ | ||
182 | - FEC_PRINTF("tx_bd ran out of descriptors to transmit\n"); | ||
183 | + trace_imx_eth_tx_bd_busy(); | ||
184 | + | ||
185 | break; | ||
186 | } | ||
187 | len = bd.length; | ||
188 | @@ -XXX,XX +XXX,XX @@ static void imx_enet_do_tx(IMXFECState *s, uint32_t index) | ||
189 | int len; | ||
190 | |||
191 | imx_enet_read_bd(&bd, addr); | ||
192 | - FEC_PRINTF("tx_bd %x flags %04x len %d data %08x option %04x " | ||
193 | - "status %04x\n", addr, bd.flags, bd.length, bd.data, | ||
194 | - bd.option, bd.status); | ||
195 | if ((bd.flags & ENET_BD_R) == 0) { | ||
196 | /* Run out of descriptors to transmit. */ | ||
197 | + | ||
198 | + trace_imx_eth_tx_bd_busy(); | ||
199 | + | ||
200 | break; | ||
201 | } | ||
202 | len = bd.length; | ||
203 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_enable_rx(IMXFECState *s, bool flush) | ||
204 | s->regs[ENET_RDAR] = (bd.flags & ENET_BD_E) ? ENET_RDAR_RDAR : 0; | ||
205 | |||
206 | if (!s->regs[ENET_RDAR]) { | ||
207 | - FEC_PRINTF("RX buffer full\n"); | ||
208 | + trace_imx_eth_rx_bd_full(); | ||
209 | } else if (flush) { | ||
210 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); | ||
211 | } | ||
212 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_reset(DeviceState *d) | ||
213 | memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor)); | ||
214 | |||
215 | /* We also reset the PHY */ | ||
216 | - phy_reset(s); | ||
217 | + imx_phy_reset(s); | ||
218 | } | ||
219 | |||
220 | static uint32_t imx_default_read(IMXFECState *s, uint32_t index) | ||
221 | @@ -XXX,XX +XXX,XX @@ static uint64_t imx_eth_read(void *opaque, hwaddr offset, unsigned size) | ||
222 | break; | ||
223 | } | ||
224 | |||
225 | - FEC_PRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_eth_reg_name(s, index), | ||
226 | - value); | ||
227 | + trace_imx_eth_read(index, imx_eth_reg_name(s, index), value); | ||
228 | |||
229 | return value; | ||
230 | } | ||
231 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, | ||
232 | const bool single_tx_ring = !imx_eth_is_multi_tx_ring(s); | ||
233 | uint32_t index = offset >> 2; | ||
234 | |||
235 | - FEC_PRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_eth_reg_name(s, index), | ||
236 | - (uint32_t)value); | ||
237 | + trace_imx_eth_write(index, imx_eth_reg_name(s, index), value); | ||
238 | |||
239 | switch (index) { | ||
240 | case ENET_EIR: | ||
241 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, | ||
242 | if (extract32(value, 29, 1)) { | ||
243 | /* This is a read operation */ | ||
244 | s->regs[ENET_MMFR] = deposit32(s->regs[ENET_MMFR], 0, 16, | ||
245 | - do_phy_read(s, | ||
246 | + imx_phy_read(s, | ||
247 | extract32(value, | ||
248 | 18, 10))); | ||
249 | } else { | ||
250 | /* This a write operation */ | ||
251 | - do_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16)); | ||
252 | + imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16)); | ||
253 | } | ||
254 | /* raise the interrupt as the PHY operation is done */ | ||
255 | s->regs[ENET_EIR] |= ENET_INT_MII; | ||
256 | @@ -XXX,XX +XXX,XX @@ static bool imx_eth_can_receive(NetClientState *nc) | ||
257 | { | ||
258 | IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc)); | ||
259 | |||
260 | - FEC_PRINTF("\n"); | ||
261 | - | ||
262 | return !!s->regs[ENET_RDAR]; | ||
263 | } | ||
264 | |||
265 | @@ -XXX,XX +XXX,XX @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, | ||
266 | unsigned int buf_len; | ||
267 | size_t size = len; | ||
268 | |||
269 | - FEC_PRINTF("len %d\n", (int)size); | ||
270 | + trace_imx_fec_receive(size); | ||
271 | |||
272 | if (!s->regs[ENET_RDAR]) { | ||
273 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Unexpected packet\n", | ||
274 | @@ -XXX,XX +XXX,XX @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, | ||
275 | bd.length = buf_len; | ||
276 | size -= buf_len; | ||
277 | |||
278 | - FEC_PRINTF("rx_bd 0x%x length %d\n", addr, bd.length); | ||
279 | + trace_imx_fec_receive_len(addr, bd.length); | ||
280 | |||
281 | /* The last 4 bytes are the CRC. */ | ||
282 | if (size < 4) { | ||
283 | @@ -XXX,XX +XXX,XX @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, | ||
284 | if (size == 0) { | ||
285 | /* Last buffer in frame. */ | ||
286 | bd.flags |= flags | ENET_BD_L; | ||
287 | - FEC_PRINTF("rx frame flags %04x\n", bd.flags); | ||
288 | + | ||
289 | + trace_imx_fec_receive_last(bd.flags); | ||
290 | + | ||
291 | s->regs[ENET_EIR] |= ENET_INT_RXF; | ||
292 | } else { | ||
293 | s->regs[ENET_EIR] |= ENET_INT_RXB; | ||
294 | @@ -XXX,XX +XXX,XX @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, | ||
295 | size_t size = len; | ||
296 | bool shift16 = s->regs[ENET_RACC] & ENET_RACC_SHIFT16; | ||
297 | |||
298 | - FEC_PRINTF("len %d\n", (int)size); | ||
299 | + trace_imx_enet_receive(size); | ||
300 | |||
301 | if (!s->regs[ENET_RDAR]) { | ||
302 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Unexpected packet\n", | ||
303 | @@ -XXX,XX +XXX,XX @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, | ||
304 | bd.length = buf_len; | ||
305 | size -= buf_len; | ||
306 | |||
307 | - FEC_PRINTF("rx_bd 0x%x length %d\n", addr, bd.length); | ||
308 | + trace_imx_enet_receive_len(addr, bd.length); | ||
309 | |||
310 | /* The last 4 bytes are the CRC. */ | ||
311 | if (size < 4) { | ||
312 | @@ -XXX,XX +XXX,XX @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, | ||
313 | if (size == 0) { | ||
314 | /* Last buffer in frame. */ | ||
315 | bd.flags |= flags | ENET_BD_L; | ||
316 | - FEC_PRINTF("rx frame flags %04x\n", bd.flags); | ||
317 | + | ||
318 | + trace_imx_enet_receive_last(bd.flags); | ||
319 | + | ||
320 | /* Indicate that we've updated the last buffer descriptor. */ | ||
321 | bd.last_buffer = ENET_BD_BDU; | ||
322 | if (bd.option & ENET_BD_RX_INT) { | ||
323 | diff --git a/hw/net/trace-events b/hw/net/trace-events | ||
324 | index XXXXXXX..XXXXXXX 100644 | 57 | index XXXXXXX..XXXXXXX 100644 |
325 | --- a/hw/net/trace-events | 58 | GIT binary patch |
326 | +++ b/hw/net/trace-events | 59 | literal 88 |
327 | @@ -XXX,XX +XXX,XX @@ i82596_receive_packet(size_t sz) "len=%zu" | 60 | zcmWIZ^bd((0D?3pe`k+i1*eDrX9XZ&1PX!JAexE60Hgv8m>C3sGzXN&z`)2L0cSHX |
328 | i82596_new_mac(const char *id_with_mac) "New MAC for: %s" | 61 | I{D-Rq0Q5fy0RR91 |
329 | i82596_set_multicast(uint16_t count) "Added %d multicast entries" | 62 | |
330 | i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION" | 63 | literal 0 |
331 | + | 64 | HcmV?d00001 |
332 | +# imx_fec.c | 65 | |
333 | +imx_phy_read(uint32_t val, int reg) "0x%04"PRIx32" <= reg[%d]" | ||
334 | +imx_phy_write(uint32_t val, int reg) "0x%04"PRIx32" => reg[%d]" | ||
335 | +imx_phy_update_link(const char *s) "%s" | ||
336 | +imx_phy_reset(void) "" | ||
337 | +imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x" | ||
338 | +imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x" | ||
339 | +imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit" | ||
340 | +imx_eth_rx_bd_full(void) "RX buffer is full" | ||
341 | +imx_eth_read(int reg, const char *reg_name, uint32_t value) "reg[%d:%s] => 0x%08"PRIx32 | ||
342 | +imx_eth_write(int reg, const char *reg_name, uint64_t value) "reg[%d:%s] <= 0x%08"PRIx64 | ||
343 | +imx_fec_receive(size_t size) "len %zu" | ||
344 | +imx_fec_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d" | ||
345 | +imx_fec_receive_last(int last) "rx frame flags 0x%04x" | ||
346 | +imx_enet_receive(size_t size) "len %zu" | ||
347 | +imx_enet_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d" | ||
348 | +imx_enet_receive_last(int last) "rx frame flags 0x%04x" | ||
349 | -- | 66 | -- |
350 | 2.20.1 | 67 | 2.25.1 |
351 | 68 | ||
352 | 69 | diff view generated by jsdifflib |