Series comparison

-[PULL 00/29] target-arm queue
+[PULL 00/24] target-arm queue
-Arm queue; some of the simpler stuff, things other have reviewed (thanks!), etc.
+The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:
--- PMM
+  Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)
 The following changes since commit 5d2f557b47dfbf8f23277a5bdd8473d4607c681a:
   Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200605-pull-request' into staging (2020-06-05 13:53:05 +0100)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200605
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702
-for you to fetch changes up to 2c35a39eda0b16c2ed85c94cec204bf5efb97812:
+for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
-  target/arm: Convert Neon one-register-and-immediate insns to decodetree (2020-06-05 17:23:10 +0100)
+  target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- hw/ssi/imx_spi: Handle tx burst lengths other than 8 correctly
+ * more MVE instructions
- hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()
+ * hw/gpio/gpio_pwr: use shutdown function for reboot
- hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()
+ * target/arm: Check NaN mode before silencing NaN
- target/arm: Convert crypto insns to gvec
+ * tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
- hw/adc/stm32f2xx_adc: Correct memory region size and access size
+ * hw/arm: Add basic power management to raspi.
- tests/acceptance: Add a boot test for the xlnx-versal-virt machine
+ * docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
  docs/system: Document Aspeed boards
  raspi: Add model of the USB controller
  target/arm: Convert 2-reg-and-shift and 1-reg-imm Neon insns to decodetree
 ----------------------------------------------------------------
-Cédric Le Goater (1):
+Joe Komlodi (1):
-      docs/system: Document Aspeed boards
+      target/arm: Check NaN mode before silencing NaN
-Eden Mikitas (2):
+Maxim Uvarov (1):
-      hw/ssi/imx_spi: changed while statement to prevent underflow
+      hw/gpio/gpio_pwr: use shutdown function for reboot
       hw/ssi/imx_spi: Removed unnecessary cast of rx data received from slave
-Paul Zimmerman (7):
+Nolan Leake (1):
-      raspi: add BCM2835 SOC MPHI emulation
+      hw/arm: Add basic power management to raspi.
       dwc-hsotg (dwc2) USB host controller register definitions
       dwc-hsotg (dwc2) USB host controller state definitions
       dwc-hsotg (dwc2) USB host controller emulation
       usb: add short-packet handling to usb-storage driver
       wire in the dwc-hsotg (dwc2) USB host controller emulation
       raspi2 acceptance test: add test for dwc-hsotg (dwc2) USB host
-Peter Maydell (9):
+Patrick Venture (2):
-      target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree
+      docs/system/arm: Add quanta-q7l1-bmc reference
-      target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree
+      docs/system/arm: Add quanta-gbs-bmc reference
       target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree
       target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree
       target/arm: Convert Neon narrowing shifts with op==8 to decodetree
       target/arm: Convert Neon narrowing shifts with op==9 to decodetree
       target/arm: Convert Neon VSHLL, VMOVL to decodetree
       target/arm: Convert VCVT fixed-point ops to decodetree
       target/arm: Convert Neon one-register-and-immediate insns to decodetree
-Philippe Mathieu-Daudé (3):
+Peter Maydell (18):
-      hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()
+      target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
-      hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()
+      target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
-      hw/adc/stm32f2xx_adc: Correct memory region size and access size
+      target/arm: Make asimd_imm_const() public
       target/arm: Use asimd_imm_const for A64 decode
       target/arm: Use dup_const() instead of bitfield_replicate()
       target/arm: Implement MVE logical immediate insns
       target/arm: Implement MVE vector shift left by immediate insns
       target/arm: Implement MVE vector shift right by immediate insns
       target/arm: Implement MVE VSHLL
       target/arm: Implement MVE VSRI, VSLI
       target/arm: Implement MVE VSHRN, VRSHRN
       target/arm: Implement MVE saturating narrowing shifts
       target/arm: Implement MVE VSHLC
       target/arm: Implement MVE VADDLV
       target/arm: Implement MVE long shifts by immediate
       target/arm: Implement MVE long shifts by register
       target/arm: Implement MVE shifts by immediate
       target/arm: Implement MVE shifts by register
-Richard Henderson (6):
+Philippe Mathieu-Daudé (1):
-      target/arm: Convert aes and sm4 to gvec helpers
+      tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
       target/arm: Convert rax1 to gvec helpers
       target/arm: Convert sha512 and sm3 to gvec helpers
       target/arm: Convert sha1 and sha256 to gvec helpers
       target/arm: Split helper_crypto_sha1_3reg
       target/arm: Split helper_crypto_sm3tt
-Thomas Huth (1):
+ docs/system/arm/aspeed.rst             |   1 +
-      tests/acceptance: Add a boot test for the xlnx-versal-virt machine
+ docs/system/arm/nuvoton.rst            |   5 +-
  include/hw/arm/bcm2835_peripherals.h   |   3 +-
  include/hw/misc/bcm2835_powermgt.h     |  29 ++
  target/arm/helper-mve.h                | 108 +++++++
  target/arm/translate.h                 |  41 +++
  target/arm/mve.decode                  | 177 ++++++++++-
  target/arm/t32.decode                  |  71 ++++-
  hw/arm/bcm2835_peripherals.c           |  13 +-
  hw/gpio/gpio_pwr.c                     |   2 +-
  hw/misc/bcm2835_powermgt.c             | 160 ++++++++++
  target/arm/helper-a64.c                |  12 +-
  target/arm/mve_helper.c                | 524 +++++++++++++++++++++++++++++++--
  target/arm/translate-a64.c             |  86 +-----
  target/arm/translate-mve.c             | 261 +++++++++++++++-
  target/arm/translate-neon.c            |  81 -----
  target/arm/translate.c                 | 327 +++++++++++++++++++-
  target/arm/vfp_helper.c                |  24 +-
  hw/misc/meson.build                    |   1 +
  tests/acceptance/boot_linux_console.py |  43 +++
 files changed, 1760 insertions(+), 209 deletions(-)
  create mode 100644 include/hw/misc/bcm2835_powermgt.h
  create mode 100644 hw/misc/bcm2835_powermgt.c
- docs/system/arm/aspeed.rst             |   85 ++
- docs/system/target-arm.rst             |    1 +
- hw/usb/hcd-dwc2.h                      |  190 +++++
- include/hw/arm/bcm2835_peripherals.h   |    5 +-
- include/hw/misc/bcm2835_mphi.h         |   44 +
- include/hw/usb/dwc2-regs.h             |  899 ++++++++++++++++++++
- target/arm/helper.h                    |   45 +-
- target/arm/translate-a64.h             |    3 +
- target/arm/vec_internal.h              |   33 +
- target/arm/neon-dp.decode              |  214 ++++-
- hw/adc/stm32f2xx_adc.c                 |    4 +-
- hw/arm/bcm2835_peripherals.c           |   38 +-
- hw/arm/pxa2xx.c                        |   66 +-
- hw/input/pxa2xx_keypad.c               |   10 +-
- hw/misc/bcm2835_mphi.c                 |  191 +++++
- hw/ssi/imx_spi.c                       |    4 +-
- hw/usb/dev-storage.c                   |   15 +-
- hw/usb/hcd-dwc2.c                      | 1417 ++++++++++++++++++++++++++++++++
- target/arm/crypto_helper.c             |  267 ++++--
- target/arm/translate-a64.c             |  198 ++---
- target/arm/translate-neon.inc.c        |  796 ++++++++++++++----
- target/arm/translate.c                 |  539 +-----------
- target/arm/vec_helper.c                |   12 +-
- hw/misc/Makefile.objs                  |    1 +
- hw/usb/Kconfig                         |    5 +
- hw/usb/Makefile.objs                   |    1 +
- hw/usb/trace-events                    |   50 ++
- tests/acceptance/boot_linux_console.py |   35 +-
-files changed, 4258 insertions(+), 910 deletions(-)
- create mode 100644 docs/system/arm/aspeed.rst
- create mode 100644 hw/usb/hcd-dwc2.h
- create mode 100644 include/hw/misc/bcm2835_mphi.h
- create mode 100644 include/hw/usb/dwc2-regs.h
- create mode 100644 target/arm/vec_internal.h
- create mode 100644 hw/misc/bcm2835_mphi.c
- create mode 100644 hw/usb/hcd-dwc2.c

-[PULL 01/29] hw/ssi/imx_spi: changed while statement to prevent underflow
+Deleted patch
-From: Eden Mikitas <e.mikitas@gmail.com>
-The while statement in question only checked if tx_burst is not 0.
-tx_burst is a signed int, which is assigned the value put by the
-guest driver in ECSPI_CONREG. The burst length can be anywhere
-between 1 and 4096, and since tx_burst is always decremented by 8
-it could possibly underflow, causing an infinite loop.
-Signed-off-by: Eden Mikitas <e.mikitas@gmail.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/ssi/imx_spi.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/ssi/imx_spi.c
-+++ b/hw/ssi/imx_spi.c
-@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
-         rx = 0;
--        while (tx_burst) {
-+        while (tx_burst > 0) {
-             uint8_t byte = tx & 0xff;
-             DPRINTF("writing 0x%02x\n", (uint32_t)byte);
---
-.20.1

-[PULL 02/29] hw/ssi/imx_spi: Removed unnecessary cast of rx data received from slave
+Deleted patch
-From: Eden Mikitas <e.mikitas@gmail.com>
-When inserting the value retrieved (rx) from the spi slave, rx is pushed to
-rx_fifo after being cast to uint8_t. rx_fifo is a fifo32, and the rx
-register the driver uses is also 32 bit. This zeroes the 24 most
-significant bits of rx. This proved problematic with devices that expect to
-use the whole 32 bits of the rx register.
-Signed-off-by: Eden Mikitas <e.mikitas@gmail.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/ssi/imx_spi.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/ssi/imx_spi.c
-+++ b/hw/ssi/imx_spi.c
-@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
-         if (fifo32_is_full(&s->rx_fifo)) {
-             s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RO;
-         } else {
--            fifo32_push(&s->rx_fifo, (uint8_t)rx);
-+            fifo32_push(&s->rx_fifo, rx);
-         }
-         if (s->burst_length <= 0) {
---
-.20.1

-[PULL 13/29] docs/system: Document Aspeed boards
+[PULL 01/24] docs/system/arm: Add quanta-q7l1-bmc reference
-From: Cédric Le Goater <clg@kaod.org>
+From: Patrick Venture <venture@google.com>
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
+Adds a line-item reference to the supported quanta-q71l-bmc aspeed
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+entry.
-Message-id: 20200602135050.593692-1-clg@kaod.org
 Signed-off-by: Patrick Venture <venture@google.com>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Message-id: 20210615192848.1065297-2-venture@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/system/arm/aspeed.rst | 85 ++++++++++++++++++++++++++++++++++++++
+ docs/system/arm/aspeed.rst | 1 +
- docs/system/target-arm.rst |  1 +
+file changed, 1 insertion(+)
 files changed, 86 insertions(+)
  create mode 100644 docs/system/arm/aspeed.rst
 diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
-new file mode 100644
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX
+--- a/docs/system/arm/aspeed.rst
 --- /dev/null
 +++ b/docs/system/arm/aspeed.rst
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ etc.
-+Aspeed family boards (``*-bmc``, ``ast2500-evb``, ``ast2600-evb``)
+ AST2400 SoC based machines :
-+==================================================================
-+
+ - ``palmetto-bmc``         OpenPOWER Palmetto POWER8 BMC
-+The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
++- ``quanta-q71l-bmc``      OpenBMC Quanta BMC
-+Aspeed evaluation boards. They are based on different releases of the
-+Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the
+ AST2500 SoC based machines :
-+AST2500 with an ARM1176JZS CPU (800MHz) and more recently the AST2600
 +with dual cores ARM Cortex A7 CPUs (1.2GHz).
 +
 +The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C,
 +etc.
 +
 +AST2400 SoC based machines :
 +
 +- ``palmetto-bmc``         OpenPOWER Palmetto POWER8 BMC
 +
 +AST2500 SoC based machines :
 +
 +- ``ast2500-evb``          Aspeed AST2500 Evaluation board
 +- ``romulus-bmc``          OpenPOWER Romulus POWER9 BMC
 +- ``witherspoon-bmc``      OpenPOWER Witherspoon POWER9 BMC
 +- ``sonorapass-bmc``       OCP SonoraPass BMC
 +- ``swift-bmc``            OpenPOWER Swift BMC POWER9
 +
 +AST2600 SoC based machines :
 +
 +- ``ast2600-evb``          Aspeed AST2600 Evaluation board (Cortex A7)
 +- ``tacoma-bmc``           OpenPOWER Witherspoon POWER9 AST2600 BMC
 +
 +Supported devices
 +-----------------
 +
 + * SMP (for the AST2600 Cortex-A7)
 + * Interrupt Controller (VIC)
 + * Timer Controller
 + * RTC Controller
 + * I2C Controller
 + * System Control Unit (SCU)
 + * SRAM mapping
 + * X-DMA Controller (basic interface)
 + * Static Memory Controller (SMC or FMC) - Only SPI Flash support
 + * SPI Memory Controller
 + * USB 2.0 Controller
 + * SD/MMC storage controllers
 + * SDRAM controller (dummy interface for basic settings and training)
 + * Watchdog Controller
 + * GPIO Controller (Master only)
 + * UART
 + * Ethernet controllers
 +
 +
 +Missing devices
 +---------------
 +
 + * Coprocessor support
 + * ADC (out of tree implementation)
 + * PWM and Fan Controller
 + * LPC Bus Controller
 + * Slave GPIO Controller
 + * Super I/O Controller
 + * Hash/Crypto Engine
 + * PCI-Express 1 Controller
 + * Graphic Display Controller
 + * PECI Controller
 + * MCTP Controller
 + * Mailbox Controller
 + * Virtual UART
 + * eSPI Controller
 + * I3C Controller
 +
 +Boot options
 +------------
 +
 +The Aspeed machines can be started using the -kernel option to load a
 +Linux kernel or from a firmare image which can be downloaded from the
 +OpenPOWER jenkins :
 +
 +   https://openpower.xyz/
 +
 +The image should be attached as an MTD drive. Run :
 +
 +.. code-block:: bash
 +
 +  $ qemu-system-arm -M romulus-bmc -nic user \
 +    -drive file=flash-romulus,format=raw,if=mtd -nographic
 diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/target-arm.rst
 +++ b/docs/system/target-arm.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
     arm/realview
     arm/versatile
     arm/vexpress
 +   arm/aspeed
     arm/musicpal
     arm/nseries
     arm/orangepi
 --
 .20.1

-[PULL 20/29] raspi2 acceptance test: add test for dwc-hsotg (dwc2) USB host
+[PULL 02/24] docs/system/arm: Add quanta-gbs-bmc reference
-From: Paul Zimmerman <pauldzim@gmail.com>
+From: Patrick Venture <venture@google.com>
-Add a check for functional dwc-hsotg (dwc2) USB host emulation to
+Add line item reference to quanta-gbs-bmc machine.
 the Raspi 2 acceptance test
-Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
+Signed-off-by: Patrick Venture <venture@google.com>
-Reviewed-by: Philippe Mathieu-Daude <f4bug@amsat.org>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Message-id: 20200520235349.21215-8-pauldzim@gmail.com
+Message-id: 20210615192848.1065297-3-venture@google.com
 [PMM: fixed underline Sphinx warning]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- tests/acceptance/boot_linux_console.py | 9 +++++++--
+ docs/system/arm/nuvoton.rst | 5 +++--
-file changed, 7 insertions(+), 2 deletions(-)
+file changed, 3 insertions(+), 2 deletions(-)
-diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
+diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
 index XXXXXXX..XXXXXXX 100644
---- a/tests/acceptance/boot_linux_console.py
+--- a/docs/system/arm/nuvoton.rst
-+++ b/tests/acceptance/boot_linux_console.py
++++ b/docs/system/arm/nuvoton.rst
-@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(LinuxKernelTest):
+@@ -XXX,XX +XXX,XX @@
+-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
-         self.vm.set_console()
+-=====================================================
-         kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
++Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
--                               serial_kernel_cmdline[uart_id])
++================================================================
-+                               serial_kernel_cmdline[uart_id] +
-+                               ' root=/dev/mmcblk0p2 rootwait ' +
+ The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
-+                               'dwc_otg.fiq_fsm_enable=0')
+ designed to be used as Baseboard Management Controllers (BMCs) in various
-         self.vm.add_args('-kernel', kernel_path,
+@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
-                          '-dtb', dtb_path,
+ The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
--                         '-append', kernel_command_line)
+ Hyperscale applications. The following machines are based on this chip :
-+                         '-append', kernel_command_line,
-+                         '-device', 'usb-kbd')
++- ``quanta-gbs-bmc``    Quanta GBS server BMC
-         self.vm.launch()
+ - ``quanta-gsj``        Quanta GSJ server BMC
-         console_pattern = 'Kernel command line: %s' % kernel_command_line
-         self.wait_for_console_pattern(console_pattern)
+ There are also two more SoCs, NPCM710 and NPCM705, which are single-core
 +        console_pattern = 'Product: QEMU USB Keyboard'
 +        self.wait_for_console_pattern(console_pattern)
      def test_arm_raspi2_uart0(self):
          """
 --
 .20.1

-[PULL 14/29] raspi: add BCM2835 SOC MPHI emulation
+[PULL 03/24] hw/arm: Add basic power management to raspi.
-From: Paul Zimmerman <pauldzim@gmail.com>
+From: Nolan Leake <nolan@sigbus.net>
-Add BCM2835 SOC MPHI (Message-based Parallel Host Interface)
+This is just enough to make reboot and poweroff work. Works for
-emulation. It is very basic, only providing the FIQ interrupt
+linux, u-boot, and the arm trusted firmware. Not tested, but should
-needed to allow the dwc-otg USB host controller driver in the
+work for plan9, and bare-metal/hobby OSes, since they seem to generally
-Raspbian kernel to function.
+do what linux does for reset.
-Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
+The watchdog timer functionality is not yet implemented.
-Acked-by: Philippe Mathieu-Daude <f4bug@amsat.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
-Message-id: 20200520235349.21215-2-pauldzim@gmail.com
+Signed-off-by: Nolan Leake <nolan@sigbus.net>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20210625210209.1870217-1-nolan@sigbus.net
 [PMM: tweaked commit title; fixed region size to 0x200;
  moved header file to include/]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/bcm2835_peripherals.h |   2 +
+ include/hw/arm/bcm2835_peripherals.h |   3 +-
- include/hw/misc/bcm2835_mphi.h       |  44 ++++++
+ include/hw/misc/bcm2835_powermgt.h   |  29 +++++
- hw/arm/bcm2835_peripherals.c         |  17 +++
+ hw/arm/bcm2835_peripherals.c         |  13 ++-
- hw/misc/bcm2835_mphi.c               | 191 +++++++++++++++++++++++++++
+ hw/misc/bcm2835_powermgt.c           | 160 +++++++++++++++++++++++++++
- hw/misc/Makefile.objs                |   1 +
+ hw/misc/meson.build                  |   1 +
-files changed, 255 insertions(+)
+files changed, 204 insertions(+), 2 deletions(-)
- create mode 100644 include/hw/misc/bcm2835_mphi.h
+ create mode 100644 include/hw/misc/bcm2835_powermgt.h
- create mode 100644 hw/misc/bcm2835_mphi.c
+ create mode 100644 hw/misc/bcm2835_powermgt.c
 diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/bcm2835_peripherals.h
 +++ b/include/hw/arm/bcm2835_peripherals.h
 @@ -XXX,XX +XXX,XX @@
- #include "hw/misc/bcm2835_property.h"
+ #include "hw/misc/bcm2835_mphi.h"
  #include "hw/misc/bcm2835_rng.h"
  #include "hw/misc/bcm2835_mbox.h"
 +#include "hw/misc/bcm2835_mphi.h"
  #include "hw/misc/bcm2835_thermal.h"
+ #include "hw/misc/bcm2835_cprman.h"
++#include "hw/misc/bcm2835_powermgt.h"
  #include "hw/sd/sdhci.h"
  #include "hw/sd/bcm2835_sdhost.h"
-@@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState {
+ #include "hw/gpio/bcm2835_gpio.h"
-     qemu_irq irq, fiq;
+@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
+     BCM2835MphiState mphi;
-     BCM2835SystemTimerState systmr;
+     UnimplementedDeviceState txp;
 +    BCM2835MphiState mphi;
      UnimplementedDeviceState armtmr;
-     UnimplementedDeviceState cprman;
+-    UnimplementedDeviceState powermgt;
-     UnimplementedDeviceState a2w;
++    BCM2835PowerMgtState powermgt;
-diff --git a/include/hw/misc/bcm2835_mphi.h b/include/hw/misc/bcm2835_mphi.h
+     BCM2835CprmanState cprman;
      PL011State uart0;
      BCM2835AuxState aux;
 diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/include/hw/misc/bcm2835_mphi.h
++++ b/include/hw/misc/bcm2835_powermgt.h
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * BCM2835 SOC MPHI state definitions
++ * BCM2835 Power Management emulation
 + *
-+ * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
++ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
-+ *
++ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
-+ * This program is free software; you can redistribute it and/or modify
++ *
-+ * it under the terms of the GNU General Public License as published by
++ * This work is licensed under the terms of the GNU GPL, version 2 or later.
-+ * the Free Software Foundation; either version 2 of the License, or
++ * See the COPYING file in the top-level directory.
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 + * GNU General Public License for more details.
 + */
 +
-+#ifndef HW_MISC_BCM2835_MPHI_H
++#ifndef BCM2835_POWERMGT_H
-+#define HW_MISC_BCM2835_MPHI_H
++#define BCM2835_POWERMGT_H
 +
 +#include "hw/irq.h"
 +#include "hw/sysbus.h"
-+
++#include "qom/object.h"
-+#define MPHI_MMIO_SIZE      0x1000
++
-+
++#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
-+typedef struct BCM2835MphiState BCM2835MphiState;
++OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
 +
-+struct BCM2835MphiState {
++struct BCM2835PowerMgtState {
-+    SysBusDevice parent_obj;
++    SysBusDevice busdev;
 +    qemu_irq irq;
 +    MemoryRegion iomem;
 +
-+    uint32_t outdda;
++    uint32_t rstc;
-+    uint32_t outddb;
++    uint32_t rsts;
-+    uint32_t ctrl;
++    uint32_t wdog;
-+    uint32_t intstat;
++};
 +    uint32_t swirq;
 +};
 +
 +#define TYPE_BCM2835_MPHI   "bcm2835-mphi"
 +
 +#define BCM2835_MPHI(obj) \
 +    OBJECT_CHECK(BCM2835MphiState, (obj), TYPE_BCM2835_MPHI)
 +
 +#endif
 diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/bcm2835_peripherals.c
 +++ b/hw/arm/bcm2835_peripherals.c
 @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
-                                    OBJECT(&s->sdhci.sdbus));
-     object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost",
+     object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
-                                    OBJECT(&s->sdhost.sdbus));
+                                    OBJECT(&s->gpu_bus_mr));
 +
-+    /* Mphi */
++    /* Power Management */
-+    sysbus_init_child_obj(obj, "mphi", &s->mphi, sizeof(s->mphi),
++    object_initialize_child(obj, "powermgt", &s->powermgt,
-+                          TYPE_BCM2835_MPHI);
++                            TYPE_BCM2835_POWERMGT);
  }
  static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
 @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
+         qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
-     object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus");
+                                INTERRUPT_USB));
-+    /* Mphi */
++    /* Power Management */
-+    object_property_set_bool(OBJECT(&s->mphi), true, "realized", &err);
++    if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
 +    if (err) {
 +        error_propagate(errp, err);
 +        return;
 +    }
 +
-+    memory_region_add_subregion(&s->peri_mr, MPHI_OFFSET,
++    memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
-+                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mphi), 0));
++                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
-+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->mphi), 0,
++
-+        qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
+     create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
 +                               INTERRUPT_HOSTPORT));
 +
      create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
-     create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
+-    create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
-     create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
+     create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
-diff --git a/hw/misc/bcm2835_mphi.c b/hw/misc/bcm2835_mphi.c
+     create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
      create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
 diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/misc/bcm2835_mphi.c
++++ b/hw/misc/bcm2835_powermgt.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * BCM2835 SOC MPHI emulation
++ * BCM2835 Power Management emulation
 + *
-+ * Very basic emulation, only providing the FIQ interrupt needed to
++ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
-+ * allow the dwc-otg USB host controller driver in the Raspbian kernel
++ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
-+ * to function.
++ *
-+ *
++ * This work is licensed under the terms of the GNU GPL, version 2 or later.
-+ * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
++ * See the COPYING file in the top-level directory.
 + *
 + * This program is free software; you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License as published by
 + * the Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 + * GNU General Public License for more details.
 + */
 +
 +#include "qemu/osdep.h"
-+#include "qapi/error.h"
++#include "qemu/log.h"
-+#include "hw/misc/bcm2835_mphi.h"
++#include "qemu/module.h"
 +#include "hw/misc/bcm2835_powermgt.h"
 +#include "migration/vmstate.h"
-+#include "qemu/error-report.h"
++#include "sysemu/runstate.h"
-+#include "qemu/log.h"
++
-+#include "qemu/main-loop.h"
++#define PASSWORD 0x5a000000
-+
++#define PASSWORD_MASK 0xff000000
-+static inline void mphi_raise_irq(BCM2835MphiState *s)
++
-+{
++#define R_RSTC 0x1c
-+    qemu_set_irq(s->irq, 1);
++#define V_RSTC_RESET 0x20
-+}
++#define R_RSTS 0x20
-+
++#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
-+static inline void mphi_lower_irq(BCM2835MphiState *s)
++#define R_WDOG 0x24
-+{
++
-+    qemu_set_irq(s->irq, 0);
++static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
-+}
++                                      unsigned size)
-+
++{
-+static uint64_t mphi_reg_read(void *ptr, hwaddr addr, unsigned size)
++    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
-+{
++    uint32_t res = 0;
-+    BCM2835MphiState *s = ptr;
++
-+    uint32_t val = 0;
++    switch (offset) {
-+
++    case R_RSTC:
-+    switch (addr) {
++        res = s->rstc;
-+    case 0x28:  /* outdda */
++        break;
-+        val = s->outdda;
++    case R_RSTS:
-+        break;
++        res = s->rsts;
-+    case 0x2c:  /* outddb */
++        break;
-+        val = s->outddb;
++    case R_WDOG:
-+        break;
++        res = s->wdog;
-+    case 0x4c:  /* ctrl */
++        break;
-+        val = s->ctrl;
++
 +        val |= 1 << 17;
 +        break;
 +    case 0x50:  /* intstat */
 +        val = s->intstat;
 +        break;
 +    case 0x1f0: /* swirq_set */
 +        val = s->swirq;
 +        break;
 +    case 0x1f4: /* swirq_clr */
 +        val = s->swirq;
 +        break;
 +    default:
-+        qemu_log_mask(LOG_UNIMP, "read from unknown register");
++        qemu_log_mask(LOG_UNIMP,
-+        break;
++                      "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
-+    }
++                      "\n", offset);
-+
++        res = 0;
-+    return val;
++        break;
-+}
++    }
 +
-+static void mphi_reg_write(void *ptr, hwaddr addr, uint64_t val, unsigned size)
++    return res;
-+{
++}
-+    BCM2835MphiState *s = ptr;
++
-+    int do_irq = 0;
++static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
-+
++                                   uint64_t value, unsigned size)
-+    switch (addr) {
++{
-+    case 0x28:  /* outdda */
++    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
-+        s->outdda = val;
++
-+        break;
++    if ((value & PASSWORD_MASK) != PASSWORD) {
-+    case 0x2c:  /* outddb */
++        qemu_log_mask(LOG_GUEST_ERROR,
-+        s->outddb = val;
++                      "bcm2835_powermgt_write: Bad password 0x%"PRIx64
-+        if (val & (1 << 29)) {
++                      " at offset 0x%08"HWADDR_PRIx"\n",
-+            do_irq = 1;
++                      value, offset);
 +        return;
 +    }
 +
 +    value = value & ~PASSWORD_MASK;
 +
 +    switch (offset) {
 +    case R_RSTC:
 +        s->rstc = value;
 +        if (value & V_RSTC_RESET) {
 +            if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
 +                qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 +            } else {
 +                qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 +            }
 +        }
 +        break;
-+    case 0x4c:  /* ctrl */
++    case R_RSTS:
-+        s->ctrl = val;
++        qemu_log_mask(LOG_UNIMP,
-+        if (val & (1 << 16)) {
++                      "bcm2835_powermgt_write: RSTS\n");
-+            do_irq = -1;
++        s->rsts = value;
-+        }
++        break;
-+        break;
++    case R_WDOG:
-+    case 0x50:  /* intstat */
++        qemu_log_mask(LOG_UNIMP,
-+        s->intstat = val;
++                      "bcm2835_powermgt_write: WDOG\n");
-+        if (val & ((1 << 16) | (1 << 29))) {
++        s->wdog = value;
-+            do_irq = -1;
++        break;
-+        }
++
 +        break;
 +    case 0x1f0: /* swirq_set */
 +        s->swirq |= val;
 +        do_irq = 1;
 +        break;
 +    case 0x1f4: /* swirq_clr */
 +        s->swirq &= ~val;
 +        do_irq = -1;
 +        break;
 +    default:
-+        qemu_log_mask(LOG_UNIMP, "write to unknown register");
++        qemu_log_mask(LOG_UNIMP,
-+        return;
++                      "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
-+    }
++                      "\n", offset);
-+
++        break;
-+    if (do_irq > 0) {
++    }
-+        mphi_raise_irq(s);
++}
-+    } else if (do_irq < 0) {
++
-+        mphi_lower_irq(s);
++static const MemoryRegionOps bcm2835_powermgt_ops = {
-+    }
++    .read = bcm2835_powermgt_read,
-+}
++    .write = bcm2835_powermgt_write,
-+
++    .endianness = DEVICE_NATIVE_ENDIAN,
 +static const MemoryRegionOps mphi_mmio_ops = {
 +    .read = mphi_reg_read,
 +    .write = mphi_reg_write,
 +    .impl.min_access_size = 4,
 +    .impl.max_access_size = 4,
-+    .endianness = DEVICE_LITTLE_ENDIAN,
++};
-+};
++
-+
++static const VMStateDescription vmstate_bcm2835_powermgt = {
-+static void mphi_reset(DeviceState *dev)
++    .name = TYPE_BCM2835_POWERMGT,
 +{
 +    BCM2835MphiState *s = BCM2835_MPHI(dev);
 +
 +    s->outdda = 0;
 +    s->outddb = 0;
 +    s->ctrl = 0;
 +    s->intstat = 0;
 +    s->swirq = 0;
 +}
 +
 +static void mphi_realize(DeviceState *dev, Error **errp)
 +{
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 +    BCM2835MphiState *s = BCM2835_MPHI(dev);
 +
 +    sysbus_init_irq(sbd, &s->irq);
 +}
 +
 +static void mphi_init(Object *obj)
 +{
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 +    BCM2835MphiState *s = BCM2835_MPHI(obj);
 +
 +    memory_region_init_io(&s->iomem, obj, &mphi_mmio_ops, s, "mphi", MPHI_MMIO_SIZE);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +}
 +
 +const VMStateDescription vmstate_mphi_state = {
 +    .name = "mphi",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
-+        VMSTATE_UINT32(outdda, BCM2835MphiState),
++        VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
-+        VMSTATE_UINT32(outddb, BCM2835MphiState),
++        VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
-+        VMSTATE_UINT32(ctrl, BCM2835MphiState),
++        VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
 +        VMSTATE_UINT32(intstat, BCM2835MphiState),
 +        VMSTATE_UINT32(swirq, BCM2835MphiState),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
-+static void mphi_class_init(ObjectClass *klass, void *data)
++static void bcm2835_powermgt_init(Object *obj)
 +{
 +    BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
 +
 +    memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
 +                          TYPE_BCM2835_POWERMGT, 0x200);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 +}
 +
 +static void bcm2835_powermgt_reset(DeviceState *dev)
 +{
 +    BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
 +
 +    /* https://elinux.org/BCM2835_registers#PM */
 +    s->rstc = 0x00000102;
 +    s->rsts = 0x00001000;
 +    s->wdog = 0x00000000;
 +}
 +
 +static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
-+    dc->realize = mphi_realize;
++    dc->reset = bcm2835_powermgt_reset;
-+    dc->reset = mphi_reset;
++    dc->vmsd = &vmstate_bcm2835_powermgt;
-+    dc->vmsd = &vmstate_mphi_state;
++}
-+}
++
-+
++static TypeInfo bcm2835_powermgt_info = {
-+static const TypeInfo bcm2835_mphi_type_info = {
++    .name          = TYPE_BCM2835_POWERMGT,
 +    .name          = TYPE_BCM2835_MPHI,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
-+    .instance_size = sizeof(BCM2835MphiState),
++    .instance_size = sizeof(BCM2835PowerMgtState),
-+    .instance_init = mphi_init,
++    .class_init    = bcm2835_powermgt_class_init,
-+    .class_init    = mphi_class_init,
++    .instance_init = bcm2835_powermgt_init,
 +};
 +
-+static void bcm2835_mphi_register_types(void)
++static void bcm2835_powermgt_register_types(void)
 +{
-+    type_register_static(&bcm2835_mphi_type_info);
++    type_register_static(&bcm2835_powermgt_info);
 +}
 +
-+type_init(bcm2835_mphi_register_types)
++type_init(bcm2835_powermgt_register_types)
-diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
+diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/Makefile.objs
+--- a/hw/misc/meson.build
-+++ b/hw/misc/Makefile.objs
++++ b/hw/misc/meson.build
-@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_OMAP) += omap_l4.o
+@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
- common-obj-$(CONFIG_OMAP) += omap_sdrc.o
+   'bcm2835_rng.c',
- common-obj-$(CONFIG_OMAP) += omap_tap.o
+   'bcm2835_thermal.c',
- common-obj-$(CONFIG_RASPI) += bcm2835_mbox.o
+   'bcm2835_cprman.c',
-+common-obj-$(CONFIG_RASPI) += bcm2835_mphi.o
++  'bcm2835_powermgt.c',
- common-obj-$(CONFIG_RASPI) += bcm2835_property.o
+ ))
- common-obj-$(CONFIG_RASPI) += bcm2835_rng.o
+ softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
- common-obj-$(CONFIG_RASPI) += bcm2835_thermal.o
+ softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
 --
 .20.1

-[PULL 12/29] tests/acceptance: Add a boot test for the xlnx-versal-virt machine
+[PULL 04/24] tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
-From: Thomas Huth <thuth@redhat.com>
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-As described by Edgar here:
+Add a test booting and quickly shutdown a raspi2 machine,
 to test the power management model:
- https://www.mail-archive.com/qemu-devel@nongnu.org/msg605124.html
+   (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
   console: [    0.000000] Booting Linux on physical CPU 0xf00
   console: [    0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
   console: [    0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
   console: [    0.000000] CPU: div instructions available: patching division code
   console: [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
   console: [    0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
   ...
   console: Boot successful.
   console: cat /proc/cpuinfo
   console: / # cat /proc/cpuinfo
   ...
   console: processor      : 3
   console: model name     : ARMv7 Processor rev 5 (v7l)
   console: BogoMIPS       : 125.00
   console: Features       : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
   console: CPU implementer        : 0x41
   console: CPU architecture: 7
   console: CPU variant    : 0x0
   console: CPU part       : 0xc07
   console: CPU revision   : 5
   console: Hardware       : BCM2835
   console: Revision       : 0000
   console: Serial         : 0000000000000000
   console: cat /proc/iomem
   console: / # cat /proc/iomem
   console: 00000000-3bffffff : System RAM
   console: 00008000-00afffff : Kernel code
   console: 00c00000-00d468ef : Kernel data
   console: 3f006000-3f006fff : dwc_otg
   console: 3f007000-3f007eff : /soc/dma@7e007000
   console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
   console: 3f100000-3f100027 : /soc/watchdog@7e100000
   console: 3f101000-3f102fff : /soc/cprman@7e101000
   console: 3f200000-3f2000b3 : /soc/gpio@7e200000
   PASS (24.59 s)
   RESULTS    : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
   JOB TIME   : 25.02 s
-we can use the Ubuntu kernel for testing the xlnx-versal-virt machine.
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-So let's add a boot test for this now.
+Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
+Message-id: 20210531113837.1689775-1-f4bug@amsat.org
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Signed-off-by: Thomas Huth <thuth@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 Message-id: 20200525141237.15243-1-thuth@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- tests/acceptance/boot_linux_console.py | 26 ++++++++++++++++++++++++++
+ tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
-file changed, 26 insertions(+)
+file changed, 43 insertions(+)
 diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/acceptance/boot_linux_console.py
 +++ b/tests/acceptance/boot_linux_console.py
-@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(LinuxKernelTest):
+@@ -XXX,XX +XXX,XX @@
-         console_pattern = 'Kernel command line: %s' % kernel_command_line
+ from avocado import skip
-         self.wait_for_console_pattern(console_pattern)
+ from avocado import skipUnless
+ from avocado_qemu import Test
-+    def test_aarch64_xlnx_versal_virt(self):
++from avocado_qemu import exec_command
  from avocado_qemu import exec_command_and_wait_for_pattern
  from avocado_qemu import interrupt_interactive_console_until_pattern
  from avocado_qemu import wait_for_console_pattern
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
          """
          self.do_test_arm_raspi2(0)
 +    def test_arm_raspi2_initrd(self):
 +        """
-+        :avocado: tags=arch:aarch64
++        :avocado: tags=arch:arm
-+        :avocado: tags=machine:xlnx-versal-virt
++        :avocado: tags=machine:raspi2
 +        :avocado: tags=device:pl011
 +        :avocado: tags=device:arm_gicv3
 +        """
-+        kernel_url = ('http://ports.ubuntu.com/ubuntu-ports/dists/'
++        deb_url = ('http://archive.raspberrypi.org/debian/'
-+                      'bionic-updates/main/installer-arm64/current/images/'
++                   'pool/main/r/raspberrypi-firmware/'
-+                      'netboot/ubuntu-installer/arm64/linux')
++                   'raspberrypi-kernel_1.20190215-1_armhf.deb')
-+        kernel_hash = '5bfc54cf7ed8157d93f6e5b0241e727b6dc22c50'
++        deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
-+        kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
++        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
 +        kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
 +        dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
 +
-+        initrd_url = ('http://ports.ubuntu.com/ubuntu-ports/dists/'
++        initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
-+                      'bionic-updates/main/installer-arm64/current/images/'
++                      '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
-+                      'netboot/ubuntu-installer/arm64/initrd.gz')
++                      'arm/rootfs-armv7a.cpio.gz')
-+        initrd_hash = 'd385d3e88d53e2004c5d43cbe668b458a094f772'
++        initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
-+        initrd_path = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
++        initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
 +        initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
 +        archive.gzip_uncompress(initrd_path_gz, initrd_path)
 +
 +        self.vm.set_console()
-+        self.vm.add_args('-m', '2G',
++        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
-+                         '-kernel', kernel_path,
++                               'earlycon=pl011,0x3f201000 console=ttyAMA0 '
-+                         '-initrd', initrd_path)
++                               'panic=-1 noreboot ' +
 +                               'dwc_otg.fiq_fsm_enable=0')
 +        self.vm.add_args('-kernel', kernel_path,
 +                         '-dtb', dtb_path,
 +                         '-initrd', initrd_path,
 +                         '-append', kernel_command_line,
 +                         '-no-reboot')
 +        self.vm.launch()
-+        self.wait_for_console_pattern('Checked W+X mappings: passed')
++        self.wait_for_console_pattern('Boot successful.')
 +
-     def test_arm_virt(self):
++        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
 +                                                'BCM2835')
 +        exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
 +                                                '/soc/cprman@7e101000')
 +        exec_command(self, 'halt')
 +        # Wait for VM to shut down gracefully
 +        self.vm.wait()
 +
      def test_arm_exynos4210_initrd(self):
          """
          :avocado: tags=arch:arm
 --
 .20.1

-[PULL 16/29] dwc-hsotg (dwc2) USB host controller state definitions
+[PULL 05/24] target/arm: Check NaN mode before silencing NaN
-From: Paul Zimmerman <pauldzim@gmail.com>
+From: Joe Komlodi <joe.komlodi@xilinx.com>
-Add the dwc-hsotg (dwc2) USB host controller state definitions.
+If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
-Mostly based on hw/usb/hcd-ehci.h.
+FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
 assert due to fpst->default_nan_mode being set.
-Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
+To avoid this, we check to see what NaN mode we're running in before we call
-Message-id: 20200520235349.21215-4-pauldzim@gmail.com
+floatxx_silence_nan().
 Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/usb/hcd-dwc2.h | 190 ++++++++++++++++++++++++++++++++++++++++++++++
+ target/arm/helper-a64.c | 12 +++++++++---
-file changed, 190 insertions(+)
+ target/arm/vfp_helper.c | 24 ++++++++++++++++++------
- create mode 100644 hw/usb/hcd-dwc2.h
+files changed, 27 insertions(+), 9 deletions(-)
-diff --git a/hw/usb/hcd-dwc2.h b/hw/usb/hcd-dwc2.h
+diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
-new file mode 100644
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX
+--- a/target/arm/helper-a64.c
---- /dev/null
++++ b/target/arm/helper-a64.c
-+++ b/hw/usb/hcd-dwc2.h
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
-@@ -XXX,XX +XXX,XX @@
+         float16 nan = a;
-+/*
+         if (float16_is_signaling_nan(a, fpst)) {
-+ * dwc-hsotg (dwc2) USB host controller state definitions
+             float_raise(float_flag_invalid, fpst);
-+ *
+-            nan = float16_silence_nan(a, fpst);
-+ * Based on hw/usb/hcd-ehci.h
++            if (!fpst->default_nan_mode) {
-+ *
++                nan = float16_silence_nan(a, fpst);
-+ * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
++            }
-+ *
+         }
-+ * This program is free software; you can redistribute it and/or modify
+         if (fpst->default_nan_mode) {
-+ * it under the terms of the GNU General Public License as published by
+             nan = float16_default_nan(fpst);
-+ * the Free Software Foundation; either version 2 of the License, or
+@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
-+ * (at your option) any later version.
+         float32 nan = a;
-+ *
+         if (float32_is_signaling_nan(a, fpst)) {
-+ * This program is distributed in the hope that it will be useful,
+             float_raise(float_flag_invalid, fpst);
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+-            nan = float32_silence_nan(a, fpst);
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++            if (!fpst->default_nan_mode) {
-+ * GNU General Public License for more details.
++                nan = float32_silence_nan(a, fpst);
-+ */
++            }
-+
+         }
-+#ifndef HW_USB_DWC2_H
+         if (fpst->default_nan_mode) {
-+#define HW_USB_DWC2_H
+             nan = float32_default_nan(fpst);
-+
+@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
-+#include "qemu/timer.h"
+         float64 nan = a;
-+#include "hw/irq.h"
+         if (float64_is_signaling_nan(a, fpst)) {
-+#include "hw/sysbus.h"
+             float_raise(float_flag_invalid, fpst);
-+#include "hw/usb.h"
+-            nan = float64_silence_nan(a, fpst);
-+#include "sysemu/dma.h"
++            if (!fpst->default_nan_mode) {
-+
++                nan = float64_silence_nan(a, fpst);
-+#define DWC2_MMIO_SIZE      0x11000
++            }
-+
+         }
-+#define DWC2_NB_CHAN        8       /* Number of host channels */
+         if (fpst->default_nan_mode) {
-+#define DWC2_MAX_XFER_SIZE  65536   /* Max transfer size expected in HCTSIZ */
+             nan = float64_default_nan(fpst);
-+
+diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
-+typedef struct DWC2Packet DWC2Packet;
+index XXXXXXX..XXXXXXX 100644
-+typedef struct DWC2State DWC2State;
+--- a/target/arm/vfp_helper.c
-+typedef struct DWC2Class DWC2Class;
++++ b/target/arm/vfp_helper.c
-+
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
-+enum async_state {
+         float16 nan = f16;
-+    DWC2_ASYNC_NONE = 0,
+         if (float16_is_signaling_nan(f16, fpst)) {
-+    DWC2_ASYNC_INITIALIZED,
+             float_raise(float_flag_invalid, fpst);
-+    DWC2_ASYNC_INFLIGHT,
+-            nan = float16_silence_nan(f16, fpst);
-+    DWC2_ASYNC_FINISHED,
++            if (!fpst->default_nan_mode) {
-+};
++                nan = float16_silence_nan(f16, fpst);
-+
++            }
-+struct DWC2Packet {
+         }
-+    USBPacket packet;
+         if (fpst->default_nan_mode) {
-+    uint32_t devadr;
+             nan =  float16_default_nan(fpst);
-+    uint32_t epnum;
+@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
-+    uint32_t epdir;
+         float32 nan = f32;
-+    uint32_t mps;
+         if (float32_is_signaling_nan(f32, fpst)) {
-+    uint32_t pid;
+             float_raise(float_flag_invalid, fpst);
-+    uint32_t index;
+-            nan = float32_silence_nan(f32, fpst);
-+    uint32_t pcnt;
++            if (!fpst->default_nan_mode) {
-+    uint32_t len;
++                nan = float32_silence_nan(f32, fpst);
-+    int32_t async;
++            }
-+    bool small;
+         }
-+    bool needs_service;
+         if (fpst->default_nan_mode) {
-+};
+             nan =  float32_default_nan(fpst);
-+
+@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
-+struct DWC2State {
+         float64 nan = f64;
-+    /*< private >*/
+         if (float64_is_signaling_nan(f64, fpst)) {
-+    SysBusDevice parent_obj;
+             float_raise(float_flag_invalid, fpst);
-+
+-            nan = float64_silence_nan(f64, fpst);
-+    /*< public >*/
++            if (!fpst->default_nan_mode) {
-+    USBBus bus;
++                nan = float64_silence_nan(f64, fpst);
-+    qemu_irq irq;
++            }
-+    MemoryRegion *dma_mr;
+         }
-+    AddressSpace dma_as;
+         if (fpst->default_nan_mode) {
-+    MemoryRegion container;
+             nan =  float64_default_nan(fpst);
-+    MemoryRegion hsotg;
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
-+    MemoryRegion fifos;
+         float16 nan = f16;
-+
+         if (float16_is_signaling_nan(f16, s)) {
-+    union {
+             float_raise(float_flag_invalid, s);
-+#define DWC2_GLBREG_SIZE    0x70
+-            nan = float16_silence_nan(f16, s);
-+        uint32_t glbreg[DWC2_GLBREG_SIZE / sizeof(uint32_t)];
++            if (!s->default_nan_mode) {
-+        struct {
++                nan = float16_silence_nan(f16, fpstp);
-+            uint32_t gotgctl;       /* 00 */
++            }
-+            uint32_t gotgint;       /* 04 */
+         }
-+            uint32_t gahbcfg;       /* 08 */
+         if (s->default_nan_mode) {
-+            uint32_t gusbcfg;       /* 0c */
+             nan =  float16_default_nan(s);
-+            uint32_t grstctl;       /* 10 */
+@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
-+            uint32_t gintsts;       /* 14 */
+         float32 nan = f32;
-+            uint32_t gintmsk;       /* 18 */
+         if (float32_is_signaling_nan(f32, s)) {
-+            uint32_t grxstsr;       /* 1c */
+             float_raise(float_flag_invalid, s);
-+            uint32_t grxstsp;       /* 20 */
+-            nan = float32_silence_nan(f32, s);
-+            uint32_t grxfsiz;       /* 24 */
++            if (!s->default_nan_mode) {
-+            uint32_t gnptxfsiz;     /* 28 */
++                nan = float32_silence_nan(f32, fpstp);
-+            uint32_t gnptxsts;      /* 2c */
++            }
-+            uint32_t gi2cctl;       /* 30 */
+         }
-+            uint32_t gpvndctl;      /* 34 */
+         if (s->default_nan_mode) {
-+            uint32_t ggpio;         /* 38 */
+             nan =  float32_default_nan(s);
-+            uint32_t guid;          /* 3c */
+@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
-+            uint32_t gsnpsid;       /* 40 */
+         float64 nan = f64;
-+            uint32_t ghwcfg1;       /* 44 */
+         if (float64_is_signaling_nan(f64, s)) {
-+            uint32_t ghwcfg2;       /* 48 */
+             float_raise(float_flag_invalid, s);
-+            uint32_t ghwcfg3;       /* 4c */
+-            nan = float64_silence_nan(f64, s);
-+            uint32_t ghwcfg4;       /* 50 */
++            if (!s->default_nan_mode) {
-+            uint32_t glpmcfg;       /* 54 */
++                nan = float64_silence_nan(f64, fpstp);
-+            uint32_t gpwrdn;        /* 58 */
++            }
-+            uint32_t gdfifocfg;     /* 5c */
+         }
-+            uint32_t gadpctl;       /* 60 */
+         if (s->default_nan_mode) {
-+            uint32_t grefclk;       /* 64 */
+             nan =  float64_default_nan(s);
 +            uint32_t gintmsk2;      /* 68 */
 +            uint32_t gintsts2;      /* 6c */
 +        };
 +    };
 +
 +    union {
 +#define DWC2_FSZREG_SIZE    0x04
 +        uint32_t fszreg[DWC2_FSZREG_SIZE / sizeof(uint32_t)];
 +        struct {
 +            uint32_t hptxfsiz;      /* 100 */
 +        };
 +    };
 +
 +    union {
 +#define DWC2_HREG0_SIZE     0x44
 +        uint32_t hreg0[DWC2_HREG0_SIZE / sizeof(uint32_t)];
 +        struct {
 +            uint32_t hcfg;          /* 400 */
 +            uint32_t hfir;          /* 404 */
 +            uint32_t hfnum;         /* 408 */
 +            uint32_t rsvd0;         /* 40c */
 +            uint32_t hptxsts;       /* 410 */
 +            uint32_t haint;         /* 414 */
 +            uint32_t haintmsk;      /* 418 */
 +            uint32_t hflbaddr;      /* 41c */
 +            uint32_t rsvd1[8];      /* 420-43c */
 +            uint32_t hprt0;         /* 440 */
 +        };
 +    };
 +
 +#define DWC2_HREG1_SIZE     (0x20 * DWC2_NB_CHAN)
 +    uint32_t hreg1[DWC2_HREG1_SIZE / sizeof(uint32_t)];
 +
 +#define hcchar(_ch)     hreg1[((_ch) << 3) + 0] /* 500, 520, ... */
 +#define hcsplt(_ch)     hreg1[((_ch) << 3) + 1] /* 504, 524, ... */
 +#define hcint(_ch)      hreg1[((_ch) << 3) + 2] /* 508, 528, ... */
 +#define hcintmsk(_ch)   hreg1[((_ch) << 3) + 3] /* 50c, 52c, ... */
 +#define hctsiz(_ch)     hreg1[((_ch) << 3) + 4] /* 510, 530, ... */
 +#define hcdma(_ch)      hreg1[((_ch) << 3) + 5] /* 514, 534, ... */
 +#define hcdmab(_ch)     hreg1[((_ch) << 3) + 7] /* 51c, 53c, ... */
 +
 +    union {
 +#define DWC2_PCGREG_SIZE    0x08
 +        uint32_t pcgreg[DWC2_PCGREG_SIZE / sizeof(uint32_t)];
 +        struct {
 +            uint32_t pcgctl;        /* e00 */
 +            uint32_t pcgcctl1;      /* e04 */
 +        };
 +    };
 +
 +    /* TODO - implement FIFO registers for slave mode */
 +#define DWC2_HFIFO_SIZE     (0x1000 * DWC2_NB_CHAN)
 +
 +    /*
 +     *  Internal state
 +     */
 +    QEMUTimer *eof_timer;
 +    QEMUTimer *frame_timer;
 +    QEMUBH *async_bh;
 +    int64_t sof_time;
 +    int64_t usb_frame_time;
 +    int64_t usb_bit_time;
 +    uint32_t usb_version;
 +    uint16_t frame_number;
 +    uint16_t fi;
 +    uint16_t next_chan;
 +    bool working;
 +    USBPort uport;
 +    DWC2Packet packet[DWC2_NB_CHAN];                   /* one packet per chan */
 +    uint8_t usb_buf[DWC2_NB_CHAN][DWC2_MAX_XFER_SIZE]; /* one buffer per chan */
 +};
 +
 +struct DWC2Class {
 +    /*< private >*/
 +    SysBusDeviceClass parent_class;
 +    ResettablePhases parent_phases;
 +
 +    /*< public >*/
 +};
 +
 +#define TYPE_DWC2_USB   "dwc2-usb"
 +#define DWC2_USB(obj) \
 +    OBJECT_CHECK(DWC2State, (obj), TYPE_DWC2_USB)
 +#define DWC2_CLASS(klass) \
 +    OBJECT_CLASS_CHECK(DWC2Class, (klass), TYPE_DWC2_USB)
 +#define DWC2_GET_CLASS(obj) \
 +    OBJECT_GET_CLASS(DWC2Class, (obj), TYPE_DWC2_USB)
 +
 +#endif
 --
 .20.1

-[PULL 06/29] target/arm: Convert rax1 to gvec helpers
+[PULL 06/24] hw/gpio/gpio_pwr: use shutdown function for reboot
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Maxim Uvarov <maxim.uvarov@linaro.org>
-With this conversion, we will be able to use the same helpers
+qemu has 2 type of functions: shutdown and reboot. Shutdown
-with sve.  This also fixes a bug in which we failed to clear
+function has to be used for machine shutdown. Otherwise we cause
-the high bits of the SVE register after an AdvSIMD operation.
+a reset with a bogus "cause" value, when we intended a shutdown.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
 Message-id: 20200514212831.31248-3-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
+[PMM: tweaked commit message]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.h        |  2 ++
+ hw/gpio/gpio_pwr.c | 2 +-
- target/arm/translate-a64.h |  3 ++
+file changed, 1 insertion(+), 1 deletion(-)
  target/arm/crypto_helper.c | 11 +++++++
  target/arm/translate-a64.c | 59 ++++++++++++++++++++------------------
 files changed, 47 insertions(+), 28 deletions(-)
-diff --git a/target/arm/helper.h b/target/arm/helper.h
+diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
+--- a/hw/gpio/gpio_pwr.c
-+++ b/target/arm/helper.h
++++ b/hw/gpio/gpio_pwr.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
+@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
- DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+ static void gpio_pwr_shutdown(void *opaque, int n, int level)
- DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+ {
+     if (level) {
-+DEF_HELPER_FLAGS_4(crypto_rax1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+-        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
-+
++        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
  DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
  DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
 diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.h
 +++ b/target/arm/translate-a64.h
@@ -XXX,XX +XXX,XX @@ static inline int vec_full_reg_size(DisasContext *s)
  bool disas_sve(DisasContext *, uint32_t);
 +void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 +                   uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 +
  #endif /* TARGET_ARM_TRANSLATE_A64_H */
 diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/crypto_helper.c
 +++ b/target/arm/crypto_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm, uint32_t desc)
      }
      clear_tail(vd, opr_sz, simd_maxsz(desc));
  }
 +
 +void HELPER(crypto_rax1)(void *vd, void *vn, void *vm, uint32_t desc)
 +{
 +    intptr_t i, opr_sz = simd_oprsz(desc);
 +    uint64_t *d = vd, *n = vn, *m = vm;
 +
 +    for (i = 0; i < opr_sz / 8; ++i) {
 +        d[i] = n[i] ^ rol64(m[i], 1);
 +    }
 +    clear_tail(vd, opr_sz, simd_maxsz(desc));
 +}
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
      tcg_temp_free_ptr(tcg_rn_ptr);
  }
 +static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
 +{
 +    tcg_gen_rotli_i64(d, m, 1);
 +    tcg_gen_xor_i64(d, d, n);
 +}
 +
 +static void gen_rax1_vec(unsigned vece, TCGv_vec d, TCGv_vec n, TCGv_vec m)
 +{
 +    tcg_gen_rotli_vec(vece, d, m, 1);
 +    tcg_gen_xor_vec(vece, d, d, n);
 +}
 +
 +void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 +                   uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz)
 +{
 +    static const TCGOpcode vecop_list[] = { INDEX_op_rotli_vec, 0 };
 +    static const GVecGen3 op = {
 +        .fni8 = gen_rax1_i64,
 +        .fniv = gen_rax1_vec,
 +        .opt_opc = vecop_list,
 +        .fno = gen_helper_crypto_rax1,
 +        .vece = MO_64,
 +    };
 +    tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &op);
 +}
 +
  /* Crypto three-reg SHA512
   *  31                   21 20  16 15  14  13 12  11  10  9    5 4    0
   * +-----------------------+------+---+---+-----+--------+------+------+
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
      bool feature;
      CryptoThreeOpFn *genfn = NULL;
      gen_helper_gvec_3 *oolfn = NULL;
 +    GVecGen3Fn *gvecfn = NULL;
      if (o == 0) {
          switch (opcode) {
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
              break;
          case 3: /* RAX1 */
              feature = dc_isar_feature(aa64_sha3, s);
 -            genfn = NULL;
 +            gvecfn = gen_gvec_rax1;
              break;
          default:
              g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
      if (oolfn) {
          gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn);
 -        return;
 -    }
 -
 -    if (genfn) {
 +    } else if (gvecfn) {
 +        gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64);
 +    } else {
          TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
          tcg_rd_ptr = vec_full_reg_ptr(s, rd);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
          tcg_temp_free_ptr(tcg_rd_ptr);
          tcg_temp_free_ptr(tcg_rn_ptr);
          tcg_temp_free_ptr(tcg_rm_ptr);
 -    } else {
 -        TCGv_i64 tcg_op1, tcg_op2, tcg_res[2];
 -        int pass;
 -
 -        tcg_op1 = tcg_temp_new_i64();
 -        tcg_op2 = tcg_temp_new_i64();
 -        tcg_res[0] = tcg_temp_new_i64();
 -        tcg_res[1] = tcg_temp_new_i64();
 -
 -        for (pass = 0; pass < 2; pass++) {
 -            read_vec_element(s, tcg_op1, rn, pass, MO_64);
 -            read_vec_element(s, tcg_op2, rm, pass, MO_64);
 -
 -            tcg_gen_rotli_i64(tcg_res[pass], tcg_op2, 1);
 -            tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
 -        }
 -        write_vec_element(s, tcg_res[0], rd, 0, MO_64);
 -        write_vec_element(s, tcg_res[1], rd, 1, MO_64);
 -
 -        tcg_temp_free_i64(tcg_op1);
 -        tcg_temp_free_i64(tcg_op2);
 -        tcg_temp_free_i64(tcg_res[0]);
 -        tcg_temp_free_i64(tcg_res[1]);
      }
  }
 --
 .20.1

-[PULL 07/29] target/arm: Convert sha512 and sm3 to gvec helpers
+[PULL 07/24] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
-From: Richard Henderson <richard.henderson@linaro.org>
+In do_ldst(), the calculation of the offset needs to be based on the
 size of the memory access, not the size of the elements in the
 vector.  This meant we were getting it wrong for the widening and
 narrowing variants of the various VLDR and VSTR insns.
-Do not yet convert the helpers to loop over opr_sz, but the
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-descriptor allows the vector tail to be cleared.  Which fixes
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-an existing bug vs SVE.
+Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
 ---
  target/arm/translate-mve.c | 17 +++++++++--------
 file changed, 9 insertions(+), 8 deletions(-)
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 Message-id: 20200514212831.31248-4-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/helper.h        | 15 +++++++-----
  target/arm/crypto_helper.c | 37 +++++++++++++++++++++++-----
  target/arm/translate-a64.c | 50 ++++++++++++--------------------------
 files changed, 55 insertions(+), 47 deletions(-)
 diff --git a/target/arm/helper.h b/target/arm/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
+--- a/target/arm/translate-mve.c
-+++ b/target/arm/helper.h
++++ b/target/arm/translate-mve.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
+@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
  DEF_HELPER_FLAGS_2(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr)
  DEF_HELPER_FLAGS_3(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
 -DEF_HELPER_FLAGS_3(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
 -DEF_HELPER_FLAGS_3(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
 -DEF_HELPER_FLAGS_2(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr)
 -DEF_HELPER_FLAGS_3(crypto_sha512su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
 +DEF_HELPER_FLAGS_4(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_3(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(crypto_sha512su1, TCG_CALL_NO_RWG,
 +                   void, ptr, ptr, ptr, i32)
  DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32, i32)
 -DEF_HELPER_FLAGS_3(crypto_sm3partw1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
 -DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
 +DEF_HELPER_FLAGS_4(crypto_sm3partw1, TCG_CALL_NO_RWG,
 +                   void, ptr, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(crypto_sm3partw2, TCG_CALL_NO_RWG,
 +                   void, ptr, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/crypto_helper.c
 +++ b/target/arm/crypto_helper.c
@@ -XXX,XX +XXX,XX @@ union CRYPTO_STATE {
  #define CR_ST_WORD(state, i)   (state.words[i])
  #endif
 +/*
 + * The caller has not been converted to full gvec, and so only
 + * modifies the low 16 bytes of the vector register.
 + */
 +static void clear_tail_16(void *vd, uint32_t desc)
 +{
 +    int opr_sz = simd_oprsz(desc);
 +    int max_sz = simd_maxsz(desc);
 +
 +    assert(opr_sz == 16);
 +    clear_tail(vd, opr_sz, max_sz);
 +}
 +
  static void do_crypto_aese(uint64_t *rd, uint64_t *rn,
                             uint64_t *rm, bool decrypt)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t s1_512(uint64_t x)
      return ror64(x, 19) ^ ror64(x, 61) ^ (x >> 6);
  }
 -void HELPER(crypto_sha512h)(void *vd, void *vn, void *vm)
 +void HELPER(crypto_sha512h)(void *vd, void *vn, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512h)(void *vd, void *vn, void *vm)
      rd[0] = d0;
      rd[1] = d1;
 +
 +    clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sha512h2)(void *vd, void *vn, void *vm)
 +void HELPER(crypto_sha512h2)(void *vd, void *vn, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512h2)(void *vd, void *vn, void *vm)
      rd[0] = d0;
      rd[1] = d1;
 +
 +    clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sha512su0)(void *vd, void *vn)
 +void HELPER(crypto_sha512su0)(void *vd, void *vn, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512su0)(void *vd, void *vn)
      rd[0] = d0;
      rd[1] = d1;
 +
 +    clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sha512su1)(void *vd, void *vn, void *vm)
 +void HELPER(crypto_sha512su1)(void *vd, void *vn, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512su1)(void *vd, void *vn, void *vm)
      rd[0] += s1_512(rn[0]) + rm[0];
      rd[1] += s1_512(rn[1]) + rm[1];
 +
 +    clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sm3partw1)(void *vd, void *vn, void *vm)
 +void HELPER(crypto_sm3partw1)(void *vd, void *vn, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3partw1)(void *vd, void *vn, void *vm)
      rd[0] = d.l[0];
      rd[1] = d.l[1];
 +
 +    clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm)
 +void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm)
      rd[0] = d.l[0];
      rd[1] = d.l[1];
 +
 +    clear_tail_16(vd, desc);
  }
  void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2,
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
      int rn = extract32(insn, 5, 5);
      int rd = extract32(insn, 0, 5);
      bool feature;
 -    CryptoThreeOpFn *genfn = NULL;
      gen_helper_gvec_3 *oolfn = NULL;
      GVecGen3Fn *gvecfn = NULL;
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
          switch (opcode) {
          case 0: /* SHA512H */
              feature = dc_isar_feature(aa64_sha512, s);
 -            genfn = gen_helper_crypto_sha512h;
 +            oolfn = gen_helper_crypto_sha512h;
              break;
          case 1: /* SHA512H2 */
              feature = dc_isar_feature(aa64_sha512, s);
 -            genfn = gen_helper_crypto_sha512h2;
 +            oolfn = gen_helper_crypto_sha512h2;
              break;
          case 2: /* SHA512SU1 */
              feature = dc_isar_feature(aa64_sha512, s);
 -            genfn = gen_helper_crypto_sha512su1;
 +            oolfn = gen_helper_crypto_sha512su1;
              break;
          case 3: /* RAX1 */
              feature = dc_isar_feature(aa64_sha3, s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
          switch (opcode) {
          case 0: /* SM3PARTW1 */
              feature = dc_isar_feature(aa64_sm3, s);
 -            genfn = gen_helper_crypto_sm3partw1;
 +            oolfn = gen_helper_crypto_sm3partw1;
              break;
          case 1: /* SM3PARTW2 */
              feature = dc_isar_feature(aa64_sm3, s);
 -            genfn = gen_helper_crypto_sm3partw2;
 +            oolfn = gen_helper_crypto_sm3partw2;
              break;
          case 2: /* SM4EKEY */
              feature = dc_isar_feature(aa64_sm4, s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
      if (oolfn) {
          gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn);
 -    } else if (gvecfn) {
 -        gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64);
      } else {
 -        TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
 -
 -        tcg_rd_ptr = vec_full_reg_ptr(s, rd);
 -        tcg_rn_ptr = vec_full_reg_ptr(s, rn);
 -        tcg_rm_ptr = vec_full_reg_ptr(s, rm);
 -
 -        genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr);
 -
 -        tcg_temp_free_ptr(tcg_rd_ptr);
 -        tcg_temp_free_ptr(tcg_rn_ptr);
 -        tcg_temp_free_ptr(tcg_rm_ptr);
 +        gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64);
      }
  }
-@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
+-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
-     int opcode = extract32(insn, 10, 2);
++static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
-     int rn = extract32(insn, 5, 5);
++                    unsigned msize)
-     int rd = extract32(insn, 0, 5);
+ {
--    TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
+     TCGv_i32 addr;
-     bool feature;
+     uint32_t offset;
--    CryptoTwoOpFn *genfn;
+@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
--    gen_helper_gvec_3 *oolfn = NULL;
+         return true;
      switch (opcode) {
      case 0: /* SHA512SU0 */
          feature = dc_isar_feature(aa64_sha512, s);
 -        genfn = gen_helper_crypto_sha512su0;
          break;
      case 1: /* SM4E */
          feature = dc_isar_feature(aa64_sm4, s);
 -        oolfn = gen_helper_crypto_sm4e;
          break;
      default:
          unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
          return;
      }
--    if (oolfn) {
+-    offset = a->imm << a->size;
--        gen_gvec_op3_ool(s, true, rd, rd, rn, 0, oolfn);
++    offset = a->imm << msize;
--        return;
+     if (!a->a) {
-+    switch (opcode) {
+         offset = -offset;
 +    case 0: /* SHA512SU0 */
 +        gen_gvec_op2_ool(s, true, rd, rn, 0, gen_helper_crypto_sha512su0);
 +        break;
 +    case 1: /* SM4E */
 +        gen_gvec_op3_ool(s, true, rd, rd, rn, 0, gen_helper_crypto_sm4e);
 +        break;
 +    default:
 +        g_assert_not_reached();
      }
--
+@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
--    tcg_rd_ptr = vec_full_reg_ptr(s, rd);
+         { gen_helper_mve_vstrw, gen_helper_mve_vldrw },
--    tcg_rn_ptr = vec_full_reg_ptr(s, rn);
+         { NULL, NULL }
--
+     };
--    genfn(tcg_rd_ptr, tcg_rn_ptr);
+-    return do_ldst(s, a, ldstfns[a->size][a->l]);
--
++    return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
 -    tcg_temp_free_ptr(tcg_rd_ptr);
 -    tcg_temp_free_ptr(tcg_rn_ptr);
  }
- /* Crypto four-register
+-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST)                  \
 +#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE)           \
      static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a)   \
      {                                                           \
          static MVEGenLdStFn * const ldstfns[2][2] = {           \
              { gen_helper_mve_##ST, gen_helper_mve_##SLD },      \
              { NULL, gen_helper_mve_##ULD },                     \
          };                                                      \
 -        return do_ldst(s, a, ldstfns[a->u][a->l]);              \
 +        return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE);       \
      }
 -DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
 -DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
 -DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
 +DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
 +DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
 +DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
  static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
  {
 --
 .20.1

-[PULL 03/29] hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()
+[PULL 08/24] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
 insns had some bugs:
  * the 32x32 multiply of elements was being done as 32x32->32,
    not 32x32->64
  * we were incorrectly maintaining the accumulator in its full
 -bit form across all 4 beats of the insn; in the pseudocode
    it is squashed back into the 64 bits of the RdaHi:RdaLo
    registers after each beat
-hw_error() calls exit(). This a bit overkill when we can log
+In particular, fixing the second of these allows us to recast
-the accesses as unimplemented or guest error.
+the implementation to avoid 128-bit arithmetic entirely.
-When fuzzing the devices, we don't want the whole process to
+Since the element size here is always 4, we can also drop the
-exit. Replace some hw_error() calls by qemu_log_mask()
+parameterization of ESIZE to make the code a little more readable.
 (missed in commit 5a0001ec7e).
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Suggested-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20200525114123.21317-2-f4bug@amsat.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
 ---
- hw/input/pxa2xx_keypad.c | 10 +++++++---
+ target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
-file changed, 7 insertions(+), 3 deletions(-)
+file changed, 21 insertions(+), 17 deletions(-)
-diff --git a/hw/input/pxa2xx_keypad.c b/hw/input/pxa2xx_keypad.c
+diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/input/pxa2xx_keypad.c
+--- a/target/arm/mve_helper.c
-+++ b/hw/input/pxa2xx_keypad.c
++++ b/target/arm/mve_helper.c
 @@ -XXX,XX +XXX,XX @@
   */
  #include "qemu/osdep.h"
--#include "hw/hw.h"
+-#include "qemu/int128.h"
-+#include "qemu/log.h"
+ #include "cpu.h"
- #include "hw/irq.h"
+ #include "internals.h"
- #include "migration/vmstate.h"
+ #include "vec_internal.h"
- #include "hw/arm/pxa.h"
+@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
-@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_keypad_read(void *opaque, hwaddr offset,
+ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
-         return s->kpkdi;
-         break;
+ /*
-     default:
+- * Rounding multiply add long dual accumulate high: we must keep
--        hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
+- * a 72-bit internal accumulator value and return the top 64 bits.
-+        qemu_log_mask(LOG_GUEST_ERROR,
++ * Rounding multiply add long dual accumulate high. In the pseudocode
-+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
++ * this is implemented with a 72-bit internal accumulator value of which
-+                      __func__, offset);
++ * the top 64 bits are returned. We optimize this to avoid having to
 + * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
 + * is squashed back into 64-bits after each beat.
   */
 -#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128)         \
 +#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB)                            \
      uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn,         \
                                      void *vm, uint64_t a)               \
      {                                                                   \
          uint16_t mask = mve_element_mask(env);                          \
          unsigned e;                                                     \
          TYPE *n = vn, *m = vm;                                          \
 -        Int128 acc = int128_lshift(TO128(a), 8);                        \
 -        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {              \
 +        for (e = 0; e < 16 / 4; e++, mask >>= 4) {                      \
              if (mask & 1) {                                             \
 +                LTYPE mul;                                              \
                  if (e & 1) {                                            \
 -                    acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
 -                                            m[H##ESIZE(e)]));           \
 +                    mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)];        \
 +                    if (SUB) {                                          \
 +                        mul = -mul;                                     \
 +                    }                                                   \
                  } else {                                                \
 -                    acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
 -                                             m[H##ESIZE(e)]));          \
 +                    mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)];        \
                  }                                                       \
 -                acc = int128_add(acc, int128_make64(1 << 7));           \
 +                mul = (mul >> 8) + ((mul >> 7) & 1);                    \
 +                a += mul;                                               \
              }                                                           \
          }                                                               \
          mve_advance_vpt(env);                                           \
 -        return int128_getlo(int128_rshift(acc, 8));                     \
 +        return a;                                                       \
      }
-     return 0;
+-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
-@@ -XXX,XX +XXX,XX @@ static void pxa2xx_keypad_write(void *opaque, hwaddr offset,
+-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
-         break;
++DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
++DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
-     default:
--        hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
+-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
-+        qemu_log_mask(LOG_GUEST_ERROR,
++DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
-+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
-+                      __func__, offset);
+-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
-     }
+-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
- }
++DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
++DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
  /* Vector add across vector */
  #define DO_VADDV(OP, ESIZE, TYPE)                               \
 --
 .20.1

-[PULL 04/29] hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()
+Deleted patch
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Replace printf() calls by qemu_log_mask(), which is disabled
-by default. This avoid flooding the terminal when fuzzing the
-device.
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20200525114123.21317-3-f4bug@amsat.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/arm/pxa2xx.c | 66 ++++++++++++++++++++++++++++++++++++-------------
-file changed, 49 insertions(+), 17 deletions(-)
-diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/pxa2xx.c
-+++ b/hw/arm/pxa2xx.c
-@@ -XXX,XX +XXX,XX @@
- #include "sysemu/blockdev.h"
- #include "sysemu/qtest.h"
- #include "qemu/cutils.h"
-+#include "qemu/log.h"
- static struct {
-     hwaddr io_base;
-@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
-         return s->pm_regs[addr >> 2];
-     default:
-     fail:
--        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
-+                      __func__, addr);
-         break;
-     }
-     return 0;
-@@ -XXX,XX +XXX,XX @@ static void pxa2xx_pm_write(void *opaque, hwaddr addr,
-             s->pm_regs[addr >> 2] = value;
-             break;
-         }
--
--        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
-+                      __func__, addr);
-         break;
-     }
- }
-@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
-         return s->cm_regs[CCCR >> 2] | (3 << 28);
-     default:
--        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
-+                      __func__, addr);
-         break;
-     }
-     return 0;
-@@ -XXX,XX +XXX,XX @@ static void pxa2xx_cm_write(void *opaque, hwaddr addr,
-         break;
-     default:
--        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
-+                      __func__, addr);
-         break;
-     }
- }
-@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
-             return s->mm_regs[addr >> 2];
-         /* fall through */
-     default:
--        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
-+                      __func__, addr);
-         break;
-     }
-     return 0;
-@@ -XXX,XX +XXX,XX @@ static void pxa2xx_mm_write(void *opaque, hwaddr addr,
-         }
-     default:
--        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
-+                      __func__, addr);
-         break;
-     }
- }
-@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
-     case SSACD:
-         return s->ssacd;
-     default:
--        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
-+                      __func__, addr);
-         break;
-     }
-     return 0;
-@@ -XXX,XX +XXX,XX @@ static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
-         break;
-     default:
--        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
-+                      __func__, addr);
-         break;
-     }
- }
-@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
-         else
-             return s->last_swcr;
-     default:
--        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
-+                      __func__, addr);
-         break;
-     }
-     return 0;
-@@ -XXX,XX +XXX,XX @@ static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
-         break;
-     default:
--        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
-+                      __func__, addr);
-     }
- }
-@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
-             s->ibmr = 0;
-         return s->ibmr;
-     default:
--        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
-+                      __func__, addr);
-         break;
-     }
-     return 0;
-@@ -XXX,XX +XXX,XX @@ static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
-         break;
-     default:
--        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
-+                      __func__, addr);
-     }
- }
-@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
-         }
-         return 0;
-     default:
--        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
-+                      __func__, addr);
-         break;
-     }
-     return 0;
-@@ -XXX,XX +XXX,XX @@ static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
-         }
-         break;
-     default:
--        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
-+                      __func__, addr);
-     }
- }
-@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
-     case ICFOR:
-         return s->rx_len;
-     default:
--        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
-+                      __func__, addr);
-         break;
-     }
-     return 0;
-@@ -XXX,XX +XXX,XX @@ static void pxa2xx_fir_write(void *opaque, hwaddr addr,
-     case ICFOR:
-         break;
-     default:
--        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
-+                      __func__, addr);
-     }
- }
---
-.20.1

-[PULL 29/29] target/arm: Convert Neon one-register-and-immediate insns to decodetree
+[PULL 09/24] target/arm: Make asimd_imm_const() public
-Convert the insns in the one-register-and-immediate group to decodetree.
+The function asimd_imm_const() in translate-neon.c is an
+implementation of the pseudocode AdvSIMDExpandImm(), which we will
-In the new decode, our asimd_imm_const() function returns a 64-bit value
+also want for MVE.  Move the implementation to translate.c, with a
-rather than a 32-bit one, which means we don't need to treat cmode=14 op=1
+prototype in translate.h.
 as a special case in the decoder (it is the only encoding where the two
 halves of the 64-bit value are different).
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200522145520.6778-10-peter.maydell@linaro.org
+Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       |  22 ++++++
+ target/arm/translate.h      | 16 ++++++++++
- target/arm/translate-neon.inc.c | 118 ++++++++++++++++++++++++++++++++
+ target/arm/translate-neon.c | 63 -------------------------------------
- target/arm/translate.c          | 101 +--------------------------
+ target/arm/translate.c      | 57 +++++++++++++++++++++++++++++++++
-files changed, 142 insertions(+), 99 deletions(-)
+files changed, 73 insertions(+), 63 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
+diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
+--- a/target/arm/translate.h
-+++ b/target/arm/neon-dp.decode
++++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ VCVT_SF_2sh      1111 001 0 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
+@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
- VCVT_UF_2sh      1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
+     return opc | s->be_data;
- VCVT_FS_2sh      1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
+ }
- VCVT_FU_2sh      1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
 +/**
 + * asimd_imm_const: Expand an encoded SIMD constant value
 + *
 + * Expand a SIMD constant value. This is essentially the pseudocode
 + * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
 + * VMVN and VBIC (when cmode < 14 && op == 1).
 + *
 + * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
 + * callers must catch this.
 + *
 + * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
 + * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
 + * we produce an immediate constant value of 0 in these cases.
 + */
 +uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
 +
-+######################################################################
+ #endif /* TARGET_ARM_TRANSLATE_H */
-+# 1-reg-and-modified-immediate grouping:
+diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
 +# 1111 001 i 1 D 000 imm:3 Vd:4 cmode:4 0 Q op 1 Vm:4
 +######################################################################
 +
 +&1reg_imm        vd q imm cmode op
 +
 +%asimd_imm_value 24:1 16:3 0:4
 +
 +@1reg_imm        .... ... . . . ... ... .... .... . q:1 . . .... \
 +                 &1reg_imm imm=%asimd_imm_value vd=%vd_dp
 +
 +# The cmode/op bits here decode VORR/VBIC/VMOV/VMNV, but
 +# not in a way we can conveniently represent in decodetree without
 +# a lot of repetition:
 +# VORR: op=0, (cmode & 1) && cmode < 12
 +# VBIC: op=1, (cmode & 1) && cmode < 12
 +# VMOV: everything else
 +# So we have a single decode line and check the cmode/op in the
 +# trans function.
 +Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
+--- a/target/arm/translate-neon.c
-+++ b/target/arm/translate-neon.inc.c
++++ b/target/arm/translate-neon.c
-@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos)
+@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
- DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos)
+ DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
- DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero)
+ DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
- DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero)
-+
+-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
-+static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
+-{
 -    /*
 -     * Expand the encoded constant.
 -     * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
 -     * We choose to not special-case this and will behave as if a
 -     * valid constant encoding of 0 had been given.
 -     * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
 -     */
 -    switch (cmode) {
 -    case 0: case 1:
 -        /* no-op */
 -        break;
 -    case 2: case 3:
 -        imm <<= 8;
 -        break;
 -    case 4: case 5:
 -        imm <<= 16;
 -        break;
 -    case 6: case 7:
 -        imm <<= 24;
 -        break;
 -    case 8: case 9:
 -        imm |= imm << 16;
 -        break;
 -    case 10: case 11:
 -        imm = (imm << 8) | (imm << 24);
 -        break;
 -    case 12:
 -        imm = (imm << 8) | 0xff;
 -        break;
 -    case 13:
 -        imm = (imm << 16) | 0xffff;
 -        break;
 -    case 14:
 -        if (op) {
 -            /*
 -             * This is the only case where the top and bottom 32 bits
 -             * of the encoded constant differ.
 -             */
 -            uint64_t imm64 = 0;
 -            int n;
 -
 -            for (n = 0; n < 8; n++) {
 -                if (imm & (1 << n)) {
 -                    imm64 |= (0xffULL << (n * 8));
 -                }
 -            }
 -            return imm64;
 -        }
 -        imm |= (imm << 8) | (imm << 16) | (imm << 24);
 -        break;
 -    case 15:
 -        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
 -            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
 -        break;
 -    }
 -    if (op) {
 -        imm = ~imm;
 -    }
 -    return dup_const(MO_32, imm);
 -}
 -
  static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
                          GVecGen2iFn *fn)
  {
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
      a64_translate_init();
  }
 +uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
 +{
-+    /*
++    /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
 +     * Expand the encoded constant.
 +     * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
 +     * We choose to not special-case this and will behave as if a
 +     * valid constant encoding of 0 had been given.
 +     * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
 +     */
 +    switch (cmode) {
 +    case 0: case 1:
 +        /* no-op */
 +        break;
 +    case 2: case 3:
 ...
 +        imm = ~imm;
 +    }
 +    return dup_const(MO_32, imm);
 +}
 +
-+static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
+ /* Generate a label used for skipping this instruction */
-+                        GVecGen2iFn *fn)
+ void arm_gen_condlabel(DisasContext *s)
-+{
+ {
 +    uint64_t imm;
 +    int reg_ofs, vec_size;
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
 +        return false;
 +    }
 +
 +    /* UNDEF accesses to D16-D31 if they don't exist. */
 +    if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
 +        return false;
 +    }
 +
 +    if (a->vd & a->q) {
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    reg_ofs = neon_reg_offset(a->vd, 0);
 +    vec_size = a->q ? 16 : 8;
 +    imm = asimd_imm_const(a->imm, a->cmode, a->op);
 +
 +    fn(MO_64, reg_ofs, reg_ofs, imm, vec_size, vec_size);
 +    return true;
 +}
 +
 +static void gen_VMOV_1r(unsigned vece, uint32_t dofs, uint32_t aofs,
 +                        int64_t c, uint32_t oprsz, uint32_t maxsz)
 +{
 +    tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, c);
 +}
 +
 +static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a)
 +{
 +    /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
 +    GVecGen2iFn *fn;
 +
 +    if ((a->cmode & 1) && a->cmode < 12) {
 +        /* for op=1, the imm will be inverted, so BIC becomes AND. */
 +        fn = a->op ? tcg_gen_gvec_andi : tcg_gen_gvec_ori;
 +    } else {
 +        /* There is one unallocated cmode/op combination in this space */
 +        if (a->cmode == 15 && a->op == 1) {
 +            return false;
 +        }
 +        fn = gen_VMOV_1r;
 +    }
 +    return do_1reg_imm(s, a, fn);
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
          /* Three register same length: handled by decodetree */
          return 1;
      } else if (insn & (1 << 4)) {
 -        if ((insn & 0x00380080) != 0) {
 -            /* Two registers and shift: handled by decodetree */
 -            return 1;
 -        } else { /* (insn & 0x00380080) == 0 */
 -            int invert, reg_ofs, vec_size;
 -
 -            if (q && (rd & 1)) {
 -                return 1;
 -            }
 -
 -            op = (insn >> 8) & 0xf;
 -            /* One register and immediate.  */
 -            imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
 -            invert = (insn & (1 << 5)) != 0;
 -            /* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
 -             * We choose to not special-case this and will behave as if a
 -             * valid constant encoding of 0 had been given.
 -             */
 -            switch (op) {
 -            case 0: case 1:
 -                /* no-op */
 -                break;
 -            case 2: case 3:
 -                imm <<= 8;
 -                break;
 -            case 4: case 5:
 -                imm <<= 16;
 -                break;
 -            case 6: case 7:
 -                imm <<= 24;
 -                break;
 -            case 8: case 9:
 -                imm |= imm << 16;
 -                break;
 -            case 10: case 11:
 -                imm = (imm << 8) | (imm << 24);
 -                break;
 -            case 12:
 -                imm = (imm << 8) | 0xff;
 -                break;
 -            case 13:
 -                imm = (imm << 16) | 0xffff;
 -                break;
 -            case 14:
 -                imm |= (imm << 8) | (imm << 16) | (imm << 24);
 -                if (invert) {
 -                    imm = ~imm;
 -                }
 -                break;
 -            case 15:
 -                if (invert) {
 -                    return 1;
 -                }
 -                imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
 -                      | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
 -                break;
 -            }
 -            if (invert) {
 -                imm = ~imm;
 -            }
 -
 -            reg_ofs = neon_reg_offset(rd, 0);
 -            vec_size = q ? 16 : 8;
 -
 -            if (op & 1 && op < 12) {
 -                if (invert) {
 -                    /* The immediate value has already been inverted,
 -                     * so BIC becomes AND.
 -                     */
 -                    tcg_gen_gvec_andi(MO_32, reg_ofs, reg_ofs, imm,
 -                                      vec_size, vec_size);
 -                } else {
 -                    tcg_gen_gvec_ori(MO_32, reg_ofs, reg_ofs, imm,
 -                                     vec_size, vec_size);
 -                }
 -            } else {
 -                /* VMOV, VMVN.  */
 -                if (op == 14 && invert) {
 -                    TCGv_i64 t64 = tcg_temp_new_i64();
 -
 -                    for (pass = 0; pass <= q; ++pass) {
 -                        uint64_t val = 0;
 -                        int n;
 -
 -                        for (n = 0; n < 8; n++) {
 -                            if (imm & (1 << (n + pass * 8))) {
 -                                val |= 0xffull << (n * 8);
 -                            }
 -                        }
 -                        tcg_gen_movi_i64(t64, val);
 -                        neon_store_reg64(t64, rd + pass);
 -                    }
 -                    tcg_temp_free_i64(t64);
 -                } else {
 -                    tcg_gen_gvec_dup_imm(MO_32, reg_ofs, vec_size,
 -                                         vec_size, imm);
 -                }
 -            }
 -        }
 +        /* Two registers and shift or reg and imm: handled by decodetree */
 +        return 1;
      } else { /* (insn & 0x00800010 == 0x00800000) */
          if (size != 3) {
              op = (insn >> 8) & 0xf;
 --
 .20.1

-[PULL 08/29] target/arm: Convert sha1 and sha256 to gvec helpers
+[PULL 10/24] target/arm: Use asimd_imm_const for A64 decode
-From: Richard Henderson <richard.henderson@linaro.org>
+The A64 AdvSIMD modified-immediate grouping uses almost the same
 constant encoding that A32 Neon does; reuse asimd_imm_const() (to
 which we add the AArch64-specific case for cmode 15 op 1) instead of
 reimplementing it all.
-Do not yet convert the helpers to loop over opr_sz, but the
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-descriptor allows the vector tail to be cleared.  Which fixes
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-an existing bug vs SVE.
+Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
 ---
  target/arm/translate.h     |  3 +-
  target/arm/translate-a64.c | 86 ++++----------------------------------
  target/arm/translate.c     | 17 +++++++-
 files changed, 24 insertions(+), 82 deletions(-)
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+diff --git a/target/arm/translate.h b/target/arm/translate.h
 Message-id: 20200514212831.31248-5-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/helper.h             |  12 ++--
  target/arm/neon-dp.decode       |  12 ++--
  target/arm/crypto_helper.c      |  24 +++++--
  target/arm/translate-a64.c      |  34 ++++-----
  target/arm/translate-neon.inc.c | 124 +++++---------------------------
  target/arm/translate.c          |  24 ++-----
 files changed, 67 insertions(+), 163 deletions(-)
 diff --git a/target/arm/helper.h b/target/arm/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
+--- a/target/arm/translate.h
-+++ b/target/arm/helper.h
++++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
- DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+  * VMVN and VBIC (when cmode < 14 && op == 1).
+  *
- DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+  * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
--DEF_HELPER_FLAGS_2(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr)
+- * callers must catch this.
--DEF_HELPER_FLAGS_2(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr)
++ * callers must catch this; we return the 64-bit constant value defined
-+DEF_HELPER_FLAGS_3(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
++ * for AArch64.
-+DEF_HELPER_FLAGS_3(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+  *
+  * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
--DEF_HELPER_FLAGS_3(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
+  * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
 -DEF_HELPER_FLAGS_3(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
 -DEF_HELPER_FLAGS_2(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr)
 -DEF_HELPER_FLAGS_3(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
 +DEF_HELPER_FLAGS_4(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_3(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/neon-dp.decode
 +++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VPADD_3s         1111 001 0 0 . .. .... .... 1011 . . . 1 .... @3same_q0
  VQRDMLAH_3s      1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
 +@3same_crypto    .... .... .... .... .... .... .... .... \
 +                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 q=1
 +
  SHA1_3s          1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \
                   vm=%vm_dp vn=%vn_dp vd=%vd_dp
 -SHA256H_3s       1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... \
 -                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
 -SHA256H2_3s      1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... \
 -                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
 -SHA256SU1_3s     1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... \
 -                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
 +SHA256H_3s       1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
 +SHA256H2_3s      1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
 +SHA256SU1_3s     1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
  VFMA_fp_3s       1111 001 0 0 . 0 . .... .... 1100 ... 1 .... @3same_fp
  VFMS_fp_3s       1111 001 0 0 . 1 . .... .... 1100 ... 1 .... @3same_fp
 diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/crypto_helper.c
 +++ b/target/arm/crypto_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha1_3reg)(void *vd, void *vn, void *vm, uint32_t op)
      rd[1] = d.l[1];
  }
 -void HELPER(crypto_sha1h)(void *vd, void *vm)
 +void HELPER(crypto_sha1h)(void *vd, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rm = vm;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha1h)(void *vd, void *vm)
      rd[0] = m.l[0];
      rd[1] = m.l[1];
 +
 +    clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sha1su1)(void *vd, void *vm)
 +void HELPER(crypto_sha1su1)(void *vd, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rm = vm;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha1su1)(void *vd, void *vm)
      rd[0] = d.l[0];
      rd[1] = d.l[1];
 +
 +    clear_tail_16(vd, desc);
  }
  /*
@@ -XXX,XX +XXX,XX @@ static uint32_t s1(uint32_t x)
      return ror32(x, 17) ^ ror32(x, 19) ^ (x >> 10);
  }
 -void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm)
 +void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm)
      rd[0] = d.l[0];
      rd[1] = d.l[1];
 +
 +    clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm)
 +void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm)
      rd[0] = d.l[0];
      rd[1] = d.l[1];
 +
 +    clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sha256su0)(void *vd, void *vm)
 +void HELPER(crypto_sha256su0)(void *vd, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rm = vm;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256su0)(void *vd, void *vm)
      rd[0] = d.l[0];
      rd[1] = d.l[1];
 +
 +    clear_tail_16(vd, desc);
  }
 -void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm)
 +void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm, uint32_t desc)
  {
      uint64_t *rd = vd;
      uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm)
      rd[0] = d.l[0];
      rd[1] = d.l[1];
 +
 +    clear_tail_16(vd, desc);
  }
  /*
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
-     int rm = extract32(insn, 16, 5);
+ {
      int rn = extract32(insn, 5, 5);
      int rd = extract32(insn, 0, 5);
--    CryptoThreeOpFn *genfn;
+     int cmode = extract32(insn, 12, 4);
--    TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
+-    int cmode_3_1 = extract32(cmode, 1, 3);
-+    gen_helper_gvec_3 *genfn;
+-    int cmode_0 = extract32(cmode, 0, 1);
-     bool feature;
+     int o2 = extract32(insn, 11, 1);
+     uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
-     if (size != 0) {
+     bool is_neg = extract32(insn, 29, 1);
-@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
          return;
      }
--    tcg_rd_ptr = vec_full_reg_ptr(s, rd);
+-    /* See AdvSIMDExpandImm() in ARM ARM */
--    tcg_rn_ptr = vec_full_reg_ptr(s, rn);
+-    switch (cmode_3_1) {
--    tcg_rm_ptr = vec_full_reg_ptr(s, rm);
+-    case 0: /* Replicate(Zeros(24):imm8, 2) */
--
+-    case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
-     if (genfn) {
+-    case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
--        genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr);
+-    case 3: /* Replicate(imm8:Zeros(24), 2) */
-+        gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn);
+-    {
-     } else {
+-        int shift = cmode_3_1 * 8;
-         TCGv_i32 tcg_opcode = tcg_const_i32(opcode);
+-        imm = bitfield_replicate(abcdefgh << shift, 32);
-+        TCGv_ptr tcg_rd_ptr = vec_full_reg_ptr(s, rd);
+-        break;
 +        TCGv_ptr tcg_rn_ptr = vec_full_reg_ptr(s, rn);
 +        TCGv_ptr tcg_rm_ptr = vec_full_reg_ptr(s, rm);
          gen_helper_crypto_sha1_3reg(tcg_rd_ptr, tcg_rn_ptr,
                                      tcg_rm_ptr, tcg_opcode);
 -        tcg_temp_free_i32(tcg_opcode);
 -    }
+-    case 4: /* Replicate(Zeros(8):imm8, 4) */
--    tcg_temp_free_ptr(tcg_rd_ptr);
+-    case 5: /* Replicate(imm8:Zeros(8), 4) */
--    tcg_temp_free_ptr(tcg_rn_ptr);
+-    {
--    tcg_temp_free_ptr(tcg_rm_ptr);
+-        int shift = (cmode_3_1 & 0x1) * 8;
-+        tcg_temp_free_i32(tcg_opcode);
+-        imm = bitfield_replicate(abcdefgh << shift, 16);
-+        tcg_temp_free_ptr(tcg_rd_ptr);
+-        break;
-+        tcg_temp_free_ptr(tcg_rn_ptr);
+-    }
-+        tcg_temp_free_ptr(tcg_rm_ptr);
+-    case 6:
-+    }
+-        if (cmode_0) {
- }
+-            /* Replicate(Zeros(8):imm8:Ones(16), 2) */
+-            imm = (abcdefgh << 16) | 0xffff;
- /* Crypto two-reg SHA
+-        } else {
-@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
+-            /* Replicate(Zeros(16):imm8:Ones(8), 2) */
-     int opcode = extract32(insn, 12, 5);
+-            imm = (abcdefgh << 8) | 0xff;
-     int rn = extract32(insn, 5, 5);
+-        }
-     int rd = extract32(insn, 0, 5);
+-        imm = bitfield_replicate(imm, 32);
--    CryptoTwoOpFn *genfn;
+-        break;
-+    gen_helper_gvec_2 *genfn;
+-    case 7:
-     bool feature;
+-        if (!cmode_0 && !is_neg) {
--    TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
+-            imm = bitfield_replicate(abcdefgh, 8);
+-        } else if (!cmode_0 && is_neg) {
-     if (size != 0) {
+-            int i;
-         unallocated_encoding(s);
+-            imm = 0;
-@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
+-            for (i = 0; i < 8; i++) {
-     if (!fp_access_check(s)) {
+-                if ((abcdefgh) & (1 << i)) {
-         return;
+-                    imm |= 0xffULL << (i * 8);
-     }
+-                }
--
+-            }
--    tcg_rd_ptr = vec_full_reg_ptr(s, rd);
+-        } else if (cmode_0) {
--    tcg_rn_ptr = vec_full_reg_ptr(s, rn);
+-            if (is_neg) {
--
+-                imm = (abcdefgh & 0x3f) << 48;
--    genfn(tcg_rd_ptr, tcg_rn_ptr);
+-                if (abcdefgh & 0x80) {
--
+-                    imm |= 0x8000000000000000ULL;
--    tcg_temp_free_ptr(tcg_rd_ptr);
+-                }
--    tcg_temp_free_ptr(tcg_rn_ptr);
+-                if (abcdefgh & 0x40) {
-+    gen_gvec_op2_ool(s, true, rd, rn, 0, genfn);
+-                    imm |= 0x3fc0000000000000ULL;
- }
+-                } else {
+-                    imm |= 0x4000000000000000ULL;
- static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
+-                }
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
+-            } else {
-index XXXXXXX..XXXXXXX 100644
+-                if (o2) {
---- a/target/arm/translate-neon.inc.c
+-                    /* FMOV (vector, immediate) - half-precision */
-+++ b/target/arm/translate-neon.inc.c
+-                    imm = vfp_expand_imm(MO_16, abcdefgh);
-@@ -XXX,XX +XXX,XX @@ DO_3SAME_CMP(VCGE_S, TCG_COND_GE)
+-                    /* now duplicate across the lanes */
- DO_3SAME_CMP(VCGE_U, TCG_COND_GEU)
+-                    imm = bitfield_replicate(imm, 16);
- DO_3SAME_CMP(VCEQ, TCG_COND_EQ)
+-                } else {
+-                    imm = (abcdefgh & 0x3f) << 19;
--static void gen_VMUL_p_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+-                    if (abcdefgh & 0x80) {
--                           uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)
+-                        imm |= 0x80000000;
--{
+-                    }
--    tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz,
+-                    if (abcdefgh & 0x40) {
--                       0, gen_helper_gvec_pmul_b);
+-                        imm |= 0x3e000000;
--}
+-                    } else {
-+#define WRAP_OOL_FN(WRAPNAME, FUNC)                                        \
+-                        imm |= 0x40000000;
-+    static void WRAPNAME(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,  \
+-                    }
-+                         uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)  \
+-                    imm |= (imm << 32);
-+    {                                                                      \
+-                }
-+        tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, 0, FUNC); \
+-            }
-+    }
+-        }
-+
+-        break;
-+WRAP_OOL_FN(gen_VMUL_p_3s, gen_helper_gvec_pmul_b)
+-    default:
+-        g_assert_not_reached();
  static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
  {
@@ -XXX,XX +XXX,XX @@ static bool trans_SHA1_3s(DisasContext *s, arg_SHA1_3s *a)
      return true;
  }
 -static bool trans_SHA256H_3s(DisasContext *s, arg_SHA256H_3s *a)
 -{
 -    TCGv_ptr ptr1, ptr2, ptr3;
 -
 -    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
 -        !dc_isar_feature(aa32_sha2, s)) {
 -        return false;
 +#define DO_SHA2(NAME, FUNC)                                             \
 +    WRAP_OOL_FN(gen_##NAME##_3s, FUNC)                                  \
 +    static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a)        \
 +    {                                                                   \
 +        if (!dc_isar_feature(aa32_sha2, s)) {                           \
 +            return false;                                               \
 +        }                                                               \
 +        return do_3same(s, a, gen_##NAME##_3s);                         \
      }
 -    /* UNDEF accesses to D16-D31 if they don't exist. */
 -    if (!dc_isar_feature(aa32_simd_r32, s) &&
 -        ((a->vd | a->vn | a->vm) & 0x10)) {
 -        return false;
 -    }
 -
--    if ((a->vn | a->vm | a->vd) & 1) {
+-    if (cmode_3_1 != 7 && is_neg) {
--        return false;
+-        imm = ~imm;
--    }
++    if (cmode == 15 && o2 && !is_neg) {
--
++        /* FMOV (vector, immediate) - half-precision */
--    if (!vfp_access_check(s)) {
++        imm = vfp_expand_imm(MO_16, abcdefgh);
--        return true;
++        /* now duplicate across the lanes */
--    }
++        imm = bitfield_replicate(imm, 16);
--
++    } else {
--    ptr1 = vfp_reg_ptr(true, a->vd);
++        imm = asimd_imm_const(abcdefgh, cmode, is_neg);
--    ptr2 = vfp_reg_ptr(true, a->vn);
+     }
--    ptr3 = vfp_reg_ptr(true, a->vm);
--    gen_helper_crypto_sha256h(ptr1, ptr2, ptr3);
+     if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
 -    tcg_temp_free_ptr(ptr1);
 -    tcg_temp_free_ptr(ptr2);
 -    tcg_temp_free_ptr(ptr3);
 -
 -    return true;
 -}
 -
 -static bool trans_SHA256H2_3s(DisasContext *s, arg_SHA256H2_3s *a)
 -{
 -    TCGv_ptr ptr1, ptr2, ptr3;
 -
 -    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
 -        !dc_isar_feature(aa32_sha2, s)) {
 -        return false;
 -    }
 -
 -    /* UNDEF accesses to D16-D31 if they don't exist. */
 -    if (!dc_isar_feature(aa32_simd_r32, s) &&
 -        ((a->vd | a->vn | a->vm) & 0x10)) {
 -        return false;
 -    }
 -
 -    if ((a->vn | a->vm | a->vd) & 1) {
 -        return false;
 -    }
 -
 -    if (!vfp_access_check(s)) {
 -        return true;
 -    }
 -
 -    ptr1 = vfp_reg_ptr(true, a->vd);
 -    ptr2 = vfp_reg_ptr(true, a->vn);
 -    ptr3 = vfp_reg_ptr(true, a->vm);
 -    gen_helper_crypto_sha256h2(ptr1, ptr2, ptr3);
 -    tcg_temp_free_ptr(ptr1);
 -    tcg_temp_free_ptr(ptr2);
 -    tcg_temp_free_ptr(ptr3);
 -
 -    return true;
 -}
 -
 -static bool trans_SHA256SU1_3s(DisasContext *s, arg_SHA256SU1_3s *a)
 -{
 -    TCGv_ptr ptr1, ptr2, ptr3;
 -
 -    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
 -        !dc_isar_feature(aa32_sha2, s)) {
 -        return false;
 -    }
 -
 -    /* UNDEF accesses to D16-D31 if they don't exist. */
 -    if (!dc_isar_feature(aa32_simd_r32, s) &&
 -        ((a->vd | a->vn | a->vm) & 0x10)) {
 -        return false;
 -    }
 -
 -    if ((a->vn | a->vm | a->vd) & 1) {
 -        return false;
 -    }
 -
 -    if (!vfp_access_check(s)) {
 -        return true;
 -    }
 -
 -    ptr1 = vfp_reg_ptr(true, a->vd);
 -    ptr2 = vfp_reg_ptr(true, a->vn);
 -    ptr3 = vfp_reg_ptr(true, a->vm);
 -    gen_helper_crypto_sha256su1(ptr1, ptr2, ptr3);
 -    tcg_temp_free_ptr(ptr1);
 -    tcg_temp_free_ptr(ptr2);
 -    tcg_temp_free_ptr(ptr3);
 -
 -    return true;
 -}
 +DO_SHA2(SHA256H, gen_helper_crypto_sha256h)
 +DO_SHA2(SHA256H2, gen_helper_crypto_sha256h2)
 +DO_SHA2(SHA256SU1, gen_helper_crypto_sha256su1)
  #define DO_3SAME_64(INSN, FUNC)                                         \
      static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
-     int vec_size;
+     case 14:
-     uint32_t imm;
+         if (op) {
-     TCGv_i32 tmp, tmp2, tmp3, tmp4, tmp5;
+             /*
--    TCGv_ptr ptr1, ptr2;
+-             * This is the only case where the top and bottom 32 bits
-+    TCGv_ptr ptr1;
+-             * of the encoded constant differ.
-     TCGv_i64 tmp64;
++             * This and cmode == 15 op == 1 are the only cases where
++             * the top and bottom 32 bits of the encoded constant differ.
-     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+              */
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
+             uint64_t imm64 = 0;
-                     if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) {
+             int n;
-                         return 1;
+@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
-                     }
+         imm |= (imm << 8) | (imm << 16) | (imm << 24);
--                    ptr1 = vfp_reg_ptr(true, rd);
+         break;
--                    ptr2 = vfp_reg_ptr(true, rm);
+     case 15:
--
++        if (op) {
--                    gen_helper_crypto_sha1h(ptr1, ptr2);
++            /* Reserved encoding for AArch32; valid for AArch64 */
--
++            uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
--                    tcg_temp_free_ptr(ptr1);
++            if (imm & 0x80) {
--                    tcg_temp_free_ptr(ptr2);
++                imm64 |= 0x8000000000000000ULL;
-+                    tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0,
++            }
-+                                       gen_helper_crypto_sha1h);
++            if (imm & 0x40) {
-                     break;
++                imm64 |= 0x3fc0000000000000ULL;
-                 case NEON_2RM_SHA1SU1:
++            } else {
-                     if ((rm | rd) & 1) {
++                imm64 |= 0x4000000000000000ULL;
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
++            }
-                     } else if (!dc_isar_feature(aa32_sha1, s)) {
++            return imm64;
-                         return 1;
++        }
-                     }
+         imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
--                    ptr1 = vfp_reg_ptr(true, rd);
+             | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
--                    ptr2 = vfp_reg_ptr(true, rm);
+         break;
 -                    if (q) {
 -                        gen_helper_crypto_sha256su0(ptr1, ptr2);
 -                    } else {
 -                        gen_helper_crypto_sha1su1(ptr1, ptr2);
 -                    }
 -                    tcg_temp_free_ptr(ptr1);
 -                    tcg_temp_free_ptr(ptr2);
 +                    tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0,
 +                                       q ? gen_helper_crypto_sha256su0
 +                                       : gen_helper_crypto_sha1su1);
                      break;
 -
                  case NEON_2RM_VMVN:
                      tcg_gen_gvec_not(0, rd_ofs, rm_ofs, vec_size, vec_size);
                      break;
 --
 .20.1

-[PULL 10/29] target/arm: Split helper_crypto_sm3tt
+[PULL 11/24] target/arm: Use dup_const() instead of bitfield_replicate()
-From: Richard Henderson <richard.henderson@linaro.org>
+Use dup_const() instead of bitfield_replicate() in
 disas_simd_mod_imm().
-Rather than passing an opcode to a helper, fully decode the
+(We can't replace the other use of bitfield_replicate() in this file,
-operation at translate time.  Use clear_tail_16 to zap the
+in logic_imm_decode_wmask(), because that location needs to handle 2
-balance of the SVE register with the AdvSIMD write.
+and 4 bit elements, which dup_const() cannot.)
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200514212831.31248-7-richard.henderson@linaro.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
 ---
- target/arm/helper.h        |  5 ++++-
+ target/arm/translate-a64.c | 2 +-
- target/arm/crypto_helper.c | 24 ++++++++++++++++++------
+file changed, 1 insertion(+), 1 deletion(-)
  target/arm/translate-a64.c | 21 +++++----------------
 files changed, 27 insertions(+), 23 deletions(-)
-diff --git a/target/arm/helper.h b/target/arm/helper.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
-+++ b/target/arm/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(crypto_sha512su1, TCG_CALL_NO_RWG,
-                    void, ptr, ptr, ptr, i32)
--DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32, i32)
-+DEF_HELPER_FLAGS_4(crypto_sm3tt1a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(crypto_sm3tt1b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(crypto_sm3tt2a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(crypto_sm3tt2b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(crypto_sm3partw1, TCG_CALL_NO_RWG,
-                    void, ptr, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(crypto_sm3partw2, TCG_CALL_NO_RWG,
-diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/crypto_helper.c
-+++ b/target/arm/crypto_helper.c
-@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm, uint32_t desc)
-     clear_tail_16(vd, desc);
- }
--void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2,
--                          uint32_t opcode)
-+static inline void QEMU_ALWAYS_INLINE
-+crypto_sm3tt(uint64_t *rd, uint64_t *rn, uint64_t *rm,
-+             uint32_t desc, uint32_t opcode)
- {
--    uint64_t *rd = vd;
--    uint64_t *rn = vn;
--    uint64_t *rm = vm;
-     union CRYPTO_STATE d = { .l = { rd[0], rd[1] } };
-     union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };
-     union CRYPTO_STATE m = { .l = { rm[0], rm[1] } };
-+    uint32_t imm2 = simd_data(desc);
-     uint32_t t;
-     assert(imm2 < 4);
-@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2,
-         /* SM3TT2B */
-         t = cho(CR_ST_WORD(d, 3), CR_ST_WORD(d, 2), CR_ST_WORD(d, 1));
-     } else {
--        g_assert_not_reached();
-+        qemu_build_not_reached();
-     }
-     t += CR_ST_WORD(d, 0) + CR_ST_WORD(m, imm2);
-@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2,
-     rd[0] = d.l[0];
-     rd[1] = d.l[1];
-+
-+    clear_tail_16(rd, desc);
- }
-+#define DO_SM3TT(NAME, OPCODE) \
-+    void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
-+    { crypto_sm3tt(vd, vn, vm, desc, OPCODE); }
-+
-+DO_SM3TT(crypto_sm3tt1a, 0)
-+DO_SM3TT(crypto_sm3tt1b, 1)
-+DO_SM3TT(crypto_sm3tt2a, 2)
-+DO_SM3TT(crypto_sm3tt2b, 3)
-+
-+#undef DO_SM3TT
-+
- static uint8_t const sm4_sbox[] = {
-xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
-x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_crypto_xar(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
-  */
+         /* FMOV (vector, immediate) - half-precision */
- static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn)
+         imm = vfp_expand_imm(MO_16, abcdefgh);
- {
+         /* now duplicate across the lanes */
-+    static gen_helper_gvec_3 * const fns[4] = {
+-        imm = bitfield_replicate(imm, 16);
-+        gen_helper_crypto_sm3tt1a, gen_helper_crypto_sm3tt1b,
++        imm = dup_const(MO_16, imm);
-+        gen_helper_crypto_sm3tt2a, gen_helper_crypto_sm3tt2b,
+     } else {
-+    };
+         imm = asimd_imm_const(abcdefgh, cmode, is_neg);
      int opcode = extract32(insn, 10, 2);
      int imm2 = extract32(insn, 12, 2);
      int rm = extract32(insn, 16, 5);
      int rn = extract32(insn, 5, 5);
      int rd = extract32(insn, 0, 5);
 -    TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
 -    TCGv_i32 tcg_imm2, tcg_opcode;
      if (!dc_isar_feature(aa64_sm3, s)) {
          unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn)
          return;
      }
--    tcg_rd_ptr = vec_full_reg_ptr(s, rd);
--    tcg_rn_ptr = vec_full_reg_ptr(s, rn);
--    tcg_rm_ptr = vec_full_reg_ptr(s, rm);
--    tcg_imm2   = tcg_const_i32(imm2);
--    tcg_opcode = tcg_const_i32(opcode);
--
--    gen_helper_crypto_sm3tt(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr, tcg_imm2,
--                            tcg_opcode);
--
--    tcg_temp_free_ptr(tcg_rd_ptr);
--    tcg_temp_free_ptr(tcg_rn_ptr);
--    tcg_temp_free_ptr(tcg_rm_ptr);
--    tcg_temp_free_i32(tcg_imm2);
--    tcg_temp_free_i32(tcg_opcode);
-+    gen_gvec_op3_ool(s, true, rd, rn, rm, imm2, fns[opcode]);
- }
- /* C3.6 Data processing - SIMD, inc Crypto
 --
 .20.1

-[PULL 28/29] target/arm: Convert VCVT fixed-point ops to decodetree
+[PULL 12/24] target/arm: Implement MVE logical immediate insns
-Convert the VCVT fixed-point conversion operations in the
+Implement the MVE logical-immediate insns (VMOV, VMVN,
-Neon 2-regs-and-shift group to decodetree.
+VORR and VBIC). These have essentially the same encoding
 as their Neon equivalents, and we implement the decode
 in the same way.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200522145520.6778-9-peter.maydell@linaro.org
+Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       | 11 +++++
+ target/arm/helper-mve.h    |  4 +++
- target/arm/translate-neon.inc.c | 49 +++++++++++++++++++++
+ target/arm/mve.decode      | 17 +++++++++++++
- target/arm/translate.c          | 75 +--------------------------------
+ target/arm/mve_helper.c    | 24 ++++++++++++++++++
-files changed, 62 insertions(+), 73 deletions(-)
+ target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
 files changed, 95 insertions(+)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
+--- a/target/arm/helper-mve.h
-+++ b/target/arm/neon-dp.decode
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
- @2reg_shll_b     .... ... . . . 001 shift:3  .... .... 0 . . . .... \
+ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
-                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
+ DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
+ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
 +# We use size=0 for fp32 and size=1 for fp16 to match the 3-same encodings.
 +@2reg_vcvt       .... ... . . . 1 ..... .... .... . q:1 . . .... \
 +                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i5
 +
- VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
++DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
- VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
++DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
- VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
++DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
-@@ -XXX,XX +XXX,XX @@ VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
+diff --git a/target/arm/mve.decode b/target/arm/mve.decode
- VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
+index XXXXXXX..XXXXXXX 100644
- VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
+--- a/target/arm/mve.decode
- VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
++++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
  # VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
  %size_28 28:1 !function=plus_1
 +# 1imm format immediate
 +%imm_28_16_0 28:1 16:3 0:4
 +
-+# VCVT fixed<->float conversions
+ &vldr_vstr rn qd imm p a w size l u
-+# TODO: FP16 fixed<->float conversions are opc==0b1100 and 0b1101
+ &1op qd qm size
-+VCVT_SF_2sh      1111 001 0 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
+ &2op qd qm qn size
-+VCVT_UF_2sh      1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
+ &2scalar qd qn rm size
-+VCVT_FS_2sh      1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
++&1imm qd imm cmode op
-+VCVT_FU_2sh      1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
+ @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
  # Note that both Rn and Qd are 3 bits only (no D bit)
@@ -XXX,XX +XXX,XX @@
  @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
  @2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \
       size=%size_28
 +@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0
  # The _rev suffix indicates that Vn and Vm are reversed. This is
  # the case for shifts. In the Arm ARM these insns are documented
@@ -XXX,XX +XXX,XX @@ VADDV            111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd
  # Predicate operations
  %mask_22_13      22:1 13:3
  VPST             1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
 +
 +# Logical immediate operations (1 reg and modified-immediate)
 +
 +# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
 +# not in a way we can conveniently represent in decodetree without
 +# a lot of repetition:
 +# VORR: op=0, (cmode & 1) && cmode < 12
 +# VBIC: op=1, (cmode & 1) && cmode < 12
 +# VMOV: everything else
 +# So we have a single decode line and check the cmode/op in the
 +# trans function.
 +Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
+--- a/target/arm/mve_helper.c
-+++ b/target/arm/translate-neon.inc.c
++++ b/target/arm/mve_helper.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a)
+@@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG)
-     };
+ DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
-     return do_vshll_2sh(s, a, widenfn[a->size], true);
+ DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
 +/*
 + * 1 operand immediates: Vda is destination and possibly also one source.
 + * All these insns work at 64-bit widths.
 + */
 +#define DO_1OP_IMM(OP, FN)                                              \
 +    void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm)    \
 +    {                                                                   \
 +        uint64_t *da = vda;                                             \
 +        uint16_t mask = mve_element_mask(env);                          \
 +        unsigned e;                                                     \
 +        for (e = 0; e < 16 / 8; e++, mask >>= 8) {                      \
 +            mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask);            \
 +        }                                                               \
 +        mve_advance_vpt(env);                                           \
 +    }
 +
 +#define DO_MOVI(N, I) (I)
 +#define DO_ANDI(N, I) ((N) & (I))
 +#define DO_ORRI(N, I) ((N) | (I))
 +
 +DO_1OP_IMM(vmovi, DO_MOVI)
 +DO_1OP_IMM(vandi, DO_ANDI)
 +DO_1OP_IMM(vorri, DO_ORRI)
 +
  #define DO_2OP(OP, ESIZE, TYPE, FN)                                     \
      void HELPER(glue(mve_, OP))(CPUARMState *env,                       \
                                  void *vd, void *vn, void *vm)           \
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
  typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
  typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
  typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
 +typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
  /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
  static inline long mve_qreg_offset(unsigned reg)
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
      mve_update_eci(s);
      return true;
  }
 +
-+static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
++static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
 +                      NeonGenTwoSingleOPFn *fn)
 +{
-+    /* FP operations in 2-reg-and-shift group */
++    TCGv_ptr qd;
-+    TCGv_i32 tmp, shiftv;
++    uint64_t imm;
 +    TCGv_ptr fpstatus;
 +    int pass;
 +
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
++    if (!dc_isar_feature(aa32_mve, s) ||
 +        !mve_check_qreg_bank(s, a->qd) ||
 +        !fn) {
 +        return false;
 +    }
-+
++    if (!mve_eci_check(s) || !vfp_access_check(s)) {
 +    /* UNDEF accesses to D16-D31 if they don't exist. */
 +    if (!dc_isar_feature(aa32_simd_r32, s) &&
 +        ((a->vd | a->vm) & 0x10)) {
 +        return false;
 +    }
 +
 +    if ((a->vm | a->vd) & a->q) {
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
-+    fpstatus = get_fpstatus_ptr(1);
++    imm = asimd_imm_const(a->imm, a->cmode, a->op);
-+    shiftv = tcg_const_i32(a->shift);
++
-+    for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
++    qd = mve_qreg_ptr(a->qd);
-+        tmp = neon_load_reg(a->vm, pass);
++    fn(cpu_env, qd, tcg_constant_i64(imm));
-+        fn(tmp, tmp, shiftv, fpstatus);
++    tcg_temp_free_ptr(qd);
-+        neon_store_reg(a->vd, pass, tmp);
++    mve_update_eci(s);
 +    }
 +    tcg_temp_free_ptr(fpstatus);
 +    tcg_temp_free_i32(shiftv);
 +    return true;
 +}
 +
-+#define DO_FP_2SH(INSN, FUNC)                                           \
++static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
-+    static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a)  \
++{
-+    {                                                                   \
++    /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
-+        return do_fp_2sh(s, a, FUNC);                                   \
++    MVEGenOneOpImmFn *fn;
 +
 +    if ((a->cmode & 1) && a->cmode < 12) {
 +        if (a->op) {
 +            /*
 +             * For op=1, the immediate will be inverted by asimd_imm_const(),
 +             * so the VBIC becomes a logical AND operation.
 +             */
 +            fn = gen_helper_mve_vandi;
 +        } else {
 +            fn = gen_helper_mve_vorri;
 +        }
 +    } else {
 +        /* There is one unallocated cmode/op combination in this space */
 +        if (a->cmode == 15 && a->op == 1) {
 +            return false;
 +        }
 +        /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
 +        fn = gen_helper_mve_vmovi;
 +    }
-+
++    return do_1imm(s, a, fn);
-+DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos)
++}
 +DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos)
 +DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero)
 +DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero)
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
      int q;
      int rd, rn, rm, rd_ofs, rn_ofs, rm_ofs;
      int size;
 -    int shift;
      int pass;
      int u;
      int vec_size;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
          return 1;
      } else if (insn & (1 << 4)) {
          if ((insn & 0x00380080) != 0) {
 -            /* Two registers and shift.  */
 -            op = (insn >> 8) & 0xf;
 -
 -            switch (op) {
 -            case 0: /* VSHR */
 -            case 1: /* VSRA */
 -            case 2: /* VRSHR */
 -            case 3: /* VRSRA */
 -            case 4: /* VSRI */
 -            case 5: /* VSHL, VSLI */
 -            case 6: /* VQSHLU */
 -            case 7: /* VQSHL */
 -            case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
 -            case 9: /* VQSHRN, VQRSHRN */
 -            case 10: /* VSHLL, including VMOVL */
 -                return 1; /* handled by decodetree */
 -            default:
 -                break;
 -            }
 -
 -            if (insn & (1 << 7)) {
 -                /* 64-bit shift. */
 -                if (op > 7) {
 -                    return 1;
 -                }
 -                size = 3;
 -            } else {
 -                size = 2;
 -                while ((insn & (1 << (size + 19))) == 0)
 -                    size--;
 -            }
 -            shift = (insn >> 16) & ((1 << (3 + size)) - 1);
 -            if (op >= 14) {
 -                /* VCVT fixed-point.  */
 -                TCGv_ptr fpst;
 -                TCGv_i32 shiftv;
 -                VFPGenFixPointFn *fn;
 -
 -                if (!(insn & (1 << 21)) || (q && ((rd | rm) & 1))) {
 -                    return 1;
 -                }
 -
 -                if (!(op & 1)) {
 -                    if (u) {
 -                        fn = gen_helper_vfp_ultos;
 -                    } else {
 -                        fn = gen_helper_vfp_sltos;
 -                    }
 -                } else {
 -                    if (u) {
 -                        fn = gen_helper_vfp_touls_round_to_zero;
 -                    } else {
 -                        fn = gen_helper_vfp_tosls_round_to_zero;
 -                    }
 -                }
 -
 -                /* We have already masked out the must-be-1 top bit of imm6,
 -                 * hence this 32-shift where the ARM ARM has 64-imm6.
 -                 */
 -                shift = 32 - shift;
 -                fpst = get_fpstatus_ptr(1);
 -                shiftv = tcg_const_i32(shift);
 -                for (pass = 0; pass < (q ? 4 : 2); pass++) {
 -                    TCGv_i32 tmpf = neon_load_reg(rm, pass);
 -                    fn(tmpf, tmpf, shiftv, fpst);
 -                    neon_store_reg(rd, pass, tmpf);
 -                }
 -                tcg_temp_free_ptr(fpst);
 -                tcg_temp_free_i32(shiftv);
 -            } else {
 -                return 1;
 -            }
 +            /* Two registers and shift: handled by decodetree */
 +            return 1;
          } else { /* (insn & 0x00380080) == 0 */
              int invert, reg_ofs, vec_size;
 --
 .20.1

-[PULL 25/29] target/arm: Convert Neon narrowing shifts with op==8 to decodetree
+[PULL 13/24] target/arm: Implement MVE vector shift left by immediate insns
-Convert the Neon narrowing shifts where op==8 to decodetree:
+Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
- * VSHRN
+and VQSHLU.
- * VRSHRN
- * VQSHRUN
+The size-and-immediate encoding here is the same as Neon, and we
- * VQRSHRUN
+handle it the same way neon-dp.decode does.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200522145520.6778-6-peter.maydell@linaro.org
+Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       |  27 ++++++
+ target/arm/helper-mve.h    | 16 +++++++++++
- target/arm/translate-neon.inc.c | 167 ++++++++++++++++++++++++++++++++
+ target/arm/mve.decode      | 23 +++++++++++++++
- target/arm/translate.c          |   1 +
+ target/arm/mve_helper.c    | 57 ++++++++++++++++++++++++++++++++++++++
-files changed, 195 insertions(+)
+ target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
+files changed, 147 insertions(+)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
-index XXXXXXX..XXXXXXX 100644
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
---- a/target/arm/neon-dp.decode
+index XXXXXXX..XXXXXXX 100644
-+++ b/target/arm/neon-dp.decode
+--- a/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
++++ b/target/arm/helper-mve.h
- @2reg_shl_b      .... ... . . . 001 shift:3  .... .... 0 q:1 . . .... \
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
-                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0
+ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
+ DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
-+# Narrowing right shifts: here the Q bit is part of the opcode decode
+ DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
-+@2reg_shrn_d     .... ... . . . 1 ..... .... .... 0 . . . .... \
++
-+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 q=0 \
++DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+                 shift=%neon_rshift_i5
++DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+@2reg_shrn_s     .... ... . . . 01 .... .... .... 0 . . . .... \
++DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0 \
++
-+                 shift=%neon_rshift_i4
++DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+@2reg_shrn_h     .... ... . . . 001 ... .... .... 0 . . . .... \
++DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 \
++DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+                 shift=%neon_rshift_i3
++
-+
++DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
++DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
++DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
++
-@@ -XXX,XX +XXX,XX @@ VQSHL_U_64_2sh   1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
++DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
++DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
++DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
+diff --git a/target/arm/mve.decode b/target/arm/mve.decode
-+
+index XXXXXXX..XXXXXXX 100644
-+VSHRN_64_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
+--- a/target/arm/mve.decode
-+VSHRN_32_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
++++ b/target/arm/mve.decode
-+VSHRN_16_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
+@@ -XXX,XX +XXX,XX @@
-+
+ &2op qd qm qn size
-+VRSHRN_64_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
+ &2scalar qd qn rm size
-+VRSHRN_32_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
+ &1imm qd imm cmode op
-+VRSHRN_16_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
++&2shift qd qm shift size
-+
-+VQSHRUN_64_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
+ @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
-+VQSHRUN_32_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
+ # Note that both Rn and Qd are 3 bits only (no D bit)
-+VQSHRUN_16_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
+@@ -XXX,XX +XXX,XX @@
-+
+ @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
-+VQRSHRUN_64_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
+ @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
-+VQRSHRUN_32_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
-+VQRSHRUN_16_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
++@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
++@2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
-index XXXXXXX..XXXXXXX 100644
++@2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
---- a/target/arm/translate-neon.inc.c
++
-+++ b/target/arm/translate-neon.inc.c
+ # Vector loads and stores
-@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
- DO_2SHIFT_ENV(VQSHLU, qshlu_s)
+ # Widening loads and narrowing stores:
- DO_2SHIFT_ENV(VQSHL_U, qshl_u)
+@@ -XXX,XX +XXX,XX @@ VPST             1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
- DO_2SHIFT_ENV(VQSHL_S, qshl_s)
+ # So we have a single decode line and check the cmode/op in the
-+
+ # trans function.
-+static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
+ Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
-+                                NeonGenTwo64OpFn *shiftfn,
++
-+                                NeonGenNarrowEnvFn *narrowfn)
++# Shifts by immediate
 +
 +VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
 +VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
 +VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
 +
 +VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
 +VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
 +VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
 +
 +VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
 +VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
 +VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
 +
 +VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
 +VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
 +VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
      WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
  #define DO_UQRSHL_OP(N, M, satp) \
      WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
 +#define DO_SUQSHL_OP(N, M, satp) \
 +    WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
  DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
  DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
  DO_VADDV(vaddvub, 1, uint8_t)
  DO_VADDV(vaddvuh, 2, uint16_t)
  DO_VADDV(vaddvuw, 4, uint32_t)
 +
 +/* Shifts by immediate */
 +#define DO_2SHIFT(OP, ESIZE, TYPE, FN)                          \
 +    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
 +                                void *vm, uint32_t shift)       \
 +    {                                                           \
 +        TYPE *d = vd, *m = vm;                                  \
 +        uint16_t mask = mve_element_mask(env);                  \
 +        unsigned e;                                             \
 +        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
 +            mergemask(&d[H##ESIZE(e)],                          \
 +                      FN(m[H##ESIZE(e)], shift), mask);         \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +    }
 +
 +#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN)                      \
 +    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
 +                                void *vm, uint32_t shift)       \
 +    {                                                           \
 +        TYPE *d = vd, *m = vm;                                  \
 +        uint16_t mask = mve_element_mask(env);                  \
 +        unsigned e;                                             \
 +        bool qc = false;                                        \
 +        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
 +            bool sat = false;                                   \
 +            mergemask(&d[H##ESIZE(e)],                          \
 +                      FN(m[H##ESIZE(e)], shift, &sat), mask);   \
 +            qc |= sat & mask & 1;                               \
 +        }                                                       \
 +        if (qc) {                                               \
 +            env->vfp.qc[0] = qc;                                \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +    }
 +
 +/* provide unsigned 2-op shift helpers for all sizes */
 +#define DO_2SHIFT_U(OP, FN)                     \
 +    DO_2SHIFT(OP##b, 1, uint8_t, FN)            \
 +    DO_2SHIFT(OP##h, 2, uint16_t, FN)           \
 +    DO_2SHIFT(OP##w, 4, uint32_t, FN)
 +
 +#define DO_2SHIFT_SAT_U(OP, FN)                 \
 +    DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN)        \
 +    DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN)       \
 +    DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
 +#define DO_2SHIFT_SAT_S(OP, FN)                 \
 +    DO_2SHIFT_SAT(OP##b, 1, int8_t, FN)         \
 +    DO_2SHIFT_SAT(OP##h, 2, int16_t, FN)        \
 +    DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
 +
 +DO_2SHIFT_U(vshli_u, DO_VSHLU)
 +DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
 +DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
 +DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
  typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
  typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
  typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
 +typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
  typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
  typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
  typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
      }
      return do_1imm(s, a, fn);
  }
 +
 +static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
 +                      bool negateshift)
 +{
-+    /* 2-reg-and-shift narrowing-shift operations, size == 3 case */
++    TCGv_ptr qd, qm;
-+    TCGv_i64 constimm, rm1, rm2;
++    int shift = a->shift;
-+    TCGv_i32 rd;
++
-+
++    if (!dc_isar_feature(aa32_mve, s) ||
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
++        !mve_check_qreg_bank(s, a->qd | a->qm) ||
 +        !fn) {
 +        return false;
 +    }
-+
++    if (!mve_eci_check(s) || !vfp_access_check(s)) {
 +    /* UNDEF accesses to D16-D31 if they don't exist. */
 +    if (!dc_isar_feature(aa32_simd_r32, s) &&
 +        ((a->vd | a->vm) & 0x10)) {
 +        return false;
 +    }
 +
 +    if (a->vm & 1) {
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    /*
-+     * This is always a right shift, and the shiftfn is always a
++     * When we handle a right shift insn using a left-shift helper
-+     * left-shift helper, which thus needs the negated shift count.
++     * which permits a negative shift count to indicate a right-shift,
 +     * we must negate the shift count.
 +     */
-+    constimm = tcg_const_i64(-a->shift);
++    if (negateshift) {
-+    rm1 = tcg_temp_new_i64();
++        shift = -shift;
-+    rm2 = tcg_temp_new_i64();
++    }
 +
-+    /* Load both inputs first to avoid potential overwrite if rm == rd */
++    qd = mve_qreg_ptr(a->qd);
-+    neon_load_reg64(rm1, a->vm);
++    qm = mve_qreg_ptr(a->qm);
-+    neon_load_reg64(rm2, a->vm + 1);
++    fn(cpu_env, qd, qm, tcg_constant_i32(shift));
-+
++    tcg_temp_free_ptr(qd);
-+    shiftfn(rm1, rm1, constimm);
++    tcg_temp_free_ptr(qm);
-+    rd = tcg_temp_new_i32();
++    mve_update_eci(s);
 +    narrowfn(rd, cpu_env, rm1);
 +    neon_store_reg(a->vd, 0, rd);
 +
 +    shiftfn(rm2, rm2, constimm);
 +    rd = tcg_temp_new_i32();
 +    narrowfn(rd, cpu_env, rm2);
 +    neon_store_reg(a->vd, 1, rd);
 +
 +    tcg_temp_free_i64(rm1);
 +    tcg_temp_free_i64(rm2);
 +    tcg_temp_free_i64(constimm);
 +
 +    return true;
 +}
 +
-+static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
++#define DO_2SHIFT(INSN, FN, NEGATESHIFT)                         \
-+                                NeonGenTwoOpFn *shiftfn,
++    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
-+                                NeonGenNarrowEnvFn *narrowfn)
++    {                                                           \
-+{
++        static MVEGenTwoOpShiftFn * const fns[] = {             \
-+    /* 2-reg-and-shift narrowing-shift operations, size < 3 case */
++            gen_helper_mve_##FN##b,                             \
-+    TCGv_i32 constimm, rm1, rm2, rm3, rm4;
++            gen_helper_mve_##FN##h,                             \
-+    TCGv_i64 rtmp;
++            gen_helper_mve_##FN##w,                             \
-+    uint32_t imm;
++            NULL,                                               \
-+
++        };                                                      \
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
++        return do_2shift(s, a, fns[a->size], NEGATESHIFT);      \
-+        return false;
++    }
-+    }
++
-+
++DO_2SHIFT(VSHLI, vshli_u, false)
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
++DO_2SHIFT(VQSHLI_S, vqshli_s, false)
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
++DO_2SHIFT(VQSHLI_U, vqshli_u, false)
-+        ((a->vd | a->vm) & 0x10)) {
++DO_2SHIFT(VQSHLUI, vqshlui_s, false)
 +        return false;
 +    }
 +
 +    if (a->vm & 1) {
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    /*
 +     * This is always a right shift, and the shiftfn is always a
 +     * left-shift helper, which thus needs the negated shift count
 +     * duplicated into each lane of the immediate value.
 +     */
 +    if (a->size == 1) {
 +        imm = (uint16_t)(-a->shift);
 +        imm |= imm << 16;
 +    } else {
 +        /* size == 2 */
 +        imm = -a->shift;
 +    }
 +    constimm = tcg_const_i32(imm);
 +
 +    /* Load all inputs first to avoid potential overwrite */
 +    rm1 = neon_load_reg(a->vm, 0);
 +    rm2 = neon_load_reg(a->vm, 1);
 +    rm3 = neon_load_reg(a->vm + 1, 0);
 +    rm4 = neon_load_reg(a->vm + 1, 1);
 +    rtmp = tcg_temp_new_i64();
 +
 +    shiftfn(rm1, rm1, constimm);
 +    shiftfn(rm2, rm2, constimm);
 +
 +    tcg_gen_concat_i32_i64(rtmp, rm1, rm2);
 +    tcg_temp_free_i32(rm2);
 +
 +    narrowfn(rm1, cpu_env, rtmp);
 +    neon_store_reg(a->vd, 0, rm1);
 +
 +    shiftfn(rm3, rm3, constimm);
 +    shiftfn(rm4, rm4, constimm);
 +    tcg_temp_free_i32(constimm);
 +
 +    tcg_gen_concat_i32_i64(rtmp, rm3, rm4);
 +    tcg_temp_free_i32(rm4);
 +
 +    narrowfn(rm3, cpu_env, rtmp);
 +    tcg_temp_free_i64(rtmp);
 +    neon_store_reg(a->vd, 1, rm3);
 +    return true;
 +}
 +
 +#define DO_2SN_64(INSN, FUNC, NARROWFUNC)                               \
 +    static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a)  \
 +    {                                                                   \
 +        return do_2shift_narrow_64(s, a, FUNC, NARROWFUNC);             \
 +    }
 +#define DO_2SN_32(INSN, FUNC, NARROWFUNC)                               \
 +    static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a)  \
 +    {                                                                   \
 +        return do_2shift_narrow_32(s, a, FUNC, NARROWFUNC);             \
 +    }
 +
 +static void gen_neon_narrow_u32(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
 +{
 +    tcg_gen_extrl_i64_i32(dest, src);
 +}
 +
 +static void gen_neon_narrow_u16(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
 +{
 +    gen_helper_neon_narrow_u16(dest, src);
 +}
 +
 +static void gen_neon_narrow_u8(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
 +{
 +    gen_helper_neon_narrow_u8(dest, src);
 +}
 +
 +DO_2SN_64(VSHRN_64, gen_ushl_i64, gen_neon_narrow_u32)
 +DO_2SN_32(VSHRN_32, gen_ushl_i32, gen_neon_narrow_u16)
 +DO_2SN_32(VSHRN_16, gen_helper_neon_shl_u16, gen_neon_narrow_u8)
 +
 +DO_2SN_64(VRSHRN_64, gen_helper_neon_rshl_u64, gen_neon_narrow_u32)
 +DO_2SN_32(VRSHRN_32, gen_helper_neon_rshl_u32, gen_neon_narrow_u16)
 +DO_2SN_32(VRSHRN_16, gen_helper_neon_rshl_u16, gen_neon_narrow_u8)
 +
 +DO_2SN_64(VQSHRUN_64, gen_sshl_i64, gen_helper_neon_unarrow_sat32)
 +DO_2SN_32(VQSHRUN_32, gen_sshl_i32, gen_helper_neon_unarrow_sat16)
 +DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat8)
 +
 +DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_sat32)
 +DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_sat16)
 +DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_sat8)
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
              case 5: /* VSHL, VSLI */
              case 6: /* VQSHLU */
              case 7: /* VQSHL */
 +            case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
                  return 1; /* handled by decodetree */
              default:
                  break;
 --
 .20.1

-[PULL 22/29] target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree
+[PULL 14/24] target/arm: Implement MVE vector shift right by immediate insns
-Convert the VSHR 2-reg-shift insns to decodetree.
+Implement the MVE vector shift right by immediate insns VSHRI and
+VRSHRI.  As with Neon, we implement these by using helper functions
-Note that unlike the legacy decoder, we present the right shift
+which perform left shifts but allow negative shift counts to indicate
-amount to the trans_ function as a positive integer.
+right shifts.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200522145520.6778-3-peter.maydell@linaro.org
+Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       | 25 ++++++++++++++++++++
+ target/arm/helper-mve.h     | 12 ++++++++++++
- target/arm/translate-neon.inc.c | 41 +++++++++++++++++++++++++++++++++
+ target/arm/translate.h      | 20 ++++++++++++++++++++
- target/arm/translate.c          | 21 +----------------
+ target/arm/mve.decode       | 28 ++++++++++++++++++++++++++++
-files changed, 67 insertions(+), 20 deletions(-)
+ target/arm/mve_helper.c     |  7 +++++++
  target/arm/translate-mve.c  |  5 +++++
  target/arm/translate-neon.c | 18 ------------------
 files changed, 72 insertions(+), 18 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
+--- a/target/arm/helper-mve.h
-+++ b/target/arm/neon-dp.decode
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
- ######################################################################
+ DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
- &2reg_shift vm vd q shift size
+ DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
-+# Right shifts are encoded as N - shift, where N is the element size in bits.
++DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+%neon_rshift_i6  16:6 !function=rsub_64
++DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+%neon_rshift_i5  16:5 !function=rsub_32
++DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +%neon_rshift_i4  16:4 !function=rsub_16
 +%neon_rshift_i3  16:3 !function=rsub_8
 +
-+@2reg_shr_d      .... ... . . . ......  .... .... 1 q:1 . . .... \
+ DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 shift=%neon_rshift_i6
+ DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+@2reg_shr_s      .... ... . . . 1 ..... .... .... 0 q:1 . . .... \
+ DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+@2reg_shr_h      .... ... . . . 01 .... .... .... 0 q:1 . . .... \
+ DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4
+ DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+@2reg_shr_b      .... ... . . . 001 ... .... .... 0 q:1 . . .... \
+ DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i3
 +
- @2reg_shl_d      .... ... . . . shift:6      .... .... 1 q:1 . . .... \
++DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-                  &2reg_shift vm=%vm_dp vd=%vd_dp size=3
++DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- @2reg_shl_s      .... ... . . . 1 shift:5    .... .... 0 q:1 . . .... \
++DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
  @2reg_shl_b      .... ... . . . 001 shift:3  .... .... 0 q:1 . . .... \
                   &2reg_shift vm=%vm_dp vd=%vd_dp size=0
 +VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
 +VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
 +VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
 +VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
 +
-+VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
++DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
++DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
++DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
+diff --git a/target/arm/translate.h b/target/arm/translate.h
 +
  VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
  VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
  VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
+--- a/target/arm/translate.h
-+++ b/target/arm/translate-neon.inc.c
++++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
+@@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x)
-     return x + 1;
+     return x * 2 + 1;
  }
 +static inline int rsub_64(DisasContext *s, int x)
 +{
 +    return 64 - x;
 +}
 +
 +static inline int rsub_32(DisasContext *s, int x)
 +{
 +    return 32 - x;
 +}
++
 +static inline int rsub_16(DisasContext *s, int x)
 +{
 +    return 16 - x;
 +}
++
 +static inline int rsub_8(DisasContext *s, int x)
 +{
 +    return 8 - x;
 +}
 +
- /* Include the generated Neon decoder */
+ static inline int arm_dc_feature(DisasContext *dc, int feature)
- #include "decode-neon-dp.inc.c"
+ {
- #include "decode-neon-ls.inc.c"
+     return (dc->features & (1ULL << feature)) != 0;
-@@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
+diff --git a/target/arm/mve.decode b/target/arm/mve.decode
+index XXXXXXX..XXXXXXX 100644
- DO_2SH(VSHL, tcg_gen_gvec_shli)
+--- a/target/arm/mve.decode
- DO_2SH(VSLI, gen_gvec_sli)
++++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
  @2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
  @2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
 +# Right shifts are encoded as N - shift, where N is the element size in bits.
 +%rshift_i5  16:5 !function=rsub_32
 +%rshift_i4  16:4 !function=rsub_16
 +%rshift_i3  16:3 !function=rsub_8
 +
-+static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a)
++@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \
-+{
++         size=0 shift=%rshift_i3
-+    /* Signed shift out of range results in all-sign-bits */
++@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \
-+    a->shift = MIN(a->shift, (8 << a->size) - 1);
++         size=1 shift=%rshift_i4
-+    return do_vector_2sh(s, a, tcg_gen_gvec_sari);
++@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
-+}
++         size=2 shift=%rshift_i5
 +
-+static void gen_zero_rd_2sh(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
+ # Vector loads and stores
-+                            int64_t shift, uint32_t oprsz, uint32_t maxsz)
-+{
+ # Widening loads and narrowing stores:
-+    tcg_gen_gvec_dup_imm(vece, rd_ofs, oprsz, maxsz, 0);
+@@ -XXX,XX +XXX,XX @@ VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
-+}
+ VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
  VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
  VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
 +
-+static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a)
++VSHRI_S           111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
-+{
++VSHRI_S           111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
-+    /* Shift out of range is architecturally valid and results in zero. */
++VSHRI_S           111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
-+    if (a->shift >= (8 << a->size)) {
++
-+        return do_vector_2sh(s, a, gen_zero_rd_2sh);
++VSHRI_U           111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
-+    } else {
++VSHRI_U           111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
-+        return do_vector_2sh(s, a, tcg_gen_gvec_shri);
++VSHRI_U           111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
-+    }
++
-+}
++VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
-diff --git a/target/arm/translate.c b/target/arm/translate.c
++VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
 +VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 +
 +VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
 +VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
 +VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/target/arm/mve_helper.c
-+++ b/target/arm/translate.c
++++ b/target/arm/mve_helper.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
-             op = (insn >> 8) & 0xf;
+     DO_2SHIFT(OP##b, 1, uint8_t, FN)            \
+     DO_2SHIFT(OP##h, 2, uint16_t, FN)           \
-             switch (op) {
+     DO_2SHIFT(OP##w, 4, uint32_t, FN)
-+            case 0: /* VSHR */
++#define DO_2SHIFT_S(OP, FN)                     \
-             case 5: /* VSHL, VSLI */
++    DO_2SHIFT(OP##b, 1, int8_t, FN)             \
-                 return 1; /* handled by decodetree */
++    DO_2SHIFT(OP##h, 2, int16_t, FN)            \
-             default:
++    DO_2SHIFT(OP##w, 4, int32_t, FN)
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                 }
+ #define DO_2SHIFT_SAT_U(OP, FN)                 \
+     DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN)        \
-                 switch (op) {
+@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
--                case 0:  /* VSHR */
+     DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
--                    /* Right shift comes here negative.  */
--                    shift = -shift;
+ DO_2SHIFT_U(vshli_u, DO_VSHLU)
--                    /* Shifts larger than the element size are architecturally
++DO_2SHIFT_S(vshli_s, DO_VSHLS)
--                     * valid.  Unsigned results in all zeros; signed results
+ DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
--                     * in all sign bits.
+ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
--                     */
+ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
--                    if (!u) {
++DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
--                        tcg_gen_gvec_sari(size, rd_ofs, rm_ofs,
++DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
--                                          MIN(shift, (8 << size) - 1),
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
--                                          vec_size, vec_size);
+index XXXXXXX..XXXXXXX 100644
--                    } else if (shift >= 8 << size) {
+--- a/target/arm/translate-mve.c
--                        tcg_gen_gvec_dup_imm(MO_8, rd_ofs, vec_size,
++++ b/target/arm/translate-mve.c
--                                             vec_size, 0);
+@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false)
--                    } else {
+ DO_2SHIFT(VQSHLI_S, vqshli_s, false)
--                        tcg_gen_gvec_shri(size, rd_ofs, rm_ofs, shift,
+ DO_2SHIFT(VQSHLI_U, vqshli_u, false)
--                                          vec_size, vec_size);
+ DO_2SHIFT(VQSHLUI, vqshlui_s, false)
--                    }
++/* These right shifts use a left-shift helper with negated shift count */
--                    return 0;
++DO_2SHIFT(VSHRI_S, vshli_s, true)
 +DO_2SHIFT(VSHRI_U, vshli_u, true)
 +DO_2SHIFT(VRSHRI_S, vrshli_s, true)
 +DO_2SHIFT(VRSHRI_U, vrshli_u, true)
 diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.c
 +++ b/target/arm/translate-neon.c
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
      return x + 1;
  }
 -static inline int rsub_64(DisasContext *s, int x)
 -{
 -    return 64 - x;
 -}
 -
-                 case 1:  /* VSRA */
+-static inline int rsub_32(DisasContext *s, int x)
-                     /* Right shift comes here negative.  */
+-{
-                     shift = -shift;
+-    return 32 - x;
 -}
 -static inline int rsub_16(DisasContext *s, int x)
 -{
 -    return 16 - x;
 -}
 -static inline int rsub_8(DisasContext *s, int x)
 -{
 -    return 8 - x;
 -}
 -
  static inline int neon_3same_fp_size(DisasContext *s, int x)
  {
      /* Convert 0==fp32, 1==fp16 into a MO_* value */
 --
 .20.1

-[PULL 17/29] dwc-hsotg (dwc2) USB host controller emulation
+[PULL 15/24] target/arm: Implement MVE VSHLL
-From: Paul Zimmerman <pauldzim@gmail.com>
+Implement the MVE VHLL (vector shift left long) insn.  This has two
 encodings: the T1 encoding is the usual shift-by-immediate format,
 and the T2 encoding is a special case where the shift count is always
 equal to the element size.
-Add the dwc-hsotg (dwc2) USB host controller emulation code.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
 ---
  target/arm/helper-mve.h    |  9 +++++++
  target/arm/mve.decode      | 53 +++++++++++++++++++++++++++++++++++---
  target/arm/mve_helper.c    | 32 +++++++++++++++++++++++
  target/arm/translate-mve.c | 15 +++++++++++
 files changed, 105 insertions(+), 4 deletions(-)
-Note that to use this with the dwc-otg driver in the Raspbian
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
-kernel, you must pass the option "dwc_otg.fiq_fsm_enable=0" on
+index XXXXXXX..XXXXXXX 100644
-the kernel command line.
+--- a/target/arm/helper-mve.h
++++ b/target/arm/helper-mve.h
-Emulation of slave mode and of descriptor-DMA mode has not been
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-implemented yet. These modes are seldom used.
+ DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-I have used some on-line sources of information while developing
+ DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-this emulation, including:
++
++DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-http://www.capital-micro.com/PDF/CME-M7_Family_User_Guide_EN.pdf
++DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-which has a pretty complete description of the controller starting
++DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-on page 370.
++DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-https://sourceforge.net/p/wive-ng/wive-ng-mt/ci/master/tree/docs/DataSheets/RT3050_5x_V2.0_081408_0902.pdf
++DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-which has a description of the controller registers starting on
++DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-page 130.
++DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+diff --git a/target/arm/mve.decode b/target/arm/mve.decode
-Thanks to Felippe Mathieu-Daude for providing a cleaner method
+index XXXXXXX..XXXXXXX 100644
-of implementing the memory regions for the controller registers.
+--- a/target/arm/mve.decode
++++ b/target/arm/mve.decode
 Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
 Message-id: 20200520235349.21215-5-pauldzim@gmail.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  hw/usb/hcd-dwc2.c    | 1417 ++++++++++++++++++++++++++++++++++++++++++
  hw/usb/Kconfig       |    5 +
  hw/usb/Makefile.objs |    1 +
  hw/usb/trace-events  |   50 ++
 files changed, 1473 insertions(+)
  create mode 100644 hw/usb/hcd-dwc2.c
 diff --git a/hw/usb/hcd-dwc2.c b/hw/usb/hcd-dwc2.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/usb/hcd-dwc2.c
 @@ -XXX,XX +XXX,XX @@
-+/*
+ @2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
-+ * dwc-hsotg (dwc2) USB host controller emulation
+ @2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
-+ *
-+ * Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c
++@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
-+ *
++@2_shll_h .... .... ... 1  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
-+ * Note that to use this emulation with the dwc-otg driver in the
++# VSHLL encoding T2 where shift == esize
-+ * Raspbian kernel, you must pass the option "dwc_otg.fiq_fsm_enable=0"
++@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
-+ * on the kernel command line.
++                qd=%qd qm=%qm size=0 shift=8
-+ *
++@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
-+ * Some useful documentation used to develop this emulation can be
++                qd=%qd qm=%qm size=1 shift=16
 + * found online (as of April 2020) at:
 + *
 + * http://www.capital-micro.com/PDF/CME-M7_Family_User_Guide_EN.pdf
 + * which has a pretty complete description of the controller starting
 + * on page 370.
 + *
 + * https://sourceforge.net/p/wive-ng/wive-ng-mt/ci/master/tree/docs/DataSheets/RT3050_5x_V2.0_081408_0902.pdf
 + * which has a description of the controller registers starting on
 + * page 130.
 + *
 + * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
 + *
 + * This program is free software; you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License as published by
 + * the Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 + * GNU General Public License for more details.
 + */
 +
-+#include "qemu/osdep.h"
+ # Right shifts are encoded as N - shift, where N is the element size in bits.
-+#include "qemu/units.h"
+ %rshift_i5  16:5 !function=rsub_32
-+#include "qapi/error.h"
+ %rshift_i4  16:4 !function=rsub_16
-+#include "hw/usb/dwc2-regs.h"
+@@ -XXX,XX +XXX,XX @@ VADD             1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
-+#include "hw/usb/hcd-dwc2.h"
+ VSUB             1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
-+#include "migration/vmstate.h"
+ VMUL             1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
-+#include "trace.h"
-+#include "qemu/log.h"
+-VMULH_S          111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
-+#include "qemu/error-report.h"
+-VMULH_U          111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
-+#include "qemu/main-loop.h"
++# The VSHLL T2 encoding is not a @2op pattern, but is here because it
-+#include "hw/qdev-properties.h"
++# overlaps what would be size=0b11 VMULH/VRMULH
 +
 +#define USB_HZ_FS       12000000
 +#define USB_HZ_HS       96000000
 +#define USB_FRMINTVL    12000
 +
 +/* nifty macros from Arnon's EHCI version  */
 +#define get_field(data, field) \
 +    (((data) & field##_MASK) >> field##_SHIFT)
 +
 +#define set_field(data, newval, field) do { \
 +    uint32_t val = *(data); \
 +    val &= ~field##_MASK; \
 +    val |= ((newval) << field##_SHIFT) & field##_MASK; \
 +    *(data) = val; \
 +} while (0)
 +
 +#define get_bit(data, bitmask) \
 +    (!!((data) & (bitmask)))
 +
 +/* update irq line */
 +static inline void dwc2_update_irq(DWC2State *s)
 +{
-+    static int oldlevel;
++  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
-+    int level = 0;
++  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
-+
-+    if ((s->gintsts & s->gintmsk) && (s->gahbcfg & GAHBCFG_GLBL_INTR_EN)) {
+-VRMULH_S         111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
-+        level = 1;
+-VRMULH_U         111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
-+    }
++  VMULH_S        111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
 +    if (level != oldlevel) {
 +        oldlevel = level;
 +        trace_usb_dwc2_update_irq(level);
 +        qemu_set_irq(s->irq, level);
 +    }
 +}
 +
-+/* flag interrupt condition */
-+static inline void dwc2_raise_global_irq(DWC2State *s, uint32_t intr)
 +{
-+    if (!(s->gintsts & intr)) {
++  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
-+        s->gintsts |= intr;
++  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
-+        trace_usb_dwc2_raise_global_irq(intr);
++
-+        dwc2_update_irq(s);
++  VMULH_U        111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
 +    }
 +}
 +
-+static inline void dwc2_lower_global_irq(DWC2State *s, uint32_t intr)
 +{
-+    if (s->gintsts & intr) {
++  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
-+        s->gintsts &= ~intr;
++  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
-+        trace_usb_dwc2_lower_global_irq(intr);
++
-+        dwc2_update_irq(s);
++  VRMULH_S       111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
 +    }
 +}
 +
-+static inline void dwc2_raise_host_irq(DWC2State *s, uint32_t host_intr)
 +{
-+    if (!(s->haint & host_intr)) {
++  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
-+        s->haint |= host_intr;
++  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
-+        s->haint &= 0xffff;
++
-+        trace_usb_dwc2_raise_host_irq(host_intr);
++  VRMULH_U       111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
 +        if (s->haint & s->haintmsk) {
 +            dwc2_raise_global_irq(s, GINTSTS_HCHINT);
 +        }
 +    }
 +}
+ VMAX_S           111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
+ VMAX_U           111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
+@@ -XXX,XX +XXX,XX @@ VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
+ VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
+ VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
+ VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 +
-+static inline void dwc2_lower_host_irq(DWC2State *s, uint32_t host_intr)
++# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
-+{
++VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
-+    if (s->haint & host_intr) {
++VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
 +        s->haint &= ~host_intr;
 +        trace_usb_dwc2_lower_host_irq(host_intr);
 +        if (!(s->haint & s->haintmsk)) {
 +            dwc2_lower_global_irq(s, GINTSTS_HCHINT);
 +        }
 +    }
 +}
 +
-+static inline void dwc2_update_hc_irq(DWC2State *s, int index)
++VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
-+{
++VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
 +    uint32_t host_intr = 1 << (index >> 3);
 +
-+    if (s->hreg1[index + 2] & s->hreg1[index + 3]) {
++VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
-+        dwc2_raise_host_irq(s, host_intr);
++VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
 +    } else {
 +        dwc2_lower_host_irq(s, host_intr);
 +    }
 +}
 +
-+/* set a timer for EOF */
++VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
-+static void dwc2_eof_timer(DWC2State *s)
++VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
-+{
+diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-+    timer_mod(s->eof_timer, s->sof_time + s->usb_frame_time);
+index XXXXXXX..XXXXXXX 100644
-+}
+--- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
  DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
  DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
  DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
 +
-+/* Set a timer for EOF and generate SOF event */
++/*
-+static void dwc2_sof(DWC2State *s)
++ * Long shifts taking half-sized inputs from top or bottom of the input
-+{
++ * vector and producing a double-width result. ESIZE, TYPE are for
-+    s->sof_time += s->usb_frame_time;
++ * the input, and LESIZE, LTYPE for the output.
-+    trace_usb_dwc2_sof(s->sof_time);
++ * Unlike the normal shift helpers, we do not handle negative shift counts,
-+    dwc2_eof_timer(s);
++ * because the long shift is strictly left-only.
-+    dwc2_raise_global_irq(s, GINTSTS_SOF);
++ */
-+}
++#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE)                   \
-+
++    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,             \
-+/* Do frame processing on frame boundary */
++                                void *vm, uint32_t shift)               \
-+static void dwc2_frame_boundary(void *opaque)
++    {                                                                   \
-+{
++        LTYPE *d = vd;                                                  \
-+    DWC2State *s = opaque;
++        TYPE *m = vm;                                                   \
-+    int64_t now;
++        uint16_t mask = mve_element_mask(env);                          \
-+    uint16_t frcnt;
++        unsigned le;                                                    \
-+
++        assert(shift <= 16);                                            \
-+    now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
++        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) {         \
-+
++            LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift;        \
-+    /* Frame boundary, so do EOF stuff here */
++            mergemask(&d[H##LESIZE(le)], r, mask);                      \
-+
++        }                                                               \
-+    /* Increment frame number */
++        mve_advance_vpt(env);                                           \
 +    frcnt = (uint16_t)((now - s->sof_time) / s->fi);
 +    s->frame_number = (s->frame_number + frcnt) & 0xffff;
 +    s->hfnum = s->frame_number & HFNUM_MAX_FRNUM;
 +
 +    /* Do SOF stuff here */
 +    dwc2_sof(s);
 +}
 +
 +/* Start sending SOF tokens on the USB bus */
 +static void dwc2_bus_start(DWC2State *s)
 +{
 +    trace_usb_dwc2_bus_start();
 +    s->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 +    dwc2_eof_timer(s);
 +}
 +
 +/* Stop sending SOF tokens on the USB bus */
 +static void dwc2_bus_stop(DWC2State *s)
 +{
 +    trace_usb_dwc2_bus_stop();
 +    timer_del(s->eof_timer);
 +}
 +
 +static USBDevice *dwc2_find_device(DWC2State *s, uint8_t addr)
 +{
 +    USBDevice *dev;
 +
 +    trace_usb_dwc2_find_device(addr);
 +
 +    if (!(s->hprt0 & HPRT0_ENA)) {
 +        trace_usb_dwc2_port_disabled(0);
 +    } else {
 +        dev = usb_find_device(&s->uport, addr);
 +        if (dev != NULL) {
 +            trace_usb_dwc2_device_found(0);
 +            return dev;
 +        }
 +    }
 +
-+    trace_usb_dwc2_device_not_found();
++#define DO_VSHLL_ALL(OP, TOP)                                \
-+    return NULL;
++    DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t)             \
-+}
++    DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t)           \
 +    DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t)            \
 +    DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t)          \
 +
-+static const char *pstatus[] = {
++DO_VSHLL_ALL(vshllb, false)
-+    "USB_RET_SUCCESS", "USB_RET_NODEV", "USB_RET_NAK", "USB_RET_STALL",
++DO_VSHLL_ALL(vshllt, true)
-+    "USB_RET_BABBLE", "USB_RET_IOERROR", "USB_RET_ASYNC",
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
-+    "USB_RET_ADD_TO_QUEUE", "USB_RET_REMOVE_FROM_QUEUE"
+index XXXXXXX..XXXXXXX 100644
-+};
+--- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
  DO_2SHIFT(VSHRI_U, vshli_u, true)
  DO_2SHIFT(VRSHRI_S, vrshli_s, true)
  DO_2SHIFT(VRSHRI_U, vrshli_u, true)
 +
-+static uint32_t pintr[] = {
++#define DO_VSHLL(INSN, FN)                                      \
-+    HCINTMSK_XFERCOMPL, HCINTMSK_XACTERR, HCINTMSK_NAK, HCINTMSK_STALL,
++    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
-+    HCINTMSK_BBLERR, HCINTMSK_XACTERR, HCINTMSK_XACTERR, HCINTMSK_XACTERR,
++    {                                                           \
-+    HCINTMSK_XACTERR
++        static MVEGenTwoOpShiftFn * const fns[] = {             \
-+};
++            gen_helper_mve_##FN##b,                             \
-+
++            gen_helper_mve_##FN##h,                             \
-+static const char *types[] = {
++        };                                                      \
-+    "Ctrl", "Isoc", "Bulk", "Intr"
++        return do_2shift(s, a, fns[a->size], false);            \
 +};
 +
 +static const char *dirs[] = {
 +    "Out", "In"
 +};
 +
 +static void dwc2_handle_packet(DWC2State *s, uint32_t devadr, USBDevice *dev,
 +                               USBEndpoint *ep, uint32_t index, bool send)
 +{
 +    DWC2Packet *p;
 +    uint32_t hcchar = s->hreg1[index];
 +    uint32_t hctsiz = s->hreg1[index + 4];
 +    uint32_t hcdma = s->hreg1[index + 5];
 +    uint32_t chan, epnum, epdir, eptype, mps, pid, pcnt, len, tlen, intr = 0;
 +    uint32_t tpcnt, stsidx, actual = 0;
 +    bool do_intr = false, done = false;
 +
 +    epnum = get_field(hcchar, HCCHAR_EPNUM);
 +    epdir = get_bit(hcchar, HCCHAR_EPDIR);
 +    eptype = get_field(hcchar, HCCHAR_EPTYPE);
 +    mps = get_field(hcchar, HCCHAR_MPS);
 +    pid = get_field(hctsiz, TSIZ_SC_MC_PID);
 +    pcnt = get_field(hctsiz, TSIZ_PKTCNT);
 +    len = get_field(hctsiz, TSIZ_XFERSIZE);
 +    assert(len <= DWC2_MAX_XFER_SIZE);
 +    chan = index >> 3;
 +    p = &s->packet[chan];
 +
 +    trace_usb_dwc2_handle_packet(chan, dev, &p->packet, epnum, types[eptype],
 +                                 dirs[epdir], mps, len, pcnt);
 +
 +    if (eptype == USB_ENDPOINT_XFER_CONTROL && pid == TSIZ_SC_MC_PID_SETUP) {
 +        pid = USB_TOKEN_SETUP;
 +    } else {
 +        pid = epdir ? USB_TOKEN_IN : USB_TOKEN_OUT;
 +    }
 +
-+    if (send) {
++DO_VSHLL(VSHLL_BS, vshllbs)
-+        tlen = len;
++DO_VSHLL(VSHLL_BU, vshllbu)
-+        if (p->small) {
++DO_VSHLL(VSHLL_TS, vshllts)
-+            if (tlen > mps) {
++DO_VSHLL(VSHLL_TU, vshlltu)
 +                tlen = mps;
 +            }
 +        }
 +
 +        if (pid != USB_TOKEN_IN) {
 +            trace_usb_dwc2_memory_read(hcdma, tlen);
 +            if (dma_memory_read(&s->dma_as, hcdma,
 +                                s->usb_buf[chan], tlen) != MEMTX_OK) {
 +                qemu_log_mask(LOG_GUEST_ERROR, "%s: dma_memory_read failed\n",
 +                              __func__);
 +            }
 +        }
 +
 +        usb_packet_init(&p->packet);
 +        usb_packet_setup(&p->packet, pid, ep, 0, hcdma,
 +                         pid != USB_TOKEN_IN, true);
 +        usb_packet_addbuf(&p->packet, s->usb_buf[chan], tlen);
 +        p->async = DWC2_ASYNC_NONE;
 +        usb_handle_packet(dev, &p->packet);
 +    } else {
 +        tlen = p->len;
 +    }
 +
 +    stsidx = -p->packet.status;
 +    assert(stsidx < sizeof(pstatus) / sizeof(*pstatus));
 +    actual = p->packet.actual_length;
 +    trace_usb_dwc2_packet_status(pstatus[stsidx], actual);
 +
 +babble:
 +    if (p->packet.status != USB_RET_SUCCESS &&
 +            p->packet.status != USB_RET_NAK &&
 +            p->packet.status != USB_RET_STALL &&
 +            p->packet.status != USB_RET_ASYNC) {
 +        trace_usb_dwc2_packet_error(pstatus[stsidx]);
 +    }
 +
 +    if (p->packet.status == USB_RET_ASYNC) {
 +        trace_usb_dwc2_async_packet(&p->packet, chan, dev, epnum,
 +                                    dirs[epdir], tlen);
 +        usb_device_flush_ep_queue(dev, ep);
 +        assert(p->async != DWC2_ASYNC_INFLIGHT);
 +        p->devadr = devadr;
 +        p->epnum = epnum;
 +        p->epdir = epdir;
 +        p->mps = mps;
 +        p->pid = pid;
 +        p->index = index;
 +        p->pcnt = pcnt;
 +        p->len = tlen;
 +        p->async = DWC2_ASYNC_INFLIGHT;
 +        p->needs_service = false;
 +        return;
 +    }
 +
 +    if (p->packet.status == USB_RET_SUCCESS) {
 +        if (actual > tlen) {
 +            p->packet.status = USB_RET_BABBLE;
 +            goto babble;
 +        }
 +
 +        if (pid == USB_TOKEN_IN) {
 +            trace_usb_dwc2_memory_write(hcdma, actual);
 +            if (dma_memory_write(&s->dma_as, hcdma, s->usb_buf[chan],
 +                                 actual) != MEMTX_OK) {
 +                qemu_log_mask(LOG_GUEST_ERROR, "%s: dma_memory_write failed\n",
 +                              __func__);
 +            }
 +        }
 +
 +        tpcnt = actual / mps;
 +        if (actual % mps) {
 +            tpcnt++;
 +            if (pid == USB_TOKEN_IN) {
 +                done = true;
 +            }
 +        }
 +
 +        pcnt -= tpcnt < pcnt ? tpcnt : pcnt;
 +        set_field(&hctsiz, pcnt, TSIZ_PKTCNT);
 +        len -= actual < len ? actual : len;
 +        set_field(&hctsiz, len, TSIZ_XFERSIZE);
 +        s->hreg1[index + 4] = hctsiz;
 +        hcdma += actual;
 +        s->hreg1[index + 5] = hcdma;
 +
 +        if (!pcnt || len == 0 || actual == 0) {
 +            done = true;
 +        }
 +    } else {
 +        intr |= pintr[stsidx];
 +        if (p->packet.status == USB_RET_NAK &&
 +            (eptype == USB_ENDPOINT_XFER_CONTROL ||
 +             eptype == USB_ENDPOINT_XFER_BULK)) {
 +            /*
 +             * for ctrl/bulk, automatically retry on NAK,
 +             * but send the interrupt anyway
 +             */
 +            intr &= ~HCINTMSK_RESERVED14_31;
 +            s->hreg1[index + 2] |= intr;
 +            do_intr = true;
 +        } else {
 +            intr |= HCINTMSK_CHHLTD;
 +            done = true;
 +        }
 +    }
 +
 +    usb_packet_cleanup(&p->packet);
 +
 +    if (done) {
 +        hcchar &= ~HCCHAR_CHENA;
 +        s->hreg1[index] = hcchar;
 +        if (!(intr & HCINTMSK_CHHLTD)) {
 +            intr |= HCINTMSK_CHHLTD | HCINTMSK_XFERCOMPL;
 +        }
 +        intr &= ~HCINTMSK_RESERVED14_31;
 +        s->hreg1[index + 2] |= intr;
 +        p->needs_service = false;
 +        trace_usb_dwc2_packet_done(pstatus[stsidx], actual, len, pcnt);
 +        dwc2_update_hc_irq(s, index);
 +        return;
 +    }
 +
 +    p->devadr = devadr;
 +    p->epnum = epnum;
 +    p->epdir = epdir;
 +    p->mps = mps;
 +    p->pid = pid;
 +    p->index = index;
 +    p->pcnt = pcnt;
 +    p->len = len;
 +    p->needs_service = true;
 +    trace_usb_dwc2_packet_next(pstatus[stsidx], len, pcnt);
 +    if (do_intr) {
 +        dwc2_update_hc_irq(s, index);
 +    }
 +}
 +
 +/* Attach or detach a device on root hub */
 +
 +static const char *speeds[] = {
 +    "low", "full", "high"
 +};
 +
 +static void dwc2_attach(USBPort *port)
 +{
 +    DWC2State *s = port->opaque;
 +    int hispd = 0;
 +
 +    trace_usb_dwc2_attach(port);
 +    assert(port->index == 0);
 +
 +    if (!port->dev || !port->dev->attached) {
 +        return;
 +    }
 +
 +    assert(port->dev->speed <= USB_SPEED_HIGH);
 +    trace_usb_dwc2_attach_speed(speeds[port->dev->speed]);
 +    s->hprt0 &= ~HPRT0_SPD_MASK;
 +
 +    switch (port->dev->speed) {
 +    case USB_SPEED_LOW:
 +        s->hprt0 |= HPRT0_SPD_LOW_SPEED << HPRT0_SPD_SHIFT;
 +        break;
 +    case USB_SPEED_FULL:
 +        s->hprt0 |= HPRT0_SPD_FULL_SPEED << HPRT0_SPD_SHIFT;
 +        break;
 +    case USB_SPEED_HIGH:
 +        s->hprt0 |= HPRT0_SPD_HIGH_SPEED << HPRT0_SPD_SHIFT;
 +        hispd = 1;
 +        break;
 +    }
 +
 +    if (hispd) {
 +        s->usb_frame_time = NANOSECONDS_PER_SECOND / 8000;        /* 125000 */
 +        if (NANOSECONDS_PER_SECOND >= USB_HZ_HS) {
 +            s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_HS; /* 10.4 */
 +        } else {
 +            s->usb_bit_time = 1;
 +        }
 +    } else {
 +        s->usb_frame_time = NANOSECONDS_PER_SECOND / 1000;        /* 1000000 */
 +        if (NANOSECONDS_PER_SECOND >= USB_HZ_FS) {
 +            s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_FS; /* 83.3 */
 +        } else {
 +            s->usb_bit_time = 1;
 +        }
 +    }
 +
 +    s->fi = USB_FRMINTVL - 1;
 +    s->hprt0 |= HPRT0_CONNDET | HPRT0_CONNSTS;
 +
 +    dwc2_bus_start(s);
 +    dwc2_raise_global_irq(s, GINTSTS_PRTINT);
 +}
 +
 +static void dwc2_detach(USBPort *port)
 +{
 +    DWC2State *s = port->opaque;
 +
 +    trace_usb_dwc2_detach(port);
 +    assert(port->index == 0);
 +
 +    dwc2_bus_stop(s);
 +
 +    s->hprt0 &= ~(HPRT0_SPD_MASK | HPRT0_SUSP | HPRT0_ENA | HPRT0_CONNSTS);
 +    s->hprt0 |= HPRT0_CONNDET | HPRT0_ENACHG;
 +
 +    dwc2_raise_global_irq(s, GINTSTS_PRTINT);
 +}
 +
 +static void dwc2_child_detach(USBPort *port, USBDevice *child)
 +{
 +    trace_usb_dwc2_child_detach(port, child);
 +    assert(port->index == 0);
 +}
 +
 +static void dwc2_wakeup(USBPort *port)
 +{
 +    DWC2State *s = port->opaque;
 +
 +    trace_usb_dwc2_wakeup(port);
 +    assert(port->index == 0);
 +
 +    if (s->hprt0 & HPRT0_SUSP) {
 +        s->hprt0 |= HPRT0_RES;
 +        dwc2_raise_global_irq(s, GINTSTS_PRTINT);
 +    }
 +
 +    qemu_bh_schedule(s->async_bh);
 +}
 +
 +static void dwc2_async_packet_complete(USBPort *port, USBPacket *packet)
 +{
 +    DWC2State *s = port->opaque;
 +    DWC2Packet *p;
 +    USBDevice *dev;
 +    USBEndpoint *ep;
 +
 +    assert(port->index == 0);
 +    p = container_of(packet, DWC2Packet, packet);
 +    dev = dwc2_find_device(s, p->devadr);
 +    ep = usb_ep_get(dev, p->pid, p->epnum);
 +    trace_usb_dwc2_async_packet_complete(port, packet, p->index >> 3, dev,
 +                                         p->epnum, dirs[p->epdir], p->len);
 +    assert(p->async == DWC2_ASYNC_INFLIGHT);
 +
 +    if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
 +        usb_cancel_packet(packet);
 +        usb_packet_cleanup(packet);
 +        return;
 +    }
 +
 +    dwc2_handle_packet(s, p->devadr, dev, ep, p->index, false);
 +
 +    p->async = DWC2_ASYNC_FINISHED;
 +    qemu_bh_schedule(s->async_bh);
 +}
 +
 +static USBPortOps dwc2_port_ops = {
 +    .attach = dwc2_attach,
 +    .detach = dwc2_detach,
 +    .child_detach = dwc2_child_detach,
 +    .wakeup = dwc2_wakeup,
 +    .complete = dwc2_async_packet_complete,
 +};
 +
 +static uint32_t dwc2_get_frame_remaining(DWC2State *s)
 +{
 +    uint32_t fr = 0;
 +    int64_t tks;
 +
 +    tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->sof_time;
 +    if (tks < 0) {
 +        tks = 0;
 +    }
 +
 +    /* avoid muldiv if possible */
 +    if (tks >= s->usb_frame_time) {
 +        goto out;
 +    }
 +    if (tks < s->usb_bit_time) {
 +        fr = s->fi;
 +        goto out;
 +    }
 +
 +    /* tks = number of ns since SOF, divided by 83 (fs) or 10 (hs) */
 +    tks = tks / s->usb_bit_time;
 +    if (tks >= (int64_t)s->fi) {
 +        goto out;
 +    }
 +
 +    /* remaining = frame interval minus tks */
 +    fr = (uint32_t)((int64_t)s->fi - tks);
 +
 +out:
 +    return fr;
 +}
 +
 +static void dwc2_work_bh(void *opaque)
 +{
 +    DWC2State *s = opaque;
 +    DWC2Packet *p;
 +    USBDevice *dev;
 +    USBEndpoint *ep;
 +    int64_t t_now, expire_time;
 +    int chan;
 +    bool found = false;
 +
 +    trace_usb_dwc2_work_bh();
 +    if (s->working) {
 +        return;
 +    }
 +    s->working = true;
 +
 +    t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 +    chan = s->next_chan;
 +
 +    do {
 +        p = &s->packet[chan];
 +        if (p->needs_service) {
 +            dev = dwc2_find_device(s, p->devadr);
 +            ep = usb_ep_get(dev, p->pid, p->epnum);
 +            trace_usb_dwc2_work_bh_service(s->next_chan, chan, dev, p->epnum);
 +            dwc2_handle_packet(s, p->devadr, dev, ep, p->index, true);
 +            found = true;
 +        }
 +        if (++chan == DWC2_NB_CHAN) {
 +            chan = 0;
 +        }
 +        if (found) {
 +            s->next_chan = chan;
 +            trace_usb_dwc2_work_bh_next(chan);
 +        }
 +    } while (chan != s->next_chan);
 +
 +    if (found) {
 +        expire_time = t_now + NANOSECONDS_PER_SECOND / 4000;
 +        timer_mod(s->frame_timer, expire_time);
 +    }
 +    s->working = false;
 +}
 +
 +static void dwc2_enable_chan(DWC2State *s,  uint32_t index)
 +{
 +    USBDevice *dev;
 +    USBEndpoint *ep;
 +    uint32_t hcchar;
 +    uint32_t hctsiz;
 +    uint32_t devadr, epnum, epdir, eptype, pid, len;
 +    DWC2Packet *p;
 +
 +    assert((index >> 3) < DWC2_NB_CHAN);
 +    p = &s->packet[index >> 3];
 +    hcchar = s->hreg1[index];
 +    hctsiz = s->hreg1[index + 4];
 +    devadr = get_field(hcchar, HCCHAR_DEVADDR);
 +    epnum = get_field(hcchar, HCCHAR_EPNUM);
 +    epdir = get_bit(hcchar, HCCHAR_EPDIR);
 +    eptype = get_field(hcchar, HCCHAR_EPTYPE);
 +    pid = get_field(hctsiz, TSIZ_SC_MC_PID);
 +    len = get_field(hctsiz, TSIZ_XFERSIZE);
 +
 +    dev = dwc2_find_device(s, devadr);
 +
 +    trace_usb_dwc2_enable_chan(index >> 3, dev, &p->packet, epnum);
 +    if (dev == NULL) {
 +        return;
 +    }
 +
 +    if (eptype == USB_ENDPOINT_XFER_CONTROL && pid == TSIZ_SC_MC_PID_SETUP) {
 +        pid = USB_TOKEN_SETUP;
 +    } else {
 +        pid = epdir ? USB_TOKEN_IN : USB_TOKEN_OUT;
 +    }
 +
 +    ep = usb_ep_get(dev, pid, epnum);
 +
 +    /*
 +     * Hack: Networking doesn't like us delivering large transfers, it kind
 +     * of works but the latency is horrible. So if the transfer is <= the mtu
 +     * size, we take that as a hint that this might be a network transfer,
 +     * and do the transfer packet-by-packet.
 +     */
 +    if (len > 1536) {
 +        p->small = false;
 +    } else {
 +        p->small = true;
 +    }
 +
 +    dwc2_handle_packet(s, devadr, dev, ep, index, true);
 +    qemu_bh_schedule(s->async_bh);
 +}
 +
 +static const char *glbregnm[] = {
 +    "GOTGCTL  ", "GOTGINT  ", "GAHBCFG  ", "GUSBCFG  ", "GRSTCTL  ",
 +    "GINTSTS  ", "GINTMSK  ", "GRXSTSR  ", "GRXSTSP  ", "GRXFSIZ  ",
 +    "GNPTXFSIZ", "GNPTXSTS ", "GI2CCTL  ", "GPVNDCTL ", "GGPIO    ",
 +    "GUID     ", "GSNPSID  ", "GHWCFG1  ", "GHWCFG2  ", "GHWCFG3  ",
 +    "GHWCFG4  ", "GLPMCFG  ", "GPWRDN   ", "GDFIFOCFG", "GADPCTL  ",
 +    "GREFCLK  ", "GINTMSK2 ", "GINTSTS2 "
 +};
 +
 +static uint64_t dwc2_glbreg_read(void *ptr, hwaddr addr, int index,
 +                                 unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    uint32_t val;
 +
 +    assert(addr <= GINTSTS2);
 +    val = s->glbreg[index];
 +
 +    switch (addr) {
 +    case GRSTCTL:
 +        /* clear any self-clearing bits that were set */
 +        val &= ~(GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH | GRSTCTL_IN_TKNQ_FLSH |
 +                 GRSTCTL_FRMCNTRRST | GRSTCTL_HSFTRST | GRSTCTL_CSFTRST);
 +        s->glbreg[index] = val;
 +        break;
 +    default:
 +        break;
 +    }
 +
 +    trace_usb_dwc2_glbreg_read(addr, glbregnm[index], val);
 +    return val;
 +}
 +
 +static void dwc2_glbreg_write(void *ptr, hwaddr addr, int index, uint64_t val,
 +                              unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    uint64_t orig = val;
 +    uint32_t *mmio;
 +    uint32_t old;
 +    int iflg = 0;
 +
 +    assert(addr <= GINTSTS2);
 +    mmio = &s->glbreg[index];
 +    old = *mmio;
 +
 +    switch (addr) {
 +    case GOTGCTL:
 +        /* don't allow setting of read-only bits */
 +        val &= ~(GOTGCTL_MULT_VALID_BC_MASK | GOTGCTL_BSESVLD |
 +                 GOTGCTL_ASESVLD | GOTGCTL_DBNC_SHORT | GOTGCTL_CONID_B |
 +                 GOTGCTL_HSTNEGSCS | GOTGCTL_SESREQSCS);
 +        /* don't allow clearing of read-only bits */
 +        val |= old & (GOTGCTL_MULT_VALID_BC_MASK | GOTGCTL_BSESVLD |
 +                      GOTGCTL_ASESVLD | GOTGCTL_DBNC_SHORT | GOTGCTL_CONID_B |
 +                      GOTGCTL_HSTNEGSCS | GOTGCTL_SESREQSCS);
 +        break;
 +    case GAHBCFG:
 +        if ((val & GAHBCFG_GLBL_INTR_EN) && !(old & GAHBCFG_GLBL_INTR_EN)) {
 +            iflg = 1;
 +        }
 +        break;
 +    case GRSTCTL:
 +        val |= GRSTCTL_AHBIDLE;
 +        val &= ~GRSTCTL_DMAREQ;
 +        if (!(old & GRSTCTL_TXFFLSH) && (val & GRSTCTL_TXFFLSH)) {
 +                /* TODO - TX fifo flush */
 +            qemu_log_mask(LOG_UNIMP, "Tx FIFO flush not implemented\n");
 +        }
 +        if (!(old & GRSTCTL_RXFFLSH) && (val & GRSTCTL_RXFFLSH)) {
 +                /* TODO - RX fifo flush */
 +            qemu_log_mask(LOG_UNIMP, "Rx FIFO flush not implemented\n");
 +        }
 +        if (!(old & GRSTCTL_IN_TKNQ_FLSH) && (val & GRSTCTL_IN_TKNQ_FLSH)) {
 +                /* TODO - device IN token queue flush */
 +            qemu_log_mask(LOG_UNIMP, "Token queue flush not implemented\n");
 +        }
 +        if (!(old & GRSTCTL_FRMCNTRRST) && (val & GRSTCTL_FRMCNTRRST)) {
 +                /* TODO - host frame counter reset */
 +            qemu_log_mask(LOG_UNIMP, "Frame counter reset not implemented\n");
 +        }
 +        if (!(old & GRSTCTL_HSFTRST) && (val & GRSTCTL_HSFTRST)) {
 +                /* TODO - host soft reset */
 +            qemu_log_mask(LOG_UNIMP, "Host soft reset not implemented\n");
 +        }
 +        if (!(old & GRSTCTL_CSFTRST) && (val & GRSTCTL_CSFTRST)) {
 +                /* TODO - core soft reset */
 +            qemu_log_mask(LOG_UNIMP, "Core soft reset not implemented\n");
 +        }
 +        /* don't allow clearing of self-clearing bits */
 +        val |= old & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH |
 +                      GRSTCTL_IN_TKNQ_FLSH | GRSTCTL_FRMCNTRRST |
 +                      GRSTCTL_HSFTRST | GRSTCTL_CSFTRST);
 +        break;
 +    case GINTSTS:
 +        /* clear the write-1-to-clear bits */
 +        val |= ~old;
 +        val = ~val;
 +        /* don't allow clearing of read-only bits */
 +        val |= old & (GINTSTS_PTXFEMP | GINTSTS_HCHINT | GINTSTS_PRTINT |
 +                      GINTSTS_OEPINT | GINTSTS_IEPINT | GINTSTS_GOUTNAKEFF |
 +                      GINTSTS_GINNAKEFF | GINTSTS_NPTXFEMP | GINTSTS_RXFLVL |
 +                      GINTSTS_OTGINT | GINTSTS_CURMODE_HOST);
 +        iflg = 1;
 +        break;
 +    case GINTMSK:
 +        iflg = 1;
 +        break;
 +    default:
 +        break;
 +    }
 +
 +    trace_usb_dwc2_glbreg_write(addr, glbregnm[index], orig, old, val);
 +    *mmio = val;
 +
 +    if (iflg) {
 +        dwc2_update_irq(s);
 +    }
 +}
 +
 +static uint64_t dwc2_fszreg_read(void *ptr, hwaddr addr, int index,
 +                                 unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    uint32_t val;
 +
 +    assert(addr == HPTXFSIZ);
 +    val = s->fszreg[index];
 +
 +    trace_usb_dwc2_fszreg_read(addr, val);
 +    return val;
 +}
 +
 +static void dwc2_fszreg_write(void *ptr, hwaddr addr, int index, uint64_t val,
 +                              unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    uint64_t orig = val;
 +    uint32_t *mmio;
 +    uint32_t old;
 +
 +    assert(addr == HPTXFSIZ);
 +    mmio = &s->fszreg[index];
 +    old = *mmio;
 +
 +    trace_usb_dwc2_fszreg_write(addr, orig, old, val);
 +    *mmio = val;
 +}
 +
 +static const char *hreg0nm[] = {
 +    "HCFG     ", "HFIR     ", "HFNUM    ", "<rsvd>   ", "HPTXSTS  ",
 +    "HAINT    ", "HAINTMSK ", "HFLBADDR ", "<rsvd>   ", "<rsvd>   ",
 +    "<rsvd>   ", "<rsvd>   ", "<rsvd>   ", "<rsvd>   ", "<rsvd>   ",
 +    "<rsvd>   ", "HPRT0    "
 +};
 +
 +static uint64_t dwc2_hreg0_read(void *ptr, hwaddr addr, int index,
 +                                unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    uint32_t val;
 +
 +    assert(addr >= HCFG && addr <= HPRT0);
 +    val = s->hreg0[index];
 +
 +    switch (addr) {
 +    case HFNUM:
 +        val = (dwc2_get_frame_remaining(s) << HFNUM_FRREM_SHIFT) |
 +              (s->hfnum << HFNUM_FRNUM_SHIFT);
 +        break;
 +    default:
 +        break;
 +    }
 +
 +    trace_usb_dwc2_hreg0_read(addr, hreg0nm[index], val);
 +    return val;
 +}
 +
 +static void dwc2_hreg0_write(void *ptr, hwaddr addr, int index, uint64_t val,
 +                             unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    USBDevice *dev = s->uport.dev;
 +    uint64_t orig = val;
 +    uint32_t *mmio;
 +    uint32_t tval, told, old;
 +    int prst = 0;
 +    int iflg = 0;
 +
 +    assert(addr >= HCFG && addr <= HPRT0);
 +    mmio = &s->hreg0[index];
 +    old = *mmio;
 +
 +    switch (addr) {
 +    case HFIR:
 +        break;
 +    case HFNUM:
 +    case HPTXSTS:
 +    case HAINT:
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: write to read-only register\n",
 +                      __func__);
 +        return;
 +    case HAINTMSK:
 +        val &= 0xffff;
 +        break;
 +    case HPRT0:
 +        /* don't allow clearing of read-only bits */
 +        val |= old & (HPRT0_SPD_MASK | HPRT0_LNSTS_MASK | HPRT0_OVRCURRACT |
 +                      HPRT0_CONNSTS);
 +        /* don't allow clearing of self-clearing bits */
 +        val |= old & (HPRT0_SUSP | HPRT0_RES);
 +        /* don't allow setting of self-setting bits */
 +        if (!(old & HPRT0_ENA) && (val & HPRT0_ENA)) {
 +            val &= ~HPRT0_ENA;
 +        }
 +        /* clear the write-1-to-clear bits */
 +        tval = val & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
 +                      HPRT0_CONNDET);
 +        told = old & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
 +                      HPRT0_CONNDET);
 +        tval |= ~told;
 +        tval = ~tval;
 +        tval &= (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
 +                 HPRT0_CONNDET);
 +        val &= ~(HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
 +                 HPRT0_CONNDET);
 +        val |= tval;
 +        if (!(val & HPRT0_RST) && (old & HPRT0_RST)) {
 +            if (dev && dev->attached) {
 +                val |= HPRT0_ENA | HPRT0_ENACHG;
 +                prst = 1;
 +            }
 +        }
 +        if (val & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_CONNDET)) {
 +            iflg = 1;
 +        } else {
 +            iflg = -1;
 +        }
 +        break;
 +    default:
 +        break;
 +    }
 +
 +    if (prst) {
 +        trace_usb_dwc2_hreg0_write(addr, hreg0nm[index], orig, old,
 +                                   val & ~HPRT0_CONNDET);
 +        trace_usb_dwc2_hreg0_action("call usb_port_reset");
 +        usb_port_reset(&s->uport);
 +        val &= ~HPRT0_CONNDET;
 +    } else {
 +        trace_usb_dwc2_hreg0_write(addr, hreg0nm[index], orig, old, val);
 +    }
 +
 +    *mmio = val;
 +
 +    if (iflg > 0) {
 +        trace_usb_dwc2_hreg0_action("enable PRTINT");
 +        dwc2_raise_global_irq(s, GINTSTS_PRTINT);
 +    } else if (iflg < 0) {
 +        trace_usb_dwc2_hreg0_action("disable PRTINT");
 +        dwc2_lower_global_irq(s, GINTSTS_PRTINT);
 +    }
 +}
 +
 +static const char *hreg1nm[] = {
 +    "HCCHAR  ", "HCSPLT  ", "HCINT   ", "HCINTMSK", "HCTSIZ  ", "HCDMA   ",
 +    "<rsvd>  ", "HCDMAB  "
 +};
 +
 +static uint64_t dwc2_hreg1_read(void *ptr, hwaddr addr, int index,
 +                                unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    uint32_t val;
 +
 +    assert(addr >= HCCHAR(0) && addr <= HCDMAB(DWC2_NB_CHAN - 1));
 +    val = s->hreg1[index];
 +
 +    trace_usb_dwc2_hreg1_read(addr, hreg1nm[index & 7], addr >> 5, val);
 +    return val;
 +}
 +
 +static void dwc2_hreg1_write(void *ptr, hwaddr addr, int index, uint64_t val,
 +                             unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    uint64_t orig = val;
 +    uint32_t *mmio;
 +    uint32_t old;
 +    int iflg = 0;
 +    int enflg = 0;
 +    int disflg = 0;
 +
 +    assert(addr >= HCCHAR(0) && addr <= HCDMAB(DWC2_NB_CHAN - 1));
 +    mmio = &s->hreg1[index];
 +    old = *mmio;
 +
 +    switch (HSOTG_REG(0x500) + (addr & 0x1c)) {
 +    case HCCHAR(0):
 +        if ((val & HCCHAR_CHDIS) && !(old & HCCHAR_CHDIS)) {
 +            val &= ~(HCCHAR_CHENA | HCCHAR_CHDIS);
 +            disflg = 1;
 +        } else {
 +            val |= old & HCCHAR_CHDIS;
 +            if ((val & HCCHAR_CHENA) && !(old & HCCHAR_CHENA)) {
 +                val &= ~HCCHAR_CHDIS;
 +                enflg = 1;
 +            } else {
 +                val |= old & HCCHAR_CHENA;
 +            }
 +        }
 +        break;
 +    case HCINT(0):
 +        /* clear the write-1-to-clear bits */
 +        val |= ~old;
 +        val = ~val;
 +        val &= ~HCINTMSK_RESERVED14_31;
 +        iflg = 1;
 +        break;
 +    case HCINTMSK(0):
 +        val &= ~HCINTMSK_RESERVED14_31;
 +        iflg = 1;
 +        break;
 +    case HCDMAB(0):
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: write to read-only register\n",
 +                      __func__);
 +        return;
 +    default:
 +        break;
 +    }
 +
 +    trace_usb_dwc2_hreg1_write(addr, hreg1nm[index & 7], index >> 3, orig,
 +                               old, val);
 +    *mmio = val;
 +
 +    if (disflg) {
 +        /* set ChHltd in HCINT */
 +        s->hreg1[(index & ~7) + 2] |= HCINTMSK_CHHLTD;
 +        iflg = 1;
 +    }
 +
 +    if (enflg) {
 +        dwc2_enable_chan(s, index & ~7);
 +    }
 +
 +    if (iflg) {
 +        dwc2_update_hc_irq(s, index & ~7);
 +    }
 +}
 +
 +static const char *pcgregnm[] = {
 +        "PCGCTL   ", "PCGCCTL1 "
 +};
 +
 +static uint64_t dwc2_pcgreg_read(void *ptr, hwaddr addr, int index,
 +                                 unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    uint32_t val;
 +
 +    assert(addr >= PCGCTL && addr <= PCGCCTL1);
 +    val = s->pcgreg[index];
 +
 +    trace_usb_dwc2_pcgreg_read(addr, pcgregnm[index], val);
 +    return val;
 +}
 +
 +static void dwc2_pcgreg_write(void *ptr, hwaddr addr, int index,
 +                              uint64_t val, unsigned size)
 +{
 +    DWC2State *s = ptr;
 +    uint64_t orig = val;
 +    uint32_t *mmio;
 +    uint32_t old;
 +
 +    assert(addr >= PCGCTL && addr <= PCGCCTL1);
 +    mmio = &s->pcgreg[index];
 +    old = *mmio;
 +
 +    trace_usb_dwc2_pcgreg_write(addr, pcgregnm[index], orig, old, val);
 +    *mmio = val;
 +}
 +
 +static uint64_t dwc2_hsotg_read(void *ptr, hwaddr addr, unsigned size)
 +{
 +    uint64_t val;
 +
 +    switch (addr) {
 +    case HSOTG_REG(0x000) ... HSOTG_REG(0x0fc):
 +        val = dwc2_glbreg_read(ptr, addr, (addr - HSOTG_REG(0x000)) >> 2, size);
 +        break;
 +    case HSOTG_REG(0x100):
 +        val = dwc2_fszreg_read(ptr, addr, (addr - HSOTG_REG(0x100)) >> 2, size);
 +        break;
 +    case HSOTG_REG(0x104) ... HSOTG_REG(0x3fc):
 +        /* Gadget-mode registers, just return 0 for now */
 +        val = 0;
 +        break;
 +    case HSOTG_REG(0x400) ... HSOTG_REG(0x4fc):
 +        val = dwc2_hreg0_read(ptr, addr, (addr - HSOTG_REG(0x400)) >> 2, size);
 +        break;
 +    case HSOTG_REG(0x500) ... HSOTG_REG(0x7fc):
 +        val = dwc2_hreg1_read(ptr, addr, (addr - HSOTG_REG(0x500)) >> 2, size);
 +        break;
 +    case HSOTG_REG(0x800) ... HSOTG_REG(0xdfc):
 +        /* Gadget-mode registers, just return 0 for now */
 +        val = 0;
 +        break;
 +    case HSOTG_REG(0xe00) ... HSOTG_REG(0xffc):
 +        val = dwc2_pcgreg_read(ptr, addr, (addr - HSOTG_REG(0xe00)) >> 2, size);
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +
 +    return val;
 +}
 +
 +static void dwc2_hsotg_write(void *ptr, hwaddr addr, uint64_t val,
 +                             unsigned size)
 +{
 +    switch (addr) {
 +    case HSOTG_REG(0x000) ... HSOTG_REG(0x0fc):
 +        dwc2_glbreg_write(ptr, addr, (addr - HSOTG_REG(0x000)) >> 2, val, size);
 +        break;
 +    case HSOTG_REG(0x100):
 +        dwc2_fszreg_write(ptr, addr, (addr - HSOTG_REG(0x100)) >> 2, val, size);
 +        break;
 +    case HSOTG_REG(0x104) ... HSOTG_REG(0x3fc):
 +        /* Gadget-mode registers, do nothing for now */
 +        break;
 +    case HSOTG_REG(0x400) ... HSOTG_REG(0x4fc):
 +        dwc2_hreg0_write(ptr, addr, (addr - HSOTG_REG(0x400)) >> 2, val, size);
 +        break;
 +    case HSOTG_REG(0x500) ... HSOTG_REG(0x7fc):
 +        dwc2_hreg1_write(ptr, addr, (addr - HSOTG_REG(0x500)) >> 2, val, size);
 +        break;
 +    case HSOTG_REG(0x800) ... HSOTG_REG(0xdfc):
 +        /* Gadget-mode registers, do nothing for now */
 +        break;
 +    case HSOTG_REG(0xe00) ... HSOTG_REG(0xffc):
 +        dwc2_pcgreg_write(ptr, addr, (addr - HSOTG_REG(0xe00)) >> 2, val, size);
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static const MemoryRegionOps dwc2_mmio_hsotg_ops = {
 +    .read = dwc2_hsotg_read,
 +    .write = dwc2_hsotg_write,
 +    .impl.min_access_size = 4,
 +    .impl.max_access_size = 4,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +};
 +
 +static uint64_t dwc2_hreg2_read(void *ptr, hwaddr addr, unsigned size)
 +{
 +    /* TODO - implement FIFOs to support slave mode */
 +    trace_usb_dwc2_hreg2_read(addr, addr >> 12, 0);
 +    qemu_log_mask(LOG_UNIMP, "FIFO read not implemented\n");
 +    return 0;
 +}
 +
 +static void dwc2_hreg2_write(void *ptr, hwaddr addr, uint64_t val,
 +                             unsigned size)
 +{
 +    uint64_t orig = val;
 +
 +    /* TODO - implement FIFOs to support slave mode */
 +    trace_usb_dwc2_hreg2_write(addr, addr >> 12, orig, 0, val);
 +    qemu_log_mask(LOG_UNIMP, "FIFO write not implemented\n");
 +}
 +
 +static const MemoryRegionOps dwc2_mmio_hreg2_ops = {
 +    .read = dwc2_hreg2_read,
 +    .write = dwc2_hreg2_write,
 +    .impl.min_access_size = 4,
 +    .impl.max_access_size = 4,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +};
 +
 +static void dwc2_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
 +                                 unsigned int stream)
 +{
 +    DWC2State *s = container_of(bus, DWC2State, bus);
 +
 +    trace_usb_dwc2_wakeup_endpoint(ep, stream);
 +
 +    /* TODO - do something here? */
 +    qemu_bh_schedule(s->async_bh);
 +}
 +
 +static USBBusOps dwc2_bus_ops = {
 +    .wakeup_endpoint = dwc2_wakeup_endpoint,
 +};
 +
 +static void dwc2_work_timer(void *opaque)
 +{
 +    DWC2State *s = opaque;
 +
 +    trace_usb_dwc2_work_timer();
 +    qemu_bh_schedule(s->async_bh);
 +}
 +
 +static void dwc2_reset_enter(Object *obj, ResetType type)
 +{
 +    DWC2Class *c = DWC2_GET_CLASS(obj);
 +    DWC2State *s = DWC2_USB(obj);
 +    int i;
 +
 +    trace_usb_dwc2_reset_enter();
 +
 +    if (c->parent_phases.enter) {
 +        c->parent_phases.enter(obj, type);
 +    }
 +
 +    timer_del(s->frame_timer);
 +    qemu_bh_cancel(s->async_bh);
 +
 +    if (s->uport.dev && s->uport.dev->attached) {
 +        usb_detach(&s->uport);
 +    }
 +
 +    dwc2_bus_stop(s);
 +
 +    s->gotgctl = GOTGCTL_BSESVLD | GOTGCTL_ASESVLD | GOTGCTL_CONID_B;
 +    s->gotgint = 0;
 +    s->gahbcfg = 0;
 +    s->gusbcfg = 5 << GUSBCFG_USBTRDTIM_SHIFT;
 +    s->grstctl = GRSTCTL_AHBIDLE;
 +    s->gintsts = GINTSTS_CONIDSTSCHNG | GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP |
 +                 GINTSTS_CURMODE_HOST;
 +    s->gintmsk = 0;
 +    s->grxstsr = 0;
 +    s->grxstsp = 0;
 +    s->grxfsiz = 1024;
 +    s->gnptxfsiz = 1024 << FIFOSIZE_DEPTH_SHIFT;
 +    s->gnptxsts = (4 << FIFOSIZE_DEPTH_SHIFT) | 1024;
 +    s->gi2cctl = GI2CCTL_I2CDATSE0 | GI2CCTL_ACK;
 +    s->gpvndctl = 0;
 +    s->ggpio = 0;
 +    s->guid = 0;
 +    s->gsnpsid = 0x4f54294a;
 +    s->ghwcfg1 = 0;
 +    s->ghwcfg2 = (8 << GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT) |
 +                 (4 << GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT) |
 +                 (4 << GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT) |
 +                 GHWCFG2_DYNAMIC_FIFO |
 +                 GHWCFG2_PERIO_EP_SUPPORTED |
 +                 ((DWC2_NB_CHAN - 1) << GHWCFG2_NUM_HOST_CHAN_SHIFT) |
 +                 (GHWCFG2_INT_DMA_ARCH << GHWCFG2_ARCHITECTURE_SHIFT) |
 +                 (GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST << GHWCFG2_OP_MODE_SHIFT);
 +    s->ghwcfg3 = (4096 << GHWCFG3_DFIFO_DEPTH_SHIFT) |
 +                 (4 << GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT) |
 +                 (4 << GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT);
 +    s->ghwcfg4 = 0;
 +    s->glpmcfg = 0;
 +    s->gpwrdn = GPWRDN_PWRDNRSTN;
 +    s->gdfifocfg = 0;
 +    s->gadpctl = 0;
 +    s->grefclk = 0;
 +    s->gintmsk2 = 0;
 +    s->gintsts2 = 0;
 +
 +    s->hptxfsiz = 500 << FIFOSIZE_DEPTH_SHIFT;
 +
 +    s->hcfg = 2 << HCFG_RESVALID_SHIFT;
 +    s->hfir = 60000;
 +    s->hfnum = 0x3fff;
 +    s->hptxsts = (16 << TXSTS_QSPCAVAIL_SHIFT) | 32768;
 +    s->haint = 0;
 +    s->haintmsk = 0;
 +    s->hprt0 = 0;
 +
 +    memset(s->hreg1, 0, sizeof(s->hreg1));
 +    memset(s->pcgreg, 0, sizeof(s->pcgreg));
 +
 +    s->sof_time = 0;
 +    s->frame_number = 0;
 +    s->fi = USB_FRMINTVL - 1;
 +    s->next_chan = 0;
 +    s->working = false;
 +
 +    for (i = 0; i < DWC2_NB_CHAN; i++) {
 +        s->packet[i].needs_service = false;
 +    }
 +}
 +
 +static void dwc2_reset_hold(Object *obj)
 +{
 +    DWC2Class *c = DWC2_GET_CLASS(obj);
 +    DWC2State *s = DWC2_USB(obj);
 +
 +    trace_usb_dwc2_reset_hold();
 +
 +    if (c->parent_phases.hold) {
 +        c->parent_phases.hold(obj);
 +    }
 +
 +    dwc2_update_irq(s);
 +}
 +
 +static void dwc2_reset_exit(Object *obj)
 +{
 +    DWC2Class *c = DWC2_GET_CLASS(obj);
 +    DWC2State *s = DWC2_USB(obj);
 +
 +    trace_usb_dwc2_reset_exit();
 +
 +    if (c->parent_phases.exit) {
 +        c->parent_phases.exit(obj);
 +    }
 +
 +    s->hprt0 = HPRT0_PWR;
 +    if (s->uport.dev && s->uport.dev->attached) {
 +        usb_attach(&s->uport);
 +        usb_device_reset(s->uport.dev);
 +    }
 +}
 +
 +static void dwc2_realize(DeviceState *dev, Error **errp)
 +{
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 +    DWC2State *s = DWC2_USB(dev);
 +    Object *obj;
 +    Error *err = NULL;
 +
 +    obj = object_property_get_link(OBJECT(dev), "dma-mr", &err);
 +    if (err) {
 +        error_setg(errp, "dwc2: required dma-mr link not found: %s",
 +                   error_get_pretty(err));
 +        return;
 +    }
 +    assert(obj != NULL);
 +
 +    s->dma_mr = MEMORY_REGION(obj);
 +    address_space_init(&s->dma_as, s->dma_mr, "dwc2");
 +
 +    usb_bus_new(&s->bus, sizeof(s->bus), &dwc2_bus_ops, dev);
 +    usb_register_port(&s->bus, &s->uport, s, 0, &dwc2_port_ops,
 +                      USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL |
 +                      (s->usb_version == 2 ? USB_SPEED_MASK_HIGH : 0));
 +    s->uport.dev = 0;
 +
 +    s->usb_frame_time = NANOSECONDS_PER_SECOND / 1000;          /* 1000000 */
 +    if (NANOSECONDS_PER_SECOND >= USB_HZ_FS) {
 +        s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_FS;   /* 83.3 */
 +    } else {
 +        s->usb_bit_time = 1;
 +    }
 +
 +    s->fi = USB_FRMINTVL - 1;
 +    s->eof_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, dwc2_frame_boundary, s);
 +    s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, dwc2_work_timer, s);
 +    s->async_bh = qemu_bh_new(dwc2_work_bh, s);
 +
 +    sysbus_init_irq(sbd, &s->irq);
 +}
 +
 +static void dwc2_init(Object *obj)
 +{
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 +    DWC2State *s = DWC2_USB(obj);
 +
 +    memory_region_init(&s->container, obj, "dwc2", DWC2_MMIO_SIZE);
 +    sysbus_init_mmio(sbd, &s->container);
 +
 +    memory_region_init_io(&s->hsotg, obj, &dwc2_mmio_hsotg_ops, s,
 +                          "dwc2-io", 4 * KiB);
 +    memory_region_add_subregion(&s->container, 0x0000, &s->hsotg);
 +
 +    memory_region_init_io(&s->fifos, obj, &dwc2_mmio_hreg2_ops, s,
 +                          "dwc2-fifo", 64 * KiB);
 +    memory_region_add_subregion(&s->container, 0x1000, &s->fifos);
 +}
 +
 +static const VMStateDescription vmstate_dwc2_state_packet = {
 +    .name = "dwc2/packet",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32(devadr, DWC2Packet),
 +        VMSTATE_UINT32(epnum, DWC2Packet),
 +        VMSTATE_UINT32(epdir, DWC2Packet),
 +        VMSTATE_UINT32(mps, DWC2Packet),
 +        VMSTATE_UINT32(pid, DWC2Packet),
 +        VMSTATE_UINT32(index, DWC2Packet),
 +        VMSTATE_UINT32(pcnt, DWC2Packet),
 +        VMSTATE_UINT32(len, DWC2Packet),
 +        VMSTATE_INT32(async, DWC2Packet),
 +        VMSTATE_BOOL(small, DWC2Packet),
 +        VMSTATE_BOOL(needs_service, DWC2Packet),
 +        VMSTATE_END_OF_LIST()
 +    },
 +};
 +
 +const VMStateDescription vmstate_dwc2_state = {
 +    .name = "dwc2",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(glbreg, DWC2State,
 +                             DWC2_GLBREG_SIZE / sizeof(uint32_t)),
 +        VMSTATE_UINT32_ARRAY(fszreg, DWC2State,
 +                             DWC2_FSZREG_SIZE / sizeof(uint32_t)),
 +        VMSTATE_UINT32_ARRAY(hreg0, DWC2State,
 +                             DWC2_HREG0_SIZE / sizeof(uint32_t)),
 +        VMSTATE_UINT32_ARRAY(hreg1, DWC2State,
 +                             DWC2_HREG1_SIZE / sizeof(uint32_t)),
 +        VMSTATE_UINT32_ARRAY(pcgreg, DWC2State,
 +                             DWC2_PCGREG_SIZE / sizeof(uint32_t)),
 +
 +        VMSTATE_TIMER_PTR(eof_timer, DWC2State),
 +        VMSTATE_TIMER_PTR(frame_timer, DWC2State),
 +        VMSTATE_INT64(sof_time, DWC2State),
 +        VMSTATE_INT64(usb_frame_time, DWC2State),
 +        VMSTATE_INT64(usb_bit_time, DWC2State),
 +        VMSTATE_UINT32(usb_version, DWC2State),
 +        VMSTATE_UINT16(frame_number, DWC2State),
 +        VMSTATE_UINT16(fi, DWC2State),
 +        VMSTATE_UINT16(next_chan, DWC2State),
 +        VMSTATE_BOOL(working, DWC2State),
 +
 +        VMSTATE_STRUCT_ARRAY(packet, DWC2State, DWC2_NB_CHAN, 1,
 +                             vmstate_dwc2_state_packet, DWC2Packet),
 +        VMSTATE_UINT8_2DARRAY(usb_buf, DWC2State, DWC2_NB_CHAN,
 +                              DWC2_MAX_XFER_SIZE),
 +
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static Property dwc2_usb_properties[] = {
 +    DEFINE_PROP_UINT32("usb_version", DWC2State, usb_version, 2),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void dwc2_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +    DWC2Class *c = DWC2_CLASS(klass);
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
 +
 +    dc->realize = dwc2_realize;
 +    dc->vmsd = &vmstate_dwc2_state;
 +    set_bit(DEVICE_CATEGORY_USB, dc->categories);
 +    device_class_set_props(dc, dwc2_usb_properties);
 +    resettable_class_set_parent_phases(rc, dwc2_reset_enter, dwc2_reset_hold,
 +                                       dwc2_reset_exit, &c->parent_phases);
 +}
 +
 +static const TypeInfo dwc2_usb_type_info = {
 +    .name          = TYPE_DWC2_USB,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(DWC2State),
 +    .instance_init = dwc2_init,
 +    .class_size    = sizeof(DWC2Class),
 +    .class_init    = dwc2_class_init,
 +};
 +
 +static void dwc2_usb_register_types(void)
 +{
 +    type_register_static(&dwc2_usb_type_info);
 +}
 +
 +type_init(dwc2_usb_register_types)
 diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/usb/Kconfig
 +++ b/hw/usb/Kconfig
@@ -XXX,XX +XXX,XX @@ config USB_MUSB
      bool
      select USB
 +config USB_DWC2
 +    bool
 +    default y
 +    select USB
 +
  config TUSB6010
      bool
      select USB_MUSB
 diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/usb/Makefile.objs
 +++ b/hw/usb/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_USB_EHCI_SYSBUS) += hcd-ehci-sysbus.o
  common-obj-$(CONFIG_USB_XHCI) += hcd-xhci.o
  common-obj-$(CONFIG_USB_XHCI_NEC) += hcd-xhci-nec.o
  common-obj-$(CONFIG_USB_MUSB) += hcd-musb.o
 +common-obj-$(CONFIG_USB_DWC2) += hcd-dwc2.o
  common-obj-$(CONFIG_TUSB6010) += tusb6010.o
  common-obj-$(CONFIG_IMX)      += chipidea.o
 diff --git a/hw/usb/trace-events b/hw/usb/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/usb/trace-events
 +++ b/hw/usb/trace-events
@@ -XXX,XX +XXX,XX @@ usb_xhci_xfer_error(void *xfer, uint32_t ret) "%p: ret %d"
  usb_xhci_unimplemented(const char *item, int nr) "%s (0x%x)"
  usb_xhci_enforced_limit(const char *item) "%s"
 +# hcd-dwc2.c
 +usb_dwc2_update_irq(uint32_t level) "level=%d"
 +usb_dwc2_raise_global_irq(uint32_t intr) "0x%08x"
 +usb_dwc2_lower_global_irq(uint32_t intr) "0x%08x"
 +usb_dwc2_raise_host_irq(uint32_t intr) "0x%04x"
 +usb_dwc2_lower_host_irq(uint32_t intr) "0x%04x"
 +usb_dwc2_sof(int64_t next) "next SOF %" PRId64
 +usb_dwc2_bus_start(void) "start SOFs"
 +usb_dwc2_bus_stop(void) "stop SOFs"
 +usb_dwc2_find_device(uint8_t addr) "%d"
 +usb_dwc2_port_disabled(uint32_t pnum) "port %d disabled"
 +usb_dwc2_device_found(uint32_t pnum) "device found on port %d"
 +usb_dwc2_device_not_found(void) "device not found"
 +usb_dwc2_handle_packet(uint32_t chan, void *dev, void *pkt, uint32_t ep, const char *type, const char *dir, uint32_t mps, uint32_t len, uint32_t pcnt) "ch %d dev %p pkt %p ep %d type %s dir %s mps %d len %d pcnt %d"
 +usb_dwc2_memory_read(uint32_t addr, uint32_t len) "addr %d len %d"
 +usb_dwc2_packet_status(const char *status, uint32_t len) "status %s len %d"
 +usb_dwc2_packet_error(const char *status) "ERROR %s"
 +usb_dwc2_async_packet(void *pkt, uint32_t chan, void *dev, uint32_t ep, const char *dir, uint32_t len) "pkt %p ch %d dev %p ep %d %s len %d"
 +usb_dwc2_memory_write(uint32_t addr, uint32_t len) "addr %d len %d"
 +usb_dwc2_packet_done(const char *status, uint32_t actual, uint32_t len, uint32_t pcnt) "status %s actual %d len %d pcnt %d"
 +usb_dwc2_packet_next(const char *status, uint32_t len, uint32_t pcnt) "status %s len %d pcnt %d"
 +usb_dwc2_attach(void *port) "port %p"
 +usb_dwc2_attach_speed(const char *speed) "%s-speed device attached"
 +usb_dwc2_detach(void *port) "port %p"
 +usb_dwc2_child_detach(void *port, void *child) "port %p child %p"
 +usb_dwc2_wakeup(void *port) "port %p"
 +usb_dwc2_async_packet_complete(void *port, void *pkt, uint32_t chan, void *dev, uint32_t ep, const char *dir, uint32_t len) "port %p packet %p ch %d dev %p ep %d %s len %d"
 +usb_dwc2_work_bh(void) ""
 +usb_dwc2_work_bh_service(uint32_t first, uint32_t current, void *dev, uint32_t ep) "first %d servicing %d dev %p ep %d"
 +usb_dwc2_work_bh_next(uint32_t chan) "next %d"
 +usb_dwc2_enable_chan(uint32_t chan, void *dev, void *pkt, uint32_t ep) "ch %d dev %p pkt %p ep %d"
 +usb_dwc2_glbreg_read(uint64_t addr, const char *reg, uint32_t val) " 0x%04" PRIx64 " %s val 0x%08x"
 +usb_dwc2_glbreg_write(uint64_t addr, const char *reg, uint64_t val, uint32_t old, uint64_t result) "0x%04" PRIx64 " %s val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
 +usb_dwc2_fszreg_read(uint64_t addr, uint32_t val) " 0x%04" PRIx64 " HPTXFSIZ  val 0x%08x"
 +usb_dwc2_fszreg_write(uint64_t addr, uint64_t val, uint32_t old, uint64_t result) "0x%04" PRIx64 " HPTXFSIZ  val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
 +usb_dwc2_hreg0_read(uint64_t addr, const char *reg, uint32_t val) "  0x%04" PRIx64 " %s val 0x%08x"
 +usb_dwc2_hreg0_write(uint64_t addr, const char *reg, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " %s val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
 +usb_dwc2_hreg1_read(uint64_t addr, const char *reg, uint64_t chan, uint32_t val) "  0x%04" PRIx64 " %s%" PRId64 " val 0x%08x"
 +usb_dwc2_hreg1_write(uint64_t addr, const char *reg, uint64_t chan, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " %s%" PRId64 " val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
 +usb_dwc2_pcgreg_read(uint64_t addr, const char *reg, uint32_t val) " 0x%04" PRIx64 " %s val 0x%08x"
 +usb_dwc2_pcgreg_write(uint64_t addr, const char *reg, uint64_t val, uint32_t old, uint64_t result) "0x%04" PRIx64 " %s val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
 +usb_dwc2_hreg2_read(uint64_t addr, uint64_t fifo, uint32_t val) "  0x%04" PRIx64 " FIFO%" PRId64 "     val 0x%08x"
 +usb_dwc2_hreg2_write(uint64_t addr, uint64_t fifo, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " FIFO%" PRId64 "     val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
 +usb_dwc2_hreg0_action(const char *s) "%s"
 +usb_dwc2_wakeup_endpoint(void *ep, uint32_t stream) "endp %p stream %d"
 +usb_dwc2_work_timer(void) ""
 +usb_dwc2_reset_enter(void) "=== RESET enter ==="
 +usb_dwc2_reset_hold(void) "=== RESET hold ==="
 +usb_dwc2_reset_exit(void) "=== RESET exit ==="
 +
  # desc.c
  usb_desc_device(int addr, int len, int ret) "dev %d query device, len %d, ret %d"
  usb_desc_device_qualifier(int addr, int len, int ret) "dev %d query device qualifier, len %d, ret %d"
 --
 .20.1

-[PULL 18/29] usb: add short-packet handling to usb-storage driver
+[PULL 16/24] target/arm: Implement MVE VSRI, VSLI
-From: Paul Zimmerman <pauldzim@gmail.com>
+Implement the MVE VSRI and VSLI insns, which perform a
 shift-and-insert operation.
-The dwc-hsotg (dwc2) USB host depends on a short packet to
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-indicate the end of an IN transfer. The usb-storage driver
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-currently doesn't provide this, so fix it.
+Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
 ---
  target/arm/helper-mve.h    |  8 ++++++++
  target/arm/mve.decode      |  9 ++++++++
  target/arm/mve_helper.c    | 42 ++++++++++++++++++++++++++++++++++++++
  target/arm/translate-mve.c |  3 +++
 files changed, 62 insertions(+)
-I have tested this change rather extensively using a PC
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 emulation with xhci, ehci, and uhci controllers, and have
 not observed any regressions.
 Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
 Message-id: 20200520235349.21215-6-pauldzim@gmail.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  hw/usb/dev-storage.c | 15 ++++++++++++++-
 file changed, 14 insertions(+), 1 deletion(-)
 diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/usb/dev-storage.c
+--- a/target/arm/helper-mve.h
-+++ b/hw/usb/dev-storage.c
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ static void usb_msd_copy_data(MSDState *s, USBPacket *p)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     usb_packet_copy(p, scsi_req_get_buf(s->req) + s->scsi_off, len);
+ DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     s->scsi_len -= len;
+ DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     s->scsi_off += len;
+ DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+    if (len > s->data_len) {
++
-+        len = s->data_len;
++DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
  VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
  VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
 +
 +# Shift-and-insert
 +VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
 +VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
 +VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
 +
 +VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
 +VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
 +VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
  DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
  DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
 +/* Shift-and-insert; we always work with 64 bits at a time */
 +#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN)                    \
 +    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,             \
 +                                void *vm, uint32_t shift)               \
 +    {                                                                   \
 +        uint64_t *d = vd, *m = vm;                                      \
 +        uint16_t mask;                                                  \
 +        uint64_t shiftmask;                                             \
 +        unsigned e;                                                     \
 +        if (shift == 0 || shift == ESIZE * 8) {                         \
 +            /*                                                          \
 +             * Only VSLI can shift by 0; only VSRI can shift by <dt>.   \
 +             * The generic logic would give the right answer for 0 but  \
 +             * fails for <dt>.                                          \
 +             */                                                         \
 +            goto done;                                                  \
 +        }                                                               \
 +        assert(shift < ESIZE * 8);                                      \
 +        mask = mve_element_mask(env);                                   \
 +        /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */     \
 +        shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift));     \
 +        for (e = 0; e < 16 / 8; e++, mask >>= 8) {                      \
 +            uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) |       \
 +                (d[H8(e)] & ~shiftmask);                                \
 +            mergemask(&d[H8(e)], r, mask);                              \
 +        }                                                               \
 +done:                                                                   \
 +        mve_advance_vpt(env);                                           \
 +    }
-     s->data_len -= len;
++
-     if (s->scsi_len == 0 || s->data_len == 0) {
++#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
-         scsi_req_continue(s->req);
++#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
-@@ -XXX,XX +XXX,XX @@ static void usb_msd_command_complete(SCSIRequest *req, uint32_t status, size_t r
++#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
-             if (s->data_len) {
++#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
-                 int len = (p->iov.size - p->actual_length);
++
-                 usb_packet_skip(p, len);
++DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
-+                if (len > s->data_len) {
++DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
-+                    len = s->data_len;
++DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
-+                }
++DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
-                 s->data_len -= len;
++DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
-             }
++DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
-             if (s->data_len == 0) {
++
-@@ -XXX,XX +XXX,XX @@ static void usb_msd_handle_data(USBDevice *dev, USBPacket *p)
+ /*
-                 int len = p->iov.size - p->actual_length;
+  * Long shifts taking half-sized inputs from top or bottom of the input
-                 if (len) {
+  * vector and producing a double-width result. ESIZE, TYPE are for
-                     usb_packet_skip(p, len);
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
-+                    if (len > s->data_len) {
+index XXXXXXX..XXXXXXX 100644
-+                        len = s->data_len;
+--- a/target/arm/translate-mve.c
-+                    }
++++ b/target/arm/translate-mve.c
-                     s->data_len -= len;
+@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
-                     if (s->data_len == 0) {
+ DO_2SHIFT(VRSHRI_S, vrshli_s, true)
-                         s->mode = USB_MSDM_CSW;
+ DO_2SHIFT(VRSHRI_U, vrshli_u, true)
-@@ -XXX,XX +XXX,XX @@ static void usb_msd_handle_data(USBDevice *dev, USBPacket *p)
-                 int len = p->iov.size - p->actual_length;
++DO_2SHIFT(VSRI, vsri, false)
-                 if (len) {
++DO_2SHIFT(VSLI, vsli, false)
-                     usb_packet_skip(p, len);
++
-+                    if (len > s->data_len) {
+ #define DO_VSHLL(INSN, FN)                                      \
-+                        len = s->data_len;
+     static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
-+                    }
+     {                                                           \
                      s->data_len -= len;
                      if (s->data_len == 0) {
                          s->mode = USB_MSDM_CSW;
                      }
                  }
              }
 -            if (p->actual_length < p->iov.size) {
 +            if (p->actual_length < p->iov.size && (p->short_not_ok ||
 +                    s->scsi_len >= p->ep->max_packet_size)) {
                  DPRINTF("Deferring packet %p [wait data-in]\n", p);
                  s->packet = p;
                  p->status = USB_RET_ASYNC;
 --
 .20.1

-[PULL 19/29] wire in the dwc-hsotg (dwc2) USB host controller emulation
+[PULL 17/24] target/arm: Implement MVE VSHRN, VRSHRN
-From: Paul Zimmerman <pauldzim@gmail.com>
+Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
-Wire the dwc-hsotg (dwc2) emulation into Qemu
+do_urshr() is borrowed from sve_helper.c.
-Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
-Reviewed-by: Philippe Mathieu-Daude <f4bug@amsat.org>
-Message-id: 20200520235349.21215-7-pauldzim@gmail.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
 ---
- include/hw/arm/bcm2835_peripherals.h |  3 ++-
+ target/arm/helper-mve.h    | 10 ++++++++++
- hw/arm/bcm2835_peripherals.c         | 21 ++++++++++++++++++++-
+ target/arm/mve.decode      | 11 +++++++++++
-files changed, 22 insertions(+), 2 deletions(-)
+ target/arm/mve_helper.c    | 40 ++++++++++++++++++++++++++++++++++++++
  target/arm/translate-mve.c | 15 ++++++++++++++
 files changed, 76 insertions(+)
-diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/bcm2835_peripherals.h
+--- a/target/arm/helper-mve.h
-+++ b/include/hw/arm/bcm2835_peripherals.h
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- #include "hw/sd/bcm2835_sdhost.h"
+ DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- #include "hw/gpio/bcm2835_gpio.h"
+ DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- #include "hw/timer/bcm2835_systmr.h"
+ DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+#include "hw/usb/hcd-dwc2.h"
++
- #include "hw/misc/unimp.h"
++DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- #define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
++DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-@@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState {
++DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     UnimplementedDeviceState ave0;
++
-     UnimplementedDeviceState bscsl;
++DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     UnimplementedDeviceState smi;
++DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
--    UnimplementedDeviceState dwc2;
++DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+    DWC2State dwc2;
++DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     UnimplementedDeviceState sdramc;
+diff --git a/target/arm/mve.decode b/target/arm/mve.decode
  } BCM2835PeripheralState;
 diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2835_peripherals.c
+--- a/target/arm/mve.decode
-+++ b/hw/arm/bcm2835_peripherals.c
++++ b/target/arm/mve.decode
-@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
-     /* Mphi */
+ VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
-     sysbus_init_child_obj(obj, "mphi", &s->mphi, sizeof(s->mphi),
+ VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
-                           TYPE_BCM2835_MPHI);
+ VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
 +
-+    /* DWC2 */
++# Narrowing shifts (which only support b and h sizes)
-+    sysbus_init_child_obj(obj, "dwc2", &s->dwc2, sizeof(s->dwc2),
++VSHRNB            111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
-+                          TYPE_DWC2_USB);
++VSHRNB            111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
 +VSHRNT            111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
 +VSHRNT            111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
 +
-+    object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
++VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
-+                                   OBJECT(&s->gpu_bus_mr));
++VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
- }
++VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
++VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
- static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
+diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
+index XXXXXXX..XXXXXXX 100644
-         qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
+--- a/target/arm/mve_helper.c
-                                INTERRUPT_HOSTPORT));
++++ b/target/arm/mve_helper.c
+@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
-+    /* DWC2 */
-+    object_property_set_bool(OBJECT(&s->dwc2), true, "realized", &err);
+ DO_VSHLL_ALL(vshllb, false)
-+    if (err) {
+ DO_VSHLL_ALL(vshllt, true)
-+        error_propagate(errp, err);
++
-+        return;
++/*
 + * Narrowing right shifts, taking a double sized input, shifting it
 + * and putting the result in either the top or bottom half of the output.
 + * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
 + */
 +#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)       \
 +    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
 +                                void *vm, uint32_t shift)       \
 +    {                                                           \
 +        LTYPE *m = vm;                                          \
 +        TYPE *d = vd;                                           \
 +        uint16_t mask = mve_element_mask(env);                  \
 +        unsigned le;                                            \
 +        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
 +            TYPE r = FN(m[H##LESIZE(le)], shift);               \
 +            mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask);     \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +    }
 +
-+    memory_region_add_subregion(&s->peri_mr, USB_OTG_OFFSET,
++#define DO_VSHRN_ALL(OP, FN)                                    \
-+                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dwc2), 0));
++    DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN)        \
-+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->dwc2), 0,
++    DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN)       \
-+        qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
++    DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN)         \
-+                               INTERRUPT_USB));
++    DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
 +
-     create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
++static inline uint64_t do_urshr(uint64_t x, unsigned sh)
-     create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
++{
-     create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
++    if (likely(sh < 64)) {
-@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
++        return (x >> sh) + ((x >> (sh - 1)) & 1);
-     create_unimp(s, &s->otp, "bcm2835-otp", OTP_OFFSET, 0x80);
++    } else if (sh == 64) {
-     create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000);
++        return x >> 63;
-     create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000);
++    } else {
--    create_unimp(s, &s->dwc2, "dwc-usb2", USB_OTG_OFFSET, 0x1000);
++        return 0;
-     create_unimp(s, &s->sdramc, "bcm2835-sdramc", SDRAMC_OFFSET, 0x100);
++    }
- }
++}
++
 +DO_VSHRN_ALL(vshrn, DO_SHR)
 +DO_VSHRN_ALL(vrshrn, do_urshr)
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs)
  DO_VSHLL(VSHLL_BU, vshllbu)
  DO_VSHLL(VSHLL_TS, vshllts)
  DO_VSHLL(VSHLL_TU, vshlltu)
 +
 +#define DO_2SHIFT_N(INSN, FN)                                   \
 +    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
 +    {                                                           \
 +        static MVEGenTwoOpShiftFn * const fns[] = {             \
 +            gen_helper_mve_##FN##b,                             \
 +            gen_helper_mve_##FN##h,                             \
 +        };                                                      \
 +        return do_2shift(s, a, fns[a->size], false);            \
 +    }
 +
 +DO_2SHIFT_N(VSHRNB, vshrnb)
 +DO_2SHIFT_N(VSHRNT, vshrnt)
 +DO_2SHIFT_N(VRSHRNB, vrshrnb)
 +DO_2SHIFT_N(VRSHRNT, vrshrnt)
 --
 .20.1

-[PULL 09/29] target/arm: Split helper_crypto_sha1_3reg
+[PULL 18/24] target/arm: Implement MVE saturating narrowing shifts
-From: Richard Henderson <richard.henderson@linaro.org>
+Implement the MVE saturating shift-right-and-narrow insns
+VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
-Rather than passing an opcode to a helper, fully decode the
-operation at translate time.  Use clear_tail_16 to zap the
+do_srshr() is borrowed from sve_helper.c.
-balance of the SVE register with the AdvSIMD write.
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20200514212831.31248-6-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
 ---
- target/arm/helper.h             |  5 +-
+ target/arm/helper-mve.h    |  30 +++++++++++
- target/arm/neon-dp.decode       |  6 +-
+ target/arm/mve.decode      |  28 ++++++++++
- target/arm/crypto_helper.c      | 99 +++++++++++++++++++++------------
+ target/arm/mve_helper.c    | 104 +++++++++++++++++++++++++++++++++++++
- target/arm/translate-a64.c      | 29 ++++------
+ target/arm/translate-mve.c |  12 +++++
- target/arm/translate-neon.inc.c | 46 ++++-----------
+files changed, 174 insertions(+)
-files changed, 93 insertions(+), 92 deletions(-)
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
-diff --git a/target/arm/helper.h b/target/arm/helper.h
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper-mve.h
---- a/target/arm/helper.h
++++ b/target/arm/helper-mve.h
-+++ b/target/arm/helper.h
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr)
+ DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+ DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+ DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++
--DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
++DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(crypto_sha1su0, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
++DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(crypto_sha1c, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
++DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(crypto_sha1p, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
++DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(crypto_sha1m, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
++
- DEF_HELPER_FLAGS_3(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
++DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_3(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
++DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
++DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-index XXXXXXX..XXXXXXX 100644
++
---- a/target/arm/neon-dp.decode
++DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+++ b/target/arm/neon-dp.decode
++DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-@@ -XXX,XX +XXX,XX @@ VQRDMLAH_3s      1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
++DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- @3same_crypto    .... .... .... .... .... .... .... .... \
++DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 q=1
++
++DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
--SHA1_3s          1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \
++DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
--                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
++DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+SHA1C_3s         1111 001 0 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
++DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+SHA1P_3s         1111 001 0 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
++
-+SHA1M_3s         1111 001 0 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
++DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+SHA1SU0_3s       1111 001 0 0 . 11 .... .... 1100 . 1 . 0 .... @3same_crypto
++DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- SHA256H_3s       1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
++DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- SHA256H2_3s      1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
++DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- SHA256SU1_3s     1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
++
-diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
++DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-index XXXXXXX..XXXXXXX 100644
++DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
---- a/target/arm/crypto_helper.c
++DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+++ b/target/arm/crypto_helper.c
++DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-@@ -XXX,XX +XXX,XX @@ union CRYPTO_STATE {
+diff --git a/target/arm/mve.decode b/target/arm/mve.decode
- };
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/mve.decode
- #ifdef HOST_WORDS_BIGENDIAN
++++ b/target/arm/mve.decode
--#define CR_ST_BYTE(state, i)   (state.bytes[(15 - (i)) ^ 8])
+@@ -XXX,XX +XXX,XX @@ VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
--#define CR_ST_WORD(state, i)   (state.words[(3 - (i)) ^ 2])
+ VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
-+#define CR_ST_BYTE(state, i)   ((state).bytes[(15 - (i)) ^ 8])
+ VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
-+#define CR_ST_WORD(state, i)   ((state).words[(3 - (i)) ^ 2])
+ VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
- #else
++
--#define CR_ST_BYTE(state, i)   (state.bytes[i])
++VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
--#define CR_ST_WORD(state, i)   (state.words[i])
++VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
-+#define CR_ST_BYTE(state, i)   ((state).bytes[i])
++VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
-+#define CR_ST_WORD(state, i)   ((state).words[i])
++VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
- #endif
++VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
++VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
- /*
++VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
-@@ -XXX,XX +XXX,XX @@ static uint32_t maj(uint32_t x, uint32_t y, uint32_t z)
++VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
-     return (x & y) | ((x | y) & z);
++
 +VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
 +VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
 +VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
 +VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
 +
 +VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
 +VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
 +VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
 +VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
 +VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
 +VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
 +VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
 +VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
 +
 +VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
 +VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
 +VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
 +VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
      }
  }
--void HELPER(crypto_sha1_3reg)(void *vd, void *vn, void *vm, uint32_t op)
++static inline int64_t do_srshr(int64_t x, unsigned sh)
 +void HELPER(crypto_sha1su0)(void *vd, void *vn, void *vm, uint32_t desc)
 +{
-+    uint64_t *d = vd, *n = vn, *m = vm;
++    if (likely(sh < 64)) {
-+    uint64_t d0, d1;
++        return (x >> sh) + ((x >> (sh - 1)) & 1);
-+
++    } else {
-+    d0 = d[1] ^ d[0] ^ m[0];
++        /* Rounding the sign bit always produces 0. */
-+    d1 = n[0] ^ d[1] ^ m[1];
++        return 0;
-+    d[0] = d0;
++    }
 +    d[1] = d1;
 +
 +    clear_tail_16(vd, desc);
 +}
 +
-+static inline void crypto_sha1_3reg(uint64_t *rd, uint64_t *rn,
+ DO_VSHRN_ALL(vshrn, DO_SHR)
-+                                    uint64_t *rm, uint32_t desc,
+ DO_VSHRN_ALL(vrshrn, do_urshr)
-+                                    uint32_t (*fn)(union CRYPTO_STATE *d))
++
- {
++static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
--    uint64_t *rd = vd;
++                                 bool *satp)
--    uint64_t *rn = vn;
++{
--    uint64_t *rm = vm;
++    if (val > max) {
-     union CRYPTO_STATE d = { .l = { rd[0], rd[1] } };
++        *satp = true;
-     union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };
++        return max;
-     union CRYPTO_STATE m = { .l = { rm[0], rm[1] } };
++    } else if (val < min) {
-+    int i;
++        *satp = true;
++        return min;
--    if (op == 3) { /* sha1su0 */
++    } else {
--        d.l[0] ^= d.l[1] ^ m.l[0];
++        return val;
--        d.l[1] ^= n.l[0] ^ m.l[1];
++    }
 -    } else {
 -        int i;
 +    for (i = 0; i < 4; i++) {
 +        uint32_t t = fn(&d);
 -        for (i = 0; i < 4; i++) {
 -            uint32_t t;
 +        t += rol32(CR_ST_WORD(d, 0), 5) + CR_ST_WORD(n, 0)
 +             + CR_ST_WORD(m, i);
 -            switch (op) {
 -            case 0: /* sha1c */
 -                t = cho(CR_ST_WORD(d, 1), CR_ST_WORD(d, 2), CR_ST_WORD(d, 3));
 -                break;
 -            case 1: /* sha1p */
 -                t = par(CR_ST_WORD(d, 1), CR_ST_WORD(d, 2), CR_ST_WORD(d, 3));
 -                break;
 -            case 2: /* sha1m */
 -                t = maj(CR_ST_WORD(d, 1), CR_ST_WORD(d, 2), CR_ST_WORD(d, 3));
 -                break;
 -            default:
 -                g_assert_not_reached();
 -            }
 -            t += rol32(CR_ST_WORD(d, 0), 5) + CR_ST_WORD(n, 0)
 -                 + CR_ST_WORD(m, i);
 -
 -            CR_ST_WORD(n, 0) = CR_ST_WORD(d, 3);
 -            CR_ST_WORD(d, 3) = CR_ST_WORD(d, 2);
 -            CR_ST_WORD(d, 2) = ror32(CR_ST_WORD(d, 1), 2);
 -            CR_ST_WORD(d, 1) = CR_ST_WORD(d, 0);
 -            CR_ST_WORD(d, 0) = t;
 -        }
 +        CR_ST_WORD(n, 0) = CR_ST_WORD(d, 3);
 +        CR_ST_WORD(d, 3) = CR_ST_WORD(d, 2);
 +        CR_ST_WORD(d, 2) = ror32(CR_ST_WORD(d, 1), 2);
 +        CR_ST_WORD(d, 1) = CR_ST_WORD(d, 0);
 +        CR_ST_WORD(d, 0) = t;
      }
      rd[0] = d.l[0];
      rd[1] = d.l[1];
 +
 +    clear_tail_16(rd, desc);
 +}
 +
-+static uint32_t do_sha1c(union CRYPTO_STATE *d)
++/* Saturating narrowing right shifts */
-+{
++#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)   \
-+    return cho(CR_ST_WORD(*d, 1), CR_ST_WORD(*d, 2), CR_ST_WORD(*d, 3));
++    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
-+}
++                                void *vm, uint32_t shift)       \
-+
++    {                                                           \
-+void HELPER(crypto_sha1c)(void *vd, void *vn, void *vm, uint32_t desc)
++        LTYPE *m = vm;                                          \
-+{
++        TYPE *d = vd;                                           \
-+    crypto_sha1_3reg(vd, vn, vm, desc, do_sha1c);
++        uint16_t mask = mve_element_mask(env);                  \
-+}
++        bool qc = false;                                        \
-+
++        unsigned le;                                            \
-+static uint32_t do_sha1p(union CRYPTO_STATE *d)
++        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
-+{
++            bool sat = false;                                   \
-+    return par(CR_ST_WORD(*d, 1), CR_ST_WORD(*d, 2), CR_ST_WORD(*d, 3));
++            TYPE r = FN(m[H##LESIZE(le)], shift, &sat);         \
-+}
++            mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask);     \
-+
++            qc |= sat && (mask & 1 << (TOP * ESIZE));           \
-+void HELPER(crypto_sha1p)(void *vd, void *vn, void *vm, uint32_t desc)
++        }                                                       \
-+{
++        if (qc) {                                               \
-+    crypto_sha1_3reg(vd, vn, vm, desc, do_sha1p);
++            env->vfp.qc[0] = qc;                                \
-+}
++        }                                                       \
-+
++        mve_advance_vpt(env);                                   \
-+static uint32_t do_sha1m(union CRYPTO_STATE *d)
++    }
-+{
++
-+    return maj(CR_ST_WORD(*d, 1), CR_ST_WORD(*d, 2), CR_ST_WORD(*d, 3));
++#define DO_VSHRN_SAT_UB(BOP, TOP, FN)                           \
-+}
++    DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN)       \
-+
++    DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
-+void HELPER(crypto_sha1m)(void *vd, void *vn, void *vm, uint32_t desc)
++
-+{
++#define DO_VSHRN_SAT_UH(BOP, TOP, FN)                           \
-+    crypto_sha1_3reg(vd, vn, vm, desc, do_sha1m);
++    DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN)      \
- }
++    DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
++
- void HELPER(crypto_sha1h)(void *vd, void *vm, uint32_t desc)
++#define DO_VSHRN_SAT_SB(BOP, TOP, FN)                           \
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
++    DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN)         \
-index XXXXXXX..XXXXXXX 100644
++    DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
---- a/target/arm/translate-a64.c
++
-+++ b/target/arm/translate-a64.c
++#define DO_VSHRN_SAT_SH(BOP, TOP, FN)                           \
-@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
++    DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN)        \
++    DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
-     switch (opcode) {
++
-     case 0: /* SHA1C */
++#define DO_SHRN_SB(N, M, SATP)                                  \
-+        genfn = gen_helper_crypto_sha1c;
++    do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
-+        feature = dc_isar_feature(aa64_sha1, s);
++#define DO_SHRN_UB(N, M, SATP)                                  \
-+        break;
++    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
-     case 1: /* SHA1P */
++#define DO_SHRUN_B(N, M, SATP)                                  \
-+        genfn = gen_helper_crypto_sha1p;
++    do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
-+        feature = dc_isar_feature(aa64_sha1, s);
++
-+        break;
++#define DO_SHRN_SH(N, M, SATP)                                  \
-     case 2: /* SHA1M */
++    do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
-+        genfn = gen_helper_crypto_sha1m;
++#define DO_SHRN_UH(N, M, SATP)                                  \
-+        feature = dc_isar_feature(aa64_sha1, s);
++    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
-+        break;
++#define DO_SHRUN_H(N, M, SATP)                                  \
-     case 3: /* SHA1SU0 */
++    do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
--        genfn = NULL;
++
-+        genfn = gen_helper_crypto_sha1su0;
++#define DO_RSHRN_SB(N, M, SATP)                                 \
-         feature = dc_isar_feature(aa64_sha1, s);
++    do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
-         break;
++#define DO_RSHRN_UB(N, M, SATP)                                 \
-     case 4: /* SHA256H */
++    do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
-@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
++#define DO_RSHRUN_B(N, M, SATP)                                 \
-     if (!fp_access_check(s)) {
++    do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
-         return;
++
-     }
++#define DO_RSHRN_SH(N, M, SATP)                                 \
--
++    do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
--    if (genfn) {
++#define DO_RSHRN_UH(N, M, SATP)                                 \
--        gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn);
++    do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
--    } else {
++#define DO_RSHRUN_H(N, M, SATP)                                 \
--        TCGv_i32 tcg_opcode = tcg_const_i32(opcode);
++    do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
--        TCGv_ptr tcg_rd_ptr = vec_full_reg_ptr(s, rd);
++
--        TCGv_ptr tcg_rn_ptr = vec_full_reg_ptr(s, rn);
++DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
--        TCGv_ptr tcg_rm_ptr = vec_full_reg_ptr(s, rm);
++DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
--
++DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
--        gen_helper_crypto_sha1_3reg(tcg_rd_ptr, tcg_rn_ptr,
++DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
--                                    tcg_rm_ptr, tcg_opcode);
++DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
--
++DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
--        tcg_temp_free_i32(tcg_opcode);
++
--        tcg_temp_free_ptr(tcg_rd_ptr);
++DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
--        tcg_temp_free_ptr(tcg_rn_ptr);
++DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
--        tcg_temp_free_ptr(tcg_rm_ptr);
++DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
--    }
++DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
-+    gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn);
++DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
- }
++DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
- /* Crypto two-reg SHA
+index XXXXXXX..XXXXXXX 100644
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
+--- a/target/arm/translate-mve.c
-index XXXXXXX..XXXXXXX 100644
++++ b/target/arm/translate-mve.c
---- a/target/arm/translate-neon.inc.c
+@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
-+++ b/target/arm/translate-neon.inc.c
+ DO_2SHIFT_N(VSHRNT, vshrnt)
-@@ -XXX,XX +XXX,XX @@ static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
+ DO_2SHIFT_N(VRSHRNB, vrshrnb)
- DO_VQRDMLAH(VQRDMLAH, gen_gvec_sqrdmlah_qc)
+ DO_2SHIFT_N(VRSHRNT, vrshrnt)
- DO_VQRDMLAH(VQRDMLSH, gen_gvec_sqrdmlsh_qc)
++DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
++DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
--static bool trans_SHA1_3s(DisasContext *s, arg_SHA1_3s *a)
++DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
--{
++DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
--    TCGv_ptr ptr1, ptr2, ptr3;
++DO_2SHIFT_N(VQSHRUNB, vqshrunb)
--    TCGv_i32 tmp;
++DO_2SHIFT_N(VQSHRUNT, vqshrunt)
--
++DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
--    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
++DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
--        !dc_isar_feature(aa32_sha1, s)) {
++DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
--        return false;
++DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
-+#define DO_SHA1(NAME, FUNC)                                             \
++DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
-+    WRAP_OOL_FN(gen_##NAME##_3s, FUNC)                                  \
++DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
 +    static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a)        \
 +    {                                                                   \
 +        if (!dc_isar_feature(aa32_sha1, s)) {                           \
 +            return false;                                               \
 +        }                                                               \
 +        return do_3same(s, a, gen_##NAME##_3s);                         \
      }
 -    /* UNDEF accesses to D16-D31 if they don't exist. */
 -    if (!dc_isar_feature(aa32_simd_r32, s) &&
 -        ((a->vd | a->vn | a->vm) & 0x10)) {
 -        return false;
 -    }
 -
 -    if ((a->vn | a->vm | a->vd) & 1) {
 -        return false;
 -    }
 -
 -    if (!vfp_access_check(s)) {
 -        return true;
 -    }
 -
 -    ptr1 = vfp_reg_ptr(true, a->vd);
 -    ptr2 = vfp_reg_ptr(true, a->vn);
 -    ptr3 = vfp_reg_ptr(true, a->vm);
 -    tmp = tcg_const_i32(a->optype);
 -    gen_helper_crypto_sha1_3reg(ptr1, ptr2, ptr3, tmp);
 -    tcg_temp_free_i32(tmp);
 -    tcg_temp_free_ptr(ptr1);
 -    tcg_temp_free_ptr(ptr2);
 -    tcg_temp_free_ptr(ptr3);
 -
 -    return true;
 -}
 +DO_SHA1(SHA1C, gen_helper_crypto_sha1c)
 +DO_SHA1(SHA1P, gen_helper_crypto_sha1p)
 +DO_SHA1(SHA1M, gen_helper_crypto_sha1m)
 +DO_SHA1(SHA1SU0, gen_helper_crypto_sha1su0)
  #define DO_SHA2(NAME, FUNC)                                             \
      WRAP_OOL_FN(gen_##NAME##_3s, FUNC)                                  \
 --
 .20.1

-[PULL 21/29] target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree
+[PULL 19/24] target/arm: Implement MVE VSHLC
-Convert the VSHL and VSLI insns from the Neon 2-registers-and-a-shift
+Implement the MVE VSHLC insn, which performs a shift left of the
-group to decodetree.
+entire vector with carry in bits provided from a general purpose
 register and carry out bits written back to that register.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200522145520.6778-2-peter.maydell@linaro.org
+Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       | 25 ++++++++++++++++++++++
+ target/arm/helper-mve.h    |  2 ++
- target/arm/translate-neon.inc.c | 38 +++++++++++++++++++++++++++++++++
+ target/arm/mve.decode      |  2 ++
- target/arm/translate.c          | 18 +++++++---------
+ target/arm/mve_helper.c    | 38 ++++++++++++++++++++++++++++++++++++++
-files changed, 71 insertions(+), 10 deletions(-)
+ target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
 files changed, 72 insertions(+)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
+--- a/target/arm/helper-mve.h
-+++ b/target/arm/neon-dp.decode
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ VRECPS_fp_3s     1111 001 0 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- VRSQRTS_fp_3s    1111 001 0 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
+ DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- VMAXNM_fp_3s     1111 001 1 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
+ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
+ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
-+######################################################################
++DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
-+# 2-reg-and-shift grouping:
+diff --git a/target/arm/mve.decode b/target/arm/mve.decode
-+# 1111 001 U 1 D immH:3 immL:3 Vd:4 opc:4 L Q M 1 Vm:4
+index XXXXXXX..XXXXXXX 100644
-+######################################################################
+--- a/target/arm/mve.decode
-+&2reg_shift vm vd q shift size
++++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
  VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
  VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
  VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
 +
-+@2reg_shl_d      .... ... . . . shift:6      .... .... 1 q:1 . . .... \
++VSHLC             111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
-+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=3
+diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-+@2reg_shl_s      .... ... . . . 1 shift:5    .... .... 0 q:1 . . .... \
+index XXXXXXX..XXXXXXX 100644
-+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2
+--- a/target/arm/mve_helper.c
-+@2reg_shl_h      .... ... . . . 01 shift:4   .... .... 0 q:1 . . .... \
++++ b/target/arm/mve_helper.c
-+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1
+@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
-+@2reg_shl_b      .... ... . . . 001 shift:3  .... .... 0 q:1 . . .... \
+ DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
-+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0
+ DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
  DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
 +
-+VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
++uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
-+VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
++                           uint32_t shift)
-+VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
++{
-+VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
++    uint32_t *d = vd;
 +    uint16_t mask = mve_element_mask(env);
 +    unsigned e;
 +    uint32_t r;
 +
-+VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
++    /*
-+VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
++     * For each 32-bit element, we shift it left, bringing in the
-+VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
++     * low 'shift' bits of rdm at the bottom. Bits shifted out at
-+VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
++     * the top become the new rdm, if the predicate mask permits.
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
++     * The final rdm value is returned to update the register.
 +     * shift == 0 here means "shift by 32 bits".
 +     */
 +    if (shift == 0) {
 +        for (e = 0; e < 16 / 4; e++, mask >>= 4) {
 +            r = rdm;
 +            if (mask & 1) {
 +                rdm = d[H4(e)];
 +            }
 +            mergemask(&d[H4(e)], r, mask);
 +        }
 +    } else {
 +        uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
 +
 +        for (e = 0; e < 16 / 4; e++, mask >>= 4) {
 +            r = (d[H4(e)] << shift) | (rdm & shiftmask);
 +            if (mask & 1) {
 +                rdm = d[H4(e)] >> (32 - shift);
 +            }
 +            mergemask(&d[H4(e)], r, mask);
 +        }
 +    }
 +    mve_advance_vpt(env);
 +    return rdm;
 +}
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
+--- a/target/arm/translate-mve.c
-+++ b/target/arm/translate-neon.inc.c
++++ b/target/arm/translate-mve.c
-@@ -XXX,XX +XXX,XX @@ static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn)
+@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
- DO_3S_FP_PAIR(VPADD, gen_helper_vfp_adds)
+ DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
- DO_3S_FP_PAIR(VPMAX, gen_helper_vfp_maxs)
+ DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
- DO_3S_FP_PAIR(VPMIN, gen_helper_vfp_mins)
+ DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
 +
-+static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
++static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
 +{
-+    /* Handle a 2-reg-shift insn which can be vectorized. */
++    /*
-+    int vec_size = a->q ? 16 : 8;
++     * Whole Vector Left Shift with Carry. The carry is taken
-+    int rd_ofs = neon_reg_offset(a->vd, 0);
++     * from a general purpose register and written back there.
-+    int rm_ofs = neon_reg_offset(a->vm, 0);
++     * An imm of 0 means "shift by 32".
 +     */
 +    TCGv_ptr qd;
 +    TCGv_i32 rdm;
 +
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
++    if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
 +        return false;
 +    }
-+
++    if (a->rdm == 13 || a->rdm == 15) {
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
++        /* CONSTRAINED UNPREDICTABLE: we UNDEF */
 +    if (!dc_isar_feature(aa32_simd_r32, s) &&
 +        ((a->vd | a->vm) & 0x10)) {
 +        return false;
 +    }
-+
++    if (!mve_eci_check(s) || !vfp_access_check(s)) {
 +    if ((a->vm | a->vd) & a->q) {
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
-+    fn(a->size, rd_ofs, rm_ofs, a->shift, vec_size, vec_size);
++    qd = mve_qreg_ptr(a->qd);
 +    rdm = load_reg(s, a->rdm);
 +    gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
 +    store_reg(s, a->rdm, rdm);
 +    tcg_temp_free_ptr(qd);
 +    mve_update_eci(s);
 +    return true;
 +}
-+
-+#define DO_2SH(INSN, FUNC)                                              \
-+    static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a)  \
-+    {                                                                   \
-+        return do_vector_2sh(s, a, FUNC);                               \
-+    }                                                                   \
-+
-+DO_2SH(VSHL, tcg_gen_gvec_shli)
-+DO_2SH(VSLI, gen_gvec_sli)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-         if ((insn & 0x00380080) != 0) {
-             /* Two registers and shift.  */
-             op = (insn >> 8) & 0xf;
-+
-+            switch (op) {
-+            case 5: /* VSHL, VSLI */
-+                return 1; /* handled by decodetree */
-+            default:
-+                break;
-+            }
-+
-             if (insn & (1 << 7)) {
-                 /* 64-bit shift. */
-                 if (op > 7) {
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                     gen_gvec_sri(size, rd_ofs, rm_ofs, shift,
-                                  vec_size, vec_size);
-                     return 0;
--
--                case 5: /* VSHL, VSLI */
--                    if (u) { /* VSLI */
--                        gen_gvec_sli(size, rd_ofs, rm_ofs, shift,
--                                     vec_size, vec_size);
--                    } else { /* VSHL */
--                        tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift,
--                                          vec_size, vec_size);
--                    }
--                    return 0;
-                 }
-                 if (size == 3) {
 --
 .20.1

-[PULL 24/29] target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree
+[PULL 20/24] target/arm: Implement MVE VADDLV
-Convert the VQSHLU and QVSHL 2-reg-shift insns to decodetree.
+Implement the MVE VADDLV insn; this is similar to VADDV, except
-These are the last of the simple shift-by-immediate insns.
+that it accumulates 32-bit elements into a 64-bit accumulator
 stored in a pair of general-purpose registers.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200522145520.6778-5-peter.maydell@linaro.org
+Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       |  15 +++++
+ target/arm/helper-mve.h    |  3 ++
- target/arm/translate-neon.inc.c | 108 +++++++++++++++++++++++++++++++
+ target/arm/mve.decode      |  6 +++-
- target/arm/translate.c          | 110 +-------------------------------
+ target/arm/mve_helper.c    | 19 ++++++++++++
-files changed, 126 insertions(+), 107 deletions(-)
+ target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
 files changed, 90 insertions(+), 1 deletion(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
+--- a/target/arm/helper-mve.h
-+++ b/target/arm/neon-dp.decode
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
- VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
+ DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
- VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
+ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
- VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
 +DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
 +DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
 +
-+VQSHLU_64_2sh    1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_d
+ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
-+VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_s
+ DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
-+VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_h
+ DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
-+VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_b
+diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar   1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
  VQRDMULH_scalar  1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
  # Vector add across vector
 -VADDV            111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
 +{
 +  VADDV          111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
 +  VADDLV         111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \
 +                 rdahi=%rdahi rdalo=%rdalo
 +}
  # Predicate operations
  %mask_22_13      22:1 13:3
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)
  DO_VADDV(vaddvuh, 2, uint16_t)
  DO_VADDV(vaddvuw, 4, uint32_t)
 +#define DO_VADDLV(OP, TYPE, LTYPE)                              \
 +    uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
 +                                    uint64_t ra)                \
 +    {                                                           \
 +        uint16_t mask = mve_element_mask(env);                  \
 +        unsigned e;                                             \
 +        TYPE *m = vm;                                           \
 +        for (e = 0; e < 16 / 4; e++, mask >>= 4) {              \
 +            if (mask & 1) {                                     \
 +                ra += (LTYPE)m[H4(e)];                          \
 +            }                                                   \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +        return ra;                                              \
 +    }                                                           \
 +
-+VQSHL_S_64_2sh   1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
++DO_VADDLV(vaddlv_s, int32_t, int64_t)
-+VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
++DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
 +VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
 +VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
 +
-+VQSHL_U_64_2sh   1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
+ /* Shifts by immediate */
-+VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
+ #define DO_2SHIFT(OP, ESIZE, TYPE, FN)                          \
-+VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
+     void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
-+VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
+--- a/target/arm/translate-mve.c
-+++ b/target/arm/translate-neon.inc.c
++++ b/target/arm/translate-mve.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a)
+@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
-         return do_vector_2sh(s, a, tcg_gen_gvec_shri);
+     return true;
      }
  }
-+
-+static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a,
++static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
 +                             NeonGenTwo64OpEnvFn *fn)
 +{
 +    /*
-+     * 2-reg-and-shift operations, size == 3 case, where the
++     * Vector Add Long Across Vector: accumulate the 32-bit
-+     * function needs to be passed cpu_env.
++     * elements of the vector into a 64-bit result stored in
 +     * a pair of general-purpose registers.
 +     * No need to check Qm's bank: it is only 3 bits in decode.
 +     */
-+    TCGv_i64 constimm;
++    TCGv_ptr qm;
-+    int pass;
++    TCGv_i64 rda;
 +    TCGv_i32 rdalo, rdahi;
 +
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
++    if (!dc_isar_feature(aa32_mve, s)) {
 +        return false;
 +    }
-+
++    /*
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
++     * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
++     * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
-+        ((a->vd | a->vm) & 0x10)) {
++     */
 +    if (a->rdahi == 13 || a->rdahi == 15) {
 +        return false;
 +    }
-+
++    if (!mve_eci_check(s) || !vfp_access_check(s)) {
 +    if ((a->vm | a->vd) & a->q) {
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    /*
-+     * To avoid excessive duplication of ops we implement shift
++     * This insn is subject to beat-wise execution. Partial execution
-+     * by immediate using the variable shift operations.
++     * of an A=0 (no-accumulate) insn which does not execute the first
 +     * beat must start with the current value of RdaHi:RdaLo, not zero.
 +     */
-+    constimm = tcg_const_i64(dup_const(a->size, a->shift));
++    if (a->a || mve_skip_first_beat(s)) {
 +        /* Accumulate input from RdaHi:RdaLo */
 +        rda = tcg_temp_new_i64();
 +        rdalo = load_reg(s, a->rdalo);
 +        rdahi = load_reg(s, a->rdahi);
 +        tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
 +        tcg_temp_free_i32(rdalo);
 +        tcg_temp_free_i32(rdahi);
 +    } else {
 +        /* Accumulate starting at zero */
 +        rda = tcg_const_i64(0);
 +    }
 +
-+    for (pass = 0; pass < a->q + 1; pass++) {
++    qm = mve_qreg_ptr(a->qm);
-+        TCGv_i64 tmp = tcg_temp_new_i64();
++    if (a->u) {
 +        gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
 +    } else {
 +        gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
 +    }
 +    tcg_temp_free_ptr(qm);
 +
-+        neon_load_reg64(tmp, a->vm + pass);
++    rdalo = tcg_temp_new_i32();
-+        fn(tmp, cpu_env, tmp, constimm);
++    rdahi = tcg_temp_new_i32();
-+        neon_store_reg64(tmp, a->vd + pass);
++    tcg_gen_extrl_i64_i32(rdalo, rda);
-+    }
++    tcg_gen_extrh_i64_i32(rdahi, rda);
-+    tcg_temp_free_i64(constimm);
++    store_reg(s, a->rdalo, rdalo);
 +    store_reg(s, a->rdahi, rdahi);
 +    tcg_temp_free_i64(rda);
 +    mve_update_eci(s);
 +    return true;
 +}
 +
-+static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
+ static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
 +                             NeonGenTwoOpEnvFn *fn)
 +{
 +    /*
 +     * 2-reg-and-shift operations, size < 3 case, where the
 +     * helper needs to be passed cpu_env.
 +     */
 +    TCGv_i32 constimm;
 +    int pass;
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
 +        return false;
 +    }
 +
 +    /* UNDEF accesses to D16-D31 if they don't exist. */
 +    if (!dc_isar_feature(aa32_simd_r32, s) &&
 +        ((a->vd | a->vm) & 0x10)) {
 +        return false;
 +    }
 +
 +    if ((a->vm | a->vd) & a->q) {
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    /*
 +     * To avoid excessive duplication of ops we implement shift
 +     * by immediate using the variable shift operations.
 +     */
 +    constimm = tcg_const_i32(dup_const(a->size, a->shift));
 +
 +    for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
 +        TCGv_i32 tmp = neon_load_reg(a->vm, pass);
 +        fn(tmp, cpu_env, tmp, constimm);
 +        neon_store_reg(a->vd, pass, tmp);
 +    }
 +    tcg_temp_free_i32(constimm);
 +    return true;
 +}
 +
 +#define DO_2SHIFT_ENV(INSN, FUNC)                                       \
 +    static bool trans_##INSN##_64_2sh(DisasContext *s, arg_2reg_shift *a) \
 +    {                                                                   \
 +        return do_2shift_env_64(s, a, gen_helper_neon_##FUNC##64);      \
 +    }                                                                   \
 +    static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a)  \
 +    {                                                                   \
 +        static NeonGenTwoOpEnvFn * const fns[] = {                      \
 +            gen_helper_neon_##FUNC##8,                                  \
 +            gen_helper_neon_##FUNC##16,                                 \
 +            gen_helper_neon_##FUNC##32,                                 \
 +        };                                                              \
 +        assert(a->size < ARRAY_SIZE(fns));                              \
 +        return do_2shift_env_32(s, a, fns[a->size]);                    \
 +    }
 +
 +DO_2SHIFT_ENV(VQSHLU, qshlu_s)
 +DO_2SHIFT_ENV(VQSHL_U, qshl_u)
 +DO_2SHIFT_ENV(VQSHL_S, qshl_s)
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_neon_rsb(int size, TCGv_i32 t0, TCGv_i32 t1)
      }
  }
 -#define GEN_NEON_INTEGER_OP_ENV(name) do { \
 -    switch ((size << 1) | u) { \
 -    case 0: \
 -        gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
 -        break; \
 -    case 1: \
 -        gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
 -        break; \
 -    case 2: \
 -        gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
 -        break; \
 -    case 3: \
 -        gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
 -        break; \
 -    case 4: \
 -        gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
 -        break; \
 -    case 5: \
 -        gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
 -        break; \
 -    default: return 1; \
 -    }} while (0)
 -
  static TCGv_i32 neon_load_scratch(int scratch)
  {
-     TCGv_i32 tmp = tcg_temp_new_i32();
+     TCGv_ptr qd;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
      int size;
      int shift;
      int pass;
 -    int count;
      int u;
      int vec_size;
      uint32_t imm;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
              case 3: /* VRSRA */
              case 4: /* VSRI */
              case 5: /* VSHL, VSLI */
 +            case 6: /* VQSHLU */
 +            case 7: /* VQSHL */
                  return 1; /* handled by decodetree */
              default:
                  break;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                      size--;
              }
              shift = (insn >> 16) & ((1 << (3 + size)) - 1);
 -            if (op < 8) {
 -                /* Shift by immediate:
 -                   VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU.  */
 -                if (q && ((rd | rm) & 1)) {
 -                    return 1;
 -                }
 -                if (!u && (op == 4 || op == 6)) {
 -                    return 1;
 -                }
 -                /* Right shifts are encoded as N - shift, where N is the
 -                   element size in bits.  */
 -                if (op <= 4) {
 -                    shift = shift - (1 << (size + 3));
 -                }
 -
 -                if (size == 3) {
 -                    count = q + 1;
 -                } else {
 -                    count = q ? 4: 2;
 -                }
 -
 -                /* To avoid excessive duplication of ops we implement shift
 -                 * by immediate using the variable shift operations.
 -                  */
 -                imm = dup_const(size, shift);
 -
 -                for (pass = 0; pass < count; pass++) {
 -                    if (size == 3) {
 -                        neon_load_reg64(cpu_V0, rm + pass);
 -                        tcg_gen_movi_i64(cpu_V1, imm);
 -                        switch (op) {
 -                        case 6: /* VQSHLU */
 -                            gen_helper_neon_qshlu_s64(cpu_V0, cpu_env,
 -                                                      cpu_V0, cpu_V1);
 -                            break;
 -                        case 7: /* VQSHL */
 -                            if (u) {
 -                                gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
 -                                                         cpu_V0, cpu_V1);
 -                            } else {
 -                                gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
 -                                                         cpu_V0, cpu_V1);
 -                            }
 -                            break;
 -                        default:
 -                            g_assert_not_reached();
 -                        }
 -                        neon_store_reg64(cpu_V0, rd + pass);
 -                    } else { /* size < 3 */
 -                        /* Operands in T0 and T1.  */
 -                        tmp = neon_load_reg(rm, pass);
 -                        tmp2 = tcg_temp_new_i32();
 -                        tcg_gen_movi_i32(tmp2, imm);
 -                        switch (op) {
 -                        case 6: /* VQSHLU */
 -                            switch (size) {
 -                            case 0:
 -                                gen_helper_neon_qshlu_s8(tmp, cpu_env,
 -                                                         tmp, tmp2);
 -                                break;
 -                            case 1:
 -                                gen_helper_neon_qshlu_s16(tmp, cpu_env,
 -                                                          tmp, tmp2);
 -                                break;
 -                            case 2:
 -                                gen_helper_neon_qshlu_s32(tmp, cpu_env,
 -                                                          tmp, tmp2);
 -                                break;
 -                            default:
 -                                abort();
 -                            }
 -                            break;
 -                        case 7: /* VQSHL */
 -                            GEN_NEON_INTEGER_OP_ENV(qshl);
 -                            break;
 -                        default:
 -                            g_assert_not_reached();
 -                        }
 -                        tcg_temp_free_i32(tmp2);
 -                        neon_store_reg(rd, pass, tmp);
 -                    }
 -                } /* for pass */
 -            } else if (op < 10) {
 +            if (op < 10) {
                  /* Shift by immediate and narrow:
                     VSHRN, VRSHRN, VQSHRN, VQRSHRN.  */
                  int input_unsigned = (op == 8) ? !u : u;
 --
 .20.1

-[PULL 23/29] target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree
+[PULL 21/24] target/arm: Implement MVE long shifts by immediate
-Convert the VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree.
+The MVE extension to v8.1M includes some new shift instructions which
-(These are the last instructions in the group that are vectorized;
+sit entirely within the non-coprocessor part of the encoding space
-the rest all require looping over each element.)
+and which operate only on general-purpose registers.  They take up
 the space which was previously UNPREDICTABLE MOVS and ORRS encodings
 with Rm == 13 or 15.
 Implement the long shifts by immediate, which perform shifts on a
 pair of general-purpose registers treated as a 64-bit quantity, with
 an immediate shift count between 1 and 32.
 Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
 the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
 cases where v8.1M now requires that.  (Trying to change MOVS and ORRS
 is too difficult, because the functions that generate the code are
 shared between a dozen different kinds of arithmetic or logical
 instruction for all A32, T16 and T32 encodings, and for some insns
 and some encodings Rm==13,15 are valid.)
 We make the helper functions we need for UQSHLL and SQSHLL take
 a 32-bit value which the helper casts to int8_t because we'll need
 these helpers also for the shift-by-register insns, where the shift
 count might be < 0 or > 32.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200522145520.6778-4-peter.maydell@linaro.org
+Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       | 35 ++++++++++++++++++++++
+ target/arm/helper-mve.h |  3 ++
- target/arm/translate-neon.inc.c |  7 +++++
+ target/arm/translate.h  |  1 +
- target/arm/translate.c          | 52 +++------------------------------
+ target/arm/t32.decode   | 28 +++++++++++++
-files changed, 46 insertions(+), 48 deletions(-)
+ target/arm/mve_helper.c | 10 +++++
+ target/arm/translate.c  | 90 +++++++++++++++++++++++++++++++++++++++++
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
+files changed, 132 insertions(+)
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
-+++ b/target/arm/neon-dp.decode
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
+--- a/target/arm/helper-mve.h
- VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
++++ b/target/arm/helper-mve.h
- VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
-+VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
+ DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
-+VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
++
-+VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
++DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+
++DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
+diff --git a/target/arm/translate.h b/target/arm/translate.h
-+VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
+index XXXXXXX..XXXXXXX 100644
-+VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
+--- a/target/arm/translate.h
-+VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
++++ b/target/arm/translate.h
-+
+@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
-+VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
+ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
-+VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
+ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
-+VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
+ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
-+VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
++typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
-+
-+VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
+ /**
-+VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
+  * arm_tbflags_from_tb:
-+VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
+diff --git a/target/arm/t32.decode b/target/arm/t32.decode
-+VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
+index XXXXXXX..XXXXXXX 100644
-+
+--- a/target/arm/t32.decode
-+VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
++++ b/target/arm/t32.decode
-+VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
+@@ -XXX,XX +XXX,XX @@
-+VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
+ &mcr             !extern cp opc1 crn crm opc2 rt
-+VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
+ &mcrr            !extern cp opc1 crm rt rt2
-+
-+VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
++&mve_shl_ri      rdalo rdahi shim
-+VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
++
-+VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
++# rdahi: bits [3:1] from insn, bit 0 is 1
-+VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
++# rdalo: bits [3:1] from insn, bit 0 is 0
-+
++%rdahi_9 9:3 !function=times_2_plus_1
-+VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_d
++%rdalo_17 17:3 !function=times_2
-+VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_s
++
-+VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_h
+ # Data-processing (register)
-+VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_b
-+
+ %imm5_12_6       12:3 6:2
- VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
+@@ -XXX,XX +XXX,XX @@
- VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
+ @S_xrr_shi       ....... .... .   rn:4 .... .... .. shty:2 rm:4 \
- VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
+                  &s_rrr_shi shim=%imm5_12_6 s=1 rd=0
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
++@mve_shl_ri      ....... .... . ... . . ... ... . .. .. .... \
---- a/target/arm/translate-neon.inc.c
++                 &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
-+++ b/target/arm/translate-neon.inc.c
++
@@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
  DO_2SH(VSHL, tcg_gen_gvec_shli)
  DO_2SH(VSLI, gen_gvec_sli)
 +DO_2SH(VSRI, gen_gvec_sri)
 +DO_2SH(VSRA_S, gen_gvec_ssra)
 +DO_2SH(VSRA_U, gen_gvec_usra)
 +DO_2SH(VRSHR_S, gen_gvec_srshr)
 +DO_2SH(VRSHR_U, gen_gvec_urshr)
 +DO_2SH(VRSRA_S, gen_gvec_srsra)
 +DO_2SH(VRSRA_U, gen_gvec_ursra)
  static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a)
  {
+   TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
+   AND_rrri       1110101 0000 . .... 0 ... .... .... ....     @s_rrr_shi
+ }
+ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
+ {
++  # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
++  # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
++  # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that
++  # they explicitly call unallocated_encoding() for cases that must UNDEF
++  # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
++  # the rest fall through (where ORR_rrri and MOV_rxri will end up
++  # handling them as r13 and r15 accesses with the same semantics as A32).
++  [
++    LSLL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111  @mve_shl_ri
++    LSRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111  @mve_shl_ri
++    ASRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111  @mve_shl_ri
++
++    UQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111  @mve_shl_ri
++    URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
++    SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
++    SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
++  ]
++
+   MOV_rxri       1110101 0010 . 1111 0 ... .... .... ....     @s_rxr_shi
+   ORR_rrri       1110101 0010 . .... 0 ... .... .... ....     @s_rrr_shi
+ }
+diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/mve_helper.c
++++ b/target/arm/mve_helper.c
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
+     mve_advance_vpt(env);
+     return rdm;
+ }
++
++uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
++{
++    return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
++}
++
++uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
++{
++    return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
++}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
+     return true;
-             switch (op) {
+ }
-             case 0: /* VSHR */
-+            case 1: /* VSRA */
++/*
-+            case 2: /* VRSHR */
++ * v8.1M MVE wide-shifts
-+            case 3: /* VRSRA */
++ */
-+            case 4: /* VSRI */
++static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,
-             case 5: /* VSHL, VSLI */
++                          WideShiftImmFn *fn)
-                 return 1; /* handled by decodetree */
++{
-             default:
++    TCGv_i64 rda;
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
++    TCGv_i32 rdalo, rdahi;
-                     shift = shift - (1 << (size + 3));
++
-                 }
++    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
++        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
--                switch (op) {
++        return false;
--                case 1:  /* VSRA */
++    }
--                    /* Right shift comes here negative.  */
++    if (a->rdahi == 15) {
--                    shift = -shift;
++        /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
--                    if (u) {
++        return false;
--                        gen_gvec_usra(size, rd_ofs, rm_ofs, shift,
++    }
--                                      vec_size, vec_size);
++    if (!dc_isar_feature(aa32_mve, s) ||
--                    } else {
++        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
--                        gen_gvec_ssra(size, rd_ofs, rm_ofs, shift,
++        a->rdahi == 13) {
--                                      vec_size, vec_size);
++        /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */
--                    }
++        unallocated_encoding(s);
--                    return 0;
++        return true;
--
++    }
--                case 2: /* VRSHR */
++
--                    /* Right shift comes here negative.  */
++    if (a->shim == 0) {
--                    shift = -shift;
++        a->shim = 32;
--                    if (u) {
++    }
--                        gen_gvec_urshr(size, rd_ofs, rm_ofs, shift,
++
--                                       vec_size, vec_size);
++    rda = tcg_temp_new_i64();
--                    } else {
++    rdalo = load_reg(s, a->rdalo);
--                        gen_gvec_srshr(size, rd_ofs, rm_ofs, shift,
++    rdahi = load_reg(s, a->rdahi);
--                                       vec_size, vec_size);
++    tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
--                    }
++
--                    return 0;
++    fn(rda, rda, a->shim);
--
++
--                case 3: /* VRSRA */
++    tcg_gen_extrl_i64_i32(rdalo, rda);
--                    /* Right shift comes here negative.  */
++    tcg_gen_extrh_i64_i32(rdahi, rda);
--                    shift = -shift;
++    store_reg(s, a->rdalo, rdalo);
--                    if (u) {
++    store_reg(s, a->rdahi, rdahi);
--                        gen_gvec_ursra(size, rd_ofs, rm_ofs, shift,
++    tcg_temp_free_i64(rda);
--                                       vec_size, vec_size);
++
--                    } else {
++    return true;
--                        gen_gvec_srsra(size, rd_ofs, rm_ofs, shift,
++}
--                                       vec_size, vec_size);
++
--                    }
++static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)
--                    return 0;
++{
--
++    return do_mve_shl_ri(s, a, tcg_gen_sari_i64);
--                case 4: /* VSRI */
++}
--                    if (!u) {
++
--                        return 1;
++static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)
--                    }
++{
--                    /* Right shift comes here negative.  */
++    return do_mve_shl_ri(s, a, tcg_gen_shli_i64);
--                    shift = -shift;
++}
--                    gen_gvec_sri(size, rd_ofs, rm_ofs, shift,
++
--                                 vec_size, vec_size);
++static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
--                    return 0;
++{
--                }
++    return do_mve_shl_ri(s, a, tcg_gen_shri_i64);
--
++}
-                 if (size == 3) {
++
-                     count = q + 1;
++static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
-                 } else {
++{
 +    gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_mve_sqshll);
 +}
 +
 +static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
 +{
 +    gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_mve_uqshll);
 +}
 +
 +static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_srshr64_i64);
 +}
 +
 +static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_urshr64_i64);
 +}
 +
  /*
   * Multiply and multiply accumulate
   */
 --
 .20.1

-[PULL 05/29] target/arm: Convert aes and sm4 to gvec helpers
+[PULL 22/24] target/arm: Implement MVE long shifts by register
-From: Richard Henderson <richard.henderson@linaro.org>
+Implement the MVE long shifts by register, which perform shifts on a
+pair of general-purpose registers treated as a 64-bit quantity, with
-With this conversion, we will be able to use the same helpers
+the shift count in another general-purpose register, which might be
-with sve.  In particular, pass 3 vector parameters for the
+either positive or negative.
--operand operations; for advsimd the destination register
-is also an input.
+Like the long-shifts-by-immediate, these encodings sit in the space
+that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
-This also fixes a bug in which we failed to clear the high bits
+Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
-of the SVE register after an AdvSIMD operation.
+also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
+we have to move the CSEL pattern into the same decodetree group.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20200514212831.31248-2-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
 ---
- target/arm/helper.h        |  6 ++--
+ target/arm/helper-mve.h |  6 +++
- target/arm/vec_internal.h  | 33 +++++++++++++++++
+ target/arm/translate.h  |  1 +
- target/arm/crypto_helper.c | 72 +++++++++++++++++++++++++++-----------
+ target/arm/t32.decode   | 16 +++++--
- target/arm/translate-a64.c | 55 ++++++++++++++++++-----------
+ target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
- target/arm/translate.c     | 27 +++++++-------
+ target/arm/translate.c  | 69 ++++++++++++++++++++++++++++++
- target/arm/vec_helper.c    | 12 +------
+files changed, 182 insertions(+), 3 deletions(-)
-files changed, 138 insertions(+), 67 deletions(-)
- create mode 100644 target/arm/vec_internal.h
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+index XXXXXXX..XXXXXXX 100644
-diff --git a/target/arm/helper.h b/target/arm/helper.h
+--- a/target/arm/helper-mve.h
-index XXXXXXX..XXXXXXX 100644
++++ b/target/arm/helper-mve.h
---- a/target/arm/helper.h
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+++ b/target/arm/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(neon_qzip8, TCG_CALL_NO_RWG, void, ptr, ptr)
+ DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
- DEF_HELPER_FLAGS_2(neon_qzip16, TCG_CALL_NO_RWG, void, ptr, ptr)
- DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr)
++DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
++DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
--DEF_HELPER_FLAGS_3(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+ DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+ DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
- DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
++DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
++DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
- DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
++DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32, i32)
++DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
- DEF_HELPER_FLAGS_3(crypto_sm3partw1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
+diff --git a/target/arm/translate.h b/target/arm/translate.h
- DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.h
--DEF_HELPER_FLAGS_2(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr)
++++ b/target/arm/translate.h
--DEF_HELPER_FLAGS_3(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
+@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
-+DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
-+DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
+ typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
- DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
++typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
- DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
-diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h
+ /**
-new file mode 100644
+  * arm_tbflags_from_tb:
-index XXXXXXX..XXXXXXX
+diff --git a/target/arm/t32.decode b/target/arm/t32.decode
---- /dev/null
+index XXXXXXX..XXXXXXX 100644
-+++ b/target/arm/vec_internal.h
+--- a/target/arm/t32.decode
 +++ b/target/arm/t32.decode
 @@ -XXX,XX +XXX,XX @@
-+/*
+ &mcrr            !extern cp opc1 crm rt rt2
-+ * ARM AdvSIMD / SVE Vector Helpers
-+ *
+ &mve_shl_ri      rdalo rdahi shim
-+ * Copyright (c) 2020 Linaro
++&mve_shl_rr      rdalo rdahi rm
-+ *
-+ * This library is free software; you can redistribute it and/or
+ # rdahi: bits [3:1] from insn, bit 0 is 1
-+ * modify it under the terms of the GNU Lesser General Public
+ # rdalo: bits [3:1] from insn, bit 0 is 0
 + * License as published by the Free Software Foundation; either
 + * version 2 of the License, or (at your option) any later version.
 + *
 + * This library is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 + * Lesser General Public License for more details.
 + *
 + * You should have received a copy of the GNU Lesser General Public
 + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#ifndef TARGET_ARM_VEC_INTERNALS_H
 +#define TARGET_ARM_VEC_INTERNALS_H
 +
 +static inline void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
 +{
 +    uint64_t *d = vd + opr_sz;
 +    uintptr_t i;
 +
 +    for (i = opr_sz; i < max_sz; i += 8) {
 +        *d++ = 0;
 +    }
 +}
 +
 +#endif /* TARGET_ARM_VEC_INTERNALS_H */
 diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/crypto_helper.c
 +++ b/target/arm/crypto_helper.c
 @@ -XXX,XX +XXX,XX @@
- #include "cpu.h"
+ @mve_shl_ri      ....... .... . ... . . ... ... . .. .. .... \
- #include "exec/helper-proto.h"
+                  &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
-+#include "tcg/tcg-gvec-desc.h"
++@mve_shl_rr      ....... .... . ... . rm:4  ... . .. .. .... \
- #include "crypto/aes.h"
++                 &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
-+#include "vec_internal.h"
+ {
- union CRYPTO_STATE {
+   TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
-     uint8_t    bytes[16];
+@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
-@@ -XXX,XX +XXX,XX @@ union CRYPTO_STATE {
+     URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
- #define CR_ST_WORD(state, i)   (state.words[i])
+     SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
- #endif
+     SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
++
--void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt)
++    LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
-+static void do_crypto_aese(uint64_t *rd, uint64_t *rn,
++    ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
-+                           uint64_t *rm, bool decrypt)
++    UQRSHLL64_rr 1110101 0010 1 ... 1 ....  ... 1  0000 1101  @mve_shl_rr
- {
++    SQRSHRL64_rr 1110101 0010 1 ... 1 ....  ... 1  0010 1101  @mve_shl_rr
-     static uint8_t const * const sbox[2] = { AES_sbox, AES_isbox };
++    UQRSHLL48_rr 1110101 0010 1 ... 1 ....  ... 1  1000 1101  @mve_shl_rr
-     static uint8_t const * const shift[2] = { AES_shifts, AES_ishifts };
++    SQRSHRL48_rr 1110101 0010 1 ... 1 ....  ... 1  1010 1101  @mve_shl_rr
--    uint64_t *rd = vd;
+   ]
--    uint64_t *rm = vm;
-     union CRYPTO_STATE rk = { .l = { rm[0], rm[1] } };
+   MOV_rxri       1110101 0010 . 1111 0 ... .... .... ....     @s_rxr_shi
--    union CRYPTO_STATE st = { .l = { rd[0], rd[1] } };
+   ORR_rrri       1110101 0010 . .... 0 ... .... .... ....     @s_rrr_shi
-+    union CRYPTO_STATE st = { .l = { rn[0], rn[1] } };
++
-     int i;
++  # v8.1M CSEL and friends
++  CSEL           1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
--    assert(decrypt < 2);
+ }
  {
    MVN_rxri       1110101 0011 . 1111 0 ... .... .... ....     @s_rxr_shi
@@ -XXX,XX +XXX,XX @@ SBC_rrri         1110101 1011 . .... 0 ... .... .... ....     @s_rrr_shi
  }
  RSB_rrri         1110101 1110 . .... 0 ... .... .... ....     @s_rrr_shi
 -# v8.1M CSEL and friends
 -CSEL             1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
 -
-     /* xor state vector with round key */
+ # Data-processing (register-shifted register)
-     rk.l[0] ^= st.l[0];
-     rk.l[1] ^= st.l[1];
+ MOV_rxrr         1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
-@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt)
+diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-     rd[1] = st.l[1];
+index XXXXXXX..XXXXXXX 100644
- }
+--- a/target/arm/mve_helper.c
++++ b/target/arm/mve_helper.c
--void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
-+void HELPER(crypto_aese)(void *vd, void *vn, void *vm, uint32_t desc)
+     return rdm;
-+{
+ }
-+    intptr_t i, opr_sz = simd_oprsz(desc);
-+    bool decrypt = simd_data(desc);
++uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
-+
++{
-+    for (i = 0; i < opr_sz; i += 16) {
++    return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
-+        do_crypto_aese(vd + i, vn + i, vm + i, decrypt);
++}
-+    }
++
-+    clear_tail(vd, opr_sz, simd_maxsz(desc));
++uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
-+}
++{
-+
++    return do_uqrshl_d(n, (int8_t)shift, false, NULL);
-+static void do_crypto_aesmc(uint64_t *rd, uint64_t *rm, bool decrypt)
++}
- {
++
-     static uint32_t const mc[][256] = { {
+ uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
-         /* MixColumns lookup table */
+ {
-@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)
+     return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
-xbe805d9f, 0xb58d5491, 0xa89a4f83, 0xa397468d,
+@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
-     } };
+ {
+     return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
--    uint64_t *rd = vd;
+ }
--    uint64_t *rm = vm;
++
-     union CRYPTO_STATE st = { .l = { rm[0], rm[1] } };
++uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
-     int i;
++{
++    return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
--    assert(decrypt < 2);
++}
--
++
-     for (i = 0; i < 16; i += 4) {
++uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
-         CR_ST_WORD(st, i >> 2) =
++{
-             mc[decrypt][CR_ST_BYTE(st, i)] ^
++    return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
-@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)
++}
-     rd[1] = st.l[1];
++
- }
++/* Operate on 64-bit values, but saturate at 48 bits */
++static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
-+void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t desc)
++                                    bool round, uint32_t *sat)
 +{
-+    intptr_t i, opr_sz = simd_oprsz(desc);
++    if (shift <= -48) {
-+    bool decrypt = simd_data(desc);
++        /* Rounding the sign bit always produces 0. */
-+
++        if (round) {
-+    for (i = 0; i < opr_sz; i += 16) {
++            return 0;
-+        do_crypto_aesmc(vd + i, vm + i, decrypt);
++        }
-+    }
++        return src >> 63;
-+    clear_tail(vd, opr_sz, simd_maxsz(desc));
++    } else if (shift < 0) {
-+}
++        if (round) {
-+
++            src >>= -shift - 1;
- /*
++            return (src >> 1) + (src & 1);
-  * SHA-1 logical functions
++        }
-  */
++        return src >> -shift;
-@@ -XXX,XX +XXX,XX @@ static uint8_t const sm4_sbox[] = {
++    } else if (shift < 48) {
-x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
++        int64_t val = src << shift;
- };
++        int64_t extval = sextract64(val, 0, 48);
++        if (!sat || val == extval) {
--void HELPER(crypto_sm4e)(void *vd, void *vn)
++            return extval;
-+static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
++        }
- {
++    } else if (!sat || src == 0) {
--    uint64_t *rd = vd;
++        return 0;
--    uint64_t *rn = vn;
++    }
--    union CRYPTO_STATE d = { .l = { rd[0], rd[1] } };
++
--    union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };
++    *sat = 1;
-+    union CRYPTO_STATE d = { .l = { rn[0], rn[1] } };
++    return (1ULL << 47) - (src >= 0);
-+    union CRYPTO_STATE n = { .l = { rm[0], rm[1] } };
++}
-     uint32_t t, i;
++
++/* Operate on 64-bit values, but saturate at 48 bits */
-     for (i = 0; i < 4; i++) {
++static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
-@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4e)(void *vd, void *vn)
++                                     bool round, uint32_t *sat)
-     rd[1] = d.l[1];
++{
- }
++    uint64_t val, extval;
++
--void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm)
++    if (shift <= -(48 + round)) {
-+void HELPER(crypto_sm4e)(void *vd, void *vn, void *vm, uint32_t desc)
++        return 0;
-+{
++    } else if (shift < 0) {
-+    intptr_t i, opr_sz = simd_oprsz(desc);
++        if (round) {
-+
++            val = src >> (-shift - 1);
-+    for (i = 0; i < opr_sz; i += 16) {
++            val = (val >> 1) + (val & 1);
-+        do_crypto_sm4e(vd + i, vn + i, vm + i);
++        } else {
-+    }
++            val = src >> -shift;
-+    clear_tail(vd, opr_sz, simd_maxsz(desc));
++        }
-+}
++        extval = extract64(val, 0, 48);
-+
++        if (!sat || val == extval) {
-+static void do_crypto_sm4ekey(uint64_t *rd, uint64_t *rn, uint64_t *rm)
++            return extval;
- {
++        }
--    uint64_t *rd = vd;
++    } else if (shift < 48) {
--    uint64_t *rn = vn;
++        uint64_t val = src << shift;
--    uint64_t *rm = vm;
++        uint64_t extval = extract64(val, 0, 48);
-     union CRYPTO_STATE d;
++        if (!sat || val == extval) {
-     union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };
++            return extval;
-     union CRYPTO_STATE m = { .l = { rm[0], rm[1] } };
++        }
-@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm)
++    } else if (!sat || src == 0) {
-     rd[0] = d.l[0];
++        return 0;
-     rd[1] = d.l[1];
++    }
- }
++
-+
++    *sat = 1;
-+void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm, uint32_t desc)
++    return MAKE_64BIT_MASK(0, 48);
-+{
++}
-+    intptr_t i, opr_sz = simd_oprsz(desc);
++
-+
++uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
-+    for (i = 0; i < opr_sz; i += 16) {
++{
-+        do_crypto_sm4ekey(vd + i, vn + i, vm + i);
++    return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
-+    }
++}
-+    clear_tail(vd, opr_sz, simd_maxsz(desc));
++
-+}
++uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
++{
-index XXXXXXX..XXXXXXX 100644
++    return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
---- a/target/arm/translate-a64.c
++}
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void gen_gvec_fn4(DisasContext *s, bool is_q, int rd, int rn, int rm,
              is_q ? 16 : 8, vec_full_reg_size(s));
  }
 +/* Expand a 2-operand operation using an out-of-line helper.  */
 +static void gen_gvec_op2_ool(DisasContext *s, bool is_q, int rd,
 +                             int rn, int data, gen_helper_gvec_2 *fn)
 +{
 +    tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
 +                       vec_full_reg_offset(s, rn),
 +                       is_q ? 16 : 8, vec_full_reg_size(s), data, fn);
 +}
 +
  /* Expand a 3-operand operation using an out-of-line helper.  */
  static void gen_gvec_op3_ool(DisasContext *s, bool is_q, int rd,
                               int rn, int rm, int data, gen_helper_gvec_3 *fn)
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
      int rn = extract32(insn, 5, 5);
      int rd = extract32(insn, 0, 5);
      int decrypt;
 -    TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
 -    TCGv_i32 tcg_decrypt;
 -    CryptoThreeOpIntFn *genfn;
 +    gen_helper_gvec_2 *genfn2 = NULL;
 +    gen_helper_gvec_3 *genfn3 = NULL;
      if (!dc_isar_feature(aa64_aes, s) || size != 0) {
          unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
      switch (opcode) {
      case 0x4: /* AESE */
          decrypt = 0;
 -        genfn = gen_helper_crypto_aese;
 +        genfn3 = gen_helper_crypto_aese;
          break;
      case 0x6: /* AESMC */
          decrypt = 0;
 -        genfn = gen_helper_crypto_aesmc;
 +        genfn2 = gen_helper_crypto_aesmc;
          break;
      case 0x5: /* AESD */
          decrypt = 1;
 -        genfn = gen_helper_crypto_aese;
 +        genfn3 = gen_helper_crypto_aese;
          break;
      case 0x7: /* AESIMC */
          decrypt = 1;
 -        genfn = gen_helper_crypto_aesmc;
 +        genfn2 = gen_helper_crypto_aesmc;
          break;
      default:
          unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
      if (!fp_access_check(s)) {
          return;
      }
 -
 -    tcg_rd_ptr = vec_full_reg_ptr(s, rd);
 -    tcg_rn_ptr = vec_full_reg_ptr(s, rn);
 -    tcg_decrypt = tcg_const_i32(decrypt);
 -
 -    genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_decrypt);
 -
 -    tcg_temp_free_ptr(tcg_rd_ptr);
 -    tcg_temp_free_ptr(tcg_rn_ptr);
 -    tcg_temp_free_i32(tcg_decrypt);
 +    if (genfn2) {
 +        gen_gvec_op2_ool(s, true, rd, rn, decrypt, genfn2);
 +    } else {
 +        gen_gvec_op3_ool(s, true, rd, rd, rn, decrypt, genfn3);
 +    }
  }
  /* Crypto three-reg SHA
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
      int rn = extract32(insn, 5, 5);
      int rd = extract32(insn, 0, 5);
      bool feature;
 -    CryptoThreeOpFn *genfn;
 +    CryptoThreeOpFn *genfn = NULL;
 +    gen_helper_gvec_3 *oolfn = NULL;
      if (o == 0) {
          switch (opcode) {
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
              break;
          case 2: /* SM4EKEY */
              feature = dc_isar_feature(aa64_sm4, s);
 -            genfn = gen_helper_crypto_sm4ekey;
 +            oolfn = gen_helper_crypto_sm4ekey;
              break;
          default:
              unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
          return;
      }
 +    if (oolfn) {
 +        gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn);
 +        return;
 +    }
 +
      if (genfn) {
          TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
      TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
      bool feature;
      CryptoTwoOpFn *genfn;
 +    gen_helper_gvec_3 *oolfn = NULL;
      switch (opcode) {
      case 0: /* SHA512SU0 */
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
          break;
      case 1: /* SM4E */
          feature = dc_isar_feature(aa64_sm4, s);
 -        genfn = gen_helper_crypto_sm4e;
 +        oolfn = gen_helper_crypto_sm4e;
          break;
      default:
          unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
          return;
      }
 +    if (oolfn) {
 +        gen_gvec_op3_ool(s, true, rd, rd, rn, 0, oolfn);
 +        return;
 +    }
 +
      tcg_rd_ptr = vec_full_reg_ptr(s, rd);
      tcg_rn_ptr = vec_full_reg_ptr(s, rn);
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
-                     if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) {
+     return do_mve_shl_ri(s, a, gen_urshr64_i64);
-                         return 1;
+ }
-                     }
--                    ptr1 = vfp_reg_ptr(true, rd);
++static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
--                    ptr2 = vfp_reg_ptr(true, rm);
++{
--
++    TCGv_i64 rda;
--                     /* Bit 6 is the lowest opcode bit; it distinguishes between
++    TCGv_i32 rdalo, rdahi;
--                      * encryption (AESE/AESMC) and decryption (AESD/AESIMC)
++
--                      */
++    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
--                    tmp3 = tcg_const_i32(extract32(insn, 6, 1));
++        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
--
++        return false;
-+                    /*
++    }
-+                     * Bit 6 is the lowest opcode bit; it distinguishes
++    if (a->rdahi == 15) {
-+                     * between encryption (AESE/AESMC) and decryption
++        /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
-+                     * (AESD/AESIMC).
++        return false;
-+                     */
++    }
-                     if (op == NEON_2RM_AESE) {
++    if (!dc_isar_feature(aa32_mve, s) ||
--                        gen_helper_crypto_aese(ptr1, ptr2, tmp3);
++        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
-+                        tcg_gen_gvec_3_ool(vfp_reg_offset(true, rd),
++        a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
-+                                           vfp_reg_offset(true, rd),
++        a->rm == a->rdahi || a->rm == a->rdalo) {
-+                                           vfp_reg_offset(true, rm),
++        /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
-+                                           16, 16, extract32(insn, 6, 1),
++        unallocated_encoding(s);
-+                                           gen_helper_crypto_aese);
++        return true;
-                     } else {
++    }
--                        gen_helper_crypto_aesmc(ptr1, ptr2, tmp3);
++
-+                        tcg_gen_gvec_2_ool(vfp_reg_offset(true, rd),
++    rda = tcg_temp_new_i64();
-+                                           vfp_reg_offset(true, rm),
++    rdalo = load_reg(s, a->rdalo);
-+                                           16, 16, extract32(insn, 6, 1),
++    rdahi = load_reg(s, a->rdahi);
-+                                           gen_helper_crypto_aesmc);
++    tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
-                     }
++
--                    tcg_temp_free_ptr(ptr1);
++    /* The helper takes care of the sign-extension of the low 8 bits of Rm */
--                    tcg_temp_free_ptr(ptr2);
++    fn(rda, cpu_env, rda, cpu_R[a->rm]);
--                    tcg_temp_free_i32(tmp3);
++
-                     break;
++    tcg_gen_extrl_i64_i32(rdalo, rda);
-                 case NEON_2RM_SHA1H:
++    tcg_gen_extrh_i64_i32(rdahi, rda);
-                     if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) {
++    store_reg(s, a->rdalo, rdalo);
-diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
++    store_reg(s, a->rdahi, rdahi);
-index XXXXXXX..XXXXXXX 100644
++    tcg_temp_free_i64(rda);
---- a/target/arm/vec_helper.c
++
-+++ b/target/arm/vec_helper.c
++    return true;
-@@ -XXX,XX +XXX,XX @@
++}
- #include "exec/helper-proto.h"
++
- #include "tcg/tcg-gvec-desc.h"
++static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
- #include "fpu/softfloat.h"
++{
--
++    return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
-+#include "vec_internal.h"
++}
++
- /* Note that vector data is stored in host-endian 64-bit chunks,
++static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
-    so addressing units smaller than that needs a host-endian fixup.  */
++{
-@@ -XXX,XX +XXX,XX @@
++    return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
- #define H4(x)  (x)
++}
- #endif
++
++static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
--static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
++{
--{
++    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
--    uint64_t *d = vd + opr_sz;
++}
--    uintptr_t i;
++
--
++static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
--    for (i = opr_sz; i < max_sz; i += 8) {
++{
--        *d++ = 0;
++    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
--    }
++}
--}
++
--
++static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
- /* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
++{
- static int16_t inl_qrdmlah_s16(int16_t src1, int16_t src2,
++    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
-                                int16_t src3, uint32_t *sat)
++}
 +
 +static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
 +{
 +    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
 +}
 +
  /*
   * Multiply and multiply accumulate
   */
 --
 .20.1

-[PULL 11/29] hw/adc/stm32f2xx_adc: Correct memory region size and access size
+Deleted patch
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-The ADC region size is 256B, split as:
- - [0x00 - 0x4f] defined
- - [0x50 - 0xff] reserved
-All registers are 32-bit (thus when the datasheet mentions the
-last defined register is 0x4c, it means its address range is
-x4c .. 0x4f.
-This model implementation is also 32-bit. Set MemoryRegionOps
-'impl' fields.
-See:
-  'RM0033 Reference manual Rev 8', Table 10.13.18 "ADC register map".
-Reported-by: Seth Kintigh <skintigh@gmail.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20200603055915.17678-1-f4bug@amsat.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/adc/stm32f2xx_adc.c | 4 +++-
-file changed, 3 insertions(+), 1 deletion(-)
-diff --git a/hw/adc/stm32f2xx_adc.c b/hw/adc/stm32f2xx_adc.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/adc/stm32f2xx_adc.c
-+++ b/hw/adc/stm32f2xx_adc.c
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps stm32f2xx_adc_ops = {
-     .read = stm32f2xx_adc_read,
-     .write = stm32f2xx_adc_write,
-     .endianness = DEVICE_NATIVE_ENDIAN,
-+    .impl.min_access_size = 4,
-+    .impl.max_access_size = 4,
- };
- static const VMStateDescription vmstate_stm32f2xx_adc = {
-@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_adc_init(Object *obj)
-     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
-     memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s,
--                          TYPE_STM32F2XX_ADC, 0xFF);
-+                          TYPE_STM32F2XX_ADC, 0x100);
-     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
- }
---
-.20.1

-[PULL 15/29] dwc-hsotg (dwc2) USB host controller register definitions
+Deleted patch
-From: Paul Zimmerman <pauldzim@gmail.com>
-Import the dwc-hsotg (dwc2) register definitions file from the
-Linux kernel. This is a copy of drivers/usb/dwc2/hw.h from the
-mainline Linux kernel, the only changes being to the header, and
-two instances of 'u32' changed to 'uint32_t' to allow it to
-compile. Checkpatch throws a boatload of errors due to the tab
-indentation, but I would rather import it as-is than reformat it.
-Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
-Message-id: 20200520235349.21215-3-pauldzim@gmail.com
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- include/hw/usb/dwc2-regs.h | 899 +++++++++++++++++++++++++++++++++++++
-file changed, 899 insertions(+)
- create mode 100644 include/hw/usb/dwc2-regs.h
-diff --git a/include/hw/usb/dwc2-regs.h b/include/hw/usb/dwc2-regs.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/include/hw/usb/dwc2-regs.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-+/*
-+ * Imported from the Linux kernel file drivers/usb/dwc2/hw.h, commit
-+ * a89bae709b3492b478480a2c9734e7e9393b279c ("usb: dwc2: Move
-+ * UTMI_PHY_DATA defines closer")
-+ *
-+ * hw.h - DesignWare HS OTG Controller hardware definitions
-+ *
-+ * Copyright 2004-2013 Synopsys, Inc.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ *    notice, this list of conditions, and the following disclaimer,
-+ *    without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ *    notice, this list of conditions and the following disclaimer in the
-+ *    documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ *    to endorse or promote products derived from this software without
-+ *    specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation; either version 2 of the License, or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef __DWC2_HW_H__
-+#define __DWC2_HW_H__
-+
-+#define HSOTG_REG(x)    (x)
-+
-+#define GOTGCTL                HSOTG_REG(0x000)
-+#define GOTGCTL_CHIRPEN            BIT(27)
-+#define GOTGCTL_MULT_VALID_BC_MASK    (0x1f << 22)
-+#define GOTGCTL_MULT_VALID_BC_SHIFT    22
-+#define GOTGCTL_OTGVER            BIT(20)
-+#define GOTGCTL_BSESVLD            BIT(19)
-+#define GOTGCTL_ASESVLD            BIT(18)
-+#define GOTGCTL_DBNC_SHORT        BIT(17)
-+#define GOTGCTL_CONID_B            BIT(16)
-+#define GOTGCTL_DBNCE_FLTR_BYPASS    BIT(15)
-+#define GOTGCTL_DEVHNPEN        BIT(11)
-+#define GOTGCTL_HSTSETHNPEN        BIT(10)
-+#define GOTGCTL_HNPREQ            BIT(9)
-+#define GOTGCTL_HSTNEGSCS        BIT(8)
-+#define GOTGCTL_SESREQ            BIT(1)
-+#define GOTGCTL_SESREQSCS        BIT(0)
-+
-+#define GOTGINT                HSOTG_REG(0x004)
-+#define GOTGINT_DBNCE_DONE        BIT(19)
-+#define GOTGINT_A_DEV_TOUT_CHG        BIT(18)
-+#define GOTGINT_HST_NEG_DET        BIT(17)
-+#define GOTGINT_HST_NEG_SUC_STS_CHNG    BIT(9)
-+#define GOTGINT_SES_REQ_SUC_STS_CHNG    BIT(8)
-+#define GOTGINT_SES_END_DET        BIT(2)
-+
-+#define GAHBCFG                HSOTG_REG(0x008)
-+#define GAHBCFG_AHB_SINGLE        BIT(23)
-+#define GAHBCFG_NOTI_ALL_DMA_WRIT    BIT(22)
-+#define GAHBCFG_REM_MEM_SUPP        BIT(21)
-+#define GAHBCFG_P_TXF_EMP_LVL        BIT(8)
-+#define GAHBCFG_NP_TXF_EMP_LVL        BIT(7)
-+#define GAHBCFG_DMA_EN            BIT(5)
-+#define GAHBCFG_HBSTLEN_MASK        (0xf << 1)
-+#define GAHBCFG_HBSTLEN_SHIFT        1
-+#define GAHBCFG_HBSTLEN_SINGLE        0
-+#define GAHBCFG_HBSTLEN_INCR        1
-+#define GAHBCFG_HBSTLEN_INCR4        3
-+#define GAHBCFG_HBSTLEN_INCR8        5
-+#define GAHBCFG_HBSTLEN_INCR16        7
-+#define GAHBCFG_GLBL_INTR_EN        BIT(0)
-+#define GAHBCFG_CTRL_MASK        (GAHBCFG_P_TXF_EMP_LVL | \
-+                     GAHBCFG_NP_TXF_EMP_LVL | \
-+                     GAHBCFG_DMA_EN | \
-+                     GAHBCFG_GLBL_INTR_EN)
-+
-+#define GUSBCFG                HSOTG_REG(0x00C)
-+#define GUSBCFG_FORCEDEVMODE        BIT(30)
-+#define GUSBCFG_FORCEHOSTMODE        BIT(29)
-+#define GUSBCFG_TXENDDELAY        BIT(28)
-+#define GUSBCFG_ICTRAFFICPULLREMOVE    BIT(27)
-+#define GUSBCFG_ICUSBCAP        BIT(26)
-+#define GUSBCFG_ULPI_INT_PROT_DIS    BIT(25)
-+#define GUSBCFG_INDICATORPASSTHROUGH    BIT(24)
-+#define GUSBCFG_INDICATORCOMPLEMENT    BIT(23)
-+#define GUSBCFG_TERMSELDLPULSE        BIT(22)
-+#define GUSBCFG_ULPI_INT_VBUS_IND    BIT(21)
-+#define GUSBCFG_ULPI_EXT_VBUS_DRV    BIT(20)
-+#define GUSBCFG_ULPI_CLK_SUSP_M        BIT(19)
-+#define GUSBCFG_ULPI_AUTO_RES        BIT(18)
-+#define GUSBCFG_ULPI_FS_LS        BIT(17)
-+#define GUSBCFG_OTG_UTMI_FS_SEL        BIT(16)
-+#define GUSBCFG_PHY_LP_CLK_SEL        BIT(15)
-+#define GUSBCFG_USBTRDTIM_MASK        (0xf << 10)
-+#define GUSBCFG_USBTRDTIM_SHIFT        10
-+#define GUSBCFG_HNPCAP            BIT(9)
-+#define GUSBCFG_SRPCAP            BIT(8)
-+#define GUSBCFG_DDRSEL            BIT(7)
-+#define GUSBCFG_PHYSEL            BIT(6)
-+#define GUSBCFG_FSINTF            BIT(5)
-+#define GUSBCFG_ULPI_UTMI_SEL        BIT(4)
-+#define GUSBCFG_PHYIF16            BIT(3)
-+#define GUSBCFG_PHYIF8            (0 << 3)
-+#define GUSBCFG_TOUTCAL_MASK        (0x7 << 0)
-+#define GUSBCFG_TOUTCAL_SHIFT        0
-+#define GUSBCFG_TOUTCAL_LIMIT        0x7
-+#define GUSBCFG_TOUTCAL(_x)        ((_x) << 0)
-+
-+#define GRSTCTL                HSOTG_REG(0x010)
-+#define GRSTCTL_AHBIDLE            BIT(31)
-+#define GRSTCTL_DMAREQ            BIT(30)
-+#define GRSTCTL_TXFNUM_MASK        (0x1f << 6)
-+#define GRSTCTL_TXFNUM_SHIFT        6
-+#define GRSTCTL_TXFNUM_LIMIT        0x1f
-+#define GRSTCTL_TXFNUM(_x)        ((_x) << 6)
-+#define GRSTCTL_TXFFLSH            BIT(5)
-+#define GRSTCTL_RXFFLSH            BIT(4)
-+#define GRSTCTL_IN_TKNQ_FLSH        BIT(3)
-+#define GRSTCTL_FRMCNTRRST        BIT(2)
-+#define GRSTCTL_HSFTRST            BIT(1)
-+#define GRSTCTL_CSFTRST            BIT(0)
-+
-+#define GINTSTS                HSOTG_REG(0x014)
-+#define GINTMSK                HSOTG_REG(0x018)
-+#define GINTSTS_WKUPINT            BIT(31)
-+#define GINTSTS_SESSREQINT        BIT(30)
-+#define GINTSTS_DISCONNINT        BIT(29)
-+#define GINTSTS_CONIDSTSCHNG        BIT(28)
-+#define GINTSTS_LPMTRANRCVD        BIT(27)
-+#define GINTSTS_PTXFEMP            BIT(26)
-+#define GINTSTS_HCHINT            BIT(25)
-+#define GINTSTS_PRTINT            BIT(24)
-+#define GINTSTS_RESETDET        BIT(23)
-+#define GINTSTS_FET_SUSP        BIT(22)
-+#define GINTSTS_INCOMPL_IP        BIT(21)
-+#define GINTSTS_INCOMPL_SOOUT        BIT(21)
-+#define GINTSTS_INCOMPL_SOIN        BIT(20)
-+#define GINTSTS_OEPINT            BIT(19)
-+#define GINTSTS_IEPINT            BIT(18)
-+#define GINTSTS_EPMIS            BIT(17)
-+#define GINTSTS_RESTOREDONE        BIT(16)
-+#define GINTSTS_EOPF            BIT(15)
-+#define GINTSTS_ISOUTDROP        BIT(14)
-+#define GINTSTS_ENUMDONE        BIT(13)
-+#define GINTSTS_USBRST            BIT(12)
-+#define GINTSTS_USBSUSP            BIT(11)
-+#define GINTSTS_ERLYSUSP        BIT(10)
-+#define GINTSTS_I2CINT            BIT(9)
-+#define GINTSTS_ULPI_CK_INT        BIT(8)
-+#define GINTSTS_GOUTNAKEFF        BIT(7)
-+#define GINTSTS_GINNAKEFF        BIT(6)
-+#define GINTSTS_NPTXFEMP        BIT(5)
-+#define GINTSTS_RXFLVL            BIT(4)
-+#define GINTSTS_SOF            BIT(3)
-+#define GINTSTS_OTGINT            BIT(2)
-+#define GINTSTS_MODEMIS            BIT(1)
-+#define GINTSTS_CURMODE_HOST        BIT(0)
-+
-+#define GRXSTSR                HSOTG_REG(0x01C)
-+#define GRXSTSP                HSOTG_REG(0x020)
-+#define GRXSTS_FN_MASK            (0x7f << 25)
-+#define GRXSTS_FN_SHIFT            25
-+#define GRXSTS_PKTSTS_MASK        (0xf << 17)
-+#define GRXSTS_PKTSTS_SHIFT        17
-+#define GRXSTS_PKTSTS_GLOBALOUTNAK    1
-+#define GRXSTS_PKTSTS_OUTRX        2
-+#define GRXSTS_PKTSTS_HCHIN        2
-+#define GRXSTS_PKTSTS_OUTDONE        3
-+#define GRXSTS_PKTSTS_HCHIN_XFER_COMP    3
-+#define GRXSTS_PKTSTS_SETUPDONE        4
-+#define GRXSTS_PKTSTS_DATATOGGLEERR    5
-+#define GRXSTS_PKTSTS_SETUPRX        6
-+#define GRXSTS_PKTSTS_HCHHALTED        7
-+#define GRXSTS_HCHNUM_MASK        (0xf << 0)
-+#define GRXSTS_HCHNUM_SHIFT        0
-+#define GRXSTS_DPID_MASK        (0x3 << 15)
-+#define GRXSTS_DPID_SHIFT        15
-+#define GRXSTS_BYTECNT_MASK        (0x7ff << 4)
-+#define GRXSTS_BYTECNT_SHIFT        4
-+#define GRXSTS_EPNUM_MASK        (0xf << 0)
-+#define GRXSTS_EPNUM_SHIFT        0
-+
-+#define GRXFSIZ                HSOTG_REG(0x024)
-+#define GRXFSIZ_DEPTH_MASK        (0xffff << 0)
-+#define GRXFSIZ_DEPTH_SHIFT        0
-+
-+#define GNPTXFSIZ            HSOTG_REG(0x028)
-+/* Use FIFOSIZE_* constants to access this register */
-+
-+#define GNPTXSTS            HSOTG_REG(0x02C)
-+#define GNPTXSTS_NP_TXQ_TOP_MASK        (0x7f << 24)
-+#define GNPTXSTS_NP_TXQ_TOP_SHIFT        24
-+#define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK        (0xff << 16)
-+#define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT        16
-+#define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v)    (((_v) >> 16) & 0xff)
-+#define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK        (0xffff << 0)
-+#define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT        0
-+#define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v)    (((_v) >> 0) & 0xffff)
-+
-+#define GI2CCTL                HSOTG_REG(0x0030)
-+#define GI2CCTL_BSYDNE            BIT(31)
-+#define GI2CCTL_RW            BIT(30)
-+#define GI2CCTL_I2CDATSE0        BIT(28)
-+#define GI2CCTL_I2CDEVADDR_MASK        (0x3 << 26)
-+#define GI2CCTL_I2CDEVADDR_SHIFT    26
-+#define GI2CCTL_I2CSUSPCTL        BIT(25)
-+#define GI2CCTL_ACK            BIT(24)
-+#define GI2CCTL_I2CEN            BIT(23)
-+#define GI2CCTL_ADDR_MASK        (0x7f << 16)
-+#define GI2CCTL_ADDR_SHIFT        16
-+#define GI2CCTL_REGADDR_MASK        (0xff << 8)
-+#define GI2CCTL_REGADDR_SHIFT        8
-+#define GI2CCTL_RWDATA_MASK        (0xff << 0)
-+#define GI2CCTL_RWDATA_SHIFT        0
-+
-+#define GPVNDCTL            HSOTG_REG(0x0034)
-+#define GGPIO                HSOTG_REG(0x0038)
-+#define GGPIO_STM32_OTG_GCCFG_PWRDWN    BIT(16)
-+
-+#define GUID                HSOTG_REG(0x003c)
-+#define GSNPSID                HSOTG_REG(0x0040)
-+#define GHWCFG1                HSOTG_REG(0x0044)
-+#define GSNPSID_ID_MASK            GENMASK(31, 16)
-+
-+#define GHWCFG2                HSOTG_REG(0x0048)
-+#define GHWCFG2_OTG_ENABLE_IC_USB        BIT(31)
-+#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK        (0x1f << 26)
-+#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT        26
-+#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK    (0x3 << 24)
-+#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT    24
-+#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK    (0x3 << 22)
-+#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT    22
-+#define GHWCFG2_MULTI_PROC_INT            BIT(20)
-+#define GHWCFG2_DYNAMIC_FIFO            BIT(19)
-+#define GHWCFG2_PERIO_EP_SUPPORTED        BIT(18)
-+#define GHWCFG2_NUM_HOST_CHAN_MASK        (0xf << 14)
-+#define GHWCFG2_NUM_HOST_CHAN_SHIFT        14
-+#define GHWCFG2_NUM_DEV_EP_MASK            (0xf << 10)
-+#define GHWCFG2_NUM_DEV_EP_SHIFT        10
-+#define GHWCFG2_FS_PHY_TYPE_MASK        (0x3 << 8)
-+#define GHWCFG2_FS_PHY_TYPE_SHIFT        8
-+#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED    0
-+#define GHWCFG2_FS_PHY_TYPE_DEDICATED        1
-+#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI        2
-+#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI        3
-+#define GHWCFG2_HS_PHY_TYPE_MASK        (0x3 << 6)
-+#define GHWCFG2_HS_PHY_TYPE_SHIFT        6
-+#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED    0
-+#define GHWCFG2_HS_PHY_TYPE_UTMI        1
-+#define GHWCFG2_HS_PHY_TYPE_ULPI        2
-+#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI        3
-+#define GHWCFG2_POINT2POINT            BIT(5)
-+#define GHWCFG2_ARCHITECTURE_MASK        (0x3 << 3)
-+#define GHWCFG2_ARCHITECTURE_SHIFT        3
-+#define GHWCFG2_SLAVE_ONLY_ARCH            0
-+#define GHWCFG2_EXT_DMA_ARCH            1
-+#define GHWCFG2_INT_DMA_ARCH            2
-+#define GHWCFG2_OP_MODE_MASK            (0x7 << 0)
-+#define GHWCFG2_OP_MODE_SHIFT            0
-+#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE        0
-+#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE    1
-+#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE    2
-+#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE    3
-+#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE    4
-+#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST    5
-+#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST    6
-+#define GHWCFG2_OP_MODE_UNDEFINED        7
-+
-+#define GHWCFG3                HSOTG_REG(0x004c)
-+#define GHWCFG3_DFIFO_DEPTH_MASK        (0xffff << 16)
-+#define GHWCFG3_DFIFO_DEPTH_SHIFT        16
-+#define GHWCFG3_OTG_LPM_EN            BIT(15)
-+#define GHWCFG3_BC_SUPPORT            BIT(14)
-+#define GHWCFG3_OTG_ENABLE_HSIC            BIT(13)
-+#define GHWCFG3_ADP_SUPP            BIT(12)
-+#define GHWCFG3_SYNCH_RESET_TYPE        BIT(11)
-+#define GHWCFG3_OPTIONAL_FEATURES        BIT(10)
-+#define GHWCFG3_VENDOR_CTRL_IF            BIT(9)
-+#define GHWCFG3_I2C                BIT(8)
-+#define GHWCFG3_OTG_FUNC            BIT(7)
-+#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK    (0x7 << 4)
-+#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT    4
-+#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK    (0xf << 0)
-+#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT    0
-+
-+#define GHWCFG4                HSOTG_REG(0x0050)
-+#define GHWCFG4_DESC_DMA_DYN            BIT(31)
-+#define GHWCFG4_DESC_DMA            BIT(30)
-+#define GHWCFG4_NUM_IN_EPS_MASK            (0xf << 26)
-+#define GHWCFG4_NUM_IN_EPS_SHIFT        26
-+#define GHWCFG4_DED_FIFO_EN            BIT(25)
-+#define GHWCFG4_DED_FIFO_SHIFT        25
-+#define GHWCFG4_SESSION_END_FILT_EN        BIT(24)
-+#define GHWCFG4_B_VALID_FILT_EN            BIT(23)
-+#define GHWCFG4_A_VALID_FILT_EN            BIT(22)
-+#define GHWCFG4_VBUS_VALID_FILT_EN        BIT(21)
-+#define GHWCFG4_IDDIG_FILT_EN            BIT(20)
-+#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK    (0xf << 16)
-+#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT    16
-+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK    (0x3 << 14)
-+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT    14
-+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8        0
-+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16        1
-+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16    2
-+#define GHWCFG4_ACG_SUPPORTED            BIT(12)
-+#define GHWCFG4_IPG_ISOC_SUPPORTED        BIT(11)
-+#define GHWCFG4_SERVICE_INTERVAL_SUPPORTED      BIT(10)
-+#define GHWCFG4_XHIBER                BIT(7)
-+#define GHWCFG4_HIBER                BIT(6)
-+#define GHWCFG4_MIN_AHB_FREQ            BIT(5)
-+#define GHWCFG4_POWER_OPTIMIZ            BIT(4)
-+#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK    (0xf << 0)
-+#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT    0
-+
-+#define GLPMCFG                HSOTG_REG(0x0054)
-+#define GLPMCFG_INVSELHSIC        BIT(31)
-+#define GLPMCFG_HSICCON            BIT(30)
-+#define GLPMCFG_RSTRSLPSTS        BIT(29)
-+#define GLPMCFG_ENBESL            BIT(28)
-+#define GLPMCFG_LPM_RETRYCNT_STS_MASK    (0x7 << 25)
-+#define GLPMCFG_LPM_RETRYCNT_STS_SHIFT    25
-+#define GLPMCFG_SNDLPM            BIT(24)
-+#define GLPMCFG_RETRY_CNT_MASK        (0x7 << 21)
-+#define GLPMCFG_RETRY_CNT_SHIFT        21
-+#define GLPMCFG_LPM_REJECT_CTRL_CONTROL    BIT(21)
-+#define GLPMCFG_LPM_ACCEPT_CTRL_ISOC    BIT(22)
-+#define GLPMCFG_LPM_CHNL_INDX_MASK    (0xf << 17)
-+#define GLPMCFG_LPM_CHNL_INDX_SHIFT    17
-+#define GLPMCFG_L1RESUMEOK        BIT(16)
-+#define GLPMCFG_SLPSTS            BIT(15)
-+#define GLPMCFG_COREL1RES_MASK        (0x3 << 13)
-+#define GLPMCFG_COREL1RES_SHIFT        13
-+#define GLPMCFG_HIRD_THRES_MASK        (0x1f << 8)
-+#define GLPMCFG_HIRD_THRES_SHIFT    8
-+#define GLPMCFG_HIRD_THRES_EN        (0x10 << 8)
-+#define GLPMCFG_ENBLSLPM        BIT(7)
-+#define GLPMCFG_BREMOTEWAKE        BIT(6)
-+#define GLPMCFG_HIRD_MASK        (0xf << 2)
-+#define GLPMCFG_HIRD_SHIFT        2
-+#define GLPMCFG_APPL1RES        BIT(1)
-+#define GLPMCFG_LPMCAP            BIT(0)
-+
-+#define GPWRDN                HSOTG_REG(0x0058)
-+#define GPWRDN_MULT_VAL_ID_BC_MASK    (0x1f << 24)
-+#define GPWRDN_MULT_VAL_ID_BC_SHIFT    24
-+#define GPWRDN_ADP_INT            BIT(23)
-+#define GPWRDN_BSESSVLD            BIT(22)
-+#define GPWRDN_IDSTS            BIT(21)
-+#define GPWRDN_LINESTATE_MASK        (0x3 << 19)
-+#define GPWRDN_LINESTATE_SHIFT        19
-+#define GPWRDN_STS_CHGINT_MSK        BIT(18)
-+#define GPWRDN_STS_CHGINT        BIT(17)
-+#define GPWRDN_SRP_DET_MSK        BIT(16)
-+#define GPWRDN_SRP_DET            BIT(15)
-+#define GPWRDN_CONNECT_DET_MSK        BIT(14)
-+#define GPWRDN_CONNECT_DET        BIT(13)
-+#define GPWRDN_DISCONN_DET_MSK        BIT(12)
-+#define GPWRDN_DISCONN_DET        BIT(11)
-+#define GPWRDN_RST_DET_MSK        BIT(10)
-+#define GPWRDN_RST_DET            BIT(9)
-+#define GPWRDN_LNSTSCHG_MSK        BIT(8)
-+#define GPWRDN_LNSTSCHG            BIT(7)
-+#define GPWRDN_DIS_VBUS            BIT(6)
-+#define GPWRDN_PWRDNSWTCH        BIT(5)
-+#define GPWRDN_PWRDNRSTN        BIT(4)
-+#define GPWRDN_PWRDNCLMP        BIT(3)
-+#define GPWRDN_RESTORE            BIT(2)
-+#define GPWRDN_PMUACTV            BIT(1)
-+#define GPWRDN_PMUINTSEL        BIT(0)
-+
-+#define GDFIFOCFG            HSOTG_REG(0x005c)
-+#define GDFIFOCFG_EPINFOBASE_MASK    (0xffff << 16)
-+#define GDFIFOCFG_EPINFOBASE_SHIFT    16
-+#define GDFIFOCFG_GDFIFOCFG_MASK    (0xffff << 0)
-+#define GDFIFOCFG_GDFIFOCFG_SHIFT    0
-+
-+#define ADPCTL                HSOTG_REG(0x0060)
-+#define ADPCTL_AR_MASK            (0x3 << 27)
-+#define ADPCTL_AR_SHIFT            27
-+#define ADPCTL_ADP_TMOUT_INT_MSK    BIT(26)
-+#define ADPCTL_ADP_SNS_INT_MSK        BIT(25)
-+#define ADPCTL_ADP_PRB_INT_MSK        BIT(24)
-+#define ADPCTL_ADP_TMOUT_INT        BIT(23)
-+#define ADPCTL_ADP_SNS_INT        BIT(22)
-+#define ADPCTL_ADP_PRB_INT        BIT(21)
-+#define ADPCTL_ADPENA            BIT(20)
-+#define ADPCTL_ADPRES            BIT(19)
-+#define ADPCTL_ENASNS            BIT(18)
-+#define ADPCTL_ENAPRB            BIT(17)
-+#define ADPCTL_RTIM_MASK        (0x7ff << 6)
-+#define ADPCTL_RTIM_SHIFT        6
-+#define ADPCTL_PRB_PER_MASK        (0x3 << 4)
-+#define ADPCTL_PRB_PER_SHIFT        4
-+#define ADPCTL_PRB_DELTA_MASK        (0x3 << 2)
-+#define ADPCTL_PRB_DELTA_SHIFT        2
-+#define ADPCTL_PRB_DSCHRG_MASK        (0x3 << 0)
-+#define ADPCTL_PRB_DSCHRG_SHIFT        0
-+
-+#define GREFCLK                    HSOTG_REG(0x0064)
-+#define GREFCLK_REFCLKPER_MASK            (0x1ffff << 15)
-+#define GREFCLK_REFCLKPER_SHIFT            15
-+#define GREFCLK_REF_CLK_MODE            BIT(14)
-+#define GREFCLK_SOF_CNT_WKUP_ALERT_MASK        (0x3ff)
-+#define GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT    0
-+
-+#define GINTMSK2            HSOTG_REG(0x0068)
-+#define GINTMSK2_WKUP_ALERT_INT_MSK    BIT(0)
-+
-+#define GINTSTS2            HSOTG_REG(0x006c)
-+#define GINTSTS2_WKUP_ALERT_INT        BIT(0)
-+
-+#define HPTXFSIZ            HSOTG_REG(0x100)
-+/* Use FIFOSIZE_* constants to access this register */
-+
-+#define DPTXFSIZN(_a)            HSOTG_REG(0x104 + (((_a) - 1) * 4))
-+/* Use FIFOSIZE_* constants to access this register */
-+
-+/* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
-+#define FIFOSIZE_DEPTH_MASK        (0xffff << 16)
-+#define FIFOSIZE_DEPTH_SHIFT        16
-+#define FIFOSIZE_STARTADDR_MASK        (0xffff << 0)
-+#define FIFOSIZE_STARTADDR_SHIFT    0
-+#define FIFOSIZE_DEPTH_GET(_x)        (((_x) >> 16) & 0xffff)
-+
-+/* Device mode registers */
-+
-+#define DCFG                HSOTG_REG(0x800)
-+#define DCFG_DESCDMA_EN            BIT(23)
-+#define DCFG_EPMISCNT_MASK        (0x1f << 18)
-+#define DCFG_EPMISCNT_SHIFT        18
-+#define DCFG_EPMISCNT_LIMIT        0x1f
-+#define DCFG_EPMISCNT(_x)        ((_x) << 18)
-+#define DCFG_IPG_ISOC_SUPPORDED        BIT(17)
-+#define DCFG_PERFRINT_MASK        (0x3 << 11)
-+#define DCFG_PERFRINT_SHIFT        11
-+#define DCFG_PERFRINT_LIMIT        0x3
-+#define DCFG_PERFRINT(_x)        ((_x) << 11)
-+#define DCFG_DEVADDR_MASK        (0x7f << 4)
-+#define DCFG_DEVADDR_SHIFT        4
-+#define DCFG_DEVADDR_LIMIT        0x7f
-+#define DCFG_DEVADDR(_x)        ((_x) << 4)
-+#define DCFG_NZ_STS_OUT_HSHK        BIT(2)
-+#define DCFG_DEVSPD_MASK        (0x3 << 0)
-+#define DCFG_DEVSPD_SHIFT        0
-+#define DCFG_DEVSPD_HS            0
-+#define DCFG_DEVSPD_FS            1
-+#define DCFG_DEVSPD_LS            2
-+#define DCFG_DEVSPD_FS48        3
-+
-+#define DCTL                HSOTG_REG(0x804)
-+#define DCTL_SERVICE_INTERVAL_SUPPORTED BIT(19)
-+#define DCTL_PWRONPRGDONE        BIT(11)
-+#define DCTL_CGOUTNAK            BIT(10)
-+#define DCTL_SGOUTNAK            BIT(9)
-+#define DCTL_CGNPINNAK            BIT(8)
-+#define DCTL_SGNPINNAK            BIT(7)
-+#define DCTL_TSTCTL_MASK        (0x7 << 4)
-+#define DCTL_TSTCTL_SHIFT        4
-+#define DCTL_GOUTNAKSTS            BIT(3)
-+#define DCTL_GNPINNAKSTS        BIT(2)
-+#define DCTL_SFTDISCON            BIT(1)
-+#define DCTL_RMTWKUPSIG            BIT(0)
-+
-+#define DSTS                HSOTG_REG(0x808)
-+#define DSTS_SOFFN_MASK            (0x3fff << 8)
-+#define DSTS_SOFFN_SHIFT        8
-+#define DSTS_SOFFN_LIMIT        0x3fff
-+#define DSTS_SOFFN(_x)            ((_x) << 8)
-+#define DSTS_ERRATICERR            BIT(3)
-+#define DSTS_ENUMSPD_MASK        (0x3 << 1)
-+#define DSTS_ENUMSPD_SHIFT        1
-+#define DSTS_ENUMSPD_HS            0
-+#define DSTS_ENUMSPD_FS            1
-+#define DSTS_ENUMSPD_LS            2
-+#define DSTS_ENUMSPD_FS48        3
-+#define DSTS_SUSPSTS            BIT(0)
-+
-+#define DIEPMSK                HSOTG_REG(0x810)
-+#define DIEPMSK_NAKMSK            BIT(13)
-+#define DIEPMSK_BNAININTRMSK        BIT(9)
-+#define DIEPMSK_TXFIFOUNDRNMSK        BIT(8)
-+#define DIEPMSK_TXFIFOEMPTY        BIT(7)
-+#define DIEPMSK_INEPNAKEFFMSK        BIT(6)
-+#define DIEPMSK_INTKNEPMISMSK        BIT(5)
-+#define DIEPMSK_INTKNTXFEMPMSK        BIT(4)
-+#define DIEPMSK_TIMEOUTMSK        BIT(3)
-+#define DIEPMSK_AHBERRMSK        BIT(2)
-+#define DIEPMSK_EPDISBLDMSK        BIT(1)
-+#define DIEPMSK_XFERCOMPLMSK        BIT(0)
-+
-+#define DOEPMSK                HSOTG_REG(0x814)
-+#define DOEPMSK_BNAMSK            BIT(9)
-+#define DOEPMSK_BACK2BACKSETUP        BIT(6)
-+#define DOEPMSK_STSPHSERCVDMSK        BIT(5)
-+#define DOEPMSK_OUTTKNEPDISMSK        BIT(4)
-+#define DOEPMSK_SETUPMSK        BIT(3)
-+#define DOEPMSK_AHBERRMSK        BIT(2)
-+#define DOEPMSK_EPDISBLDMSK        BIT(1)
-+#define DOEPMSK_XFERCOMPLMSK        BIT(0)
-+
-+#define DAINT                HSOTG_REG(0x818)
-+#define DAINTMSK            HSOTG_REG(0x81C)
-+#define DAINT_OUTEP_SHIFT        16
-+#define DAINT_OUTEP(_x)            (1 << ((_x) + 16))
-+#define DAINT_INEP(_x)            (1 << (_x))
-+
-+#define DTKNQR1                HSOTG_REG(0x820)
-+#define DTKNQR2                HSOTG_REG(0x824)
-+#define DTKNQR3                HSOTG_REG(0x830)
-+#define DTKNQR4                HSOTG_REG(0x834)
-+#define DIEPEMPMSK            HSOTG_REG(0x834)
-+
-+#define DVBUSDIS            HSOTG_REG(0x828)
-+#define DVBUSPULSE            HSOTG_REG(0x82C)
-+
-+#define DIEPCTL0            HSOTG_REG(0x900)
-+#define DIEPCTL(_a)            HSOTG_REG(0x900 + ((_a) * 0x20))
-+
-+#define DOEPCTL0            HSOTG_REG(0xB00)
-+#define DOEPCTL(_a)            HSOTG_REG(0xB00 + ((_a) * 0x20))
-+
-+/* EP0 specialness:
-+ * bits[29..28] - reserved (no SetD0PID, SetD1PID)
-+ * bits[25..22] - should always be zero, this isn't a periodic endpoint
-+ * bits[10..0]  - MPS setting different for EP0
-+ */
-+#define D0EPCTL_MPS_MASK        (0x3 << 0)
-+#define D0EPCTL_MPS_SHIFT        0
-+#define D0EPCTL_MPS_64            0
-+#define D0EPCTL_MPS_32            1
-+#define D0EPCTL_MPS_16            2
-+#define D0EPCTL_MPS_8            3
-+
-+#define DXEPCTL_EPENA            BIT(31)
-+#define DXEPCTL_EPDIS            BIT(30)
-+#define DXEPCTL_SETD1PID        BIT(29)
-+#define DXEPCTL_SETODDFR        BIT(29)
-+#define DXEPCTL_SETD0PID        BIT(28)
-+#define DXEPCTL_SETEVENFR        BIT(28)
-+#define DXEPCTL_SNAK            BIT(27)
-+#define DXEPCTL_CNAK            BIT(26)
-+#define DXEPCTL_TXFNUM_MASK        (0xf << 22)
-+#define DXEPCTL_TXFNUM_SHIFT        22
-+#define DXEPCTL_TXFNUM_LIMIT        0xf
-+#define DXEPCTL_TXFNUM(_x)        ((_x) << 22)
-+#define DXEPCTL_STALL            BIT(21)
-+#define DXEPCTL_SNP            BIT(20)
-+#define DXEPCTL_EPTYPE_MASK        (0x3 << 18)
-+#define DXEPCTL_EPTYPE_CONTROL        (0x0 << 18)
-+#define DXEPCTL_EPTYPE_ISO        (0x1 << 18)
-+#define DXEPCTL_EPTYPE_BULK        (0x2 << 18)
-+#define DXEPCTL_EPTYPE_INTERRUPT    (0x3 << 18)
-+
-+#define DXEPCTL_NAKSTS            BIT(17)
-+#define DXEPCTL_DPID            BIT(16)
-+#define DXEPCTL_EOFRNUM            BIT(16)
-+#define DXEPCTL_USBACTEP        BIT(15)
-+#define DXEPCTL_NEXTEP_MASK        (0xf << 11)
-+#define DXEPCTL_NEXTEP_SHIFT        11
-+#define DXEPCTL_NEXTEP_LIMIT        0xf
-+#define DXEPCTL_NEXTEP(_x)        ((_x) << 11)
-+#define DXEPCTL_MPS_MASK        (0x7ff << 0)
-+#define DXEPCTL_MPS_SHIFT        0
-+#define DXEPCTL_MPS_LIMIT        0x7ff
-+#define DXEPCTL_MPS(_x)            ((_x) << 0)
-+
-+#define DIEPINT(_a)            HSOTG_REG(0x908 + ((_a) * 0x20))
-+#define DOEPINT(_a)            HSOTG_REG(0xB08 + ((_a) * 0x20))
-+#define DXEPINT_SETUP_RCVD        BIT(15)
-+#define DXEPINT_NYETINTRPT        BIT(14)
-+#define DXEPINT_NAKINTRPT        BIT(13)
-+#define DXEPINT_BBLEERRINTRPT        BIT(12)
-+#define DXEPINT_PKTDRPSTS        BIT(11)
-+#define DXEPINT_BNAINTR            BIT(9)
-+#define DXEPINT_TXFIFOUNDRN        BIT(8)
-+#define DXEPINT_OUTPKTERR        BIT(8)
-+#define DXEPINT_TXFEMP            BIT(7)
-+#define DXEPINT_INEPNAKEFF        BIT(6)
-+#define DXEPINT_BACK2BACKSETUP        BIT(6)
-+#define DXEPINT_INTKNEPMIS        BIT(5)
-+#define DXEPINT_STSPHSERCVD        BIT(5)
-+#define DXEPINT_INTKNTXFEMP        BIT(4)
-+#define DXEPINT_OUTTKNEPDIS        BIT(4)
-+#define DXEPINT_TIMEOUT            BIT(3)
-+#define DXEPINT_SETUP            BIT(3)
-+#define DXEPINT_AHBERR            BIT(2)
-+#define DXEPINT_EPDISBLD        BIT(1)
-+#define DXEPINT_XFERCOMPL        BIT(0)
-+
-+#define DIEPTSIZ0            HSOTG_REG(0x910)
-+#define DIEPTSIZ0_PKTCNT_MASK        (0x3 << 19)
-+#define DIEPTSIZ0_PKTCNT_SHIFT        19
-+#define DIEPTSIZ0_PKTCNT_LIMIT        0x3
-+#define DIEPTSIZ0_PKTCNT(_x)        ((_x) << 19)
-+#define DIEPTSIZ0_XFERSIZE_MASK        (0x7f << 0)
-+#define DIEPTSIZ0_XFERSIZE_SHIFT    0
-+#define DIEPTSIZ0_XFERSIZE_LIMIT    0x7f
-+#define DIEPTSIZ0_XFERSIZE(_x)        ((_x) << 0)
-+
-+#define DOEPTSIZ0            HSOTG_REG(0xB10)
-+#define DOEPTSIZ0_SUPCNT_MASK        (0x3 << 29)
-+#define DOEPTSIZ0_SUPCNT_SHIFT        29
-+#define DOEPTSIZ0_SUPCNT_LIMIT        0x3
-+#define DOEPTSIZ0_SUPCNT(_x)        ((_x) << 29)
-+#define DOEPTSIZ0_PKTCNT        BIT(19)
-+#define DOEPTSIZ0_XFERSIZE_MASK        (0x7f << 0)
-+#define DOEPTSIZ0_XFERSIZE_SHIFT    0
-+
-+#define DIEPTSIZ(_a)            HSOTG_REG(0x910 + ((_a) * 0x20))
-+#define DOEPTSIZ(_a)            HSOTG_REG(0xB10 + ((_a) * 0x20))
-+#define DXEPTSIZ_MC_MASK        (0x3 << 29)
-+#define DXEPTSIZ_MC_SHIFT        29
-+#define DXEPTSIZ_MC_LIMIT        0x3
-+#define DXEPTSIZ_MC(_x)            ((_x) << 29)
-+#define DXEPTSIZ_PKTCNT_MASK        (0x3ff << 19)
-+#define DXEPTSIZ_PKTCNT_SHIFT        19
-+#define DXEPTSIZ_PKTCNT_LIMIT        0x3ff
-+#define DXEPTSIZ_PKTCNT_GET(_v)        (((_v) >> 19) & 0x3ff)
-+#define DXEPTSIZ_PKTCNT(_x)        ((_x) << 19)
-+#define DXEPTSIZ_XFERSIZE_MASK        (0x7ffff << 0)
-+#define DXEPTSIZ_XFERSIZE_SHIFT        0
-+#define DXEPTSIZ_XFERSIZE_LIMIT        0x7ffff
-+#define DXEPTSIZ_XFERSIZE_GET(_v)    (((_v) >> 0) & 0x7ffff)
-+#define DXEPTSIZ_XFERSIZE(_x)        ((_x) << 0)
-+
-+#define DIEPDMA(_a)            HSOTG_REG(0x914 + ((_a) * 0x20))
-+#define DOEPDMA(_a)            HSOTG_REG(0xB14 + ((_a) * 0x20))
-+
-+#define DTXFSTS(_a)            HSOTG_REG(0x918 + ((_a) * 0x20))
-+
-+#define PCGCTL                HSOTG_REG(0x0e00)
-+#define PCGCTL_IF_DEV_MODE        BIT(31)
-+#define PCGCTL_P2HD_PRT_SPD_MASK    (0x3 << 29)
-+#define PCGCTL_P2HD_PRT_SPD_SHIFT    29
-+#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK    (0x3 << 27)
-+#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT    27
-+#define PCGCTL_MAC_DEV_ADDR_MASK    (0x7f << 20)
-+#define PCGCTL_MAC_DEV_ADDR_SHIFT    20
-+#define PCGCTL_MAX_TERMSEL        BIT(19)
-+#define PCGCTL_MAX_XCVRSELECT_MASK    (0x3 << 17)
-+#define PCGCTL_MAX_XCVRSELECT_SHIFT    17
-+#define PCGCTL_PORT_POWER        BIT(16)
-+#define PCGCTL_PRT_CLK_SEL_MASK        (0x3 << 14)
-+#define PCGCTL_PRT_CLK_SEL_SHIFT    14
-+#define PCGCTL_ESS_REG_RESTORED        BIT(13)
-+#define PCGCTL_EXTND_HIBER_SWITCH    BIT(12)
-+#define PCGCTL_EXTND_HIBER_PWRCLMP    BIT(11)
-+#define PCGCTL_ENBL_EXTND_HIBER        BIT(10)
-+#define PCGCTL_RESTOREMODE        BIT(9)
-+#define PCGCTL_RESETAFTSUSP        BIT(8)
-+#define PCGCTL_DEEP_SLEEP        BIT(7)
-+#define PCGCTL_PHY_IN_SLEEP        BIT(6)
-+#define PCGCTL_ENBL_SLEEP_GATING    BIT(5)
-+#define PCGCTL_RSTPDWNMODULE        BIT(3)
-+#define PCGCTL_PWRCLMP            BIT(2)
-+#define PCGCTL_GATEHCLK            BIT(1)
-+#define PCGCTL_STOPPCLK            BIT(0)
-+
-+#define PCGCCTL1                        HSOTG_REG(0xe04)
-+#define PCGCCTL1_TIMER                  (0x3 << 1)
-+#define PCGCCTL1_GATEEN                 BIT(0)
-+
-+#define EPFIFO(_a)            HSOTG_REG(0x1000 + ((_a) * 0x1000))
-+
-+/* Host Mode Registers */
-+
-+#define HCFG                HSOTG_REG(0x0400)
-+#define HCFG_MODECHTIMEN        BIT(31)
-+#define HCFG_PERSCHEDENA        BIT(26)
-+#define HCFG_FRLISTEN_MASK        (0x3 << 24)
-+#define HCFG_FRLISTEN_SHIFT        24
-+#define HCFG_FRLISTEN_8                (0 << 24)
-+#define FRLISTEN_8_SIZE                8
-+#define HCFG_FRLISTEN_16            BIT(24)
-+#define FRLISTEN_16_SIZE            16
-+#define HCFG_FRLISTEN_32            (2 << 24)
-+#define FRLISTEN_32_SIZE            32
-+#define HCFG_FRLISTEN_64            (3 << 24)
-+#define FRLISTEN_64_SIZE            64
-+#define HCFG_DESCDMA            BIT(23)
-+#define HCFG_RESVALID_MASK        (0xff << 8)
-+#define HCFG_RESVALID_SHIFT        8
-+#define HCFG_ENA32KHZ            BIT(7)
-+#define HCFG_FSLSSUPP            BIT(2)
-+#define HCFG_FSLSPCLKSEL_MASK        (0x3 << 0)
-+#define HCFG_FSLSPCLKSEL_SHIFT        0
-+#define HCFG_FSLSPCLKSEL_30_60_MHZ    0
-+#define HCFG_FSLSPCLKSEL_48_MHZ        1
-+#define HCFG_FSLSPCLKSEL_6_MHZ        2
-+
-+#define HFIR                HSOTG_REG(0x0404)
-+#define HFIR_FRINT_MASK            (0xffff << 0)
-+#define HFIR_FRINT_SHIFT        0
-+#define HFIR_RLDCTRL            BIT(16)
-+
-+#define HFNUM                HSOTG_REG(0x0408)
-+#define HFNUM_FRREM_MASK        (0xffff << 16)
-+#define HFNUM_FRREM_SHIFT        16
-+#define HFNUM_FRNUM_MASK        (0xffff << 0)
-+#define HFNUM_FRNUM_SHIFT        0
-+#define HFNUM_MAX_FRNUM            0x3fff
-+
-+#define HPTXSTS                HSOTG_REG(0x0410)
-+#define TXSTS_QTOP_ODD            BIT(31)
-+#define TXSTS_QTOP_CHNEP_MASK        (0xf << 27)
-+#define TXSTS_QTOP_CHNEP_SHIFT        27
-+#define TXSTS_QTOP_TOKEN_MASK        (0x3 << 25)
-+#define TXSTS_QTOP_TOKEN_SHIFT        25
-+#define TXSTS_QTOP_TERMINATE        BIT(24)
-+#define TXSTS_QSPCAVAIL_MASK        (0xff << 16)
-+#define TXSTS_QSPCAVAIL_SHIFT        16
-+#define TXSTS_FSPCAVAIL_MASK        (0xffff << 0)
-+#define TXSTS_FSPCAVAIL_SHIFT        0
-+
-+#define HAINT                HSOTG_REG(0x0414)
-+#define HAINTMSK            HSOTG_REG(0x0418)
-+#define HFLBADDR            HSOTG_REG(0x041c)
-+
-+#define HPRT0                HSOTG_REG(0x0440)
-+#define HPRT0_SPD_MASK            (0x3 << 17)
-+#define HPRT0_SPD_SHIFT            17
-+#define HPRT0_SPD_HIGH_SPEED        0
-+#define HPRT0_SPD_FULL_SPEED        1
-+#define HPRT0_SPD_LOW_SPEED        2
-+#define HPRT0_TSTCTL_MASK        (0xf << 13)
-+#define HPRT0_TSTCTL_SHIFT        13
-+#define HPRT0_PWR            BIT(12)
-+#define HPRT0_LNSTS_MASK        (0x3 << 10)
-+#define HPRT0_LNSTS_SHIFT        10
-+#define HPRT0_RST            BIT(8)
-+#define HPRT0_SUSP            BIT(7)
-+#define HPRT0_RES            BIT(6)
-+#define HPRT0_OVRCURRCHG        BIT(5)
-+#define HPRT0_OVRCURRACT        BIT(4)
-+#define HPRT0_ENACHG            BIT(3)
-+#define HPRT0_ENA            BIT(2)
-+#define HPRT0_CONNDET            BIT(1)
-+#define HPRT0_CONNSTS            BIT(0)
-+
-+#define HCCHAR(_ch)            HSOTG_REG(0x0500 + 0x20 * (_ch))
-+#define HCCHAR_CHENA            BIT(31)
-+#define HCCHAR_CHDIS            BIT(30)
-+#define HCCHAR_ODDFRM            BIT(29)
-+#define HCCHAR_DEVADDR_MASK        (0x7f << 22)
-+#define HCCHAR_DEVADDR_SHIFT        22
-+#define HCCHAR_MULTICNT_MASK        (0x3 << 20)
-+#define HCCHAR_MULTICNT_SHIFT        20
-+#define HCCHAR_EPTYPE_MASK        (0x3 << 18)
-+#define HCCHAR_EPTYPE_SHIFT        18
-+#define HCCHAR_LSPDDEV            BIT(17)
-+#define HCCHAR_EPDIR            BIT(15)
-+#define HCCHAR_EPNUM_MASK        (0xf << 11)
-+#define HCCHAR_EPNUM_SHIFT        11
-+#define HCCHAR_MPS_MASK            (0x7ff << 0)
-+#define HCCHAR_MPS_SHIFT        0
-+
-+#define HCSPLT(_ch)            HSOTG_REG(0x0504 + 0x20 * (_ch))
-+#define HCSPLT_SPLTENA            BIT(31)
-+#define HCSPLT_COMPSPLT            BIT(16)
-+#define HCSPLT_XACTPOS_MASK        (0x3 << 14)
-+#define HCSPLT_XACTPOS_SHIFT        14
-+#define HCSPLT_XACTPOS_MID        0
-+#define HCSPLT_XACTPOS_END        1
-+#define HCSPLT_XACTPOS_BEGIN        2
-+#define HCSPLT_XACTPOS_ALL        3
-+#define HCSPLT_HUBADDR_MASK        (0x7f << 7)
-+#define HCSPLT_HUBADDR_SHIFT        7
-+#define HCSPLT_PRTADDR_MASK        (0x7f << 0)
-+#define HCSPLT_PRTADDR_SHIFT        0
-+
-+#define HCINT(_ch)            HSOTG_REG(0x0508 + 0x20 * (_ch))
-+#define HCINTMSK(_ch)            HSOTG_REG(0x050c + 0x20 * (_ch))
-+#define HCINTMSK_RESERVED14_31        (0x3ffff << 14)
-+#define HCINTMSK_FRM_LIST_ROLL        BIT(13)
-+#define HCINTMSK_XCS_XACT        BIT(12)
-+#define HCINTMSK_BNA            BIT(11)
-+#define HCINTMSK_DATATGLERR        BIT(10)
-+#define HCINTMSK_FRMOVRUN        BIT(9)
-+#define HCINTMSK_BBLERR            BIT(8)
-+#define HCINTMSK_XACTERR        BIT(7)
-+#define HCINTMSK_NYET            BIT(6)
-+#define HCINTMSK_ACK            BIT(5)
-+#define HCINTMSK_NAK            BIT(4)
-+#define HCINTMSK_STALL            BIT(3)
-+#define HCINTMSK_AHBERR            BIT(2)
-+#define HCINTMSK_CHHLTD            BIT(1)
-+#define HCINTMSK_XFERCOMPL        BIT(0)
-+
-+#define HCTSIZ(_ch)            HSOTG_REG(0x0510 + 0x20 * (_ch))
-+#define TSIZ_DOPNG            BIT(31)
-+#define TSIZ_SC_MC_PID_MASK        (0x3 << 29)
-+#define TSIZ_SC_MC_PID_SHIFT        29
-+#define TSIZ_SC_MC_PID_DATA0        0
-+#define TSIZ_SC_MC_PID_DATA2        1
-+#define TSIZ_SC_MC_PID_DATA1        2
-+#define TSIZ_SC_MC_PID_MDATA        3
-+#define TSIZ_SC_MC_PID_SETUP        3
-+#define TSIZ_PKTCNT_MASK        (0x3ff << 19)
-+#define TSIZ_PKTCNT_SHIFT        19
-+#define TSIZ_NTD_MASK            (0xff << 8)
-+#define TSIZ_NTD_SHIFT            8
-+#define TSIZ_SCHINFO_MASK        (0xff << 0)
-+#define TSIZ_SCHINFO_SHIFT        0
-+#define TSIZ_XFERSIZE_MASK        (0x7ffff << 0)
-+#define TSIZ_XFERSIZE_SHIFT        0
-+
-+#define HCDMA(_ch)            HSOTG_REG(0x0514 + 0x20 * (_ch))
-+
-+#define HCDMAB(_ch)            HSOTG_REG(0x051c + 0x20 * (_ch))
-+
-+#define HCFIFO(_ch)            HSOTG_REG(0x1000 + 0x1000 * (_ch))
-+
-+/**
-+ * struct dwc2_dma_desc - DMA descriptor structure,
-+ * used for both host and gadget modes
-+ *
-+ * @status: DMA descriptor status quadlet
-+ * @buf:    DMA descriptor data buffer pointer
-+ *
-+ * DMA Descriptor structure contains two quadlets:
-+ * Status quadlet and Data buffer pointer.
-+ */
-+struct dwc2_dma_desc {
-+    uint32_t status;
-+    uint32_t buf;
-+} __packed;
-+
-+/* Host Mode DMA descriptor status quadlet */
-+
-+#define HOST_DMA_A            BIT(31)
-+#define HOST_DMA_STS_MASK        (0x3 << 28)
-+#define HOST_DMA_STS_SHIFT        28
-+#define HOST_DMA_STS_PKTERR        BIT(28)
-+#define HOST_DMA_EOL            BIT(26)
-+#define HOST_DMA_IOC            BIT(25)
-+#define HOST_DMA_SUP            BIT(24)
-+#define HOST_DMA_ALT_QTD        BIT(23)
-+#define HOST_DMA_QTD_OFFSET_MASK    (0x3f << 17)
-+#define HOST_DMA_QTD_OFFSET_SHIFT    17
-+#define HOST_DMA_ISOC_NBYTES_MASK    (0xfff << 0)
-+#define HOST_DMA_ISOC_NBYTES_SHIFT    0
-+#define HOST_DMA_NBYTES_MASK        (0x1ffff << 0)
-+#define HOST_DMA_NBYTES_SHIFT        0
-+#define HOST_DMA_NBYTES_LIMIT        131071
-+
-+/* Device Mode DMA descriptor status quadlet */
-+
-+#define DEV_DMA_BUFF_STS_MASK        (0x3 << 30)
-+#define DEV_DMA_BUFF_STS_SHIFT        30
-+#define DEV_DMA_BUFF_STS_HREADY        0
-+#define DEV_DMA_BUFF_STS_DMABUSY    1
-+#define DEV_DMA_BUFF_STS_DMADONE    2
-+#define DEV_DMA_BUFF_STS_HBUSY        3
-+#define DEV_DMA_STS_MASK        (0x3 << 28)
-+#define DEV_DMA_STS_SHIFT        28
-+#define DEV_DMA_STS_SUCC        0
-+#define DEV_DMA_STS_BUFF_FLUSH        1
-+#define DEV_DMA_STS_BUFF_ERR        3
-+#define DEV_DMA_L            BIT(27)
-+#define DEV_DMA_SHORT            BIT(26)
-+#define DEV_DMA_IOC            BIT(25)
-+#define DEV_DMA_SR            BIT(24)
-+#define DEV_DMA_MTRF            BIT(23)
-+#define DEV_DMA_ISOC_PID_MASK        (0x3 << 23)
-+#define DEV_DMA_ISOC_PID_SHIFT        23
-+#define DEV_DMA_ISOC_PID_DATA0        0
-+#define DEV_DMA_ISOC_PID_DATA2        1
-+#define DEV_DMA_ISOC_PID_DATA1        2
-+#define DEV_DMA_ISOC_PID_MDATA        3
-+#define DEV_DMA_ISOC_FRNUM_MASK        (0x7ff << 12)
-+#define DEV_DMA_ISOC_FRNUM_SHIFT    12
-+#define DEV_DMA_ISOC_TX_NBYTES_MASK    (0xfff << 0)
-+#define DEV_DMA_ISOC_TX_NBYTES_LIMIT    0xfff
-+#define DEV_DMA_ISOC_RX_NBYTES_MASK    (0x7ff << 0)
-+#define DEV_DMA_ISOC_RX_NBYTES_LIMIT    0x7ff
-+#define DEV_DMA_ISOC_NBYTES_SHIFT    0
-+#define DEV_DMA_NBYTES_MASK        (0xffff << 0)
-+#define DEV_DMA_NBYTES_SHIFT        0
-+#define DEV_DMA_NBYTES_LIMIT        0xffff
-+
-+#define MAX_DMA_DESC_NUM_GENERIC    64
-+#define MAX_DMA_DESC_NUM_HS_ISOC    256
-+
-+#endif /* __DWC2_HW_H__ */
---
-.20.1

-[PULL 26/29] target/arm: Convert Neon narrowing shifts with op==9 to decodetree
+[PULL 23/24] target/arm: Implement MVE shifts by immediate
-Convert the remaining Neon narrowing shifts to decodetree:
+Implement the MVE shifts by immediate, which perform shifts
-  * VQSHRN
+on a single general-purpose register.
-  * VQRSHRN
 These patterns overlap with the long-shift-by-immediates,
 so we have to rearrange the grouping a little here.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200522145520.6778-7-peter.maydell@linaro.org
+Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       |  20 ++++++
+ target/arm/helper-mve.h |  3 ++
- target/arm/translate-neon.inc.c |  15 +++++
+ target/arm/translate.h  |  1 +
- target/arm/translate.c          | 110 +-------------------------------
+ target/arm/t32.decode   | 31 ++++++++++++++-----
-files changed, 37 insertions(+), 108 deletions(-)
+ target/arm/mve_helper.c | 10 ++++++
+ target/arm/translate.c  | 68 +++++++++++++++++++++++++++++++++++++++--
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
+files changed, 104 insertions(+), 9 deletions(-)
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
-+++ b/target/arm/neon-dp.decode
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ VQSHRUN_16_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
+--- a/target/arm/helper-mve.h
- VQRSHRUN_64_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
++++ b/target/arm/helper-mve.h
- VQRSHRUN_32_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
- VQRSHRUN_16_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
+ DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+
+ DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+# VQSHRN with signed input
+ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+VQSHRN_S64_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
++
-+VQSHRN_S32_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
++DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
-+VQSHRN_S16_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
++DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
-+
+diff --git a/target/arm/translate.h b/target/arm/translate.h
-+# VQRSHRN with signed input
+index XXXXXXX..XXXXXXX 100644
-+VQRSHRN_S64_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
+--- a/target/arm/translate.h
-+VQRSHRN_S32_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
++++ b/target/arm/translate.h
-+VQRSHRN_S16_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
+@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
-+
+ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
-+# VQSHRN with unsigned input
+ typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
-+VQSHRN_U64_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
+ typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
-+VQSHRN_U32_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
++typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
-+VQSHRN_U16_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
-+
+ /**
-+# VQRSHRN with unsigned input
+  * arm_tbflags_from_tb:
-+VQRSHRN_U64_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
+diff --git a/target/arm/t32.decode b/target/arm/t32.decode
-+VQRSHRN_U32_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
+index XXXXXXX..XXXXXXX 100644
-+VQRSHRN_U16_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
+--- a/target/arm/t32.decode
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
++++ b/target/arm/t32.decode
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
+ &mve_shl_ri      rdalo rdahi shim
-@@ -XXX,XX +XXX,XX @@ DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat8)
+ &mve_shl_rr      rdalo rdahi rm
- DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_sat32)
++&mve_sh_ri       rda shim
- DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_sat16)
- DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_sat8)
+ # rdahi: bits [3:1] from insn, bit 0 is 1
-+DO_2SN_64(VQSHRN_S64, gen_sshl_i64, gen_helper_neon_narrow_sat_s32)
+ # rdalo: bits [3:1] from insn, bit 0 is 0
-+DO_2SN_32(VQSHRN_S32, gen_sshl_i32, gen_helper_neon_narrow_sat_s16)
+@@ -XXX,XX +XXX,XX @@
-+DO_2SN_32(VQSHRN_S16, gen_helper_neon_shl_s16, gen_helper_neon_narrow_sat_s8)
+                  &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
-+
+ @mve_shl_rr      ....... .... . ... . rm:4  ... . .. .. .... \
-+DO_2SN_64(VQRSHRN_S64, gen_helper_neon_rshl_s64, gen_helper_neon_narrow_sat_s32)
+                  &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
-+DO_2SN_32(VQRSHRN_S32, gen_helper_neon_rshl_s32, gen_helper_neon_narrow_sat_s16)
++@mve_sh_ri       ....... .... . rda:4 . ... ... . .. .. .... \
-+DO_2SN_32(VQRSHRN_S16, gen_helper_neon_rshl_s16, gen_helper_neon_narrow_sat_s8)
++                 &mve_sh_ri shim=%imm5_12_6
-+
-+DO_2SN_64(VQSHRN_U64, gen_ushl_i64, gen_helper_neon_narrow_sat_u32)
+ {
-+DO_2SN_32(VQSHRN_U32, gen_ushl_i32, gen_helper_neon_narrow_sat_u16)
+   TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
-+DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_u8)
+@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
-+
+   # the rest fall through (where ORR_rrri and MOV_rxri will end up
-+DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sat_u32)
+   # handling them as r13 and r15 accesses with the same semantics as A32).
-+DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sat_u16)
+   [
-+DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sat_u8)
+-    LSLL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111  @mve_shl_ri
 -    LSRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111  @mve_shl_ri
 -    ASRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +    {
 +      UQSHL_ri   1110101 0010 1 ....  0 ...  1111 .. 00 1111  @mve_sh_ri
 +      LSLL_ri    1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111  @mve_shl_ri
 +      UQSHLL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111  @mve_shl_ri
 +    }
 -    UQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111  @mve_shl_ri
 -    URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
 -    SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
 -    SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
 +    {
 +      URSHR_ri   1110101 0010 1 ....  0 ...  1111 .. 01 1111  @mve_sh_ri
 +      LSRL_ri    1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111  @mve_shl_ri
 +      URSHRL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
 +    }
 +
 +    {
 +      SRSHR_ri   1110101 0010 1 ....  0 ...  1111 .. 10 1111  @mve_sh_ri
 +      ASRL_ri    1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +      SRSHRL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +    }
 +
 +    {
 +      SQSHL_ri   1110101 0010 1 ....  0 ...  1111 .. 11 1111  @mve_sh_ri
 +      SQSHLL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
 +    }
      LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
      ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
  {
      return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
  }
 +
 +uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
 +{
 +    return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
 +}
 +
 +uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
 +{
 +    return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static inline void gen_neon_unarrow_sats(int size, TCGv_i32 dest, TCGv_i64 src)
+@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
-     }
  static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
  {
 -    TCGv_i32 t = tcg_temp_new_i32();
 +    TCGv_i32 t;
 +    /* Handle shift by the input size for the benefit of trans_SRSHR_ri */
 +    if (sh == 32) {
 +        tcg_gen_movi_i32(d, 0);
 +        return;
 +    }
 +    t = tcg_temp_new_i32();
      tcg_gen_extract_i32(t, a, sh - 1, 1);
      tcg_gen_sari_i32(d, a, sh);
      tcg_gen_add_i32(d, d, t);
@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
  static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
  {
 -    TCGv_i32 t = tcg_temp_new_i32();
 +    TCGv_i32 t;
 +    /* Handle shift by the input size for the benefit of trans_URSHR_ri */
 +    if (sh == 32) {
 +        tcg_gen_extract_i32(d, a, sh - 1, 1);
 +        return;
 +    }
 +    t = tcg_temp_new_i32();
      tcg_gen_extract_i32(t, a, sh - 1, 1);
      tcg_gen_shri_i32(d, a, sh);
      tcg_gen_add_i32(d, d, t);
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
      return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
  }
--static inline void gen_neon_shift_narrow(int size, TCGv_i32 var, TCGv_i32 shift,
++static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)
--                                         int q, int u)
++{
--{
++    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
--    if (q) {
++        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
--        if (u) {
++        return false;
--            switch (size) {
++    }
--            case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
++    if (!dc_isar_feature(aa32_mve, s) ||
--            case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
++        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
--            default: abort();
++        a->rda == 13 || a->rda == 15) {
--            }
++        /* These rda cases are UNPREDICTABLE; we choose to UNDEF */
--        } else {
++        unallocated_encoding(s);
--            switch (size) {
++        return true;
--            case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
++    }
--            case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
++
--            default: abort();
++    if (a->shim == 0) {
--            }
++        a->shim = 32;
--        }
++    }
--    } else {
++    fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);
--        if (u) {
++
--            switch (size) {
++    return true;
--            case 1: gen_helper_neon_shl_u16(var, var, shift); break;
++}
--            case 2: gen_ushl_i32(var, var, shift); break;
++
--            default: abort();
++static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
--            }
++{
--        } else {
++    return do_mve_sh_ri(s, a, gen_urshr32_i32);
--            switch (size) {
++}
--            case 1: gen_helper_neon_shl_s16(var, var, shift); break;
++
--            case 2: gen_sshl_i32(var, var, shift); break;
++static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
--            default: abort();
++{
--            }
++    return do_mve_sh_ri(s, a, gen_srshr32_i32);
--        }
++}
--    }
++
--}
++static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
--
++{
- static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u)
++    gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
- {
++}
-     if (u) {
++
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
++static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
-             case 6: /* VQSHLU */
++{
-             case 7: /* VQSHL */
++    return do_mve_sh_ri(s, a, gen_mve_sqshl);
-             case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
++}
-+            case 9: /* VQSHRN, VQRSHRN */
++
-                 return 1; /* handled by decodetree */
++static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
-             default:
++{
-                 break;
++    gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
++}
-                     size--;
++
-             }
++static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
-             shift = (insn >> 16) & ((1 << (3 + size)) - 1);
++{
--            if (op < 10) {
++    return do_mve_sh_ri(s, a, gen_mve_uqshl);
--                /* Shift by immediate and narrow:
++}
--                   VSHRN, VRSHRN, VQSHRN, VQRSHRN.  */
++
--                int input_unsigned = (op == 8) ? !u : u;
+ /*
--                if (rm & 1) {
+  * Multiply and multiply accumulate
--                    return 1;
+  */
 -                }
 -                shift = shift - (1 << (size + 3));
 -                size++;
 -                if (size == 3) {
 -                    tmp64 = tcg_const_i64(shift);
 -                    neon_load_reg64(cpu_V0, rm);
 -                    neon_load_reg64(cpu_V1, rm + 1);
 -                    for (pass = 0; pass < 2; pass++) {
 -                        TCGv_i64 in;
 -                        if (pass == 0) {
 -                            in = cpu_V0;
 -                        } else {
 -                            in = cpu_V1;
 -                        }
 -                        if (q) {
 -                            if (input_unsigned) {
 -                                gen_helper_neon_rshl_u64(cpu_V0, in, tmp64);
 -                            } else {
 -                                gen_helper_neon_rshl_s64(cpu_V0, in, tmp64);
 -                            }
 -                        } else {
 -                            if (input_unsigned) {
 -                                gen_ushl_i64(cpu_V0, in, tmp64);
 -                            } else {
 -                                gen_sshl_i64(cpu_V0, in, tmp64);
 -                            }
 -                        }
 -                        tmp = tcg_temp_new_i32();
 -                        gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
 -                        neon_store_reg(rd, pass, tmp);
 -                    } /* for pass */
 -                    tcg_temp_free_i64(tmp64);
 -                } else {
 -                    if (size == 1) {
 -                        imm = (uint16_t)shift;
 -                        imm |= imm << 16;
 -                    } else {
 -                        /* size == 2 */
 -                        imm = (uint32_t)shift;
 -                    }
 -                    tmp2 = tcg_const_i32(imm);
 -                    tmp4 = neon_load_reg(rm + 1, 0);
 -                    tmp5 = neon_load_reg(rm + 1, 1);
 -                    for (pass = 0; pass < 2; pass++) {
 -                        if (pass == 0) {
 -                            tmp = neon_load_reg(rm, 0);
 -                        } else {
 -                            tmp = tmp4;
 -                        }
 -                        gen_neon_shift_narrow(size, tmp, tmp2, q,
 -                                              input_unsigned);
 -                        if (pass == 0) {
 -                            tmp3 = neon_load_reg(rm, 1);
 -                        } else {
 -                            tmp3 = tmp5;
 -                        }
 -                        gen_neon_shift_narrow(size, tmp3, tmp2, q,
 -                                              input_unsigned);
 -                        tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
 -                        tcg_temp_free_i32(tmp);
 -                        tcg_temp_free_i32(tmp3);
 -                        tmp = tcg_temp_new_i32();
 -                        gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
 -                        neon_store_reg(rd, pass, tmp);
 -                    } /* for pass */
 -                    tcg_temp_free_i32(tmp2);
 -                }
 -            } else if (op == 10) {
 +            if (op == 10) {
                  /* VSHLL, VMOVL */
                  if (q || (rd & 1)) {
                      return 1;
 --
 .20.1

-[PULL 27/29] target/arm: Convert Neon VSHLL, VMOVL to decodetree
+[PULL 24/24] target/arm: Implement MVE shifts by register
-Convert the VSHLL and VMOVL insns from the 2-reg-shift group
+Implement the MVE shifts by register, which perform
-to decodetree. Since the loop always has two passes, we unroll
+shifts on a single general-purpose register.
 it to avoid the awkward reassignment of one TCGv to another.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200522145520.6778-8-peter.maydell@linaro.org
+Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       | 16 +++++++
+ target/arm/helper-mve.h |  2 ++
- target/arm/translate-neon.inc.c | 81 +++++++++++++++++++++++++++++++++
+ target/arm/translate.h  |  1 +
- target/arm/translate.c          | 46 +------------------
+ target/arm/t32.decode   | 18 ++++++++++++++----
-files changed, 99 insertions(+), 44 deletions(-)
+ target/arm/mve_helper.c | 10 ++++++++++
  target/arm/translate.c  | 30 ++++++++++++++++++++++++++++++
 files changed, 57 insertions(+), 4 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
+--- a/target/arm/helper-mve.h
-+++ b/target/arm/neon-dp.decode
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
-                  &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 \
-                  shift=%neon_rshift_i3
+ DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
+ DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
-+# Long left shifts: again Q is part of opcode decode
++DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
-+@2reg_shll_s     .... ... . . . 1 shift:5    .... .... 0 . . . .... \
++DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
-+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0
+diff --git a/target/arm/translate.h b/target/arm/translate.h
 +@2reg_shll_h     .... ... . . . 01 shift:4   .... .... 0 . . . .... \
 +                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0
 +@2reg_shll_b     .... ... . . . 001 shift:3  .... .... 0 . . . .... \
 +                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
 +
  VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
  VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
  VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
@@ -XXX,XX +XXX,XX @@ VQSHRN_U16_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
  VQRSHRN_U64_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
  VQRSHRN_U32_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
  VQRSHRN_U16_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
 +
 +VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
 +VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
 +VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
 +
 +VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
 +VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
 +VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
+--- a/target/arm/translate.h
-+++ b/target/arm/translate-neon.inc.c
++++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_u8)
+@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
- DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sat_u32)
+ typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
- DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sat_u16)
+ typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
- DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sat_u8)
+ typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
-+
++typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
-+static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
-+                         NeonGenWidenFn *widenfn, bool u)
+ /**
-+{
+  * arm_tbflags_from_tb:
-+    TCGv_i64 tmp;
+diff --git a/target/arm/t32.decode b/target/arm/t32.decode
-+    TCGv_i32 rm0, rm1;
+index XXXXXXX..XXXXXXX 100644
-+    uint64_t widen_mask = 0;
+--- a/target/arm/t32.decode
-+
++++ b/target/arm/t32.decode
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+@@ -XXX,XX +XXX,XX @@
-+        return false;
+ &mve_shl_ri      rdalo rdahi shim
  &mve_shl_rr      rdalo rdahi rm
  &mve_sh_ri       rda shim
 +&mve_sh_rr       rda rm
  # rdahi: bits [3:1] from insn, bit 0 is 1
  # rdalo: bits [3:1] from insn, bit 0 is 0
@@ -XXX,XX +XXX,XX @@
                   &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
  @mve_sh_ri       ....... .... . rda:4 . ... ... . .. .. .... \
                   &mve_sh_ri shim=%imm5_12_6
 +@mve_sh_rr       ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
  {
    TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
        SQSHLL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
      }
 -    LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
 -    ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
 -    UQRSHLL64_rr 1110101 0010 1 ... 1 ....  ... 1  0000 1101  @mve_shl_rr
 -    SQRSHRL64_rr 1110101 0010 1 ... 1 ....  ... 1  0010 1101  @mve_shl_rr
 +    {
 +      UQRSHL_rr    1110101 0010 1 ....  ....  1111 0000 1101  @mve_sh_rr
 +      LSLL_rr      1110101 0010 1 ... 0 .... ... 1 0000 1101  @mve_shl_rr
 +      UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101  @mve_shl_rr
 +    }
 +
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
++    {
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
++      SQRSHR_rr    1110101 0010 1 ....  ....  1111 0010 1101  @mve_sh_rr
-+        ((a->vd | a->vm) & 0x10)) {
++      ASRL_rr      1110101 0010 1 ... 0 .... ... 1 0010 1101  @mve_shl_rr
-+        return false;
++      SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101  @mve_shl_rr
 +    }
 +
-+    if (a->vd & 1) {
+     UQRSHLL48_rr 1110101 0010 1 ... 1 ....  ... 1  1000 1101  @mve_shl_rr
-+        return false;
+     SQRSHRL48_rr 1110101 0010 1 ... 1 ....  ... 1  1010 1101  @mve_shl_rr
-+    }
+   ]
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
  {
      return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
  }
 +
-+    if (!vfp_access_check(s)) {
++uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
-+        return true;
++{
-+    }
++    return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
 +
 +    /*
 +     * This is a widen-and-shift operation. The shift is always less
 +     * than the width of the source type, so after widening the input
 +     * vector we can simply shift the whole 64-bit widened register,
 +     * and then clear the potential overflow bits resulting from left
 +     * bits of the narrow input appearing as right bits of the left
 +     * neighbour narrow input. Calculate a mask of bits to clear.
 +     */
 +    if ((a->shift != 0) && (a->size < 2 || u)) {
 +        int esize = 8 << a->size;
 +        widen_mask = MAKE_64BIT_MASK(0, esize);
 +        widen_mask >>= esize - a->shift;
 +        widen_mask = dup_const(a->size + 1, widen_mask);
 +    }
 +
 +    rm0 = neon_load_reg(a->vm, 0);
 +    rm1 = neon_load_reg(a->vm, 1);
 +    tmp = tcg_temp_new_i64();
 +
 +    widenfn(tmp, rm0);
 +    if (a->shift != 0) {
 +        tcg_gen_shli_i64(tmp, tmp, a->shift);
 +        tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
 +    }
 +    neon_store_reg64(tmp, a->vd);
 +
 +    widenfn(tmp, rm1);
 +    if (a->shift != 0) {
 +        tcg_gen_shli_i64(tmp, tmp, a->shift);
 +        tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
 +    }
 +    neon_store_reg64(tmp, a->vd + 1);
 +    tcg_temp_free_i64(tmp);
 +    return true;
 +}
 +
-+static bool trans_VSHLL_S_2sh(DisasContext *s, arg_2reg_shift *a)
++uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
 +{
-+    NeonGenWidenFn *widenfn[] = {
++    return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
 +        gen_helper_neon_widen_s8,
 +        gen_helper_neon_widen_s16,
 +        tcg_gen_ext_i32_i64,
 +    };
 +    return do_vshll_2sh(s, a, widenfn[a->size], false);
 +}
 +
 +static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a)
 +{
 +    NeonGenWidenFn *widenfn[] = {
 +        gen_helper_neon_widen_u8,
 +        gen_helper_neon_widen_u16,
 +        tcg_gen_extu_i32_i64,
 +    };
 +    return do_vshll_2sh(s, a, widenfn[a->size], true);
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
-             case 7: /* VQSHL */
+     return do_mve_sh_ri(s, a, gen_mve_uqshl);
-             case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
+ }
-             case 9: /* VQSHRN, VQRSHRN */
-+            case 10: /* VSHLL, including VMOVL */
++static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
-                 return 1; /* handled by decodetree */
++{
-             default:
++    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
-                 break;
++        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
++        return false;
-                     size--;
++    }
-             }
++    if (!dc_isar_feature(aa32_mve, s) ||
-             shift = (insn >> 16) & ((1 << (3 + size)) - 1);
++        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
--            if (op == 10) {
++        a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||
--                /* VSHLL, VMOVL */
++        a->rm == a->rda) {
--                if (q || (rd & 1)) {
++        /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */
--                    return 1;
++        unallocated_encoding(s);
--                }
++        return true;
--                tmp = neon_load_reg(rm, 0);
++    }
--                tmp2 = neon_load_reg(rm, 1);
++
--                for (pass = 0; pass < 2; pass++) {
++    /* The helper takes care of the sign-extension of the low 8 bits of Rm */
--                    if (pass == 1)
++    fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
--                        tmp = tmp2;
++    return true;
--
++}
--                    gen_neon_widen(cpu_V0, tmp, size, u);
++
--
++static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)
--                    if (shift != 0) {
++{
--                        /* The shift is less than the width of the source
++    return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);
--                           type, so we can just shift the whole register.  */
++}
--                        tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
++
--                        /* Widen the result of shift: we need to clear
++static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)
--                         * the potential overflow bits resulting from
++{
--                         * left bits of the narrow input appearing as
++    return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);
--                         * right bits of left the neighbour narrow
++}
--                         * input.  */
++
--                        if (size < 2 || !u) {
+ /*
--                            uint64_t imm64;
+  * Multiply and multiply accumulate
--                            if (size == 0) {
+  */
 -                                imm = (0xffu >> (8 - shift));
 -                                imm |= imm << 16;
 -                            } else if (size == 1) {
 -                                imm = 0xffff >> (16 - shift);
 -                            } else {
 -                                /* size == 2 */
 -                                imm = 0xffffffff >> (32 - shift);
 -                            }
 -                            if (size < 2) {
 -                                imm64 = imm | (((uint64_t)imm) << 32);
 -                            } else {
 -                                imm64 = imm;
 -                            }
 -                            tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64);
 -                        }
 -                    }
 -                    neon_store_reg64(cpu_V0, rd + pass);
 -                }
 -            } else if (op >= 14) {
 +            if (op >= 14) {
                  /* VCVT fixed-point.  */
                  TCGv_ptr fpst;
                  TCGv_i32 shiftv;
 --
 .20.1

Arm queue; some of the simpler stuff, things other have reviewed (thanks!), etc.

-- PMM

The following changes since commit 5d2f557b47dfbf8f23277a5bdd8473d4607c681a:

Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200605-pull-request' into staging (2020-06-05 13:53:05 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200605

for you to fetch changes up to 2c35a39eda0b16c2ed85c94cec204bf5efb97812:

target/arm: Convert Neon one-register-and-immediate insns to decodetree (2020-06-05 17:23:10 +0100)

----------------------------------------------------------------
target-arm queue:
 hw/ssi/imx_spi: Handle tx burst lengths other than 8 correctly
 hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()
 hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()
 target/arm: Convert crypto insns to gvec
 hw/adc/stm32f2xx_adc: Correct memory region size and access size
 tests/acceptance: Add a boot test for the xlnx-versal-virt machine
 docs/system: Document Aspeed boards
 raspi: Add model of the USB controller
 target/arm: Convert 2-reg-and-shift and 1-reg-imm Neon insns to decodetree

----------------------------------------------------------------
Cédric Le Goater (1):
      docs/system: Document Aspeed boards

Eden Mikitas (2):
      hw/ssi/imx_spi: changed while statement to prevent underflow
      hw/ssi/imx_spi: Removed unnecessary cast of rx data received from slave

Paul Zimmerman (7):
      raspi: add BCM2835 SOC MPHI emulation
      dwc-hsotg (dwc2) USB host controller register definitions
      dwc-hsotg (dwc2) USB host controller state definitions
      dwc-hsotg (dwc2) USB host controller emulation
      usb: add short-packet handling to usb-storage driver
      wire in the dwc-hsotg (dwc2) USB host controller emulation
      raspi2 acceptance test: add test for dwc-hsotg (dwc2) USB host

Peter Maydell (9):
      target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree
      target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree
      target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree
      target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree
      target/arm: Convert Neon narrowing shifts with op==8 to decodetree
      target/arm: Convert Neon narrowing shifts with op==9 to decodetree
      target/arm: Convert Neon VSHLL, VMOVL to decodetree
      target/arm: Convert VCVT fixed-point ops to decodetree
      target/arm: Convert Neon one-register-and-immediate insns to decodetree

Philippe Mathieu-Daudé (3):
      hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()
      hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()
      hw/adc/stm32f2xx_adc: Correct memory region size and access size

Richard Henderson (6):
      target/arm: Convert aes and sm4 to gvec helpers
      target/arm: Convert rax1 to gvec helpers
      target/arm: Convert sha512 and sm3 to gvec helpers
      target/arm: Convert sha1 and sha256 to gvec helpers
      target/arm: Split helper_crypto_sha1_3reg
      target/arm: Split helper_crypto_sm3tt

Thomas Huth (1):
      tests/acceptance: Add a boot test for the xlnx-versal-virt machine

docs/system/arm/aspeed.rst             |   85 ++
 docs/system/target-arm.rst             |    1 +
 hw/usb/hcd-dwc2.h                      |  190 +++++
 include/hw/arm/bcm2835_peripherals.h   |    5 +-
 include/hw/misc/bcm2835_mphi.h         |   44 +
 include/hw/usb/dwc2-regs.h             |  899 ++++++++++++++++++++
 target/arm/helper.h                    |   45 +-
 target/arm/translate-a64.h             |    3 +
 target/arm/vec_internal.h              |   33 +
 target/arm/neon-dp.decode              |  214 ++++-
 hw/adc/stm32f2xx_adc.c                 |    4 +-
 hw/arm/bcm2835_peripherals.c           |   38 +-
 hw/arm/pxa2xx.c                        |   66 +-
 hw/input/pxa2xx_keypad.c               |   10 +-
 hw/misc/bcm2835_mphi.c                 |  191 +++++
 hw/ssi/imx_spi.c                       |    4 +-
 hw/usb/dev-storage.c                   |   15 +-
 hw/usb/hcd-dwc2.c                      | 1417 ++++++++++++++++++++++++++++++++
 target/arm/crypto_helper.c             |  267 ++++--
 target/arm/translate-a64.c             |  198 ++---
 target/arm/translate-neon.inc.c        |  796 ++++++++++++++----
 target/arm/translate.c                 |  539 +-----------
 target/arm/vec_helper.c                |   12 +-
 hw/misc/Makefile.objs                  |    1 +
 hw/usb/Kconfig                         |    5 +
 hw/usb/Makefile.objs                   |    1 +
 hw/usb/trace-events                    |   50 ++
 tests/acceptance/boot_linux_console.py |   35 +-
 28 files changed, 4258 insertions(+), 910 deletions(-)
 create mode 100644 docs/system/arm/aspeed.rst
 create mode 100644 hw/usb/hcd-dwc2.h
 create mode 100644 include/hw/misc/bcm2835_mphi.h
 create mode 100644 include/hw/usb/dwc2-regs.h
 create mode 100644 target/arm/vec_internal.h
 create mode 100644 hw/misc/bcm2835_mphi.c
 create mode 100644 hw/usb/hcd-dwc2.c

From: Eden Mikitas <e.mikitas@gmail.com>

When inserting the value retrieved (rx) from the spi slave, rx is pushed to
rx_fifo after being cast to uint8_t. rx_fifo is a fifo32, and the rx
register the driver uses is also 32 bit. This zeroes the 24 most
significant bits of rx. This proved problematic with devices that expect to
use the whole 32 bits of the rx register.

Signed-off-by: Eden Mikitas <e.mikitas@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/ssi/imx_spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
         if (fifo32_is_full(&s->rx_fifo)) {
             s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RO;
         } else {
-            fifo32_push(&s->rx_fifo, (uint8_t)rx);
+            fifo32_push(&s->rx_fifo, rx);
         }
 
         if (s->burst_length <= 0) {
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

hw_error() calls exit(). This a bit overkill when we can log
the accesses as unimplemented or guest error.

When fuzzing the devices, we don't want the whole process to
exit. Replace some hw_error() calls by qemu_log_mask()
(missed in commit 5a0001ec7e).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200525114123.21317-2-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/input/pxa2xx_keypad.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/input/pxa2xx_keypad.c b/hw/input/pxa2xx_keypad.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/input/pxa2xx_keypad.c
+++ b/hw/input/pxa2xx_keypad.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
-#include "hw/hw.h"
+#include "qemu/log.h"
 #include "hw/irq.h"
 #include "migration/vmstate.h"
 #include "hw/arm/pxa.h"
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_keypad_read(void *opaque, hwaddr offset,
         return s->kpkdi;
         break;
     default:
-        hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+                      __func__, offset);
     }
 
     return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_keypad_write(void *opaque, hwaddr offset,
         break;
 
     default:
-        hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+                      __func__, offset);
     }
 }
 
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Replace printf() calls by qemu_log_mask(), which is disabled
by default. This avoid flooding the terminal when fuzzing the
device.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200525114123.21317-3-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/pxa2xx.c | 66 ++++++++++++++++++++++++++++++++++++-------------
 1 file changed, 49 insertions(+), 17 deletions(-)

diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/blockdev.h"
 #include "sysemu/qtest.h"
 #include "qemu/cutils.h"
+#include "qemu/log.h"
 
 static struct {
     hwaddr io_base;
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
         return s->pm_regs[addr >> 2];
     default:
     fail:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_pm_write(void *opaque, hwaddr addr,
             s->pm_regs[addr >> 2] = value;
             break;
         }
-
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
         return s->cm_regs[CCCR >> 2] | (3 << 28);
 
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_cm_write(void *opaque, hwaddr addr,
         break;
 
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
             return s->mm_regs[addr >> 2];
         /* fall through */
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_mm_write(void *opaque, hwaddr addr,
         }
 
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
     case SSACD:
         return s->ssacd;
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
         break;
 
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
         else
             return s->last_swcr;
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
         break;
 
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
             s->ibmr = 0;
         return s->ibmr;
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
         break;
 
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
         }
         return 0;
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
         }
         break;
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
     case ICFOR:
         return s->rx_len;
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
         break;
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_fir_write(void *opaque, hwaddr addr,
     case ICFOR:
         break;
     default:
-        printf("%s: Bad register " REG_FMT "\n", __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
     }
 }
 
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

With this conversion, we will be able to use the same helpers
with sve.  In particular, pass 3 vector parameters for the
3-operand operations; for advsimd the destination register
is also an input.

This also fixes a bug in which we failed to clear the high bits
of the SVE register after an AdvSIMD operation.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h        |  6 ++--
 target/arm/vec_internal.h  | 33 +++++++++++++++++
 target/arm/crypto_helper.c | 72 +++++++++++++++++++++++++++-----------
 target/arm/translate-a64.c | 55 ++++++++++++++++++-----------
 target/arm/translate.c     | 27 +++++++-------
 target/arm/vec_helper.c    | 12 +------
 6 files changed, 138 insertions(+), 67 deletions(-)
 create mode 100644 target/arm/vec_internal.h

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(neon_qzip8, TCG_CALL_NO_RWG, void, ptr, ptr)
 DEF_HELPER_FLAGS_2(neon_qzip16, TCG_CALL_NO_RWG, void, ptr, ptr)
 DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr)
 
-DEF_HELPER_FLAGS_3(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 
 DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32, i32)
 DEF_HELPER_FLAGS_3(crypto_sm3partw1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
 DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
 
-DEF_HELPER_FLAGS_2(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr)
-DEF_HELPER_FLAGS_3(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 
 DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
 DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/vec_internal.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * ARM AdvSIMD / SVE Vector Helpers
+ *
+ * Copyright (c) 2020 Linaro
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARM_VEC_INTERNALS_H
+#define TARGET_ARM_VEC_INTERNALS_H
+
+static inline void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
+{
+    uint64_t *d = vd + opr_sz;
+    uintptr_t i;
+
+    for (i = opr_sz; i < max_sz; i += 8) {
+        *d++ = 0;
+    }
+}
+
+#endif /* TARGET_ARM_VEC_INTERNALS_H */
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/crypto_helper.c
+++ b/target/arm/crypto_helper.c
@@ -XXX,XX +XXX,XX @@
 
 #include "cpu.h"
 #include "exec/helper-proto.h"
+#include "tcg/tcg-gvec-desc.h"
 #include "crypto/aes.h"
+#include "vec_internal.h"
 
 union CRYPTO_STATE {
     uint8_t    bytes[16];
@@ -XXX,XX +XXX,XX @@ union CRYPTO_STATE {
 #define CR_ST_WORD(state, i)   (state.words[i])
 #endif
 
-void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt)
+static void do_crypto_aese(uint64_t *rd, uint64_t *rn,
+                           uint64_t *rm, bool decrypt)
 {
     static uint8_t const * const sbox[2] = { AES_sbox, AES_isbox };
     static uint8_t const * const shift[2] = { AES_shifts, AES_ishifts };
-    uint64_t *rd = vd;
-    uint64_t *rm = vm;
     union CRYPTO_STATE rk = { .l = { rm[0], rm[1] } };
-    union CRYPTO_STATE st = { .l = { rd[0], rd[1] } };
+    union CRYPTO_STATE st = { .l = { rn[0], rn[1] } };
     int i;
 
-    assert(decrypt < 2);
-
     /* xor state vector with round key */
     rk.l[0] ^= st.l[0];
     rk.l[1] ^= st.l[1];
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt)
     rd[1] = st.l[1];
 }
 
-void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)
+void HELPER(crypto_aese)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+    intptr_t i, opr_sz = simd_oprsz(desc);
+    bool decrypt = simd_data(desc);
+
+    for (i = 0; i < opr_sz; i += 16) {
+        do_crypto_aese(vd + i, vn + i, vm + i, decrypt);
+    }
+    clear_tail(vd, opr_sz, simd_maxsz(desc));
+}
+
+static void do_crypto_aesmc(uint64_t *rd, uint64_t *rm, bool decrypt)
 {
     static uint32_t const mc[][256] = { {
         /* MixColumns lookup table */
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)
         0xbe805d9f, 0xb58d5491, 0xa89a4f83, 0xa397468d,
     } };
 
-    uint64_t *rd = vd;
-    uint64_t *rm = vm;
     union CRYPTO_STATE st = { .l = { rm[0], rm[1] } };
     int i;
 
-    assert(decrypt < 2);
-
     for (i = 0; i < 16; i += 4) {
         CR_ST_WORD(st, i >> 2) =
             mc[decrypt][CR_ST_BYTE(st, i)] ^
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)
     rd[1] = st.l[1];
 }
 
+void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t desc)
+{
+    intptr_t i, opr_sz = simd_oprsz(desc);
+    bool decrypt = simd_data(desc);
+
+    for (i = 0; i < opr_sz; i += 16) {
+        do_crypto_aesmc(vd + i, vm + i, decrypt);
+    }
+    clear_tail(vd, opr_sz, simd_maxsz(desc));
+}
+
 /*
  * SHA-1 logical functions
  */
@@ -XXX,XX +XXX,XX @@ static uint8_t const sm4_sbox[] = {
     0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
 };
 
-void HELPER(crypto_sm4e)(void *vd, void *vn)
+static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
 {
-    uint64_t *rd = vd;
-    uint64_t *rn = vn;
-    union CRYPTO_STATE d = { .l = { rd[0], rd[1] } };
-    union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };
+    union CRYPTO_STATE d = { .l = { rn[0], rn[1] } };
+    union CRYPTO_STATE n = { .l = { rm[0], rm[1] } };
     uint32_t t, i;
 
     for (i = 0; i < 4; i++) {
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4e)(void *vd, void *vn)
     rd[1] = d.l[1];
 }
 
-void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm)
+void HELPER(crypto_sm4e)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+    intptr_t i, opr_sz = simd_oprsz(desc);
+
+    for (i = 0; i < opr_sz; i += 16) {
+        do_crypto_sm4e(vd + i, vn + i, vm + i);
+    }
+    clear_tail(vd, opr_sz, simd_maxsz(desc));
+}
+
+static void do_crypto_sm4ekey(uint64_t *rd, uint64_t *rn, uint64_t *rm)
 {
-    uint64_t *rd = vd;
-    uint64_t *rn = vn;
-    uint64_t *rm = vm;
     union CRYPTO_STATE d;
     union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };
     union CRYPTO_STATE m = { .l = { rm[0], rm[1] } };
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm)
     rd[0] = d.l[0];
     rd[1] = d.l[1];
 }
+
+void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm, uint32_t desc)
+{
+    intptr_t i, opr_sz = simd_oprsz(desc);
+
+    for (i = 0; i < opr_sz; i += 16) {
+        do_crypto_sm4ekey(vd + i, vn + i, vm + i);
+    }
+    clear_tail(vd, opr_sz, simd_maxsz(desc));
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void gen_gvec_fn4(DisasContext *s, bool is_q, int rd, int rn, int rm,
             is_q ? 16 : 8, vec_full_reg_size(s));
 }
 
+/* Expand a 2-operand operation using an out-of-line helper.  */
+static void gen_gvec_op2_ool(DisasContext *s, bool is_q, int rd,
+                             int rn, int data, gen_helper_gvec_2 *fn)
+{
+    tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
+                       vec_full_reg_offset(s, rn),
+                       is_q ? 16 : 8, vec_full_reg_size(s), data, fn);
+}
+
 /* Expand a 3-operand operation using an out-of-line helper.  */
 static void gen_gvec_op3_ool(DisasContext *s, bool is_q, int rd,
                              int rn, int rm, int data, gen_helper_gvec_3 *fn)
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
     int rn = extract32(insn, 5, 5);
     int rd = extract32(insn, 0, 5);
     int decrypt;
-    TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
-    TCGv_i32 tcg_decrypt;
-    CryptoThreeOpIntFn *genfn;
+    gen_helper_gvec_2 *genfn2 = NULL;
+    gen_helper_gvec_3 *genfn3 = NULL;
 
     if (!dc_isar_feature(aa64_aes, s) || size != 0) {
         unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
     switch (opcode) {
     case 0x4: /* AESE */
         decrypt = 0;
-        genfn = gen_helper_crypto_aese;
+        genfn3 = gen_helper_crypto_aese;
         break;
     case 0x6: /* AESMC */
         decrypt = 0;
-        genfn = gen_helper_crypto_aesmc;
+        genfn2 = gen_helper_crypto_aesmc;
         break;
     case 0x5: /* AESD */
         decrypt = 1;
-        genfn = gen_helper_crypto_aese;
+        genfn3 = gen_helper_crypto_aese;
         break;
     case 0x7: /* AESIMC */
         decrypt = 1;
-        genfn = gen_helper_crypto_aesmc;
+        genfn2 = gen_helper_crypto_aesmc;
         break;
     default:
         unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
     if (!fp_access_check(s)) {
         return;
     }
-
-    tcg_rd_ptr = vec_full_reg_ptr(s, rd);
-    tcg_rn_ptr = vec_full_reg_ptr(s, rn);
-    tcg_decrypt = tcg_const_i32(decrypt);
-
-    genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_decrypt);
-
-    tcg_temp_free_ptr(tcg_rd_ptr);
-    tcg_temp_free_ptr(tcg_rn_ptr);
-    tcg_temp_free_i32(tcg_decrypt);
+    if (genfn2) {
+        gen_gvec_op2_ool(s, true, rd, rn, decrypt, genfn2);
+    } else {
+        gen_gvec_op3_ool(s, true, rd, rd, rn, decrypt, genfn3);
+    }
 }
 
 /* Crypto three-reg SHA
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
     int rn = extract32(insn, 5, 5);
     int rd = extract32(insn, 0, 5);
     bool feature;
-    CryptoThreeOpFn *genfn;
+    CryptoThreeOpFn *genfn = NULL;
+    gen_helper_gvec_3 *oolfn = NULL;
 
     if (o == 0) {
         switch (opcode) {
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
             break;
         case 2: /* SM4EKEY */
             feature = dc_isar_feature(aa64_sm4, s);
-            genfn = gen_helper_crypto_sm4ekey;
+            oolfn = gen_helper_crypto_sm4ekey;
             break;
         default:
             unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
         return;
     }
 
+    if (oolfn) {
+        gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn);
+        return;
+    }
+
     if (genfn) {
         TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
 
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
     TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
     bool feature;
     CryptoTwoOpFn *genfn;
+    gen_helper_gvec_3 *oolfn = NULL;
 
     switch (opcode) {
     case 0: /* SHA512SU0 */
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
         break;
     case 1: /* SM4E */
         feature = dc_isar_feature(aa64_sm4, s);
-        genfn = gen_helper_crypto_sm4e;
+        oolfn = gen_helper_crypto_sm4e;
         break;
     default:
         unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
         return;
     }
 
+    if (oolfn) {
+        gen_gvec_op3_ool(s, true, rd, rd, rn, 0, oolfn);
+        return;
+    }
+
     tcg_rd_ptr = vec_full_reg_ptr(s, rd);
     tcg_rn_ptr = vec_full_reg_ptr(s, rn);
 
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) {
                         return 1;
                     }
-                    ptr1 = vfp_reg_ptr(true, rd);
-                    ptr2 = vfp_reg_ptr(true, rm);
-
-                     /* Bit 6 is the lowest opcode bit; it distinguishes between
-                      * encryption (AESE/AESMC) and decryption (AESD/AESIMC)
-                      */
-                    tmp3 = tcg_const_i32(extract32(insn, 6, 1));
-
+                    /*
+                     * Bit 6 is the lowest opcode bit; it distinguishes
+                     * between encryption (AESE/AESMC) and decryption
+                     * (AESD/AESIMC).
+                     */
                     if (op == NEON_2RM_AESE) {
-                        gen_helper_crypto_aese(ptr1, ptr2, tmp3);
+                        tcg_gen_gvec_3_ool(vfp_reg_offset(true, rd),
+                                           vfp_reg_offset(true, rd),
+                                           vfp_reg_offset(true, rm),
+                                           16, 16, extract32(insn, 6, 1),
+                                           gen_helper_crypto_aese);
                     } else {
-                        gen_helper_crypto_aesmc(ptr1, ptr2, tmp3);
+                        tcg_gen_gvec_2_ool(vfp_reg_offset(true, rd),
+                                           vfp_reg_offset(true, rm),
+                                           16, 16, extract32(insn, 6, 1),
+                                           gen_helper_crypto_aesmc);
                     }
-                    tcg_temp_free_ptr(ptr1);
-                    tcg_temp_free_ptr(ptr2);
-                    tcg_temp_free_i32(tmp3);
                     break;
                 case NEON_2RM_SHA1H:
                     if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) {
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-proto.h"
 #include "tcg/tcg-gvec-desc.h"
 #include "fpu/softfloat.h"
-
+#include "vec_internal.h"
 
 /* Note that vector data is stored in host-endian 64-bit chunks,
    so addressing units smaller than that needs a host-endian fixup.  */
@@ -XXX,XX +XXX,XX @@
 #define H4(x)  (x)
 #endif
 
-static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
-{
-    uint64_t *d = vd + opr_sz;
-    uintptr_t i;
-
-    for (i = opr_sz; i < max_sz; i += 8) {
-        *d++ = 0;
-    }
-}
-
 /* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
 static int16_t inl_qrdmlah_s16(int16_t src1, int16_t src2,
                                int16_t src3, uint32_t *sat)
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

With this conversion, we will be able to use the same helpers
with sve.  This also fixes a bug in which we failed to clear
the high bits of the SVE register after an AdvSIMD operation.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h        |  2 ++
 target/arm/translate-a64.h |  3 ++
 target/arm/crypto_helper.c | 11 +++++++
 target/arm/translate-a64.c | 59 ++++++++++++++++++++------------------
 4 files changed, 47 insertions(+), 28 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Do not yet convert the helpers to loop over opr_sz, but the
descriptor allows the vector tail to be cleared.  Which fixes
an existing bug vs SVE.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h        | 15 +++++++-----
 target/arm/crypto_helper.c | 37 +++++++++++++++++++++++-----
 target/arm/translate-a64.c | 50 ++++++++++++--------------------------
 3 files changed, 55 insertions(+), 47 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Do not yet convert the helpers to loop over opr_sz, but the
descriptor allows the vector tail to be cleared.  Which fixes
an existing bug vs SVE.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h             |  12 ++--
 target/arm/neon-dp.decode       |  12 ++--
 target/arm/crypto_helper.c      |  24 +++++--
 target/arm/translate-a64.c      |  34 ++++-----
 target/arm/translate-neon.inc.c | 124 +++++---------------------------
 target/arm/translate.c          |  24 ++-----
 6 files changed, 67 insertions(+), 163 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 
 DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-DEF_HELPER_FLAGS_2(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr)
-DEF_HELPER_FLAGS_2(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr)
+DEF_HELPER_FLAGS_3(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 
-DEF_HELPER_FLAGS_3(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
-DEF_HELPER_FLAGS_3(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
-DEF_HELPER_FLAGS_2(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr)
-DEF_HELPER_FLAGS_3(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 
 DEF_HELPER_FLAGS_4(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VPADD_3s         1111 001 0 0 . .. .... .... 1011 . . . 1 .... @3same_q0
 
 VQRDMLAH_3s      1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
 
+@3same_crypto    .... .... .... .... .... .... .... .... \
+                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 q=1
+
 SHA1_3s          1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \
                  vm=%vm_dp vn=%vn_dp vd=%vd_dp
-SHA256H_3s       1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... \
-                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
-SHA256H2_3s      1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... \
-                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
-SHA256SU1_3s     1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... \
-                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
+SHA256H_3s       1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
+SHA256H2_3s      1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
+SHA256SU1_3s     1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
 
 VFMA_fp_3s       1111 001 0 0 . 0 . .... .... 1100 ... 1 .... @3same_fp
 VFMS_fp_3s       1111 001 0 0 . 1 . .... .... 1100 ... 1 .... @3same_fp
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/crypto_helper.c
+++ b/target/arm/crypto_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha1_3reg)(void *vd, void *vn, void *vm, uint32_t op)
     rd[1] = d.l[1];
 }
 
-void HELPER(crypto_sha1h)(void *vd, void *vm)
+void HELPER(crypto_sha1h)(void *vd, void *vm, uint32_t desc)
 {
     uint64_t *rd = vd;
     uint64_t *rm = vm;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha1h)(void *vd, void *vm)
 
     rd[0] = m.l[0];
     rd[1] = m.l[1];
+
+    clear_tail_16(vd, desc);
 }
 
-void HELPER(crypto_sha1su1)(void *vd, void *vm)
+void HELPER(crypto_sha1su1)(void *vd, void *vm, uint32_t desc)
 {
     uint64_t *rd = vd;
     uint64_t *rm = vm;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha1su1)(void *vd, void *vm)
 
     rd[0] = d.l[0];
     rd[1] = d.l[1];
+
+    clear_tail_16(vd, desc);
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static uint32_t s1(uint32_t x)
     return ror32(x, 17) ^ ror32(x, 19) ^ (x >> 10);
 }
 
-void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm)
+void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm, uint32_t desc)
 {
     uint64_t *rd = vd;
     uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm)
 
     rd[0] = d.l[0];
     rd[1] = d.l[1];
+
+    clear_tail_16(vd, desc);
 }
 
-void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm)
+void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm, uint32_t desc)
 {
     uint64_t *rd = vd;
     uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm)
 
     rd[0] = d.l[0];
     rd[1] = d.l[1];
+
+    clear_tail_16(vd, desc);
 }
 
-void HELPER(crypto_sha256su0)(void *vd, void *vm)
+void HELPER(crypto_sha256su0)(void *vd, void *vm, uint32_t desc)
 {
     uint64_t *rd = vd;
     uint64_t *rm = vm;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256su0)(void *vd, void *vm)
 
     rd[0] = d.l[0];
     rd[1] = d.l[1];
+
+    clear_tail_16(vd, desc);
 }
 
-void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm)
+void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm, uint32_t desc)
 {
     uint64_t *rd = vd;
     uint64_t *rn = vn;
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm)
 
     rd[0] = d.l[0];
     rd[1] = d.l[1];
+
+    clear_tail_16(vd, desc);
 }
 
 /*
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
     int rm = extract32(insn, 16, 5);
     int rn = extract32(insn, 5, 5);
     int rd = extract32(insn, 0, 5);
-    CryptoThreeOpFn *genfn;
-    TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
+    gen_helper_gvec_3 *genfn;
     bool feature;
 
     if (size != 0) {
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
         return;
     }
 
-    tcg_rd_ptr = vec_full_reg_ptr(s, rd);
-    tcg_rn_ptr = vec_full_reg_ptr(s, rn);
-    tcg_rm_ptr = vec_full_reg_ptr(s, rm);
-
     if (genfn) {
-        genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr);
+        gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn);
     } else {
         TCGv_i32 tcg_opcode = tcg_const_i32(opcode);
+        TCGv_ptr tcg_rd_ptr = vec_full_reg_ptr(s, rd);
+        TCGv_ptr tcg_rn_ptr = vec_full_reg_ptr(s, rn);
+        TCGv_ptr tcg_rm_ptr = vec_full_reg_ptr(s, rm);
 
         gen_helper_crypto_sha1_3reg(tcg_rd_ptr, tcg_rn_ptr,
                                     tcg_rm_ptr, tcg_opcode);
-        tcg_temp_free_i32(tcg_opcode);
-    }
 
-    tcg_temp_free_ptr(tcg_rd_ptr);
-    tcg_temp_free_ptr(tcg_rn_ptr);
-    tcg_temp_free_ptr(tcg_rm_ptr);
+        tcg_temp_free_i32(tcg_opcode);
+        tcg_temp_free_ptr(tcg_rd_ptr);
+        tcg_temp_free_ptr(tcg_rn_ptr);
+        tcg_temp_free_ptr(tcg_rm_ptr);
+    }
 }
 
 /* Crypto two-reg SHA
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
     int opcode = extract32(insn, 12, 5);
     int rn = extract32(insn, 5, 5);
     int rd = extract32(insn, 0, 5);
-    CryptoTwoOpFn *genfn;
+    gen_helper_gvec_2 *genfn;
     bool feature;
-    TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
 
     if (size != 0) {
         unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
     if (!fp_access_check(s)) {
         return;
     }
-
-    tcg_rd_ptr = vec_full_reg_ptr(s, rd);
-    tcg_rn_ptr = vec_full_reg_ptr(s, rn);
-
-    genfn(tcg_rd_ptr, tcg_rn_ptr);
-
-    tcg_temp_free_ptr(tcg_rd_ptr);
-    tcg_temp_free_ptr(tcg_rn_ptr);
+    gen_gvec_op2_ool(s, true, rd, rn, 0, genfn);
 }
 
 static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ DO_3SAME_CMP(VCGE_S, TCG_COND_GE)
 DO_3SAME_CMP(VCGE_U, TCG_COND_GEU)
 DO_3SAME_CMP(VCEQ, TCG_COND_EQ)
 
-static void gen_VMUL_p_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
-                           uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)
-{
-    tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz,
-                       0, gen_helper_gvec_pmul_b);
-}
+#define WRAP_OOL_FN(WRAPNAME, FUNC)                                        \
+    static void WRAPNAME(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,  \
+                         uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)  \
+    {                                                                      \
+        tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, 0, FUNC); \
+    }
+
+WRAP_OOL_FN(gen_VMUL_p_3s, gen_helper_gvec_pmul_b)
 
 static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
 {
@@ -XXX,XX +XXX,XX @@ static bool trans_SHA1_3s(DisasContext *s, arg_SHA1_3s *a)
     return true;
 }
 
-static bool trans_SHA256H_3s(DisasContext *s, arg_SHA256H_3s *a)
-{
-    TCGv_ptr ptr1, ptr2, ptr3;
-
-    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
-        !dc_isar_feature(aa32_sha2, s)) {
-        return false;
+#define DO_SHA2(NAME, FUNC)                                             \
+    WRAP_OOL_FN(gen_##NAME##_3s, FUNC)                                  \
+    static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a)        \
+    {                                                                   \
+        if (!dc_isar_feature(aa32_sha2, s)) {                           \
+            return false;                                               \
+        }                                                               \
+        return do_3same(s, a, gen_##NAME##_3s);                         \
     }
 
-    /* UNDEF accesses to D16-D31 if they don't exist. */
-    if (!dc_isar_feature(aa32_simd_r32, s) &&
-        ((a->vd | a->vn | a->vm) & 0x10)) {
-        return false;
-    }
-
-    if ((a->vn | a->vm | a->vd) & 1) {
-        return false;
-    }
-
-    if (!vfp_access_check(s)) {
-        return true;
-    }
-
-    ptr1 = vfp_reg_ptr(true, a->vd);
-    ptr2 = vfp_reg_ptr(true, a->vn);
-    ptr3 = vfp_reg_ptr(true, a->vm);
-    gen_helper_crypto_sha256h(ptr1, ptr2, ptr3);
-    tcg_temp_free_ptr(ptr1);
-    tcg_temp_free_ptr(ptr2);
-    tcg_temp_free_ptr(ptr3);
-
-    return true;
-}
-
-static bool trans_SHA256H2_3s(DisasContext *s, arg_SHA256H2_3s *a)
-{
-    TCGv_ptr ptr1, ptr2, ptr3;
-
-    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
-        !dc_isar_feature(aa32_sha2, s)) {
-        return false;
-    }
-
-    /* UNDEF accesses to D16-D31 if they don't exist. */
-    if (!dc_isar_feature(aa32_simd_r32, s) &&
-        ((a->vd | a->vn | a->vm) & 0x10)) {
-        return false;
-    }
-
-    if ((a->vn | a->vm | a->vd) & 1) {
-        return false;
-    }
-
-    if (!vfp_access_check(s)) {
-        return true;
-    }
-
-    ptr1 = vfp_reg_ptr(true, a->vd);
-    ptr2 = vfp_reg_ptr(true, a->vn);
-    ptr3 = vfp_reg_ptr(true, a->vm);
-    gen_helper_crypto_sha256h2(ptr1, ptr2, ptr3);
-    tcg_temp_free_ptr(ptr1);
-    tcg_temp_free_ptr(ptr2);
-    tcg_temp_free_ptr(ptr3);
-
-    return true;
-}
-
-static bool trans_SHA256SU1_3s(DisasContext *s, arg_SHA256SU1_3s *a)
-{
-    TCGv_ptr ptr1, ptr2, ptr3;
-
-    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
-        !dc_isar_feature(aa32_sha2, s)) {
-        return false;
-    }
-
-    /* UNDEF accesses to D16-D31 if they don't exist. */
-    if (!dc_isar_feature(aa32_simd_r32, s) &&
-        ((a->vd | a->vn | a->vm) & 0x10)) {
-        return false;
-    }
-
-    if ((a->vn | a->vm | a->vd) & 1) {
-        return false;
-    }
-
-    if (!vfp_access_check(s)) {
-        return true;
-    }
-
-    ptr1 = vfp_reg_ptr(true, a->vd);
-    ptr2 = vfp_reg_ptr(true, a->vn);
-    ptr3 = vfp_reg_ptr(true, a->vm);
-    gen_helper_crypto_sha256su1(ptr1, ptr2, ptr3);
-    tcg_temp_free_ptr(ptr1);
-    tcg_temp_free_ptr(ptr2);
-    tcg_temp_free_ptr(ptr3);
-
-    return true;
-}
+DO_SHA2(SHA256H, gen_helper_crypto_sha256h)
+DO_SHA2(SHA256H2, gen_helper_crypto_sha256h2)
+DO_SHA2(SHA256SU1, gen_helper_crypto_sha256su1)
 
 #define DO_3SAME_64(INSN, FUNC)                                         \
     static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
     int vec_size;
     uint32_t imm;
     TCGv_i32 tmp, tmp2, tmp3, tmp4, tmp5;
-    TCGv_ptr ptr1, ptr2;
+    TCGv_ptr ptr1;
     TCGv_i64 tmp64;
 
     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) {
                         return 1;
                     }
-                    ptr1 = vfp_reg_ptr(true, rd);
-                    ptr2 = vfp_reg_ptr(true, rm);
-
-                    gen_helper_crypto_sha1h(ptr1, ptr2);
-
-                    tcg_temp_free_ptr(ptr1);
-                    tcg_temp_free_ptr(ptr2);
+                    tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0,
+                                       gen_helper_crypto_sha1h);
                     break;
                 case NEON_2RM_SHA1SU1:
                     if ((rm | rd) & 1) {
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     } else if (!dc_isar_feature(aa32_sha1, s)) {
                         return 1;
                     }
-                    ptr1 = vfp_reg_ptr(true, rd);
-                    ptr2 = vfp_reg_ptr(true, rm);
-                    if (q) {
-                        gen_helper_crypto_sha256su0(ptr1, ptr2);
-                    } else {
-                        gen_helper_crypto_sha1su1(ptr1, ptr2);
-                    }
-                    tcg_temp_free_ptr(ptr1);
-                    tcg_temp_free_ptr(ptr2);
+                    tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0,
+                                       q ? gen_helper_crypto_sha256su0
+                                       : gen_helper_crypto_sha1su1);
                     break;
-
                 case NEON_2RM_VMVN:
                     tcg_gen_gvec_not(0, rd_ofs, rm_ofs, vec_size, vec_size);
                     break;
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Rather than passing an opcode to a helper, fully decode the
operation at translate time.  Use clear_tail_16 to zap the
balance of the SVE register with the AdvSIMD write.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-6-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h             |  5 +-
 target/arm/neon-dp.decode       |  6 +-
 target/arm/crypto_helper.c      | 99 +++++++++++++++++++++------------
 target/arm/translate-a64.c      | 29 ++++------
 target/arm/translate-neon.inc.c | 46 ++++-----------
 5 files changed, 93 insertions(+), 92 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Rather than passing an opcode to a helper, fully decode the
operation at translate time.  Use clear_tail_16 to zap the
balance of the SVE register with the AdvSIMD write.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-7-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h        |  5 ++++-
 target/arm/crypto_helper.c | 24 ++++++++++++++++++------
 target/arm/translate-a64.c | 21 +++++----------------
 3 files changed, 27 insertions(+), 23 deletions(-)

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The ADC region size is 256B, split as:
 - [0x00 - 0x4f] defined
 - [0x50 - 0xff] reserved

All registers are 32-bit (thus when the datasheet mentions the
last defined register is 0x4c, it means its address range is
0x4c .. 0x4f.

This model implementation is also 32-bit. Set MemoryRegionOps
'impl' fields.

See:
  'RM0033 Reference manual Rev 8', Table 10.13.18 "ADC register map".

Reported-by: Seth Kintigh <skintigh@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200603055915.17678-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/adc/stm32f2xx_adc.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/adc/stm32f2xx_adc.c b/hw/adc/stm32f2xx_adc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/adc/stm32f2xx_adc.c
+++ b/hw/adc/stm32f2xx_adc.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps stm32f2xx_adc_ops = {
     .read = stm32f2xx_adc_read,
     .write = stm32f2xx_adc_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
 };
 
 static const VMStateDescription vmstate_stm32f2xx_adc = {
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_adc_init(Object *obj)
     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 
     memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s,
-                          TYPE_STM32F2XX_ADC, 0xFF);
+                          TYPE_STM32F2XX_ADC, 0x100);
     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 }
 
-- 
2.20.1

From: Thomas Huth <thuth@redhat.com>

As described by Edgar here:

https://www.mail-archive.com/qemu-devel@nongnu.org/msg605124.html

we can use the Ubuntu kernel for testing the xlnx-versal-virt machine.
So let's add a boot test for this now.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20200525141237.15243-1-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/acceptance/boot_linux_console.py | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

From: Cédric Le Goater <clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200602135050.593692-1-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/aspeed.rst | 85 ++++++++++++++++++++++++++++++++++++++
 docs/system/target-arm.rst |  1 +
 2 files changed, 86 insertions(+)
 create mode 100644 docs/system/arm/aspeed.rst

diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/arm/aspeed.rst
@@ -XXX,XX +XXX,XX @@
+Aspeed family boards (``*-bmc``, ``ast2500-evb``, ``ast2600-evb``)
+==================================================================
+
+The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
+Aspeed evaluation boards. They are based on different releases of the
+Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the
+AST2500 with an ARM1176JZS CPU (800MHz) and more recently the AST2600
+with dual cores ARM Cortex A7 CPUs (1.2GHz).
+
+The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C,
+etc.
+
+AST2400 SoC based machines :
+
+- ``palmetto-bmc``         OpenPOWER Palmetto POWER8 BMC
+
+AST2500 SoC based machines :
+
+- ``ast2500-evb``          Aspeed AST2500 Evaluation board
+- ``romulus-bmc``          OpenPOWER Romulus POWER9 BMC
+- ``witherspoon-bmc``      OpenPOWER Witherspoon POWER9 BMC
+- ``sonorapass-bmc``       OCP SonoraPass BMC
+- ``swift-bmc``            OpenPOWER Swift BMC POWER9
+
+AST2600 SoC based machines :
+
+- ``ast2600-evb``          Aspeed AST2600 Evaluation board (Cortex A7)
+- ``tacoma-bmc``           OpenPOWER Witherspoon POWER9 AST2600 BMC
+
+Supported devices
+-----------------
+
+ * SMP (for the AST2600 Cortex-A7)
+ * Interrupt Controller (VIC)
+ * Timer Controller
+ * RTC Controller
+ * I2C Controller
+ * System Control Unit (SCU)
+ * SRAM mapping
+ * X-DMA Controller (basic interface)
+ * Static Memory Controller (SMC or FMC) - Only SPI Flash support
+ * SPI Memory Controller
+ * USB 2.0 Controller
+ * SD/MMC storage controllers
+ * SDRAM controller (dummy interface for basic settings and training)
+ * Watchdog Controller
+ * GPIO Controller (Master only)
+ * UART
+ * Ethernet controllers
+
+
+Missing devices
+---------------
+
+ * Coprocessor support
+ * ADC (out of tree implementation)
+ * PWM and Fan Controller
+ * LPC Bus Controller
+ * Slave GPIO Controller
+ * Super I/O Controller
+ * Hash/Crypto Engine
+ * PCI-Express 1 Controller
+ * Graphic Display Controller
+ * PECI Controller
+ * MCTP Controller
+ * Mailbox Controller
+ * Virtual UART
+ * eSPI Controller
+ * I3C Controller
+
+Boot options
+------------
+
+The Aspeed machines can be started using the -kernel option to load a
+Linux kernel or from a firmare image which can be downloaded from the
+OpenPOWER jenkins :
+
+   https://openpower.xyz/
+
+The image should be attached as an MTD drive. Run :
+
+.. code-block:: bash
+
+  $ qemu-system-arm -M romulus-bmc -nic user \
+	-drive file=flash-romulus,format=raw,if=mtd -nographic
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
    arm/realview
    arm/versatile
    arm/vexpress
+   arm/aspeed
    arm/musicpal
    arm/nseries
    arm/orangepi
-- 
2.20.1

From: Paul Zimmerman <pauldzim@gmail.com>

Add BCM2835 SOC MPHI (Message-based Parallel Host Interface)
emulation. It is very basic, only providing the FIQ interrupt
needed to allow the dwc-otg USB host controller driver in the
Raspbian kernel to function.

Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Acked-by: Philippe Mathieu-Daude <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200520235349.21215-2-pauldzim@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/bcm2835_peripherals.h |   2 +
 include/hw/misc/bcm2835_mphi.h       |  44 ++++++
 hw/arm/bcm2835_peripherals.c         |  17 +++
 hw/misc/bcm2835_mphi.c               | 191 +++++++++++++++++++++++++++
 hw/misc/Makefile.objs                |   1 +
 5 files changed, 255 insertions(+)
 create mode 100644 include/hw/misc/bcm2835_mphi.h
 create mode 100644 hw/misc/bcm2835_mphi.c

diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2835_peripherals.h
+++ b/include/hw/arm/bcm2835_peripherals.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/bcm2835_property.h"
 #include "hw/misc/bcm2835_rng.h"
 #include "hw/misc/bcm2835_mbox.h"
+#include "hw/misc/bcm2835_mphi.h"
 #include "hw/misc/bcm2835_thermal.h"
 #include "hw/sd/sdhci.h"
 #include "hw/sd/bcm2835_sdhost.h"
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState {
     qemu_irq irq, fiq;
 
     BCM2835SystemTimerState systmr;
+    BCM2835MphiState mphi;
     UnimplementedDeviceState armtmr;
     UnimplementedDeviceState cprman;
     UnimplementedDeviceState a2w;
diff --git a/include/hw/misc/bcm2835_mphi.h b/include/hw/misc/bcm2835_mphi.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/bcm2835_mphi.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * BCM2835 SOC MPHI state definitions
+ *
+ * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef HW_MISC_BCM2835_MPHI_H
+#define HW_MISC_BCM2835_MPHI_H
+
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+
+#define MPHI_MMIO_SIZE      0x1000
+
+typedef struct BCM2835MphiState BCM2835MphiState;
+
+struct BCM2835MphiState {
+    SysBusDevice parent_obj;
+    qemu_irq irq;
+    MemoryRegion iomem;
+
+    uint32_t outdda;
+    uint32_t outddb;
+    uint32_t ctrl;
+    uint32_t intstat;
+    uint32_t swirq;
+};
+
+#define TYPE_BCM2835_MPHI   "bcm2835-mphi"
+
+#define BCM2835_MPHI(obj) \
+    OBJECT_CHECK(BCM2835MphiState, (obj), TYPE_BCM2835_MPHI)
+
+#endif
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2835_peripherals.c
+++ b/hw/arm/bcm2835_peripherals.c
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
                                    OBJECT(&s->sdhci.sdbus));
     object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost",
                                    OBJECT(&s->sdhost.sdbus));
+
+    /* Mphi */
+    sysbus_init_child_obj(obj, "mphi", &s->mphi, sizeof(s->mphi),
+                          TYPE_BCM2835_MPHI);
 }
 
 static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
 
     object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus");
 
+    /* Mphi */
+    object_property_set_bool(OBJECT(&s->mphi), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+
+    memory_region_add_subregion(&s->peri_mr, MPHI_OFFSET,
+                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mphi), 0));
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->mphi), 0,
+        qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
+                               INTERRUPT_HOSTPORT));
+
     create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
     create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
     create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
diff --git a/hw/misc/bcm2835_mphi.c b/hw/misc/bcm2835_mphi.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/bcm2835_mphi.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * BCM2835 SOC MPHI emulation
+ *
+ * Very basic emulation, only providing the FIQ interrupt needed to
+ * allow the dwc-otg USB host controller driver in the Raspbian kernel
+ * to function.
+ *
+ * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/misc/bcm2835_mphi.h"
+#include "migration/vmstate.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/main-loop.h"
+
+static inline void mphi_raise_irq(BCM2835MphiState *s)
+{
+    qemu_set_irq(s->irq, 1);
+}
+
+static inline void mphi_lower_irq(BCM2835MphiState *s)
+{
+    qemu_set_irq(s->irq, 0);
+}
+
+static uint64_t mphi_reg_read(void *ptr, hwaddr addr, unsigned size)
+{
+    BCM2835MphiState *s = ptr;
+    uint32_t val = 0;
+
+    switch (addr) {
+    case 0x28:  /* outdda */
+        val = s->outdda;
+        break;
+    case 0x2c:  /* outddb */
+        val = s->outddb;
+        break;
+    case 0x4c:  /* ctrl */
+        val = s->ctrl;
+        val |= 1 << 17;
+        break;
+    case 0x50:  /* intstat */
+        val = s->intstat;
+        break;
+    case 0x1f0: /* swirq_set */
+        val = s->swirq;
+        break;
+    case 0x1f4: /* swirq_clr */
+        val = s->swirq;
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "read from unknown register");
+        break;
+    }
+
+    return val;
+}
+
+static void mphi_reg_write(void *ptr, hwaddr addr, uint64_t val, unsigned size)
+{
+    BCM2835MphiState *s = ptr;
+    int do_irq = 0;
+
+    switch (addr) {
+    case 0x28:  /* outdda */
+        s->outdda = val;
+        break;
+    case 0x2c:  /* outddb */
+        s->outddb = val;
+        if (val & (1 << 29)) {
+            do_irq = 1;
+        }
+        break;
+    case 0x4c:  /* ctrl */
+        s->ctrl = val;
+        if (val & (1 << 16)) {
+            do_irq = -1;
+        }
+        break;
+    case 0x50:  /* intstat */
+        s->intstat = val;
+        if (val & ((1 << 16) | (1 << 29))) {
+            do_irq = -1;
+        }
+        break;
+    case 0x1f0: /* swirq_set */
+        s->swirq |= val;
+        do_irq = 1;
+        break;
+    case 0x1f4: /* swirq_clr */
+        s->swirq &= ~val;
+        do_irq = -1;
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "write to unknown register");
+        return;
+    }
+
+    if (do_irq > 0) {
+        mphi_raise_irq(s);
+    } else if (do_irq < 0) {
+        mphi_lower_irq(s);
+    }
+}
+
+static const MemoryRegionOps mphi_mmio_ops = {
+    .read = mphi_reg_read,
+    .write = mphi_reg_write,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void mphi_reset(DeviceState *dev)
+{
+    BCM2835MphiState *s = BCM2835_MPHI(dev);
+
+    s->outdda = 0;
+    s->outddb = 0;
+    s->ctrl = 0;
+    s->intstat = 0;
+    s->swirq = 0;
+}
+
+static void mphi_realize(DeviceState *dev, Error **errp)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+    BCM2835MphiState *s = BCM2835_MPHI(dev);
+
+    sysbus_init_irq(sbd, &s->irq);
+}
+
+static void mphi_init(Object *obj)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    BCM2835MphiState *s = BCM2835_MPHI(obj);
+
+    memory_region_init_io(&s->iomem, obj, &mphi_mmio_ops, s, "mphi", MPHI_MMIO_SIZE);
+    sysbus_init_mmio(sbd, &s->iomem);
+}
+
+const VMStateDescription vmstate_mphi_state = {
+    .name = "mphi",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(outdda, BCM2835MphiState),
+        VMSTATE_UINT32(outddb, BCM2835MphiState),
+        VMSTATE_UINT32(ctrl, BCM2835MphiState),
+        VMSTATE_UINT32(intstat, BCM2835MphiState),
+        VMSTATE_UINT32(swirq, BCM2835MphiState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void mphi_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = mphi_realize;
+    dc->reset = mphi_reset;
+    dc->vmsd = &vmstate_mphi_state;
+}
+
+static const TypeInfo bcm2835_mphi_type_info = {
+    .name          = TYPE_BCM2835_MPHI,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(BCM2835MphiState),
+    .instance_init = mphi_init,
+    .class_init    = mphi_class_init,
+};
+
+static void bcm2835_mphi_register_types(void)
+{
+    type_register_static(&bcm2835_mphi_type_info);
+}
+
+type_init(bcm2835_mphi_register_types)
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_OMAP) += omap_l4.o
 common-obj-$(CONFIG_OMAP) += omap_sdrc.o
 common-obj-$(CONFIG_OMAP) += omap_tap.o
 common-obj-$(CONFIG_RASPI) += bcm2835_mbox.o
+common-obj-$(CONFIG_RASPI) += bcm2835_mphi.o
 common-obj-$(CONFIG_RASPI) += bcm2835_property.o
 common-obj-$(CONFIG_RASPI) += bcm2835_rng.o
 common-obj-$(CONFIG_RASPI) += bcm2835_thermal.o
-- 
2.20.1

From: Paul Zimmerman <pauldzim@gmail.com>

Import the dwc-hsotg (dwc2) register definitions file from the
Linux kernel. This is a copy of drivers/usb/dwc2/hw.h from the
mainline Linux kernel, the only changes being to the header, and
two instances of 'u32' changed to 'uint32_t' to allow it to
compile. Checkpatch throws a boatload of errors due to the tab
indentation, but I would rather import it as-is than reformat it.

Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Message-id: 20200520235349.21215-3-pauldzim@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/usb/dwc2-regs.h | 899 +++++++++++++++++++++++++++++++++++++
 1 file changed, 899 insertions(+)
 create mode 100644 include/hw/usb/dwc2-regs.h

diff --git a/include/hw/usb/dwc2-regs.h b/include/hw/usb/dwc2-regs.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/usb/dwc2-regs.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Imported from the Linux kernel file drivers/usb/dwc2/hw.h, commit
+ * a89bae709b3492b478480a2c9734e7e9393b279c ("usb: dwc2: Move
+ * UTMI_PHY_DATA defines closer")
+ *
+ * hw.h - DesignWare HS OTG Controller hardware definitions
+ *
+ * Copyright 2004-2013 Synopsys, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The names of the above-listed copyright holders may not be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __DWC2_HW_H__
+#define __DWC2_HW_H__
+
+#define HSOTG_REG(x)	(x)
+
+#define GOTGCTL				HSOTG_REG(0x000)
+#define GOTGCTL_CHIRPEN			BIT(27)
+#define GOTGCTL_MULT_VALID_BC_MASK	(0x1f << 22)
+#define GOTGCTL_MULT_VALID_BC_SHIFT	22
+#define GOTGCTL_OTGVER			BIT(20)
+#define GOTGCTL_BSESVLD			BIT(19)
+#define GOTGCTL_ASESVLD			BIT(18)
+#define GOTGCTL_DBNC_SHORT		BIT(17)
+#define GOTGCTL_CONID_B			BIT(16)
+#define GOTGCTL_DBNCE_FLTR_BYPASS	BIT(15)
+#define GOTGCTL_DEVHNPEN		BIT(11)
+#define GOTGCTL_HSTSETHNPEN		BIT(10)
+#define GOTGCTL_HNPREQ			BIT(9)
+#define GOTGCTL_HSTNEGSCS		BIT(8)
+#define GOTGCTL_SESREQ			BIT(1)
+#define GOTGCTL_SESREQSCS		BIT(0)
+
+#define GOTGINT				HSOTG_REG(0x004)
+#define GOTGINT_DBNCE_DONE		BIT(19)
+#define GOTGINT_A_DEV_TOUT_CHG		BIT(18)
+#define GOTGINT_HST_NEG_DET		BIT(17)
+#define GOTGINT_HST_NEG_SUC_STS_CHNG	BIT(9)
+#define GOTGINT_SES_REQ_SUC_STS_CHNG	BIT(8)
+#define GOTGINT_SES_END_DET		BIT(2)
+
+#define GAHBCFG				HSOTG_REG(0x008)
+#define GAHBCFG_AHB_SINGLE		BIT(23)
+#define GAHBCFG_NOTI_ALL_DMA_WRIT	BIT(22)
+#define GAHBCFG_REM_MEM_SUPP		BIT(21)
+#define GAHBCFG_P_TXF_EMP_LVL		BIT(8)
+#define GAHBCFG_NP_TXF_EMP_LVL		BIT(7)
+#define GAHBCFG_DMA_EN			BIT(5)
+#define GAHBCFG_HBSTLEN_MASK		(0xf << 1)
+#define GAHBCFG_HBSTLEN_SHIFT		1
+#define GAHBCFG_HBSTLEN_SINGLE		0
+#define GAHBCFG_HBSTLEN_INCR		1
+#define GAHBCFG_HBSTLEN_INCR4		3
+#define GAHBCFG_HBSTLEN_INCR8		5
+#define GAHBCFG_HBSTLEN_INCR16		7
+#define GAHBCFG_GLBL_INTR_EN		BIT(0)
+#define GAHBCFG_CTRL_MASK		(GAHBCFG_P_TXF_EMP_LVL | \
+					 GAHBCFG_NP_TXF_EMP_LVL | \
+					 GAHBCFG_DMA_EN | \
+					 GAHBCFG_GLBL_INTR_EN)
+
+#define GUSBCFG				HSOTG_REG(0x00C)
+#define GUSBCFG_FORCEDEVMODE		BIT(30)
+#define GUSBCFG_FORCEHOSTMODE		BIT(29)
+#define GUSBCFG_TXENDDELAY		BIT(28)
+#define GUSBCFG_ICTRAFFICPULLREMOVE	BIT(27)
+#define GUSBCFG_ICUSBCAP		BIT(26)
+#define GUSBCFG_ULPI_INT_PROT_DIS	BIT(25)
+#define GUSBCFG_INDICATORPASSTHROUGH	BIT(24)
+#define GUSBCFG_INDICATORCOMPLEMENT	BIT(23)
+#define GUSBCFG_TERMSELDLPULSE		BIT(22)
+#define GUSBCFG_ULPI_INT_VBUS_IND	BIT(21)
+#define GUSBCFG_ULPI_EXT_VBUS_DRV	BIT(20)
+#define GUSBCFG_ULPI_CLK_SUSP_M		BIT(19)
+#define GUSBCFG_ULPI_AUTO_RES		BIT(18)
+#define GUSBCFG_ULPI_FS_LS		BIT(17)
+#define GUSBCFG_OTG_UTMI_FS_SEL		BIT(16)
+#define GUSBCFG_PHY_LP_CLK_SEL		BIT(15)
+#define GUSBCFG_USBTRDTIM_MASK		(0xf << 10)
+#define GUSBCFG_USBTRDTIM_SHIFT		10
+#define GUSBCFG_HNPCAP			BIT(9)
+#define GUSBCFG_SRPCAP			BIT(8)
+#define GUSBCFG_DDRSEL			BIT(7)
+#define GUSBCFG_PHYSEL			BIT(6)
+#define GUSBCFG_FSINTF			BIT(5)
+#define GUSBCFG_ULPI_UTMI_SEL		BIT(4)
+#define GUSBCFG_PHYIF16			BIT(3)
+#define GUSBCFG_PHYIF8			(0 << 3)
+#define GUSBCFG_TOUTCAL_MASK		(0x7 << 0)
+#define GUSBCFG_TOUTCAL_SHIFT		0
+#define GUSBCFG_TOUTCAL_LIMIT		0x7
+#define GUSBCFG_TOUTCAL(_x)		((_x) << 0)
+
+#define GRSTCTL				HSOTG_REG(0x010)
+#define GRSTCTL_AHBIDLE			BIT(31)
+#define GRSTCTL_DMAREQ			BIT(30)
+#define GRSTCTL_TXFNUM_MASK		(0x1f << 6)
+#define GRSTCTL_TXFNUM_SHIFT		6
+#define GRSTCTL_TXFNUM_LIMIT		0x1f
+#define GRSTCTL_TXFNUM(_x)		((_x) << 6)
+#define GRSTCTL_TXFFLSH			BIT(5)
+#define GRSTCTL_RXFFLSH			BIT(4)
+#define GRSTCTL_IN_TKNQ_FLSH		BIT(3)
+#define GRSTCTL_FRMCNTRRST		BIT(2)
+#define GRSTCTL_HSFTRST			BIT(1)
+#define GRSTCTL_CSFTRST			BIT(0)
+
+#define GINTSTS				HSOTG_REG(0x014)
+#define GINTMSK				HSOTG_REG(0x018)
+#define GINTSTS_WKUPINT			BIT(31)
+#define GINTSTS_SESSREQINT		BIT(30)
+#define GINTSTS_DISCONNINT		BIT(29)
+#define GINTSTS_CONIDSTSCHNG		BIT(28)
+#define GINTSTS_LPMTRANRCVD		BIT(27)
+#define GINTSTS_PTXFEMP			BIT(26)
+#define GINTSTS_HCHINT			BIT(25)
+#define GINTSTS_PRTINT			BIT(24)
+#define GINTSTS_RESETDET		BIT(23)
+#define GINTSTS_FET_SUSP		BIT(22)
+#define GINTSTS_INCOMPL_IP		BIT(21)
+#define GINTSTS_INCOMPL_SOOUT		BIT(21)
+#define GINTSTS_INCOMPL_SOIN		BIT(20)
+#define GINTSTS_OEPINT			BIT(19)
+#define GINTSTS_IEPINT			BIT(18)
+#define GINTSTS_EPMIS			BIT(17)
+#define GINTSTS_RESTOREDONE		BIT(16)
+#define GINTSTS_EOPF			BIT(15)
+#define GINTSTS_ISOUTDROP		BIT(14)
+#define GINTSTS_ENUMDONE		BIT(13)
+#define GINTSTS_USBRST			BIT(12)
+#define GINTSTS_USBSUSP			BIT(11)
+#define GINTSTS_ERLYSUSP		BIT(10)
+#define GINTSTS_I2CINT			BIT(9)
+#define GINTSTS_ULPI_CK_INT		BIT(8)
+#define GINTSTS_GOUTNAKEFF		BIT(7)
+#define GINTSTS_GINNAKEFF		BIT(6)
+#define GINTSTS_NPTXFEMP		BIT(5)
+#define GINTSTS_RXFLVL			BIT(4)
+#define GINTSTS_SOF			BIT(3)
+#define GINTSTS_OTGINT			BIT(2)
+#define GINTSTS_MODEMIS			BIT(1)
+#define GINTSTS_CURMODE_HOST		BIT(0)
+
+#define GRXSTSR				HSOTG_REG(0x01C)
+#define GRXSTSP				HSOTG_REG(0x020)
+#define GRXSTS_FN_MASK			(0x7f << 25)
+#define GRXSTS_FN_SHIFT			25
+#define GRXSTS_PKTSTS_MASK		(0xf << 17)
+#define GRXSTS_PKTSTS_SHIFT		17
+#define GRXSTS_PKTSTS_GLOBALOUTNAK	1
+#define GRXSTS_PKTSTS_OUTRX		2
+#define GRXSTS_PKTSTS_HCHIN		2
+#define GRXSTS_PKTSTS_OUTDONE		3
+#define GRXSTS_PKTSTS_HCHIN_XFER_COMP	3
+#define GRXSTS_PKTSTS_SETUPDONE		4
+#define GRXSTS_PKTSTS_DATATOGGLEERR	5
+#define GRXSTS_PKTSTS_SETUPRX		6
+#define GRXSTS_PKTSTS_HCHHALTED		7
+#define GRXSTS_HCHNUM_MASK		(0xf << 0)
+#define GRXSTS_HCHNUM_SHIFT		0
+#define GRXSTS_DPID_MASK		(0x3 << 15)
+#define GRXSTS_DPID_SHIFT		15
+#define GRXSTS_BYTECNT_MASK		(0x7ff << 4)
+#define GRXSTS_BYTECNT_SHIFT		4
+#define GRXSTS_EPNUM_MASK		(0xf << 0)
+#define GRXSTS_EPNUM_SHIFT		0
+
+#define GRXFSIZ				HSOTG_REG(0x024)
+#define GRXFSIZ_DEPTH_MASK		(0xffff << 0)
+#define GRXFSIZ_DEPTH_SHIFT		0
+
+#define GNPTXFSIZ			HSOTG_REG(0x028)
+/* Use FIFOSIZE_* constants to access this register */
+
+#define GNPTXSTS			HSOTG_REG(0x02C)
+#define GNPTXSTS_NP_TXQ_TOP_MASK		(0x7f << 24)
+#define GNPTXSTS_NP_TXQ_TOP_SHIFT		24
+#define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK		(0xff << 16)
+#define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT		16
+#define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v)	(((_v) >> 16) & 0xff)
+#define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK		(0xffff << 0)
+#define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT		0
+#define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v)	(((_v) >> 0) & 0xffff)
+
+#define GI2CCTL				HSOTG_REG(0x0030)
+#define GI2CCTL_BSYDNE			BIT(31)
+#define GI2CCTL_RW			BIT(30)
+#define GI2CCTL_I2CDATSE0		BIT(28)
+#define GI2CCTL_I2CDEVADDR_MASK		(0x3 << 26)
+#define GI2CCTL_I2CDEVADDR_SHIFT	26
+#define GI2CCTL_I2CSUSPCTL		BIT(25)
+#define GI2CCTL_ACK			BIT(24)
+#define GI2CCTL_I2CEN			BIT(23)
+#define GI2CCTL_ADDR_MASK		(0x7f << 16)
+#define GI2CCTL_ADDR_SHIFT		16
+#define GI2CCTL_REGADDR_MASK		(0xff << 8)
+#define GI2CCTL_REGADDR_SHIFT		8
+#define GI2CCTL_RWDATA_MASK		(0xff << 0)
+#define GI2CCTL_RWDATA_SHIFT		0
+
+#define GPVNDCTL			HSOTG_REG(0x0034)
+#define GGPIO				HSOTG_REG(0x0038)
+#define GGPIO_STM32_OTG_GCCFG_PWRDWN	BIT(16)
+
+#define GUID				HSOTG_REG(0x003c)
+#define GSNPSID				HSOTG_REG(0x0040)
+#define GHWCFG1				HSOTG_REG(0x0044)
+#define GSNPSID_ID_MASK			GENMASK(31, 16)
+
+#define GHWCFG2				HSOTG_REG(0x0048)
+#define GHWCFG2_OTG_ENABLE_IC_USB		BIT(31)
+#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK		(0x1f << 26)
+#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT		26
+#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK	(0x3 << 24)
+#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT	24
+#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK	(0x3 << 22)
+#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT	22
+#define GHWCFG2_MULTI_PROC_INT			BIT(20)
+#define GHWCFG2_DYNAMIC_FIFO			BIT(19)
+#define GHWCFG2_PERIO_EP_SUPPORTED		BIT(18)
+#define GHWCFG2_NUM_HOST_CHAN_MASK		(0xf << 14)
+#define GHWCFG2_NUM_HOST_CHAN_SHIFT		14
+#define GHWCFG2_NUM_DEV_EP_MASK			(0xf << 10)
+#define GHWCFG2_NUM_DEV_EP_SHIFT		10
+#define GHWCFG2_FS_PHY_TYPE_MASK		(0x3 << 8)
+#define GHWCFG2_FS_PHY_TYPE_SHIFT		8
+#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED	0
+#define GHWCFG2_FS_PHY_TYPE_DEDICATED		1
+#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI		2
+#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI		3
+#define GHWCFG2_HS_PHY_TYPE_MASK		(0x3 << 6)
+#define GHWCFG2_HS_PHY_TYPE_SHIFT		6
+#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED	0
+#define GHWCFG2_HS_PHY_TYPE_UTMI		1
+#define GHWCFG2_HS_PHY_TYPE_ULPI		2
+#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI		3
+#define GHWCFG2_POINT2POINT			BIT(5)
+#define GHWCFG2_ARCHITECTURE_MASK		(0x3 << 3)
+#define GHWCFG2_ARCHITECTURE_SHIFT		3
+#define GHWCFG2_SLAVE_ONLY_ARCH			0
+#define GHWCFG2_EXT_DMA_ARCH			1
+#define GHWCFG2_INT_DMA_ARCH			2
+#define GHWCFG2_OP_MODE_MASK			(0x7 << 0)
+#define GHWCFG2_OP_MODE_SHIFT			0
+#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE		0
+#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE	1
+#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE	2
+#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE	3
+#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE	4
+#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST	5
+#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST	6
+#define GHWCFG2_OP_MODE_UNDEFINED		7
+
+#define GHWCFG3				HSOTG_REG(0x004c)
+#define GHWCFG3_DFIFO_DEPTH_MASK		(0xffff << 16)
+#define GHWCFG3_DFIFO_DEPTH_SHIFT		16
+#define GHWCFG3_OTG_LPM_EN			BIT(15)
+#define GHWCFG3_BC_SUPPORT			BIT(14)
+#define GHWCFG3_OTG_ENABLE_HSIC			BIT(13)
+#define GHWCFG3_ADP_SUPP			BIT(12)
+#define GHWCFG3_SYNCH_RESET_TYPE		BIT(11)
+#define GHWCFG3_OPTIONAL_FEATURES		BIT(10)
+#define GHWCFG3_VENDOR_CTRL_IF			BIT(9)
+#define GHWCFG3_I2C				BIT(8)
+#define GHWCFG3_OTG_FUNC			BIT(7)
+#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK	(0x7 << 4)
+#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT	4
+#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK	(0xf << 0)
+#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT	0
+
+#define GHWCFG4				HSOTG_REG(0x0050)
+#define GHWCFG4_DESC_DMA_DYN			BIT(31)
+#define GHWCFG4_DESC_DMA			BIT(30)
+#define GHWCFG4_NUM_IN_EPS_MASK			(0xf << 26)
+#define GHWCFG4_NUM_IN_EPS_SHIFT		26
+#define GHWCFG4_DED_FIFO_EN			BIT(25)
+#define GHWCFG4_DED_FIFO_SHIFT		25
+#define GHWCFG4_SESSION_END_FILT_EN		BIT(24)
+#define GHWCFG4_B_VALID_FILT_EN			BIT(23)
+#define GHWCFG4_A_VALID_FILT_EN			BIT(22)
+#define GHWCFG4_VBUS_VALID_FILT_EN		BIT(21)
+#define GHWCFG4_IDDIG_FILT_EN			BIT(20)
+#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK	(0xf << 16)
+#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT	16
+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK	(0x3 << 14)
+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT	14
+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8		0
+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16		1
+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16	2
+#define GHWCFG4_ACG_SUPPORTED			BIT(12)
+#define GHWCFG4_IPG_ISOC_SUPPORTED		BIT(11)
+#define GHWCFG4_SERVICE_INTERVAL_SUPPORTED      BIT(10)
+#define GHWCFG4_XHIBER				BIT(7)
+#define GHWCFG4_HIBER				BIT(6)
+#define GHWCFG4_MIN_AHB_FREQ			BIT(5)
+#define GHWCFG4_POWER_OPTIMIZ			BIT(4)
+#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK	(0xf << 0)
+#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT	0
+
+#define GLPMCFG				HSOTG_REG(0x0054)
+#define GLPMCFG_INVSELHSIC		BIT(31)
+#define GLPMCFG_HSICCON			BIT(30)
+#define GLPMCFG_RSTRSLPSTS		BIT(29)
+#define GLPMCFG_ENBESL			BIT(28)
+#define GLPMCFG_LPM_RETRYCNT_STS_MASK	(0x7 << 25)
+#define GLPMCFG_LPM_RETRYCNT_STS_SHIFT	25
+#define GLPMCFG_SNDLPM			BIT(24)
+#define GLPMCFG_RETRY_CNT_MASK		(0x7 << 21)
+#define GLPMCFG_RETRY_CNT_SHIFT		21
+#define GLPMCFG_LPM_REJECT_CTRL_CONTROL	BIT(21)
+#define GLPMCFG_LPM_ACCEPT_CTRL_ISOC	BIT(22)
+#define GLPMCFG_LPM_CHNL_INDX_MASK	(0xf << 17)
+#define GLPMCFG_LPM_CHNL_INDX_SHIFT	17
+#define GLPMCFG_L1RESUMEOK		BIT(16)
+#define GLPMCFG_SLPSTS			BIT(15)
+#define GLPMCFG_COREL1RES_MASK		(0x3 << 13)
+#define GLPMCFG_COREL1RES_SHIFT		13
+#define GLPMCFG_HIRD_THRES_MASK		(0x1f << 8)
+#define GLPMCFG_HIRD_THRES_SHIFT	8
+#define GLPMCFG_HIRD_THRES_EN		(0x10 << 8)
+#define GLPMCFG_ENBLSLPM		BIT(7)
+#define GLPMCFG_BREMOTEWAKE		BIT(6)
+#define GLPMCFG_HIRD_MASK		(0xf << 2)
+#define GLPMCFG_HIRD_SHIFT		2
+#define GLPMCFG_APPL1RES		BIT(1)
+#define GLPMCFG_LPMCAP			BIT(0)
+
+#define GPWRDN				HSOTG_REG(0x0058)
+#define GPWRDN_MULT_VAL_ID_BC_MASK	(0x1f << 24)
+#define GPWRDN_MULT_VAL_ID_BC_SHIFT	24
+#define GPWRDN_ADP_INT			BIT(23)
+#define GPWRDN_BSESSVLD			BIT(22)
+#define GPWRDN_IDSTS			BIT(21)
+#define GPWRDN_LINESTATE_MASK		(0x3 << 19)
+#define GPWRDN_LINESTATE_SHIFT		19
+#define GPWRDN_STS_CHGINT_MSK		BIT(18)
+#define GPWRDN_STS_CHGINT		BIT(17)
+#define GPWRDN_SRP_DET_MSK		BIT(16)
+#define GPWRDN_SRP_DET			BIT(15)
+#define GPWRDN_CONNECT_DET_MSK		BIT(14)
+#define GPWRDN_CONNECT_DET		BIT(13)
+#define GPWRDN_DISCONN_DET_MSK		BIT(12)
+#define GPWRDN_DISCONN_DET		BIT(11)
+#define GPWRDN_RST_DET_MSK		BIT(10)
+#define GPWRDN_RST_DET			BIT(9)
+#define GPWRDN_LNSTSCHG_MSK		BIT(8)
+#define GPWRDN_LNSTSCHG			BIT(7)
+#define GPWRDN_DIS_VBUS			BIT(6)
+#define GPWRDN_PWRDNSWTCH		BIT(5)
+#define GPWRDN_PWRDNRSTN		BIT(4)
+#define GPWRDN_PWRDNCLMP		BIT(3)
+#define GPWRDN_RESTORE			BIT(2)
+#define GPWRDN_PMUACTV			BIT(1)
+#define GPWRDN_PMUINTSEL		BIT(0)
+
+#define GDFIFOCFG			HSOTG_REG(0x005c)
+#define GDFIFOCFG_EPINFOBASE_MASK	(0xffff << 16)
+#define GDFIFOCFG_EPINFOBASE_SHIFT	16
+#define GDFIFOCFG_GDFIFOCFG_MASK	(0xffff << 0)
+#define GDFIFOCFG_GDFIFOCFG_SHIFT	0
+
+#define ADPCTL				HSOTG_REG(0x0060)
+#define ADPCTL_AR_MASK			(0x3 << 27)
+#define ADPCTL_AR_SHIFT			27
+#define ADPCTL_ADP_TMOUT_INT_MSK	BIT(26)
+#define ADPCTL_ADP_SNS_INT_MSK		BIT(25)
+#define ADPCTL_ADP_PRB_INT_MSK		BIT(24)
+#define ADPCTL_ADP_TMOUT_INT		BIT(23)
+#define ADPCTL_ADP_SNS_INT		BIT(22)
+#define ADPCTL_ADP_PRB_INT		BIT(21)
+#define ADPCTL_ADPENA			BIT(20)
+#define ADPCTL_ADPRES			BIT(19)
+#define ADPCTL_ENASNS			BIT(18)
+#define ADPCTL_ENAPRB			BIT(17)
+#define ADPCTL_RTIM_MASK		(0x7ff << 6)
+#define ADPCTL_RTIM_SHIFT		6
+#define ADPCTL_PRB_PER_MASK		(0x3 << 4)
+#define ADPCTL_PRB_PER_SHIFT		4
+#define ADPCTL_PRB_DELTA_MASK		(0x3 << 2)
+#define ADPCTL_PRB_DELTA_SHIFT		2
+#define ADPCTL_PRB_DSCHRG_MASK		(0x3 << 0)
+#define ADPCTL_PRB_DSCHRG_SHIFT		0
+
+#define GREFCLK				    HSOTG_REG(0x0064)
+#define GREFCLK_REFCLKPER_MASK		    (0x1ffff << 15)
+#define GREFCLK_REFCLKPER_SHIFT		    15
+#define GREFCLK_REF_CLK_MODE		    BIT(14)
+#define GREFCLK_SOF_CNT_WKUP_ALERT_MASK	    (0x3ff)
+#define GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT    0
+
+#define GINTMSK2			HSOTG_REG(0x0068)
+#define GINTMSK2_WKUP_ALERT_INT_MSK	BIT(0)
+
+#define GINTSTS2			HSOTG_REG(0x006c)
+#define GINTSTS2_WKUP_ALERT_INT		BIT(0)
+
+#define HPTXFSIZ			HSOTG_REG(0x100)
+/* Use FIFOSIZE_* constants to access this register */
+
+#define DPTXFSIZN(_a)			HSOTG_REG(0x104 + (((_a) - 1) * 4))
+/* Use FIFOSIZE_* constants to access this register */
+
+/* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
+#define FIFOSIZE_DEPTH_MASK		(0xffff << 16)
+#define FIFOSIZE_DEPTH_SHIFT		16
+#define FIFOSIZE_STARTADDR_MASK		(0xffff << 0)
+#define FIFOSIZE_STARTADDR_SHIFT	0
+#define FIFOSIZE_DEPTH_GET(_x)		(((_x) >> 16) & 0xffff)
+
+/* Device mode registers */
+
+#define DCFG				HSOTG_REG(0x800)
+#define DCFG_DESCDMA_EN			BIT(23)
+#define DCFG_EPMISCNT_MASK		(0x1f << 18)
+#define DCFG_EPMISCNT_SHIFT		18
+#define DCFG_EPMISCNT_LIMIT		0x1f
+#define DCFG_EPMISCNT(_x)		((_x) << 18)
+#define DCFG_IPG_ISOC_SUPPORDED		BIT(17)
+#define DCFG_PERFRINT_MASK		(0x3 << 11)
+#define DCFG_PERFRINT_SHIFT		11
+#define DCFG_PERFRINT_LIMIT		0x3
+#define DCFG_PERFRINT(_x)		((_x) << 11)
+#define DCFG_DEVADDR_MASK		(0x7f << 4)
+#define DCFG_DEVADDR_SHIFT		4
+#define DCFG_DEVADDR_LIMIT		0x7f
+#define DCFG_DEVADDR(_x)		((_x) << 4)
+#define DCFG_NZ_STS_OUT_HSHK		BIT(2)
+#define DCFG_DEVSPD_MASK		(0x3 << 0)
+#define DCFG_DEVSPD_SHIFT		0
+#define DCFG_DEVSPD_HS			0
+#define DCFG_DEVSPD_FS			1
+#define DCFG_DEVSPD_LS			2
+#define DCFG_DEVSPD_FS48		3
+
+#define DCTL				HSOTG_REG(0x804)
+#define DCTL_SERVICE_INTERVAL_SUPPORTED BIT(19)
+#define DCTL_PWRONPRGDONE		BIT(11)
+#define DCTL_CGOUTNAK			BIT(10)
+#define DCTL_SGOUTNAK			BIT(9)
+#define DCTL_CGNPINNAK			BIT(8)
+#define DCTL_SGNPINNAK			BIT(7)
+#define DCTL_TSTCTL_MASK		(0x7 << 4)
+#define DCTL_TSTCTL_SHIFT		4
+#define DCTL_GOUTNAKSTS			BIT(3)
+#define DCTL_GNPINNAKSTS		BIT(2)
+#define DCTL_SFTDISCON			BIT(1)
+#define DCTL_RMTWKUPSIG			BIT(0)
+
+#define DSTS				HSOTG_REG(0x808)
+#define DSTS_SOFFN_MASK			(0x3fff << 8)
+#define DSTS_SOFFN_SHIFT		8
+#define DSTS_SOFFN_LIMIT		0x3fff
+#define DSTS_SOFFN(_x)			((_x) << 8)
+#define DSTS_ERRATICERR			BIT(3)
+#define DSTS_ENUMSPD_MASK		(0x3 << 1)
+#define DSTS_ENUMSPD_SHIFT		1
+#define DSTS_ENUMSPD_HS			0
+#define DSTS_ENUMSPD_FS			1
+#define DSTS_ENUMSPD_LS			2
+#define DSTS_ENUMSPD_FS48		3
+#define DSTS_SUSPSTS			BIT(0)
+
+#define DIEPMSK				HSOTG_REG(0x810)
+#define DIEPMSK_NAKMSK			BIT(13)
+#define DIEPMSK_BNAININTRMSK		BIT(9)
+#define DIEPMSK_TXFIFOUNDRNMSK		BIT(8)
+#define DIEPMSK_TXFIFOEMPTY		BIT(7)
+#define DIEPMSK_INEPNAKEFFMSK		BIT(6)
+#define DIEPMSK_INTKNEPMISMSK		BIT(5)
+#define DIEPMSK_INTKNTXFEMPMSK		BIT(4)
+#define DIEPMSK_TIMEOUTMSK		BIT(3)
+#define DIEPMSK_AHBERRMSK		BIT(2)
+#define DIEPMSK_EPDISBLDMSK		BIT(1)
+#define DIEPMSK_XFERCOMPLMSK		BIT(0)
+
+#define DOEPMSK				HSOTG_REG(0x814)
+#define DOEPMSK_BNAMSK			BIT(9)
+#define DOEPMSK_BACK2BACKSETUP		BIT(6)
+#define DOEPMSK_STSPHSERCVDMSK		BIT(5)
+#define DOEPMSK_OUTTKNEPDISMSK		BIT(4)
+#define DOEPMSK_SETUPMSK		BIT(3)
+#define DOEPMSK_AHBERRMSK		BIT(2)
+#define DOEPMSK_EPDISBLDMSK		BIT(1)
+#define DOEPMSK_XFERCOMPLMSK		BIT(0)
+
+#define DAINT				HSOTG_REG(0x818)
+#define DAINTMSK			HSOTG_REG(0x81C)
+#define DAINT_OUTEP_SHIFT		16
+#define DAINT_OUTEP(_x)			(1 << ((_x) + 16))
+#define DAINT_INEP(_x)			(1 << (_x))
+
+#define DTKNQR1				HSOTG_REG(0x820)
+#define DTKNQR2				HSOTG_REG(0x824)
+#define DTKNQR3				HSOTG_REG(0x830)
+#define DTKNQR4				HSOTG_REG(0x834)
+#define DIEPEMPMSK			HSOTG_REG(0x834)
+
+#define DVBUSDIS			HSOTG_REG(0x828)
+#define DVBUSPULSE			HSOTG_REG(0x82C)
+
+#define DIEPCTL0			HSOTG_REG(0x900)
+#define DIEPCTL(_a)			HSOTG_REG(0x900 + ((_a) * 0x20))
+
+#define DOEPCTL0			HSOTG_REG(0xB00)
+#define DOEPCTL(_a)			HSOTG_REG(0xB00 + ((_a) * 0x20))
+
+/* EP0 specialness:
+ * bits[29..28] - reserved (no SetD0PID, SetD1PID)
+ * bits[25..22] - should always be zero, this isn't a periodic endpoint
+ * bits[10..0]  - MPS setting different for EP0
+ */
+#define D0EPCTL_MPS_MASK		(0x3 << 0)
+#define D0EPCTL_MPS_SHIFT		0
+#define D0EPCTL_MPS_64			0
+#define D0EPCTL_MPS_32			1
+#define D0EPCTL_MPS_16			2
+#define D0EPCTL_MPS_8			3
+
+#define DXEPCTL_EPENA			BIT(31)
+#define DXEPCTL_EPDIS			BIT(30)
+#define DXEPCTL_SETD1PID		BIT(29)
+#define DXEPCTL_SETODDFR		BIT(29)
+#define DXEPCTL_SETD0PID		BIT(28)
+#define DXEPCTL_SETEVENFR		BIT(28)
+#define DXEPCTL_SNAK			BIT(27)
+#define DXEPCTL_CNAK			BIT(26)
+#define DXEPCTL_TXFNUM_MASK		(0xf << 22)
+#define DXEPCTL_TXFNUM_SHIFT		22
+#define DXEPCTL_TXFNUM_LIMIT		0xf
+#define DXEPCTL_TXFNUM(_x)		((_x) << 22)
+#define DXEPCTL_STALL			BIT(21)
+#define DXEPCTL_SNP			BIT(20)
+#define DXEPCTL_EPTYPE_MASK		(0x3 << 18)
+#define DXEPCTL_EPTYPE_CONTROL		(0x0 << 18)
+#define DXEPCTL_EPTYPE_ISO		(0x1 << 18)
+#define DXEPCTL_EPTYPE_BULK		(0x2 << 18)
+#define DXEPCTL_EPTYPE_INTERRUPT	(0x3 << 18)
+
+#define DXEPCTL_NAKSTS			BIT(17)
+#define DXEPCTL_DPID			BIT(16)
+#define DXEPCTL_EOFRNUM			BIT(16)
+#define DXEPCTL_USBACTEP		BIT(15)
+#define DXEPCTL_NEXTEP_MASK		(0xf << 11)
+#define DXEPCTL_NEXTEP_SHIFT		11
+#define DXEPCTL_NEXTEP_LIMIT		0xf
+#define DXEPCTL_NEXTEP(_x)		((_x) << 11)
+#define DXEPCTL_MPS_MASK		(0x7ff << 0)
+#define DXEPCTL_MPS_SHIFT		0
+#define DXEPCTL_MPS_LIMIT		0x7ff
+#define DXEPCTL_MPS(_x)			((_x) << 0)
+
+#define DIEPINT(_a)			HSOTG_REG(0x908 + ((_a) * 0x20))
+#define DOEPINT(_a)			HSOTG_REG(0xB08 + ((_a) * 0x20))
+#define DXEPINT_SETUP_RCVD		BIT(15)
+#define DXEPINT_NYETINTRPT		BIT(14)
+#define DXEPINT_NAKINTRPT		BIT(13)
+#define DXEPINT_BBLEERRINTRPT		BIT(12)
+#define DXEPINT_PKTDRPSTS		BIT(11)
+#define DXEPINT_BNAINTR			BIT(9)
+#define DXEPINT_TXFIFOUNDRN		BIT(8)
+#define DXEPINT_OUTPKTERR		BIT(8)
+#define DXEPINT_TXFEMP			BIT(7)
+#define DXEPINT_INEPNAKEFF		BIT(6)
+#define DXEPINT_BACK2BACKSETUP		BIT(6)
+#define DXEPINT_INTKNEPMIS		BIT(5)
+#define DXEPINT_STSPHSERCVD		BIT(5)
+#define DXEPINT_INTKNTXFEMP		BIT(4)
+#define DXEPINT_OUTTKNEPDIS		BIT(4)
+#define DXEPINT_TIMEOUT			BIT(3)
+#define DXEPINT_SETUP			BIT(3)
+#define DXEPINT_AHBERR			BIT(2)
+#define DXEPINT_EPDISBLD		BIT(1)
+#define DXEPINT_XFERCOMPL		BIT(0)
+
+#define DIEPTSIZ0			HSOTG_REG(0x910)
+#define DIEPTSIZ0_PKTCNT_MASK		(0x3 << 19)
+#define DIEPTSIZ0_PKTCNT_SHIFT		19
+#define DIEPTSIZ0_PKTCNT_LIMIT		0x3
+#define DIEPTSIZ0_PKTCNT(_x)		((_x) << 19)
+#define DIEPTSIZ0_XFERSIZE_MASK		(0x7f << 0)
+#define DIEPTSIZ0_XFERSIZE_SHIFT	0
+#define DIEPTSIZ0_XFERSIZE_LIMIT	0x7f
+#define DIEPTSIZ0_XFERSIZE(_x)		((_x) << 0)
+
+#define DOEPTSIZ0			HSOTG_REG(0xB10)
+#define DOEPTSIZ0_SUPCNT_MASK		(0x3 << 29)
+#define DOEPTSIZ0_SUPCNT_SHIFT		29
+#define DOEPTSIZ0_SUPCNT_LIMIT		0x3
+#define DOEPTSIZ0_SUPCNT(_x)		((_x) << 29)
+#define DOEPTSIZ0_PKTCNT		BIT(19)
+#define DOEPTSIZ0_XFERSIZE_MASK		(0x7f << 0)
+#define DOEPTSIZ0_XFERSIZE_SHIFT	0
+
+#define DIEPTSIZ(_a)			HSOTG_REG(0x910 + ((_a) * 0x20))
+#define DOEPTSIZ(_a)			HSOTG_REG(0xB10 + ((_a) * 0x20))
+#define DXEPTSIZ_MC_MASK		(0x3 << 29)
+#define DXEPTSIZ_MC_SHIFT		29
+#define DXEPTSIZ_MC_LIMIT		0x3
+#define DXEPTSIZ_MC(_x)			((_x) << 29)
+#define DXEPTSIZ_PKTCNT_MASK		(0x3ff << 19)
+#define DXEPTSIZ_PKTCNT_SHIFT		19
+#define DXEPTSIZ_PKTCNT_LIMIT		0x3ff
+#define DXEPTSIZ_PKTCNT_GET(_v)		(((_v) >> 19) & 0x3ff)
+#define DXEPTSIZ_PKTCNT(_x)		((_x) << 19)
+#define DXEPTSIZ_XFERSIZE_MASK		(0x7ffff << 0)
+#define DXEPTSIZ_XFERSIZE_SHIFT		0
+#define DXEPTSIZ_XFERSIZE_LIMIT		0x7ffff
+#define DXEPTSIZ_XFERSIZE_GET(_v)	(((_v) >> 0) & 0x7ffff)
+#define DXEPTSIZ_XFERSIZE(_x)		((_x) << 0)
+
+#define DIEPDMA(_a)			HSOTG_REG(0x914 + ((_a) * 0x20))
+#define DOEPDMA(_a)			HSOTG_REG(0xB14 + ((_a) * 0x20))
+
+#define DTXFSTS(_a)			HSOTG_REG(0x918 + ((_a) * 0x20))
+
+#define PCGCTL				HSOTG_REG(0x0e00)
+#define PCGCTL_IF_DEV_MODE		BIT(31)
+#define PCGCTL_P2HD_PRT_SPD_MASK	(0x3 << 29)
+#define PCGCTL_P2HD_PRT_SPD_SHIFT	29
+#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK	(0x3 << 27)
+#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT	27
+#define PCGCTL_MAC_DEV_ADDR_MASK	(0x7f << 20)
+#define PCGCTL_MAC_DEV_ADDR_SHIFT	20
+#define PCGCTL_MAX_TERMSEL		BIT(19)
+#define PCGCTL_MAX_XCVRSELECT_MASK	(0x3 << 17)
+#define PCGCTL_MAX_XCVRSELECT_SHIFT	17
+#define PCGCTL_PORT_POWER		BIT(16)
+#define PCGCTL_PRT_CLK_SEL_MASK		(0x3 << 14)
+#define PCGCTL_PRT_CLK_SEL_SHIFT	14
+#define PCGCTL_ESS_REG_RESTORED		BIT(13)
+#define PCGCTL_EXTND_HIBER_SWITCH	BIT(12)
+#define PCGCTL_EXTND_HIBER_PWRCLMP	BIT(11)
+#define PCGCTL_ENBL_EXTND_HIBER		BIT(10)
+#define PCGCTL_RESTOREMODE		BIT(9)
+#define PCGCTL_RESETAFTSUSP		BIT(8)
+#define PCGCTL_DEEP_SLEEP		BIT(7)
+#define PCGCTL_PHY_IN_SLEEP		BIT(6)
+#define PCGCTL_ENBL_SLEEP_GATING	BIT(5)
+#define PCGCTL_RSTPDWNMODULE		BIT(3)
+#define PCGCTL_PWRCLMP			BIT(2)
+#define PCGCTL_GATEHCLK			BIT(1)
+#define PCGCTL_STOPPCLK			BIT(0)
+
+#define PCGCCTL1                        HSOTG_REG(0xe04)
+#define PCGCCTL1_TIMER                  (0x3 << 1)
+#define PCGCCTL1_GATEEN                 BIT(0)
+
+#define EPFIFO(_a)			HSOTG_REG(0x1000 + ((_a) * 0x1000))
+
+/* Host Mode Registers */
+
+#define HCFG				HSOTG_REG(0x0400)
+#define HCFG_MODECHTIMEN		BIT(31)
+#define HCFG_PERSCHEDENA		BIT(26)
+#define HCFG_FRLISTEN_MASK		(0x3 << 24)
+#define HCFG_FRLISTEN_SHIFT		24
+#define HCFG_FRLISTEN_8				(0 << 24)
+#define FRLISTEN_8_SIZE				8
+#define HCFG_FRLISTEN_16			BIT(24)
+#define FRLISTEN_16_SIZE			16
+#define HCFG_FRLISTEN_32			(2 << 24)
+#define FRLISTEN_32_SIZE			32
+#define HCFG_FRLISTEN_64			(3 << 24)
+#define FRLISTEN_64_SIZE			64
+#define HCFG_DESCDMA			BIT(23)
+#define HCFG_RESVALID_MASK		(0xff << 8)
+#define HCFG_RESVALID_SHIFT		8
+#define HCFG_ENA32KHZ			BIT(7)
+#define HCFG_FSLSSUPP			BIT(2)
+#define HCFG_FSLSPCLKSEL_MASK		(0x3 << 0)
+#define HCFG_FSLSPCLKSEL_SHIFT		0
+#define HCFG_FSLSPCLKSEL_30_60_MHZ	0
+#define HCFG_FSLSPCLKSEL_48_MHZ		1
+#define HCFG_FSLSPCLKSEL_6_MHZ		2
+
+#define HFIR				HSOTG_REG(0x0404)
+#define HFIR_FRINT_MASK			(0xffff << 0)
+#define HFIR_FRINT_SHIFT		0
+#define HFIR_RLDCTRL			BIT(16)
+
+#define HFNUM				HSOTG_REG(0x0408)
+#define HFNUM_FRREM_MASK		(0xffff << 16)
+#define HFNUM_FRREM_SHIFT		16
+#define HFNUM_FRNUM_MASK		(0xffff << 0)
+#define HFNUM_FRNUM_SHIFT		0
+#define HFNUM_MAX_FRNUM			0x3fff
+
+#define HPTXSTS				HSOTG_REG(0x0410)
+#define TXSTS_QTOP_ODD			BIT(31)
+#define TXSTS_QTOP_CHNEP_MASK		(0xf << 27)
+#define TXSTS_QTOP_CHNEP_SHIFT		27
+#define TXSTS_QTOP_TOKEN_MASK		(0x3 << 25)
+#define TXSTS_QTOP_TOKEN_SHIFT		25
+#define TXSTS_QTOP_TERMINATE		BIT(24)
+#define TXSTS_QSPCAVAIL_MASK		(0xff << 16)
+#define TXSTS_QSPCAVAIL_SHIFT		16
+#define TXSTS_FSPCAVAIL_MASK		(0xffff << 0)
+#define TXSTS_FSPCAVAIL_SHIFT		0
+
+#define HAINT				HSOTG_REG(0x0414)
+#define HAINTMSK			HSOTG_REG(0x0418)
+#define HFLBADDR			HSOTG_REG(0x041c)
+
+#define HPRT0				HSOTG_REG(0x0440)
+#define HPRT0_SPD_MASK			(0x3 << 17)
+#define HPRT0_SPD_SHIFT			17
+#define HPRT0_SPD_HIGH_SPEED		0
+#define HPRT0_SPD_FULL_SPEED		1
+#define HPRT0_SPD_LOW_SPEED		2
+#define HPRT0_TSTCTL_MASK		(0xf << 13)
+#define HPRT0_TSTCTL_SHIFT		13
+#define HPRT0_PWR			BIT(12)
+#define HPRT0_LNSTS_MASK		(0x3 << 10)
+#define HPRT0_LNSTS_SHIFT		10
+#define HPRT0_RST			BIT(8)
+#define HPRT0_SUSP			BIT(7)
+#define HPRT0_RES			BIT(6)
+#define HPRT0_OVRCURRCHG		BIT(5)
+#define HPRT0_OVRCURRACT		BIT(4)
+#define HPRT0_ENACHG			BIT(3)
+#define HPRT0_ENA			BIT(2)
+#define HPRT0_CONNDET			BIT(1)
+#define HPRT0_CONNSTS			BIT(0)
+
+#define HCCHAR(_ch)			HSOTG_REG(0x0500 + 0x20 * (_ch))
+#define HCCHAR_CHENA			BIT(31)
+#define HCCHAR_CHDIS			BIT(30)
+#define HCCHAR_ODDFRM			BIT(29)
+#define HCCHAR_DEVADDR_MASK		(0x7f << 22)
+#define HCCHAR_DEVADDR_SHIFT		22
+#define HCCHAR_MULTICNT_MASK		(0x3 << 20)
+#define HCCHAR_MULTICNT_SHIFT		20
+#define HCCHAR_EPTYPE_MASK		(0x3 << 18)
+#define HCCHAR_EPTYPE_SHIFT		18
+#define HCCHAR_LSPDDEV			BIT(17)
+#define HCCHAR_EPDIR			BIT(15)
+#define HCCHAR_EPNUM_MASK		(0xf << 11)
+#define HCCHAR_EPNUM_SHIFT		11
+#define HCCHAR_MPS_MASK			(0x7ff << 0)
+#define HCCHAR_MPS_SHIFT		0
+
+#define HCSPLT(_ch)			HSOTG_REG(0x0504 + 0x20 * (_ch))
+#define HCSPLT_SPLTENA			BIT(31)
+#define HCSPLT_COMPSPLT			BIT(16)
+#define HCSPLT_XACTPOS_MASK		(0x3 << 14)
+#define HCSPLT_XACTPOS_SHIFT		14
+#define HCSPLT_XACTPOS_MID		0
+#define HCSPLT_XACTPOS_END		1
+#define HCSPLT_XACTPOS_BEGIN		2
+#define HCSPLT_XACTPOS_ALL		3
+#define HCSPLT_HUBADDR_MASK		(0x7f << 7)
+#define HCSPLT_HUBADDR_SHIFT		7
+#define HCSPLT_PRTADDR_MASK		(0x7f << 0)
+#define HCSPLT_PRTADDR_SHIFT		0
+
+#define HCINT(_ch)			HSOTG_REG(0x0508 + 0x20 * (_ch))
+#define HCINTMSK(_ch)			HSOTG_REG(0x050c + 0x20 * (_ch))
+#define HCINTMSK_RESERVED14_31		(0x3ffff << 14)
+#define HCINTMSK_FRM_LIST_ROLL		BIT(13)
+#define HCINTMSK_XCS_XACT		BIT(12)
+#define HCINTMSK_BNA			BIT(11)
+#define HCINTMSK_DATATGLERR		BIT(10)
+#define HCINTMSK_FRMOVRUN		BIT(9)
+#define HCINTMSK_BBLERR			BIT(8)
+#define HCINTMSK_XACTERR		BIT(7)
+#define HCINTMSK_NYET			BIT(6)
+#define HCINTMSK_ACK			BIT(5)
+#define HCINTMSK_NAK			BIT(4)
+#define HCINTMSK_STALL			BIT(3)
+#define HCINTMSK_AHBERR			BIT(2)
+#define HCINTMSK_CHHLTD			BIT(1)
+#define HCINTMSK_XFERCOMPL		BIT(0)
+
+#define HCTSIZ(_ch)			HSOTG_REG(0x0510 + 0x20 * (_ch))
+#define TSIZ_DOPNG			BIT(31)
+#define TSIZ_SC_MC_PID_MASK		(0x3 << 29)
+#define TSIZ_SC_MC_PID_SHIFT		29
+#define TSIZ_SC_MC_PID_DATA0		0
+#define TSIZ_SC_MC_PID_DATA2		1
+#define TSIZ_SC_MC_PID_DATA1		2
+#define TSIZ_SC_MC_PID_MDATA		3
+#define TSIZ_SC_MC_PID_SETUP		3
+#define TSIZ_PKTCNT_MASK		(0x3ff << 19)
+#define TSIZ_PKTCNT_SHIFT		19
+#define TSIZ_NTD_MASK			(0xff << 8)
+#define TSIZ_NTD_SHIFT			8
+#define TSIZ_SCHINFO_MASK		(0xff << 0)
+#define TSIZ_SCHINFO_SHIFT		0
+#define TSIZ_XFERSIZE_MASK		(0x7ffff << 0)
+#define TSIZ_XFERSIZE_SHIFT		0
+
+#define HCDMA(_ch)			HSOTG_REG(0x0514 + 0x20 * (_ch))
+
+#define HCDMAB(_ch)			HSOTG_REG(0x051c + 0x20 * (_ch))
+
+#define HCFIFO(_ch)			HSOTG_REG(0x1000 + 0x1000 * (_ch))
+
+/**
+ * struct dwc2_dma_desc - DMA descriptor structure,
+ * used for both host and gadget modes
+ *
+ * @status: DMA descriptor status quadlet
+ * @buf:    DMA descriptor data buffer pointer
+ *
+ * DMA Descriptor structure contains two quadlets:
+ * Status quadlet and Data buffer pointer.
+ */
+struct dwc2_dma_desc {
+	uint32_t status;
+	uint32_t buf;
+} __packed;
+
+/* Host Mode DMA descriptor status quadlet */
+
+#define HOST_DMA_A			BIT(31)
+#define HOST_DMA_STS_MASK		(0x3 << 28)
+#define HOST_DMA_STS_SHIFT		28
+#define HOST_DMA_STS_PKTERR		BIT(28)
+#define HOST_DMA_EOL			BIT(26)
+#define HOST_DMA_IOC			BIT(25)
+#define HOST_DMA_SUP			BIT(24)
+#define HOST_DMA_ALT_QTD		BIT(23)
+#define HOST_DMA_QTD_OFFSET_MASK	(0x3f << 17)
+#define HOST_DMA_QTD_OFFSET_SHIFT	17
+#define HOST_DMA_ISOC_NBYTES_MASK	(0xfff << 0)
+#define HOST_DMA_ISOC_NBYTES_SHIFT	0
+#define HOST_DMA_NBYTES_MASK		(0x1ffff << 0)
+#define HOST_DMA_NBYTES_SHIFT		0
+#define HOST_DMA_NBYTES_LIMIT		131071
+
+/* Device Mode DMA descriptor status quadlet */
+
+#define DEV_DMA_BUFF_STS_MASK		(0x3 << 30)
+#define DEV_DMA_BUFF_STS_SHIFT		30
+#define DEV_DMA_BUFF_STS_HREADY		0
+#define DEV_DMA_BUFF_STS_DMABUSY	1
+#define DEV_DMA_BUFF_STS_DMADONE	2
+#define DEV_DMA_BUFF_STS_HBUSY		3
+#define DEV_DMA_STS_MASK		(0x3 << 28)
+#define DEV_DMA_STS_SHIFT		28
+#define DEV_DMA_STS_SUCC		0
+#define DEV_DMA_STS_BUFF_FLUSH		1
+#define DEV_DMA_STS_BUFF_ERR		3
+#define DEV_DMA_L			BIT(27)
+#define DEV_DMA_SHORT			BIT(26)
+#define DEV_DMA_IOC			BIT(25)
+#define DEV_DMA_SR			BIT(24)
+#define DEV_DMA_MTRF			BIT(23)
+#define DEV_DMA_ISOC_PID_MASK		(0x3 << 23)
+#define DEV_DMA_ISOC_PID_SHIFT		23
+#define DEV_DMA_ISOC_PID_DATA0		0
+#define DEV_DMA_ISOC_PID_DATA2		1
+#define DEV_DMA_ISOC_PID_DATA1		2
+#define DEV_DMA_ISOC_PID_MDATA		3
+#define DEV_DMA_ISOC_FRNUM_MASK		(0x7ff << 12)
+#define DEV_DMA_ISOC_FRNUM_SHIFT	12
+#define DEV_DMA_ISOC_TX_NBYTES_MASK	(0xfff << 0)
+#define DEV_DMA_ISOC_TX_NBYTES_LIMIT	0xfff
+#define DEV_DMA_ISOC_RX_NBYTES_MASK	(0x7ff << 0)
+#define DEV_DMA_ISOC_RX_NBYTES_LIMIT	0x7ff
+#define DEV_DMA_ISOC_NBYTES_SHIFT	0
+#define DEV_DMA_NBYTES_MASK		(0xffff << 0)
+#define DEV_DMA_NBYTES_SHIFT		0
+#define DEV_DMA_NBYTES_LIMIT		0xffff
+
+#define MAX_DMA_DESC_NUM_GENERIC	64
+#define MAX_DMA_DESC_NUM_HS_ISOC	256
+
+#endif /* __DWC2_HW_H__ */
-- 
2.20.1

From: Paul Zimmerman <pauldzim@gmail.com>

Add the dwc-hsotg (dwc2) USB host controller state definitions.
Mostly based on hw/usb/hcd-ehci.h.

Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Message-id: 20200520235349.21215-4-pauldzim@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/usb/hcd-dwc2.h | 190 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 190 insertions(+)
 create mode 100644 hw/usb/hcd-dwc2.h

diff --git a/hw/usb/hcd-dwc2.h b/hw/usb/hcd-dwc2.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/usb/hcd-dwc2.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * dwc-hsotg (dwc2) USB host controller state definitions
+ *
+ * Based on hw/usb/hcd-ehci.h
+ *
+ * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef HW_USB_DWC2_H
+#define HW_USB_DWC2_H
+
+#include "qemu/timer.h"
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "hw/usb.h"
+#include "sysemu/dma.h"
+
+#define DWC2_MMIO_SIZE      0x11000
+
+#define DWC2_NB_CHAN        8       /* Number of host channels */
+#define DWC2_MAX_XFER_SIZE  65536   /* Max transfer size expected in HCTSIZ */
+
+typedef struct DWC2Packet DWC2Packet;
+typedef struct DWC2State DWC2State;
+typedef struct DWC2Class DWC2Class;
+
+enum async_state {
+    DWC2_ASYNC_NONE = 0,
+    DWC2_ASYNC_INITIALIZED,
+    DWC2_ASYNC_INFLIGHT,
+    DWC2_ASYNC_FINISHED,
+};
+
+struct DWC2Packet {
+    USBPacket packet;
+    uint32_t devadr;
+    uint32_t epnum;
+    uint32_t epdir;
+    uint32_t mps;
+    uint32_t pid;
+    uint32_t index;
+    uint32_t pcnt;
+    uint32_t len;
+    int32_t async;
+    bool small;
+    bool needs_service;
+};
+
+struct DWC2State {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
+    USBBus bus;
+    qemu_irq irq;
+    MemoryRegion *dma_mr;
+    AddressSpace dma_as;
+    MemoryRegion container;
+    MemoryRegion hsotg;
+    MemoryRegion fifos;
+
+    union {
+#define DWC2_GLBREG_SIZE    0x70
+        uint32_t glbreg[DWC2_GLBREG_SIZE / sizeof(uint32_t)];
+        struct {
+            uint32_t gotgctl;       /* 00 */
+            uint32_t gotgint;       /* 04 */
+            uint32_t gahbcfg;       /* 08 */
+            uint32_t gusbcfg;       /* 0c */
+            uint32_t grstctl;       /* 10 */
+            uint32_t gintsts;       /* 14 */
+            uint32_t gintmsk;       /* 18 */
+            uint32_t grxstsr;       /* 1c */
+            uint32_t grxstsp;       /* 20 */
+            uint32_t grxfsiz;       /* 24 */
+            uint32_t gnptxfsiz;     /* 28 */
+            uint32_t gnptxsts;      /* 2c */
+            uint32_t gi2cctl;       /* 30 */
+            uint32_t gpvndctl;      /* 34 */
+            uint32_t ggpio;         /* 38 */
+            uint32_t guid;          /* 3c */
+            uint32_t gsnpsid;       /* 40 */
+            uint32_t ghwcfg1;       /* 44 */
+            uint32_t ghwcfg2;       /* 48 */
+            uint32_t ghwcfg3;       /* 4c */
+            uint32_t ghwcfg4;       /* 50 */
+            uint32_t glpmcfg;       /* 54 */
+            uint32_t gpwrdn;        /* 58 */
+            uint32_t gdfifocfg;     /* 5c */
+            uint32_t gadpctl;       /* 60 */
+            uint32_t grefclk;       /* 64 */
+            uint32_t gintmsk2;      /* 68 */
+            uint32_t gintsts2;      /* 6c */
+        };
+    };
+
+    union {
+#define DWC2_FSZREG_SIZE    0x04
+        uint32_t fszreg[DWC2_FSZREG_SIZE / sizeof(uint32_t)];
+        struct {
+            uint32_t hptxfsiz;      /* 100 */
+        };
+    };
+
+    union {
+#define DWC2_HREG0_SIZE     0x44
+        uint32_t hreg0[DWC2_HREG0_SIZE / sizeof(uint32_t)];
+        struct {
+            uint32_t hcfg;          /* 400 */
+            uint32_t hfir;          /* 404 */
+            uint32_t hfnum;         /* 408 */
+            uint32_t rsvd0;         /* 40c */
+            uint32_t hptxsts;       /* 410 */
+            uint32_t haint;         /* 414 */
+            uint32_t haintmsk;      /* 418 */
+            uint32_t hflbaddr;      /* 41c */
+            uint32_t rsvd1[8];      /* 420-43c */
+            uint32_t hprt0;         /* 440 */
+        };
+    };
+
+#define DWC2_HREG1_SIZE     (0x20 * DWC2_NB_CHAN)
+    uint32_t hreg1[DWC2_HREG1_SIZE / sizeof(uint32_t)];
+
+#define hcchar(_ch)     hreg1[((_ch) << 3) + 0] /* 500, 520, ... */
+#define hcsplt(_ch)     hreg1[((_ch) << 3) + 1] /* 504, 524, ... */
+#define hcint(_ch)      hreg1[((_ch) << 3) + 2] /* 508, 528, ... */
+#define hcintmsk(_ch)   hreg1[((_ch) << 3) + 3] /* 50c, 52c, ... */
+#define hctsiz(_ch)     hreg1[((_ch) << 3) + 4] /* 510, 530, ... */
+#define hcdma(_ch)      hreg1[((_ch) << 3) + 5] /* 514, 534, ... */
+#define hcdmab(_ch)     hreg1[((_ch) << 3) + 7] /* 51c, 53c, ... */
+
+    union {
+#define DWC2_PCGREG_SIZE    0x08
+        uint32_t pcgreg[DWC2_PCGREG_SIZE / sizeof(uint32_t)];
+        struct {
+            uint32_t pcgctl;        /* e00 */
+            uint32_t pcgcctl1;      /* e04 */
+        };
+    };
+
+    /* TODO - implement FIFO registers for slave mode */
+#define DWC2_HFIFO_SIZE     (0x1000 * DWC2_NB_CHAN)
+
+    /*
+     *  Internal state
+     */
+    QEMUTimer *eof_timer;
+    QEMUTimer *frame_timer;
+    QEMUBH *async_bh;
+    int64_t sof_time;
+    int64_t usb_frame_time;
+    int64_t usb_bit_time;
+    uint32_t usb_version;
+    uint16_t frame_number;
+    uint16_t fi;
+    uint16_t next_chan;
+    bool working;
+    USBPort uport;
+    DWC2Packet packet[DWC2_NB_CHAN];                   /* one packet per chan */
+    uint8_t usb_buf[DWC2_NB_CHAN][DWC2_MAX_XFER_SIZE]; /* one buffer per chan */
+};
+
+struct DWC2Class {
+    /*< private >*/
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+
+    /*< public >*/
+};
+
+#define TYPE_DWC2_USB   "dwc2-usb"
+#define DWC2_USB(obj) \
+    OBJECT_CHECK(DWC2State, (obj), TYPE_DWC2_USB)
+#define DWC2_CLASS(klass) \
+    OBJECT_CLASS_CHECK(DWC2Class, (klass), TYPE_DWC2_USB)
+#define DWC2_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(DWC2Class, (obj), TYPE_DWC2_USB)
+
+#endif
-- 
2.20.1

From: Paul Zimmerman <pauldzim@gmail.com>

Add the dwc-hsotg (dwc2) USB host controller emulation code.
Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c.

Note that to use this with the dwc-otg driver in the Raspbian
kernel, you must pass the option "dwc_otg.fiq_fsm_enable=0" on
the kernel command line.

Emulation of slave mode and of descriptor-DMA mode has not been
implemented yet. These modes are seldom used.

I have used some on-line sources of information while developing
this emulation, including:

http://www.capital-micro.com/PDF/CME-M7_Family_User_Guide_EN.pdf
which has a pretty complete description of the controller starting
on page 370.

https://sourceforge.net/p/wive-ng/wive-ng-mt/ci/master/tree/docs/DataSheets/RT3050_5x_V2.0_081408_0902.pdf
which has a description of the controller registers starting on
page 130.

Thanks to Felippe Mathieu-Daude for providing a cleaner method
of implementing the memory regions for the controller registers.

Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Message-id: 20200520235349.21215-5-pauldzim@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/usb/hcd-dwc2.c    | 1417 ++++++++++++++++++++++++++++++++++++++++++
 hw/usb/Kconfig       |    5 +
 hw/usb/Makefile.objs |    1 +
 hw/usb/trace-events  |   50 ++
 4 files changed, 1473 insertions(+)
 create mode 100644 hw/usb/hcd-dwc2.c

diff --git a/hw/usb/hcd-dwc2.c b/hw/usb/hcd-dwc2.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/usb/hcd-dwc2.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * dwc-hsotg (dwc2) USB host controller emulation
+ *
+ * Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c
+ *
+ * Note that to use this emulation with the dwc-otg driver in the
+ * Raspbian kernel, you must pass the option "dwc_otg.fiq_fsm_enable=0"
+ * on the kernel command line.
+ *
+ * Some useful documentation used to develop this emulation can be
+ * found online (as of April 2020) at:
+ *
+ * http://www.capital-micro.com/PDF/CME-M7_Family_User_Guide_EN.pdf
+ * which has a pretty complete description of the controller starting
+ * on page 370.
+ *
+ * https://sourceforge.net/p/wive-ng/wive-ng-mt/ci/master/tree/docs/DataSheets/RT3050_5x_V2.0_081408_0902.pdf
+ * which has a description of the controller registers starting on
+ * page 130.
+ *
+ * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qapi/error.h"
+#include "hw/usb/dwc2-regs.h"
+#include "hw/usb/hcd-dwc2.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
+#include "hw/qdev-properties.h"
+
+#define USB_HZ_FS       12000000
+#define USB_HZ_HS       96000000
+#define USB_FRMINTVL    12000
+
+/* nifty macros from Arnon's EHCI version  */
+#define get_field(data, field) \
+    (((data) & field##_MASK) >> field##_SHIFT)
+
+#define set_field(data, newval, field) do { \
+    uint32_t val = *(data); \
+    val &= ~field##_MASK; \
+    val |= ((newval) << field##_SHIFT) & field##_MASK; \
+    *(data) = val; \
+} while (0)
+
+#define get_bit(data, bitmask) \
+    (!!((data) & (bitmask)))
+
+/* update irq line */
+static inline void dwc2_update_irq(DWC2State *s)
+{
+    static int oldlevel;
+    int level = 0;
+
+    if ((s->gintsts & s->gintmsk) && (s->gahbcfg & GAHBCFG_GLBL_INTR_EN)) {
+        level = 1;
+    }
+    if (level != oldlevel) {
+        oldlevel = level;
+        trace_usb_dwc2_update_irq(level);
+        qemu_set_irq(s->irq, level);
+    }
+}
+
+/* flag interrupt condition */
+static inline void dwc2_raise_global_irq(DWC2State *s, uint32_t intr)
+{
+    if (!(s->gintsts & intr)) {
+        s->gintsts |= intr;
+        trace_usb_dwc2_raise_global_irq(intr);
+        dwc2_update_irq(s);
+    }
+}
+
+static inline void dwc2_lower_global_irq(DWC2State *s, uint32_t intr)
+{
+    if (s->gintsts & intr) {
+        s->gintsts &= ~intr;
+        trace_usb_dwc2_lower_global_irq(intr);
+        dwc2_update_irq(s);
+    }
+}
+
+static inline void dwc2_raise_host_irq(DWC2State *s, uint32_t host_intr)
+{
+    if (!(s->haint & host_intr)) {
+        s->haint |= host_intr;
+        s->haint &= 0xffff;
+        trace_usb_dwc2_raise_host_irq(host_intr);
+        if (s->haint & s->haintmsk) {
+            dwc2_raise_global_irq(s, GINTSTS_HCHINT);
+        }
+    }
+}
+
+static inline void dwc2_lower_host_irq(DWC2State *s, uint32_t host_intr)
+{
+    if (s->haint & host_intr) {
+        s->haint &= ~host_intr;
+        trace_usb_dwc2_lower_host_irq(host_intr);
+        if (!(s->haint & s->haintmsk)) {
+            dwc2_lower_global_irq(s, GINTSTS_HCHINT);
+        }
+    }
+}
+
+static inline void dwc2_update_hc_irq(DWC2State *s, int index)
+{
+    uint32_t host_intr = 1 << (index >> 3);
+
+    if (s->hreg1[index + 2] & s->hreg1[index + 3]) {
+        dwc2_raise_host_irq(s, host_intr);
+    } else {
+        dwc2_lower_host_irq(s, host_intr);
+    }
+}
+
+/* set a timer for EOF */
+static void dwc2_eof_timer(DWC2State *s)
+{
+    timer_mod(s->eof_timer, s->sof_time + s->usb_frame_time);
+}
+
+/* Set a timer for EOF and generate SOF event */
+static void dwc2_sof(DWC2State *s)
+{
+    s->sof_time += s->usb_frame_time;
+    trace_usb_dwc2_sof(s->sof_time);
+    dwc2_eof_timer(s);
+    dwc2_raise_global_irq(s, GINTSTS_SOF);
+}
+
+/* Do frame processing on frame boundary */
+static void dwc2_frame_boundary(void *opaque)
+{
+    DWC2State *s = opaque;
+    int64_t now;
+    uint16_t frcnt;
+
+    now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+
+    /* Frame boundary, so do EOF stuff here */
+
+    /* Increment frame number */
+    frcnt = (uint16_t)((now - s->sof_time) / s->fi);
+    s->frame_number = (s->frame_number + frcnt) & 0xffff;
+    s->hfnum = s->frame_number & HFNUM_MAX_FRNUM;
+
+    /* Do SOF stuff here */
+    dwc2_sof(s);
+}
+
+/* Start sending SOF tokens on the USB bus */
+static void dwc2_bus_start(DWC2State *s)
+{
+    trace_usb_dwc2_bus_start();
+    s->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+    dwc2_eof_timer(s);
+}
+
+/* Stop sending SOF tokens on the USB bus */
+static void dwc2_bus_stop(DWC2State *s)
+{
+    trace_usb_dwc2_bus_stop();
+    timer_del(s->eof_timer);
+}
+
+static USBDevice *dwc2_find_device(DWC2State *s, uint8_t addr)
+{
+    USBDevice *dev;
+
+    trace_usb_dwc2_find_device(addr);
+
+    if (!(s->hprt0 & HPRT0_ENA)) {
+        trace_usb_dwc2_port_disabled(0);
+    } else {
+        dev = usb_find_device(&s->uport, addr);
+        if (dev != NULL) {
+            trace_usb_dwc2_device_found(0);
+            return dev;
+        }
+    }
+
+    trace_usb_dwc2_device_not_found();
+    return NULL;
+}
+
+static const char *pstatus[] = {
+    "USB_RET_SUCCESS", "USB_RET_NODEV", "USB_RET_NAK", "USB_RET_STALL",
+    "USB_RET_BABBLE", "USB_RET_IOERROR", "USB_RET_ASYNC",
+    "USB_RET_ADD_TO_QUEUE", "USB_RET_REMOVE_FROM_QUEUE"
+};
+
+static uint32_t pintr[] = {
+    HCINTMSK_XFERCOMPL, HCINTMSK_XACTERR, HCINTMSK_NAK, HCINTMSK_STALL,
+    HCINTMSK_BBLERR, HCINTMSK_XACTERR, HCINTMSK_XACTERR, HCINTMSK_XACTERR,
+    HCINTMSK_XACTERR
+};
+
+static const char *types[] = {
+    "Ctrl", "Isoc", "Bulk", "Intr"
+};
+
+static const char *dirs[] = {
+    "Out", "In"
+};
+
+static void dwc2_handle_packet(DWC2State *s, uint32_t devadr, USBDevice *dev,
+                               USBEndpoint *ep, uint32_t index, bool send)
+{
+    DWC2Packet *p;
+    uint32_t hcchar = s->hreg1[index];
+    uint32_t hctsiz = s->hreg1[index + 4];
+    uint32_t hcdma = s->hreg1[index + 5];
+    uint32_t chan, epnum, epdir, eptype, mps, pid, pcnt, len, tlen, intr = 0;
+    uint32_t tpcnt, stsidx, actual = 0;
+    bool do_intr = false, done = false;
+
+    epnum = get_field(hcchar, HCCHAR_EPNUM);
+    epdir = get_bit(hcchar, HCCHAR_EPDIR);
+    eptype = get_field(hcchar, HCCHAR_EPTYPE);
+    mps = get_field(hcchar, HCCHAR_MPS);
+    pid = get_field(hctsiz, TSIZ_SC_MC_PID);
+    pcnt = get_field(hctsiz, TSIZ_PKTCNT);
+    len = get_field(hctsiz, TSIZ_XFERSIZE);
+    assert(len <= DWC2_MAX_XFER_SIZE);
+    chan = index >> 3;
+    p = &s->packet[chan];
+
+    trace_usb_dwc2_handle_packet(chan, dev, &p->packet, epnum, types[eptype],
+                                 dirs[epdir], mps, len, pcnt);
+
+    if (eptype == USB_ENDPOINT_XFER_CONTROL && pid == TSIZ_SC_MC_PID_SETUP) {
+        pid = USB_TOKEN_SETUP;
+    } else {
+        pid = epdir ? USB_TOKEN_IN : USB_TOKEN_OUT;
+    }
+
+    if (send) {
+        tlen = len;
+        if (p->small) {
+            if (tlen > mps) {
+                tlen = mps;
+            }
+        }
+
+        if (pid != USB_TOKEN_IN) {
+            trace_usb_dwc2_memory_read(hcdma, tlen);
+            if (dma_memory_read(&s->dma_as, hcdma,
+                                s->usb_buf[chan], tlen) != MEMTX_OK) {
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: dma_memory_read failed\n",
+                              __func__);
+            }
+        }
+
+        usb_packet_init(&p->packet);
+        usb_packet_setup(&p->packet, pid, ep, 0, hcdma,
+                         pid != USB_TOKEN_IN, true);
+        usb_packet_addbuf(&p->packet, s->usb_buf[chan], tlen);
+        p->async = DWC2_ASYNC_NONE;
+        usb_handle_packet(dev, &p->packet);
+    } else {
+        tlen = p->len;
+    }
+
+    stsidx = -p->packet.status;
+    assert(stsidx < sizeof(pstatus) / sizeof(*pstatus));
+    actual = p->packet.actual_length;
+    trace_usb_dwc2_packet_status(pstatus[stsidx], actual);
+
+babble:
+    if (p->packet.status != USB_RET_SUCCESS &&
+            p->packet.status != USB_RET_NAK &&
+            p->packet.status != USB_RET_STALL &&
+            p->packet.status != USB_RET_ASYNC) {
+        trace_usb_dwc2_packet_error(pstatus[stsidx]);
+    }
+
+    if (p->packet.status == USB_RET_ASYNC) {
+        trace_usb_dwc2_async_packet(&p->packet, chan, dev, epnum,
+                                    dirs[epdir], tlen);
+        usb_device_flush_ep_queue(dev, ep);
+        assert(p->async != DWC2_ASYNC_INFLIGHT);
+        p->devadr = devadr;
+        p->epnum = epnum;
+        p->epdir = epdir;
+        p->mps = mps;
+        p->pid = pid;
+        p->index = index;
+        p->pcnt = pcnt;
+        p->len = tlen;
+        p->async = DWC2_ASYNC_INFLIGHT;
+        p->needs_service = false;
+        return;
+    }
+
+    if (p->packet.status == USB_RET_SUCCESS) {
+        if (actual > tlen) {
+            p->packet.status = USB_RET_BABBLE;
+            goto babble;
+        }
+
+        if (pid == USB_TOKEN_IN) {
+            trace_usb_dwc2_memory_write(hcdma, actual);
+            if (dma_memory_write(&s->dma_as, hcdma, s->usb_buf[chan],
+                                 actual) != MEMTX_OK) {
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: dma_memory_write failed\n",
+                              __func__);
+            }
+        }
+
+        tpcnt = actual / mps;
+        if (actual % mps) {
+            tpcnt++;
+            if (pid == USB_TOKEN_IN) {
+                done = true;
+            }
+        }
+
+        pcnt -= tpcnt < pcnt ? tpcnt : pcnt;
+        set_field(&hctsiz, pcnt, TSIZ_PKTCNT);
+        len -= actual < len ? actual : len;
+        set_field(&hctsiz, len, TSIZ_XFERSIZE);
+        s->hreg1[index + 4] = hctsiz;
+        hcdma += actual;
+        s->hreg1[index + 5] = hcdma;
+
+        if (!pcnt || len == 0 || actual == 0) {
+            done = true;
+        }
+    } else {
+        intr |= pintr[stsidx];
+        if (p->packet.status == USB_RET_NAK &&
+            (eptype == USB_ENDPOINT_XFER_CONTROL ||
+             eptype == USB_ENDPOINT_XFER_BULK)) {
+            /*
+             * for ctrl/bulk, automatically retry on NAK,
+             * but send the interrupt anyway
+             */
+            intr &= ~HCINTMSK_RESERVED14_31;
+            s->hreg1[index + 2] |= intr;
+            do_intr = true;
+        } else {
+            intr |= HCINTMSK_CHHLTD;
+            done = true;
+        }
+    }
+
+    usb_packet_cleanup(&p->packet);
+
+    if (done) {
+        hcchar &= ~HCCHAR_CHENA;
+        s->hreg1[index] = hcchar;
+        if (!(intr & HCINTMSK_CHHLTD)) {
+            intr |= HCINTMSK_CHHLTD | HCINTMSK_XFERCOMPL;
+        }
+        intr &= ~HCINTMSK_RESERVED14_31;
+        s->hreg1[index + 2] |= intr;
+        p->needs_service = false;
+        trace_usb_dwc2_packet_done(pstatus[stsidx], actual, len, pcnt);
+        dwc2_update_hc_irq(s, index);
+        return;
+    }
+
+    p->devadr = devadr;
+    p->epnum = epnum;
+    p->epdir = epdir;
+    p->mps = mps;
+    p->pid = pid;
+    p->index = index;
+    p->pcnt = pcnt;
+    p->len = len;
+    p->needs_service = true;
+    trace_usb_dwc2_packet_next(pstatus[stsidx], len, pcnt);
+    if (do_intr) {
+        dwc2_update_hc_irq(s, index);
+    }
+}
+
+/* Attach or detach a device on root hub */
+
+static const char *speeds[] = {
+    "low", "full", "high"
+};
+
+static void dwc2_attach(USBPort *port)
+{
+    DWC2State *s = port->opaque;
+    int hispd = 0;
+
+    trace_usb_dwc2_attach(port);
+    assert(port->index == 0);
+
+    if (!port->dev || !port->dev->attached) {
+        return;
+    }
+
+    assert(port->dev->speed <= USB_SPEED_HIGH);
+    trace_usb_dwc2_attach_speed(speeds[port->dev->speed]);
+    s->hprt0 &= ~HPRT0_SPD_MASK;
+
+    switch (port->dev->speed) {
+    case USB_SPEED_LOW:
+        s->hprt0 |= HPRT0_SPD_LOW_SPEED << HPRT0_SPD_SHIFT;
+        break;
+    case USB_SPEED_FULL:
+        s->hprt0 |= HPRT0_SPD_FULL_SPEED << HPRT0_SPD_SHIFT;
+        break;
+    case USB_SPEED_HIGH:
+        s->hprt0 |= HPRT0_SPD_HIGH_SPEED << HPRT0_SPD_SHIFT;
+        hispd = 1;
+        break;
+    }
+
+    if (hispd) {
+        s->usb_frame_time = NANOSECONDS_PER_SECOND / 8000;        /* 125000 */
+        if (NANOSECONDS_PER_SECOND >= USB_HZ_HS) {
+            s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_HS; /* 10.4 */
+        } else {
+            s->usb_bit_time = 1;
+        }
+    } else {
+        s->usb_frame_time = NANOSECONDS_PER_SECOND / 1000;        /* 1000000 */
+        if (NANOSECONDS_PER_SECOND >= USB_HZ_FS) {
+            s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_FS; /* 83.3 */
+        } else {
+            s->usb_bit_time = 1;
+        }
+    }
+
+    s->fi = USB_FRMINTVL - 1;
+    s->hprt0 |= HPRT0_CONNDET | HPRT0_CONNSTS;
+
+    dwc2_bus_start(s);
+    dwc2_raise_global_irq(s, GINTSTS_PRTINT);
+}
+
+static void dwc2_detach(USBPort *port)
+{
+    DWC2State *s = port->opaque;
+
+    trace_usb_dwc2_detach(port);
+    assert(port->index == 0);
+
+    dwc2_bus_stop(s);
+
+    s->hprt0 &= ~(HPRT0_SPD_MASK | HPRT0_SUSP | HPRT0_ENA | HPRT0_CONNSTS);
+    s->hprt0 |= HPRT0_CONNDET | HPRT0_ENACHG;
+
+    dwc2_raise_global_irq(s, GINTSTS_PRTINT);
+}
+
+static void dwc2_child_detach(USBPort *port, USBDevice *child)
+{
+    trace_usb_dwc2_child_detach(port, child);
+    assert(port->index == 0);
+}
+
+static void dwc2_wakeup(USBPort *port)
+{
+    DWC2State *s = port->opaque;
+
+    trace_usb_dwc2_wakeup(port);
+    assert(port->index == 0);
+
+    if (s->hprt0 & HPRT0_SUSP) {
+        s->hprt0 |= HPRT0_RES;
+        dwc2_raise_global_irq(s, GINTSTS_PRTINT);
+    }
+
+    qemu_bh_schedule(s->async_bh);
+}
+
+static void dwc2_async_packet_complete(USBPort *port, USBPacket *packet)
+{
+    DWC2State *s = port->opaque;
+    DWC2Packet *p;
+    USBDevice *dev;
+    USBEndpoint *ep;
+
+    assert(port->index == 0);
+    p = container_of(packet, DWC2Packet, packet);
+    dev = dwc2_find_device(s, p->devadr);
+    ep = usb_ep_get(dev, p->pid, p->epnum);
+    trace_usb_dwc2_async_packet_complete(port, packet, p->index >> 3, dev,
+                                         p->epnum, dirs[p->epdir], p->len);
+    assert(p->async == DWC2_ASYNC_INFLIGHT);
+
+    if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
+        usb_cancel_packet(packet);
+        usb_packet_cleanup(packet);
+        return;
+    }
+
+    dwc2_handle_packet(s, p->devadr, dev, ep, p->index, false);
+
+    p->async = DWC2_ASYNC_FINISHED;
+    qemu_bh_schedule(s->async_bh);
+}
+
+static USBPortOps dwc2_port_ops = {
+    .attach = dwc2_attach,
+    .detach = dwc2_detach,
+    .child_detach = dwc2_child_detach,
+    .wakeup = dwc2_wakeup,
+    .complete = dwc2_async_packet_complete,
+};
+
+static uint32_t dwc2_get_frame_remaining(DWC2State *s)
+{
+    uint32_t fr = 0;
+    int64_t tks;
+
+    tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->sof_time;
+    if (tks < 0) {
+        tks = 0;
+    }
+
+    /* avoid muldiv if possible */
+    if (tks >= s->usb_frame_time) {
+        goto out;
+    }
+    if (tks < s->usb_bit_time) {
+        fr = s->fi;
+        goto out;
+    }
+
+    /* tks = number of ns since SOF, divided by 83 (fs) or 10 (hs) */
+    tks = tks / s->usb_bit_time;
+    if (tks >= (int64_t)s->fi) {
+        goto out;
+    }
+
+    /* remaining = frame interval minus tks */
+    fr = (uint32_t)((int64_t)s->fi - tks);
+
+out:
+    return fr;
+}
+
+static void dwc2_work_bh(void *opaque)
+{
+    DWC2State *s = opaque;
+    DWC2Packet *p;
+    USBDevice *dev;
+    USBEndpoint *ep;
+    int64_t t_now, expire_time;
+    int chan;
+    bool found = false;
+
+    trace_usb_dwc2_work_bh();
+    if (s->working) {
+        return;
+    }
+    s->working = true;
+
+    t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+    chan = s->next_chan;
+
+    do {
+        p = &s->packet[chan];
+        if (p->needs_service) {
+            dev = dwc2_find_device(s, p->devadr);
+            ep = usb_ep_get(dev, p->pid, p->epnum);
+            trace_usb_dwc2_work_bh_service(s->next_chan, chan, dev, p->epnum);
+            dwc2_handle_packet(s, p->devadr, dev, ep, p->index, true);
+            found = true;
+        }
+        if (++chan == DWC2_NB_CHAN) {
+            chan = 0;
+        }
+        if (found) {
+            s->next_chan = chan;
+            trace_usb_dwc2_work_bh_next(chan);
+        }
+    } while (chan != s->next_chan);
+
+    if (found) {
+        expire_time = t_now + NANOSECONDS_PER_SECOND / 4000;
+        timer_mod(s->frame_timer, expire_time);
+    }
+    s->working = false;
+}
+
+static void dwc2_enable_chan(DWC2State *s,  uint32_t index)
+{
+    USBDevice *dev;
+    USBEndpoint *ep;
+    uint32_t hcchar;
+    uint32_t hctsiz;
+    uint32_t devadr, epnum, epdir, eptype, pid, len;
+    DWC2Packet *p;
+
+    assert((index >> 3) < DWC2_NB_CHAN);
+    p = &s->packet[index >> 3];
+    hcchar = s->hreg1[index];
+    hctsiz = s->hreg1[index + 4];
+    devadr = get_field(hcchar, HCCHAR_DEVADDR);
+    epnum = get_field(hcchar, HCCHAR_EPNUM);
+    epdir = get_bit(hcchar, HCCHAR_EPDIR);
+    eptype = get_field(hcchar, HCCHAR_EPTYPE);
+    pid = get_field(hctsiz, TSIZ_SC_MC_PID);
+    len = get_field(hctsiz, TSIZ_XFERSIZE);
+
+    dev = dwc2_find_device(s, devadr);
+
+    trace_usb_dwc2_enable_chan(index >> 3, dev, &p->packet, epnum);
+    if (dev == NULL) {
+        return;
+    }
+
+    if (eptype == USB_ENDPOINT_XFER_CONTROL && pid == TSIZ_SC_MC_PID_SETUP) {
+        pid = USB_TOKEN_SETUP;
+    } else {
+        pid = epdir ? USB_TOKEN_IN : USB_TOKEN_OUT;
+    }
+
+    ep = usb_ep_get(dev, pid, epnum);
+
+    /*
+     * Hack: Networking doesn't like us delivering large transfers, it kind
+     * of works but the latency is horrible. So if the transfer is <= the mtu
+     * size, we take that as a hint that this might be a network transfer,
+     * and do the transfer packet-by-packet.
+     */
+    if (len > 1536) {
+        p->small = false;
+    } else {
+        p->small = true;
+    }
+
+    dwc2_handle_packet(s, devadr, dev, ep, index, true);
+    qemu_bh_schedule(s->async_bh);
+}
+
+static const char *glbregnm[] = {
+    "GOTGCTL  ", "GOTGINT  ", "GAHBCFG  ", "GUSBCFG  ", "GRSTCTL  ",
+    "GINTSTS  ", "GINTMSK  ", "GRXSTSR  ", "GRXSTSP  ", "GRXFSIZ  ",
+    "GNPTXFSIZ", "GNPTXSTS ", "GI2CCTL  ", "GPVNDCTL ", "GGPIO    ",
+    "GUID     ", "GSNPSID  ", "GHWCFG1  ", "GHWCFG2  ", "GHWCFG3  ",
+    "GHWCFG4  ", "GLPMCFG  ", "GPWRDN   ", "GDFIFOCFG", "GADPCTL  ",
+    "GREFCLK  ", "GINTMSK2 ", "GINTSTS2 "
+};
+
+static uint64_t dwc2_glbreg_read(void *ptr, hwaddr addr, int index,
+                                 unsigned size)
+{
+    DWC2State *s = ptr;
+    uint32_t val;
+
+    assert(addr <= GINTSTS2);
+    val = s->glbreg[index];
+
+    switch (addr) {
+    case GRSTCTL:
+        /* clear any self-clearing bits that were set */
+        val &= ~(GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH | GRSTCTL_IN_TKNQ_FLSH |
+                 GRSTCTL_FRMCNTRRST | GRSTCTL_HSFTRST | GRSTCTL_CSFTRST);
+        s->glbreg[index] = val;
+        break;
+    default:
+        break;
+    }
+
+    trace_usb_dwc2_glbreg_read(addr, glbregnm[index], val);
+    return val;
+}
+
+static void dwc2_glbreg_write(void *ptr, hwaddr addr, int index, uint64_t val,
+                              unsigned size)
+{
+    DWC2State *s = ptr;
+    uint64_t orig = val;
+    uint32_t *mmio;
+    uint32_t old;
+    int iflg = 0;
+
+    assert(addr <= GINTSTS2);
+    mmio = &s->glbreg[index];
+    old = *mmio;
+
+    switch (addr) {
+    case GOTGCTL:
+        /* don't allow setting of read-only bits */
+        val &= ~(GOTGCTL_MULT_VALID_BC_MASK | GOTGCTL_BSESVLD |
+                 GOTGCTL_ASESVLD | GOTGCTL_DBNC_SHORT | GOTGCTL_CONID_B |
+                 GOTGCTL_HSTNEGSCS | GOTGCTL_SESREQSCS);
+        /* don't allow clearing of read-only bits */
+        val |= old & (GOTGCTL_MULT_VALID_BC_MASK | GOTGCTL_BSESVLD |
+                      GOTGCTL_ASESVLD | GOTGCTL_DBNC_SHORT | GOTGCTL_CONID_B |
+                      GOTGCTL_HSTNEGSCS | GOTGCTL_SESREQSCS);
+        break;
+    case GAHBCFG:
+        if ((val & GAHBCFG_GLBL_INTR_EN) && !(old & GAHBCFG_GLBL_INTR_EN)) {
+            iflg = 1;
+        }
+        break;
+    case GRSTCTL:
+        val |= GRSTCTL_AHBIDLE;
+        val &= ~GRSTCTL_DMAREQ;
+        if (!(old & GRSTCTL_TXFFLSH) && (val & GRSTCTL_TXFFLSH)) {
+                /* TODO - TX fifo flush */
+            qemu_log_mask(LOG_UNIMP, "Tx FIFO flush not implemented\n");
+        }
+        if (!(old & GRSTCTL_RXFFLSH) && (val & GRSTCTL_RXFFLSH)) {
+                /* TODO - RX fifo flush */
+            qemu_log_mask(LOG_UNIMP, "Rx FIFO flush not implemented\n");
+        }
+        if (!(old & GRSTCTL_IN_TKNQ_FLSH) && (val & GRSTCTL_IN_TKNQ_FLSH)) {
+                /* TODO - device IN token queue flush */
+            qemu_log_mask(LOG_UNIMP, "Token queue flush not implemented\n");
+        }
+        if (!(old & GRSTCTL_FRMCNTRRST) && (val & GRSTCTL_FRMCNTRRST)) {
+                /* TODO - host frame counter reset */
+            qemu_log_mask(LOG_UNIMP, "Frame counter reset not implemented\n");
+        }
+        if (!(old & GRSTCTL_HSFTRST) && (val & GRSTCTL_HSFTRST)) {
+                /* TODO - host soft reset */
+            qemu_log_mask(LOG_UNIMP, "Host soft reset not implemented\n");
+        }
+        if (!(old & GRSTCTL_CSFTRST) && (val & GRSTCTL_CSFTRST)) {
+                /* TODO - core soft reset */
+            qemu_log_mask(LOG_UNIMP, "Core soft reset not implemented\n");
+        }
+        /* don't allow clearing of self-clearing bits */
+        val |= old & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH |
+                      GRSTCTL_IN_TKNQ_FLSH | GRSTCTL_FRMCNTRRST |
+                      GRSTCTL_HSFTRST | GRSTCTL_CSFTRST);
+        break;
+    case GINTSTS:
+        /* clear the write-1-to-clear bits */
+        val |= ~old;
+        val = ~val;
+        /* don't allow clearing of read-only bits */
+        val |= old & (GINTSTS_PTXFEMP | GINTSTS_HCHINT | GINTSTS_PRTINT |
+                      GINTSTS_OEPINT | GINTSTS_IEPINT | GINTSTS_GOUTNAKEFF |
+                      GINTSTS_GINNAKEFF | GINTSTS_NPTXFEMP | GINTSTS_RXFLVL |
+                      GINTSTS_OTGINT | GINTSTS_CURMODE_HOST);
+        iflg = 1;
+        break;
+    case GINTMSK:
+        iflg = 1;
+        break;
+    default:
+        break;
+    }
+
+    trace_usb_dwc2_glbreg_write(addr, glbregnm[index], orig, old, val);
+    *mmio = val;
+
+    if (iflg) {
+        dwc2_update_irq(s);
+    }
+}
+
+static uint64_t dwc2_fszreg_read(void *ptr, hwaddr addr, int index,
+                                 unsigned size)
+{
+    DWC2State *s = ptr;
+    uint32_t val;
+
+    assert(addr == HPTXFSIZ);
+    val = s->fszreg[index];
+
+    trace_usb_dwc2_fszreg_read(addr, val);
+    return val;
+}
+
+static void dwc2_fszreg_write(void *ptr, hwaddr addr, int index, uint64_t val,
+                              unsigned size)
+{
+    DWC2State *s = ptr;
+    uint64_t orig = val;
+    uint32_t *mmio;
+    uint32_t old;
+
+    assert(addr == HPTXFSIZ);
+    mmio = &s->fszreg[index];
+    old = *mmio;
+
+    trace_usb_dwc2_fszreg_write(addr, orig, old, val);
+    *mmio = val;
+}
+
+static const char *hreg0nm[] = {
+    "HCFG     ", "HFIR     ", "HFNUM    ", "<rsvd>   ", "HPTXSTS  ",
+    "HAINT    ", "HAINTMSK ", "HFLBADDR ", "<rsvd>   ", "<rsvd>   ",
+    "<rsvd>   ", "<rsvd>   ", "<rsvd>   ", "<rsvd>   ", "<rsvd>   ",
+    "<rsvd>   ", "HPRT0    "
+};
+
+static uint64_t dwc2_hreg0_read(void *ptr, hwaddr addr, int index,
+                                unsigned size)
+{
+    DWC2State *s = ptr;
+    uint32_t val;
+
+    assert(addr >= HCFG && addr <= HPRT0);
+    val = s->hreg0[index];
+
+    switch (addr) {
+    case HFNUM:
+        val = (dwc2_get_frame_remaining(s) << HFNUM_FRREM_SHIFT) |
+              (s->hfnum << HFNUM_FRNUM_SHIFT);
+        break;
+    default:
+        break;
+    }
+
+    trace_usb_dwc2_hreg0_read(addr, hreg0nm[index], val);
+    return val;
+}
+
+static void dwc2_hreg0_write(void *ptr, hwaddr addr, int index, uint64_t val,
+                             unsigned size)
+{
+    DWC2State *s = ptr;
+    USBDevice *dev = s->uport.dev;
+    uint64_t orig = val;
+    uint32_t *mmio;
+    uint32_t tval, told, old;
+    int prst = 0;
+    int iflg = 0;
+
+    assert(addr >= HCFG && addr <= HPRT0);
+    mmio = &s->hreg0[index];
+    old = *mmio;
+
+    switch (addr) {
+    case HFIR:
+        break;
+    case HFNUM:
+    case HPTXSTS:
+    case HAINT:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: write to read-only register\n",
+                      __func__);
+        return;
+    case HAINTMSK:
+        val &= 0xffff;
+        break;
+    case HPRT0:
+        /* don't allow clearing of read-only bits */
+        val |= old & (HPRT0_SPD_MASK | HPRT0_LNSTS_MASK | HPRT0_OVRCURRACT |
+                      HPRT0_CONNSTS);
+        /* don't allow clearing of self-clearing bits */
+        val |= old & (HPRT0_SUSP | HPRT0_RES);
+        /* don't allow setting of self-setting bits */
+        if (!(old & HPRT0_ENA) && (val & HPRT0_ENA)) {
+            val &= ~HPRT0_ENA;
+        }
+        /* clear the write-1-to-clear bits */
+        tval = val & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
+                      HPRT0_CONNDET);
+        told = old & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
+                      HPRT0_CONNDET);
+        tval |= ~told;
+        tval = ~tval;
+        tval &= (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
+                 HPRT0_CONNDET);
+        val &= ~(HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
+                 HPRT0_CONNDET);
+        val |= tval;
+        if (!(val & HPRT0_RST) && (old & HPRT0_RST)) {
+            if (dev && dev->attached) {
+                val |= HPRT0_ENA | HPRT0_ENACHG;
+                prst = 1;
+            }
+        }
+        if (val & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_CONNDET)) {
+            iflg = 1;
+        } else {
+            iflg = -1;
+        }
+        break;
+    default:
+        break;
+    }
+
+    if (prst) {
+        trace_usb_dwc2_hreg0_write(addr, hreg0nm[index], orig, old,
+                                   val & ~HPRT0_CONNDET);
+        trace_usb_dwc2_hreg0_action("call usb_port_reset");
+        usb_port_reset(&s->uport);
+        val &= ~HPRT0_CONNDET;
+    } else {
+        trace_usb_dwc2_hreg0_write(addr, hreg0nm[index], orig, old, val);
+    }
+
+    *mmio = val;
+
+    if (iflg > 0) {
+        trace_usb_dwc2_hreg0_action("enable PRTINT");
+        dwc2_raise_global_irq(s, GINTSTS_PRTINT);
+    } else if (iflg < 0) {
+        trace_usb_dwc2_hreg0_action("disable PRTINT");
+        dwc2_lower_global_irq(s, GINTSTS_PRTINT);
+    }
+}
+
+static const char *hreg1nm[] = {
+    "HCCHAR  ", "HCSPLT  ", "HCINT   ", "HCINTMSK", "HCTSIZ  ", "HCDMA   ",
+    "<rsvd>  ", "HCDMAB  "
+};
+
+static uint64_t dwc2_hreg1_read(void *ptr, hwaddr addr, int index,
+                                unsigned size)
+{
+    DWC2State *s = ptr;
+    uint32_t val;
+
+    assert(addr >= HCCHAR(0) && addr <= HCDMAB(DWC2_NB_CHAN - 1));
+    val = s->hreg1[index];
+
+    trace_usb_dwc2_hreg1_read(addr, hreg1nm[index & 7], addr >> 5, val);
+    return val;
+}
+
+static void dwc2_hreg1_write(void *ptr, hwaddr addr, int index, uint64_t val,
+                             unsigned size)
+{
+    DWC2State *s = ptr;
+    uint64_t orig = val;
+    uint32_t *mmio;
+    uint32_t old;
+    int iflg = 0;
+    int enflg = 0;
+    int disflg = 0;
+
+    assert(addr >= HCCHAR(0) && addr <= HCDMAB(DWC2_NB_CHAN - 1));
+    mmio = &s->hreg1[index];
+    old = *mmio;
+
+    switch (HSOTG_REG(0x500) + (addr & 0x1c)) {
+    case HCCHAR(0):
+        if ((val & HCCHAR_CHDIS) && !(old & HCCHAR_CHDIS)) {
+            val &= ~(HCCHAR_CHENA | HCCHAR_CHDIS);
+            disflg = 1;
+        } else {
+            val |= old & HCCHAR_CHDIS;
+            if ((val & HCCHAR_CHENA) && !(old & HCCHAR_CHENA)) {
+                val &= ~HCCHAR_CHDIS;
+                enflg = 1;
+            } else {
+                val |= old & HCCHAR_CHENA;
+            }
+        }
+        break;
+    case HCINT(0):
+        /* clear the write-1-to-clear bits */
+        val |= ~old;
+        val = ~val;
+        val &= ~HCINTMSK_RESERVED14_31;
+        iflg = 1;
+        break;
+    case HCINTMSK(0):
+        val &= ~HCINTMSK_RESERVED14_31;
+        iflg = 1;
+        break;
+    case HCDMAB(0):
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: write to read-only register\n",
+                      __func__);
+        return;
+    default:
+        break;
+    }
+
+    trace_usb_dwc2_hreg1_write(addr, hreg1nm[index & 7], index >> 3, orig,
+                               old, val);
+    *mmio = val;
+
+    if (disflg) {
+        /* set ChHltd in HCINT */
+        s->hreg1[(index & ~7) + 2] |= HCINTMSK_CHHLTD;
+        iflg = 1;
+    }
+
+    if (enflg) {
+        dwc2_enable_chan(s, index & ~7);
+    }
+
+    if (iflg) {
+        dwc2_update_hc_irq(s, index & ~7);
+    }
+}
+
+static const char *pcgregnm[] = {
+        "PCGCTL   ", "PCGCCTL1 "
+};
+
+static uint64_t dwc2_pcgreg_read(void *ptr, hwaddr addr, int index,
+                                 unsigned size)
+{
+    DWC2State *s = ptr;
+    uint32_t val;
+
+    assert(addr >= PCGCTL && addr <= PCGCCTL1);
+    val = s->pcgreg[index];
+
+    trace_usb_dwc2_pcgreg_read(addr, pcgregnm[index], val);
+    return val;
+}
+
+static void dwc2_pcgreg_write(void *ptr, hwaddr addr, int index,
+                              uint64_t val, unsigned size)
+{
+    DWC2State *s = ptr;
+    uint64_t orig = val;
+    uint32_t *mmio;
+    uint32_t old;
+
+    assert(addr >= PCGCTL && addr <= PCGCCTL1);
+    mmio = &s->pcgreg[index];
+    old = *mmio;
+
+    trace_usb_dwc2_pcgreg_write(addr, pcgregnm[index], orig, old, val);
+    *mmio = val;
+}
+
+static uint64_t dwc2_hsotg_read(void *ptr, hwaddr addr, unsigned size)
+{
+    uint64_t val;
+
+    switch (addr) {
+    case HSOTG_REG(0x000) ... HSOTG_REG(0x0fc):
+        val = dwc2_glbreg_read(ptr, addr, (addr - HSOTG_REG(0x000)) >> 2, size);
+        break;
+    case HSOTG_REG(0x100):
+        val = dwc2_fszreg_read(ptr, addr, (addr - HSOTG_REG(0x100)) >> 2, size);
+        break;
+    case HSOTG_REG(0x104) ... HSOTG_REG(0x3fc):
+        /* Gadget-mode registers, just return 0 for now */
+        val = 0;
+        break;
+    case HSOTG_REG(0x400) ... HSOTG_REG(0x4fc):
+        val = dwc2_hreg0_read(ptr, addr, (addr - HSOTG_REG(0x400)) >> 2, size);
+        break;
+    case HSOTG_REG(0x500) ... HSOTG_REG(0x7fc):
+        val = dwc2_hreg1_read(ptr, addr, (addr - HSOTG_REG(0x500)) >> 2, size);
+        break;
+    case HSOTG_REG(0x800) ... HSOTG_REG(0xdfc):
+        /* Gadget-mode registers, just return 0 for now */
+        val = 0;
+        break;
+    case HSOTG_REG(0xe00) ... HSOTG_REG(0xffc):
+        val = dwc2_pcgreg_read(ptr, addr, (addr - HSOTG_REG(0xe00)) >> 2, size);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    return val;
+}
+
+static void dwc2_hsotg_write(void *ptr, hwaddr addr, uint64_t val,
+                             unsigned size)
+{
+    switch (addr) {
+    case HSOTG_REG(0x000) ... HSOTG_REG(0x0fc):
+        dwc2_glbreg_write(ptr, addr, (addr - HSOTG_REG(0x000)) >> 2, val, size);
+        break;
+    case HSOTG_REG(0x100):
+        dwc2_fszreg_write(ptr, addr, (addr - HSOTG_REG(0x100)) >> 2, val, size);
+        break;
+    case HSOTG_REG(0x104) ... HSOTG_REG(0x3fc):
+        /* Gadget-mode registers, do nothing for now */
+        break;
+    case HSOTG_REG(0x400) ... HSOTG_REG(0x4fc):
+        dwc2_hreg0_write(ptr, addr, (addr - HSOTG_REG(0x400)) >> 2, val, size);
+        break;
+    case HSOTG_REG(0x500) ... HSOTG_REG(0x7fc):
+        dwc2_hreg1_write(ptr, addr, (addr - HSOTG_REG(0x500)) >> 2, val, size);
+        break;
+    case HSOTG_REG(0x800) ... HSOTG_REG(0xdfc):
+        /* Gadget-mode registers, do nothing for now */
+        break;
+    case HSOTG_REG(0xe00) ... HSOTG_REG(0xffc):
+        dwc2_pcgreg_write(ptr, addr, (addr - HSOTG_REG(0xe00)) >> 2, val, size);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static const MemoryRegionOps dwc2_mmio_hsotg_ops = {
+    .read = dwc2_hsotg_read,
+    .write = dwc2_hsotg_write,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static uint64_t dwc2_hreg2_read(void *ptr, hwaddr addr, unsigned size)
+{
+    /* TODO - implement FIFOs to support slave mode */
+    trace_usb_dwc2_hreg2_read(addr, addr >> 12, 0);
+    qemu_log_mask(LOG_UNIMP, "FIFO read not implemented\n");
+    return 0;
+}
+
+static void dwc2_hreg2_write(void *ptr, hwaddr addr, uint64_t val,
+                             unsigned size)
+{
+    uint64_t orig = val;
+
+    /* TODO - implement FIFOs to support slave mode */
+    trace_usb_dwc2_hreg2_write(addr, addr >> 12, orig, 0, val);
+    qemu_log_mask(LOG_UNIMP, "FIFO write not implemented\n");
+}
+
+static const MemoryRegionOps dwc2_mmio_hreg2_ops = {
+    .read = dwc2_hreg2_read,
+    .write = dwc2_hreg2_write,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void dwc2_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
+                                 unsigned int stream)
+{
+    DWC2State *s = container_of(bus, DWC2State, bus);
+
+    trace_usb_dwc2_wakeup_endpoint(ep, stream);
+
+    /* TODO - do something here? */
+    qemu_bh_schedule(s->async_bh);
+}
+
+static USBBusOps dwc2_bus_ops = {
+    .wakeup_endpoint = dwc2_wakeup_endpoint,
+};
+
+static void dwc2_work_timer(void *opaque)
+{
+    DWC2State *s = opaque;
+
+    trace_usb_dwc2_work_timer();
+    qemu_bh_schedule(s->async_bh);
+}
+
+static void dwc2_reset_enter(Object *obj, ResetType type)
+{
+    DWC2Class *c = DWC2_GET_CLASS(obj);
+    DWC2State *s = DWC2_USB(obj);
+    int i;
+
+    trace_usb_dwc2_reset_enter();
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    timer_del(s->frame_timer);
+    qemu_bh_cancel(s->async_bh);
+
+    if (s->uport.dev && s->uport.dev->attached) {
+        usb_detach(&s->uport);
+    }
+
+    dwc2_bus_stop(s);
+
+    s->gotgctl = GOTGCTL_BSESVLD | GOTGCTL_ASESVLD | GOTGCTL_CONID_B;
+    s->gotgint = 0;
+    s->gahbcfg = 0;
+    s->gusbcfg = 5 << GUSBCFG_USBTRDTIM_SHIFT;
+    s->grstctl = GRSTCTL_AHBIDLE;
+    s->gintsts = GINTSTS_CONIDSTSCHNG | GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP |
+                 GINTSTS_CURMODE_HOST;
+    s->gintmsk = 0;
+    s->grxstsr = 0;
+    s->grxstsp = 0;
+    s->grxfsiz = 1024;
+    s->gnptxfsiz = 1024 << FIFOSIZE_DEPTH_SHIFT;
+    s->gnptxsts = (4 << FIFOSIZE_DEPTH_SHIFT) | 1024;
+    s->gi2cctl = GI2CCTL_I2CDATSE0 | GI2CCTL_ACK;
+    s->gpvndctl = 0;
+    s->ggpio = 0;
+    s->guid = 0;
+    s->gsnpsid = 0x4f54294a;
+    s->ghwcfg1 = 0;
+    s->ghwcfg2 = (8 << GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT) |
+                 (4 << GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT) |
+                 (4 << GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT) |
+                 GHWCFG2_DYNAMIC_FIFO |
+                 GHWCFG2_PERIO_EP_SUPPORTED |
+                 ((DWC2_NB_CHAN - 1) << GHWCFG2_NUM_HOST_CHAN_SHIFT) |
+                 (GHWCFG2_INT_DMA_ARCH << GHWCFG2_ARCHITECTURE_SHIFT) |
+                 (GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST << GHWCFG2_OP_MODE_SHIFT);
+    s->ghwcfg3 = (4096 << GHWCFG3_DFIFO_DEPTH_SHIFT) |
+                 (4 << GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT) |
+                 (4 << GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT);
+    s->ghwcfg4 = 0;
+    s->glpmcfg = 0;
+    s->gpwrdn = GPWRDN_PWRDNRSTN;
+    s->gdfifocfg = 0;
+    s->gadpctl = 0;
+    s->grefclk = 0;
+    s->gintmsk2 = 0;
+    s->gintsts2 = 0;
+
+    s->hptxfsiz = 500 << FIFOSIZE_DEPTH_SHIFT;
+
+    s->hcfg = 2 << HCFG_RESVALID_SHIFT;
+    s->hfir = 60000;
+    s->hfnum = 0x3fff;
+    s->hptxsts = (16 << TXSTS_QSPCAVAIL_SHIFT) | 32768;
+    s->haint = 0;
+    s->haintmsk = 0;
+    s->hprt0 = 0;
+
+    memset(s->hreg1, 0, sizeof(s->hreg1));
+    memset(s->pcgreg, 0, sizeof(s->pcgreg));
+
+    s->sof_time = 0;
+    s->frame_number = 0;
+    s->fi = USB_FRMINTVL - 1;
+    s->next_chan = 0;
+    s->working = false;
+
+    for (i = 0; i < DWC2_NB_CHAN; i++) {
+        s->packet[i].needs_service = false;
+    }
+}
+
+static void dwc2_reset_hold(Object *obj)
+{
+    DWC2Class *c = DWC2_GET_CLASS(obj);
+    DWC2State *s = DWC2_USB(obj);
+
+    trace_usb_dwc2_reset_hold();
+
+    if (c->parent_phases.hold) {
+        c->parent_phases.hold(obj);
+    }
+
+    dwc2_update_irq(s);
+}
+
+static void dwc2_reset_exit(Object *obj)
+{
+    DWC2Class *c = DWC2_GET_CLASS(obj);
+    DWC2State *s = DWC2_USB(obj);
+
+    trace_usb_dwc2_reset_exit();
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj);
+    }
+
+    s->hprt0 = HPRT0_PWR;
+    if (s->uport.dev && s->uport.dev->attached) {
+        usb_attach(&s->uport);
+        usb_device_reset(s->uport.dev);
+    }
+}
+
+static void dwc2_realize(DeviceState *dev, Error **errp)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+    DWC2State *s = DWC2_USB(dev);
+    Object *obj;
+    Error *err = NULL;
+
+    obj = object_property_get_link(OBJECT(dev), "dma-mr", &err);
+    if (err) {
+        error_setg(errp, "dwc2: required dma-mr link not found: %s",
+                   error_get_pretty(err));
+        return;
+    }
+    assert(obj != NULL);
+
+    s->dma_mr = MEMORY_REGION(obj);
+    address_space_init(&s->dma_as, s->dma_mr, "dwc2");
+
+    usb_bus_new(&s->bus, sizeof(s->bus), &dwc2_bus_ops, dev);
+    usb_register_port(&s->bus, &s->uport, s, 0, &dwc2_port_ops,
+                      USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL |
+                      (s->usb_version == 2 ? USB_SPEED_MASK_HIGH : 0));
+    s->uport.dev = 0;
+
+    s->usb_frame_time = NANOSECONDS_PER_SECOND / 1000;          /* 1000000 */
+    if (NANOSECONDS_PER_SECOND >= USB_HZ_FS) {
+        s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_FS;   /* 83.3 */
+    } else {
+        s->usb_bit_time = 1;
+    }
+
+    s->fi = USB_FRMINTVL - 1;
+    s->eof_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, dwc2_frame_boundary, s);
+    s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, dwc2_work_timer, s);
+    s->async_bh = qemu_bh_new(dwc2_work_bh, s);
+
+    sysbus_init_irq(sbd, &s->irq);
+}
+
+static void dwc2_init(Object *obj)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    DWC2State *s = DWC2_USB(obj);
+
+    memory_region_init(&s->container, obj, "dwc2", DWC2_MMIO_SIZE);
+    sysbus_init_mmio(sbd, &s->container);
+
+    memory_region_init_io(&s->hsotg, obj, &dwc2_mmio_hsotg_ops, s,
+                          "dwc2-io", 4 * KiB);
+    memory_region_add_subregion(&s->container, 0x0000, &s->hsotg);
+
+    memory_region_init_io(&s->fifos, obj, &dwc2_mmio_hreg2_ops, s,
+                          "dwc2-fifo", 64 * KiB);
+    memory_region_add_subregion(&s->container, 0x1000, &s->fifos);
+}
+
+static const VMStateDescription vmstate_dwc2_state_packet = {
+    .name = "dwc2/packet",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(devadr, DWC2Packet),
+        VMSTATE_UINT32(epnum, DWC2Packet),
+        VMSTATE_UINT32(epdir, DWC2Packet),
+        VMSTATE_UINT32(mps, DWC2Packet),
+        VMSTATE_UINT32(pid, DWC2Packet),
+        VMSTATE_UINT32(index, DWC2Packet),
+        VMSTATE_UINT32(pcnt, DWC2Packet),
+        VMSTATE_UINT32(len, DWC2Packet),
+        VMSTATE_INT32(async, DWC2Packet),
+        VMSTATE_BOOL(small, DWC2Packet),
+        VMSTATE_BOOL(needs_service, DWC2Packet),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+const VMStateDescription vmstate_dwc2_state = {
+    .name = "dwc2",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(glbreg, DWC2State,
+                             DWC2_GLBREG_SIZE / sizeof(uint32_t)),
+        VMSTATE_UINT32_ARRAY(fszreg, DWC2State,
+                             DWC2_FSZREG_SIZE / sizeof(uint32_t)),
+        VMSTATE_UINT32_ARRAY(hreg0, DWC2State,
+                             DWC2_HREG0_SIZE / sizeof(uint32_t)),
+        VMSTATE_UINT32_ARRAY(hreg1, DWC2State,
+                             DWC2_HREG1_SIZE / sizeof(uint32_t)),
+        VMSTATE_UINT32_ARRAY(pcgreg, DWC2State,
+                             DWC2_PCGREG_SIZE / sizeof(uint32_t)),
+
+        VMSTATE_TIMER_PTR(eof_timer, DWC2State),
+        VMSTATE_TIMER_PTR(frame_timer, DWC2State),
+        VMSTATE_INT64(sof_time, DWC2State),
+        VMSTATE_INT64(usb_frame_time, DWC2State),
+        VMSTATE_INT64(usb_bit_time, DWC2State),
+        VMSTATE_UINT32(usb_version, DWC2State),
+        VMSTATE_UINT16(frame_number, DWC2State),
+        VMSTATE_UINT16(fi, DWC2State),
+        VMSTATE_UINT16(next_chan, DWC2State),
+        VMSTATE_BOOL(working, DWC2State),
+
+        VMSTATE_STRUCT_ARRAY(packet, DWC2State, DWC2_NB_CHAN, 1,
+                             vmstate_dwc2_state_packet, DWC2Packet),
+        VMSTATE_UINT8_2DARRAY(usb_buf, DWC2State, DWC2_NB_CHAN,
+                              DWC2_MAX_XFER_SIZE),
+
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static Property dwc2_usb_properties[] = {
+    DEFINE_PROP_UINT32("usb_version", DWC2State, usb_version, 2),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void dwc2_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    DWC2Class *c = DWC2_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+    dc->realize = dwc2_realize;
+    dc->vmsd = &vmstate_dwc2_state;
+    set_bit(DEVICE_CATEGORY_USB, dc->categories);
+    device_class_set_props(dc, dwc2_usb_properties);
+    resettable_class_set_parent_phases(rc, dwc2_reset_enter, dwc2_reset_hold,
+                                       dwc2_reset_exit, &c->parent_phases);
+}
+
+static const TypeInfo dwc2_usb_type_info = {
+    .name          = TYPE_DWC2_USB,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(DWC2State),
+    .instance_init = dwc2_init,
+    .class_size    = sizeof(DWC2Class),
+    .class_init    = dwc2_class_init,
+};
+
+static void dwc2_usb_register_types(void)
+{
+    type_register_static(&dwc2_usb_type_info);
+}
+
+type_init(dwc2_usb_register_types)
diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/usb/Kconfig
+++ b/hw/usb/Kconfig
@@ -XXX,XX +XXX,XX @@ config USB_MUSB
     bool
     select USB
 
+config USB_DWC2
+    bool
+    default y
+    select USB
+
 config TUSB6010
     bool
     select USB_MUSB
diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/usb/Makefile.objs
+++ b/hw/usb/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_USB_EHCI_SYSBUS) += hcd-ehci-sysbus.o
 common-obj-$(CONFIG_USB_XHCI) += hcd-xhci.o
 common-obj-$(CONFIG_USB_XHCI_NEC) += hcd-xhci-nec.o
 common-obj-$(CONFIG_USB_MUSB) += hcd-musb.o
+common-obj-$(CONFIG_USB_DWC2) += hcd-dwc2.o
 
 common-obj-$(CONFIG_TUSB6010) += tusb6010.o
 common-obj-$(CONFIG_IMX)      += chipidea.o
diff --git a/hw/usb/trace-events b/hw/usb/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/usb/trace-events
+++ b/hw/usb/trace-events
@@ -XXX,XX +XXX,XX @@ usb_xhci_xfer_error(void *xfer, uint32_t ret) "%p: ret %d"
 usb_xhci_unimplemented(const char *item, int nr) "%s (0x%x)"
 usb_xhci_enforced_limit(const char *item) "%s"
 
+# hcd-dwc2.c
+usb_dwc2_update_irq(uint32_t level) "level=%d"
+usb_dwc2_raise_global_irq(uint32_t intr) "0x%08x"
+usb_dwc2_lower_global_irq(uint32_t intr) "0x%08x"
+usb_dwc2_raise_host_irq(uint32_t intr) "0x%04x"
+usb_dwc2_lower_host_irq(uint32_t intr) "0x%04x"
+usb_dwc2_sof(int64_t next) "next SOF %" PRId64
+usb_dwc2_bus_start(void) "start SOFs"
+usb_dwc2_bus_stop(void) "stop SOFs"
+usb_dwc2_find_device(uint8_t addr) "%d"
+usb_dwc2_port_disabled(uint32_t pnum) "port %d disabled"
+usb_dwc2_device_found(uint32_t pnum) "device found on port %d"
+usb_dwc2_device_not_found(void) "device not found"
+usb_dwc2_handle_packet(uint32_t chan, void *dev, void *pkt, uint32_t ep, const char *type, const char *dir, uint32_t mps, uint32_t len, uint32_t pcnt) "ch %d dev %p pkt %p ep %d type %s dir %s mps %d len %d pcnt %d"
+usb_dwc2_memory_read(uint32_t addr, uint32_t len) "addr %d len %d"
+usb_dwc2_packet_status(const char *status, uint32_t len) "status %s len %d"
+usb_dwc2_packet_error(const char *status) "ERROR %s"
+usb_dwc2_async_packet(void *pkt, uint32_t chan, void *dev, uint32_t ep, const char *dir, uint32_t len) "pkt %p ch %d dev %p ep %d %s len %d"
+usb_dwc2_memory_write(uint32_t addr, uint32_t len) "addr %d len %d"
+usb_dwc2_packet_done(const char *status, uint32_t actual, uint32_t len, uint32_t pcnt) "status %s actual %d len %d pcnt %d"
+usb_dwc2_packet_next(const char *status, uint32_t len, uint32_t pcnt) "status %s len %d pcnt %d"
+usb_dwc2_attach(void *port) "port %p"
+usb_dwc2_attach_speed(const char *speed) "%s-speed device attached"
+usb_dwc2_detach(void *port) "port %p"
+usb_dwc2_child_detach(void *port, void *child) "port %p child %p"
+usb_dwc2_wakeup(void *port) "port %p"
+usb_dwc2_async_packet_complete(void *port, void *pkt, uint32_t chan, void *dev, uint32_t ep, const char *dir, uint32_t len) "port %p packet %p ch %d dev %p ep %d %s len %d"
+usb_dwc2_work_bh(void) ""
+usb_dwc2_work_bh_service(uint32_t first, uint32_t current, void *dev, uint32_t ep) "first %d servicing %d dev %p ep %d"
+usb_dwc2_work_bh_next(uint32_t chan) "next %d"
+usb_dwc2_enable_chan(uint32_t chan, void *dev, void *pkt, uint32_t ep) "ch %d dev %p pkt %p ep %d"
+usb_dwc2_glbreg_read(uint64_t addr, const char *reg, uint32_t val) " 0x%04" PRIx64 " %s val 0x%08x"
+usb_dwc2_glbreg_write(uint64_t addr, const char *reg, uint64_t val, uint32_t old, uint64_t result) "0x%04" PRIx64 " %s val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
+usb_dwc2_fszreg_read(uint64_t addr, uint32_t val) " 0x%04" PRIx64 " HPTXFSIZ  val 0x%08x"
+usb_dwc2_fszreg_write(uint64_t addr, uint64_t val, uint32_t old, uint64_t result) "0x%04" PRIx64 " HPTXFSIZ  val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
+usb_dwc2_hreg0_read(uint64_t addr, const char *reg, uint32_t val) "  0x%04" PRIx64 " %s val 0x%08x"
+usb_dwc2_hreg0_write(uint64_t addr, const char *reg, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " %s val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
+usb_dwc2_hreg1_read(uint64_t addr, const char *reg, uint64_t chan, uint32_t val) "  0x%04" PRIx64 " %s%" PRId64 " val 0x%08x"
+usb_dwc2_hreg1_write(uint64_t addr, const char *reg, uint64_t chan, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " %s%" PRId64 " val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
+usb_dwc2_pcgreg_read(uint64_t addr, const char *reg, uint32_t val) " 0x%04" PRIx64 " %s val 0x%08x"
+usb_dwc2_pcgreg_write(uint64_t addr, const char *reg, uint64_t val, uint32_t old, uint64_t result) "0x%04" PRIx64 " %s val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
+usb_dwc2_hreg2_read(uint64_t addr, uint64_t fifo, uint32_t val) "  0x%04" PRIx64 " FIFO%" PRId64 "     val 0x%08x"
+usb_dwc2_hreg2_write(uint64_t addr, uint64_t fifo, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " FIFO%" PRId64 "     val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
+usb_dwc2_hreg0_action(const char *s) "%s"
+usb_dwc2_wakeup_endpoint(void *ep, uint32_t stream) "endp %p stream %d"
+usb_dwc2_work_timer(void) ""
+usb_dwc2_reset_enter(void) "=== RESET enter ==="
+usb_dwc2_reset_hold(void) "=== RESET hold ==="
+usb_dwc2_reset_exit(void) "=== RESET exit ==="
+
 # desc.c
 usb_desc_device(int addr, int len, int ret) "dev %d query device, len %d, ret %d"
 usb_desc_device_qualifier(int addr, int len, int ret) "dev %d query device qualifier, len %d, ret %d"
-- 
2.20.1

From: Paul Zimmerman <pauldzim@gmail.com>

The dwc-hsotg (dwc2) USB host depends on a short packet to
indicate the end of an IN transfer. The usb-storage driver
currently doesn't provide this, so fix it.

I have tested this change rather extensively using a PC
emulation with xhci, ehci, and uhci controllers, and have
not observed any regressions.

Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Message-id: 20200520235349.21215-6-pauldzim@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/usb/dev-storage.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/usb/dev-storage.c
+++ b/hw/usb/dev-storage.c
@@ -XXX,XX +XXX,XX @@ static void usb_msd_copy_data(MSDState *s, USBPacket *p)
     usb_packet_copy(p, scsi_req_get_buf(s->req) + s->scsi_off, len);
     s->scsi_len -= len;
     s->scsi_off += len;
+    if (len > s->data_len) {
+        len = s->data_len;
+    }
     s->data_len -= len;
     if (s->scsi_len == 0 || s->data_len == 0) {
         scsi_req_continue(s->req);
@@ -XXX,XX +XXX,XX @@ static void usb_msd_command_complete(SCSIRequest *req, uint32_t status, size_t r
             if (s->data_len) {
                 int len = (p->iov.size - p->actual_length);
                 usb_packet_skip(p, len);
+                if (len > s->data_len) {
+                    len = s->data_len;
+                }
                 s->data_len -= len;
             }
             if (s->data_len == 0) {
@@ -XXX,XX +XXX,XX @@ static void usb_msd_handle_data(USBDevice *dev, USBPacket *p)
                 int len = p->iov.size - p->actual_length;
                 if (len) {
                     usb_packet_skip(p, len);
+                    if (len > s->data_len) {
+                        len = s->data_len;
+                    }
                     s->data_len -= len;
                     if (s->data_len == 0) {
                         s->mode = USB_MSDM_CSW;
@@ -XXX,XX +XXX,XX @@ static void usb_msd_handle_data(USBDevice *dev, USBPacket *p)
                 int len = p->iov.size - p->actual_length;
                 if (len) {
                     usb_packet_skip(p, len);
+                    if (len > s->data_len) {
+                        len = s->data_len;
+                    }
                     s->data_len -= len;
                     if (s->data_len == 0) {
                         s->mode = USB_MSDM_CSW;
                     }
                 }
             }
-            if (p->actual_length < p->iov.size) {
+            if (p->actual_length < p->iov.size && (p->short_not_ok ||
+                    s->scsi_len >= p->ep->max_packet_size)) {
                 DPRINTF("Deferring packet %p [wait data-in]\n", p);
                 s->packet = p;
                 p->status = USB_RET_ASYNC;
-- 
2.20.1

From: Paul Zimmerman <pauldzim@gmail.com>

Wire the dwc-hsotg (dwc2) emulation into Qemu

Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Reviewed-by: Philippe Mathieu-Daude <f4bug@amsat.org>
Message-id: 20200520235349.21215-7-pauldzim@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/bcm2835_peripherals.h |  3 ++-
 hw/arm/bcm2835_peripherals.c         | 21 ++++++++++++++++++++-
 2 files changed, 22 insertions(+), 2 deletions(-)

From: Paul Zimmerman <pauldzim@gmail.com>

Add a check for functional dwc-hsotg (dwc2) USB host emulation to
the Raspi 2 acceptance test

Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Reviewed-by: Philippe Mathieu-Daude <f4bug@amsat.org>
Message-id: 20200520235349.21215-8-pauldzim@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/acceptance/boot_linux_console.py | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

Convert the VSHL and VSLI insns from the Neon 2-registers-and-a-shift
group to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-2-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 25 ++++++++++++++++++++++
 target/arm/translate-neon.inc.c | 38 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 18 +++++++---------
 3 files changed, 71 insertions(+), 10 deletions(-)

Convert the VSHR 2-reg-shift insns to decodetree.

Note that unlike the legacy decoder, we present the right shift
amount to the trans_ function as a positive integer.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-3-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 25 ++++++++++++++++++++
 target/arm/translate-neon.inc.c | 41 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 21 +----------------
 3 files changed, 67 insertions(+), 20 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
 ######################################################################
 &2reg_shift vm vd q shift size
 
+# Right shifts are encoded as N - shift, where N is the element size in bits.
+%neon_rshift_i6  16:6 !function=rsub_64
+%neon_rshift_i5  16:5 !function=rsub_32
+%neon_rshift_i4  16:4 !function=rsub_16
+%neon_rshift_i3  16:3 !function=rsub_8
+
+@2reg_shr_d      .... ... . . . ......  .... .... 1 q:1 . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 shift=%neon_rshift_i6
+@2reg_shr_s      .... ... . . . 1 ..... .... .... 0 q:1 . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
+@2reg_shr_h      .... ... . . . 01 .... .... .... 0 q:1 . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4
+@2reg_shr_b      .... ... . . . 001 ... .... .... 0 q:1 . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i3
+
 @2reg_shl_d      .... ... . . . shift:6      .... .... 1 q:1 . . .... \
                  &2reg_shift vm=%vm_dp vd=%vd_dp size=3
 @2reg_shl_s      .... ... . . . 1 shift:5    .... .... 0 q:1 . . .... \
@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
 @2reg_shl_b      .... ... . . . 001 shift:3  .... .... 0 q:1 . . .... \
                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0
 
+VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
+VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
+VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
+VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
+
+VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
+VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
+VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
+VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
+
 VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
 VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
 VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
     return x + 1;
 }
 
+static inline int rsub_64(DisasContext *s, int x)
+{
+    return 64 - x;
+}
+
+static inline int rsub_32(DisasContext *s, int x)
+{
+    return 32 - x;
+}
+static inline int rsub_16(DisasContext *s, int x)
+{
+    return 16 - x;
+}
+static inline int rsub_8(DisasContext *s, int x)
+{
+    return 8 - x;
+}
+
 /* Include the generated Neon decoder */
 #include "decode-neon-dp.inc.c"
 #include "decode-neon-ls.inc.c"
@@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
 
 DO_2SH(VSHL, tcg_gen_gvec_shli)
 DO_2SH(VSLI, gen_gvec_sli)
+
+static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a)
+{
+    /* Signed shift out of range results in all-sign-bits */
+    a->shift = MIN(a->shift, (8 << a->size) - 1);
+    return do_vector_2sh(s, a, tcg_gen_gvec_sari);
+}
+
+static void gen_zero_rd_2sh(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
+                            int64_t shift, uint32_t oprsz, uint32_t maxsz)
+{
+    tcg_gen_gvec_dup_imm(vece, rd_ofs, oprsz, maxsz, 0);
+}
+
+static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a)
+{
+    /* Shift out of range is architecturally valid and results in zero. */
+    if (a->shift >= (8 << a->size)) {
+        return do_vector_2sh(s, a, gen_zero_rd_2sh);
+    } else {
+        return do_vector_2sh(s, a, tcg_gen_gvec_shri);
+    }
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             op = (insn >> 8) & 0xf;
 
             switch (op) {
+            case 0: /* VSHR */
             case 5: /* VSHL, VSLI */
                 return 1; /* handled by decodetree */
             default:
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                 }
 
                 switch (op) {
-                case 0:  /* VSHR */
-                    /* Right shift comes here negative.  */
-                    shift = -shift;
-                    /* Shifts larger than the element size are architecturally
-                     * valid.  Unsigned results in all zeros; signed results
-                     * in all sign bits.
-                     */
-                    if (!u) {
-                        tcg_gen_gvec_sari(size, rd_ofs, rm_ofs,
-                                          MIN(shift, (8 << size) - 1),
-                                          vec_size, vec_size);
-                    } else if (shift >= 8 << size) {
-                        tcg_gen_gvec_dup_imm(MO_8, rd_ofs, vec_size,
-                                             vec_size, 0);
-                    } else {
-                        tcg_gen_gvec_shri(size, rd_ofs, rm_ofs, shift,
-                                          vec_size, vec_size);
-                    }
-                    return 0;
-
                 case 1:  /* VSRA */
                     /* Right shift comes here negative.  */
                     shift = -shift;
-- 
2.20.1

Convert the VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree.
(These are the last instructions in the group that are vectorized;
the rest all require looping over each element.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-4-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 35 ++++++++++++++++++++++
 target/arm/translate-neon.inc.c |  7 +++++
 target/arm/translate.c          | 52 +++------------------------------
 3 files changed, 46 insertions(+), 48 deletions(-)

Convert the VQSHLU and QVSHL 2-reg-shift insns to decodetree.
These are the last of the simple shift-by-immediate insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-5-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  15 +++++
 target/arm/translate-neon.inc.c | 108 +++++++++++++++++++++++++++++++
 target/arm/translate.c          | 110 +-------------------------------
 3 files changed, 126 insertions(+), 107 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
 VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
 VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
 VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
+
+VQSHLU_64_2sh    1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_d
+VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_s
+VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_h
+VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_b
+
+VQSHL_S_64_2sh   1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
+VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
+VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
+VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
+
+VQSHL_U_64_2sh   1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
+VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
+VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
+VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a)
         return do_vector_2sh(s, a, tcg_gen_gvec_shri);
     }
 }
+
+static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a,
+                             NeonGenTwo64OpEnvFn *fn)
+{
+    /*
+     * 2-reg-and-shift operations, size == 3 case, where the
+     * function needs to be passed cpu_env.
+     */
+    TCGv_i64 constimm;
+    int pass;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if ((a->vm | a->vd) & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    /*
+     * To avoid excessive duplication of ops we implement shift
+     * by immediate using the variable shift operations.
+     */
+    constimm = tcg_const_i64(dup_const(a->size, a->shift));
+
+    for (pass = 0; pass < a->q + 1; pass++) {
+        TCGv_i64 tmp = tcg_temp_new_i64();
+
+        neon_load_reg64(tmp, a->vm + pass);
+        fn(tmp, cpu_env, tmp, constimm);
+        neon_store_reg64(tmp, a->vd + pass);
+    }
+    tcg_temp_free_i64(constimm);
+    return true;
+}
+
+static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
+                             NeonGenTwoOpEnvFn *fn)
+{
+    /*
+     * 2-reg-and-shift operations, size < 3 case, where the
+     * helper needs to be passed cpu_env.
+     */
+    TCGv_i32 constimm;
+    int pass;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if ((a->vm | a->vd) & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    /*
+     * To avoid excessive duplication of ops we implement shift
+     * by immediate using the variable shift operations.
+     */
+    constimm = tcg_const_i32(dup_const(a->size, a->shift));
+
+    for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
+        TCGv_i32 tmp = neon_load_reg(a->vm, pass);
+        fn(tmp, cpu_env, tmp, constimm);
+        neon_store_reg(a->vd, pass, tmp);
+    }
+    tcg_temp_free_i32(constimm);
+    return true;
+}
+
+#define DO_2SHIFT_ENV(INSN, FUNC)                                       \
+    static bool trans_##INSN##_64_2sh(DisasContext *s, arg_2reg_shift *a) \
+    {                                                                   \
+        return do_2shift_env_64(s, a, gen_helper_neon_##FUNC##64);      \
+    }                                                                   \
+    static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a)  \
+    {                                                                   \
+        static NeonGenTwoOpEnvFn * const fns[] = {                      \
+            gen_helper_neon_##FUNC##8,                                  \
+            gen_helper_neon_##FUNC##16,                                 \
+            gen_helper_neon_##FUNC##32,                                 \
+        };                                                              \
+        assert(a->size < ARRAY_SIZE(fns));                              \
+        return do_2shift_env_32(s, a, fns[a->size]);                    \
+    }
+
+DO_2SHIFT_ENV(VQSHLU, qshlu_s)
+DO_2SHIFT_ENV(VQSHL_U, qshl_u)
+DO_2SHIFT_ENV(VQSHL_S, qshl_s)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_neon_rsb(int size, TCGv_i32 t0, TCGv_i32 t1)
     }
 }
 
-#define GEN_NEON_INTEGER_OP_ENV(name) do { \
-    switch ((size << 1) | u) { \
-    case 0: \
-        gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
-        break; \
-    case 1: \
-        gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
-        break; \
-    case 2: \
-        gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
-        break; \
-    case 3: \
-        gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
-        break; \
-    case 4: \
-        gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
-        break; \
-    case 5: \
-        gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
-        break; \
-    default: return 1; \
-    }} while (0)
-
 static TCGv_i32 neon_load_scratch(int scratch)
 {
     TCGv_i32 tmp = tcg_temp_new_i32();
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
     int size;
     int shift;
     int pass;
-    int count;
     int u;
     int vec_size;
     uint32_t imm;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             case 3: /* VRSRA */
             case 4: /* VSRI */
             case 5: /* VSHL, VSLI */
+            case 6: /* VQSHLU */
+            case 7: /* VQSHL */
                 return 1; /* handled by decodetree */
             default:
                 break;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     size--;
             }
             shift = (insn >> 16) & ((1 << (3 + size)) - 1);
-            if (op < 8) {
-                /* Shift by immediate:
-                   VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU.  */
-                if (q && ((rd | rm) & 1)) {
-                    return 1;
-                }
-                if (!u && (op == 4 || op == 6)) {
-                    return 1;
-                }
-                /* Right shifts are encoded as N - shift, where N is the
-                   element size in bits.  */
-                if (op <= 4) {
-                    shift = shift - (1 << (size + 3));
-                }
-
-                if (size == 3) {
-                    count = q + 1;
-                } else {
-                    count = q ? 4: 2;
-                }
-
-                /* To avoid excessive duplication of ops we implement shift
-                 * by immediate using the variable shift operations.
-                  */
-                imm = dup_const(size, shift);
-
-                for (pass = 0; pass < count; pass++) {
-                    if (size == 3) {
-                        neon_load_reg64(cpu_V0, rm + pass);
-                        tcg_gen_movi_i64(cpu_V1, imm);
-                        switch (op) {
-                        case 6: /* VQSHLU */
-                            gen_helper_neon_qshlu_s64(cpu_V0, cpu_env,
-                                                      cpu_V0, cpu_V1);
-                            break;
-                        case 7: /* VQSHL */
-                            if (u) {
-                                gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
-                                                         cpu_V0, cpu_V1);
-                            } else {
-                                gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
-                                                         cpu_V0, cpu_V1);
-                            }
-                            break;
-                        default:
-                            g_assert_not_reached();
-                        }
-                        neon_store_reg64(cpu_V0, rd + pass);
-                    } else { /* size < 3 */
-                        /* Operands in T0 and T1.  */
-                        tmp = neon_load_reg(rm, pass);
-                        tmp2 = tcg_temp_new_i32();
-                        tcg_gen_movi_i32(tmp2, imm);
-                        switch (op) {
-                        case 6: /* VQSHLU */
-                            switch (size) {
-                            case 0:
-                                gen_helper_neon_qshlu_s8(tmp, cpu_env,
-                                                         tmp, tmp2);
-                                break;
-                            case 1:
-                                gen_helper_neon_qshlu_s16(tmp, cpu_env,
-                                                          tmp, tmp2);
-                                break;
-                            case 2:
-                                gen_helper_neon_qshlu_s32(tmp, cpu_env,
-                                                          tmp, tmp2);
-                                break;
-                            default:
-                                abort();
-                            }
-                            break;
-                        case 7: /* VQSHL */
-                            GEN_NEON_INTEGER_OP_ENV(qshl);
-                            break;
-                        default:
-                            g_assert_not_reached();
-                        }
-                        tcg_temp_free_i32(tmp2);
-                        neon_store_reg(rd, pass, tmp);
-                    }
-                } /* for pass */
-            } else if (op < 10) {
+            if (op < 10) {
                 /* Shift by immediate and narrow:
                    VSHRN, VRSHRN, VQSHRN, VQRSHRN.  */
                 int input_unsigned = (op == 8) ? !u : u;
-- 
2.20.1

Convert the Neon narrowing shifts where op==8 to decodetree:
 * VSHRN
 * VRSHRN
 * VQSHRUN
 * VQRSHRUN

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-6-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  27 ++++++
 target/arm/translate-neon.inc.c | 167 ++++++++++++++++++++++++++++++++
 target/arm/translate.c          |   1 +
 3 files changed, 195 insertions(+)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
 @2reg_shl_b      .... ... . . . 001 shift:3  .... .... 0 q:1 . . .... \
                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0
 
+# Narrowing right shifts: here the Q bit is part of the opcode decode
+@2reg_shrn_d     .... ... . . . 1 ..... .... .... 0 . . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 q=0 \
+                 shift=%neon_rshift_i5
+@2reg_shrn_s     .... ... . . . 01 .... .... .... 0 . . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0 \
+                 shift=%neon_rshift_i4
+@2reg_shrn_h     .... ... . . . 001 ... .... .... 0 . . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 \
+                 shift=%neon_rshift_i3
+
 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
@@ -XXX,XX +XXX,XX @@ VQSHL_U_64_2sh   1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
 VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
 VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
 VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
+
+VSHRN_64_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
+VSHRN_32_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
+VSHRN_16_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
+
+VRSHRN_64_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
+VRSHRN_32_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
+VRSHRN_16_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
+
+VQSHRUN_64_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
+VQSHRUN_32_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
+VQSHRUN_16_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
+
+VQRSHRUN_64_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
+VQRSHRUN_32_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
+VQRSHRUN_16_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
 DO_2SHIFT_ENV(VQSHLU, qshlu_s)
 DO_2SHIFT_ENV(VQSHL_U, qshl_u)
 DO_2SHIFT_ENV(VQSHL_S, qshl_s)
+
+static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
+                                NeonGenTwo64OpFn *shiftfn,
+                                NeonGenNarrowEnvFn *narrowfn)
+{
+    /* 2-reg-and-shift narrowing-shift operations, size == 3 case */
+    TCGv_i64 constimm, rm1, rm2;
+    TCGv_i32 rd;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if (a->vm & 1) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    /*
+     * This is always a right shift, and the shiftfn is always a
+     * left-shift helper, which thus needs the negated shift count.
+     */
+    constimm = tcg_const_i64(-a->shift);
+    rm1 = tcg_temp_new_i64();
+    rm2 = tcg_temp_new_i64();
+
+    /* Load both inputs first to avoid potential overwrite if rm == rd */
+    neon_load_reg64(rm1, a->vm);
+    neon_load_reg64(rm2, a->vm + 1);
+
+    shiftfn(rm1, rm1, constimm);
+    rd = tcg_temp_new_i32();
+    narrowfn(rd, cpu_env, rm1);
+    neon_store_reg(a->vd, 0, rd);
+
+    shiftfn(rm2, rm2, constimm);
+    rd = tcg_temp_new_i32();
+    narrowfn(rd, cpu_env, rm2);
+    neon_store_reg(a->vd, 1, rd);
+
+    tcg_temp_free_i64(rm1);
+    tcg_temp_free_i64(rm2);
+    tcg_temp_free_i64(constimm);
+
+    return true;
+}
+
+static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
+                                NeonGenTwoOpFn *shiftfn,
+                                NeonGenNarrowEnvFn *narrowfn)
+{
+    /* 2-reg-and-shift narrowing-shift operations, size < 3 case */
+    TCGv_i32 constimm, rm1, rm2, rm3, rm4;
+    TCGv_i64 rtmp;
+    uint32_t imm;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if (a->vm & 1) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    /*
+     * This is always a right shift, and the shiftfn is always a
+     * left-shift helper, which thus needs the negated shift count
+     * duplicated into each lane of the immediate value.
+     */
+    if (a->size == 1) {
+        imm = (uint16_t)(-a->shift);
+        imm |= imm << 16;
+    } else {
+        /* size == 2 */
+        imm = -a->shift;
+    }
+    constimm = tcg_const_i32(imm);
+
+    /* Load all inputs first to avoid potential overwrite */
+    rm1 = neon_load_reg(a->vm, 0);
+    rm2 = neon_load_reg(a->vm, 1);
+    rm3 = neon_load_reg(a->vm + 1, 0);
+    rm4 = neon_load_reg(a->vm + 1, 1);
+    rtmp = tcg_temp_new_i64();
+
+    shiftfn(rm1, rm1, constimm);
+    shiftfn(rm2, rm2, constimm);
+
+    tcg_gen_concat_i32_i64(rtmp, rm1, rm2);
+    tcg_temp_free_i32(rm2);
+
+    narrowfn(rm1, cpu_env, rtmp);
+    neon_store_reg(a->vd, 0, rm1);
+
+    shiftfn(rm3, rm3, constimm);
+    shiftfn(rm4, rm4, constimm);
+    tcg_temp_free_i32(constimm);
+
+    tcg_gen_concat_i32_i64(rtmp, rm3, rm4);
+    tcg_temp_free_i32(rm4);
+
+    narrowfn(rm3, cpu_env, rtmp);
+    tcg_temp_free_i64(rtmp);
+    neon_store_reg(a->vd, 1, rm3);
+    return true;
+}
+
+#define DO_2SN_64(INSN, FUNC, NARROWFUNC)                               \
+    static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a)  \
+    {                                                                   \
+        return do_2shift_narrow_64(s, a, FUNC, NARROWFUNC);             \
+    }
+#define DO_2SN_32(INSN, FUNC, NARROWFUNC)                               \
+    static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a)  \
+    {                                                                   \
+        return do_2shift_narrow_32(s, a, FUNC, NARROWFUNC);             \
+    }
+
+static void gen_neon_narrow_u32(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
+{
+    tcg_gen_extrl_i64_i32(dest, src);
+}
+
+static void gen_neon_narrow_u16(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
+{
+    gen_helper_neon_narrow_u16(dest, src);
+}
+
+static void gen_neon_narrow_u8(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
+{
+    gen_helper_neon_narrow_u8(dest, src);
+}
+
+DO_2SN_64(VSHRN_64, gen_ushl_i64, gen_neon_narrow_u32)
+DO_2SN_32(VSHRN_32, gen_ushl_i32, gen_neon_narrow_u16)
+DO_2SN_32(VSHRN_16, gen_helper_neon_shl_u16, gen_neon_narrow_u8)
+
+DO_2SN_64(VRSHRN_64, gen_helper_neon_rshl_u64, gen_neon_narrow_u32)
+DO_2SN_32(VRSHRN_32, gen_helper_neon_rshl_u32, gen_neon_narrow_u16)
+DO_2SN_32(VRSHRN_16, gen_helper_neon_rshl_u16, gen_neon_narrow_u8)
+
+DO_2SN_64(VQSHRUN_64, gen_sshl_i64, gen_helper_neon_unarrow_sat32)
+DO_2SN_32(VQSHRUN_32, gen_sshl_i32, gen_helper_neon_unarrow_sat16)
+DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat8)
+
+DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_sat32)
+DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_sat16)
+DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_sat8)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             case 5: /* VSHL, VSLI */
             case 6: /* VQSHLU */
             case 7: /* VQSHL */
+            case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
                 return 1; /* handled by decodetree */
             default:
                 break;
-- 
2.20.1

Convert the remaining Neon narrowing shifts to decodetree:
  * VQSHRN
  * VQRSHRN

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-7-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  20 ++++++
 target/arm/translate-neon.inc.c |  15 +++++
 target/arm/translate.c          | 110 +-------------------------------
 3 files changed, 37 insertions(+), 108 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VQSHRUN_16_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
 VQRSHRUN_64_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
 VQRSHRUN_32_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
 VQRSHRUN_16_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
+
+# VQSHRN with signed input
+VQSHRN_S64_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
+VQSHRN_S32_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
+VQSHRN_S16_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
+
+# VQRSHRN with signed input
+VQRSHRN_S64_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
+VQRSHRN_S32_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
+VQRSHRN_S16_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
+
+# VQSHRN with unsigned input
+VQSHRN_U64_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
+VQSHRN_U32_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
+VQSHRN_U16_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
+
+# VQRSHRN with unsigned input
+VQRSHRN_U64_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
+VQRSHRN_U32_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
+VQRSHRN_U16_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat8)
 DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_sat32)
 DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_sat16)
 DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_sat8)
+DO_2SN_64(VQSHRN_S64, gen_sshl_i64, gen_helper_neon_narrow_sat_s32)
+DO_2SN_32(VQSHRN_S32, gen_sshl_i32, gen_helper_neon_narrow_sat_s16)
+DO_2SN_32(VQSHRN_S16, gen_helper_neon_shl_s16, gen_helper_neon_narrow_sat_s8)
+
+DO_2SN_64(VQRSHRN_S64, gen_helper_neon_rshl_s64, gen_helper_neon_narrow_sat_s32)
+DO_2SN_32(VQRSHRN_S32, gen_helper_neon_rshl_s32, gen_helper_neon_narrow_sat_s16)
+DO_2SN_32(VQRSHRN_S16, gen_helper_neon_rshl_s16, gen_helper_neon_narrow_sat_s8)
+
+DO_2SN_64(VQSHRN_U64, gen_ushl_i64, gen_helper_neon_narrow_sat_u32)
+DO_2SN_32(VQSHRN_U32, gen_ushl_i32, gen_helper_neon_narrow_sat_u16)
+DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_u8)
+
+DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sat_u32)
+DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sat_u16)
+DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sat_u8)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_neon_unarrow_sats(int size, TCGv_i32 dest, TCGv_i64 src)
     }
 }
 
-static inline void gen_neon_shift_narrow(int size, TCGv_i32 var, TCGv_i32 shift,
-                                         int q, int u)
-{
-    if (q) {
-        if (u) {
-            switch (size) {
-            case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
-            case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
-            default: abort();
-            }
-        } else {
-            switch (size) {
-            case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
-            case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
-            default: abort();
-            }
-        }
-    } else {
-        if (u) {
-            switch (size) {
-            case 1: gen_helper_neon_shl_u16(var, var, shift); break;
-            case 2: gen_ushl_i32(var, var, shift); break;
-            default: abort();
-            }
-        } else {
-            switch (size) {
-            case 1: gen_helper_neon_shl_s16(var, var, shift); break;
-            case 2: gen_sshl_i32(var, var, shift); break;
-            default: abort();
-            }
-        }
-    }
-}
-
 static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u)
 {
     if (u) {
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             case 6: /* VQSHLU */
             case 7: /* VQSHL */
             case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
+            case 9: /* VQSHRN, VQRSHRN */
                 return 1; /* handled by decodetree */
             default:
                 break;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     size--;
             }
             shift = (insn >> 16) & ((1 << (3 + size)) - 1);
-            if (op < 10) {
-                /* Shift by immediate and narrow:
-                   VSHRN, VRSHRN, VQSHRN, VQRSHRN.  */
-                int input_unsigned = (op == 8) ? !u : u;
-                if (rm & 1) {
-                    return 1;
-                }
-                shift = shift - (1 << (size + 3));
-                size++;
-                if (size == 3) {
-                    tmp64 = tcg_const_i64(shift);
-                    neon_load_reg64(cpu_V0, rm);
-                    neon_load_reg64(cpu_V1, rm + 1);
-                    for (pass = 0; pass < 2; pass++) {
-                        TCGv_i64 in;
-                        if (pass == 0) {
-                            in = cpu_V0;
-                        } else {
-                            in = cpu_V1;
-                        }
-                        if (q) {
-                            if (input_unsigned) {
-                                gen_helper_neon_rshl_u64(cpu_V0, in, tmp64);
-                            } else {
-                                gen_helper_neon_rshl_s64(cpu_V0, in, tmp64);
-                            }
-                        } else {
-                            if (input_unsigned) {
-                                gen_ushl_i64(cpu_V0, in, tmp64);
-                            } else {
-                                gen_sshl_i64(cpu_V0, in, tmp64);
-                            }
-                        }
-                        tmp = tcg_temp_new_i32();
-                        gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
-                        neon_store_reg(rd, pass, tmp);
-                    } /* for pass */
-                    tcg_temp_free_i64(tmp64);
-                } else {
-                    if (size == 1) {
-                        imm = (uint16_t)shift;
-                        imm |= imm << 16;
-                    } else {
-                        /* size == 2 */
-                        imm = (uint32_t)shift;
-                    }
-                    tmp2 = tcg_const_i32(imm);
-                    tmp4 = neon_load_reg(rm + 1, 0);
-                    tmp5 = neon_load_reg(rm + 1, 1);
-                    for (pass = 0; pass < 2; pass++) {
-                        if (pass == 0) {
-                            tmp = neon_load_reg(rm, 0);
-                        } else {
-                            tmp = tmp4;
-                        }
-                        gen_neon_shift_narrow(size, tmp, tmp2, q,
-                                              input_unsigned);
-                        if (pass == 0) {
-                            tmp3 = neon_load_reg(rm, 1);
-                        } else {
-                            tmp3 = tmp5;
-                        }
-                        gen_neon_shift_narrow(size, tmp3, tmp2, q,
-                                              input_unsigned);
-                        tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
-                        tcg_temp_free_i32(tmp);
-                        tcg_temp_free_i32(tmp3);
-                        tmp = tcg_temp_new_i32();
-                        gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
-                        neon_store_reg(rd, pass, tmp);
-                    } /* for pass */
-                    tcg_temp_free_i32(tmp2);
-                }
-            } else if (op == 10) {
+            if (op == 10) {
                 /* VSHLL, VMOVL */
                 if (q || (rd & 1)) {
                     return 1;
-- 
2.20.1

Convert the VSHLL and VMOVL insns from the 2-reg-shift group
to decodetree. Since the loop always has two passes, we unroll
it to avoid the awkward reassignment of one TCGv to another.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-8-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 16 +++++++
 target/arm/translate-neon.inc.c | 81 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 46 +------------------
 3 files changed, 99 insertions(+), 44 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
                  &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 \
                  shift=%neon_rshift_i3
 
+# Long left shifts: again Q is part of opcode decode
+@2reg_shll_s     .... ... . . . 1 shift:5    .... .... 0 . . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0
+@2reg_shll_h     .... ... . . . 01 shift:4   .... .... 0 . . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0
+@2reg_shll_b     .... ... . . . 001 shift:3  .... .... 0 . . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
+
 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
@@ -XXX,XX +XXX,XX @@ VQSHRN_U16_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
 VQRSHRN_U64_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
 VQRSHRN_U32_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
 VQRSHRN_U16_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
+
+VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
+VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
+VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
+
+VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
+VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
+VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_u8)
 DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sat_u32)
 DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sat_u16)
 DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sat_u8)
+
+static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
+                         NeonGenWidenFn *widenfn, bool u)
+{
+    TCGv_i64 tmp;
+    TCGv_i32 rm0, rm1;
+    uint64_t widen_mask = 0;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if (a->vd & 1) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    /*
+     * This is a widen-and-shift operation. The shift is always less
+     * than the width of the source type, so after widening the input
+     * vector we can simply shift the whole 64-bit widened register,
+     * and then clear the potential overflow bits resulting from left
+     * bits of the narrow input appearing as right bits of the left
+     * neighbour narrow input. Calculate a mask of bits to clear.
+     */
+    if ((a->shift != 0) && (a->size < 2 || u)) {
+        int esize = 8 << a->size;
+        widen_mask = MAKE_64BIT_MASK(0, esize);
+        widen_mask >>= esize - a->shift;
+        widen_mask = dup_const(a->size + 1, widen_mask);
+    }
+
+    rm0 = neon_load_reg(a->vm, 0);
+    rm1 = neon_load_reg(a->vm, 1);
+    tmp = tcg_temp_new_i64();
+
+    widenfn(tmp, rm0);
+    if (a->shift != 0) {
+        tcg_gen_shli_i64(tmp, tmp, a->shift);
+        tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
+    }
+    neon_store_reg64(tmp, a->vd);
+
+    widenfn(tmp, rm1);
+    if (a->shift != 0) {
+        tcg_gen_shli_i64(tmp, tmp, a->shift);
+        tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
+    }
+    neon_store_reg64(tmp, a->vd + 1);
+    tcg_temp_free_i64(tmp);
+    return true;
+}
+
+static bool trans_VSHLL_S_2sh(DisasContext *s, arg_2reg_shift *a)
+{
+    NeonGenWidenFn *widenfn[] = {
+        gen_helper_neon_widen_s8,
+        gen_helper_neon_widen_s16,
+        tcg_gen_ext_i32_i64,
+    };
+    return do_vshll_2sh(s, a, widenfn[a->size], false);
+}
+
+static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a)
+{
+    NeonGenWidenFn *widenfn[] = {
+        gen_helper_neon_widen_u8,
+        gen_helper_neon_widen_u16,
+        tcg_gen_extu_i32_i64,
+    };
+    return do_vshll_2sh(s, a, widenfn[a->size], true);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             case 7: /* VQSHL */
             case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
             case 9: /* VQSHRN, VQRSHRN */
+            case 10: /* VSHLL, including VMOVL */
                 return 1; /* handled by decodetree */
             default:
                 break;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     size--;
             }
             shift = (insn >> 16) & ((1 << (3 + size)) - 1);
-            if (op == 10) {
-                /* VSHLL, VMOVL */
-                if (q || (rd & 1)) {
-                    return 1;
-                }
-                tmp = neon_load_reg(rm, 0);
-                tmp2 = neon_load_reg(rm, 1);
-                for (pass = 0; pass < 2; pass++) {
-                    if (pass == 1)
-                        tmp = tmp2;
-
-                    gen_neon_widen(cpu_V0, tmp, size, u);
-
-                    if (shift != 0) {
-                        /* The shift is less than the width of the source
-                           type, so we can just shift the whole register.  */
-                        tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
-                        /* Widen the result of shift: we need to clear
-                         * the potential overflow bits resulting from
-                         * left bits of the narrow input appearing as
-                         * right bits of left the neighbour narrow
-                         * input.  */
-                        if (size < 2 || !u) {
-                            uint64_t imm64;
-                            if (size == 0) {
-                                imm = (0xffu >> (8 - shift));
-                                imm |= imm << 16;
-                            } else if (size == 1) {
-                                imm = 0xffff >> (16 - shift);
-                            } else {
-                                /* size == 2 */
-                                imm = 0xffffffff >> (32 - shift);
-                            }
-                            if (size < 2) {
-                                imm64 = imm | (((uint64_t)imm) << 32);
-                            } else {
-                                imm64 = imm;
-                            }
-                            tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64);
-                        }
-                    }
-                    neon_store_reg64(cpu_V0, rd + pass);
-                }
-            } else if (op >= 14) {
+            if (op >= 14) {
                 /* VCVT fixed-point.  */
                 TCGv_ptr fpst;
                 TCGv_i32 shiftv;
-- 
2.20.1

Convert the VCVT fixed-point conversion operations in the
Neon 2-regs-and-shift group to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-9-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 11 +++++
 target/arm/translate-neon.inc.c | 49 +++++++++++++++++++++
 target/arm/translate.c          | 75 +--------------------------------
 3 files changed, 62 insertions(+), 73 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
 @2reg_shll_b     .... ... . . . 001 shift:3  .... .... 0 . . . .... \
                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
 
+# We use size=0 for fp32 and size=1 for fp16 to match the 3-same encodings.
+@2reg_vcvt       .... ... . . . 1 ..... .... .... . q:1 . . .... \
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i5
+
 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
@@ -XXX,XX +XXX,XX @@ VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
 VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
 VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
 VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
+
+# VCVT fixed<->float conversions
+# TODO: FP16 fixed<->float conversions are opc==0b1100 and 0b1101
+VCVT_SF_2sh      1111 001 0 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
+VCVT_UF_2sh      1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
+VCVT_FS_2sh      1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
+VCVT_FU_2sh      1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a)
     };
     return do_vshll_2sh(s, a, widenfn[a->size], true);
 }
+
+static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
+                      NeonGenTwoSingleOPFn *fn)
+{
+    /* FP operations in 2-reg-and-shift group */
+    TCGv_i32 tmp, shiftv;
+    TCGv_ptr fpstatus;
+    int pass;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if ((a->vm | a->vd) & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    fpstatus = get_fpstatus_ptr(1);
+    shiftv = tcg_const_i32(a->shift);
+    for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
+        tmp = neon_load_reg(a->vm, pass);
+        fn(tmp, tmp, shiftv, fpstatus);
+        neon_store_reg(a->vd, pass, tmp);
+    }
+    tcg_temp_free_ptr(fpstatus);
+    tcg_temp_free_i32(shiftv);
+    return true;
+}
+
+#define DO_FP_2SH(INSN, FUNC)                                           \
+    static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a)  \
+    {                                                                   \
+        return do_fp_2sh(s, a, FUNC);                                   \
+    }
+
+DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos)
+DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos)
+DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero)
+DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
     int q;
     int rd, rn, rm, rd_ofs, rn_ofs, rm_ofs;
     int size;
-    int shift;
     int pass;
     int u;
     int vec_size;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
         return 1;
     } else if (insn & (1 << 4)) {
         if ((insn & 0x00380080) != 0) {
-            /* Two registers and shift.  */
-            op = (insn >> 8) & 0xf;
-
-            switch (op) {
-            case 0: /* VSHR */
-            case 1: /* VSRA */
-            case 2: /* VRSHR */
-            case 3: /* VRSRA */
-            case 4: /* VSRI */
-            case 5: /* VSHL, VSLI */
-            case 6: /* VQSHLU */
-            case 7: /* VQSHL */
-            case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
-            case 9: /* VQSHRN, VQRSHRN */
-            case 10: /* VSHLL, including VMOVL */
-                return 1; /* handled by decodetree */
-            default:
-                break;
-            }
-
-            if (insn & (1 << 7)) {
-                /* 64-bit shift. */
-                if (op > 7) {
-                    return 1;
-                }
-                size = 3;
-            } else {
-                size = 2;
-                while ((insn & (1 << (size + 19))) == 0)
-                    size--;
-            }
-            shift = (insn >> 16) & ((1 << (3 + size)) - 1);
-            if (op >= 14) {
-                /* VCVT fixed-point.  */
-                TCGv_ptr fpst;
-                TCGv_i32 shiftv;
-                VFPGenFixPointFn *fn;
-
-                if (!(insn & (1 << 21)) || (q && ((rd | rm) & 1))) {
-                    return 1;
-                }
-
-                if (!(op & 1)) {
-                    if (u) {
-                        fn = gen_helper_vfp_ultos;
-                    } else {
-                        fn = gen_helper_vfp_sltos;
-                    }
-                } else {
-                    if (u) {
-                        fn = gen_helper_vfp_touls_round_to_zero;
-                    } else {
-                        fn = gen_helper_vfp_tosls_round_to_zero;
-                    }
-                }
-
-                /* We have already masked out the must-be-1 top bit of imm6,
-                 * hence this 32-shift where the ARM ARM has 64-imm6.
-                 */
-                shift = 32 - shift;
-                fpst = get_fpstatus_ptr(1);
-                shiftv = tcg_const_i32(shift);
-                for (pass = 0; pass < (q ? 4 : 2); pass++) {
-                    TCGv_i32 tmpf = neon_load_reg(rm, pass);
-                    fn(tmpf, tmpf, shiftv, fpst);
-                    neon_store_reg(rd, pass, tmpf);
-                }
-                tcg_temp_free_ptr(fpst);
-                tcg_temp_free_i32(shiftv);
-            } else {
-                return 1;
-            }
+            /* Two registers and shift: handled by decodetree */
+            return 1;
         } else { /* (insn & 0x00380080) == 0 */
             int invert, reg_ofs, vec_size;
 
-- 
2.20.1

Convert the insns in the one-register-and-immediate group to decodetree.

In the new decode, our asimd_imm_const() function returns a 64-bit value
rather than a 32-bit one, which means we don't need to treat cmode=14 op=1
as a special case in the decoder (it is the only encoding where the two
halves of the 64-bit value are different).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-10-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  22 ++++++
 target/arm/translate-neon.inc.c | 118 ++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 101 +--------------------------
 3 files changed, 142 insertions(+), 99 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VCVT_SF_2sh      1111 001 0 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
 VCVT_UF_2sh      1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
 VCVT_FS_2sh      1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
 VCVT_FU_2sh      1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
+
+######################################################################
+# 1-reg-and-modified-immediate grouping:
+# 1111 001 i 1 D 000 imm:3 Vd:4 cmode:4 0 Q op 1 Vm:4
+######################################################################
+
+&1reg_imm        vd q imm cmode op
+
+%asimd_imm_value 24:1 16:3 0:4
+
+@1reg_imm        .... ... . . . ... ... .... .... . q:1 . . .... \
+                 &1reg_imm imm=%asimd_imm_value vd=%vd_dp
+
+# The cmode/op bits here decode VORR/VBIC/VMOV/VMNV, but
+# not in a way we can conveniently represent in decodetree without
+# a lot of repetition:
+# VORR: op=0, (cmode & 1) && cmode < 12
+# VBIC: op=1, (cmode & 1) && cmode < 12
+# VMOV: everything else
+# So we have a single decode line and check the cmode/op in the
+# trans function.
+Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos)
 DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos)
 DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero)
 DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero)
+
+static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
+{
+    /*
+     * Expand the encoded constant.
+     * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
+     * We choose to not special-case this and will behave as if a
+     * valid constant encoding of 0 had been given.
+     * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
+     */
+    switch (cmode) {
+    case 0: case 1:
+        /* no-op */
+        break;
+    case 2: case 3:
+        imm <<= 8;
+        break;
+    case 4: case 5:
+        imm <<= 16;
+        break;
+    case 6: case 7:
+        imm <<= 24;
+        break;
+    case 8: case 9:
+        imm |= imm << 16;
+        break;
+    case 10: case 11:
+        imm = (imm << 8) | (imm << 24);
+        break;
+    case 12:
+        imm = (imm << 8) | 0xff;
+        break;
+    case 13:
+        imm = (imm << 16) | 0xffff;
+        break;
+    case 14:
+        if (op) {
+            /*
+             * This is the only case where the top and bottom 32 bits
+             * of the encoded constant differ.
+             */
+            uint64_t imm64 = 0;
+            int n;
+
+            for (n = 0; n < 8; n++) {
+                if (imm & (1 << n)) {
+                    imm64 |= (0xffULL << (n * 8));
+                }
+            }
+            return imm64;
+        }
+        imm |= (imm << 8) | (imm << 16) | (imm << 24);
+        break;
+    case 15:
+        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
+            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
+        break;
+    }
+    if (op) {
+        imm = ~imm;
+    }
+    return dup_const(MO_32, imm);
+}
+
+static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
+                        GVecGen2iFn *fn)
+{
+    uint64_t imm;
+    int reg_ofs, vec_size;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+        return false;
+    }
+
+    if (a->vd & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    reg_ofs = neon_reg_offset(a->vd, 0);
+    vec_size = a->q ? 16 : 8;
+    imm = asimd_imm_const(a->imm, a->cmode, a->op);
+
+    fn(MO_64, reg_ofs, reg_ofs, imm, vec_size, vec_size);
+    return true;
+}
+
+static void gen_VMOV_1r(unsigned vece, uint32_t dofs, uint32_t aofs,
+                        int64_t c, uint32_t oprsz, uint32_t maxsz)
+{
+    tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, c);
+}
+
+static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a)
+{
+    /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
+    GVecGen2iFn *fn;
+
+    if ((a->cmode & 1) && a->cmode < 12) {
+        /* for op=1, the imm will be inverted, so BIC becomes AND. */
+        fn = a->op ? tcg_gen_gvec_andi : tcg_gen_gvec_ori;
+    } else {
+        /* There is one unallocated cmode/op combination in this space */
+        if (a->cmode == 15 && a->op == 1) {
+            return false;
+        }
+        fn = gen_VMOV_1r;
+    }
+    return do_1reg_imm(s, a, fn);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
         /* Three register same length: handled by decodetree */
         return 1;
     } else if (insn & (1 << 4)) {
-        if ((insn & 0x00380080) != 0) {
-            /* Two registers and shift: handled by decodetree */
-            return 1;
-        } else { /* (insn & 0x00380080) == 0 */
-            int invert, reg_ofs, vec_size;
-
-            if (q && (rd & 1)) {
-                return 1;
-            }
-
-            op = (insn >> 8) & 0xf;
-            /* One register and immediate.  */
-            imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
-            invert = (insn & (1 << 5)) != 0;
-            /* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
-             * We choose to not special-case this and will behave as if a
-             * valid constant encoding of 0 had been given.
-             */
-            switch (op) {
-            case 0: case 1:
-                /* no-op */
-                break;
-            case 2: case 3:
-                imm <<= 8;
-                break;
-            case 4: case 5:
-                imm <<= 16;
-                break;
-            case 6: case 7:
-                imm <<= 24;
-                break;
-            case 8: case 9:
-                imm |= imm << 16;
-                break;
-            case 10: case 11:
-                imm = (imm << 8) | (imm << 24);
-                break;
-            case 12:
-                imm = (imm << 8) | 0xff;
-                break;
-            case 13:
-                imm = (imm << 16) | 0xffff;
-                break;
-            case 14:
-                imm |= (imm << 8) | (imm << 16) | (imm << 24);
-                if (invert) {
-                    imm = ~imm;
-                }
-                break;
-            case 15:
-                if (invert) {
-                    return 1;
-                }
-                imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
-                      | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
-                break;
-            }
-            if (invert) {
-                imm = ~imm;
-            }
-
-            reg_ofs = neon_reg_offset(rd, 0);
-            vec_size = q ? 16 : 8;
-
-            if (op & 1 && op < 12) {
-                if (invert) {
-                    /* The immediate value has already been inverted,
-                     * so BIC becomes AND.
-                     */
-                    tcg_gen_gvec_andi(MO_32, reg_ofs, reg_ofs, imm,
-                                      vec_size, vec_size);
-                } else {
-                    tcg_gen_gvec_ori(MO_32, reg_ofs, reg_ofs, imm,
-                                     vec_size, vec_size);
-                }
-            } else {
-                /* VMOV, VMVN.  */
-                if (op == 14 && invert) {
-                    TCGv_i64 t64 = tcg_temp_new_i64();
-
-                    for (pass = 0; pass <= q; ++pass) {
-                        uint64_t val = 0;
-                        int n;
-
-                        for (n = 0; n < 8; n++) {
-                            if (imm & (1 << (n + pass * 8))) {
-                                val |= 0xffull << (n * 8);
-                            }
-                        }
-                        tcg_gen_movi_i64(t64, val);
-                        neon_store_reg64(t64, rd + pass);
-                    }
-                    tcg_temp_free_i64(t64);
-                } else {
-                    tcg_gen_gvec_dup_imm(MO_32, reg_ofs, vec_size,
-                                         vec_size, imm);
-                }
-            }
-        }
+        /* Two registers and shift or reg and imm: handled by decodetree */
+        return 1;
     } else { /* (insn & 0x00800010 == 0x00800000) */
         if (size != 3) {
             op = (insn >> 8) & 0xf;
-- 
2.20.1

The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:

Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702

for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:

target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)

----------------------------------------------------------------
target-arm queue:
 * more MVE instructions
 * hw/gpio/gpio_pwr: use shutdown function for reboot
 * target/arm: Check NaN mode before silencing NaN
 * tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
 * hw/arm: Add basic power management to raspi.
 * docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc

----------------------------------------------------------------
Joe Komlodi (1):
      target/arm: Check NaN mode before silencing NaN

Maxim Uvarov (1):
      hw/gpio/gpio_pwr: use shutdown function for reboot

Nolan Leake (1):
      hw/arm: Add basic power management to raspi.

Patrick Venture (2):
      docs/system/arm: Add quanta-q7l1-bmc reference
      docs/system/arm: Add quanta-gbs-bmc reference

Peter Maydell (18):
      target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
      target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
      target/arm: Make asimd_imm_const() public
      target/arm: Use asimd_imm_const for A64 decode
      target/arm: Use dup_const() instead of bitfield_replicate()
      target/arm: Implement MVE logical immediate insns
      target/arm: Implement MVE vector shift left by immediate insns
      target/arm: Implement MVE vector shift right by immediate insns
      target/arm: Implement MVE VSHLL
      target/arm: Implement MVE VSRI, VSLI
      target/arm: Implement MVE VSHRN, VRSHRN
      target/arm: Implement MVE saturating narrowing shifts
      target/arm: Implement MVE VSHLC
      target/arm: Implement MVE VADDLV
      target/arm: Implement MVE long shifts by immediate
      target/arm: Implement MVE long shifts by register
      target/arm: Implement MVE shifts by immediate
      target/arm: Implement MVE shifts by register

Philippe Mathieu-Daudé (1):
      tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine

docs/system/arm/aspeed.rst             |   1 +
 docs/system/arm/nuvoton.rst            |   5 +-
 include/hw/arm/bcm2835_peripherals.h   |   3 +-
 include/hw/misc/bcm2835_powermgt.h     |  29 ++
 target/arm/helper-mve.h                | 108 +++++++
 target/arm/translate.h                 |  41 +++
 target/arm/mve.decode                  | 177 ++++++++++-
 target/arm/t32.decode                  |  71 ++++-
 hw/arm/bcm2835_peripherals.c           |  13 +-
 hw/gpio/gpio_pwr.c                     |   2 +-
 hw/misc/bcm2835_powermgt.c             | 160 ++++++++++
 target/arm/helper-a64.c                |  12 +-
 target/arm/mve_helper.c                | 524 +++++++++++++++++++++++++++++++--
 target/arm/translate-a64.c             |  86 +-----
 target/arm/translate-mve.c             | 261 +++++++++++++++-
 target/arm/translate-neon.c            |  81 -----
 target/arm/translate.c                 | 327 +++++++++++++++++++-
 target/arm/vfp_helper.c                |  24 +-
 hw/misc/meson.build                    |   1 +
 tests/acceptance/boot_linux_console.py |  43 +++
 20 files changed, 1760 insertions(+), 209 deletions(-)
 create mode 100644 include/hw/misc/bcm2835_powermgt.h
 create mode 100644 hw/misc/bcm2835_powermgt.c

From: Patrick Venture <venture@google.com>

Add line item reference to quanta-gbs-bmc machine.

Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20210615192848.1065297-3-venture@google.com
[PMM: fixed underline Sphinx warning]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/nuvoton.rst | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@
-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
-=====================================================
+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
+================================================================
 
 The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
 designed to be used as Baseboard Management Controllers (BMCs) in various
@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
 Hyperscale applications. The following machines are based on this chip :
 
+- ``quanta-gbs-bmc``    Quanta GBS server BMC
 - ``quanta-gsj``        Quanta GSJ server BMC
 
 There are also two more SoCs, NPCM710 and NPCM705, which are single-core
-- 
2.20.1

From: Nolan Leake <nolan@sigbus.net>

This is just enough to make reboot and poweroff work. Works for
linux, u-boot, and the arm trusted firmware. Not tested, but should
work for plan9, and bare-metal/hobby OSes, since they seem to generally
do what linux does for reset.

The watchdog timer functionality is not yet implemented.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
Signed-off-by: Nolan Leake <nolan@sigbus.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
[PMM: tweaked commit title; fixed region size to 0x200;
 moved header file to include/]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/bcm2835_peripherals.h |   3 +-
 include/hw/misc/bcm2835_powermgt.h   |  29 +++++
 hw/arm/bcm2835_peripherals.c         |  13 ++-
 hw/misc/bcm2835_powermgt.c           | 160 +++++++++++++++++++++++++++
 hw/misc/meson.build                  |   1 +
 5 files changed, 204 insertions(+), 2 deletions(-)
 create mode 100644 include/hw/misc/bcm2835_powermgt.h
 create mode 100644 hw/misc/bcm2835_powermgt.c

diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2835_peripherals.h
+++ b/include/hw/arm/bcm2835_peripherals.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/bcm2835_mphi.h"
 #include "hw/misc/bcm2835_thermal.h"
 #include "hw/misc/bcm2835_cprman.h"
+#include "hw/misc/bcm2835_powermgt.h"
 #include "hw/sd/sdhci.h"
 #include "hw/sd/bcm2835_sdhost.h"
 #include "hw/gpio/bcm2835_gpio.h"
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
     BCM2835MphiState mphi;
     UnimplementedDeviceState txp;
     UnimplementedDeviceState armtmr;
-    UnimplementedDeviceState powermgt;
+    BCM2835PowerMgtState powermgt;
     BCM2835CprmanState cprman;
     PL011State uart0;
     BCM2835AuxState aux;
diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/bcm2835_powermgt.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * BCM2835 Power Management emulation
+ *
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef BCM2835_POWERMGT_H
+#define BCM2835_POWERMGT_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
+
+struct BCM2835PowerMgtState {
+    SysBusDevice busdev;
+    MemoryRegion iomem;
+
+    uint32_t rstc;
+    uint32_t rsts;
+    uint32_t wdog;
+};
+
+#endif
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2835_peripherals.c
+++ b/hw/arm/bcm2835_peripherals.c
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
 
     object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
                                    OBJECT(&s->gpu_bus_mr));
+
+    /* Power Management */
+    object_initialize_child(obj, "powermgt", &s->powermgt,
+                            TYPE_BCM2835_POWERMGT);
 }
 
 static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
         qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
                                INTERRUPT_USB));
 
+    /* Power Management */
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
+        return;
+    }
+
+    memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
+                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
+
     create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
     create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
-    create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
     create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
     create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
     create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/bcm2835_powermgt.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * BCM2835 Power Management emulation
+ *
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/misc/bcm2835_powermgt.h"
+#include "migration/vmstate.h"
+#include "sysemu/runstate.h"
+
+#define PASSWORD 0x5a000000
+#define PASSWORD_MASK 0xff000000
+
+#define R_RSTC 0x1c
+#define V_RSTC_RESET 0x20
+#define R_RSTS 0x20
+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
+#define R_WDOG 0x24
+
+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
+                                      unsigned size)
+{
+    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
+    uint32_t res = 0;
+
+    switch (offset) {
+    case R_RSTC:
+        res = s->rstc;
+        break;
+    case R_RSTS:
+        res = s->rsts;
+        break;
+    case R_WDOG:
+        res = s->wdog;
+        break;
+
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
+                      "\n", offset);
+        res = 0;
+        break;
+    }
+
+    return res;
+}
+
+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
+                                   uint64_t value, unsigned size)
+{
+    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
+
+    if ((value & PASSWORD_MASK) != PASSWORD) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "bcm2835_powermgt_write: Bad password 0x%"PRIx64
+                      " at offset 0x%08"HWADDR_PRIx"\n",
+                      value, offset);
+        return;
+    }
+
+    value = value & ~PASSWORD_MASK;
+
+    switch (offset) {
+    case R_RSTC:
+        s->rstc = value;
+        if (value & V_RSTC_RESET) {
+            if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
+                qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+            } else {
+                qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+            }
+        }
+        break;
+    case R_RSTS:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_write: RSTS\n");
+        s->rsts = value;
+        break;
+    case R_WDOG:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_write: WDOG\n");
+        s->wdog = value;
+        break;
+
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
+                      "\n", offset);
+        break;
+    }
+}
+
+static const MemoryRegionOps bcm2835_powermgt_ops = {
+    .read = bcm2835_powermgt_read,
+    .write = bcm2835_powermgt_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static const VMStateDescription vmstate_bcm2835_powermgt = {
+    .name = TYPE_BCM2835_POWERMGT,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
+        VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
+        VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void bcm2835_powermgt_init(Object *obj)
+{
+    BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
+
+    memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
+                          TYPE_BCM2835_POWERMGT, 0x200);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+}
+
+static void bcm2835_powermgt_reset(DeviceState *dev)
+{
+    BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
+
+    /* https://elinux.org/BCM2835_registers#PM */
+    s->rstc = 0x00000102;
+    s->rsts = 0x00001000;
+    s->wdog = 0x00000000;
+}
+
+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = bcm2835_powermgt_reset;
+    dc->vmsd = &vmstate_bcm2835_powermgt;
+}
+
+static TypeInfo bcm2835_powermgt_info = {
+    .name          = TYPE_BCM2835_POWERMGT,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(BCM2835PowerMgtState),
+    .class_init    = bcm2835_powermgt_class_init,
+    .instance_init = bcm2835_powermgt_init,
+};
+
+static void bcm2835_powermgt_register_types(void)
+{
+    type_register_static(&bcm2835_powermgt_info);
+}
+
+type_init(bcm2835_powermgt_register_types)
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
   'bcm2835_rng.c',
   'bcm2835_thermal.c',
   'bcm2835_cprman.c',
+  'bcm2835_powermgt.c',
 ))
 softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
 softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Add a test booting and quickly shutdown a raspi2 machine,
to test the power management model:

(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
  console: [    0.000000] Booting Linux on physical CPU 0xf00
  console: [    0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
  console: [    0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
  console: [    0.000000] CPU: div instructions available: patching division code
  console: [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
  console: [    0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
  ...
  console: Boot successful.
  console: cat /proc/cpuinfo
  console: / # cat /proc/cpuinfo
  ...
  console: processor      : 3
  console: model name     : ARMv7 Processor rev 5 (v7l)
  console: BogoMIPS       : 125.00
  console: Features       : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
  console: CPU implementer        : 0x41
  console: CPU architecture: 7
  console: CPU variant    : 0x0
  console: CPU part       : 0xc07
  console: CPU revision   : 5
  console: Hardware       : BCM2835
  console: Revision       : 0000
  console: Serial         : 0000000000000000
  console: cat /proc/iomem
  console: / # cat /proc/iomem
  console: 00000000-3bffffff : System RAM
  console: 00008000-00afffff : Kernel code
  console: 00c00000-00d468ef : Kernel data
  console: 3f006000-3f006fff : dwc_otg
  console: 3f007000-3f007eff : /soc/dma@7e007000
  console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
  console: 3f100000-3f100027 : /soc/watchdog@7e100000
  console: 3f101000-3f102fff : /soc/cprman@7e101000
  console: 3f200000-3f2000b3 : /soc/gpio@7e200000
  PASS (24.59 s)
  RESULTS    : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
  JOB TIME   : 25.02 s

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@
 from avocado import skip
 from avocado import skipUnless
 from avocado_qemu import Test
+from avocado_qemu import exec_command
 from avocado_qemu import exec_command_and_wait_for_pattern
 from avocado_qemu import interrupt_interactive_console_until_pattern
 from avocado_qemu import wait_for_console_pattern
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
         """
         self.do_test_arm_raspi2(0)
 
+    def test_arm_raspi2_initrd(self):
+        """
+        :avocado: tags=arch:arm
+        :avocado: tags=machine:raspi2
+        """
+        deb_url = ('http://archive.raspberrypi.org/debian/'
+                   'pool/main/r/raspberrypi-firmware/'
+                   'raspberrypi-kernel_1.20190215-1_armhf.deb')
+        deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
+        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
+        kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
+        dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
+
+        initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
+                      '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
+                      'arm/rootfs-armv7a.cpio.gz')
+        initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
+        initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
+        initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
+        archive.gzip_uncompress(initrd_path_gz, initrd_path)
+
+        self.vm.set_console()
+        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
+                               'earlycon=pl011,0x3f201000 console=ttyAMA0 '
+                               'panic=-1 noreboot ' +
+                               'dwc_otg.fiq_fsm_enable=0')
+        self.vm.add_args('-kernel', kernel_path,
+                         '-dtb', dtb_path,
+                         '-initrd', initrd_path,
+                         '-append', kernel_command_line,
+                         '-no-reboot')
+        self.vm.launch()
+        self.wait_for_console_pattern('Boot successful.')
+
+        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
+                                                'BCM2835')
+        exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
+                                                '/soc/cprman@7e101000')
+        exec_command(self, 'halt')
+        # Wait for VM to shut down gracefully
+        self.vm.wait()
+
     def test_arm_exynos4210_initrd(self):
         """
         :avocado: tags=arch:arm
-- 
2.20.1

From: Joe Komlodi <joe.komlodi@xilinx.com>

If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
assert due to fpst->default_nan_mode being set.

To avoid this, we check to see what NaN mode we're running in before we call
floatxx_silence_nan().

Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.c | 12 +++++++++---
 target/arm/vfp_helper.c | 24 ++++++++++++++++++------
 2 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
         float16 nan = a;
         if (float16_is_signaling_nan(a, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float16_silence_nan(a, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float16_silence_nan(a, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan = float16_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
         float32 nan = a;
         if (float32_is_signaling_nan(a, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float32_silence_nan(a, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float32_silence_nan(a, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan = float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
         float64 nan = a;
         if (float64_is_signaling_nan(a, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float64_silence_nan(a, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float64_silence_nan(a, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan = float64_default_nan(fpst);
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
         float16 nan = f16;
         if (float16_is_signaling_nan(f16, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float16_silence_nan(f16, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float16_silence_nan(f16, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan =  float16_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
         float32 nan = f32;
         if (float32_is_signaling_nan(f32, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float32_silence_nan(f32, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float32_silence_nan(f32, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan =  float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
         float64 nan = f64;
         if (float64_is_signaling_nan(f64, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float64_silence_nan(f64, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float64_silence_nan(f64, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan =  float64_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
         float16 nan = f16;
         if (float16_is_signaling_nan(f16, s)) {
             float_raise(float_flag_invalid, s);
-            nan = float16_silence_nan(f16, s);
+            if (!s->default_nan_mode) {
+                nan = float16_silence_nan(f16, fpstp);
+            }
         }
         if (s->default_nan_mode) {
             nan =  float16_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
         float32 nan = f32;
         if (float32_is_signaling_nan(f32, s)) {
             float_raise(float_flag_invalid, s);
-            nan = float32_silence_nan(f32, s);
+            if (!s->default_nan_mode) {
+                nan = float32_silence_nan(f32, fpstp);
+            }
         }
         if (s->default_nan_mode) {
             nan =  float32_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
         float64 nan = f64;
         if (float64_is_signaling_nan(f64, s)) {
             float_raise(float_flag_invalid, s);
-            nan = float64_silence_nan(f64, s);
+            if (!s->default_nan_mode) {
+                nan = float64_silence_nan(f64, fpstp);
+            }
         }
         if (s->default_nan_mode) {
             nan =  float64_default_nan(s);
-- 
2.20.1

From: Maxim Uvarov <maxim.uvarov@linaro.org>

qemu has 2 type of functions: shutdown and reboot. Shutdown
function has to be used for machine shutdown. Otherwise we cause
a reset with a bogus "cause" value, when we intended a shutdown.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
[PMM: tweaked commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/gpio/gpio_pwr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/gpio_pwr.c
+++ b/hw/gpio/gpio_pwr.c
@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
 static void gpio_pwr_shutdown(void *opaque, int n, int level)
 {
     if (level) {
-        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
     }
 }
 
-- 
2.20.1

In do_ldst(), the calculation of the offset needs to be based on the
size of the memory access, not the size of the elements in the
vector.  This meant we were getting it wrong for the widening and
narrowing variants of the various VLDR and VSTR insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
---
 target/arm/translate-mve.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
     }
 }
 
-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
+                    unsigned msize)
 {
     TCGv_i32 addr;
     uint32_t offset;
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
         return true;
     }
 
-    offset = a->imm << a->size;
+    offset = a->imm << msize;
     if (!a->a) {
         offset = -offset;
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
         { gen_helper_mve_vstrw, gen_helper_mve_vldrw },
         { NULL, NULL }
     };
-    return do_ldst(s, a, ldstfns[a->size][a->l]);
+    return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
 }
 
-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST)                  \
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE)           \
     static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a)   \
     {                                                           \
         static MVEGenLdStFn * const ldstfns[2][2] = {           \
             { gen_helper_mve_##ST, gen_helper_mve_##SLD },      \
             { NULL, gen_helper_mve_##ULD },                     \
         };                                                      \
-        return do_ldst(s, a, ldstfns[a->u][a->l]);              \
+        return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE);       \
     }
 
-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
 
 static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
 {
-- 
2.20.1

The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
insns had some bugs:
 * the 32x32 multiply of elements was being done as 32x32->32,
   not 32x32->64
 * we were incorrectly maintaining the accumulator in its full
   72-bit form across all 4 beats of the insn; in the pseudocode
   it is squashed back into the 64 bits of the RdaHi:RdaLo
   registers after each beat

In particular, fixing the second of these allows us to recast
the implementation to avoid 128-bit arithmetic entirely.

Since the element size here is always 4, we can also drop the
parameterization of ESIZE to make the code a little more readable.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
---
 target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
 1 file changed, 21 insertions(+), 17 deletions(-)

diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
-#include "qemu/int128.h"
 #include "cpu.h"
 #include "internals.h"
 #include "vec_internal.h"
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
 
 /*
- * Rounding multiply add long dual accumulate high: we must keep
- * a 72-bit internal accumulator value and return the top 64 bits.
+ * Rounding multiply add long dual accumulate high. In the pseudocode
+ * this is implemented with a 72-bit internal accumulator value of which
+ * the top 64 bits are returned. We optimize this to avoid having to
+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
+ * is squashed back into 64-bits after each beat.
  */
-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128)         \
+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB)                            \
     uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn,         \
                                     void *vm, uint64_t a)               \
     {                                                                   \
         uint16_t mask = mve_element_mask(env);                          \
         unsigned e;                                                     \
         TYPE *n = vn, *m = vm;                                          \
-        Int128 acc = int128_lshift(TO128(a), 8);                        \
-        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {              \
+        for (e = 0; e < 16 / 4; e++, mask >>= 4) {                      \
             if (mask & 1) {                                             \
+                LTYPE mul;                                              \
                 if (e & 1) {                                            \
-                    acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
-                                            m[H##ESIZE(e)]));           \
+                    mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)];        \
+                    if (SUB) {                                          \
+                        mul = -mul;                                     \
+                    }                                                   \
                 } else {                                                \
-                    acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
-                                             m[H##ESIZE(e)]));          \
+                    mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)];        \
                 }                                                       \
-                acc = int128_add(acc, int128_make64(1 << 7));           \
+                mul = (mul >> 8) + ((mul >> 7) & 1);                    \
+                a += mul;                                               \
             }                                                           \
         }                                                               \
         mve_advance_vpt(env);                                           \
-        return int128_getlo(int128_rshift(acc, 8));                     \
+        return a;                                                       \
     }
 
-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
 
-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
 
-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
 
 /* Vector add across vector */
 #define DO_VADDV(OP, ESIZE, TYPE)                               \
-- 
2.20.1

The function asimd_imm_const() in translate-neon.c is an
implementation of the pseudocode AdvSIMDExpandImm(), which we will
also want for MVE.  Move the implementation to translate.c, with a
prototype in translate.h.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
---
 target/arm/translate.h      | 16 ++++++++++
 target/arm/translate-neon.c | 63 -------------------------------------
 target/arm/translate.c      | 57 +++++++++++++++++++++++++++++++++
 3 files changed, 73 insertions(+), 63 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
     return opc | s->be_data;
 }
 
+/**
+ * asimd_imm_const: Expand an encoded SIMD constant value
+ *
+ * Expand a SIMD constant value. This is essentially the pseudocode
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
+ * VMVN and VBIC (when cmode < 14 && op == 1).
+ *
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
+ * callers must catch this.
+ *
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
+ * we produce an immediate constant value of 0 in these cases.
+ */
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
+
 #endif /* TARGET_ARM_TRANSLATE_H */
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
 DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
 DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
 
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
-{
-    /*
-     * Expand the encoded constant.
-     * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
-     * We choose to not special-case this and will behave as if a
-     * valid constant encoding of 0 had been given.
-     * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
-     */
-    switch (cmode) {
-    case 0: case 1:
-        /* no-op */
-        break;
-    case 2: case 3:
-        imm <<= 8;
-        break;
-    case 4: case 5:
-        imm <<= 16;
-        break;
-    case 6: case 7:
-        imm <<= 24;
-        break;
-    case 8: case 9:
-        imm |= imm << 16;
-        break;
-    case 10: case 11:
-        imm = (imm << 8) | (imm << 24);
-        break;
-    case 12:
-        imm = (imm << 8) | 0xff;
-        break;
-    case 13:
-        imm = (imm << 16) | 0xffff;
-        break;
-    case 14:
-        if (op) {
-            /*
-             * This is the only case where the top and bottom 32 bits
-             * of the encoded constant differ.
-             */
-            uint64_t imm64 = 0;
-            int n;
-
-            for (n = 0; n < 8; n++) {
-                if (imm & (1 << n)) {
-                    imm64 |= (0xffULL << (n * 8));
-                }
-            }
-            return imm64;
-        }
-        imm |= (imm << 8) | (imm << 16) | (imm << 24);
-        break;
-    case 15:
-        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
-            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
-        break;
-    }
-    if (op) {
-        imm = ~imm;
-    }
-    return dup_const(MO_32, imm);
-}
-
 static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
                         GVecGen2iFn *fn)
 {
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
     a64_translate_init();
 }
 
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
+{
+    /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
+    switch (cmode) {
+    case 0: case 1:
+        /* no-op */
+        break;
+    case 2: case 3:
+        imm <<= 8;
+        break;
+    case 4: case 5:
+        imm <<= 16;
+        break;
+    case 6: case 7:
+        imm <<= 24;
+        break;
+    case 8: case 9:
+        imm |= imm << 16;
+        break;
+    case 10: case 11:
+        imm = (imm << 8) | (imm << 24);
+        break;
+    case 12:
+        imm = (imm << 8) | 0xff;
+        break;
+    case 13:
+        imm = (imm << 16) | 0xffff;
+        break;
+    case 14:
+        if (op) {
+            /*
+             * This is the only case where the top and bottom 32 bits
+             * of the encoded constant differ.
+             */
+            uint64_t imm64 = 0;
+            int n;
+
+            for (n = 0; n < 8; n++) {
+                if (imm & (1 << n)) {
+                    imm64 |= (0xffULL << (n * 8));
+                }
+            }
+            return imm64;
+        }
+        imm |= (imm << 8) | (imm << 16) | (imm << 24);
+        break;
+    case 15:
+        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
+            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
+        break;
+    }
+    if (op) {
+        imm = ~imm;
+    }
+    return dup_const(MO_32, imm);
+}
+
 /* Generate a label used for skipping this instruction */
 void arm_gen_condlabel(DisasContext *s)
 {
-- 
2.20.1

The A64 AdvSIMD modified-immediate grouping uses almost the same
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
which we add the AArch64-specific case for cmode 15 op 1) instead of
reimplementing it all.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
---
 target/arm/translate.h     |  3 +-
 target/arm/translate-a64.c | 86 ++++----------------------------------
 target/arm/translate.c     | 17 +++++++-
 3 files changed, 24 insertions(+), 82 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
  * VMVN and VBIC (when cmode < 14 && op == 1).
  *
  * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
- * callers must catch this.
+ * callers must catch this; we return the 64-bit constant value defined
+ * for AArch64.
  *
  * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
  * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
 {
     int rd = extract32(insn, 0, 5);
     int cmode = extract32(insn, 12, 4);
-    int cmode_3_1 = extract32(cmode, 1, 3);
-    int cmode_0 = extract32(cmode, 0, 1);
     int o2 = extract32(insn, 11, 1);
     uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
     bool is_neg = extract32(insn, 29, 1);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
         return;
     }
 
-    /* See AdvSIMDExpandImm() in ARM ARM */
-    switch (cmode_3_1) {
-    case 0: /* Replicate(Zeros(24):imm8, 2) */
-    case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
-    case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
-    case 3: /* Replicate(imm8:Zeros(24), 2) */
-    {
-        int shift = cmode_3_1 * 8;
-        imm = bitfield_replicate(abcdefgh << shift, 32);
-        break;
-    }
-    case 4: /* Replicate(Zeros(8):imm8, 4) */
-    case 5: /* Replicate(imm8:Zeros(8), 4) */
-    {
-        int shift = (cmode_3_1 & 0x1) * 8;
-        imm = bitfield_replicate(abcdefgh << shift, 16);
-        break;
-    }
-    case 6:
-        if (cmode_0) {
-            /* Replicate(Zeros(8):imm8:Ones(16), 2) */
-            imm = (abcdefgh << 16) | 0xffff;
-        } else {
-            /* Replicate(Zeros(16):imm8:Ones(8), 2) */
-            imm = (abcdefgh << 8) | 0xff;
-        }
-        imm = bitfield_replicate(imm, 32);
-        break;
-    case 7:
-        if (!cmode_0 && !is_neg) {
-            imm = bitfield_replicate(abcdefgh, 8);
-        } else if (!cmode_0 && is_neg) {
-            int i;
-            imm = 0;
-            for (i = 0; i < 8; i++) {
-                if ((abcdefgh) & (1 << i)) {
-                    imm |= 0xffULL << (i * 8);
-                }
-            }
-        } else if (cmode_0) {
-            if (is_neg) {
-                imm = (abcdefgh & 0x3f) << 48;
-                if (abcdefgh & 0x80) {
-                    imm |= 0x8000000000000000ULL;
-                }
-                if (abcdefgh & 0x40) {
-                    imm |= 0x3fc0000000000000ULL;
-                } else {
-                    imm |= 0x4000000000000000ULL;
-                }
-            } else {
-                if (o2) {
-                    /* FMOV (vector, immediate) - half-precision */
-                    imm = vfp_expand_imm(MO_16, abcdefgh);
-                    /* now duplicate across the lanes */
-                    imm = bitfield_replicate(imm, 16);
-                } else {
-                    imm = (abcdefgh & 0x3f) << 19;
-                    if (abcdefgh & 0x80) {
-                        imm |= 0x80000000;
-                    }
-                    if (abcdefgh & 0x40) {
-                        imm |= 0x3e000000;
-                    } else {
-                        imm |= 0x40000000;
-                    }
-                    imm |= (imm << 32);
-                }
-            }
-        }
-        break;
-    default:
-        g_assert_not_reached();
-    }
-
-    if (cmode_3_1 != 7 && is_neg) {
-        imm = ~imm;
+    if (cmode == 15 && o2 && !is_neg) {
+        /* FMOV (vector, immediate) - half-precision */
+        imm = vfp_expand_imm(MO_16, abcdefgh);
+        /* now duplicate across the lanes */
+        imm = bitfield_replicate(imm, 16);
+    } else {
+        imm = asimd_imm_const(abcdefgh, cmode, is_neg);
     }
 
     if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
     case 14:
         if (op) {
             /*
-             * This is the only case where the top and bottom 32 bits
-             * of the encoded constant differ.
+             * This and cmode == 15 op == 1 are the only cases where
+             * the top and bottom 32 bits of the encoded constant differ.
              */
             uint64_t imm64 = 0;
             int n;
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
         imm |= (imm << 8) | (imm << 16) | (imm << 24);
         break;
     case 15:
+        if (op) {
+            /* Reserved encoding for AArch32; valid for AArch64 */
+            uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
+            if (imm & 0x80) {
+                imm64 |= 0x8000000000000000ULL;
+            }
+            if (imm & 0x40) {
+                imm64 |= 0x3fc0000000000000ULL;
+            } else {
+                imm64 |= 0x4000000000000000ULL;
+            }
+            return imm64;
+        }
         imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
             | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
         break;
-- 
2.20.1

Use dup_const() instead of bitfield_replicate() in
disas_simd_mod_imm().

(We can't replace the other use of bitfield_replicate() in this file,
in logic_imm_decode_wmask(), because that location needs to handle 2
and 4 bit elements, which dup_const() cannot.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
---
 target/arm/translate-a64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
         /* FMOV (vector, immediate) - half-precision */
         imm = vfp_expand_imm(MO_16, abcdefgh);
         /* now duplicate across the lanes */
-        imm = bitfield_replicate(imm, 16);
+        imm = dup_const(MO_16, imm);
     } else {
         imm = asimd_imm_const(abcdefgh, cmode, is_neg);
     }
-- 
2.20.1

Implement the MVE logical-immediate insns (VMOV, VMVN,
VORR and VBIC). These have essentially the same encoding
as their Neon equivalents, and we implement the decode
in the same way.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  4 +++
 target/arm/mve.decode      | 17 +++++++++++++
 target/arm/mve_helper.c    | 24 ++++++++++++++++++
 target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 95 insertions(+)

Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
and VQSHLU.

The size-and-immediate encoding here is the same as Neon, and we
handle it the same way neon-dp.decode does.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    | 16 +++++++++++
 target/arm/mve.decode      | 23 +++++++++++++++
 target/arm/mve_helper.c    | 57 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
 4 files changed, 147 insertions(+)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
 DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
 DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
 DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
+
+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
 &2op qd qm qn size
 &2scalar qd qn rm size
 &1imm qd imm cmode op
+&2shift qd qm shift size
 
 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
 # Note that both Rn and Qd are 3 bits only (no D bit)
@@ -XXX,XX +XXX,XX @@
 @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
 @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
 
+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
+@2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
+@2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
+
 # Vector loads and stores
 
 # Widening loads and narrowing stores:
@@ -XXX,XX +XXX,XX @@ VPST             1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
 # So we have a single decode line and check the cmode/op in the
 # trans function.
 Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
+
+# Shifts by immediate
+
+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
+
+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
+
+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
+
+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
     WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
 #define DO_UQRSHL_OP(N, M, satp) \
     WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
+#define DO_SUQSHL_OP(N, M, satp) \
+    WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
 
 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
 DO_VADDV(vaddvub, 1, uint8_t)
 DO_VADDV(vaddvuh, 2, uint16_t)
 DO_VADDV(vaddvuw, 4, uint32_t)
+
+/* Shifts by immediate */
+#define DO_2SHIFT(OP, ESIZE, TYPE, FN)                          \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+                                void *vm, uint32_t shift)       \
+    {                                                           \
+        TYPE *d = vd, *m = vm;                                  \
+        uint16_t mask = mve_element_mask(env);                  \
+        unsigned e;                                             \
+        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
+            mergemask(&d[H##ESIZE(e)],                          \
+                      FN(m[H##ESIZE(e)], shift), mask);         \
+        }                                                       \
+        mve_advance_vpt(env);                                   \
+    }
+
+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN)                      \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+                                void *vm, uint32_t shift)       \
+    {                                                           \
+        TYPE *d = vd, *m = vm;                                  \
+        uint16_t mask = mve_element_mask(env);                  \
+        unsigned e;                                             \
+        bool qc = false;                                        \
+        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
+            bool sat = false;                                   \
+            mergemask(&d[H##ESIZE(e)],                          \
+                      FN(m[H##ESIZE(e)], shift, &sat), mask);   \
+            qc |= sat & mask & 1;                               \
+        }                                                       \
+        if (qc) {                                               \
+            env->vfp.qc[0] = qc;                                \
+        }                                                       \
+        mve_advance_vpt(env);                                   \
+    }
+
+/* provide unsigned 2-op shift helpers for all sizes */
+#define DO_2SHIFT_U(OP, FN)                     \
+    DO_2SHIFT(OP##b, 1, uint8_t, FN)            \
+    DO_2SHIFT(OP##h, 2, uint16_t, FN)           \
+    DO_2SHIFT(OP##w, 4, uint32_t, FN)
+
+#define DO_2SHIFT_SAT_U(OP, FN)                 \
+    DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN)        \
+    DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN)       \
+    DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
+#define DO_2SHIFT_SAT_S(OP, FN)                 \
+    DO_2SHIFT_SAT(OP##b, 1, int8_t, FN)         \
+    DO_2SHIFT_SAT(OP##h, 2, int16_t, FN)        \
+    DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
+
+DO_2SHIFT_U(vshli_u, DO_VSHLU)
+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
 typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
 typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
 typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
     }
     return do_1imm(s, a, fn);
 }
+
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
+                      bool negateshift)
+{
+    TCGv_ptr qd, qm;
+    int shift = a->shift;
+
+    if (!dc_isar_feature(aa32_mve, s) ||
+        !mve_check_qreg_bank(s, a->qd | a->qm) ||
+        !fn) {
+        return false;
+    }
+    if (!mve_eci_check(s) || !vfp_access_check(s)) {
+        return true;
+    }
+
+    /*
+     * When we handle a right shift insn using a left-shift helper
+     * which permits a negative shift count to indicate a right-shift,
+     * we must negate the shift count.
+     */
+    if (negateshift) {
+        shift = -shift;
+    }
+
+    qd = mve_qreg_ptr(a->qd);
+    qm = mve_qreg_ptr(a->qm);
+    fn(cpu_env, qd, qm, tcg_constant_i32(shift));
+    tcg_temp_free_ptr(qd);
+    tcg_temp_free_ptr(qm);
+    mve_update_eci(s);
+    return true;
+}
+
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT)                         \
+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
+    {                                                           \
+        static MVEGenTwoOpShiftFn * const fns[] = {             \
+            gen_helper_mve_##FN##b,                             \
+            gen_helper_mve_##FN##h,                             \
+            gen_helper_mve_##FN##w,                             \
+            NULL,                                               \
+        };                                                      \
+        return do_2shift(s, a, fns[a->size], NEGATESHIFT);      \
+    }
+
+DO_2SHIFT(VSHLI, vshli_u, false)
+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
-- 
2.20.1

Implement the MVE vector shift right by immediate insns VSHRI and
VRSHRI.  As with Neon, we implement these by using helper functions
which perform left shifts but allow negative shift counts to indicate
right shifts.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
---
 target/arm/helper-mve.h     | 12 ++++++++++++
 target/arm/translate.h      | 20 ++++++++++++++++++++
 target/arm/mve.decode       | 28 ++++++++++++++++++++++++++++
 target/arm/mve_helper.c     |  7 +++++++
 target/arm/translate-mve.c  |  5 +++++
 target/arm/translate-neon.c | 18 ------------------
 6 files changed, 72 insertions(+), 18 deletions(-)

Implement the MVE VHLL (vector shift left long) insn.  This has two
encodings: the T1 encoding is the usual shift-by-immediate format,
and the T2 encoding is a special case where the shift count is always
equal to the element size.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  9 +++++++
 target/arm/mve.decode      | 53 +++++++++++++++++++++++++++++++++++---
 target/arm/mve_helper.c    | 32 +++++++++++++++++++++++
 target/arm/translate-mve.c | 15 +++++++++++
 4 files changed, 105 insertions(+), 4 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
 @2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
 @2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
 
+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
+@2_shll_h .... .... ... 1  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
+# VSHLL encoding T2 where shift == esize
+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
+                qd=%qd qm=%qm size=0 shift=8
+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
+                qd=%qd qm=%qm size=1 shift=16
+
 # Right shifts are encoded as N - shift, where N is the element size in bits.
 %rshift_i5  16:5 !function=rsub_32
 %rshift_i4  16:4 !function=rsub_16
@@ -XXX,XX +XXX,XX @@ VADD             1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
 VSUB             1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
 VMUL             1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
 
-VMULH_S          111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
-VMULH_U          111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
+# overlaps what would be size=0b11 VMULH/VRMULH
+{
+  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
 
-VRMULH_S         111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
-VRMULH_U         111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+  VMULH_S        111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+}
+
+{
+  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
+
+  VMULH_U        111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+}
+
+{
+  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
+
+  VRMULH_S       111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+}
+
+{
+  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
+
+  VRMULH_U       111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+}
 
 VMAX_S           111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
 VMAX_U           111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
@@ -XXX,XX +XXX,XX @@ VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
 VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
 VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
+
+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
+VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
+
+VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
+
+VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
+
+VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
 DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
 DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
 DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
+
+/*
+ * Long shifts taking half-sized inputs from top or bottom of the input
+ * vector and producing a double-width result. ESIZE, TYPE are for
+ * the input, and LESIZE, LTYPE for the output.
+ * Unlike the normal shift helpers, we do not handle negative shift counts,
+ * because the long shift is strictly left-only.
+ */
+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE)                   \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,             \
+                                void *vm, uint32_t shift)               \
+    {                                                                   \
+        LTYPE *d = vd;                                                  \
+        TYPE *m = vm;                                                   \
+        uint16_t mask = mve_element_mask(env);                          \
+        unsigned le;                                                    \
+        assert(shift <= 16);                                            \
+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) {         \
+            LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift;        \
+            mergemask(&d[H##LESIZE(le)], r, mask);                      \
+        }                                                               \
+        mve_advance_vpt(env);                                           \
+    }
+
+#define DO_VSHLL_ALL(OP, TOP)                                \
+    DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t)             \
+    DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t)           \
+    DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t)            \
+    DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t)          \
+
+DO_VSHLL_ALL(vshllb, false)
+DO_VSHLL_ALL(vshllt, true)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
 DO_2SHIFT(VSHRI_U, vshli_u, true)
 DO_2SHIFT(VRSHRI_S, vrshli_s, true)
 DO_2SHIFT(VRSHRI_U, vrshli_u, true)
+
+#define DO_VSHLL(INSN, FN)                                      \
+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
+    {                                                           \
+        static MVEGenTwoOpShiftFn * const fns[] = {             \
+            gen_helper_mve_##FN##b,                             \
+            gen_helper_mve_##FN##h,                             \
+        };                                                      \
+        return do_2shift(s, a, fns[a->size], false);            \
+    }
+
+DO_VSHLL(VSHLL_BS, vshllbs)
+DO_VSHLL(VSHLL_BU, vshllbu)
+DO_VSHLL(VSHLL_TS, vshllts)
+DO_VSHLL(VSHLL_TU, vshlltu)
-- 
2.20.1

Implement the MVE VSRI and VSLI insns, which perform a
shift-and-insert operation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  8 ++++++++
 target/arm/mve.decode      |  9 ++++++++
 target/arm/mve_helper.c    | 42 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c |  3 +++
 4 files changed, 62 insertions(+)

Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.

do_urshr() is borrowed from sve_helper.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    | 10 ++++++++++
 target/arm/mve.decode      | 11 +++++++++++
 target/arm/mve_helper.c    | 40 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c | 15 ++++++++++++++
 4 files changed, 76 insertions(+)

Implement the MVE saturating shift-right-and-narrow insns
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.

do_srshr() is borrowed from sve_helper.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  30 +++++++++++
 target/arm/mve.decode      |  28 ++++++++++
 target/arm/mve_helper.c    | 104 +++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c |  12 +++++
 4 files changed, 174 insertions(+)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
 VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
 VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
 VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
+
+VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
+VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
+VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
+VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
+
+VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
+VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
+VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
+VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
+
+VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
+VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
+VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
+VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
+
+VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
+VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
+VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
+VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
     }
 }
 
+static inline int64_t do_srshr(int64_t x, unsigned sh)
+{
+    if (likely(sh < 64)) {
+        return (x >> sh) + ((x >> (sh - 1)) & 1);
+    } else {
+        /* Rounding the sign bit always produces 0. */
+        return 0;
+    }
+}
+
 DO_VSHRN_ALL(vshrn, DO_SHR)
 DO_VSHRN_ALL(vrshrn, do_urshr)
+
+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
+                                 bool *satp)
+{
+    if (val > max) {
+        *satp = true;
+        return max;
+    } else if (val < min) {
+        *satp = true;
+        return min;
+    } else {
+        return val;
+    }
+}
+
+/* Saturating narrowing right shifts */
+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)   \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+                                void *vm, uint32_t shift)       \
+    {                                                           \
+        LTYPE *m = vm;                                          \
+        TYPE *d = vd;                                           \
+        uint16_t mask = mve_element_mask(env);                  \
+        bool qc = false;                                        \
+        unsigned le;                                            \
+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
+            bool sat = false;                                   \
+            TYPE r = FN(m[H##LESIZE(le)], shift, &sat);         \
+            mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask);     \
+            qc |= sat && (mask & 1 << (TOP * ESIZE));           \
+        }                                                       \
+        if (qc) {                                               \
+            env->vfp.qc[0] = qc;                                \
+        }                                                       \
+        mve_advance_vpt(env);                                   \
+    }
+
+#define DO_VSHRN_SAT_UB(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN)       \
+    DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
+
+#define DO_VSHRN_SAT_UH(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN)      \
+    DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
+
+#define DO_VSHRN_SAT_SB(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN)         \
+    DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
+
+#define DO_VSHRN_SAT_SH(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN)        \
+    DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
+
+#define DO_SHRN_SB(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
+#define DO_SHRN_UB(N, M, SATP)                                  \
+    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
+#define DO_SHRUN_B(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
+
+#define DO_SHRN_SH(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
+#define DO_SHRN_UH(N, M, SATP)                                  \
+    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
+#define DO_SHRUN_H(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
+
+#define DO_RSHRN_SB(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
+#define DO_RSHRN_UB(N, M, SATP)                                 \
+    do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
+#define DO_RSHRUN_B(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
+
+#define DO_RSHRN_SH(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
+#define DO_RSHRN_UH(N, M, SATP)                                 \
+    do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
+#define DO_RSHRUN_H(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
+
+DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
+DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
+DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
+DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
+DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
+DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
+
+DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
+DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
+DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
+DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
+DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
+DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
 DO_2SHIFT_N(VSHRNT, vshrnt)
 DO_2SHIFT_N(VRSHRNB, vrshrnb)
 DO_2SHIFT_N(VRSHRNT, vrshrnt)
+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
+DO_2SHIFT_N(VQSHRUNT, vqshrunt)
+DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
+DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
+DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
+DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
+DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
+DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
-- 
2.20.1

Implement the MVE VSHLC insn, which performs a shift left of the
entire vector with carry in bits provided from a general purpose
register and carry out bits written back to that register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  2 ++
 target/arm/mve.decode      |  2 ++
 target/arm/mve_helper.c    | 38 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
 4 files changed, 72 insertions(+)

Implement the MVE VADDLV insn; this is similar to VADDV, except
that it accumulates 32-bit elements into a 64-bit accumulator
stored in a pair of general-purpose registers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  3 ++
 target/arm/mve.decode      |  6 +++-
 target/arm/mve_helper.c    | 19 ++++++++++++
 target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 90 insertions(+), 1 deletion(-)

The MVE extension to v8.1M includes some new shift instructions which
sit entirely within the non-coprocessor part of the encoding space
and which operate only on general-purpose registers.  They take up
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
with Rm == 13 or 15.

Implement the long shifts by immediate, which perform shifts on a
pair of general-purpose registers treated as a 64-bit quantity, with
an immediate shift count between 1 and 32.

Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
cases where v8.1M now requires that.  (Trying to change MOVS and ORRS
is too difficult, because the functions that generate the code are
shared between a dozen different kinds of arithmetic or logical
instruction for all A32, T16 and T32 encodings, and for some insns
and some encodings Rm==13,15 are valid.)

We make the helper functions we need for UQSHLL and SQSHLL take
a 32-bit value which the helper casts to int8_t because we'll need
these helpers also for the shift-by-register insns, where the shift
count might be < 0 or > 32.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  3 ++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 28 +++++++++++++
 target/arm/mve_helper.c | 10 +++++
 target/arm/translate.c  | 90 +++++++++++++++++++++++++++++++++++++++++
 5 files changed, 132 insertions(+)

Implement the MVE long shifts by register, which perform shifts on a
pair of general-purpose registers treated as a 64-bit quantity, with
the shift count in another general-purpose register, which might be
either positive or negative.

Like the long-shifts-by-immediate, these encodings sit in the space
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
we have to move the CSEL pattern into the same decodetree group.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  6 +++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 16 +++++--
 target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
 target/arm/translate.c  | 69 ++++++++++++++++++++++++++++++
 5 files changed, 182 insertions(+), 3 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 
 DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
 
+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
 DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
 DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
 typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
 
 /**
  * arm_tbflags_from_tb:
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@
 &mcrr            !extern cp opc1 crm rt rt2
 
 &mve_shl_ri      rdalo rdahi shim
+&mve_shl_rr      rdalo rdahi rm
 
 # rdahi: bits [3:1] from insn, bit 0 is 1
 # rdalo: bits [3:1] from insn, bit 0 is 0
@@ -XXX,XX +XXX,XX @@
 
 @mve_shl_ri      ....... .... . ... . . ... ... . .. .. .... \
                  &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
+@mve_shl_rr      ....... .... . ... . rm:4  ... . .. .. .... \
+                 &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
 
 {
   TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
     URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
     SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
     SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
+
+    LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
+    ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
+    UQRSHLL64_rr 1110101 0010 1 ... 1 ....  ... 1  0000 1101  @mve_shl_rr
+    SQRSHRL64_rr 1110101 0010 1 ... 1 ....  ... 1  0010 1101  @mve_shl_rr
+    UQRSHLL48_rr 1110101 0010 1 ... 1 ....  ... 1  1000 1101  @mve_shl_rr
+    SQRSHRL48_rr 1110101 0010 1 ... 1 ....  ... 1  1010 1101  @mve_shl_rr
   ]
 
   MOV_rxri       1110101 0010 . 1111 0 ... .... .... ....     @s_rxr_shi
   ORR_rrri       1110101 0010 . .... 0 ... .... .... ....     @s_rrr_shi
+
+  # v8.1M CSEL and friends
+  CSEL           1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
 }
 {
   MVN_rxri       1110101 0011 . 1111 0 ... .... .... ....     @s_rxr_shi
@@ -XXX,XX +XXX,XX @@ SBC_rrri         1110101 1011 . .... 0 ... .... .... ....     @s_rrr_shi
 }
 RSB_rrri         1110101 1110 . .... 0 ... .... .... ....     @s_rrr_shi
 
-# v8.1M CSEL and friends
-CSEL             1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
-
 # Data-processing (register-shifted register)
 
 MOV_rxrr         1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
     return rdm;
 }
 
+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
+}
+
+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_uqrshl_d(n, (int8_t)shift, false, NULL);
+}
+
 uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 {
     return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 {
     return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
 }
+
+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
+}
+
+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
+}
+
+/* Operate on 64-bit values, but saturate at 48 bits */
+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
+                                    bool round, uint32_t *sat)
+{
+    if (shift <= -48) {
+        /* Rounding the sign bit always produces 0. */
+        if (round) {
+            return 0;
+        }
+        return src >> 63;
+    } else if (shift < 0) {
+        if (round) {
+            src >>= -shift - 1;
+            return (src >> 1) + (src & 1);
+        }
+        return src >> -shift;
+    } else if (shift < 48) {
+        int64_t val = src << shift;
+        int64_t extval = sextract64(val, 0, 48);
+        if (!sat || val == extval) {
+            return extval;
+        }
+    } else if (!sat || src == 0) {
+        return 0;
+    }
+
+    *sat = 1;
+    return (1ULL << 47) - (src >= 0);
+}
+
+/* Operate on 64-bit values, but saturate at 48 bits */
+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
+                                     bool round, uint32_t *sat)
+{
+    uint64_t val, extval;
+
+    if (shift <= -(48 + round)) {
+        return 0;
+    } else if (shift < 0) {
+        if (round) {
+            val = src >> (-shift - 1);
+            val = (val >> 1) + (val & 1);
+        } else {
+            val = src >> -shift;
+        }
+        extval = extract64(val, 0, 48);
+        if (!sat || val == extval) {
+            return extval;
+        }
+    } else if (shift < 48) {
+        uint64_t val = src << shift;
+        uint64_t extval = extract64(val, 0, 48);
+        if (!sat || val == extval) {
+            return extval;
+        }
+    } else if (!sat || src == 0) {
+        return 0;
+    }
+
+    *sat = 1;
+    return MAKE_64BIT_MASK(0, 48);
+}
+
+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
+}
+
+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
     return do_mve_shl_ri(s, a, gen_urshr64_i64);
 }
 
+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
+{
+    TCGv_i64 rda;
+    TCGv_i32 rdalo, rdahi;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
+        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
+        return false;
+    }
+    if (a->rdahi == 15) {
+        /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
+        return false;
+    }
+    if (!dc_isar_feature(aa32_mve, s) ||
+        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
+        a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
+        a->rm == a->rdahi || a->rm == a->rdalo) {
+        /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
+        unallocated_encoding(s);
+        return true;
+    }
+
+    rda = tcg_temp_new_i64();
+    rdalo = load_reg(s, a->rdalo);
+    rdahi = load_reg(s, a->rdahi);
+    tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
+
+    /* The helper takes care of the sign-extension of the low 8 bits of Rm */
+    fn(rda, cpu_env, rda, cpu_R[a->rm]);
+
+    tcg_gen_extrl_i64_i32(rdalo, rda);
+    tcg_gen_extrh_i64_i32(rdahi, rda);
+    store_reg(s, a->rdalo, rdalo);
+    store_reg(s, a->rdahi, rdahi);
+    tcg_temp_free_i64(rda);
+
+    return true;
+}
+
+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
+}
+
+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
+}
+
+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
+}
+
+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
+}
+
+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
+}
+
+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
+}
+
 /*
  * Multiply and multiply accumulate
  */
-- 
2.20.1

Implement the MVE shifts by immediate, which perform shifts
on a single general-purpose register.

These patterns overlap with the long-shift-by-immediates,
so we have to rearrange the grouping a little here.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  3 ++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 31 ++++++++++++++-----
 target/arm/mve_helper.c | 10 ++++++
 target/arm/translate.c  | 68 +++++++++++++++++++++++++++++++++++++++--
 5 files changed, 104 insertions(+), 9 deletions(-)

Implement the MVE shifts by register, which perform
shifts on a single general-purpose register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  2 ++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 18 ++++++++++++++----
 target/arm/mve_helper.c | 10 ++++++++++
 target/arm/translate.c  | 30 ++++++++++++++++++++++++++++++
 5 files changed, 57 insertions(+), 4 deletions(-)