A grab-bag of minor stuff for the end of the year. My to-review

queue is not empty, but it it at least in single figures...

The following changes since commit 5bfbd8170ce7acb98a1834ff49ed7340b0837144:

Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pull-request' into staging (2020-12-14 20:32:38 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201215

for you to fetch changes up to 23af268566069183285bebbdf95b1b37cb7c0942:

hw/block/m25p80: Fix Numonyx fast read dummy cycle count (2020-12-15 13:39:30 +0000)

* gdbstub: Correct misparsing of vCont C/S requests

* openrisc: Move pic_cpu code into CPU object proper

* nios2: Move IIC code into CPU object proper

* Improve reporting of ROM overlap errors

* xlnx-versal: Add USB support

* hw/misc/zynq_slcr: Avoid #DIV/0! error

* Numonyx: Fix dummy cycles and check for SPI mode on cmds

Joe Komlodi (4):

hw/block/m25p80: Make Numonyx config field names more accurate

hw/block/m25p80: Fix when VCFG XIP bit is set for Numonyx

hw/block/m25p80: Check SPI mode before running some Numonyx commands

hw/block/m25p80: Fix Numonyx fast read dummy cycle count

Peter Maydell (11):

gdbstub: Correct misparsing of vCont C/S requests

hw/openrisc/openrisc_sim: Use IRQ splitter when connecting IRQ to multiple CPUs

hw/openrisc/openrisc_sim: Abstract out "get IRQ x of CPU y"

target/openrisc: Move pic_cpu code into CPU object proper

target/nios2: Move IIC code into CPU object proper

target/nios2: Move nios2_check_interrupts() into target/nios2

target/nios2: Use deposit32() to update ipending register

hw/core/loader.c: Track last-seen ROM in rom_check_and_register_reset()

hw/core/loader.c: Improve reporting of ROM overlap errors

elf_ops.h: Don't truncate name of the ROM blobs we create

elf_ops.h: Be more verbose with ROM blob names

Philippe Mathieu-Daudé (1):

hw/misc/zynq_slcr: Avoid #DIV/0! error

Sai Pavan Boddu (2):

usb: Add versal-usb2-ctrl-regs module

usb: xlnx-usb-subsystem: Add xilinx usb subsystem

Vikram Garhwal (2):

usb: Add DWC3 model

arm: xlnx-versal: Connect usb to virt-versal

include/hw/arm/xlnx-versal.h | 9 +

include/hw/elf_ops.h | 5 +-

include/hw/usb/hcd-dwc3.h | 55 +++

include/hw/usb/xlnx-usb-subsystem.h | 45 ++

include/hw/usb/xlnx-versal-usb2-ctrl-regs.h | 45 ++

target/nios2/cpu.h | 3 -

target/openrisc/cpu.h | 1 -

gdbstub.c | 2 +-

hw/arm/xlnx-versal-virt.c | 55 +++

hw/arm/xlnx-versal.c | 26 ++

hw/block/m25p80.c | 158 +++++--

hw/core/loader.c | 67 ++-

hw/intc/nios2_iic.c | 95 ----

hw/misc/zynq_slcr.c | 5 +

hw/nios2/10m50_devboard.c | 13 +-

hw/nios2/cpu_pic.c | 67 ---

hw/openrisc/openrisc_sim.c | 46 +-

hw/openrisc/pic_cpu.c | 61 ---

hw/usb/hcd-dwc3.c | 689 ++++++++++++++++++++++++++++

hw/usb/xlnx-usb-subsystem.c | 94 ++++

hw/usb/xlnx-versal-usb2-ctrl-regs.c | 229 +++++++++

softmmu/vl.c | 1 -

target/nios2/cpu.c | 29 ++

target/nios2/op_helper.c | 9 +

target/openrisc/cpu.c | 32 ++

MAINTAINERS | 1 -

hw/intc/meson.build | 1 -

hw/nios2/meson.build | 2 +-

hw/openrisc/Kconfig | 1 +

hw/openrisc/meson.build | 2 +-

hw/usb/Kconfig | 10 +

hw/usb/meson.build | 3 +

32 files changed, 1557 insertions(+), 304 deletions(-)

create mode 100644 include/hw/usb/hcd-dwc3.h

create mode 100644 include/hw/usb/xlnx-usb-subsystem.h

create mode 100644 include/hw/usb/xlnx-versal-usb2-ctrl-regs.h

delete mode 100644 hw/intc/nios2_iic.c

delete mode 100644 hw/nios2/cpu_pic.c

delete mode 100644 hw/openrisc/pic_cpu.c

create mode 100644 hw/usb/hcd-dwc3.c

create mode 100644 hw/usb/xlnx-usb-subsystem.c

create mode 100644 hw/usb/xlnx-versal-usb2-ctrl-regs.c

In the vCont packet, two of the command actions (C and S) take an

argument specifying the signal to be sent to the process/thread, which is

sent as an ASCII string of two hex digits which immediately follow the

'C' or 'S' character.

Our code for parsing this packet accidentally skipped the first of the

two bytes of the signal value, because it started parsing the hex string

at 'p + 1' when the preceding code had already moved past the 'C' or

'S' with "cur_action = *p++".

This meant that we would only do the right thing for signals below

10, and would misinterpret the rest. For instance, when the debugger

wants to send the process a SIGPROF (27 on x86-64) we mangle this into

a SIGSEGV (11).

Remove the accidental double increment.

Fixes: https://bugs.launchpad.net/qemu/+bug/1773743

gdbstub.c | 2 +-

diff --git a/gdbstub.c b/gdbstub.c

--- a/gdbstub.c

+++ b/gdbstub.c

@@ -XXX,XX +XXX,XX @@ static int gdb_handle_vcont(const char *p)

cur_action = *p++;

if (cur_action == 'C' || cur_action == 'S') {

cur_action = qemu_tolower(cur_action);

- res = qemu_strtoul(p + 1, &p, 16, &tmp);

+ res = qemu_strtoul(p, &p, 16, &tmp);

if (res) {

goto out;

}

openrisc_sim_net_init() attempts to connect the IRQ line from the

ethernet device to both CPUs in an SMP configuration by simply caling

sysbus_connect_irq() for it twice. This doesn't work, because the

second connection simply overrides the first.

Fix this by creating a TYPE_SPLIT_IRQ to split the IRQ in the SMP

case.

Reviewed-by: Stafford Horne <shorne@gmail.com>

Message-id: 20201127225127.14770-2-peter.maydell@linaro.org

hw/openrisc/openrisc_sim.c | 13 +++++++++++--

hw/openrisc/Kconfig | 1 +

2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c

--- a/hw/openrisc/openrisc_sim.c

+++ b/hw/openrisc/openrisc_sim.c

@@ -XXX,XX +XXX,XX @@

#include "hw/sysbus.h"

#include "sysemu/qtest.h"

#include "sysemu/reset.h"

+#include "hw/core/split-irq.h"

#define KERNEL_LOAD_ADDR 0x100

@@ -XXX,XX +XXX,XX @@ static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors,

s = SYS_BUS_DEVICE(dev);

sysbus_realize_and_unref(s, &error_fatal);

- for (i = 0; i < num_cpus; i++) {

- sysbus_connect_irq(s, 0, cpu_irqs[i][irq_pin]);

+ if (num_cpus > 1) {

+ DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);

+ qdev_prop_set_uint32(splitter, "num-lines", num_cpus);

+ qdev_realize_and_unref(splitter, NULL, &error_fatal);

+ for (i = 0; i < num_cpus; i++) {

+ qdev_connect_gpio_out(splitter, i, cpu_irqs[i][irq_pin]);

+ }

+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(splitter, 0));

+ } else {

+ sysbus_connect_irq(s, 0, cpu_irqs[0][irq_pin]);

}

sysbus_mmio_map(s, 0, base);

sysbus_mmio_map(s, 1, descriptors);

diff --git a/hw/openrisc/Kconfig b/hw/openrisc/Kconfig

--- a/hw/openrisc/Kconfig

+++ b/hw/openrisc/Kconfig

@@ -XXX,XX +XXX,XX @@ config OR1K_SIM

select SERIAL

select OPENCORES_ETH

select OMPIC

+ select SPLIT_IRQ

We're about to refactor the OpenRISC pic_cpu code in a way that means

that just grabbing the whole qemu_irq[] array of inbound IRQs for a

CPU won't be possible any more. Abstract out a function for "return

the qemu_irq for IRQ x input of CPU y" so we can more easily replace

the implementation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Stafford Horne <shorne@gmail.com>

Message-id: 20201127225127.14770-3-peter.maydell@linaro.org

---

hw/openrisc/openrisc_sim.c | 38 +++++++++++++++++++++-----------------

1 file changed, 21 insertions(+), 17 deletions(-)

diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c

--- a/hw/openrisc/openrisc_sim.c

+++ b/hw/openrisc/openrisc_sim.c

@@ -XXX,XX +XXX,XX @@ static void main_cpu_reset(void *opaque)

cpu_set_pc(cs, boot_info.bootstrap_pc);

+static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin)

+ return cpus[cpunum]->env.irq[irq_pin];

static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors,

- int num_cpus, qemu_irq **cpu_irqs,

+ int num_cpus, OpenRISCCPU *cpus[],

int irq_pin, NICInfo *nd)

DeviceState *dev;

@@ -XXX,XX +XXX,XX @@ static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors,

qdev_prop_set_uint32(splitter, "num-lines", num_cpus);

qdev_realize_and_unref(splitter, NULL, &error_fatal);

for (i = 0; i < num_cpus; i++) {

- qdev_connect_gpio_out(splitter, i, cpu_irqs[i][irq_pin]);

+ qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin));

}

sysbus_connect_irq(s, 0, qdev_get_gpio_in(splitter, 0));

} else {

- sysbus_connect_irq(s, 0, cpu_irqs[0][irq_pin]);

+ sysbus_connect_irq(s, 0, get_cpu_irq(cpus, 0, irq_pin));

sysbus_mmio_map(s, 0, base);

sysbus_mmio_map(s, 1, descriptors);

static void openrisc_sim_ompic_init(hwaddr base, int num_cpus,

- qemu_irq **cpu_irqs, int irq_pin)

+ OpenRISCCPU *cpus[], int irq_pin)

{

DeviceState *dev;

SysBusDevice *s;

@@ -XXX,XX +XXX,XX @@ static void openrisc_sim_ompic_init(hwaddr base, int num_cpus,

s = SYS_BUS_DEVICE(dev);

sysbus_realize_and_unref(s, &error_fatal);

for (i = 0; i < num_cpus; i++) {

- sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]);

+ sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin));

sysbus_mmio_map(s, 0, base);

@@ -XXX,XX +XXX,XX @@ static void openrisc_sim_init(MachineState *machine)

{

ram_addr_t ram_size = machine->ram_size;

const char *kernel_filename = machine->kernel_filename;

- OpenRISCCPU *cpu = NULL;

+ OpenRISCCPU *cpus[2] = {};

MemoryRegion *ram;

- qemu_irq *cpu_irqs[2];

qemu_irq serial_irq;

int n;

unsigned int smp_cpus = machine->smp.cpus;

assert(smp_cpus >= 1 && smp_cpus <= 2);

for (n = 0; n < smp_cpus; n++) {

- cpu = OPENRISC_CPU(cpu_create(machine->cpu_type));

- if (cpu == NULL) {

+ cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type));

+ if (cpus[n] == NULL) {

fprintf(stderr, "Unable to find CPU definition!\n");

exit(1);

}

- cpu_openrisc_pic_init(cpu);

- cpu_irqs[n] = (qemu_irq *) cpu->env.irq;

+ cpu_openrisc_pic_init(cpus[n]);

- cpu_openrisc_clock_init(cpu);

+ cpu_openrisc_clock_init(cpus[n]);

- qemu_register_reset(main_cpu_reset, cpu);

+ qemu_register_reset(main_cpu_reset, cpus[n]);

ram = g_malloc(sizeof(*ram));

@@ -XXX,XX +XXX,XX @@ static void openrisc_sim_init(MachineState *machine)

if (nd_table[0].used) {

openrisc_sim_net_init(0x92000000, 0x92000400, smp_cpus,

- cpu_irqs, 4, nd_table);

+ cpus, 4, nd_table);

}

if (smp_cpus > 1) {

- openrisc_sim_ompic_init(0x98000000, smp_cpus, cpu_irqs, 1);

+ openrisc_sim_ompic_init(0x98000000, smp_cpus, cpus, 1);

- serial_irq = qemu_irq_split(cpu_irqs[0][2], cpu_irqs[1][2]);

+ serial_irq = qemu_irq_split(get_cpu_irq(cpus, 0, 2),

+ get_cpu_irq(cpus, 1, 2));

} else {

- serial_irq = cpu_irqs[0][2];

+ serial_irq = get_cpu_irq(cpus, 0, 2);

}

serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq,

The openrisc code uses an old style of interrupt handling, where a

separate standalone set of qemu_irqs invoke a function

openrisc_pic_cpu_handler() which signals the interrupt to the CPU

proper by directly calling cpu_interrupt() and cpu_reset_interrupt().

Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they

can have GPIO input lines themselves, and the neater modern way to

implement this is to simply have the CPU object itself provide the

input IRQ lines.

Reviewed-by: Stafford Horne <shorne@gmail.com>

Message-id: 20201127225127.14770-4-peter.maydell@linaro.org

target/openrisc/cpu.h | 1 -

hw/openrisc/openrisc_sim.c | 3 +-

hw/openrisc/pic_cpu.c | 61 --------------------------------------

target/openrisc/cpu.c | 32 ++++++++++++++++++++

hw/openrisc/meson.build | 2 +-

5 files changed, 34 insertions(+), 65 deletions(-)

delete mode 100644 hw/openrisc/pic_cpu.c

diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h

--- a/target/openrisc/cpu.h

+++ b/target/openrisc/cpu.h

@@ -XXX,XX +XXX,XX @@ typedef struct CPUOpenRISCState {

uint32_t picmr; /* Interrupt mask register */

uint32_t picsr; /* Interrupt contrl register*/

#endif

- void *irq[32]; /* Interrupt irq input */

} CPUOpenRISCState;

/**

diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c

--- a/hw/openrisc/openrisc_sim.c

+++ b/hw/openrisc/openrisc_sim.c

@@ -XXX,XX +XXX,XX @@ static void main_cpu_reset(void *opaque)

static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin)

{

- return cpus[cpunum]->env.irq[irq_pin];

+ return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin);

static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors,

@@ -XXX,XX +XXX,XX @@ static void openrisc_sim_init(MachineState *machine)

fprintf(stderr, "Unable to find CPU definition!\n");

exit(1);

}

- cpu_openrisc_pic_init(cpus[n]);

cpu_openrisc_clock_init(cpus[n]);

diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c

deleted file mode 100644

index XXXXXXX..XXXXXXX

--- a/hw/openrisc/pic_cpu.c

+++ /dev/null

@@ -XXX,XX +XXX,XX @@

-/*

- * OpenRISC Programmable Interrupt Controller support.

- *

- * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>

- * Feng Gao <gf91597@gmail.com>

- *

- * This library is free software; you can redistribute it and/or

- * modify it under the terms of the GNU Lesser General Public

- * License as published by the Free Software Foundation; either

- * version 2.1 of the License, or (at your option) any later version.

- *

- * This library is distributed in the hope that it will be useful,

- * but WITHOUT ANY WARRANTY; without even the implied warranty of

- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU

- * Lesser General Public License for more details.

- *

- * You should have received a copy of the GNU Lesser General Public

- * License along with this library; if not, see <http://www.gnu.org/licenses/>.

- */

-

-#include "qemu/osdep.h"

-#include "hw/irq.h"

-#include "cpu.h"

-

-/* OpenRISC pic handler */

-static void openrisc_pic_cpu_handler(void *opaque, int irq, int level)

- OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;

- CPUState *cs = CPU(cpu);

- uint32_t irq_bit;

-

- if (irq > 31 || irq < 0) {

- return;

- }

-

- irq_bit = 1U << irq;

-

- if (level) {

- cpu->env.picsr |= irq_bit;

- cpu->env.picsr &= ~irq_bit;

- }

-

- if (cpu->env.picsr & cpu->env.picmr) {

- cpu_interrupt(cs, CPU_INTERRUPT_HARD);

- } else {

- cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);

- cpu->env.picsr = 0;

-void cpu_openrisc_pic_init(OpenRISCCPU *cpu)

-{

- int i;

- qemu_irq *qi;

- qi = qemu_allocate_irqs(openrisc_pic_cpu_handler, cpu, NR_IRQS);

-

- for (i = 0; i < NR_IRQS; i++) {

- cpu->env.irq[i] = qi[i];

- }

-}

diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/openrisc/cpu.c

+++ b/target/openrisc/cpu.c

@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset(DeviceState *dev)

#endif

}

+#ifndef CONFIG_USER_ONLY

+static void openrisc_cpu_set_irq(void *opaque, int irq, int level)

+{

+ OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;

+ CPUState *cs = CPU(cpu);

+ uint32_t irq_bit;

+

+ if (irq > 31 || irq < 0) {

+ return;

+ }

+

+ irq_bit = 1U << irq;

+

+ if (level) {

+ cpu->env.picsr |= irq_bit;

+ } else {

+ cpu->env.picsr &= ~irq_bit;

+ }

+

+ if (cpu->env.picsr & cpu->env.picmr) {

+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);

+ } else {

+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);

+ cpu->env.picsr = 0;

+ }

+}

+#endif

+

static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)

CPUState *cs = CPU(dev);

@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_initfn(Object *obj)

OpenRISCCPU *cpu = OPENRISC_CPU(obj);

cpu_set_cpustate_pointers(cpu);

+

+#ifndef CONFIG_USER_ONLY

+ qdev_init_gpio_in_named(DEVICE(cpu), openrisc_cpu_set_irq, "IRQ", NR_IRQS);

+#endif

}

/* CPU models */

diff --git a/hw/openrisc/meson.build b/hw/openrisc/meson.build

index XXXXXXX..XXXXXXX 100644

--- a/hw/openrisc/meson.build

+++ b/hw/openrisc/meson.build

@@ -XXX,XX +XXX,XX @@

openrisc_ss = ss.source_set()

-openrisc_ss.add(files('pic_cpu.c', 'cputimer.c'))

+openrisc_ss.add(files('cputimer.c'))

openrisc_ss.add(when: 'CONFIG_OR1K_SIM', if_true: files('openrisc_sim.c'))

hw_arch += {'openrisc': openrisc_ss}

The Nios2 architecture supports two different interrupt controller

options:

* The IIC (Internal Interrupt Controller) is part of the CPU itself;

it has 32 IRQ input lines and no NMI support. Interrupt status is

queried and controlled via the CPU's ipending and istatus

registers.

* The EIC (External Interrupt Controller) interface allows the CPU

to connect to an external interrupt controller. The interface

allows the interrupt controller to present a packet of information

containing:

- handler address

- interrupt level

- register set

- NMI mode

QEMU does not model an EIC currently. We do model the IIC, but its

implementation is split across code in hw/nios2/cpu_pic.c and

hw/intc/nios2_iic.c. The code in those two files has no state of its

own -- the IIC state is in the Nios2CPU state struct.

Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they

can have GPIO input lines themselves, so we can implement the IIC

directly in the CPU object the same way that real hardware does.

Create named "IRQ" GPIO inputs to the Nios2 CPU object, and make the

only user of the IIC wire up directly to those instead.

Note that the old code had an "NMI" concept which was entirely unused

and also as far as I can see not architecturally correct, since only

the EIC has a concept of an NMI.

This fixes a Coverity-reported trivial memory leak of the IRQ array

allocated in nios2_cpu_pic_init().

Fixes: Coverity CID 1421916

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20201129174022.26530-2-peter.maydell@linaro.org

Reviewed-by: Wentong Wu <wentong.wu@intel.com>

Tested-by: Wentong Wu <wentong.wu@intel.com>

target/nios2/cpu.h | 1 -

hw/intc/nios2_iic.c | 95 ---------------------------------------

hw/nios2/10m50_devboard.c | 13 +-----

hw/nios2/cpu_pic.c | 31 -------------

target/nios2/cpu.c | 30 +++++++++++++

MAINTAINERS | 1 -

hw/intc/meson.build | 1 -

7 files changed, 32 insertions(+), 140 deletions(-)

delete mode 100644 hw/intc/nios2_iic.c

diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/nios2/cpu.h

+++ b/target/nios2/cpu.h

@@ -XXX,XX +XXX,XX @@ void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,

MMUAccessType access_type,

int mmu_idx, uintptr_t retaddr);

-qemu_irq *nios2_cpu_pic_init(Nios2CPU *cpu);

void nios2_check_interrupts(CPUNios2State *env);

void do_nios2_semihosting(CPUNios2State *env);

diff --git a/hw/intc/nios2_iic.c b/hw/intc/nios2_iic.c

deleted file mode 100644

index XXXXXXX..XXXXXXX

--- a/hw/intc/nios2_iic.c

+++ /dev/null

@@ -XXX,XX +XXX,XX @@

-/*

- * QEMU Altera Internal Interrupt Controller.

- *

- * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>

- *

- * This library is free software; you can redistribute it and/or

- * modify it under the terms of the GNU Lesser General Public

- * License as published by the Free Software Foundation; either

- * version 2.1 of the License, or (at your option) any later version.

- *

- * This library is distributed in the hope that it will be useful,

- * but WITHOUT ANY WARRANTY; without even the implied warranty of

- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU

- * Lesser General Public License for more details.

- *

- * You should have received a copy of the GNU Lesser General Public

- * License along with this library; if not, see

- * <http://www.gnu.org/licenses/lgpl-2.1.html>

- */

-

-#include "qemu/osdep.h"

-#include "qemu/module.h"

-#include "qapi/error.h"

-

-#include "hw/irq.h"

-#include "hw/sysbus.h"

-#include "cpu.h"

-#include "qom/object.h"

-

-#define TYPE_ALTERA_IIC "altera,iic"

-OBJECT_DECLARE_SIMPLE_TYPE(AlteraIIC, ALTERA_IIC)

-

-struct AlteraIIC {

- SysBusDevice parent_obj;

- void *cpu;

- qemu_irq parent_irq;

-};

-

-static void update_irq(AlteraIIC *pv)

-{

- CPUNios2State *env = &((Nios2CPU *)(pv->cpu))->env;

-

- qemu_set_irq(pv->parent_irq,

- env->regs[CR_IPENDING] & env->regs[CR_IENABLE]);

-}

-

-static void irq_handler(void *opaque, int irq, int level)

-{

- AlteraIIC *pv = opaque;

- CPUNios2State *env = &((Nios2CPU *)(pv->cpu))->env;

-

- env->regs[CR_IPENDING] &= ~(1 << irq);

- env->regs[CR_IPENDING] |= !!level << irq;

-

- update_irq(pv);

-}

-

-static void altera_iic_init(Object *obj)

-{

- AlteraIIC *pv = ALTERA_IIC(obj);

-

- qdev_init_gpio_in(DEVICE(pv), irq_handler, 32);

- sysbus_init_irq(SYS_BUS_DEVICE(obj), &pv->parent_irq);

-}

-

-static void altera_iic_realize(DeviceState *dev, Error **errp)

-{

- struct AlteraIIC *pv = ALTERA_IIC(dev);

-

- pv->cpu = object_property_get_link(OBJECT(dev), "cpu", &error_abort);

-}

-

-static void altera_iic_class_init(ObjectClass *klass, void *data)

-{

- DeviceClass *dc = DEVICE_CLASS(klass);

-