1
The following changes since commit 5cc7a54c2e91d82cb6a52e4921325c511fd90712:
1
The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
2
2
3
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200602' into staging (2020-06-02 18:16:38 +0100)
3
Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200603
7
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528
8
8
9
for you to fetch changes up to fe0fe4735e798578097758781166cc221319b93d:
9
for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:
10
10
11
riscv: Initial commit of OpenTitan machine (2020-06-03 09:11:51 -0700)
11
target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
This is a collection of RISC-V patches for 5.1.
14
RISC-V PR for 9.1
15
15
16
This incldues removing deprecated features and part of the OpenTitan
16
* APLICs add child earlier than realize
17
support series.
17
* Fix exposure of Zkr
18
* Raise exceptions on wrs.nto
19
* Implement SBI debug console (DBCN) calls for KVM
20
* Support 64-bit addresses for initrd
21
* Change RISCV_EXCP_SEMIHOST exception number to 63
22
* Tolerate KVM disable ext errors
23
* Set tval in breakpoints
24
* Add support for Zve32x extension
25
* Add support for Zve64x extension
26
* Relax vector register check in RISCV gdbstub
27
* Fix the element agnostic Vector function problem
28
* Fix Zvkb extension config
29
* Implement dynamic establishment of custom decoder
30
* Add th.sxstatus CSR emulation
31
* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
32
* Check single width operator for vector fp widen instructions
33
* Check single width operator for vfncvt.rod.f.f.w
34
* Remove redudant SEW checking for vector fp narrow/widen instructions
35
* Prioritize pmp errors in raise_mmu_exception()
36
* Do not set mtval2 for non guest-page faults
37
* Remove experimental prefix from "B" extension
38
* Fixup CBO extension register calculation
39
* Fix the hart bit setting of AIA
40
* Fix reg_width in ricsv_gen_dynamic_vector_feature()
41
* Decode all of the pmpcfg and pmpaddr CSRs
42
* Raise an exception when CSRRS/CSRRC writes a read-only CSR
18
43
19
----------------------------------------------------------------
44
----------------------------------------------------------------
20
Alistair Francis (11):
45
Alexei Filippov (1):
21
hw/riscv: spike: Remove deprecated ISA specific machines
46
target/riscv: do not set mtval2 for non guest-page faults
22
target/riscv: Remove the deprecated CPUs
23
target/riscv: Drop support for ISA spec version 1.09.1
24
docs: deprecated: Update the -bios documentation
25
riscv: sifive_e: Manually define the machine
26
riscv/boot: Add a missing header include
27
target/riscv: Don't overwrite the reset vector
28
target/riscv: Disable the MMU correctly
29
target/riscv: Don't set PMP feature in the cpu init
30
target/riscv: Add the lowRISC Ibex CPU
31
riscv: Initial commit of OpenTitan machine
32
47
33
Bin Meng (4):
48
Alistair Francis (2):
34
riscv: Suppress the error report for QEMU testing with riscv_find_firmware()
49
target/riscv: rvzicbo: Fixup CBO extension register calculation
35
riscv: Change the default behavior if no -bios option is specified
50
disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
36
hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions
37
hw/riscv: virt: Remove the riscv_ prefix of the machine* functions
38
51
39
docs/system/deprecated.rst | 98 +++++------
52
Andrew Jones (2):
40
default-configs/riscv32-softmmu.mak | 1 +
53
target/riscv/kvm: Fix exposure of Zkr
41
default-configs/riscv64-softmmu.mak | 11 +-
54
target/riscv: Raise exceptions on wrs.nto
42
include/hw/riscv/boot.h | 1 +
43
include/hw/riscv/opentitan.h | 68 ++++++++
44
include/hw/riscv/sifive_e.h | 4 +
45
include/hw/riscv/spike.h | 6 +-
46
target/riscv/cpu.h | 9 +-
47
hw/riscv/boot.c | 45 ++---
48
hw/riscv/opentitan.c | 184 +++++++++++++++++++++
49
hw/riscv/sifive_e.c | 41 +++--
50
hw/riscv/sifive_u.c | 24 +--
51
hw/riscv/spike.c | 217 -------------------------
52
hw/riscv/virt.c | 20 +--
53
target/riscv/cpu.c | 45 ++---
54
target/riscv/cpu_helper.c | 82 ++++------
55
target/riscv/csr.c | 138 +++-------------
56
target/riscv/insn_trans/trans_privileged.inc.c | 18 +-
57
target/riscv/monitor.c | 5 -
58
target/riscv/op_helper.c | 17 +-
59
tests/qtest/machine-none-test.c | 4 +-
60
MAINTAINERS | 9 +
61
hw/riscv/Kconfig | 5 +
62
hw/riscv/Makefile.objs | 1 +
63
24 files changed, 480 insertions(+), 573 deletions(-)
64
create mode 100644 include/hw/riscv/opentitan.h
65
create mode 100644 hw/riscv/opentitan.c
66
55
56
Cheng Yang (1):
57
hw/riscv/boot.c: Support 64-bit address for initrd
58
59
Christoph Müllner (1):
60
riscv: thead: Add th.sxstatus CSR emulation
61
62
Clément Léger (1):
63
target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
64
65
Daniel Henrique Barboza (6):
66
target/riscv/kvm: implement SBI debug console (DBCN) calls
67
target/riscv/kvm: tolerate KVM disable ext errors
68
target/riscv/debug: set tval=pc in breakpoint exceptions
69
trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
70
target/riscv: prioritize pmp errors in raise_mmu_exception()
71
riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
72
73
Huang Tao (2):
74
target/riscv: Fix the element agnostic function problem
75
target/riscv: Implement dynamic establishment of custom decoder
76
77
Jason Chien (3):
78
target/riscv: Add support for Zve32x extension
79
target/riscv: Add support for Zve64x extension
80
target/riscv: Relax vector register check in RISCV gdbstub
81
82
Max Chou (4):
83
target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
84
target/riscv: rvv: Check single width operator for vector fp widen instructions
85
target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
86
target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
87
88
Rob Bradford (1):
89
target/riscv: Remove experimental prefix from "B" extension
90
91
Yangyu Chen (1):
92
target/riscv/cpu.c: fix Zvkb extension config
93
94
Yong-Xuan Wang (1):
95
target/riscv/kvm.c: Fix the hart bit setting of AIA
96
97
Yu-Ming Chang (1):
98
target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
99
100
yang.zhang (1):
101
hw/intc/riscv_aplic: APLICs should add child earlier than realize
102
103
MAINTAINERS | 1 +
104
target/riscv/cpu.h | 11 ++
105
target/riscv/cpu_bits.h | 2 +-
106
target/riscv/cpu_cfg.h | 2 +
107
target/riscv/helper.h | 1 +
108
target/riscv/sbi_ecall_interface.h | 17 +++
109
target/riscv/tcg/tcg-cpu.h | 15 +++
110
disas/riscv.c | 65 +++++++++-
111
hw/intc/riscv_aplic.c | 8 +-
112
hw/riscv/boot.c | 4 +-
113
target/riscv/cpu.c | 10 +-
114
target/riscv/cpu_helper.c | 37 +++---
115
target/riscv/csr.c | 71 +++++++++--
116
target/riscv/debug.c | 3 +
117
target/riscv/gdbstub.c | 8 +-
118
target/riscv/kvm/kvm-cpu.c | 157 ++++++++++++++++++++++++-
119
target/riscv/op_helper.c | 17 ++-
120
target/riscv/tcg/tcg-cpu.c | 50 +++++---
121
target/riscv/th_csr.c | 79 +++++++++++++
122
target/riscv/translate.c | 31 +++--
123
target/riscv/vector_internals.c | 22 ++++
124
target/riscv/insn_trans/trans_privileged.c.inc | 2 +
125
target/riscv/insn_trans/trans_rvv.c.inc | 46 +++++---
126
target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 +++--
127
target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++-
128
target/riscv/meson.build | 1 +
129
26 files changed, 596 insertions(+), 109 deletions(-)
130
create mode 100644 target/riscv/th_csr.c
131
diff view generated by jsdifflib
New patch
1
From: "yang.zhang" <yang.zhang@hexintek.com>
1
2
3
Since only root APLICs can have hw IRQ lines, aplic->parent should
4
be initialized first.
5
6
Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
9
Cc: qemu-stable <qemu-stable@nongnu.org>
10
Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
hw/intc/riscv_aplic.c | 8 ++++----
14
1 file changed, 4 insertions(+), 4 deletions(-)
15
16
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/riscv_aplic.c
19
+++ b/hw/intc/riscv_aplic.c
20
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
21
qdev_prop_set_bit(dev, "msimode", msimode);
22
qdev_prop_set_bit(dev, "mmode", mmode);
23
24
+ if (parent) {
25
+ riscv_aplic_add_child(parent, dev);
26
+ }
27
+
28
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
29
30
if (!is_kvm_aia(msimode)) {
31
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
32
}
33
34
- if (parent) {
35
- riscv_aplic_add_child(parent, dev);
36
- }
37
-
38
if (!msimode) {
39
for (i = 0; i < num_harts; i++) {
40
CPUState *cpu = cpu_by_arch_id(hartid_base + i);
41
--
42
2.45.1
diff view generated by jsdifflib
New patch
1
From: Andrew Jones <ajones@ventanamicro.com>
1
2
3
The Zkr extension may only be exposed to KVM guests if the VMM
4
implements the SEED CSR. Use the same implementation as TCG.
5
6
Without this patch, running with a KVM which does not forward the
7
SEED CSR access to QEMU will result in an ILL exception being
8
injected into the guest (this results in Linux guests crashing on
9
boot). And, when running with a KVM which does forward the access,
10
QEMU will crash, since QEMU doesn't know what to do with the exit.
11
12
Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
13
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
14
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
15
Cc: qemu-stable <qemu-stable@nongnu.org>
16
Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
19
target/riscv/cpu.h | 3 +++
20
target/riscv/csr.c | 18 ++++++++++++++----
21
target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
22
3 files changed, 42 insertions(+), 4 deletions(-)
23
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/riscv/cpu.h
27
+++ b/target/riscv/cpu.h
28
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
29
30
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
31
32
+target_ulong riscv_new_csr_seed(target_ulong new_value,
33
+ target_ulong write_mask);
34
+
35
uint8_t satp_mode_max_from_map(uint32_t map);
36
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
37
38
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/riscv/csr.c
41
+++ b/target/riscv/csr.c
42
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
43
#endif
44
45
/* Crypto Extension */
46
-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
47
- target_ulong *ret_value,
48
- target_ulong new_value,
49
- target_ulong write_mask)
50
+target_ulong riscv_new_csr_seed(target_ulong new_value,
51
+ target_ulong write_mask)
52
{
53
uint16_t random_v;
54
Error *random_e = NULL;
55
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
56
rval = random_v | SEED_OPST_ES16;
57
}
58
59
+ return rval;
60
+}
61
+
62
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
63
+ target_ulong *ret_value,
64
+ target_ulong new_value,
65
+ target_ulong write_mask)
66
+{
67
+ target_ulong rval;
68
+
69
+ rval = riscv_new_csr_seed(new_value, write_mask);
70
+
71
if (ret_value) {
72
*ret_value = rval;
73
}
74
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/target/riscv/kvm/kvm-cpu.c
77
+++ b/target/riscv/kvm/kvm-cpu.c
78
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
79
return ret;
80
}
81
82
+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
83
+{
84
+ target_ulong csr_num = run->riscv_csr.csr_num;
85
+ target_ulong new_value = run->riscv_csr.new_value;
86
+ target_ulong write_mask = run->riscv_csr.write_mask;
87
+ int ret = 0;
88
+
89
+ switch (csr_num) {
90
+ case CSR_SEED:
91
+ run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
92
+ break;
93
+ default:
94
+ qemu_log_mask(LOG_UNIMP,
95
+ "%s: un-handled CSR EXIT for CSR %lx\n",
96
+ __func__, csr_num);
97
+ ret = -1;
98
+ break;
99
+ }
100
+
101
+ return ret;
102
+}
103
+
104
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
105
{
106
int ret = 0;
107
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
108
case KVM_EXIT_RISCV_SBI:
109
ret = kvm_riscv_handle_sbi(cs, run);
110
break;
111
+ case KVM_EXIT_RISCV_CSR:
112
+ ret = kvm_riscv_handle_csr(cs, run);
113
+ break;
114
default:
115
qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
116
__func__, run->exit_reason);
117
--
118
2.45.1
diff view generated by jsdifflib
1
From: Andrew Jones <ajones@ventanamicro.com>
2
3
Implementing wrs.nto to always just return is consistent with the
4
specification, as the instruction is permitted to terminate the
5
stall for any reason, but it's not useful for virtualization, where
6
we'd like the guest to trap to the hypervisor in order to allow
7
scheduling of the lock holding VCPU. Change to always immediately
8
raise exceptions when the appropriate conditions are present,
9
otherwise continue to just return. Note, immediately raising
10
exceptions is also consistent with the specification since the
11
time limit that should expire prior to the exception is
12
implementation-specific.
13
14
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
15
Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
16
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
18
Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
3
---
20
---
4
include/hw/riscv/sifive_e.h | 4 ++++
21
target/riscv/helper.h | 1 +
5
hw/riscv/sifive_e.c | 41 +++++++++++++++++++++++++++----------
22
target/riscv/op_helper.c | 11 ++++++++
6
2 files changed, 34 insertions(+), 11 deletions(-)
23
target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
24
3 files changed, 32 insertions(+), 9 deletions(-)
7
25
8
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
26
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
9
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
10
--- a/include/hw/riscv/sifive_e.h
28
--- a/target/riscv/helper.h
11
+++ b/include/hw/riscv/sifive_e.h
29
+++ b/target/riscv/helper.h
12
@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveEState {
30
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
13
SiFiveESoCState soc;
31
DEF_HELPER_1(sret, tl, env)
14
} SiFiveEState;
32
DEF_HELPER_1(mret, tl, env)
15
33
DEF_HELPER_1(wfi, void, env)
16
+#define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
34
+DEF_HELPER_1(wrs_nto, void, env)
17
+#define RISCV_E_MACHINE(obj) \
35
DEF_HELPER_1(tlb_flush, void, env)
18
+ OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
36
DEF_HELPER_1(tlb_flush_all, void, env)
19
+
37
/* Native Debug */
20
enum {
38
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
21
SIFIVE_E_DEBUG,
22
SIFIVE_E_MROM,
23
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
24
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/riscv/sifive_e.c
40
--- a/target/riscv/op_helper.c
26
+++ b/hw/riscv/sifive_e.c
41
+++ b/target/riscv/op_helper.c
27
@@ -XXX,XX +XXX,XX @@ static void riscv_sifive_e_init(MachineState *machine)
42
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
28
{
29
const struct MemmapEntry *memmap = sifive_e_memmap;
30
31
- SiFiveEState *s = g_new0(SiFiveEState, 1);
32
+ SiFiveEState *s = RISCV_E_MACHINE(machine);
33
MemoryRegion *sys_mem = get_system_memory();
34
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
35
int i;
36
@@ -XXX,XX +XXX,XX @@ static void riscv_sifive_e_init(MachineState *machine)
37
}
43
}
38
}
44
}
39
45
40
+static void sifive_e_machine_instance_init(Object *obj)
46
+void helper_wrs_nto(CPURISCVState *env)
41
+{
47
+{
48
+ if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
49
+ get_field(env->hstatus, HSTATUS_VTW) &&
50
+ !get_field(env->mstatus, MSTATUS_TW)) {
51
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
52
+ } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
53
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
54
+ }
42
+}
55
+}
43
+
56
+
44
+static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
57
void helper_tlb_flush(CPURISCVState *env)
58
{
59
CPUState *cs = env_cpu(env);
60
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
61
index XXXXXXX..XXXXXXX 100644
62
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
63
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
64
@@ -XXX,XX +XXX,XX @@
65
* this program. If not, see <http://www.gnu.org/licenses/>.
66
*/
67
68
-static bool trans_wrs(DisasContext *ctx)
69
+static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
70
{
71
if (!ctx->cfg_ptr->ext_zawrs) {
72
return false;
73
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
74
return true;
75
}
76
77
-#define GEN_TRANS_WRS(insn) \
78
-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a) \
79
-{ \
80
- (void)a; \
81
- return trans_wrs(ctx); \
82
-}
83
+static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
45
+{
84
+{
46
+ MachineClass *mc = MACHINE_CLASS(oc);
85
+ if (!ctx->cfg_ptr->ext_zawrs) {
86
+ return false;
87
+ }
88
89
-GEN_TRANS_WRS(wrs_nto)
90
-GEN_TRANS_WRS(wrs_sto)
91
+ /*
92
+ * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
93
+ * should raise an exception when the implementation-specific bounded time
94
+ * limit has expired. Our time limit is zero, so we either return
95
+ * immediately, as does our implementation of wrs.sto, or raise an
96
+ * exception, as handled by the wrs.nto helper.
97
+ */
98
+#ifndef CONFIG_USER_ONLY
99
+ gen_helper_wrs_nto(tcg_env);
100
+#endif
47
+
101
+
48
+ mc->desc = "RISC-V Board compatible with SiFive E SDK";
102
+ /* We only get here when helper_wrs_nto() doesn't raise an exception. */
49
+ mc->init = riscv_sifive_e_init;
103
+ return trans_wrs_sto(ctx, NULL);
50
+ mc->max_cpus = 1;
51
+ mc->default_cpu_type = SIFIVE_E_CPU;
52
+}
104
+}
53
+
54
+static const TypeInfo sifive_e_machine_typeinfo = {
55
+ .name = MACHINE_TYPE_NAME("sifive_e"),
56
+ .parent = TYPE_MACHINE,
57
+ .class_init = sifive_e_machine_class_init,
58
+ .instance_init = sifive_e_machine_instance_init,
59
+ .instance_size = sizeof(SiFiveEState),
60
+};
61
+
62
+static void sifive_e_machine_init_register_types(void)
63
+{
64
+ type_register_static(&sifive_e_machine_typeinfo);
65
+}
66
+
67
+type_init(sifive_e_machine_init_register_types)
68
+
69
static void riscv_sifive_e_soc_init(Object *obj)
70
{
71
MachineState *ms = MACHINE(qdev_get_machine());
72
@@ -XXX,XX +XXX,XX @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
73
&s->xip_mem);
74
}
75
76
-static void riscv_sifive_e_machine_init(MachineClass *mc)
77
-{
78
- mc->desc = "RISC-V Board compatible with SiFive E SDK";
79
- mc->init = riscv_sifive_e_init;
80
- mc->max_cpus = 1;
81
- mc->default_cpu_type = SIFIVE_E_CPU;
82
-}
83
-
84
-DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
85
-
86
static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
87
{
88
DeviceClass *dc = DEVICE_CLASS(oc);
89
--
105
--
90
2.26.2
106
2.45.1
91
107
92
108
diff view generated by jsdifflib
New patch
1
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
3
SBI defines a Debug Console extension "DBCN" that will, in time, replace
4
the legacy console putchar and getchar SBI extensions.
5
6
The appeal of the DBCN extension is that it allows multiple bytes to be
7
read/written in the SBI console in a single SBI call.
8
9
As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
10
module to userspace. But this will only happens if the KVM module
11
actually supports this SBI extension and we activate it.
12
13
We'll check for DBCN support during init time, checking if get-reg-list
14
is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
15
kvm_set_one_reg() during kvm_arch_init_vcpu().
16
17
Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
18
SBI_EXT_DBCN, reading and writing as required.
19
20
A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
21
host, takes around 20 seconds to boot without using DBCN. With this
22
patch we're taking around 14 seconds to boot due to the speed-up in the
23
terminal output. There's no change in boot time if the guest isn't
24
using earlycon.
25
26
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
27
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
28
Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
29
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
30
---
31
target/riscv/sbi_ecall_interface.h | 17 +++++
32
target/riscv/kvm/kvm-cpu.c | 111 +++++++++++++++++++++++++++++
33
2 files changed, 128 insertions(+)
34
35
diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/sbi_ecall_interface.h
38
+++ b/target/riscv/sbi_ecall_interface.h
39
@@ -XXX,XX +XXX,XX @@
40
41
/* clang-format off */
42
43
+#define SBI_SUCCESS 0
44
+#define SBI_ERR_FAILED -1
45
+#define SBI_ERR_NOT_SUPPORTED -2
46
+#define SBI_ERR_INVALID_PARAM -3
47
+#define SBI_ERR_DENIED -4
48
+#define SBI_ERR_INVALID_ADDRESS -5
49
+#define SBI_ERR_ALREADY_AVAILABLE -6
50
+#define SBI_ERR_ALREADY_STARTED -7
51
+#define SBI_ERR_ALREADY_STOPPED -8
52
+#define SBI_ERR_NO_SHMEM -9
53
+
54
/* SBI Extension IDs */
55
#define SBI_EXT_0_1_SET_TIMER 0x0
56
#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
57
@@ -XXX,XX +XXX,XX @@
58
#define SBI_EXT_IPI 0x735049
59
#define SBI_EXT_RFENCE 0x52464E43
60
#define SBI_EXT_HSM 0x48534D
61
+#define SBI_EXT_DBCN 0x4442434E
62
63
/* SBI function IDs for BASE extension */
64
#define SBI_EXT_BASE_GET_SPEC_VERSION 0x0
65
@@ -XXX,XX +XXX,XX @@
66
#define SBI_EXT_HSM_HART_STOP 0x1
67
#define SBI_EXT_HSM_HART_GET_STATUS 0x2
68
69
+/* SBI function IDs for DBCN extension */
70
+#define SBI_EXT_DBCN_CONSOLE_WRITE 0x0
71
+#define SBI_EXT_DBCN_CONSOLE_READ 0x1
72
+#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
73
+
74
#define SBI_HSM_HART_STATUS_STARTED 0x0
75
#define SBI_HSM_HART_STATUS_STOPPED 0x1
76
#define SBI_HSM_HART_STATUS_START_PENDING 0x2
77
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/target/riscv/kvm/kvm-cpu.c
80
+++ b/target/riscv/kvm/kvm-cpu.c
81
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
82
KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
83
};
84
85
+static KVMCPUConfig kvm_sbi_dbcn = {
86
+ .name = "sbi_dbcn",
87
+ .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
88
+ KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
89
+};
90
+
91
static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
92
{
93
CPURISCVState *env = &cpu->env;
94
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
95
return 0;
96
}
97
98
+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
99
+ KVMScratchCPU *kvmcpu,
100
+ struct kvm_reg_list *reglist)
101
+{
102
+ struct kvm_reg_list *reg_search;
103
+
104
+ reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
105
+ sizeof(uint64_t), uint64_cmp);
106
+
107
+ if (reg_search) {
108
+ kvm_sbi_dbcn.supported = true;
109
+ }
110
+}
111
+
112
static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
113
struct kvm_reg_list *reglist)
114
{
115
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
116
if (riscv_has_ext(&cpu->env, RVV)) {
117
kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
118
}
119
+
120
+ kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
121
}
122
123
static void riscv_init_kvm_registers(Object *cpu_obj)
124
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
125
return ret;
126
}
127
128
+static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
129
+{
130
+ target_ulong reg = 1;
131
+
132
+ if (!kvm_sbi_dbcn.supported) {
133
+ return 0;
134
+ }
135
+
136
+ return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
137
+}
138
+
139
int kvm_arch_init_vcpu(CPUState *cs)
140
{
141
int ret = 0;
142
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
143
kvm_riscv_update_cpu_misa_ext(cpu, cs);
144
kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
145
146
+ ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
147
+
148
return ret;
149
}
150
151
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
152
return true;
153
}
154
155
+static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
156
+{
157
+ g_autofree uint8_t *buf = NULL;
158
+ RISCVCPU *cpu = RISCV_CPU(cs);
159
+ target_ulong num_bytes;
160
+ uint64_t addr;
161
+ unsigned char ch;
162
+ int ret;
163
+
164
+ switch (run->riscv_sbi.function_id) {
165
+ case SBI_EXT_DBCN_CONSOLE_READ:
166
+ case SBI_EXT_DBCN_CONSOLE_WRITE:
167
+ num_bytes = run->riscv_sbi.args[0];
168
+
169
+ if (num_bytes == 0) {
170
+ run->riscv_sbi.ret[0] = SBI_SUCCESS;
171
+ run->riscv_sbi.ret[1] = 0;
172
+ break;
173
+ }
174
+
175
+ addr = run->riscv_sbi.args[1];
176
+
177
+ /*
178
+ * Handle the case where a 32 bit CPU is running in a
179
+ * 64 bit addressing env.
180
+ */
181
+ if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
182
+ addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
183
+ }
184
+
185
+ buf = g_malloc0(num_bytes);
186
+
187
+ if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
188
+ ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
189
+ if (ret < 0) {
190
+ error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
191
+ "reading chardev");
192
+ exit(1);
193
+ }
194
+
195
+ cpu_physical_memory_write(addr, buf, ret);
196
+ } else {
197
+ cpu_physical_memory_read(addr, buf, num_bytes);
198
+
199
+ ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
200
+ if (ret < 0) {
201
+ error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
202
+ "writing chardev");
203
+ exit(1);
204
+ }
205
+ }
206
+
207
+ run->riscv_sbi.ret[0] = SBI_SUCCESS;
208
+ run->riscv_sbi.ret[1] = ret;
209
+ break;
210
+ case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
211
+ ch = run->riscv_sbi.args[0];
212
+ ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
213
+
214
+ if (ret < 0) {
215
+ error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
216
+ "writing chardev");
217
+ exit(1);
218
+ }
219
+
220
+ run->riscv_sbi.ret[0] = SBI_SUCCESS;
221
+ run->riscv_sbi.ret[1] = 0;
222
+ break;
223
+ default:
224
+ run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
225
+ }
226
+}
227
+
228
static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
229
{
230
int ret = 0;
231
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
232
}
233
ret = 0;
234
break;
235
+ case SBI_EXT_DBCN:
236
+ kvm_riscv_handle_sbi_dbcn(cs, run);
237
+ break;
238
default:
239
qemu_log_mask(LOG_UNIMP,
240
"%s: un-handled SBI EXIT, specific reasons is %lu\n",
241
--
242
2.45.1
diff view generated by jsdifflib
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Cheng Yang <yangcheng.work@foxmail.com>
2
2
3
Per QEMU deprecated doc, QEMU 4.1 introduced support for the -bios
3
Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
4
option in QEMU for RISC-V for the virt machine and sifive_u machine.
4
to set the address of initrd in FDT to support 64-bit address.
5
The default behavior has been that QEMU does not automatically load
6
any firmware if no -bios option is included.
7
5
8
Now 2 releases passed, it's time to change the default behavior to
6
Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
9
load the default OpenSBI firmware automatically. The firmware is
10
included with the QEMU release and no user interaction is required.
11
All a user needs to do is specify the kernel they want to boot with
12
the -kernel option.
13
14
Signed-off-by: Bin Meng <bin.meng@windriver.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 1588335545-649-1-git-send-email-bmeng.cn@gmail.com
8
Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
17
Message-Id: <1588335545-649-1-git-send-email-bmeng.cn@gmail.com>
18
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
---
10
---
20
hw/riscv/boot.c | 31 ++++---------------------------
11
hw/riscv/boot.c | 4 ++--
21
1 file changed, 4 insertions(+), 27 deletions(-)
12
1 file changed, 2 insertions(+), 2 deletions(-)
22
13
23
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
14
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
24
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/riscv/boot.c
16
--- a/hw/riscv/boot.c
26
+++ b/hw/riscv/boot.c
17
+++ b/hw/riscv/boot.c
27
@@ -XXX,XX +XXX,XX @@ void riscv_find_and_load_firmware(MachineState *machine,
18
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
28
{
19
/* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
29
char *firmware_filename = NULL;
20
if (fdt) {
30
21
end = start + size;
31
- if (!machine->firmware) {
22
- qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
32
+ if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) {
23
- qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
33
/*
24
+ qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
34
- * The user didn't specify -bios.
25
+ qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
35
- * At the moment we default to loading nothing when this hapens.
26
}
36
- * In the future this defaul will change to loading the prebuilt
27
}
37
- * OpenSBI firmware. Let's warn the user and then continue.
28
38
- */
39
- if (!qtest_enabled()) {
40
- warn_report("No -bios option specified. Not loading a firmware.");
41
- warn_report("This default will change in a future QEMU release. " \
42
- "Please use the -bios option to avoid breakages when "\
43
- "this happens.");
44
- warn_report("See QEMU's deprecation documentation for details.");
45
- }
46
- return;
47
- }
48
-
49
- if (!strcmp(machine->firmware, "default")) {
50
- /*
51
- * The user has specified "-bios default". That means we are going to
52
- * load the OpenSBI binary included in the QEMU source.
53
- *
54
- * We can't load the binary by default as it will break existing users
55
- * as users are already loading their own firmware.
56
- *
57
- * Let's try to get everyone to specify the -bios option at all times,
58
- * so then in the future we can make "-bios default" the default option
59
- * if no -bios option is set without breaking anything.
60
+ * The user didn't specify -bios, or has specified "-bios default".
61
+ * That means we are going to load the OpenSBI binary included in
62
+ * the QEMU source.
63
*/
64
firmware_filename = riscv_find_firmware(default_machine_firmware);
65
} else if (strcmp(machine->firmware, "none")) {
66
--
29
--
67
2.26.2
30
2.45.1
68
69
diff view generated by jsdifflib
New patch
1
From: Clément Léger <cleger@rivosinc.com>
1
2
3
The current semihost exception number (16) is a reserved number (range
4
[16-17]). The upcoming double trap specification uses that number for
5
the double trap exception. Since the privileged spec (Table 22) defines
6
ranges for custom uses change the semihosting exception number to 63
7
which belongs to the range [48-63] in order to avoid any future
8
collisions with reserved exception.
9
10
Signed-off-by: Clément Léger <cleger@rivosinc.com>
11
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
16
target/riscv/cpu_bits.h | 2 +-
17
1 file changed, 1 insertion(+), 1 deletion(-)
18
19
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu_bits.h
22
+++ b/target/riscv/cpu_bits.h
23
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
24
RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
25
RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
26
RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
27
- RISCV_EXCP_SEMIHOST = 0x10,
28
RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
29
RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
30
RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
31
RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
32
+ RISCV_EXCP_SEMIHOST = 0x3f,
33
} RISCVException;
34
35
#define RISCV_EXCP_INT_FLAG 0x80000000
36
--
37
2.45.1
38
39
diff view generated by jsdifflib
New patch
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
4
enabled, will fail with a kernel oops SIGILL right at the start. The
5
reason is that we can't expose zkr without implementing the SEED CSR.
6
Disabling zkr in the guest would be a workaround, but if the KVM doesn't
7
allow it we'll error out and never boot.
8
9
In hindsight this is too strict. If we keep proceeding, despite not
10
disabling the extension in the KVM vcpu, we'll not add the extension in
11
the riscv,isa. The guest kernel will be unaware of the extension, i.e.
12
it doesn't matter if the KVM vcpu has it enabled underneath or not. So
13
it's ok to keep booting in this case.
14
15
Change our current logic to not error out if we fail to disable an
16
extension in kvm_set_one_reg(), but show a warning and keep booting. It
17
is important to throw a warning because we must make the user aware that
18
the extension is still available in the vcpu, meaning that an
19
ill-behaved guest can ignore the riscv,isa settings and use the
20
extension.
21
22
The case we're handling happens with an EINVAL error code. If we fail to
23
disable the extension in KVM for any other reason, error out.
24
25
We'll also keep erroring out when we fail to enable an extension in KVM,
26
since adding the extension in riscv,isa at this point will cause a guest
27
malfunction because the extension isn't enabled in the vcpu.
28
29
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
30
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
31
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
32
Cc: qemu-stable <qemu-stable@nongnu.org>
33
Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
34
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
35
---
36
target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
37
1 file changed, 8 insertions(+), 4 deletions(-)
38
39
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/riscv/kvm/kvm-cpu.c
42
+++ b/target/riscv/kvm/kvm-cpu.c
43
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
44
reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
45
ret = kvm_set_one_reg(cs, id, &reg);
46
if (ret != 0) {
47
- error_report("Unable to %s extension %s in KVM, error %d",
48
- reg ? "enable" : "disable",
49
- multi_ext_cfg->name, ret);
50
- exit(EXIT_FAILURE);
51
+ if (!reg && ret == -EINVAL) {
52
+ warn_report("KVM cannot disable extension %s",
53
+ multi_ext_cfg->name);
54
+ } else {
55
+ error_report("Unable to enable extension %s in KVM, error %d",
56
+ multi_ext_cfg->name, ret);
57
+ exit(EXIT_FAILURE);
58
+ }
59
}
60
}
61
}
62
--
63
2.45.1
diff view generated by jsdifflib
New patch
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
We're not setting (s/m)tval when triggering breakpoints of type 2
4
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5
5.7.12, "Match Control Type 6":
6
7
"The Privileged Spec says that breakpoint exceptions that occur on
8
instruction fetches, loads, or stores update the tval CSR with either
9
zero or the faulting virtual address. The faulting virtual address for
10
an mcontrol6 trigger with action = 0 is the address being accessed and
11
which caused that trigger to fire."
12
13
A similar text is also found in the Debug spec section 5.7.11 w.r.t.
14
mcontrol.
15
16
Note that what we're doing ATM is not violating the spec, but it's
17
simple enough to set mtval/stval and it makes life easier for any
18
software that relies on this info.
19
20
Given that we always use action = 0, save the faulting address for the
21
mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
22
used as as scratch area for traps with address information. 'tval' is
23
then set during riscv_cpu_do_interrupt().
24
25
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
26
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
27
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
28
Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
29
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
30
---
31
target/riscv/cpu_helper.c | 1 +
32
target/riscv/debug.c | 3 +++
33
2 files changed, 4 insertions(+)
34
35
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/cpu_helper.c
38
+++ b/target/riscv/cpu_helper.c
39
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
40
tval = env->bins;
41
break;
42
case RISCV_EXCP_BREAKPOINT:
43
+ tval = env->badaddr;
44
if (cs->watchpoint_hit) {
45
tval = cs->watchpoint_hit->hitaddr;
46
cs->watchpoint_hit = NULL;
47
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/riscv/debug.c
50
+++ b/target/riscv/debug.c
51
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
52
if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
53
/* check U/S/M bit against current privilege level */
54
if ((ctrl >> 3) & BIT(env->priv)) {
55
+ env->badaddr = pc;
56
return true;
57
}
58
}
59
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
60
if (env->virt_enabled) {
61
/* check VU/VS bit against current privilege level */
62
if ((ctrl >> 23) & BIT(env->priv)) {
63
+ env->badaddr = pc;
64
return true;
65
}
66
} else {
67
/* check U/S/M bit against current privilege level */
68
if ((ctrl >> 3) & BIT(env->priv)) {
69
+ env->badaddr = pc;
70
return true;
71
}
72
}
73
--
74
2.45.1
diff view generated by jsdifflib
New patch
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Privileged spec section 4.1.9 mentions:
4
5
"When a trap is taken into S-mode, stval is written with
6
exception-specific information to assist software in handling the trap.
7
(...)
8
9
If stval is written with a nonzero value when a breakpoint,
10
address-misaligned, access-fault, or page-fault exception occurs on an
11
instruction fetch, load, or store, then stval will contain the faulting
12
virtual address."
13
14
A similar text is found for mtval in section 3.1.16.
15
16
Setting mtval/stval in this scenario is optional, but some softwares read
17
these regs when handling ebreaks.
18
19
Write 'badaddr' in all ebreak breakpoints to write the appropriate
20
'tval' during riscv_do_cpu_interrrupt().
21
22
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
23
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
24
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
28
---
29
target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
30
1 file changed, 2 insertions(+)
31
32
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/riscv/insn_trans/trans_privileged.c.inc
35
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
36
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
37
if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
38
generate_exception(ctx, RISCV_EXCP_SEMIHOST);
39
} else {
40
+ tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
41
+ offsetof(CPURISCVState, badaddr));
42
generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
43
}
44
return true;
45
--
46
2.45.1
diff view generated by jsdifflib
1
The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since
1
From: Jason Chien <jason.chien@sifive.com>
2
4.1. It's not commonly used so let's remove support for it.
3
2
3
Add support for Zve32x extension and replace some checks for Zve32f with
4
Zve32x, since Zve32f depends on Zve32x.
5
6
Signed-off-by: Jason Chien <jason.chien@sifive.com>
7
Reviewed-by: Frank Chang <frank.chang@sifive.com>
8
Reviewed-by: Max Chou <max.chou@sifive.com>
9
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
4
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
5
Reviewed-by: Bin Meng <bin.meng@windriver.com>
6
---
12
---
7
docs/system/deprecated.rst | 20 +--
13
target/riscv/cpu_cfg.h | 1 +
8
target/riscv/cpu.h | 1 -
14
target/riscv/cpu.c | 2 ++
9
target/riscv/cpu.c | 2 -
15
target/riscv/cpu_helper.c | 2 +-
10
target/riscv/cpu_helper.c | 82 ++++-------
16
target/riscv/csr.c | 2 +-
11
target/riscv/csr.c | 138 ++++--------------
17
target/riscv/tcg/tcg-cpu.c | 16 ++++++++--------
12
.../riscv/insn_trans/trans_privileged.inc.c | 18 +--
18
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
13
target/riscv/monitor.c | 5 -
19
6 files changed, 15 insertions(+), 12 deletions(-)
14
target/riscv/op_helper.c | 17 +--
15
8 files changed, 73 insertions(+), 210 deletions(-)
16
20
17
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
21
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
18
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
19
--- a/docs/system/deprecated.rst
23
--- a/target/riscv/cpu_cfg.h
20
+++ b/docs/system/deprecated.rst
24
+++ b/target/riscv/cpu_cfg.h
21
@@ -XXX,XX +XXX,XX @@ The ``acl_show``, ``acl_reset``, ``acl_policy``, ``acl_add``, and
25
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
22
``acl_remove`` commands are deprecated with no replacement. Authorization
26
bool ext_zhinx;
23
for VNC should be performed using the pluggable QAuthZ objects.
27
bool ext_zhinxmin;
24
28
bool ext_zve32f;
25
-Guest Emulator ISAs
29
+ bool ext_zve32x;
26
--------------------
30
bool ext_zve64f;
27
-
31
bool ext_zve64d;
28
-RISC-V ISA privledge specification version 1.09.1 (since 4.1)
32
bool ext_zvbb;
29
-'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
30
-
31
-The RISC-V ISA privledge specification version 1.09.1 has been deprecated.
32
-QEMU supports both the newer version 1.10.0 and the ratified version 1.11.0, these
33
-should be used instead of the 1.09.1 version.
34
-
35
System emulator CPUS
36
--------------------
37
38
@@ -XXX,XX +XXX,XX @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfwd_remove`` (removed in 5.0
39
The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and
40
'hostfwd_remove' HMP commands has been replaced by ``netdev_id``.
41
42
+Guest Emulator ISAs
43
+-------------------
44
+
45
+RISC-V ISA privledge specification version 1.09.1 (removed in 5.1)
46
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
47
+
48
+The RISC-V ISA privledge specification version 1.09.1 has been removed.
49
+QEMU supports both the newer version 1.10.0 and the ratified version 1.11.0, these
50
+should be used instead of the 1.09.1 version.
51
+
52
System emulator CPUS
53
--------------------
54
55
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/riscv/cpu.h
58
+++ b/target/riscv/cpu.h
59
@@ -XXX,XX +XXX,XX @@ enum {
60
RISCV_FEATURE_MISA
61
};
62
63
-#define PRIV_VERSION_1_09_1 0x00010901
64
#define PRIV_VERSION_1_10_0 0x00011000
65
#define PRIV_VERSION_1_11_0 0x00011100
66
67
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
33
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
68
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
69
--- a/target/riscv/cpu.c
35
--- a/target/riscv/cpu.c
70
+++ b/target/riscv/cpu.c
36
+++ b/target/riscv/cpu.c
71
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
37
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
72
priv_version = PRIV_VERSION_1_11_0;
38
ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
73
} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
39
ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
74
priv_version = PRIV_VERSION_1_10_0;
40
ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
75
- } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) {
41
+ ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
76
- priv_version = PRIV_VERSION_1_09_1;
42
ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
77
} else {
43
ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
78
error_setg(errp,
44
ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
79
"Unsupported privilege spec version '%s'",
45
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
46
MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
47
MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
48
MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
49
+ MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
50
MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
51
MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
52
MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
80
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
53
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
81
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
82
--- a/target/riscv/cpu_helper.c
55
--- a/target/riscv/cpu_helper.c
83
+++ b/target/riscv/cpu_helper.c
56
+++ b/target/riscv/cpu_helper.c
84
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
57
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
85
mxr = get_field(env->vsstatus, MSTATUS_MXR);
58
*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
86
}
59
*cs_base = 0;
87
60
88
- if (env->priv_ver >= PRIV_VERSION_1_10_0) {
61
- if (cpu->cfg.ext_zve32f) {
89
- if (first_stage == true) {
62
+ if (cpu->cfg.ext_zve32x) {
90
- if (use_background) {
63
/*
91
- base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
64
* If env->vl equals to VLMAX, we can use generic vector operation
92
- vm = get_field(env->vsatp, SATP_MODE);
65
* expanders (GVEC) to accerlate the vector operations.
93
- } else {
94
- base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
95
- vm = get_field(env->satp, SATP_MODE);
96
- }
97
- widened = 0;
98
+ if (first_stage == true) {
99
+ if (use_background) {
100
+ base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
101
+ vm = get_field(env->vsatp, SATP_MODE);
102
} else {
103
- base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
104
- vm = get_field(env->hgatp, HGATP_MODE);
105
- widened = 2;
106
- }
107
- sum = get_field(env->mstatus, MSTATUS_SUM);
108
- switch (vm) {
109
- case VM_1_10_SV32:
110
- levels = 2; ptidxbits = 10; ptesize = 4; break;
111
- case VM_1_10_SV39:
112
- levels = 3; ptidxbits = 9; ptesize = 8; break;
113
- case VM_1_10_SV48:
114
- levels = 4; ptidxbits = 9; ptesize = 8; break;
115
- case VM_1_10_SV57:
116
- levels = 5; ptidxbits = 9; ptesize = 8; break;
117
- case VM_1_10_MBARE:
118
- *physical = addr;
119
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
120
- return TRANSLATE_SUCCESS;
121
- default:
122
- g_assert_not_reached();
123
+ base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
124
+ vm = get_field(env->satp, SATP_MODE);
125
}
126
- } else {
127
widened = 0;
128
- base = (hwaddr)(env->sptbr) << PGSHIFT;
129
- sum = !get_field(env->mstatus, MSTATUS_PUM);
130
- vm = get_field(env->mstatus, MSTATUS_VM);
131
- switch (vm) {
132
- case VM_1_09_SV32:
133
- levels = 2; ptidxbits = 10; ptesize = 4; break;
134
- case VM_1_09_SV39:
135
- levels = 3; ptidxbits = 9; ptesize = 8; break;
136
- case VM_1_09_SV48:
137
- levels = 4; ptidxbits = 9; ptesize = 8; break;
138
- case VM_1_09_MBARE:
139
- *physical = addr;
140
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
141
- return TRANSLATE_SUCCESS;
142
- default:
143
- g_assert_not_reached();
144
- }
145
+ } else {
146
+ base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
147
+ vm = get_field(env->hgatp, HGATP_MODE);
148
+ widened = 2;
149
+ }
150
+ sum = get_field(env->mstatus, MSTATUS_SUM);
151
+ switch (vm) {
152
+ case VM_1_10_SV32:
153
+ levels = 2; ptidxbits = 10; ptesize = 4; break;
154
+ case VM_1_10_SV39:
155
+ levels = 3; ptidxbits = 9; ptesize = 8; break;
156
+ case VM_1_10_SV48:
157
+ levels = 4; ptidxbits = 9; ptesize = 8; break;
158
+ case VM_1_10_SV57:
159
+ levels = 5; ptidxbits = 9; ptesize = 8; break;
160
+ case VM_1_10_MBARE:
161
+ *physical = addr;
162
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
163
+ return TRANSLATE_SUCCESS;
164
+ default:
165
+ g_assert_not_reached();
166
}
167
168
CPUState *cs = env_cpu(env);
169
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
170
int page_fault_exceptions;
171
if (first_stage) {
172
page_fault_exceptions =
173
- (env->priv_ver >= PRIV_VERSION_1_10_0) &&
174
get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
175
!pmp_violation;
176
} else {
177
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
178
}
179
180
s = env->mstatus;
181
- s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
182
- get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv));
183
+ s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
184
s = set_field(s, MSTATUS_SPP, env->priv);
185
s = set_field(s, MSTATUS_SIE, 0);
186
env->mstatus = s;
187
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
188
}
189
190
s = env->mstatus;
191
- s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
192
- get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv));
193
+ s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
194
s = set_field(s, MSTATUS_MPP, env->priv);
195
s = set_field(s, MSTATUS_MIE, 0);
196
env->mstatus = s;
197
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
66
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
198
index XXXXXXX..XXXXXXX 100644
67
index XXXXXXX..XXXXXXX 100644
199
--- a/target/riscv/csr.c
68
--- a/target/riscv/csr.c
200
+++ b/target/riscv/csr.c
69
+++ b/target/riscv/csr.c
201
@@ -XXX,XX +XXX,XX @@ static int ctr(CPURISCVState *env, int csrno)
70
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
71
72
static RISCVException vs(CPURISCVState *env, int csrno)
73
{
74
- if (riscv_cpu_cfg(env)->ext_zve32f) {
75
+ if (riscv_cpu_cfg(env)->ext_zve32x) {
202
#if !defined(CONFIG_USER_ONLY)
76
#if !defined(CONFIG_USER_ONLY)
203
CPUState *cs = env_cpu(env);
77
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
204
RISCVCPU *cpu = RISCV_CPU(cs);
78
return RISCV_EXCP_ILLEGAL_INST;
205
- uint32_t ctr_en = ~0u;
79
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
206
207
if (!cpu->cfg.ext_counters) {
208
/* The Counters extensions is not enabled */
209
return -1;
210
}
211
-
212
- /*
213
- * The counters are always enabled at run time on newer priv specs, as the
214
- * CSR has changed from controlling that the counters can be read to
215
- * controlling that the counters increment.
216
- */
217
- if (env->priv_ver > PRIV_VERSION_1_09_1) {
218
- return 0;
219
- }
220
-
221
- if (env->priv < PRV_M) {
222
- ctr_en &= env->mcounteren;
223
- }
224
- if (env->priv < PRV_S) {
225
- ctr_en &= env->scounteren;
226
- }
227
- if (!(ctr_en & (1u << (csrno & 31)))) {
228
- return -1;
229
- }
230
#endif
231
return 0;
232
}
233
@@ -XXX,XX +XXX,XX @@ static const target_ulong delegable_excps =
234
(1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
235
(1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
236
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
237
-static const target_ulong sstatus_v1_9_mask = SSTATUS_SIE | SSTATUS_SPIE |
238
- SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
239
- SSTATUS_SUM | SSTATUS_SD;
240
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
241
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
242
SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
243
@@ -XXX,XX +XXX,XX @@ static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
244
static const target_ulong vsip_writable_mask = MIP_VSSIP;
245
246
#if defined(TARGET_RISCV32)
247
-static const char valid_vm_1_09[16] = {
248
- [VM_1_09_MBARE] = 1,
249
- [VM_1_09_SV32] = 1,
250
-};
251
static const char valid_vm_1_10[16] = {
252
[VM_1_10_MBARE] = 1,
253
[VM_1_10_SV32] = 1
254
};
255
#elif defined(TARGET_RISCV64)
256
-static const char valid_vm_1_09[16] = {
257
- [VM_1_09_MBARE] = 1,
258
- [VM_1_09_SV39] = 1,
259
- [VM_1_09_SV48] = 1,
260
-};
261
static const char valid_vm_1_10[16] = {
262
[VM_1_10_MBARE] = 1,
263
[VM_1_10_SV39] = 1,
264
@@ -XXX,XX +XXX,XX @@ static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
265
266
static int validate_vm(CPURISCVState *env, target_ulong vm)
267
{
268
- return (env->priv_ver >= PRIV_VERSION_1_10_0) ?
269
- valid_vm_1_10[vm & 0xf] : valid_vm_1_09[vm & 0xf];
270
+ return valid_vm_1_10[vm & 0xf];
271
}
272
273
static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
274
@@ -XXX,XX +XXX,XX @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
275
int dirty;
276
277
/* flush tlb on mstatus fields that affect VM */
278
- if (env->priv_ver <= PRIV_VERSION_1_09_1) {
279
- if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP |
280
- MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) {
281
- tlb_flush(env_cpu(env));
282
- }
283
- mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
284
- MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
285
- MSTATUS_MPP | MSTATUS_MXR |
286
- (validate_vm(env, get_field(val, MSTATUS_VM)) ?
287
- MSTATUS_VM : 0);
288
+ if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
289
+ MSTATUS_MPRV | MSTATUS_SUM)) {
290
+ tlb_flush(env_cpu(env));
291
}
292
- if (env->priv_ver >= PRIV_VERSION_1_10_0) {
293
- if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
294
- MSTATUS_MPRV | MSTATUS_SUM)) {
295
- tlb_flush(env_cpu(env));
296
- }
297
- mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
298
- MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
299
- MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
300
- MSTATUS_TW;
301
+ mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
302
+ MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
303
+ MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
304
+ MSTATUS_TW;
305
#if defined(TARGET_RISCV64)
306
- /*
307
- * RV32: MPV and MTL are not in mstatus. The current plan is to
308
- * add them to mstatush. For now, we just don't support it.
309
- */
310
- mask |= MSTATUS_MTL | MSTATUS_MPV;
311
+ /*
312
+ * RV32: MPV and MTL are not in mstatus. The current plan is to
313
+ * add them to mstatush. For now, we just don't support it.
314
+ */
315
+ mask |= MSTATUS_MTL | MSTATUS_MPV;
316
#endif
317
- }
318
319
mstatus = (mstatus & ~mask) | (val & mask);
320
321
@@ -XXX,XX +XXX,XX @@ static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
322
323
static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val)
324
{
325
- if (env->priv_ver < PRIV_VERSION_1_10_0) {
326
- return -1;
327
- }
328
*val = env->mcounteren;
329
return 0;
330
}
331
332
static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
333
{
334
- if (env->priv_ver < PRIV_VERSION_1_10_0) {
335
- return -1;
336
- }
337
env->mcounteren = val;
338
return 0;
339
}
340
@@ -XXX,XX +XXX,XX @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
341
/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
342
static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
343
{
344
- if (env->priv_ver > PRIV_VERSION_1_09_1
345
- && env->priv_ver < PRIV_VERSION_1_11_0) {
346
+ if (env->priv_ver < PRIV_VERSION_1_11_0) {
347
return -1;
348
}
349
*val = env->mcounteren;
350
@@ -XXX,XX +XXX,XX @@ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
351
/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
352
static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
353
{
354
- if (env->priv_ver > PRIV_VERSION_1_09_1
355
- && env->priv_ver < PRIV_VERSION_1_11_0) {
356
+ if (env->priv_ver < PRIV_VERSION_1_11_0) {
357
return -1;
358
}
359
env->mcounteren = val;
360
return 0;
361
}
362
363
-static int read_mucounteren(CPURISCVState *env, int csrno, target_ulong *val)
364
-{
365
- if (env->priv_ver > PRIV_VERSION_1_09_1) {
366
- return -1;
367
- }
368
- *val = env->scounteren;
369
- return 0;
370
-}
371
-
372
-static int write_mucounteren(CPURISCVState *env, int csrno, target_ulong val)
373
-{
374
- if (env->priv_ver > PRIV_VERSION_1_09_1) {
375
- return -1;
376
- }
377
- env->scounteren = val;
378
- return 0;
379
-}
380
-
381
/* Machine Trap Handling */
382
static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
383
{
384
@@ -XXX,XX +XXX,XX @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
385
/* Supervisor Trap Setup */
386
static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val)
387
{
388
- target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ?
389
- sstatus_v1_10_mask : sstatus_v1_9_mask);
390
+ target_ulong mask = (sstatus_v1_10_mask);
391
*val = env->mstatus & mask;
392
return 0;
393
}
394
395
static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
396
{
397
- target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ?
398
- sstatus_v1_10_mask : sstatus_v1_9_mask);
399
+ target_ulong mask = (sstatus_v1_10_mask);
400
target_ulong newval = (env->mstatus & ~mask) | (val & mask);
401
return write_mstatus(env, CSR_MSTATUS, newval);
402
}
403
@@ -XXX,XX +XXX,XX @@ static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
404
405
static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val)
406
{
407
- if (env->priv_ver < PRIV_VERSION_1_10_0) {
408
- return -1;
409
- }
410
*val = env->scounteren;
411
return 0;
412
}
413
414
static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val)
415
{
416
- if (env->priv_ver < PRIV_VERSION_1_10_0) {
417
- return -1;
418
- }
419
env->scounteren = val;
420
return 0;
421
}
422
@@ -XXX,XX +XXX,XX @@ static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
423
{
424
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
425
*val = 0;
426
- } else if (env->priv_ver >= PRIV_VERSION_1_10_0) {
427
- if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
428
- return -1;
429
- } else {
430
- *val = env->satp;
431
- }
432
+ return 0;
433
+ }
434
+
435
+ if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
436
+ return -1;
437
} else {
438
- *val = env->sptbr;
439
+ *val = env->satp;
440
}
441
+
442
return 0;
443
}
444
445
@@ -XXX,XX +XXX,XX @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
446
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
447
return 0;
448
}
449
- if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) {
450
- tlb_flush(env_cpu(env));
451
- env->sptbr = val & (((target_ulong)
452
- 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1);
453
- }
454
- if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
455
- validate_vm(env, get_field(val, SATP_MODE)) &&
456
+ if (validate_vm(env, get_field(val, SATP_MODE)) &&
457
((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
458
{
459
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
460
@@ -XXX,XX +XXX,XX @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
461
[CSR_MSTATUSH] = { any, read_mstatush, write_mstatush },
462
#endif
463
464
- /* Legacy Counter Setup (priv v1.9.1) */
465
- [CSR_MUCOUNTEREN] = { any, read_mucounteren, write_mucounteren },
466
[CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren },
467
468
/* Machine Trap Handling */
469
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c
470
index XXXXXXX..XXXXXXX 100644
80
index XXXXXXX..XXXXXXX 100644
471
--- a/target/riscv/insn_trans/trans_privileged.inc.c
81
--- a/target/riscv/tcg/tcg-cpu.c
472
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
82
+++ b/target/riscv/tcg/tcg-cpu.c
473
@@ -XXX,XX +XXX,XX @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
83
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
474
static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
475
{
476
#ifndef CONFIG_USER_ONLY
477
- if (ctx->priv_ver >= PRIV_VERSION_1_10_0) {
478
- gen_helper_tlb_flush(cpu_env);
479
- return true;
480
- }
481
+ gen_helper_tlb_flush(cpu_env);
482
+ return true;
483
#endif
484
return false;
485
}
486
487
static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
488
{
489
-#ifndef CONFIG_USER_ONLY
490
- if (ctx->priv_ver <= PRIV_VERSION_1_09_1) {
491
- gen_helper_tlb_flush(cpu_env);
492
- return true;
493
- }
494
-#endif
495
return false;
496
}
497
498
static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
499
{
500
#ifndef CONFIG_USER_ONLY
501
- if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
502
- has_ext(ctx, RVH)) {
503
+ if (has_ext(ctx, RVH)) {
504
/* Hpervisor extensions exist */
505
/*
506
* if (env->priv == PRV_M ||
507
@@ -XXX,XX +XXX,XX @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
508
static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a)
509
{
510
#ifndef CONFIG_USER_ONLY
511
- if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
512
- has_ext(ctx, RVH)) {
513
+ if (has_ext(ctx, RVH)) {
514
/* Hpervisor extensions exist */
515
/*
516
* if (env->priv == PRV_M ||
517
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
518
index XXXXXXX..XXXXXXX 100644
519
--- a/target/riscv/monitor.c
520
+++ b/target/riscv/monitor.c
521
@@ -XXX,XX +XXX,XX @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
522
return;
84
return;
523
}
85
}
524
86
525
- if (env->priv_ver < PRIV_VERSION_1_10_0) {
87
- if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
526
- monitor_printf(mon, "Privileged mode < 1.10 unsupported\n");
88
- error_setg(errp, "Zve32f/Zve64f extensions require F extension");
527
- return;
89
- return;
528
- }
90
+ /* The Zve32f extension depends on the Zve32x extension */
529
-
91
+ if (cpu->cfg.ext_zve32f) {
530
if (!(env->satp & SATP_MODE)) {
92
+ if (!riscv_has_ext(env, RVF)) {
531
monitor_printf(mon, "No translation or protection\n");
93
+ error_setg(errp, "Zve32f/Zve64f extensions require F extension");
94
+ return;
95
+ }
96
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
97
}
98
99
if (cpu->cfg.ext_zvfh) {
100
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
101
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
102
}
103
104
- /*
105
- * In principle Zve*x would also suffice here, were they supported
106
- * in qemu
107
- */
108
if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
109
cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
110
- cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
111
+ cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
112
error_setg(errp,
113
"Vector crypto extensions require V or Zve* extensions");
532
return;
114
return;
533
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
115
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
534
index XXXXXXX..XXXXXXX 100644
116
index XXXXXXX..XXXXXXX 100644
535
--- a/target/riscv/op_helper.c
117
--- a/target/riscv/insn_trans/trans_rvv.c.inc
536
+++ b/target/riscv/op_helper.c
118
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
537
@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
119
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
538
riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
120
{
121
TCGv s1, dst;
122
123
- if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
124
+ if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
125
return false;
539
}
126
}
540
127
541
- if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
128
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
542
- get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
129
{
543
+ if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
130
TCGv dst;
544
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
131
132
- if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
133
+ if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
134
return false;
545
}
135
}
546
136
547
@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
548
} else {
549
prev_priv = get_field(mstatus, MSTATUS_SPP);
550
551
- mstatus = set_field(mstatus,
552
- env->priv_ver >= PRIV_VERSION_1_10_0 ?
553
- MSTATUS_SIE : MSTATUS_UIE << prev_priv,
554
- get_field(mstatus, MSTATUS_SPIE));
555
+ mstatus = set_field(mstatus, MSTATUS_SIE,
556
+ get_field(mstatus, MSTATUS_SPIE));
557
mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
558
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
559
env->mstatus = mstatus;
560
@@ -XXX,XX +XXX,XX @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
561
target_ulong mstatus = env->mstatus;
562
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
563
target_ulong prev_virt = MSTATUS_MPV_ISSET(env);
564
- mstatus = set_field(mstatus,
565
- env->priv_ver >= PRIV_VERSION_1_10_0 ?
566
- MSTATUS_MIE : MSTATUS_UIE << prev_priv,
567
- get_field(mstatus, MSTATUS_MPIE));
568
+ mstatus = set_field(mstatus, MSTATUS_MIE,
569
+ get_field(mstatus, MSTATUS_MPIE));
570
mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
571
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
572
#ifdef TARGET_RISCV32
573
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
574
CPUState *cs = env_cpu(env);
575
576
if ((env->priv == PRV_S &&
577
- env->priv_ver >= PRIV_VERSION_1_10_0 &&
578
get_field(env->mstatus, MSTATUS_TW)) ||
579
riscv_cpu_virt_enabled(env)) {
580
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
581
@@ -XXX,XX +XXX,XX @@ void helper_tlb_flush(CPURISCVState *env)
582
CPUState *cs = env_cpu(env);
583
if (!(env->priv >= PRV_S) ||
584
(env->priv == PRV_S &&
585
- env->priv_ver >= PRIV_VERSION_1_10_0 &&
586
get_field(env->mstatus, MSTATUS_TVM))) {
587
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
588
} else {
589
--
137
--
590
2.26.2
138
2.45.1
591
592
diff view generated by jsdifflib
New patch
1
From: Jason Chien <jason.chien@sifive.com>
1
2
3
Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
4
enabling Zve64x enables Zve32x according to their dependency.
5
6
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
7
Signed-off-by: Jason Chien <jason.chien@sifive.com>
8
Reviewed-by: Frank Chang <frank.chang@sifive.com>
9
Reviewed-by: Max Chou <max.chou@sifive.com>
10
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/cpu_cfg.h | 1 +
15
target/riscv/cpu.c | 2 ++
16
target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
17
3 files changed, 14 insertions(+), 6 deletions(-)
18
19
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu_cfg.h
22
+++ b/target/riscv/cpu_cfg.h
23
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
24
bool ext_zve32x;
25
bool ext_zve64f;
26
bool ext_zve64d;
27
+ bool ext_zve64x;
28
bool ext_zvbb;
29
bool ext_zvbc;
30
bool ext_zvkb;
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/cpu.c
34
+++ b/target/riscv/cpu.c
35
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
36
ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
37
ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
38
ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
39
+ ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
40
ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
41
ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
42
ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
43
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
44
MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
45
MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
46
MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
47
+ MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
48
MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
49
MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
50
MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
51
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/riscv/tcg/tcg-cpu.c
54
+++ b/target/riscv/tcg/tcg-cpu.c
55
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
56
57
/* The Zve64d extension depends on the Zve64f extension */
58
if (cpu->cfg.ext_zve64d) {
59
+ if (!riscv_has_ext(env, RVD)) {
60
+ error_setg(errp, "Zve64d/V extensions require D extension");
61
+ return;
62
+ }
63
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
64
}
65
66
- /* The Zve64f extension depends on the Zve32f extension */
67
+ /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
68
if (cpu->cfg.ext_zve64f) {
69
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
70
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
71
}
72
73
- if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
74
- error_setg(errp, "Zve64d/V extensions require D extension");
75
- return;
76
+ /* The Zve64x extension depends on the Zve32x extension */
77
+ if (cpu->cfg.ext_zve64x) {
78
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
79
}
80
81
/* The Zve32f extension depends on the Zve32x extension */
82
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
83
return;
84
}
85
86
- if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
87
+ if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
88
error_setg(
89
errp,
90
- "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
91
+ "Zvbc and Zvknhb extensions require V or Zve64x extensions");
92
return;
93
}
94
95
--
96
2.45.1
diff view generated by jsdifflib
New patch
1
From: Jason Chien <jason.chien@sifive.com>
1
2
3
In current implementation, the gdbstub allows reading vector registers
4
only if V extension is supported. However, all vector extensions and
5
vector crypto extensions have the vector registers and they all depend
6
on Zve32x. The gdbstub should check for Zve32x instead.
7
8
Signed-off-by: Jason Chien <jason.chien@sifive.com>
9
Reviewed-by: Frank Chang <frank.chang@sifive.com>
10
Reviewed-by: Max Chou <max.chou@sifive.com>
11
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/gdbstub.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/gdbstub.c
20
+++ b/target/riscv/gdbstub.c
21
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
22
gdb_find_static_feature("riscv-32bit-fpu.xml"),
23
0);
24
}
25
- if (env->misa_ext & RVV) {
26
+ if (cpu->cfg.ext_zve32x) {
27
gdb_register_coprocessor(cs, riscv_gdb_get_vector,
28
riscv_gdb_set_vector,
29
ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
30
--
31
2.45.1
diff view generated by jsdifflib
New patch
1
From: Huang Tao <eric.huang@linux.alibaba.com>
1
2
3
In RVV and vcrypto instructions, the masked and tail elements are set to 1s
4
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
5
agnostic policy.
6
7
However, this function can't deal the big endian situation. This patch fixes
8
the problem by adding handling of such case.
9
10
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
11
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
14
Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
18
1 file changed, 22 insertions(+)
19
20
diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/riscv/vector_internals.c
23
+++ b/target/riscv/vector_internals.c
24
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
25
if (tot - cnt == 0) {
26
return ;
27
}
28
+
29
+ if (HOST_BIG_ENDIAN) {
30
+ /*
31
+ * Deal the situation when the elements are insdie
32
+ * only one uint64 block including setting the
33
+ * masked-off element.
34
+ */
35
+ if (((tot - 1) ^ cnt) < 8) {
36
+ memset(base + H1(tot - 1), -1, tot - cnt);
37
+ return;
38
+ }
39
+ /*
40
+ * Otherwise, at least cross two uint64_t blocks.
41
+ * Set first unaligned block.
42
+ */
43
+ if (cnt % 8 != 0) {
44
+ uint32_t j = ROUND_UP(cnt, 8);
45
+ memset(base + H1(j - 1), -1, j - cnt);
46
+ cnt = j;
47
+ }
48
+ /* Set other 64bit aligend blocks */
49
+ }
50
memset(base + cnt, -1, tot - cnt);
51
}
52
53
--
54
2.45.1
diff view generated by jsdifflib
New patch
1
From: Yangyu Chen <cyy@cyyself.name>
1
2
3
This code has a typo that writes zvkb to zvkg, causing users can't
4
enable zvkb through the config. This patch gets this fixed.
5
6
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
7
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
8
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Max Chou <max.chou@sifive.com>
11
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
12
Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
16
target/riscv/cpu.c | 2 +-
17
1 file changed, 1 insertion(+), 1 deletion(-)
18
19
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu.c
22
+++ b/target/riscv/cpu.c
23
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
24
/* Vector cryptography extensions */
25
MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
26
MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
27
- MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
28
+ MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
29
MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
30
MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
31
MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
32
--
33
2.45.1
34
35
diff view generated by jsdifflib
1
The ISA specific Spike machines have been deprecated in QEMU since 4.1,
1
From: Huang Tao <eric.huang@linux.alibaba.com>
2
let's finally remove them.
3
2
3
In this patch, we modify the decoder to be a freely composable data
4
structure instead of a hardcoded one. It can be dynamically builded up
5
according to the extensions.
6
This approach has several benefits:
7
1. Provides support for heterogeneous cpu architectures. As we add decoder in
8
RISCVCPU, each cpu can have their own decoder, and the decoders can be
9
different due to cpu's features.
10
2. Improve the decoding efficiency. We run the guard_func to see if the decoder
11
can be added to the dynamic_decoder when building up the decoder. Therefore,
12
there is no need to run the guard_func when decoding each instruction. It can
13
improve the decoding efficiency
14
3. For vendor or dynamic cpus, it allows them to customize their own decoder
15
functions to improve decoding efficiency, especially when vendor-defined
16
instruction sets increase. Because of dynamic building up, it can skip the other
17
decoder guard functions when decoding.
18
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
19
overhead for users that don't need this particular vendor decoder.
20
21
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
22
Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
23
Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
26
Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
4
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Bin Meng <bin.meng@windriver.com>
7
Reviewed-by: Thomas Huth <thuth@redhat.com>
8
---
28
---
9
docs/system/deprecated.rst | 17 +--
29
target/riscv/cpu.h | 1 +
10
include/hw/riscv/spike.h | 6 +-
30
target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
11
hw/riscv/spike.c | 217 -------------------------------------
31
target/riscv/cpu.c | 1 +
12
3 files changed, 12 insertions(+), 228 deletions(-)
32
target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
33
target/riscv/translate.c | 31 +++++++++++++++----------------
34
5 files changed, 47 insertions(+), 16 deletions(-)
13
35
14
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
36
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
15
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/deprecated.rst
38
--- a/target/riscv/cpu.h
17
+++ b/docs/system/deprecated.rst
39
+++ b/target/riscv/cpu.h
18
@@ -XXX,XX +XXX,XX @@ This machine has been renamed ``fuloong2e``.
40
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
19
These machine types are very old and likely can not be used for live migration
41
uint32_t pmu_avail_ctrs;
20
from old QEMU versions anymore. A newer machine type should be used instead.
42
/* Mapping of events to counters */
21
43
GHashTable *pmu_event_ctr_map;
22
-``spike_v1.9.1`` and ``spike_v1.10`` (since 4.1)
44
+ const GPtrArray *decoders;
23
-''''''''''''''''''''''''''''''''''''''''''''''''
45
};
24
-
46
25
-The version specific Spike machines have been deprecated in favour of the
47
/**
26
-generic ``spike`` machine. If you need to specify an older version of the RISC-V
48
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
27
-spec you can use the ``-cpu rv64gcsu,priv_spec=v1.9.1`` command line argument.
49
index XXXXXXX..XXXXXXX 100644
28
-
50
--- a/target/riscv/tcg/tcg-cpu.h
29
Device options
51
+++ b/target/riscv/tcg/tcg-cpu.h
30
--------------
52
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
31
53
void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
32
@@ -XXX,XX +XXX,XX @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfwd_remove`` (removed in 5.0
54
bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
33
The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and
55
34
'hostfwd_remove' HMP commands has been replaced by ``netdev_id``.
56
+struct DisasContext;
35
57
+struct RISCVCPUConfig;
36
+System emulator machines
58
+typedef struct RISCVDecoder {
37
+------------------------
59
+ bool (*guard_func)(const struct RISCVCPUConfig *);
60
+ bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
61
+} RISCVDecoder;
38
+
62
+
39
+``spike_v1.9.1`` and ``spike_v1.10`` (removed in 5.1)
63
+typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
40
+'''''''''''''''''''''''''''''''''''''''''''''''''''''
41
+
64
+
42
+The version specific Spike machines have been removed in favour of the
65
+extern const size_t decoder_table_size;
43
+generic ``spike`` machine. If you need to specify an older version of the RISC-V
44
+spec you can use the ``-cpu rv64gcsu,priv_spec=v1.10.0`` command line argument.
45
+
66
+
46
Related binaries
67
+extern const RISCVDecoder decoder_table[];
47
----------------
68
+
48
69
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
49
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
70
+
71
#endif
72
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
50
index XXXXXXX..XXXXXXX 100644
73
index XXXXXXX..XXXXXXX 100644
51
--- a/include/hw/riscv/spike.h
74
--- a/target/riscv/cpu.c
52
+++ b/include/hw/riscv/spike.h
75
+++ b/target/riscv/cpu.c
53
@@ -XXX,XX +XXX,XX @@ enum {
76
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
54
};
77
error_propagate(errp, local_err);
55
78
return;
56
#if defined(TARGET_RISCV32)
79
}
57
-#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
80
+ riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
58
-#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
81
} else if (kvm_enabled()) {
59
+#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32
82
riscv_kvm_cpu_finalize_features(cpu, &local_err);
60
#elif defined(TARGET_RISCV64)
83
if (local_err != NULL) {
61
-#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1
84
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
62
-#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
63
+#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64
64
#endif
65
66
#endif
67
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
68
index XXXXXXX..XXXXXXX 100644
85
index XXXXXXX..XXXXXXX 100644
69
--- a/hw/riscv/spike.c
86
--- a/target/riscv/tcg/tcg-cpu.c
70
+++ b/hw/riscv/spike.c
87
+++ b/target/riscv/tcg/tcg-cpu.c
71
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
88
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
72
false);
89
}
73
}
90
}
74
91
75
-static void spike_v1_10_0_board_init(MachineState *machine)
92
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
76
-{
93
+{
77
- const struct MemmapEntry *memmap = spike_memmap;
94
+ GPtrArray *dynamic_decoders;
78
-
95
+ dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
79
- SpikeState *s = g_new0(SpikeState, 1);
96
+ for (size_t i = 0; i < decoder_table_size; ++i) {
80
- MemoryRegion *system_memory = get_system_memory();
97
+ if (decoder_table[i].guard_func &&
81
- MemoryRegion *main_mem = g_new(MemoryRegion, 1);
98
+ decoder_table[i].guard_func(&cpu->cfg)) {
82
- MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
99
+ g_ptr_array_add(dynamic_decoders,
83
- int i;
100
+ (gpointer)decoder_table[i].riscv_cpu_decode_fn);
84
- unsigned int smp_cpus = machine->smp.cpus;
101
+ }
85
-
102
+ }
86
- if (!qtest_enabled()) {
103
+
87
- info_report("The Spike v1.10.0 machine has been deprecated. "
104
+ cpu->decoders = dynamic_decoders;
88
- "Please use the generic spike machine and specify the ISA "
105
+}
89
- "versions using -cpu.");
106
+
90
- }
107
bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
91
-
108
{
92
- /* Initialize SOC */
109
return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
93
- object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
110
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
94
- TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
111
index XXXXXXX..XXXXXXX 100644
95
- object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type",
112
--- a/target/riscv/translate.c
96
- &error_abort);
113
+++ b/target/riscv/translate.c
97
- object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
114
@@ -XXX,XX +XXX,XX @@
98
- &error_abort);
115
#include "exec/helper-info.c.inc"
99
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
116
#undef HELPER_H
100
- &error_abort);
117
101
-
118
+#include "tcg/tcg-cpu.h"
102
- /* register system main memory (actual RAM) */
119
+
103
- memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
120
/* global register indices */
104
- machine->ram_size, &error_fatal);
121
static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
105
- memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
122
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
106
- main_mem);
123
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
107
-
124
/* FRM is known to contain a valid value. */
108
- /* create device tree */
125
bool frm_valid;
109
- create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
126
bool insn_start_updated;
110
-
127
+ const GPtrArray *decoders;
111
- /* boot rom */
128
} DisasContext;
112
- memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
129
113
- memmap[SPIKE_MROM].size, &error_fatal);
130
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
114
- memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
131
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
115
- mask_rom);
132
return (first_word & 3) == 3 ? 4 : 2;
116
-
133
}
117
- if (machine->kernel_filename) {
134
118
- riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
135
+const RISCVDecoder decoder_table[] = {
119
- }
136
+ { always_true_p, decode_insn32 },
120
-
137
+ { has_xthead_p, decode_xthead},
121
- /* reset vector */
138
+ { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
122
- uint32_t reset_vec[8] = {
139
+};
123
- 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
140
+
124
- 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
141
+const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
125
- 0xf1402573, /* csrr a0, mhartid */
142
+
126
-#if defined(TARGET_RISCV32)
143
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
127
- 0x0182a283, /* lw t0, 24(t0) */
144
{
128
-#elif defined(TARGET_RISCV64)
145
- /*
129
- 0x0182b283, /* ld t0, 24(t0) */
146
- * A table with predicate (i.e., guard) functions and decoder functions
130
-#endif
147
- * that are tested in-order until a decoder matches onto the opcode.
131
- 0x00028067, /* jr t0 */
148
- */
132
- 0x00000000,
149
- static const struct {
133
- memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */
150
- bool (*guard_func)(const RISCVCPUConfig *);
134
- 0x00000000,
151
- bool (*decode_func)(DisasContext *, uint32_t);
135
- /* dtb: */
152
- } decoders[] = {
153
- { always_true_p, decode_insn32 },
154
- { has_xthead_p, decode_xthead },
155
- { has_XVentanaCondOps_p, decode_XVentanaCodeOps },
136
- };
156
- };
137
-
157
-
138
- /* copy in the reset vector in little_endian byte order */
158
ctx->virt_inst_excp = false;
139
- for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
159
ctx->cur_insn_len = insn_len(opcode);
140
- reset_vec[i] = cpu_to_le32(reset_vec[i]);
160
/* Check for compressed insn */
141
- }
161
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
142
- rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
162
ctx->base.pc_next + 2));
143
- memmap[SPIKE_MROM].base, &address_space_memory);
163
ctx->opcode = opcode32;
144
-
164
145
- /* copy in the device tree */
165
- for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
146
- if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
166
- if (decoders[i].guard_func(ctx->cfg_ptr) &&
147
- memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
167
- decoders[i].decode_func(ctx, opcode32)) {
148
- error_report("not enough space to store device-tree");
168
+ for (guint i = 0; i < ctx->decoders->len; ++i) {
149
- exit(1);
169
+ riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
150
- }
170
+ if (func(ctx, opcode32)) {
151
- qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
171
return;
152
- rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
172
}
153
- memmap[SPIKE_MROM].base + sizeof(reset_vec),
173
}
154
- &address_space_memory);
174
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
155
-
175
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
156
- /* initialize HTIF using symbols found in load_kernel */
176
ctx->zero = tcg_constant_tl(0);
157
- htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
177
ctx->virt_inst_excp = false;
158
-
178
+ ctx->decoders = cpu->decoders;
159
- /* Core Local Interruptor (timer and IPI) */
160
- sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
161
- smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
162
- false);
163
-}
164
-
165
-static void spike_v1_09_1_board_init(MachineState *machine)
166
-{
167
- const struct MemmapEntry *memmap = spike_memmap;
168
-
169
- SpikeState *s = g_new0(SpikeState, 1);
170
- MemoryRegion *system_memory = get_system_memory();
171
- MemoryRegion *main_mem = g_new(MemoryRegion, 1);
172
- MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
173
- int i;
174
- unsigned int smp_cpus = machine->smp.cpus;
175
-
176
- if (!qtest_enabled()) {
177
- info_report("The Spike v1.09.1 machine has been deprecated. "
178
- "Please use the generic spike machine and specify the ISA "
179
- "versions using -cpu.");
180
- }
181
-
182
- /* Initialize SOC */
183
- object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
184
- TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
185
- object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type",
186
- &error_abort);
187
- object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
188
- &error_abort);
189
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
190
- &error_abort);
191
-
192
- /* register system main memory (actual RAM) */
193
- memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
194
- machine->ram_size, &error_fatal);
195
- memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
196
- main_mem);
197
-
198
- /* boot rom */
199
- memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
200
- memmap[SPIKE_MROM].size, &error_fatal);
201
- memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
202
- mask_rom);
203
-
204
- if (machine->kernel_filename) {
205
- riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
206
- }
207
-
208
- /* reset vector */
209
- uint32_t reset_vec[8] = {
210
- 0x297 + memmap[SPIKE_DRAM].base - memmap[SPIKE_MROM].base, /* lui */
211
- 0x00028067, /* jump to DRAM_BASE */
212
- 0x00000000, /* reserved */
213
- memmap[SPIKE_MROM].base + sizeof(reset_vec), /* config string pointer */
214
- 0, 0, 0, 0 /* trap vector */
215
- };
216
-
217
- /* part one of config string - before memory size specified */
218
- const char *config_string_tmpl =
219
- "platform {\n"
220
- " vendor ucb;\n"
221
- " arch spike;\n"
222
- "};\n"
223
- "rtc {\n"
224
- " addr 0x%" PRIx64 "x;\n"
225
- "};\n"
226
- "ram {\n"
227
- " 0 {\n"
228
- " addr 0x%" PRIx64 "x;\n"
229
- " size 0x%" PRIx64 "x;\n"
230
- " };\n"
231
- "};\n"
232
- "core {\n"
233
- " 0" " {\n"
234
- " " "0 {\n"
235
- " isa %s;\n"
236
- " timecmp 0x%" PRIx64 "x;\n"
237
- " ipi 0x%" PRIx64 "x;\n"
238
- " };\n"
239
- " };\n"
240
- "};\n";
241
-
242
- /* build config string with supplied memory size */
243
- char *isa = riscv_isa_string(&s->soc.harts[0]);
244
- char *config_string = g_strdup_printf(config_string_tmpl,
245
- (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE,
246
- (uint64_t)memmap[SPIKE_DRAM].base,
247
- (uint64_t)ram_size, isa,
248
- (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIMECMP_BASE,
249
- (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_SIP_BASE);
250
- g_free(isa);
251
- size_t config_string_len = strlen(config_string);
252
-
253
- /* copy in the reset vector in little_endian byte order */
254
- for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
255
- reset_vec[i] = cpu_to_le32(reset_vec[i]);
256
- }
257
- rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
258
- memmap[SPIKE_MROM].base, &address_space_memory);
259
-
260
- /* copy in the config string */
261
- rom_add_blob_fixed_as("mrom.reset", config_string, config_string_len,
262
- memmap[SPIKE_MROM].base + sizeof(reset_vec),
263
- &address_space_memory);
264
-
265
- /* initialize HTIF using symbols found in load_kernel */
266
- htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
267
-
268
- /* Core Local Interruptor (timer and IPI) */
269
- sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
270
- smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
271
- false);
272
-
273
- g_free(config_string);
274
-}
275
-
276
-static void spike_v1_09_1_machine_init(MachineClass *mc)
277
-{
278
- mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)";
279
- mc->init = spike_v1_09_1_board_init;
280
- mc->max_cpus = 1;
281
-}
282
-
283
-static void spike_v1_10_0_machine_init(MachineClass *mc)
284
-{
285
- mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)";
286
- mc->init = spike_v1_10_0_board_init;
287
- mc->max_cpus = 1;
288
-}
289
-
290
static void spike_machine_init(MachineClass *mc)
291
{
292
mc->desc = "RISC-V Spike Board";
293
@@ -XXX,XX +XXX,XX @@ static void spike_machine_init(MachineClass *mc)
294
mc->default_cpu_type = SPIKE_V1_10_0_CPU;
295
}
179
}
296
180
297
-DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
181
static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
298
-DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
299
DEFINE_MACHINE("spike", spike_machine_init)
300
--
182
--
301
2.26.2
183
2.45.1
302
303
diff view generated by jsdifflib
1
From: Christoph Müllner <christoph.muellner@vrull.eu>
2
3
The th.sxstatus CSR can be used to identify available custom extension
4
on T-Head CPUs. The CSR is documented here:
5
https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
6
7
An important property of this patch is, that the th.sxstatus MAEE field
8
is not set (indicating that XTheadMae is not available).
9
XTheadMae is a memory attribute extension (similar to Svpbmt) which is
10
implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
11
in PTEs that are marked as reserved. QEMU maintainers prefer to not
12
implement XTheadMae, so we need give kernels a mechanism to identify
13
if XTheadMae is available in a system or not. And this patch introduces
14
this mechanism in QEMU in a way that's compatible with real HW
15
(i.e., probing the th.sxstatus.MAEE bit).
16
17
Further context can be found on the list:
18
https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html
19
20
Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
21
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
22
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
23
Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
---
25
---
4
docs/system/deprecated.rst | 33 ++++++++++++++++++---------------
26
MAINTAINERS | 1 +
5
target/riscv/cpu.h | 7 -------
27
target/riscv/cpu.h | 3 ++
6
target/riscv/cpu.c | 28 ----------------------------
28
target/riscv/cpu.c | 1 +
7
tests/qtest/machine-none-test.c | 4 ++--
29
target/riscv/th_csr.c | 79 ++++++++++++++++++++++++++++++++++++++++
8
4 files changed, 20 insertions(+), 52 deletions(-)
30
target/riscv/meson.build | 1 +
31
5 files changed, 85 insertions(+)
32
create mode 100644 target/riscv/th_csr.c
9
33
10
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
34
diff --git a/MAINTAINERS b/MAINTAINERS
11
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
12
--- a/docs/system/deprecated.rst
36
--- a/MAINTAINERS
13
+++ b/docs/system/deprecated.rst
37
+++ b/MAINTAINERS
14
@@ -XXX,XX +XXX,XX @@ should be used instead of the 1.09.1 version.
38
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
15
System emulator CPUS
39
S: Supported
16
--------------------
40
F: target/riscv/insn_trans/trans_xthead.c.inc
17
41
F: target/riscv/xthead*.decode
18
-RISC-V ISA CPUs (since 4.1)
42
+F: target/riscv/th_*
19
-'''''''''''''''''''''''''''
43
F: disas/riscv-xthead*
20
-
44
21
-The RISC-V cpus with the ISA version in the CPU name have been depcreated. The
45
RISC-V XVentanaCondOps extension
22
-four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.1`` and
23
-``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``priv_spec``
24
-option when using the ``rv32`` or ``rv64`` CPUs.
25
-
26
-RISC-V ISA CPUs (since 4.1)
27
-'''''''''''''''''''''''''''
28
-
29
-The RISC-V no MMU cpus have been depcreated. The two CPUs: ``rv32imacu-nommu`` and
30
-``rv64imacu-nommu`` should no longer be used. Instead the MMU status can be specified
31
-via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
32
-
33
``compat`` property of server class POWER CPUs (since 5.0)
34
''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
35
36
@@ -XXX,XX +XXX,XX @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfwd_remove`` (removed in 5.0
37
The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and
38
'hostfwd_remove' HMP commands has been replaced by ``netdev_id``.
39
40
+System emulator CPUS
41
+--------------------
42
+
43
+RISC-V ISA Specific CPUs (removed in 5.1)
44
+'''''''''''''''''''''''''''''''''''''''''
45
+
46
+The RISC-V cpus with the ISA version in the CPU name have been removed. The
47
+four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.1`` and
48
+``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``priv_spec``
49
+option when using the ``rv32`` or ``rv64`` CPUs.
50
+
51
+RISC-V no MMU CPUs (removed in 5.1)
52
+'''''''''''''''''''''''''''''''''''
53
+
54
+The RISC-V no MMU cpus have been removed. The two CPUs: ``rv32imacu-nommu`` and
55
+``rv64imacu-nommu`` can no longer be used. Instead the MMU status can be specified
56
+via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
57
+
58
System emulator machines
59
------------------------
60
61
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
46
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
62
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
63
--- a/target/riscv/cpu.h
48
--- a/target/riscv/cpu.h
64
+++ b/target/riscv/cpu.h
49
+++ b/target/riscv/cpu.h
65
@@ -XXX,XX +XXX,XX @@
50
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
66
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
51
uint8_t satp_mode_max_from_map(uint32_t map);
67
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
52
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
68
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
53
69
-/* Deprecated */
54
+/* Implemented in th_csr.c */
70
-#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
55
+void th_register_custom_csrs(RISCVCPU *cpu);
71
-#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
56
+
72
-#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
57
#endif /* RISCV_CPU_H */
73
-#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
74
-#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
75
-#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
76
77
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
78
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
79
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
58
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
80
index XXXXXXX..XXXXXXX 100644
59
index XXXXXXX..XXXXXXX 100644
81
--- a/target/riscv/cpu.c
60
--- a/target/riscv/cpu.c
82
+++ b/target/riscv/cpu.c
61
+++ b/target/riscv/cpu.c
83
@@ -XXX,XX +XXX,XX @@ static void riscv_base32_cpu_init(Object *obj)
62
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
84
set_misa(env, 0);
63
cpu->cfg.mvendorid = THEAD_VENDOR_ID;
85
}
64
#ifndef CONFIG_USER_ONLY
86
65
set_satp_mode_max_supported(cpu, VM_1_10_SV39);
87
-static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
66
+ th_register_custom_csrs(cpu);
88
-{
89
- CPURISCVState *env = &RISCV_CPU(obj)->env;
90
- set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
91
- set_priv_version(env, PRIV_VERSION_1_09_1);
92
- set_resetvec(env, DEFAULT_RSTVEC);
93
- set_feature(env, RISCV_FEATURE_MMU);
94
- set_feature(env, RISCV_FEATURE_PMP);
95
-}
96
-
97
static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
98
{
99
CPURISCVState *env = &RISCV_CPU(obj)->env;
100
@@ -XXX,XX +XXX,XX @@ static void riscv_base64_cpu_init(Object *obj)
101
set_misa(env, 0);
102
}
103
104
-static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
105
-{
106
- CPURISCVState *env = &RISCV_CPU(obj)->env;
107
- set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
108
- set_priv_version(env, PRIV_VERSION_1_09_1);
109
- set_resetvec(env, DEFAULT_RSTVEC);
110
- set_feature(env, RISCV_FEATURE_MMU);
111
- set_feature(env, RISCV_FEATURE_PMP);
112
-}
113
-
114
static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
115
{
116
CPURISCVState *env = &RISCV_CPU(obj)->env;
117
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
118
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
119
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
120
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
121
- /* Depreacted */
122
- DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
123
- DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
124
- DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init)
125
#elif defined(TARGET_RISCV64)
126
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
127
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
128
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
129
- /* Deprecated */
130
- DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
131
- DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
132
- DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init)
133
#endif
67
#endif
134
};
68
135
69
/* inherited from parent obj via riscv_cpu_init() */
136
diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-test.c
70
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
71
new file mode 100644
72
index XXXXXXX..XXXXXXX
73
--- /dev/null
74
+++ b/target/riscv/th_csr.c
75
@@ -XXX,XX +XXX,XX @@
76
+/*
77
+ * T-Head-specific CSRs.
78
+ *
79
+ * Copyright (c) 2024 VRULL GmbH
80
+ *
81
+ * This program is free software; you can redistribute it and/or modify it
82
+ * under the terms and conditions of the GNU General Public License,
83
+ * version 2 or later, as published by the Free Software Foundation.
84
+ *
85
+ * This program is distributed in the hope it will be useful, but WITHOUT
86
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
87
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
88
+ * more details.
89
+ *
90
+ * You should have received a copy of the GNU General Public License along with
91
+ * this program. If not, see <http://www.gnu.org/licenses/>.
92
+ */
93
+
94
+#include "qemu/osdep.h"
95
+#include "cpu.h"
96
+#include "cpu_vendorid.h"
97
+
98
+#define CSR_TH_SXSTATUS 0x5c0
99
+
100
+/* TH_SXSTATUS bits */
101
+#define TH_SXSTATUS_UCME BIT(16)
102
+#define TH_SXSTATUS_MAEE BIT(21)
103
+#define TH_SXSTATUS_THEADISAEE BIT(22)
104
+
105
+typedef struct {
106
+ int csrno;
107
+ int (*insertion_test)(RISCVCPU *cpu);
108
+ riscv_csr_operations csr_ops;
109
+} riscv_csr;
110
+
111
+static RISCVException smode(CPURISCVState *env, int csrno)
112
+{
113
+ if (riscv_has_ext(env, RVS)) {
114
+ return RISCV_EXCP_NONE;
115
+ }
116
+
117
+ return RISCV_EXCP_ILLEGAL_INST;
118
+}
119
+
120
+static int test_thead_mvendorid(RISCVCPU *cpu)
121
+{
122
+ if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
123
+ return -1;
124
+ }
125
+
126
+ return 0;
127
+}
128
+
129
+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
130
+ target_ulong *val)
131
+{
132
+ /* We don't set MAEE here, because QEMU does not implement MAEE. */
133
+ *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
134
+ return RISCV_EXCP_NONE;
135
+}
136
+
137
+static riscv_csr th_csr_list[] = {
138
+ {
139
+ .csrno = CSR_TH_SXSTATUS,
140
+ .insertion_test = test_thead_mvendorid,
141
+ .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
142
+ }
143
+};
144
+
145
+void th_register_custom_csrs(RISCVCPU *cpu)
146
+{
147
+ for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
148
+ int csrno = th_csr_list[i].csrno;
149
+ riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
150
+ if (!th_csr_list[i].insertion_test(cpu)) {
151
+ riscv_set_csr_ops(csrno, csr_ops);
152
+ }
153
+ }
154
+}
155
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
137
index XXXXXXX..XXXXXXX 100644
156
index XXXXXXX..XXXXXXX 100644
138
--- a/tests/qtest/machine-none-test.c
157
--- a/target/riscv/meson.build
139
+++ b/tests/qtest/machine-none-test.c
158
+++ b/target/riscv/meson.build
140
@@ -XXX,XX +XXX,XX @@ static struct arch2cpu cpus_map[] = {
159
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
141
{ "xtensa", "dc233c" },
160
'monitor.c',
142
{ "xtensaeb", "fsf" },
161
'machine.c',
143
{ "hppa", "hppa" },
162
'pmu.c',
144
- { "riscv64", "rv64gcsu-v1.10.0" },
163
+ 'th_csr.c',
145
- { "riscv32", "rv32gcsu-v1.9.1" },
164
'time_helper.c',
146
+ { "riscv64", "rv64" },
165
'riscv-qmp-cmds.c',
147
+ { "riscv32", "rv32" },
166
))
148
{ "rx", "rx62n" },
149
};
150
151
--
167
--
152
2.26.2
168
2.45.1
153
169
154
170
diff view generated by jsdifflib
New patch
1
From: Max Chou <max.chou@sifive.com>
1
2
3
According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
4
instructions will be affected by Zvfhmin extension.
5
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
6
conversions of
7
8
* From 1*SEW(16/32) to 2*SEW(32/64)
9
* From 2*SEW(32/64) to 1*SEW(16/32)
10
11
Signed-off-by: Max Chou <max.chou@sifive.com>
12
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
14
Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
18
1 file changed, 18 insertions(+), 2 deletions(-)
19
20
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/riscv/insn_trans/trans_rvv.c.inc
23
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
24
@@ -XXX,XX +XXX,XX @@ static bool require_rvf(DisasContext *s)
25
}
26
}
27
28
+static bool require_rvfmin(DisasContext *s)
29
+{
30
+ if (s->mstatus_fs == EXT_STATUS_DISABLED) {
31
+ return false;
32
+ }
33
+
34
+ switch (s->sew) {
35
+ case MO_16:
36
+ return s->cfg_ptr->ext_zvfhmin;
37
+ case MO_32:
38
+ return s->cfg_ptr->ext_zve32f;
39
+ default:
40
+ return false;
41
+ }
42
+}
43
+
44
static bool require_scale_rvf(DisasContext *s)
45
{
46
if (s->mstatus_fs == EXT_STATUS_DISABLED) {
47
@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvfmin(DisasContext *s)
48
}
49
50
switch (s->sew) {
51
- case MO_8:
52
- return s->cfg_ptr->ext_zvfhmin;
53
case MO_16:
54
return s->cfg_ptr->ext_zve32f;
55
case MO_32:
56
@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
57
static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
58
{
59
return opfv_widen_check(s, a) &&
60
+ require_rvfmin(s) &&
61
require_scale_rvfmin(s) &&
62
(s->sew != MO_8);
63
}
64
@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
65
static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
66
{
67
return opfv_narrow_check(s, a) &&
68
+ require_rvfmin(s) &&
69
require_scale_rvfmin(s) &&
70
(s->sew != MO_8);
71
}
72
--
73
2.45.1
diff view generated by jsdifflib
1
Update the -bios deprecation documentation to describe the new
1
From: Max Chou <max.chou@sifive.com>
2
behaviour.
3
2
3
The require_scale_rvf function only checks the double width operator for
4
the vector floating point widen instructions, so most of the widen
5
checking functions need to add require_rvf for single width operator.
6
7
The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
8
integer to double width float, so the opfxv_widen_check function doesn’t
9
need require_rvf for the single width operator(integer).
10
11
Signed-off-by: Max Chou <max.chou@sifive.com>
12
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
14
Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
4
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
5
Reviewed-by: Bin Meng <bin.meng@windriver.com>
6
---
16
---
7
docs/system/deprecated.rst | 28 +++++++++++++---------------
17
target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
8
1 file changed, 13 insertions(+), 15 deletions(-)
18
1 file changed, 5 insertions(+)
9
19
10
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
20
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
11
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
12
--- a/docs/system/deprecated.rst
22
--- a/target/riscv/insn_trans/trans_rvv.c.inc
13
+++ b/docs/system/deprecated.rst
23
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
14
@@ -XXX,XX +XXX,XX @@ the backing storage specified with ``-mem-path`` can actually provide
24
@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
15
the guest RAM configured with ``-m`` and QEMU will fail to start up if
25
static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
16
RAM allocation is unsuccessful.
26
{
17
27
return require_rvv(s) &&
18
-RISC-V ``-bios`` (since 4.1)
28
+ require_rvf(s) &&
19
+RISC-V ``-bios`` (since 5.1)
29
require_scale_rvf(s) &&
20
''''''''''''''''''''''''''''
30
(s->sew != MO_8) &&
21
31
vext_check_isa_ill(s) &&
22
QEMU 4.1 introduced support for the -bios option in QEMU for RISC-V for the
32
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
23
-RISC-V virt machine and sifive_u machine.
33
static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
24
-
34
{
25
-QEMU 4.1 has no changes to the default behaviour to avoid breakages. This
35
return require_rvv(s) &&
26
-default will change in a future QEMU release, so please prepare now. All users
36
+ require_rvf(s) &&
27
-of the virt or sifive_u machine must change their command line usage.
37
require_scale_rvf(s) &&
28
-
38
(s->sew != MO_8) &&
29
-QEMU 4.1 has three options, please migrate to one of these three:
39
vext_check_isa_ill(s) &&
30
- 1. ``-bios none`` - This is the current default behavior if no -bios option
40
@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
31
- is included. QEMU will not automatically load any firmware. It is up
41
static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
32
+RISC-V virt machine and sifive_u machine. QEMU 4.1 had no changes to the
42
{
33
+default behaviour to avoid breakages.
43
return require_rvv(s) &&
34
+
44
+ require_rvf(s) &&
35
+QEMU 5.1 changes the default behaviour from ``-bios none`` to ``-bios default``.
45
require_scale_rvf(s) &&
36
+
46
(s->sew != MO_8) &&
37
+QEMU 5.1 has three options:
47
vext_check_isa_ill(s) &&
38
+ 1. ``-bios default`` - This is the current default behavior if no -bios option
48
@@ -XXX,XX +XXX,XX @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
39
+ is included. This option will load the default OpenSBI firmware automatically.
49
static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
40
+ The firmware is included with the QEMU release and no user interaction is
50
{
41
+ required. All a user needs to do is specify the kernel they want to boot
51
return require_rvv(s) &&
42
+ with the -kernel option
52
+ require_rvf(s) &&
43
+ 2. ``-bios none`` - QEMU will not automatically load any firmware. It is up
53
require_scale_rvf(s) &&
44
to the user to load all the images they need.
54
(s->sew != MO_8) &&
45
- 2. ``-bios default`` - In a future QEMU release this will become the default
55
vext_check_isa_ill(s) &&
46
- behaviour if no -bios option is specified. This option will load the
56
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
47
- default OpenSBI firmware automatically. The firmware is included with
57
static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
48
- the QEMU release and no user interaction is required. All a user needs
58
{
49
- to do is specify the kernel they want to boot with the -kernel option
59
return reduction_widen_check(s, a) &&
50
3. ``-bios <file>`` - Tells QEMU to load the specified file as the firmwrae.
60
+ require_rvf(s) &&
51
61
require_scale_rvf(s) &&
52
``-tb-size`` option (since 5.0)
62
(s->sew != MO_8);
63
}
53
--
64
--
54
2.26.2
65
2.45.1
55
66
56
67
diff view generated by jsdifflib
New patch
1
From: Max Chou <max.chou@sifive.com>
1
2
3
The opfv_narrow_check needs to check the single width float operator by
4
require_rvf.
5
6
Signed-off-by: Max Chou <max.chou@sifive.com>
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Cc: qemu-stable <qemu-stable@nongnu.org>
9
Message-ID: <20240322092600.1198921-4-max.chou@sifive.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
13
1 file changed, 1 insertion(+)
14
15
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/insn_trans/trans_rvv.c.inc
18
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
19
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
20
static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
21
{
22
return opfv_narrow_check(s, a) &&
23
+ require_rvf(s) &&
24
require_scale_rvf(s) &&
25
(s->sew != MO_8);
26
}
27
--
28
2.45.1
diff view generated by jsdifflib
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Max Chou <max.chou@sifive.com>
2
2
3
To keep consistency with the machine* functions, remove the riscv_
3
If the checking functions check both the single and double width
4
prefix of the soc* functions.
4
operators at the same time, then the single width operator checking
5
functions (require_rvf[min]) will check whether the SEW is 8.
5
6
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Signed-off-by: Max Chou <max.chou@sifive.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Cc: qemu-stable <qemu-stable@nongnu.org>
9
Message-id: 1590072147-13035-1-git-send-email-bmeng.cn@gmail.com
10
Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
10
Message-Id: <1590072147-13035-1-git-send-email-bmeng.cn@gmail.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
12
---
13
hw/riscv/sifive_u.c | 24 ++++++++++++------------
13
target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
14
1 file changed, 12 insertions(+), 12 deletions(-)
14
1 file changed, 4 insertions(+), 12 deletions(-)
15
15
16
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
16
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/riscv/sifive_u.c
18
--- a/target/riscv/insn_trans/trans_rvv.c.inc
19
+++ b/hw/riscv/sifive_u.c
19
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
20
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init_register_types(void)
20
@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
21
21
return require_rvv(s) &&
22
type_init(sifive_u_machine_init_register_types)
22
require_rvf(s) &&
23
23
require_scale_rvf(s) &&
24
-static void riscv_sifive_u_soc_init(Object *obj)
24
- (s->sew != MO_8) &&
25
+static void sifive_u_soc_instance_init(Object *obj)
25
vext_check_isa_ill(s) &&
26
vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
27
}
28
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
29
return require_rvv(s) &&
30
require_rvf(s) &&
31
require_scale_rvf(s) &&
32
- (s->sew != MO_8) &&
33
vext_check_isa_ill(s) &&
34
vext_check_ds(s, a->rd, a->rs2, a->vm);
35
}
36
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
37
return require_rvv(s) &&
38
require_rvf(s) &&
39
require_scale_rvf(s) &&
40
- (s->sew != MO_8) &&
41
vext_check_isa_ill(s) &&
42
vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
43
}
44
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
45
return require_rvv(s) &&
46
require_rvf(s) &&
47
require_scale_rvf(s) &&
48
- (s->sew != MO_8) &&
49
vext_check_isa_ill(s) &&
50
vext_check_dd(s, a->rd, a->rs2, a->vm);
51
}
52
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
26
{
53
{
27
MachineState *ms = MACHINE(qdev_get_machine());
54
return opfv_widen_check(s, a) &&
28
SiFiveUSoCState *s = RISCV_U_SOC(obj);
55
require_rvfmin(s) &&
29
@@ -XXX,XX +XXX,XX @@ static void riscv_sifive_u_soc_init(Object *obj)
56
- require_scale_rvfmin(s) &&
30
TYPE_CADENCE_GEM);
57
- (s->sew != MO_8);
58
+ require_scale_rvfmin(s);
31
}
59
}
32
60
33
-static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
61
#define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \
34
+static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
62
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
35
{
63
{
36
MachineState *ms = MACHINE(qdev_get_machine());
64
return opfv_narrow_check(s, a) &&
37
SiFiveUSoCState *s = RISCV_U_SOC(dev);
65
require_rvfmin(s) &&
38
@@ -XXX,XX +XXX,XX @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
66
- require_scale_rvfmin(s) &&
39
memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
67
- (s->sew != MO_8);
68
+ require_scale_rvfmin(s);
40
}
69
}
41
70
42
-static Property riscv_sifive_u_soc_props[] = {
71
static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
43
+static Property sifive_u_soc_props[] = {
44
DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
45
DEFINE_PROP_END_OF_LIST()
46
};
47
48
-static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
49
+static void sifive_u_soc_class_init(ObjectClass *oc, void *data)
50
{
72
{
51
DeviceClass *dc = DEVICE_CLASS(oc);
73
return opfv_narrow_check(s, a) &&
52
74
require_rvf(s) &&
53
- device_class_set_props(dc, riscv_sifive_u_soc_props);
75
- require_scale_rvf(s) &&
54
- dc->realize = riscv_sifive_u_soc_realize;
76
- (s->sew != MO_8);
55
+ device_class_set_props(dc, sifive_u_soc_props);
77
+ require_scale_rvf(s);
56
+ dc->realize = sifive_u_soc_realize;
57
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
58
dc->user_creatable = false;
59
}
78
}
60
79
61
-static const TypeInfo riscv_sifive_u_soc_type_info = {
80
#define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \
62
+static const TypeInfo sifive_u_soc_type_info = {
81
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
63
.name = TYPE_RISCV_U_SOC,
64
.parent = TYPE_DEVICE,
65
.instance_size = sizeof(SiFiveUSoCState),
66
- .instance_init = riscv_sifive_u_soc_init,
67
- .class_init = riscv_sifive_u_soc_class_init,
68
+ .instance_init = sifive_u_soc_instance_init,
69
+ .class_init = sifive_u_soc_class_init,
70
};
71
72
-static void riscv_sifive_u_soc_register_types(void)
73
+static void sifive_u_soc_register_types(void)
74
{
82
{
75
- type_register_static(&riscv_sifive_u_soc_type_info);
83
return reduction_widen_check(s, a) &&
76
+ type_register_static(&sifive_u_soc_type_info);
84
require_rvf(s) &&
85
- require_scale_rvf(s) &&
86
- (s->sew != MO_8);
87
+ require_scale_rvf(s);
77
}
88
}
78
89
79
-type_init(riscv_sifive_u_soc_register_types)
90
GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
80
+type_init(sifive_u_soc_register_types)
81
--
91
--
82
2.26.2
92
2.45.1
83
84
diff view generated by jsdifflib
New patch
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
raise_mmu_exception(), as is today, is prioritizing guest page faults by
4
checking first if virt_enabled && !first_stage, and then considering the
5
regular inst/load/store faults.
6
7
There's no mention in the spec about guest page fault being a higher
8
priority that PMP faults. In fact, privileged spec section 3.7.1 says:
9
10
"Attempting to fetch an instruction from a PMP region that does not have
11
execute permissions raises an instruction access-fault exception.
12
Attempting to execute a load or load-reserved instruction which accesses
13
a physical address within a PMP region without read permissions raises a
14
load access-fault exception. Attempting to execute a store,
15
store-conditional, or AMO instruction which accesses a physical address
16
within a PMP region without write permissions raises a store
17
access-fault exception."
18
19
So, in fact, we're doing it wrong - PMP faults should always be thrown,
20
regardless of also being a first or second stage fault.
21
22
The way riscv_cpu_tlb_fill() and get_physical_address() work is
23
adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
24
reflected in the 'pmp_violation' flag. What we need is to change
25
raise_mmu_exception() to prioritize it.
26
27
Reported-by: Joseph Chan <jchan@ventanamicro.com>
28
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
29
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
30
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
31
Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
32
Cc: qemu-stable <qemu-stable@nongnu.org>
33
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
34
---
35
target/riscv/cpu_helper.c | 22 ++++++++++++----------
36
1 file changed, 12 insertions(+), 10 deletions(-)
37
38
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/riscv/cpu_helper.c
41
+++ b/target/riscv/cpu_helper.c
42
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
43
44
switch (access_type) {
45
case MMU_INST_FETCH:
46
- if (env->virt_enabled && !first_stage) {
47
+ if (pmp_violation) {
48
+ cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
49
+ } else if (env->virt_enabled && !first_stage) {
50
cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
51
} else {
52
- cs->exception_index = pmp_violation ?
53
- RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
54
+ cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
55
}
56
break;
57
case MMU_DATA_LOAD:
58
- if (two_stage && !first_stage) {
59
+ if (pmp_violation) {
60
+ cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
61
+ } else if (two_stage && !first_stage) {
62
cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
63
} else {
64
- cs->exception_index = pmp_violation ?
65
- RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
66
+ cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
67
}
68
break;
69
case MMU_DATA_STORE:
70
- if (two_stage && !first_stage) {
71
+ if (pmp_violation) {
72
+ cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
73
+ } else if (two_stage && !first_stage) {
74
cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
75
} else {
76
- cs->exception_index = pmp_violation ?
77
- RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
78
- RISCV_EXCP_STORE_PAGE_FAULT;
79
+ cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
80
}
81
break;
82
default:
83
--
84
2.45.1
diff view generated by jsdifflib
New patch
1
From: Alexei Filippov <alexei.filippov@syntacore.com>
1
2
3
Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
4
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
5
translation part, mtval2 will be set in case of successes 2 stage translation but
6
failed pmp check.
7
8
In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
9
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
10
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
11
page-fault is taken into M-mode, mtval2 is written with either zero or guest
12
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
13
is set to zero...*
14
15
Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
16
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
18
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
19
Cc: qemu-stable <qemu-stable@nongnu.org>
20
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
21
---
22
target/riscv/cpu_helper.c | 12 ++++++------
23
1 file changed, 6 insertions(+), 6 deletions(-)
24
25
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/riscv/cpu_helper.c
28
+++ b/target/riscv/cpu_helper.c
29
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
30
__func__, pa, ret, prot_pmp, tlb_size);
31
32
prot &= prot_pmp;
33
- }
34
-
35
- if (ret != TRANSLATE_SUCCESS) {
36
+ } else {
37
/*
38
* Guest physical address translation failed, this is a HS
39
* level exception
40
*/
41
first_stage_error = false;
42
- env->guest_phys_fault_addr = (im_address |
43
- (address &
44
- (TARGET_PAGE_SIZE - 1))) >> 2;
45
+ if (ret != TRANSLATE_PMP_FAIL) {
46
+ env->guest_phys_fault_addr = (im_address |
47
+ (address &
48
+ (TARGET_PAGE_SIZE - 1))) >> 2;
49
+ }
50
}
51
}
52
} else {
53
--
54
2.45.1
diff view generated by jsdifflib
New patch
1
From: Rob Bradford <rbradford@rivosinc.com>
1
2
3
This extension has now been ratified:
4
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
5
removed.
6
7
Since this is now a ratified extension add it to the list of extensions
8
included in the "max" CPU variant.
9
10
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
11
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
15
Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
18
target/riscv/cpu.c | 2 +-
19
target/riscv/tcg/tcg-cpu.c | 2 +-
20
2 files changed, 2 insertions(+), 2 deletions(-)
21
22
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/cpu.c
25
+++ b/target/riscv/cpu.c
26
@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
27
MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
28
MISA_EXT_INFO(RVV, "v", "Vector operations"),
29
MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
30
- MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
31
+ MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
32
};
33
34
static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
35
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/tcg/tcg-cpu.c
38
+++ b/target/riscv/tcg/tcg-cpu.c
39
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
40
const RISCVCPUMultiExtConfig *prop;
41
42
/* Enable RVG, RVJ and RVV that are disabled by default */
43
- riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
44
+ riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
45
46
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
47
isa_ext_update_enabled(cpu, prop->offset, true);
48
--
49
2.45.1
diff view generated by jsdifflib
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Alistair Francis <alistair23@gmail.com>
2
2
3
Remove the riscv_ prefix of the machine* functions.
3
When running the instruction
4
4
5
Signed-off-by: Bin Meng <bin.meng@windriver.com>
5
```
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
cbo.flush 0(x0)
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
```
8
Message-id: 1590072147-13035-2-git-send-email-bmeng.cn@gmail.com
8
9
Message-Id: <1590072147-13035-2-git-send-email-bmeng.cn@gmail.com>
9
QEMU would segfault.
10
11
The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
12
allocated.
13
14
In order to fix this let's use the existing get_address()
15
helper. This also has the benefit of performing pointer mask
16
calculations on the address specified in rs1.
17
18
The pointer masking specificiation specifically states:
19
20
"""
21
Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
22
"""
23
24
So this is the correct behaviour and we previously have been incorrectly
25
not masking the address.
26
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
28
Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
29
Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
30
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
31
Cc: qemu-stable <qemu-stable@nongnu.org>
32
Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
33
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
34
---
12
hw/riscv/virt.c | 20 ++++++++++----------
35
target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
13
1 file changed, 10 insertions(+), 10 deletions(-)
36
1 file changed, 12 insertions(+), 4 deletions(-)
14
37
15
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
38
diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
16
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/riscv/virt.c
40
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
18
+++ b/hw/riscv/virt.c
41
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
19
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
42
@@ -XXX,XX +XXX,XX @@
20
return dev;
43
static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
44
{
45
REQUIRE_ZICBOM(ctx);
46
- gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
47
+ TCGv src = get_address(ctx, a->rs1, 0);
48
+
49
+ gen_helper_cbo_clean_flush(tcg_env, src);
50
return true;
21
}
51
}
22
52
23
-static void riscv_virt_board_init(MachineState *machine)
53
static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
24
+static void virt_machine_init(MachineState *machine)
25
{
54
{
26
const struct MemmapEntry *memmap = virt_memmap;
55
REQUIRE_ZICBOM(ctx);
27
RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
56
- gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
28
@@ -XXX,XX +XXX,XX @@ static void riscv_virt_board_init(MachineState *machine)
57
+ TCGv src = get_address(ctx, a->rs1, 0);
29
g_free(plic_hart_config);
58
+
59
+ gen_helper_cbo_clean_flush(tcg_env, src);
60
return true;
30
}
61
}
31
62
32
-static void riscv_virt_machine_instance_init(Object *obj)
63
static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
33
+static void virt_machine_instance_init(Object *obj)
34
{
64
{
65
REQUIRE_ZICBOM(ctx);
66
- gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
67
+ TCGv src = get_address(ctx, a->rs1, 0);
68
+
69
+ gen_helper_cbo_inval(tcg_env, src);
70
return true;
35
}
71
}
36
72
37
-static void riscv_virt_machine_class_init(ObjectClass *oc, void *data)
73
static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
38
+static void virt_machine_class_init(ObjectClass *oc, void *data)
39
{
74
{
40
MachineClass *mc = MACHINE_CLASS(oc);
75
REQUIRE_ZICBOZ(ctx);
41
76
- gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
42
mc->desc = "RISC-V VirtIO board";
77
+ TCGv src = get_address(ctx, a->rs1, 0);
43
- mc->init = riscv_virt_board_init;
78
+
44
+ mc->init = virt_machine_init;
79
+ gen_helper_cbo_zero(tcg_env, src);
45
mc->max_cpus = 8;
80
return true;
46
mc->default_cpu_type = VIRT_CPU;
47
mc->pci_allow_0_address = true;
48
}
81
}
49
50
-static const TypeInfo riscv_virt_machine_typeinfo = {
51
+static const TypeInfo virt_machine_typeinfo = {
52
.name = MACHINE_TYPE_NAME("virt"),
53
.parent = TYPE_MACHINE,
54
- .class_init = riscv_virt_machine_class_init,
55
- .instance_init = riscv_virt_machine_instance_init,
56
+ .class_init = virt_machine_class_init,
57
+ .instance_init = virt_machine_instance_init,
58
.instance_size = sizeof(RISCVVirtState),
59
};
60
61
-static void riscv_virt_machine_init_register_types(void)
62
+static void virt_machine_init_register_types(void)
63
{
64
- type_register_static(&riscv_virt_machine_typeinfo);
65
+ type_register_static(&virt_machine_typeinfo);
66
}
67
68
-type_init(riscv_virt_machine_init_register_types)
69
+type_init(virt_machine_init_register_types)
70
--
82
--
71
2.26.2
83
2.45.1
72
73
diff view generated by jsdifflib
New patch
1
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
1
2
3
In AIA spec, each hart (or each hart within a group) has a unique hart
4
number to locate the memory pages of interrupt files in the address
5
space. The number of bits required to represent any hart number is equal
6
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
7
groups.
8
9
However, if the largest hart number among groups is a power of 2, QEMU
10
will pass an inaccurate hart-index-bit setting to Linux. For example, when
11
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
12
to represent 4 harts, but we passes 3 to Linux. The code needs to be
13
updated to ensure accurate hart-index-bit settings.
14
15
Additionally, a Linux patch[1] is necessary to correctly recover the hart
16
index when the guest OS has only 1 hart, where the hart-index-bit is 0.
17
18
[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
19
20
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
21
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
22
Cc: qemu-stable <qemu-stable@nongnu.org>
23
Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
25
---
26
target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
27
1 file changed, 8 insertions(+), 1 deletion(-)
28
29
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/riscv/kvm/kvm-cpu.c
32
+++ b/target/riscv/kvm/kvm-cpu.c
33
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
34
}
35
}
36
37
- hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
38
+
39
+ if (max_hart_per_socket > 1) {
40
+ max_hart_per_socket--;
41
+ hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
42
+ } else {
43
+ hart_bits = 0;
44
+ }
45
+
46
ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
47
KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
48
&hart_bits, true, NULL);
49
--
50
2.45.1
diff view generated by jsdifflib
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
We only ship plain binary bios images in the QEMU source. With Spike
3
Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
4
machine that uses ELF images as the default bios, running QEMU test
4
in bytes, when in this context we want 'reg_width' as the length in
5
will complain hence let's suppress the error report for QEMU testing.
5
bits.
6
6
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Fix 'reg_width' back to the value in bits like 7cb59921c05a
8
Reviewed-by: Anup Patel <anup@brainfault.org>
8
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
9
Message-Id: <1588348254-7241-6-git-send-email-bmeng.cn@gmail.com>
9
beforehand.
10
11
While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
12
clarity about what the variable represents. 'bitsize' is also used in
13
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
14
gdb_feature_builder_append_reg().
15
16
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
17
Cc: Alex Bennée <alex.bennee@linaro.org>
18
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
19
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
20
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
21
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
22
Acked-by: Alex Bennée <alex.bennee@linaro.org>
23
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
24
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
25
Cc: qemu-stable <qemu-stable@nongnu.org>
26
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
28
---
12
hw/riscv/boot.c | 14 +++++++++++---
29
target/riscv/gdbstub.c | 6 +++---
13
1 file changed, 11 insertions(+), 3 deletions(-)
30
1 file changed, 3 insertions(+), 3 deletions(-)
14
31
15
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
32
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
16
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/riscv/boot.c
34
--- a/target/riscv/gdbstub.c
18
+++ b/hw/riscv/boot.c
35
+++ b/target/riscv/gdbstub.c
19
@@ -XXX,XX +XXX,XX @@ char *riscv_find_firmware(const char *firmware_filename)
36
@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
20
37
static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
21
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename);
38
{
22
if (filename == NULL) {
39
RISCVCPU *cpu = RISCV_CPU(cs);
23
- error_report("Unable to load the RISC-V firmware \"%s\"",
40
- int reg_width = cpu->cfg.vlenb;
24
- firmware_filename);
41
+ int bitsize = cpu->cfg.vlenb << 3;
25
- exit(1);
42
GDBFeatureBuilder builder;
26
+ if (!qtest_enabled()) {
43
int i;
27
+ /*
44
28
+ * We only ship plain binary bios images in the QEMU source.
45
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
29
+ * With Spike machine that uses ELF images as the default bios,
46
30
+ * running QEMU test will complain hence let's suppress the error
47
/* First define types and totals in a whole VL */
31
+ * report for QEMU testing.
48
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
32
+ */
49
- int count = reg_width / vec_lanes[i].size;
33
+ error_report("Unable to load the RISC-V firmware \"%s\"",
50
+ int count = bitsize / vec_lanes[i].size;
34
+ firmware_filename);
51
gdb_feature_builder_append_tag(
35
+ exit(1);
52
&builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
36
+ }
53
vec_lanes[i].id, vec_lanes[i].gdb_type, count);
54
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
55
/* Define vector registers */
56
for (i = 0; i < 32; i++) {
57
gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
58
- reg_width, i, "riscv_vector", "vector");
59
+ bitsize, i, "riscv_vector", "vector");
37
}
60
}
38
61
39
return filename;
62
gdb_feature_builder_end(&builder);
40
--
63
--
41
2.26.2
64
2.45.1
42
65
43
66
diff view generated by jsdifflib
New patch
1
From: Alistair Francis <alistair23@gmail.com>
1
2
3
Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
4
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
5
CSRs are part of the disassembly.
6
7
Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Fixes: ea10325917 ("RISC-V Disassembler")
10
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Cc: qemu-stable <qemu-stable@nongnu.org>
12
Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
16
1 file changed, 64 insertions(+), 1 deletion(-)
17
18
diff --git a/disas/riscv.c b/disas/riscv.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/disas/riscv.c
21
+++ b/disas/riscv.c
22
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
23
case 0x0383: return "mibound";
24
case 0x0384: return "mdbase";
25
case 0x0385: return "mdbound";
26
- case 0x03a0: return "pmpcfg3";
27
+ case 0x03a0: return "pmpcfg0";
28
+ case 0x03a1: return "pmpcfg1";
29
+ case 0x03a2: return "pmpcfg2";
30
+ case 0x03a3: return "pmpcfg3";
31
+ case 0x03a4: return "pmpcfg4";
32
+ case 0x03a5: return "pmpcfg5";
33
+ case 0x03a6: return "pmpcfg6";
34
+ case 0x03a7: return "pmpcfg7";
35
+ case 0x03a8: return "pmpcfg8";
36
+ case 0x03a9: return "pmpcfg9";
37
+ case 0x03aa: return "pmpcfg10";
38
+ case 0x03ab: return "pmpcfg11";
39
+ case 0x03ac: return "pmpcfg12";
40
+ case 0x03ad: return "pmpcfg13";
41
+ case 0x03ae: return "pmpcfg14";
42
+ case 0x03af: return "pmpcfg15";
43
case 0x03b0: return "pmpaddr0";
44
case 0x03b1: return "pmpaddr1";
45
case 0x03b2: return "pmpaddr2";
46
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
47
case 0x03bd: return "pmpaddr13";
48
case 0x03be: return "pmpaddr14";
49
case 0x03bf: return "pmpaddr15";
50
+ case 0x03c0: return "pmpaddr16";
51
+ case 0x03c1: return "pmpaddr17";
52
+ case 0x03c2: return "pmpaddr18";
53
+ case 0x03c3: return "pmpaddr19";
54
+ case 0x03c4: return "pmpaddr20";
55
+ case 0x03c5: return "pmpaddr21";
56
+ case 0x03c6: return "pmpaddr22";
57
+ case 0x03c7: return "pmpaddr23";
58
+ case 0x03c8: return "pmpaddr24";
59
+ case 0x03c9: return "pmpaddr25";
60
+ case 0x03ca: return "pmpaddr26";
61
+ case 0x03cb: return "pmpaddr27";
62
+ case 0x03cc: return "pmpaddr28";
63
+ case 0x03cd: return "pmpaddr29";
64
+ case 0x03ce: return "pmpaddr30";
65
+ case 0x03cf: return "pmpaddr31";
66
+ case 0x03d0: return "pmpaddr32";
67
+ case 0x03d1: return "pmpaddr33";
68
+ case 0x03d2: return "pmpaddr34";
69
+ case 0x03d3: return "pmpaddr35";
70
+ case 0x03d4: return "pmpaddr36";
71
+ case 0x03d5: return "pmpaddr37";
72
+ case 0x03d6: return "pmpaddr38";
73
+ case 0x03d7: return "pmpaddr39";
74
+ case 0x03d8: return "pmpaddr40";
75
+ case 0x03d9: return "pmpaddr41";
76
+ case 0x03da: return "pmpaddr42";
77
+ case 0x03db: return "pmpaddr43";
78
+ case 0x03dc: return "pmpaddr44";
79
+ case 0x03dd: return "pmpaddr45";
80
+ case 0x03de: return "pmpaddr46";
81
+ case 0x03df: return "pmpaddr47";
82
+ case 0x03e0: return "pmpaddr48";
83
+ case 0x03e1: return "pmpaddr49";
84
+ case 0x03e2: return "pmpaddr50";
85
+ case 0x03e3: return "pmpaddr51";
86
+ case 0x03e4: return "pmpaddr52";
87
+ case 0x03e5: return "pmpaddr53";
88
+ case 0x03e6: return "pmpaddr54";
89
+ case 0x03e7: return "pmpaddr55";
90
+ case 0x03e8: return "pmpaddr56";
91
+ case 0x03e9: return "pmpaddr57";
92
+ case 0x03ea: return "pmpaddr58";
93
+ case 0x03eb: return "pmpaddr59";
94
+ case 0x03ec: return "pmpaddr60";
95
+ case 0x03ed: return "pmpaddr61";
96
+ case 0x03ee: return "pmpaddr62";
97
+ case 0x03ef: return "pmpaddr63";
98
case 0x0780: return "mtohost";
99
case 0x0781: return "mfromhost";
100
case 0x0782: return "mreset";
101
--
102
2.45.1
diff view generated by jsdifflib
New patch
1
From: Yu-Ming Chang <yumin686@andestech.com>
1
2
3
Both CSRRS and CSRRC always read the addressed CSR and cause any read side
4
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
5
holding a zero value other than x0, the instruction will still attempt to write
6
the unmodified value back to the CSR and will cause any attendant side effects.
7
8
So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
9
a register holding a zero value, an illegal instruction exception should be
10
raised.
11
12
Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/cpu.h | 4 ++++
18
target/riscv/csr.c | 51 ++++++++++++++++++++++++++++++++++++----
19
target/riscv/op_helper.c | 6 ++---
20
3 files changed, 53 insertions(+), 8 deletions(-)
21
22
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/cpu.h
25
+++ b/target/riscv/cpu.h
26
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
27
void riscv_cpu_update_mask(CPURISCVState *env);
28
bool riscv_cpu_is_32bit(RISCVCPU *cpu);
29
30
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
31
+ target_ulong *ret_value);
32
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
33
target_ulong *ret_value,
34
target_ulong new_value, target_ulong write_mask);
35
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
36
target_ulong new_value,
37
target_ulong write_mask);
38
39
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
40
+ Int128 *ret_value);
41
RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
42
Int128 *ret_value,
43
Int128 new_value, Int128 write_mask);
44
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/riscv/csr.c
47
+++ b/target/riscv/csr.c
48
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
49
50
static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
51
int csrno,
52
- bool write_mask)
53
+ bool write)
54
{
55
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
56
bool read_only = get_field(csrno, 0xC00) == 3;
57
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
58
}
59
60
/* read / write check */
61
- if (write_mask && read_only) {
62
+ if (write && read_only) {
63
return RISCV_EXCP_ILLEGAL_INST;
64
}
65
66
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
67
return RISCV_EXCP_NONE;
68
}
69
70
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
71
+ target_ulong *ret_value)
72
+{
73
+ RISCVException ret = riscv_csrrw_check(env, csrno, false);
74
+ if (ret != RISCV_EXCP_NONE) {
75
+ return ret;
76
+ }
77
+
78
+ return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
79
+}
80
+
81
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
82
target_ulong *ret_value,
83
target_ulong new_value, target_ulong write_mask)
84
{
85
- RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
86
+ RISCVException ret = riscv_csrrw_check(env, csrno, true);
87
if (ret != RISCV_EXCP_NONE) {
88
return ret;
89
}
90
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
91
return RISCV_EXCP_NONE;
92
}
93
94
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
95
+ Int128 *ret_value)
96
+{
97
+ RISCVException ret;
98
+
99
+ ret = riscv_csrrw_check(env, csrno, false);
100
+ if (ret != RISCV_EXCP_NONE) {
101
+ return ret;
102
+ }
103
+
104
+ if (csr_ops[csrno].read128) {
105
+ return riscv_csrrw_do128(env, csrno, ret_value,
106
+ int128_zero(), int128_zero());
107
+ }
108
+
109
+ /*
110
+ * Fall back to 64-bit version for now, if the 128-bit alternative isn't
111
+ * at all defined.
112
+ * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
113
+ * significant), for those, this fallback is correctly handling the
114
+ * accesses
115
+ */
116
+ target_ulong old_value;
117
+ ret = riscv_csrrw_do64(env, csrno, &old_value,
118
+ (target_ulong)0,
119
+ (target_ulong)0);
120
+ if (ret == RISCV_EXCP_NONE && ret_value) {
121
+ *ret_value = int128_make64(old_value);
122
+ }
123
+ return ret;
124
+}
125
+
126
RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
127
Int128 *ret_value,
128
Int128 new_value, Int128 write_mask)
129
{
130
RISCVException ret;
131
132
- ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
133
+ ret = riscv_csrrw_check(env, csrno, true);
134
if (ret != RISCV_EXCP_NONE) {
135
return ret;
136
}
137
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
138
index XXXXXXX..XXXXXXX 100644
139
--- a/target/riscv/op_helper.c
140
+++ b/target/riscv/op_helper.c
141
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
142
}
143
144
target_ulong val = 0;
145
- RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
146
+ RISCVException ret = riscv_csrr(env, csr, &val);
147
148
if (ret != RISCV_EXCP_NONE) {
149
riscv_raise_exception(env, ret, GETPC());
150
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
151
target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
152
{
153
Int128 rv = int128_zero();
154
- RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
155
- int128_zero(),
156
- int128_zero());
157
+ RISCVException ret = riscv_csrr_i128(env, csr, &rv);
158
159
if (ret != RISCV_EXCP_NONE) {
160
riscv_raise_exception(env, ret, GETPC());
161
--
162
2.45.1
diff view generated by jsdifflib