The following changes since commit 5cc7a54c2e91d82cb6a52e4921325c511fd90712:

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200602' into staging (2020-06-02 18:16:38 +0100)

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200603

for you to fetch changes up to fe0fe4735e798578097758781166cc221319b93d:

riscv: Initial commit of OpenTitan machine (2020-06-03 09:11:51 -0700)

This is a collection of RISC-V patches for 5.1.

This incldues removing deprecated features and part of the OpenTitan

support series.

Alistair Francis (11):

hw/riscv: spike: Remove deprecated ISA specific machines

target/riscv: Remove the deprecated CPUs

target/riscv: Drop support for ISA spec version 1.09.1

docs: deprecated: Update the -bios documentation

riscv: sifive_e: Manually define the machine

riscv/boot: Add a missing header include

target/riscv: Don't overwrite the reset vector

target/riscv: Disable the MMU correctly

target/riscv: Don't set PMP feature in the cpu init

target/riscv: Add the lowRISC Ibex CPU

riscv: Initial commit of OpenTitan machine

Bin Meng (4):

riscv: Suppress the error report for QEMU testing with riscv_find_firmware()

riscv: Change the default behavior if no -bios option is specified

hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions

hw/riscv: virt: Remove the riscv_ prefix of the machine* functions

docs/system/deprecated.rst | 98 +++++------

default-configs/riscv32-softmmu.mak | 1 +

default-configs/riscv64-softmmu.mak | 11 +-

include/hw/riscv/boot.h | 1 +

include/hw/riscv/opentitan.h | 68 ++++++++

include/hw/riscv/sifive_e.h | 4 +

include/hw/riscv/spike.h | 6 +-

target/riscv/cpu.h | 9 +-

hw/riscv/boot.c | 45 ++---

hw/riscv/opentitan.c | 184 +++++++++++++++++++++

hw/riscv/sifive_e.c | 41 +++--

hw/riscv/sifive_u.c | 24 +--

hw/riscv/spike.c | 217 -------------------------

hw/riscv/virt.c | 20 +--

target/riscv/cpu.c | 45 ++---

target/riscv/cpu_helper.c | 82 ++++------

target/riscv/csr.c | 138 +++-------------

target/riscv/insn_trans/trans_privileged.inc.c | 18 +-

target/riscv/monitor.c | 5 -

target/riscv/op_helper.c | 17 +-

tests/qtest/machine-none-test.c | 4 +-

MAINTAINERS | 9 +

hw/riscv/Kconfig | 5 +

hw/riscv/Makefile.objs | 1 +

24 files changed, 480 insertions(+), 573 deletions(-)

create mode 100644 include/hw/riscv/opentitan.h

create mode 100644 hw/riscv/opentitan.c

From: Bin Meng <bin.meng@windriver.com>

Per QEMU deprecated doc, QEMU 4.1 introduced support for the -bios

option in QEMU for RISC-V for the virt machine and sifive_u machine.

The default behavior has been that QEMU does not automatically load

any firmware if no -bios option is included.

Now 2 releases passed, it's time to change the default behavior to

load the default OpenSBI firmware automatically. The firmware is

included with the QEMU release and no user interaction is required.

All a user needs to do is specify the kernel they want to boot with

the -kernel option.

Signed-off-by: Bin Meng <bin.meng@windriver.com>

Message-id: 1588335545-649-1-git-send-email-bmeng.cn@gmail.com

Message-Id: <1588335545-649-1-git-send-email-bmeng.cn@gmail.com>

hw/riscv/boot.c | 31 ++++---------------------------

1 file changed, 4 insertions(+), 27 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c

--- a/hw/riscv/boot.c

+++ b/hw/riscv/boot.c

@@ -XXX,XX +XXX,XX @@ void riscv_find_and_load_firmware(MachineState *machine,

{

char *firmware_filename = NULL;

- if (!machine->firmware) {

+ if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) {

/*

- * The user didn't specify -bios.

- * At the moment we default to loading nothing when this hapens.

- * In the future this defaul will change to loading the prebuilt

- * OpenSBI firmware. Let's warn the user and then continue.

- */

- if (!qtest_enabled()) {

- warn_report("No -bios option specified. Not loading a firmware.");

- warn_report("This default will change in a future QEMU release. " \

- "Please use the -bios option to avoid breakages when "\

- "this happens.");

- warn_report("See QEMU's deprecation documentation for details.");

- }

- return;

- }

-

- if (!strcmp(machine->firmware, "default")) {

- /*

- * The user has specified "-bios default". That means we are going to

- * load the OpenSBI binary included in the QEMU source.

- *

- * We can't load the binary by default as it will break existing users

- * as users are already loading their own firmware.

- *

- * Let's try to get everyone to specify the -bios option at all times,

- * so then in the future we can make "-bios default" the default option

- * if no -bios option is set without breaking anything.

+ * The user didn't specify -bios, or has specified "-bios default".

+ * That means we are going to load the OpenSBI binary included in

+ * the QEMU source.

*/

firmware_filename = riscv_find_firmware(default_machine_firmware);

} else if (strcmp(machine->firmware, "none")) {

2.26.2

From: Bin Meng <bin.meng@windriver.com>

To keep consistency with the machine* functions, remove the riscv_

prefix of the soc* functions.

Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 1590072147-13035-1-git-send-email-bmeng.cn@gmail.com

Message-Id: <1590072147-13035-1-git-send-email-bmeng.cn@gmail.com>

hw/riscv/sifive_u.c | 24 ++++++++++++------------

1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c

--- a/hw/riscv/sifive_u.c

+++ b/hw/riscv/sifive_u.c

@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init_register_types(void)

type_init(sifive_u_machine_init_register_types)

-static void riscv_sifive_u_soc_init(Object *obj)

+static void sifive_u_soc_instance_init(Object *obj)

{

MachineState *ms = MACHINE(qdev_get_machine());

SiFiveUSoCState *s = RISCV_U_SOC(obj);

@@ -XXX,XX +XXX,XX @@ static void riscv_sifive_u_soc_init(Object *obj)

TYPE_CADENCE_GEM);

-static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)

+static void sifive_u_soc_realize(DeviceState *dev, Error **errp)

{

MachineState *ms = MACHINE(qdev_get_machine());

SiFiveUSoCState *s = RISCV_U_SOC(dev);

@@ -XXX,XX +XXX,XX @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)

memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);

}

-static Property riscv_sifive_u_soc_props[] = {

+static Property sifive_u_soc_props[] = {

DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),

DEFINE_PROP_END_OF_LIST()

};

-static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)

+static void sifive_u_soc_class_init(ObjectClass *oc, void *data)

{

DeviceClass *dc = DEVICE_CLASS(oc);

- device_class_set_props(dc, riscv_sifive_u_soc_props);

- dc->realize = riscv_sifive_u_soc_realize;

+ device_class_set_props(dc, sifive_u_soc_props);

+ dc->realize = sifive_u_soc_realize;

/* Reason: Uses serial_hds in realize function, thus can't be used twice */

dc->user_creatable = false;

}

-static const TypeInfo riscv_sifive_u_soc_type_info = {

+static const TypeInfo sifive_u_soc_type_info = {

.name = TYPE_RISCV_U_SOC,

.parent = TYPE_DEVICE,

.instance_size = sizeof(SiFiveUSoCState),

- .instance_init = riscv_sifive_u_soc_init,

- .class_init = riscv_sifive_u_soc_class_init,

+ .instance_init = sifive_u_soc_instance_init,

+ .class_init = sifive_u_soc_class_init,

};

-static void riscv_sifive_u_soc_register_types(void)

+static void sifive_u_soc_register_types(void)

{

- type_register_static(&riscv_sifive_u_soc_type_info);

+ type_register_static(&sifive_u_soc_type_info);

}

-type_init(riscv_sifive_u_soc_register_types)

+type_init(sifive_u_soc_register_types)

2.26.2