Series comparison

-[PULL 00/12] tcg patch queue
+[PULL 0/4] tcg patch queue
-I have not been able to prod reviews of all of the rotate patches
+Pretty small still, but there are two patches that ought
-in 4 weeks, but let's not let that block ARM work forever.
+to get backported to stable, so no point in delaying.
 r~
+The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
-The following changes since commit cccdd8c7971896c339d59c9c5d4647d4ffd9568a:
+  Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
   Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging (2020-06-02 10:25:55 +0100)
 are available in the Git repository at:
-  https://github.com/rth7680/qemu.git tags/pull-tcg-20200602
+  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212
-for you to fetch changes up to 71b04329c4f7d5824a289ca5225e1883a278cf3b:
+for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:
-  accel/tcg: Provide a NetBSD specific aarch64 cpu_signal_handler (2020-06-02 08:42:37 -0700)
+  target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)
 ----------------------------------------------------------------
-Vector rotate support
+tcg: Reset free_temps before tcg_optimize
-Signal handling support for NetBSD arm/aarch64
+tcg/riscv: Fix StoreStore barrier generation
 include/exec: Introduce fpst alias in helper-head.h.inc
 target/sparc: Use memcpy() and remove memcpy32()
 ----------------------------------------------------------------
-Nick Hudson (2):
+Philippe Mathieu-Daudé (1):
-      accel/tcg: Adjust cpu_signal_handler for NetBSD/arm
+      target/sparc: Use memcpy() and remove memcpy32()
       accel/tcg: Provide a NetBSD specific aarch64 cpu_signal_handler
-Richard Henderson (10):
+Richard Henderson (2):
-      tcg: Implement gvec support for rotate by immediate
+      tcg: Reset free_temps before tcg_optimize
-      tcg: Implement gvec support for rotate by vector
+      include/exec: Introduce fpst alias in helper-head.h.inc
       tcg: Remove expansion to shift by vector from do_shifts
       tcg: Implement gvec support for rotate by scalar
       tcg/i386: Implement INDEX_op_rotl{i,s,v}_vec
       tcg/aarch64: Implement INDEX_op_rotl{i,v}_vec
       tcg/ppc: Implement INDEX_op_rot[lr]v_vec
       target/ppc: Use tcg_gen_gvec_rotlv
       target/s390x: Use tcg_gen_gvec_rotl{i,s,v}
       tcg: Improve move ops in liveness_pass_2
- accel/tcg/tcg-runtime.h             |  15 +++
+Roman Artemev (1):
- include/tcg/tcg-op-gvec.h           |  12 ++
+      tcg/riscv: Fix StoreStore barrier generation
  include/tcg/tcg-op.h                |   5 +
  include/tcg/tcg-opc.h               |   4 +
  include/tcg/tcg.h                   |   3 +
  target/ppc/helper.h                 |   4 -
  target/s390x/helper.h               |   4 -
  tcg/aarch64/tcg-target.h            |   3 +
  tcg/aarch64/tcg-target.opc.h        |   1 +
  tcg/i386/tcg-target.h               |   3 +
  tcg/ppc/tcg-target.h                |   3 +
  tcg/ppc/tcg-target.opc.h            |   1 -
  accel/tcg/tcg-runtime-gvec.c        | 144 ++++++++++++++++++++++++
  accel/tcg/user-exec.c               |  43 +++++++-
  target/ppc/int_helper.c             |  17 ---
  target/ppc/translate/vmx-impl.inc.c |   8 +-
  target/s390x/translate_vx.inc.c     |  66 ++---------
  target/s390x/vec_int_helper.c       |  31 ------
  tcg/aarch64/tcg-target.inc.c        |  53 ++++++++-
  tcg/i386/tcg-target.inc.c           | 116 +++++++++++++++++---
  tcg/ppc/tcg-target.inc.c            |  23 +++-
  tcg/tcg-op-gvec.c                   | 212 ++++++++++++++++++++++++++++++++++++
  tcg/tcg-op-vec.c                    |  62 +++++++----
  tcg/tcg.c                           |  85 +++++++++++----
  target/s390x/insn-data.def          |   4 +-
  tcg/README                          |   7 +-
 files changed, 736 insertions(+), 193 deletions(-)
+ include/tcg/tcg-temp-internal.h |  6 ++++++
+ accel/tcg/plugin-gen.c          |  2 +-
+ target/sparc/win_helper.c       | 26 ++++++++------------------
+ tcg/tcg.c                       |  5 ++++-
+ include/exec/helper-head.h.inc  |  3 +++
+ tcg/riscv/tcg-target.c.inc      |  2 +-
+files changed, 23 insertions(+), 21 deletions(-)

-[PULL 02/12] tcg: Implement gvec support for rotate by vector
+[PULL 1/4] tcg: Reset free_temps before tcg_optimize
-No host backend support yet, but the interfaces for rotlv
+When allocating new temps during tcg_optmize, do not re-use
-and rotrv are in place.
+any EBB temps that were used within the TB.  We do not have
 any idea what span of the TB in which the temp was live.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
 as well as replacing the equivalent in plugin_gen_inject and
 tcg_func_start.
 Cc: qemu-stable@nongnu.org
 Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
 Reported-by: wannacu <wannacu2049@gmail.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 ---
-v3: Drop the generic expansion from rot to shift; we can do better
+ include/tcg/tcg-temp-internal.h | 6 ++++++
-    for each backend, and then this code becomes unused.
+ accel/tcg/plugin-gen.c          | 2 +-
----
+ tcg/tcg.c                       | 5 ++++-
- accel/tcg/tcg-runtime.h      |  10 +++
+files changed, 11 insertions(+), 2 deletions(-)
  include/tcg/tcg-op-gvec.h    |   4 ++
  include/tcg/tcg-op.h         |   2 +
  include/tcg/tcg-opc.h        |   2 +
  include/tcg/tcg.h            |   1 +
  tcg/aarch64/tcg-target.h     |   1 +
  tcg/i386/tcg-target.h        |   1 +
  tcg/ppc/tcg-target.h         |   1 +
  accel/tcg/tcg-runtime-gvec.c |  96 +++++++++++++++++++++++++++
  tcg/tcg-op-gvec.c            | 122 +++++++++++++++++++++++++++++++++++
  tcg/tcg-op-vec.c             |  10 +++
  tcg/tcg.c                    |   3 +
  tcg/README                   |   4 +-
 files changed, 256 insertions(+), 1 deletion(-)
-diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
+diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
 index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/tcg-runtime.h
+--- a/include/tcg/tcg-temp-internal.h
-+++ b/accel/tcg/tcg-runtime.h
++++ b/include/tcg/tcg-temp-internal.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(gvec_sar16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
- DEF_HELPER_FLAGS_4(gvec_sar32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+ TCGv_ptr tcg_temp_ebb_new_ptr(void);
- DEF_HELPER_FLAGS_4(gvec_sar64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+ TCGv_i128 tcg_temp_ebb_new_i128(void);
-+DEF_HELPER_FLAGS_4(gvec_rotl8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
++/* Forget all freed EBB temps, so that new allocations produce new temps. */
-+DEF_HELPER_FLAGS_4(gvec_rotl16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
++static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
 +DEF_HELPER_FLAGS_4(gvec_rotl32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(gvec_rotl64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(gvec_rotr8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(gvec_rotr16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(gvec_rotr32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(gvec_rotr64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 +
  DEF_HELPER_FLAGS_4(gvec_eq8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(gvec_eq16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(gvec_eq32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/tcg/tcg-op-gvec.h
 +++ b/include/tcg/tcg-op-gvec.h
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs,
                         uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
  void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs,
                         uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
 +void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, uint32_t aofs,
 +                        uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
 +void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs,
 +                        uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
  void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
                        uint32_t aofs, uint32_t bofs,
 diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/tcg/tcg-op.h
 +++ b/include/tcg/tcg-op.h
@@ -XXX,XX +XXX,XX @@ void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
  void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
  void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
  void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
 +void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
 +void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
  void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
                       TCGv_vec a, TCGv_vec b);
 diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/tcg/tcg-opc.h
 +++ b/include/tcg/tcg-opc.h
@@ -XXX,XX +XXX,XX @@ DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
  DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
  DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
  DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
 +DEF(rotlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec))
 +DEF(rotrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec))
  DEF(cmp_vec, 1, 2, 1, IMPLVEC)
 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/tcg/tcg.h
 +++ b/include/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@ typedef uint64_t TCGRegSet;
  #define TCG_TARGET_HAS_andc_vec         0
  #define TCG_TARGET_HAS_orc_vec          0
  #define TCG_TARGET_HAS_roti_vec         0
 +#define TCG_TARGET_HAS_rotv_vec         0
  #define TCG_TARGET_HAS_shi_vec          0
  #define TCG_TARGET_HAS_shs_vec          0
  #define TCG_TARGET_HAS_shv_vec          0
 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/aarch64/tcg-target.h
 +++ b/tcg/aarch64/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
  #define TCG_TARGET_HAS_neg_vec          1
  #define TCG_TARGET_HAS_abs_vec          1
  #define TCG_TARGET_HAS_roti_vec         0
 +#define TCG_TARGET_HAS_rotv_vec         0
  #define TCG_TARGET_HAS_shi_vec          1
  #define TCG_TARGET_HAS_shs_vec          0
  #define TCG_TARGET_HAS_shv_vec          1
 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/i386/tcg-target.h
 +++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
  #define TCG_TARGET_HAS_neg_vec          0
  #define TCG_TARGET_HAS_abs_vec          1
  #define TCG_TARGET_HAS_roti_vec         0
 +#define TCG_TARGET_HAS_rotv_vec         0
  #define TCG_TARGET_HAS_shi_vec          1
  #define TCG_TARGET_HAS_shs_vec          1
  #define TCG_TARGET_HAS_shv_vec          have_avx2
 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/ppc/tcg-target.h
 +++ b/tcg/ppc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;
  #define TCG_TARGET_HAS_neg_vec          have_isa_3_00
  #define TCG_TARGET_HAS_abs_vec          0
  #define TCG_TARGET_HAS_roti_vec         0
 +#define TCG_TARGET_HAS_rotv_vec         0
  #define TCG_TARGET_HAS_shi_vec          0
  #define TCG_TARGET_HAS_shs_vec          0
  #define TCG_TARGET_HAS_shv_vec          1
 diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/tcg/tcg-runtime-gvec.c
 +++ b/accel/tcg/tcg-runtime-gvec.c
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sar64v)(void *d, void *a, void *b, uint32_t desc)
      clear_high(d, oprsz, desc);
  }
 +void HELPER(gvec_rotl8v)(void *d, void *a, void *b, uint32_t desc)
 +{
-+    intptr_t oprsz = simd_oprsz(desc);
++    memset(s->free_temps, 0, sizeof(s->free_temps));
 +    intptr_t i;
 +
 +    for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
 +        uint8_t sh = *(uint8_t *)(b + i) & 7;
 +        *(uint8_t *)(d + i) = rol8(*(uint8_t *)(a + i), sh);
 +    }
 +    clear_high(d, oprsz, desc);
 +}
 +
-+void HELPER(gvec_rotl16v)(void *d, void *a, void *b, uint32_t desc)
+ #endif /* TCG_TEMP_FREE_H */
-+{
+diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
 +    intptr_t oprsz = simd_oprsz(desc);
 +    intptr_t i;
 +
 +    for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
 +        uint8_t sh = *(uint16_t *)(b + i) & 15;
 +        *(uint16_t *)(d + i) = rol16(*(uint16_t *)(a + i), sh);
 +    }
 +    clear_high(d, oprsz, desc);
 +}
 +
 +void HELPER(gvec_rotl32v)(void *d, void *a, void *b, uint32_t desc)
 +{
 +    intptr_t oprsz = simd_oprsz(desc);
 +    intptr_t i;
 +
 +    for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
 +        uint8_t sh = *(uint32_t *)(b + i) & 31;
 +        *(uint32_t *)(d + i) = rol32(*(uint32_t *)(a + i), sh);
 +    }
 +    clear_high(d, oprsz, desc);
 +}
 +
 +void HELPER(gvec_rotl64v)(void *d, void *a, void *b, uint32_t desc)
 +{
 +    intptr_t oprsz = simd_oprsz(desc);
 +    intptr_t i;
 +
 +    for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
 +        uint8_t sh = *(uint64_t *)(b + i) & 63;
 +        *(uint64_t *)(d + i) = rol64(*(uint64_t *)(a + i), sh);
 +    }
 +    clear_high(d, oprsz, desc);
 +}
 +
 +void HELPER(gvec_rotr8v)(void *d, void *a, void *b, uint32_t desc)
 +{
 +    intptr_t oprsz = simd_oprsz(desc);
 +    intptr_t i;
 +
 +    for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
 +        uint8_t sh = *(uint8_t *)(b + i) & 7;
 +        *(uint8_t *)(d + i) = ror8(*(uint8_t *)(a + i), sh);
 +    }
 +    clear_high(d, oprsz, desc);
 +}
 +
 +void HELPER(gvec_rotr16v)(void *d, void *a, void *b, uint32_t desc)
 +{
 +    intptr_t oprsz = simd_oprsz(desc);
 +    intptr_t i;
 +
 +    for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
 +        uint8_t sh = *(uint16_t *)(b + i) & 15;
 +        *(uint16_t *)(d + i) = ror16(*(uint16_t *)(a + i), sh);
 +    }
 +    clear_high(d, oprsz, desc);
 +}
 +
 +void HELPER(gvec_rotr32v)(void *d, void *a, void *b, uint32_t desc)
 +{
 +    intptr_t oprsz = simd_oprsz(desc);
 +    intptr_t i;
 +
 +    for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
 +        uint8_t sh = *(uint32_t *)(b + i) & 31;
 +        *(uint32_t *)(d + i) = ror32(*(uint32_t *)(a + i), sh);
 +    }
 +    clear_high(d, oprsz, desc);
 +}
 +
 +void HELPER(gvec_rotr64v)(void *d, void *a, void *b, uint32_t desc)
 +{
 +    intptr_t oprsz = simd_oprsz(desc);
 +    intptr_t i;
 +
 +    for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
 +        uint8_t sh = *(uint64_t *)(b + i) & 63;
 +        *(uint64_t *)(d + i) = ror64(*(uint64_t *)(a + i), sh);
 +    }
 +    clear_high(d, oprsz, desc);
 +}
 +
  #define DO_CMP1(NAME, TYPE, OP)                                            \
  void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc)                \
  {                                                                          \
 diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg-op-gvec.c
+--- a/accel/tcg/plugin-gen.c
-+++ b/tcg/tcg-op-gvec.c
++++ b/accel/tcg/plugin-gen.c
-@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs,
+@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
-     tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
+      * that might be live within the existing opcode stream.
- }
+      * The simplest solution is to release them all and create new.
+      */
-+/*
+-    memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
-+ * Similarly for rotates.
++    tcg_temp_ebb_reset_freed(tcg_ctx);
-+ */
-+
+     QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
-+static void tcg_gen_rotlv_mod_vec(unsigned vece, TCGv_vec d,
+         switch (op->opc) {
 +                                  TCGv_vec a, TCGv_vec b)
 +{
 +    TCGv_vec t = tcg_temp_new_vec_matching(d);
 +
 +    tcg_gen_dupi_vec(vece, t, (8 << vece) - 1);
 +    tcg_gen_and_vec(vece, t, t, b);
 +    tcg_gen_rotlv_vec(vece, d, a, t);
 +    tcg_temp_free_vec(t);
 +}
 +
 +static void tcg_gen_rotl_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
 +{
 +    TCGv_i32 t = tcg_temp_new_i32();
 +
 +    tcg_gen_andi_i32(t, b, 31);
 +    tcg_gen_rotl_i32(d, a, t);
 +    tcg_temp_free_i32(t);
 +}
 +
 +static void tcg_gen_rotl_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
 +{
 +    TCGv_i64 t = tcg_temp_new_i64();
 +
 +    tcg_gen_andi_i64(t, b, 63);
 +    tcg_gen_rotl_i64(d, a, t);
 +    tcg_temp_free_i64(t);
 +}
 +
 +void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, uint32_t aofs,
 +                        uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
 +{
 +    static const TCGOpcode vecop_list[] = { INDEX_op_rotlv_vec, 0 };
 +    static const GVecGen3 g[4] = {
 +        { .fniv = tcg_gen_rotlv_mod_vec,
 +          .fno = gen_helper_gvec_rotl8v,
 +          .opt_opc = vecop_list,
 +          .vece = MO_8 },
 +        { .fniv = tcg_gen_rotlv_mod_vec,
 +          .fno = gen_helper_gvec_rotl16v,
 +          .opt_opc = vecop_list,
 +          .vece = MO_16 },
 +        { .fni4 = tcg_gen_rotl_mod_i32,
 +          .fniv = tcg_gen_rotlv_mod_vec,
 +          .fno = gen_helper_gvec_rotl32v,
 +          .opt_opc = vecop_list,
 +          .vece = MO_32 },
 +        { .fni8 = tcg_gen_rotl_mod_i64,
 +          .fniv = tcg_gen_rotlv_mod_vec,
 +          .fno = gen_helper_gvec_rotl64v,
 +          .opt_opc = vecop_list,
 +          .prefer_i64 = TCG_TARGET_REG_BITS == 64,
 +          .vece = MO_64 },
 +    };
 +
 +    tcg_debug_assert(vece <= MO_64);
 +    tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
 +}
 +
 +static void tcg_gen_rotrv_mod_vec(unsigned vece, TCGv_vec d,
 +                                  TCGv_vec a, TCGv_vec b)
 +{
 +    TCGv_vec t = tcg_temp_new_vec_matching(d);
 +
 +    tcg_gen_dupi_vec(vece, t, (8 << vece) - 1);
 +    tcg_gen_and_vec(vece, t, t, b);
 +    tcg_gen_rotrv_vec(vece, d, a, t);
 +    tcg_temp_free_vec(t);
 +}
 +
 +static void tcg_gen_rotr_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
 +{
 +    TCGv_i32 t = tcg_temp_new_i32();
 +
 +    tcg_gen_andi_i32(t, b, 31);
 +    tcg_gen_rotr_i32(d, a, t);
 +    tcg_temp_free_i32(t);
 +}
 +
 +static void tcg_gen_rotr_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
 +{
 +    TCGv_i64 t = tcg_temp_new_i64();
 +
 +    tcg_gen_andi_i64(t, b, 63);
 +    tcg_gen_rotr_i64(d, a, t);
 +    tcg_temp_free_i64(t);
 +}
 +
 +void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs,
 +                        uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
 +{
 +    static const TCGOpcode vecop_list[] = { INDEX_op_rotrv_vec, 0 };
 +    static const GVecGen3 g[4] = {
 +        { .fniv = tcg_gen_rotrv_mod_vec,
 +          .fno = gen_helper_gvec_rotr8v,
 +          .opt_opc = vecop_list,
 +          .vece = MO_8 },
 +        { .fniv = tcg_gen_rotrv_mod_vec,
 +          .fno = gen_helper_gvec_rotr16v,
 +          .opt_opc = vecop_list,
 +          .vece = MO_16 },
 +        { .fni4 = tcg_gen_rotr_mod_i32,
 +          .fniv = tcg_gen_rotrv_mod_vec,
 +          .fno = gen_helper_gvec_rotr32v,
 +          .opt_opc = vecop_list,
 +          .vece = MO_32 },
 +        { .fni8 = tcg_gen_rotr_mod_i64,
 +          .fniv = tcg_gen_rotrv_mod_vec,
 +          .fno = gen_helper_gvec_rotr64v,
 +          .opt_opc = vecop_list,
 +          .prefer_i64 = TCG_TARGET_REG_BITS == 64,
 +          .vece = MO_64 },
 +    };
 +
 +    tcg_debug_assert(vece <= MO_64);
 +    tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
 +}
 +
  /* Expand OPSZ bytes worth of three-operand operations using i32 elements.  */
  static void expand_cmp_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
                             uint32_t oprsz, TCGCond cond)
 diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/tcg-op-vec.c
 +++ b/tcg/tcg-op-vec.c
@@ -XXX,XX +XXX,XX @@ void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
      do_op3_nofail(vece, r, a, b, INDEX_op_sarv_vec);
  }
 +void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
 +{
 +    do_op3_nofail(vece, r, a, b, INDEX_op_rotlv_vec);
 +}
 +
 +void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
 +{
 +    do_op3_nofail(vece, r, a, b, INDEX_op_rotrv_vec);
 +}
 +
  static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a,
                        TCGv_i32 s, TCGOpcode opc_s, TCGOpcode opc_v)
  {
 diff --git a/tcg/tcg.c b/tcg/tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/tcg.c
 +++ b/tcg/tcg.c
-@@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op)
+@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
-         return have_vec && TCG_TARGET_HAS_shv_vec;
+     s->nb_temps = s->nb_globals;
-     case INDEX_op_rotli_vec:
-         return have_vec && TCG_TARGET_HAS_roti_vec;
+     /* No temps have been previously allocated for size or locality.  */
-+    case INDEX_op_rotlv_vec:
+-    memset(s->free_temps, 0, sizeof(s->free_temps));
-+    case INDEX_op_rotrv_vec:
++    tcg_temp_ebb_reset_freed(s);
-+        return have_vec && TCG_TARGET_HAS_rotv_vec;
-     case INDEX_op_ssadd_vec:
+     /* No constant temps have been previously allocated. */
-     case INDEX_op_usadd_vec:
+     for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
-     case INDEX_op_sssub_vec:
+@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
-diff --git a/tcg/README b/tcg/README
+     }
-index XXXXXXX..XXXXXXX 100644
+ #endif
---- a/tcg/README
-+++ b/tcg/README
++    /* Do not reuse any EBB that may be allocated within the TB. */
-@@ -XXX,XX +XXX,XX @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
++    tcg_temp_ebb_reset_freed(s);
++
- * shrv_vec   v0, v1, v2
+     tcg_optimize(s);
- * sarv_vec   v0, v1, v2
-+* rotlv_vec  v0, v1, v2
+     reachable_code_pass(s);
 +* rotrv_vec  v0, v1, v2
 -  Similarly for logical and arithmetic right shift.
 +  Similarly for logical and arithmetic right shift, and rotates.
  * cmp_vec  v0, v1, v2, cond
 --
-.25.1
+.43.0

-[PULL 12/12] accel/tcg: Provide a NetBSD specific aarch64 cpu_signal_handler
+[PULL 2/4] tcg/riscv: Fix StoreStore barrier generation
-From: Nick Hudson <skrll@netbsd.org>
+From: Roman Artemev <roman.artemev@syntacore.com>
-Fix qemu build on NetBSD/evbarm-aarch64 by providing a NetBSD specific
+On RISC-V to StoreStore barrier corresponds
-cpu_signal_handler.
+`fence w, w` not `fence r, r`
+Cc: qemu-stable@nongnu.org
+Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: Nick Hudson <skrll@netbsd.org>
+Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
-Message-Id: <20200517101529.5367-1-skrll@netbsd.org>
+Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
 Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- accel/tcg/user-exec.c | 27 +++++++++++++++++++++++++++
+ tcg/riscv/tcg-target.c.inc | 2 +-
-file changed, 27 insertions(+)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
+diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/user-exec.c
+--- a/tcg/riscv/tcg-target.c.inc
-+++ b/accel/tcg/user-exec.c
++++ b/tcg/riscv/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo,
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
+         insn |= 0x02100000;
  #elif defined(__aarch64__)
 +#if defined(__NetBSD__)
 +
 +#include <ucontext.h>
 +#include <sys/siginfo.h>
 +
 +int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
 +{
 +    ucontext_t *uc = puc;
 +    siginfo_t *si = pinfo;
 +    unsigned long pc;
 +    int is_write;
 +    uint32_t esr;
 +
 +    pc = uc->uc_mcontext.__gregs[_REG_PC];
 +    esr = si->si_trap;
 +
 +    /*
 +     * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC
 +     * is 0b10010x: then bit 6 is the WnR bit
 +     */
 +    is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1;
 +    return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask);
 +}
 +
 +#else
 +
  #ifndef ESR_MAGIC
  /* Pre-3.16 kernel headers don't have these, so provide fallback definitions */
  #define ESR_MAGIC 0x45535201
@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
      }
-     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
+     if (a0 & TCG_MO_ST_ST) {
 -        insn |= 0x02200000;
 +        insn |= 0x01100000;
      }
      tcg_out32(s, insn);
  }
-+#endif
- #elif defined(__s390__)
 --
-.25.1
+.43.0

-[PULL 11/12] accel/tcg: Adjust cpu_signal_handler for NetBSD/arm
+[PULL 3/4] include/exec: Introduce fpst alias in helper-head.h.inc
-From: Nick Hudson <skrll@netbsd.org>
+This allows targets to declare that the helper requires a
 float_status pointer and instead of a generic void pointer.
-Fix building on NetBSD/arm by extracting the FSR value from the
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 correct siginfo_t field.
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Nick Hudson <skrll@netbsd.org>
 Message-Id: <20200516154147.24842-1-skrll@netbsd.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- accel/tcg/user-exec.c | 16 +++++++++++++---
+ include/exec/helper-head.h.inc | 3 +++
-file changed, 13 insertions(+), 3 deletions(-)
+file changed, 3 insertions(+)
-diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
+diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
 index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/user-exec.c
+--- a/include/exec/helper-head.h.inc
-+++ b/accel/tcg/user-exec.c
++++ b/include/exec/helper-head.h.inc
-@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo,
+@@ -XXX,XX +XXX,XX @@
+ #define dh_alias_ptr ptr
- #if defined(__NetBSD__)
+ #define dh_alias_cptr ptr
- #include <ucontext.h>
+ #define dh_alias_env ptr
-+#include <sys/siginfo.h>
++#define dh_alias_fpst ptr
- #endif
+ #define dh_alias_void void
+ #define dh_alias_noreturn noreturn
- int cpu_signal_handler(int host_signum, void *pinfo,
+ #define dh_alias(t) glue(dh_alias_, t)
-@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo,
+@@ -XXX,XX +XXX,XX @@
-     siginfo_t *info = pinfo;
+ #define dh_ctype_ptr void *
- #if defined(__NetBSD__)
+ #define dh_ctype_cptr const void *
-     ucontext_t *uc = puc;
+ #define dh_ctype_env CPUArchState *
-+    siginfo_t *si = pinfo;
++#define dh_ctype_fpst float_status *
- #else
+ #define dh_ctype_void void
-     ucontext_t *uc = puc;
+ #define dh_ctype_noreturn G_NORETURN void
- #endif
+ #define dh_ctype(t) dh_ctype_##t
-     unsigned long pc;
+@@ -XXX,XX +XXX,XX @@
-+    uint32_t fsr;
+ #define dh_typecode_f64 dh_typecode_i64
-     int is_write;
+ #define dh_typecode_cptr dh_typecode_ptr
+ #define dh_typecode_env dh_typecode_ptr
- #if defined(__NetBSD__)
++#define dh_typecode_fpst dh_typecode_ptr
-@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo,
+ #define dh_typecode(t) dh_typecode_##t
-     pc = uc->uc_mcontext.arm_pc;
- #endif
+ #define dh_callflag_i32  0
 -    /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
 -     * later processor; on v5 we will always report this as a read).
 +#ifdef __NetBSD__
 +    fsr = si->si_trap;
 +#else
 +    fsr = uc->uc_mcontext.error_code;
 +#endif
 +    /*
 +     * In the FSR, bit 11 is WnR, assuming a v6 or
 +     * later processor.  On v5 we will always report
 +     * this as a read, which will fail later.
       */
 -    is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
 +    is_write = extract32(fsr, 11, 1);
      return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
  }
 --
-.25.1
+.43.0

-[PULL 01/12] tcg: Implement gvec support for rotate by immediate
+[PULL 4/4] target/sparc: Use memcpy() and remove memcpy32()
-No host backend support yet, but the interfaces for rotli
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 are in place.  Canonicalize immediate rotate to the left,
 based on a survey of architectures, but provide both left
 and right shift interfaces to the translators.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Rather than manually copying each register, use
 the libc memcpy(), which is well optimized nowadays.
 Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
 Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-ID: <20241205205418.67613-1-philmd@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- accel/tcg/tcg-runtime.h      |  5 +++
+ target/sparc/win_helper.c | 26 ++++++++------------------
- include/tcg/tcg-op-gvec.h    |  6 ++++
+file changed, 8 insertions(+), 18 deletions(-)
  include/tcg/tcg-op.h         |  2 ++
  include/tcg/tcg-opc.h        |  1 +
  include/tcg/tcg.h            |  1 +
  tcg/aarch64/tcg-target.h     |  1 +
  tcg/i386/tcg-target.h        |  1 +
  tcg/ppc/tcg-target.h         |  1 +
  accel/tcg/tcg-runtime-gvec.c | 48 +++++++++++++++++++++++++
  tcg/tcg-op-gvec.c            | 68 ++++++++++++++++++++++++++++++++++++
  tcg/tcg-op-vec.c             | 12 +++++++
  tcg/tcg.c                    |  2 ++
  tcg/README                   |  3 +-
 files changed, 150 insertions(+), 1 deletion(-)
-diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
+diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/tcg-runtime.h
+--- a/target/sparc/win_helper.c
-+++ b/accel/tcg/tcg-runtime.h
++++ b/target/sparc/win_helper.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(gvec_sar16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@
- DEF_HELPER_FLAGS_3(gvec_sar32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+ #include "exec/helper-proto.h"
- DEF_HELPER_FLAGS_3(gvec_sar64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+ #include "trace.h"
-+DEF_HELPER_FLAGS_3(gvec_rotl8i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
-+DEF_HELPER_FLAGS_3(gvec_rotl16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+-{
-+DEF_HELPER_FLAGS_3(gvec_rotl32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+-    dst[0] = src[0];
-+DEF_HELPER_FLAGS_3(gvec_rotl64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+-    dst[1] = src[1];
-+
+-    dst[2] = src[2];
- DEF_HELPER_FLAGS_4(gvec_shl8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+-    dst[3] = src[3];
- DEF_HELPER_FLAGS_4(gvec_shl16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+-    dst[4] = src[4];
- DEF_HELPER_FLAGS_4(gvec_shl32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+-    dst[5] = src[5];
-diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
+-    dst[6] = src[6];
-index XXXXXXX..XXXXXXX 100644
+-    dst[7] = src[7];
---- a/include/tcg/tcg-op-gvec.h
+-}
-+++ b/include/tcg/tcg-op-gvec.h
+-
-@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
+ void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
-                        int64_t shift, uint32_t oprsz, uint32_t maxsz);
+ {
- void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
+     /* put the modified wrap registers at their proper location */
-                        int64_t shift, uint32_t oprsz, uint32_t maxsz);
+     if (env->cwp == env->nwindows - 1) {
-+void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs,
+-        memcpy32(env->regbase, env->regbase + env->nwindows * 16);
-+                        int64_t shift, uint32_t oprsz, uint32_t maxsz);
++        memcpy(env->regbase, env->regbase + env->nwindows * 16,
-+void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs,
++               sizeof(env->gregs));
-+                        int64_t shift, uint32_t oprsz, uint32_t maxsz);
+     }
+     env->cwp = new_cwp;
- void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs,
-                        TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
+     /* put the wrap registers at their temporary location */
-@@ -XXX,XX +XXX,XX @@ void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
+     if (new_cwp == env->nwindows - 1) {
- void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
+-        memcpy32(env->regbase + env->nwindows * 16, env->regbase);
- void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
++        memcpy(env->regbase + env->nwindows * 16, env->regbase,
- void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
++               sizeof(env->gregs));
-+void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c);
+     }
-+void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c);
+     env->regwptr = env->regbase + (new_cwp * 16);
  #endif
 diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/tcg/tcg-op.h
 +++ b/include/tcg/tcg-op.h
@@ -XXX,XX +XXX,XX @@ void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
  void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
  void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
  void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
 +void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
 +void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
  void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
  void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
 diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/tcg/tcg-opc.h
 +++ b/include/tcg/tcg-opc.h
@@ -XXX,XX +XXX,XX @@ DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
  DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
  DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
  DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
 +DEF(rotli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_roti_vec))
  DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
  DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/tcg/tcg.h
 +++ b/include/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@ typedef uint64_t TCGRegSet;
  #define TCG_TARGET_HAS_not_vec          0
  #define TCG_TARGET_HAS_andc_vec         0
  #define TCG_TARGET_HAS_orc_vec          0
 +#define TCG_TARGET_HAS_roti_vec         0
  #define TCG_TARGET_HAS_shi_vec          0
  #define TCG_TARGET_HAS_shs_vec          0
  #define TCG_TARGET_HAS_shv_vec          0
 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/aarch64/tcg-target.h
 +++ b/tcg/aarch64/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
  #define TCG_TARGET_HAS_not_vec          1
  #define TCG_TARGET_HAS_neg_vec          1
  #define TCG_TARGET_HAS_abs_vec          1
 +#define TCG_TARGET_HAS_roti_vec         0
  #define TCG_TARGET_HAS_shi_vec          1
  #define TCG_TARGET_HAS_shs_vec          0
  #define TCG_TARGET_HAS_shv_vec          1
 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/i386/tcg-target.h
 +++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
  #define TCG_TARGET_HAS_not_vec          0
  #define TCG_TARGET_HAS_neg_vec          0
  #define TCG_TARGET_HAS_abs_vec          1
 +#define TCG_TARGET_HAS_roti_vec         0
  #define TCG_TARGET_HAS_shi_vec          1
  #define TCG_TARGET_HAS_shs_vec          1
  #define TCG_TARGET_HAS_shv_vec          have_avx2
 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/ppc/tcg-target.h
 +++ b/tcg/ppc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;
  #define TCG_TARGET_HAS_not_vec          1
  #define TCG_TARGET_HAS_neg_vec          have_isa_3_00
  #define TCG_TARGET_HAS_abs_vec          0
 +#define TCG_TARGET_HAS_roti_vec         0
  #define TCG_TARGET_HAS_shi_vec          0
  #define TCG_TARGET_HAS_shs_vec          0
  #define TCG_TARGET_HAS_shv_vec          1
 diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/tcg/tcg-runtime-gvec.c
 +++ b/accel/tcg/tcg-runtime-gvec.c
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sar64i)(void *d, void *a, uint32_t desc)
      clear_high(d, oprsz, desc);
  }
+@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
-+void HELPER(gvec_rotl8i)(void *d, void *a, uint32_t desc)
+     dst = get_gl_gregset(env, env->gl);
-+{
-+    intptr_t oprsz = simd_oprsz(desc);
+     if (src != dst) {
-+    int shift = simd_data(desc);
+-        memcpy32(dst, env->gregs);
-+    intptr_t i;
+-        memcpy32(env->gregs, src);
-+
++        memcpy(dst, env->gregs, sizeof(env->gregs));
-+    for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
++        memcpy(env->gregs, src, sizeof(env->gregs));
 +        *(uint8_t *)(d + i) = rol8(*(uint8_t *)(a + i), shift);
 +    }
 +    clear_high(d, oprsz, desc);
 +}
 +
 +void HELPER(gvec_rotl16i)(void *d, void *a, uint32_t desc)
 +{
 +    intptr_t oprsz = simd_oprsz(desc);
 +    int shift = simd_data(desc);
 +    intptr_t i;
 +
 +    for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
 +        *(uint16_t *)(d + i) = rol16(*(uint16_t *)(a + i), shift);
 +    }
 +    clear_high(d, oprsz, desc);
 +}
 +
 +void HELPER(gvec_rotl32i)(void *d, void *a, uint32_t desc)
 +{
 +    intptr_t oprsz = simd_oprsz(desc);
 +    int shift = simd_data(desc);
 +    intptr_t i;
 +
 +    for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
 +        *(uint32_t *)(d + i) = rol32(*(uint32_t *)(a + i), shift);
 +    }
 +    clear_high(d, oprsz, desc);
 +}
 +
 +void HELPER(gvec_rotl64i)(void *d, void *a, uint32_t desc)
 +{
 +    intptr_t oprsz = simd_oprsz(desc);
 +    int shift = simd_data(desc);
 +    intptr_t i;
 +
 +    for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
 +        *(uint64_t *)(d + i) = rol64(*(uint64_t *)(a + i), shift);
 +    }
 +    clear_high(d, oprsz, desc);
 +}
 +
  void HELPER(gvec_shl8v)(void *d, void *a, void *b, uint32_t desc)
  {
      intptr_t oprsz = simd_oprsz(desc);
 diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/tcg-op-gvec.c
 +++ b/tcg/tcg-op-gvec.c
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
      }
  }
-+void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
+@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
-+{
+         /* Switch global register bank */
-+    uint64_t mask = dup_const(MO_8, 0xff << c);
+         src = get_gregset(env, new_pstate_regs);
-+
+         dst = get_gregset(env, pstate_regs);
-+    tcg_gen_shli_i64(d, a, c);
+-        memcpy32(dst, env->gregs);
-+    tcg_gen_shri_i64(a, a, 8 - c);
+-        memcpy32(env->gregs, src);
-+    tcg_gen_andi_i64(d, d, mask);
++        memcpy(dst, env->gregs, sizeof(env->gregs));
-+    tcg_gen_andi_i64(a, a, ~mask);
++        memcpy(env->gregs, src, sizeof(env->gregs));
-+    tcg_gen_or_i64(d, d, a);
+     } else {
-+}
+         trace_win_helper_no_switch_pstate(new_pstate_regs);
-+
+     }
 +void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
 +{
 +    uint64_t mask = dup_const(MO_16, 0xffff << c);
 +
 +    tcg_gen_shli_i64(d, a, c);
 +    tcg_gen_shri_i64(a, a, 16 - c);
 +    tcg_gen_andi_i64(d, d, mask);
 +    tcg_gen_andi_i64(a, a, ~mask);
 +    tcg_gen_or_i64(d, d, a);
 +}
 +
 +void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs,
 +                        int64_t shift, uint32_t oprsz, uint32_t maxsz)
 +{
 +    static const TCGOpcode vecop_list[] = { INDEX_op_rotli_vec, 0 };
 +    static const GVecGen2i g[4] = {
 +        { .fni8 = tcg_gen_vec_rotl8i_i64,
 +          .fniv = tcg_gen_rotli_vec,
 +          .fno = gen_helper_gvec_rotl8i,
 +          .opt_opc = vecop_list,
 +          .vece = MO_8 },
 +        { .fni8 = tcg_gen_vec_rotl16i_i64,
 +          .fniv = tcg_gen_rotli_vec,
 +          .fno = gen_helper_gvec_rotl16i,
 +          .opt_opc = vecop_list,
 +          .vece = MO_16 },
 +        { .fni4 = tcg_gen_rotli_i32,
 +          .fniv = tcg_gen_rotli_vec,
 +          .fno = gen_helper_gvec_rotl32i,
 +          .opt_opc = vecop_list,
 +          .vece = MO_32 },
 +        { .fni8 = tcg_gen_rotli_i64,
 +          .fniv = tcg_gen_rotli_vec,
 +          .fno = gen_helper_gvec_rotl64i,
 +          .opt_opc = vecop_list,
 +          .prefer_i64 = TCG_TARGET_REG_BITS == 64,
 +          .vece = MO_64 },
 +    };
 +
 +    tcg_debug_assert(vece <= MO_64);
 +    tcg_debug_assert(shift >= 0 && shift < (8 << vece));
 +    if (shift == 0) {
 +        tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
 +    } else {
 +        tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]);
 +    }
 +}
 +
 +void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs,
 +                        int64_t shift, uint32_t oprsz, uint32_t maxsz)
 +{
 +    tcg_debug_assert(vece <= MO_64);
 +    tcg_debug_assert(shift >= 0 && shift < (8 << vece));
 +    tcg_gen_gvec_rotli(vece, dofs, aofs, -shift & ((8 << vece) - 1),
 +                       oprsz, maxsz);
 +}
 +
  /*
   * Specialized generation vector shifts by a non-constant scalar.
   */
 diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/tcg-op-vec.c
 +++ b/tcg/tcg-op-vec.c
@@ -XXX,XX +XXX,XX @@ void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
      do_shifti(INDEX_op_sari_vec, vece, r, a, i);
  }
 +void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
 +{
 +    do_shifti(INDEX_op_rotli_vec, vece, r, a, i);
 +}
 +
 +void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
 +{
 +    int bits = 8 << vece;
 +    tcg_debug_assert(i >= 0 && i < bits);
 +    do_shifti(INDEX_op_rotli_vec, vece, r, a, -i & (bits - 1));
 +}
 +
  void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
                       TCGv_vec r, TCGv_vec a, TCGv_vec b)
  {
 diff --git a/tcg/tcg.c b/tcg/tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/tcg.c
 +++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op)
      case INDEX_op_shrv_vec:
      case INDEX_op_sarv_vec:
          return have_vec && TCG_TARGET_HAS_shv_vec;
 +    case INDEX_op_rotli_vec:
 +        return have_vec && TCG_TARGET_HAS_roti_vec;
      case INDEX_op_ssadd_vec:
      case INDEX_op_usadd_vec:
      case INDEX_op_sssub_vec:
 diff --git a/tcg/README b/tcg/README
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/README
 +++ b/tcg/README
@@ -XXX,XX +XXX,XX @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
  * shri_vec   v0, v1, i2
  * sari_vec   v0, v1, i2
 +* rotli_vec  v0, v1, i2
  * shrs_vec   v0, v1, s2
  * sars_vec   v0, v1, s2
 -  Similarly for logical and arithmetic right shift.
 +  Similarly for logical and arithmetic right shift, and left rotate.
  * shlv_vec   v0, v1, v2
 --
-.25.1
+.43.0

-[PULL 03/12] tcg: Remove expansion to shift by vector from do_shifts
+Deleted patch
-We do not reflect this expansion in tcg_can_emit_vecop_list,
-so it is unused and unusable.  However, we actually perform
-the same expansion in do_gvec_shifts, so it is also unneeded.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/tcg-op-vec.c | 35 +++++++++++------------------------
-file changed, 11 insertions(+), 24 deletions(-)
-diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg-op-vec.c
-+++ b/tcg/tcg-op-vec.c
-@@ -XXX,XX +XXX,XX @@ void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
- }
- static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a,
--                      TCGv_i32 s, TCGOpcode opc_s, TCGOpcode opc_v)
-+                      TCGv_i32 s, TCGOpcode opc)
- {
-     TCGTemp *rt = tcgv_vec_temp(r);
-     TCGTemp *at = tcgv_vec_temp(a);
-@@ -XXX,XX +XXX,XX @@ static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a,
-     TCGArg ai = temp_arg(at);
-     TCGArg si = temp_arg(st);
-     TCGType type = rt->base_type;
--    const TCGOpcode *hold_list;
-     int can;
-     tcg_debug_assert(at->base_type >= type);
--    tcg_assert_listed_vecop(opc_s);
--    hold_list = tcg_swap_vecop_list(NULL);
--
--    can = tcg_can_emit_vec_op(opc_s, type, vece);
-+    tcg_assert_listed_vecop(opc);
-+    can = tcg_can_emit_vec_op(opc, type, vece);
-     if (can > 0) {
--        vec_gen_3(opc_s, type, vece, ri, ai, si);
-+        vec_gen_3(opc, type, vece, ri, ai, si);
-     } else if (can < 0) {
--        tcg_expand_vec_op(opc_s, type, vece, ri, ai, si);
-+        const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
-+        tcg_expand_vec_op(opc, type, vece, ri, ai, si);
-+        tcg_swap_vecop_list(hold_list);
-     } else {
--        TCGv_vec vec_s = tcg_temp_new_vec(type);
--
--        if (vece == MO_64) {
--            TCGv_i64 s64 = tcg_temp_new_i64();
--            tcg_gen_extu_i32_i64(s64, s);
--            tcg_gen_dup_i64_vec(MO_64, vec_s, s64);
--            tcg_temp_free_i64(s64);
--        } else {
--            tcg_gen_dup_i32_vec(vece, vec_s, s);
--        }
--        do_op3_nofail(vece, r, a, vec_s, opc_v);
--        tcg_temp_free_vec(vec_s);
-+        g_assert_not_reached();
-     }
--    tcg_swap_vecop_list(hold_list);
- }
- void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b)
- {
--    do_shifts(vece, r, a, b, INDEX_op_shls_vec, INDEX_op_shlv_vec);
-+    do_shifts(vece, r, a, b, INDEX_op_shls_vec);
- }
- void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b)
- {
--    do_shifts(vece, r, a, b, INDEX_op_shrs_vec, INDEX_op_shrv_vec);
-+    do_shifts(vece, r, a, b, INDEX_op_shrs_vec);
- }
- void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b)
- {
--    do_shifts(vece, r, a, b, INDEX_op_sars_vec, INDEX_op_sarv_vec);
-+    do_shifts(vece, r, a, b, INDEX_op_sars_vec);
- }
- void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a,
---
-.25.1

-[PULL 04/12] tcg: Implement gvec support for rotate by scalar
+Deleted patch
-No host backend support yet, but the interfaces for rotls
-are in place.  Only implement left-rotate for now, as the
-only known use of vector rotate by scalar is s390x, so any
-right-rotate would be unused and untestable.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- include/tcg/tcg-op-gvec.h |  2 ++
- include/tcg/tcg-op.h      |  1 +
- include/tcg/tcg-opc.h     |  1 +
- include/tcg/tcg.h         |  1 +
- tcg/aarch64/tcg-target.h  |  1 +
- tcg/i386/tcg-target.h     |  1 +
- tcg/ppc/tcg-target.h      |  1 +
- tcg/tcg-op-gvec.c         | 22 ++++++++++++++++++++++
- tcg/tcg-op-vec.c          |  5 +++++
- tcg/tcg.c                 |  2 ++
-files changed, 37 insertions(+)
-diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/tcg/tcg-op-gvec.h
-+++ b/include/tcg/tcg-op-gvec.h
-@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs,
-                        TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
- void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs,
-                        TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
-+void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs,
-+                        TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
- /*
-  * Perform vector shift by vector element, modulo the element size.
-diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/tcg/tcg-op.h
-+++ b/include/tcg/tcg-op.h
-@@ -XXX,XX +XXX,XX @@ void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
- void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
- void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
- void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
-+void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
- void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
- void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
-diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/tcg/tcg-opc.h
-+++ b/include/tcg/tcg-opc.h
-@@ -XXX,XX +XXX,XX @@ DEF(rotli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_roti_vec))
- DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
- DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
- DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
-+DEF(rotls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rots_vec))
- DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
- DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
-diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/tcg/tcg.h
-+++ b/include/tcg/tcg.h
-@@ -XXX,XX +XXX,XX @@ typedef uint64_t TCGRegSet;
- #define TCG_TARGET_HAS_andc_vec         0
- #define TCG_TARGET_HAS_orc_vec          0
- #define TCG_TARGET_HAS_roti_vec         0
-+#define TCG_TARGET_HAS_rots_vec         0
- #define TCG_TARGET_HAS_rotv_vec         0
- #define TCG_TARGET_HAS_shi_vec          0
- #define TCG_TARGET_HAS_shs_vec          0
-diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/aarch64/tcg-target.h
-+++ b/tcg/aarch64/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ typedef enum {
- #define TCG_TARGET_HAS_neg_vec          1
- #define TCG_TARGET_HAS_abs_vec          1
- #define TCG_TARGET_HAS_roti_vec         0
-+#define TCG_TARGET_HAS_rots_vec         0
- #define TCG_TARGET_HAS_rotv_vec         0
- #define TCG_TARGET_HAS_shi_vec          1
- #define TCG_TARGET_HAS_shs_vec          0
-diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/i386/tcg-target.h
-+++ b/tcg/i386/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
- #define TCG_TARGET_HAS_neg_vec          0
- #define TCG_TARGET_HAS_abs_vec          1
- #define TCG_TARGET_HAS_roti_vec         0
-+#define TCG_TARGET_HAS_rots_vec         0
- #define TCG_TARGET_HAS_rotv_vec         0
- #define TCG_TARGET_HAS_shi_vec          1
- #define TCG_TARGET_HAS_shs_vec          1
-diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/ppc/tcg-target.h
-+++ b/tcg/ppc/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;
- #define TCG_TARGET_HAS_neg_vec          have_isa_3_00
- #define TCG_TARGET_HAS_abs_vec          0
- #define TCG_TARGET_HAS_roti_vec         0
-+#define TCG_TARGET_HAS_rots_vec         0
- #define TCG_TARGET_HAS_rotv_vec         0
- #define TCG_TARGET_HAS_shi_vec          0
- #define TCG_TARGET_HAS_shs_vec          0
-diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg-op-gvec.c
-+++ b/tcg/tcg-op-gvec.c
-@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs,
-     do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g);
- }
-+void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs,
-+                        TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz)
-+{
-+    static const GVecGen2sh g = {
-+        .fni4 = tcg_gen_rotl_i32,
-+        .fni8 = tcg_gen_rotl_i64,
-+        .fniv_s = tcg_gen_rotls_vec,
-+        .fniv_v = tcg_gen_rotlv_vec,
-+        .fno = {
-+            gen_helper_gvec_rotl8i,
-+            gen_helper_gvec_rotl16i,
-+            gen_helper_gvec_rotl32i,
-+            gen_helper_gvec_rotl64i,
-+        },
-+        .s_list = { INDEX_op_rotls_vec, 0 },
-+        .v_list = { INDEX_op_rotlv_vec, 0 },
-+    };
-+
-+    tcg_debug_assert(vece <= MO_64);
-+    do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g);
-+}
-+
- /*
-  * Expand D = A << (B % element bits)
-  *
-diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg-op-vec.c
-+++ b/tcg/tcg-op-vec.c
-@@ -XXX,XX +XXX,XX @@ void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b)
-     do_shifts(vece, r, a, b, INDEX_op_sars_vec);
- }
-+void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s)
-+{
-+    do_shifts(vece, r, a, s, INDEX_op_rotls_vec);
-+}
-+
- void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a,
-                         TCGv_vec b, TCGv_vec c)
- {
-diff --git a/tcg/tcg.c b/tcg/tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg.c
-+++ b/tcg/tcg.c
-@@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op)
-         return have_vec && TCG_TARGET_HAS_shv_vec;
-     case INDEX_op_rotli_vec:
-         return have_vec && TCG_TARGET_HAS_roti_vec;
-+    case INDEX_op_rotls_vec:
-+        return have_vec && TCG_TARGET_HAS_rots_vec;
-     case INDEX_op_rotlv_vec:
-     case INDEX_op_rotrv_vec:
-         return have_vec && TCG_TARGET_HAS_rotv_vec;
---
-.25.1

-[PULL 05/12] tcg/i386: Implement INDEX_op_rotl{i,s,v}_vec
+Deleted patch
-For immediates, we must continue the special casing of 8-bit
-elements.  The other element sizes and shift types are trivially
-implemented with shifts.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/i386/tcg-target.inc.c | 116 ++++++++++++++++++++++++++++++++------
-file changed, 100 insertions(+), 16 deletions(-)
-diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/i386/tcg-target.inc.c
-+++ b/tcg/i386/tcg-target.inc.c
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_shls_vec:
-     case INDEX_op_shrs_vec:
-     case INDEX_op_sars_vec:
-+    case INDEX_op_rotls_vec:
-     case INDEX_op_cmp_vec:
-     case INDEX_op_x86_shufps_vec:
-     case INDEX_op_x86_blend_vec:
-@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
-     case INDEX_op_xor_vec:
-     case INDEX_op_andc_vec:
-         return 1;
-+    case INDEX_op_rotli_vec:
-     case INDEX_op_cmp_vec:
-     case INDEX_op_cmpsel_vec:
-         return -1;
-@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
-         return vece >= MO_16;
-     case INDEX_op_sars_vec:
-         return vece >= MO_16 && vece <= MO_32;
-+    case INDEX_op_rotls_vec:
-+        return vece >= MO_16 ? -1 : 0;
-     case INDEX_op_shlv_vec:
-     case INDEX_op_shrv_vec:
-         return have_avx2 && vece >= MO_32;
-     case INDEX_op_sarv_vec:
-         return have_avx2 && vece == MO_32;
-+    case INDEX_op_rotlv_vec:
-+    case INDEX_op_rotrv_vec:
-+        return have_avx2 && vece >= MO_32 ? -1 : 0;
-     case INDEX_op_mul_vec:
-         if (vece == MO_8) {
-@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
-     }
- }
--static void expand_vec_shi(TCGType type, unsigned vece, bool shr,
-+static void expand_vec_shi(TCGType type, unsigned vece, TCGOpcode opc,
-                            TCGv_vec v0, TCGv_vec v1, TCGArg imm)
- {
-     TCGv_vec t1, t2;
-@@ -XXX,XX +XXX,XX @@ static void expand_vec_shi(TCGType type, unsigned vece, bool shr,
-     t1 = tcg_temp_new_vec(type);
-     t2 = tcg_temp_new_vec(type);
--    /* Unpack to W, shift, and repack.  Tricky bits:
--       (1) Use punpck*bw x,x to produce DDCCBBAA,
--           i.e. duplicate in other half of the 16-bit lane.
--       (2) For right-shift, add 8 so that the high half of
--           the lane becomes zero.  For left-shift, we must
--           shift up and down again.
--       (3) Step 2 leaves high half zero such that PACKUSWB
--           (pack with unsigned saturation) does not modify
--           the quantity.  */
-+    /*
-+     * Unpack to W, shift, and repack.  Tricky bits:
-+     * (1) Use punpck*bw x,x to produce DDCCBBAA,
-+     *     i.e. duplicate in other half of the 16-bit lane.
-+     * (2) For right-shift, add 8 so that the high half of the lane
-+     *     becomes zero.  For left-shift, and left-rotate, we must
-+     *     shift up and down again.
-+     * (3) Step 2 leaves high half zero such that PACKUSWB
-+     *     (pack with unsigned saturation) does not modify
-+     *     the quantity.
-+     */
-     vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
-               tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
-     vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
-               tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
--    if (shr) {
--        tcg_gen_shri_vec(MO_16, t1, t1, imm + 8);
--        tcg_gen_shri_vec(MO_16, t2, t2, imm + 8);
-+    if (opc != INDEX_op_rotli_vec) {
-+        imm += 8;
-+    }
-+    if (opc == INDEX_op_shri_vec) {
-+        tcg_gen_shri_vec(MO_16, t1, t1, imm);
-+        tcg_gen_shri_vec(MO_16, t2, t2, imm);
-     } else {
--        tcg_gen_shli_vec(MO_16, t1, t1, imm + 8);
--        tcg_gen_shli_vec(MO_16, t2, t2, imm + 8);
-+        tcg_gen_shli_vec(MO_16, t1, t1, imm);
-+        tcg_gen_shli_vec(MO_16, t2, t2, imm);
-         tcg_gen_shri_vec(MO_16, t1, t1, 8);
-         tcg_gen_shri_vec(MO_16, t2, t2, 8);
-     }
-@@ -XXX,XX +XXX,XX @@ static void expand_vec_sari(TCGType type, unsigned vece,
-     }
- }
-+static void expand_vec_rotli(TCGType type, unsigned vece,
-+                             TCGv_vec v0, TCGv_vec v1, TCGArg imm)
-+{
-+    TCGv_vec t;
-+
-+    if (vece == MO_8) {
-+        expand_vec_shi(type, vece, INDEX_op_rotli_vec, v0, v1, imm);
-+        return;
-+    }
-+
-+    t = tcg_temp_new_vec(type);
-+    tcg_gen_shli_vec(vece, t, v1, imm);
-+    tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm);
-+    tcg_gen_or_vec(vece, v0, v0, t);
-+    tcg_temp_free_vec(t);
-+}
-+
-+static void expand_vec_rotls(TCGType type, unsigned vece,
-+                             TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh)
-+{
-+    TCGv_i32 rsh;
-+    TCGv_vec t;
-+
-+    tcg_debug_assert(vece != MO_8);
-+
-+    t = tcg_temp_new_vec(type);
-+    rsh = tcg_temp_new_i32();
-+
-+    tcg_gen_neg_i32(rsh, lsh);
-+    tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1);
-+    tcg_gen_shls_vec(vece, t, v1, lsh);
-+    tcg_gen_shrs_vec(vece, v0, v1, rsh);
-+    tcg_gen_or_vec(vece, v0, v0, t);
-+    tcg_temp_free_vec(t);
-+    tcg_temp_free_i32(rsh);
-+}
-+
-+static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0,
-+                            TCGv_vec v1, TCGv_vec sh, bool right)
-+{
-+    TCGv_vec t = tcg_temp_new_vec(type);
-+
-+    tcg_gen_dupi_vec(vece, t, 8 << vece);
-+    tcg_gen_sub_vec(vece, t, t, sh);
-+    if (right) {
-+        tcg_gen_shlv_vec(vece, t, v1, t);
-+        tcg_gen_shrv_vec(vece, v0, v1, sh);
-+    } else {
-+        tcg_gen_shrv_vec(vece, t, v1, t);
-+        tcg_gen_shlv_vec(vece, v0, v1, sh);
-+    }
-+    tcg_gen_or_vec(vece, v0, v0, t);
-+    tcg_temp_free_vec(t);
-+}
-+
- static void expand_vec_mul(TCGType type, unsigned vece,
-                            TCGv_vec v0, TCGv_vec v1, TCGv_vec v2)
- {
-@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
-     switch (opc) {
-     case INDEX_op_shli_vec:
-     case INDEX_op_shri_vec:
--        expand_vec_shi(type, vece, opc == INDEX_op_shri_vec, v0, v1, a2);
-+        expand_vec_shi(type, vece, opc, v0, v1, a2);
-         break;
-     case INDEX_op_sari_vec:
-         expand_vec_sari(type, vece, v0, v1, a2);
-         break;
-+    case INDEX_op_rotli_vec:
-+        expand_vec_rotli(type, vece, v0, v1, a2);
-+        break;
-+
-+    case INDEX_op_rotls_vec:
-+        expand_vec_rotls(type, vece, v0, v1, temp_tcgv_i32(arg_temp(a2)));
-+        break;
-+
-+    case INDEX_op_rotlv_vec:
-+        v2 = temp_tcgv_vec(arg_temp(a2));
-+        expand_vec_rotv(type, vece, v0, v1, v2, false);
-+        break;
-+    case INDEX_op_rotrv_vec:
-+        v2 = temp_tcgv_vec(arg_temp(a2));
-+        expand_vec_rotv(type, vece, v0, v1, v2, true);
-+        break;
-+
-     case INDEX_op_mul_vec:
-         v2 = temp_tcgv_vec(arg_temp(a2));
-         expand_vec_mul(type, vece, v0, v1, v2);
---
-.25.1

-[PULL 06/12] tcg/aarch64: Implement INDEX_op_rotl{i,v}_vec
+Deleted patch
-For immediate rotate , we can implement this in two instructions,
-using SLI.  For variable rotate, the oddness of aarch64 right-shift-
-as-negative-left-shift means a backend-specific expansion works best.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/aarch64/tcg-target.opc.h |  1 +
- tcg/aarch64/tcg-target.inc.c | 53 ++++++++++++++++++++++++++++++++++--
-files changed, 52 insertions(+), 2 deletions(-)
-diff --git a/tcg/aarch64/tcg-target.opc.h b/tcg/aarch64/tcg-target.opc.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/aarch64/tcg-target.opc.h
-+++ b/tcg/aarch64/tcg-target.opc.h
-@@ -XXX,XX +XXX,XX @@
-  */
- DEF(aa64_sshl_vec, 1, 2, 0, IMPLVEC)
-+DEF(aa64_sli_vec, 1, 2, 1, IMPLVEC)
-diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/aarch64/tcg-target.inc.c
-+++ b/tcg/aarch64/tcg-target.inc.c
-@@ -XXX,XX +XXX,XX @@ typedef enum {
-     I3614_SSHR      = 0x0f000400,
-     I3614_SSRA      = 0x0f001400,
-     I3614_SHL       = 0x0f005400,
-+    I3614_SLI       = 0x2f005400,
-     I3614_USHR      = 0x2f000400,
-     I3614_USRA      = 0x2f001400,
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
-     case INDEX_op_sari_vec:
-         tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2);
-         break;
-+    case INDEX_op_aa64_sli_vec:
-+        tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece));
-+        break;
-     case INDEX_op_shlv_vec:
-         tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2);
-         break;
-@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
-     case INDEX_op_shlv_vec:
-     case INDEX_op_bitsel_vec:
-         return 1;
-+    case INDEX_op_rotli_vec:
-     case INDEX_op_shrv_vec:
-     case INDEX_op_sarv_vec:
-+    case INDEX_op_rotlv_vec:
-+    case INDEX_op_rotrv_vec:
-         return -1;
-     case INDEX_op_mul_vec:
-     case INDEX_op_smax_vec:
-@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
-                        TCGArg a0, ...)
- {
-     va_list va;
--    TCGv_vec v0, v1, v2, t1;
-+    TCGv_vec v0, v1, v2, t1, t2;
-+    TCGArg a2;
-     va_start(va, a0);
-     v0 = temp_tcgv_vec(arg_temp(a0));
-     v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
--    v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
-+    a2 = va_arg(va, TCGArg);
-+    v2 = temp_tcgv_vec(arg_temp(a2));
-     switch (opc) {
-+    case INDEX_op_rotli_vec:
-+        t1 = tcg_temp_new_vec(type);
-+        tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1));
-+        vec_gen_4(INDEX_op_aa64_sli_vec, type, vece,
-+                  tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2);
-+        tcg_temp_free_vec(t1);
-+        break;
-+
-     case INDEX_op_shrv_vec:
-     case INDEX_op_sarv_vec:
-         /* Right shifts are negative left shifts for AArch64.  */
-@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
-         tcg_temp_free_vec(t1);
-         break;
-+    case INDEX_op_rotlv_vec:
-+        t1 = tcg_temp_new_vec(type);
-+        tcg_gen_dupi_vec(vece, t1, 8 << vece);
-+        tcg_gen_sub_vec(vece, t1, v2, t1);
-+        /* Right shifts are negative left shifts for AArch64.  */
-+        vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1),
-+                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
-+        vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(v0),
-+                  tcgv_vec_arg(v1), tcgv_vec_arg(v2));
-+        tcg_gen_or_vec(vece, v0, v0, t1);
-+        tcg_temp_free_vec(t1);
-+        break;
-+
-+    case INDEX_op_rotrv_vec:
-+        t1 = tcg_temp_new_vec(type);
-+        t2 = tcg_temp_new_vec(type);
-+        tcg_gen_neg_vec(vece, t1, v2);
-+        tcg_gen_dupi_vec(vece, t2, 8 << vece);
-+        tcg_gen_add_vec(vece, t2, t1, t2);
-+        /* Right shifts are negative left shifts for AArch64.  */
-+        vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1),
-+                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
-+        vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t2),
-+                  tcgv_vec_arg(v1), tcgv_vec_arg(t2));
-+        tcg_gen_or_vec(vece, v0, t1, t2);
-+        tcg_temp_free_vec(t1);
-+        tcg_temp_free_vec(t2);
-+        break;
-+
-     default:
-         g_assert_not_reached();
-     }
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } };
-     static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
-     static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } };
-+    static const TCGTargetOpDef w_0_w = { .args_ct_str = { "w", "0", "w" } };
-     static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } };
-     static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } };
-     static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } };
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-         return &w_w_wZ;
-     case INDEX_op_bitsel_vec:
-         return &w_w_w_w;
-+    case INDEX_op_aa64_sli_vec:
-+        return &w_0_w;
-     default:
-         return NULL;
---
-.25.1

-[PULL 07/12] tcg/ppc: Implement INDEX_op_rot[lr]v_vec
+Deleted patch
-We already had support for rotlv, using a target-specific opcode;
-convert to use the generic opcode.  Handle rotrv via simple negation.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/ppc/tcg-target.h     |  2 +-
- tcg/ppc/tcg-target.opc.h |  1 -
- tcg/ppc/tcg-target.inc.c | 23 +++++++++++++++++++----
-files changed, 20 insertions(+), 6 deletions(-)
-diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/ppc/tcg-target.h
-+++ b/tcg/ppc/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;
- #define TCG_TARGET_HAS_abs_vec          0
- #define TCG_TARGET_HAS_roti_vec         0
- #define TCG_TARGET_HAS_rots_vec         0
--#define TCG_TARGET_HAS_rotv_vec         0
-+#define TCG_TARGET_HAS_rotv_vec         1
- #define TCG_TARGET_HAS_shi_vec          0
- #define TCG_TARGET_HAS_shs_vec          0
- #define TCG_TARGET_HAS_shv_vec          1
-diff --git a/tcg/ppc/tcg-target.opc.h b/tcg/ppc/tcg-target.opc.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/ppc/tcg-target.opc.h
-+++ b/tcg/ppc/tcg-target.opc.h
-@@ -XXX,XX +XXX,XX @@ DEF(ppc_msum_vec, 1, 3, 0, IMPLVEC)
- DEF(ppc_muleu_vec, 1, 2, 0, IMPLVEC)
- DEF(ppc_mulou_vec, 1, 2, 0, IMPLVEC)
- DEF(ppc_pkum_vec, 1, 2, 0, IMPLVEC)
--DEF(ppc_rotl_vec, 1, 2, 0, IMPLVEC)
-diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/ppc/tcg-target.inc.c
-+++ b/tcg/ppc/tcg-target.inc.c
-@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
-     case INDEX_op_shlv_vec:
-     case INDEX_op_shrv_vec:
-     case INDEX_op_sarv_vec:
-+    case INDEX_op_rotlv_vec:
-         return vece <= MO_32 || have_isa_2_07;
-     case INDEX_op_ssadd_vec:
-     case INDEX_op_sssub_vec:
-@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
-     case INDEX_op_shli_vec:
-     case INDEX_op_shri_vec:
-     case INDEX_op_sari_vec:
-+    case INDEX_op_rotli_vec:
-         return vece <= MO_32 || have_isa_2_07 ? -1 : 0;
-     case INDEX_op_neg_vec:
-         return vece >= MO_32 && have_isa_3_00;
-@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
-         return 0;
-     case INDEX_op_bitsel_vec:
-         return have_vsx;
-+    case INDEX_op_rotrv_vec:
-+        return -1;
-     default:
-         return 0;
-     }
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
-     case INDEX_op_ppc_pkum_vec:
-         insn = pkum_op[vece];
-         break;
--    case INDEX_op_ppc_rotl_vec:
-+    case INDEX_op_rotlv_vec:
-         insn = rotl_op[vece];
-         break;
-     case INDEX_op_ppc_msum_vec:
-@@ -XXX,XX +XXX,XX @@ static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0,
-         t3 = tcg_temp_new_vec(type);
-         t4 = tcg_temp_new_vec(type);
-         tcg_gen_dupi_vec(MO_8, t4, -16);
--        vec_gen_3(INDEX_op_ppc_rotl_vec, type, MO_32, tcgv_vec_arg(t1),
-+        vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1),
-                   tcgv_vec_arg(v2), tcgv_vec_arg(t4));
-         vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2),
-                   tcgv_vec_arg(v1), tcgv_vec_arg(v2));
-@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
-                        TCGArg a0, ...)
- {
-     va_list va;
--    TCGv_vec v0, v1, v2;
-+    TCGv_vec v0, v1, v2, t0;
-     TCGArg a2;
-     va_start(va, a0);
-@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
-     case INDEX_op_sari_vec:
-         expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec);
-         break;
-+    case INDEX_op_rotli_vec:
-+        expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec);
-+        break;
-     case INDEX_op_cmp_vec:
-         v2 = temp_tcgv_vec(arg_temp(a2));
-         expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
-@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
-         v2 = temp_tcgv_vec(arg_temp(a2));
-         expand_vec_mul(type, vece, v0, v1, v2);
-         break;
-+    case INDEX_op_rotlv_vec:
-+        v2 = temp_tcgv_vec(arg_temp(a2));
-+        t0 = tcg_temp_new_vec(type);
-+        tcg_gen_neg_vec(vece, t0, v2);
-+        tcg_gen_rotlv_vec(vece, v0, v1, t0);
-+        tcg_temp_free_vec(t0);
-+        break;
-     default:
-         g_assert_not_reached();
-     }
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_shlv_vec:
-     case INDEX_op_shrv_vec:
-     case INDEX_op_sarv_vec:
-+    case INDEX_op_rotlv_vec:
-+    case INDEX_op_rotrv_vec:
-     case INDEX_op_ppc_mrgh_vec:
-     case INDEX_op_ppc_mrgl_vec:
-     case INDEX_op_ppc_muleu_vec:
-     case INDEX_op_ppc_mulou_vec:
-     case INDEX_op_ppc_pkum_vec:
--    case INDEX_op_ppc_rotl_vec:
-     case INDEX_op_dup2_vec:
-         return &v_v_v;
-     case INDEX_op_not_vec:
---
-.25.1

-[PULL 08/12] target/ppc: Use tcg_gen_gvec_rotlv
+Deleted patch
-Acked-by: David Gibson <david@gibson.dropbear.id.au>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- target/ppc/helper.h                 |  4 ----
- target/ppc/int_helper.c             | 17 -----------------
- target/ppc/translate/vmx-impl.inc.c |  8 ++++----
-files changed, 4 insertions(+), 25 deletions(-)
-diff --git a/target/ppc/helper.h b/target/ppc/helper.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/ppc/helper.h
-+++ b/target/ppc/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vsubuqm, void, avr, avr, avr)
- DEF_HELPER_4(vsubecuq, void, avr, avr, avr, avr)
- DEF_HELPER_4(vsubeuqm, void, avr, avr, avr, avr)
- DEF_HELPER_3(vsubcuq, void, avr, avr, avr)
--DEF_HELPER_3(vrlb, void, avr, avr, avr)
--DEF_HELPER_3(vrlh, void, avr, avr, avr)
--DEF_HELPER_3(vrlw, void, avr, avr, avr)
--DEF_HELPER_3(vrld, void, avr, avr, avr)
- DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32)
- DEF_HELPER_3(vextractub, void, avr, avr, i32)
- DEF_HELPER_3(vextractuh, void, avr, avr, i32)
-diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/ppc/int_helper.c
-+++ b/target/ppc/int_helper.c
-@@ -XXX,XX +XXX,XX @@ VRFI(p, float_round_up)
- VRFI(z, float_round_to_zero)
- #undef VRFI
--#define VROTATE(suffix, element, mask)                                  \
--    void helper_vrl##suffix(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)   \
--    {                                                                   \
--        int i;                                                          \
--                                                                        \
--        for (i = 0; i < ARRAY_SIZE(r->element); i++) {                  \
--            unsigned int shift = b->element[i] & mask;                  \
--            r->element[i] = (a->element[i] << shift) |                  \
--                (a->element[i] >> (sizeof(a->element[0]) * 8 - shift)); \
--        }                                                               \
--    }
--VROTATE(b, u8, 0x7)
--VROTATE(h, u16, 0xF)
--VROTATE(w, u32, 0x1F)
--VROTATE(d, u64, 0x3F)
--#undef VROTATE
--
- void helper_vrsqrtefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b)
- {
-     int i;
-diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/ppc/translate/vmx-impl.inc.c
-+++ b/target/ppc/translate/vmx-impl.inc.c
-@@ -XXX,XX +XXX,XX @@ GEN_VXFORM3(vsubeuqm, 31, 0);
- GEN_VXFORM3(vsubecuq, 31, 0);
- GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
-             vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
--GEN_VXFORM(vrlb, 2, 0);
--GEN_VXFORM(vrlh, 2, 1);
--GEN_VXFORM(vrlw, 2, 2);
-+GEN_VXFORM_V(vrlb, MO_8, tcg_gen_gvec_rotlv, 2, 0);
-+GEN_VXFORM_V(vrlh, MO_16, tcg_gen_gvec_rotlv, 2, 1);
-+GEN_VXFORM_V(vrlw, MO_32, tcg_gen_gvec_rotlv, 2, 2);
- GEN_VXFORM(vrlwmi, 2, 2);
- GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \
-                 vrlwmi, PPC_NONE, PPC2_ISA300)
--GEN_VXFORM(vrld, 2, 3);
-+GEN_VXFORM_V(vrld, MO_64, tcg_gen_gvec_rotlv, 2, 3);
- GEN_VXFORM(vrldmi, 2, 3);
- GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \
-                 vrldmi, PPC_NONE, PPC2_ISA300)
---
-.25.1

-[PULL 09/12] target/s390x: Use tcg_gen_gvec_rotl{i,s,v}
+Deleted patch
-Merge VERLL and VERLLV into op_vesv and op_ves, alongside
-all of the other vector shift operations.
-Reviewed-by: David Hildenbrand <david@redhat.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- target/s390x/helper.h           |  4 --
- target/s390x/translate_vx.inc.c | 66 +++++----------------------------
- target/s390x/vec_int_helper.c   | 31 ----------------
- target/s390x/insn-data.def      |  4 +-
-files changed, 11 insertions(+), 94 deletions(-)
-diff --git a/target/s390x/helper.h b/target/s390x/helper.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/s390x/helper.h
-+++ b/target/s390x/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(gvec_vmlo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
- DEF_HELPER_FLAGS_4(gvec_vmlo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
- DEF_HELPER_FLAGS_3(gvec_vpopct8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
- DEF_HELPER_FLAGS_3(gvec_vpopct16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
--DEF_HELPER_FLAGS_4(gvec_verllv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
--DEF_HELPER_FLAGS_4(gvec_verllv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
--DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
--DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
- DEF_HELPER_FLAGS_4(gvec_verim8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
- DEF_HELPER_FLAGS_4(gvec_verim16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
- DEF_HELPER_FLAGS_4(gvec_vsl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
-diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/s390x/translate_vx.inc.c
-+++ b/target/s390x/translate_vx.inc.c
-@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_vpopct(DisasContext *s, DisasOps *o)
-     return DISAS_NEXT;
- }
--static void gen_rll_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
--{
--    TCGv_i32 t0 = tcg_temp_new_i32();
--
--    tcg_gen_andi_i32(t0, b, 31);
--    tcg_gen_rotl_i32(d, a, t0);
--    tcg_temp_free_i32(t0);
--}
--
--static void gen_rll_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
--{
--    TCGv_i64 t0 = tcg_temp_new_i64();
--
--    tcg_gen_andi_i64(t0, b, 63);
--    tcg_gen_rotl_i64(d, a, t0);
--    tcg_temp_free_i64(t0);
--}
--
--static DisasJumpType op_verllv(DisasContext *s, DisasOps *o)
--{
--    const uint8_t es = get_field(s, m4);
--    static const GVecGen3 g[4] = {
--        { .fno = gen_helper_gvec_verllv8, },
--        { .fno = gen_helper_gvec_verllv16, },
--        { .fni4 = gen_rll_i32, },
--        { .fni8 = gen_rll_i64, },
--    };
--
--    if (es > ES_64) {
--        gen_program_exception(s, PGM_SPECIFICATION);
--        return DISAS_NORETURN;
--    }
--
--    gen_gvec_3(get_field(s, v1), get_field(s, v2),
--               get_field(s, v3), &g[es]);
--    return DISAS_NEXT;
--}
--
--static DisasJumpType op_verll(DisasContext *s, DisasOps *o)
--{
--    const uint8_t es = get_field(s, m4);
--    static const GVecGen2s g[4] = {
--        { .fno = gen_helper_gvec_verll8, },
--        { .fno = gen_helper_gvec_verll16, },
--        { .fni4 = gen_rll_i32, },
--        { .fni8 = gen_rll_i64, },
--    };
--
--    if (es > ES_64) {
--        gen_program_exception(s, PGM_SPECIFICATION);
--        return DISAS_NORETURN;
--    }
--    gen_gvec_2s(get_field(s, v1), get_field(s, v3), o->addr1,
--                &g[es]);
--    return DISAS_NEXT;
--}
--
- static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, int32_t c)
- {
-     TCGv_i32 t = tcg_temp_new_i32();
-@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_vesv(DisasContext *s, DisasOps *o)
-     case 0x70:
-         gen_gvec_fn_3(shlv, es, v1, v2, v3);
-         break;
-+    case 0x73:
-+        gen_gvec_fn_3(rotlv, es, v1, v2, v3);
-+        break;
-     case 0x7a:
-         gen_gvec_fn_3(sarv, es, v1, v2, v3);
-         break;
-@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_ves(DisasContext *s, DisasOps *o)
-         case 0x30:
-             gen_gvec_fn_2i(shli, es, v1, v3, d2);
-             break;
-+        case 0x33:
-+            gen_gvec_fn_2i(rotli, es, v1, v3, d2);
-+            break;
-         case 0x3a:
-             gen_gvec_fn_2i(sari, es, v1, v3, d2);
-             break;
-@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_ves(DisasContext *s, DisasOps *o)
-         case 0x30:
-             gen_gvec_fn_2s(shls, es, v1, v3, shift);
-             break;
-+        case 0x33:
-+            gen_gvec_fn_2s(rotls, es, v1, v3, shift);
-+            break;
-         case 0x3a:
-             gen_gvec_fn_2s(sars, es, v1, v3, shift);
-             break;
-diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/s390x/vec_int_helper.c
-+++ b/target/s390x/vec_int_helper.c
-@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_vpopct##BITS)(void *v1, const void *v2, uint32_t desc)        \
- DEF_VPOPCT(8)
- DEF_VPOPCT(16)
--#define DEF_VERLLV(BITS)                                                       \
--void HELPER(gvec_verllv##BITS)(void *v1, const void *v2, const void *v3,       \
--                               uint32_t desc)                                  \
--{                                                                              \
--    int i;                                                                     \
--                                                                               \
--    for (i = 0; i < (128 / BITS); i++) {                                       \
--        const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i);           \
--        const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i);           \
--                                                                               \
--        s390_vec_write_element##BITS(v1, i, rol##BITS(a, b));                  \
--    }                                                                          \
--}
--DEF_VERLLV(8)
--DEF_VERLLV(16)
--
--#define DEF_VERLL(BITS)                                                        \
--void HELPER(gvec_verll##BITS)(void *v1, const void *v2, uint64_t count,        \
--                              uint32_t desc)                                   \
--{                                                                              \
--    int i;                                                                     \
--                                                                               \
--    for (i = 0; i < (128 / BITS); i++) {                                       \
--        const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i);           \
--                                                                               \
--        s390_vec_write_element##BITS(v1, i, rol##BITS(a, count));              \
--    }                                                                          \
--}
--DEF_VERLL(8)
--DEF_VERLL(16)
--
- #define DEF_VERIM(BITS)                                                        \
- void HELPER(gvec_verim##BITS)(void *v1, const void *v2, const void *v3,        \
-                               uint32_t desc)                                   \
-diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
-index XXXXXXX..XXXXXXX 100644
---- a/target/s390x/insn-data.def
-+++ b/target/s390x/insn-data.def
-@@ -XXX,XX +XXX,XX @@
- /* VECTOR POPULATION COUNT */
-     F(0xe750, VPOPCT,  VRR_a, V,   0, 0, 0, 0, vpopct, 0, IF_VEC)
- /* VECTOR ELEMENT ROTATE LEFT LOGICAL */
--    F(0xe773, VERLLV,  VRR_c, V,   0, 0, 0, 0, verllv, 0, IF_VEC)
--    F(0xe733, VERLL,   VRS_a, V,   la2, 0, 0, 0, verll, 0, IF_VEC)
-+    F(0xe773, VERLLV,  VRR_c, V,   0, 0, 0, 0, vesv, 0, IF_VEC)
-+    F(0xe733, VERLL,   VRS_a, V,   la2, 0, 0, 0, ves, 0, IF_VEC)
- /* VECTOR ELEMENT ROTATE AND INSERT UNDER MASK */
-     F(0xe772, VERIM,   VRI_d, V,   0, 0, 0, 0, verim, 0, IF_VEC)
- /* VECTOR ELEMENT SHIFT LEFT */
---
-.25.1

-[PULL 10/12] tcg: Improve move ops in liveness_pass_2
+Deleted patch
-If the output of the move is dead, then the last use is in
-the store.  If we propagate the input to the store, then we
-can remove the move opcode entirely.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/tcg.c | 78 +++++++++++++++++++++++++++++++++++++++----------------
-file changed, 56 insertions(+), 22 deletions(-)
-diff --git a/tcg/tcg.c b/tcg/tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg.c
-+++ b/tcg/tcg.c
-@@ -XXX,XX +XXX,XX @@ static bool liveness_pass_2(TCGContext *s)
-         }
-         /* Outputs become available.  */
--        for (i = 0; i < nb_oargs; i++) {
--            arg_ts = arg_temp(op->args[i]);
-+        if (opc == INDEX_op_mov_i32 || opc == INDEX_op_mov_i64) {
-+            arg_ts = arg_temp(op->args[0]);
-             dir_ts = arg_ts->state_ptr;
--            if (!dir_ts) {
--                continue;
-+            if (dir_ts) {
-+                op->args[0] = temp_arg(dir_ts);
-+                changes = true;
-+
-+                /* The output is now live and modified.  */
-+                arg_ts->state = 0;
-+
-+                if (NEED_SYNC_ARG(0)) {
-+                    TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32
-+                                      ? INDEX_op_st_i32
-+                                      : INDEX_op_st_i64);
-+                    TCGOp *sop = tcg_op_insert_after(s, op, sopc);
-+                    TCGTemp *out_ts = dir_ts;
-+
-+                    if (IS_DEAD_ARG(0)) {
-+                        out_ts = arg_temp(op->args[1]);
-+                        arg_ts->state = TS_DEAD;
-+                        tcg_op_remove(s, op);
-+                    } else {
-+                        arg_ts->state = TS_MEM;
-+                    }
-+
-+                    sop->args[0] = temp_arg(out_ts);
-+                    sop->args[1] = temp_arg(arg_ts->mem_base);
-+                    sop->args[2] = arg_ts->mem_offset;
-+                } else {
-+                    tcg_debug_assert(!IS_DEAD_ARG(0));
-+                }
-             }
--            op->args[i] = temp_arg(dir_ts);
--            changes = true;
-+        } else {
-+            for (i = 0; i < nb_oargs; i++) {
-+                arg_ts = arg_temp(op->args[i]);
-+                dir_ts = arg_ts->state_ptr;
-+                if (!dir_ts) {
-+                    continue;
-+                }
-+                op->args[i] = temp_arg(dir_ts);
-+                changes = true;
--            /* The output is now live and modified.  */
--            arg_ts->state = 0;
-+                /* The output is now live and modified.  */
-+                arg_ts->state = 0;
--            /* Sync outputs upon their last write.  */
--            if (NEED_SYNC_ARG(i)) {
--                TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32
--                                  ? INDEX_op_st_i32
--                                  : INDEX_op_st_i64);
--                TCGOp *sop = tcg_op_insert_after(s, op, sopc);
-+                /* Sync outputs upon their last write.  */
-+                if (NEED_SYNC_ARG(i)) {
-+                    TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32
-+                                      ? INDEX_op_st_i32
-+                                      : INDEX_op_st_i64);
-+                    TCGOp *sop = tcg_op_insert_after(s, op, sopc);
--                sop->args[0] = temp_arg(dir_ts);
--                sop->args[1] = temp_arg(arg_ts->mem_base);
--                sop->args[2] = arg_ts->mem_offset;
-+                    sop->args[0] = temp_arg(dir_ts);
-+                    sop->args[1] = temp_arg(arg_ts->mem_base);
-+                    sop->args[2] = arg_ts->mem_offset;
--                arg_ts->state = TS_MEM;
--            }
--            /* Drop outputs that are dead.  */
--            if (IS_DEAD_ARG(i)) {
--                arg_ts->state = TS_DEAD;
-+                    arg_ts->state = TS_MEM;
-+                }
-+                /* Drop outputs that are dead.  */
-+                if (IS_DEAD_ARG(i)) {
-+                    arg_ts->state = TS_DEAD;
-+                }
-             }
-         }
-     }
---
-.25.1

I have not been able to prod reviews of all of the rotate patches
in 4 weeks, but let's not let that block ARM work forever.

The following changes since commit cccdd8c7971896c339d59c9c5d4647d4ffd9568a:

Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging (2020-06-02 10:25:55 +0100)

are available in the Git repository at:

https://github.com/rth7680/qemu.git tags/pull-tcg-20200602

for you to fetch changes up to 71b04329c4f7d5824a289ca5225e1883a278cf3b:

accel/tcg: Provide a NetBSD specific aarch64 cpu_signal_handler (2020-06-02 08:42:37 -0700)

----------------------------------------------------------------
Vector rotate support
Signal handling support for NetBSD arm/aarch64

----------------------------------------------------------------
Nick Hudson (2):
      accel/tcg: Adjust cpu_signal_handler for NetBSD/arm
      accel/tcg: Provide a NetBSD specific aarch64 cpu_signal_handler

Richard Henderson (10):
      tcg: Implement gvec support for rotate by immediate
      tcg: Implement gvec support for rotate by vector
      tcg: Remove expansion to shift by vector from do_shifts
      tcg: Implement gvec support for rotate by scalar
      tcg/i386: Implement INDEX_op_rotl{i,s,v}_vec
      tcg/aarch64: Implement INDEX_op_rotl{i,v}_vec
      tcg/ppc: Implement INDEX_op_rot[lr]v_vec
      target/ppc: Use tcg_gen_gvec_rotlv
      target/s390x: Use tcg_gen_gvec_rotl{i,s,v}
      tcg: Improve move ops in liveness_pass_2

No host backend support yet, but the interfaces for rotli
are in place.  Canonicalize immediate rotate to the left,
based on a survey of architectures, but provide both left
and right shift interfaces to the translators.

diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(gvec_sar16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 DEF_HELPER_FLAGS_3(gvec_sar32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 DEF_HELPER_FLAGS_3(gvec_sar64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 
+DEF_HELPER_FLAGS_3(gvec_rotl8i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_rotl16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_rotl32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_rotl64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
 DEF_HELPER_FLAGS_4(gvec_shl8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(gvec_shl16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(gvec_shl32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg-op-gvec.h
+++ b/include/tcg/tcg-op-gvec.h
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
                        int64_t shift, uint32_t oprsz, uint32_t maxsz);
 void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
                        int64_t shift, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs,
+                        int64_t shift, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs,
+                        int64_t shift, uint32_t oprsz, uint32_t maxsz);
 
 void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs,
                        TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
@@ -XXX,XX +XXX,XX @@ void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
 void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
 void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
 void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
+void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c);
+void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c);
 
 #endif
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -XXX,XX +XXX,XX @@ void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
 void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
 void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
 void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
+void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
+void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
 
 void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
 void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -XXX,XX +XXX,XX @@ DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
 DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
 DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
 DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
+DEF(rotli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_roti_vec))
 
 DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
 DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@ typedef uint64_t TCGRegSet;
 #define TCG_TARGET_HAS_not_vec          0
 #define TCG_TARGET_HAS_andc_vec         0
 #define TCG_TARGET_HAS_orc_vec          0
+#define TCG_TARGET_HAS_roti_vec         0
 #define TCG_TARGET_HAS_shi_vec          0
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          0
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 #define TCG_TARGET_HAS_not_vec          1
 #define TCG_TARGET_HAS_neg_vec          1
 #define TCG_TARGET_HAS_abs_vec          1
+#define TCG_TARGET_HAS_roti_vec         0
 #define TCG_TARGET_HAS_shi_vec          1
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          1
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
 #define TCG_TARGET_HAS_not_vec          0
 #define TCG_TARGET_HAS_neg_vec          0
 #define TCG_TARGET_HAS_abs_vec          1
+#define TCG_TARGET_HAS_roti_vec         0
 #define TCG_TARGET_HAS_shi_vec          1
 #define TCG_TARGET_HAS_shs_vec          1
 #define TCG_TARGET_HAS_shv_vec          have_avx2
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;
 #define TCG_TARGET_HAS_not_vec          1
 #define TCG_TARGET_HAS_neg_vec          have_isa_3_00
 #define TCG_TARGET_HAS_abs_vec          0
+#define TCG_TARGET_HAS_roti_vec         0
 #define TCG_TARGET_HAS_shi_vec          0
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          1
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sar64i)(void *d, void *a, uint32_t desc)
     clear_high(d, oprsz, desc);
 }
 
+void HELPER(gvec_rotl8i)(void *d, void *a, uint32_t desc)
+{
+    intptr_t oprsz = simd_oprsz(desc);
+    int shift = simd_data(desc);
+    intptr_t i;
+
+    for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+        *(uint8_t *)(d + i) = rol8(*(uint8_t *)(a + i), shift);
+    }
+    clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_rotl16i)(void *d, void *a, uint32_t desc)
+{
+    intptr_t oprsz = simd_oprsz(desc);
+    int shift = simd_data(desc);
+    intptr_t i;
+
+    for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+        *(uint16_t *)(d + i) = rol16(*(uint16_t *)(a + i), shift);
+    }
+    clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_rotl32i)(void *d, void *a, uint32_t desc)
+{
+    intptr_t oprsz = simd_oprsz(desc);
+    int shift = simd_data(desc);
+    intptr_t i;
+
+    for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+        *(uint32_t *)(d + i) = rol32(*(uint32_t *)(a + i), shift);
+    }
+    clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_rotl64i)(void *d, void *a, uint32_t desc)
+{
+    intptr_t oprsz = simd_oprsz(desc);
+    int shift = simd_data(desc);
+    intptr_t i;
+
+    for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+        *(uint64_t *)(d + i) = rol64(*(uint64_t *)(a + i), shift);
+    }
+    clear_high(d, oprsz, desc);
+}
+
 void HELPER(gvec_shl8v)(void *d, void *a, void *b, uint32_t desc)
 {
     intptr_t oprsz = simd_oprsz(desc);
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
     }
 }
 
+void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
+{
+    uint64_t mask = dup_const(MO_8, 0xff << c);
+
+    tcg_gen_shli_i64(d, a, c);
+    tcg_gen_shri_i64(a, a, 8 - c);
+    tcg_gen_andi_i64(d, d, mask);
+    tcg_gen_andi_i64(a, a, ~mask);
+    tcg_gen_or_i64(d, d, a);
+}
+
+void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
+{
+    uint64_t mask = dup_const(MO_16, 0xffff << c);
+
+    tcg_gen_shli_i64(d, a, c);
+    tcg_gen_shri_i64(a, a, 16 - c);
+    tcg_gen_andi_i64(d, d, mask);
+    tcg_gen_andi_i64(a, a, ~mask);
+    tcg_gen_or_i64(d, d, a);
+}
+
+void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs,
+                        int64_t shift, uint32_t oprsz, uint32_t maxsz)
+{
+    static const TCGOpcode vecop_list[] = { INDEX_op_rotli_vec, 0 };
+    static const GVecGen2i g[4] = {
+        { .fni8 = tcg_gen_vec_rotl8i_i64,
+          .fniv = tcg_gen_rotli_vec,
+          .fno = gen_helper_gvec_rotl8i,
+          .opt_opc = vecop_list,
+          .vece = MO_8 },
+        { .fni8 = tcg_gen_vec_rotl16i_i64,
+          .fniv = tcg_gen_rotli_vec,
+          .fno = gen_helper_gvec_rotl16i,
+          .opt_opc = vecop_list,
+          .vece = MO_16 },
+        { .fni4 = tcg_gen_rotli_i32,
+          .fniv = tcg_gen_rotli_vec,
+          .fno = gen_helper_gvec_rotl32i,
+          .opt_opc = vecop_list,
+          .vece = MO_32 },
+        { .fni8 = tcg_gen_rotli_i64,
+          .fniv = tcg_gen_rotli_vec,
+          .fno = gen_helper_gvec_rotl64i,
+          .opt_opc = vecop_list,
+          .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+          .vece = MO_64 },
+    };
+
+    tcg_debug_assert(vece <= MO_64);
+    tcg_debug_assert(shift >= 0 && shift < (8 << vece));
+    if (shift == 0) {
+        tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
+    } else {
+        tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]);
+    }
+}
+
+void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs,
+                        int64_t shift, uint32_t oprsz, uint32_t maxsz)
+{
+    tcg_debug_assert(vece <= MO_64);
+    tcg_debug_assert(shift >= 0 && shift < (8 << vece));
+    tcg_gen_gvec_rotli(vece, dofs, aofs, -shift & ((8 << vece) - 1),
+                       oprsz, maxsz);
+}
+
 /*
  * Specialized generation vector shifts by a non-constant scalar.
  */
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -XXX,XX +XXX,XX @@ void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
     do_shifti(INDEX_op_sari_vec, vece, r, a, i);
 }
 
+void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
+{
+    do_shifti(INDEX_op_rotli_vec, vece, r, a, i);
+}
+
+void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
+{
+    int bits = 8 << vece;
+    tcg_debug_assert(i >= 0 && i < bits);
+    do_shifti(INDEX_op_rotli_vec, vece, r, a, -i & (bits - 1));
+}
+
 void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
                      TCGv_vec r, TCGv_vec a, TCGv_vec b)
 {
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op)
     case INDEX_op_shrv_vec:
     case INDEX_op_sarv_vec:
         return have_vec && TCG_TARGET_HAS_shv_vec;
+    case INDEX_op_rotli_vec:
+        return have_vec && TCG_TARGET_HAS_roti_vec;
     case INDEX_op_ssadd_vec:
     case INDEX_op_usadd_vec:
     case INDEX_op_sssub_vec:
diff --git a/tcg/README b/tcg/README
index XXXXXXX..XXXXXXX 100644
--- a/tcg/README
+++ b/tcg/README
@@ -XXX,XX +XXX,XX @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
 
 * shri_vec   v0, v1, i2
 * sari_vec   v0, v1, i2
+* rotli_vec  v0, v1, i2
 * shrs_vec   v0, v1, s2
 * sars_vec   v0, v1, s2
 
-  Similarly for logical and arithmetic right shift.
+  Similarly for logical and arithmetic right shift, and left rotate.
 
 * shlv_vec   v0, v1, v2
 
-- 
2.25.1

No host backend support yet, but the interfaces for rotlv
and rotrv are in place.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v3: Drop the generic expansion from rot to shift; we can do better
    for each backend, and then this code becomes unused.
---
 accel/tcg/tcg-runtime.h      |  10 +++
 include/tcg/tcg-op-gvec.h    |   4 ++
 include/tcg/tcg-op.h         |   2 +
 include/tcg/tcg-opc.h        |   2 +
 include/tcg/tcg.h            |   1 +
 tcg/aarch64/tcg-target.h     |   1 +
 tcg/i386/tcg-target.h        |   1 +
 tcg/ppc/tcg-target.h         |   1 +
 accel/tcg/tcg-runtime-gvec.c |  96 +++++++++++++++++++++++++++
 tcg/tcg-op-gvec.c            | 122 +++++++++++++++++++++++++++++++++++
 tcg/tcg-op-vec.c             |  10 +++
 tcg/tcg.c                    |   3 +
 tcg/README                   |   4 +-
 13 files changed, 256 insertions(+), 1 deletion(-)

diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(gvec_sar16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(gvec_sar32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(gvec_sar64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 
+DEF_HELPER_FLAGS_4(gvec_rotl8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_rotl16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_rotl32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_rotl64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_rotr8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_rotr16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_rotr32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_rotr64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
 DEF_HELPER_FLAGS_4(gvec_eq8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(gvec_eq16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(gvec_eq32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg-op-gvec.h
+++ b/include/tcg/tcg-op-gvec.h
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs,
                        uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
 void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs,
                        uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, uint32_t aofs,
+                        uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs,
+                        uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
 
 void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
                       uint32_t aofs, uint32_t bofs,
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -XXX,XX +XXX,XX @@ void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
 void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
 void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
 void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
+void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
+void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
 
 void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
                      TCGv_vec a, TCGv_vec b);
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -XXX,XX +XXX,XX @@ DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
 DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
 DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
 DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
+DEF(rotlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec))
+DEF(rotrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec))
 
 DEF(cmp_vec, 1, 2, 1, IMPLVEC)
 
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@ typedef uint64_t TCGRegSet;
 #define TCG_TARGET_HAS_andc_vec         0
 #define TCG_TARGET_HAS_orc_vec          0
 #define TCG_TARGET_HAS_roti_vec         0
+#define TCG_TARGET_HAS_rotv_vec         0
 #define TCG_TARGET_HAS_shi_vec          0
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          0
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 #define TCG_TARGET_HAS_neg_vec          1
 #define TCG_TARGET_HAS_abs_vec          1
 #define TCG_TARGET_HAS_roti_vec         0
+#define TCG_TARGET_HAS_rotv_vec         0
 #define TCG_TARGET_HAS_shi_vec          1
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          1
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
 #define TCG_TARGET_HAS_neg_vec          0
 #define TCG_TARGET_HAS_abs_vec          1
 #define TCG_TARGET_HAS_roti_vec         0
+#define TCG_TARGET_HAS_rotv_vec         0
 #define TCG_TARGET_HAS_shi_vec          1
 #define TCG_TARGET_HAS_shs_vec          1
 #define TCG_TARGET_HAS_shv_vec          have_avx2
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;
 #define TCG_TARGET_HAS_neg_vec          have_isa_3_00
 #define TCG_TARGET_HAS_abs_vec          0
 #define TCG_TARGET_HAS_roti_vec         0
+#define TCG_TARGET_HAS_rotv_vec         0
 #define TCG_TARGET_HAS_shi_vec          0
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          1
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sar64v)(void *d, void *a, void *b, uint32_t desc)
     clear_high(d, oprsz, desc);
 }
 
+void HELPER(gvec_rotl8v)(void *d, void *a, void *b, uint32_t desc)
+{
+    intptr_t oprsz = simd_oprsz(desc);
+    intptr_t i;
+
+    for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+        uint8_t sh = *(uint8_t *)(b + i) & 7;
+        *(uint8_t *)(d + i) = rol8(*(uint8_t *)(a + i), sh);
+    }
+    clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_rotl16v)(void *d, void *a, void *b, uint32_t desc)
+{
+    intptr_t oprsz = simd_oprsz(desc);
+    intptr_t i;
+
+    for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+        uint8_t sh = *(uint16_t *)(b + i) & 15;
+        *(uint16_t *)(d + i) = rol16(*(uint16_t *)(a + i), sh);
+    }
+    clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_rotl32v)(void *d, void *a, void *b, uint32_t desc)
+{
+    intptr_t oprsz = simd_oprsz(desc);
+    intptr_t i;
+
+    for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+        uint8_t sh = *(uint32_t *)(b + i) & 31;
+        *(uint32_t *)(d + i) = rol32(*(uint32_t *)(a + i), sh);
+    }
+    clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_rotl64v)(void *d, void *a, void *b, uint32_t desc)
+{
+    intptr_t oprsz = simd_oprsz(desc);
+    intptr_t i;
+
+    for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+        uint8_t sh = *(uint64_t *)(b + i) & 63;
+        *(uint64_t *)(d + i) = rol64(*(uint64_t *)(a + i), sh);
+    }
+    clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_rotr8v)(void *d, void *a, void *b, uint32_t desc)
+{
+    intptr_t oprsz = simd_oprsz(desc);
+    intptr_t i;
+
+    for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+        uint8_t sh = *(uint8_t *)(b + i) & 7;
+        *(uint8_t *)(d + i) = ror8(*(uint8_t *)(a + i), sh);
+    }
+    clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_rotr16v)(void *d, void *a, void *b, uint32_t desc)
+{
+    intptr_t oprsz = simd_oprsz(desc);
+    intptr_t i;
+
+    for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+        uint8_t sh = *(uint16_t *)(b + i) & 15;
+        *(uint16_t *)(d + i) = ror16(*(uint16_t *)(a + i), sh);
+    }
+    clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_rotr32v)(void *d, void *a, void *b, uint32_t desc)
+{
+    intptr_t oprsz = simd_oprsz(desc);
+    intptr_t i;
+
+    for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+        uint8_t sh = *(uint32_t *)(b + i) & 31;
+        *(uint32_t *)(d + i) = ror32(*(uint32_t *)(a + i), sh);
+    }
+    clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_rotr64v)(void *d, void *a, void *b, uint32_t desc)
+{
+    intptr_t oprsz = simd_oprsz(desc);
+    intptr_t i;
+
+    for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+        uint8_t sh = *(uint64_t *)(b + i) & 63;
+        *(uint64_t *)(d + i) = ror64(*(uint64_t *)(a + i), sh);
+    }
+    clear_high(d, oprsz, desc);
+}
+
 #define DO_CMP1(NAME, TYPE, OP)                                            \
 void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc)                \
 {                                                                          \
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs,
     tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
 }
 
+/*
+ * Similarly for rotates.
+ */
+
+static void tcg_gen_rotlv_mod_vec(unsigned vece, TCGv_vec d,
+                                  TCGv_vec a, TCGv_vec b)
+{
+    TCGv_vec t = tcg_temp_new_vec_matching(d);
+
+    tcg_gen_dupi_vec(vece, t, (8 << vece) - 1);
+    tcg_gen_and_vec(vece, t, t, b);
+    tcg_gen_rotlv_vec(vece, d, a, t);
+    tcg_temp_free_vec(t);
+}
+
+static void tcg_gen_rotl_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+    TCGv_i32 t = tcg_temp_new_i32();
+
+    tcg_gen_andi_i32(t, b, 31);
+    tcg_gen_rotl_i32(d, a, t);
+    tcg_temp_free_i32(t);
+}
+
+static void tcg_gen_rotl_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+    TCGv_i64 t = tcg_temp_new_i64();
+
+    tcg_gen_andi_i64(t, b, 63);
+    tcg_gen_rotl_i64(d, a, t);
+    tcg_temp_free_i64(t);
+}
+
+void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, uint32_t aofs,
+                        uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+    static const TCGOpcode vecop_list[] = { INDEX_op_rotlv_vec, 0 };
+    static const GVecGen3 g[4] = {
+        { .fniv = tcg_gen_rotlv_mod_vec,
+          .fno = gen_helper_gvec_rotl8v,
+          .opt_opc = vecop_list,
+          .vece = MO_8 },
+        { .fniv = tcg_gen_rotlv_mod_vec,
+          .fno = gen_helper_gvec_rotl16v,
+          .opt_opc = vecop_list,
+          .vece = MO_16 },
+        { .fni4 = tcg_gen_rotl_mod_i32,
+          .fniv = tcg_gen_rotlv_mod_vec,
+          .fno = gen_helper_gvec_rotl32v,
+          .opt_opc = vecop_list,
+          .vece = MO_32 },
+        { .fni8 = tcg_gen_rotl_mod_i64,
+          .fniv = tcg_gen_rotlv_mod_vec,
+          .fno = gen_helper_gvec_rotl64v,
+          .opt_opc = vecop_list,
+          .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+          .vece = MO_64 },
+    };
+
+    tcg_debug_assert(vece <= MO_64);
+    tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
+}
+
+static void tcg_gen_rotrv_mod_vec(unsigned vece, TCGv_vec d,
+                                  TCGv_vec a, TCGv_vec b)
+{
+    TCGv_vec t = tcg_temp_new_vec_matching(d);
+
+    tcg_gen_dupi_vec(vece, t, (8 << vece) - 1);
+    tcg_gen_and_vec(vece, t, t, b);
+    tcg_gen_rotrv_vec(vece, d, a, t);
+    tcg_temp_free_vec(t);
+}
+
+static void tcg_gen_rotr_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+    TCGv_i32 t = tcg_temp_new_i32();
+
+    tcg_gen_andi_i32(t, b, 31);
+    tcg_gen_rotr_i32(d, a, t);
+    tcg_temp_free_i32(t);
+}
+
+static void tcg_gen_rotr_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+    TCGv_i64 t = tcg_temp_new_i64();
+
+    tcg_gen_andi_i64(t, b, 63);
+    tcg_gen_rotr_i64(d, a, t);
+    tcg_temp_free_i64(t);
+}
+
+void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs,
+                        uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+    static const TCGOpcode vecop_list[] = { INDEX_op_rotrv_vec, 0 };
+    static const GVecGen3 g[4] = {
+        { .fniv = tcg_gen_rotrv_mod_vec,
+          .fno = gen_helper_gvec_rotr8v,
+          .opt_opc = vecop_list,
+          .vece = MO_8 },
+        { .fniv = tcg_gen_rotrv_mod_vec,
+          .fno = gen_helper_gvec_rotr16v,
+          .opt_opc = vecop_list,
+          .vece = MO_16 },
+        { .fni4 = tcg_gen_rotr_mod_i32,
+          .fniv = tcg_gen_rotrv_mod_vec,
+          .fno = gen_helper_gvec_rotr32v,
+          .opt_opc = vecop_list,
+          .vece = MO_32 },
+        { .fni8 = tcg_gen_rotr_mod_i64,
+          .fniv = tcg_gen_rotrv_mod_vec,
+          .fno = gen_helper_gvec_rotr64v,
+          .opt_opc = vecop_list,
+          .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+          .vece = MO_64 },
+    };
+
+    tcg_debug_assert(vece <= MO_64);
+    tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
+}
+
 /* Expand OPSZ bytes worth of three-operand operations using i32 elements.  */
 static void expand_cmp_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
                            uint32_t oprsz, TCGCond cond)
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -XXX,XX +XXX,XX @@ void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
     do_op3_nofail(vece, r, a, b, INDEX_op_sarv_vec);
 }
 
+void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+    do_op3_nofail(vece, r, a, b, INDEX_op_rotlv_vec);
+}
+
+void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+    do_op3_nofail(vece, r, a, b, INDEX_op_rotrv_vec);
+}
+
 static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a,
                       TCGv_i32 s, TCGOpcode opc_s, TCGOpcode opc_v)
 {
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op)
         return have_vec && TCG_TARGET_HAS_shv_vec;
     case INDEX_op_rotli_vec:
         return have_vec && TCG_TARGET_HAS_roti_vec;
+    case INDEX_op_rotlv_vec:
+    case INDEX_op_rotrv_vec:
+        return have_vec && TCG_TARGET_HAS_rotv_vec;
     case INDEX_op_ssadd_vec:
     case INDEX_op_usadd_vec:
     case INDEX_op_sssub_vec:
diff --git a/tcg/README b/tcg/README
index XXXXXXX..XXXXXXX 100644
--- a/tcg/README
+++ b/tcg/README
@@ -XXX,XX +XXX,XX @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
 
 * shrv_vec   v0, v1, v2
 * sarv_vec   v0, v1, v2
+* rotlv_vec  v0, v1, v2
+* rotrv_vec  v0, v1, v2
 
-  Similarly for logical and arithmetic right shift.
+  Similarly for logical and arithmetic right shift, and rotates.
 
 * cmp_vec  v0, v1, v2, cond
 
-- 
2.25.1

We do not reflect this expansion in tcg_can_emit_vecop_list,
so it is unused and unusable.  However, we actually perform
the same expansion in do_gvec_shifts, so it is also unneeded.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tcg-op-vec.c | 35 +++++++++++------------------------
 1 file changed, 11 insertions(+), 24 deletions(-)

diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -XXX,XX +XXX,XX @@ void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
 }
 
 static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a,
-                      TCGv_i32 s, TCGOpcode opc_s, TCGOpcode opc_v)
+                      TCGv_i32 s, TCGOpcode opc)
 {
     TCGTemp *rt = tcgv_vec_temp(r);
     TCGTemp *at = tcgv_vec_temp(a);
@@ -XXX,XX +XXX,XX @@ static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a,
     TCGArg ai = temp_arg(at);
     TCGArg si = temp_arg(st);
     TCGType type = rt->base_type;
-    const TCGOpcode *hold_list;
     int can;
 
     tcg_debug_assert(at->base_type >= type);
-    tcg_assert_listed_vecop(opc_s);
-    hold_list = tcg_swap_vecop_list(NULL);
-
-    can = tcg_can_emit_vec_op(opc_s, type, vece);
+    tcg_assert_listed_vecop(opc);
+    can = tcg_can_emit_vec_op(opc, type, vece);
     if (can > 0) {
-        vec_gen_3(opc_s, type, vece, ri, ai, si);
+        vec_gen_3(opc, type, vece, ri, ai, si);
     } else if (can < 0) {
-        tcg_expand_vec_op(opc_s, type, vece, ri, ai, si);
+        const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
+        tcg_expand_vec_op(opc, type, vece, ri, ai, si);
+        tcg_swap_vecop_list(hold_list);
     } else {
-        TCGv_vec vec_s = tcg_temp_new_vec(type);
-
-        if (vece == MO_64) {
-            TCGv_i64 s64 = tcg_temp_new_i64();
-            tcg_gen_extu_i32_i64(s64, s);
-            tcg_gen_dup_i64_vec(MO_64, vec_s, s64);
-            tcg_temp_free_i64(s64);
-        } else {
-            tcg_gen_dup_i32_vec(vece, vec_s, s);
-        }
-        do_op3_nofail(vece, r, a, vec_s, opc_v);
-        tcg_temp_free_vec(vec_s);
+        g_assert_not_reached();
     }
-    tcg_swap_vecop_list(hold_list);
 }
 
 void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b)
 {
-    do_shifts(vece, r, a, b, INDEX_op_shls_vec, INDEX_op_shlv_vec);
+    do_shifts(vece, r, a, b, INDEX_op_shls_vec);
 }
 
 void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b)
 {
-    do_shifts(vece, r, a, b, INDEX_op_shrs_vec, INDEX_op_shrv_vec);
+    do_shifts(vece, r, a, b, INDEX_op_shrs_vec);
 }
 
 void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b)
 {
-    do_shifts(vece, r, a, b, INDEX_op_sars_vec, INDEX_op_sarv_vec);
+    do_shifts(vece, r, a, b, INDEX_op_sars_vec);
 }
 
 void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a,
-- 
2.25.1

No host backend support yet, but the interfaces for rotls
are in place.  Only implement left-rotate for now, as the
only known use of vector rotate by scalar is s390x, so any
right-rotate would be unused and untestable.

diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg-op-gvec.h
+++ b/include/tcg/tcg-op-gvec.h
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs,
                        TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
 void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs,
                        TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs,
+                        TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
 
 /*
  * Perform vector shift by vector element, modulo the element size.
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -XXX,XX +XXX,XX @@ void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
 void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
 void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
 void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
+void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
 
 void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
 void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -XXX,XX +XXX,XX @@ DEF(rotli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_roti_vec))
 DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
 DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
 DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
+DEF(rotls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rots_vec))
 
 DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
 DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@ typedef uint64_t TCGRegSet;
 #define TCG_TARGET_HAS_andc_vec         0
 #define TCG_TARGET_HAS_orc_vec          0
 #define TCG_TARGET_HAS_roti_vec         0
+#define TCG_TARGET_HAS_rots_vec         0
 #define TCG_TARGET_HAS_rotv_vec         0
 #define TCG_TARGET_HAS_shi_vec          0
 #define TCG_TARGET_HAS_shs_vec          0
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 #define TCG_TARGET_HAS_neg_vec          1
 #define TCG_TARGET_HAS_abs_vec          1
 #define TCG_TARGET_HAS_roti_vec         0
+#define TCG_TARGET_HAS_rots_vec         0
 #define TCG_TARGET_HAS_rotv_vec         0
 #define TCG_TARGET_HAS_shi_vec          1
 #define TCG_TARGET_HAS_shs_vec          0
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
 #define TCG_TARGET_HAS_neg_vec          0
 #define TCG_TARGET_HAS_abs_vec          1
 #define TCG_TARGET_HAS_roti_vec         0
+#define TCG_TARGET_HAS_rots_vec         0
 #define TCG_TARGET_HAS_rotv_vec         0
 #define TCG_TARGET_HAS_shi_vec          1
 #define TCG_TARGET_HAS_shs_vec          1
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;
 #define TCG_TARGET_HAS_neg_vec          have_isa_3_00
 #define TCG_TARGET_HAS_abs_vec          0
 #define TCG_TARGET_HAS_roti_vec         0
+#define TCG_TARGET_HAS_rots_vec         0
 #define TCG_TARGET_HAS_rotv_vec         0
 #define TCG_TARGET_HAS_shi_vec          0
 #define TCG_TARGET_HAS_shs_vec          0
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs,
     do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g);
 }
 
+void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs,
+                        TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz)
+{
+    static const GVecGen2sh g = {
+        .fni4 = tcg_gen_rotl_i32,
+        .fni8 = tcg_gen_rotl_i64,
+        .fniv_s = tcg_gen_rotls_vec,
+        .fniv_v = tcg_gen_rotlv_vec,
+        .fno = {
+            gen_helper_gvec_rotl8i,
+            gen_helper_gvec_rotl16i,
+            gen_helper_gvec_rotl32i,
+            gen_helper_gvec_rotl64i,
+        },
+        .s_list = { INDEX_op_rotls_vec, 0 },
+        .v_list = { INDEX_op_rotlv_vec, 0 },
+    };
+
+    tcg_debug_assert(vece <= MO_64);
+    do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g);
+}
+
 /*
  * Expand D = A << (B % element bits)
  *
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -XXX,XX +XXX,XX @@ void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b)
     do_shifts(vece, r, a, b, INDEX_op_sars_vec);
 }
 
+void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s)
+{
+    do_shifts(vece, r, a, s, INDEX_op_rotls_vec);
+}
+
 void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a,
                         TCGv_vec b, TCGv_vec c)
 {
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op)
         return have_vec && TCG_TARGET_HAS_shv_vec;
     case INDEX_op_rotli_vec:
         return have_vec && TCG_TARGET_HAS_roti_vec;
+    case INDEX_op_rotls_vec:
+        return have_vec && TCG_TARGET_HAS_rots_vec;
     case INDEX_op_rotlv_vec:
     case INDEX_op_rotrv_vec:
         return have_vec && TCG_TARGET_HAS_rotv_vec;
-- 
2.25.1

For immediates, we must continue the special casing of 8-bit
elements.  The other element sizes and shift types are trivially
implemented with shifts.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.inc.c | 116 ++++++++++++++++++++++++++++++++------
 1 file changed, 100 insertions(+), 16 deletions(-)

diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_shls_vec:
     case INDEX_op_shrs_vec:
     case INDEX_op_sars_vec:
+    case INDEX_op_rotls_vec:
     case INDEX_op_cmp_vec:
     case INDEX_op_x86_shufps_vec:
     case INDEX_op_x86_blend_vec:
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_xor_vec:
     case INDEX_op_andc_vec:
         return 1;
+    case INDEX_op_rotli_vec:
     case INDEX_op_cmp_vec:
     case INDEX_op_cmpsel_vec:
         return -1;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
         return vece >= MO_16;
     case INDEX_op_sars_vec:
         return vece >= MO_16 && vece <= MO_32;
+    case INDEX_op_rotls_vec:
+        return vece >= MO_16 ? -1 : 0;
 
     case INDEX_op_shlv_vec:
     case INDEX_op_shrv_vec:
         return have_avx2 && vece >= MO_32;
     case INDEX_op_sarv_vec:
         return have_avx2 && vece == MO_32;
+    case INDEX_op_rotlv_vec:
+    case INDEX_op_rotrv_vec:
+        return have_avx2 && vece >= MO_32 ? -1 : 0;
 
     case INDEX_op_mul_vec:
         if (vece == MO_8) {
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     }
 }
 
-static void expand_vec_shi(TCGType type, unsigned vece, bool shr,
+static void expand_vec_shi(TCGType type, unsigned vece, TCGOpcode opc,
                            TCGv_vec v0, TCGv_vec v1, TCGArg imm)
 {
     TCGv_vec t1, t2;
@@ -XXX,XX +XXX,XX @@ static void expand_vec_shi(TCGType type, unsigned vece, bool shr,
     t1 = tcg_temp_new_vec(type);
     t2 = tcg_temp_new_vec(type);
 
-    /* Unpack to W, shift, and repack.  Tricky bits:
-       (1) Use punpck*bw x,x to produce DDCCBBAA,
-           i.e. duplicate in other half of the 16-bit lane.
-       (2) For right-shift, add 8 so that the high half of
-           the lane becomes zero.  For left-shift, we must
-           shift up and down again.
-       (3) Step 2 leaves high half zero such that PACKUSWB
-           (pack with unsigned saturation) does not modify
-           the quantity.  */
+    /*
+     * Unpack to W, shift, and repack.  Tricky bits:
+     * (1) Use punpck*bw x,x to produce DDCCBBAA,
+     *     i.e. duplicate in other half of the 16-bit lane.
+     * (2) For right-shift, add 8 so that the high half of the lane
+     *     becomes zero.  For left-shift, and left-rotate, we must
+     *     shift up and down again.
+     * (3) Step 2 leaves high half zero such that PACKUSWB
+     *     (pack with unsigned saturation) does not modify
+     *     the quantity.
+     */
     vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
               tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
     vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
               tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
 
-    if (shr) {
-        tcg_gen_shri_vec(MO_16, t1, t1, imm + 8);
-        tcg_gen_shri_vec(MO_16, t2, t2, imm + 8);
+    if (opc != INDEX_op_rotli_vec) {
+        imm += 8;
+    }
+    if (opc == INDEX_op_shri_vec) {
+        tcg_gen_shri_vec(MO_16, t1, t1, imm);
+        tcg_gen_shri_vec(MO_16, t2, t2, imm);
     } else {
-        tcg_gen_shli_vec(MO_16, t1, t1, imm + 8);
-        tcg_gen_shli_vec(MO_16, t2, t2, imm + 8);
+        tcg_gen_shli_vec(MO_16, t1, t1, imm);
+        tcg_gen_shli_vec(MO_16, t2, t2, imm);
         tcg_gen_shri_vec(MO_16, t1, t1, 8);
         tcg_gen_shri_vec(MO_16, t2, t2, 8);
     }
@@ -XXX,XX +XXX,XX @@ static void expand_vec_sari(TCGType type, unsigned vece,
     }
 }
 
+static void expand_vec_rotli(TCGType type, unsigned vece,
+                             TCGv_vec v0, TCGv_vec v1, TCGArg imm)
+{
+    TCGv_vec t;
+
+    if (vece == MO_8) {
+        expand_vec_shi(type, vece, INDEX_op_rotli_vec, v0, v1, imm);
+        return;
+    }
+
+    t = tcg_temp_new_vec(type);
+    tcg_gen_shli_vec(vece, t, v1, imm);
+    tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm);
+    tcg_gen_or_vec(vece, v0, v0, t);
+    tcg_temp_free_vec(t);
+}
+
+static void expand_vec_rotls(TCGType type, unsigned vece,
+                             TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh)
+{
+    TCGv_i32 rsh;
+    TCGv_vec t;
+
+    tcg_debug_assert(vece != MO_8);
+
+    t = tcg_temp_new_vec(type);
+    rsh = tcg_temp_new_i32();
+
+    tcg_gen_neg_i32(rsh, lsh);
+    tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1);
+    tcg_gen_shls_vec(vece, t, v1, lsh);
+    tcg_gen_shrs_vec(vece, v0, v1, rsh);
+    tcg_gen_or_vec(vece, v0, v0, t);
+    tcg_temp_free_vec(t);
+    tcg_temp_free_i32(rsh);
+}
+
+static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0,
+                            TCGv_vec v1, TCGv_vec sh, bool right)
+{
+    TCGv_vec t = tcg_temp_new_vec(type);
+
+    tcg_gen_dupi_vec(vece, t, 8 << vece);
+    tcg_gen_sub_vec(vece, t, t, sh);
+    if (right) {
+        tcg_gen_shlv_vec(vece, t, v1, t);
+        tcg_gen_shrv_vec(vece, v0, v1, sh);
+    } else {
+        tcg_gen_shrv_vec(vece, t, v1, t);
+        tcg_gen_shlv_vec(vece, v0, v1, sh);
+    }
+    tcg_gen_or_vec(vece, v0, v0, t);
+    tcg_temp_free_vec(t);
+}
+
 static void expand_vec_mul(TCGType type, unsigned vece,
                            TCGv_vec v0, TCGv_vec v1, TCGv_vec v2)
 {
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
     switch (opc) {
     case INDEX_op_shli_vec:
     case INDEX_op_shri_vec:
-        expand_vec_shi(type, vece, opc == INDEX_op_shri_vec, v0, v1, a2);
+        expand_vec_shi(type, vece, opc, v0, v1, a2);
         break;
 
     case INDEX_op_sari_vec:
         expand_vec_sari(type, vece, v0, v1, a2);
         break;
 
+    case INDEX_op_rotli_vec:
+        expand_vec_rotli(type, vece, v0, v1, a2);
+        break;
+
+    case INDEX_op_rotls_vec:
+        expand_vec_rotls(type, vece, v0, v1, temp_tcgv_i32(arg_temp(a2)));
+        break;
+
+    case INDEX_op_rotlv_vec:
+        v2 = temp_tcgv_vec(arg_temp(a2));
+        expand_vec_rotv(type, vece, v0, v1, v2, false);
+        break;
+    case INDEX_op_rotrv_vec:
+        v2 = temp_tcgv_vec(arg_temp(a2));
+        expand_vec_rotv(type, vece, v0, v1, v2, true);
+        break;
+
     case INDEX_op_mul_vec:
         v2 = temp_tcgv_vec(arg_temp(a2));
         expand_vec_mul(type, vece, v0, v1, v2);
-- 
2.25.1

For immediate rotate , we can implement this in two instructions,
using SLI.  For variable rotate, the oddness of aarch64 right-shift-
as-negative-left-shift means a backend-specific expansion works best.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/aarch64/tcg-target.opc.h |  1 +
 tcg/aarch64/tcg-target.inc.c | 53 ++++++++++++++++++++++++++++++++++--
 2 files changed, 52 insertions(+), 2 deletions(-)

diff --git a/tcg/aarch64/tcg-target.opc.h b/tcg/aarch64/tcg-target.opc.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.opc.h
+++ b/tcg/aarch64/tcg-target.opc.h
@@ -XXX,XX +XXX,XX @@
  */
 
 DEF(aa64_sshl_vec, 1, 2, 0, IMPLVEC)
+DEF(aa64_sli_vec, 1, 2, 1, IMPLVEC)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -XXX,XX +XXX,XX @@ typedef enum {
     I3614_SSHR      = 0x0f000400,
     I3614_SSRA      = 0x0f001400,
     I3614_SHL       = 0x0f005400,
+    I3614_SLI       = 0x2f005400,
     I3614_USHR      = 0x2f000400,
     I3614_USRA      = 0x2f001400,
 
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_sari_vec:
         tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2);
         break;
+    case INDEX_op_aa64_sli_vec:
+        tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece));
+        break;
     case INDEX_op_shlv_vec:
         tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2);
         break;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_shlv_vec:
     case INDEX_op_bitsel_vec:
         return 1;
+    case INDEX_op_rotli_vec:
     case INDEX_op_shrv_vec:
     case INDEX_op_sarv_vec:
+    case INDEX_op_rotlv_vec:
+    case INDEX_op_rotrv_vec:
         return -1;
     case INDEX_op_mul_vec:
     case INDEX_op_smax_vec:
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
                        TCGArg a0, ...)
 {
     va_list va;
-    TCGv_vec v0, v1, v2, t1;
+    TCGv_vec v0, v1, v2, t1, t2;
+    TCGArg a2;
 
     va_start(va, a0);
     v0 = temp_tcgv_vec(arg_temp(a0));
     v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
-    v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+    a2 = va_arg(va, TCGArg);
+    v2 = temp_tcgv_vec(arg_temp(a2));
 
     switch (opc) {
+    case INDEX_op_rotli_vec:
+        t1 = tcg_temp_new_vec(type);
+        tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1));
+        vec_gen_4(INDEX_op_aa64_sli_vec, type, vece,
+                  tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2);
+        tcg_temp_free_vec(t1);
+        break;
+
     case INDEX_op_shrv_vec:
     case INDEX_op_sarv_vec:
         /* Right shifts are negative left shifts for AArch64.  */
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
         tcg_temp_free_vec(t1);
         break;
 
+    case INDEX_op_rotlv_vec:
+        t1 = tcg_temp_new_vec(type);
+        tcg_gen_dupi_vec(vece, t1, 8 << vece);
+        tcg_gen_sub_vec(vece, t1, v2, t1);
+        /* Right shifts are negative left shifts for AArch64.  */
+        vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+        vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(v0),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+        tcg_gen_or_vec(vece, v0, v0, t1);
+        tcg_temp_free_vec(t1);
+        break;
+
+    case INDEX_op_rotrv_vec:
+        t1 = tcg_temp_new_vec(type);
+        t2 = tcg_temp_new_vec(type);
+        tcg_gen_neg_vec(vece, t1, v2);
+        tcg_gen_dupi_vec(vece, t2, 8 << vece);
+        tcg_gen_add_vec(vece, t2, t1, t2);
+        /* Right shifts are negative left shifts for AArch64.  */
+        vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+        vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t2),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(t2));
+        tcg_gen_or_vec(vece, v0, t1, t2);
+        tcg_temp_free_vec(t1);
+        tcg_temp_free_vec(t2);
+        break;
+
     default:
         g_assert_not_reached();
     }
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } };
     static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
     static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } };
+    static const TCGTargetOpDef w_0_w = { .args_ct_str = { "w", "0", "w" } };
     static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } };
     static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } };
     static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } };
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
         return &w_w_wZ;
     case INDEX_op_bitsel_vec:
         return &w_w_w_w;
+    case INDEX_op_aa64_sli_vec:
+        return &w_0_w;
 
     default:
         return NULL;
-- 
2.25.1

We already had support for rotlv, using a target-specific opcode;
convert to use the generic opcode.  Handle rotrv via simple negation.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/ppc/tcg-target.h     |  2 +-
 tcg/ppc/tcg-target.opc.h |  1 -
 tcg/ppc/tcg-target.inc.c | 23 +++++++++++++++++++----
 3 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;
 #define TCG_TARGET_HAS_abs_vec          0
 #define TCG_TARGET_HAS_roti_vec         0
 #define TCG_TARGET_HAS_rots_vec         0
-#define TCG_TARGET_HAS_rotv_vec         0
+#define TCG_TARGET_HAS_rotv_vec         1
 #define TCG_TARGET_HAS_shi_vec          0
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          1
diff --git a/tcg/ppc/tcg-target.opc.h b/tcg/ppc/tcg-target.opc.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.opc.h
+++ b/tcg/ppc/tcg-target.opc.h
@@ -XXX,XX +XXX,XX @@ DEF(ppc_msum_vec, 1, 3, 0, IMPLVEC)
 DEF(ppc_muleu_vec, 1, 2, 0, IMPLVEC)
 DEF(ppc_mulou_vec, 1, 2, 0, IMPLVEC)
 DEF(ppc_pkum_vec, 1, 2, 0, IMPLVEC)
-DEF(ppc_rotl_vec, 1, 2, 0, IMPLVEC)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_shlv_vec:
     case INDEX_op_shrv_vec:
     case INDEX_op_sarv_vec:
+    case INDEX_op_rotlv_vec:
         return vece <= MO_32 || have_isa_2_07;
     case INDEX_op_ssadd_vec:
     case INDEX_op_sssub_vec:
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_shli_vec:
     case INDEX_op_shri_vec:
     case INDEX_op_sari_vec:
+    case INDEX_op_rotli_vec:
         return vece <= MO_32 || have_isa_2_07 ? -1 : 0;
     case INDEX_op_neg_vec:
         return vece >= MO_32 && have_isa_3_00;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
         return 0;
     case INDEX_op_bitsel_vec:
         return have_vsx;
+    case INDEX_op_rotrv_vec:
+        return -1;
     default:
         return 0;
     }
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_ppc_pkum_vec:
         insn = pkum_op[vece];
         break;
-    case INDEX_op_ppc_rotl_vec:
+    case INDEX_op_rotlv_vec:
         insn = rotl_op[vece];
         break;
     case INDEX_op_ppc_msum_vec:
@@ -XXX,XX +XXX,XX @@ static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0,
         t3 = tcg_temp_new_vec(type);
         t4 = tcg_temp_new_vec(type);
         tcg_gen_dupi_vec(MO_8, t4, -16);
-        vec_gen_3(INDEX_op_ppc_rotl_vec, type, MO_32, tcgv_vec_arg(t1),
+        vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1),
                   tcgv_vec_arg(v2), tcgv_vec_arg(t4));
         vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2),
                   tcgv_vec_arg(v1), tcgv_vec_arg(v2));
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
                        TCGArg a0, ...)
 {
     va_list va;
-    TCGv_vec v0, v1, v2;
+    TCGv_vec v0, v1, v2, t0;
     TCGArg a2;
 
     va_start(va, a0);
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
     case INDEX_op_sari_vec:
         expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec);
         break;
+    case INDEX_op_rotli_vec:
+        expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec);
+        break;
     case INDEX_op_cmp_vec:
         v2 = temp_tcgv_vec(arg_temp(a2));
         expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
         v2 = temp_tcgv_vec(arg_temp(a2));
         expand_vec_mul(type, vece, v0, v1, v2);
         break;
+    case INDEX_op_rotlv_vec:
+        v2 = temp_tcgv_vec(arg_temp(a2));
+        t0 = tcg_temp_new_vec(type);
+        tcg_gen_neg_vec(vece, t0, v2);
+        tcg_gen_rotlv_vec(vece, v0, v1, t0);
+        tcg_temp_free_vec(t0);
+        break;
     default:
         g_assert_not_reached();
     }
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_shlv_vec:
     case INDEX_op_shrv_vec:
     case INDEX_op_sarv_vec:
+    case INDEX_op_rotlv_vec:
+    case INDEX_op_rotrv_vec:
     case INDEX_op_ppc_mrgh_vec:
     case INDEX_op_ppc_mrgl_vec:
     case INDEX_op_ppc_muleu_vec:
     case INDEX_op_ppc_mulou_vec:
     case INDEX_op_ppc_pkum_vec:
-    case INDEX_op_ppc_rotl_vec:
     case INDEX_op_dup2_vec:
         return &v_v_v;
     case INDEX_op_not_vec:
-- 
2.25.1

Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/ppc/helper.h                 |  4 ----
 target/ppc/int_helper.c             | 17 -----------------
 target/ppc/translate/vmx-impl.inc.c |  8 ++++----
 3 files changed, 4 insertions(+), 25 deletions(-)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vsubuqm, void, avr, avr, avr)
 DEF_HELPER_4(vsubecuq, void, avr, avr, avr, avr)
 DEF_HELPER_4(vsubeuqm, void, avr, avr, avr, avr)
 DEF_HELPER_3(vsubcuq, void, avr, avr, avr)
-DEF_HELPER_3(vrlb, void, avr, avr, avr)
-DEF_HELPER_3(vrlh, void, avr, avr, avr)
-DEF_HELPER_3(vrlw, void, avr, avr, avr)
-DEF_HELPER_3(vrld, void, avr, avr, avr)
 DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32)
 DEF_HELPER_3(vextractub, void, avr, avr, i32)
 DEF_HELPER_3(vextractuh, void, avr, avr, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -XXX,XX +XXX,XX @@ VRFI(p, float_round_up)
 VRFI(z, float_round_to_zero)
 #undef VRFI
 
-#define VROTATE(suffix, element, mask)                                  \
-    void helper_vrl##suffix(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)   \
-    {                                                                   \
-        int i;                                                          \
-                                                                        \
-        for (i = 0; i < ARRAY_SIZE(r->element); i++) {                  \
-            unsigned int shift = b->element[i] & mask;                  \
-            r->element[i] = (a->element[i] << shift) |                  \
-                (a->element[i] >> (sizeof(a->element[0]) * 8 - shift)); \
-        }                                                               \
-    }
-VROTATE(b, u8, 0x7)
-VROTATE(h, u16, 0xF)
-VROTATE(w, u32, 0x1F)
-VROTATE(d, u64, 0x3F)
-#undef VROTATE
-
 void helper_vrsqrtefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b)
 {
     int i;
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -XXX,XX +XXX,XX @@ GEN_VXFORM3(vsubeuqm, 31, 0);
 GEN_VXFORM3(vsubecuq, 31, 0);
 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
             vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM(vrlb, 2, 0);
-GEN_VXFORM(vrlh, 2, 1);
-GEN_VXFORM(vrlw, 2, 2);
+GEN_VXFORM_V(vrlb, MO_8, tcg_gen_gvec_rotlv, 2, 0);
+GEN_VXFORM_V(vrlh, MO_16, tcg_gen_gvec_rotlv, 2, 1);
+GEN_VXFORM_V(vrlw, MO_32, tcg_gen_gvec_rotlv, 2, 2);
 GEN_VXFORM(vrlwmi, 2, 2);
 GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \
                 vrlwmi, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM(vrld, 2, 3);
+GEN_VXFORM_V(vrld, MO_64, tcg_gen_gvec_rotlv, 2, 3);
 GEN_VXFORM(vrldmi, 2, 3);
 GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \
                 vrldmi, PPC_NONE, PPC2_ISA300)
-- 
2.25.1

Merge VERLL and VERLLV into op_vesv and op_ves, alongside
all of the other vector shift operations.

Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/s390x/helper.h           |  4 --
 target/s390x/translate_vx.inc.c | 66 +++++----------------------------
 target/s390x/vec_int_helper.c   | 31 ----------------
 target/s390x/insn-data.def      |  4 +-
 4 files changed, 11 insertions(+), 94 deletions(-)

diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(gvec_vmlo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
 DEF_HELPER_FLAGS_4(gvec_vmlo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
 DEF_HELPER_FLAGS_3(gvec_vpopct8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
 DEF_HELPER_FLAGS_3(gvec_vpopct16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
-DEF_HELPER_FLAGS_4(gvec_verllv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
-DEF_HELPER_FLAGS_4(gvec_verllv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
-DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
-DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
 DEF_HELPER_FLAGS_4(gvec_verim8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
 DEF_HELPER_FLAGS_4(gvec_verim16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
 DEF_HELPER_FLAGS_4(gvec_vsl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_vpopct(DisasContext *s, DisasOps *o)
     return DISAS_NEXT;
 }
 
-static void gen_rll_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
-{
-    TCGv_i32 t0 = tcg_temp_new_i32();
-
-    tcg_gen_andi_i32(t0, b, 31);
-    tcg_gen_rotl_i32(d, a, t0);
-    tcg_temp_free_i32(t0);
-}
-
-static void gen_rll_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
-{
-    TCGv_i64 t0 = tcg_temp_new_i64();
-
-    tcg_gen_andi_i64(t0, b, 63);
-    tcg_gen_rotl_i64(d, a, t0);
-    tcg_temp_free_i64(t0);
-}
-
-static DisasJumpType op_verllv(DisasContext *s, DisasOps *o)
-{
-    const uint8_t es = get_field(s, m4);
-    static const GVecGen3 g[4] = {
-        { .fno = gen_helper_gvec_verllv8, },
-        { .fno = gen_helper_gvec_verllv16, },
-        { .fni4 = gen_rll_i32, },
-        { .fni8 = gen_rll_i64, },
-    };
-
-    if (es > ES_64) {
-        gen_program_exception(s, PGM_SPECIFICATION);
-        return DISAS_NORETURN;
-    }
-
-    gen_gvec_3(get_field(s, v1), get_field(s, v2),
-               get_field(s, v3), &g[es]);
-    return DISAS_NEXT;
-}
-
-static DisasJumpType op_verll(DisasContext *s, DisasOps *o)
-{
-    const uint8_t es = get_field(s, m4);
-    static const GVecGen2s g[4] = {
-        { .fno = gen_helper_gvec_verll8, },
-        { .fno = gen_helper_gvec_verll16, },
-        { .fni4 = gen_rll_i32, },
-        { .fni8 = gen_rll_i64, },
-    };
-
-    if (es > ES_64) {
-        gen_program_exception(s, PGM_SPECIFICATION);
-        return DISAS_NORETURN;
-    }
-    gen_gvec_2s(get_field(s, v1), get_field(s, v3), o->addr1,
-                &g[es]);
-    return DISAS_NEXT;
-}
-
 static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, int32_t c)
 {
     TCGv_i32 t = tcg_temp_new_i32();
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_vesv(DisasContext *s, DisasOps *o)
     case 0x70:
         gen_gvec_fn_3(shlv, es, v1, v2, v3);
         break;
+    case 0x73:
+        gen_gvec_fn_3(rotlv, es, v1, v2, v3);
+        break;
     case 0x7a:
         gen_gvec_fn_3(sarv, es, v1, v2, v3);
         break;
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_ves(DisasContext *s, DisasOps *o)
         case 0x30:
             gen_gvec_fn_2i(shli, es, v1, v3, d2);
             break;
+        case 0x33:
+            gen_gvec_fn_2i(rotli, es, v1, v3, d2);
+            break;
         case 0x3a:
             gen_gvec_fn_2i(sari, es, v1, v3, d2);
             break;
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_ves(DisasContext *s, DisasOps *o)
         case 0x30:
             gen_gvec_fn_2s(shls, es, v1, v3, shift);
             break;
+        case 0x33:
+            gen_gvec_fn_2s(rotls, es, v1, v3, shift);
+            break;
         case 0x3a:
             gen_gvec_fn_2s(sars, es, v1, v3, shift);
             break;
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_vpopct##BITS)(void *v1, const void *v2, uint32_t desc)        \
 DEF_VPOPCT(8)
 DEF_VPOPCT(16)
 
-#define DEF_VERLLV(BITS)                                                       \
-void HELPER(gvec_verllv##BITS)(void *v1, const void *v2, const void *v3,       \
-                               uint32_t desc)                                  \
-{                                                                              \
-    int i;                                                                     \
-                                                                               \
-    for (i = 0; i < (128 / BITS); i++) {                                       \
-        const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i);           \
-        const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i);           \
-                                                                               \
-        s390_vec_write_element##BITS(v1, i, rol##BITS(a, b));                  \
-    }                                                                          \
-}
-DEF_VERLLV(8)
-DEF_VERLLV(16)
-
-#define DEF_VERLL(BITS)                                                        \
-void HELPER(gvec_verll##BITS)(void *v1, const void *v2, uint64_t count,        \
-                              uint32_t desc)                                   \
-{                                                                              \
-    int i;                                                                     \
-                                                                               \
-    for (i = 0; i < (128 / BITS); i++) {                                       \
-        const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i);           \
-                                                                               \
-        s390_vec_write_element##BITS(v1, i, rol##BITS(a, count));              \
-    }                                                                          \
-}
-DEF_VERLL(8)
-DEF_VERLL(16)
-
 #define DEF_VERIM(BITS)                                                        \
 void HELPER(gvec_verim##BITS)(void *v1, const void *v2, const void *v3,        \
                               uint32_t desc)                                   \
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -XXX,XX +XXX,XX @@
 /* VECTOR POPULATION COUNT */
     F(0xe750, VPOPCT,  VRR_a, V,   0, 0, 0, 0, vpopct, 0, IF_VEC)
 /* VECTOR ELEMENT ROTATE LEFT LOGICAL */
-    F(0xe773, VERLLV,  VRR_c, V,   0, 0, 0, 0, verllv, 0, IF_VEC)
-    F(0xe733, VERLL,   VRS_a, V,   la2, 0, 0, 0, verll, 0, IF_VEC)
+    F(0xe773, VERLLV,  VRR_c, V,   0, 0, 0, 0, vesv, 0, IF_VEC)
+    F(0xe733, VERLL,   VRS_a, V,   la2, 0, 0, 0, ves, 0, IF_VEC)
 /* VECTOR ELEMENT ROTATE AND INSERT UNDER MASK */
     F(0xe772, VERIM,   VRI_d, V,   0, 0, 0, 0, verim, 0, IF_VEC)
 /* VECTOR ELEMENT SHIFT LEFT */
-- 
2.25.1

If the output of the move is dead, then the last use is in
the store.  If we propagate the input to the store, then we
can remove the move opcode entirely.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tcg.c | 78 +++++++++++++++++++++++++++++++++++++++----------------
 1 file changed, 56 insertions(+), 22 deletions(-)

diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ static bool liveness_pass_2(TCGContext *s)
         }
 
         /* Outputs become available.  */
-        for (i = 0; i < nb_oargs; i++) {
-            arg_ts = arg_temp(op->args[i]);
+        if (opc == INDEX_op_mov_i32 || opc == INDEX_op_mov_i64) {
+            arg_ts = arg_temp(op->args[0]);
             dir_ts = arg_ts->state_ptr;
-            if (!dir_ts) {
-                continue;
+            if (dir_ts) {
+                op->args[0] = temp_arg(dir_ts);
+                changes = true;
+
+                /* The output is now live and modified.  */
+                arg_ts->state = 0;
+
+                if (NEED_SYNC_ARG(0)) {
+                    TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32
+                                      ? INDEX_op_st_i32
+                                      : INDEX_op_st_i64);
+                    TCGOp *sop = tcg_op_insert_after(s, op, sopc);
+                    TCGTemp *out_ts = dir_ts;
+
+                    if (IS_DEAD_ARG(0)) {
+                        out_ts = arg_temp(op->args[1]);
+                        arg_ts->state = TS_DEAD;
+                        tcg_op_remove(s, op);
+                    } else {
+                        arg_ts->state = TS_MEM;
+                    }
+
+                    sop->args[0] = temp_arg(out_ts);
+                    sop->args[1] = temp_arg(arg_ts->mem_base);
+                    sop->args[2] = arg_ts->mem_offset;
+                } else {
+                    tcg_debug_assert(!IS_DEAD_ARG(0));
+                }
             }
-            op->args[i] = temp_arg(dir_ts);
-            changes = true;
+        } else {
+            for (i = 0; i < nb_oargs; i++) {
+                arg_ts = arg_temp(op->args[i]);
+                dir_ts = arg_ts->state_ptr;
+                if (!dir_ts) {
+                    continue;
+                }
+                op->args[i] = temp_arg(dir_ts);
+                changes = true;
 
-            /* The output is now live and modified.  */
-            arg_ts->state = 0;
+                /* The output is now live and modified.  */
+                arg_ts->state = 0;
 
-            /* Sync outputs upon their last write.  */
-            if (NEED_SYNC_ARG(i)) {
-                TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32
-                                  ? INDEX_op_st_i32
-                                  : INDEX_op_st_i64);
-                TCGOp *sop = tcg_op_insert_after(s, op, sopc);
+                /* Sync outputs upon their last write.  */
+                if (NEED_SYNC_ARG(i)) {
+                    TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32
+                                      ? INDEX_op_st_i32
+                                      : INDEX_op_st_i64);
+                    TCGOp *sop = tcg_op_insert_after(s, op, sopc);
 
-                sop->args[0] = temp_arg(dir_ts);
-                sop->args[1] = temp_arg(arg_ts->mem_base);
-                sop->args[2] = arg_ts->mem_offset;
+                    sop->args[0] = temp_arg(dir_ts);
+                    sop->args[1] = temp_arg(arg_ts->mem_base);
+                    sop->args[2] = arg_ts->mem_offset;
 
-                arg_ts->state = TS_MEM;
-            }
-            /* Drop outputs that are dead.  */
-            if (IS_DEAD_ARG(i)) {
-                arg_ts->state = TS_DEAD;
+                    arg_ts->state = TS_MEM;
+                }
+                /* Drop outputs that are dead.  */
+                if (IS_DEAD_ARG(i)) {
+                    arg_ts->state = TS_DEAD;
+                }
             }
         }
     }
-- 
2.25.1

From: Nick Hudson <skrll@netbsd.org>

Fix building on NetBSD/arm by extracting the FSR value from the
correct siginfo_t field.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nick Hudson <skrll@netbsd.org>
Message-Id: <20200516154147.24842-1-skrll@netbsd.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/user-exec.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo,
 
 #if defined(__NetBSD__)
 #include <ucontext.h>
+#include <sys/siginfo.h>
 #endif
 
 int cpu_signal_handler(int host_signum, void *pinfo,
@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo,
     siginfo_t *info = pinfo;
 #if defined(__NetBSD__)
     ucontext_t *uc = puc;
+    siginfo_t *si = pinfo;
 #else
     ucontext_t *uc = puc;
 #endif
     unsigned long pc;
+    uint32_t fsr;
     int is_write;
 
 #if defined(__NetBSD__)
@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo,
     pc = uc->uc_mcontext.arm_pc;
 #endif
 
-    /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
-     * later processor; on v5 we will always report this as a read).
+#ifdef __NetBSD__
+    fsr = si->si_trap;
+#else
+    fsr = uc->uc_mcontext.error_code;
+#endif
+    /*
+     * In the FSR, bit 11 is WnR, assuming a v6 or
+     * later processor.  On v5 we will always report
+     * this as a read, which will fail later.
      */
-    is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
+    is_write = extract32(fsr, 11, 1);
     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 }
 
-- 
2.25.1

From: Nick Hudson <skrll@netbsd.org>

Fix qemu build on NetBSD/evbarm-aarch64 by providing a NetBSD specific
cpu_signal_handler.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nick Hudson <skrll@netbsd.org>
Message-Id: <20200517101529.5367-1-skrll@netbsd.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/user-exec.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo,
 
 #elif defined(__aarch64__)
 
+#if defined(__NetBSD__)
+
+#include <ucontext.h>
+#include <sys/siginfo.h>
+
+int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
+{
+    ucontext_t *uc = puc;
+    siginfo_t *si = pinfo;
+    unsigned long pc;
+    int is_write;
+    uint32_t esr;
+
+    pc = uc->uc_mcontext.__gregs[_REG_PC];
+    esr = si->si_trap;
+
+    /*
+     * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC
+     * is 0b10010x: then bit 6 is the WnR bit
+     */
+    is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1;
+    return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask);
+}
+
+#else
+
 #ifndef ESR_MAGIC
 /* Pre-3.16 kernel headers don't have these, so provide fallback definitions */
 #define ESR_MAGIC 0x45535201
@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
     }
     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 }
+#endif
 
 #elif defined(__s390__)
 
-- 
2.25.1

Pretty small still, but there are two patches that ought
to get backported to stable, so no point in delaying.

The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:

Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212

for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:

target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)

----------------------------------------------------------------
tcg: Reset free_temps before tcg_optimize
tcg/riscv: Fix StoreStore barrier generation
include/exec: Introduce fpst alias in helper-head.h.inc
target/sparc: Use memcpy() and remove memcpy32()

----------------------------------------------------------------
Philippe Mathieu-Daudé (1):
      target/sparc: Use memcpy() and remove memcpy32()

Richard Henderson (2):
      tcg: Reset free_temps before tcg_optimize
      include/exec: Introduce fpst alias in helper-head.h.inc

Roman Artemev (1):
      tcg/riscv: Fix StoreStore barrier generation

When allocating new temps during tcg_optmize, do not re-use
any EBB temps that were used within the TB.  We do not have
any idea what span of the TB in which the temp was live.

Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
as well as replacing the equivalent in plugin_gen_inject and
tcg_func_start.

Cc: qemu-stable@nongnu.org
Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
Reported-by: wannacu <wannacu2049@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/tcg/tcg-temp-internal.h | 6 ++++++
 accel/tcg/plugin-gen.c          | 2 +-
 tcg/tcg.c                       | 5 ++++-
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg-temp-internal.h
+++ b/include/tcg/tcg-temp-internal.h
@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
 TCGv_ptr tcg_temp_ebb_new_ptr(void);
 TCGv_i128 tcg_temp_ebb_new_i128(void);
 
+/* Forget all freed EBB temps, so that new allocations produce new temps. */
+static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
+{
+    memset(s->free_temps, 0, sizeof(s->free_temps));
+}
+
 #endif /* TCG_TEMP_FREE_H */
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
      * that might be live within the existing opcode stream.
      * The simplest solution is to release them all and create new.
      */
-    memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
+    tcg_temp_ebb_reset_freed(tcg_ctx);
 
     QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
         switch (op->opc) {
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
     s->nb_temps = s->nb_globals;
 
     /* No temps have been previously allocated for size or locality.  */
-    memset(s->free_temps, 0, sizeof(s->free_temps));
+    tcg_temp_ebb_reset_freed(s);
 
     /* No constant temps have been previously allocated. */
     for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
     }
 #endif
 
+    /* Do not reuse any EBB that may be allocated within the TB. */
+    tcg_temp_ebb_reset_freed(s);
+
     tcg_optimize(s);
 
     reachable_code_pass(s);
-- 
2.43.0

From: Roman Artemev <roman.artemev@syntacore.com>

On RISC-V to StoreStore barrier corresponds
`fence w, w` not `fence r, r`

Cc: qemu-stable@nongnu.org
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/riscv/tcg-target.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
         insn |= 0x02100000;
     }
     if (a0 & TCG_MO_ST_ST) {
-        insn |= 0x02200000;
+        insn |= 0x01100000;
     }
     tcg_out32(s, insn);
 }
-- 
2.43.0

This allows targets to declare that the helper requires a
float_status pointer and instead of a generic void pointer.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/helper-head.h.inc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/helper-head.h.inc
+++ b/include/exec/helper-head.h.inc
@@ -XXX,XX +XXX,XX @@
 #define dh_alias_ptr ptr
 #define dh_alias_cptr ptr
 #define dh_alias_env ptr
+#define dh_alias_fpst ptr
 #define dh_alias_void void
 #define dh_alias_noreturn noreturn
 #define dh_alias(t) glue(dh_alias_, t)
@@ -XXX,XX +XXX,XX @@
 #define dh_ctype_ptr void *
 #define dh_ctype_cptr const void *
 #define dh_ctype_env CPUArchState *
+#define dh_ctype_fpst float_status *
 #define dh_ctype_void void
 #define dh_ctype_noreturn G_NORETURN void
 #define dh_ctype(t) dh_ctype_##t
@@ -XXX,XX +XXX,XX @@
 #define dh_typecode_f64 dh_typecode_i64
 #define dh_typecode_cptr dh_typecode_ptr
 #define dh_typecode_env dh_typecode_ptr
+#define dh_typecode_fpst dh_typecode_ptr
 #define dh_typecode(t) dh_typecode_##t
 
 #define dh_callflag_i32  0
-- 
2.43.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Rather than manually copying each register, use
the libc memcpy(), which is well optimized nowadays.

Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20241205205418.67613-1-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/win_helper.c | 26 ++++++++------------------
 1 file changed, 8 insertions(+), 18 deletions(-)

diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/sparc/win_helper.c
+++ b/target/sparc/win_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-proto.h"
 #include "trace.h"
 
-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
-{
-    dst[0] = src[0];
-    dst[1] = src[1];
-    dst[2] = src[2];
-    dst[3] = src[3];
-    dst[4] = src[4];
-    dst[5] = src[5];
-    dst[6] = src[6];
-    dst[7] = src[7];
-}
-
 void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
 {
     /* put the modified wrap registers at their proper location */
     if (env->cwp == env->nwindows - 1) {
-        memcpy32(env->regbase, env->regbase + env->nwindows * 16);
+        memcpy(env->regbase, env->regbase + env->nwindows * 16,
+               sizeof(env->gregs));
     }
     env->cwp = new_cwp;
 
     /* put the wrap registers at their temporary location */
     if (new_cwp == env->nwindows - 1) {
-        memcpy32(env->regbase + env->nwindows * 16, env->regbase);
+        memcpy(env->regbase + env->nwindows * 16, env->regbase,
+               sizeof(env->gregs));
     }
     env->regwptr = env->regbase + (new_cwp * 16);
 }
@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
     dst = get_gl_gregset(env, env->gl);
 
     if (src != dst) {
-        memcpy32(dst, env->gregs);
-        memcpy32(env->gregs, src);
+        memcpy(dst, env->gregs, sizeof(env->gregs));
+        memcpy(env->gregs, src, sizeof(env->gregs));
     }
 }
 
@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
         /* Switch global register bank */
         src = get_gregset(env, new_pstate_regs);
         dst = get_gregset(env, pstate_regs);
-        memcpy32(dst, env->gregs);
-        memcpy32(env->gregs, src);
+        memcpy(dst, env->gregs, sizeof(env->gregs));
+        memcpy(env->gregs, src, sizeof(env->gregs));
     } else {
         trace_win_helper_no_switch_pstate(new_pstate_regs);
     }
-- 
2.43.0