1 | I have not been able to prod reviews of all of the rotate patches | 1 | TCG patch queue, plus one target/sh4 patch that |
---|---|---|---|
2 | in 4 weeks, but let's not let that block ARM work forever. | 2 | Yoshinori Sato asked me to process. |
3 | 3 | ||
4 | 4 | ||
5 | r~ | 5 | r~ |
6 | 6 | ||
7 | 7 | ||
8 | The following changes since commit cccdd8c7971896c339d59c9c5d4647d4ffd9568a: | 8 | The following changes since commit efbf38d73e5dcc4d5f8b98c6e7a12be1f3b91745: |
9 | 9 | ||
10 | Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging (2020-06-02 10:25:55 +0100) | 10 | Merge tag 'for-upstream' of git://repo.or.cz/qemu/kevin into staging (2022-10-03 15:06:07 -0400) |
11 | 11 | ||
12 | are available in the Git repository at: | 12 | are available in the Git repository at: |
13 | 13 | ||
14 | https://github.com/rth7680/qemu.git tags/pull-tcg-20200602 | 14 | https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20221004 |
15 | 15 | ||
16 | for you to fetch changes up to 71b04329c4f7d5824a289ca5225e1883a278cf3b: | 16 | for you to fetch changes up to ab419fd8a035a65942de4e63effcd55ccbf1a9fe: |
17 | 17 | ||
18 | accel/tcg: Provide a NetBSD specific aarch64 cpu_signal_handler (2020-06-02 08:42:37 -0700) | 18 | target/sh4: Fix TB_FLAG_UNALIGN (2022-10-04 12:33:05 -0700) |
19 | 19 | ||
20 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
21 | Vector rotate support | 21 | Cache CPUClass for use in hot code paths. |
22 | Signal handling support for NetBSD arm/aarch64 | 22 | Add CPUTLBEntryFull, probe_access_full, tlb_set_page_full. |
23 | Add generic support for TARGET_TB_PCREL. | ||
24 | tcg/ppc: Optimize 26-bit jumps using STQ for POWER 2.07 | ||
25 | target/sh4: Fix TB_FLAG_UNALIGN | ||
23 | 26 | ||
24 | ---------------------------------------------------------------- | 27 | ---------------------------------------------------------------- |
25 | Nick Hudson (2): | 28 | Alex Bennée (3): |
26 | accel/tcg: Adjust cpu_signal_handler for NetBSD/arm | 29 | cpu: cache CPUClass in CPUState for hot code paths |
27 | accel/tcg: Provide a NetBSD specific aarch64 cpu_signal_handler | 30 | hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs |
31 | cputlb: used cached CPUClass in our hot-paths | ||
28 | 32 | ||
29 | Richard Henderson (10): | 33 | Leandro Lupori (1): |
30 | tcg: Implement gvec support for rotate by immediate | 34 | tcg/ppc: Optimize 26-bit jumps |
31 | tcg: Implement gvec support for rotate by vector | ||
32 | tcg: Remove expansion to shift by vector from do_shifts | ||
33 | tcg: Implement gvec support for rotate by scalar | ||
34 | tcg/i386: Implement INDEX_op_rotl{i,s,v}_vec | ||
35 | tcg/aarch64: Implement INDEX_op_rotl{i,v}_vec | ||
36 | tcg/ppc: Implement INDEX_op_rot[lr]v_vec | ||
37 | target/ppc: Use tcg_gen_gvec_rotlv | ||
38 | target/s390x: Use tcg_gen_gvec_rotl{i,s,v} | ||
39 | tcg: Improve move ops in liveness_pass_2 | ||
40 | 35 | ||
41 | accel/tcg/tcg-runtime.h | 15 +++ | 36 | Richard Henderson (16): |
42 | include/tcg/tcg-op-gvec.h | 12 ++ | 37 | accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull |
43 | include/tcg/tcg-op.h | 5 + | 38 | accel/tcg: Drop addr member from SavedIOTLB |
44 | include/tcg/tcg-opc.h | 4 + | 39 | accel/tcg: Suppress auto-invalidate in probe_access_internal |
45 | include/tcg/tcg.h | 3 + | 40 | accel/tcg: Introduce probe_access_full |
46 | target/ppc/helper.h | 4 - | 41 | accel/tcg: Introduce tlb_set_page_full |
47 | target/s390x/helper.h | 4 - | 42 | include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA |
48 | tcg/aarch64/tcg-target.h | 3 + | 43 | accel/tcg: Remove PageDesc code_bitmap |
49 | tcg/aarch64/tcg-target.opc.h | 1 + | 44 | accel/tcg: Use bool for page_find_alloc |
50 | tcg/i386/tcg-target.h | 3 + | 45 | accel/tcg: Use DisasContextBase in plugin_gen_tb_start |
51 | tcg/ppc/tcg-target.h | 3 + | 46 | accel/tcg: Do not align tb->page_addr[0] |
52 | tcg/ppc/tcg-target.opc.h | 1 - | 47 | accel/tcg: Inline tb_flush_jmp_cache |
53 | accel/tcg/tcg-runtime-gvec.c | 144 ++++++++++++++++++++++++ | 48 | include/hw/core: Create struct CPUJumpCache |
54 | accel/tcg/user-exec.c | 43 +++++++- | 49 | hw/core: Add CPUClass.get_pc |
55 | target/ppc/int_helper.c | 17 --- | 50 | accel/tcg: Introduce tb_pc and log_pc |
56 | target/ppc/translate/vmx-impl.inc.c | 8 +- | 51 | accel/tcg: Introduce TARGET_TB_PCREL |
57 | target/s390x/translate_vx.inc.c | 66 ++--------- | 52 | target/sh4: Fix TB_FLAG_UNALIGN |
58 | target/s390x/vec_int_helper.c | 31 ------ | ||
59 | tcg/aarch64/tcg-target.inc.c | 53 ++++++++- | ||
60 | tcg/i386/tcg-target.inc.c | 116 +++++++++++++++++--- | ||
61 | tcg/ppc/tcg-target.inc.c | 23 +++- | ||
62 | tcg/tcg-op-gvec.c | 212 ++++++++++++++++++++++++++++++++++++ | ||
63 | tcg/tcg-op-vec.c | 62 +++++++---- | ||
64 | tcg/tcg.c | 85 +++++++++++---- | ||
65 | target/s390x/insn-data.def | 4 +- | ||
66 | tcg/README | 7 +- | ||
67 | 26 files changed, 736 insertions(+), 193 deletions(-) | ||
68 | 53 | ||
54 | accel/tcg/internal.h | 10 ++ | ||
55 | accel/tcg/tb-hash.h | 1 + | ||
56 | accel/tcg/tb-jmp-cache.h | 65 ++++++++ | ||
57 | include/exec/cpu-common.h | 1 + | ||
58 | include/exec/cpu-defs.h | 48 ++++-- | ||
59 | include/exec/exec-all.h | 75 ++++++++- | ||
60 | include/exec/plugin-gen.h | 7 +- | ||
61 | include/hw/core/cpu.h | 28 ++-- | ||
62 | include/qemu/typedefs.h | 2 + | ||
63 | include/tcg/tcg.h | 2 +- | ||
64 | target/sh4/cpu.h | 56 ++++--- | ||
65 | accel/stubs/tcg-stub.c | 4 + | ||
66 | accel/tcg/cpu-exec.c | 80 +++++----- | ||
67 | accel/tcg/cputlb.c | 259 ++++++++++++++++++-------------- | ||
68 | accel/tcg/plugin-gen.c | 22 +-- | ||
69 | accel/tcg/translate-all.c | 214 ++++++++++++-------------- | ||
70 | accel/tcg/translator.c | 2 +- | ||
71 | cpu.c | 9 +- | ||
72 | hw/core/cpu-common.c | 3 +- | ||
73 | hw/core/cpu-sysemu.c | 5 +- | ||
74 | linux-user/sh4/signal.c | 6 +- | ||
75 | plugins/core.c | 2 +- | ||
76 | target/alpha/cpu.c | 9 ++ | ||
77 | target/arm/cpu.c | 17 ++- | ||
78 | target/arm/mte_helper.c | 14 +- | ||
79 | target/arm/sve_helper.c | 4 +- | ||
80 | target/arm/translate-a64.c | 2 +- | ||
81 | target/avr/cpu.c | 10 +- | ||
82 | target/cris/cpu.c | 8 + | ||
83 | target/hexagon/cpu.c | 10 +- | ||
84 | target/hppa/cpu.c | 12 +- | ||
85 | target/i386/cpu.c | 9 ++ | ||
86 | target/i386/tcg/tcg-cpu.c | 2 +- | ||
87 | target/loongarch/cpu.c | 11 +- | ||
88 | target/m68k/cpu.c | 8 + | ||
89 | target/microblaze/cpu.c | 10 +- | ||
90 | target/mips/cpu.c | 8 + | ||
91 | target/mips/tcg/exception.c | 2 +- | ||
92 | target/mips/tcg/sysemu/special_helper.c | 2 +- | ||
93 | target/nios2/cpu.c | 9 ++ | ||
94 | target/openrisc/cpu.c | 10 +- | ||
95 | target/ppc/cpu_init.c | 8 + | ||
96 | target/riscv/cpu.c | 17 ++- | ||
97 | target/rx/cpu.c | 10 +- | ||
98 | target/s390x/cpu.c | 8 + | ||
99 | target/s390x/tcg/mem_helper.c | 4 - | ||
100 | target/sh4/cpu.c | 18 ++- | ||
101 | target/sh4/helper.c | 6 +- | ||
102 | target/sh4/translate.c | 90 +++++------ | ||
103 | target/sparc/cpu.c | 10 +- | ||
104 | target/tricore/cpu.c | 11 +- | ||
105 | target/xtensa/cpu.c | 8 + | ||
106 | tcg/tcg.c | 8 +- | ||
107 | trace/control-target.c | 2 +- | ||
108 | tcg/ppc/tcg-target.c.inc | 119 +++++++++++---- | ||
109 | 55 files changed, 915 insertions(+), 462 deletions(-) | ||
110 | create mode 100644 accel/tcg/tb-jmp-cache.h | ||
111 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Alex Bennée <alex.bennee@linaro.org> | ||
1 | 2 | ||
3 | The class cast checkers are quite expensive and always on (unlike the | ||
4 | dynamic case who's checks are gated by CONFIG_QOM_CAST_DEBUG). To | ||
5 | avoid the overhead of repeatedly checking something which should never | ||
6 | change we cache the CPUClass reference for use in the hot code paths. | ||
7 | |||
8 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-Id: <20220811151413.3350684-3-alex.bennee@linaro.org> | ||
11 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
12 | Message-Id: <20220923084803.498337-3-clg@kaod.org> | ||
13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | --- | ||
15 | include/hw/core/cpu.h | 9 +++++++++ | ||
16 | cpu.c | 9 ++++----- | ||
17 | 2 files changed, 13 insertions(+), 5 deletions(-) | ||
18 | |||
19 | diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/include/hw/core/cpu.h | ||
22 | +++ b/include/hw/core/cpu.h | ||
23 | @@ -XXX,XX +XXX,XX @@ typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, | ||
24 | */ | ||
25 | #define CPU(obj) ((CPUState *)(obj)) | ||
26 | |||
27 | +/* | ||
28 | + * The class checkers bring in CPU_GET_CLASS() which is potentially | ||
29 | + * expensive given the eventual call to | ||
30 | + * object_class_dynamic_cast_assert(). Because of this the CPUState | ||
31 | + * has a cached value for the class in cs->cc which is set up in | ||
32 | + * cpu_exec_realizefn() for use in hot code paths. | ||
33 | + */ | ||
34 | typedef struct CPUClass CPUClass; | ||
35 | DECLARE_CLASS_CHECKERS(CPUClass, CPU, | ||
36 | TYPE_CPU) | ||
37 | @@ -XXX,XX +XXX,XX @@ struct qemu_work_item; | ||
38 | struct CPUState { | ||
39 | /*< private >*/ | ||
40 | DeviceState parent_obj; | ||
41 | + /* cache to avoid expensive CPU_GET_CLASS */ | ||
42 | + CPUClass *cc; | ||
43 | /*< public >*/ | ||
44 | |||
45 | int nr_cores; | ||
46 | diff --git a/cpu.c b/cpu.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/cpu.c | ||
49 | +++ b/cpu.c | ||
50 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_cpu_common = { | ||
51 | |||
52 | void cpu_exec_realizefn(CPUState *cpu, Error **errp) | ||
53 | { | ||
54 | -#ifndef CONFIG_USER_ONLY | ||
55 | - CPUClass *cc = CPU_GET_CLASS(cpu); | ||
56 | -#endif | ||
57 | + /* cache the cpu class for the hotpath */ | ||
58 | + cpu->cc = CPU_GET_CLASS(cpu); | ||
59 | |||
60 | cpu_list_add(cpu); | ||
61 | if (!accel_cpu_realizefn(cpu, errp)) { | ||
62 | @@ -XXX,XX +XXX,XX @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) | ||
63 | if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { | ||
64 | vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); | ||
65 | } | ||
66 | - if (cc->sysemu_ops->legacy_vmsd != NULL) { | ||
67 | - vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu); | ||
68 | + if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) { | ||
69 | + vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu); | ||
70 | } | ||
71 | #endif /* CONFIG_USER_ONLY */ | ||
72 | } | ||
73 | -- | ||
74 | 2.34.1 | ||
75 | |||
76 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Alex Bennée <alex.bennee@linaro.org> | ||
1 | 2 | ||
3 | This is a heavily used function so lets avoid the cost of | ||
4 | CPU_GET_CLASS. On the romulus-bmc run it has a modest effect: | ||
5 | |||
6 | Before: 36.812 s ± 0.506 s | ||
7 | After: 35.912 s ± 0.168 s | ||
8 | |||
9 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-Id: <20220811151413.3350684-4-alex.bennee@linaro.org> | ||
12 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
13 | Message-Id: <20220923084803.498337-4-clg@kaod.org> | ||
14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | --- | ||
16 | hw/core/cpu-sysemu.c | 5 ++--- | ||
17 | 1 file changed, 2 insertions(+), 3 deletions(-) | ||
18 | |||
19 | diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/hw/core/cpu-sysemu.c | ||
22 | +++ b/hw/core/cpu-sysemu.c | ||
23 | @@ -XXX,XX +XXX,XX @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) | ||
24 | |||
25 | int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) | ||
26 | { | ||
27 | - CPUClass *cc = CPU_GET_CLASS(cpu); | ||
28 | int ret = 0; | ||
29 | |||
30 | - if (cc->sysemu_ops->asidx_from_attrs) { | ||
31 | - ret = cc->sysemu_ops->asidx_from_attrs(cpu, attrs); | ||
32 | + if (cpu->cc->sysemu_ops->asidx_from_attrs) { | ||
33 | + ret = cpu->cc->sysemu_ops->asidx_from_attrs(cpu, attrs); | ||
34 | assert(ret < cpu->num_ases && ret >= 0); | ||
35 | } | ||
36 | return ret; | ||
37 | -- | ||
38 | 2.34.1 | ||
39 | |||
40 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Alex Bennée <alex.bennee@linaro.org> | ||
1 | 2 | ||
3 | Before: 35.912 s ± 0.168 s | ||
4 | After: 35.565 s ± 0.087 s | ||
5 | |||
6 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-Id: <20220811151413.3350684-5-alex.bennee@linaro.org> | ||
9 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
10 | Message-Id: <20220923084803.498337-5-clg@kaod.org> | ||
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | --- | ||
13 | accel/tcg/cputlb.c | 15 ++++++--------- | ||
14 | 1 file changed, 6 insertions(+), 9 deletions(-) | ||
15 | |||
16 | diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/accel/tcg/cputlb.c | ||
19 | +++ b/accel/tcg/cputlb.c | ||
20 | @@ -XXX,XX +XXX,XX @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, | ||
21 | static void tlb_fill(CPUState *cpu, target_ulong addr, int size, | ||
22 | MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) | ||
23 | { | ||
24 | - CPUClass *cc = CPU_GET_CLASS(cpu); | ||
25 | bool ok; | ||
26 | |||
27 | /* | ||
28 | * This is not a probe, so only valid return is success; failure | ||
29 | * should result in exception + longjmp to the cpu loop. | ||
30 | */ | ||
31 | - ok = cc->tcg_ops->tlb_fill(cpu, addr, size, | ||
32 | - access_type, mmu_idx, false, retaddr); | ||
33 | + ok = cpu->cc->tcg_ops->tlb_fill(cpu, addr, size, | ||
34 | + access_type, mmu_idx, false, retaddr); | ||
35 | assert(ok); | ||
36 | } | ||
37 | |||
38 | @@ -XXX,XX +XXX,XX @@ static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, | ||
39 | MMUAccessType access_type, | ||
40 | int mmu_idx, uintptr_t retaddr) | ||
41 | { | ||
42 | - CPUClass *cc = CPU_GET_CLASS(cpu); | ||
43 | - | ||
44 | - cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); | ||
45 | + cpu->cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, | ||
46 | + mmu_idx, retaddr); | ||
47 | } | ||
48 | |||
49 | static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, | ||
50 | @@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, | ||
51 | if (!tlb_hit_page(tlb_addr, page_addr)) { | ||
52 | if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) { | ||
53 | CPUState *cs = env_cpu(env); | ||
54 | - CPUClass *cc = CPU_GET_CLASS(cs); | ||
55 | |||
56 | - if (!cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_type, | ||
57 | - mmu_idx, nonfault, retaddr)) { | ||
58 | + if (!cs->cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_type, | ||
59 | + mmu_idx, nonfault, retaddr)) { | ||
60 | /* Non-faulting page table read failed. */ | ||
61 | *phost = NULL; | ||
62 | return TLB_INVALID_MASK; | ||
63 | -- | ||
64 | 2.34.1 | ||
65 | |||
66 | diff view generated by jsdifflib |
1 | From: Nick Hudson <skrll@netbsd.org> | 1 | This structure will shortly contain more than just |
---|---|---|---|
2 | data for accessing MMIO. Rename the 'addr' member | ||
3 | to 'xlat_section' to more clearly indicate its purpose. | ||
2 | 4 | ||
3 | Fix building on NetBSD/arm by extracting the FSR value from the | 5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
4 | correct siginfo_t field. | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Signed-off-by: Nick Hudson <skrll@netbsd.org> | ||
8 | Message-Id: <20200516154147.24842-1-skrll@netbsd.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | --- | 9 | --- |
11 | accel/tcg/user-exec.c | 16 +++++++++++++--- | 10 | include/exec/cpu-defs.h | 22 ++++---- |
12 | 1 file changed, 13 insertions(+), 3 deletions(-) | 11 | accel/tcg/cputlb.c | 102 +++++++++++++++++++------------------ |
12 | target/arm/mte_helper.c | 14 ++--- | ||
13 | target/arm/sve_helper.c | 4 +- | ||
14 | target/arm/translate-a64.c | 2 +- | ||
15 | 5 files changed, 73 insertions(+), 71 deletions(-) | ||
13 | 16 | ||
14 | diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c | 17 | diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h |
15 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/accel/tcg/user-exec.c | 19 | --- a/include/exec/cpu-defs.h |
17 | +++ b/accel/tcg/user-exec.c | 20 | +++ b/include/exec/cpu-defs.h |
18 | @@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo, | 21 | @@ -XXX,XX +XXX,XX @@ typedef uint64_t target_ulong; |
19 | 22 | # endif | |
20 | #if defined(__NetBSD__) | 23 | # endif |
21 | #include <ucontext.h> | 24 | |
22 | +#include <sys/siginfo.h> | 25 | +/* Minimalized TLB entry for use by TCG fast path. */ |
26 | typedef struct CPUTLBEntry { | ||
27 | /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address | ||
28 | bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not | ||
29 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntry { | ||
30 | |||
31 | QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); | ||
32 | |||
33 | -/* The IOTLB is not accessed directly inline by generated TCG code, | ||
34 | - * so the CPUIOTLBEntry layout is not as critical as that of the | ||
35 | - * CPUTLBEntry. (This is also why we don't want to combine the two | ||
36 | - * structs into one.) | ||
37 | +/* | ||
38 | + * The full TLB entry, which is not accessed by generated TCG code, | ||
39 | + * so the layout is not as critical as that of CPUTLBEntry. This is | ||
40 | + * also why we don't want to combine the two structs. | ||
41 | */ | ||
42 | -typedef struct CPUIOTLBEntry { | ||
43 | +typedef struct CPUTLBEntryFull { | ||
44 | /* | ||
45 | - * @addr contains: | ||
46 | + * @xlat_section contains: | ||
47 | * - in the lower TARGET_PAGE_BITS, a physical section number | ||
48 | * - with the lower TARGET_PAGE_BITS masked off, an offset which | ||
49 | * must be added to the virtual address to obtain: | ||
50 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUIOTLBEntry { | ||
51 | * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) | ||
52 | * + the offset within the target MemoryRegion (otherwise) | ||
53 | */ | ||
54 | - hwaddr addr; | ||
55 | + hwaddr xlat_section; | ||
56 | MemTxAttrs attrs; | ||
57 | -} CPUIOTLBEntry; | ||
58 | +} CPUTLBEntryFull; | ||
59 | |||
60 | /* | ||
61 | * Data elements that are per MMU mode, minus the bits accessed by | ||
62 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBDesc { | ||
63 | size_t vindex; | ||
64 | /* The tlb victim table, in two parts. */ | ||
65 | CPUTLBEntry vtable[CPU_VTLB_SIZE]; | ||
66 | - CPUIOTLBEntry viotlb[CPU_VTLB_SIZE]; | ||
67 | - /* The iotlb. */ | ||
68 | - CPUIOTLBEntry *iotlb; | ||
69 | + CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; | ||
70 | + CPUTLBEntryFull *fulltlb; | ||
71 | } CPUTLBDesc; | ||
72 | |||
73 | /* | ||
74 | diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c | ||
75 | index XXXXXXX..XXXXXXX 100644 | ||
76 | --- a/accel/tcg/cputlb.c | ||
77 | +++ b/accel/tcg/cputlb.c | ||
78 | @@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast, | ||
79 | } | ||
80 | |||
81 | g_free(fast->table); | ||
82 | - g_free(desc->iotlb); | ||
83 | + g_free(desc->fulltlb); | ||
84 | |||
85 | tlb_window_reset(desc, now, 0); | ||
86 | /* desc->n_used_entries is cleared by the caller */ | ||
87 | fast->mask = (new_size - 1) << CPU_TLB_ENTRY_BITS; | ||
88 | fast->table = g_try_new(CPUTLBEntry, new_size); | ||
89 | - desc->iotlb = g_try_new(CPUIOTLBEntry, new_size); | ||
90 | + desc->fulltlb = g_try_new(CPUTLBEntryFull, new_size); | ||
91 | |||
92 | /* | ||
93 | * If the allocations fail, try smaller sizes. We just freed some | ||
94 | @@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast, | ||
95 | * allocations to fail though, so we progressively reduce the allocation | ||
96 | * size, aborting if we cannot even allocate the smallest TLB we support. | ||
97 | */ | ||
98 | - while (fast->table == NULL || desc->iotlb == NULL) { | ||
99 | + while (fast->table == NULL || desc->fulltlb == NULL) { | ||
100 | if (new_size == (1 << CPU_TLB_DYN_MIN_BITS)) { | ||
101 | error_report("%s: %s", __func__, strerror(errno)); | ||
102 | abort(); | ||
103 | @@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast, | ||
104 | fast->mask = (new_size - 1) << CPU_TLB_ENTRY_BITS; | ||
105 | |||
106 | g_free(fast->table); | ||
107 | - g_free(desc->iotlb); | ||
108 | + g_free(desc->fulltlb); | ||
109 | fast->table = g_try_new(CPUTLBEntry, new_size); | ||
110 | - desc->iotlb = g_try_new(CPUIOTLBEntry, new_size); | ||
111 | + desc->fulltlb = g_try_new(CPUTLBEntryFull, new_size); | ||
112 | } | ||
113 | } | ||
114 | |||
115 | @@ -XXX,XX +XXX,XX @@ static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDescFast *fast, int64_t now) | ||
116 | desc->n_used_entries = 0; | ||
117 | fast->mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS; | ||
118 | fast->table = g_new(CPUTLBEntry, n_entries); | ||
119 | - desc->iotlb = g_new(CPUIOTLBEntry, n_entries); | ||
120 | + desc->fulltlb = g_new(CPUTLBEntryFull, n_entries); | ||
121 | tlb_mmu_flush_locked(desc, fast); | ||
122 | } | ||
123 | |||
124 | @@ -XXX,XX +XXX,XX @@ void tlb_destroy(CPUState *cpu) | ||
125 | CPUTLBDescFast *fast = &env_tlb(env)->f[i]; | ||
126 | |||
127 | g_free(fast->table); | ||
128 | - g_free(desc->iotlb); | ||
129 | + g_free(desc->fulltlb); | ||
130 | } | ||
131 | } | ||
132 | |||
133 | @@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, | ||
134 | |||
135 | /* Evict the old entry into the victim tlb. */ | ||
136 | copy_tlb_helper_locked(tv, te); | ||
137 | - desc->viotlb[vidx] = desc->iotlb[index]; | ||
138 | + desc->vfulltlb[vidx] = desc->fulltlb[index]; | ||
139 | tlb_n_used_entries_dec(env, mmu_idx); | ||
140 | } | ||
141 | |||
142 | @@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, | ||
143 | * subtract here is that of the page base, and not the same as the | ||
144 | * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). | ||
145 | */ | ||
146 | - desc->iotlb[index].addr = iotlb - vaddr_page; | ||
147 | - desc->iotlb[index].attrs = attrs; | ||
148 | + desc->fulltlb[index].xlat_section = iotlb - vaddr_page; | ||
149 | + desc->fulltlb[index].attrs = attrs; | ||
150 | |||
151 | /* Now calculate the new entry */ | ||
152 | tn.addend = addend - vaddr_page; | ||
153 | @@ -XXX,XX +XXX,XX @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, | ||
154 | } | ||
155 | } | ||
156 | |||
157 | -static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, | ||
158 | +static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full, | ||
159 | int mmu_idx, target_ulong addr, uintptr_t retaddr, | ||
160 | MMUAccessType access_type, MemOp op) | ||
161 | { | ||
162 | @@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, | ||
163 | bool locked = false; | ||
164 | MemTxResult r; | ||
165 | |||
166 | - section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); | ||
167 | + section = iotlb_to_section(cpu, full->xlat_section, full->attrs); | ||
168 | mr = section->mr; | ||
169 | - mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; | ||
170 | + mr_offset = (full->xlat_section & TARGET_PAGE_MASK) + addr; | ||
171 | cpu->mem_io_pc = retaddr; | ||
172 | if (!cpu->can_do_io) { | ||
173 | cpu_io_recompile(cpu, retaddr); | ||
174 | @@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, | ||
175 | qemu_mutex_lock_iothread(); | ||
176 | locked = true; | ||
177 | } | ||
178 | - r = memory_region_dispatch_read(mr, mr_offset, &val, op, iotlbentry->attrs); | ||
179 | + r = memory_region_dispatch_read(mr, mr_offset, &val, op, full->attrs); | ||
180 | if (r != MEMTX_OK) { | ||
181 | hwaddr physaddr = mr_offset + | ||
182 | section->offset_within_address_space - | ||
183 | section->offset_within_region; | ||
184 | |||
185 | cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), access_type, | ||
186 | - mmu_idx, iotlbentry->attrs, r, retaddr); | ||
187 | + mmu_idx, full->attrs, r, retaddr); | ||
188 | } | ||
189 | if (locked) { | ||
190 | qemu_mutex_unlock_iothread(); | ||
191 | @@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, | ||
192 | } | ||
193 | |||
194 | /* | ||
195 | - * Save a potentially trashed IOTLB entry for later lookup by plugin. | ||
196 | - * This is read by tlb_plugin_lookup if the iotlb entry doesn't match | ||
197 | + * Save a potentially trashed CPUTLBEntryFull for later lookup by plugin. | ||
198 | + * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match | ||
199 | * because of the side effect of io_writex changing memory layout. | ||
200 | */ | ||
201 | static void save_iotlb_data(CPUState *cs, hwaddr addr, | ||
202 | @@ -XXX,XX +XXX,XX @@ static void save_iotlb_data(CPUState *cs, hwaddr addr, | ||
23 | #endif | 203 | #endif |
24 | 204 | } | |
25 | int cpu_signal_handler(int host_signum, void *pinfo, | 205 | |
26 | @@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo, | 206 | -static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, |
27 | siginfo_t *info = pinfo; | 207 | +static void io_writex(CPUArchState *env, CPUTLBEntryFull *full, |
28 | #if defined(__NetBSD__) | 208 | int mmu_idx, uint64_t val, target_ulong addr, |
29 | ucontext_t *uc = puc; | 209 | uintptr_t retaddr, MemOp op) |
30 | + siginfo_t *si = pinfo; | 210 | { |
211 | @@ -XXX,XX +XXX,XX @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, | ||
212 | bool locked = false; | ||
213 | MemTxResult r; | ||
214 | |||
215 | - section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); | ||
216 | + section = iotlb_to_section(cpu, full->xlat_section, full->attrs); | ||
217 | mr = section->mr; | ||
218 | - mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; | ||
219 | + mr_offset = (full->xlat_section & TARGET_PAGE_MASK) + addr; | ||
220 | if (!cpu->can_do_io) { | ||
221 | cpu_io_recompile(cpu, retaddr); | ||
222 | } | ||
223 | @@ -XXX,XX +XXX,XX @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, | ||
224 | * The memory_region_dispatch may trigger a flush/resize | ||
225 | * so for plugins we save the iotlb_data just in case. | ||
226 | */ | ||
227 | - save_iotlb_data(cpu, iotlbentry->addr, section, mr_offset); | ||
228 | + save_iotlb_data(cpu, full->xlat_section, section, mr_offset); | ||
229 | |||
230 | if (!qemu_mutex_iothread_locked()) { | ||
231 | qemu_mutex_lock_iothread(); | ||
232 | locked = true; | ||
233 | } | ||
234 | - r = memory_region_dispatch_write(mr, mr_offset, val, op, iotlbentry->attrs); | ||
235 | + r = memory_region_dispatch_write(mr, mr_offset, val, op, full->attrs); | ||
236 | if (r != MEMTX_OK) { | ||
237 | hwaddr physaddr = mr_offset + | ||
238 | section->offset_within_address_space - | ||
239 | section->offset_within_region; | ||
240 | |||
241 | cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), | ||
242 | - MMU_DATA_STORE, mmu_idx, iotlbentry->attrs, r, | ||
243 | + MMU_DATA_STORE, mmu_idx, full->attrs, r, | ||
244 | retaddr); | ||
245 | } | ||
246 | if (locked) { | ||
247 | @@ -XXX,XX +XXX,XX @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, | ||
248 | copy_tlb_helper_locked(vtlb, &tmptlb); | ||
249 | qemu_spin_unlock(&env_tlb(env)->c.lock); | ||
250 | |||
251 | - CPUIOTLBEntry tmpio, *io = &env_tlb(env)->d[mmu_idx].iotlb[index]; | ||
252 | - CPUIOTLBEntry *vio = &env_tlb(env)->d[mmu_idx].viotlb[vidx]; | ||
253 | - tmpio = *io; *io = *vio; *vio = tmpio; | ||
254 | + CPUTLBEntryFull *f1 = &env_tlb(env)->d[mmu_idx].fulltlb[index]; | ||
255 | + CPUTLBEntryFull *f2 = &env_tlb(env)->d[mmu_idx].vfulltlb[vidx]; | ||
256 | + CPUTLBEntryFull tmpf; | ||
257 | + tmpf = *f1; *f1 = *f2; *f2 = tmpf; | ||
258 | return true; | ||
259 | } | ||
260 | } | ||
261 | @@ -XXX,XX +XXX,XX @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, | ||
262 | (ADDR) & TARGET_PAGE_MASK) | ||
263 | |||
264 | static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size, | ||
265 | - CPUIOTLBEntry *iotlbentry, uintptr_t retaddr) | ||
266 | + CPUTLBEntryFull *full, uintptr_t retaddr) | ||
267 | { | ||
268 | - ram_addr_t ram_addr = mem_vaddr + iotlbentry->addr; | ||
269 | + ram_addr_t ram_addr = mem_vaddr + full->xlat_section; | ||
270 | |||
271 | trace_memory_notdirty_write_access(mem_vaddr, ram_addr, size); | ||
272 | |||
273 | @@ -XXX,XX +XXX,XX @@ int probe_access_flags(CPUArchState *env, target_ulong addr, | ||
274 | /* Handle clean RAM pages. */ | ||
275 | if (unlikely(flags & TLB_NOTDIRTY)) { | ||
276 | uintptr_t index = tlb_index(env, mmu_idx, addr); | ||
277 | - CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index]; | ||
278 | + CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; | ||
279 | |||
280 | - notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr); | ||
281 | + notdirty_write(env_cpu(env), addr, 1, full, retaddr); | ||
282 | flags &= ~TLB_NOTDIRTY; | ||
283 | } | ||
284 | |||
285 | @@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, | ||
286 | |||
287 | if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) { | ||
288 | uintptr_t index = tlb_index(env, mmu_idx, addr); | ||
289 | - CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index]; | ||
290 | + CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; | ||
291 | |||
292 | /* Handle watchpoints. */ | ||
293 | if (flags & TLB_WATCHPOINT) { | ||
294 | int wp_access = (access_type == MMU_DATA_STORE | ||
295 | ? BP_MEM_WRITE : BP_MEM_READ); | ||
296 | cpu_check_watchpoint(env_cpu(env), addr, size, | ||
297 | - iotlbentry->attrs, wp_access, retaddr); | ||
298 | + full->attrs, wp_access, retaddr); | ||
299 | } | ||
300 | |||
301 | /* Handle clean RAM pages. */ | ||
302 | if (flags & TLB_NOTDIRTY) { | ||
303 | - notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr); | ||
304 | + notdirty_write(env_cpu(env), addr, 1, full, retaddr); | ||
305 | } | ||
306 | } | ||
307 | |||
308 | @@ -XXX,XX +XXX,XX @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr, | ||
309 | * should have just filled the TLB. The one corner case is io_writex | ||
310 | * which can cause TLB flushes and potential resizing of the TLBs | ||
311 | * losing the information we need. In those cases we need to recover | ||
312 | - * data from a copy of the iotlbentry. As long as this always occurs | ||
313 | + * data from a copy of the CPUTLBEntryFull. As long as this always occurs | ||
314 | * from the same thread (which a mem callback will be) this is safe. | ||
315 | */ | ||
316 | |||
317 | @@ -XXX,XX +XXX,XX @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx, | ||
318 | if (likely(tlb_hit(tlb_addr, addr))) { | ||
319 | /* We must have an iotlb entry for MMIO */ | ||
320 | if (tlb_addr & TLB_MMIO) { | ||
321 | - CPUIOTLBEntry *iotlbentry; | ||
322 | - iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index]; | ||
323 | + CPUTLBEntryFull *full; | ||
324 | + full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; | ||
325 | data->is_io = true; | ||
326 | - data->v.io.section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); | ||
327 | - data->v.io.offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; | ||
328 | + data->v.io.section = | ||
329 | + iotlb_to_section(cpu, full->xlat_section, full->attrs); | ||
330 | + data->v.io.offset = (full->xlat_section & TARGET_PAGE_MASK) + addr; | ||
331 | } else { | ||
332 | data->is_io = false; | ||
333 | data->v.ram.hostaddr = (void *)((uintptr_t)addr + tlbe->addend); | ||
334 | @@ -XXX,XX +XXX,XX @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, | ||
335 | |||
336 | if (unlikely(tlb_addr & TLB_NOTDIRTY)) { | ||
337 | notdirty_write(env_cpu(env), addr, size, | ||
338 | - &env_tlb(env)->d[mmu_idx].iotlb[index], retaddr); | ||
339 | + &env_tlb(env)->d[mmu_idx].fulltlb[index], retaddr); | ||
340 | } | ||
341 | |||
342 | return hostaddr; | ||
343 | @@ -XXX,XX +XXX,XX @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi, | ||
344 | |||
345 | /* Handle anything that isn't just a straight memory access. */ | ||
346 | if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { | ||
347 | - CPUIOTLBEntry *iotlbentry; | ||
348 | + CPUTLBEntryFull *full; | ||
349 | bool need_swap; | ||
350 | |||
351 | /* For anything that is unaligned, recurse through full_load. */ | ||
352 | @@ -XXX,XX +XXX,XX @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi, | ||
353 | goto do_unaligned_access; | ||
354 | } | ||
355 | |||
356 | - iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index]; | ||
357 | + full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; | ||
358 | |||
359 | /* Handle watchpoints. */ | ||
360 | if (unlikely(tlb_addr & TLB_WATCHPOINT)) { | ||
361 | /* On watchpoint hit, this will longjmp out. */ | ||
362 | cpu_check_watchpoint(env_cpu(env), addr, size, | ||
363 | - iotlbentry->attrs, BP_MEM_READ, retaddr); | ||
364 | + full->attrs, BP_MEM_READ, retaddr); | ||
365 | } | ||
366 | |||
367 | need_swap = size > 1 && (tlb_addr & TLB_BSWAP); | ||
368 | |||
369 | /* Handle I/O access. */ | ||
370 | if (likely(tlb_addr & TLB_MMIO)) { | ||
371 | - return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, | ||
372 | + return io_readx(env, full, mmu_idx, addr, retaddr, | ||
373 | access_type, op ^ (need_swap * MO_BSWAP)); | ||
374 | } | ||
375 | |||
376 | @@ -XXX,XX +XXX,XX @@ store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val, | ||
377 | */ | ||
378 | if (unlikely(tlb_addr & TLB_WATCHPOINT)) { | ||
379 | cpu_check_watchpoint(env_cpu(env), addr, size - size2, | ||
380 | - env_tlb(env)->d[mmu_idx].iotlb[index].attrs, | ||
381 | + env_tlb(env)->d[mmu_idx].fulltlb[index].attrs, | ||
382 | BP_MEM_WRITE, retaddr); | ||
383 | } | ||
384 | if (unlikely(tlb_addr2 & TLB_WATCHPOINT)) { | ||
385 | cpu_check_watchpoint(env_cpu(env), page2, size2, | ||
386 | - env_tlb(env)->d[mmu_idx].iotlb[index2].attrs, | ||
387 | + env_tlb(env)->d[mmu_idx].fulltlb[index2].attrs, | ||
388 | BP_MEM_WRITE, retaddr); | ||
389 | } | ||
390 | |||
391 | @@ -XXX,XX +XXX,XX @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, | ||
392 | |||
393 | /* Handle anything that isn't just a straight memory access. */ | ||
394 | if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { | ||
395 | - CPUIOTLBEntry *iotlbentry; | ||
396 | + CPUTLBEntryFull *full; | ||
397 | bool need_swap; | ||
398 | |||
399 | /* For anything that is unaligned, recurse through byte stores. */ | ||
400 | @@ -XXX,XX +XXX,XX @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, | ||
401 | goto do_unaligned_access; | ||
402 | } | ||
403 | |||
404 | - iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index]; | ||
405 | + full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; | ||
406 | |||
407 | /* Handle watchpoints. */ | ||
408 | if (unlikely(tlb_addr & TLB_WATCHPOINT)) { | ||
409 | /* On watchpoint hit, this will longjmp out. */ | ||
410 | cpu_check_watchpoint(env_cpu(env), addr, size, | ||
411 | - iotlbentry->attrs, BP_MEM_WRITE, retaddr); | ||
412 | + full->attrs, BP_MEM_WRITE, retaddr); | ||
413 | } | ||
414 | |||
415 | need_swap = size > 1 && (tlb_addr & TLB_BSWAP); | ||
416 | |||
417 | /* Handle I/O access. */ | ||
418 | if (tlb_addr & TLB_MMIO) { | ||
419 | - io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, | ||
420 | + io_writex(env, full, mmu_idx, val, addr, retaddr, | ||
421 | op ^ (need_swap * MO_BSWAP)); | ||
422 | return; | ||
423 | } | ||
424 | @@ -XXX,XX +XXX,XX @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, | ||
425 | |||
426 | /* Handle clean RAM pages. */ | ||
427 | if (tlb_addr & TLB_NOTDIRTY) { | ||
428 | - notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr); | ||
429 | + notdirty_write(env_cpu(env), addr, size, full, retaddr); | ||
430 | } | ||
431 | |||
432 | haddr = (void *)((uintptr_t)addr + entry->addend); | ||
433 | diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c | ||
434 | index XXXXXXX..XXXXXXX 100644 | ||
435 | --- a/target/arm/mte_helper.c | ||
436 | +++ b/target/arm/mte_helper.c | ||
437 | @@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, | ||
438 | return tags + index; | ||
31 | #else | 439 | #else |
32 | ucontext_t *uc = puc; | 440 | uintptr_t index; |
441 | - CPUIOTLBEntry *iotlbentry; | ||
442 | + CPUTLBEntryFull *full; | ||
443 | int in_page, flags; | ||
444 | ram_addr_t ptr_ra; | ||
445 | hwaddr ptr_paddr, tag_paddr, xlat; | ||
446 | @@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, | ||
447 | assert(!(flags & TLB_INVALID_MASK)); | ||
448 | |||
449 | /* | ||
450 | - * Find the iotlbentry for ptr. This *must* be present in the TLB | ||
451 | + * Find the CPUTLBEntryFull for ptr. This *must* be present in the TLB | ||
452 | * because we just found the mapping. | ||
453 | * TODO: Perhaps there should be a cputlb helper that returns a | ||
454 | * matching tlb entry + iotlb entry. | ||
455 | @@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, | ||
456 | g_assert(tlb_hit(comparator, ptr)); | ||
457 | } | ||
458 | # endif | ||
459 | - iotlbentry = &env_tlb(env)->d[ptr_mmu_idx].iotlb[index]; | ||
460 | + full = &env_tlb(env)->d[ptr_mmu_idx].fulltlb[index]; | ||
461 | |||
462 | /* If the virtual page MemAttr != Tagged, access unchecked. */ | ||
463 | - if (!arm_tlb_mte_tagged(&iotlbentry->attrs)) { | ||
464 | + if (!arm_tlb_mte_tagged(&full->attrs)) { | ||
465 | return NULL; | ||
466 | } | ||
467 | |||
468 | @@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, | ||
469 | int wp = ptr_access == MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_WRITE; | ||
470 | assert(ra != 0); | ||
471 | cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, | ||
472 | - iotlbentry->attrs, wp, ra); | ||
473 | + full->attrs, wp, ra); | ||
474 | } | ||
475 | |||
476 | /* | ||
477 | @@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, | ||
478 | tag_paddr = ptr_paddr >> (LOG2_TAG_GRANULE + 1); | ||
479 | |||
480 | /* Look up the address in tag space. */ | ||
481 | - tag_asi = iotlbentry->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; | ||
482 | + tag_asi = full->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; | ||
483 | tag_as = cpu_get_address_space(env_cpu(env), tag_asi); | ||
484 | mr = address_space_translate(tag_as, tag_paddr, &xlat, NULL, | ||
485 | tag_access == MMU_DATA_STORE, | ||
486 | - iotlbentry->attrs); | ||
487 | + full->attrs); | ||
488 | |||
489 | /* | ||
490 | * Note that @mr will never be NULL. If there is nothing in the address | ||
491 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | ||
492 | index XXXXXXX..XXXXXXX 100644 | ||
493 | --- a/target/arm/sve_helper.c | ||
494 | +++ b/target/arm/sve_helper.c | ||
495 | @@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env, | ||
496 | g_assert(tlb_hit(comparator, addr)); | ||
497 | # endif | ||
498 | |||
499 | - CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index]; | ||
500 | - info->attrs = iotlbentry->attrs; | ||
501 | + CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; | ||
502 | + info->attrs = full->attrs; | ||
503 | } | ||
33 | #endif | 504 | #endif |
34 | unsigned long pc; | 505 | |
35 | + uint32_t fsr; | 506 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
36 | int is_write; | 507 | index XXXXXXX..XXXXXXX 100644 |
37 | 508 | --- a/target/arm/translate-a64.c | |
38 | #if defined(__NetBSD__) | 509 | +++ b/target/arm/translate-a64.c |
39 | @@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo, | 510 | @@ -XXX,XX +XXX,XX @@ static bool is_guarded_page(CPUARMState *env, DisasContext *s) |
40 | pc = uc->uc_mcontext.arm_pc; | 511 | * table entry even for that case. |
512 | */ | ||
513 | return (tlb_hit(entry->addr_code, addr) && | ||
514 | - arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].iotlb[index].attrs)); | ||
515 | + arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].fulltlb[index].attrs)); | ||
41 | #endif | 516 | #endif |
42 | 517 | } | |
43 | - /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or | ||
44 | - * later processor; on v5 we will always report this as a read). | ||
45 | +#ifdef __NetBSD__ | ||
46 | + fsr = si->si_trap; | ||
47 | +#else | ||
48 | + fsr = uc->uc_mcontext.error_code; | ||
49 | +#endif | ||
50 | + /* | ||
51 | + * In the FSR, bit 11 is WnR, assuming a v6 or | ||
52 | + * later processor. On v5 we will always report | ||
53 | + * this as a read, which will fail later. | ||
54 | */ | ||
55 | - is_write = extract32(uc->uc_mcontext.error_code, 11, 1); | ||
56 | + is_write = extract32(fsr, 11, 1); | ||
57 | return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); | ||
58 | } | ||
59 | 518 | ||
60 | -- | 519 | -- |
61 | 2.25.1 | 520 | 2.34.1 |
62 | 521 | ||
63 | 522 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | This field is only written, not read; remove it. | ||
1 | 2 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | --- | ||
8 | include/hw/core/cpu.h | 1 - | ||
9 | accel/tcg/cputlb.c | 7 +++---- | ||
10 | 2 files changed, 3 insertions(+), 5 deletions(-) | ||
11 | |||
12 | diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/include/hw/core/cpu.h | ||
15 | +++ b/include/hw/core/cpu.h | ||
16 | @@ -XXX,XX +XXX,XX @@ struct CPUWatchpoint { | ||
17 | * the memory regions get moved around by io_writex. | ||
18 | */ | ||
19 | typedef struct SavedIOTLB { | ||
20 | - hwaddr addr; | ||
21 | MemoryRegionSection *section; | ||
22 | hwaddr mr_offset; | ||
23 | } SavedIOTLB; | ||
24 | diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/accel/tcg/cputlb.c | ||
27 | +++ b/accel/tcg/cputlb.c | ||
28 | @@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full, | ||
29 | * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match | ||
30 | * because of the side effect of io_writex changing memory layout. | ||
31 | */ | ||
32 | -static void save_iotlb_data(CPUState *cs, hwaddr addr, | ||
33 | - MemoryRegionSection *section, hwaddr mr_offset) | ||
34 | +static void save_iotlb_data(CPUState *cs, MemoryRegionSection *section, | ||
35 | + hwaddr mr_offset) | ||
36 | { | ||
37 | #ifdef CONFIG_PLUGIN | ||
38 | SavedIOTLB *saved = &cs->saved_iotlb; | ||
39 | - saved->addr = addr; | ||
40 | saved->section = section; | ||
41 | saved->mr_offset = mr_offset; | ||
42 | #endif | ||
43 | @@ -XXX,XX +XXX,XX @@ static void io_writex(CPUArchState *env, CPUTLBEntryFull *full, | ||
44 | * The memory_region_dispatch may trigger a flush/resize | ||
45 | * so for plugins we save the iotlb_data just in case. | ||
46 | */ | ||
47 | - save_iotlb_data(cpu, full->xlat_section, section, mr_offset); | ||
48 | + save_iotlb_data(cpu, section, mr_offset); | ||
49 | |||
50 | if (!qemu_mutex_iothread_locked()) { | ||
51 | qemu_mutex_lock_iothread(); | ||
52 | -- | ||
53 | 2.34.1 | ||
54 | |||
55 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | When PAGE_WRITE_INV is set when calling tlb_set_page, | ||
2 | we immediately set TLB_INVALID_MASK in order to force | ||
3 | tlb_fill to be called on the next lookup. Here in | ||
4 | probe_access_internal, we have just called tlb_fill | ||
5 | and eliminated true misses, thus the lookup must be valid. | ||
1 | 6 | ||
7 | This allows us to remove a warning comment from s390x. | ||
8 | There doesn't seem to be a reason to change the code though. | ||
9 | |||
10 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
11 | Reviewed-by: David Hildenbrand <david@redhat.com> | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | --- | ||
15 | accel/tcg/cputlb.c | 10 +++++++++- | ||
16 | target/s390x/tcg/mem_helper.c | 4 ---- | ||
17 | 2 files changed, 9 insertions(+), 5 deletions(-) | ||
18 | |||
19 | diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/accel/tcg/cputlb.c | ||
22 | +++ b/accel/tcg/cputlb.c | ||
23 | @@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, | ||
24 | } | ||
25 | tlb_addr = tlb_read_ofs(entry, elt_ofs); | ||
26 | |||
27 | + flags = TLB_FLAGS_MASK; | ||
28 | page_addr = addr & TARGET_PAGE_MASK; | ||
29 | if (!tlb_hit_page(tlb_addr, page_addr)) { | ||
30 | if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) { | ||
31 | @@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, | ||
32 | |||
33 | /* TLB resize via tlb_fill may have moved the entry. */ | ||
34 | entry = tlb_entry(env, mmu_idx, addr); | ||
35 | + | ||
36 | + /* | ||
37 | + * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately, | ||
38 | + * to force the next access through tlb_fill. We've just | ||
39 | + * called tlb_fill, so we know that this entry *is* valid. | ||
40 | + */ | ||
41 | + flags &= ~TLB_INVALID_MASK; | ||
42 | } | ||
43 | tlb_addr = tlb_read_ofs(entry, elt_ofs); | ||
44 | } | ||
45 | - flags = tlb_addr & TLB_FLAGS_MASK; | ||
46 | + flags &= tlb_addr; | ||
47 | |||
48 | /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ | ||
49 | if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) { | ||
50 | diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c | ||
51 | index XXXXXXX..XXXXXXX 100644 | ||
52 | --- a/target/s390x/tcg/mem_helper.c | ||
53 | +++ b/target/s390x/tcg/mem_helper.c | ||
54 | @@ -XXX,XX +XXX,XX @@ static int s390_probe_access(CPUArchState *env, target_ulong addr, int size, | ||
55 | #else | ||
56 | int flags; | ||
57 | |||
58 | - /* | ||
59 | - * For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr==NULL | ||
60 | - * to detect if there was an exception during tlb_fill(). | ||
61 | - */ | ||
62 | env->tlb_fill_exc = 0; | ||
63 | flags = probe_access_flags(env, addr, access_type, mmu_idx, nonfault, phost, | ||
64 | ra); | ||
65 | -- | ||
66 | 2.34.1 | ||
67 | |||
68 | diff view generated by jsdifflib |
1 | For immediates, we must continue the special casing of 8-bit | 1 | Add an interface to return the CPUTLBEntryFull struct |
---|---|---|---|
2 | elements. The other element sizes and shift types are trivially | 2 | that goes with the lookup. The result is not intended |
3 | implemented with shifts. | 3 | to be valid across multiple lookups, so the user must |
4 | use the results immediately. | ||
4 | 5 | ||
6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | --- | 10 | --- |
7 | tcg/i386/tcg-target.inc.c | 116 ++++++++++++++++++++++++++++++++------ | 11 | include/exec/exec-all.h | 15 +++++++++++++ |
8 | 1 file changed, 100 insertions(+), 16 deletions(-) | 12 | include/qemu/typedefs.h | 1 + |
13 | accel/tcg/cputlb.c | 47 +++++++++++++++++++++++++---------------- | ||
14 | 3 files changed, 45 insertions(+), 18 deletions(-) | ||
9 | 15 | ||
10 | diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c | 16 | diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h |
11 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/tcg/i386/tcg-target.inc.c | 18 | --- a/include/exec/exec-all.h |
13 | +++ b/tcg/i386/tcg-target.inc.c | 19 | +++ b/include/exec/exec-all.h |
14 | @@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) | 20 | @@ -XXX,XX +XXX,XX @@ int probe_access_flags(CPUArchState *env, target_ulong addr, |
15 | case INDEX_op_shls_vec: | 21 | MMUAccessType access_type, int mmu_idx, |
16 | case INDEX_op_shrs_vec: | 22 | bool nonfault, void **phost, uintptr_t retaddr); |
17 | case INDEX_op_sars_vec: | 23 | |
18 | + case INDEX_op_rotls_vec: | 24 | +#ifndef CONFIG_USER_ONLY |
19 | case INDEX_op_cmp_vec: | 25 | +/** |
20 | case INDEX_op_x86_shufps_vec: | 26 | + * probe_access_full: |
21 | case INDEX_op_x86_blend_vec: | 27 | + * Like probe_access_flags, except also return into @pfull. |
22 | @@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) | 28 | + * |
23 | case INDEX_op_xor_vec: | 29 | + * The CPUTLBEntryFull structure returned via @pfull is transient |
24 | case INDEX_op_andc_vec: | 30 | + * and must be consumed or copied immediately, before any further |
25 | return 1; | 31 | + * access or changes to TLB @mmu_idx. |
26 | + case INDEX_op_rotli_vec: | 32 | + */ |
27 | case INDEX_op_cmp_vec: | 33 | +int probe_access_full(CPUArchState *env, target_ulong addr, |
28 | case INDEX_op_cmpsel_vec: | 34 | + MMUAccessType access_type, int mmu_idx, |
29 | return -1; | 35 | + bool nonfault, void **phost, |
30 | @@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) | 36 | + CPUTLBEntryFull **pfull, uintptr_t retaddr); |
31 | return vece >= MO_16; | 37 | +#endif |
32 | case INDEX_op_sars_vec: | 38 | + |
33 | return vece >= MO_16 && vece <= MO_32; | 39 | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
34 | + case INDEX_op_rotls_vec: | 40 | |
35 | + return vece >= MO_16 ? -1 : 0; | 41 | /* Estimated block size for TB allocation. */ |
36 | 42 | diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h | |
37 | case INDEX_op_shlv_vec: | 43 | index XXXXXXX..XXXXXXX 100644 |
38 | case INDEX_op_shrv_vec: | 44 | --- a/include/qemu/typedefs.h |
39 | return have_avx2 && vece >= MO_32; | 45 | +++ b/include/qemu/typedefs.h |
40 | case INDEX_op_sarv_vec: | 46 | @@ -XXX,XX +XXX,XX @@ typedef struct ConfidentialGuestSupport ConfidentialGuestSupport; |
41 | return have_avx2 && vece == MO_32; | 47 | typedef struct CPUAddressSpace CPUAddressSpace; |
42 | + case INDEX_op_rotlv_vec: | 48 | typedef struct CPUArchState CPUArchState; |
43 | + case INDEX_op_rotrv_vec: | 49 | typedef struct CPUState CPUState; |
44 | + return have_avx2 && vece >= MO_32 ? -1 : 0; | 50 | +typedef struct CPUTLBEntryFull CPUTLBEntryFull; |
45 | 51 | typedef struct DeviceListener DeviceListener; | |
46 | case INDEX_op_mul_vec: | 52 | typedef struct DeviceState DeviceState; |
47 | if (vece == MO_8) { | 53 | typedef struct DirtyBitmapSnapshot DirtyBitmapSnapshot; |
48 | @@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) | 54 | diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c |
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/accel/tcg/cputlb.c | ||
57 | +++ b/accel/tcg/cputlb.c | ||
58 | @@ -XXX,XX +XXX,XX @@ static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size, | ||
59 | static int probe_access_internal(CPUArchState *env, target_ulong addr, | ||
60 | int fault_size, MMUAccessType access_type, | ||
61 | int mmu_idx, bool nonfault, | ||
62 | - void **phost, uintptr_t retaddr) | ||
63 | + void **phost, CPUTLBEntryFull **pfull, | ||
64 | + uintptr_t retaddr) | ||
65 | { | ||
66 | uintptr_t index = tlb_index(env, mmu_idx, addr); | ||
67 | CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); | ||
68 | @@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, | ||
69 | mmu_idx, nonfault, retaddr)) { | ||
70 | /* Non-faulting page table read failed. */ | ||
71 | *phost = NULL; | ||
72 | + *pfull = NULL; | ||
73 | return TLB_INVALID_MASK; | ||
74 | } | ||
75 | |||
76 | /* TLB resize via tlb_fill may have moved the entry. */ | ||
77 | + index = tlb_index(env, mmu_idx, addr); | ||
78 | entry = tlb_entry(env, mmu_idx, addr); | ||
79 | |||
80 | /* | ||
81 | @@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, | ||
49 | } | 82 | } |
83 | flags &= tlb_addr; | ||
84 | |||
85 | + *pfull = &env_tlb(env)->d[mmu_idx].fulltlb[index]; | ||
86 | + | ||
87 | /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ | ||
88 | if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) { | ||
89 | *phost = NULL; | ||
90 | @@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, | ||
91 | return flags; | ||
50 | } | 92 | } |
51 | 93 | ||
52 | -static void expand_vec_shi(TCGType type, unsigned vece, bool shr, | 94 | -int probe_access_flags(CPUArchState *env, target_ulong addr, |
53 | +static void expand_vec_shi(TCGType type, unsigned vece, TCGOpcode opc, | 95 | - MMUAccessType access_type, int mmu_idx, |
54 | TCGv_vec v0, TCGv_vec v1, TCGArg imm) | 96 | - bool nonfault, void **phost, uintptr_t retaddr) |
97 | +int probe_access_full(CPUArchState *env, target_ulong addr, | ||
98 | + MMUAccessType access_type, int mmu_idx, | ||
99 | + bool nonfault, void **phost, CPUTLBEntryFull **pfull, | ||
100 | + uintptr_t retaddr) | ||
55 | { | 101 | { |
56 | TCGv_vec t1, t2; | 102 | - int flags; |
57 | @@ -XXX,XX +XXX,XX @@ static void expand_vec_shi(TCGType type, unsigned vece, bool shr, | 103 | - |
58 | t1 = tcg_temp_new_vec(type); | 104 | - flags = probe_access_internal(env, addr, 0, access_type, mmu_idx, |
59 | t2 = tcg_temp_new_vec(type); | 105 | - nonfault, phost, retaddr); |
60 | 106 | + int flags = probe_access_internal(env, addr, 0, access_type, mmu_idx, | |
61 | - /* Unpack to W, shift, and repack. Tricky bits: | 107 | + nonfault, phost, pfull, retaddr); |
62 | - (1) Use punpck*bw x,x to produce DDCCBBAA, | 108 | |
63 | - i.e. duplicate in other half of the 16-bit lane. | 109 | /* Handle clean RAM pages. */ |
64 | - (2) For right-shift, add 8 so that the high half of | 110 | if (unlikely(flags & TLB_NOTDIRTY)) { |
65 | - the lane becomes zero. For left-shift, we must | 111 | - uintptr_t index = tlb_index(env, mmu_idx, addr); |
66 | - shift up and down again. | 112 | - CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; |
67 | - (3) Step 2 leaves high half zero such that PACKUSWB | 113 | - |
68 | - (pack with unsigned saturation) does not modify | 114 | - notdirty_write(env_cpu(env), addr, 1, full, retaddr); |
69 | - the quantity. */ | 115 | + notdirty_write(env_cpu(env), addr, 1, *pfull, retaddr); |
70 | + /* | 116 | flags &= ~TLB_NOTDIRTY; |
71 | + * Unpack to W, shift, and repack. Tricky bits: | ||
72 | + * (1) Use punpck*bw x,x to produce DDCCBBAA, | ||
73 | + * i.e. duplicate in other half of the 16-bit lane. | ||
74 | + * (2) For right-shift, add 8 so that the high half of the lane | ||
75 | + * becomes zero. For left-shift, and left-rotate, we must | ||
76 | + * shift up and down again. | ||
77 | + * (3) Step 2 leaves high half zero such that PACKUSWB | ||
78 | + * (pack with unsigned saturation) does not modify | ||
79 | + * the quantity. | ||
80 | + */ | ||
81 | vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, | ||
82 | tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); | ||
83 | vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, | ||
84 | tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); | ||
85 | |||
86 | - if (shr) { | ||
87 | - tcg_gen_shri_vec(MO_16, t1, t1, imm + 8); | ||
88 | - tcg_gen_shri_vec(MO_16, t2, t2, imm + 8); | ||
89 | + if (opc != INDEX_op_rotli_vec) { | ||
90 | + imm += 8; | ||
91 | + } | ||
92 | + if (opc == INDEX_op_shri_vec) { | ||
93 | + tcg_gen_shri_vec(MO_16, t1, t1, imm); | ||
94 | + tcg_gen_shri_vec(MO_16, t2, t2, imm); | ||
95 | } else { | ||
96 | - tcg_gen_shli_vec(MO_16, t1, t1, imm + 8); | ||
97 | - tcg_gen_shli_vec(MO_16, t2, t2, imm + 8); | ||
98 | + tcg_gen_shli_vec(MO_16, t1, t1, imm); | ||
99 | + tcg_gen_shli_vec(MO_16, t2, t2, imm); | ||
100 | tcg_gen_shri_vec(MO_16, t1, t1, 8); | ||
101 | tcg_gen_shri_vec(MO_16, t2, t2, 8); | ||
102 | } | 117 | } |
103 | @@ -XXX,XX +XXX,XX @@ static void expand_vec_sari(TCGType type, unsigned vece, | 118 | |
104 | } | 119 | return flags; |
105 | } | 120 | } |
106 | 121 | ||
107 | +static void expand_vec_rotli(TCGType type, unsigned vece, | 122 | +int probe_access_flags(CPUArchState *env, target_ulong addr, |
108 | + TCGv_vec v0, TCGv_vec v1, TCGArg imm) | 123 | + MMUAccessType access_type, int mmu_idx, |
124 | + bool nonfault, void **phost, uintptr_t retaddr) | ||
109 | +{ | 125 | +{ |
110 | + TCGv_vec t; | 126 | + CPUTLBEntryFull *full; |
111 | + | 127 | + |
112 | + if (vece == MO_8) { | 128 | + return probe_access_full(env, addr, access_type, mmu_idx, |
113 | + expand_vec_shi(type, vece, INDEX_op_rotli_vec, v0, v1, imm); | 129 | + nonfault, phost, &full, retaddr); |
114 | + return; | ||
115 | + } | ||
116 | + | ||
117 | + t = tcg_temp_new_vec(type); | ||
118 | + tcg_gen_shli_vec(vece, t, v1, imm); | ||
119 | + tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm); | ||
120 | + tcg_gen_or_vec(vece, v0, v0, t); | ||
121 | + tcg_temp_free_vec(t); | ||
122 | +} | 130 | +} |
123 | + | 131 | + |
124 | +static void expand_vec_rotls(TCGType type, unsigned vece, | 132 | void *probe_access(CPUArchState *env, target_ulong addr, int size, |
125 | + TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh) | 133 | MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) |
126 | +{ | ||
127 | + TCGv_i32 rsh; | ||
128 | + TCGv_vec t; | ||
129 | + | ||
130 | + tcg_debug_assert(vece != MO_8); | ||
131 | + | ||
132 | + t = tcg_temp_new_vec(type); | ||
133 | + rsh = tcg_temp_new_i32(); | ||
134 | + | ||
135 | + tcg_gen_neg_i32(rsh, lsh); | ||
136 | + tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1); | ||
137 | + tcg_gen_shls_vec(vece, t, v1, lsh); | ||
138 | + tcg_gen_shrs_vec(vece, v0, v1, rsh); | ||
139 | + tcg_gen_or_vec(vece, v0, v0, t); | ||
140 | + tcg_temp_free_vec(t); | ||
141 | + tcg_temp_free_i32(rsh); | ||
142 | +} | ||
143 | + | ||
144 | +static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0, | ||
145 | + TCGv_vec v1, TCGv_vec sh, bool right) | ||
146 | +{ | ||
147 | + TCGv_vec t = tcg_temp_new_vec(type); | ||
148 | + | ||
149 | + tcg_gen_dupi_vec(vece, t, 8 << vece); | ||
150 | + tcg_gen_sub_vec(vece, t, t, sh); | ||
151 | + if (right) { | ||
152 | + tcg_gen_shlv_vec(vece, t, v1, t); | ||
153 | + tcg_gen_shrv_vec(vece, v0, v1, sh); | ||
154 | + } else { | ||
155 | + tcg_gen_shrv_vec(vece, t, v1, t); | ||
156 | + tcg_gen_shlv_vec(vece, v0, v1, sh); | ||
157 | + } | ||
158 | + tcg_gen_or_vec(vece, v0, v0, t); | ||
159 | + tcg_temp_free_vec(t); | ||
160 | +} | ||
161 | + | ||
162 | static void expand_vec_mul(TCGType type, unsigned vece, | ||
163 | TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) | ||
164 | { | 134 | { |
165 | @@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, | 135 | + CPUTLBEntryFull *full; |
166 | switch (opc) { | 136 | void *host; |
167 | case INDEX_op_shli_vec: | 137 | int flags; |
168 | case INDEX_op_shri_vec: | 138 | |
169 | - expand_vec_shi(type, vece, opc == INDEX_op_shri_vec, v0, v1, a2); | 139 | g_assert(-(addr | TARGET_PAGE_MASK) >= size); |
170 | + expand_vec_shi(type, vece, opc, v0, v1, a2); | 140 | |
171 | break; | 141 | flags = probe_access_internal(env, addr, size, access_type, mmu_idx, |
172 | 142 | - false, &host, retaddr); | |
173 | case INDEX_op_sari_vec: | 143 | + false, &host, &full, retaddr); |
174 | expand_vec_sari(type, vece, v0, v1, a2); | 144 | |
175 | break; | 145 | /* Per the interface, size == 0 merely faults the access. */ |
176 | 146 | if (size == 0) { | |
177 | + case INDEX_op_rotli_vec: | 147 | @@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, |
178 | + expand_vec_rotli(type, vece, v0, v1, a2); | 148 | } |
179 | + break; | 149 | |
180 | + | 150 | if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) { |
181 | + case INDEX_op_rotls_vec: | 151 | - uintptr_t index = tlb_index(env, mmu_idx, addr); |
182 | + expand_vec_rotls(type, vece, v0, v1, temp_tcgv_i32(arg_temp(a2))); | 152 | - CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; |
183 | + break; | 153 | - |
184 | + | 154 | /* Handle watchpoints. */ |
185 | + case INDEX_op_rotlv_vec: | 155 | if (flags & TLB_WATCHPOINT) { |
186 | + v2 = temp_tcgv_vec(arg_temp(a2)); | 156 | int wp_access = (access_type == MMU_DATA_STORE |
187 | + expand_vec_rotv(type, vece, v0, v1, v2, false); | 157 | @@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, |
188 | + break; | 158 | void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, |
189 | + case INDEX_op_rotrv_vec: | 159 | MMUAccessType access_type, int mmu_idx) |
190 | + v2 = temp_tcgv_vec(arg_temp(a2)); | 160 | { |
191 | + expand_vec_rotv(type, vece, v0, v1, v2, true); | 161 | + CPUTLBEntryFull *full; |
192 | + break; | 162 | void *host; |
193 | + | 163 | int flags; |
194 | case INDEX_op_mul_vec: | 164 | |
195 | v2 = temp_tcgv_vec(arg_temp(a2)); | 165 | flags = probe_access_internal(env, addr, 0, access_type, |
196 | expand_vec_mul(type, vece, v0, v1, v2); | 166 | - mmu_idx, true, &host, 0); |
167 | + mmu_idx, true, &host, &full, 0); | ||
168 | |||
169 | /* No combination of flags are expected by the caller. */ | ||
170 | return flags ? NULL : host; | ||
171 | @@ -XXX,XX +XXX,XX @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, | ||
172 | tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr, | ||
173 | void **hostp) | ||
174 | { | ||
175 | + CPUTLBEntryFull *full; | ||
176 | void *p; | ||
177 | |||
178 | (void)probe_access_internal(env, addr, 1, MMU_INST_FETCH, | ||
179 | - cpu_mmu_index(env, true), false, &p, 0); | ||
180 | + cpu_mmu_index(env, true), false, &p, &full, 0); | ||
181 | if (p == NULL) { | ||
182 | return -1; | ||
183 | } | ||
197 | -- | 184 | -- |
198 | 2.25.1 | 185 | 2.34.1 |
199 | 186 | ||
200 | 187 | diff view generated by jsdifflib |
1 | No host backend support yet, but the interfaces for rotls | 1 | Now that we have collected all of the page data into |
---|---|---|---|
2 | are in place. Only implement left-rotate for now, as the | 2 | CPUTLBEntryFull, provide an interface to record that |
3 | only known use of vector rotate by scalar is s390x, so any | 3 | all in one go, instead of using 4 arguments. This interface |
4 | right-rotate would be unused and untestable. | 4 | allows CPUTLBEntryFull to be extended without having to |
5 | change the number of arguments. | ||
5 | 6 | ||
6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | --- | 11 | --- |
9 | include/tcg/tcg-op-gvec.h | 2 ++ | 12 | include/exec/cpu-defs.h | 14 +++++++++++ |
10 | include/tcg/tcg-op.h | 1 + | 13 | include/exec/exec-all.h | 22 ++++++++++++++++++ |
11 | include/tcg/tcg-opc.h | 1 + | 14 | accel/tcg/cputlb.c | 51 ++++++++++++++++++++++++++--------------- |
12 | include/tcg/tcg.h | 1 + | 15 | 3 files changed, 69 insertions(+), 18 deletions(-) |
13 | tcg/aarch64/tcg-target.h | 1 + | ||
14 | tcg/i386/tcg-target.h | 1 + | ||
15 | tcg/ppc/tcg-target.h | 1 + | ||
16 | tcg/tcg-op-gvec.c | 22 ++++++++++++++++++++++ | ||
17 | tcg/tcg-op-vec.c | 5 +++++ | ||
18 | tcg/tcg.c | 2 ++ | ||
19 | 10 files changed, 37 insertions(+) | ||
20 | 16 | ||
21 | diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h | 17 | diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h |
22 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/include/tcg/tcg-op-gvec.h | 19 | --- a/include/exec/cpu-defs.h |
24 | +++ b/include/tcg/tcg-op-gvec.h | 20 | +++ b/include/exec/cpu-defs.h |
25 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs, | 21 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntryFull { |
26 | TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); | 22 | * + the offset within the target MemoryRegion (otherwise) |
27 | void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, | 23 | */ |
28 | TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); | 24 | hwaddr xlat_section; |
29 | +void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, | 25 | + |
30 | + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); | 26 | + /* |
27 | + * @phys_addr contains the physical address in the address space | ||
28 | + * given by cpu_asidx_from_attrs(cpu, @attrs). | ||
29 | + */ | ||
30 | + hwaddr phys_addr; | ||
31 | + | ||
32 | + /* @attrs contains the memory transaction attributes for the page. */ | ||
33 | MemTxAttrs attrs; | ||
34 | + | ||
35 | + /* @prot contains the complete protections for the page. */ | ||
36 | + uint8_t prot; | ||
37 | + | ||
38 | + /* @lg_page_size contains the log2 of the page size. */ | ||
39 | + uint8_t lg_page_size; | ||
40 | } CPUTLBEntryFull; | ||
31 | 41 | ||
32 | /* | 42 | /* |
33 | * Perform vector shift by vector element, modulo the element size. | 43 | diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h |
34 | diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h | ||
35 | index XXXXXXX..XXXXXXX 100644 | 44 | index XXXXXXX..XXXXXXX 100644 |
36 | --- a/include/tcg/tcg-op.h | 45 | --- a/include/exec/exec-all.h |
37 | +++ b/include/tcg/tcg-op.h | 46 | +++ b/include/exec/exec-all.h |
38 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); | 47 | @@ -XXX,XX +XXX,XX @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, |
39 | void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); | 48 | uint16_t idxmap, |
40 | void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); | 49 | unsigned bits); |
41 | void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); | 50 | |
42 | +void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); | 51 | +/** |
43 | 52 | + * tlb_set_page_full: | |
44 | void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); | 53 | + * @cpu: CPU context |
45 | void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); | 54 | + * @mmu_idx: mmu index of the tlb to modify |
46 | diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h | 55 | + * @vaddr: virtual address of the entry to add |
56 | + * @full: the details of the tlb entry | ||
57 | + * | ||
58 | + * Add an entry to @cpu tlb index @mmu_idx. All of the fields of | ||
59 | + * @full must be filled, except for xlat_section, and constitute | ||
60 | + * the complete description of the translated page. | ||
61 | + * | ||
62 | + * This is generally called by the target tlb_fill function after | ||
63 | + * having performed a successful page table walk to find the physical | ||
64 | + * address and attributes for the translation. | ||
65 | + * | ||
66 | + * At most one entry for a given virtual address is permitted. Only a | ||
67 | + * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only | ||
68 | + * used by tlb_flush_page. | ||
69 | + */ | ||
70 | +void tlb_set_page_full(CPUState *cpu, int mmu_idx, target_ulong vaddr, | ||
71 | + CPUTLBEntryFull *full); | ||
72 | + | ||
73 | /** | ||
74 | * tlb_set_page_with_attrs: | ||
75 | * @cpu: CPU to add this TLB entry for | ||
76 | diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | 77 | index XXXXXXX..XXXXXXX 100644 |
48 | --- a/include/tcg/tcg-opc.h | 78 | --- a/accel/tcg/cputlb.c |
49 | +++ b/include/tcg/tcg-opc.h | 79 | +++ b/accel/tcg/cputlb.c |
50 | @@ -XXX,XX +XXX,XX @@ DEF(rotli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_roti_vec)) | 80 | @@ -XXX,XX +XXX,XX @@ static void tlb_add_large_page(CPUArchState *env, int mmu_idx, |
51 | DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) | 81 | env_tlb(env)->d[mmu_idx].large_page_mask = lp_mask; |
52 | DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) | ||
53 | DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) | ||
54 | +DEF(rotls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rots_vec)) | ||
55 | |||
56 | DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) | ||
57 | DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) | ||
58 | diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/include/tcg/tcg.h | ||
61 | +++ b/include/tcg/tcg.h | ||
62 | @@ -XXX,XX +XXX,XX @@ typedef uint64_t TCGRegSet; | ||
63 | #define TCG_TARGET_HAS_andc_vec 0 | ||
64 | #define TCG_TARGET_HAS_orc_vec 0 | ||
65 | #define TCG_TARGET_HAS_roti_vec 0 | ||
66 | +#define TCG_TARGET_HAS_rots_vec 0 | ||
67 | #define TCG_TARGET_HAS_rotv_vec 0 | ||
68 | #define TCG_TARGET_HAS_shi_vec 0 | ||
69 | #define TCG_TARGET_HAS_shs_vec 0 | ||
70 | diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h | ||
71 | index XXXXXXX..XXXXXXX 100644 | ||
72 | --- a/tcg/aarch64/tcg-target.h | ||
73 | +++ b/tcg/aarch64/tcg-target.h | ||
74 | @@ -XXX,XX +XXX,XX @@ typedef enum { | ||
75 | #define TCG_TARGET_HAS_neg_vec 1 | ||
76 | #define TCG_TARGET_HAS_abs_vec 1 | ||
77 | #define TCG_TARGET_HAS_roti_vec 0 | ||
78 | +#define TCG_TARGET_HAS_rots_vec 0 | ||
79 | #define TCG_TARGET_HAS_rotv_vec 0 | ||
80 | #define TCG_TARGET_HAS_shi_vec 1 | ||
81 | #define TCG_TARGET_HAS_shs_vec 0 | ||
82 | diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h | ||
83 | index XXXXXXX..XXXXXXX 100644 | ||
84 | --- a/tcg/i386/tcg-target.h | ||
85 | +++ b/tcg/i386/tcg-target.h | ||
86 | @@ -XXX,XX +XXX,XX @@ extern bool have_avx2; | ||
87 | #define TCG_TARGET_HAS_neg_vec 0 | ||
88 | #define TCG_TARGET_HAS_abs_vec 1 | ||
89 | #define TCG_TARGET_HAS_roti_vec 0 | ||
90 | +#define TCG_TARGET_HAS_rots_vec 0 | ||
91 | #define TCG_TARGET_HAS_rotv_vec 0 | ||
92 | #define TCG_TARGET_HAS_shi_vec 1 | ||
93 | #define TCG_TARGET_HAS_shs_vec 1 | ||
94 | diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h | ||
95 | index XXXXXXX..XXXXXXX 100644 | ||
96 | --- a/tcg/ppc/tcg-target.h | ||
97 | +++ b/tcg/ppc/tcg-target.h | ||
98 | @@ -XXX,XX +XXX,XX @@ extern bool have_vsx; | ||
99 | #define TCG_TARGET_HAS_neg_vec have_isa_3_00 | ||
100 | #define TCG_TARGET_HAS_abs_vec 0 | ||
101 | #define TCG_TARGET_HAS_roti_vec 0 | ||
102 | +#define TCG_TARGET_HAS_rots_vec 0 | ||
103 | #define TCG_TARGET_HAS_rotv_vec 0 | ||
104 | #define TCG_TARGET_HAS_shi_vec 0 | ||
105 | #define TCG_TARGET_HAS_shs_vec 0 | ||
106 | diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c | ||
107 | index XXXXXXX..XXXXXXX 100644 | ||
108 | --- a/tcg/tcg-op-gvec.c | ||
109 | +++ b/tcg/tcg-op-gvec.c | ||
110 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
111 | do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); | ||
112 | } | 82 | } |
113 | 83 | ||
114 | +void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, | 84 | -/* Add a new TLB entry. At most one entry for a given virtual address |
115 | + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) | 85 | +/* |
86 | + * Add a new TLB entry. At most one entry for a given virtual address | ||
87 | * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the | ||
88 | * supplied size is only used by tlb_flush_page. | ||
89 | * | ||
90 | * Called from TCG-generated code, which is under an RCU read-side | ||
91 | * critical section. | ||
92 | */ | ||
93 | -void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, | ||
94 | - hwaddr paddr, MemTxAttrs attrs, int prot, | ||
95 | - int mmu_idx, target_ulong size) | ||
96 | +void tlb_set_page_full(CPUState *cpu, int mmu_idx, | ||
97 | + target_ulong vaddr, CPUTLBEntryFull *full) | ||
98 | { | ||
99 | CPUArchState *env = cpu->env_ptr; | ||
100 | CPUTLB *tlb = env_tlb(env); | ||
101 | @@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, | ||
102 | CPUTLBEntry *te, tn; | ||
103 | hwaddr iotlb, xlat, sz, paddr_page; | ||
104 | target_ulong vaddr_page; | ||
105 | - int asidx = cpu_asidx_from_attrs(cpu, attrs); | ||
106 | - int wp_flags; | ||
107 | + int asidx, wp_flags, prot; | ||
108 | bool is_ram, is_romd; | ||
109 | |||
110 | assert_cpu_is_self(cpu); | ||
111 | |||
112 | - if (size <= TARGET_PAGE_SIZE) { | ||
113 | + if (full->lg_page_size <= TARGET_PAGE_BITS) { | ||
114 | sz = TARGET_PAGE_SIZE; | ||
115 | } else { | ||
116 | - tlb_add_large_page(env, mmu_idx, vaddr, size); | ||
117 | - sz = size; | ||
118 | + sz = (hwaddr)1 << full->lg_page_size; | ||
119 | + tlb_add_large_page(env, mmu_idx, vaddr, sz); | ||
120 | } | ||
121 | vaddr_page = vaddr & TARGET_PAGE_MASK; | ||
122 | - paddr_page = paddr & TARGET_PAGE_MASK; | ||
123 | + paddr_page = full->phys_addr & TARGET_PAGE_MASK; | ||
124 | |||
125 | + prot = full->prot; | ||
126 | + asidx = cpu_asidx_from_attrs(cpu, full->attrs); | ||
127 | section = address_space_translate_for_iotlb(cpu, asidx, paddr_page, | ||
128 | - &xlat, &sz, attrs, &prot); | ||
129 | + &xlat, &sz, full->attrs, &prot); | ||
130 | assert(sz >= TARGET_PAGE_SIZE); | ||
131 | |||
132 | tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx | ||
133 | " prot=%x idx=%d\n", | ||
134 | - vaddr, paddr, prot, mmu_idx); | ||
135 | + vaddr, full->phys_addr, prot, mmu_idx); | ||
136 | |||
137 | address = vaddr_page; | ||
138 | - if (size < TARGET_PAGE_SIZE) { | ||
139 | + if (full->lg_page_size < TARGET_PAGE_BITS) { | ||
140 | /* Repeat the MMU check and TLB fill on every access. */ | ||
141 | address |= TLB_INVALID_MASK; | ||
142 | } | ||
143 | - if (attrs.byte_swap) { | ||
144 | + if (full->attrs.byte_swap) { | ||
145 | address |= TLB_BSWAP; | ||
146 | } | ||
147 | |||
148 | @@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, | ||
149 | * subtract here is that of the page base, and not the same as the | ||
150 | * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). | ||
151 | */ | ||
152 | + desc->fulltlb[index] = *full; | ||
153 | desc->fulltlb[index].xlat_section = iotlb - vaddr_page; | ||
154 | - desc->fulltlb[index].attrs = attrs; | ||
155 | + desc->fulltlb[index].phys_addr = paddr_page; | ||
156 | + desc->fulltlb[index].prot = prot; | ||
157 | |||
158 | /* Now calculate the new entry */ | ||
159 | tn.addend = addend - vaddr_page; | ||
160 | @@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, | ||
161 | qemu_spin_unlock(&tlb->c.lock); | ||
162 | } | ||
163 | |||
164 | -/* Add a new TLB entry, but without specifying the memory | ||
165 | - * transaction attributes to be used. | ||
166 | - */ | ||
167 | +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, | ||
168 | + hwaddr paddr, MemTxAttrs attrs, int prot, | ||
169 | + int mmu_idx, target_ulong size) | ||
116 | +{ | 170 | +{ |
117 | + static const GVecGen2sh g = { | 171 | + CPUTLBEntryFull full = { |
118 | + .fni4 = tcg_gen_rotl_i32, | 172 | + .phys_addr = paddr, |
119 | + .fni8 = tcg_gen_rotl_i64, | 173 | + .attrs = attrs, |
120 | + .fniv_s = tcg_gen_rotls_vec, | 174 | + .prot = prot, |
121 | + .fniv_v = tcg_gen_rotlv_vec, | 175 | + .lg_page_size = ctz64(size) |
122 | + .fno = { | ||
123 | + gen_helper_gvec_rotl8i, | ||
124 | + gen_helper_gvec_rotl16i, | ||
125 | + gen_helper_gvec_rotl32i, | ||
126 | + gen_helper_gvec_rotl64i, | ||
127 | + }, | ||
128 | + .s_list = { INDEX_op_rotls_vec, 0 }, | ||
129 | + .v_list = { INDEX_op_rotlv_vec, 0 }, | ||
130 | + }; | 176 | + }; |
131 | + | 177 | + |
132 | + tcg_debug_assert(vece <= MO_64); | 178 | + assert(is_power_of_2(size)); |
133 | + do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); | 179 | + tlb_set_page_full(cpu, mmu_idx, vaddr, &full); |
134 | +} | 180 | +} |
135 | + | 181 | + |
136 | /* | 182 | void tlb_set_page(CPUState *cpu, target_ulong vaddr, |
137 | * Expand D = A << (B % element bits) | 183 | hwaddr paddr, int prot, |
138 | * | 184 | int mmu_idx, target_ulong size) |
139 | diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c | ||
140 | index XXXXXXX..XXXXXXX 100644 | ||
141 | --- a/tcg/tcg-op-vec.c | ||
142 | +++ b/tcg/tcg-op-vec.c | ||
143 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) | ||
144 | do_shifts(vece, r, a, b, INDEX_op_sars_vec); | ||
145 | } | ||
146 | |||
147 | +void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s) | ||
148 | +{ | ||
149 | + do_shifts(vece, r, a, s, INDEX_op_rotls_vec); | ||
150 | +} | ||
151 | + | ||
152 | void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, | ||
153 | TCGv_vec b, TCGv_vec c) | ||
154 | { | ||
155 | diff --git a/tcg/tcg.c b/tcg/tcg.c | ||
156 | index XXXXXXX..XXXXXXX 100644 | ||
157 | --- a/tcg/tcg.c | ||
158 | +++ b/tcg/tcg.c | ||
159 | @@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op) | ||
160 | return have_vec && TCG_TARGET_HAS_shv_vec; | ||
161 | case INDEX_op_rotli_vec: | ||
162 | return have_vec && TCG_TARGET_HAS_roti_vec; | ||
163 | + case INDEX_op_rotls_vec: | ||
164 | + return have_vec && TCG_TARGET_HAS_rots_vec; | ||
165 | case INDEX_op_rotlv_vec: | ||
166 | case INDEX_op_rotrv_vec: | ||
167 | return have_vec && TCG_TARGET_HAS_rotv_vec; | ||
168 | -- | 185 | -- |
169 | 2.25.1 | 186 | 2.34.1 |
170 | 187 | ||
171 | 188 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Allow the target to cache items from the guest page tables. | ||
1 | 2 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | --- | ||
8 | include/exec/cpu-defs.h | 9 +++++++++ | ||
9 | 1 file changed, 9 insertions(+) | ||
10 | |||
11 | diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/include/exec/cpu-defs.h | ||
14 | +++ b/include/exec/cpu-defs.h | ||
15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntryFull { | ||
16 | |||
17 | /* @lg_page_size contains the log2 of the page size. */ | ||
18 | uint8_t lg_page_size; | ||
19 | + | ||
20 | + /* | ||
21 | + * Allow target-specific additions to this structure. | ||
22 | + * This may be used to cache items from the guest cpu | ||
23 | + * page tables for later use by the implementation. | ||
24 | + */ | ||
25 | +#ifdef TARGET_PAGE_ENTRY_EXTRA | ||
26 | + TARGET_PAGE_ENTRY_EXTRA | ||
27 | +#endif | ||
28 | } CPUTLBEntryFull; | ||
29 | |||
30 | /* | ||
31 | -- | ||
32 | 2.34.1 | ||
33 | |||
34 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | This bitmap is created and discarded immediately. | ||
2 | We gain nothing by its existence. | ||
1 | 3 | ||
4 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-Id: <20220822232338.1727934-2-richard.henderson@linaro.org> | ||
7 | --- | ||
8 | accel/tcg/translate-all.c | 78 ++------------------------------------- | ||
9 | 1 file changed, 4 insertions(+), 74 deletions(-) | ||
10 | |||
11 | diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/accel/tcg/translate-all.c | ||
14 | +++ b/accel/tcg/translate-all.c | ||
15 | @@ -XXX,XX +XXX,XX @@ | ||
16 | #define assert_memory_lock() tcg_debug_assert(have_mmap_lock()) | ||
17 | #endif | ||
18 | |||
19 | -#define SMC_BITMAP_USE_THRESHOLD 10 | ||
20 | - | ||
21 | typedef struct PageDesc { | ||
22 | /* list of TBs intersecting this ram page */ | ||
23 | uintptr_t first_tb; | ||
24 | -#ifdef CONFIG_SOFTMMU | ||
25 | - /* in order to optimize self modifying code, we count the number | ||
26 | - of lookups we do to a given page to use a bitmap */ | ||
27 | - unsigned long *code_bitmap; | ||
28 | - unsigned int code_write_count; | ||
29 | -#else | ||
30 | +#ifdef CONFIG_USER_ONLY | ||
31 | unsigned long flags; | ||
32 | void *target_data; | ||
33 | #endif | ||
34 | -#ifndef CONFIG_USER_ONLY | ||
35 | +#ifdef CONFIG_SOFTMMU | ||
36 | QemuSpin lock; | ||
37 | #endif | ||
38 | } PageDesc; | ||
39 | @@ -XXX,XX +XXX,XX @@ void tb_htable_init(void) | ||
40 | qht_init(&tb_ctx.htable, tb_cmp, CODE_GEN_HTABLE_SIZE, mode); | ||
41 | } | ||
42 | |||
43 | -/* call with @p->lock held */ | ||
44 | -static inline void invalidate_page_bitmap(PageDesc *p) | ||
45 | -{ | ||
46 | - assert_page_locked(p); | ||
47 | -#ifdef CONFIG_SOFTMMU | ||
48 | - g_free(p->code_bitmap); | ||
49 | - p->code_bitmap = NULL; | ||
50 | - p->code_write_count = 0; | ||
51 | -#endif | ||
52 | -} | ||
53 | - | ||
54 | /* Set to NULL all the 'first_tb' fields in all PageDescs. */ | ||
55 | static void page_flush_tb_1(int level, void **lp) | ||
56 | { | ||
57 | @@ -XXX,XX +XXX,XX @@ static void page_flush_tb_1(int level, void **lp) | ||
58 | for (i = 0; i < V_L2_SIZE; ++i) { | ||
59 | page_lock(&pd[i]); | ||
60 | pd[i].first_tb = (uintptr_t)NULL; | ||
61 | - invalidate_page_bitmap(pd + i); | ||
62 | page_unlock(&pd[i]); | ||
63 | } | ||
64 | } else { | ||
65 | @@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) | ||
66 | if (rm_from_page_list) { | ||
67 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); | ||
68 | tb_page_remove(p, tb); | ||
69 | - invalidate_page_bitmap(p); | ||
70 | if (tb->page_addr[1] != -1) { | ||
71 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); | ||
72 | tb_page_remove(p, tb); | ||
73 | - invalidate_page_bitmap(p); | ||
74 | } | ||
75 | } | ||
76 | |||
77 | @@ -XXX,XX +XXX,XX @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) | ||
78 | } | ||
79 | } | ||
80 | |||
81 | -#ifdef CONFIG_SOFTMMU | ||
82 | -/* call with @p->lock held */ | ||
83 | -static void build_page_bitmap(PageDesc *p) | ||
84 | -{ | ||
85 | - int n, tb_start, tb_end; | ||
86 | - TranslationBlock *tb; | ||
87 | - | ||
88 | - assert_page_locked(p); | ||
89 | - p->code_bitmap = bitmap_new(TARGET_PAGE_SIZE); | ||
90 | - | ||
91 | - PAGE_FOR_EACH_TB(p, tb, n) { | ||
92 | - /* NOTE: this is subtle as a TB may span two physical pages */ | ||
93 | - if (n == 0) { | ||
94 | - /* NOTE: tb_end may be after the end of the page, but | ||
95 | - it is not a problem */ | ||
96 | - tb_start = tb->pc & ~TARGET_PAGE_MASK; | ||
97 | - tb_end = tb_start + tb->size; | ||
98 | - if (tb_end > TARGET_PAGE_SIZE) { | ||
99 | - tb_end = TARGET_PAGE_SIZE; | ||
100 | - } | ||
101 | - } else { | ||
102 | - tb_start = 0; | ||
103 | - tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | ||
104 | - } | ||
105 | - bitmap_set(p->code_bitmap, tb_start, tb_end - tb_start); | ||
106 | - } | ||
107 | -} | ||
108 | -#endif | ||
109 | - | ||
110 | /* add the tb in the target page and protect it if necessary | ||
111 | * | ||
112 | * Called with mmap_lock held for user-mode emulation. | ||
113 | @@ -XXX,XX +XXX,XX @@ static inline void tb_page_add(PageDesc *p, TranslationBlock *tb, | ||
114 | page_already_protected = p->first_tb != (uintptr_t)NULL; | ||
115 | #endif | ||
116 | p->first_tb = (uintptr_t)tb | n; | ||
117 | - invalidate_page_bitmap(p); | ||
118 | |||
119 | #if defined(CONFIG_USER_ONLY) | ||
120 | /* translator_loop() must have made all TB pages non-writable */ | ||
121 | @@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, | ||
122 | /* remove TB from the page(s) if we couldn't insert it */ | ||
123 | if (unlikely(existing_tb)) { | ||
124 | tb_page_remove(p, tb); | ||
125 | - invalidate_page_bitmap(p); | ||
126 | if (p2) { | ||
127 | tb_page_remove(p2, tb); | ||
128 | - invalidate_page_bitmap(p2); | ||
129 | } | ||
130 | tb = existing_tb; | ||
131 | } | ||
132 | @@ -XXX,XX +XXX,XX @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages, | ||
133 | #if !defined(CONFIG_USER_ONLY) | ||
134 | /* if no code remaining, no need to continue to use slow writes */ | ||
135 | if (!p->first_tb) { | ||
136 | - invalidate_page_bitmap(p); | ||
137 | tlb_unprotect_code(start); | ||
138 | } | ||
139 | #endif | ||
140 | @@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_page_fast(struct page_collection *pages, | ||
141 | } | ||
142 | |||
143 | assert_page_locked(p); | ||
144 | - if (!p->code_bitmap && | ||
145 | - ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD) { | ||
146 | - build_page_bitmap(p); | ||
147 | - } | ||
148 | - if (p->code_bitmap) { | ||
149 | - unsigned int nr; | ||
150 | - unsigned long b; | ||
151 | - | ||
152 | - nr = start & ~TARGET_PAGE_MASK; | ||
153 | - b = p->code_bitmap[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG - 1)); | ||
154 | - if (b & ((1 << len) - 1)) { | ||
155 | - goto do_invalidate; | ||
156 | - } | ||
157 | - } else { | ||
158 | - do_invalidate: | ||
159 | - tb_invalidate_phys_page_range__locked(pages, p, start, start + len, | ||
160 | - retaddr); | ||
161 | - } | ||
162 | + tb_invalidate_phys_page_range__locked(pages, p, start, start + len, | ||
163 | + retaddr); | ||
164 | } | ||
165 | #else | ||
166 | /* Called with mmap_lock held. If pc is not 0 then it indicates the | ||
167 | -- | ||
168 | 2.34.1 | ||
169 | |||
170 | diff view generated by jsdifflib |
1 | We do not reflect this expansion in tcg_can_emit_vecop_list, | 1 | Bool is more appropriate type for the alloc parameter. |
---|---|---|---|
2 | so it is unused and unusable. However, we actually perform | ||
3 | the same expansion in do_gvec_shifts, so it is also unneeded. | ||
4 | 2 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | --- | 6 | --- |
7 | tcg/tcg-op-vec.c | 35 +++++++++++------------------------ | 7 | accel/tcg/translate-all.c | 14 +++++++------- |
8 | 1 file changed, 11 insertions(+), 24 deletions(-) | 8 | 1 file changed, 7 insertions(+), 7 deletions(-) |
9 | 9 | ||
10 | diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c | 10 | diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c |
11 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/tcg/tcg-op-vec.c | 12 | --- a/accel/tcg/translate-all.c |
13 | +++ b/tcg/tcg-op-vec.c | 13 | +++ b/accel/tcg/translate-all.c |
14 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) | 14 | @@ -XXX,XX +XXX,XX @@ void page_init(void) |
15 | #endif | ||
15 | } | 16 | } |
16 | 17 | ||
17 | static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a, | 18 | -static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) |
18 | - TCGv_i32 s, TCGOpcode opc_s, TCGOpcode opc_v) | 19 | +static PageDesc *page_find_alloc(tb_page_addr_t index, bool alloc) |
19 | + TCGv_i32 s, TCGOpcode opc) | ||
20 | { | 20 | { |
21 | TCGTemp *rt = tcgv_vec_temp(r); | 21 | PageDesc *pd; |
22 | TCGTemp *at = tcgv_vec_temp(a); | 22 | void **lp; |
23 | @@ -XXX,XX +XXX,XX @@ static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a, | 23 | @@ -XXX,XX +XXX,XX @@ static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) |
24 | TCGArg ai = temp_arg(at); | 24 | |
25 | TCGArg si = temp_arg(st); | 25 | static inline PageDesc *page_find(tb_page_addr_t index) |
26 | TCGType type = rt->base_type; | 26 | { |
27 | - const TCGOpcode *hold_list; | 27 | - return page_find_alloc(index, 0); |
28 | int can; | 28 | + return page_find_alloc(index, false); |
29 | |||
30 | tcg_debug_assert(at->base_type >= type); | ||
31 | - tcg_assert_listed_vecop(opc_s); | ||
32 | - hold_list = tcg_swap_vecop_list(NULL); | ||
33 | - | ||
34 | - can = tcg_can_emit_vec_op(opc_s, type, vece); | ||
35 | + tcg_assert_listed_vecop(opc); | ||
36 | + can = tcg_can_emit_vec_op(opc, type, vece); | ||
37 | if (can > 0) { | ||
38 | - vec_gen_3(opc_s, type, vece, ri, ai, si); | ||
39 | + vec_gen_3(opc, type, vece, ri, ai, si); | ||
40 | } else if (can < 0) { | ||
41 | - tcg_expand_vec_op(opc_s, type, vece, ri, ai, si); | ||
42 | + const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); | ||
43 | + tcg_expand_vec_op(opc, type, vece, ri, ai, si); | ||
44 | + tcg_swap_vecop_list(hold_list); | ||
45 | } else { | ||
46 | - TCGv_vec vec_s = tcg_temp_new_vec(type); | ||
47 | - | ||
48 | - if (vece == MO_64) { | ||
49 | - TCGv_i64 s64 = tcg_temp_new_i64(); | ||
50 | - tcg_gen_extu_i32_i64(s64, s); | ||
51 | - tcg_gen_dup_i64_vec(MO_64, vec_s, s64); | ||
52 | - tcg_temp_free_i64(s64); | ||
53 | - } else { | ||
54 | - tcg_gen_dup_i32_vec(vece, vec_s, s); | ||
55 | - } | ||
56 | - do_op3_nofail(vece, r, a, vec_s, opc_v); | ||
57 | - tcg_temp_free_vec(vec_s); | ||
58 | + g_assert_not_reached(); | ||
59 | } | ||
60 | - tcg_swap_vecop_list(hold_list); | ||
61 | } | 29 | } |
62 | 30 | ||
63 | void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) | 31 | static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1, |
32 | - PageDesc **ret_p2, tb_page_addr_t phys2, int alloc); | ||
33 | + PageDesc **ret_p2, tb_page_addr_t phys2, bool alloc); | ||
34 | |||
35 | /* In user-mode page locks aren't used; mmap_lock is enough */ | ||
36 | #ifdef CONFIG_USER_ONLY | ||
37 | @@ -XXX,XX +XXX,XX @@ static inline void page_unlock(PageDesc *pd) | ||
38 | /* lock the page(s) of a TB in the correct acquisition order */ | ||
39 | static inline void page_lock_tb(const TranslationBlock *tb) | ||
64 | { | 40 | { |
65 | - do_shifts(vece, r, a, b, INDEX_op_shls_vec, INDEX_op_shlv_vec); | 41 | - page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], 0); |
66 | + do_shifts(vece, r, a, b, INDEX_op_shls_vec); | 42 | + page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], false); |
67 | } | 43 | } |
68 | 44 | ||
69 | void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) | 45 | static inline void page_unlock_tb(const TranslationBlock *tb) |
46 | @@ -XXX,XX +XXX,XX @@ void page_collection_unlock(struct page_collection *set) | ||
47 | #endif /* !CONFIG_USER_ONLY */ | ||
48 | |||
49 | static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1, | ||
50 | - PageDesc **ret_p2, tb_page_addr_t phys2, int alloc) | ||
51 | + PageDesc **ret_p2, tb_page_addr_t phys2, bool alloc) | ||
70 | { | 52 | { |
71 | - do_shifts(vece, r, a, b, INDEX_op_shrs_vec, INDEX_op_shrv_vec); | 53 | PageDesc *p1, *p2; |
72 | + do_shifts(vece, r, a, b, INDEX_op_shrs_vec); | 54 | tb_page_addr_t page1; |
73 | } | 55 | @@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, |
74 | 56 | * Note that inserting into the hash table first isn't an option, since | |
75 | void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) | 57 | * we can only insert TBs that are fully initialized. |
76 | { | 58 | */ |
77 | - do_shifts(vece, r, a, b, INDEX_op_sars_vec, INDEX_op_sarv_vec); | 59 | - page_lock_pair(&p, phys_pc, &p2, phys_page2, 1); |
78 | + do_shifts(vece, r, a, b, INDEX_op_sars_vec); | 60 | + page_lock_pair(&p, phys_pc, &p2, phys_page2, true); |
79 | } | 61 | tb_page_add(p, tb, 0, phys_pc & TARGET_PAGE_MASK); |
80 | 62 | if (p2) { | |
81 | void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, | 63 | tb_page_add(p2, tb, 1, phys_page2); |
64 | @@ -XXX,XX +XXX,XX @@ void page_set_flags(target_ulong start, target_ulong end, int flags) | ||
65 | for (addr = start, len = end - start; | ||
66 | len != 0; | ||
67 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | ||
68 | - PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | ||
69 | + PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, true); | ||
70 | |||
71 | /* If the write protection bit is set, then we invalidate | ||
72 | the code inside. */ | ||
82 | -- | 73 | -- |
83 | 2.25.1 | 74 | 2.34.1 |
84 | 75 | ||
85 | 76 | diff view generated by jsdifflib |
1 | Merge VERLL and VERLLV into op_vesv and op_ves, alongside | 1 | Use the pc coming from db->pc_first rather than the TB. |
---|---|---|---|
2 | all of the other vector shift operations. | ||
3 | 2 | ||
4 | Reviewed-by: David Hildenbrand <david@redhat.com> | 3 | Use the cached host_addr rather than re-computing for the |
4 | first page. We still need a separate lookup for the second | ||
5 | page because it won't be computed for DisasContextBase until | ||
6 | the translator actually performs a read from the page. | ||
7 | |||
8 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | --- | 10 | --- |
7 | target/s390x/helper.h | 4 -- | 11 | include/exec/plugin-gen.h | 7 ++++--- |
8 | target/s390x/translate_vx.inc.c | 66 +++++---------------------------- | 12 | accel/tcg/plugin-gen.c | 22 +++++++++++----------- |
9 | target/s390x/vec_int_helper.c | 31 ---------------- | 13 | accel/tcg/translator.c | 2 +- |
10 | target/s390x/insn-data.def | 4 +- | 14 | 3 files changed, 16 insertions(+), 15 deletions(-) |
11 | 4 files changed, 11 insertions(+), 94 deletions(-) | ||
12 | 15 | ||
13 | diff --git a/target/s390x/helper.h b/target/s390x/helper.h | 16 | diff --git a/include/exec/plugin-gen.h b/include/exec/plugin-gen.h |
14 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/s390x/helper.h | 18 | --- a/include/exec/plugin-gen.h |
16 | +++ b/target/s390x/helper.h | 19 | +++ b/include/exec/plugin-gen.h |
17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(gvec_vmlo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) | 20 | @@ -XXX,XX +XXX,XX @@ struct DisasContextBase; |
18 | DEF_HELPER_FLAGS_4(gvec_vmlo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) | 21 | |
19 | DEF_HELPER_FLAGS_3(gvec_vpopct8, TCG_CALL_NO_RWG, void, ptr, cptr, i32) | 22 | #ifdef CONFIG_PLUGIN |
20 | DEF_HELPER_FLAGS_3(gvec_vpopct16, TCG_CALL_NO_RWG, void, ptr, cptr, i32) | 23 | |
21 | -DEF_HELPER_FLAGS_4(gvec_verllv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) | 24 | -bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool supress); |
22 | -DEF_HELPER_FLAGS_4(gvec_verllv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) | 25 | +bool plugin_gen_tb_start(CPUState *cpu, const struct DisasContextBase *db, |
23 | -DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) | 26 | + bool supress); |
24 | -DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) | 27 | void plugin_gen_tb_end(CPUState *cpu); |
25 | DEF_HELPER_FLAGS_4(gvec_verim8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) | 28 | void plugin_gen_insn_start(CPUState *cpu, const struct DisasContextBase *db); |
26 | DEF_HELPER_FLAGS_4(gvec_verim16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) | 29 | void plugin_gen_insn_end(void); |
27 | DEF_HELPER_FLAGS_4(gvec_vsl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) | 30 | @@ -XXX,XX +XXX,XX @@ static inline void plugin_insn_append(abi_ptr pc, const void *from, size_t size) |
28 | diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c | 31 | |
32 | #else /* !CONFIG_PLUGIN */ | ||
33 | |||
34 | -static inline | ||
35 | -bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool supress) | ||
36 | +static inline bool | ||
37 | +plugin_gen_tb_start(CPUState *cpu, const struct DisasContextBase *db, bool sup) | ||
38 | { | ||
39 | return false; | ||
40 | } | ||
41 | diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | 42 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/target/s390x/translate_vx.inc.c | 43 | --- a/accel/tcg/plugin-gen.c |
31 | +++ b/target/s390x/translate_vx.inc.c | 44 | +++ b/accel/tcg/plugin-gen.c |
32 | @@ -XXX,XX +XXX,XX @@ static DisasJumpType op_vpopct(DisasContext *s, DisasOps *o) | 45 | @@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(const struct qemu_plugin_tb *plugin_tb) |
33 | return DISAS_NEXT; | 46 | pr_ops(); |
34 | } | 47 | } |
35 | 48 | ||
36 | -static void gen_rll_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) | 49 | -bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool mem_only) |
37 | -{ | 50 | +bool plugin_gen_tb_start(CPUState *cpu, const DisasContextBase *db, |
38 | - TCGv_i32 t0 = tcg_temp_new_i32(); | 51 | + bool mem_only) |
39 | - | 52 | { |
40 | - tcg_gen_andi_i32(t0, b, 31); | 53 | bool ret = false; |
41 | - tcg_gen_rotl_i32(d, a, t0); | 54 | |
42 | - tcg_temp_free_i32(t0); | 55 | @@ -XXX,XX +XXX,XX @@ bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool mem_onl |
43 | -} | 56 | |
44 | - | 57 | ret = true; |
45 | -static void gen_rll_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) | 58 | |
46 | -{ | 59 | - ptb->vaddr = tb->pc; |
47 | - TCGv_i64 t0 = tcg_temp_new_i64(); | 60 | + ptb->vaddr = db->pc_first; |
48 | - | 61 | ptb->vaddr2 = -1; |
49 | - tcg_gen_andi_i64(t0, b, 63); | 62 | - get_page_addr_code_hostp(cpu->env_ptr, tb->pc, &ptb->haddr1); |
50 | - tcg_gen_rotl_i64(d, a, t0); | 63 | + ptb->haddr1 = db->host_addr[0]; |
51 | - tcg_temp_free_i64(t0); | 64 | ptb->haddr2 = NULL; |
52 | -} | 65 | ptb->mem_only = mem_only; |
53 | - | 66 | |
54 | -static DisasJumpType op_verllv(DisasContext *s, DisasOps *o) | 67 | @@ -XXX,XX +XXX,XX @@ void plugin_gen_insn_start(CPUState *cpu, const DisasContextBase *db) |
55 | -{ | 68 | * Note that we skip this when haddr1 == NULL, e.g. when we're |
56 | - const uint8_t es = get_field(s, m4); | 69 | * fetching instructions from a region not backed by RAM. |
57 | - static const GVecGen3 g[4] = { | 70 | */ |
58 | - { .fno = gen_helper_gvec_verllv8, }, | 71 | - if (likely(ptb->haddr1 != NULL && ptb->vaddr2 == -1) && |
59 | - { .fno = gen_helper_gvec_verllv16, }, | 72 | - unlikely((db->pc_next & TARGET_PAGE_MASK) != |
60 | - { .fni4 = gen_rll_i32, }, | 73 | - (db->pc_first & TARGET_PAGE_MASK))) { |
61 | - { .fni8 = gen_rll_i64, }, | 74 | - get_page_addr_code_hostp(cpu->env_ptr, db->pc_next, |
62 | - }; | 75 | - &ptb->haddr2); |
63 | - | 76 | - ptb->vaddr2 = db->pc_next; |
64 | - if (es > ES_64) { | ||
65 | - gen_program_exception(s, PGM_SPECIFICATION); | ||
66 | - return DISAS_NORETURN; | ||
67 | - } | 77 | - } |
68 | - | 78 | - if (likely(ptb->vaddr2 == -1)) { |
69 | - gen_gvec_3(get_field(s, v1), get_field(s, v2), | 79 | + if (ptb->haddr1 == NULL) { |
70 | - get_field(s, v3), &g[es]); | 80 | + pinsn->haddr = NULL; |
71 | - return DISAS_NEXT; | 81 | + } else if (is_same_page(db, db->pc_next)) { |
72 | -} | 82 | pinsn->haddr = ptb->haddr1 + pinsn->vaddr - ptb->vaddr; |
73 | - | 83 | } else { |
74 | -static DisasJumpType op_verll(DisasContext *s, DisasOps *o) | 84 | + if (ptb->vaddr2 == -1) { |
75 | -{ | 85 | + ptb->vaddr2 = TARGET_PAGE_ALIGN(db->pc_first); |
76 | - const uint8_t es = get_field(s, m4); | 86 | + get_page_addr_code_hostp(cpu->env_ptr, ptb->vaddr2, &ptb->haddr2); |
77 | - static const GVecGen2s g[4] = { | 87 | + } |
78 | - { .fno = gen_helper_gvec_verll8, }, | 88 | pinsn->haddr = ptb->haddr2 + pinsn->vaddr - ptb->vaddr2; |
79 | - { .fno = gen_helper_gvec_verll16, }, | 89 | } |
80 | - { .fni4 = gen_rll_i32, }, | 90 | } |
81 | - { .fni8 = gen_rll_i64, }, | 91 | diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c |
82 | - }; | ||
83 | - | ||
84 | - if (es > ES_64) { | ||
85 | - gen_program_exception(s, PGM_SPECIFICATION); | ||
86 | - return DISAS_NORETURN; | ||
87 | - } | ||
88 | - gen_gvec_2s(get_field(s, v1), get_field(s, v3), o->addr1, | ||
89 | - &g[es]); | ||
90 | - return DISAS_NEXT; | ||
91 | -} | ||
92 | - | ||
93 | static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, int32_t c) | ||
94 | { | ||
95 | TCGv_i32 t = tcg_temp_new_i32(); | ||
96 | @@ -XXX,XX +XXX,XX @@ static DisasJumpType op_vesv(DisasContext *s, DisasOps *o) | ||
97 | case 0x70: | ||
98 | gen_gvec_fn_3(shlv, es, v1, v2, v3); | ||
99 | break; | ||
100 | + case 0x73: | ||
101 | + gen_gvec_fn_3(rotlv, es, v1, v2, v3); | ||
102 | + break; | ||
103 | case 0x7a: | ||
104 | gen_gvec_fn_3(sarv, es, v1, v2, v3); | ||
105 | break; | ||
106 | @@ -XXX,XX +XXX,XX @@ static DisasJumpType op_ves(DisasContext *s, DisasOps *o) | ||
107 | case 0x30: | ||
108 | gen_gvec_fn_2i(shli, es, v1, v3, d2); | ||
109 | break; | ||
110 | + case 0x33: | ||
111 | + gen_gvec_fn_2i(rotli, es, v1, v3, d2); | ||
112 | + break; | ||
113 | case 0x3a: | ||
114 | gen_gvec_fn_2i(sari, es, v1, v3, d2); | ||
115 | break; | ||
116 | @@ -XXX,XX +XXX,XX @@ static DisasJumpType op_ves(DisasContext *s, DisasOps *o) | ||
117 | case 0x30: | ||
118 | gen_gvec_fn_2s(shls, es, v1, v3, shift); | ||
119 | break; | ||
120 | + case 0x33: | ||
121 | + gen_gvec_fn_2s(rotls, es, v1, v3, shift); | ||
122 | + break; | ||
123 | case 0x3a: | ||
124 | gen_gvec_fn_2s(sars, es, v1, v3, shift); | ||
125 | break; | ||
126 | diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c | ||
127 | index XXXXXXX..XXXXXXX 100644 | 92 | index XXXXXXX..XXXXXXX 100644 |
128 | --- a/target/s390x/vec_int_helper.c | 93 | --- a/accel/tcg/translator.c |
129 | +++ b/target/s390x/vec_int_helper.c | 94 | +++ b/accel/tcg/translator.c |
130 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_vpopct##BITS)(void *v1, const void *v2, uint32_t desc) \ | 95 | @@ -XXX,XX +XXX,XX @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns, |
131 | DEF_VPOPCT(8) | 96 | ops->tb_start(db, cpu); |
132 | DEF_VPOPCT(16) | 97 | tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */ |
133 | 98 | ||
134 | -#define DEF_VERLLV(BITS) \ | 99 | - plugin_enabled = plugin_gen_tb_start(cpu, tb, cflags & CF_MEMI_ONLY); |
135 | -void HELPER(gvec_verllv##BITS)(void *v1, const void *v2, const void *v3, \ | 100 | + plugin_enabled = plugin_gen_tb_start(cpu, db, cflags & CF_MEMI_ONLY); |
136 | - uint32_t desc) \ | 101 | |
137 | -{ \ | 102 | while (true) { |
138 | - int i; \ | 103 | db->num_insns++; |
139 | - \ | ||
140 | - for (i = 0; i < (128 / BITS); i++) { \ | ||
141 | - const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \ | ||
142 | - const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \ | ||
143 | - \ | ||
144 | - s390_vec_write_element##BITS(v1, i, rol##BITS(a, b)); \ | ||
145 | - } \ | ||
146 | -} | ||
147 | -DEF_VERLLV(8) | ||
148 | -DEF_VERLLV(16) | ||
149 | - | ||
150 | -#define DEF_VERLL(BITS) \ | ||
151 | -void HELPER(gvec_verll##BITS)(void *v1, const void *v2, uint64_t count, \ | ||
152 | - uint32_t desc) \ | ||
153 | -{ \ | ||
154 | - int i; \ | ||
155 | - \ | ||
156 | - for (i = 0; i < (128 / BITS); i++) { \ | ||
157 | - const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \ | ||
158 | - \ | ||
159 | - s390_vec_write_element##BITS(v1, i, rol##BITS(a, count)); \ | ||
160 | - } \ | ||
161 | -} | ||
162 | -DEF_VERLL(8) | ||
163 | -DEF_VERLL(16) | ||
164 | - | ||
165 | #define DEF_VERIM(BITS) \ | ||
166 | void HELPER(gvec_verim##BITS)(void *v1, const void *v2, const void *v3, \ | ||
167 | uint32_t desc) \ | ||
168 | diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def | ||
169 | index XXXXXXX..XXXXXXX 100644 | ||
170 | --- a/target/s390x/insn-data.def | ||
171 | +++ b/target/s390x/insn-data.def | ||
172 | @@ -XXX,XX +XXX,XX @@ | ||
173 | /* VECTOR POPULATION COUNT */ | ||
174 | F(0xe750, VPOPCT, VRR_a, V, 0, 0, 0, 0, vpopct, 0, IF_VEC) | ||
175 | /* VECTOR ELEMENT ROTATE LEFT LOGICAL */ | ||
176 | - F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, verllv, 0, IF_VEC) | ||
177 | - F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, verll, 0, IF_VEC) | ||
178 | + F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC) | ||
179 | + F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC) | ||
180 | /* VECTOR ELEMENT ROTATE AND INSERT UNDER MASK */ | ||
181 | F(0xe772, VERIM, VRI_d, V, 0, 0, 0, 0, verim, 0, IF_VEC) | ||
182 | /* VECTOR ELEMENT SHIFT LEFT */ | ||
183 | -- | 104 | -- |
184 | 2.25.1 | 105 | 2.34.1 |
185 | 106 | ||
186 | 107 | diff view generated by jsdifflib |
1 | If the output of the move is dead, then the last use is in | 1 | Let tb->page_addr[0] contain the address of the first byte of the |
---|---|---|---|
2 | the store. If we propagate the input to the store, then we | 2 | translated block, rather than the address of the page containing the |
3 | can remove the move opcode entirely. | 3 | start of the translated block. We need to recover this value anyway |
4 | at various points, and it is easier to discard a page offset when it | ||
5 | is not needed, which happens naturally via the existing find_page shift. | ||
4 | 6 | ||
7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | --- | 9 | --- |
7 | tcg/tcg.c | 78 +++++++++++++++++++++++++++++++++++++++---------------- | 10 | accel/tcg/cpu-exec.c | 16 ++++++++-------- |
8 | 1 file changed, 56 insertions(+), 22 deletions(-) | 11 | accel/tcg/cputlb.c | 3 ++- |
12 | accel/tcg/translate-all.c | 9 +++++---- | ||
13 | 3 files changed, 15 insertions(+), 13 deletions(-) | ||
9 | 14 | ||
10 | diff --git a/tcg/tcg.c b/tcg/tcg.c | 15 | diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c |
11 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/tcg/tcg.c | 17 | --- a/accel/tcg/cpu-exec.c |
13 | +++ b/tcg/tcg.c | 18 | +++ b/accel/tcg/cpu-exec.c |
14 | @@ -XXX,XX +XXX,XX @@ static bool liveness_pass_2(TCGContext *s) | 19 | @@ -XXX,XX +XXX,XX @@ struct tb_desc { |
15 | } | 20 | target_ulong pc; |
16 | 21 | target_ulong cs_base; | |
17 | /* Outputs become available. */ | 22 | CPUArchState *env; |
18 | - for (i = 0; i < nb_oargs; i++) { | 23 | - tb_page_addr_t phys_page1; |
19 | - arg_ts = arg_temp(op->args[i]); | 24 | + tb_page_addr_t page_addr0; |
20 | + if (opc == INDEX_op_mov_i32 || opc == INDEX_op_mov_i64) { | 25 | uint32_t flags; |
21 | + arg_ts = arg_temp(op->args[0]); | 26 | uint32_t cflags; |
22 | dir_ts = arg_ts->state_ptr; | 27 | uint32_t trace_vcpu_dstate; |
23 | - if (!dir_ts) { | 28 | @@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d) |
24 | - continue; | 29 | const struct tb_desc *desc = d; |
25 | + if (dir_ts) { | 30 | |
26 | + op->args[0] = temp_arg(dir_ts); | 31 | if (tb->pc == desc->pc && |
27 | + changes = true; | 32 | - tb->page_addr[0] == desc->phys_page1 && |
28 | + | 33 | + tb->page_addr[0] == desc->page_addr0 && |
29 | + /* The output is now live and modified. */ | 34 | tb->cs_base == desc->cs_base && |
30 | + arg_ts->state = 0; | 35 | tb->flags == desc->flags && |
31 | + | 36 | tb->trace_vcpu_dstate == desc->trace_vcpu_dstate && |
32 | + if (NEED_SYNC_ARG(0)) { | 37 | @@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d) |
33 | + TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32 | 38 | if (tb->page_addr[1] == -1) { |
34 | + ? INDEX_op_st_i32 | 39 | return true; |
35 | + : INDEX_op_st_i64); | 40 | } else { |
36 | + TCGOp *sop = tcg_op_insert_after(s, op, sopc); | 41 | - tb_page_addr_t phys_page2; |
37 | + TCGTemp *out_ts = dir_ts; | 42 | - target_ulong virt_page2; |
38 | + | 43 | + tb_page_addr_t phys_page1; |
39 | + if (IS_DEAD_ARG(0)) { | 44 | + target_ulong virt_page1; |
40 | + out_ts = arg_temp(op->args[1]); | 45 | |
41 | + arg_ts->state = TS_DEAD; | 46 | /* |
42 | + tcg_op_remove(s, op); | 47 | * We know that the first page matched, and an otherwise valid TB |
43 | + } else { | 48 | @@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d) |
44 | + arg_ts->state = TS_MEM; | 49 | * is different for the new TB. Therefore any exception raised |
45 | + } | 50 | * here by the faulting lookup is not premature. |
46 | + | 51 | */ |
47 | + sop->args[0] = temp_arg(out_ts); | 52 | - virt_page2 = TARGET_PAGE_ALIGN(desc->pc); |
48 | + sop->args[1] = temp_arg(arg_ts->mem_base); | 53 | - phys_page2 = get_page_addr_code(desc->env, virt_page2); |
49 | + sop->args[2] = arg_ts->mem_offset; | 54 | - if (tb->page_addr[1] == phys_page2) { |
50 | + } else { | 55 | + virt_page1 = TARGET_PAGE_ALIGN(desc->pc); |
51 | + tcg_debug_assert(!IS_DEAD_ARG(0)); | 56 | + phys_page1 = get_page_addr_code(desc->env, virt_page1); |
52 | + } | 57 | + if (tb->page_addr[1] == phys_page1) { |
53 | } | 58 | return true; |
54 | - op->args[i] = temp_arg(dir_ts); | ||
55 | - changes = true; | ||
56 | + } else { | ||
57 | + for (i = 0; i < nb_oargs; i++) { | ||
58 | + arg_ts = arg_temp(op->args[i]); | ||
59 | + dir_ts = arg_ts->state_ptr; | ||
60 | + if (!dir_ts) { | ||
61 | + continue; | ||
62 | + } | ||
63 | + op->args[i] = temp_arg(dir_ts); | ||
64 | + changes = true; | ||
65 | |||
66 | - /* The output is now live and modified. */ | ||
67 | - arg_ts->state = 0; | ||
68 | + /* The output is now live and modified. */ | ||
69 | + arg_ts->state = 0; | ||
70 | |||
71 | - /* Sync outputs upon their last write. */ | ||
72 | - if (NEED_SYNC_ARG(i)) { | ||
73 | - TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32 | ||
74 | - ? INDEX_op_st_i32 | ||
75 | - : INDEX_op_st_i64); | ||
76 | - TCGOp *sop = tcg_op_insert_after(s, op, sopc); | ||
77 | + /* Sync outputs upon their last write. */ | ||
78 | + if (NEED_SYNC_ARG(i)) { | ||
79 | + TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32 | ||
80 | + ? INDEX_op_st_i32 | ||
81 | + : INDEX_op_st_i64); | ||
82 | + TCGOp *sop = tcg_op_insert_after(s, op, sopc); | ||
83 | |||
84 | - sop->args[0] = temp_arg(dir_ts); | ||
85 | - sop->args[1] = temp_arg(arg_ts->mem_base); | ||
86 | - sop->args[2] = arg_ts->mem_offset; | ||
87 | + sop->args[0] = temp_arg(dir_ts); | ||
88 | + sop->args[1] = temp_arg(arg_ts->mem_base); | ||
89 | + sop->args[2] = arg_ts->mem_offset; | ||
90 | |||
91 | - arg_ts->state = TS_MEM; | ||
92 | - } | ||
93 | - /* Drop outputs that are dead. */ | ||
94 | - if (IS_DEAD_ARG(i)) { | ||
95 | - arg_ts->state = TS_DEAD; | ||
96 | + arg_ts->state = TS_MEM; | ||
97 | + } | ||
98 | + /* Drop outputs that are dead. */ | ||
99 | + if (IS_DEAD_ARG(i)) { | ||
100 | + arg_ts->state = TS_DEAD; | ||
101 | + } | ||
102 | } | 59 | } |
103 | } | 60 | } |
61 | @@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, | ||
62 | if (phys_pc == -1) { | ||
63 | return NULL; | ||
104 | } | 64 | } |
65 | - desc.phys_page1 = phys_pc & TARGET_PAGE_MASK; | ||
66 | + desc.page_addr0 = phys_pc; | ||
67 | h = tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate); | ||
68 | return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); | ||
69 | } | ||
70 | diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c | ||
71 | index XXXXXXX..XXXXXXX 100644 | ||
72 | --- a/accel/tcg/cputlb.c | ||
73 | +++ b/accel/tcg/cputlb.c | ||
74 | @@ -XXX,XX +XXX,XX @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, | ||
75 | can be detected */ | ||
76 | void tlb_protect_code(ram_addr_t ram_addr) | ||
77 | { | ||
78 | - cpu_physical_memory_test_and_clear_dirty(ram_addr, TARGET_PAGE_SIZE, | ||
79 | + cpu_physical_memory_test_and_clear_dirty(ram_addr & TARGET_PAGE_MASK, | ||
80 | + TARGET_PAGE_SIZE, | ||
81 | DIRTY_MEMORY_CODE); | ||
82 | } | ||
83 | |||
84 | diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c | ||
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/accel/tcg/translate-all.c | ||
87 | +++ b/accel/tcg/translate-all.c | ||
88 | @@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) | ||
89 | qemu_spin_unlock(&tb->jmp_lock); | ||
90 | |||
91 | /* remove the TB from the hash list */ | ||
92 | - phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | ||
93 | + phys_pc = tb->page_addr[0]; | ||
94 | h = tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags, | ||
95 | tb->trace_vcpu_dstate); | ||
96 | if (!qht_remove(&tb_ctx.htable, tb, h)) { | ||
97 | @@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, | ||
98 | * we can only insert TBs that are fully initialized. | ||
99 | */ | ||
100 | page_lock_pair(&p, phys_pc, &p2, phys_page2, true); | ||
101 | - tb_page_add(p, tb, 0, phys_pc & TARGET_PAGE_MASK); | ||
102 | + tb_page_add(p, tb, 0, phys_pc); | ||
103 | if (p2) { | ||
104 | tb_page_add(p2, tb, 1, phys_page2); | ||
105 | } else { | ||
106 | @@ -XXX,XX +XXX,XX @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages, | ||
107 | if (n == 0) { | ||
108 | /* NOTE: tb_end may be after the end of the page, but | ||
109 | it is not a problem */ | ||
110 | - tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | ||
111 | + tb_start = tb->page_addr[0]; | ||
112 | tb_end = tb_start + tb->size; | ||
113 | } else { | ||
114 | tb_start = tb->page_addr[1]; | ||
115 | - tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | ||
116 | + tb_end = tb_start + ((tb->page_addr[0] + tb->size) | ||
117 | + & ~TARGET_PAGE_MASK); | ||
118 | } | ||
119 | if (!(tb_end <= start || tb_start >= end)) { | ||
120 | #ifdef TARGET_HAS_PRECISE_SMC | ||
105 | -- | 121 | -- |
106 | 2.25.1 | 122 | 2.34.1 |
107 | 123 | ||
108 | 124 | diff view generated by jsdifflib |
1 | No host backend support yet, but the interfaces for rotli | 1 | This function has two users, who use it incompatibly. |
---|---|---|---|
2 | are in place. Canonicalize immediate rotate to the left, | 2 | In tlb_flush_page_by_mmuidx_async_0, when flushing a |
3 | based on a survey of architectures, but provide both left | 3 | single page, we need to flush exactly two pages. |
4 | and right shift interfaces to the translators. | 4 | In tlb_flush_range_by_mmuidx_async_0, when flushing a |
5 | range of pages, we need to flush N+1 pages. | ||
6 | |||
7 | This avoids double-flushing of jmp cache pages in a range. | ||
5 | 8 | ||
6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 9 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | --- | 11 | --- |
9 | accel/tcg/tcg-runtime.h | 5 +++ | 12 | accel/tcg/cputlb.c | 25 ++++++++++++++----------- |
10 | include/tcg/tcg-op-gvec.h | 6 ++++ | 13 | 1 file changed, 14 insertions(+), 11 deletions(-) |
11 | include/tcg/tcg-op.h | 2 ++ | ||
12 | include/tcg/tcg-opc.h | 1 + | ||
13 | include/tcg/tcg.h | 1 + | ||
14 | tcg/aarch64/tcg-target.h | 1 + | ||
15 | tcg/i386/tcg-target.h | 1 + | ||
16 | tcg/ppc/tcg-target.h | 1 + | ||
17 | accel/tcg/tcg-runtime-gvec.c | 48 +++++++++++++++++++++++++ | ||
18 | tcg/tcg-op-gvec.c | 68 ++++++++++++++++++++++++++++++++++++ | ||
19 | tcg/tcg-op-vec.c | 12 +++++++ | ||
20 | tcg/tcg.c | 2 ++ | ||
21 | tcg/README | 3 +- | ||
22 | 13 files changed, 150 insertions(+), 1 deletion(-) | ||
23 | 14 | ||
24 | diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h | 15 | diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c |
25 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/accel/tcg/tcg-runtime.h | 17 | --- a/accel/tcg/cputlb.c |
27 | +++ b/accel/tcg/tcg-runtime.h | 18 | +++ b/accel/tcg/cputlb.c |
28 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(gvec_sar16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | 19 | @@ -XXX,XX +XXX,XX @@ static void tb_jmp_cache_clear_page(CPUState *cpu, target_ulong page_addr) |
29 | DEF_HELPER_FLAGS_3(gvec_sar32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
30 | DEF_HELPER_FLAGS_3(gvec_sar64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
31 | |||
32 | +DEF_HELPER_FLAGS_3(gvec_rotl8i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
33 | +DEF_HELPER_FLAGS_3(gvec_rotl16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
34 | +DEF_HELPER_FLAGS_3(gvec_rotl32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
35 | +DEF_HELPER_FLAGS_3(gvec_rotl64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
36 | + | ||
37 | DEF_HELPER_FLAGS_4(gvec_shl8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
38 | DEF_HELPER_FLAGS_4(gvec_shl16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
39 | DEF_HELPER_FLAGS_4(gvec_shl32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
40 | diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/include/tcg/tcg-op-gvec.h | ||
43 | +++ b/include/tcg/tcg-op-gvec.h | ||
44 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
45 | int64_t shift, uint32_t oprsz, uint32_t maxsz); | ||
46 | void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
47 | int64_t shift, uint32_t oprsz, uint32_t maxsz); | ||
48 | +void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
49 | + int64_t shift, uint32_t oprsz, uint32_t maxsz); | ||
50 | +void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
51 | + int64_t shift, uint32_t oprsz, uint32_t maxsz); | ||
52 | |||
53 | void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
54 | TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); | ||
55 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); | ||
56 | void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); | ||
57 | void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); | ||
58 | void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); | ||
59 | +void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c); | ||
60 | +void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c); | ||
61 | |||
62 | #endif | ||
63 | diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h | ||
64 | index XXXXXXX..XXXXXXX 100644 | ||
65 | --- a/include/tcg/tcg-op.h | ||
66 | +++ b/include/tcg/tcg-op.h | ||
67 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); | ||
68 | void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); | ||
69 | void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); | ||
70 | void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); | ||
71 | +void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); | ||
72 | +void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); | ||
73 | |||
74 | void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); | ||
75 | void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); | ||
76 | diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h | ||
77 | index XXXXXXX..XXXXXXX 100644 | ||
78 | --- a/include/tcg/tcg-opc.h | ||
79 | +++ b/include/tcg/tcg-opc.h | ||
80 | @@ -XXX,XX +XXX,XX @@ DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec)) | ||
81 | DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) | ||
82 | DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) | ||
83 | DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) | ||
84 | +DEF(rotli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_roti_vec)) | ||
85 | |||
86 | DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) | ||
87 | DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) | ||
88 | diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h | ||
89 | index XXXXXXX..XXXXXXX 100644 | ||
90 | --- a/include/tcg/tcg.h | ||
91 | +++ b/include/tcg/tcg.h | ||
92 | @@ -XXX,XX +XXX,XX @@ typedef uint64_t TCGRegSet; | ||
93 | #define TCG_TARGET_HAS_not_vec 0 | ||
94 | #define TCG_TARGET_HAS_andc_vec 0 | ||
95 | #define TCG_TARGET_HAS_orc_vec 0 | ||
96 | +#define TCG_TARGET_HAS_roti_vec 0 | ||
97 | #define TCG_TARGET_HAS_shi_vec 0 | ||
98 | #define TCG_TARGET_HAS_shs_vec 0 | ||
99 | #define TCG_TARGET_HAS_shv_vec 0 | ||
100 | diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h | ||
101 | index XXXXXXX..XXXXXXX 100644 | ||
102 | --- a/tcg/aarch64/tcg-target.h | ||
103 | +++ b/tcg/aarch64/tcg-target.h | ||
104 | @@ -XXX,XX +XXX,XX @@ typedef enum { | ||
105 | #define TCG_TARGET_HAS_not_vec 1 | ||
106 | #define TCG_TARGET_HAS_neg_vec 1 | ||
107 | #define TCG_TARGET_HAS_abs_vec 1 | ||
108 | +#define TCG_TARGET_HAS_roti_vec 0 | ||
109 | #define TCG_TARGET_HAS_shi_vec 1 | ||
110 | #define TCG_TARGET_HAS_shs_vec 0 | ||
111 | #define TCG_TARGET_HAS_shv_vec 1 | ||
112 | diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h | ||
113 | index XXXXXXX..XXXXXXX 100644 | ||
114 | --- a/tcg/i386/tcg-target.h | ||
115 | +++ b/tcg/i386/tcg-target.h | ||
116 | @@ -XXX,XX +XXX,XX @@ extern bool have_avx2; | ||
117 | #define TCG_TARGET_HAS_not_vec 0 | ||
118 | #define TCG_TARGET_HAS_neg_vec 0 | ||
119 | #define TCG_TARGET_HAS_abs_vec 1 | ||
120 | +#define TCG_TARGET_HAS_roti_vec 0 | ||
121 | #define TCG_TARGET_HAS_shi_vec 1 | ||
122 | #define TCG_TARGET_HAS_shs_vec 1 | ||
123 | #define TCG_TARGET_HAS_shv_vec have_avx2 | ||
124 | diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h | ||
125 | index XXXXXXX..XXXXXXX 100644 | ||
126 | --- a/tcg/ppc/tcg-target.h | ||
127 | +++ b/tcg/ppc/tcg-target.h | ||
128 | @@ -XXX,XX +XXX,XX @@ extern bool have_vsx; | ||
129 | #define TCG_TARGET_HAS_not_vec 1 | ||
130 | #define TCG_TARGET_HAS_neg_vec have_isa_3_00 | ||
131 | #define TCG_TARGET_HAS_abs_vec 0 | ||
132 | +#define TCG_TARGET_HAS_roti_vec 0 | ||
133 | #define TCG_TARGET_HAS_shi_vec 0 | ||
134 | #define TCG_TARGET_HAS_shs_vec 0 | ||
135 | #define TCG_TARGET_HAS_shv_vec 1 | ||
136 | diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c | ||
137 | index XXXXXXX..XXXXXXX 100644 | ||
138 | --- a/accel/tcg/tcg-runtime-gvec.c | ||
139 | +++ b/accel/tcg/tcg-runtime-gvec.c | ||
140 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sar64i)(void *d, void *a, uint32_t desc) | ||
141 | clear_high(d, oprsz, desc); | ||
142 | } | ||
143 | |||
144 | +void HELPER(gvec_rotl8i)(void *d, void *a, uint32_t desc) | ||
145 | +{ | ||
146 | + intptr_t oprsz = simd_oprsz(desc); | ||
147 | + int shift = simd_data(desc); | ||
148 | + intptr_t i; | ||
149 | + | ||
150 | + for (i = 0; i < oprsz; i += sizeof(uint8_t)) { | ||
151 | + *(uint8_t *)(d + i) = rol8(*(uint8_t *)(a + i), shift); | ||
152 | + } | ||
153 | + clear_high(d, oprsz, desc); | ||
154 | +} | ||
155 | + | ||
156 | +void HELPER(gvec_rotl16i)(void *d, void *a, uint32_t desc) | ||
157 | +{ | ||
158 | + intptr_t oprsz = simd_oprsz(desc); | ||
159 | + int shift = simd_data(desc); | ||
160 | + intptr_t i; | ||
161 | + | ||
162 | + for (i = 0; i < oprsz; i += sizeof(uint16_t)) { | ||
163 | + *(uint16_t *)(d + i) = rol16(*(uint16_t *)(a + i), shift); | ||
164 | + } | ||
165 | + clear_high(d, oprsz, desc); | ||
166 | +} | ||
167 | + | ||
168 | +void HELPER(gvec_rotl32i)(void *d, void *a, uint32_t desc) | ||
169 | +{ | ||
170 | + intptr_t oprsz = simd_oprsz(desc); | ||
171 | + int shift = simd_data(desc); | ||
172 | + intptr_t i; | ||
173 | + | ||
174 | + for (i = 0; i < oprsz; i += sizeof(uint32_t)) { | ||
175 | + *(uint32_t *)(d + i) = rol32(*(uint32_t *)(a + i), shift); | ||
176 | + } | ||
177 | + clear_high(d, oprsz, desc); | ||
178 | +} | ||
179 | + | ||
180 | +void HELPER(gvec_rotl64i)(void *d, void *a, uint32_t desc) | ||
181 | +{ | ||
182 | + intptr_t oprsz = simd_oprsz(desc); | ||
183 | + int shift = simd_data(desc); | ||
184 | + intptr_t i; | ||
185 | + | ||
186 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
187 | + *(uint64_t *)(d + i) = rol64(*(uint64_t *)(a + i), shift); | ||
188 | + } | ||
189 | + clear_high(d, oprsz, desc); | ||
190 | +} | ||
191 | + | ||
192 | void HELPER(gvec_shl8v)(void *d, void *a, void *b, uint32_t desc) | ||
193 | { | ||
194 | intptr_t oprsz = simd_oprsz(desc); | ||
195 | diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c | ||
196 | index XXXXXXX..XXXXXXX 100644 | ||
197 | --- a/tcg/tcg-op-gvec.c | ||
198 | +++ b/tcg/tcg-op-gvec.c | ||
199 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
200 | } | 20 | } |
201 | } | 21 | } |
202 | 22 | ||
203 | +void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) | 23 | -static void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr) |
204 | +{ | 24 | -{ |
205 | + uint64_t mask = dup_const(MO_8, 0xff << c); | 25 | - /* Discard jump cache entries for any tb which might potentially |
206 | + | 26 | - overlap the flushed page. */ |
207 | + tcg_gen_shli_i64(d, a, c); | 27 | - tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE); |
208 | + tcg_gen_shri_i64(a, a, 8 - c); | 28 | - tb_jmp_cache_clear_page(cpu, addr); |
209 | + tcg_gen_andi_i64(d, d, mask); | 29 | -} |
210 | + tcg_gen_andi_i64(a, a, ~mask); | 30 | - |
211 | + tcg_gen_or_i64(d, d, a); | 31 | /** |
212 | +} | 32 | * tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary |
213 | + | 33 | * @desc: The CPUTLBDesc portion of the TLB |
214 | +void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) | 34 | @@ -XXX,XX +XXX,XX @@ static void tlb_flush_page_by_mmuidx_async_0(CPUState *cpu, |
215 | +{ | 35 | } |
216 | + uint64_t mask = dup_const(MO_16, 0xffff << c); | 36 | qemu_spin_unlock(&env_tlb(env)->c.lock); |
217 | + | 37 | |
218 | + tcg_gen_shli_i64(d, a, c); | 38 | - tb_flush_jmp_cache(cpu, addr); |
219 | + tcg_gen_shri_i64(a, a, 16 - c); | 39 | + /* |
220 | + tcg_gen_andi_i64(d, d, mask); | 40 | + * Discard jump cache entries for any tb which might potentially |
221 | + tcg_gen_andi_i64(a, a, ~mask); | 41 | + * overlap the flushed page, which includes the previous. |
222 | + tcg_gen_or_i64(d, d, a); | 42 | + */ |
223 | +} | 43 | + tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE); |
224 | + | 44 | + tb_jmp_cache_clear_page(cpu, addr); |
225 | +void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
226 | + int64_t shift, uint32_t oprsz, uint32_t maxsz) | ||
227 | +{ | ||
228 | + static const TCGOpcode vecop_list[] = { INDEX_op_rotli_vec, 0 }; | ||
229 | + static const GVecGen2i g[4] = { | ||
230 | + { .fni8 = tcg_gen_vec_rotl8i_i64, | ||
231 | + .fniv = tcg_gen_rotli_vec, | ||
232 | + .fno = gen_helper_gvec_rotl8i, | ||
233 | + .opt_opc = vecop_list, | ||
234 | + .vece = MO_8 }, | ||
235 | + { .fni8 = tcg_gen_vec_rotl16i_i64, | ||
236 | + .fniv = tcg_gen_rotli_vec, | ||
237 | + .fno = gen_helper_gvec_rotl16i, | ||
238 | + .opt_opc = vecop_list, | ||
239 | + .vece = MO_16 }, | ||
240 | + { .fni4 = tcg_gen_rotli_i32, | ||
241 | + .fniv = tcg_gen_rotli_vec, | ||
242 | + .fno = gen_helper_gvec_rotl32i, | ||
243 | + .opt_opc = vecop_list, | ||
244 | + .vece = MO_32 }, | ||
245 | + { .fni8 = tcg_gen_rotli_i64, | ||
246 | + .fniv = tcg_gen_rotli_vec, | ||
247 | + .fno = gen_helper_gvec_rotl64i, | ||
248 | + .opt_opc = vecop_list, | ||
249 | + .prefer_i64 = TCG_TARGET_REG_BITS == 64, | ||
250 | + .vece = MO_64 }, | ||
251 | + }; | ||
252 | + | ||
253 | + tcg_debug_assert(vece <= MO_64); | ||
254 | + tcg_debug_assert(shift >= 0 && shift < (8 << vece)); | ||
255 | + if (shift == 0) { | ||
256 | + tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); | ||
257 | + } else { | ||
258 | + tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]); | ||
259 | + } | ||
260 | +} | ||
261 | + | ||
262 | +void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
263 | + int64_t shift, uint32_t oprsz, uint32_t maxsz) | ||
264 | +{ | ||
265 | + tcg_debug_assert(vece <= MO_64); | ||
266 | + tcg_debug_assert(shift >= 0 && shift < (8 << vece)); | ||
267 | + tcg_gen_gvec_rotli(vece, dofs, aofs, -shift & ((8 << vece) - 1), | ||
268 | + oprsz, maxsz); | ||
269 | +} | ||
270 | + | ||
271 | /* | ||
272 | * Specialized generation vector shifts by a non-constant scalar. | ||
273 | */ | ||
274 | diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c | ||
275 | index XXXXXXX..XXXXXXX 100644 | ||
276 | --- a/tcg/tcg-op-vec.c | ||
277 | +++ b/tcg/tcg-op-vec.c | ||
278 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i) | ||
279 | do_shifti(INDEX_op_sari_vec, vece, r, a, i); | ||
280 | } | 45 | } |
281 | 46 | ||
282 | +void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i) | 47 | /** |
283 | +{ | 48 | @@ -XXX,XX +XXX,XX @@ static void tlb_flush_range_by_mmuidx_async_0(CPUState *cpu, |
284 | + do_shifti(INDEX_op_rotli_vec, vece, r, a, i); | 49 | return; |
285 | +} | 50 | } |
286 | + | 51 | |
287 | +void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i) | 52 | - for (target_ulong i = 0; i < d.len; i += TARGET_PAGE_SIZE) { |
288 | +{ | 53 | - tb_flush_jmp_cache(cpu, d.addr + i); |
289 | + int bits = 8 << vece; | 54 | + /* |
290 | + tcg_debug_assert(i >= 0 && i < bits); | 55 | + * Discard jump cache entries for any tb which might potentially |
291 | + do_shifti(INDEX_op_rotli_vec, vece, r, a, -i & (bits - 1)); | 56 | + * overlap the flushed pages, which includes the previous. |
292 | +} | 57 | + */ |
293 | + | 58 | + d.addr -= TARGET_PAGE_SIZE; |
294 | void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, | 59 | + for (target_ulong i = 0, n = d.len / TARGET_PAGE_SIZE + 1; i < n; i++) { |
295 | TCGv_vec r, TCGv_vec a, TCGv_vec b) | 60 | + tb_jmp_cache_clear_page(cpu, d.addr); |
296 | { | 61 | + d.addr += TARGET_PAGE_SIZE; |
297 | diff --git a/tcg/tcg.c b/tcg/tcg.c | 62 | } |
298 | index XXXXXXX..XXXXXXX 100644 | 63 | } |
299 | --- a/tcg/tcg.c | ||
300 | +++ b/tcg/tcg.c | ||
301 | @@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op) | ||
302 | case INDEX_op_shrv_vec: | ||
303 | case INDEX_op_sarv_vec: | ||
304 | return have_vec && TCG_TARGET_HAS_shv_vec; | ||
305 | + case INDEX_op_rotli_vec: | ||
306 | + return have_vec && TCG_TARGET_HAS_roti_vec; | ||
307 | case INDEX_op_ssadd_vec: | ||
308 | case INDEX_op_usadd_vec: | ||
309 | case INDEX_op_sssub_vec: | ||
310 | diff --git a/tcg/README b/tcg/README | ||
311 | index XXXXXXX..XXXXXXX 100644 | ||
312 | --- a/tcg/README | ||
313 | +++ b/tcg/README | ||
314 | @@ -XXX,XX +XXX,XX @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32. | ||
315 | |||
316 | * shri_vec v0, v1, i2 | ||
317 | * sari_vec v0, v1, i2 | ||
318 | +* rotli_vec v0, v1, i2 | ||
319 | * shrs_vec v0, v1, s2 | ||
320 | * sars_vec v0, v1, s2 | ||
321 | |||
322 | - Similarly for logical and arithmetic right shift. | ||
323 | + Similarly for logical and arithmetic right shift, and left rotate. | ||
324 | |||
325 | * shlv_vec v0, v1, v2 | ||
326 | 64 | ||
327 | -- | 65 | -- |
328 | 2.25.1 | 66 | 2.34.1 |
329 | 67 | ||
330 | 68 | diff view generated by jsdifflib |
1 | Acked-by: David Gibson <david@gibson.dropbear.id.au> | 1 | Wrap the bare TranslationBlock pointer into a structure. |
---|---|---|---|
2 | |||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
3 | --- | 6 | --- |
4 | target/ppc/helper.h | 4 ---- | 7 | accel/tcg/tb-hash.h | 1 + |
5 | target/ppc/int_helper.c | 17 ----------------- | 8 | accel/tcg/tb-jmp-cache.h | 24 ++++++++++++++++++++++++ |
6 | target/ppc/translate/vmx-impl.inc.c | 8 ++++---- | 9 | include/exec/cpu-common.h | 1 + |
7 | 3 files changed, 4 insertions(+), 25 deletions(-) | 10 | include/hw/core/cpu.h | 15 +-------------- |
11 | include/qemu/typedefs.h | 1 + | ||
12 | accel/stubs/tcg-stub.c | 4 ++++ | ||
13 | accel/tcg/cpu-exec.c | 10 +++++++--- | ||
14 | accel/tcg/cputlb.c | 9 +++++---- | ||
15 | accel/tcg/translate-all.c | 28 +++++++++++++++++++++++++--- | ||
16 | hw/core/cpu-common.c | 3 +-- | ||
17 | plugins/core.c | 2 +- | ||
18 | trace/control-target.c | 2 +- | ||
19 | 12 files changed, 72 insertions(+), 28 deletions(-) | ||
20 | create mode 100644 accel/tcg/tb-jmp-cache.h | ||
8 | 21 | ||
9 | diff --git a/target/ppc/helper.h b/target/ppc/helper.h | 22 | diff --git a/accel/tcg/tb-hash.h b/accel/tcg/tb-hash.h |
10 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
11 | --- a/target/ppc/helper.h | 24 | --- a/accel/tcg/tb-hash.h |
12 | +++ b/target/ppc/helper.h | 25 | +++ b/accel/tcg/tb-hash.h |
13 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vsubuqm, void, avr, avr, avr) | 26 | @@ -XXX,XX +XXX,XX @@ |
14 | DEF_HELPER_4(vsubecuq, void, avr, avr, avr, avr) | 27 | #include "exec/cpu-defs.h" |
15 | DEF_HELPER_4(vsubeuqm, void, avr, avr, avr, avr) | 28 | #include "exec/exec-all.h" |
16 | DEF_HELPER_3(vsubcuq, void, avr, avr, avr) | 29 | #include "qemu/xxhash.h" |
17 | -DEF_HELPER_3(vrlb, void, avr, avr, avr) | 30 | +#include "tb-jmp-cache.h" |
18 | -DEF_HELPER_3(vrlh, void, avr, avr, avr) | 31 | |
19 | -DEF_HELPER_3(vrlw, void, avr, avr, avr) | 32 | #ifdef CONFIG_SOFTMMU |
20 | -DEF_HELPER_3(vrld, void, avr, avr, avr) | 33 | |
21 | DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32) | 34 | diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h |
22 | DEF_HELPER_3(vextractub, void, avr, avr, i32) | 35 | new file mode 100644 |
23 | DEF_HELPER_3(vextractuh, void, avr, avr, i32) | 36 | index XXXXXXX..XXXXXXX |
24 | diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c | 37 | --- /dev/null |
25 | index XXXXXXX..XXXXXXX 100644 | 38 | +++ b/accel/tcg/tb-jmp-cache.h |
26 | --- a/target/ppc/int_helper.c | 39 | @@ -XXX,XX +XXX,XX @@ |
27 | +++ b/target/ppc/int_helper.c | 40 | +/* |
28 | @@ -XXX,XX +XXX,XX @@ VRFI(p, float_round_up) | 41 | + * The per-CPU TranslationBlock jump cache. |
29 | VRFI(z, float_round_to_zero) | 42 | + * |
30 | #undef VRFI | 43 | + * Copyright (c) 2003 Fabrice Bellard |
31 | 44 | + * | |
32 | -#define VROTATE(suffix, element, mask) \ | 45 | + * SPDX-License-Identifier: GPL-2.0-or-later |
33 | - void helper_vrl##suffix(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ | 46 | + */ |
34 | - { \ | 47 | + |
35 | - int i; \ | 48 | +#ifndef ACCEL_TCG_TB_JMP_CACHE_H |
36 | - \ | 49 | +#define ACCEL_TCG_TB_JMP_CACHE_H |
37 | - for (i = 0; i < ARRAY_SIZE(r->element); i++) { \ | 50 | + |
38 | - unsigned int shift = b->element[i] & mask; \ | 51 | +#define TB_JMP_CACHE_BITS 12 |
39 | - r->element[i] = (a->element[i] << shift) | \ | 52 | +#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) |
40 | - (a->element[i] >> (sizeof(a->element[0]) * 8 - shift)); \ | 53 | + |
41 | - } \ | 54 | +/* |
55 | + * Accessed in parallel; all accesses to 'tb' must be atomic. | ||
56 | + */ | ||
57 | +struct CPUJumpCache { | ||
58 | + struct { | ||
59 | + TranslationBlock *tb; | ||
60 | + } array[TB_JMP_CACHE_SIZE]; | ||
61 | +}; | ||
62 | + | ||
63 | +#endif /* ACCEL_TCG_TB_JMP_CACHE_H */ | ||
64 | diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h | ||
65 | index XXXXXXX..XXXXXXX 100644 | ||
66 | --- a/include/exec/cpu-common.h | ||
67 | +++ b/include/exec/cpu-common.h | ||
68 | @@ -XXX,XX +XXX,XX @@ void cpu_list_unlock(void); | ||
69 | unsigned int cpu_list_generation_id_get(void); | ||
70 | |||
71 | void tcg_flush_softmmu_tlb(CPUState *cs); | ||
72 | +void tcg_flush_jmp_cache(CPUState *cs); | ||
73 | |||
74 | void tcg_iommu_init_notifier_list(CPUState *cpu); | ||
75 | void tcg_iommu_free_notifier_list(CPUState *cpu); | ||
76 | diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h | ||
77 | index XXXXXXX..XXXXXXX 100644 | ||
78 | --- a/include/hw/core/cpu.h | ||
79 | +++ b/include/hw/core/cpu.h | ||
80 | @@ -XXX,XX +XXX,XX @@ struct kvm_run; | ||
81 | struct hax_vcpu_state; | ||
82 | struct hvf_vcpu_state; | ||
83 | |||
84 | -#define TB_JMP_CACHE_BITS 12 | ||
85 | -#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) | ||
86 | - | ||
87 | /* work queue */ | ||
88 | |||
89 | /* The union type allows passing of 64 bit target pointers on 32 bit | ||
90 | @@ -XXX,XX +XXX,XX @@ struct CPUState { | ||
91 | CPUArchState *env_ptr; | ||
92 | IcountDecr *icount_decr_ptr; | ||
93 | |||
94 | - /* Accessed in parallel; all accesses must be atomic */ | ||
95 | - TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; | ||
96 | + CPUJumpCache *tb_jmp_cache; | ||
97 | |||
98 | struct GDBRegisterState *gdb_regs; | ||
99 | int gdb_num_regs; | ||
100 | @@ -XXX,XX +XXX,XX @@ extern CPUTailQ cpus; | ||
101 | |||
102 | extern __thread CPUState *current_cpu; | ||
103 | |||
104 | -static inline void cpu_tb_jmp_cache_clear(CPUState *cpu) | ||
105 | -{ | ||
106 | - unsigned int i; | ||
107 | - | ||
108 | - for (i = 0; i < TB_JMP_CACHE_SIZE; i++) { | ||
109 | - qatomic_set(&cpu->tb_jmp_cache[i], NULL); | ||
42 | - } | 110 | - } |
43 | -VROTATE(b, u8, 0x7) | 111 | -} |
44 | -VROTATE(h, u16, 0xF) | ||
45 | -VROTATE(w, u32, 0x1F) | ||
46 | -VROTATE(d, u64, 0x3F) | ||
47 | -#undef VROTATE | ||
48 | - | 112 | - |
49 | void helper_vrsqrtefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b) | 113 | /** |
50 | { | 114 | * qemu_tcg_mttcg_enabled: |
51 | int i; | 115 | * Check whether we are running MultiThread TCG or not. |
52 | diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c | 116 | diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h |
53 | index XXXXXXX..XXXXXXX 100644 | 117 | index XXXXXXX..XXXXXXX 100644 |
54 | --- a/target/ppc/translate/vmx-impl.inc.c | 118 | --- a/include/qemu/typedefs.h |
55 | +++ b/target/ppc/translate/vmx-impl.inc.c | 119 | +++ b/include/qemu/typedefs.h |
56 | @@ -XXX,XX +XXX,XX @@ GEN_VXFORM3(vsubeuqm, 31, 0); | 120 | @@ -XXX,XX +XXX,XX @@ typedef struct CoMutex CoMutex; |
57 | GEN_VXFORM3(vsubecuq, 31, 0); | 121 | typedef struct ConfidentialGuestSupport ConfidentialGuestSupport; |
58 | GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ | 122 | typedef struct CPUAddressSpace CPUAddressSpace; |
59 | vsubecuq, PPC_NONE, PPC2_ALTIVEC_207) | 123 | typedef struct CPUArchState CPUArchState; |
60 | -GEN_VXFORM(vrlb, 2, 0); | 124 | +typedef struct CPUJumpCache CPUJumpCache; |
61 | -GEN_VXFORM(vrlh, 2, 1); | 125 | typedef struct CPUState CPUState; |
62 | -GEN_VXFORM(vrlw, 2, 2); | 126 | typedef struct CPUTLBEntryFull CPUTLBEntryFull; |
63 | +GEN_VXFORM_V(vrlb, MO_8, tcg_gen_gvec_rotlv, 2, 0); | 127 | typedef struct DeviceListener DeviceListener; |
64 | +GEN_VXFORM_V(vrlh, MO_16, tcg_gen_gvec_rotlv, 2, 1); | 128 | diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c |
65 | +GEN_VXFORM_V(vrlw, MO_32, tcg_gen_gvec_rotlv, 2, 2); | 129 | index XXXXXXX..XXXXXXX 100644 |
66 | GEN_VXFORM(vrlwmi, 2, 2); | 130 | --- a/accel/stubs/tcg-stub.c |
67 | GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \ | 131 | +++ b/accel/stubs/tcg-stub.c |
68 | vrlwmi, PPC_NONE, PPC2_ISA300) | 132 | @@ -XXX,XX +XXX,XX @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) |
69 | -GEN_VXFORM(vrld, 2, 3); | 133 | { |
70 | +GEN_VXFORM_V(vrld, MO_64, tcg_gen_gvec_rotlv, 2, 3); | 134 | } |
71 | GEN_VXFORM(vrldmi, 2, 3); | 135 | |
72 | GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \ | 136 | +void tcg_flush_jmp_cache(CPUState *cpu) |
73 | vrldmi, PPC_NONE, PPC2_ISA300) | 137 | +{ |
138 | +} | ||
139 | + | ||
140 | int probe_access_flags(CPUArchState *env, target_ulong addr, | ||
141 | MMUAccessType access_type, int mmu_idx, | ||
142 | bool nonfault, void **phost, uintptr_t retaddr) | ||
143 | diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c | ||
144 | index XXXXXXX..XXXXXXX 100644 | ||
145 | --- a/accel/tcg/cpu-exec.c | ||
146 | +++ b/accel/tcg/cpu-exec.c | ||
147 | @@ -XXX,XX +XXX,XX @@ | ||
148 | #include "sysemu/replay.h" | ||
149 | #include "sysemu/tcg.h" | ||
150 | #include "exec/helper-proto.h" | ||
151 | +#include "tb-jmp-cache.h" | ||
152 | #include "tb-hash.h" | ||
153 | #include "tb-context.h" | ||
154 | #include "internal.h" | ||
155 | @@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc, | ||
156 | tcg_debug_assert(!(cflags & CF_INVALID)); | ||
157 | |||
158 | hash = tb_jmp_cache_hash_func(pc); | ||
159 | - tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]); | ||
160 | + tb = qatomic_rcu_read(&cpu->tb_jmp_cache->array[hash].tb); | ||
161 | |||
162 | if (likely(tb && | ||
163 | tb->pc == pc && | ||
164 | @@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc, | ||
165 | if (tb == NULL) { | ||
166 | return NULL; | ||
167 | } | ||
168 | - qatomic_set(&cpu->tb_jmp_cache[hash], tb); | ||
169 | + qatomic_set(&cpu->tb_jmp_cache->array[hash].tb, tb); | ||
170 | return tb; | ||
171 | } | ||
172 | |||
173 | @@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu) | ||
174 | |||
175 | tb = tb_lookup(cpu, pc, cs_base, flags, cflags); | ||
176 | if (tb == NULL) { | ||
177 | + uint32_t h; | ||
178 | + | ||
179 | mmap_lock(); | ||
180 | tb = tb_gen_code(cpu, pc, cs_base, flags, cflags); | ||
181 | mmap_unlock(); | ||
182 | @@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu) | ||
183 | * We add the TB in the virtual pc hash table | ||
184 | * for the fast lookup | ||
185 | */ | ||
186 | - qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb); | ||
187 | + h = tb_jmp_cache_hash_func(pc); | ||
188 | + qatomic_set(&cpu->tb_jmp_cache->array[h].tb, tb); | ||
189 | } | ||
190 | |||
191 | #ifndef CONFIG_USER_ONLY | ||
192 | diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c | ||
193 | index XXXXXXX..XXXXXXX 100644 | ||
194 | --- a/accel/tcg/cputlb.c | ||
195 | +++ b/accel/tcg/cputlb.c | ||
196 | @@ -XXX,XX +XXX,XX @@ static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns, | ||
197 | |||
198 | static void tb_jmp_cache_clear_page(CPUState *cpu, target_ulong page_addr) | ||
199 | { | ||
200 | - unsigned int i, i0 = tb_jmp_cache_hash_page(page_addr); | ||
201 | + int i, i0 = tb_jmp_cache_hash_page(page_addr); | ||
202 | + CPUJumpCache *jc = cpu->tb_jmp_cache; | ||
203 | |||
204 | for (i = 0; i < TB_JMP_PAGE_SIZE; i++) { | ||
205 | - qatomic_set(&cpu->tb_jmp_cache[i0 + i], NULL); | ||
206 | + qatomic_set(&jc->array[i0 + i].tb, NULL); | ||
207 | } | ||
208 | } | ||
209 | |||
210 | @@ -XXX,XX +XXX,XX @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data) | ||
211 | |||
212 | qemu_spin_unlock(&env_tlb(env)->c.lock); | ||
213 | |||
214 | - cpu_tb_jmp_cache_clear(cpu); | ||
215 | + tcg_flush_jmp_cache(cpu); | ||
216 | |||
217 | if (to_clean == ALL_MMUIDX_BITS) { | ||
218 | qatomic_set(&env_tlb(env)->c.full_flush_count, | ||
219 | @@ -XXX,XX +XXX,XX @@ static void tlb_flush_range_by_mmuidx_async_0(CPUState *cpu, | ||
220 | * longer to clear each entry individually than it will to clear it all. | ||
221 | */ | ||
222 | if (d.len >= (TARGET_PAGE_SIZE * TB_JMP_CACHE_SIZE)) { | ||
223 | - cpu_tb_jmp_cache_clear(cpu); | ||
224 | + tcg_flush_jmp_cache(cpu); | ||
225 | return; | ||
226 | } | ||
227 | |||
228 | diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c | ||
229 | index XXXXXXX..XXXXXXX 100644 | ||
230 | --- a/accel/tcg/translate-all.c | ||
231 | +++ b/accel/tcg/translate-all.c | ||
232 | @@ -XXX,XX +XXX,XX @@ | ||
233 | #include "sysemu/tcg.h" | ||
234 | #include "qapi/error.h" | ||
235 | #include "hw/core/tcg-cpu-ops.h" | ||
236 | +#include "tb-jmp-cache.h" | ||
237 | #include "tb-hash.h" | ||
238 | #include "tb-context.h" | ||
239 | #include "internal.h" | ||
240 | @@ -XXX,XX +XXX,XX @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count) | ||
241 | } | ||
242 | |||
243 | CPU_FOREACH(cpu) { | ||
244 | - cpu_tb_jmp_cache_clear(cpu); | ||
245 | + tcg_flush_jmp_cache(cpu); | ||
246 | } | ||
247 | |||
248 | qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE); | ||
249 | @@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) | ||
250 | /* remove the TB from the hash list */ | ||
251 | h = tb_jmp_cache_hash_func(tb->pc); | ||
252 | CPU_FOREACH(cpu) { | ||
253 | - if (qatomic_read(&cpu->tb_jmp_cache[h]) == tb) { | ||
254 | - qatomic_set(&cpu->tb_jmp_cache[h], NULL); | ||
255 | + CPUJumpCache *jc = cpu->tb_jmp_cache; | ||
256 | + if (qatomic_read(&jc->array[h].tb) == tb) { | ||
257 | + qatomic_set(&jc->array[h].tb, NULL); | ||
258 | } | ||
259 | } | ||
260 | |||
261 | @@ -XXX,XX +XXX,XX @@ int page_unprotect(target_ulong address, uintptr_t pc) | ||
262 | } | ||
263 | #endif /* CONFIG_USER_ONLY */ | ||
264 | |||
265 | +/* | ||
266 | + * Called by generic code at e.g. cpu reset after cpu creation, | ||
267 | + * therefore we must be prepared to allocate the jump cache. | ||
268 | + */ | ||
269 | +void tcg_flush_jmp_cache(CPUState *cpu) | ||
270 | +{ | ||
271 | + CPUJumpCache *jc = cpu->tb_jmp_cache; | ||
272 | + | ||
273 | + if (likely(jc)) { | ||
274 | + for (int i = 0; i < TB_JMP_CACHE_SIZE; i++) { | ||
275 | + qatomic_set(&jc->array[i].tb, NULL); | ||
276 | + } | ||
277 | + } else { | ||
278 | + /* This should happen once during realize, and thus never race. */ | ||
279 | + jc = g_new0(CPUJumpCache, 1); | ||
280 | + jc = qatomic_xchg(&cpu->tb_jmp_cache, jc); | ||
281 | + assert(jc == NULL); | ||
282 | + } | ||
283 | +} | ||
284 | + | ||
285 | /* This is a wrapper for common code that can not use CONFIG_SOFTMMU */ | ||
286 | void tcg_flush_softmmu_tlb(CPUState *cs) | ||
287 | { | ||
288 | diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c | ||
289 | index XXXXXXX..XXXXXXX 100644 | ||
290 | --- a/hw/core/cpu-common.c | ||
291 | +++ b/hw/core/cpu-common.c | ||
292 | @@ -XXX,XX +XXX,XX @@ static void cpu_common_reset(DeviceState *dev) | ||
293 | cpu->cflags_next_tb = -1; | ||
294 | |||
295 | if (tcg_enabled()) { | ||
296 | - cpu_tb_jmp_cache_clear(cpu); | ||
297 | - | ||
298 | + tcg_flush_jmp_cache(cpu); | ||
299 | tcg_flush_softmmu_tlb(cpu); | ||
300 | } | ||
301 | } | ||
302 | diff --git a/plugins/core.c b/plugins/core.c | ||
303 | index XXXXXXX..XXXXXXX 100644 | ||
304 | --- a/plugins/core.c | ||
305 | +++ b/plugins/core.c | ||
306 | @@ -XXX,XX +XXX,XX @@ struct qemu_plugin_ctx *plugin_id_to_ctx_locked(qemu_plugin_id_t id) | ||
307 | static void plugin_cpu_update__async(CPUState *cpu, run_on_cpu_data data) | ||
308 | { | ||
309 | bitmap_copy(cpu->plugin_mask, &data.host_ulong, QEMU_PLUGIN_EV_MAX); | ||
310 | - cpu_tb_jmp_cache_clear(cpu); | ||
311 | + tcg_flush_jmp_cache(cpu); | ||
312 | } | ||
313 | |||
314 | static void plugin_cpu_update__locked(gpointer k, gpointer v, gpointer udata) | ||
315 | diff --git a/trace/control-target.c b/trace/control-target.c | ||
316 | index XXXXXXX..XXXXXXX 100644 | ||
317 | --- a/trace/control-target.c | ||
318 | +++ b/trace/control-target.c | ||
319 | @@ -XXX,XX +XXX,XX @@ static void trace_event_synchronize_vcpu_state_dynamic( | ||
320 | { | ||
321 | bitmap_copy(vcpu->trace_dstate, vcpu->trace_dstate_delayed, | ||
322 | CPU_TRACE_DSTATE_MAX_EVENTS); | ||
323 | - cpu_tb_jmp_cache_clear(vcpu); | ||
324 | + tcg_flush_jmp_cache(vcpu); | ||
325 | } | ||
326 | |||
327 | void trace_event_set_vcpu_state_dynamic(CPUState *vcpu, | ||
74 | -- | 328 | -- |
75 | 2.25.1 | 329 | 2.34.1 |
76 | 330 | ||
77 | 331 | diff view generated by jsdifflib |
1 | We already had support for rotlv, using a target-specific opcode; | 1 | Populate this new method for all targets. Always match |
---|---|---|---|
2 | convert to use the generic opcode. Handle rotrv via simple negation. | 2 | the result that would be given by cpu_get_tb_cpu_state, |
3 | as we will want these values to correspond in the logs. | ||
3 | 4 | ||
5 | Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> | ||
6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
7 | Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (target/sparc) | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | --- | 9 | --- |
6 | tcg/ppc/tcg-target.h | 2 +- | 10 | Cc: Eduardo Habkost <eduardo@habkost.net> (supporter:Machine core) |
7 | tcg/ppc/tcg-target.opc.h | 1 - | 11 | Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> (supporter:Machine core) |
8 | tcg/ppc/tcg-target.inc.c | 23 +++++++++++++++++++---- | 12 | Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org> (reviewer:Machine core) |
9 | 3 files changed, 20 insertions(+), 6 deletions(-) | 13 | Cc: Yanan Wang <wangyanan55@huawei.com> (reviewer:Machine core) |
14 | Cc: Michael Rolnik <mrolnik@gmail.com> (maintainer:AVR TCG CPUs) | ||
15 | Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> (maintainer:CRIS TCG CPUs) | ||
16 | Cc: Taylor Simpson <tsimpson@quicinc.com> (supporter:Hexagon TCG CPUs) | ||
17 | Cc: Song Gao <gaosong@loongson.cn> (maintainer:LoongArch TCG CPUs) | ||
18 | Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn> (maintainer:LoongArch TCG CPUs) | ||
19 | Cc: Laurent Vivier <laurent@vivier.eu> (maintainer:M68K TCG CPUs) | ||
20 | Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> (reviewer:MIPS TCG CPUs) | ||
21 | Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> (reviewer:MIPS TCG CPUs) | ||
22 | Cc: Chris Wulff <crwulff@gmail.com> (maintainer:NiosII TCG CPUs) | ||
23 | Cc: Marek Vasut <marex@denx.de> (maintainer:NiosII TCG CPUs) | ||
24 | Cc: Stafford Horne <shorne@gmail.com> (odd fixer:OpenRISC TCG CPUs) | ||
25 | Cc: Yoshinori Sato <ysato@users.sourceforge.jp> (reviewer:RENESAS RX CPUs) | ||
26 | Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (maintainer:SPARC TCG CPUs) | ||
27 | Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (maintainer:TriCore TCG CPUs) | ||
28 | Cc: Max Filippov <jcmvbkbc@gmail.com> (maintainer:Xtensa TCG CPUs) | ||
29 | Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs) | ||
30 | Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs) | ||
31 | Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) | ||
32 | Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs) | ||
33 | --- | ||
34 | include/hw/core/cpu.h | 3 +++ | ||
35 | target/alpha/cpu.c | 9 +++++++++ | ||
36 | target/arm/cpu.c | 13 +++++++++++++ | ||
37 | target/avr/cpu.c | 8 ++++++++ | ||
38 | target/cris/cpu.c | 8 ++++++++ | ||
39 | target/hexagon/cpu.c | 8 ++++++++ | ||
40 | target/hppa/cpu.c | 8 ++++++++ | ||
41 | target/i386/cpu.c | 9 +++++++++ | ||
42 | target/loongarch/cpu.c | 9 +++++++++ | ||
43 | target/m68k/cpu.c | 8 ++++++++ | ||
44 | target/microblaze/cpu.c | 8 ++++++++ | ||
45 | target/mips/cpu.c | 8 ++++++++ | ||
46 | target/nios2/cpu.c | 9 +++++++++ | ||
47 | target/openrisc/cpu.c | 8 ++++++++ | ||
48 | target/ppc/cpu_init.c | 8 ++++++++ | ||
49 | target/riscv/cpu.c | 13 +++++++++++++ | ||
50 | target/rx/cpu.c | 8 ++++++++ | ||
51 | target/s390x/cpu.c | 8 ++++++++ | ||
52 | target/sh4/cpu.c | 8 ++++++++ | ||
53 | target/sparc/cpu.c | 8 ++++++++ | ||
54 | target/tricore/cpu.c | 9 +++++++++ | ||
55 | target/xtensa/cpu.c | 8 ++++++++ | ||
56 | 22 files changed, 186 insertions(+) | ||
10 | 57 | ||
11 | diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h | 58 | diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h |
12 | index XXXXXXX..XXXXXXX 100644 | 59 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/tcg/ppc/tcg-target.h | 60 | --- a/include/hw/core/cpu.h |
14 | +++ b/tcg/ppc/tcg-target.h | 61 | +++ b/include/hw/core/cpu.h |
15 | @@ -XXX,XX +XXX,XX @@ extern bool have_vsx; | 62 | @@ -XXX,XX +XXX,XX @@ struct SysemuCPUOps; |
16 | #define TCG_TARGET_HAS_abs_vec 0 | 63 | * If the target behaviour here is anything other than "set |
17 | #define TCG_TARGET_HAS_roti_vec 0 | 64 | * the PC register to the value passed in" then the target must |
18 | #define TCG_TARGET_HAS_rots_vec 0 | 65 | * also implement the synchronize_from_tb hook. |
19 | -#define TCG_TARGET_HAS_rotv_vec 0 | 66 | + * @get_pc: Callback for getting the Program Counter register. |
20 | +#define TCG_TARGET_HAS_rotv_vec 1 | 67 | + * As above, with the semantics of the target architecture. |
21 | #define TCG_TARGET_HAS_shi_vec 0 | 68 | * @gdb_read_register: Callback for letting GDB read a register. |
22 | #define TCG_TARGET_HAS_shs_vec 0 | 69 | * @gdb_write_register: Callback for letting GDB write a register. |
23 | #define TCG_TARGET_HAS_shv_vec 1 | 70 | * @gdb_adjust_breakpoint: Callback for adjusting the address of a |
24 | diff --git a/tcg/ppc/tcg-target.opc.h b/tcg/ppc/tcg-target.opc.h | 71 | @@ -XXX,XX +XXX,XX @@ struct CPUClass { |
25 | index XXXXXXX..XXXXXXX 100644 | 72 | void (*dump_state)(CPUState *cpu, FILE *, int flags); |
26 | --- a/tcg/ppc/tcg-target.opc.h | 73 | int64_t (*get_arch_id)(CPUState *cpu); |
27 | +++ b/tcg/ppc/tcg-target.opc.h | 74 | void (*set_pc)(CPUState *cpu, vaddr value); |
28 | @@ -XXX,XX +XXX,XX @@ DEF(ppc_msum_vec, 1, 3, 0, IMPLVEC) | 75 | + vaddr (*get_pc)(CPUState *cpu); |
29 | DEF(ppc_muleu_vec, 1, 2, 0, IMPLVEC) | 76 | int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); |
30 | DEF(ppc_mulou_vec, 1, 2, 0, IMPLVEC) | 77 | int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); |
31 | DEF(ppc_pkum_vec, 1, 2, 0, IMPLVEC) | 78 | vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr); |
32 | -DEF(ppc_rotl_vec, 1, 2, 0, IMPLVEC) | 79 | diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c |
33 | diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c | 80 | index XXXXXXX..XXXXXXX 100644 |
34 | index XXXXXXX..XXXXXXX 100644 | 81 | --- a/target/alpha/cpu.c |
35 | --- a/tcg/ppc/tcg-target.inc.c | 82 | +++ b/target/alpha/cpu.c |
36 | +++ b/tcg/ppc/tcg-target.inc.c | 83 | @@ -XXX,XX +XXX,XX @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value) |
37 | @@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) | 84 | cpu->env.pc = value; |
38 | case INDEX_op_shlv_vec: | 85 | } |
39 | case INDEX_op_shrv_vec: | 86 | |
40 | case INDEX_op_sarv_vec: | 87 | +static vaddr alpha_cpu_get_pc(CPUState *cs) |
41 | + case INDEX_op_rotlv_vec: | 88 | +{ |
42 | return vece <= MO_32 || have_isa_2_07; | 89 | + AlphaCPU *cpu = ALPHA_CPU(cs); |
43 | case INDEX_op_ssadd_vec: | 90 | + |
44 | case INDEX_op_sssub_vec: | 91 | + return cpu->env.pc; |
45 | @@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) | 92 | +} |
46 | case INDEX_op_shli_vec: | 93 | + |
47 | case INDEX_op_shri_vec: | 94 | + |
48 | case INDEX_op_sari_vec: | 95 | static bool alpha_cpu_has_work(CPUState *cs) |
49 | + case INDEX_op_rotli_vec: | 96 | { |
50 | return vece <= MO_32 || have_isa_2_07 ? -1 : 0; | 97 | /* Here we are checking to see if the CPU should wake up from HALT. |
51 | case INDEX_op_neg_vec: | 98 | @@ -XXX,XX +XXX,XX @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) |
52 | return vece >= MO_32 && have_isa_3_00; | 99 | cc->has_work = alpha_cpu_has_work; |
53 | @@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) | 100 | cc->dump_state = alpha_cpu_dump_state; |
54 | return 0; | 101 | cc->set_pc = alpha_cpu_set_pc; |
55 | case INDEX_op_bitsel_vec: | 102 | + cc->get_pc = alpha_cpu_get_pc; |
56 | return have_vsx; | 103 | cc->gdb_read_register = alpha_cpu_gdb_read_register; |
57 | + case INDEX_op_rotrv_vec: | 104 | cc->gdb_write_register = alpha_cpu_gdb_write_register; |
58 | + return -1; | 105 | #ifndef CONFIG_USER_ONLY |
59 | default: | 106 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
60 | return 0; | 107 | index XXXXXXX..XXXXXXX 100644 |
108 | --- a/target/arm/cpu.c | ||
109 | +++ b/target/arm/cpu.c | ||
110 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) | ||
61 | } | 111 | } |
62 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, | 112 | } |
63 | case INDEX_op_ppc_pkum_vec: | 113 | |
64 | insn = pkum_op[vece]; | 114 | +static vaddr arm_cpu_get_pc(CPUState *cs) |
65 | break; | 115 | +{ |
66 | - case INDEX_op_ppc_rotl_vec: | 116 | + ARMCPU *cpu = ARM_CPU(cs); |
67 | + case INDEX_op_rotlv_vec: | 117 | + CPUARMState *env = &cpu->env; |
68 | insn = rotl_op[vece]; | 118 | + |
69 | break; | 119 | + if (is_a64(env)) { |
70 | case INDEX_op_ppc_msum_vec: | 120 | + return env->pc; |
71 | @@ -XXX,XX +XXX,XX @@ static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, | 121 | + } else { |
72 | t3 = tcg_temp_new_vec(type); | 122 | + return env->regs[15]; |
73 | t4 = tcg_temp_new_vec(type); | 123 | + } |
74 | tcg_gen_dupi_vec(MO_8, t4, -16); | 124 | +} |
75 | - vec_gen_3(INDEX_op_ppc_rotl_vec, type, MO_32, tcgv_vec_arg(t1), | 125 | + |
76 | + vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1), | 126 | #ifdef CONFIG_TCG |
77 | tcgv_vec_arg(v2), tcgv_vec_arg(t4)); | 127 | void arm_cpu_synchronize_from_tb(CPUState *cs, |
78 | vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2), | 128 | const TranslationBlock *tb) |
79 | tcgv_vec_arg(v1), tcgv_vec_arg(v2)); | 129 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) |
80 | @@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, | 130 | cc->has_work = arm_cpu_has_work; |
81 | TCGArg a0, ...) | 131 | cc->dump_state = arm_cpu_dump_state; |
82 | { | 132 | cc->set_pc = arm_cpu_set_pc; |
83 | va_list va; | 133 | + cc->get_pc = arm_cpu_get_pc; |
84 | - TCGv_vec v0, v1, v2; | 134 | cc->gdb_read_register = arm_cpu_gdb_read_register; |
85 | + TCGv_vec v0, v1, v2, t0; | 135 | cc->gdb_write_register = arm_cpu_gdb_write_register; |
86 | TCGArg a2; | 136 | #ifndef CONFIG_USER_ONLY |
87 | 137 | diff --git a/target/avr/cpu.c b/target/avr/cpu.c | |
88 | va_start(va, a0); | 138 | index XXXXXXX..XXXXXXX 100644 |
89 | @@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, | 139 | --- a/target/avr/cpu.c |
90 | case INDEX_op_sari_vec: | 140 | +++ b/target/avr/cpu.c |
91 | expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec); | 141 | @@ -XXX,XX +XXX,XX @@ static void avr_cpu_set_pc(CPUState *cs, vaddr value) |
92 | break; | 142 | cpu->env.pc_w = value / 2; /* internally PC points to words */ |
93 | + case INDEX_op_rotli_vec: | 143 | } |
94 | + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec); | 144 | |
95 | + break; | 145 | +static vaddr avr_cpu_get_pc(CPUState *cs) |
96 | case INDEX_op_cmp_vec: | 146 | +{ |
97 | v2 = temp_tcgv_vec(arg_temp(a2)); | 147 | + AVRCPU *cpu = AVR_CPU(cs); |
98 | expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); | 148 | + |
99 | @@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, | 149 | + return cpu->env.pc_w * 2; |
100 | v2 = temp_tcgv_vec(arg_temp(a2)); | 150 | +} |
101 | expand_vec_mul(type, vece, v0, v1, v2); | 151 | + |
102 | break; | 152 | static bool avr_cpu_has_work(CPUState *cs) |
103 | + case INDEX_op_rotlv_vec: | 153 | { |
104 | + v2 = temp_tcgv_vec(arg_temp(a2)); | 154 | AVRCPU *cpu = AVR_CPU(cs); |
105 | + t0 = tcg_temp_new_vec(type); | 155 | @@ -XXX,XX +XXX,XX @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) |
106 | + tcg_gen_neg_vec(vece, t0, v2); | 156 | cc->has_work = avr_cpu_has_work; |
107 | + tcg_gen_rotlv_vec(vece, v0, v1, t0); | 157 | cc->dump_state = avr_cpu_dump_state; |
108 | + tcg_temp_free_vec(t0); | 158 | cc->set_pc = avr_cpu_set_pc; |
109 | + break; | 159 | + cc->get_pc = avr_cpu_get_pc; |
110 | default: | 160 | dc->vmsd = &vms_avr_cpu; |
111 | g_assert_not_reached(); | 161 | cc->sysemu_ops = &avr_sysemu_ops; |
162 | cc->disas_set_info = avr_cpu_disas_set_info; | ||
163 | diff --git a/target/cris/cpu.c b/target/cris/cpu.c | ||
164 | index XXXXXXX..XXXXXXX 100644 | ||
165 | --- a/target/cris/cpu.c | ||
166 | +++ b/target/cris/cpu.c | ||
167 | @@ -XXX,XX +XXX,XX @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value) | ||
168 | cpu->env.pc = value; | ||
169 | } | ||
170 | |||
171 | +static vaddr cris_cpu_get_pc(CPUState *cs) | ||
172 | +{ | ||
173 | + CRISCPU *cpu = CRIS_CPU(cs); | ||
174 | + | ||
175 | + return cpu->env.pc; | ||
176 | +} | ||
177 | + | ||
178 | static bool cris_cpu_has_work(CPUState *cs) | ||
179 | { | ||
180 | return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); | ||
181 | @@ -XXX,XX +XXX,XX @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) | ||
182 | cc->has_work = cris_cpu_has_work; | ||
183 | cc->dump_state = cris_cpu_dump_state; | ||
184 | cc->set_pc = cris_cpu_set_pc; | ||
185 | + cc->get_pc = cris_cpu_get_pc; | ||
186 | cc->gdb_read_register = cris_cpu_gdb_read_register; | ||
187 | cc->gdb_write_register = cris_cpu_gdb_write_register; | ||
188 | #ifndef CONFIG_USER_ONLY | ||
189 | diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c | ||
190 | index XXXXXXX..XXXXXXX 100644 | ||
191 | --- a/target/hexagon/cpu.c | ||
192 | +++ b/target/hexagon/cpu.c | ||
193 | @@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_set_pc(CPUState *cs, vaddr value) | ||
194 | env->gpr[HEX_REG_PC] = value; | ||
195 | } | ||
196 | |||
197 | +static vaddr hexagon_cpu_get_pc(CPUState *cs) | ||
198 | +{ | ||
199 | + HexagonCPU *cpu = HEXAGON_CPU(cs); | ||
200 | + CPUHexagonState *env = &cpu->env; | ||
201 | + return env->gpr[HEX_REG_PC]; | ||
202 | +} | ||
203 | + | ||
204 | static void hexagon_cpu_synchronize_from_tb(CPUState *cs, | ||
205 | const TranslationBlock *tb) | ||
206 | { | ||
207 | @@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data) | ||
208 | cc->has_work = hexagon_cpu_has_work; | ||
209 | cc->dump_state = hexagon_dump_state; | ||
210 | cc->set_pc = hexagon_cpu_set_pc; | ||
211 | + cc->get_pc = hexagon_cpu_get_pc; | ||
212 | cc->gdb_read_register = hexagon_gdb_read_register; | ||
213 | cc->gdb_write_register = hexagon_gdb_write_register; | ||
214 | cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS + NUM_VREGS + NUM_QREGS; | ||
215 | diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c | ||
216 | index XXXXXXX..XXXXXXX 100644 | ||
217 | --- a/target/hppa/cpu.c | ||
218 | +++ b/target/hppa/cpu.c | ||
219 | @@ -XXX,XX +XXX,XX @@ static void hppa_cpu_set_pc(CPUState *cs, vaddr value) | ||
220 | cpu->env.iaoq_b = value + 4; | ||
221 | } | ||
222 | |||
223 | +static vaddr hppa_cpu_get_pc(CPUState *cs) | ||
224 | +{ | ||
225 | + HPPACPU *cpu = HPPA_CPU(cs); | ||
226 | + | ||
227 | + return cpu->env.iaoq_f; | ||
228 | +} | ||
229 | + | ||
230 | static void hppa_cpu_synchronize_from_tb(CPUState *cs, | ||
231 | const TranslationBlock *tb) | ||
232 | { | ||
233 | @@ -XXX,XX +XXX,XX @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) | ||
234 | cc->has_work = hppa_cpu_has_work; | ||
235 | cc->dump_state = hppa_cpu_dump_state; | ||
236 | cc->set_pc = hppa_cpu_set_pc; | ||
237 | + cc->get_pc = hppa_cpu_get_pc; | ||
238 | cc->gdb_read_register = hppa_cpu_gdb_read_register; | ||
239 | cc->gdb_write_register = hppa_cpu_gdb_write_register; | ||
240 | #ifndef CONFIG_USER_ONLY | ||
241 | diff --git a/target/i386/cpu.c b/target/i386/cpu.c | ||
242 | index XXXXXXX..XXXXXXX 100644 | ||
243 | --- a/target/i386/cpu.c | ||
244 | +++ b/target/i386/cpu.c | ||
245 | @@ -XXX,XX +XXX,XX @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value) | ||
246 | cpu->env.eip = value; | ||
247 | } | ||
248 | |||
249 | +static vaddr x86_cpu_get_pc(CPUState *cs) | ||
250 | +{ | ||
251 | + X86CPU *cpu = X86_CPU(cs); | ||
252 | + | ||
253 | + /* Match cpu_get_tb_cpu_state. */ | ||
254 | + return cpu->env.eip + cpu->env.segs[R_CS].base; | ||
255 | +} | ||
256 | + | ||
257 | int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) | ||
258 | { | ||
259 | X86CPU *cpu = X86_CPU(cs); | ||
260 | @@ -XXX,XX +XXX,XX @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) | ||
261 | cc->has_work = x86_cpu_has_work; | ||
262 | cc->dump_state = x86_cpu_dump_state; | ||
263 | cc->set_pc = x86_cpu_set_pc; | ||
264 | + cc->get_pc = x86_cpu_get_pc; | ||
265 | cc->gdb_read_register = x86_cpu_gdb_read_register; | ||
266 | cc->gdb_write_register = x86_cpu_gdb_write_register; | ||
267 | cc->get_arch_id = x86_cpu_get_arch_id; | ||
268 | diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c | ||
269 | index XXXXXXX..XXXXXXX 100644 | ||
270 | --- a/target/loongarch/cpu.c | ||
271 | +++ b/target/loongarch/cpu.c | ||
272 | @@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) | ||
273 | env->pc = value; | ||
274 | } | ||
275 | |||
276 | +static vaddr loongarch_cpu_get_pc(CPUState *cs) | ||
277 | +{ | ||
278 | + LoongArchCPU *cpu = LOONGARCH_CPU(cs); | ||
279 | + CPULoongArchState *env = &cpu->env; | ||
280 | + | ||
281 | + return env->pc; | ||
282 | +} | ||
283 | + | ||
284 | #ifndef CONFIG_USER_ONLY | ||
285 | #include "hw/loongarch/virt.h" | ||
286 | |||
287 | @@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data) | ||
288 | cc->has_work = loongarch_cpu_has_work; | ||
289 | cc->dump_state = loongarch_cpu_dump_state; | ||
290 | cc->set_pc = loongarch_cpu_set_pc; | ||
291 | + cc->get_pc = loongarch_cpu_get_pc; | ||
292 | #ifndef CONFIG_USER_ONLY | ||
293 | dc->vmsd = &vmstate_loongarch_cpu; | ||
294 | cc->sysemu_ops = &loongarch_sysemu_ops; | ||
295 | diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c | ||
296 | index XXXXXXX..XXXXXXX 100644 | ||
297 | --- a/target/m68k/cpu.c | ||
298 | +++ b/target/m68k/cpu.c | ||
299 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_set_pc(CPUState *cs, vaddr value) | ||
300 | cpu->env.pc = value; | ||
301 | } | ||
302 | |||
303 | +static vaddr m68k_cpu_get_pc(CPUState *cs) | ||
304 | +{ | ||
305 | + M68kCPU *cpu = M68K_CPU(cs); | ||
306 | + | ||
307 | + return cpu->env.pc; | ||
308 | +} | ||
309 | + | ||
310 | static bool m68k_cpu_has_work(CPUState *cs) | ||
311 | { | ||
312 | return cs->interrupt_request & CPU_INTERRUPT_HARD; | ||
313 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) | ||
314 | cc->has_work = m68k_cpu_has_work; | ||
315 | cc->dump_state = m68k_cpu_dump_state; | ||
316 | cc->set_pc = m68k_cpu_set_pc; | ||
317 | + cc->get_pc = m68k_cpu_get_pc; | ||
318 | cc->gdb_read_register = m68k_cpu_gdb_read_register; | ||
319 | cc->gdb_write_register = m68k_cpu_gdb_write_register; | ||
320 | #if defined(CONFIG_SOFTMMU) | ||
321 | diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c | ||
322 | index XXXXXXX..XXXXXXX 100644 | ||
323 | --- a/target/microblaze/cpu.c | ||
324 | +++ b/target/microblaze/cpu.c | ||
325 | @@ -XXX,XX +XXX,XX @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value) | ||
326 | cpu->env.iflags = 0; | ||
327 | } | ||
328 | |||
329 | +static vaddr mb_cpu_get_pc(CPUState *cs) | ||
330 | +{ | ||
331 | + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); | ||
332 | + | ||
333 | + return cpu->env.pc; | ||
334 | +} | ||
335 | + | ||
336 | static void mb_cpu_synchronize_from_tb(CPUState *cs, | ||
337 | const TranslationBlock *tb) | ||
338 | { | ||
339 | @@ -XXX,XX +XXX,XX @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) | ||
340 | |||
341 | cc->dump_state = mb_cpu_dump_state; | ||
342 | cc->set_pc = mb_cpu_set_pc; | ||
343 | + cc->get_pc = mb_cpu_get_pc; | ||
344 | cc->gdb_read_register = mb_cpu_gdb_read_register; | ||
345 | cc->gdb_write_register = mb_cpu_gdb_write_register; | ||
346 | |||
347 | diff --git a/target/mips/cpu.c b/target/mips/cpu.c | ||
348 | index XXXXXXX..XXXXXXX 100644 | ||
349 | --- a/target/mips/cpu.c | ||
350 | +++ b/target/mips/cpu.c | ||
351 | @@ -XXX,XX +XXX,XX @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value) | ||
352 | mips_env_set_pc(&cpu->env, value); | ||
353 | } | ||
354 | |||
355 | +static vaddr mips_cpu_get_pc(CPUState *cs) | ||
356 | +{ | ||
357 | + MIPSCPU *cpu = MIPS_CPU(cs); | ||
358 | + | ||
359 | + return cpu->env.active_tc.PC; | ||
360 | +} | ||
361 | + | ||
362 | static bool mips_cpu_has_work(CPUState *cs) | ||
363 | { | ||
364 | MIPSCPU *cpu = MIPS_CPU(cs); | ||
365 | @@ -XXX,XX +XXX,XX @@ static void mips_cpu_class_init(ObjectClass *c, void *data) | ||
366 | cc->has_work = mips_cpu_has_work; | ||
367 | cc->dump_state = mips_cpu_dump_state; | ||
368 | cc->set_pc = mips_cpu_set_pc; | ||
369 | + cc->get_pc = mips_cpu_get_pc; | ||
370 | cc->gdb_read_register = mips_cpu_gdb_read_register; | ||
371 | cc->gdb_write_register = mips_cpu_gdb_write_register; | ||
372 | #ifndef CONFIG_USER_ONLY | ||
373 | diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c | ||
374 | index XXXXXXX..XXXXXXX 100644 | ||
375 | --- a/target/nios2/cpu.c | ||
376 | +++ b/target/nios2/cpu.c | ||
377 | @@ -XXX,XX +XXX,XX @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value) | ||
378 | env->pc = value; | ||
379 | } | ||
380 | |||
381 | +static vaddr nios2_cpu_get_pc(CPUState *cs) | ||
382 | +{ | ||
383 | + Nios2CPU *cpu = NIOS2_CPU(cs); | ||
384 | + CPUNios2State *env = &cpu->env; | ||
385 | + | ||
386 | + return env->pc; | ||
387 | +} | ||
388 | + | ||
389 | static bool nios2_cpu_has_work(CPUState *cs) | ||
390 | { | ||
391 | return cs->interrupt_request & CPU_INTERRUPT_HARD; | ||
392 | @@ -XXX,XX +XXX,XX @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data) | ||
393 | cc->has_work = nios2_cpu_has_work; | ||
394 | cc->dump_state = nios2_cpu_dump_state; | ||
395 | cc->set_pc = nios2_cpu_set_pc; | ||
396 | + cc->get_pc = nios2_cpu_get_pc; | ||
397 | cc->disas_set_info = nios2_cpu_disas_set_info; | ||
398 | #ifndef CONFIG_USER_ONLY | ||
399 | cc->sysemu_ops = &nios2_sysemu_ops; | ||
400 | diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c | ||
401 | index XXXXXXX..XXXXXXX 100644 | ||
402 | --- a/target/openrisc/cpu.c | ||
403 | +++ b/target/openrisc/cpu.c | ||
404 | @@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) | ||
405 | cpu->env.dflag = 0; | ||
406 | } | ||
407 | |||
408 | +static vaddr openrisc_cpu_get_pc(CPUState *cs) | ||
409 | +{ | ||
410 | + OpenRISCCPU *cpu = OPENRISC_CPU(cs); | ||
411 | + | ||
412 | + return cpu->env.pc; | ||
413 | +} | ||
414 | + | ||
415 | static void openrisc_cpu_synchronize_from_tb(CPUState *cs, | ||
416 | const TranslationBlock *tb) | ||
417 | { | ||
418 | @@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) | ||
419 | cc->has_work = openrisc_cpu_has_work; | ||
420 | cc->dump_state = openrisc_cpu_dump_state; | ||
421 | cc->set_pc = openrisc_cpu_set_pc; | ||
422 | + cc->get_pc = openrisc_cpu_get_pc; | ||
423 | cc->gdb_read_register = openrisc_cpu_gdb_read_register; | ||
424 | cc->gdb_write_register = openrisc_cpu_gdb_write_register; | ||
425 | #ifndef CONFIG_USER_ONLY | ||
426 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c | ||
427 | index XXXXXXX..XXXXXXX 100644 | ||
428 | --- a/target/ppc/cpu_init.c | ||
429 | +++ b/target/ppc/cpu_init.c | ||
430 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value) | ||
431 | cpu->env.nip = value; | ||
432 | } | ||
433 | |||
434 | +static vaddr ppc_cpu_get_pc(CPUState *cs) | ||
435 | +{ | ||
436 | + PowerPCCPU *cpu = POWERPC_CPU(cs); | ||
437 | + | ||
438 | + return cpu->env.nip; | ||
439 | +} | ||
440 | + | ||
441 | static bool ppc_cpu_has_work(CPUState *cs) | ||
442 | { | ||
443 | PowerPCCPU *cpu = POWERPC_CPU(cs); | ||
444 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) | ||
445 | cc->has_work = ppc_cpu_has_work; | ||
446 | cc->dump_state = ppc_cpu_dump_state; | ||
447 | cc->set_pc = ppc_cpu_set_pc; | ||
448 | + cc->get_pc = ppc_cpu_get_pc; | ||
449 | cc->gdb_read_register = ppc_cpu_gdb_read_register; | ||
450 | cc->gdb_write_register = ppc_cpu_gdb_write_register; | ||
451 | #ifndef CONFIG_USER_ONLY | ||
452 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
453 | index XXXXXXX..XXXXXXX 100644 | ||
454 | --- a/target/riscv/cpu.c | ||
455 | +++ b/target/riscv/cpu.c | ||
456 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value) | ||
112 | } | 457 | } |
113 | @@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) | 458 | } |
114 | case INDEX_op_shlv_vec: | 459 | |
115 | case INDEX_op_shrv_vec: | 460 | +static vaddr riscv_cpu_get_pc(CPUState *cs) |
116 | case INDEX_op_sarv_vec: | 461 | +{ |
117 | + case INDEX_op_rotlv_vec: | 462 | + RISCVCPU *cpu = RISCV_CPU(cs); |
118 | + case INDEX_op_rotrv_vec: | 463 | + CPURISCVState *env = &cpu->env; |
119 | case INDEX_op_ppc_mrgh_vec: | 464 | + |
120 | case INDEX_op_ppc_mrgl_vec: | 465 | + /* Match cpu_get_tb_cpu_state. */ |
121 | case INDEX_op_ppc_muleu_vec: | 466 | + if (env->xl == MXL_RV32) { |
122 | case INDEX_op_ppc_mulou_vec: | 467 | + return env->pc & UINT32_MAX; |
123 | case INDEX_op_ppc_pkum_vec: | 468 | + } |
124 | - case INDEX_op_ppc_rotl_vec: | 469 | + return env->pc; |
125 | case INDEX_op_dup2_vec: | 470 | +} |
126 | return &v_v_v; | 471 | + |
127 | case INDEX_op_not_vec: | 472 | static void riscv_cpu_synchronize_from_tb(CPUState *cs, |
473 | const TranslationBlock *tb) | ||
474 | { | ||
475 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) | ||
476 | cc->has_work = riscv_cpu_has_work; | ||
477 | cc->dump_state = riscv_cpu_dump_state; | ||
478 | cc->set_pc = riscv_cpu_set_pc; | ||
479 | + cc->get_pc = riscv_cpu_get_pc; | ||
480 | cc->gdb_read_register = riscv_cpu_gdb_read_register; | ||
481 | cc->gdb_write_register = riscv_cpu_gdb_write_register; | ||
482 | cc->gdb_num_core_regs = 33; | ||
483 | diff --git a/target/rx/cpu.c b/target/rx/cpu.c | ||
484 | index XXXXXXX..XXXXXXX 100644 | ||
485 | --- a/target/rx/cpu.c | ||
486 | +++ b/target/rx/cpu.c | ||
487 | @@ -XXX,XX +XXX,XX @@ static void rx_cpu_set_pc(CPUState *cs, vaddr value) | ||
488 | cpu->env.pc = value; | ||
489 | } | ||
490 | |||
491 | +static vaddr rx_cpu_get_pc(CPUState *cs) | ||
492 | +{ | ||
493 | + RXCPU *cpu = RX_CPU(cs); | ||
494 | + | ||
495 | + return cpu->env.pc; | ||
496 | +} | ||
497 | + | ||
498 | static void rx_cpu_synchronize_from_tb(CPUState *cs, | ||
499 | const TranslationBlock *tb) | ||
500 | { | ||
501 | @@ -XXX,XX +XXX,XX @@ static void rx_cpu_class_init(ObjectClass *klass, void *data) | ||
502 | cc->has_work = rx_cpu_has_work; | ||
503 | cc->dump_state = rx_cpu_dump_state; | ||
504 | cc->set_pc = rx_cpu_set_pc; | ||
505 | + cc->get_pc = rx_cpu_get_pc; | ||
506 | |||
507 | #ifndef CONFIG_USER_ONLY | ||
508 | cc->sysemu_ops = &rx_sysemu_ops; | ||
509 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c | ||
510 | index XXXXXXX..XXXXXXX 100644 | ||
511 | --- a/target/s390x/cpu.c | ||
512 | +++ b/target/s390x/cpu.c | ||
513 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value) | ||
514 | cpu->env.psw.addr = value; | ||
515 | } | ||
516 | |||
517 | +static vaddr s390_cpu_get_pc(CPUState *cs) | ||
518 | +{ | ||
519 | + S390CPU *cpu = S390_CPU(cs); | ||
520 | + | ||
521 | + return cpu->env.psw.addr; | ||
522 | +} | ||
523 | + | ||
524 | static bool s390_cpu_has_work(CPUState *cs) | ||
525 | { | ||
526 | S390CPU *cpu = S390_CPU(cs); | ||
527 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) | ||
528 | cc->has_work = s390_cpu_has_work; | ||
529 | cc->dump_state = s390_cpu_dump_state; | ||
530 | cc->set_pc = s390_cpu_set_pc; | ||
531 | + cc->get_pc = s390_cpu_get_pc; | ||
532 | cc->gdb_read_register = s390_cpu_gdb_read_register; | ||
533 | cc->gdb_write_register = s390_cpu_gdb_write_register; | ||
534 | #ifndef CONFIG_USER_ONLY | ||
535 | diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c | ||
536 | index XXXXXXX..XXXXXXX 100644 | ||
537 | --- a/target/sh4/cpu.c | ||
538 | +++ b/target/sh4/cpu.c | ||
539 | @@ -XXX,XX +XXX,XX @@ static void superh_cpu_set_pc(CPUState *cs, vaddr value) | ||
540 | cpu->env.pc = value; | ||
541 | } | ||
542 | |||
543 | +static vaddr superh_cpu_get_pc(CPUState *cs) | ||
544 | +{ | ||
545 | + SuperHCPU *cpu = SUPERH_CPU(cs); | ||
546 | + | ||
547 | + return cpu->env.pc; | ||
548 | +} | ||
549 | + | ||
550 | static void superh_cpu_synchronize_from_tb(CPUState *cs, | ||
551 | const TranslationBlock *tb) | ||
552 | { | ||
553 | @@ -XXX,XX +XXX,XX @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) | ||
554 | cc->has_work = superh_cpu_has_work; | ||
555 | cc->dump_state = superh_cpu_dump_state; | ||
556 | cc->set_pc = superh_cpu_set_pc; | ||
557 | + cc->get_pc = superh_cpu_get_pc; | ||
558 | cc->gdb_read_register = superh_cpu_gdb_read_register; | ||
559 | cc->gdb_write_register = superh_cpu_gdb_write_register; | ||
560 | #ifndef CONFIG_USER_ONLY | ||
561 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c | ||
562 | index XXXXXXX..XXXXXXX 100644 | ||
563 | --- a/target/sparc/cpu.c | ||
564 | +++ b/target/sparc/cpu.c | ||
565 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_set_pc(CPUState *cs, vaddr value) | ||
566 | cpu->env.npc = value + 4; | ||
567 | } | ||
568 | |||
569 | +static vaddr sparc_cpu_get_pc(CPUState *cs) | ||
570 | +{ | ||
571 | + SPARCCPU *cpu = SPARC_CPU(cs); | ||
572 | + | ||
573 | + return cpu->env.pc; | ||
574 | +} | ||
575 | + | ||
576 | static void sparc_cpu_synchronize_from_tb(CPUState *cs, | ||
577 | const TranslationBlock *tb) | ||
578 | { | ||
579 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) | ||
580 | cc->memory_rw_debug = sparc_cpu_memory_rw_debug; | ||
581 | #endif | ||
582 | cc->set_pc = sparc_cpu_set_pc; | ||
583 | + cc->get_pc = sparc_cpu_get_pc; | ||
584 | cc->gdb_read_register = sparc_cpu_gdb_read_register; | ||
585 | cc->gdb_write_register = sparc_cpu_gdb_write_register; | ||
586 | #ifndef CONFIG_USER_ONLY | ||
587 | diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c | ||
588 | index XXXXXXX..XXXXXXX 100644 | ||
589 | --- a/target/tricore/cpu.c | ||
590 | +++ b/target/tricore/cpu.c | ||
591 | @@ -XXX,XX +XXX,XX @@ static void tricore_cpu_set_pc(CPUState *cs, vaddr value) | ||
592 | env->PC = value & ~(target_ulong)1; | ||
593 | } | ||
594 | |||
595 | +static vaddr tricore_cpu_get_pc(CPUState *cs) | ||
596 | +{ | ||
597 | + TriCoreCPU *cpu = TRICORE_CPU(cs); | ||
598 | + CPUTriCoreState *env = &cpu->env; | ||
599 | + | ||
600 | + return env->PC; | ||
601 | +} | ||
602 | + | ||
603 | static void tricore_cpu_synchronize_from_tb(CPUState *cs, | ||
604 | const TranslationBlock *tb) | ||
605 | { | ||
606 | @@ -XXX,XX +XXX,XX @@ static void tricore_cpu_class_init(ObjectClass *c, void *data) | ||
607 | |||
608 | cc->dump_state = tricore_cpu_dump_state; | ||
609 | cc->set_pc = tricore_cpu_set_pc; | ||
610 | + cc->get_pc = tricore_cpu_get_pc; | ||
611 | cc->sysemu_ops = &tricore_sysemu_ops; | ||
612 | cc->tcg_ops = &tricore_tcg_ops; | ||
613 | } | ||
614 | diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c | ||
615 | index XXXXXXX..XXXXXXX 100644 | ||
616 | --- a/target/xtensa/cpu.c | ||
617 | +++ b/target/xtensa/cpu.c | ||
618 | @@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) | ||
619 | cpu->env.pc = value; | ||
620 | } | ||
621 | |||
622 | +static vaddr xtensa_cpu_get_pc(CPUState *cs) | ||
623 | +{ | ||
624 | + XtensaCPU *cpu = XTENSA_CPU(cs); | ||
625 | + | ||
626 | + return cpu->env.pc; | ||
627 | +} | ||
628 | + | ||
629 | static bool xtensa_cpu_has_work(CPUState *cs) | ||
630 | { | ||
631 | #ifndef CONFIG_USER_ONLY | ||
632 | @@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) | ||
633 | cc->has_work = xtensa_cpu_has_work; | ||
634 | cc->dump_state = xtensa_cpu_dump_state; | ||
635 | cc->set_pc = xtensa_cpu_set_pc; | ||
636 | + cc->get_pc = xtensa_cpu_get_pc; | ||
637 | cc->gdb_read_register = xtensa_cpu_gdb_read_register; | ||
638 | cc->gdb_write_register = xtensa_cpu_gdb_write_register; | ||
639 | cc->gdb_stop_before_watchpoint = true; | ||
128 | -- | 640 | -- |
129 | 2.25.1 | 641 | 2.34.1 |
130 | 642 | ||
131 | 643 | diff view generated by jsdifflib |
1 | No host backend support yet, but the interfaces for rotlv | 1 | The availability of tb->pc will shortly be conditional. |
---|---|---|---|
2 | and rotrv are in place. | 2 | Introduce accessor functions to minimize ifdefs. |
3 | |||
4 | Pass around a known pc to places like tcg_gen_code, | ||
5 | where the caller must already have the value. | ||
3 | 6 | ||
4 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | --- | 9 | --- |
7 | v3: Drop the generic expansion from rot to shift; we can do better | 10 | accel/tcg/internal.h | 6 ++++ |
8 | for each backend, and then this code becomes unused. | 11 | include/exec/exec-all.h | 6 ++++ |
9 | --- | 12 | include/tcg/tcg.h | 2 +- |
10 | accel/tcg/tcg-runtime.h | 10 +++ | 13 | accel/tcg/cpu-exec.c | 46 ++++++++++++++----------- |
11 | include/tcg/tcg-op-gvec.h | 4 ++ | 14 | accel/tcg/translate-all.c | 37 +++++++++++--------- |
12 | include/tcg/tcg-op.h | 2 + | 15 | target/arm/cpu.c | 4 +-- |
13 | include/tcg/tcg-opc.h | 2 + | 16 | target/avr/cpu.c | 2 +- |
14 | include/tcg/tcg.h | 1 + | 17 | target/hexagon/cpu.c | 2 +- |
15 | tcg/aarch64/tcg-target.h | 1 + | 18 | target/hppa/cpu.c | 4 +-- |
16 | tcg/i386/tcg-target.h | 1 + | 19 | target/i386/tcg/tcg-cpu.c | 2 +- |
17 | tcg/ppc/tcg-target.h | 1 + | 20 | target/loongarch/cpu.c | 2 +- |
18 | accel/tcg/tcg-runtime-gvec.c | 96 +++++++++++++++++++++++++++ | 21 | target/microblaze/cpu.c | 2 +- |
19 | tcg/tcg-op-gvec.c | 122 +++++++++++++++++++++++++++++++++++ | 22 | target/mips/tcg/exception.c | 2 +- |
20 | tcg/tcg-op-vec.c | 10 +++ | 23 | target/mips/tcg/sysemu/special_helper.c | 2 +- |
21 | tcg/tcg.c | 3 + | 24 | target/openrisc/cpu.c | 2 +- |
22 | tcg/README | 4 +- | 25 | target/riscv/cpu.c | 4 +-- |
23 | 13 files changed, 256 insertions(+), 1 deletion(-) | 26 | target/rx/cpu.c | 2 +- |
27 | target/sh4/cpu.c | 4 +-- | ||
28 | target/sparc/cpu.c | 2 +- | ||
29 | target/tricore/cpu.c | 2 +- | ||
30 | tcg/tcg.c | 8 ++--- | ||
31 | 21 files changed, 82 insertions(+), 61 deletions(-) | ||
24 | 32 | ||
25 | diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h | 33 | diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h |
26 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/accel/tcg/tcg-runtime.h | 35 | --- a/accel/tcg/internal.h |
28 | +++ b/accel/tcg/tcg-runtime.h | 36 | +++ b/accel/tcg/internal.h |
29 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(gvec_sar16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 37 | @@ -XXX,XX +XXX,XX @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); |
30 | DEF_HELPER_FLAGS_4(gvec_sar32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 38 | void page_init(void); |
31 | DEF_HELPER_FLAGS_4(gvec_sar64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 39 | void tb_htable_init(void); |
32 | 40 | ||
33 | +DEF_HELPER_FLAGS_4(gvec_rotl8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 41 | +/* Return the current PC from CPU, which may be cached in TB. */ |
34 | +DEF_HELPER_FLAGS_4(gvec_rotl16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 42 | +static inline target_ulong log_pc(CPUState *cpu, const TranslationBlock *tb) |
35 | +DEF_HELPER_FLAGS_4(gvec_rotl32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 43 | +{ |
36 | +DEF_HELPER_FLAGS_4(gvec_rotl64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 44 | + return tb_pc(tb); |
45 | +} | ||
37 | + | 46 | + |
38 | +DEF_HELPER_FLAGS_4(gvec_rotr8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 47 | #endif /* ACCEL_TCG_INTERNAL_H */ |
39 | +DEF_HELPER_FLAGS_4(gvec_rotr16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 48 | diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h |
40 | +DEF_HELPER_FLAGS_4(gvec_rotr32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 49 | index XXXXXXX..XXXXXXX 100644 |
41 | +DEF_HELPER_FLAGS_4(gvec_rotr64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 50 | --- a/include/exec/exec-all.h |
51 | +++ b/include/exec/exec-all.h | ||
52 | @@ -XXX,XX +XXX,XX @@ struct TranslationBlock { | ||
53 | uintptr_t jmp_dest[2]; | ||
54 | }; | ||
55 | |||
56 | +/* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */ | ||
57 | +static inline target_ulong tb_pc(const TranslationBlock *tb) | ||
58 | +{ | ||
59 | + return tb->pc; | ||
60 | +} | ||
42 | + | 61 | + |
43 | DEF_HELPER_FLAGS_4(gvec_eq8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 62 | /* Hide the qatomic_read to make code a little easier on the eyes */ |
44 | DEF_HELPER_FLAGS_4(gvec_eq16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 63 | static inline uint32_t tb_cflags(const TranslationBlock *tb) |
45 | DEF_HELPER_FLAGS_4(gvec_eq32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 64 | { |
46 | diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/include/tcg/tcg-op-gvec.h | ||
49 | +++ b/include/tcg/tcg-op-gvec.h | ||
50 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
51 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz); | ||
52 | void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
53 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz); | ||
54 | +void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
55 | + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); | ||
56 | +void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
57 | + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); | ||
58 | |||
59 | void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, | ||
60 | uint32_t aofs, uint32_t bofs, | ||
61 | diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/include/tcg/tcg-op.h | ||
64 | +++ b/include/tcg/tcg-op.h | ||
65 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); | ||
66 | void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); | ||
67 | void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); | ||
68 | void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); | ||
69 | +void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); | ||
70 | +void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); | ||
71 | |||
72 | void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, | ||
73 | TCGv_vec a, TCGv_vec b); | ||
74 | diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h | ||
75 | index XXXXXXX..XXXXXXX 100644 | ||
76 | --- a/include/tcg/tcg-opc.h | ||
77 | +++ b/include/tcg/tcg-opc.h | ||
78 | @@ -XXX,XX +XXX,XX @@ DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) | ||
79 | DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) | ||
80 | DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) | ||
81 | DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) | ||
82 | +DEF(rotlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec)) | ||
83 | +DEF(rotrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec)) | ||
84 | |||
85 | DEF(cmp_vec, 1, 2, 1, IMPLVEC) | ||
86 | |||
87 | diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h | 65 | diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h |
88 | index XXXXXXX..XXXXXXX 100644 | 66 | index XXXXXXX..XXXXXXX 100644 |
89 | --- a/include/tcg/tcg.h | 67 | --- a/include/tcg/tcg.h |
90 | +++ b/include/tcg/tcg.h | 68 | +++ b/include/tcg/tcg.h |
91 | @@ -XXX,XX +XXX,XX @@ typedef uint64_t TCGRegSet; | 69 | @@ -XXX,XX +XXX,XX @@ void tcg_register_thread(void); |
92 | #define TCG_TARGET_HAS_andc_vec 0 | 70 | void tcg_prologue_init(TCGContext *s); |
93 | #define TCG_TARGET_HAS_orc_vec 0 | 71 | void tcg_func_start(TCGContext *s); |
94 | #define TCG_TARGET_HAS_roti_vec 0 | 72 | |
95 | +#define TCG_TARGET_HAS_rotv_vec 0 | 73 | -int tcg_gen_code(TCGContext *s, TranslationBlock *tb); |
96 | #define TCG_TARGET_HAS_shi_vec 0 | 74 | +int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_start); |
97 | #define TCG_TARGET_HAS_shs_vec 0 | 75 | |
98 | #define TCG_TARGET_HAS_shv_vec 0 | 76 | void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); |
99 | diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h | 77 | |
100 | index XXXXXXX..XXXXXXX 100644 | 78 | diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c |
101 | --- a/tcg/aarch64/tcg-target.h | 79 | index XXXXXXX..XXXXXXX 100644 |
102 | +++ b/tcg/aarch64/tcg-target.h | 80 | --- a/accel/tcg/cpu-exec.c |
103 | @@ -XXX,XX +XXX,XX @@ typedef enum { | 81 | +++ b/accel/tcg/cpu-exec.c |
104 | #define TCG_TARGET_HAS_neg_vec 1 | 82 | @@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d) |
105 | #define TCG_TARGET_HAS_abs_vec 1 | 83 | const TranslationBlock *tb = p; |
106 | #define TCG_TARGET_HAS_roti_vec 0 | 84 | const struct tb_desc *desc = d; |
107 | +#define TCG_TARGET_HAS_rotv_vec 0 | 85 | |
108 | #define TCG_TARGET_HAS_shi_vec 1 | 86 | - if (tb->pc == desc->pc && |
109 | #define TCG_TARGET_HAS_shs_vec 0 | 87 | + if (tb_pc(tb) == desc->pc && |
110 | #define TCG_TARGET_HAS_shv_vec 1 | 88 | tb->page_addr[0] == desc->page_addr0 && |
111 | diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h | 89 | tb->cs_base == desc->cs_base && |
112 | index XXXXXXX..XXXXXXX 100644 | 90 | tb->flags == desc->flags && |
113 | --- a/tcg/i386/tcg-target.h | 91 | @@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc, |
114 | +++ b/tcg/i386/tcg-target.h | 92 | return tb; |
115 | @@ -XXX,XX +XXX,XX @@ extern bool have_avx2; | 93 | } |
116 | #define TCG_TARGET_HAS_neg_vec 0 | 94 | |
117 | #define TCG_TARGET_HAS_abs_vec 1 | 95 | -static inline void log_cpu_exec(target_ulong pc, CPUState *cpu, |
118 | #define TCG_TARGET_HAS_roti_vec 0 | 96 | - const TranslationBlock *tb) |
119 | +#define TCG_TARGET_HAS_rotv_vec 0 | 97 | +static void log_cpu_exec(target_ulong pc, CPUState *cpu, |
120 | #define TCG_TARGET_HAS_shi_vec 1 | 98 | + const TranslationBlock *tb) |
121 | #define TCG_TARGET_HAS_shs_vec 1 | 99 | { |
122 | #define TCG_TARGET_HAS_shv_vec have_avx2 | 100 | - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) |
123 | diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h | 101 | - && qemu_log_in_addr_range(pc)) { |
124 | index XXXXXXX..XXXXXXX 100644 | 102 | - |
125 | --- a/tcg/ppc/tcg-target.h | 103 | + if (qemu_log_in_addr_range(pc)) { |
126 | +++ b/tcg/ppc/tcg-target.h | 104 | qemu_log_mask(CPU_LOG_EXEC, |
127 | @@ -XXX,XX +XXX,XX @@ extern bool have_vsx; | 105 | "Trace %d: %p [" TARGET_FMT_lx |
128 | #define TCG_TARGET_HAS_neg_vec have_isa_3_00 | 106 | "/" TARGET_FMT_lx "/%08x/%08x] %s\n", |
129 | #define TCG_TARGET_HAS_abs_vec 0 | 107 | @@ -XXX,XX +XXX,XX @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) |
130 | #define TCG_TARGET_HAS_roti_vec 0 | 108 | return tcg_code_gen_epilogue; |
131 | +#define TCG_TARGET_HAS_rotv_vec 0 | 109 | } |
132 | #define TCG_TARGET_HAS_shi_vec 0 | 110 | |
133 | #define TCG_TARGET_HAS_shs_vec 0 | 111 | - log_cpu_exec(pc, cpu, tb); |
134 | #define TCG_TARGET_HAS_shv_vec 1 | 112 | + if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) { |
135 | diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c | 113 | + log_cpu_exec(pc, cpu, tb); |
136 | index XXXXXXX..XXXXXXX 100644 | 114 | + } |
137 | --- a/accel/tcg/tcg-runtime-gvec.c | 115 | |
138 | +++ b/accel/tcg/tcg-runtime-gvec.c | 116 | return tb->tc.ptr; |
139 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sar64v)(void *d, void *a, void *b, uint32_t desc) | 117 | } |
140 | clear_high(d, oprsz, desc); | 118 | @@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) |
141 | } | 119 | TranslationBlock *last_tb; |
142 | 120 | const void *tb_ptr = itb->tc.ptr; | |
143 | +void HELPER(gvec_rotl8v)(void *d, void *a, void *b, uint32_t desc) | 121 | |
144 | +{ | 122 | - log_cpu_exec(itb->pc, cpu, itb); |
145 | + intptr_t oprsz = simd_oprsz(desc); | 123 | + if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) { |
146 | + intptr_t i; | 124 | + log_cpu_exec(log_pc(cpu, itb), cpu, itb); |
125 | + } | ||
126 | |||
127 | qemu_thread_jit_execute(); | ||
128 | ret = tcg_qemu_tb_exec(env, tb_ptr); | ||
129 | @@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) | ||
130 | * of the start of the TB. | ||
131 | */ | ||
132 | CPUClass *cc = CPU_GET_CLASS(cpu); | ||
133 | - qemu_log_mask_and_addr(CPU_LOG_EXEC, last_tb->pc, | ||
134 | - "Stopped execution of TB chain before %p [" | ||
135 | - TARGET_FMT_lx "] %s\n", | ||
136 | - last_tb->tc.ptr, last_tb->pc, | ||
137 | - lookup_symbol(last_tb->pc)); | ||
147 | + | 138 | + |
148 | + for (i = 0; i < oprsz; i += sizeof(uint8_t)) { | 139 | if (cc->tcg_ops->synchronize_from_tb) { |
149 | + uint8_t sh = *(uint8_t *)(b + i) & 7; | 140 | cc->tcg_ops->synchronize_from_tb(cpu, last_tb); |
150 | + *(uint8_t *)(d + i) = rol8(*(uint8_t *)(a + i), sh); | 141 | } else { |
142 | assert(cc->set_pc); | ||
143 | - cc->set_pc(cpu, last_tb->pc); | ||
144 | + cc->set_pc(cpu, tb_pc(last_tb)); | ||
145 | + } | ||
146 | + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { | ||
147 | + target_ulong pc = log_pc(cpu, last_tb); | ||
148 | + if (qemu_log_in_addr_range(pc)) { | ||
149 | + qemu_log("Stopped execution of TB chain before %p [" | ||
150 | + TARGET_FMT_lx "] %s\n", | ||
151 | + last_tb->tc.ptr, pc, lookup_symbol(pc)); | ||
152 | + } | ||
153 | } | ||
154 | } | ||
155 | |||
156 | @@ -XXX,XX +XXX,XX @@ static inline void tb_add_jump(TranslationBlock *tb, int n, | ||
157 | |||
158 | qemu_spin_unlock(&tb_next->jmp_lock); | ||
159 | |||
160 | - qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, | ||
161 | - "Linking TBs %p [" TARGET_FMT_lx | ||
162 | - "] index %d -> %p [" TARGET_FMT_lx "]\n", | ||
163 | - tb->tc.ptr, tb->pc, n, | ||
164 | - tb_next->tc.ptr, tb_next->pc); | ||
165 | + qemu_log_mask(CPU_LOG_EXEC, "Linking TBs %p index %d -> %p\n", | ||
166 | + tb->tc.ptr, n, tb_next->tc.ptr); | ||
167 | return; | ||
168 | |||
169 | out_unlock_next: | ||
170 | @@ -XXX,XX +XXX,XX @@ static inline bool cpu_handle_interrupt(CPUState *cpu, | ||
171 | } | ||
172 | |||
173 | static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, | ||
174 | + target_ulong pc, | ||
175 | TranslationBlock **last_tb, int *tb_exit) | ||
176 | { | ||
177 | int32_t insns_left; | ||
178 | |||
179 | - trace_exec_tb(tb, tb->pc); | ||
180 | + trace_exec_tb(tb, pc); | ||
181 | tb = cpu_tb_exec(cpu, tb, tb_exit); | ||
182 | if (*tb_exit != TB_EXIT_REQUESTED) { | ||
183 | *last_tb = tb; | ||
184 | @@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu) | ||
185 | tb_add_jump(last_tb, tb_exit, tb); | ||
186 | } | ||
187 | |||
188 | - cpu_loop_exec_tb(cpu, tb, &last_tb, &tb_exit); | ||
189 | + cpu_loop_exec_tb(cpu, tb, pc, &last_tb, &tb_exit); | ||
190 | |||
191 | /* Try to align the host and virtual clocks | ||
192 | if the guest is in advance */ | ||
193 | diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c | ||
194 | index XXXXXXX..XXXXXXX 100644 | ||
195 | --- a/accel/tcg/translate-all.c | ||
196 | +++ b/accel/tcg/translate-all.c | ||
197 | @@ -XXX,XX +XXX,XX @@ static int encode_search(TranslationBlock *tb, uint8_t *block) | ||
198 | |||
199 | for (j = 0; j < TARGET_INSN_START_WORDS; ++j) { | ||
200 | if (i == 0) { | ||
201 | - prev = (j == 0 ? tb->pc : 0); | ||
202 | + prev = (j == 0 ? tb_pc(tb) : 0); | ||
203 | } else { | ||
204 | prev = tcg_ctx->gen_insn_data[i - 1][j]; | ||
205 | } | ||
206 | @@ -XXX,XX +XXX,XX @@ static int encode_search(TranslationBlock *tb, uint8_t *block) | ||
207 | static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, | ||
208 | uintptr_t searched_pc, bool reset_icount) | ||
209 | { | ||
210 | - target_ulong data[TARGET_INSN_START_WORDS] = { tb->pc }; | ||
211 | + target_ulong data[TARGET_INSN_START_WORDS] = { tb_pc(tb) }; | ||
212 | uintptr_t host_pc = (uintptr_t)tb->tc.ptr; | ||
213 | CPUArchState *env = cpu->env_ptr; | ||
214 | const uint8_t *p = tb->tc.ptr + tb->tc.size; | ||
215 | @@ -XXX,XX +XXX,XX @@ static bool tb_cmp(const void *ap, const void *bp) | ||
216 | const TranslationBlock *a = ap; | ||
217 | const TranslationBlock *b = bp; | ||
218 | |||
219 | - return a->pc == b->pc && | ||
220 | + return tb_pc(a) == tb_pc(b) && | ||
221 | a->cs_base == b->cs_base && | ||
222 | a->flags == b->flags && | ||
223 | (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) && | ||
224 | @@ -XXX,XX +XXX,XX @@ static void do_tb_invalidate_check(void *p, uint32_t hash, void *userp) | ||
225 | TranslationBlock *tb = p; | ||
226 | target_ulong addr = *(target_ulong *)userp; | ||
227 | |||
228 | - if (!(addr + TARGET_PAGE_SIZE <= tb->pc || addr >= tb->pc + tb->size)) { | ||
229 | + if (!(addr + TARGET_PAGE_SIZE <= tb_pc(tb) || | ||
230 | + addr >= tb_pc(tb) + tb->size)) { | ||
231 | printf("ERROR invalidate: address=" TARGET_FMT_lx | ||
232 | - " PC=%08lx size=%04x\n", addr, (long)tb->pc, tb->size); | ||
233 | + " PC=%08lx size=%04x\n", addr, (long)tb_pc(tb), tb->size); | ||
234 | } | ||
235 | } | ||
236 | |||
237 | @@ -XXX,XX +XXX,XX @@ static void do_tb_page_check(void *p, uint32_t hash, void *userp) | ||
238 | TranslationBlock *tb = p; | ||
239 | int flags1, flags2; | ||
240 | |||
241 | - flags1 = page_get_flags(tb->pc); | ||
242 | - flags2 = page_get_flags(tb->pc + tb->size - 1); | ||
243 | + flags1 = page_get_flags(tb_pc(tb)); | ||
244 | + flags2 = page_get_flags(tb_pc(tb) + tb->size - 1); | ||
245 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { | ||
246 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", | ||
247 | - (long)tb->pc, tb->size, flags1, flags2); | ||
248 | + (long)tb_pc(tb), tb->size, flags1, flags2); | ||
249 | } | ||
250 | } | ||
251 | |||
252 | @@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) | ||
253 | |||
254 | /* remove the TB from the hash list */ | ||
255 | phys_pc = tb->page_addr[0]; | ||
256 | - h = tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags, | ||
257 | + h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, orig_cflags, | ||
258 | tb->trace_vcpu_dstate); | ||
259 | if (!qht_remove(&tb_ctx.htable, tb, h)) { | ||
260 | return; | ||
261 | @@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, | ||
262 | } | ||
263 | |||
264 | /* add in the hash table */ | ||
265 | - h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags, | ||
266 | + h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, tb->cflags, | ||
267 | tb->trace_vcpu_dstate); | ||
268 | qht_insert(&tb_ctx.htable, tb, h, &existing_tb); | ||
269 | |||
270 | @@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu, | ||
271 | tcg_ctx->cpu = NULL; | ||
272 | max_insns = tb->icount; | ||
273 | |||
274 | - trace_translate_block(tb, tb->pc, tb->tc.ptr); | ||
275 | + trace_translate_block(tb, pc, tb->tc.ptr); | ||
276 | |||
277 | /* generate machine code */ | ||
278 | tb->jmp_reset_offset[0] = TB_JMP_RESET_OFFSET_INVALID; | ||
279 | @@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu, | ||
280 | ti = profile_getclock(); | ||
281 | #endif | ||
282 | |||
283 | - gen_code_size = tcg_gen_code(tcg_ctx, tb); | ||
284 | + gen_code_size = tcg_gen_code(tcg_ctx, tb, pc); | ||
285 | if (unlikely(gen_code_size < 0)) { | ||
286 | error_return: | ||
287 | switch (gen_code_size) { | ||
288 | @@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu, | ||
289 | |||
290 | #ifdef DEBUG_DISAS | ||
291 | if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) && | ||
292 | - qemu_log_in_addr_range(tb->pc)) { | ||
293 | + qemu_log_in_addr_range(pc)) { | ||
294 | FILE *logfile = qemu_log_trylock(); | ||
295 | if (logfile) { | ||
296 | int code_size, data_size; | ||
297 | @@ -XXX,XX +XXX,XX @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) | ||
298 | */ | ||
299 | cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | CF_LAST_IO | n; | ||
300 | |||
301 | - qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, | ||
302 | - "cpu_io_recompile: rewound execution of TB to " | ||
303 | - TARGET_FMT_lx "\n", tb->pc); | ||
304 | + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { | ||
305 | + target_ulong pc = log_pc(cpu, tb); | ||
306 | + if (qemu_log_in_addr_range(pc)) { | ||
307 | + qemu_log("cpu_io_recompile: rewound execution of TB to " | ||
308 | + TARGET_FMT_lx "\n", pc); | ||
309 | + } | ||
151 | + } | 310 | + } |
152 | + clear_high(d, oprsz, desc); | 311 | |
153 | +} | 312 | cpu_loop_exit_noexc(cpu); |
154 | + | 313 | } |
155 | +void HELPER(gvec_rotl16v)(void *d, void *a, void *b, uint32_t desc) | 314 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
156 | +{ | 315 | index XXXXXXX..XXXXXXX 100644 |
157 | + intptr_t oprsz = simd_oprsz(desc); | 316 | --- a/target/arm/cpu.c |
158 | + intptr_t i; | 317 | +++ b/target/arm/cpu.c |
159 | + | 318 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_synchronize_from_tb(CPUState *cs, |
160 | + for (i = 0; i < oprsz; i += sizeof(uint16_t)) { | 319 | * never possible for an AArch64 TB to chain to an AArch32 TB. |
161 | + uint8_t sh = *(uint16_t *)(b + i) & 15; | 320 | */ |
162 | + *(uint16_t *)(d + i) = rol16(*(uint16_t *)(a + i), sh); | 321 | if (is_a64(env)) { |
163 | + } | 322 | - env->pc = tb->pc; |
164 | + clear_high(d, oprsz, desc); | 323 | + env->pc = tb_pc(tb); |
165 | +} | 324 | } else { |
166 | + | 325 | - env->regs[15] = tb->pc; |
167 | +void HELPER(gvec_rotl32v)(void *d, void *a, void *b, uint32_t desc) | 326 | + env->regs[15] = tb_pc(tb); |
168 | +{ | 327 | } |
169 | + intptr_t oprsz = simd_oprsz(desc); | 328 | } |
170 | + intptr_t i; | 329 | #endif /* CONFIG_TCG */ |
171 | + | 330 | diff --git a/target/avr/cpu.c b/target/avr/cpu.c |
172 | + for (i = 0; i < oprsz; i += sizeof(uint32_t)) { | 331 | index XXXXXXX..XXXXXXX 100644 |
173 | + uint8_t sh = *(uint32_t *)(b + i) & 31; | 332 | --- a/target/avr/cpu.c |
174 | + *(uint32_t *)(d + i) = rol32(*(uint32_t *)(a + i), sh); | 333 | +++ b/target/avr/cpu.c |
175 | + } | 334 | @@ -XXX,XX +XXX,XX @@ static void avr_cpu_synchronize_from_tb(CPUState *cs, |
176 | + clear_high(d, oprsz, desc); | 335 | AVRCPU *cpu = AVR_CPU(cs); |
177 | +} | 336 | CPUAVRState *env = &cpu->env; |
178 | + | 337 | |
179 | +void HELPER(gvec_rotl64v)(void *d, void *a, void *b, uint32_t desc) | 338 | - env->pc_w = tb->pc / 2; /* internally PC points to words */ |
180 | +{ | 339 | + env->pc_w = tb_pc(tb) / 2; /* internally PC points to words */ |
181 | + intptr_t oprsz = simd_oprsz(desc); | 340 | } |
182 | + intptr_t i; | 341 | |
183 | + | 342 | static void avr_cpu_reset(DeviceState *ds) |
184 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | 343 | diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c |
185 | + uint8_t sh = *(uint64_t *)(b + i) & 63; | 344 | index XXXXXXX..XXXXXXX 100644 |
186 | + *(uint64_t *)(d + i) = rol64(*(uint64_t *)(a + i), sh); | 345 | --- a/target/hexagon/cpu.c |
187 | + } | 346 | +++ b/target/hexagon/cpu.c |
188 | + clear_high(d, oprsz, desc); | 347 | @@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_synchronize_from_tb(CPUState *cs, |
189 | +} | 348 | { |
190 | + | 349 | HexagonCPU *cpu = HEXAGON_CPU(cs); |
191 | +void HELPER(gvec_rotr8v)(void *d, void *a, void *b, uint32_t desc) | 350 | CPUHexagonState *env = &cpu->env; |
192 | +{ | 351 | - env->gpr[HEX_REG_PC] = tb->pc; |
193 | + intptr_t oprsz = simd_oprsz(desc); | 352 | + env->gpr[HEX_REG_PC] = tb_pc(tb); |
194 | + intptr_t i; | 353 | } |
195 | + | 354 | |
196 | + for (i = 0; i < oprsz; i += sizeof(uint8_t)) { | 355 | static bool hexagon_cpu_has_work(CPUState *cs) |
197 | + uint8_t sh = *(uint8_t *)(b + i) & 7; | 356 | diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c |
198 | + *(uint8_t *)(d + i) = ror8(*(uint8_t *)(a + i), sh); | 357 | index XXXXXXX..XXXXXXX 100644 |
199 | + } | 358 | --- a/target/hppa/cpu.c |
200 | + clear_high(d, oprsz, desc); | 359 | +++ b/target/hppa/cpu.c |
201 | +} | 360 | @@ -XXX,XX +XXX,XX @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, |
202 | + | 361 | HPPACPU *cpu = HPPA_CPU(cs); |
203 | +void HELPER(gvec_rotr16v)(void *d, void *a, void *b, uint32_t desc) | 362 | |
204 | +{ | 363 | #ifdef CONFIG_USER_ONLY |
205 | + intptr_t oprsz = simd_oprsz(desc); | 364 | - cpu->env.iaoq_f = tb->pc; |
206 | + intptr_t i; | 365 | + cpu->env.iaoq_f = tb_pc(tb); |
207 | + | 366 | cpu->env.iaoq_b = tb->cs_base; |
208 | + for (i = 0; i < oprsz; i += sizeof(uint16_t)) { | 367 | #else |
209 | + uint8_t sh = *(uint16_t *)(b + i) & 15; | 368 | /* Recover the IAOQ values from the GVA + PRIV. */ |
210 | + *(uint16_t *)(d + i) = ror16(*(uint16_t *)(a + i), sh); | 369 | @@ -XXX,XX +XXX,XX @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, |
211 | + } | 370 | int32_t diff = cs_base; |
212 | + clear_high(d, oprsz, desc); | 371 | |
213 | +} | 372 | cpu->env.iasq_f = iasq_f; |
214 | + | 373 | - cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv; |
215 | +void HELPER(gvec_rotr32v)(void *d, void *a, void *b, uint32_t desc) | 374 | + cpu->env.iaoq_f = (tb_pc(tb) & ~iasq_f) + priv; |
216 | +{ | 375 | if (diff) { |
217 | + intptr_t oprsz = simd_oprsz(desc); | 376 | cpu->env.iaoq_b = cpu->env.iaoq_f + diff; |
218 | + intptr_t i; | 377 | } |
219 | + | 378 | diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c |
220 | + for (i = 0; i < oprsz; i += sizeof(uint32_t)) { | 379 | index XXXXXXX..XXXXXXX 100644 |
221 | + uint8_t sh = *(uint32_t *)(b + i) & 31; | 380 | --- a/target/i386/tcg/tcg-cpu.c |
222 | + *(uint32_t *)(d + i) = ror32(*(uint32_t *)(a + i), sh); | 381 | +++ b/target/i386/tcg/tcg-cpu.c |
223 | + } | 382 | @@ -XXX,XX +XXX,XX @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, |
224 | + clear_high(d, oprsz, desc); | 383 | { |
225 | +} | 384 | X86CPU *cpu = X86_CPU(cs); |
226 | + | 385 | |
227 | +void HELPER(gvec_rotr64v)(void *d, void *a, void *b, uint32_t desc) | 386 | - cpu->env.eip = tb->pc - tb->cs_base; |
228 | +{ | 387 | + cpu->env.eip = tb_pc(tb) - tb->cs_base; |
229 | + intptr_t oprsz = simd_oprsz(desc); | 388 | } |
230 | + intptr_t i; | 389 | |
231 | + | 390 | #ifndef CONFIG_USER_ONLY |
232 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | 391 | diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c |
233 | + uint8_t sh = *(uint64_t *)(b + i) & 63; | 392 | index XXXXXXX..XXXXXXX 100644 |
234 | + *(uint64_t *)(d + i) = ror64(*(uint64_t *)(a + i), sh); | 393 | --- a/target/loongarch/cpu.c |
235 | + } | 394 | +++ b/target/loongarch/cpu.c |
236 | + clear_high(d, oprsz, desc); | 395 | @@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_synchronize_from_tb(CPUState *cs, |
237 | +} | 396 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); |
238 | + | 397 | CPULoongArchState *env = &cpu->env; |
239 | #define DO_CMP1(NAME, TYPE, OP) \ | 398 | |
240 | void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) \ | 399 | - env->pc = tb->pc; |
241 | { \ | 400 | + env->pc = tb_pc(tb); |
242 | diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c | 401 | } |
243 | index XXXXXXX..XXXXXXX 100644 | 402 | #endif /* CONFIG_TCG */ |
244 | --- a/tcg/tcg-op-gvec.c | 403 | |
245 | +++ b/tcg/tcg-op-gvec.c | 404 | diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c |
246 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs, | 405 | index XXXXXXX..XXXXXXX 100644 |
247 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | 406 | --- a/target/microblaze/cpu.c |
248 | } | 407 | +++ b/target/microblaze/cpu.c |
249 | 408 | @@ -XXX,XX +XXX,XX @@ static void mb_cpu_synchronize_from_tb(CPUState *cs, | |
250 | +/* | 409 | { |
251 | + * Similarly for rotates. | 410 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); |
252 | + */ | 411 | |
253 | + | 412 | - cpu->env.pc = tb->pc; |
254 | +static void tcg_gen_rotlv_mod_vec(unsigned vece, TCGv_vec d, | 413 | + cpu->env.pc = tb_pc(tb); |
255 | + TCGv_vec a, TCGv_vec b) | 414 | cpu->env.iflags = tb->flags & IFLAGS_TB_MASK; |
256 | +{ | 415 | } |
257 | + TCGv_vec t = tcg_temp_new_vec_matching(d); | 416 | |
258 | + | 417 | diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c |
259 | + tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); | 418 | index XXXXXXX..XXXXXXX 100644 |
260 | + tcg_gen_and_vec(vece, t, t, b); | 419 | --- a/target/mips/tcg/exception.c |
261 | + tcg_gen_rotlv_vec(vece, d, a, t); | 420 | +++ b/target/mips/tcg/exception.c |
262 | + tcg_temp_free_vec(t); | 421 | @@ -XXX,XX +XXX,XX @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) |
263 | +} | 422 | MIPSCPU *cpu = MIPS_CPU(cs); |
264 | + | 423 | CPUMIPSState *env = &cpu->env; |
265 | +static void tcg_gen_rotl_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) | 424 | |
266 | +{ | 425 | - env->active_tc.PC = tb->pc; |
267 | + TCGv_i32 t = tcg_temp_new_i32(); | 426 | + env->active_tc.PC = tb_pc(tb); |
268 | + | 427 | env->hflags &= ~MIPS_HFLAG_BMASK; |
269 | + tcg_gen_andi_i32(t, b, 31); | 428 | env->hflags |= tb->flags & MIPS_HFLAG_BMASK; |
270 | + tcg_gen_rotl_i32(d, a, t); | 429 | } |
271 | + tcg_temp_free_i32(t); | 430 | diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/sysemu/special_helper.c |
272 | +} | 431 | index XXXXXXX..XXXXXXX 100644 |
273 | + | 432 | --- a/target/mips/tcg/sysemu/special_helper.c |
274 | +static void tcg_gen_rotl_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) | 433 | +++ b/target/mips/tcg/sysemu/special_helper.c |
275 | +{ | 434 | @@ -XXX,XX +XXX,XX @@ bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb) |
276 | + TCGv_i64 t = tcg_temp_new_i64(); | 435 | CPUMIPSState *env = &cpu->env; |
277 | + | 436 | |
278 | + tcg_gen_andi_i64(t, b, 63); | 437 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 |
279 | + tcg_gen_rotl_i64(d, a, t); | 438 | - && env->active_tc.PC != tb->pc) { |
280 | + tcg_temp_free_i64(t); | 439 | + && env->active_tc.PC != tb_pc(tb)) { |
281 | +} | 440 | env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); |
282 | + | 441 | env->hflags &= ~MIPS_HFLAG_BMASK; |
283 | +void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, uint32_t aofs, | 442 | return true; |
284 | + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | 443 | diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c |
285 | +{ | 444 | index XXXXXXX..XXXXXXX 100644 |
286 | + static const TCGOpcode vecop_list[] = { INDEX_op_rotlv_vec, 0 }; | 445 | --- a/target/openrisc/cpu.c |
287 | + static const GVecGen3 g[4] = { | 446 | +++ b/target/openrisc/cpu.c |
288 | + { .fniv = tcg_gen_rotlv_mod_vec, | 447 | @@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_synchronize_from_tb(CPUState *cs, |
289 | + .fno = gen_helper_gvec_rotl8v, | 448 | { |
290 | + .opt_opc = vecop_list, | 449 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); |
291 | + .vece = MO_8 }, | 450 | |
292 | + { .fniv = tcg_gen_rotlv_mod_vec, | 451 | - cpu->env.pc = tb->pc; |
293 | + .fno = gen_helper_gvec_rotl16v, | 452 | + cpu->env.pc = tb_pc(tb); |
294 | + .opt_opc = vecop_list, | 453 | } |
295 | + .vece = MO_16 }, | 454 | |
296 | + { .fni4 = tcg_gen_rotl_mod_i32, | 455 | |
297 | + .fniv = tcg_gen_rotlv_mod_vec, | 456 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c |
298 | + .fno = gen_helper_gvec_rotl32v, | 457 | index XXXXXXX..XXXXXXX 100644 |
299 | + .opt_opc = vecop_list, | 458 | --- a/target/riscv/cpu.c |
300 | + .vece = MO_32 }, | 459 | +++ b/target/riscv/cpu.c |
301 | + { .fni8 = tcg_gen_rotl_mod_i64, | 460 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, |
302 | + .fniv = tcg_gen_rotlv_mod_vec, | 461 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
303 | + .fno = gen_helper_gvec_rotl64v, | 462 | |
304 | + .opt_opc = vecop_list, | 463 | if (xl == MXL_RV32) { |
305 | + .prefer_i64 = TCG_TARGET_REG_BITS == 64, | 464 | - env->pc = (int32_t)tb->pc; |
306 | + .vece = MO_64 }, | 465 | + env->pc = (int32_t)tb_pc(tb); |
307 | + }; | 466 | } else { |
308 | + | 467 | - env->pc = tb->pc; |
309 | + tcg_debug_assert(vece <= MO_64); | 468 | + env->pc = tb_pc(tb); |
310 | + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | 469 | } |
311 | +} | 470 | } |
312 | + | 471 | |
313 | +static void tcg_gen_rotrv_mod_vec(unsigned vece, TCGv_vec d, | 472 | diff --git a/target/rx/cpu.c b/target/rx/cpu.c |
314 | + TCGv_vec a, TCGv_vec b) | 473 | index XXXXXXX..XXXXXXX 100644 |
315 | +{ | 474 | --- a/target/rx/cpu.c |
316 | + TCGv_vec t = tcg_temp_new_vec_matching(d); | 475 | +++ b/target/rx/cpu.c |
317 | + | 476 | @@ -XXX,XX +XXX,XX @@ static void rx_cpu_synchronize_from_tb(CPUState *cs, |
318 | + tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); | 477 | { |
319 | + tcg_gen_and_vec(vece, t, t, b); | 478 | RXCPU *cpu = RX_CPU(cs); |
320 | + tcg_gen_rotrv_vec(vece, d, a, t); | 479 | |
321 | + tcg_temp_free_vec(t); | 480 | - cpu->env.pc = tb->pc; |
322 | +} | 481 | + cpu->env.pc = tb_pc(tb); |
323 | + | 482 | } |
324 | +static void tcg_gen_rotr_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) | 483 | |
325 | +{ | 484 | static bool rx_cpu_has_work(CPUState *cs) |
326 | + TCGv_i32 t = tcg_temp_new_i32(); | 485 | diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c |
327 | + | 486 | index XXXXXXX..XXXXXXX 100644 |
328 | + tcg_gen_andi_i32(t, b, 31); | 487 | --- a/target/sh4/cpu.c |
329 | + tcg_gen_rotr_i32(d, a, t); | 488 | +++ b/target/sh4/cpu.c |
330 | + tcg_temp_free_i32(t); | 489 | @@ -XXX,XX +XXX,XX @@ static void superh_cpu_synchronize_from_tb(CPUState *cs, |
331 | +} | 490 | { |
332 | + | 491 | SuperHCPU *cpu = SUPERH_CPU(cs); |
333 | +static void tcg_gen_rotr_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) | 492 | |
334 | +{ | 493 | - cpu->env.pc = tb->pc; |
335 | + TCGv_i64 t = tcg_temp_new_i64(); | 494 | + cpu->env.pc = tb_pc(tb); |
336 | + | 495 | cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK; |
337 | + tcg_gen_andi_i64(t, b, 63); | 496 | } |
338 | + tcg_gen_rotr_i64(d, a, t); | 497 | |
339 | + tcg_temp_free_i64(t); | 498 | @@ -XXX,XX +XXX,XX @@ static bool superh_io_recompile_replay_branch(CPUState *cs, |
340 | +} | 499 | CPUSH4State *env = &cpu->env; |
341 | + | 500 | |
342 | +void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs, | 501 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 |
343 | + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | 502 | - && env->pc != tb->pc) { |
344 | +{ | 503 | + && env->pc != tb_pc(tb)) { |
345 | + static const TCGOpcode vecop_list[] = { INDEX_op_rotrv_vec, 0 }; | 504 | env->pc -= 2; |
346 | + static const GVecGen3 g[4] = { | 505 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); |
347 | + { .fniv = tcg_gen_rotrv_mod_vec, | 506 | return true; |
348 | + .fno = gen_helper_gvec_rotr8v, | 507 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c |
349 | + .opt_opc = vecop_list, | 508 | index XXXXXXX..XXXXXXX 100644 |
350 | + .vece = MO_8 }, | 509 | --- a/target/sparc/cpu.c |
351 | + { .fniv = tcg_gen_rotrv_mod_vec, | 510 | +++ b/target/sparc/cpu.c |
352 | + .fno = gen_helper_gvec_rotr16v, | 511 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, |
353 | + .opt_opc = vecop_list, | 512 | { |
354 | + .vece = MO_16 }, | 513 | SPARCCPU *cpu = SPARC_CPU(cs); |
355 | + { .fni4 = tcg_gen_rotr_mod_i32, | 514 | |
356 | + .fniv = tcg_gen_rotrv_mod_vec, | 515 | - cpu->env.pc = tb->pc; |
357 | + .fno = gen_helper_gvec_rotr32v, | 516 | + cpu->env.pc = tb_pc(tb); |
358 | + .opt_opc = vecop_list, | 517 | cpu->env.npc = tb->cs_base; |
359 | + .vece = MO_32 }, | 518 | } |
360 | + { .fni8 = tcg_gen_rotr_mod_i64, | 519 | |
361 | + .fniv = tcg_gen_rotrv_mod_vec, | 520 | diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c |
362 | + .fno = gen_helper_gvec_rotr64v, | 521 | index XXXXXXX..XXXXXXX 100644 |
363 | + .opt_opc = vecop_list, | 522 | --- a/target/tricore/cpu.c |
364 | + .prefer_i64 = TCG_TARGET_REG_BITS == 64, | 523 | +++ b/target/tricore/cpu.c |
365 | + .vece = MO_64 }, | 524 | @@ -XXX,XX +XXX,XX @@ static void tricore_cpu_synchronize_from_tb(CPUState *cs, |
366 | + }; | 525 | TriCoreCPU *cpu = TRICORE_CPU(cs); |
367 | + | 526 | CPUTriCoreState *env = &cpu->env; |
368 | + tcg_debug_assert(vece <= MO_64); | 527 | |
369 | + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | 528 | - env->PC = tb->pc; |
370 | +} | 529 | + env->PC = tb_pc(tb); |
371 | + | 530 | } |
372 | /* Expand OPSZ bytes worth of three-operand operations using i32 elements. */ | 531 | |
373 | static void expand_cmp_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, | 532 | static void tricore_cpu_reset(DeviceState *dev) |
374 | uint32_t oprsz, TCGCond cond) | ||
375 | diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c | ||
376 | index XXXXXXX..XXXXXXX 100644 | ||
377 | --- a/tcg/tcg-op-vec.c | ||
378 | +++ b/tcg/tcg-op-vec.c | ||
379 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) | ||
380 | do_op3_nofail(vece, r, a, b, INDEX_op_sarv_vec); | ||
381 | } | ||
382 | |||
383 | +void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) | ||
384 | +{ | ||
385 | + do_op3_nofail(vece, r, a, b, INDEX_op_rotlv_vec); | ||
386 | +} | ||
387 | + | ||
388 | +void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) | ||
389 | +{ | ||
390 | + do_op3_nofail(vece, r, a, b, INDEX_op_rotrv_vec); | ||
391 | +} | ||
392 | + | ||
393 | static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a, | ||
394 | TCGv_i32 s, TCGOpcode opc_s, TCGOpcode opc_v) | ||
395 | { | ||
396 | diff --git a/tcg/tcg.c b/tcg/tcg.c | 533 | diff --git a/tcg/tcg.c b/tcg/tcg.c |
397 | index XXXXXXX..XXXXXXX 100644 | 534 | index XXXXXXX..XXXXXXX 100644 |
398 | --- a/tcg/tcg.c | 535 | --- a/tcg/tcg.c |
399 | +++ b/tcg/tcg.c | 536 | +++ b/tcg/tcg.c |
400 | @@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op) | 537 | @@ -XXX,XX +XXX,XX @@ int64_t tcg_cpu_exec_time(void) |
401 | return have_vec && TCG_TARGET_HAS_shv_vec; | 538 | #endif |
402 | case INDEX_op_rotli_vec: | 539 | |
403 | return have_vec && TCG_TARGET_HAS_roti_vec; | 540 | |
404 | + case INDEX_op_rotlv_vec: | 541 | -int tcg_gen_code(TCGContext *s, TranslationBlock *tb) |
405 | + case INDEX_op_rotrv_vec: | 542 | +int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_start) |
406 | + return have_vec && TCG_TARGET_HAS_rotv_vec; | 543 | { |
407 | case INDEX_op_ssadd_vec: | 544 | #ifdef CONFIG_PROFILER |
408 | case INDEX_op_usadd_vec: | 545 | TCGProfile *prof = &s->prof; |
409 | case INDEX_op_sssub_vec: | 546 | @@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) |
410 | diff --git a/tcg/README b/tcg/README | 547 | |
411 | index XXXXXXX..XXXXXXX 100644 | 548 | #ifdef DEBUG_DISAS |
412 | --- a/tcg/README | 549 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) |
413 | +++ b/tcg/README | 550 | - && qemu_log_in_addr_range(tb->pc))) { |
414 | @@ -XXX,XX +XXX,XX @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32. | 551 | + && qemu_log_in_addr_range(pc_start))) { |
415 | 552 | FILE *logfile = qemu_log_trylock(); | |
416 | * shrv_vec v0, v1, v2 | 553 | if (logfile) { |
417 | * sarv_vec v0, v1, v2 | 554 | fprintf(logfile, "OP:\n"); |
418 | +* rotlv_vec v0, v1, v2 | 555 | @@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) |
419 | +* rotrv_vec v0, v1, v2 | 556 | if (s->nb_indirects > 0) { |
420 | 557 | #ifdef DEBUG_DISAS | |
421 | - Similarly for logical and arithmetic right shift. | 558 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) |
422 | + Similarly for logical and arithmetic right shift, and rotates. | 559 | - && qemu_log_in_addr_range(tb->pc))) { |
423 | 560 | + && qemu_log_in_addr_range(pc_start))) { | |
424 | * cmp_vec v0, v1, v2, cond | 561 | FILE *logfile = qemu_log_trylock(); |
425 | 562 | if (logfile) { | |
563 | fprintf(logfile, "OP before indirect lowering:\n"); | ||
564 | @@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) | ||
565 | |||
566 | #ifdef DEBUG_DISAS | ||
567 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT) | ||
568 | - && qemu_log_in_addr_range(tb->pc))) { | ||
569 | + && qemu_log_in_addr_range(pc_start))) { | ||
570 | FILE *logfile = qemu_log_trylock(); | ||
571 | if (logfile) { | ||
572 | fprintf(logfile, "OP after optimization and liveness analysis:\n"); | ||
426 | -- | 573 | -- |
427 | 2.25.1 | 574 | 2.34.1 |
428 | 575 | ||
429 | 576 | diff view generated by jsdifflib |
1 | For immediate rotate , we can implement this in two instructions, | 1 | Prepare for targets to be able to produce TBs that can |
---|---|---|---|
2 | using SLI. For variable rotate, the oddness of aarch64 right-shift- | 2 | run in more than one virtual context. |
3 | as-negative-left-shift means a backend-specific expansion works best. | ||
4 | 3 | ||
4 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | --- | 6 | --- |
7 | tcg/aarch64/tcg-target.opc.h | 1 + | 7 | accel/tcg/internal.h | 4 +++ |
8 | tcg/aarch64/tcg-target.inc.c | 53 ++++++++++++++++++++++++++++++++++-- | 8 | accel/tcg/tb-jmp-cache.h | 41 +++++++++++++++++++++++++ |
9 | 2 files changed, 52 insertions(+), 2 deletions(-) | 9 | include/exec/cpu-defs.h | 3 ++ |
10 | include/exec/exec-all.h | 32 ++++++++++++++++++-- | ||
11 | accel/tcg/cpu-exec.c | 16 ++++++---- | ||
12 | accel/tcg/translate-all.c | 64 ++++++++++++++++++++++++++------------- | ||
13 | 6 files changed, 131 insertions(+), 29 deletions(-) | ||
10 | 14 | ||
11 | diff --git a/tcg/aarch64/tcg-target.opc.h b/tcg/aarch64/tcg-target.opc.h | 15 | diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h |
12 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/tcg/aarch64/tcg-target.opc.h | 17 | --- a/accel/tcg/internal.h |
14 | +++ b/tcg/aarch64/tcg-target.opc.h | 18 | +++ b/accel/tcg/internal.h |
19 | @@ -XXX,XX +XXX,XX @@ void tb_htable_init(void); | ||
20 | /* Return the current PC from CPU, which may be cached in TB. */ | ||
21 | static inline target_ulong log_pc(CPUState *cpu, const TranslationBlock *tb) | ||
22 | { | ||
23 | +#if TARGET_TB_PCREL | ||
24 | + return cpu->cc->get_pc(cpu); | ||
25 | +#else | ||
26 | return tb_pc(tb); | ||
27 | +#endif | ||
28 | } | ||
29 | |||
30 | #endif /* ACCEL_TCG_INTERNAL_H */ | ||
31 | diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/accel/tcg/tb-jmp-cache.h | ||
34 | +++ b/accel/tcg/tb-jmp-cache.h | ||
15 | @@ -XXX,XX +XXX,XX @@ | 35 | @@ -XXX,XX +XXX,XX @@ |
36 | |||
37 | /* | ||
38 | * Accessed in parallel; all accesses to 'tb' must be atomic. | ||
39 | + * For TARGET_TB_PCREL, accesses to 'pc' must be protected by | ||
40 | + * a load_acquire/store_release to 'tb'. | ||
16 | */ | 41 | */ |
17 | 42 | struct CPUJumpCache { | |
18 | DEF(aa64_sshl_vec, 1, 2, 0, IMPLVEC) | 43 | struct { |
19 | +DEF(aa64_sli_vec, 1, 2, 1, IMPLVEC) | 44 | TranslationBlock *tb; |
20 | diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c | 45 | +#if TARGET_TB_PCREL |
21 | index XXXXXXX..XXXXXXX 100644 | 46 | + target_ulong pc; |
22 | --- a/tcg/aarch64/tcg-target.inc.c | 47 | +#endif |
23 | +++ b/tcg/aarch64/tcg-target.inc.c | 48 | } array[TB_JMP_CACHE_SIZE]; |
24 | @@ -XXX,XX +XXX,XX @@ typedef enum { | 49 | }; |
25 | I3614_SSHR = 0x0f000400, | 50 | |
26 | I3614_SSRA = 0x0f001400, | 51 | +static inline TranslationBlock * |
27 | I3614_SHL = 0x0f005400, | 52 | +tb_jmp_cache_get_tb(CPUJumpCache *jc, uint32_t hash) |
28 | + I3614_SLI = 0x2f005400, | 53 | +{ |
29 | I3614_USHR = 0x2f000400, | 54 | +#if TARGET_TB_PCREL |
30 | I3614_USRA = 0x2f001400, | 55 | + /* Use acquire to ensure current load of pc from jc. */ |
31 | 56 | + return qatomic_load_acquire(&jc->array[hash].tb); | |
32 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, | 57 | +#else |
33 | case INDEX_op_sari_vec: | 58 | + /* Use rcu_read to ensure current load of pc from *tb. */ |
34 | tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2); | 59 | + return qatomic_rcu_read(&jc->array[hash].tb); |
35 | break; | 60 | +#endif |
36 | + case INDEX_op_aa64_sli_vec: | 61 | +} |
37 | + tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece)); | 62 | + |
38 | + break; | 63 | +static inline target_ulong |
39 | case INDEX_op_shlv_vec: | 64 | +tb_jmp_cache_get_pc(CPUJumpCache *jc, uint32_t hash, TranslationBlock *tb) |
40 | tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2); | 65 | +{ |
41 | break; | 66 | +#if TARGET_TB_PCREL |
42 | @@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) | 67 | + return jc->array[hash].pc; |
43 | case INDEX_op_shlv_vec: | 68 | +#else |
44 | case INDEX_op_bitsel_vec: | 69 | + return tb_pc(tb); |
45 | return 1; | 70 | +#endif |
46 | + case INDEX_op_rotli_vec: | 71 | +} |
47 | case INDEX_op_shrv_vec: | 72 | + |
48 | case INDEX_op_sarv_vec: | 73 | +static inline void |
49 | + case INDEX_op_rotlv_vec: | 74 | +tb_jmp_cache_set(CPUJumpCache *jc, uint32_t hash, |
50 | + case INDEX_op_rotrv_vec: | 75 | + TranslationBlock *tb, target_ulong pc) |
76 | +{ | ||
77 | +#if TARGET_TB_PCREL | ||
78 | + jc->array[hash].pc = pc; | ||
79 | + /* Use store_release on tb to ensure pc is written first. */ | ||
80 | + qatomic_store_release(&jc->array[hash].tb, tb); | ||
81 | +#else | ||
82 | + /* Use the pc value already stored in tb->pc. */ | ||
83 | + qatomic_set(&jc->array[hash].tb, tb); | ||
84 | +#endif | ||
85 | +} | ||
86 | + | ||
87 | #endif /* ACCEL_TCG_TB_JMP_CACHE_H */ | ||
88 | diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h | ||
89 | index XXXXXXX..XXXXXXX 100644 | ||
90 | --- a/include/exec/cpu-defs.h | ||
91 | +++ b/include/exec/cpu-defs.h | ||
92 | @@ -XXX,XX +XXX,XX @@ | ||
93 | # error TARGET_PAGE_BITS must be defined in cpu-param.h | ||
94 | # endif | ||
95 | #endif | ||
96 | +#ifndef TARGET_TB_PCREL | ||
97 | +# define TARGET_TB_PCREL 0 | ||
98 | +#endif | ||
99 | |||
100 | #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) | ||
101 | |||
102 | diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h | ||
103 | index XXXXXXX..XXXXXXX 100644 | ||
104 | --- a/include/exec/exec-all.h | ||
105 | +++ b/include/exec/exec-all.h | ||
106 | @@ -XXX,XX +XXX,XX @@ struct tb_tc { | ||
107 | }; | ||
108 | |||
109 | struct TranslationBlock { | ||
110 | - target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ | ||
111 | - target_ulong cs_base; /* CS base for this block */ | ||
112 | +#if !TARGET_TB_PCREL | ||
113 | + /* | ||
114 | + * Guest PC corresponding to this block. This must be the true | ||
115 | + * virtual address. Therefore e.g. x86 stores EIP + CS_BASE, and | ||
116 | + * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or | ||
117 | + * privilege, must store those bits elsewhere. | ||
118 | + * | ||
119 | + * If TARGET_TB_PCREL, the opcodes for the TranslationBlock are | ||
120 | + * written such that the TB is associated only with the physical | ||
121 | + * page and may be run in any virtual address context. In this case, | ||
122 | + * PC must always be taken from ENV in a target-specific manner. | ||
123 | + * Unwind information is taken as offsets from the page, to be | ||
124 | + * deposited into the "current" PC. | ||
125 | + */ | ||
126 | + target_ulong pc; | ||
127 | +#endif | ||
128 | + | ||
129 | + /* | ||
130 | + * Target-specific data associated with the TranslationBlock, e.g.: | ||
131 | + * x86: the original user, the Code Segment virtual base, | ||
132 | + * arm: an extension of tb->flags, | ||
133 | + * s390x: instruction data for EXECUTE, | ||
134 | + * sparc: the next pc of the instruction queue (for delay slots). | ||
135 | + */ | ||
136 | + target_ulong cs_base; | ||
137 | + | ||
138 | uint32_t flags; /* flags defining in which context the code was generated */ | ||
139 | uint32_t cflags; /* compile flags */ | ||
140 | |||
141 | @@ -XXX,XX +XXX,XX @@ struct TranslationBlock { | ||
142 | /* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */ | ||
143 | static inline target_ulong tb_pc(const TranslationBlock *tb) | ||
144 | { | ||
145 | +#if TARGET_TB_PCREL | ||
146 | + qemu_build_not_reached(); | ||
147 | +#else | ||
148 | return tb->pc; | ||
149 | +#endif | ||
150 | } | ||
151 | |||
152 | /* Hide the qatomic_read to make code a little easier on the eyes */ | ||
153 | diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c | ||
154 | index XXXXXXX..XXXXXXX 100644 | ||
155 | --- a/accel/tcg/cpu-exec.c | ||
156 | +++ b/accel/tcg/cpu-exec.c | ||
157 | @@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d) | ||
158 | const TranslationBlock *tb = p; | ||
159 | const struct tb_desc *desc = d; | ||
160 | |||
161 | - if (tb_pc(tb) == desc->pc && | ||
162 | + if ((TARGET_TB_PCREL || tb_pc(tb) == desc->pc) && | ||
163 | tb->page_addr[0] == desc->page_addr0 && | ||
164 | tb->cs_base == desc->cs_base && | ||
165 | tb->flags == desc->flags && | ||
166 | @@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, | ||
167 | return NULL; | ||
168 | } | ||
169 | desc.page_addr0 = phys_pc; | ||
170 | - h = tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate); | ||
171 | + h = tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : pc), | ||
172 | + flags, cflags, *cpu->trace_dstate); | ||
173 | return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); | ||
174 | } | ||
175 | |||
176 | @@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc, | ||
177 | uint32_t flags, uint32_t cflags) | ||
178 | { | ||
179 | TranslationBlock *tb; | ||
180 | + CPUJumpCache *jc; | ||
181 | uint32_t hash; | ||
182 | |||
183 | /* we should never be trying to look up an INVALID tb */ | ||
184 | tcg_debug_assert(!(cflags & CF_INVALID)); | ||
185 | |||
186 | hash = tb_jmp_cache_hash_func(pc); | ||
187 | - tb = qatomic_rcu_read(&cpu->tb_jmp_cache->array[hash].tb); | ||
188 | + jc = cpu->tb_jmp_cache; | ||
189 | + tb = tb_jmp_cache_get_tb(jc, hash); | ||
190 | |||
191 | if (likely(tb && | ||
192 | - tb->pc == pc && | ||
193 | + tb_jmp_cache_get_pc(jc, hash, tb) == pc && | ||
194 | tb->cs_base == cs_base && | ||
195 | tb->flags == flags && | ||
196 | tb->trace_vcpu_dstate == *cpu->trace_dstate && | ||
197 | @@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc, | ||
198 | if (tb == NULL) { | ||
199 | return NULL; | ||
200 | } | ||
201 | - qatomic_set(&cpu->tb_jmp_cache->array[hash].tb, tb); | ||
202 | + tb_jmp_cache_set(jc, hash, tb, pc); | ||
203 | return tb; | ||
204 | } | ||
205 | |||
206 | @@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) | ||
207 | if (cc->tcg_ops->synchronize_from_tb) { | ||
208 | cc->tcg_ops->synchronize_from_tb(cpu, last_tb); | ||
209 | } else { | ||
210 | + assert(!TARGET_TB_PCREL); | ||
211 | assert(cc->set_pc); | ||
212 | cc->set_pc(cpu, tb_pc(last_tb)); | ||
213 | } | ||
214 | @@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu) | ||
215 | * for the fast lookup | ||
216 | */ | ||
217 | h = tb_jmp_cache_hash_func(pc); | ||
218 | - qatomic_set(&cpu->tb_jmp_cache->array[h].tb, tb); | ||
219 | + tb_jmp_cache_set(cpu->tb_jmp_cache, h, tb, pc); | ||
220 | } | ||
221 | |||
222 | #ifndef CONFIG_USER_ONLY | ||
223 | diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c | ||
224 | index XXXXXXX..XXXXXXX 100644 | ||
225 | --- a/accel/tcg/translate-all.c | ||
226 | +++ b/accel/tcg/translate-all.c | ||
227 | @@ -XXX,XX +XXX,XX @@ static int encode_search(TranslationBlock *tb, uint8_t *block) | ||
228 | |||
229 | for (j = 0; j < TARGET_INSN_START_WORDS; ++j) { | ||
230 | if (i == 0) { | ||
231 | - prev = (j == 0 ? tb_pc(tb) : 0); | ||
232 | + prev = (!TARGET_TB_PCREL && j == 0 ? tb_pc(tb) : 0); | ||
233 | } else { | ||
234 | prev = tcg_ctx->gen_insn_data[i - 1][j]; | ||
235 | } | ||
236 | @@ -XXX,XX +XXX,XX @@ static int encode_search(TranslationBlock *tb, uint8_t *block) | ||
237 | static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, | ||
238 | uintptr_t searched_pc, bool reset_icount) | ||
239 | { | ||
240 | - target_ulong data[TARGET_INSN_START_WORDS] = { tb_pc(tb) }; | ||
241 | + target_ulong data[TARGET_INSN_START_WORDS]; | ||
242 | uintptr_t host_pc = (uintptr_t)tb->tc.ptr; | ||
243 | CPUArchState *env = cpu->env_ptr; | ||
244 | const uint8_t *p = tb->tc.ptr + tb->tc.size; | ||
245 | @@ -XXX,XX +XXX,XX @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, | ||
51 | return -1; | 246 | return -1; |
52 | case INDEX_op_mul_vec: | 247 | } |
53 | case INDEX_op_smax_vec: | 248 | |
54 | @@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, | 249 | + memset(data, 0, sizeof(data)); |
55 | TCGArg a0, ...) | 250 | + if (!TARGET_TB_PCREL) { |
56 | { | 251 | + data[0] = tb_pc(tb); |
57 | va_list va; | 252 | + } |
58 | - TCGv_vec v0, v1, v2, t1; | 253 | + |
59 | + TCGv_vec v0, v1, v2, t1, t2; | 254 | /* Reconstruct the stored insn data while looking for the point at |
60 | + TCGArg a2; | 255 | which the end of the insn exceeds the searched_pc. */ |
61 | 256 | for (i = 0; i < num_insns; ++i) { | |
62 | va_start(va, a0); | 257 | @@ -XXX,XX +XXX,XX @@ static bool tb_cmp(const void *ap, const void *bp) |
63 | v0 = temp_tcgv_vec(arg_temp(a0)); | 258 | const TranslationBlock *a = ap; |
64 | v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); | 259 | const TranslationBlock *b = bp; |
65 | - v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); | 260 | |
66 | + a2 = va_arg(va, TCGArg); | 261 | - return tb_pc(a) == tb_pc(b) && |
67 | + v2 = temp_tcgv_vec(arg_temp(a2)); | 262 | - a->cs_base == b->cs_base && |
68 | 263 | - a->flags == b->flags && | |
69 | switch (opc) { | 264 | - (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) && |
70 | + case INDEX_op_rotli_vec: | 265 | - a->trace_vcpu_dstate == b->trace_vcpu_dstate && |
71 | + t1 = tcg_temp_new_vec(type); | 266 | - a->page_addr[0] == b->page_addr[0] && |
72 | + tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); | 267 | - a->page_addr[1] == b->page_addr[1]; |
73 | + vec_gen_4(INDEX_op_aa64_sli_vec, type, vece, | 268 | + return ((TARGET_TB_PCREL || tb_pc(a) == tb_pc(b)) && |
74 | + tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); | 269 | + a->cs_base == b->cs_base && |
75 | + tcg_temp_free_vec(t1); | 270 | + a->flags == b->flags && |
76 | + break; | 271 | + (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) && |
77 | + | 272 | + a->trace_vcpu_dstate == b->trace_vcpu_dstate && |
78 | case INDEX_op_shrv_vec: | 273 | + a->page_addr[0] == b->page_addr[0] && |
79 | case INDEX_op_sarv_vec: | 274 | + a->page_addr[1] == b->page_addr[1]); |
80 | /* Right shifts are negative left shifts for AArch64. */ | 275 | } |
81 | @@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, | 276 | |
82 | tcg_temp_free_vec(t1); | 277 | void tb_htable_init(void) |
83 | break; | 278 | @@ -XXX,XX +XXX,XX @@ static inline void tb_jmp_unlink(TranslationBlock *dest) |
84 | 279 | qemu_spin_unlock(&dest->jmp_lock); | |
85 | + case INDEX_op_rotlv_vec: | 280 | } |
86 | + t1 = tcg_temp_new_vec(type); | 281 | |
87 | + tcg_gen_dupi_vec(vece, t1, 8 << vece); | 282 | +static void tb_jmp_cache_inval_tb(TranslationBlock *tb) |
88 | + tcg_gen_sub_vec(vece, t1, v2, t1); | 283 | +{ |
89 | + /* Right shifts are negative left shifts for AArch64. */ | 284 | + CPUState *cpu; |
90 | + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), | 285 | + |
91 | + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); | 286 | + if (TARGET_TB_PCREL) { |
92 | + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(v0), | 287 | + /* A TB may be at any virtual address */ |
93 | + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); | 288 | + CPU_FOREACH(cpu) { |
94 | + tcg_gen_or_vec(vece, v0, v0, t1); | 289 | + tcg_flush_jmp_cache(cpu); |
95 | + tcg_temp_free_vec(t1); | 290 | + } |
96 | + break; | 291 | + } else { |
97 | + | 292 | + uint32_t h = tb_jmp_cache_hash_func(tb_pc(tb)); |
98 | + case INDEX_op_rotrv_vec: | 293 | + |
99 | + t1 = tcg_temp_new_vec(type); | 294 | + CPU_FOREACH(cpu) { |
100 | + t2 = tcg_temp_new_vec(type); | 295 | + CPUJumpCache *jc = cpu->tb_jmp_cache; |
101 | + tcg_gen_neg_vec(vece, t1, v2); | 296 | + |
102 | + tcg_gen_dupi_vec(vece, t2, 8 << vece); | 297 | + if (qatomic_read(&jc->array[h].tb) == tb) { |
103 | + tcg_gen_add_vec(vece, t2, t1, t2); | 298 | + qatomic_set(&jc->array[h].tb, NULL); |
104 | + /* Right shifts are negative left shifts for AArch64. */ | 299 | + } |
105 | + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), | 300 | + } |
106 | + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); | 301 | + } |
107 | + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t2), | 302 | +} |
108 | + tcgv_vec_arg(v1), tcgv_vec_arg(t2)); | 303 | + |
109 | + tcg_gen_or_vec(vece, v0, t1, t2); | 304 | /* |
110 | + tcg_temp_free_vec(t1); | 305 | * In user-mode, call with mmap_lock held. |
111 | + tcg_temp_free_vec(t2); | 306 | * In !user-mode, if @rm_from_page_list is set, call with the TB's pages' |
112 | + break; | 307 | @@ -XXX,XX +XXX,XX @@ static inline void tb_jmp_unlink(TranslationBlock *dest) |
113 | + | 308 | */ |
114 | default: | 309 | static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) |
115 | g_assert_not_reached(); | 310 | { |
116 | } | 311 | - CPUState *cpu; |
117 | @@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) | 312 | PageDesc *p; |
118 | static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } }; | 313 | uint32_t h; |
119 | static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; | 314 | tb_page_addr_t phys_pc; |
120 | static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } }; | 315 | @@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) |
121 | + static const TCGTargetOpDef w_0_w = { .args_ct_str = { "w", "0", "w" } }; | 316 | |
122 | static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } }; | 317 | /* remove the TB from the hash list */ |
123 | static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } }; | 318 | phys_pc = tb->page_addr[0]; |
124 | static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } }; | 319 | - h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, orig_cflags, |
125 | @@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) | 320 | - tb->trace_vcpu_dstate); |
126 | return &w_w_wZ; | 321 | + h = tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)), |
127 | case INDEX_op_bitsel_vec: | 322 | + tb->flags, orig_cflags, tb->trace_vcpu_dstate); |
128 | return &w_w_w_w; | 323 | if (!qht_remove(&tb_ctx.htable, tb, h)) { |
129 | + case INDEX_op_aa64_sli_vec: | 324 | return; |
130 | + return &w_0_w; | 325 | } |
131 | 326 | @@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) | |
132 | default: | 327 | } |
133 | return NULL; | 328 | |
329 | /* remove the TB from the hash list */ | ||
330 | - h = tb_jmp_cache_hash_func(tb->pc); | ||
331 | - CPU_FOREACH(cpu) { | ||
332 | - CPUJumpCache *jc = cpu->tb_jmp_cache; | ||
333 | - if (qatomic_read(&jc->array[h].tb) == tb) { | ||
334 | - qatomic_set(&jc->array[h].tb, NULL); | ||
335 | - } | ||
336 | - } | ||
337 | + tb_jmp_cache_inval_tb(tb); | ||
338 | |||
339 | /* suppress this TB from the two jump lists */ | ||
340 | tb_remove_from_jmp_list(tb, 0); | ||
341 | @@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, | ||
342 | } | ||
343 | |||
344 | /* add in the hash table */ | ||
345 | - h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, tb->cflags, | ||
346 | - tb->trace_vcpu_dstate); | ||
347 | + h = tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)), | ||
348 | + tb->flags, tb->cflags, tb->trace_vcpu_dstate); | ||
349 | qht_insert(&tb_ctx.htable, tb, h, &existing_tb); | ||
350 | |||
351 | /* remove TB from the page(s) if we couldn't insert it */ | ||
352 | @@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu, | ||
353 | |||
354 | gen_code_buf = tcg_ctx->code_gen_ptr; | ||
355 | tb->tc.ptr = tcg_splitwx_to_rx(gen_code_buf); | ||
356 | +#if !TARGET_TB_PCREL | ||
357 | tb->pc = pc; | ||
358 | +#endif | ||
359 | tb->cs_base = cs_base; | ||
360 | tb->flags = flags; | ||
361 | tb->cflags = cflags; | ||
134 | -- | 362 | -- |
135 | 2.25.1 | 363 | 2.34.1 |
136 | 364 | ||
137 | 365 | diff view generated by jsdifflib |
1 | From: Nick Hudson <skrll@netbsd.org> | 1 | From: Leandro Lupori <leandro.lupori@eldorado.org.br> |
---|---|---|---|
2 | 2 | ||
3 | Fix qemu build on NetBSD/evbarm-aarch64 by providing a NetBSD specific | 3 | PowerPC64 processors handle direct branches better than indirect |
4 | cpu_signal_handler. | 4 | ones, resulting in less stalled cycles and branch misses. |
5 | |||
6 | However, PPC's tb_target_set_jmp_target() was only using direct | ||
7 | branches for 16-bit jumps, while PowerPC64's unconditional branch | ||
8 | instructions are able to handle displacements of up to 26 bits. | ||
9 | To take advantage of this, now jumps whose displacements fit in | ||
10 | between 17 and 26 bits are also converted to direct branches. | ||
5 | 11 | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Signed-off-by: Nick Hudson <skrll@netbsd.org> | 13 | Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br> |
8 | Message-Id: <20200517101529.5367-1-skrll@netbsd.org> | 14 | [rth: Expanded some commentary.] |
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 15 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | --- | 16 | --- |
11 | accel/tcg/user-exec.c | 27 +++++++++++++++++++++++++++ | 17 | tcg/ppc/tcg-target.c.inc | 119 +++++++++++++++++++++++++++++---------- |
12 | 1 file changed, 27 insertions(+) | 18 | 1 file changed, 88 insertions(+), 31 deletions(-) |
13 | 19 | ||
14 | diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c | 20 | diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc |
15 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/accel/tcg/user-exec.c | 22 | --- a/tcg/ppc/tcg-target.c.inc |
17 | +++ b/accel/tcg/user-exec.c | 23 | +++ b/tcg/ppc/tcg-target.c.inc |
18 | @@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo, | 24 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) |
19 | 25 | tcg_out32(s, insn); | |
20 | #elif defined(__aarch64__) | 26 | } |
21 | 27 | ||
22 | +#if defined(__NetBSD__) | 28 | +static inline uint64_t make_pair(tcg_insn_unit i1, tcg_insn_unit i2) |
29 | +{ | ||
30 | + if (HOST_BIG_ENDIAN) { | ||
31 | + return (uint64_t)i1 << 32 | i2; | ||
32 | + } | ||
33 | + return (uint64_t)i2 << 32 | i1; | ||
34 | +} | ||
23 | + | 35 | + |
24 | +#include <ucontext.h> | 36 | +static inline void ppc64_replace2(uintptr_t rx, uintptr_t rw, |
25 | +#include <sys/siginfo.h> | 37 | + tcg_insn_unit i0, tcg_insn_unit i1) |
38 | +{ | ||
39 | +#if TCG_TARGET_REG_BITS == 64 | ||
40 | + qatomic_set((uint64_t *)rw, make_pair(i0, i1)); | ||
41 | + flush_idcache_range(rx, rw, 8); | ||
42 | +#else | ||
43 | + qemu_build_not_reached(); | ||
44 | +#endif | ||
45 | +} | ||
26 | + | 46 | + |
27 | +int cpu_signal_handler(int host_signum, void *pinfo, void *puc) | 47 | +static inline void ppc64_replace4(uintptr_t rx, uintptr_t rw, |
48 | + tcg_insn_unit i0, tcg_insn_unit i1, | ||
49 | + tcg_insn_unit i2, tcg_insn_unit i3) | ||
28 | +{ | 50 | +{ |
29 | + ucontext_t *uc = puc; | 51 | + uint64_t p[2]; |
30 | + siginfo_t *si = pinfo; | ||
31 | + unsigned long pc; | ||
32 | + int is_write; | ||
33 | + uint32_t esr; | ||
34 | + | 52 | + |
35 | + pc = uc->uc_mcontext.__gregs[_REG_PC]; | 53 | + p[!HOST_BIG_ENDIAN] = make_pair(i0, i1); |
36 | + esr = si->si_trap; | 54 | + p[HOST_BIG_ENDIAN] = make_pair(i2, i3); |
37 | + | 55 | + |
38 | + /* | 56 | + /* |
39 | + * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC | 57 | + * There's no convenient way to get the compiler to allocate a pair |
40 | + * is 0b10010x: then bit 6 is the WnR bit | 58 | + * of registers at an even index, so copy into r6/r7 and clobber. |
41 | + */ | 59 | + */ |
42 | + is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; | 60 | + asm("mr %%r6, %1\n\t" |
43 | + return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask); | 61 | + "mr %%r7, %2\n\t" |
62 | + "stq %%r6, %0" | ||
63 | + : "=Q"(*(__int128 *)rw) : "r"(p[0]), "r"(p[1]) : "r6", "r7"); | ||
64 | + flush_idcache_range(rx, rw, 16); | ||
44 | +} | 65 | +} |
45 | + | 66 | + |
46 | +#else | 67 | void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, |
68 | uintptr_t jmp_rw, uintptr_t addr) | ||
69 | { | ||
70 | - if (TCG_TARGET_REG_BITS == 64) { | ||
71 | - tcg_insn_unit i1, i2; | ||
72 | - intptr_t tb_diff = addr - tc_ptr; | ||
73 | - intptr_t br_diff = addr - (jmp_rx + 4); | ||
74 | - uint64_t pair; | ||
75 | + tcg_insn_unit i0, i1, i2, i3; | ||
76 | + intptr_t tb_diff = addr - tc_ptr; | ||
77 | + intptr_t br_diff = addr - (jmp_rx + 4); | ||
78 | + intptr_t lo, hi; | ||
79 | |||
80 | - /* This does not exercise the range of the branch, but we do | ||
81 | - still need to be able to load the new value of TCG_REG_TB. | ||
82 | - But this does still happen quite often. */ | ||
83 | - if (tb_diff == (int16_t)tb_diff) { | ||
84 | - i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff); | ||
85 | - i2 = B | (br_diff & 0x3fffffc); | ||
86 | - } else { | ||
87 | - intptr_t lo = (int16_t)tb_diff; | ||
88 | - intptr_t hi = (int32_t)(tb_diff - lo); | ||
89 | - assert(tb_diff == hi + lo); | ||
90 | - i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16); | ||
91 | - i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo); | ||
92 | - } | ||
93 | -#if HOST_BIG_ENDIAN | ||
94 | - pair = (uint64_t)i1 << 32 | i2; | ||
95 | -#else | ||
96 | - pair = (uint64_t)i2 << 32 | i1; | ||
97 | -#endif | ||
98 | - | ||
99 | - /* As per the enclosing if, this is ppc64. Avoid the _Static_assert | ||
100 | - within qatomic_set that would fail to build a ppc32 host. */ | ||
101 | - qatomic_set__nocheck((uint64_t *)jmp_rw, pair); | ||
102 | - flush_idcache_range(jmp_rx, jmp_rw, 8); | ||
103 | - } else { | ||
104 | + if (TCG_TARGET_REG_BITS == 32) { | ||
105 | intptr_t diff = addr - jmp_rx; | ||
106 | tcg_debug_assert(in_range_b(diff)); | ||
107 | qatomic_set((uint32_t *)jmp_rw, B | (diff & 0x3fffffc)); | ||
108 | flush_idcache_range(jmp_rx, jmp_rw, 4); | ||
109 | + return; | ||
110 | } | ||
47 | + | 111 | + |
48 | #ifndef ESR_MAGIC | 112 | + /* |
49 | /* Pre-3.16 kernel headers don't have these, so provide fallback definitions */ | 113 | + * For 16-bit displacements, we can use a single add + branch. |
50 | #define ESR_MAGIC 0x45535201 | 114 | + * This happens quite often. |
51 | @@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo, void *puc) | 115 | + */ |
52 | } | 116 | + if (tb_diff == (int16_t)tb_diff) { |
53 | return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); | 117 | + i0 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff); |
118 | + i1 = B | (br_diff & 0x3fffffc); | ||
119 | + ppc64_replace2(jmp_rx, jmp_rw, i0, i1); | ||
120 | + return; | ||
121 | + } | ||
122 | + | ||
123 | + lo = (int16_t)tb_diff; | ||
124 | + hi = (int32_t)(tb_diff - lo); | ||
125 | + assert(tb_diff == hi + lo); | ||
126 | + i0 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16); | ||
127 | + i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo); | ||
128 | + | ||
129 | + /* | ||
130 | + * Without stq from 2.07, we can only update two insns, | ||
131 | + * and those must be the ones that load the target address. | ||
132 | + */ | ||
133 | + if (!have_isa_2_07) { | ||
134 | + ppc64_replace2(jmp_rx, jmp_rw, i0, i1); | ||
135 | + return; | ||
136 | + } | ||
137 | + | ||
138 | + /* | ||
139 | + * For 26-bit displacements, we can use a direct branch. | ||
140 | + * Otherwise we still need the indirect branch, which we | ||
141 | + * must restore after a potential direct branch write. | ||
142 | + */ | ||
143 | + br_diff -= 4; | ||
144 | + if (in_range_b(br_diff)) { | ||
145 | + i2 = B | (br_diff & 0x3fffffc); | ||
146 | + i3 = NOP; | ||
147 | + } else { | ||
148 | + i2 = MTSPR | RS(TCG_REG_TB) | CTR; | ||
149 | + i3 = BCCTR | BO_ALWAYS; | ||
150 | + } | ||
151 | + ppc64_replace4(jmp_rx, jmp_rw, i0, i1, i2, i3); | ||
54 | } | 152 | } |
55 | +#endif | 153 | |
56 | 154 | static void tcg_out_call_int(TCGContext *s, int lk, | |
57 | #elif defined(__s390__) | 155 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, |
58 | 156 | if (s->tb_jmp_insn_offset) { | |
157 | /* Direct jump. */ | ||
158 | if (TCG_TARGET_REG_BITS == 64) { | ||
159 | - /* Ensure the next insns are 8-byte aligned. */ | ||
160 | - if ((uintptr_t)s->code_ptr & 7) { | ||
161 | + /* Ensure the next insns are 8 or 16-byte aligned. */ | ||
162 | + while ((uintptr_t)s->code_ptr & (have_isa_2_07 ? 15 : 7)) { | ||
163 | tcg_out32(s, NOP); | ||
164 | } | ||
165 | s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s); | ||
59 | -- | 166 | -- |
60 | 2.25.1 | 167 | 2.34.1 |
61 | |||
62 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The value previously chosen overlaps GUSA_MASK. | ||
1 | 2 | ||
3 | Rename all DELAY_SLOT_* and GUSA_* defines to emphasize | ||
4 | that they are included in TB_FLAGs. Add aliases for the | ||
5 | FPSCR and SR bits that are included in TB_FLAGS, so that | ||
6 | we don't accidentally reassign those bits. | ||
7 | |||
8 | Fixes: 4da06fb3062 ("target/sh4: Implement prctl_unalign_sigbus") | ||
9 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/856 | ||
10 | Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> | ||
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | --- | ||
13 | target/sh4/cpu.h | 56 +++++++++++++------------ | ||
14 | linux-user/sh4/signal.c | 6 +-- | ||
15 | target/sh4/cpu.c | 6 +-- | ||
16 | target/sh4/helper.c | 6 +-- | ||
17 | target/sh4/translate.c | 90 ++++++++++++++++++++++------------------- | ||
18 | 5 files changed, 88 insertions(+), 76 deletions(-) | ||
19 | |||
20 | diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/target/sh4/cpu.h | ||
23 | +++ b/target/sh4/cpu.h | ||
24 | @@ -XXX,XX +XXX,XX @@ | ||
25 | #define FPSCR_RM_NEAREST (0 << 0) | ||
26 | #define FPSCR_RM_ZERO (1 << 0) | ||
27 | |||
28 | -#define DELAY_SLOT_MASK 0x7 | ||
29 | -#define DELAY_SLOT (1 << 0) | ||
30 | -#define DELAY_SLOT_CONDITIONAL (1 << 1) | ||
31 | -#define DELAY_SLOT_RTE (1 << 2) | ||
32 | +#define TB_FLAG_DELAY_SLOT (1 << 0) | ||
33 | +#define TB_FLAG_DELAY_SLOT_COND (1 << 1) | ||
34 | +#define TB_FLAG_DELAY_SLOT_RTE (1 << 2) | ||
35 | +#define TB_FLAG_PENDING_MOVCA (1 << 3) | ||
36 | +#define TB_FLAG_GUSA_SHIFT 4 /* [11:4] */ | ||
37 | +#define TB_FLAG_GUSA_EXCLUSIVE (1 << 12) | ||
38 | +#define TB_FLAG_UNALIGN (1 << 13) | ||
39 | +#define TB_FLAG_SR_FD (1 << SR_FD) /* 15 */ | ||
40 | +#define TB_FLAG_FPSCR_PR FPSCR_PR /* 19 */ | ||
41 | +#define TB_FLAG_FPSCR_SZ FPSCR_SZ /* 20 */ | ||
42 | +#define TB_FLAG_FPSCR_FR FPSCR_FR /* 21 */ | ||
43 | +#define TB_FLAG_SR_RB (1 << SR_RB) /* 29 */ | ||
44 | +#define TB_FLAG_SR_MD (1 << SR_MD) /* 30 */ | ||
45 | |||
46 | -#define TB_FLAG_PENDING_MOVCA (1 << 3) | ||
47 | -#define TB_FLAG_UNALIGN (1 << 4) | ||
48 | - | ||
49 | -#define GUSA_SHIFT 4 | ||
50 | -#ifdef CONFIG_USER_ONLY | ||
51 | -#define GUSA_EXCLUSIVE (1 << 12) | ||
52 | -#define GUSA_MASK ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE) | ||
53 | -#else | ||
54 | -/* Provide dummy versions of the above to allow tests against tbflags | ||
55 | - to be elided while avoiding ifdefs. */ | ||
56 | -#define GUSA_EXCLUSIVE 0 | ||
57 | -#define GUSA_MASK 0 | ||
58 | -#endif | ||
59 | - | ||
60 | -#define TB_FLAG_ENVFLAGS_MASK (DELAY_SLOT_MASK | GUSA_MASK) | ||
61 | +#define TB_FLAG_DELAY_SLOT_MASK (TB_FLAG_DELAY_SLOT | \ | ||
62 | + TB_FLAG_DELAY_SLOT_COND | \ | ||
63 | + TB_FLAG_DELAY_SLOT_RTE) | ||
64 | +#define TB_FLAG_GUSA_MASK ((0xff << TB_FLAG_GUSA_SHIFT) | \ | ||
65 | + TB_FLAG_GUSA_EXCLUSIVE) | ||
66 | +#define TB_FLAG_FPSCR_MASK (TB_FLAG_FPSCR_PR | \ | ||
67 | + TB_FLAG_FPSCR_SZ | \ | ||
68 | + TB_FLAG_FPSCR_FR) | ||
69 | +#define TB_FLAG_SR_MASK (TB_FLAG_SR_FD | \ | ||
70 | + TB_FLAG_SR_RB | \ | ||
71 | + TB_FLAG_SR_MD) | ||
72 | +#define TB_FLAG_ENVFLAGS_MASK (TB_FLAG_DELAY_SLOT_MASK | \ | ||
73 | + TB_FLAG_GUSA_MASK) | ||
74 | |||
75 | typedef struct tlb_t { | ||
76 | uint32_t vpn; /* virtual page number */ | ||
77 | @@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch) | ||
78 | { | ||
79 | /* The instruction in a RTE delay slot is fetched in privileged | ||
80 | mode, but executed in user mode. */ | ||
81 | - if (ifetch && (env->flags & DELAY_SLOT_RTE)) { | ||
82 | + if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) { | ||
83 | return 0; | ||
84 | } else { | ||
85 | return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0; | ||
86 | @@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc, | ||
87 | { | ||
88 | *pc = env->pc; | ||
89 | /* For a gUSA region, notice the end of the region. */ | ||
90 | - *cs_base = env->flags & GUSA_MASK ? env->gregs[0] : 0; | ||
91 | - *flags = env->flags /* TB_FLAG_ENVFLAGS_MASK: bits 0-2, 4-12 */ | ||
92 | - | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */ | ||
93 | - | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */ | ||
94 | - | (env->sr & (1u << SR_FD)) /* Bit 15 */ | ||
95 | + *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; | ||
96 | + *flags = env->flags | ||
97 | + | (env->fpscr & TB_FLAG_FPSCR_MASK) | ||
98 | + | (env->sr & TB_FLAG_SR_MASK) | ||
99 | | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ | ||
100 | #ifdef CONFIG_USER_ONLY | ||
101 | *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; | ||
102 | diff --git a/linux-user/sh4/signal.c b/linux-user/sh4/signal.c | ||
103 | index XXXXXXX..XXXXXXX 100644 | ||
104 | --- a/linux-user/sh4/signal.c | ||
105 | +++ b/linux-user/sh4/signal.c | ||
106 | @@ -XXX,XX +XXX,XX @@ static void restore_sigcontext(CPUSH4State *regs, struct target_sigcontext *sc) | ||
107 | __get_user(regs->fpul, &sc->sc_fpul); | ||
108 | |||
109 | regs->tra = -1; /* disable syscall checks */ | ||
110 | - regs->flags &= ~(DELAY_SLOT_MASK | GUSA_MASK); | ||
111 | + regs->flags = 0; | ||
112 | } | ||
113 | |||
114 | void setup_frame(int sig, struct target_sigaction *ka, | ||
115 | @@ -XXX,XX +XXX,XX @@ void setup_frame(int sig, struct target_sigaction *ka, | ||
116 | regs->gregs[5] = 0; | ||
117 | regs->gregs[6] = frame_addr += offsetof(typeof(*frame), sc); | ||
118 | regs->pc = (unsigned long) ka->_sa_handler; | ||
119 | - regs->flags &= ~(DELAY_SLOT_MASK | GUSA_MASK); | ||
120 | + regs->flags &= ~(TB_FLAG_DELAY_SLOT_MASK | TB_FLAG_GUSA_MASK); | ||
121 | |||
122 | unlock_user_struct(frame, frame_addr, 1); | ||
123 | return; | ||
124 | @@ -XXX,XX +XXX,XX @@ void setup_rt_frame(int sig, struct target_sigaction *ka, | ||
125 | regs->gregs[5] = frame_addr + offsetof(typeof(*frame), info); | ||
126 | regs->gregs[6] = frame_addr + offsetof(typeof(*frame), uc); | ||
127 | regs->pc = (unsigned long) ka->_sa_handler; | ||
128 | - regs->flags &= ~(DELAY_SLOT_MASK | GUSA_MASK); | ||
129 | + regs->flags &= ~(TB_FLAG_DELAY_SLOT_MASK | TB_FLAG_GUSA_MASK); | ||
130 | |||
131 | unlock_user_struct(frame, frame_addr, 1); | ||
132 | return; | ||
133 | diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c | ||
134 | index XXXXXXX..XXXXXXX 100644 | ||
135 | --- a/target/sh4/cpu.c | ||
136 | +++ b/target/sh4/cpu.c | ||
137 | @@ -XXX,XX +XXX,XX @@ static void superh_cpu_synchronize_from_tb(CPUState *cs, | ||
138 | SuperHCPU *cpu = SUPERH_CPU(cs); | ||
139 | |||
140 | cpu->env.pc = tb_pc(tb); | ||
141 | - cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK; | ||
142 | + cpu->env.flags = tb->flags; | ||
143 | } | ||
144 | |||
145 | #ifndef CONFIG_USER_ONLY | ||
146 | @@ -XXX,XX +XXX,XX @@ static bool superh_io_recompile_replay_branch(CPUState *cs, | ||
147 | SuperHCPU *cpu = SUPERH_CPU(cs); | ||
148 | CPUSH4State *env = &cpu->env; | ||
149 | |||
150 | - if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 | ||
151 | + if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND)) | ||
152 | && env->pc != tb_pc(tb)) { | ||
153 | env->pc -= 2; | ||
154 | - env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); | ||
155 | + env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND); | ||
156 | return true; | ||
157 | } | ||
158 | return false; | ||
159 | diff --git a/target/sh4/helper.c b/target/sh4/helper.c | ||
160 | index XXXXXXX..XXXXXXX 100644 | ||
161 | --- a/target/sh4/helper.c | ||
162 | +++ b/target/sh4/helper.c | ||
163 | @@ -XXX,XX +XXX,XX @@ void superh_cpu_do_interrupt(CPUState *cs) | ||
164 | env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB); | ||
165 | env->lock_addr = -1; | ||
166 | |||
167 | - if (env->flags & DELAY_SLOT_MASK) { | ||
168 | + if (env->flags & TB_FLAG_DELAY_SLOT_MASK) { | ||
169 | /* Branch instruction should be executed again before delay slot. */ | ||
170 | env->spc -= 2; | ||
171 | /* Clear flags for exception/interrupt routine. */ | ||
172 | - env->flags &= ~DELAY_SLOT_MASK; | ||
173 | + env->flags &= ~TB_FLAG_DELAY_SLOT_MASK; | ||
174 | } | ||
175 | |||
176 | if (do_exp) { | ||
177 | @@ -XXX,XX +XXX,XX @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | ||
178 | CPUSH4State *env = &cpu->env; | ||
179 | |||
180 | /* Delay slots are indivisible, ignore interrupts */ | ||
181 | - if (env->flags & DELAY_SLOT_MASK) { | ||
182 | + if (env->flags & TB_FLAG_DELAY_SLOT_MASK) { | ||
183 | return false; | ||
184 | } else { | ||
185 | superh_cpu_do_interrupt(cs); | ||
186 | diff --git a/target/sh4/translate.c b/target/sh4/translate.c | ||
187 | index XXXXXXX..XXXXXXX 100644 | ||
188 | --- a/target/sh4/translate.c | ||
189 | +++ b/target/sh4/translate.c | ||
190 | @@ -XXX,XX +XXX,XX @@ void superh_cpu_dump_state(CPUState *cs, FILE *f, int flags) | ||
191 | i, env->gregs[i], i + 1, env->gregs[i + 1], | ||
192 | i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]); | ||
193 | } | ||
194 | - if (env->flags & DELAY_SLOT) { | ||
195 | + if (env->flags & TB_FLAG_DELAY_SLOT) { | ||
196 | qemu_printf("in delay slot (delayed_pc=0x%08x)\n", | ||
197 | env->delayed_pc); | ||
198 | - } else if (env->flags & DELAY_SLOT_CONDITIONAL) { | ||
199 | + } else if (env->flags & TB_FLAG_DELAY_SLOT_COND) { | ||
200 | qemu_printf("in conditional delay slot (delayed_pc=0x%08x)\n", | ||
201 | env->delayed_pc); | ||
202 | - } else if (env->flags & DELAY_SLOT_RTE) { | ||
203 | + } else if (env->flags & TB_FLAG_DELAY_SLOT_RTE) { | ||
204 | qemu_fprintf(f, "in rte delay slot (delayed_pc=0x%08x)\n", | ||
205 | env->delayed_pc); | ||
206 | } | ||
207 | @@ -XXX,XX +XXX,XX @@ static inline void gen_save_cpu_state(DisasContext *ctx, bool save_pc) | ||
208 | |||
209 | static inline bool use_exit_tb(DisasContext *ctx) | ||
210 | { | ||
211 | - return (ctx->tbflags & GUSA_EXCLUSIVE) != 0; | ||
212 | + return (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) != 0; | ||
213 | } | ||
214 | |||
215 | static bool use_goto_tb(DisasContext *ctx, target_ulong dest) | ||
216 | @@ -XXX,XX +XXX,XX @@ static void gen_conditional_jump(DisasContext *ctx, target_ulong dest, | ||
217 | TCGLabel *l1 = gen_new_label(); | ||
218 | TCGCond cond_not_taken = jump_if_true ? TCG_COND_EQ : TCG_COND_NE; | ||
219 | |||
220 | - if (ctx->tbflags & GUSA_EXCLUSIVE) { | ||
221 | + if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) { | ||
222 | /* When in an exclusive region, we must continue to the end. | ||
223 | Therefore, exit the region on a taken branch, but otherwise | ||
224 | fall through to the next instruction. */ | ||
225 | tcg_gen_brcondi_i32(cond_not_taken, cpu_sr_t, 0, l1); | ||
226 | - tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~GUSA_MASK); | ||
227 | + tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~TB_FLAG_GUSA_MASK); | ||
228 | /* Note that this won't actually use a goto_tb opcode because we | ||
229 | disallow it in use_goto_tb, but it handles exit + singlestep. */ | ||
230 | gen_goto_tb(ctx, 0, dest); | ||
231 | @@ -XXX,XX +XXX,XX @@ static void gen_delayed_conditional_jump(DisasContext * ctx) | ||
232 | tcg_gen_mov_i32(ds, cpu_delayed_cond); | ||
233 | tcg_gen_discard_i32(cpu_delayed_cond); | ||
234 | |||
235 | - if (ctx->tbflags & GUSA_EXCLUSIVE) { | ||
236 | + if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) { | ||
237 | /* When in an exclusive region, we must continue to the end. | ||
238 | Therefore, exit the region on a taken branch, but otherwise | ||
239 | fall through to the next instruction. */ | ||
240 | tcg_gen_brcondi_i32(TCG_COND_EQ, ds, 0, l1); | ||
241 | |||
242 | /* Leave the gUSA region. */ | ||
243 | - tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~GUSA_MASK); | ||
244 | + tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~TB_FLAG_GUSA_MASK); | ||
245 | gen_jump(ctx); | ||
246 | |||
247 | gen_set_label(l1); | ||
248 | @@ -XXX,XX +XXX,XX @@ static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) | ||
249 | #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) | ||
250 | |||
251 | #define CHECK_NOT_DELAY_SLOT \ | ||
252 | - if (ctx->envflags & DELAY_SLOT_MASK) { \ | ||
253 | - goto do_illegal_slot; \ | ||
254 | + if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) { \ | ||
255 | + goto do_illegal_slot; \ | ||
256 | } | ||
257 | |||
258 | #define CHECK_PRIVILEGED \ | ||
259 | @@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx) | ||
260 | case 0x000b: /* rts */ | ||
261 | CHECK_NOT_DELAY_SLOT | ||
262 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr); | ||
263 | - ctx->envflags |= DELAY_SLOT; | ||
264 | + ctx->envflags |= TB_FLAG_DELAY_SLOT; | ||
265 | ctx->delayed_pc = (uint32_t) - 1; | ||
266 | return; | ||
267 | case 0x0028: /* clrmac */ | ||
268 | @@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx) | ||
269 | CHECK_NOT_DELAY_SLOT | ||
270 | gen_write_sr(cpu_ssr); | ||
271 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc); | ||
272 | - ctx->envflags |= DELAY_SLOT_RTE; | ||
273 | + ctx->envflags |= TB_FLAG_DELAY_SLOT_RTE; | ||
274 | ctx->delayed_pc = (uint32_t) - 1; | ||
275 | ctx->base.is_jmp = DISAS_STOP; | ||
276 | return; | ||
277 | @@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx) | ||
278 | return; | ||
279 | case 0xe000: /* mov #imm,Rn */ | ||
280 | #ifdef CONFIG_USER_ONLY | ||
281 | - /* Detect the start of a gUSA region. If so, update envflags | ||
282 | - and end the TB. This will allow us to see the end of the | ||
283 | - region (stored in R0) in the next TB. */ | ||
284 | + /* | ||
285 | + * Detect the start of a gUSA region (mov #-n, r15). | ||
286 | + * If so, update envflags and end the TB. This will allow us | ||
287 | + * to see the end of the region (stored in R0) in the next TB. | ||
288 | + */ | ||
289 | if (B11_8 == 15 && B7_0s < 0 && | ||
290 | (tb_cflags(ctx->base.tb) & CF_PARALLEL)) { | ||
291 | - ctx->envflags = deposit32(ctx->envflags, GUSA_SHIFT, 8, B7_0s); | ||
292 | + ctx->envflags = | ||
293 | + deposit32(ctx->envflags, TB_FLAG_GUSA_SHIFT, 8, B7_0s); | ||
294 | ctx->base.is_jmp = DISAS_STOP; | ||
295 | } | ||
296 | #endif | ||
297 | @@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx) | ||
298 | case 0xa000: /* bra disp */ | ||
299 | CHECK_NOT_DELAY_SLOT | ||
300 | ctx->delayed_pc = ctx->base.pc_next + 4 + B11_0s * 2; | ||
301 | - ctx->envflags |= DELAY_SLOT; | ||
302 | + ctx->envflags |= TB_FLAG_DELAY_SLOT; | ||
303 | return; | ||
304 | case 0xb000: /* bsr disp */ | ||
305 | CHECK_NOT_DELAY_SLOT | ||
306 | tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4); | ||
307 | ctx->delayed_pc = ctx->base.pc_next + 4 + B11_0s * 2; | ||
308 | - ctx->envflags |= DELAY_SLOT; | ||
309 | + ctx->envflags |= TB_FLAG_DELAY_SLOT; | ||
310 | return; | ||
311 | } | ||
312 | |||
313 | @@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx) | ||
314 | CHECK_NOT_DELAY_SLOT | ||
315 | tcg_gen_xori_i32(cpu_delayed_cond, cpu_sr_t, 1); | ||
316 | ctx->delayed_pc = ctx->base.pc_next + 4 + B7_0s * 2; | ||
317 | - ctx->envflags |= DELAY_SLOT_CONDITIONAL; | ||
318 | + ctx->envflags |= TB_FLAG_DELAY_SLOT_COND; | ||
319 | return; | ||
320 | case 0x8900: /* bt label */ | ||
321 | CHECK_NOT_DELAY_SLOT | ||
322 | @@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx) | ||
323 | CHECK_NOT_DELAY_SLOT | ||
324 | tcg_gen_mov_i32(cpu_delayed_cond, cpu_sr_t); | ||
325 | ctx->delayed_pc = ctx->base.pc_next + 4 + B7_0s * 2; | ||
326 | - ctx->envflags |= DELAY_SLOT_CONDITIONAL; | ||
327 | + ctx->envflags |= TB_FLAG_DELAY_SLOT_COND; | ||
328 | return; | ||
329 | case 0x8800: /* cmp/eq #imm,R0 */ | ||
330 | tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(0), B7_0s); | ||
331 | @@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx) | ||
332 | case 0x0023: /* braf Rn */ | ||
333 | CHECK_NOT_DELAY_SLOT | ||
334 | tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->base.pc_next + 4); | ||
335 | - ctx->envflags |= DELAY_SLOT; | ||
336 | + ctx->envflags |= TB_FLAG_DELAY_SLOT; | ||
337 | ctx->delayed_pc = (uint32_t) - 1; | ||
338 | return; | ||
339 | case 0x0003: /* bsrf Rn */ | ||
340 | CHECK_NOT_DELAY_SLOT | ||
341 | tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4); | ||
342 | tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr); | ||
343 | - ctx->envflags |= DELAY_SLOT; | ||
344 | + ctx->envflags |= TB_FLAG_DELAY_SLOT; | ||
345 | ctx->delayed_pc = (uint32_t) - 1; | ||
346 | return; | ||
347 | case 0x4015: /* cmp/pl Rn */ | ||
348 | @@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx) | ||
349 | case 0x402b: /* jmp @Rn */ | ||
350 | CHECK_NOT_DELAY_SLOT | ||
351 | tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); | ||
352 | - ctx->envflags |= DELAY_SLOT; | ||
353 | + ctx->envflags |= TB_FLAG_DELAY_SLOT; | ||
354 | ctx->delayed_pc = (uint32_t) - 1; | ||
355 | return; | ||
356 | case 0x400b: /* jsr @Rn */ | ||
357 | CHECK_NOT_DELAY_SLOT | ||
358 | tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4); | ||
359 | tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); | ||
360 | - ctx->envflags |= DELAY_SLOT; | ||
361 | + ctx->envflags |= TB_FLAG_DELAY_SLOT; | ||
362 | ctx->delayed_pc = (uint32_t) - 1; | ||
363 | return; | ||
364 | case 0x400e: /* ldc Rm,SR */ | ||
365 | @@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx) | ||
366 | fflush(stderr); | ||
367 | #endif | ||
368 | do_illegal: | ||
369 | - if (ctx->envflags & DELAY_SLOT_MASK) { | ||
370 | + if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) { | ||
371 | do_illegal_slot: | ||
372 | gen_save_cpu_state(ctx, true); | ||
373 | gen_helper_raise_slot_illegal_instruction(cpu_env); | ||
374 | @@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx) | ||
375 | |||
376 | do_fpu_disabled: | ||
377 | gen_save_cpu_state(ctx, true); | ||
378 | - if (ctx->envflags & DELAY_SLOT_MASK) { | ||
379 | + if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) { | ||
380 | gen_helper_raise_slot_fpu_disable(cpu_env); | ||
381 | } else { | ||
382 | gen_helper_raise_fpu_disable(cpu_env); | ||
383 | @@ -XXX,XX +XXX,XX @@ static void decode_opc(DisasContext * ctx) | ||
384 | |||
385 | _decode_opc(ctx); | ||
386 | |||
387 | - if (old_flags & DELAY_SLOT_MASK) { | ||
388 | + if (old_flags & TB_FLAG_DELAY_SLOT_MASK) { | ||
389 | /* go out of the delay slot */ | ||
390 | - ctx->envflags &= ~DELAY_SLOT_MASK; | ||
391 | + ctx->envflags &= ~TB_FLAG_DELAY_SLOT_MASK; | ||
392 | |||
393 | /* When in an exclusive region, we must continue to the end | ||
394 | for conditional branches. */ | ||
395 | - if (ctx->tbflags & GUSA_EXCLUSIVE | ||
396 | - && old_flags & DELAY_SLOT_CONDITIONAL) { | ||
397 | + if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE | ||
398 | + && old_flags & TB_FLAG_DELAY_SLOT_COND) { | ||
399 | gen_delayed_conditional_jump(ctx); | ||
400 | return; | ||
401 | } | ||
402 | /* Otherwise this is probably an invalid gUSA region. | ||
403 | Drop the GUSA bits so the next TB doesn't see them. */ | ||
404 | - ctx->envflags &= ~GUSA_MASK; | ||
405 | + ctx->envflags &= ~TB_FLAG_GUSA_MASK; | ||
406 | |||
407 | tcg_gen_movi_i32(cpu_flags, ctx->envflags); | ||
408 | - if (old_flags & DELAY_SLOT_CONDITIONAL) { | ||
409 | + if (old_flags & TB_FLAG_DELAY_SLOT_COND) { | ||
410 | gen_delayed_conditional_jump(ctx); | ||
411 | } else { | ||
412 | gen_jump(ctx); | ||
413 | @@ -XXX,XX +XXX,XX @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env) | ||
414 | } | ||
415 | |||
416 | /* The entire region has been translated. */ | ||
417 | - ctx->envflags &= ~GUSA_MASK; | ||
418 | + ctx->envflags &= ~TB_FLAG_GUSA_MASK; | ||
419 | ctx->base.pc_next = pc_end; | ||
420 | ctx->base.num_insns += max_insns - 1; | ||
421 | return; | ||
422 | @@ -XXX,XX +XXX,XX @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env) | ||
423 | |||
424 | /* Restart with the EXCLUSIVE bit set, within a TB run via | ||
425 | cpu_exec_step_atomic holding the exclusive lock. */ | ||
426 | - ctx->envflags |= GUSA_EXCLUSIVE; | ||
427 | + ctx->envflags |= TB_FLAG_GUSA_EXCLUSIVE; | ||
428 | gen_save_cpu_state(ctx, false); | ||
429 | gen_helper_exclusive(cpu_env); | ||
430 | ctx->base.is_jmp = DISAS_NORETURN; | ||
431 | @@ -XXX,XX +XXX,XX @@ static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) | ||
432 | (tbflags & (1 << SR_RB))) * 0x10; | ||
433 | ctx->fbank = tbflags & FPSCR_FR ? 0x10 : 0; | ||
434 | |||
435 | - if (tbflags & GUSA_MASK) { | ||
436 | +#ifdef CONFIG_USER_ONLY | ||
437 | + if (tbflags & TB_FLAG_GUSA_MASK) { | ||
438 | + /* In gUSA exclusive region. */ | ||
439 | uint32_t pc = ctx->base.pc_next; | ||
440 | uint32_t pc_end = ctx->base.tb->cs_base; | ||
441 | - int backup = sextract32(ctx->tbflags, GUSA_SHIFT, 8); | ||
442 | + int backup = sextract32(ctx->tbflags, TB_FLAG_GUSA_SHIFT, 8); | ||
443 | int max_insns = (pc_end - pc) / 2; | ||
444 | |||
445 | if (pc != pc_end + backup || max_insns < 2) { | ||
446 | /* This is a malformed gUSA region. Don't do anything special, | ||
447 | since the interpreter is likely to get confused. */ | ||
448 | - ctx->envflags &= ~GUSA_MASK; | ||
449 | - } else if (tbflags & GUSA_EXCLUSIVE) { | ||
450 | + ctx->envflags &= ~TB_FLAG_GUSA_MASK; | ||
451 | + } else if (tbflags & TB_FLAG_GUSA_EXCLUSIVE) { | ||
452 | /* Regardless of single-stepping or the end of the page, | ||
453 | we must complete execution of the gUSA region while | ||
454 | holding the exclusive lock. */ | ||
455 | @@ -XXX,XX +XXX,XX @@ static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) | ||
456 | return; | ||
457 | } | ||
458 | } | ||
459 | +#endif | ||
460 | |||
461 | /* Since the ISA is fixed-width, we can bound by the number | ||
462 | of instructions remaining on the page. */ | ||
463 | @@ -XXX,XX +XXX,XX @@ static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) | ||
464 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | ||
465 | |||
466 | #ifdef CONFIG_USER_ONLY | ||
467 | - if (unlikely(ctx->envflags & GUSA_MASK) | ||
468 | - && !(ctx->envflags & GUSA_EXCLUSIVE)) { | ||
469 | + if (unlikely(ctx->envflags & TB_FLAG_GUSA_MASK) | ||
470 | + && !(ctx->envflags & TB_FLAG_GUSA_EXCLUSIVE)) { | ||
471 | /* We're in an gUSA region, and we have not already fallen | ||
472 | back on using an exclusive region. Attempt to parse the | ||
473 | region into a single supported atomic operation. Failure | ||
474 | @@ -XXX,XX +XXX,XX @@ static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | ||
475 | { | ||
476 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | ||
477 | |||
478 | - if (ctx->tbflags & GUSA_EXCLUSIVE) { | ||
479 | + if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) { | ||
480 | /* Ending the region of exclusivity. Clear the bits. */ | ||
481 | - ctx->envflags &= ~GUSA_MASK; | ||
482 | + ctx->envflags &= ~TB_FLAG_GUSA_MASK; | ||
483 | } | ||
484 | |||
485 | switch (ctx->base.is_jmp) { | ||
486 | -- | ||
487 | 2.34.1 | diff view generated by jsdifflib |