[PULL 00/29] target-arm queue
[PULL 00/14] target-arm queue
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target-arm queue: nothing big, just a collection of minor things.
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The following changes since commit 8f6330a807f2642dc2a3cdf33347aa28a4c00a87:
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-- PMM
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Merge tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu into staging (2024-03-06 16:56:20 +0000)
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The following changes since commit ae3aa5da96f4ccf0c2a28851449d92db9fcfad71:
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Merge remote-tracking branch 'remotes/berrange/tags/socket-next-pull-request' into staging (2020-05-21 16:47:28 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200521
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240308
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for you to fetch changes up to 17b5df7b65d0192c5d775b5e1581518580774c77:
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for you to fetch changes up to bbf6c6dbead82292a20951eb1204442a6b838de9:
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linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 (2020-05-21 20:00:19 +0100)
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target/arm: Move v7m-related code from cpu32.c into a separate file (2024-03-08 14:45:03 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* tests/acceptance: Add a test for the canon-a1100 machine
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* Implement FEAT_ECV
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* docs/system: Document some of the Arm development boards
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* STM32L4x5: Implement GPIO device
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* linux-user: make BKPT insn cause SIGTRAP, not be a syscall
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* Fix 32-bit SMOPA
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* target/arm: Remove unused GEN_NEON_INTEGER_OP macro
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* Refactor v7m related code from cpu32.c into its own file
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* fsl-imx25, fsl-imx31, fsl-imx6, fsl-imx6ul, fsl-imx7: implement watchdog
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* hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
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* hw/arm: Use qemu_log_mask() instead of hw_error() in various places
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* ARM: PL061: Introduce N_GPIOS
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* target/arm: Improve clear_vec_high() usage
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* target/arm: Allow user-mode code to write CPSR.E via MSR
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* linux-user/arm: Reset CPSR_E when entering a signal handler
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* linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32
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----------------------------------------------------------------
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----------------------------------------------------------------
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Amanieu d'Antras (1):
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Inès Varhol (3):
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linux-user/arm: Reset CPSR_E when entering a signal handler
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hw/gpio: Implement STM32L4x5 GPIO
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hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC
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tests/qtest: Add STM32L4x5 GPIO QTest testcase
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Geert Uytterhoeven (1):
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Peter Maydell (9):
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ARM: PL061: Introduce N_GPIOS
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target/arm: Move some register related defines to internals.h
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target/arm: Timer _EL02 registers UNDEF for E2H == 0
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target/arm: use FIELD macro for CNTHCTL bit definitions
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target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written
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target/arm: Implement new FEAT_ECV trap bits
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target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0
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target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
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target/arm: Enable FEAT_ECV for 'max' CPU
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hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
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Guenter Roeck (8):
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Richard Henderson (1):
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hw: Move i.MX watchdog driver to hw/watchdog
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target/arm: Fix 32-bit SMOPA
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hw/watchdog: Implement full i.MX watchdog support
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hw/arm/fsl-imx25: Wire up watchdog
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hw/arm/fsl-imx31: Wire up watchdog
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hw/arm/fsl-imx6: Connect watchdog interrupts
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hw/arm/fsl-imx6ul: Connect watchdog interrupts
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hw/arm/fsl-imx7: Instantiate various unimplemented devices
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hw/arm/fsl-imx7: Connect watchdog interrupts
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Peter Maydell (12):
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docs/system: Add 'Arm' to the Integrator/CP document title
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docs/system: Sort Arm board index into alphabetical order
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docs/system: Document Arm Versatile Express boards
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docs/system: Document the various MPS2 models
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docs/system: Document Musca boards
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linux-user/arm: BKPT should cause SIGTRAP, not be a syscall
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linux-user/arm: Remove bogus SVC 0xf0002 handling
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linux-user/arm: Handle invalid arm-specific syscalls correctly
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linux-user/arm: Fix identification of syscall numbers
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target/arm: Remove unused GEN_NEON_INTEGER_OP macro
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target/arm: Allow user-mode code to write CPSR.E via MSR
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linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32
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Philippe Mathieu-Daudé (4):
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hw/arm/integratorcp: Replace hw_error() by qemu_log_mask()
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hw/arm/pxa2xx: Replace hw_error() by qemu_log_mask()
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hw/char/xilinx_uartlite: Replace hw_error() by qemu_log_mask()
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hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask()
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Richard Henderson (2):
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target/arm: Use tcg_gen_gvec_mov for clear_vec_high
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target/arm: Use clear_vec_high more effectively
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Thomas Huth (1):
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Thomas Huth (1):
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tests/acceptance: Add a test for the canon-a1100 machine
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target/arm: Move v7m-related code from cpu32.c into a separate file
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docs/system/arm/integratorcp.rst | 4 +-
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MAINTAINERS | 1 +
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docs/system/arm/mps2.rst | 29 +++
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docs/system/arm/b-l475e-iot01a.rst | 2 +-
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docs/system/arm/musca.rst | 31 +++
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docs/system/arm/emulation.rst | 1 +
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docs/system/arm/vexpress.rst | 60 ++++++
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include/hw/arm/stm32l4x5_soc.h | 2 +
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docs/system/target-arm.rst | 20 +-
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include/hw/gpio/stm32l4x5_gpio.h | 71 +++++
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include/hw/arm/fsl-imx25.h | 5 +
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include/hw/misc/stm32l4x5_syscfg.h | 3 +-
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include/hw/arm/fsl-imx31.h | 4 +
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include/hw/rtc/sun4v-rtc.h | 2 +-
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include/hw/arm/fsl-imx6.h | 2 +-
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target/arm/cpu-features.h | 10 +
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include/hw/arm/fsl-imx6ul.h | 2 +-
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target/arm/cpu.h | 129 +--------
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include/hw/arm/fsl-imx7.h | 23 ++-
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target/arm/internals.h | 151 ++++++++++
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include/hw/misc/imx2_wdt.h | 33 ----
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hw/arm/stm32l4x5_soc.c | 71 ++++-
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include/hw/watchdog/wdt_imx2.h | 90 +++++++++
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hw/gpio/stm32l4x5_gpio.c | 477 ++++++++++++++++++++++++++++++++
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target/arm/cpu.h | 2 +-
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hw/misc/stm32l4x5_syscfg.c | 1 +
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hw/arm/fsl-imx25.c | 10 +
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hw/rtc/sun4v-rtc.c | 2 +-
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hw/arm/fsl-imx31.c | 6 +
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target/arm/helper.c | 189 ++++++++++++-
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hw/arm/fsl-imx6.c | 9 +
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target/arm/tcg/cpu-v7m.c | 290 +++++++++++++++++++
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hw/arm/fsl-imx6ul.c | 10 +
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target/arm/tcg/cpu32.c | 261 ------------------
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hw/arm/fsl-imx7.c | 35 ++++
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target/arm/tcg/cpu64.c | 1 +
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hw/arm/integratorcp.c | 23 ++-
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target/arm/tcg/sme_helper.c | 77 +++---
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hw/arm/pxa2xx_gpio.c | 7 +-
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tests/qtest/stm32l4x5_gpio-test.c | 551 +++++++++++++++++++++++++++++++++++++
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hw/char/xilinx_uartlite.c | 5 +-
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tests/tcg/aarch64/sme-smopa-1.c | 47 ++++
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hw/display/pxa2xx_lcd.c | 8 +-
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tests/tcg/aarch64/sme-smopa-2.c | 54 ++++
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hw/dma/pxa2xx_dma.c | 14 +-
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hw/arm/Kconfig | 3 +-
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hw/gpio/pl061.c | 12 +-
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hw/gpio/Kconfig | 3 +
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hw/misc/imx2_wdt.c | 90 ---------
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hw/gpio/meson.build | 1 +
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hw/timer/exynos4210_mct.c | 12 +-
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hw/gpio/trace-events | 6 +
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hw/watchdog/wdt_imx2.c | 303 +++++++++++++++++++++++++++++
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target/arm/meson.build | 3 +
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linux-user/arm/cpu_loop.c | 145 ++++++++------
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target/arm/tcg/meson.build | 3 +
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linux-user/arm/signal.c | 15 +-
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target/arm/trace-events | 1 +
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target/arm/translate-a64.c | 63 +++---
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tests/qtest/meson.build | 3 +-
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target/arm/translate.c | 23 ---
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tests/tcg/aarch64/Makefile.target | 2 +-
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MAINTAINERS | 6 +
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31 files changed, 1962 insertions(+), 456 deletions(-)
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hw/arm/Kconfig | 5 +
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create mode 100644 include/hw/gpio/stm32l4x5_gpio.h
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hw/misc/Makefile.objs | 1 -
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create mode 100644 hw/gpio/stm32l4x5_gpio.c
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hw/watchdog/Kconfig | 3 +
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create mode 100644 target/arm/tcg/cpu-v7m.c
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hw/watchdog/Makefile.objs | 1 +
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create mode 100644 tests/qtest/stm32l4x5_gpio-test.c
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tests/acceptance/machine_arm_canona1100.py | 35 ++++
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create mode 100644 tests/tcg/aarch64/sme-smopa-1.c
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37 files changed, 854 insertions(+), 292 deletions(-)
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create mode 100644 tests/tcg/aarch64/sme-smopa-2.c
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create mode 100644 docs/system/arm/mps2.rst
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create mode 100644 docs/system/arm/musca.rst
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create mode 100644 docs/system/arm/vexpress.rst
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delete mode 100644 include/hw/misc/imx2_wdt.h
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create mode 100644 include/hw/watchdog/wdt_imx2.h
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delete mode 100644 hw/misc/imx2_wdt.c
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create mode 100644 hw/watchdog/wdt_imx2.c
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create mode 100644 tests/acceptance/machine_arm_canona1100.py
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diff view generated by jsdifflib
[PULL 27/29] target/arm: Allow user-mode code to write CPSR.E via MSR
[PULL 01/14] target/arm: Move some register related defines to internals.h
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Using the MSR instruction to write to CPSR.E is deprecated, but it is
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cpu.h has a lot of #defines relating to CPU register fields.
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required to work from any mode including unprivileged code. We were
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Most of these aren't actually used outside target/arm code,
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incorrectly forbidding usermode code from writing it because
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so there's no point in cluttering up the cpu.h file with them.
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CPSR_USER did not include the CPSR_E bit.
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Move some easy ones to internals.h.
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We use CPSR_USER in only three places:
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* as the mask of what to allow userspace MSR to write to CPSR
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* when deciding what bits a linux-user signal-return should be
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able to write from the sigcontext structure
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* in target_user_copy_regs() when we set up the initial
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registers for the linux-user process
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In the first two cases not being able to update CPSR.E is a bug, and
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in the third case it doesn't matter because CPSR.E is always 0 there.
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So we can fix both bugs by adding CPSR_E to CPSR_USER.
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Because the cpsr_write() in restore_sigcontext() is now changing
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a CPSR bit which is cached in hflags, we need to add an
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arm_rebuild_hflags() call there; the callsite in
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target_user_copy_regs() was already rebuilding hflags for other
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reasons.
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(The recommended way to change CPSR.E is to use the 'SETEND'
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instruction, which we do correctly allow from usermode code.)
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20200518142801.20503-1-peter.maydell@linaro.org
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Message-id: 20240301183219.2424889-2-peter.maydell@linaro.org
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---
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---
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target/arm/cpu.h | 2 +-
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target/arm/cpu.h | 128 -----------------------------------------
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linux-user/arm/signal.c | 1 +
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target/arm/internals.h | 128 +++++++++++++++++++++++++++++++++++++++++
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2 files changed, 2 insertions(+), 1 deletion(-)
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2 files changed, 128 insertions(+), 128 deletions(-)
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diff --git a/target/arm/cpu.h b/target/arm/cpu.h
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diff --git a/target/arm/cpu.h b/target/arm/cpu.h
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index XXXXXXX..XXXXXXX 100644
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/cpu.h
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--- a/target/arm/cpu.h
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+++ b/target/arm/cpu.h
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+++ b/target/arm/cpu.h
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@@ -XXX,XX +XXX,XX @@ typedef struct ARMGenericTimer {
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uint64_t ctl; /* Timer Control register */
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} ARMGenericTimer;
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-#define VTCR_NSW (1u << 29)
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-#define VTCR_NSA (1u << 30)
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-#define VSTCR_SW VTCR_NSW
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-#define VSTCR_SA VTCR_NSA
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-
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/* Define a maximum sized vector register.
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* For 32-bit, this is a 128-bit NEON/AdvSIMD register.
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* For 64-bit, this is a 2048-bit SVE register.
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@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
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@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
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#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
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#define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */
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| CPSR_NZCV)
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#define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */
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/* Bits writable in user mode. */
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-#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
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-/* Bit definitions for CPACR (AArch32 only) */
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+#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
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-FIELD(CPACR, CP10, 20, 2)
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/* Execution state bits. MRS read as zero, MSR writes ignored. */
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-FIELD(CPACR, CP11, 22, 2)
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#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
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-FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */
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-FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */
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diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
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-FIELD(CPACR, ASEDIS, 31, 1)
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-
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-/* Bit definitions for CPACR_EL1 (AArch64 only) */
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-FIELD(CPACR_EL1, ZEN, 16, 2)
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-FIELD(CPACR_EL1, FPEN, 20, 2)
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-FIELD(CPACR_EL1, SMEN, 24, 2)
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-FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */
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-
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-/* Bit definitions for HCPTR (AArch32 only) */
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-FIELD(HCPTR, TCP10, 10, 1)
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-FIELD(HCPTR, TCP11, 11, 1)
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-FIELD(HCPTR, TASE, 15, 1)
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-FIELD(HCPTR, TTA, 20, 1)
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-FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */
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-FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */
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-
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-/* Bit definitions for CPTR_EL2 (AArch64 only) */
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-FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */
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-FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */
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-FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */
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-FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */
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-FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */
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-FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */
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-FIELD(CPTR_EL2, TTA, 28, 1)
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-FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */
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-FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */
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-
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-/* Bit definitions for CPTR_EL3 (AArch64 only) */
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-FIELD(CPTR_EL3, EZ, 8, 1)
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-FIELD(CPTR_EL3, TFP, 10, 1)
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-FIELD(CPTR_EL3, ESM, 12, 1)
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-FIELD(CPTR_EL3, TTA, 20, 1)
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-FIELD(CPTR_EL3, TAM, 30, 1)
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-FIELD(CPTR_EL3, TCPAC, 31, 1)
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-
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-#define MDCR_MTPME (1U << 28)
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-#define MDCR_TDCC (1U << 27)
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-#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
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-#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
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-#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
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-#define MDCR_EPMAD (1U << 21)
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-#define MDCR_EDAD (1U << 20)
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-#define MDCR_TTRF (1U << 19)
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-#define MDCR_STE (1U << 18) /* MDCR_EL3 */
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-#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
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-#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
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-#define MDCR_SDD (1U << 16)
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-#define MDCR_SPD (3U << 14)
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-#define MDCR_TDRA (1U << 11)
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-#define MDCR_TDOSA (1U << 10)
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-#define MDCR_TDA (1U << 9)
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-#define MDCR_TDE (1U << 8)
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-#define MDCR_HPME (1U << 7)
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-#define MDCR_TPM (1U << 6)
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-#define MDCR_TPMCR (1U << 5)
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-#define MDCR_HPMN (0x1fU)
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-
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-/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
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-#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
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- MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
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- MDCR_STE | MDCR_SPME | MDCR_SPD)
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-
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#define CPSR_M (0x1fU)
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#define CPSR_T (1U << 5)
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#define CPSR_F (1U << 6)
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@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TCPAC, 31, 1)
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#define XPSR_NZCV CPSR_NZCV
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#define XPSR_IT CPSR_IT
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-#define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
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-#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
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-#define TTBCR_PD0 (1U << 4)
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-#define TTBCR_PD1 (1U << 5)
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-#define TTBCR_EPD0 (1U << 7)
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-#define TTBCR_IRGN0 (3U << 8)
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-#define TTBCR_ORGN0 (3U << 10)
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-#define TTBCR_SH0 (3U << 12)
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-#define TTBCR_T1SZ (3U << 16)
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-#define TTBCR_A1 (1U << 22)
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-#define TTBCR_EPD1 (1U << 23)
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-#define TTBCR_IRGN1 (3U << 24)
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-#define TTBCR_ORGN1 (3U << 26)
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-#define TTBCR_SH1 (1U << 28)
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-#define TTBCR_EAE (1U << 31)
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-
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-FIELD(VTCR, T0SZ, 0, 6)
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-FIELD(VTCR, SL0, 6, 2)
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-FIELD(VTCR, IRGN0, 8, 2)
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-FIELD(VTCR, ORGN0, 10, 2)
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-FIELD(VTCR, SH0, 12, 2)
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-FIELD(VTCR, TG0, 14, 2)
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-FIELD(VTCR, PS, 16, 3)
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-FIELD(VTCR, VS, 19, 1)
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-FIELD(VTCR, HA, 21, 1)
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-FIELD(VTCR, HD, 22, 1)
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-FIELD(VTCR, HWU59, 25, 1)
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-FIELD(VTCR, HWU60, 26, 1)
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-FIELD(VTCR, HWU61, 27, 1)
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-FIELD(VTCR, HWU62, 28, 1)
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-FIELD(VTCR, NSW, 29, 1)
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-FIELD(VTCR, NSA, 30, 1)
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-FIELD(VTCR, DS, 32, 1)
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-FIELD(VTCR, SL2, 33, 1)
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-
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/* Bit definitions for ARMv8 SPSR (PSTATE) format.
145
* Only these are valid when in AArch64 mode; in
146
* AArch32 mode SPSRs are basically CPSR-format.
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@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
148
#define HCR_TWEDEN (1ULL << 59)
149
#define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
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151
-#define HCRX_ENAS0 (1ULL << 0)
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-#define HCRX_ENALS (1ULL << 1)
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-#define HCRX_ENASR (1ULL << 2)
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-#define HCRX_FNXS (1ULL << 3)
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-#define HCRX_FGTNXS (1ULL << 4)
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-#define HCRX_SMPME (1ULL << 5)
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-#define HCRX_TALLINT (1ULL << 6)
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-#define HCRX_VINMI (1ULL << 7)
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-#define HCRX_VFNMI (1ULL << 8)
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-#define HCRX_CMOW (1ULL << 9)
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-#define HCRX_MCE2 (1ULL << 10)
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-#define HCRX_MSCEN (1ULL << 11)
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-
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-#define HPFAR_NS (1ULL << 63)
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-
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#define SCR_NS (1ULL << 0)
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#define SCR_IRQ (1ULL << 1)
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#define SCR_FIQ (1ULL << 2)
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@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
170
#define SCR_GPF (1ULL << 48)
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#define SCR_NSE (1ULL << 62)
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173
-#define HSTR_TTEE (1 << 16)
174
-#define HSTR_TJDBX (1 << 17)
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-
176
-#define CNTHCTL_CNTVMASK (1 << 18)
177
-#define CNTHCTL_CNTPMASK (1 << 19)
178
-
179
/* Return the current FPSCR value. */
180
uint32_t vfp_get_fpscr(CPUARMState *env);
181
void vfp_set_fpscr(CPUARMState *env, uint32_t val);
182
diff --git a/target/arm/internals.h b/target/arm/internals.h
48
index XXXXXXX..XXXXXXX 100644
183
index XXXXXXX..XXXXXXX 100644
49
--- a/linux-user/arm/signal.c
184
--- a/target/arm/internals.h
50
+++ b/linux-user/arm/signal.c
185
+++ b/target/arm/internals.h
51
@@ -XXX,XX +XXX,XX @@ restore_sigcontext(CPUARMState *env, struct target_sigcontext *sc)
186
@@ -XXX,XX +XXX,XX @@ FIELD(DBGWCR, WT, 20, 1)
52
#ifdef TARGET_CONFIG_CPU_32
187
FIELD(DBGWCR, MASK, 24, 5)
53
__get_user(cpsr, &sc->arm_cpsr);
188
FIELD(DBGWCR, SSCE, 29, 1)
54
cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr);
189
55
+ arm_rebuild_hflags(env);
190
+#define VTCR_NSW (1u << 29)
56
#endif
191
+#define VTCR_NSA (1u << 30)
57
192
+#define VSTCR_SW VTCR_NSW
58
err |= !valid_user_regs(env);
193
+#define VSTCR_SA VTCR_NSA
194
+
195
+/* Bit definitions for CPACR (AArch32 only) */
196
+FIELD(CPACR, CP10, 20, 2)
197
+FIELD(CPACR, CP11, 22, 2)
198
+FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */
199
+FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */
200
+FIELD(CPACR, ASEDIS, 31, 1)
201
+
202
+/* Bit definitions for CPACR_EL1 (AArch64 only) */
203
+FIELD(CPACR_EL1, ZEN, 16, 2)
204
+FIELD(CPACR_EL1, FPEN, 20, 2)
205
+FIELD(CPACR_EL1, SMEN, 24, 2)
206
+FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */
207
+
208
+/* Bit definitions for HCPTR (AArch32 only) */
209
+FIELD(HCPTR, TCP10, 10, 1)
210
+FIELD(HCPTR, TCP11, 11, 1)
211
+FIELD(HCPTR, TASE, 15, 1)
212
+FIELD(HCPTR, TTA, 20, 1)
213
+FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */
214
+FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */
215
+
216
+/* Bit definitions for CPTR_EL2 (AArch64 only) */
217
+FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */
218
+FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */
219
+FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */
220
+FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */
221
+FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */
222
+FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */
223
+FIELD(CPTR_EL2, TTA, 28, 1)
224
+FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */
225
+FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */
226
+
227
+/* Bit definitions for CPTR_EL3 (AArch64 only) */
228
+FIELD(CPTR_EL3, EZ, 8, 1)
229
+FIELD(CPTR_EL3, TFP, 10, 1)
230
+FIELD(CPTR_EL3, ESM, 12, 1)
231
+FIELD(CPTR_EL3, TTA, 20, 1)
232
+FIELD(CPTR_EL3, TAM, 30, 1)
233
+FIELD(CPTR_EL3, TCPAC, 31, 1)
234
+
235
+#define MDCR_MTPME (1U << 28)
236
+#define MDCR_TDCC (1U << 27)
237
+#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
238
+#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
239
+#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
240
+#define MDCR_EPMAD (1U << 21)
241
+#define MDCR_EDAD (1U << 20)
242
+#define MDCR_TTRF (1U << 19)
243
+#define MDCR_STE (1U << 18) /* MDCR_EL3 */
244
+#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
245
+#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
246
+#define MDCR_SDD (1U << 16)
247
+#define MDCR_SPD (3U << 14)
248
+#define MDCR_TDRA (1U << 11)
249
+#define MDCR_TDOSA (1U << 10)
250
+#define MDCR_TDA (1U << 9)
251
+#define MDCR_TDE (1U << 8)
252
+#define MDCR_HPME (1U << 7)
253
+#define MDCR_TPM (1U << 6)
254
+#define MDCR_TPMCR (1U << 5)
255
+#define MDCR_HPMN (0x1fU)
256
+
257
+/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
258
+#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
259
+ MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
260
+ MDCR_STE | MDCR_SPME | MDCR_SPD)
261
+
262
+#define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
263
+#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
264
+#define TTBCR_PD0 (1U << 4)
265
+#define TTBCR_PD1 (1U << 5)
266
+#define TTBCR_EPD0 (1U << 7)
267
+#define TTBCR_IRGN0 (3U << 8)
268
+#define TTBCR_ORGN0 (3U << 10)
269
+#define TTBCR_SH0 (3U << 12)
270
+#define TTBCR_T1SZ (3U << 16)
271
+#define TTBCR_A1 (1U << 22)
272
+#define TTBCR_EPD1 (1U << 23)
273
+#define TTBCR_IRGN1 (3U << 24)
274
+#define TTBCR_ORGN1 (3U << 26)
275
+#define TTBCR_SH1 (1U << 28)
276
+#define TTBCR_EAE (1U << 31)
277
+
278
+FIELD(VTCR, T0SZ, 0, 6)
279
+FIELD(VTCR, SL0, 6, 2)
280
+FIELD(VTCR, IRGN0, 8, 2)
281
+FIELD(VTCR, ORGN0, 10, 2)
282
+FIELD(VTCR, SH0, 12, 2)
283
+FIELD(VTCR, TG0, 14, 2)
284
+FIELD(VTCR, PS, 16, 3)
285
+FIELD(VTCR, VS, 19, 1)
286
+FIELD(VTCR, HA, 21, 1)
287
+FIELD(VTCR, HD, 22, 1)
288
+FIELD(VTCR, HWU59, 25, 1)
289
+FIELD(VTCR, HWU60, 26, 1)
290
+FIELD(VTCR, HWU61, 27, 1)
291
+FIELD(VTCR, HWU62, 28, 1)
292
+FIELD(VTCR, NSW, 29, 1)
293
+FIELD(VTCR, NSA, 30, 1)
294
+FIELD(VTCR, DS, 32, 1)
295
+FIELD(VTCR, SL2, 33, 1)
296
+
297
+#define HCRX_ENAS0 (1ULL << 0)
298
+#define HCRX_ENALS (1ULL << 1)
299
+#define HCRX_ENASR (1ULL << 2)
300
+#define HCRX_FNXS (1ULL << 3)
301
+#define HCRX_FGTNXS (1ULL << 4)
302
+#define HCRX_SMPME (1ULL << 5)
303
+#define HCRX_TALLINT (1ULL << 6)
304
+#define HCRX_VINMI (1ULL << 7)
305
+#define HCRX_VFNMI (1ULL << 8)
306
+#define HCRX_CMOW (1ULL << 9)
307
+#define HCRX_MCE2 (1ULL << 10)
308
+#define HCRX_MSCEN (1ULL << 11)
309
+
310
+#define HPFAR_NS (1ULL << 63)
311
+
312
+#define HSTR_TTEE (1 << 16)
313
+#define HSTR_TJDBX (1 << 17)
314
+
315
+#define CNTHCTL_CNTVMASK (1 << 18)
316
+#define CNTHCTL_CNTPMASK (1 << 19)
317
+
318
/* We use a few fake FSR values for internal purposes in M profile.
319
* M profile cores don't have A/R format FSRs, but currently our
320
* get_phys_addr() code assumes A/R profile and reports failures via
59
--
321
--
60
2.20.1
322
2.34.1
61
323
62
324
diff view generated by jsdifflib
[PULL 28/29] linux-user/arm: Reset CPSR_E when entering a signal handler
[PULL 02/14] target/arm: Timer _EL02 registers UNDEF for E2H == 0
1
From: Amanieu d'Antras <amanieu@gmail.com>
1
The timer _EL02 registers should UNDEF for invalid accesses from EL2
2
or EL3 when HCR_EL2.E2H == 0, not take a cp access trap. We were
3
delivering the exception to EL2 with the wrong syndrome.
2
4
3
This fixes signal handlers running with the wrong endianness if the
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
interrupted code used SETEND to dynamically switch endianness.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20240301183219.2424889-3-peter.maydell@linaro.org
8
---
9
target/arm/helper.c | 2 +-
10
1 file changed, 1 insertion(+), 1 deletion(-)
5
11
6
Signed-off-by: Amanieu d'Antras <amanieu@gmail.com>
12
diff --git a/target/arm/helper.c b/target/arm/helper.c
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20200511131117.2486486-1-amanieu@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
linux-user/arm/signal.c | 8 +++++++-
12
1 file changed, 7 insertions(+), 1 deletion(-)
13
14
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/linux-user/arm/signal.c
14
--- a/target/arm/helper.c
17
+++ b/linux-user/arm/signal.c
15
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ setup_return(CPUARMState *env, struct target_sigaction *ka,
16
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
19
} else {
17
return CP_ACCESS_OK;
20
cpsr &= ~CPSR_T;
21
}
18
}
22
+ if (env->cp15.sctlr_el[1] & SCTLR_E0E) {
19
if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
23
+ cpsr |= CPSR_E;
20
- return CP_ACCESS_TRAP;
24
+ } else {
21
+ return CP_ACCESS_TRAP_UNCATEGORIZED;
25
+ cpsr &= ~CPSR_E;
22
}
26
+ }
23
return CP_ACCESS_OK;
27
28
if (ka->sa_flags & TARGET_SA_RESTORER) {
29
if (is_fdpic) {
30
@@ -XXX,XX +XXX,XX @@ setup_return(CPUARMState *env, struct target_sigaction *ka,
31
env->regs[13] = frame_addr;
32
env->regs[14] = retcode;
33
env->regs[15] = handler & (thumb ? ~1 : ~3);
34
- cpsr_write(env, cpsr, CPSR_IT | CPSR_T, CPSRWriteByInstr);
35
+ cpsr_write(env, cpsr, CPSR_IT | CPSR_T | CPSR_E, CPSRWriteByInstr);
36
+ arm_rebuild_hflags(env);
37
38
return 0;
39
}
24
}
40
--
25
--
41
2.20.1
26
2.34.1
42
43
diff view generated by jsdifflib
[PULL 23/29] hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask()
[PULL 03/14] target/arm: use FIELD macro for CNTHCTL bit definitions
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
We prefer the FIELD macro over ad-hoc #defines for register bits;
2
switch CNTHCTL to that style before we add any more bits.
2
3
3
hw_error() calls exit(). This a bit overkill when we can log
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
the accesses as unimplemented or guest error.
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20240301183219.2424889-4-peter.maydell@linaro.org
8
---
9
target/arm/internals.h | 27 +++++++++++++++++++++++++--
10
target/arm/helper.c | 9 ++++-----
11
2 files changed, 29 insertions(+), 7 deletions(-)
5
12
6
When fuzzing the devices, we don't want the whole process to
13
diff --git a/target/arm/internals.h b/target/arm/internals.h
7
exit. Replace some hw_error() calls by qemu_log_mask().
8
9
Per the datasheet "Exynos 4412 RISC Microprocessor Rev 1.00"
10
Chapter 25 "Multi Core Timer (MCT)" figure 1 and table 4,
11
the default value on the APB bus is 0.
12
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Message-id: 20200518140309.5220-5-f4bug@amsat.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/timer/exynos4210_mct.c | 12 +++++-------
19
1 file changed, 5 insertions(+), 7 deletions(-)
20
21
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
22
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/timer/exynos4210_mct.c
15
--- a/target/arm/internals.h
24
+++ b/hw/timer/exynos4210_mct.c
16
+++ b/target/arm/internals.h
25
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ FIELD(VTCR, SL2, 33, 1)
26
18
#define HSTR_TTEE (1 << 16)
27
#include "qemu/osdep.h"
19
#define HSTR_TJDBX (1 << 17)
28
#include "qemu/log.h"
20
29
-#include "hw/hw.h"
21
-#define CNTHCTL_CNTVMASK (1 << 18)
30
#include "hw/sysbus.h"
22
-#define CNTHCTL_CNTPMASK (1 << 19)
31
#include "migration/vmstate.h"
23
+/*
32
#include "qemu/timer.h"
24
+ * Depending on the value of HCR_EL2.E2H, bits 0 and 1
33
@@ -XXX,XX +XXX,XX @@
25
+ * have different bit definitions, and EL1PCTEN might be
34
#include "hw/ptimer.h"
26
+ * bit 0 or bit 10. We use _E2H1 and _E2H0 suffixes to
35
27
+ * disambiguate if necessary.
36
#include "hw/arm/exynos4210.h"
28
+ */
37
-#include "hw/hw.h"
29
+FIELD(CNTHCTL, EL0PCTEN_E2H1, 0, 1)
38
#include "hw/irq.h"
30
+FIELD(CNTHCTL, EL0VCTEN_E2H1, 1, 1)
39
31
+FIELD(CNTHCTL, EL1PCTEN_E2H0, 0, 1)
40
//#define DEBUG_MCT
32
+FIELD(CNTHCTL, EL1PCEN_E2H0, 1, 1)
41
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
33
+FIELD(CNTHCTL, EVNTEN, 2, 1)
42
int index;
34
+FIELD(CNTHCTL, EVNTDIR, 3, 1)
43
int shift;
35
+FIELD(CNTHCTL, EVNTI, 4, 4)
44
uint64_t count;
36
+FIELD(CNTHCTL, EL0VTEN, 8, 1)
45
- uint32_t value;
37
+FIELD(CNTHCTL, EL0PTEN, 9, 1)
46
+ uint32_t value = 0;
38
+FIELD(CNTHCTL, EL1PCTEN_E2H1, 10, 1)
47
int lt_i;
39
+FIELD(CNTHCTL, EL1PTEN, 11, 1)
48
40
+FIELD(CNTHCTL, ECV, 12, 1)
49
switch (offset) {
41
+FIELD(CNTHCTL, EL1TVT, 13, 1)
50
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
42
+FIELD(CNTHCTL, EL1TVCT, 14, 1)
51
break;
43
+FIELD(CNTHCTL, EL1NVPCT, 15, 1)
52
44
+FIELD(CNTHCTL, EL1NVVCT, 16, 1)
53
default:
45
+FIELD(CNTHCTL, EVNTIS, 17, 1)
54
- hw_error("exynos4210.mct: bad read offset "
46
+FIELD(CNTHCTL, CNTVMASK, 18, 1)
55
- TARGET_FMT_plx "\n", offset);
47
+FIELD(CNTHCTL, CNTPMASK, 19, 1)
56
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
48
57
+ __func__, offset);
49
/* We use a few fake FSR values for internal purposes in M profile.
58
break;
50
* M profile cores don't have A/R format FSRs, but currently our
51
diff --git a/target/arm/helper.c b/target/arm/helper.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/helper.c
54
+++ b/target/arm/helper.c
55
@@ -XXX,XX +XXX,XX @@ static void gt_update_irq(ARMCPU *cpu, int timeridx)
56
* It is RES0 in Secure and NonSecure state.
57
*/
58
if ((ss == ARMSS_Root || ss == ARMSS_Realm) &&
59
- ((timeridx == GTIMER_VIRT && (cnthctl & CNTHCTL_CNTVMASK)) ||
60
- (timeridx == GTIMER_PHYS && (cnthctl & CNTHCTL_CNTPMASK)))) {
61
+ ((timeridx == GTIMER_VIRT && (cnthctl & R_CNTHCTL_CNTVMASK_MASK)) ||
62
+ (timeridx == GTIMER_PHYS && (cnthctl & R_CNTHCTL_CNTPMASK_MASK)))) {
63
irqstate = 0;
59
}
64
}
60
return value;
65
61
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
66
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
62
break;
67
{
63
68
ARMCPU *cpu = env_archcpu(env);
64
default:
69
uint32_t oldval = env->cp15.cnthctl_el2;
65
- hw_error("exynos4210.mct: bad write offset "
70
-
66
- TARGET_FMT_plx "\n", offset);
71
raw_write(env, ri, value);
67
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
72
68
+ __func__, offset);
73
- if ((oldval ^ value) & CNTHCTL_CNTVMASK) {
69
break;
74
+ if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) {
75
gt_update_irq(cpu, GTIMER_VIRT);
76
- } else if ((oldval ^ value) & CNTHCTL_CNTPMASK) {
77
+ } else if ((oldval ^ value) & R_CNTHCTL_CNTPMASK_MASK) {
78
gt_update_irq(cpu, GTIMER_PHYS);
70
}
79
}
71
}
80
}
72
--
81
--
73
2.20.1
82
2.34.1
74
83
75
84
diff view generated by jsdifflib
[PULL 11/29] target/arm: Remove unused GEN_NEON_INTEGER_OP macro
[PULL 04/14] target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written
1
The GEN_NEON_INTEGER_OP macro is no longer used; remove it.
1
Don't allow the guest to write CNTHCTL_EL2 bits which don't exist.
2
This is not strictly architecturally required, but it is how we've
3
tended to implement registers more recently.
4
5
In particular, bits [19:18] are only present with FEAT_RME,
6
and bits [17:12] will only be present with FEAT_ECV.
2
7
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20240301183219.2424889-5-peter.maydell@linaro.org
5
---
11
---
6
target/arm/translate.c | 23 -----------------------
12
target/arm/helper.c | 18 ++++++++++++++++++
7
1 file changed, 23 deletions(-)
13
1 file changed, 18 insertions(+)
8
14
9
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
10
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
11
--- a/target/arm/translate.c
17
--- a/target/arm/helper.c
12
+++ b/target/arm/translate.c
18
+++ b/target/arm/helper.c
13
@@ -XXX,XX +XXX,XX @@ static inline void gen_neon_rsb(int size, TCGv_i32 t0, TCGv_i32 t1)
19
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
14
default: return 1; \
15
}} while (0)
16
17
-#define GEN_NEON_INTEGER_OP(name) do { \
18
- switch ((size << 1) | u) { \
19
- case 0: \
20
- gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
21
- break; \
22
- case 1: \
23
- gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
24
- break; \
25
- case 2: \
26
- gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
27
- break; \
28
- case 3: \
29
- gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
30
- break; \
31
- case 4: \
32
- gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
33
- break; \
34
- case 5: \
35
- gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
36
- break; \
37
- default: return 1; \
38
- }} while (0)
39
-
40
static TCGv_i32 neon_load_scratch(int scratch)
41
{
20
{
42
TCGv_i32 tmp = tcg_temp_new_i32();
21
ARMCPU *cpu = env_archcpu(env);
22
uint32_t oldval = env->cp15.cnthctl_el2;
23
+ uint32_t valid_mask =
24
+ R_CNTHCTL_EL0PCTEN_E2H1_MASK |
25
+ R_CNTHCTL_EL0VCTEN_E2H1_MASK |
26
+ R_CNTHCTL_EVNTEN_MASK |
27
+ R_CNTHCTL_EVNTDIR_MASK |
28
+ R_CNTHCTL_EVNTI_MASK |
29
+ R_CNTHCTL_EL0VTEN_MASK |
30
+ R_CNTHCTL_EL0PTEN_MASK |
31
+ R_CNTHCTL_EL1PCTEN_E2H1_MASK |
32
+ R_CNTHCTL_EL1PTEN_MASK;
33
+
34
+ if (cpu_isar_feature(aa64_rme, cpu)) {
35
+ valid_mask |= R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK;
36
+ }
37
+
38
+ /* Clear RES0 bits */
39
+ value &= valid_mask;
40
+
41
raw_write(env, ri, value);
42
43
if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) {
43
--
44
--
44
2.20.1
45
2.34.1
45
46
diff view generated by jsdifflib
[PULL 10/29] linux-user/arm: Fix identification of syscall numbers
[PULL 05/14] target/arm: Implement new FEAT_ECV trap bits
1
Our code to identify syscall numbers has some issues:
1
The functionality defined by ID_AA64MMFR0_EL1.ECV == 1 is:
2
* for Thumb mode, we never need the immediate value from the insn,
2
* four new trap bits for various counter and timer registers
3
but we always read it anyway
3
* the CNTHCTL_EL2.EVNTIS and CNTKCTL_EL1.EVNTIS bits which control
4
* bad immediate values in the svc insn should cause a SIGILL, but we
4
scaling of the event stream. This is a no-op for us, because we don't
5
were abort()ing instead (via "goto error")
5
implement the event stream (our WFE is a NOP): all we need to do is
6
allow CNTHCTL_EL2.ENVTIS to be read and written.
7
* extensions to PMSCR_EL1.PCT, PMSCR_EL2.PCT, TRFCR_EL1.TS and
8
TRFCR_EL2.TS: these are all no-ops for us, because we don't implement
9
FEAT_SPE or FEAT_TRF.
10
* new registers CNTPCTSS_EL0 and NCTVCTSS_EL0 which are
11
"self-sychronizing" views of the CNTPCT_EL0 and CNTVCT_EL0, meaning
12
that no barriers are needed around their accesses. For us these
13
are just the same as the normal views, because all our sysregs are
14
inherently self-sychronizing.
6
15
7
We can fix both these things by refactoring the code that identifies
16
In this commit we implement the trap handling and permit the new
8
the syscall number to more closely follow the kernel COMPAT_OABI code:
17
CNTHCTL_EL2 bits to be written.
9
* for Thumb it is always r7
10
* for Arm, if the immediate value is 0, then this is an EABI call
11
with the syscall number in r7
12
* otherwise, we XOR the immediate value with 0x900000
13
(ARM_SYSCALL_BASE for QEMU; __NR_OABI_SYSCALL_BASE in the kernel),
14
which converts valid syscall immediates into the desired value,
15
and puts all invalid immediates in the range 0x100000 or above
16
* then we can just let the existing "value too large, deliver
17
SIGILL" case handle invalid numbers, and drop the 'goto error'
18
18
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20200420212206.12776-5-peter.maydell@linaro.org
21
Message-id: 20240301183219.2424889-6-peter.maydell@linaro.org
22
---
22
---
23
linux-user/arm/cpu_loop.c | 143 ++++++++++++++++++++------------------
23
target/arm/cpu-features.h | 5 ++++
24
1 file changed, 77 insertions(+), 66 deletions(-)
24
target/arm/helper.c | 51 +++++++++++++++++++++++++++++++++++----
25
2 files changed, 51 insertions(+), 5 deletions(-)
25
26
26
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
27
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
27
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
28
--- a/linux-user/arm/cpu_loop.c
29
--- a/target/arm/cpu-features.h
29
+++ b/linux-user/arm/cpu_loop.c
30
+++ b/target/arm/cpu-features.h
30
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
31
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
31
env->eabi = 1;
32
return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
32
/* system call */
33
}
33
if (env->thumb) {
34
34
- /* FIXME - what to do if get_user() fails? */
35
+static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id)
35
- get_user_code_u16(insn, env->regs[15] - 2, env);
36
+{
36
- n = insn & 0xff;
37
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0;
37
+ /* Thumb is always EABI style with syscall number in r7 */
38
+}
38
+ n = env->regs[7];
39
} else {
40
+ /*
41
+ * Equivalent of kernel CONFIG_OABI_COMPAT: read the
42
+ * Arm SVC insn to extract the immediate, which is the
43
+ * syscall number in OABI.
44
+ */
45
/* FIXME - what to do if get_user() fails? */
46
get_user_code_u32(insn, env->regs[15] - 4, env);
47
n = insn & 0xffffff;
48
- }
49
-
50
- if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
51
- /* linux syscall */
52
- if (env->thumb || n == 0) {
53
+ if (n == 0) {
54
+ /* zero immediate: EABI, syscall number in r7 */
55
n = env->regs[7];
56
} else {
57
- n -= ARM_SYSCALL_BASE;
58
+ /*
59
+ * This XOR matches the kernel code: an immediate
60
+ * in the valid range (0x900000 .. 0x9fffff) is
61
+ * converted into the correct EABI-style syscall
62
+ * number; invalid immediates end up as values
63
+ * > 0xfffff and are handled below as out-of-range.
64
+ */
65
+ n ^= ARM_SYSCALL_BASE;
66
env->eabi = 0;
67
}
68
- if ( n > ARM_NR_BASE) {
69
- switch (n) {
70
- case ARM_NR_cacheflush:
71
- /* nop */
72
- break;
73
- case ARM_NR_set_tls:
74
- cpu_set_tls(env, env->regs[0]);
75
- env->regs[0] = 0;
76
- break;
77
- case ARM_NR_breakpoint:
78
- env->regs[15] -= env->thumb ? 2 : 4;
79
- goto excp_debug;
80
- case ARM_NR_get_tls:
81
- env->regs[0] = cpu_get_tls(env);
82
- break;
83
- default:
84
- if (n < 0xf0800) {
85
- /*
86
- * Syscalls 0xf0000..0xf07ff (or 0x9f0000..
87
- * 0x9f07ff in OABI numbering) are defined
88
- * to return -ENOSYS rather than raising
89
- * SIGILL. Note that we have already
90
- * removed the 0x900000 prefix.
91
- */
92
- qemu_log_mask(LOG_UNIMP,
93
- "qemu: Unsupported ARM syscall: 0x%x\n",
94
- n);
95
- env->regs[0] = -TARGET_ENOSYS;
96
+ }
97
+
39
+
98
+ if (n > ARM_NR_BASE) {
40
static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
99
+ switch (n) {
41
{
100
+ case ARM_NR_cacheflush:
42
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
101
+ /* nop */
43
diff --git a/target/arm/helper.c b/target/arm/helper.c
102
+ break;
44
index XXXXXXX..XXXXXXX 100644
103
+ case ARM_NR_set_tls:
45
--- a/target/arm/helper.c
104
+ cpu_set_tls(env, env->regs[0]);
46
+++ b/target/arm/helper.c
105
+ env->regs[0] = 0;
47
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
106
+ break;
48
: !extract32(env->cp15.cnthctl_el2, 0, 1))) {
107
+ case ARM_NR_breakpoint:
49
return CP_ACCESS_TRAP_EL2;
108
+ env->regs[15] -= env->thumb ? 2 : 4;
50
}
109
+ goto excp_debug;
51
+ if (has_el2 && timeridx == GTIMER_VIRT) {
110
+ case ARM_NR_get_tls:
52
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVCT)) {
111
+ env->regs[0] = cpu_get_tls(env);
53
+ return CP_ACCESS_TRAP_EL2;
112
+ break;
54
+ }
113
+ default:
55
+ }
114
+ if (n < 0xf0800) {
56
break;
115
+ /*
57
}
116
+ * Syscalls 0xf0000..0xf07ff (or 0x9f0000..
58
return CP_ACCESS_OK;
117
+ * 0x9f07ff in OABI numbering) are defined
59
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
118
+ * to return -ENOSYS rather than raising
119
+ * SIGILL. Note that we have already
120
+ * removed the 0x900000 prefix.
121
+ */
122
+ qemu_log_mask(LOG_UNIMP,
123
+ "qemu: Unsupported ARM syscall: 0x%x\n",
124
+ n);
125
+ env->regs[0] = -TARGET_ENOSYS;
126
+ } else {
127
+ /*
128
+ * Otherwise SIGILL. This includes any SWI with
129
+ * immediate not originally 0x9fxxxx, because
130
+ * of the earlier XOR.
131
+ */
132
+ info.si_signo = TARGET_SIGILL;
133
+ info.si_errno = 0;
134
+ info.si_code = TARGET_ILL_ILLTRP;
135
+ info._sifields._sigfault._addr = env->regs[15];
136
+ if (env->thumb) {
137
+ info._sifields._sigfault._addr -= 2;
138
} else {
139
- /* Otherwise SIGILL */
140
- info.si_signo = TARGET_SIGILL;
141
- info.si_errno = 0;
142
- info.si_code = TARGET_ILL_ILLTRP;
143
- info._sifields._sigfault._addr = env->regs[15];
144
- if (env->thumb) {
145
- info._sifields._sigfault._addr -= 2;
146
- } else {
147
- info._sifields._sigfault._addr -= 4;
148
- }
149
- queue_signal(env, info.si_signo,
150
- QEMU_SI_FAULT, &info);
151
+ info._sifields._sigfault._addr -= 4;
152
}
153
- break;
154
- }
155
- } else {
156
- ret = do_syscall(env,
157
- n,
158
- env->regs[0],
159
- env->regs[1],
160
- env->regs[2],
161
- env->regs[3],
162
- env->regs[4],
163
- env->regs[5],
164
- 0, 0);
165
- if (ret == -TARGET_ERESTARTSYS) {
166
- env->regs[15] -= env->thumb ? 2 : 4;
167
- } else if (ret != -TARGET_QEMU_ESIGRETURN) {
168
- env->regs[0] = ret;
169
+ queue_signal(env, info.si_signo,
170
+ QEMU_SI_FAULT, &info);
171
}
172
+ break;
173
}
174
} else {
175
- goto error;
176
+ ret = do_syscall(env,
177
+ n,
178
+ env->regs[0],
179
+ env->regs[1],
180
+ env->regs[2],
181
+ env->regs[3],
182
+ env->regs[4],
183
+ env->regs[5],
184
+ 0, 0);
185
+ if (ret == -TARGET_ERESTARTSYS) {
186
+ env->regs[15] -= env->thumb ? 2 : 4;
187
+ } else if (ret != -TARGET_QEMU_ESIGRETURN) {
188
+ env->regs[0] = ret;
189
+ }
190
}
60
}
191
}
61
}
192
break;
62
}
63
+ if (has_el2 && timeridx == GTIMER_VIRT) {
64
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVT)) {
65
+ return CP_ACCESS_TRAP_EL2;
66
+ }
67
+ }
68
break;
69
}
70
return CP_ACCESS_OK;
71
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
72
if (cpu_isar_feature(aa64_rme, cpu)) {
73
valid_mask |= R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK;
74
}
75
+ if (cpu_isar_feature(aa64_ecv_traps, cpu)) {
76
+ valid_mask |=
77
+ R_CNTHCTL_EL1TVT_MASK |
78
+ R_CNTHCTL_EL1TVCT_MASK |
79
+ R_CNTHCTL_EL1NVPCT_MASK |
80
+ R_CNTHCTL_EL1NVVCT_MASK |
81
+ R_CNTHCTL_EVNTIS_MASK;
82
+ }
83
84
/* Clear RES0 bits */
85
value &= valid_mask;
86
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
87
{
88
if (arm_current_el(env) == 1) {
89
/* This must be a FEAT_NV access */
90
- /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */
91
return CP_ACCESS_OK;
92
}
93
if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
94
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
95
return CP_ACCESS_OK;
96
}
97
98
+static CPAccessResult access_el1nvpct(CPUARMState *env, const ARMCPRegInfo *ri,
99
+ bool isread)
100
+{
101
+ if (arm_current_el(env) == 1) {
102
+ /* This must be a FEAT_NV access with NVx == 101 */
103
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVPCT)) {
104
+ return CP_ACCESS_TRAP_EL2;
105
+ }
106
+ }
107
+ return e2h_access(env, ri, isread);
108
+}
109
+
110
+static CPAccessResult access_el1nvvct(CPUARMState *env, const ARMCPRegInfo *ri,
111
+ bool isread)
112
+{
113
+ if (arm_current_el(env) == 1) {
114
+ /* This must be a FEAT_NV access with NVx == 101 */
115
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVVCT)) {
116
+ return CP_ACCESS_TRAP_EL2;
117
+ }
118
+ }
119
+ return e2h_access(env, ri, isread);
120
+}
121
+
122
/* Test if system register redirection is to occur in the current state. */
123
static bool redirect_for_e2h(CPUARMState *env)
124
{
125
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
126
{ .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64,
127
.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1,
128
.type = ARM_CP_IO | ARM_CP_ALIAS,
129
- .access = PL2_RW, .accessfn = e2h_access,
130
+ .access = PL2_RW, .accessfn = access_el1nvpct,
131
.nv2_redirect_offset = 0x180 | NV2_REDIR_NO_NV1,
132
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
133
.writefn = gt_phys_ctl_write, .raw_writefn = raw_write },
134
{ .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64,
135
.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1,
136
.type = ARM_CP_IO | ARM_CP_ALIAS,
137
- .access = PL2_RW, .accessfn = e2h_access,
138
+ .access = PL2_RW, .accessfn = access_el1nvvct,
139
.nv2_redirect_offset = 0x170 | NV2_REDIR_NO_NV1,
140
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
141
.writefn = gt_virt_ctl_write, .raw_writefn = raw_write },
142
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
143
.type = ARM_CP_IO | ARM_CP_ALIAS,
144
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
145
.nv2_redirect_offset = 0x178 | NV2_REDIR_NO_NV1,
146
- .access = PL2_RW, .accessfn = e2h_access,
147
+ .access = PL2_RW, .accessfn = access_el1nvpct,
148
.writefn = gt_phys_cval_write, .raw_writefn = raw_write },
149
{ .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64,
150
.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2,
151
.type = ARM_CP_IO | ARM_CP_ALIAS,
152
.nv2_redirect_offset = 0x168 | NV2_REDIR_NO_NV1,
153
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
154
- .access = PL2_RW, .accessfn = e2h_access,
155
+ .access = PL2_RW, .accessfn = access_el1nvvct,
156
.writefn = gt_virt_cval_write, .raw_writefn = raw_write },
157
#endif
158
};
193
--
159
--
194
2.20.1
160
2.34.1
195
196
diff view generated by jsdifflib
[PULL 29/29] linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32
[PULL 06/14] target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0
1
The Arm signal-handling code has some parts ifdeffed with a
1
For FEAT_ECV, new registers CNTPCTSS_EL0 and CNTVCTSS_EL0 are
2
TARGET_CONFIG_CPU_32, which is always defined. This is a leftover
2
defined, which are "self-synchronized" views of the physical and
3
from when this code's structure was based on the Linux kernel
3
virtual counts as seen in the CNTPCT_EL0 and CNTVCT_EL0 registers
4
signal handling code, where it was intended to support 26-bit
4
(meaning that no barriers are needed around accesses to them to
5
Arm CPUs. The kernel dropped its CONFIG_CPU_32 in kernel commit
5
ensure that reads of them do not occur speculatively and out-of-order
6
4da8b8208eded0ba21e3 in 2009.
6
with other instructions).
7
7
8
QEMU has never had 26-bit CPU support and is unlikely to ever
8
For QEMU, all our system registers are self-synchronized, so we can
9
add it; we certainly aren't going to support 26-bit Linux
9
simply copy the existing implementation of CNTPCT_EL0 and CNTVCT_EL0
10
binaries via linux-user mode. The ifdef is just unhelpful
10
to the new register encodings.
11
noise, so remove it entirely.
11
12
This means we now implement all the functionality required for
13
ID_AA64MMFR0_EL1.ECV == 0b0001.
12
14
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20200518143014.20689-1-peter.maydell@linaro.org
17
Message-id: 20240301183219.2424889-7-peter.maydell@linaro.org
16
---
18
---
17
linux-user/arm/signal.c | 6 ------
19
target/arm/helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++
18
1 file changed, 6 deletions(-)
20
1 file changed, 43 insertions(+)
19
21
20
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
22
diff --git a/target/arm/helper.c b/target/arm/helper.c
21
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
22
--- a/linux-user/arm/signal.c
24
--- a/target/arm/helper.c
23
+++ b/linux-user/arm/signal.c
25
+++ b/target/arm/helper.c
24
@@ -XXX,XX +XXX,XX @@ struct rt_sigframe_v2
26
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
25
abi_ulong retcode[4];
27
},
26
};
28
};
27
29
28
-#define TARGET_CONFIG_CPU_32 1
30
+/*
29
-
31
+ * FEAT_ECV adds extra views of CNTVCT_EL0 and CNTPCT_EL0 which
32
+ * are "self-synchronizing". For QEMU all sysregs are self-synchronizing,
33
+ * so our implementations here are identical to the normal registers.
34
+ */
35
+static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = {
36
+ { .name = "CNTVCTSS", .cp = 15, .crm = 14, .opc1 = 9,
37
+ .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
38
+ .accessfn = gt_vct_access,
39
+ .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
40
+ },
41
+ { .name = "CNTVCTSS_EL0", .state = ARM_CP_STATE_AA64,
42
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 6,
43
+ .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
44
+ .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
45
+ },
46
+ { .name = "CNTPCTSS", .cp = 15, .crm = 14, .opc1 = 8,
47
+ .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
48
+ .accessfn = gt_pct_access,
49
+ .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
50
+ },
51
+ { .name = "CNTPCTSS_EL0", .state = ARM_CP_STATE_AA64,
52
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 5,
53
+ .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
54
+ .accessfn = gt_pct_access, .readfn = gt_cnt_read,
55
+ },
56
+};
57
+
58
#else
59
30
/*
60
/*
31
* For ARM syscalls, we encode the syscall number into the instruction.
61
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
32
*/
62
},
33
@@ -XXX,XX +XXX,XX @@ setup_sigcontext(struct target_sigcontext *sc, /*struct _fpstate *fpstate,*/
63
};
34
__put_user(env->regs[13], &sc->arm_sp);
64
35
__put_user(env->regs[14], &sc->arm_lr);
65
+/*
36
__put_user(env->regs[15], &sc->arm_pc);
66
+ * CNTVCTSS_EL0 has the same trap conditions as CNTVCT_EL0, so it also
37
-#ifdef TARGET_CONFIG_CPU_32
67
+ * is exposed to userspace by Linux.
38
__put_user(cpsr_read(env), &sc->arm_cpsr);
68
+ */
39
-#endif
69
+static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = {
40
70
+ { .name = "CNTVCTSS_EL0", .state = ARM_CP_STATE_AA64,
41
__put_user(/* current->thread.trap_no */ 0, &sc->trap_no);
71
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 6,
42
__put_user(/* current->thread.error_code */ 0, &sc->error_code);
72
+ .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
43
@@ -XXX,XX +XXX,XX @@ restore_sigcontext(CPUARMState *env, struct target_sigcontext *sc)
73
+ .readfn = gt_virt_cnt_read,
44
__get_user(env->regs[13], &sc->arm_sp);
74
+ },
45
__get_user(env->regs[14], &sc->arm_lr);
75
+};
46
__get_user(env->regs[15], &sc->arm_pc);
76
+
47
-#ifdef TARGET_CONFIG_CPU_32
77
#endif
48
__get_user(cpsr, &sc->arm_cpsr);
78
49
cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr);
79
static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
50
arm_rebuild_hflags(env);
80
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
51
-#endif
81
if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
52
82
define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
53
err |= !valid_user_regs(env);
83
}
54
84
+ if (cpu_isar_feature(aa64_ecv_traps, cpu)) {
85
+ define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo);
86
+ }
87
if (arm_feature(env, ARM_FEATURE_VAPA)) {
88
ARMCPRegInfo vapa_cp_reginfo[] = {
89
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
55
--
90
--
56
2.20.1
91
2.34.1
57
58
diff view generated by jsdifflib
[PULL 14/29] hw/arm/fsl-imx25: Wire up watchdog
[PULL 07/14] target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
1
From: Guenter Roeck <linux@roeck-us.net>
1
When ID_AA64MMFR0_EL1.ECV is 0b0010, a new register CNTPOFF_EL2 is
2
implemented. This is similar to the existing CNTVOFF_EL2, except
3
that it controls a hypervisor-adjustable offset made to the physical
4
counter and timer.
2
5
3
With this commit, the watchdog on imx25-pdk is fully operational,
6
Implement the handling for this register, which includes control/trap
4
including pretimeout support.
7
bits in SCR_EL3 and CNTHCTL_EL2.
5
8
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20200517162135.110364-4-linux@roeck-us.net
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20240301183219.2424889-8-peter.maydell@linaro.org
10
---
12
---
11
include/hw/arm/fsl-imx25.h | 5 +++++
13
target/arm/cpu-features.h | 5 +++
12
hw/arm/fsl-imx25.c | 10 ++++++++++
14
target/arm/cpu.h | 1 +
13
hw/arm/Kconfig | 1 +
15
target/arm/helper.c | 68 +++++++++++++++++++++++++++++++++++++--
14
3 files changed, 16 insertions(+)
16
target/arm/trace-events | 1 +
17
4 files changed, 73 insertions(+), 2 deletions(-)
15
18
16
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
19
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
17
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/fsl-imx25.h
21
--- a/target/arm/cpu-features.h
19
+++ b/include/hw/arm/fsl-imx25.h
22
+++ b/target/arm/cpu-features.h
20
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id)
21
#include "hw/gpio/imx_gpio.h"
24
return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0;
22
#include "hw/sd/sdhci.h"
25
}
23
#include "hw/usb/chipidea.h"
26
24
+#include "hw/watchdog/wdt_imx2.h"
27
+static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id)
25
#include "exec/memory.h"
28
+{
26
#include "target/arm/cpu.h"
29
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 1;
27
30
+}
28
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
31
+
29
IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
32
static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
30
SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
33
{
31
ChipideaState usb[FSL_IMX25_NUM_USBS];
34
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
32
+ IMX2WdtState wdt;
35
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
33
MemoryRegion rom[2];
34
MemoryRegion iram;
35
MemoryRegion iram_alias;
36
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
37
#define FSL_IMX25_GPIO1_SIZE 0x4000
38
#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
39
#define FSL_IMX25_GPIO2_SIZE 0x4000
40
+#define FSL_IMX25_WDT_ADDR 0x53FDC000
41
+#define FSL_IMX25_WDT_SIZE 0x4000
42
#define FSL_IMX25_USB1_ADDR 0x53FF4000
43
#define FSL_IMX25_USB1_SIZE 0x0200
44
#define FSL_IMX25_USB2_ADDR 0x53FF4400
45
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
46
#define FSL_IMX25_ESDHC2_IRQ 8
47
#define FSL_IMX25_USB1_IRQ 37
48
#define FSL_IMX25_USB2_IRQ 35
49
+#define FSL_IMX25_WDT_IRQ 55
50
51
#endif /* FSL_IMX25_H */
52
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
53
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/arm/fsl-imx25.c
37
--- a/target/arm/cpu.h
55
+++ b/hw/arm/fsl-imx25.c
38
+++ b/target/arm/cpu.h
56
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
39
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
57
TYPE_CHIPIDEA);
40
uint64_t c14_cntkctl; /* Timer Control register */
41
uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */
42
uint64_t cntvoff_el2; /* Counter Virtual Offset register */
43
+ uint64_t cntpoff_el2; /* Counter Physical Offset register */
44
ARMGenericTimer c14_timer[NUM_GTIMERS];
45
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
46
uint32_t c15_ticonfig; /* TI925T configuration byte. */
47
diff --git a/target/arm/helper.c b/target/arm/helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/helper.c
50
+++ b/target/arm/helper.c
51
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
52
if (cpu_isar_feature(aa64_rme, cpu)) {
53
valid_mask |= SCR_NSE | SCR_GPF;
54
}
55
+ if (cpu_isar_feature(aa64_ecv, cpu)) {
56
+ valid_mask |= SCR_ECVEN;
57
+ }
58
} else {
59
valid_mask &= ~(SCR_RW | SCR_ST);
60
if (cpu_isar_feature(aa32_ras, cpu)) {
61
@@ -XXX,XX +XXX,XX @@ void gt_rme_post_el_change(ARMCPU *cpu, void *ignored)
62
gt_update_irq(cpu, GTIMER_PHYS);
63
}
64
65
+static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env)
66
+{
67
+ if ((env->cp15.scr_el3 & SCR_ECVEN) &&
68
+ FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) &&
69
+ arm_is_el2_enabled(env) &&
70
+ (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
71
+ return env->cp15.cntpoff_el2;
72
+ }
73
+ return 0;
74
+}
75
+
76
+static uint64_t gt_phys_cnt_offset(CPUARMState *env)
77
+{
78
+ if (arm_current_el(env) >= 2) {
79
+ return 0;
80
+ }
81
+ return gt_phys_raw_cnt_offset(env);
82
+}
83
+
84
static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
85
{
86
ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
87
@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
88
* reset timer to when ISTATUS next has to change
89
*/
90
uint64_t offset = timeridx == GTIMER_VIRT ?
91
- cpu->env.cp15.cntvoff_el2 : 0;
92
+ cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env);
93
uint64_t count = gt_get_countervalue(&cpu->env);
94
/* Note that this must be unsigned 64 bit arithmetic: */
95
int istatus = count - offset >= gt->cval;
96
@@ -XXX,XX +XXX,XX @@ static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
97
98
static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
99
{
100
- return gt_get_countervalue(env);
101
+ return gt_get_countervalue(env) - gt_phys_cnt_offset(env);
102
}
103
104
static uint64_t gt_virt_cnt_offset(CPUARMState *env)
105
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
106
case GTIMER_HYPVIRT:
107
offset = gt_virt_cnt_offset(env);
108
break;
109
+ case GTIMER_PHYS:
110
+ offset = gt_phys_cnt_offset(env);
111
+ break;
58
}
112
}
59
113
60
+ sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), TYPE_IMX2_WDT);
114
return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
61
}
115
@@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
62
116
case GTIMER_HYPVIRT:
63
static void fsl_imx25_realize(DeviceState *dev, Error **errp)
117
offset = gt_virt_cnt_offset(env);
64
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
118
break;
65
usb_table[i].irq));
119
+ case GTIMER_PHYS:
120
+ offset = gt_phys_cnt_offset(env);
121
+ break;
66
}
122
}
67
123
68
+ /* Watchdog */
124
trace_arm_gt_tval_write(timeridx, value);
69
+ object_property_set_bool(OBJECT(&s->wdt), true, "pretimeout-support",
125
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
70
+ &error_abort);
126
R_CNTHCTL_EL1NVVCT_MASK |
71
+ object_property_set_bool(OBJECT(&s->wdt), true, "realized", &error_abort);
127
R_CNTHCTL_EVNTIS_MASK;
72
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX25_WDT_ADDR);
128
}
73
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt), 0,
129
+ if (cpu_isar_feature(aa64_ecv, cpu)) {
74
+ qdev_get_gpio_in(DEVICE(&s->avic),
130
+ valid_mask |= R_CNTHCTL_ECV_MASK;
75
+ FSL_IMX25_WDT_IRQ));
131
+ }
132
133
/* Clear RES0 bits */
134
value &= valid_mask;
135
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = {
136
},
137
};
138
139
+static CPAccessResult gt_cntpoff_access(CPUARMState *env,
140
+ const ARMCPRegInfo *ri,
141
+ bool isread)
142
+{
143
+ if (arm_current_el(env) == 2 && !(env->cp15.scr_el3 & SCR_ECVEN)) {
144
+ return CP_ACCESS_TRAP_EL3;
145
+ }
146
+ return CP_ACCESS_OK;
147
+}
76
+
148
+
77
/* initialize 2 x 16 KB ROM */
149
+static void gt_cntpoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
78
memory_region_init_rom(&s->rom[0], OBJECT(dev), "imx25.rom0",
150
+ uint64_t value)
79
FSL_IMX25_ROM0_SIZE, &err);
151
+{
80
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
152
+ ARMCPU *cpu = env_archcpu(env);
153
+
154
+ trace_arm_gt_cntpoff_write(value);
155
+ raw_write(env, ri, value);
156
+ gt_recalc_timer(cpu, GTIMER_PHYS);
157
+}
158
+
159
+static const ARMCPRegInfo gen_timer_cntpoff_reginfo = {
160
+ .name = "CNTPOFF_EL2", .state = ARM_CP_STATE_AA64,
161
+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 6,
162
+ .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
163
+ .accessfn = gt_cntpoff_access, .writefn = gt_cntpoff_write,
164
+ .nv2_redirect_offset = 0x1a8,
165
+ .fieldoffset = offsetof(CPUARMState, cp15.cntpoff_el2),
166
+};
167
#else
168
169
/*
170
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
171
if (cpu_isar_feature(aa64_ecv_traps, cpu)) {
172
define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo);
173
}
174
+#ifndef CONFIG_USER_ONLY
175
+ if (cpu_isar_feature(aa64_ecv, cpu)) {
176
+ define_one_arm_cp_reg(cpu, &gen_timer_cntpoff_reginfo);
177
+ }
178
+#endif
179
if (arm_feature(env, ARM_FEATURE_VAPA)) {
180
ARMCPRegInfo vapa_cp_reginfo[] = {
181
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
182
diff --git a/target/arm/trace-events b/target/arm/trace-events
81
index XXXXXXX..XXXXXXX 100644
183
index XXXXXXX..XXXXXXX 100644
82
--- a/hw/arm/Kconfig
184
--- a/target/arm/trace-events
83
+++ b/hw/arm/Kconfig
185
+++ b/target/arm/trace-events
84
@@ -XXX,XX +XXX,XX @@ config FSL_IMX25
186
@@ -XXX,XX +XXX,XX @@ arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d value 0x%"
85
select IMX
187
arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value 0x%" PRIx64
86
select IMX_FEC
188
arm_gt_imask_toggle(int timer) "gt_ctl_write: timer %d IMASK toggle"
87
select IMX_I2C
189
arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value 0x%" PRIx64
88
+ select WDT_IMX2
190
+arm_gt_cntpoff_write(uint64_t value) "gt_cntpoff_write: value 0x%" PRIx64
89
select DS1338
191
arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d"
90
192
91
config FSL_IMX31
193
# kvm.c
92
--
194
--
93
2.20.1
195
2.34.1
94
95
diff view generated by jsdifflib
[PULL 08/29] linux-user/arm: Remove bogus SVC 0xf0002 handling
[PULL 08/14] target/arm: Enable FEAT_ECV for 'max' CPU
1
We incorrectly treat SVC 0xf0002 as a cacheflush request (which is a
1
Enable all FEAT_ECV features on the 'max' CPU.
2
NOP for QEMU). This is the wrong syscall number, because in the
3
svc-immediate OABI syscall numbers are all offset by the
4
ARM_SYSCALL_BASE value and so the correct insn is SVC 0x9f0002.
5
(This is handled further down in the code with the other Arm-specific
6
syscalls like NR_breakpoint.)
7
8
When this code was initially added in commit 6f1f31c069b20611 in
9
2004, ARM_NR_cacheflush was defined as (ARM_SYSCALL_BASE + 0xf0000 + 2)
10
so the value in the comparison took account of the extra 0x900000
11
offset. In commit fbb4a2e371f2fa7 in 2008, the ARM_SYSCALL_BASE
12
was removed from the definition of ARM_NR_cacheflush and handling
13
for this group of syscalls was added below the point where we subtract
14
ARM_SYSCALL_BASE from the SVC immediate value. However that commit
15
forgot to remove the now-obsolete earlier handling code.
16
17
Remove the spurious ARM_NR_cacheflush condition.
18
2
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
21
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22
Message-id: 20200420212206.12776-3-peter.maydell@linaro.org
6
Message-id: 20240301183219.2424889-9-peter.maydell@linaro.org
23
---
7
---
24
linux-user/arm/cpu_loop.c | 4 +---
8
docs/system/arm/emulation.rst | 1 +
25
1 file changed, 1 insertion(+), 3 deletions(-)
9
target/arm/tcg/cpu64.c | 1 +
10
2 files changed, 2 insertions(+)
26
11
27
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
12
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
28
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
29
--- a/linux-user/arm/cpu_loop.c
14
--- a/docs/system/arm/emulation.rst
30
+++ b/linux-user/arm/cpu_loop.c
15
+++ b/docs/system/arm/emulation.rst
31
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
16
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
32
n = insn & 0xffffff;
17
- FEAT_DotProd (Advanced SIMD dot product instructions)
33
}
18
- FEAT_DoubleFault (Double Fault Extension)
34
19
- FEAT_E0PD (Preventing EL0 access to halves of address maps)
35
- if (n == ARM_NR_cacheflush) {
20
+- FEAT_ECV (Enhanced Counter Virtualization)
36
- /* nop */
21
- FEAT_EPAC (Enhanced pointer authentication)
37
- } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
22
- FEAT_ETS (Enhanced Translation Synchronization)
38
+ if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
23
- FEAT_EVT (Enhanced Virtualization Traps)
39
/* linux syscall */
24
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
40
if (env->thumb || n == 0) {
25
index XXXXXXX..XXXXXXX 100644
41
n = env->regs[7];
26
--- a/target/arm/tcg/cpu64.c
27
+++ b/target/arm/tcg/cpu64.c
28
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
29
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
30
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
31
t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */
32
+ t = FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */
33
cpu->isar.id_aa64mmfr0 = t;
34
35
t = cpu->isar.id_aa64mmfr1;
42
--
36
--
43
2.20.1
37
2.34.1
44
38
45
39
diff view generated by jsdifflib
[PULL 13/29] hw/watchdog: Implement full i.MX watchdog support
[PULL 09/14] hw/gpio: Implement STM32L4x5 GPIO
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
Implement full support for the watchdog in i.MX systems.
3
Features supported :
4
Pretimeout support is optional because the watchdog hardware
4
- the 8 STM32L4x5 GPIOs are initialized with their reset values
5
on i.MX31 does not support pretimeouts.
5
(except IDR, see below)
6
- input mode : setting a pin in input mode "externally" (using input
7
irqs) results in an out irq (transmitted to SYSCFG)
8
- output mode : setting a bit in ODR sets the corresponding out irq
9
(if this line is configured in output mode)
10
- pull-up, pull-down
11
- push-pull, open-drain
6
12
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
13
Difference with the real GPIOs :
8
Message-id: 20200517162135.110364-3-linux@roeck-us.net
14
- Alternate Function and Analog mode aren't implemented :
15
pins in AF/Analog behave like pins in input mode
16
- floating pins stay at their last value
17
- register IDR reset values differ from the real one :
18
values are coherent with the other registers reset values
19
and the fact that AF/Analog modes aren't implemented
20
- setting I/O output speed isn't supported
21
- locking port bits isn't supported
22
- ADC function isn't supported
23
- GPIOH has 16 pins instead of 2 pins
24
- writing to registers LCKR, AFRL, AFRH and ASCR is ineffective
25
26
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
27
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
29
Acked-by: Alistair Francis <alistair.francis@wdc.com>
30
Message-id: 20240305210444.310665-2-ines.varhol@telecom-paris.fr
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
---
32
---
12
include/hw/watchdog/wdt_imx2.h | 61 ++++++++-
33
MAINTAINERS | 1 +
13
hw/watchdog/wdt_imx2.c | 239 +++++++++++++++++++++++++++++++--
34
docs/system/arm/b-l475e-iot01a.rst | 2 +-
14
2 files changed, 285 insertions(+), 15 deletions(-)
35
include/hw/gpio/stm32l4x5_gpio.h | 70 +++++
36
hw/gpio/stm32l4x5_gpio.c | 477 +++++++++++++++++++++++++++++
37
hw/gpio/Kconfig | 3 +
38
hw/gpio/meson.build | 1 +
39
hw/gpio/trace-events | 6 +
40
7 files changed, 559 insertions(+), 1 deletion(-)
41
create mode 100644 include/hw/gpio/stm32l4x5_gpio.h
42
create mode 100644 hw/gpio/stm32l4x5_gpio.c
15
43
16
diff --git a/include/hw/watchdog/wdt_imx2.h b/include/hw/watchdog/wdt_imx2.h
44
diff --git a/MAINTAINERS b/MAINTAINERS
17
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/watchdog/wdt_imx2.h
46
--- a/MAINTAINERS
19
+++ b/include/hw/watchdog/wdt_imx2.h
47
+++ b/MAINTAINERS
48
@@ -XXX,XX +XXX,XX @@ F: hw/arm/stm32l4x5_soc.c
49
F: hw/misc/stm32l4x5_exti.c
50
F: hw/misc/stm32l4x5_syscfg.c
51
F: hw/misc/stm32l4x5_rcc.c
52
+F: hw/gpio/stm32l4x5_gpio.c
53
F: include/hw/*/stm32l4x5_*.h
54
55
B-L475E-IOT01A IoT Node
56
diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst
57
index XXXXXXX..XXXXXXX 100644
58
--- a/docs/system/arm/b-l475e-iot01a.rst
59
+++ b/docs/system/arm/b-l475e-iot01a.rst
60
@@ -XXX,XX +XXX,XX @@ Currently B-L475E-IOT01A machine's only supports the following devices:
61
- STM32L4x5 EXTI (Extended interrupts and events controller)
62
- STM32L4x5 SYSCFG (System configuration controller)
63
- STM32L4x5 RCC (Reset and clock control)
64
+- STM32L4x5 GPIOs (General-purpose I/Os)
65
66
Missing devices
67
"""""""""""""""
68
@@ -XXX,XX +XXX,XX @@ Missing devices
69
The B-L475E-IOT01A does *not* support the following devices:
70
71
- Serial ports (UART)
72
-- General-purpose I/Os (GPIO)
73
- Analog to Digital Converter (ADC)
74
- SPI controller
75
- Timer controller (TIMER)
76
diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_gpio.h
77
new file mode 100644
78
index XXXXXXX..XXXXXXX
79
--- /dev/null
80
+++ b/include/hw/gpio/stm32l4x5_gpio.h
20
@@ -XXX,XX +XXX,XX @@
81
@@ -XXX,XX +XXX,XX @@
21
#ifndef IMX2_WDT_H
82
+/*
22
#define IMX2_WDT_H
83
+ * STM32L4x5 GPIO (General Purpose Input/Ouput)
23
84
+ *
24
+#include "qemu/bitops.h"
85
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
25
#include "hw/sysbus.h"
86
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
87
+ *
88
+ * SPDX-License-Identifier: GPL-2.0-or-later
89
+ *
90
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
91
+ * See the COPYING file in the top-level directory.
92
+ */
93
+
94
+/*
95
+ * The reference used is the STMicroElectronics RM0351 Reference manual
96
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
97
+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
98
+ */
99
+
100
+#ifndef HW_STM32L4X5_GPIO_H
101
+#define HW_STM32L4X5_GPIO_H
102
+
103
+#include "hw/sysbus.h"
104
+#include "qom/object.h"
105
+
106
+#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"
107
+OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO)
108
+
109
+#define GPIO_NUM_PINS 16
110
+
111
+struct Stm32l4x5GpioState {
112
+ SysBusDevice parent_obj;
113
+
114
+ MemoryRegion mmio;
115
+
116
+ /* GPIO registers */
117
+ uint32_t moder;
118
+ uint32_t otyper;
119
+ uint32_t ospeedr;
120
+ uint32_t pupdr;
121
+ uint32_t idr;
122
+ uint32_t odr;
123
+ uint32_t lckr;
124
+ uint32_t afrl;
125
+ uint32_t afrh;
126
+ uint32_t ascr;
127
+
128
+ /* GPIO registers reset values */
129
+ uint32_t moder_reset;
130
+ uint32_t ospeedr_reset;
131
+ uint32_t pupdr_reset;
132
+
133
+ /*
134
+ * External driving of pins.
135
+ * The pins can be set externally through the device
136
+ * anonymous input GPIOs lines under certain conditions.
137
+ * The pin must not be in push-pull output mode,
138
+ * and can't be set high in open-drain mode.
139
+ * Pins driven externally and configured to
140
+ * output mode will in general be "disconnected"
141
+ * (see `get_gpio_pinmask_to_disconnect()`)
142
+ */
143
+ uint16_t disconnected_pins;
144
+ uint16_t pins_connected_high;
145
+
146
+ char *name;
147
+ Clock *clk;
148
+ qemu_irq pin[GPIO_NUM_PINS];
149
+};
150
+
151
+#endif
152
diff --git a/hw/gpio/stm32l4x5_gpio.c b/hw/gpio/stm32l4x5_gpio.c
153
new file mode 100644
154
index XXXXXXX..XXXXXXX
155
--- /dev/null
156
+++ b/hw/gpio/stm32l4x5_gpio.c
157
@@ -XXX,XX +XXX,XX @@
158
+/*
159
+ * STM32L4x5 GPIO (General Purpose Input/Ouput)
160
+ *
161
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
162
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
163
+ *
164
+ * SPDX-License-Identifier: GPL-2.0-or-later
165
+ *
166
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
167
+ * See the COPYING file in the top-level directory.
168
+ */
169
+
170
+/*
171
+ * The reference used is the STMicroElectronics RM0351 Reference manual
172
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
173
+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
174
+ */
175
+
176
+#include "qemu/osdep.h"
177
+#include "qemu/log.h"
178
+#include "hw/gpio/stm32l4x5_gpio.h"
26
+#include "hw/irq.h"
179
+#include "hw/irq.h"
27
+#include "hw/ptimer.h"
180
+#include "hw/qdev-clock.h"
28
181
+#include "hw/qdev-properties.h"
29
#define TYPE_IMX2_WDT "imx2.wdt"
182
+#include "qapi/visitor.h"
30
#define IMX2_WDT(obj) OBJECT_CHECK(IMX2WdtState, (obj), TYPE_IMX2_WDT)
183
+#include "qapi/error.h"
31
32
enum IMX2WdtRegisters {
33
- IMX2_WDT_WCR = 0x0000,
34
- IMX2_WDT_REG_NUM = 0x0008 / sizeof(uint16_t) + 1,
35
+ IMX2_WDT_WCR = 0x0000, /* Control Register */
36
+ IMX2_WDT_WSR = 0x0002, /* Service Register */
37
+ IMX2_WDT_WRSR = 0x0004, /* Reset Status Register */
38
+ IMX2_WDT_WICR = 0x0006, /* Interrupt Control Register */
39
+ IMX2_WDT_WMCR = 0x0008, /* Misc Register */
40
};
41
42
+#define IMX2_WDT_MMIO_SIZE 0x000a
43
+
44
+/* Control Register definitions */
45
+#define IMX2_WDT_WCR_WT (0xFF << 8) /* Watchdog Timeout Field */
46
+#define IMX2_WDT_WCR_WDW BIT(7) /* WDOG Disable for Wait */
47
+#define IMX2_WDT_WCR_WDA BIT(5) /* WDOG Assertion */
48
+#define IMX2_WDT_WCR_SRS BIT(4) /* Software Reset Signal */
49
+#define IMX2_WDT_WCR_WDT BIT(3) /* WDOG Timeout Assertion */
50
+#define IMX2_WDT_WCR_WDE BIT(2) /* Watchdog Enable */
51
+#define IMX2_WDT_WCR_WDBG BIT(1) /* Watchdog Debug Enable */
52
+#define IMX2_WDT_WCR_WDZST BIT(0) /* Watchdog Timer Suspend */
53
+
54
+#define IMX2_WDT_WCR_LOCK_MASK (IMX2_WDT_WCR_WDZST | IMX2_WDT_WCR_WDBG \
55
+ | IMX2_WDT_WCR_WDW)
56
+
57
+/* Service Register definitions */
58
+#define IMX2_WDT_SEQ1 0x5555 /* service sequence 1 */
59
+#define IMX2_WDT_SEQ2 0xAAAA /* service sequence 2 */
60
+
61
+/* Reset Status Register definitions */
62
+#define IMX2_WDT_WRSR_TOUT BIT(1) /* Reset due to Timeout */
63
+#define IMX2_WDT_WRSR_SFTW BIT(0) /* Reset due to software reset */
64
+
65
+/* Interrupt Control Register definitions */
66
+#define IMX2_WDT_WICR_WIE BIT(15) /* Interrupt Enable */
67
+#define IMX2_WDT_WICR_WTIS BIT(14) /* Interrupt Status */
68
+#define IMX2_WDT_WICR_WICT 0xff /* Interrupt Timeout */
69
+#define IMX2_WDT_WICR_WICT_DEF 0x04 /* Default interrupt timeout (2s) */
70
+
71
+#define IMX2_WDT_WICR_LOCK_MASK (IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT)
72
+
73
+/* Misc Control Register definitions */
74
+#define IMX2_WDT_WMCR_PDE BIT(0) /* Power-Down Enable */
75
76
typedef struct IMX2WdtState {
77
/* <private> */
78
SysBusDevice parent_obj;
79
80
+ /*< public >*/
81
MemoryRegion mmio;
82
+ qemu_irq irq;
83
+
84
+ struct ptimer_state *timer;
85
+ struct ptimer_state *itimer;
86
+
87
+ bool pretimeout_support;
88
+ bool wicr_locked;
89
+
90
+ uint16_t wcr;
91
+ uint16_t wsr;
92
+ uint16_t wrsr;
93
+ uint16_t wicr;
94
+ uint16_t wmcr;
95
+
96
+ bool wcr_locked; /* affects WDZST, WDBG, and WDW */
97
+ bool wcr_wde_locked; /* affects WDE */
98
+ bool wcr_wdt_locked; /* affects WDT (never cleared) */
99
} IMX2WdtState;
100
101
#endif /* IMX2_WDT_H */
102
diff --git a/hw/watchdog/wdt_imx2.c b/hw/watchdog/wdt_imx2.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/hw/watchdog/wdt_imx2.c
105
+++ b/hw/watchdog/wdt_imx2.c
106
@@ -XXX,XX +XXX,XX @@
107
#include "qemu/bitops.h"
108
#include "qemu/module.h"
109
#include "sysemu/watchdog.h"
110
+#include "migration/vmstate.h"
184
+#include "migration/vmstate.h"
111
+#include "hw/qdev-properties.h"
185
+#include "trace.h"
112
186
+
113
#include "hw/watchdog/wdt_imx2.h"
187
+#define GPIO_MODER 0x00
114
188
+#define GPIO_OTYPER 0x04
115
-#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
189
+#define GPIO_OSPEEDR 0x08
116
-#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
190
+#define GPIO_PUPDR 0x0C
117
-
191
+#define GPIO_IDR 0x10
118
-static uint64_t imx2_wdt_read(void *opaque, hwaddr addr,
192
+#define GPIO_ODR 0x14
119
- unsigned int size)
193
+#define GPIO_BSRR 0x18
120
+static void imx2_wdt_interrupt(void *opaque)
194
+#define GPIO_LCKR 0x1C
121
{
195
+#define GPIO_AFRL 0x20
122
+ IMX2WdtState *s = IMX2_WDT(opaque);
196
+#define GPIO_AFRH 0x24
123
+
197
+#define GPIO_BRR 0x28
124
+ s->wicr |= IMX2_WDT_WICR_WTIS;
198
+#define GPIO_ASCR 0x2C
125
+ qemu_set_irq(s->irq, 1);
199
+
126
+}
200
+/* 0b11111111_11111111_00000000_00000000 */
127
+
201
+#define RESERVED_BITS_MASK 0xFFFF0000
128
+static void imx2_wdt_expired(void *opaque)
202
+
129
+{
203
+static void update_gpio_idr(Stm32l4x5GpioState *s);
130
+ IMX2WdtState *s = IMX2_WDT(opaque);
204
+
131
+
205
+static bool is_pull_up(Stm32l4x5GpioState *s, unsigned pin)
132
+ s->wrsr = IMX2_WDT_WRSR_TOUT;
206
+{
133
+
207
+ return extract32(s->pupdr, 2 * pin, 2) == 1;
134
+ /* Perform watchdog action if watchdog is enabled */
208
+}
135
+ if (s->wcr & IMX2_WDT_WCR_WDE) {
209
+
136
+ s->wrsr = IMX2_WDT_WRSR_TOUT;
210
+static bool is_pull_down(Stm32l4x5GpioState *s, unsigned pin)
137
+ watchdog_perform_action();
211
+{
138
+ }
212
+ return extract32(s->pupdr, 2 * pin, 2) == 2;
139
+}
213
+}
140
+
214
+
141
+static void imx2_wdt_reset(DeviceState *dev)
215
+static bool is_output(Stm32l4x5GpioState *s, unsigned pin)
142
+{
216
+{
143
+ IMX2WdtState *s = IMX2_WDT(dev);
217
+ return extract32(s->moder, 2 * pin, 2) == 1;
144
+
218
+}
145
+ ptimer_transaction_begin(s->timer);
219
+
146
+ ptimer_stop(s->timer);
220
+static bool is_open_drain(Stm32l4x5GpioState *s, unsigned pin)
147
+ ptimer_transaction_commit(s->timer);
221
+{
148
+
222
+ return extract32(s->otyper, pin, 1) == 1;
149
+ if (s->pretimeout_support) {
223
+}
150
+ ptimer_transaction_begin(s->itimer);
224
+
151
+ ptimer_stop(s->itimer);
225
+static bool is_push_pull(Stm32l4x5GpioState *s, unsigned pin)
152
+ ptimer_transaction_commit(s->itimer);
226
+{
153
+ }
227
+ return extract32(s->otyper, pin, 1) == 0;
154
+
228
+}
155
+ s->wicr_locked = false;
229
+
156
+ s->wcr_locked = false;
230
+static void stm32l4x5_gpio_reset_hold(Object *obj)
157
+ s->wcr_wde_locked = false;
231
+{
158
+
232
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
159
+ s->wcr = IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS;
233
+
160
+ s->wsr = 0;
234
+ s->moder = s->moder_reset;
161
+ s->wrsr &= ~(IMX2_WDT_WRSR_TOUT | IMX2_WDT_WRSR_SFTW);
235
+ s->otyper = 0x00000000;
162
+ s->wicr = IMX2_WDT_WICR_WICT_DEF;
236
+ s->ospeedr = s->ospeedr_reset;
163
+ s->wmcr = IMX2_WDT_WMCR_PDE;
237
+ s->pupdr = s->pupdr_reset;
164
+}
238
+ s->idr = 0x00000000;
165
+
239
+ s->odr = 0x00000000;
166
+static uint64_t imx2_wdt_read(void *opaque, hwaddr addr, unsigned int size)
240
+ s->lckr = 0x00000000;
167
+{
241
+ s->afrl = 0x00000000;
168
+ IMX2WdtState *s = IMX2_WDT(opaque);
242
+ s->afrh = 0x00000000;
169
+
243
+ s->ascr = 0x00000000;
170
+ switch (addr) {
244
+
171
+ case IMX2_WDT_WCR:
245
+ s->disconnected_pins = 0xFFFF;
172
+ return s->wcr;
246
+ s->pins_connected_high = 0x0000;
173
+ case IMX2_WDT_WSR:
247
+ update_gpio_idr(s);
174
+ return s->wsr;
248
+}
175
+ case IMX2_WDT_WRSR:
249
+
176
+ return s->wrsr;
250
+static void stm32l4x5_gpio_set(void *opaque, int line, int level)
177
+ case IMX2_WDT_WICR:
251
+{
178
+ return s->wicr;
252
+ Stm32l4x5GpioState *s = opaque;
179
+ case IMX2_WDT_WMCR:
253
+ /*
180
+ return s->wmcr;
254
+ * The pin isn't set if line is configured in output mode
181
+ }
255
+ * except if level is 0 and the output is open-drain.
182
return 0;
256
+ * This way there will be no short-circuit prone situations.
183
}
257
+ */
184
258
+ if (is_output(s, line) && !(is_open_drain(s, line) && (level == 0))) {
185
+static void imx_wdt2_update_itimer(IMX2WdtState *s, bool start)
259
+ qemu_log_mask(LOG_GUEST_ERROR, "Line %d can't be driven externally\n",
186
+{
260
+ line);
187
+ bool running = (s->wcr & IMX2_WDT_WCR_WDE) && (s->wcr & IMX2_WDT_WCR_WT);
261
+ return;
188
+ bool enabled = s->wicr & IMX2_WDT_WICR_WIE;
262
+ }
189
+
263
+
190
+ ptimer_transaction_begin(s->itimer);
264
+ s->disconnected_pins &= ~(1 << line);
191
+ if (start || !enabled) {
265
+ if (level) {
192
+ ptimer_stop(s->itimer);
266
+ s->pins_connected_high |= (1 << line);
193
+ }
267
+ } else {
194
+ if (running && enabled) {
268
+ s->pins_connected_high &= ~(1 << line);
195
+ int count = ptimer_get_count(s->timer);
269
+ }
196
+ int pretimeout = s->wicr & IMX2_WDT_WICR_WICT;
270
+ trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins,
197
+
271
+ s->pins_connected_high);
198
+ /*
272
+ update_gpio_idr(s);
199
+ * Only (re-)start pretimeout timer if its counter value is larger
273
+}
200
+ * than 0. Otherwise it will fire right away and we'll get an
274
+
201
+ * interrupt loop.
275
+
202
+ */
276
+static void update_gpio_idr(Stm32l4x5GpioState *s)
203
+ if (count > pretimeout) {
277
+{
204
+ ptimer_set_count(s->itimer, count - pretimeout);
278
+ uint32_t new_idr_mask = 0;
205
+ if (start) {
279
+ uint32_t new_idr = s->odr;
206
+ ptimer_run(s->itimer, 1);
280
+ uint32_t old_idr = s->idr;
281
+ int new_pin_state, old_pin_state;
282
+
283
+ for (int i = 0; i < GPIO_NUM_PINS; i++) {
284
+ if (is_output(s, i)) {
285
+ if (is_push_pull(s, i)) {
286
+ new_idr_mask |= (1 << i);
287
+ } else if (!(s->odr & (1 << i))) {
288
+ /* open-drain ODR 0 */
289
+ new_idr_mask |= (1 << i);
290
+ /* open-drain ODR 1 */
291
+ } else if (!(s->disconnected_pins & (1 << i)) &&
292
+ !(s->pins_connected_high & (1 << i))) {
293
+ /* open-drain ODR 1 with pin connected low */
294
+ new_idr_mask |= (1 << i);
295
+ new_idr &= ~(1 << i);
296
+ /* open-drain ODR 1 with unactive pin */
297
+ } else if (is_pull_up(s, i)) {
298
+ new_idr_mask |= (1 << i);
299
+ } else if (is_pull_down(s, i)) {
300
+ new_idr_mask |= (1 << i);
301
+ new_idr &= ~(1 << i);
302
+ }
303
+ /*
304
+ * The only case left is for open-drain ODR 1
305
+ * with unactive pin without pull-up or pull-down :
306
+ * the value is floating.
307
+ */
308
+ /* input or analog mode with connected pin */
309
+ } else if (!(s->disconnected_pins & (1 << i))) {
310
+ if (s->pins_connected_high & (1 << i)) {
311
+ /* pin high */
312
+ new_idr_mask |= (1 << i);
313
+ new_idr |= (1 << i);
314
+ } else {
315
+ /* pin low */
316
+ new_idr_mask |= (1 << i);
317
+ new_idr &= ~(1 << i);
318
+ }
319
+ /* input or analog mode with disconnected pin */
320
+ } else {
321
+ if (is_pull_up(s, i)) {
322
+ /* pull-up */
323
+ new_idr_mask |= (1 << i);
324
+ new_idr |= (1 << i);
325
+ } else if (is_pull_down(s, i)) {
326
+ /* pull-down */
327
+ new_idr_mask |= (1 << i);
328
+ new_idr &= ~(1 << i);
329
+ }
330
+ /*
331
+ * The only case left is for a disconnected pin
332
+ * without pull-up or pull-down :
333
+ * the value is floating.
334
+ */
335
+ }
336
+ }
337
+
338
+ s->idr = (old_idr & ~new_idr_mask) | (new_idr & new_idr_mask);
339
+ trace_stm32l4x5_gpio_update_idr(s->name, old_idr, s->idr);
340
+
341
+ for (int i = 0; i < GPIO_NUM_PINS; i++) {
342
+ if (new_idr_mask & (1 << i)) {
343
+ new_pin_state = (new_idr & (1 << i)) > 0;
344
+ old_pin_state = (old_idr & (1 << i)) > 0;
345
+ if (new_pin_state > old_pin_state) {
346
+ qemu_irq_raise(s->pin[i]);
347
+ } else if (new_pin_state < old_pin_state) {
348
+ qemu_irq_lower(s->pin[i]);
207
+ }
349
+ }
208
+ }
350
+ }
209
+ }
351
+ }
210
+ ptimer_transaction_commit(s->itimer);
352
+}
211
+}
353
+
212
+
354
+/*
213
+static void imx_wdt2_update_timer(IMX2WdtState *s, bool start)
355
+ * Return mask of pins that are both configured in output
214
+{
356
+ * mode and externally driven (except pins in open-drain
215
+ ptimer_transaction_begin(s->timer);
357
+ * mode externally set to 0).
216
+ if (start) {
358
+ */
217
+ ptimer_stop(s->timer);
359
+static uint32_t get_gpio_pinmask_to_disconnect(Stm32l4x5GpioState *s)
218
+ }
360
+{
219
+ if ((s->wcr & IMX2_WDT_WCR_WDE) && (s->wcr & IMX2_WDT_WCR_WT)) {
361
+ uint32_t pins_to_disconnect = 0;
220
+ int count = (s->wcr & IMX2_WDT_WCR_WT) >> 8;
362
+ for (int i = 0; i < GPIO_NUM_PINS; i++) {
221
+
363
+ /* for each connected pin in output mode */
222
+ /* A value of 0 reflects one period (0.5s). */
364
+ if (!(s->disconnected_pins & (1 << i)) && is_output(s, i)) {
223
+ ptimer_set_count(s->timer, count + 1);
365
+ /* if either push-pull or high level */
224
+ if (start) {
366
+ if (is_push_pull(s, i) || s->pins_connected_high & (1 << i)) {
225
+ ptimer_run(s->timer, 1);
367
+ pins_to_disconnect |= (1 << i);
368
+ qemu_log_mask(LOG_GUEST_ERROR,
369
+ "Line %d can't be driven externally\n",
370
+ i);
371
+ }
226
+ }
372
+ }
227
+ }
373
+ }
228
+ ptimer_transaction_commit(s->timer);
374
+ return pins_to_disconnect;
229
+ if (s->pretimeout_support) {
375
+}
230
+ imx_wdt2_update_itimer(s, start);
376
+
231
+ }
377
+/*
232
+}
378
+ * Set field `disconnected_pins` and call `update_gpio_idr()`
233
+
379
+ */
234
static void imx2_wdt_write(void *opaque, hwaddr addr,
380
+static void disconnect_gpio_pins(Stm32l4x5GpioState *s, uint16_t lines)
235
uint64_t value, unsigned int size)
381
+{
236
{
382
+ s->disconnected_pins |= lines;
237
- if (addr == IMX2_WDT_WCR &&
383
+ trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins,
238
- (~value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS))) {
384
+ s->pins_connected_high);
239
- watchdog_perform_action();
385
+ update_gpio_idr(s);
240
+ IMX2WdtState *s = IMX2_WDT(opaque);
386
+}
387
+
388
+static void disconnected_pins_set(Object *obj, Visitor *v,
389
+ const char *name, void *opaque, Error **errp)
390
+{
391
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
392
+ uint16_t value;
393
+ if (!visit_type_uint16(v, name, &value, errp)) {
394
+ return;
395
+ }
396
+ disconnect_gpio_pins(s, value);
397
+}
398
+
399
+static void disconnected_pins_get(Object *obj, Visitor *v,
400
+ const char *name, void *opaque, Error **errp)
401
+{
402
+ visit_type_uint16(v, name, (uint16_t *)opaque, errp);
403
+}
404
+
405
+static void clock_freq_get(Object *obj, Visitor *v,
406
+ const char *name, void *opaque, Error **errp)
407
+{
408
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
409
+ uint32_t clock_freq_hz = clock_get_hz(s->clk);
410
+ visit_type_uint32(v, name, &clock_freq_hz, errp);
411
+}
412
+
413
+static void stm32l4x5_gpio_write(void *opaque, hwaddr addr,
414
+ uint64_t val64, unsigned int size)
415
+{
416
+ Stm32l4x5GpioState *s = opaque;
417
+
418
+ uint32_t value = val64;
419
+ trace_stm32l4x5_gpio_write(s->name, addr, val64);
241
+
420
+
242
+ switch (addr) {
421
+ switch (addr) {
243
+ case IMX2_WDT_WCR:
422
+ case GPIO_MODER:
244
+ if (s->wcr_locked) {
423
+ s->moder = value;
245
+ value &= ~IMX2_WDT_WCR_LOCK_MASK;
424
+ disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s));
246
+ value |= (s->wicr & IMX2_WDT_WCR_LOCK_MASK);
425
+ qemu_log_mask(LOG_UNIMP,
247
+ }
426
+ "%s: Analog and AF modes aren't supported\n\
248
+ s->wcr_locked = true;
427
+ Analog and AF mode behave like input mode\n",
249
+ if (s->wcr_wde_locked) {
428
+ __func__);
250
+ value &= ~IMX2_WDT_WCR_WDE;
429
+ return;
251
+ value |= (s->wicr & ~IMX2_WDT_WCR_WDE);
430
+ case GPIO_OTYPER:
252
+ } else if (value & IMX2_WDT_WCR_WDE) {
431
+ s->otyper = value & ~RESERVED_BITS_MASK;
253
+ s->wcr_wde_locked = true;
432
+ disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s));
254
+ }
433
+ return;
255
+ if (s->wcr_wdt_locked) {
434
+ case GPIO_OSPEEDR:
256
+ value &= ~IMX2_WDT_WCR_WDT;
435
+ qemu_log_mask(LOG_UNIMP,
257
+ value |= (s->wicr & ~IMX2_WDT_WCR_WDT);
436
+ "%s: Changing I/O output speed isn't supported\n\
258
+ } else if (value & IMX2_WDT_WCR_WDT) {
437
+ I/O speed is already maximal\n",
259
+ s->wcr_wdt_locked = true;
438
+ __func__);
260
+ }
439
+ s->ospeedr = value;
261
+
440
+ return;
262
+ s->wcr = value;
441
+ case GPIO_PUPDR:
263
+ if (!(value & IMX2_WDT_WCR_SRS)) {
442
+ s->pupdr = value;
264
+ s->wrsr = IMX2_WDT_WRSR_SFTW;
443
+ update_gpio_idr(s);
265
+ }
444
+ return;
266
+ if (!(value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS)) ||
445
+ case GPIO_IDR:
267
+ (!(value & IMX2_WDT_WCR_WT) && (value & IMX2_WDT_WCR_WDE))) {
446
+ qemu_log_mask(LOG_UNIMP,
268
+ watchdog_perform_action();
447
+ "%s: GPIO->IDR is read-only\n",
269
+ }
448
+ __func__);
270
+ s->wcr |= IMX2_WDT_WCR_SRS;
449
+ return;
271
+ imx_wdt2_update_timer(s, true);
450
+ case GPIO_ODR:
272
+ break;
451
+ s->odr = value & ~RESERVED_BITS_MASK;
273
+ case IMX2_WDT_WSR:
452
+ update_gpio_idr(s);
274
+ if (s->wsr == IMX2_WDT_SEQ1 && value == IMX2_WDT_SEQ2) {
453
+ return;
275
+ imx_wdt2_update_timer(s, false);
454
+ case GPIO_BSRR: {
276
+ }
455
+ uint32_t bits_to_reset = (value & RESERVED_BITS_MASK) >> GPIO_NUM_PINS;
277
+ s->wsr = value;
456
+ uint32_t bits_to_set = value & ~RESERVED_BITS_MASK;
278
+ break;
457
+ /* If both BSx and BRx are set, BSx has priority.*/
279
+ case IMX2_WDT_WRSR:
458
+ s->odr &= ~bits_to_reset;
280
+ break;
459
+ s->odr |= bits_to_set;
281
+ case IMX2_WDT_WICR:
460
+ update_gpio_idr(s);
282
+ if (!s->pretimeout_support) {
461
+ return;
283
+ return;
462
+ }
284
+ }
463
+ case GPIO_LCKR:
285
+ value &= IMX2_WDT_WICR_LOCK_MASK | IMX2_WDT_WICR_WTIS;
464
+ qemu_log_mask(LOG_UNIMP,
286
+ if (s->wicr_locked) {
465
+ "%s: Locking port bits configuration isn't supported\n",
287
+ value &= IMX2_WDT_WICR_WTIS;
466
+ __func__);
288
+ value |= (s->wicr & IMX2_WDT_WICR_LOCK_MASK);
467
+ s->lckr = value & ~RESERVED_BITS_MASK;
289
+ }
468
+ return;
290
+ s->wicr = value | (s->wicr & IMX2_WDT_WICR_WTIS);
469
+ case GPIO_AFRL:
291
+ if (value & IMX2_WDT_WICR_WTIS) {
470
+ qemu_log_mask(LOG_UNIMP,
292
+ s->wicr &= ~IMX2_WDT_WICR_WTIS;
471
+ "%s: Alternate functions aren't supported\n",
293
+ qemu_set_irq(s->irq, 0);
472
+ __func__);
294
+ }
473
+ s->afrl = value;
295
+ imx_wdt2_update_itimer(s, true);
474
+ return;
296
+ s->wicr_locked = true;
475
+ case GPIO_AFRH:
297
+ break;
476
+ qemu_log_mask(LOG_UNIMP,
298
+ case IMX2_WDT_WMCR:
477
+ "%s: Alternate functions aren't supported\n",
299
+ s->wmcr = value & IMX2_WDT_WMCR_PDE;
478
+ __func__);
300
+ break;
479
+ s->afrh = value;
301
}
480
+ return;
302
}
481
+ case GPIO_BRR: {
303
482
+ uint32_t bits_to_reset = value & ~RESERVED_BITS_MASK;
304
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps imx2_wdt_ops = {
483
+ s->odr &= ~bits_to_reset;
305
* real device but in practice there is no reason for a guest
484
+ update_gpio_idr(s);
306
* to access this device unaligned.
485
+ return;
307
*/
486
+ }
308
- .min_access_size = 4,
487
+ case GPIO_ASCR:
309
- .max_access_size = 4,
488
+ qemu_log_mask(LOG_UNIMP,
310
+ .min_access_size = 2,
489
+ "%s: ADC function isn't supported\n",
311
+ .max_access_size = 2,
490
+ __func__);
312
.unaligned = false,
491
+ s->ascr = value & ~RESERVED_BITS_MASK;
313
},
492
+ return;
314
};
493
+ default:
315
494
+ qemu_log_mask(LOG_GUEST_ERROR,
316
+static const VMStateDescription vmstate_imx2_wdt = {
495
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
317
+ .name = "imx2.wdt",
496
+ }
318
+ .fields = (VMStateField[]) {
497
+}
319
+ VMSTATE_PTIMER(timer, IMX2WdtState),
498
+
320
+ VMSTATE_PTIMER(itimer, IMX2WdtState),
499
+static uint64_t stm32l4x5_gpio_read(void *opaque, hwaddr addr,
321
+ VMSTATE_BOOL(wicr_locked, IMX2WdtState),
500
+ unsigned int size)
322
+ VMSTATE_BOOL(wcr_locked, IMX2WdtState),
501
+{
323
+ VMSTATE_BOOL(wcr_wde_locked, IMX2WdtState),
502
+ Stm32l4x5GpioState *s = opaque;
324
+ VMSTATE_BOOL(wcr_wdt_locked, IMX2WdtState),
503
+
325
+ VMSTATE_UINT16(wcr, IMX2WdtState),
504
+ trace_stm32l4x5_gpio_read(s->name, addr);
326
+ VMSTATE_UINT16(wsr, IMX2WdtState),
505
+
327
+ VMSTATE_UINT16(wrsr, IMX2WdtState),
506
+ switch (addr) {
328
+ VMSTATE_UINT16(wmcr, IMX2WdtState),
507
+ case GPIO_MODER:
329
+ VMSTATE_UINT16(wicr, IMX2WdtState),
508
+ return s->moder;
509
+ case GPIO_OTYPER:
510
+ return s->otyper;
511
+ case GPIO_OSPEEDR:
512
+ return s->ospeedr;
513
+ case GPIO_PUPDR:
514
+ return s->pupdr;
515
+ case GPIO_IDR:
516
+ return s->idr;
517
+ case GPIO_ODR:
518
+ return s->odr;
519
+ case GPIO_BSRR:
520
+ return 0;
521
+ case GPIO_LCKR:
522
+ return s->lckr;
523
+ case GPIO_AFRL:
524
+ return s->afrl;
525
+ case GPIO_AFRH:
526
+ return s->afrh;
527
+ case GPIO_BRR:
528
+ return 0;
529
+ case GPIO_ASCR:
530
+ return s->ascr;
531
+ default:
532
+ qemu_log_mask(LOG_GUEST_ERROR,
533
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
534
+ return 0;
535
+ }
536
+}
537
+
538
+static const MemoryRegionOps stm32l4x5_gpio_ops = {
539
+ .read = stm32l4x5_gpio_read,
540
+ .write = stm32l4x5_gpio_write,
541
+ .endianness = DEVICE_NATIVE_ENDIAN,
542
+ .impl = {
543
+ .min_access_size = 4,
544
+ .max_access_size = 4,
545
+ .unaligned = false,
546
+ },
547
+ .valid = {
548
+ .min_access_size = 4,
549
+ .max_access_size = 4,
550
+ .unaligned = false,
551
+ },
552
+};
553
+
554
+static void stm32l4x5_gpio_init(Object *obj)
555
+{
556
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
557
+
558
+ memory_region_init_io(&s->mmio, obj, &stm32l4x5_gpio_ops, s,
559
+ TYPE_STM32L4X5_GPIO, 0x400);
560
+
561
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
562
+
563
+ qdev_init_gpio_out(DEVICE(obj), s->pin, GPIO_NUM_PINS);
564
+ qdev_init_gpio_in(DEVICE(obj), stm32l4x5_gpio_set, GPIO_NUM_PINS);
565
+
566
+ s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0);
567
+
568
+ object_property_add(obj, "disconnected-pins", "uint16",
569
+ disconnected_pins_get, disconnected_pins_set,
570
+ NULL, &s->disconnected_pins);
571
+ object_property_add(obj, "clock-freq-hz", "uint32",
572
+ clock_freq_get, NULL, NULL, NULL);
573
+}
574
+
575
+static void stm32l4x5_gpio_realize(DeviceState *dev, Error **errp)
576
+{
577
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(dev);
578
+ if (!clock_has_source(s->clk)) {
579
+ error_setg(errp, "GPIO: clk input must be connected");
580
+ return;
581
+ }
582
+}
583
+
584
+static const VMStateDescription vmstate_stm32l4x5_gpio = {
585
+ .name = TYPE_STM32L4X5_GPIO,
586
+ .version_id = 1,
587
+ .minimum_version_id = 1,
588
+ .fields = (VMStateField[]){
589
+ VMSTATE_UINT32(moder, Stm32l4x5GpioState),
590
+ VMSTATE_UINT32(otyper, Stm32l4x5GpioState),
591
+ VMSTATE_UINT32(ospeedr, Stm32l4x5GpioState),
592
+ VMSTATE_UINT32(pupdr, Stm32l4x5GpioState),
593
+ VMSTATE_UINT32(idr, Stm32l4x5GpioState),
594
+ VMSTATE_UINT32(odr, Stm32l4x5GpioState),
595
+ VMSTATE_UINT32(lckr, Stm32l4x5GpioState),
596
+ VMSTATE_UINT32(afrl, Stm32l4x5GpioState),
597
+ VMSTATE_UINT32(afrh, Stm32l4x5GpioState),
598
+ VMSTATE_UINT32(ascr, Stm32l4x5GpioState),
599
+ VMSTATE_UINT16(disconnected_pins, Stm32l4x5GpioState),
600
+ VMSTATE_UINT16(pins_connected_high, Stm32l4x5GpioState),
330
+ VMSTATE_END_OF_LIST()
601
+ VMSTATE_END_OF_LIST()
331
+ }
602
+ }
332
+};
603
+};
333
+
604
+
334
static void imx2_wdt_realize(DeviceState *dev, Error **errp)
605
+static Property stm32l4x5_gpio_properties[] = {
335
{
606
+ DEFINE_PROP_STRING("name", Stm32l4x5GpioState, name),
336
IMX2WdtState *s = IMX2_WDT(dev);
607
+ DEFINE_PROP_UINT32("mode-reset", Stm32l4x5GpioState, moder_reset, 0),
337
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
608
+ DEFINE_PROP_UINT32("ospeed-reset", Stm32l4x5GpioState, ospeedr_reset, 0),
338
609
+ DEFINE_PROP_UINT32("pupd-reset", Stm32l4x5GpioState, pupdr_reset, 0),
339
memory_region_init_io(&s->mmio, OBJECT(dev),
610
+ DEFINE_PROP_END_OF_LIST(),
340
&imx2_wdt_ops, s,
341
- TYPE_IMX2_WDT".mmio",
342
- IMX2_WDT_REG_NUM * sizeof(uint16_t));
343
- sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
344
+ TYPE_IMX2_WDT,
345
+ IMX2_WDT_MMIO_SIZE);
346
+ sysbus_init_mmio(sbd, &s->mmio);
347
+ sysbus_init_irq(sbd, &s->irq);
348
+
349
+ s->timer = ptimer_init(imx2_wdt_expired, s,
350
+ PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
351
+ PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
352
+ PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
353
+ ptimer_transaction_begin(s->timer);
354
+ ptimer_set_freq(s->timer, 2);
355
+ ptimer_set_limit(s->timer, 0xff, 1);
356
+ ptimer_transaction_commit(s->timer);
357
+ if (s->pretimeout_support) {
358
+ s->itimer = ptimer_init(imx2_wdt_interrupt, s,
359
+ PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
360
+ PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
361
+ PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
362
+ ptimer_transaction_begin(s->itimer);
363
+ ptimer_set_freq(s->itimer, 2);
364
+ ptimer_set_limit(s->itimer, 0xff, 1);
365
+ ptimer_transaction_commit(s->itimer);
366
+ }
367
}
368
369
+static Property imx2_wdt_properties[] = {
370
+ DEFINE_PROP_BOOL("pretimeout-support", IMX2WdtState, pretimeout_support,
371
+ false),
372
+};
611
+};
373
+
612
+
374
static void imx2_wdt_class_init(ObjectClass *klass, void *data)
613
+static void stm32l4x5_gpio_class_init(ObjectClass *klass, void *data)
375
{
614
+{
376
DeviceClass *dc = DEVICE_CLASS(klass);
615
+ DeviceClass *dc = DEVICE_CLASS(klass);
377
616
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
378
+ device_class_set_props(dc, imx2_wdt_properties);
617
+
379
dc->realize = imx2_wdt_realize;
618
+ device_class_set_props(dc, stm32l4x5_gpio_properties);
380
+ dc->reset = imx2_wdt_reset;
619
+ dc->vmsd = &vmstate_stm32l4x5_gpio;
381
+ dc->vmsd = &vmstate_imx2_wdt;
620
+ dc->realize = stm32l4x5_gpio_realize;
382
+ dc->desc = "i.MX watchdog timer";
621
+ rc->phases.hold = stm32l4x5_gpio_reset_hold;
383
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
622
+}
384
}
623
+
385
624
+static const TypeInfo stm32l4x5_gpio_types[] = {
625
+ {
626
+ .name = TYPE_STM32L4X5_GPIO,
627
+ .parent = TYPE_SYS_BUS_DEVICE,
628
+ .instance_size = sizeof(Stm32l4x5GpioState),
629
+ .instance_init = stm32l4x5_gpio_init,
630
+ .class_init = stm32l4x5_gpio_class_init,
631
+ },
632
+};
633
+
634
+DEFINE_TYPES(stm32l4x5_gpio_types)
635
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
636
index XXXXXXX..XXXXXXX 100644
637
--- a/hw/gpio/Kconfig
638
+++ b/hw/gpio/Kconfig
639
@@ -XXX,XX +XXX,XX @@ config GPIO_PWR
640
641
config SIFIVE_GPIO
642
bool
643
+
644
+config STM32L4X5_GPIO
645
+ bool
646
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
647
index XXXXXXX..XXXXXXX 100644
648
--- a/hw/gpio/meson.build
649
+++ b/hw/gpio/meson.build
650
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files(
651
'bcm2835_gpio.c',
652
'bcm2838_gpio.c'
653
))
654
+system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_gpio.c'))
655
system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
656
system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
657
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
658
index XXXXXXX..XXXXXXX 100644
659
--- a/hw/gpio/trace-events
660
+++ b/hw/gpio/trace-events
661
@@ -XXX,XX +XXX,XX @@ sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " val
662
# aspeed_gpio.c
663
aspeed_gpio_read(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64
664
aspeed_gpio_write(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64
665
+
666
+# stm32l4x5_gpio.c
667
+stm32l4x5_gpio_read(char *gpio, uint64_t addr) "GPIO%s addr: 0x%" PRIx64 " "
668
+stm32l4x5_gpio_write(char *gpio, uint64_t addr, uint64_t data) "GPIO%s addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
669
+stm32l4x5_gpio_update_idr(char *gpio, uint32_t old_idr, uint32_t new_idr) "GPIO%s from: 0x%x to: 0x%x"
670
+stm32l4x5_gpio_pins(char *gpio, uint16_t disconnected, uint16_t high) "GPIO%s disconnected pins: 0x%x levels: 0x%x"
386
--
671
--
387
2.20.1
672
2.34.1
388
673
389
674
diff view generated by jsdifflib
[PULL 15/29] hw/arm/fsl-imx31: Wire up watchdog
[PULL 10/14] hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
With this patch, the watchdog on i.MX31 emulations is fully operational.
3
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
4
4
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-id: 20200517162135.110364-5-linux@roeck-us.net
7
Message-id: 20240305210444.310665-3-ines.varhol@telecom-paris.fr
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
9
---
10
include/hw/arm/fsl-imx31.h | 4 ++++
10
include/hw/arm/stm32l4x5_soc.h | 2 +
11
hw/arm/fsl-imx31.c | 6 ++++++
11
include/hw/gpio/stm32l4x5_gpio.h | 1 +
12
hw/arm/Kconfig | 1 +
12
include/hw/misc/stm32l4x5_syscfg.h | 3 +-
13
3 files changed, 11 insertions(+)
13
hw/arm/stm32l4x5_soc.c | 71 +++++++++++++++++++++++-------
14
14
hw/misc/stm32l4x5_syscfg.c | 1 +
15
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
15
hw/arm/Kconfig | 3 +-
16
index XXXXXXX..XXXXXXX 100644
16
6 files changed, 63 insertions(+), 18 deletions(-)
17
--- a/include/hw/arm/fsl-imx31.h
17
18
+++ b/include/hw/arm/fsl-imx31.h
18
diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h
19
@@ -XXX,XX +XXX,XX @@
19
index XXXXXXX..XXXXXXX 100644
20
#include "hw/timer/imx_epit.h"
20
--- a/include/hw/arm/stm32l4x5_soc.h
21
#include "hw/i2c/imx_i2c.h"
21
+++ b/include/hw/arm/stm32l4x5_soc.h
22
#include "hw/gpio/imx_gpio.h"
22
@@ -XXX,XX +XXX,XX @@
23
+#include "hw/watchdog/wdt_imx2.h"
23
#include "hw/misc/stm32l4x5_syscfg.h"
24
#include "exec/memory.h"
24
#include "hw/misc/stm32l4x5_exti.h"
25
#include "target/arm/cpu.h"
25
#include "hw/misc/stm32l4x5_rcc.h"
26
26
+#include "hw/gpio/stm32l4x5_gpio.h"
27
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX31State {
27
#include "qom/object.h"
28
IMXEPITState epit[FSL_IMX31_NUM_EPITS];
28
29
IMXI2CState i2c[FSL_IMX31_NUM_I2CS];
29
#define TYPE_STM32L4X5_SOC "stm32l4x5-soc"
30
IMXGPIOState gpio[FSL_IMX31_NUM_GPIOS];
30
@@ -XXX,XX +XXX,XX @@ struct Stm32l4x5SocState {
31
+ IMX2WdtState wdt;
31
OrIRQState exti_or_gates[NUM_EXTI_OR_GATES];
32
MemoryRegion secure_rom;
32
Stm32l4x5SyscfgState syscfg;
33
MemoryRegion rom;
33
Stm32l4x5RccState rcc;
34
MemoryRegion iram;
34
+ Stm32l4x5GpioState gpio[NUM_GPIOS];
35
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX31State {
35
36
#define FSL_IMX31_GPIO1_SIZE 0x4000
36
MemoryRegion sram1;
37
#define FSL_IMX31_GPIO2_ADDR 0x53FD0000
37
MemoryRegion sram2;
38
#define FSL_IMX31_GPIO2_SIZE 0x4000
38
diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_gpio.h
39
+#define FSL_IMX31_WDT_ADDR 0x53FDC000
39
index XXXXXXX..XXXXXXX 100644
40
+#define FSL_IMX31_WDT_SIZE 0x4000
40
--- a/include/hw/gpio/stm32l4x5_gpio.h
41
#define FSL_IMX31_AVIC_ADDR 0x68000000
41
+++ b/include/hw/gpio/stm32l4x5_gpio.h
42
#define FSL_IMX31_AVIC_SIZE 0x100
42
@@ -XXX,XX +XXX,XX @@
43
#define FSL_IMX31_SDRAM0_ADDR 0x80000000
43
#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"
44
diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c
44
OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO)
45
index XXXXXXX..XXXXXXX 100644
45
46
--- a/hw/arm/fsl-imx31.c
46
+#define NUM_GPIOS 8
47
+++ b/hw/arm/fsl-imx31.c
47
#define GPIO_NUM_PINS 16
48
@@ -XXX,XX +XXX,XX @@ static void fsl_imx31_init(Object *obj)
48
49
sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
49
struct Stm32l4x5GpioState {
50
TYPE_IMX_GPIO);
50
diff --git a/include/hw/misc/stm32l4x5_syscfg.h b/include/hw/misc/stm32l4x5_syscfg.h
51
}
51
index XXXXXXX..XXXXXXX 100644
52
+
52
--- a/include/hw/misc/stm32l4x5_syscfg.h
53
+ sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), TYPE_IMX2_WDT);
53
+++ b/include/hw/misc/stm32l4x5_syscfg.h
54
@@ -XXX,XX +XXX,XX @@
55
56
#include "hw/sysbus.h"
57
#include "qom/object.h"
58
+#include "hw/gpio/stm32l4x5_gpio.h"
59
60
#define TYPE_STM32L4X5_SYSCFG "stm32l4x5-syscfg"
61
OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5SyscfgState, STM32L4X5_SYSCFG)
62
63
-#define NUM_GPIOS 8
64
-#define GPIO_NUM_PINS 16
65
#define SYSCFG_NUM_EXTICR 4
66
67
struct Stm32l4x5SyscfgState {
68
diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/arm/stm32l4x5_soc.c
71
+++ b/hw/arm/stm32l4x5_soc.c
72
@@ -XXX,XX +XXX,XX @@
73
#include "sysemu/sysemu.h"
74
#include "hw/or-irq.h"
75
#include "hw/arm/stm32l4x5_soc.h"
76
+#include "hw/gpio/stm32l4x5_gpio.h"
77
#include "hw/qdev-clock.h"
78
#include "hw/misc/unimp.h"
79
80
@@ -XXX,XX +XXX,XX @@ static const int exti_or_gate1_lines_in[EXTI_OR_GATE1_NUM_LINES_IN] = {
81
16, 35, 36, 37, 38,
82
};
83
84
+static const struct {
85
+ uint32_t addr;
86
+ uint32_t moder_reset;
87
+ uint32_t ospeedr_reset;
88
+ uint32_t pupdr_reset;
89
+} stm32l4x5_gpio_cfg[NUM_GPIOS] = {
90
+ { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 },
91
+ { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 },
92
+ { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
93
+ { 0x48000C00, 0xFFFFFFFF, 0x00000000, 0x00000000 },
94
+ { 0x48001000, 0xFFFFFFFF, 0x00000000, 0x00000000 },
95
+ { 0x48001400, 0xFFFFFFFF, 0x00000000, 0x00000000 },
96
+ { 0x48001800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
97
+ { 0x48001C00, 0x0000000F, 0x00000000, 0x00000000 },
98
+};
99
+
100
static void stm32l4x5_soc_initfn(Object *obj)
101
{
102
Stm32l4x5SocState *s = STM32L4X5_SOC(obj);
103
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_initfn(Object *obj)
104
}
105
object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSCFG);
106
object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32L4X5_RCC);
107
+
108
+ for (unsigned i = 0; i < NUM_GPIOS; i++) {
109
+ g_autofree char *name = g_strdup_printf("gpio%c", 'a' + i);
110
+ object_initialize_child(obj, name, &s->gpio[i], TYPE_STM32L4X5_GPIO);
111
+ }
54
}
112
}
55
113
56
static void fsl_imx31_realize(DeviceState *dev, Error **errp)
114
static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
57
@@ -XXX,XX +XXX,XX @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
115
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
58
gpio_table[i].irq));
116
Stm32l4x5SocState *s = STM32L4X5_SOC(dev_soc);
59
}
117
const Stm32l4x5SocClass *sc = STM32L4X5_SOC_GET_CLASS(dev_soc);
60
118
MemoryRegion *system_memory = get_system_memory();
61
+ /* Watchdog */
119
- DeviceState *armv7m;
62
+ object_property_set_bool(OBJECT(&s->wdt), true, "realized", &error_abort);
120
+ DeviceState *armv7m, *dev;
63
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX31_WDT_ADDR);
121
SysBusDevice *busdev;
64
+
122
+ uint32_t pin_index;
65
/* On a real system, the first 16k is a `secure boot rom' */
123
66
memory_region_init_rom(&s->secure_rom, OBJECT(dev), "imx31.secure_rom",
124
if (!memory_region_init_rom(&s->flash, OBJECT(dev_soc), "flash",
67
FSL_IMX31_SECURE_ROM_SIZE, &err);
125
sc->flash_size, errp)) {
126
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
127
return;
128
}
129
130
+ /* GPIOs */
131
+ for (unsigned i = 0; i < NUM_GPIOS; i++) {
132
+ g_autofree char *name = g_strdup_printf("%c", 'A' + i);
133
+ dev = DEVICE(&s->gpio[i]);
134
+ qdev_prop_set_string(dev, "name", name);
135
+ qdev_prop_set_uint32(dev, "mode-reset",
136
+ stm32l4x5_gpio_cfg[i].moder_reset);
137
+ qdev_prop_set_uint32(dev, "ospeed-reset",
138
+ stm32l4x5_gpio_cfg[i].ospeedr_reset);
139
+ qdev_prop_set_uint32(dev, "pupd-reset",
140
+ stm32l4x5_gpio_cfg[i].pupdr_reset);
141
+ busdev = SYS_BUS_DEVICE(&s->gpio[i]);
142
+ g_free(name);
143
+ name = g_strdup_printf("gpio%c-out", 'a' + i);
144
+ qdev_connect_clock_in(DEVICE(&s->gpio[i]), "clk",
145
+ qdev_get_clock_out(DEVICE(&(s->rcc)), name));
146
+ if (!sysbus_realize(busdev, errp)) {
147
+ return;
148
+ }
149
+ sysbus_mmio_map(busdev, 0, stm32l4x5_gpio_cfg[i].addr);
150
+ }
151
+
152
/* System configuration controller */
153
busdev = SYS_BUS_DEVICE(&s->syscfg);
154
if (!sysbus_realize(busdev, errp)) {
155
return;
156
}
157
sysbus_mmio_map(busdev, 0, SYSCFG_ADDR);
158
- /*
159
- * TODO: when the GPIO device is implemented, connect it
160
- * to SYCFG using `qdev_connect_gpio_out`, NUM_GPIOS and
161
- * GPIO_NUM_PINS.
162
- */
163
+
164
+ for (unsigned i = 0; i < NUM_GPIOS; i++) {
165
+ for (unsigned j = 0; j < GPIO_NUM_PINS; j++) {
166
+ pin_index = GPIO_NUM_PINS * i + j;
167
+ qdev_connect_gpio_out(DEVICE(&s->gpio[i]), j,
168
+ qdev_get_gpio_in(DEVICE(&s->syscfg),
169
+ pin_index));
170
+ }
171
+ }
172
173
/* EXTI device */
174
busdev = SYS_BUS_DEVICE(&s->exti);
175
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
176
}
177
}
178
179
- for (unsigned i = 0; i < 16; i++) {
180
+ for (unsigned i = 0; i < GPIO_NUM_PINS; i++) {
181
qdev_connect_gpio_out(DEVICE(&s->syscfg), i,
182
qdev_get_gpio_in(DEVICE(&s->exti), i));
183
}
184
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
185
/* RESERVED: 0x40024400, 0x7FDBC00 */
186
187
/* AHB2 BUS */
188
- create_unimplemented_device("GPIOA", 0x48000000, 0x400);
189
- create_unimplemented_device("GPIOB", 0x48000400, 0x400);
190
- create_unimplemented_device("GPIOC", 0x48000800, 0x400);
191
- create_unimplemented_device("GPIOD", 0x48000C00, 0x400);
192
- create_unimplemented_device("GPIOE", 0x48001000, 0x400);
193
- create_unimplemented_device("GPIOF", 0x48001400, 0x400);
194
- create_unimplemented_device("GPIOG", 0x48001800, 0x400);
195
- create_unimplemented_device("GPIOH", 0x48001C00, 0x400);
196
/* RESERVED: 0x48002000, 0x7FDBC00 */
197
create_unimplemented_device("OTG_FS", 0x50000000, 0x40000);
198
create_unimplemented_device("ADC", 0x50040000, 0x400);
199
diff --git a/hw/misc/stm32l4x5_syscfg.c b/hw/misc/stm32l4x5_syscfg.c
200
index XXXXXXX..XXXXXXX 100644
201
--- a/hw/misc/stm32l4x5_syscfg.c
202
+++ b/hw/misc/stm32l4x5_syscfg.c
203
@@ -XXX,XX +XXX,XX @@
204
#include "hw/irq.h"
205
#include "migration/vmstate.h"
206
#include "hw/misc/stm32l4x5_syscfg.h"
207
+#include "hw/gpio/stm32l4x5_gpio.h"
208
209
#define SYSCFG_MEMRMP 0x00
210
#define SYSCFG_CFGR1 0x04
68
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
211
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
69
index XXXXXXX..XXXXXXX 100644
212
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/arm/Kconfig
213
--- a/hw/arm/Kconfig
71
+++ b/hw/arm/Kconfig
214
+++ b/hw/arm/Kconfig
72
@@ -XXX,XX +XXX,XX @@ config FSL_IMX31
215
@@ -XXX,XX +XXX,XX @@ config STM32L4X5_SOC
73
select SERIAL
216
bool
74
select IMX
217
select ARM_V7M
75
select IMX_I2C
218
select OR_IRQ
76
+ select WDT_IMX2
219
- select STM32L4X5_SYSCFG
77
select LAN9118
220
select STM32L4X5_EXTI
78
221
+ select STM32L4X5_SYSCFG
79
config FSL_IMX6
222
select STM32L4X5_RCC
223
+ select STM32L4X5_GPIO
224
225
config XLNX_ZYNQMP_ARM
226
bool
80
--
227
--
81
2.20.1
228
2.34.1
82
229
83
230
diff view generated by jsdifflib
[PULL 06/29] docs/system: Document Musca boards
[PULL 11/14] tests/qtest: Add STM32L4x5 GPIO QTest testcase
1
Provide a minimal documentation of the Musca boards.
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
The testcase contains :
4
- `test_idr_reset_value()` :
5
Checks the reset values of MODER, OTYPER, PUPDR, ODR and IDR.
6
- `test_gpio_output_mode()` :
7
Checks that writing a bit in register ODR results in the corresponding
8
pin rising or lowering, if this pin is configured in output mode.
9
- `test_gpio_input_mode()` :
10
Checks that a input pin set high or low externally results
11
in the pin rising and lowering.
12
- `test_pull_up_pull_down()` :
13
Checks that a floating pin in pull-up/down mode is actually high/down.
14
- `test_push_pull()` :
15
Checks that a pin set externally is disconnected when configured in
16
push-pull output mode, and can't be set externally while in this mode.
17
- `test_open_drain()` :
18
Checks that a pin set externally high is disconnected when configured
19
in open-drain output mode, and can't be set high while in this mode.
20
- `test_bsrr_brr()` :
21
Checks that writing to BSRR and BRR has the desired result in ODR.
22
- `test_clock_enable()` :
23
Checks that GPIO clock is at the right frequency after enabling it.
24
25
Acked-by: Thomas Huth <thuth@redhat.com>
26
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
27
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
28
Message-id: 20240305210444.310665-4-ines.varhol@telecom-paris.fr
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20200507151819.28444-6-peter.maydell@linaro.org
8
---
30
---
9
docs/system/arm/musca.rst | 31 +++++++++++++++++++++++++++++++
31
tests/qtest/stm32l4x5_gpio-test.c | 551 ++++++++++++++++++++++++++++++
10
docs/system/target-arm.rst | 1 +
32
tests/qtest/meson.build | 3 +-
11
MAINTAINERS | 1 +
33
2 files changed, 553 insertions(+), 1 deletion(-)
12
3 files changed, 33 insertions(+)
34
create mode 100644 tests/qtest/stm32l4x5_gpio-test.c
13
create mode 100644 docs/system/arm/musca.rst
14
35
15
diff --git a/docs/system/arm/musca.rst b/docs/system/arm/musca.rst
36
diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c
16
new file mode 100644
37
new file mode 100644
17
index XXXXXXX..XXXXXXX
38
index XXXXXXX..XXXXXXX
18
--- /dev/null
39
--- /dev/null
19
+++ b/docs/system/arm/musca.rst
40
+++ b/tests/qtest/stm32l4x5_gpio-test.c
20
@@ -XXX,XX +XXX,XX @@
41
@@ -XXX,XX +XXX,XX @@
21
+Arm Musca boards (``musca-a``, ``musca-b1``)
42
+/*
22
+============================================
43
+ * QTest testcase for STM32L4x5_GPIO
23
+
44
+ *
24
+The Arm Musca development boards are a reference implementation
45
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
25
+of a system using the SSE-200 Subsystem for Embedded. They are
46
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
26
+dual Cortex-M33 systems.
47
+ *
27
+
48
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
28
+QEMU provides models of the A and B1 variants of this board.
49
+ * See the COPYING file in the top-level directory.
29
+
50
+ */
30
+Unimplemented devices:
51
+
31
+
52
+#include "qemu/osdep.h"
32
+- SPI
53
+#include "libqtest-single.h"
33
+- |I2C|
54
+
34
+- |I2S|
55
+#define GPIO_BASE_ADDR 0x48000000
35
+- PWM
56
+#define GPIO_SIZE 0x400
36
+- QSPI
57
+#define NUM_GPIOS 8
37
+- Timer
58
+#define NUM_GPIO_PINS 16
38
+- SCC
59
+
39
+- GPIO
60
+#define GPIO_A 0x48000000
40
+- eFlash
61
+#define GPIO_B 0x48000400
41
+- MHU
62
+#define GPIO_C 0x48000800
42
+- PVT
63
+#define GPIO_D 0x48000C00
43
+- SDIO
64
+#define GPIO_E 0x48001000
44
+- CryptoCell
65
+#define GPIO_F 0x48001400
45
+
66
+#define GPIO_G 0x48001800
46
+Note that (like the real hardware) the Musca-A machine is
67
+#define GPIO_H 0x48001C00
47
+asymmetric: CPU 0 does not have the FPU or DSP extensions,
68
+
48
+but CPU 1 does. Also like the real hardware, the memory maps
69
+#define MODER 0x00
49
+for the A and B1 variants differ significantly, so guest
70
+#define OTYPER 0x04
50
+software must be built for the right variant.
71
+#define PUPDR 0x0C
51
+
72
+#define IDR 0x10
52
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
73
+#define ODR 0x14
74
+#define BSRR 0x18
75
+#define BRR 0x28
76
+
77
+#define MODER_INPUT 0
78
+#define MODER_OUTPUT 1
79
+
80
+#define PUPDR_NONE 0
81
+#define PUPDR_PULLUP 1
82
+#define PUPDR_PULLDOWN 2
83
+
84
+#define OTYPER_PUSH_PULL 0
85
+#define OTYPER_OPEN_DRAIN 1
86
+
87
+const uint32_t moder_reset[NUM_GPIOS] = {
88
+ 0xABFFFFFF,
89
+ 0xFFFFFEBF,
90
+ 0xFFFFFFFF,
91
+ 0xFFFFFFFF,
92
+ 0xFFFFFFFF,
93
+ 0xFFFFFFFF,
94
+ 0xFFFFFFFF,
95
+ 0x0000000F
96
+};
97
+
98
+const uint32_t pupdr_reset[NUM_GPIOS] = {
99
+ 0x64000000,
100
+ 0x00000100,
101
+ 0x00000000,
102
+ 0x00000000,
103
+ 0x00000000,
104
+ 0x00000000,
105
+ 0x00000000,
106
+ 0x00000000
107
+};
108
+
109
+const uint32_t idr_reset[NUM_GPIOS] = {
110
+ 0x0000A000,
111
+ 0x00000010,
112
+ 0x00000000,
113
+ 0x00000000,
114
+ 0x00000000,
115
+ 0x00000000,
116
+ 0x00000000,
117
+ 0x00000000
118
+};
119
+
120
+static uint32_t gpio_readl(unsigned int gpio, unsigned int offset)
121
+{
122
+ return readl(gpio + offset);
123
+}
124
+
125
+static void gpio_writel(unsigned int gpio, unsigned int offset, uint32_t value)
126
+{
127
+ writel(gpio + offset, value);
128
+}
129
+
130
+static void gpio_set_bit(unsigned int gpio, unsigned int reg,
131
+ unsigned int pin, uint32_t value)
132
+{
133
+ uint32_t mask = 0xFFFFFFFF & ~(0x1 << pin);
134
+ gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << pin);
135
+}
136
+
137
+static void gpio_set_2bits(unsigned int gpio, unsigned int reg,
138
+ unsigned int pin, uint32_t value)
139
+{
140
+ uint32_t offset = 2 * pin;
141
+ uint32_t mask = 0xFFFFFFFF & ~(0x3 << offset);
142
+ gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << offset);
143
+}
144
+
145
+static unsigned int get_gpio_id(uint32_t gpio_addr)
146
+{
147
+ return (gpio_addr - GPIO_BASE_ADDR) / GPIO_SIZE;
148
+}
149
+
150
+static void gpio_set_irq(unsigned int gpio, int num, int level)
151
+{
152
+ g_autofree char *name = g_strdup_printf("/machine/soc/gpio%c",
153
+ get_gpio_id(gpio) + 'a');
154
+ qtest_set_irq_in(global_qtest, name, NULL, num, level);
155
+}
156
+
157
+static void disconnect_all_pins(unsigned int gpio)
158
+{
159
+ g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c",
160
+ get_gpio_id(gpio) + 'a');
161
+ QDict *r;
162
+
163
+ r = qtest_qmp(global_qtest, "{ 'execute': 'qom-set', 'arguments': "
164
+ "{ 'path': %s, 'property': 'disconnected-pins', 'value': %d } }",
165
+ path, 0xFFFF);
166
+ g_assert_false(qdict_haskey(r, "error"));
167
+ qobject_unref(r);
168
+}
169
+
170
+static uint32_t get_disconnected_pins(unsigned int gpio)
171
+{
172
+ g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c",
173
+ get_gpio_id(gpio) + 'a');
174
+ uint32_t disconnected_pins = 0;
175
+ QDict *r;
176
+
177
+ r = qtest_qmp(global_qtest, "{ 'execute': 'qom-get', 'arguments':"
178
+ " { 'path': %s, 'property': 'disconnected-pins'} }", path);
179
+ g_assert_false(qdict_haskey(r, "error"));
180
+ disconnected_pins = qdict_get_int(r, "return");
181
+ qobject_unref(r);
182
+ return disconnected_pins;
183
+}
184
+
185
+static uint32_t reset(uint32_t gpio, unsigned int offset)
186
+{
187
+ switch (offset) {
188
+ case MODER:
189
+ return moder_reset[get_gpio_id(gpio)];
190
+ case PUPDR:
191
+ return pupdr_reset[get_gpio_id(gpio)];
192
+ case IDR:
193
+ return idr_reset[get_gpio_id(gpio)];
194
+ }
195
+ return 0x0;
196
+}
197
+
198
+static void system_reset(void)
199
+{
200
+ QDict *r;
201
+ r = qtest_qmp(global_qtest, "{'execute': 'system_reset'}");
202
+ g_assert_false(qdict_haskey(r, "error"));
203
+ qobject_unref(r);
204
+}
205
+
206
+static void test_idr_reset_value(void)
207
+{
208
+ /*
209
+ * Checks that the values in MODER, OTYPER, PUPDR and ODR
210
+ * after reset are correct, and that the value in IDR is
211
+ * coherent.
212
+ * Since AF and analog modes aren't implemented, IDR reset
213
+ * values aren't the same as with a real board.
214
+ *
215
+ * Register IDR contains the actual values of all GPIO pins.
216
+ * Its value depends on the pins' configuration
217
+ * (intput/output/analog : register MODER, push-pull/open-drain :
218
+ * register OTYPER, pull-up/pull-down/none : register PUPDR)
219
+ * and on the values stored in register ODR
220
+ * (in case the pin is in output mode).
221
+ */
222
+
223
+ gpio_writel(GPIO_A, MODER, 0xDEADBEEF);
224
+ gpio_writel(GPIO_A, ODR, 0xDEADBEEF);
225
+ gpio_writel(GPIO_A, OTYPER, 0xDEADBEEF);
226
+ gpio_writel(GPIO_A, PUPDR, 0xDEADBEEF);
227
+
228
+ gpio_writel(GPIO_B, MODER, 0xDEADBEEF);
229
+ gpio_writel(GPIO_B, ODR, 0xDEADBEEF);
230
+ gpio_writel(GPIO_B, OTYPER, 0xDEADBEEF);
231
+ gpio_writel(GPIO_B, PUPDR, 0xDEADBEEF);
232
+
233
+ gpio_writel(GPIO_C, MODER, 0xDEADBEEF);
234
+ gpio_writel(GPIO_C, ODR, 0xDEADBEEF);
235
+ gpio_writel(GPIO_C, OTYPER, 0xDEADBEEF);
236
+ gpio_writel(GPIO_C, PUPDR, 0xDEADBEEF);
237
+
238
+ gpio_writel(GPIO_H, MODER, 0xDEADBEEF);
239
+ gpio_writel(GPIO_H, ODR, 0xDEADBEEF);
240
+ gpio_writel(GPIO_H, OTYPER, 0xDEADBEEF);
241
+ gpio_writel(GPIO_H, PUPDR, 0xDEADBEEF);
242
+
243
+ system_reset();
244
+
245
+ uint32_t moder = gpio_readl(GPIO_A, MODER);
246
+ uint32_t odr = gpio_readl(GPIO_A, ODR);
247
+ uint32_t otyper = gpio_readl(GPIO_A, OTYPER);
248
+ uint32_t pupdr = gpio_readl(GPIO_A, PUPDR);
249
+ uint32_t idr = gpio_readl(GPIO_A, IDR);
250
+ /* 15: AF, 14: AF, 13: AF, 12: Analog ... */
251
+ /* here AF is the same as Analog and Input mode */
252
+ g_assert_cmphex(moder, ==, reset(GPIO_A, MODER));
253
+ g_assert_cmphex(odr, ==, reset(GPIO_A, ODR));
254
+ g_assert_cmphex(otyper, ==, reset(GPIO_A, OTYPER));
255
+ /* 15: pull-up, 14: pull-down, 13: pull-up, 12: neither ... */
256
+ g_assert_cmphex(pupdr, ==, reset(GPIO_A, PUPDR));
257
+ /* 15 : 1, 14: 0, 13: 1, 12 : reset value ... */
258
+ g_assert_cmphex(idr, ==, reset(GPIO_A, IDR));
259
+
260
+ moder = gpio_readl(GPIO_B, MODER);
261
+ odr = gpio_readl(GPIO_B, ODR);
262
+ otyper = gpio_readl(GPIO_B, OTYPER);
263
+ pupdr = gpio_readl(GPIO_B, PUPDR);
264
+ idr = gpio_readl(GPIO_B, IDR);
265
+ /* ... 5: Analog, 4: AF, 3: AF, 2: Analog ... */
266
+ /* here AF is the same as Analog and Input mode */
267
+ g_assert_cmphex(moder, ==, reset(GPIO_B, MODER));
268
+ g_assert_cmphex(odr, ==, reset(GPIO_B, ODR));
269
+ g_assert_cmphex(otyper, ==, reset(GPIO_B, OTYPER));
270
+ /* ... 5: neither, 4: pull-up, 3: neither ... */
271
+ g_assert_cmphex(pupdr, ==, reset(GPIO_B, PUPDR));
272
+ /* ... 5 : reset value, 4 : 1, 3 : reset value ... */
273
+ g_assert_cmphex(idr, ==, reset(GPIO_B, IDR));
274
+
275
+ moder = gpio_readl(GPIO_C, MODER);
276
+ odr = gpio_readl(GPIO_C, ODR);
277
+ otyper = gpio_readl(GPIO_C, OTYPER);
278
+ pupdr = gpio_readl(GPIO_C, PUPDR);
279
+ idr = gpio_readl(GPIO_C, IDR);
280
+ /* Analog, same as Input mode*/
281
+ g_assert_cmphex(moder, ==, reset(GPIO_C, MODER));
282
+ g_assert_cmphex(odr, ==, reset(GPIO_C, ODR));
283
+ g_assert_cmphex(otyper, ==, reset(GPIO_C, OTYPER));
284
+ /* no pull-up or pull-down */
285
+ g_assert_cmphex(pupdr, ==, reset(GPIO_C, PUPDR));
286
+ /* reset value */
287
+ g_assert_cmphex(idr, ==, reset(GPIO_C, IDR));
288
+
289
+ moder = gpio_readl(GPIO_H, MODER);
290
+ odr = gpio_readl(GPIO_H, ODR);
291
+ otyper = gpio_readl(GPIO_H, OTYPER);
292
+ pupdr = gpio_readl(GPIO_H, PUPDR);
293
+ idr = gpio_readl(GPIO_H, IDR);
294
+ /* Analog, same as Input mode */
295
+ g_assert_cmphex(moder, ==, reset(GPIO_H, MODER));
296
+ g_assert_cmphex(odr, ==, reset(GPIO_H, ODR));
297
+ g_assert_cmphex(otyper, ==, reset(GPIO_H, OTYPER));
298
+ /* no pull-up or pull-down */
299
+ g_assert_cmphex(pupdr, ==, reset(GPIO_H, PUPDR));
300
+ /* reset value */
301
+ g_assert_cmphex(idr, ==, reset(GPIO_H, IDR));
302
+}
303
+
304
+static void test_gpio_output_mode(const void *data)
305
+{
306
+ /*
307
+ * Checks that setting a bit in ODR sets the corresponding
308
+ * GPIO line high : it should set the right bit in IDR
309
+ * and send an irq to syscfg.
310
+ * Additionally, it checks that values written to ODR
311
+ * when not in output mode are stored and not discarded.
312
+ */
313
+ unsigned int pin = ((uint64_t)data) & 0xF;
314
+ uint32_t gpio = ((uint64_t)data) >> 32;
315
+ unsigned int gpio_id = get_gpio_id(gpio);
316
+
317
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
318
+
319
+ /* Set a bit in ODR and check nothing happens */
320
+ gpio_set_bit(gpio, ODR, pin, 1);
321
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
322
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
323
+
324
+ /* Configure the relevant line as output and check the pin is high */
325
+ gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
326
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
327
+ g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
328
+
329
+ /* Reset the bit in ODR and check the pin is low */
330
+ gpio_set_bit(gpio, ODR, pin, 0);
331
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
332
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
333
+
334
+ /* Clean the test */
335
+ gpio_writel(gpio, ODR, reset(gpio, ODR));
336
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
337
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
338
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
339
+}
340
+
341
+static void test_gpio_input_mode(const void *data)
342
+{
343
+ /*
344
+ * Test that setting a line high/low externally sets the
345
+ * corresponding GPIO line high/low : it should set the
346
+ * right bit in IDR and send an irq to syscfg.
347
+ */
348
+ unsigned int pin = ((uint64_t)data) & 0xF;
349
+ uint32_t gpio = ((uint64_t)data) >> 32;
350
+ unsigned int gpio_id = get_gpio_id(gpio);
351
+
352
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
353
+
354
+ /* Configure a line as input, raise it, and check that the pin is high */
355
+ gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
356
+ gpio_set_irq(gpio, pin, 1);
357
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
358
+ g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
359
+
360
+ /* Lower the line and check that the pin is low */
361
+ gpio_set_irq(gpio, pin, 0);
362
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
363
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
364
+
365
+ /* Clean the test */
366
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
367
+ disconnect_all_pins(gpio);
368
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
369
+}
370
+
371
+static void test_pull_up_pull_down(const void *data)
372
+{
373
+ /*
374
+ * Test that a floating pin with pull-up sets the pin
375
+ * high and vice-versa.
376
+ */
377
+ unsigned int pin = ((uint64_t)data) & 0xF;
378
+ uint32_t gpio = ((uint64_t)data) >> 32;
379
+ unsigned int gpio_id = get_gpio_id(gpio);
380
+
381
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
382
+
383
+ /* Configure a line as input with pull-up, check the line is set high */
384
+ gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
385
+ gpio_set_2bits(gpio, PUPDR, pin, PUPDR_PULLUP);
386
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
387
+ g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
388
+
389
+ /* Configure the line with pull-down, check the line is low */
390
+ gpio_set_2bits(gpio, PUPDR, pin, PUPDR_PULLDOWN);
391
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
392
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
393
+
394
+ /* Clean the test */
395
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
396
+ gpio_writel(gpio, PUPDR, reset(gpio, PUPDR));
397
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
398
+}
399
+
400
+static void test_push_pull(const void *data)
401
+{
402
+ /*
403
+ * Test that configuring a line in push-pull output mode
404
+ * disconnects the pin, that the pin can't be set or reset
405
+ * externally afterwards.
406
+ */
407
+ unsigned int pin = ((uint64_t)data) & 0xF;
408
+ uint32_t gpio = ((uint64_t)data) >> 32;
409
+ uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
410
+
411
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
412
+
413
+ /* Setting a line high externally, configuring it in push-pull output */
414
+ /* And checking the pin was disconnected */
415
+ gpio_set_irq(gpio, pin, 1);
416
+ gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
417
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
418
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
419
+
420
+ /* Setting a line low externally, configuring it in push-pull output */
421
+ /* And checking the pin was disconnected */
422
+ gpio_set_irq(gpio2, pin, 0);
423
+ gpio_set_bit(gpio2, ODR, pin, 1);
424
+ gpio_set_2bits(gpio2, MODER, pin, MODER_OUTPUT);
425
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF);
426
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR) | (1 << pin));
427
+
428
+ /* Trying to set a push-pull output pin, checking it doesn't work */
429
+ gpio_set_irq(gpio, pin, 1);
430
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
431
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
432
+
433
+ /* Trying to reset a push-pull output pin, checking it doesn't work */
434
+ gpio_set_irq(gpio2, pin, 0);
435
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF);
436
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR) | (1 << pin));
437
+
438
+ /* Clean the test */
439
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
440
+ gpio_writel(gpio2, ODR, reset(gpio2, ODR));
441
+ gpio_writel(gpio2, MODER, reset(gpio2, MODER));
442
+}
443
+
444
+static void test_open_drain(const void *data)
445
+{
446
+ /*
447
+ * Test that configuring a line in open-drain output mode
448
+ * disconnects a pin set high externally and that the pin
449
+ * can't be set high externally while configured in open-drain.
450
+ *
451
+ * However a pin set low externally shouldn't be disconnected,
452
+ * and it can be set low externally when in open-drain mode.
453
+ */
454
+ unsigned int pin = ((uint64_t)data) & 0xF;
455
+ uint32_t gpio = ((uint64_t)data) >> 32;
456
+ uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
457
+
458
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
459
+
460
+ /* Setting a line high externally, configuring it in open-drain output */
461
+ /* And checking the pin was disconnected */
462
+ gpio_set_irq(gpio, pin, 1);
463
+ gpio_set_bit(gpio, OTYPER, pin, OTYPER_OPEN_DRAIN);
464
+ gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
465
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
466
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
467
+
468
+ /* Setting a line low externally, configuring it in open-drain output */
469
+ /* And checking the pin wasn't disconnected */
470
+ gpio_set_irq(gpio2, pin, 0);
471
+ gpio_set_bit(gpio2, ODR, pin, 1);
472
+ gpio_set_bit(gpio2, OTYPER, pin, OTYPER_OPEN_DRAIN);
473
+ gpio_set_2bits(gpio2, MODER, pin, MODER_OUTPUT);
474
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF & ~(1 << pin));
475
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==,
476
+ reset(gpio2, IDR) & ~(1 << pin));
477
+
478
+ /* Trying to set a open-drain output pin, checking it doesn't work */
479
+ gpio_set_irq(gpio, pin, 1);
480
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
481
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
482
+
483
+ /* Trying to reset a open-drain output pin, checking it works */
484
+ gpio_set_bit(gpio, ODR, pin, 1);
485
+ gpio_set_irq(gpio, pin, 0);
486
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF & ~(1 << pin));
487
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==,
488
+ reset(gpio2, IDR) & ~(1 << pin));
489
+
490
+ /* Clean the test */
491
+ disconnect_all_pins(gpio2);
492
+ gpio_writel(gpio2, OTYPER, reset(gpio2, OTYPER));
493
+ gpio_writel(gpio2, ODR, reset(gpio2, ODR));
494
+ gpio_writel(gpio2, MODER, reset(gpio2, MODER));
495
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR));
496
+ disconnect_all_pins(gpio);
497
+ gpio_writel(gpio, OTYPER, reset(gpio, OTYPER));
498
+ gpio_writel(gpio, ODR, reset(gpio, ODR));
499
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
500
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
501
+}
502
+
503
+static void test_bsrr_brr(const void *data)
504
+{
505
+ /*
506
+ * Test that writing a '1' in BSS and BSRR
507
+ * has the desired effect on ODR.
508
+ * In BSRR, BSx has priority over BRx.
509
+ */
510
+ unsigned int pin = ((uint64_t)data) & 0xF;
511
+ uint32_t gpio = ((uint64_t)data) >> 32;
512
+
513
+ gpio_writel(gpio, BSRR, (1 << pin));
514
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
515
+
516
+ gpio_writel(gpio, BSRR, (1 << (pin + NUM_GPIO_PINS)));
517
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
518
+
519
+ gpio_writel(gpio, BSRR, (1 << pin));
520
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
521
+
522
+ gpio_writel(gpio, BRR, (1 << pin));
523
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
524
+
525
+ /* BSx should have priority over BRx */
526
+ gpio_writel(gpio, BSRR, (1 << pin) | (1 << (pin + NUM_GPIO_PINS)));
527
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
528
+
529
+ gpio_writel(gpio, BRR, (1 << pin));
530
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
531
+
532
+ gpio_writel(gpio, ODR, reset(gpio, ODR));
533
+}
534
+
535
+int main(int argc, char **argv)
536
+{
537
+ int ret;
538
+
539
+ g_test_init(&argc, &argv, NULL);
540
+ g_test_set_nonfatal_assertions();
541
+ qtest_add_func("stm32l4x5/gpio/test_idr_reset_value",
542
+ test_idr_reset_value);
543
+ /*
544
+ * The inputs for the tests (gpio and pin) can be changed,
545
+ * but the tests don't work for pins that are high at reset
546
+ * (GPIOA15, GPIO13 and GPIOB5).
547
+ * Specifically, rising the pin then checking `get_irq()`
548
+ * is problematic since the pin was already high.
549
+ */
550
+ qtest_add_data_func("stm32l4x5/gpio/test_gpioc5_output_mode",
551
+ (void *)((uint64_t)GPIO_C << 32 | 5),
552
+ test_gpio_output_mode);
553
+ qtest_add_data_func("stm32l4x5/gpio/test_gpioh3_output_mode",
554
+ (void *)((uint64_t)GPIO_H << 32 | 3),
555
+ test_gpio_output_mode);
556
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode1",
557
+ (void *)((uint64_t)GPIO_D << 32 | 6),
558
+ test_gpio_input_mode);
559
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode2",
560
+ (void *)((uint64_t)GPIO_C << 32 | 10),
561
+ test_gpio_input_mode);
562
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down1",
563
+ (void *)((uint64_t)GPIO_B << 32 | 5),
564
+ test_pull_up_pull_down);
565
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down2",
566
+ (void *)((uint64_t)GPIO_F << 32 | 1),
567
+ test_pull_up_pull_down);
568
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull1",
569
+ (void *)((uint64_t)GPIO_G << 32 | 6),
570
+ test_push_pull);
571
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull2",
572
+ (void *)((uint64_t)GPIO_H << 32 | 3),
573
+ test_push_pull);
574
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain1",
575
+ (void *)((uint64_t)GPIO_C << 32 | 4),
576
+ test_open_drain);
577
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain2",
578
+ (void *)((uint64_t)GPIO_E << 32 | 11),
579
+ test_open_drain);
580
+ qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr1",
581
+ (void *)((uint64_t)GPIO_A << 32 | 12),
582
+ test_bsrr_brr);
583
+ qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr2",
584
+ (void *)((uint64_t)GPIO_D << 32 | 0),
585
+ test_bsrr_brr);
586
+
587
+ qtest_start("-machine b-l475e-iot01a");
588
+ ret = g_test_run();
589
+ qtest_end();
590
+
591
+ return ret;
592
+}
593
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
53
index XXXXXXX..XXXXXXX 100644
594
index XXXXXXX..XXXXXXX 100644
54
--- a/docs/system/target-arm.rst
595
--- a/tests/qtest/meson.build
55
+++ b/docs/system/target-arm.rst
596
+++ b/tests/qtest/meson.build
56
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
597
@@ -XXX,XX +XXX,XX @@ qtests_aspeed = \
57
598
qtests_stm32l4x5 = \
58
arm/integratorcp
599
['stm32l4x5_exti-test',
59
arm/mps2
600
'stm32l4x5_syscfg-test',
60
+ arm/musca
601
- 'stm32l4x5_rcc-test']
61
arm/realview
602
+ 'stm32l4x5_rcc-test',
62
arm/versatile
603
+ 'stm32l4x5_gpio-test']
63
arm/vexpress
604
64
diff --git a/MAINTAINERS b/MAINTAINERS
605
qtests_arm = \
65
index XXXXXXX..XXXXXXX 100644
606
(config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \
66
--- a/MAINTAINERS
67
+++ b/MAINTAINERS
68
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
69
L: qemu-arm@nongnu.org
70
S: Maintained
71
F: hw/arm/musca.c
72
+F: docs/system/arm/musca.rst
73
74
Musicpal
75
M: Jan Kiszka <jan.kiszka@web.de>
76
--
607
--
77
2.20.1
608
2.34.1
78
609
79
610
diff view generated by jsdifflib
[PULL 26/29] target/arm: Use clear_vec_high more effectively
[PULL 12/14] target/arm: Fix 32-bit SMOPA
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Do not explicitly store zero to the NEON high part
3
While the 8-bit input elements are sequential in the input vector,
4
when we can pass !is_q to clear_vec_high.
4
the 32-bit output elements are not sequential in the output matrix.
5
5
Do not attempt to compute 2 32-bit outputs at the same time.
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
7
Cc: qemu-stable@nongnu.org
8
Fixes: 23a5e3859f5 ("target/arm: Implement SME integer outer product")
9
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2083
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200519212453.28494-3-richard.henderson@linaro.org
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Message-id: 20240305163931.242795-1-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
14
---
11
target/arm/translate-a64.c | 53 +++++++++++++++++++++++---------------
15
target/arm/tcg/sme_helper.c | 77 ++++++++++++++++++-------------
12
1 file changed, 32 insertions(+), 21 deletions(-)
16
tests/tcg/aarch64/sme-smopa-1.c | 47 +++++++++++++++++++
13
17
tests/tcg/aarch64/sme-smopa-2.c | 54 ++++++++++++++++++++++
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
18
tests/tcg/aarch64/Makefile.target | 2 +-
19
4 files changed, 147 insertions(+), 33 deletions(-)
20
create mode 100644 tests/tcg/aarch64/sme-smopa-1.c
21
create mode 100644 tests/tcg/aarch64/sme-smopa-2.c
22
23
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
15
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
25
--- a/target/arm/tcg/sme_helper.c
17
+++ b/target/arm/translate-a64.c
26
+++ b/target/arm/tcg/sme_helper.c
18
@@ -XXX,XX +XXX,XX @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
27
@@ -XXX,XX +XXX,XX @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn,
28
}
29
}
30
31
-typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool);
32
+typedef uint32_t IMOPFn32(uint32_t, uint32_t, uint32_t, uint8_t, bool);
33
+static inline void do_imopa_s(uint32_t *za, uint32_t *zn, uint32_t *zm,
34
+ uint8_t *pn, uint8_t *pm,
35
+ uint32_t desc, IMOPFn32 *fn)
36
+{
37
+ intptr_t row, col, oprsz = simd_oprsz(desc) / 4;
38
+ bool neg = simd_data(desc);
39
40
-static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm,
41
- uint8_t *pn, uint8_t *pm,
42
- uint32_t desc, IMOPFn *fn)
43
+ for (row = 0; row < oprsz; ++row) {
44
+ uint8_t pa = (pn[H1(row >> 1)] >> ((row & 1) * 4)) & 0xf;
45
+ uint32_t *za_row = &za[tile_vslice_index(row)];
46
+ uint32_t n = zn[H4(row)];
47
+
48
+ for (col = 0; col < oprsz; ++col) {
49
+ uint8_t pb = pm[H1(col >> 1)] >> ((col & 1) * 4);
50
+ uint32_t *a = &za_row[H4(col)];
51
+
52
+ *a = fn(n, zm[H4(col)], *a, pa & pb, neg);
53
+ }
54
+ }
55
+}
56
+
57
+typedef uint64_t IMOPFn64(uint64_t, uint64_t, uint64_t, uint8_t, bool);
58
+static inline void do_imopa_d(uint64_t *za, uint64_t *zn, uint64_t *zm,
59
+ uint8_t *pn, uint8_t *pm,
60
+ uint32_t desc, IMOPFn64 *fn)
19
{
61
{
20
/* This always zero-extends and writes to a full 128 bit wide vector */
62
intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
21
TCGv_i64 tmplo = tcg_temp_new_i64();
63
bool neg = simd_data(desc);
22
- TCGv_i64 tmphi;
64
@@ -XXX,XX +XXX,XX @@ static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm,
23
+ TCGv_i64 tmphi = NULL;
24
25
if (size < 4) {
26
MemOp memop = s->be_data + size;
27
- tmphi = tcg_const_i64(0);
28
tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop);
29
} else {
30
bool be = s->be_data == MO_BE;
31
@@ -XXX,XX +XXX,XX @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
32
}
33
34
tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64));
35
- tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx));
36
-
37
tcg_temp_free_i64(tmplo);
38
- tcg_temp_free_i64(tmphi);
39
40
- clear_vec_high(s, true, destidx);
41
+ if (tmphi) {
42
+ tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx));
43
+ tcg_temp_free_i64(tmphi);
44
+ }
45
+ clear_vec_high(s, tmphi != NULL, destidx);
46
}
65
}
47
66
48
/*
67
#define DEF_IMOP_32(NAME, NTYPE, MTYPE) \
49
@@ -XXX,XX +XXX,XX @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
68
-static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \
50
read_vec_element(s, tcg_resh, rm, 0, MO_64);
69
+static uint32_t NAME(uint32_t n, uint32_t m, uint32_t a, uint8_t p, bool neg) \
51
do_ext64(s, tcg_resh, tcg_resl, pos);
70
{ \
52
}
71
- uint32_t sum0 = 0, sum1 = 0; \
53
- tcg_gen_movi_i64(tcg_resh, 0);
72
+ uint32_t sum = 0; \
54
} else {
73
/* Apply P to N as a mask, making the inactive elements 0. */ \
55
TCGv_i64 tcg_hh;
74
n &= expand_pred_b(p); \
56
typedef struct {
75
- sum0 += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \
57
@@ -XXX,XX +XXX,XX @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
76
- sum0 += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \
58
77
- sum0 += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \
59
write_vec_element(s, tcg_resl, rd, 0, MO_64);
78
- sum0 += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \
60
tcg_temp_free_i64(tcg_resl);
79
- sum1 += (NTYPE)(n >> 32) * (MTYPE)(m >> 32); \
61
- write_vec_element(s, tcg_resh, rd, 1, MO_64);
80
- sum1 += (NTYPE)(n >> 40) * (MTYPE)(m >> 40); \
62
+ if (is_q) {
81
- sum1 += (NTYPE)(n >> 48) * (MTYPE)(m >> 48); \
63
+ write_vec_element(s, tcg_resh, rd, 1, MO_64);
82
- sum1 += (NTYPE)(n >> 56) * (MTYPE)(m >> 56); \
64
+ }
83
- if (neg) { \
65
tcg_temp_free_i64(tcg_resh);
84
- sum0 = (uint32_t)a - sum0, sum1 = (uint32_t)(a >> 32) - sum1; \
66
- clear_vec_high(s, true, rd);
85
- } else { \
67
+ clear_vec_high(s, is_q, rd);
86
- sum0 = (uint32_t)a + sum0, sum1 = (uint32_t)(a >> 32) + sum1; \
87
- } \
88
- return ((uint64_t)sum1 << 32) | sum0; \
89
+ sum += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \
90
+ sum += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \
91
+ sum += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \
92
+ sum += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \
93
+ return neg ? a - sum : a + sum; \
68
}
94
}
69
95
70
/* TBL/TBX
96
#define DEF_IMOP_64(NAME, NTYPE, MTYPE) \
71
@@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
97
@@ -XXX,XX +XXX,XX @@ DEF_IMOP_64(umopa_d, uint16_t, uint16_t)
72
* the input.
98
DEF_IMOP_64(sumopa_d, int16_t, uint16_t)
73
*/
99
DEF_IMOP_64(usmopa_d, uint16_t, int16_t)
74
tcg_resl = tcg_temp_new_i64();
100
75
- tcg_resh = tcg_temp_new_i64();
101
-#define DEF_IMOPH(NAME) \
76
+ tcg_resh = NULL;
102
- void HELPER(sme_##NAME)(void *vza, void *vzn, void *vzm, void *vpn, \
77
103
- void *vpm, uint32_t desc) \
78
if (is_tblx) {
104
- { do_imopa(vza, vzn, vzm, vpn, vpm, desc, NAME); }
79
read_vec_element(s, tcg_resl, rd, 0, MO_64);
105
+#define DEF_IMOPH(NAME, S) \
80
} else {
106
+ void HELPER(sme_##NAME##_##S)(void *vza, void *vzn, void *vzm, \
81
tcg_gen_movi_i64(tcg_resl, 0);
107
+ void *vpn, void *vpm, uint32_t desc) \
82
}
108
+ { do_imopa_##S(vza, vzn, vzm, vpn, vpm, desc, NAME##_##S); }
83
- if (is_tblx && is_q) {
109
84
- read_vec_element(s, tcg_resh, rd, 1, MO_64);
110
-DEF_IMOPH(smopa_s)
85
- } else {
111
-DEF_IMOPH(umopa_s)
86
- tcg_gen_movi_i64(tcg_resh, 0);
112
-DEF_IMOPH(sumopa_s)
87
+
113
-DEF_IMOPH(usmopa_s)
88
+ if (is_q) {
114
-DEF_IMOPH(smopa_d)
89
+ tcg_resh = tcg_temp_new_i64();
115
-DEF_IMOPH(umopa_d)
90
+ if (is_tblx) {
116
-DEF_IMOPH(sumopa_d)
91
+ read_vec_element(s, tcg_resh, rd, 1, MO_64);
117
-DEF_IMOPH(usmopa_d)
92
+ } else {
118
+DEF_IMOPH(smopa, s)
93
+ tcg_gen_movi_i64(tcg_resh, 0);
119
+DEF_IMOPH(umopa, s)
120
+DEF_IMOPH(sumopa, s)
121
+DEF_IMOPH(usmopa, s)
122
+
123
+DEF_IMOPH(smopa, d)
124
+DEF_IMOPH(umopa, d)
125
+DEF_IMOPH(sumopa, d)
126
+DEF_IMOPH(usmopa, d)
127
diff --git a/tests/tcg/aarch64/sme-smopa-1.c b/tests/tcg/aarch64/sme-smopa-1.c
128
new file mode 100644
129
index XXXXXXX..XXXXXXX
130
--- /dev/null
131
+++ b/tests/tcg/aarch64/sme-smopa-1.c
132
@@ -XXX,XX +XXX,XX @@
133
+#include <stdio.h>
134
+#include <string.h>
135
+
136
+int main()
137
+{
138
+ static const int cmp[4][4] = {
139
+ { 110, 134, 158, 182 },
140
+ { 390, 478, 566, 654 },
141
+ { 670, 822, 974, 1126 },
142
+ { 950, 1166, 1382, 1598 }
143
+ };
144
+ int dst[4][4];
145
+ int *tmp = &dst[0][0];
146
+
147
+ asm volatile(
148
+ ".arch armv8-r+sme\n\t"
149
+ "smstart\n\t"
150
+ "index z0.b, #0, #1\n\t"
151
+ "movprfx z1, z0\n\t"
152
+ "add z1.b, z1.b, #16\n\t"
153
+ "ptrue p0.b\n\t"
154
+ "smopa za0.s, p0/m, p0/m, z0.b, z1.b\n\t"
155
+ "ptrue p0.s, vl4\n\t"
156
+ "mov w12, #0\n\t"
157
+ "st1w { za0h.s[w12, #0] }, p0, [%0]\n\t"
158
+ "add %0, %0, #16\n\t"
159
+ "st1w { za0h.s[w12, #1] }, p0, [%0]\n\t"
160
+ "add %0, %0, #16\n\t"
161
+ "st1w { za0h.s[w12, #2] }, p0, [%0]\n\t"
162
+ "add %0, %0, #16\n\t"
163
+ "st1w { za0h.s[w12, #3] }, p0, [%0]\n\t"
164
+ "smstop"
165
+ : "+r"(tmp) : : "memory");
166
+
167
+ if (memcmp(cmp, dst, sizeof(dst)) == 0) {
168
+ return 0;
169
+ }
170
+
171
+ /* See above for correct results. */
172
+ for (int i = 0; i < 4; ++i) {
173
+ for (int j = 0; j < 4; ++j) {
174
+ printf("%6d", dst[i][j]);
94
+ }
175
+ }
95
}
176
+ printf("\n");
96
177
+ }
97
tcg_idx = tcg_temp_new_i64();
178
+ return 1;
98
@@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
179
+}
99
180
diff --git a/tests/tcg/aarch64/sme-smopa-2.c b/tests/tcg/aarch64/sme-smopa-2.c
100
write_vec_element(s, tcg_resl, rd, 0, MO_64);
181
new file mode 100644
101
tcg_temp_free_i64(tcg_resl);
182
index XXXXXXX..XXXXXXX
102
- write_vec_element(s, tcg_resh, rd, 1, MO_64);
183
--- /dev/null
103
- tcg_temp_free_i64(tcg_resh);
184
+++ b/tests/tcg/aarch64/sme-smopa-2.c
104
- clear_vec_high(s, true, rd);
185
@@ -XXX,XX +XXX,XX @@
105
+
186
+#include <stdio.h>
106
+ if (is_q) {
187
+#include <string.h>
107
+ write_vec_element(s, tcg_resh, rd, 1, MO_64);
188
+
108
+ tcg_temp_free_i64(tcg_resh);
189
+int main()
109
+ }
190
+{
110
+ clear_vec_high(s, is_q, rd);
191
+ static const long cmp[4][4] = {
111
}
192
+ { 110, 134, 158, 182 },
112
193
+ { 390, 478, 566, 654 },
113
/* ZIP/UZP/TRN
194
+ { 670, 822, 974, 1126 },
114
@@ -XXX,XX +XXX,XX @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
195
+ { 950, 1166, 1382, 1598 }
115
}
196
+ };
116
197
+ long dst[4][4];
117
tcg_resl = tcg_const_i64(0);
198
+ long *tmp = &dst[0][0];
118
- tcg_resh = tcg_const_i64(0);
199
+ long svl;
119
+ tcg_resh = is_q ? tcg_const_i64(0) : NULL;
200
+
120
tcg_res = tcg_temp_new_i64();
201
+ /* Validate that we have a wide enough vector for 4 elements. */
121
202
+ asm(".arch armv8-r+sme-i64\n\trdsvl %0, #1" : "=r"(svl));
122
for (i = 0; i < elements; i++) {
203
+ if (svl < 32) {
123
@@ -XXX,XX +XXX,XX @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
204
+ return 0;
124
205
+ }
125
write_vec_element(s, tcg_resl, rd, 0, MO_64);
206
+
126
tcg_temp_free_i64(tcg_resl);
207
+ asm volatile(
127
- write_vec_element(s, tcg_resh, rd, 1, MO_64);
208
+ "smstart\n\t"
128
- tcg_temp_free_i64(tcg_resh);
209
+ "index z0.h, #0, #1\n\t"
129
- clear_vec_high(s, true, rd);
210
+ "movprfx z1, z0\n\t"
130
+
211
+ "add z1.h, z1.h, #16\n\t"
131
+ if (is_q) {
212
+ "ptrue p0.b\n\t"
132
+ write_vec_element(s, tcg_resh, rd, 1, MO_64);
213
+ "smopa za0.d, p0/m, p0/m, z0.h, z1.h\n\t"
133
+ tcg_temp_free_i64(tcg_resh);
214
+ "ptrue p0.d, vl4\n\t"
134
+ }
215
+ "mov w12, #0\n\t"
135
+ clear_vec_high(s, is_q, rd);
216
+ "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t"
136
}
217
+ "add %0, %0, #32\n\t"
137
218
+ "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t"
138
/*
219
+ "mov w12, #2\n\t"
220
+ "add %0, %0, #32\n\t"
221
+ "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t"
222
+ "add %0, %0, #32\n\t"
223
+ "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t"
224
+ "smstop"
225
+ : "+r"(tmp) : : "memory");
226
+
227
+ if (memcmp(cmp, dst, sizeof(dst)) == 0) {
228
+ return 0;
229
+ }
230
+
231
+ /* See above for correct results. */
232
+ for (int i = 0; i < 4; ++i) {
233
+ for (int j = 0; j < 4; ++j) {
234
+ printf("%6ld", dst[i][j]);
235
+ }
236
+ printf("\n");
237
+ }
238
+ return 1;
239
+}
240
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
241
index XXXXXXX..XXXXXXX 100644
242
--- a/tests/tcg/aarch64/Makefile.target
243
+++ b/tests/tcg/aarch64/Makefile.target
244
@@ -XXX,XX +XXX,XX @@ endif
245
246
# SME Tests
247
ifneq ($(CROSS_AS_HAS_ARMV9_SME),)
248
-AARCH64_TESTS += sme-outprod1
249
+AARCH64_TESTS += sme-outprod1 sme-smopa-1 sme-smopa-2
250
endif
251
252
# System Registers Tests
139
--
253
--
140
2.20.1
254
2.34.1
141
255
142
256
diff view generated by jsdifflib
[PULL 22/29] hw/char/xilinx_uartlite: Replace hw_error() by qemu_log_mask()
[PULL 13/14] hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
The sun4v RTC device model added under commit a0e893039cf2ce0 in 2016
2
was unfortunately added with a license of GPL-v3-or-later, which is
3
not compatible with other QEMU code which has a GPL-v2-only license.
2
4
3
hw_error() calls exit(). This a bit overkill when we can log
5
Relicense the code in the .c and the .h file to GPL-v2-or-later,
4
the accesses as unimplemented or guest error.
6
to make it compatible with the rest of QEMU.
5
7
6
When fuzzing the devices, we don't want the whole process to
8
Cc: qemu-stable@nongnu.org
7
exit. Replace some hw_error() calls by qemu_log_mask().
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
10
Signed-off-by: Paolo Bonzini (for Red Hat) <pbonzini@redhat.com>
9
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
11
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
10
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Signed-off-by: Markus Armbruster <armbru@redhat.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 20200518140309.5220-4-f4bug@amsat.org
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
15
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
16
Acked-by: Alex Bennée <alex.bennee@linaro.org>
17
Message-id: 20240223161300.938542-1-peter.maydell@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
19
---
15
hw/char/xilinx_uartlite.c | 5 +++--
20
include/hw/rtc/sun4v-rtc.h | 2 +-
16
1 file changed, 3 insertions(+), 2 deletions(-)
21
hw/rtc/sun4v-rtc.c | 2 +-
22
2 files changed, 2 insertions(+), 2 deletions(-)
17
23
18
diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c
24
diff --git a/include/hw/rtc/sun4v-rtc.h b/include/hw/rtc/sun4v-rtc.h
19
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/char/xilinx_uartlite.c
26
--- a/include/hw/rtc/sun4v-rtc.h
21
+++ b/hw/char/xilinx_uartlite.c
27
+++ b/include/hw/rtc/sun4v-rtc.h
22
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@
29
*
30
* Copyright (c) 2016 Artyom Tarasenko
31
*
32
- * This code is licensed under the GNU GPL v3 or (at your option) any later
33
+ * This code is licensed under the GNU GPL v2 or (at your option) any later
34
* version.
23
*/
35
*/
24
36
25
#include "qemu/osdep.h"
37
diff --git a/hw/rtc/sun4v-rtc.c b/hw/rtc/sun4v-rtc.c
26
-#include "hw/hw.h"
38
index XXXXXXX..XXXXXXX 100644
27
+#include "qemu/log.h"
39
--- a/hw/rtc/sun4v-rtc.c
28
#include "hw/irq.h"
40
+++ b/hw/rtc/sun4v-rtc.c
29
#include "hw/qdev-properties.h"
41
@@ -XXX,XX +XXX,XX @@
30
#include "hw/sysbus.h"
42
*
31
@@ -XXX,XX +XXX,XX @@ uart_write(void *opaque, hwaddr addr,
43
* Copyright (c) 2016 Artyom Tarasenko
32
switch (addr)
44
*
33
{
45
- * This code is licensed under the GNU GPL v3 or (at your option) any later
34
case R_STATUS:
46
+ * This code is licensed under the GNU GPL v2 or (at your option) any later
35
- hw_error("write to UART STATUS?\n");
47
* version.
36
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: write to UART STATUS\n",
48
*/
37
+ __func__);
49
38
break;
39
40
case R_CTRL:
41
--
50
--
42
2.20.1
51
2.34.1
43
52
44
53
diff view generated by jsdifflib
[PULL 01/29] tests/acceptance: Add a test for the canon-a1100 machine
[PULL 14/14] target/arm: Move v7m-related code from cpu32.c into a separate file
1
From: Thomas Huth <thuth@redhat.com>
1
From: Thomas Huth <thuth@redhat.com>
2
2
3
The canon-a1100 machine can be used with the Barebox firmware. The
3
Move the code to a separate file so that we do not have to compile
4
QEMU Advent Calendar 2018 features a pre-compiled image which we
4
it anymore if CONFIG_ARM_V7M is not set.
5
can use for testing.
6
5
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
10
Tested-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
11
Signed-off-by: Thomas Huth <thuth@redhat.com>
6
Signed-off-by: Thomas Huth <thuth@redhat.com>
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20240308141051.536599-2-thuth@redhat.com
13
Message-id: 20200514190422.23645-1-f4bug@amsat.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-Id: <20200129090420.13954-1-thuth@redhat.com>
15
[PMD: Rebased MAINTAINERS]
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
10
---
19
MAINTAINERS | 1 +
11
target/arm/tcg/cpu-v7m.c | 290 +++++++++++++++++++++++++++++++++++++
20
tests/acceptance/machine_arm_canona1100.py | 35 ++++++++++++++++++++++
12
target/arm/tcg/cpu32.c | 261 ---------------------------------
21
2 files changed, 36 insertions(+)
13
target/arm/meson.build | 3 +
22
create mode 100644 tests/acceptance/machine_arm_canona1100.py
14
target/arm/tcg/meson.build | 3 +
15
4 files changed, 296 insertions(+), 261 deletions(-)
16
create mode 100644 target/arm/tcg/cpu-v7m.c
23
17
24
diff --git a/MAINTAINERS b/MAINTAINERS
18
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/MAINTAINERS
27
+++ b/MAINTAINERS
28
@@ -XXX,XX +XXX,XX @@ S: Odd Fixes
29
F: include/hw/arm/digic.h
30
F: hw/*/digic*
31
F: include/hw/*/digic*
32
+F: tests/acceptance/machine_arm_canona1100.py
33
34
Goldfish RTC
35
M: Anup Patel <anup.patel@wdc.com>
36
diff --git a/tests/acceptance/machine_arm_canona1100.py b/tests/acceptance/machine_arm_canona1100.py
37
new file mode 100644
19
new file mode 100644
38
index XXXXXXX..XXXXXXX
20
index XXXXXXX..XXXXXXX
39
--- /dev/null
21
--- /dev/null
40
+++ b/tests/acceptance/machine_arm_canona1100.py
22
+++ b/target/arm/tcg/cpu-v7m.c
41
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@
42
+# Functional test that boots the canon-a1100 machine with firmware
24
+/*
43
+#
25
+ * QEMU ARMv7-M TCG-only CPUs.
44
+# Copyright (c) 2020 Red Hat, Inc.
26
+ *
45
+#
27
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
46
+# Author:
28
+ *
47
+# Thomas Huth <thuth@redhat.com>
29
+ * This code is licensed under the GNU GPL v2 or later.
48
+#
30
+ *
49
+# This work is licensed under the terms of the GNU GPL, version 2 or
31
+ * SPDX-License-Identifier: GPL-2.0-or-later
50
+# later. See the COPYING file in the top-level directory.
32
+ */
51
+
33
+
52
+from avocado_qemu import Test
34
+#include "qemu/osdep.h"
53
+from avocado_qemu import wait_for_console_pattern
35
+#include "cpu.h"
54
+from avocado.utils import archive
36
+#include "hw/core/tcg-cpu-ops.h"
55
+
37
+#include "internals.h"
56
+class CanonA1100Machine(Test):
38
+
57
+ """Boots the barebox firmware and checks that the console is operational"""
39
+#if !defined(CONFIG_USER_ONLY)
58
+
40
+
59
+ timeout = 90
41
+#include "hw/intc/armv7m_nvic.h"
60
+
42
+
61
+ def test_arm_canona1100(self):
43
+static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
62
+ """
44
+{
63
+ :avocado: tags=arch:arm
45
+ CPUClass *cc = CPU_GET_CLASS(cs);
64
+ :avocado: tags=machine:canon-a1100
46
+ ARMCPU *cpu = ARM_CPU(cs);
65
+ :avocado: tags=device:pflash_cfi02
47
+ CPUARMState *env = &cpu->env;
66
+ """
48
+ bool ret = false;
67
+ tar_url = ('https://www.qemu-advent-calendar.org'
49
+
68
+ '/2018/download/day18.tar.xz')
50
+ /*
69
+ tar_hash = '068b5fc4242b29381acee94713509f8a876e9db6'
51
+ * ARMv7-M interrupt masking works differently than -A or -R.
70
+ file_path = self.fetch_asset(tar_url, asset_hash=tar_hash)
52
+ * There is no FIQ/IRQ distinction. Instead of I and F bits
71
+ archive.extract(file_path, self.workdir)
53
+ * masking FIQ and IRQ interrupts, an exception is taken only
72
+ self.vm.set_console()
54
+ * if it is higher priority than the current execution priority
73
+ self.vm.add_args('-bios',
55
+ * (which depends on state like BASEPRI, FAULTMASK and the
74
+ self.workdir + '/day18/barebox.canon-a1100.bin')
56
+ * currently active exception).
75
+ self.vm.launch()
57
+ */
76
+ wait_for_console_pattern(self, 'running /env/bin/init')
58
+ if (interrupt_request & CPU_INTERRUPT_HARD
59
+ && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
60
+ cs->exception_index = EXCP_IRQ;
61
+ cc->tcg_ops->do_interrupt(cs);
62
+ ret = true;
63
+ }
64
+ return ret;
65
+}
66
+
67
+#endif /* !CONFIG_USER_ONLY */
68
+
69
+static void cortex_m0_initfn(Object *obj)
70
+{
71
+ ARMCPU *cpu = ARM_CPU(obj);
72
+ set_feature(&cpu->env, ARM_FEATURE_V6);
73
+ set_feature(&cpu->env, ARM_FEATURE_M);
74
+
75
+ cpu->midr = 0x410cc200;
76
+
77
+ /*
78
+ * These ID register values are not guest visible, because
79
+ * we do not implement the Main Extension. They must be set
80
+ * to values corresponding to the Cortex-M0's implemented
81
+ * features, because QEMU generally controls its emulation
82
+ * by looking at ID register fields. We use the same values as
83
+ * for the M3.
84
+ */
85
+ cpu->isar.id_pfr0 = 0x00000030;
86
+ cpu->isar.id_pfr1 = 0x00000200;
87
+ cpu->isar.id_dfr0 = 0x00100000;
88
+ cpu->id_afr0 = 0x00000000;
89
+ cpu->isar.id_mmfr0 = 0x00000030;
90
+ cpu->isar.id_mmfr1 = 0x00000000;
91
+ cpu->isar.id_mmfr2 = 0x00000000;
92
+ cpu->isar.id_mmfr3 = 0x00000000;
93
+ cpu->isar.id_isar0 = 0x01141110;
94
+ cpu->isar.id_isar1 = 0x02111000;
95
+ cpu->isar.id_isar2 = 0x21112231;
96
+ cpu->isar.id_isar3 = 0x01111110;
97
+ cpu->isar.id_isar4 = 0x01310102;
98
+ cpu->isar.id_isar5 = 0x00000000;
99
+ cpu->isar.id_isar6 = 0x00000000;
100
+}
101
+
102
+static void cortex_m3_initfn(Object *obj)
103
+{
104
+ ARMCPU *cpu = ARM_CPU(obj);
105
+ set_feature(&cpu->env, ARM_FEATURE_V7);
106
+ set_feature(&cpu->env, ARM_FEATURE_M);
107
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
108
+ cpu->midr = 0x410fc231;
109
+ cpu->pmsav7_dregion = 8;
110
+ cpu->isar.id_pfr0 = 0x00000030;
111
+ cpu->isar.id_pfr1 = 0x00000200;
112
+ cpu->isar.id_dfr0 = 0x00100000;
113
+ cpu->id_afr0 = 0x00000000;
114
+ cpu->isar.id_mmfr0 = 0x00000030;
115
+ cpu->isar.id_mmfr1 = 0x00000000;
116
+ cpu->isar.id_mmfr2 = 0x00000000;
117
+ cpu->isar.id_mmfr3 = 0x00000000;
118
+ cpu->isar.id_isar0 = 0x01141110;
119
+ cpu->isar.id_isar1 = 0x02111000;
120
+ cpu->isar.id_isar2 = 0x21112231;
121
+ cpu->isar.id_isar3 = 0x01111110;
122
+ cpu->isar.id_isar4 = 0x01310102;
123
+ cpu->isar.id_isar5 = 0x00000000;
124
+ cpu->isar.id_isar6 = 0x00000000;
125
+}
126
+
127
+static void cortex_m4_initfn(Object *obj)
128
+{
129
+ ARMCPU *cpu = ARM_CPU(obj);
130
+
131
+ set_feature(&cpu->env, ARM_FEATURE_V7);
132
+ set_feature(&cpu->env, ARM_FEATURE_M);
133
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
134
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
135
+ cpu->midr = 0x410fc240; /* r0p0 */
136
+ cpu->pmsav7_dregion = 8;
137
+ cpu->isar.mvfr0 = 0x10110021;
138
+ cpu->isar.mvfr1 = 0x11000011;
139
+ cpu->isar.mvfr2 = 0x00000000;
140
+ cpu->isar.id_pfr0 = 0x00000030;
141
+ cpu->isar.id_pfr1 = 0x00000200;
142
+ cpu->isar.id_dfr0 = 0x00100000;
143
+ cpu->id_afr0 = 0x00000000;
144
+ cpu->isar.id_mmfr0 = 0x00000030;
145
+ cpu->isar.id_mmfr1 = 0x00000000;
146
+ cpu->isar.id_mmfr2 = 0x00000000;
147
+ cpu->isar.id_mmfr3 = 0x00000000;
148
+ cpu->isar.id_isar0 = 0x01141110;
149
+ cpu->isar.id_isar1 = 0x02111000;
150
+ cpu->isar.id_isar2 = 0x21112231;
151
+ cpu->isar.id_isar3 = 0x01111110;
152
+ cpu->isar.id_isar4 = 0x01310102;
153
+ cpu->isar.id_isar5 = 0x00000000;
154
+ cpu->isar.id_isar6 = 0x00000000;
155
+}
156
+
157
+static void cortex_m7_initfn(Object *obj)
158
+{
159
+ ARMCPU *cpu = ARM_CPU(obj);
160
+
161
+ set_feature(&cpu->env, ARM_FEATURE_V7);
162
+ set_feature(&cpu->env, ARM_FEATURE_M);
163
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
164
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
165
+ cpu->midr = 0x411fc272; /* r1p2 */
166
+ cpu->pmsav7_dregion = 8;
167
+ cpu->isar.mvfr0 = 0x10110221;
168
+ cpu->isar.mvfr1 = 0x12000011;
169
+ cpu->isar.mvfr2 = 0x00000040;
170
+ cpu->isar.id_pfr0 = 0x00000030;
171
+ cpu->isar.id_pfr1 = 0x00000200;
172
+ cpu->isar.id_dfr0 = 0x00100000;
173
+ cpu->id_afr0 = 0x00000000;
174
+ cpu->isar.id_mmfr0 = 0x00100030;
175
+ cpu->isar.id_mmfr1 = 0x00000000;
176
+ cpu->isar.id_mmfr2 = 0x01000000;
177
+ cpu->isar.id_mmfr3 = 0x00000000;
178
+ cpu->isar.id_isar0 = 0x01101110;
179
+ cpu->isar.id_isar1 = 0x02112000;
180
+ cpu->isar.id_isar2 = 0x20232231;
181
+ cpu->isar.id_isar3 = 0x01111131;
182
+ cpu->isar.id_isar4 = 0x01310132;
183
+ cpu->isar.id_isar5 = 0x00000000;
184
+ cpu->isar.id_isar6 = 0x00000000;
185
+}
186
+
187
+static void cortex_m33_initfn(Object *obj)
188
+{
189
+ ARMCPU *cpu = ARM_CPU(obj);
190
+
191
+ set_feature(&cpu->env, ARM_FEATURE_V8);
192
+ set_feature(&cpu->env, ARM_FEATURE_M);
193
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
194
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
195
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
196
+ cpu->midr = 0x410fd213; /* r0p3 */
197
+ cpu->pmsav7_dregion = 16;
198
+ cpu->sau_sregion = 8;
199
+ cpu->isar.mvfr0 = 0x10110021;
200
+ cpu->isar.mvfr1 = 0x11000011;
201
+ cpu->isar.mvfr2 = 0x00000040;
202
+ cpu->isar.id_pfr0 = 0x00000030;
203
+ cpu->isar.id_pfr1 = 0x00000210;
204
+ cpu->isar.id_dfr0 = 0x00200000;
205
+ cpu->id_afr0 = 0x00000000;
206
+ cpu->isar.id_mmfr0 = 0x00101F40;
207
+ cpu->isar.id_mmfr1 = 0x00000000;
208
+ cpu->isar.id_mmfr2 = 0x01000000;
209
+ cpu->isar.id_mmfr3 = 0x00000000;
210
+ cpu->isar.id_isar0 = 0x01101110;
211
+ cpu->isar.id_isar1 = 0x02212000;
212
+ cpu->isar.id_isar2 = 0x20232232;
213
+ cpu->isar.id_isar3 = 0x01111131;
214
+ cpu->isar.id_isar4 = 0x01310132;
215
+ cpu->isar.id_isar5 = 0x00000000;
216
+ cpu->isar.id_isar6 = 0x00000000;
217
+ cpu->clidr = 0x00000000;
218
+ cpu->ctr = 0x8000c000;
219
+}
220
+
221
+static void cortex_m55_initfn(Object *obj)
222
+{
223
+ ARMCPU *cpu = ARM_CPU(obj);
224
+
225
+ set_feature(&cpu->env, ARM_FEATURE_V8);
226
+ set_feature(&cpu->env, ARM_FEATURE_V8_1M);
227
+ set_feature(&cpu->env, ARM_FEATURE_M);
228
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
229
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
230
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
231
+ cpu->midr = 0x410fd221; /* r0p1 */
232
+ cpu->revidr = 0;
233
+ cpu->pmsav7_dregion = 16;
234
+ cpu->sau_sregion = 8;
235
+ /* These are the MVFR* values for the FPU + full MVE configuration */
236
+ cpu->isar.mvfr0 = 0x10110221;
237
+ cpu->isar.mvfr1 = 0x12100211;
238
+ cpu->isar.mvfr2 = 0x00000040;
239
+ cpu->isar.id_pfr0 = 0x20000030;
240
+ cpu->isar.id_pfr1 = 0x00000230;
241
+ cpu->isar.id_dfr0 = 0x10200000;
242
+ cpu->id_afr0 = 0x00000000;
243
+ cpu->isar.id_mmfr0 = 0x00111040;
244
+ cpu->isar.id_mmfr1 = 0x00000000;
245
+ cpu->isar.id_mmfr2 = 0x01000000;
246
+ cpu->isar.id_mmfr3 = 0x00000011;
247
+ cpu->isar.id_isar0 = 0x01103110;
248
+ cpu->isar.id_isar1 = 0x02212000;
249
+ cpu->isar.id_isar2 = 0x20232232;
250
+ cpu->isar.id_isar3 = 0x01111131;
251
+ cpu->isar.id_isar4 = 0x01310132;
252
+ cpu->isar.id_isar5 = 0x00000000;
253
+ cpu->isar.id_isar6 = 0x00000000;
254
+ cpu->clidr = 0x00000000; /* caches not implemented */
255
+ cpu->ctr = 0x8303c003;
256
+}
257
+
258
+static const TCGCPUOps arm_v7m_tcg_ops = {
259
+ .initialize = arm_translate_init,
260
+ .synchronize_from_tb = arm_cpu_synchronize_from_tb,
261
+ .debug_excp_handler = arm_debug_excp_handler,
262
+ .restore_state_to_opc = arm_restore_state_to_opc,
263
+
264
+#ifdef CONFIG_USER_ONLY
265
+ .record_sigsegv = arm_cpu_record_sigsegv,
266
+ .record_sigbus = arm_cpu_record_sigbus,
267
+#else
268
+ .tlb_fill = arm_cpu_tlb_fill,
269
+ .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
270
+ .do_interrupt = arm_v7m_cpu_do_interrupt,
271
+ .do_transaction_failed = arm_cpu_do_transaction_failed,
272
+ .do_unaligned_access = arm_cpu_do_unaligned_access,
273
+ .adjust_watchpoint_address = arm_adjust_watchpoint_address,
274
+ .debug_check_watchpoint = arm_debug_check_watchpoint,
275
+ .debug_check_breakpoint = arm_debug_check_breakpoint,
276
+#endif /* !CONFIG_USER_ONLY */
277
+};
278
+
279
+static void arm_v7m_class_init(ObjectClass *oc, void *data)
280
+{
281
+ ARMCPUClass *acc = ARM_CPU_CLASS(oc);
282
+ CPUClass *cc = CPU_CLASS(oc);
283
+
284
+ acc->info = data;
285
+ cc->tcg_ops = &arm_v7m_tcg_ops;
286
+ cc->gdb_core_xml_file = "arm-m-profile.xml";
287
+}
288
+
289
+static const ARMCPUInfo arm_v7m_cpus[] = {
290
+ { .name = "cortex-m0", .initfn = cortex_m0_initfn,
291
+ .class_init = arm_v7m_class_init },
292
+ { .name = "cortex-m3", .initfn = cortex_m3_initfn,
293
+ .class_init = arm_v7m_class_init },
294
+ { .name = "cortex-m4", .initfn = cortex_m4_initfn,
295
+ .class_init = arm_v7m_class_init },
296
+ { .name = "cortex-m7", .initfn = cortex_m7_initfn,
297
+ .class_init = arm_v7m_class_init },
298
+ { .name = "cortex-m33", .initfn = cortex_m33_initfn,
299
+ .class_init = arm_v7m_class_init },
300
+ { .name = "cortex-m55", .initfn = cortex_m55_initfn,
301
+ .class_init = arm_v7m_class_init },
302
+};
303
+
304
+static void arm_v7m_cpu_register_types(void)
305
+{
306
+ size_t i;
307
+
308
+ for (i = 0; i < ARRAY_SIZE(arm_v7m_cpus); ++i) {
309
+ arm_cpu_register(&arm_v7m_cpus[i]);
310
+ }
311
+}
312
+
313
+type_init(arm_v7m_cpu_register_types)
314
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
315
index XXXXXXX..XXXXXXX 100644
316
--- a/target/arm/tcg/cpu32.c
317
+++ b/target/arm/tcg/cpu32.c
318
@@ -XXX,XX +XXX,XX @@
319
#include "hw/boards.h"
320
#endif
321
#include "cpregs.h"
322
-#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
323
-#include "hw/intc/armv7m_nvic.h"
324
-#endif
325
326
327
/* Share AArch32 -cpu max features with AArch64. */
328
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
329
/* CPU models. These are not needed for the AArch64 linux-user build. */
330
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
331
332
-#if !defined(CONFIG_USER_ONLY)
333
-static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
334
-{
335
- CPUClass *cc = CPU_GET_CLASS(cs);
336
- ARMCPU *cpu = ARM_CPU(cs);
337
- CPUARMState *env = &cpu->env;
338
- bool ret = false;
339
-
340
- /*
341
- * ARMv7-M interrupt masking works differently than -A or -R.
342
- * There is no FIQ/IRQ distinction. Instead of I and F bits
343
- * masking FIQ and IRQ interrupts, an exception is taken only
344
- * if it is higher priority than the current execution priority
345
- * (which depends on state like BASEPRI, FAULTMASK and the
346
- * currently active exception).
347
- */
348
- if (interrupt_request & CPU_INTERRUPT_HARD
349
- && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
350
- cs->exception_index = EXCP_IRQ;
351
- cc->tcg_ops->do_interrupt(cs);
352
- ret = true;
353
- }
354
- return ret;
355
-}
356
-#endif /* !CONFIG_USER_ONLY */
357
-
358
static void arm926_initfn(Object *obj)
359
{
360
ARMCPU *cpu = ARM_CPU(obj);
361
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
362
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
363
}
364
365
-static void cortex_m0_initfn(Object *obj)
366
-{
367
- ARMCPU *cpu = ARM_CPU(obj);
368
- set_feature(&cpu->env, ARM_FEATURE_V6);
369
- set_feature(&cpu->env, ARM_FEATURE_M);
370
-
371
- cpu->midr = 0x410cc200;
372
-
373
- /*
374
- * These ID register values are not guest visible, because
375
- * we do not implement the Main Extension. They must be set
376
- * to values corresponding to the Cortex-M0's implemented
377
- * features, because QEMU generally controls its emulation
378
- * by looking at ID register fields. We use the same values as
379
- * for the M3.
380
- */
381
- cpu->isar.id_pfr0 = 0x00000030;
382
- cpu->isar.id_pfr1 = 0x00000200;
383
- cpu->isar.id_dfr0 = 0x00100000;
384
- cpu->id_afr0 = 0x00000000;
385
- cpu->isar.id_mmfr0 = 0x00000030;
386
- cpu->isar.id_mmfr1 = 0x00000000;
387
- cpu->isar.id_mmfr2 = 0x00000000;
388
- cpu->isar.id_mmfr3 = 0x00000000;
389
- cpu->isar.id_isar0 = 0x01141110;
390
- cpu->isar.id_isar1 = 0x02111000;
391
- cpu->isar.id_isar2 = 0x21112231;
392
- cpu->isar.id_isar3 = 0x01111110;
393
- cpu->isar.id_isar4 = 0x01310102;
394
- cpu->isar.id_isar5 = 0x00000000;
395
- cpu->isar.id_isar6 = 0x00000000;
396
-}
397
-
398
-static void cortex_m3_initfn(Object *obj)
399
-{
400
- ARMCPU *cpu = ARM_CPU(obj);
401
- set_feature(&cpu->env, ARM_FEATURE_V7);
402
- set_feature(&cpu->env, ARM_FEATURE_M);
403
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
404
- cpu->midr = 0x410fc231;
405
- cpu->pmsav7_dregion = 8;
406
- cpu->isar.id_pfr0 = 0x00000030;
407
- cpu->isar.id_pfr1 = 0x00000200;
408
- cpu->isar.id_dfr0 = 0x00100000;
409
- cpu->id_afr0 = 0x00000000;
410
- cpu->isar.id_mmfr0 = 0x00000030;
411
- cpu->isar.id_mmfr1 = 0x00000000;
412
- cpu->isar.id_mmfr2 = 0x00000000;
413
- cpu->isar.id_mmfr3 = 0x00000000;
414
- cpu->isar.id_isar0 = 0x01141110;
415
- cpu->isar.id_isar1 = 0x02111000;
416
- cpu->isar.id_isar2 = 0x21112231;
417
- cpu->isar.id_isar3 = 0x01111110;
418
- cpu->isar.id_isar4 = 0x01310102;
419
- cpu->isar.id_isar5 = 0x00000000;
420
- cpu->isar.id_isar6 = 0x00000000;
421
-}
422
-
423
-static void cortex_m4_initfn(Object *obj)
424
-{
425
- ARMCPU *cpu = ARM_CPU(obj);
426
-
427
- set_feature(&cpu->env, ARM_FEATURE_V7);
428
- set_feature(&cpu->env, ARM_FEATURE_M);
429
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
430
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
431
- cpu->midr = 0x410fc240; /* r0p0 */
432
- cpu->pmsav7_dregion = 8;
433
- cpu->isar.mvfr0 = 0x10110021;
434
- cpu->isar.mvfr1 = 0x11000011;
435
- cpu->isar.mvfr2 = 0x00000000;
436
- cpu->isar.id_pfr0 = 0x00000030;
437
- cpu->isar.id_pfr1 = 0x00000200;
438
- cpu->isar.id_dfr0 = 0x00100000;
439
- cpu->id_afr0 = 0x00000000;
440
- cpu->isar.id_mmfr0 = 0x00000030;
441
- cpu->isar.id_mmfr1 = 0x00000000;
442
- cpu->isar.id_mmfr2 = 0x00000000;
443
- cpu->isar.id_mmfr3 = 0x00000000;
444
- cpu->isar.id_isar0 = 0x01141110;
445
- cpu->isar.id_isar1 = 0x02111000;
446
- cpu->isar.id_isar2 = 0x21112231;
447
- cpu->isar.id_isar3 = 0x01111110;
448
- cpu->isar.id_isar4 = 0x01310102;
449
- cpu->isar.id_isar5 = 0x00000000;
450
- cpu->isar.id_isar6 = 0x00000000;
451
-}
452
-
453
-static void cortex_m7_initfn(Object *obj)
454
-{
455
- ARMCPU *cpu = ARM_CPU(obj);
456
-
457
- set_feature(&cpu->env, ARM_FEATURE_V7);
458
- set_feature(&cpu->env, ARM_FEATURE_M);
459
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
460
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
461
- cpu->midr = 0x411fc272; /* r1p2 */
462
- cpu->pmsav7_dregion = 8;
463
- cpu->isar.mvfr0 = 0x10110221;
464
- cpu->isar.mvfr1 = 0x12000011;
465
- cpu->isar.mvfr2 = 0x00000040;
466
- cpu->isar.id_pfr0 = 0x00000030;
467
- cpu->isar.id_pfr1 = 0x00000200;
468
- cpu->isar.id_dfr0 = 0x00100000;
469
- cpu->id_afr0 = 0x00000000;
470
- cpu->isar.id_mmfr0 = 0x00100030;
471
- cpu->isar.id_mmfr1 = 0x00000000;
472
- cpu->isar.id_mmfr2 = 0x01000000;
473
- cpu->isar.id_mmfr3 = 0x00000000;
474
- cpu->isar.id_isar0 = 0x01101110;
475
- cpu->isar.id_isar1 = 0x02112000;
476
- cpu->isar.id_isar2 = 0x20232231;
477
- cpu->isar.id_isar3 = 0x01111131;
478
- cpu->isar.id_isar4 = 0x01310132;
479
- cpu->isar.id_isar5 = 0x00000000;
480
- cpu->isar.id_isar6 = 0x00000000;
481
-}
482
-
483
-static void cortex_m33_initfn(Object *obj)
484
-{
485
- ARMCPU *cpu = ARM_CPU(obj);
486
-
487
- set_feature(&cpu->env, ARM_FEATURE_V8);
488
- set_feature(&cpu->env, ARM_FEATURE_M);
489
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
490
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
491
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
492
- cpu->midr = 0x410fd213; /* r0p3 */
493
- cpu->pmsav7_dregion = 16;
494
- cpu->sau_sregion = 8;
495
- cpu->isar.mvfr0 = 0x10110021;
496
- cpu->isar.mvfr1 = 0x11000011;
497
- cpu->isar.mvfr2 = 0x00000040;
498
- cpu->isar.id_pfr0 = 0x00000030;
499
- cpu->isar.id_pfr1 = 0x00000210;
500
- cpu->isar.id_dfr0 = 0x00200000;
501
- cpu->id_afr0 = 0x00000000;
502
- cpu->isar.id_mmfr0 = 0x00101F40;
503
- cpu->isar.id_mmfr1 = 0x00000000;
504
- cpu->isar.id_mmfr2 = 0x01000000;
505
- cpu->isar.id_mmfr3 = 0x00000000;
506
- cpu->isar.id_isar0 = 0x01101110;
507
- cpu->isar.id_isar1 = 0x02212000;
508
- cpu->isar.id_isar2 = 0x20232232;
509
- cpu->isar.id_isar3 = 0x01111131;
510
- cpu->isar.id_isar4 = 0x01310132;
511
- cpu->isar.id_isar5 = 0x00000000;
512
- cpu->isar.id_isar6 = 0x00000000;
513
- cpu->clidr = 0x00000000;
514
- cpu->ctr = 0x8000c000;
515
-}
516
-
517
-static void cortex_m55_initfn(Object *obj)
518
-{
519
- ARMCPU *cpu = ARM_CPU(obj);
520
-
521
- set_feature(&cpu->env, ARM_FEATURE_V8);
522
- set_feature(&cpu->env, ARM_FEATURE_V8_1M);
523
- set_feature(&cpu->env, ARM_FEATURE_M);
524
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
525
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
526
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
527
- cpu->midr = 0x410fd221; /* r0p1 */
528
- cpu->revidr = 0;
529
- cpu->pmsav7_dregion = 16;
530
- cpu->sau_sregion = 8;
531
- /* These are the MVFR* values for the FPU + full MVE configuration */
532
- cpu->isar.mvfr0 = 0x10110221;
533
- cpu->isar.mvfr1 = 0x12100211;
534
- cpu->isar.mvfr2 = 0x00000040;
535
- cpu->isar.id_pfr0 = 0x20000030;
536
- cpu->isar.id_pfr1 = 0x00000230;
537
- cpu->isar.id_dfr0 = 0x10200000;
538
- cpu->id_afr0 = 0x00000000;
539
- cpu->isar.id_mmfr0 = 0x00111040;
540
- cpu->isar.id_mmfr1 = 0x00000000;
541
- cpu->isar.id_mmfr2 = 0x01000000;
542
- cpu->isar.id_mmfr3 = 0x00000011;
543
- cpu->isar.id_isar0 = 0x01103110;
544
- cpu->isar.id_isar1 = 0x02212000;
545
- cpu->isar.id_isar2 = 0x20232232;
546
- cpu->isar.id_isar3 = 0x01111131;
547
- cpu->isar.id_isar4 = 0x01310132;
548
- cpu->isar.id_isar5 = 0x00000000;
549
- cpu->isar.id_isar6 = 0x00000000;
550
- cpu->clidr = 0x00000000; /* caches not implemented */
551
- cpu->ctr = 0x8303c003;
552
-}
553
-
554
static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
555
/* Dummy the TCM region regs for the moment */
556
{ .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
557
@@ -XXX,XX +XXX,XX @@ static void pxa270c5_initfn(Object *obj)
558
cpu->reset_sctlr = 0x00000078;
559
}
560
561
-static const TCGCPUOps arm_v7m_tcg_ops = {
562
- .initialize = arm_translate_init,
563
- .synchronize_from_tb = arm_cpu_synchronize_from_tb,
564
- .debug_excp_handler = arm_debug_excp_handler,
565
- .restore_state_to_opc = arm_restore_state_to_opc,
566
-
567
-#ifdef CONFIG_USER_ONLY
568
- .record_sigsegv = arm_cpu_record_sigsegv,
569
- .record_sigbus = arm_cpu_record_sigbus,
570
-#else
571
- .tlb_fill = arm_cpu_tlb_fill,
572
- .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
573
- .do_interrupt = arm_v7m_cpu_do_interrupt,
574
- .do_transaction_failed = arm_cpu_do_transaction_failed,
575
- .do_unaligned_access = arm_cpu_do_unaligned_access,
576
- .adjust_watchpoint_address = arm_adjust_watchpoint_address,
577
- .debug_check_watchpoint = arm_debug_check_watchpoint,
578
- .debug_check_breakpoint = arm_debug_check_breakpoint,
579
-#endif /* !CONFIG_USER_ONLY */
580
-};
581
-
582
-static void arm_v7m_class_init(ObjectClass *oc, void *data)
583
-{
584
- ARMCPUClass *acc = ARM_CPU_CLASS(oc);
585
- CPUClass *cc = CPU_CLASS(oc);
586
-
587
- acc->info = data;
588
- cc->tcg_ops = &arm_v7m_tcg_ops;
589
- cc->gdb_core_xml_file = "arm-m-profile.xml";
590
-}
591
-
592
#ifndef TARGET_AARCH64
593
/*
594
* -cpu max: a CPU with as many features enabled as our emulation supports.
595
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = {
596
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
597
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
598
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
599
- { .name = "cortex-m0", .initfn = cortex_m0_initfn,
600
- .class_init = arm_v7m_class_init },
601
- { .name = "cortex-m3", .initfn = cortex_m3_initfn,
602
- .class_init = arm_v7m_class_init },
603
- { .name = "cortex-m4", .initfn = cortex_m4_initfn,
604
- .class_init = arm_v7m_class_init },
605
- { .name = "cortex-m7", .initfn = cortex_m7_initfn,
606
- .class_init = arm_v7m_class_init },
607
- { .name = "cortex-m33", .initfn = cortex_m33_initfn,
608
- .class_init = arm_v7m_class_init },
609
- { .name = "cortex-m55", .initfn = cortex_m55_initfn,
610
- .class_init = arm_v7m_class_init },
611
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
612
{ .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
613
{ .name = "cortex-r52", .initfn = cortex_r52_initfn },
614
diff --git a/target/arm/meson.build b/target/arm/meson.build
615
index XXXXXXX..XXXXXXX 100644
616
--- a/target/arm/meson.build
617
+++ b/target/arm/meson.build
618
@@ -XXX,XX +XXX,XX @@ arm_system_ss.add(files(
619
'ptw.c',
620
))
621
622
+arm_user_ss = ss.source_set()
623
+
624
subdir('hvf')
625
626
if 'CONFIG_TCG' in config_all_accel
627
@@ -XXX,XX +XXX,XX @@ endif
628
629
target_arch += {'arm': arm_ss}
630
target_system_arch += {'arm': arm_system_ss}
631
+target_user_arch += {'arm': arm_user_ss}
632
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
633
index XXXXXXX..XXXXXXX 100644
634
--- a/target/arm/tcg/meson.build
635
+++ b/target/arm/tcg/meson.build
636
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
637
arm_system_ss.add(files(
638
'psci.c',
639
))
640
+
641
+arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c'))
642
+arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c'))
77
--
643
--
78
2.20.1
644
2.34.1
79
80
diff view generated by jsdifflib
[PULL 02/29] docs/system: Add 'Arm' to the Integrator/CP document title
Deleted patch
1
Add 'Arm' to the Integrator/CP document title, for consistency with
2
the titling of the other documentation of Arm devboard models
3
(versatile, realview).
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20200507151819.28444-2-peter.maydell@linaro.org
10
---
11
docs/system/arm/integratorcp.rst | 4 ++--
12
1 file changed, 2 insertions(+), 2 deletions(-)
13
14
diff --git a/docs/system/arm/integratorcp.rst b/docs/system/arm/integratorcp.rst
15
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/integratorcp.rst
17
+++ b/docs/system/arm/integratorcp.rst
18
@@ -XXX,XX +XXX,XX @@
19
-Integrator/CP (``integratorcp``)
20
-================================
21
+Arm Integrator/CP (``integratorcp``)
22
+====================================
23
24
The Arm Integrator/CP board is emulated with the following devices:
25
26
--
27
2.20.1
28
29
diff view generated by jsdifflib
[PULL 03/29] docs/system: Sort Arm board index into alphabetical order
Deleted patch
1
Sort the board index into alphabetical order. (Note that we need to
2
sort alphabetically by the title text of each file, which isn't the
3
same ordering as sorting by the filename.)
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20200507151819.28444-3-peter.maydell@linaro.org
10
---
11
docs/system/target-arm.rst | 17 +++++++++++------
12
1 file changed, 11 insertions(+), 6 deletions(-)
13
14
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
15
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/target-arm.rst
17
+++ b/docs/system/target-arm.rst
18
@@ -XXX,XX +XXX,XX @@ Unfortunately many of the Arm boards QEMU supports are currently
19
undocumented; you can get a complete list by running
20
``qemu-system-aarch64 --machine help``.
21
22
+..
23
+ This table of contents should be kept sorted alphabetically
24
+ by the title text of each file, which isn't the same ordering
25
+ as an alphabetical sort by filename.
26
+
27
.. toctree::
28
:maxdepth: 1
29
30
arm/integratorcp
31
- arm/versatile
32
arm/realview
33
- arm/xscale
34
- arm/palm
35
- arm/nseries
36
- arm/stellaris
37
+ arm/versatile
38
arm/musicpal
39
- arm/sx1
40
+ arm/nseries
41
arm/orangepi
42
+ arm/palm
43
+ arm/xscale
44
+ arm/sx1
45
+ arm/stellaris
46
47
Arm CPU features
48
================
49
--
50
2.20.1
51
52
diff view generated by jsdifflib
[PULL 04/29] docs/system: Document Arm Versatile Express boards
Deleted patch
1
Provide a minimal documentation of the Versatile Express boards
2
(vexpress-a9, vexpress-a15).
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20200507151819.28444-4-peter.maydell@linaro.org
9
---
10
docs/system/arm/vexpress.rst | 60 ++++++++++++++++++++++++++++++++++++
11
docs/system/target-arm.rst | 1 +
12
MAINTAINERS | 1 +
13
3 files changed, 62 insertions(+)
14
create mode 100644 docs/system/arm/vexpress.rst
15
16
diff --git a/docs/system/arm/vexpress.rst b/docs/system/arm/vexpress.rst
17
new file mode 100644
18
index XXXXXXX..XXXXXXX
19
--- /dev/null
20
+++ b/docs/system/arm/vexpress.rst
21
@@ -XXX,XX +XXX,XX @@
22
+Arm Versatile Express boards (``vexpress-a9``, ``vexpress-a15``)
23
+================================================================
24
+
25
+QEMU models two variants of the Arm Versatile Express development
26
+board family:
27
+
28
+- ``vexpress-a9`` models the combination of the Versatile Express
29
+ motherboard and the CoreTile Express A9x4 daughterboard
30
+- ``vexpress-a15`` models the combination of the Versatile Express
31
+ motherboard and the CoreTile Express A15x2 daughterboard
32
+
33
+Note that as this hardware does not have PCI, IDE or SCSI,
34
+the only available storage option is emulated SD card.
35
+
36
+Implemented devices:
37
+
38
+- PL041 audio
39
+- PL181 SD controller
40
+- PL050 keyboard and mouse
41
+- PL011 UARTs
42
+- SP804 timers
43
+- I2C controller
44
+- PL031 RTC
45
+- PL111 LCD display controller
46
+- Flash memory
47
+- LAN9118 ethernet
48
+
49
+Unimplemented devices:
50
+
51
+- SP810 system control block
52
+- PCI-express
53
+- USB controller (Philips ISP1761)
54
+- Local DAP ROM
55
+- CoreSight interfaces
56
+- PL301 AXI interconnect
57
+- SCC
58
+- System counter
59
+- HDLCD controller (``vexpress-a15``)
60
+- SP805 watchdog
61
+- PL341 dynamic memory controller
62
+- DMA330 DMA controller
63
+- PL354 static memory controller
64
+- BP147 TrustZone Protection Controller
65
+- TrustZone Address Space Controller
66
+
67
+Other differences between the hardware and the QEMU model:
68
+
69
+- QEMU will default to creating one CPU unless you pass a different
70
+ ``-smp`` argument
71
+- QEMU allows the amount of RAM provided to be specified with the
72
+ ``-m`` argument
73
+- QEMU defaults to providing a CPU which does not provide either
74
+ TrustZone or the Virtualization Extensions: if you want these you
75
+ must enable them with ``-machine secure=on`` and ``-machine
76
+ virtualization=on``
77
+- QEMU provides 4 virtio-mmio virtio transports; these start at
78
+ address ``0x10013000`` for ``vexpress-a9`` and at ``0x1c130000`` for
79
+ ``vexpress-a15``, and have IRQs from 40 upwards. If a dtb is
80
+ provided on the command line then QEMU will edit it to include
81
+ suitable entries describing these transports for the guest.
82
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
83
index XXXXXXX..XXXXXXX 100644
84
--- a/docs/system/target-arm.rst
85
+++ b/docs/system/target-arm.rst
86
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
87
arm/integratorcp
88
arm/realview
89
arm/versatile
90
+ arm/vexpress
91
arm/musicpal
92
arm/nseries
93
arm/orangepi
94
diff --git a/MAINTAINERS b/MAINTAINERS
95
index XXXXXXX..XXXXXXX 100644
96
--- a/MAINTAINERS
97
+++ b/MAINTAINERS
98
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
99
L: qemu-arm@nongnu.org
100
S: Maintained
101
F: hw/arm/vexpress.c
102
+F: docs/system/arm/vexpress.rst
103
104
Versatile PB
105
M: Peter Maydell <peter.maydell@linaro.org>
106
--
107
2.20.1
108
109
diff view generated by jsdifflib
[PULL 05/29] docs/system: Document the various MPS2 models
Deleted patch
1
Add basic documentation of the MPS2 board models.
2
1
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20200507151819.28444-5-peter.maydell@linaro.org
8
---
9
docs/system/arm/mps2.rst | 29 +++++++++++++++++++++++++++++
10
docs/system/target-arm.rst | 1 +
11
MAINTAINERS | 1 +
12
3 files changed, 31 insertions(+)
13
create mode 100644 docs/system/arm/mps2.rst
14
15
diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
16
new file mode 100644
17
index XXXXXXX..XXXXXXX
18
--- /dev/null
19
+++ b/docs/system/arm/mps2.rst
20
@@ -XXX,XX +XXX,XX @@
21
+Arm MPS2 boards (``mps2-an385``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
22
+================================================================================
23
+
24
+These board models all use Arm M-profile CPUs.
25
+
26
+The Arm MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
27
+FPGA but is otherwise the same as the 2). Since the CPU itself
28
+and most of the devices are in the FPGA, the details of the board
29
+as seen by the guest depend significantly on the FPGA image.
30
+
31
+QEMU models the following FPGA images:
32
+
33
+``mps2-an385``
34
+ Cortex-M3 as documented in ARM Application Note AN385
35
+``mps2-an511``
36
+ Cortex-M3 'DesignStart' as documented in AN511
37
+``mps2-an505``
38
+ Cortex-M33 as documented in ARM Application Note AN505
39
+``mps2-an521``
40
+ Dual Cortex-M33 as documented in Application Note AN521
41
+
42
+Differences between QEMU and real hardware:
43
+
44
+- AN385 remapping of low 16K of memory to either ZBT SSRAM1 or to
45
+ block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as
46
+ if zbt_boot_ctrl is always zero)
47
+- QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest
48
+ visible difference is that the LAN9118 doesn't support checksum
49
+ offloading
50
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
51
index XXXXXXX..XXXXXXX 100644
52
--- a/docs/system/target-arm.rst
53
+++ b/docs/system/target-arm.rst
54
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
55
:maxdepth: 1
56
57
arm/integratorcp
58
+ arm/mps2
59
arm/realview
60
arm/versatile
61
arm/vexpress
62
diff --git a/MAINTAINERS b/MAINTAINERS
63
index XXXXXXX..XXXXXXX 100644
64
--- a/MAINTAINERS
65
+++ b/MAINTAINERS
66
@@ -XXX,XX +XXX,XX @@ F: hw/misc/armsse-cpuid.c
67
F: include/hw/misc/armsse-cpuid.h
68
F: hw/misc/armsse-mhu.c
69
F: include/hw/misc/armsse-mhu.h
70
+F: docs/system/arm/mps2.rst
71
72
Musca
73
M: Peter Maydell <peter.maydell@linaro.org>
74
--
75
2.20.1
76
77
diff view generated by jsdifflib
[PULL 07/29] linux-user/arm: BKPT should cause SIGTRAP, not be a syscall
Deleted patch
1
In linux-user/arm/cpu-loop.c we incorrectly treat EXCP_BKPT similarly
2
to EXCP_SWI, which means that if the guest executes a BKPT insn then
3
QEMU will perform a syscall for it (which syscall depends on what
4
value happens to be in r7...). The correct behaviour is that the
5
guest process should take a SIGTRAP.
6
1
7
This code has been like this (more or less) since commit
8
06c949e62a098f in 2006 which added BKPT in the first place. This is
9
probably because at the time the same code path was used to handle
10
both Linux syscalls and semihosting calls, and (on M profile) BKPT
11
with a suitable magic number is used for semihosting calls. But
12
these days we've moved handling of semihosting out to an entirely
13
different codepath, so we can fix this bug by simply removing this
14
handling of EXCP_BKPT and instead making it deliver a SIGTRAP like
15
EXCP_DEBUG (as we do already on aarch64).
16
17
Reported-by: <omerg681@gmail.com>
18
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
19
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Message-id: 20200420212206.12776-2-peter.maydell@linaro.org
22
Fixes: https://bugs.launchpad.net/qemu/+bug/1873898
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
---
25
linux-user/arm/cpu_loop.c | 30 ++++++++----------------------
26
1 file changed, 8 insertions(+), 22 deletions(-)
27
28
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/linux-user/arm/cpu_loop.c
31
+++ b/linux-user/arm/cpu_loop.c
32
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
33
}
34
break;
35
case EXCP_SWI:
36
- case EXCP_BKPT:
37
{
38
env->eabi = 1;
39
/* system call */
40
- if (trapnr == EXCP_BKPT) {
41
- if (env->thumb) {
42
- /* FIXME - what to do if get_user() fails? */
43
- get_user_code_u16(insn, env->regs[15], env);
44
- n = insn & 0xff;
45
- env->regs[15] += 2;
46
- } else {
47
- /* FIXME - what to do if get_user() fails? */
48
- get_user_code_u32(insn, env->regs[15], env);
49
- n = (insn & 0xf) | ((insn >> 4) & 0xff0);
50
- env->regs[15] += 4;
51
- }
52
+ if (env->thumb) {
53
+ /* FIXME - what to do if get_user() fails? */
54
+ get_user_code_u16(insn, env->regs[15] - 2, env);
55
+ n = insn & 0xff;
56
} else {
57
- if (env->thumb) {
58
- /* FIXME - what to do if get_user() fails? */
59
- get_user_code_u16(insn, env->regs[15] - 2, env);
60
- n = insn & 0xff;
61
- } else {
62
- /* FIXME - what to do if get_user() fails? */
63
- get_user_code_u32(insn, env->regs[15] - 4, env);
64
- n = insn & 0xffffff;
65
- }
66
+ /* FIXME - what to do if get_user() fails? */
67
+ get_user_code_u32(insn, env->regs[15] - 4, env);
68
+ n = insn & 0xffffff;
69
}
70
71
if (n == ARM_NR_cacheflush) {
72
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
73
}
74
break;
75
case EXCP_DEBUG:
76
+ case EXCP_BKPT:
77
excp_debug:
78
info.si_signo = TARGET_SIGTRAP;
79
info.si_errno = 0;
80
--
81
2.20.1
82
83
diff view generated by jsdifflib
[PULL 09/29] linux-user/arm: Handle invalid arm-specific syscalls correctly
Deleted patch
1
The kernel has different handling for syscalls with invalid
2
numbers that are in the "arm-specific" range 0x9f0000 and up:
3
* 0x9f0000..0x9f07ff return -ENOSYS if not implemented
4
* other out of range syscalls cause a SIGILL
5
(see the kernel's arch/arm/kernel/traps.c:arm_syscall())
6
1
7
Implement this distinction. (Note that our code doesn't look
8
quite like the kernel's, because we have removed the
9
0x900000 prefix by this point, whereas the kernel retains
10
it in arm_syscall().)
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20200420212206.12776-4-peter.maydell@linaro.org
15
---
16
linux-user/arm/cpu_loop.c | 30 ++++++++++++++++++++++++++----
17
1 file changed, 26 insertions(+), 4 deletions(-)
18
19
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/linux-user/arm/cpu_loop.c
22
+++ b/linux-user/arm/cpu_loop.c
23
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
24
env->regs[0] = cpu_get_tls(env);
25
break;
26
default:
27
- qemu_log_mask(LOG_UNIMP,
28
- "qemu: Unsupported ARM syscall: 0x%x\n",
29
- n);
30
- env->regs[0] = -TARGET_ENOSYS;
31
+ if (n < 0xf0800) {
32
+ /*
33
+ * Syscalls 0xf0000..0xf07ff (or 0x9f0000..
34
+ * 0x9f07ff in OABI numbering) are defined
35
+ * to return -ENOSYS rather than raising
36
+ * SIGILL. Note that we have already
37
+ * removed the 0x900000 prefix.
38
+ */
39
+ qemu_log_mask(LOG_UNIMP,
40
+ "qemu: Unsupported ARM syscall: 0x%x\n",
41
+ n);
42
+ env->regs[0] = -TARGET_ENOSYS;
43
+ } else {
44
+ /* Otherwise SIGILL */
45
+ info.si_signo = TARGET_SIGILL;
46
+ info.si_errno = 0;
47
+ info.si_code = TARGET_ILL_ILLTRP;
48
+ info._sifields._sigfault._addr = env->regs[15];
49
+ if (env->thumb) {
50
+ info._sifields._sigfault._addr -= 2;
51
+ } else {
52
+ info._sifields._sigfault._addr -= 4;
53
+ }
54
+ queue_signal(env, info.si_signo,
55
+ QEMU_SI_FAULT, &info);
56
+ }
57
break;
58
}
59
} else {
60
--
61
2.20.1
62
63
diff view generated by jsdifflib
[PULL 12/29] hw: Move i.MX watchdog driver to hw/watchdog
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
In preparation for a full implementation, move i.MX watchdog driver
4
from hw/misc to hw/watchdog. While at it, add the watchdog files
5
to MAINTAINERS.
6
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
9
Message-id: 20200517162135.110364-2-linux@roeck-us.net
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/arm/fsl-imx6.h | 2 +-
13
include/hw/arm/fsl-imx6ul.h | 2 +-
14
include/hw/arm/fsl-imx7.h | 2 +-
15
include/hw/{misc/imx2_wdt.h => watchdog/wdt_imx2.h} | 0
16
hw/{misc/imx2_wdt.c => watchdog/wdt_imx2.c} | 2 +-
17
MAINTAINERS | 2 ++
18
hw/arm/Kconfig | 3 +++
19
hw/misc/Makefile.objs | 1 -
20
hw/watchdog/Kconfig | 3 +++
21
hw/watchdog/Makefile.objs | 1 +
22
10 files changed, 13 insertions(+), 5 deletions(-)
23
rename include/hw/{misc/imx2_wdt.h => watchdog/wdt_imx2.h} (100%)
24
rename hw/{misc/imx2_wdt.c => watchdog/wdt_imx2.c} (98%)
25
26
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/arm/fsl-imx6.h
29
+++ b/include/hw/arm/fsl-imx6.h
30
@@ -XXX,XX +XXX,XX @@
31
#include "hw/cpu/a9mpcore.h"
32
#include "hw/misc/imx6_ccm.h"
33
#include "hw/misc/imx6_src.h"
34
-#include "hw/misc/imx2_wdt.h"
35
+#include "hw/watchdog/wdt_imx2.h"
36
#include "hw/char/imx_serial.h"
37
#include "hw/timer/imx_gpt.h"
38
#include "hw/timer/imx_epit.h"
39
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/include/hw/arm/fsl-imx6ul.h
42
+++ b/include/hw/arm/fsl-imx6ul.h
43
@@ -XXX,XX +XXX,XX @@
44
#include "hw/misc/imx7_snvs.h"
45
#include "hw/misc/imx7_gpr.h"
46
#include "hw/intc/imx_gpcv2.h"
47
-#include "hw/misc/imx2_wdt.h"
48
+#include "hw/watchdog/wdt_imx2.h"
49
#include "hw/gpio/imx_gpio.h"
50
#include "hw/char/imx_serial.h"
51
#include "hw/timer/imx_gpt.h"
52
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
53
index XXXXXXX..XXXXXXX 100644
54
--- a/include/hw/arm/fsl-imx7.h
55
+++ b/include/hw/arm/fsl-imx7.h
56
@@ -XXX,XX +XXX,XX @@
57
#include "hw/misc/imx7_snvs.h"
58
#include "hw/misc/imx7_gpr.h"
59
#include "hw/misc/imx6_src.h"
60
-#include "hw/misc/imx2_wdt.h"
61
+#include "hw/watchdog/wdt_imx2.h"
62
#include "hw/gpio/imx_gpio.h"
63
#include "hw/char/imx_serial.h"
64
#include "hw/timer/imx_gpt.h"
65
diff --git a/include/hw/misc/imx2_wdt.h b/include/hw/watchdog/wdt_imx2.h
66
similarity index 100%
67
rename from include/hw/misc/imx2_wdt.h
68
rename to include/hw/watchdog/wdt_imx2.h
69
diff --git a/hw/misc/imx2_wdt.c b/hw/watchdog/wdt_imx2.c
70
similarity index 98%
71
rename from hw/misc/imx2_wdt.c
72
rename to hw/watchdog/wdt_imx2.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/hw/misc/imx2_wdt.c
75
+++ b/hw/watchdog/wdt_imx2.c
76
@@ -XXX,XX +XXX,XX @@
77
#include "qemu/module.h"
78
#include "sysemu/watchdog.h"
79
80
-#include "hw/misc/imx2_wdt.h"
81
+#include "hw/watchdog/wdt_imx2.h"
82
83
#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
84
#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
85
diff --git a/MAINTAINERS b/MAINTAINERS
86
index XXXXXXX..XXXXXXX 100644
87
--- a/MAINTAINERS
88
+++ b/MAINTAINERS
89
@@ -XXX,XX +XXX,XX @@ S: Odd Fixes
90
F: hw/arm/fsl-imx25.c
91
F: hw/arm/imx25_pdk.c
92
F: hw/misc/imx25_ccm.c
93
+F: hw/watchdog/wdt_imx2.c
94
F: include/hw/arm/fsl-imx25.h
95
F: include/hw/misc/imx25_ccm.h
96
+F: include/hw/watchdog/wdt_imx2.h
97
98
i.MX31 (kzm)
99
M: Peter Chubb <peter.chubb@nicta.com.au>
100
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
101
index XXXXXXX..XXXXXXX 100644
102
--- a/hw/arm/Kconfig
103
+++ b/hw/arm/Kconfig
104
@@ -XXX,XX +XXX,XX @@ config FSL_IMX6
105
select IMX_FEC
106
select IMX_I2C
107
select IMX_USBPHY
108
+ select WDT_IMX2
109
select SDHCI
110
111
config ASPEED_SOC
112
@@ -XXX,XX +XXX,XX @@ config FSL_IMX7
113
select IMX
114
select IMX_FEC
115
select IMX_I2C
116
+ select WDT_IMX2
117
select PCI_EXPRESS_DESIGNWARE
118
select SDHCI
119
select UNIMP
120
@@ -XXX,XX +XXX,XX @@ config FSL_IMX6UL
121
select IMX
122
select IMX_FEC
123
select IMX_I2C
124
+ select WDT_IMX2
125
select SDHCI
126
select UNIMP
127
128
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
129
index XXXXXXX..XXXXXXX 100644
130
--- a/hw/misc/Makefile.objs
131
+++ b/hw/misc/Makefile.objs
132
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IMX) += imx6_ccm.o
133
common-obj-$(CONFIG_IMX) += imx6ul_ccm.o
134
obj-$(CONFIG_IMX) += imx6_src.o
135
common-obj-$(CONFIG_IMX) += imx7_ccm.o
136
-common-obj-$(CONFIG_IMX) += imx2_wdt.o
137
common-obj-$(CONFIG_IMX) += imx7_snvs.o
138
common-obj-$(CONFIG_IMX) += imx7_gpr.o
139
common-obj-$(CONFIG_IMX) += imx_rngc.o
140
diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig
141
index XXXXXXX..XXXXXXX 100644
142
--- a/hw/watchdog/Kconfig
143
+++ b/hw/watchdog/Kconfig
144
@@ -XXX,XX +XXX,XX @@ config WDT_IB700
145
146
config WDT_DIAG288
147
bool
148
+
149
+config WDT_IMX2
150
+ bool
151
diff --git a/hw/watchdog/Makefile.objs b/hw/watchdog/Makefile.objs
152
index XXXXXXX..XXXXXXX 100644
153
--- a/hw/watchdog/Makefile.objs
154
+++ b/hw/watchdog/Makefile.objs
155
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_WDT_IB6300ESB) += wdt_i6300esb.o
156
common-obj-$(CONFIG_WDT_IB700) += wdt_ib700.o
157
common-obj-$(CONFIG_WDT_DIAG288) += wdt_diag288.o
158
common-obj-$(CONFIG_ASPEED_SOC) += wdt_aspeed.o
159
+common-obj-$(CONFIG_WDT_IMX2) += wdt_imx2.o
160
--
161
2.20.1
162
163
diff view generated by jsdifflib
[PULL 16/29] hw/arm/fsl-imx6: Connect watchdog interrupts
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
With this patch applied, the watchdog in the sabrelite emulation
4
is fully operational, including pretimeout support.
5
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20200517162135.110364-6-linux@roeck-us.net
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/fsl-imx6.c | 9 +++++++++
12
1 file changed, 9 insertions(+)
13
14
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/fsl-imx6.c
17
+++ b/hw/arm/fsl-imx6.c
18
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
19
FSL_IMX6_WDOG1_ADDR,
20
FSL_IMX6_WDOG2_ADDR,
21
};
22
+ static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = {
23
+ FSL_IMX6_WDOG1_IRQ,
24
+ FSL_IMX6_WDOG2_IRQ,
25
+ };
26
27
+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
28
+ &error_abort);
29
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
30
&error_abort);
31
32
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
33
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
34
+ qdev_get_gpio_in(DEVICE(&s->a9mpcore),
35
+ FSL_IMX6_WDOGn_IRQ[i]));
36
}
37
38
/* ROM memory */
39
--
40
2.20.1
41
42
diff view generated by jsdifflib
[PULL 17/29] hw/arm/fsl-imx6ul: Connect watchdog interrupts
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
With this commit, the watchdog on mcimx6ul-evk is fully operational,
4
including pretimeout support.
5
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20200517162135.110364-7-linux@roeck-us.net
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/fsl-imx6ul.c | 10 ++++++++++
12
1 file changed, 10 insertions(+)
13
14
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/fsl-imx6ul.c
17
+++ b/hw/arm/fsl-imx6ul.c
18
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
19
FSL_IMX6UL_WDOG2_ADDR,
20
FSL_IMX6UL_WDOG3_ADDR,
21
};
22
+ static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
23
+ FSL_IMX6UL_WDOG1_IRQ,
24
+ FSL_IMX6UL_WDOG2_IRQ,
25
+ FSL_IMX6UL_WDOG3_IRQ,
26
+ };
27
28
+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
29
+ &error_abort);
30
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
31
&error_abort);
32
33
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
34
FSL_IMX6UL_WDOGn_ADDR[i]);
35
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
36
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
37
+ FSL_IMX6UL_WDOGn_IRQ[i]));
38
}
39
40
/*
41
--
42
2.20.1
43
44
diff view generated by jsdifflib
[PULL 18/29] hw/arm/fsl-imx7: Instantiate various unimplemented devices
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
Instantiating PWM, CAN, CAAM, and OCOTP devices is necessary to avoid
4
crashes when booting mainline Linux.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20200517162135.110364-8-linux@roeck-us.net
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/fsl-imx7.h | 16 ++++++++++++++++
12
hw/arm/fsl-imx7.c | 24 ++++++++++++++++++++++++
13
2 files changed, 40 insertions(+)
14
15
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/fsl-imx7.h
18
+++ b/include/hw/arm/fsl-imx7.h
19
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
20
FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000,
21
FSL_IMX7_IOMUXCn_SIZE = 0x1000,
22
23
+ FSL_IMX7_OCOTP_ADDR = 0x30350000,
24
+ FSL_IMX7_OCOTP_SIZE = 0x10000,
25
+
26
FSL_IMX7_ANALOG_ADDR = 0x30360000,
27
FSL_IMX7_SNVS_ADDR = 0x30370000,
28
FSL_IMX7_CCM_ADDR = 0x30380000,
29
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
30
FSL_IMX7_ADC2_ADDR = 0x30620000,
31
FSL_IMX7_ADCn_SIZE = 0x1000,
32
33
+ FSL_IMX7_PWM1_ADDR = 0x30660000,
34
+ FSL_IMX7_PWM2_ADDR = 0x30670000,
35
+ FSL_IMX7_PWM3_ADDR = 0x30680000,
36
+ FSL_IMX7_PWM4_ADDR = 0x30690000,
37
+ FSL_IMX7_PWMn_SIZE = 0x10000,
38
+
39
FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
40
FSL_IMX7_PCIE_PHY_SIZE = 0x10000,
41
42
FSL_IMX7_GPC_ADDR = 0x303A0000,
43
44
+ FSL_IMX7_CAAM_ADDR = 0x30900000,
45
+ FSL_IMX7_CAAM_SIZE = 0x40000,
46
+
47
+ FSL_IMX7_CAN1_ADDR = 0x30A00000,
48
+ FSL_IMX7_CAN2_ADDR = 0x30A10000,
49
+ FSL_IMX7_CANn_SIZE = 0x10000,
50
+
51
FSL_IMX7_I2C1_ADDR = 0x30A20000,
52
FSL_IMX7_I2C2_ADDR = 0x30A30000,
53
FSL_IMX7_I2C3_ADDR = 0x30A40000,
54
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/arm/fsl-imx7.c
57
+++ b/hw/arm/fsl-imx7.c
58
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
59
*/
60
create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR, FSL_IMX7_SDMA_SIZE);
61
62
+ /*
63
+ * CAAM
64
+ */
65
+ create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
66
+
67
+ /*
68
+ * PWM
69
+ */
70
+ create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
71
+ create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
72
+ create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
73
+ create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
74
+
75
+ /*
76
+ * CAN
77
+ */
78
+ create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
79
+ create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
80
+
81
+ /*
82
+ * OCOTP
83
+ */
84
+ create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
85
+ FSL_IMX7_OCOTP_SIZE);
86
87
object_property_set_bool(OBJECT(&s->gpr), true, "realized",
88
&error_abort);
89
--
90
2.20.1
91
92
diff view generated by jsdifflib
[PULL 19/29] hw/arm/fsl-imx7: Connect watchdog interrupts
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
i.MX7 supports watchdog pretimeout interupts. With this commit,
4
the watchdog in mcimx7d-sabre is fully operational, including
5
pretimeout support.
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
9
Message-id: 20200517162135.110364-9-linux@roeck-us.net
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/arm/fsl-imx7.h | 5 +++++
13
hw/arm/fsl-imx7.c | 11 +++++++++++
14
2 files changed, 16 insertions(+)
15
16
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/fsl-imx7.h
19
+++ b/include/hw/arm/fsl-imx7.h
20
@@ -XXX,XX +XXX,XX @@ enum FslIMX7IRQs {
21
FSL_IMX7_USB2_IRQ = 42,
22
FSL_IMX7_USB3_IRQ = 40,
23
24
+ FSL_IMX7_WDOG1_IRQ = 78,
25
+ FSL_IMX7_WDOG2_IRQ = 79,
26
+ FSL_IMX7_WDOG3_IRQ = 10,
27
+ FSL_IMX7_WDOG4_IRQ = 109,
28
+
29
FSL_IMX7_PCI_INTA_IRQ = 125,
30
FSL_IMX7_PCI_INTB_IRQ = 124,
31
FSL_IMX7_PCI_INTC_IRQ = 123,
32
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/fsl-imx7.c
35
+++ b/hw/arm/fsl-imx7.c
36
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
37
FSL_IMX7_WDOG3_ADDR,
38
FSL_IMX7_WDOG4_ADDR,
39
};
40
+ static const int FSL_IMX7_WDOGn_IRQ[FSL_IMX7_NUM_WDTS] = {
41
+ FSL_IMX7_WDOG1_IRQ,
42
+ FSL_IMX7_WDOG2_IRQ,
43
+ FSL_IMX7_WDOG3_IRQ,
44
+ FSL_IMX7_WDOG4_IRQ,
45
+ };
46
47
+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
48
+ &error_abort);
49
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
50
&error_abort);
51
52
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);
53
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
54
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
55
+ FSL_IMX7_WDOGn_IRQ[i]));
56
}
57
58
/*
59
--
60
2.20.1
61
62
diff view generated by jsdifflib
[PULL 20/29] hw/arm/integratorcp: Replace hw_error() by qemu_log_mask()
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
hw_error() calls exit(). This a bit overkill when we can log
4
the accesses as unimplemented or guest error.
5
6
When fuzzing the devices, we don't want the whole process to
7
exit. Replace some hw_error() calls by qemu_log_mask().
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 20200518140309.5220-2-f4bug@amsat.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/integratorcp.c | 23 +++++++++++++++--------
15
1 file changed, 15 insertions(+), 8 deletions(-)
16
17
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/integratorcp.c
20
+++ b/hw/arm/integratorcp.c
21
@@ -XXX,XX +XXX,XX @@
22
#include "exec/address-spaces.h"
23
#include "sysemu/runstate.h"
24
#include "sysemu/sysemu.h"
25
+#include "qemu/log.h"
26
#include "qemu/error-report.h"
27
#include "hw/char/pl011.h"
28
#include "hw/hw.h"
29
@@ -XXX,XX +XXX,XX @@ static uint64_t integratorcm_read(void *opaque, hwaddr offset,
30
/* ??? Voltage control unimplemented. */
31
return 0;
32
default:
33
- hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
34
- (int)offset);
35
+ qemu_log_mask(LOG_UNIMP,
36
+ "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n",
37
+ __func__, offset);
38
return 0;
39
}
40
}
41
@@ -XXX,XX +XXX,XX @@ static void integratorcm_write(void *opaque, hwaddr offset,
42
/* ??? Voltage control unimplemented. */
43
break;
44
default:
45
- hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
46
- (int)offset);
47
+ qemu_log_mask(LOG_UNIMP,
48
+ "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n",
49
+ __func__, offset);
50
break;
51
}
52
}
53
@@ -XXX,XX +XXX,XX @@ static uint64_t icp_pic_read(void *opaque, hwaddr offset,
54
case 5: /* INT_SOFTCLR */
55
case 11: /* FRQ_ENABLECLR */
56
default:
57
- printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
58
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
59
+ __func__, offset);
60
return 0;
61
}
62
}
63
@@ -XXX,XX +XXX,XX @@ static void icp_pic_write(void *opaque, hwaddr offset,
64
case 8: /* FRQ_STATUS */
65
case 9: /* FRQ_RAWSTAT */
66
default:
67
- printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
68
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
69
+ __func__, offset);
70
return;
71
}
72
icp_pic_update(s);
73
@@ -XXX,XX +XXX,XX @@ static uint64_t icp_control_read(void *opaque, hwaddr offset,
74
case 3: /* CP_DECODE */
75
return 0x11;
76
default:
77
- hw_error("icp_control_read: Bad offset %x\n", (int)offset);
78
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
79
+ __func__, offset);
80
return 0;
81
}
82
}
83
@@ -XXX,XX +XXX,XX @@ static void icp_control_write(void *opaque, hwaddr offset,
84
/* Nothing interesting implemented yet. */
85
break;
86
default:
87
- hw_error("icp_control_write: Bad offset %x\n", (int)offset);
88
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
89
+ __func__, offset);
90
}
91
}
92
93
--
94
2.20.1
95
96
diff view generated by jsdifflib
[PULL 21/29] hw/arm/pxa2xx: Replace hw_error() by qemu_log_mask()
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
hw_error() calls exit(). This a bit overkill when we can log
4
the accesses as unimplemented or guest error.
5
6
When fuzzing the devices, we don't want the whole process to
7
exit. Replace some hw_error() calls by qemu_log_mask().
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 20200518140309.5220-3-f4bug@amsat.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/pxa2xx_gpio.c | 7 ++++---
15
hw/display/pxa2xx_lcd.c | 8 +++++---
16
hw/dma/pxa2xx_dma.c | 14 +++++++++-----
17
3 files changed, 18 insertions(+), 11 deletions(-)
18
19
diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/pxa2xx_gpio.c
22
+++ b/hw/arm/pxa2xx_gpio.c
23
@@ -XXX,XX +XXX,XX @@
24
25
#include "qemu/osdep.h"
26
#include "cpu.h"
27
-#include "hw/hw.h"
28
#include "hw/irq.h"
29
#include "hw/qdev-properties.h"
30
#include "hw/sysbus.h"
31
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
32
return s->status[bank];
33
34
default:
35
- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
36
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
37
+ __func__, offset);
38
}
39
40
return 0;
41
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
42
break;
43
44
default:
45
- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
46
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
47
+ __func__, offset);
48
}
49
}
50
51
diff --git a/hw/display/pxa2xx_lcd.c b/hw/display/pxa2xx_lcd.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/display/pxa2xx_lcd.c
54
+++ b/hw/display/pxa2xx_lcd.c
55
@@ -XXX,XX +XXX,XX @@
56
*/
57
58
#include "qemu/osdep.h"
59
-#include "hw/hw.h"
60
+#include "qemu/log.h"
61
#include "hw/irq.h"
62
#include "migration/vmstate.h"
63
#include "ui/console.h"
64
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_lcdc_read(void *opaque, hwaddr offset,
65
66
default:
67
fail:
68
- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
69
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
70
+ __func__, offset);
71
}
72
73
return 0;
74
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
75
76
default:
77
fail:
78
- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
79
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
80
+ __func__, offset);
81
}
82
}
83
84
diff --git a/hw/dma/pxa2xx_dma.c b/hw/dma/pxa2xx_dma.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/hw/dma/pxa2xx_dma.c
87
+++ b/hw/dma/pxa2xx_dma.c
88
@@ -XXX,XX +XXX,XX @@
89
*/
90
91
#include "qemu/osdep.h"
92
+#include "qemu/log.h"
93
#include "hw/hw.h"
94
#include "hw/irq.h"
95
#include "hw/qdev-properties.h"
96
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
97
unsigned int channel;
98
99
if (size != 4) {
100
- hw_error("%s: Bad access width\n", __func__);
101
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n",
102
+ __func__, size);
103
return 5;
104
}
105
106
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
107
return s->chan[channel].cmd;
108
}
109
}
110
-
111
- hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
112
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
113
+ __func__, offset);
114
return 7;
115
}
116
117
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset,
118
unsigned int channel;
119
120
if (size != 4) {
121
- hw_error("%s: Bad access width\n", __func__);
122
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n",
123
+ __func__, size);
124
return;
125
}
126
127
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset,
128
break;
129
}
130
fail:
131
- hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __func__, offset);
132
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
133
+ __func__, offset);
134
}
135
}
136
137
--
138
2.20.1
139
140
diff view generated by jsdifflib
[PULL 24/29] ARM: PL061: Introduce N_GPIOS
Deleted patch
1
From: Geert Uytterhoeven <geert+renesas@glider.be>
2
1
3
Add a definition for the number of GPIO lines controlled by a PL061
4
instance, and use it instead of the hardcoded magic value 8.
5
6
Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20200519085143.1376-1-geert+renesas@glider.be
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/gpio/pl061.c | 12 +++++++-----
13
1 file changed, 7 insertions(+), 5 deletions(-)
14
15
diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/gpio/pl061.c
18
+++ b/hw/gpio/pl061.c
19
@@ -XXX,XX +XXX,XX @@ static const uint8_t pl061_id_luminary[12] =
20
#define TYPE_PL061 "pl061"
21
#define PL061(obj) OBJECT_CHECK(PL061State, (obj), TYPE_PL061)
22
23
+#define N_GPIOS 8
24
+
25
typedef struct PL061State {
26
SysBusDevice parent_obj;
27
28
@@ -XXX,XX +XXX,XX @@ typedef struct PL061State {
29
uint32_t cr;
30
uint32_t amsel;
31
qemu_irq irq;
32
- qemu_irq out[8];
33
+ qemu_irq out[N_GPIOS];
34
const unsigned char *id;
35
uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */
36
} PL061State;
37
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
38
changed = s->old_out_data ^ out;
39
if (changed) {
40
s->old_out_data = out;
41
- for (i = 0; i < 8; i++) {
42
+ for (i = 0; i < N_GPIOS; i++) {
43
mask = 1 << i;
44
if (changed & mask) {
45
DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
46
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
47
changed = (s->old_in_data ^ s->data) & ~s->dir;
48
if (changed) {
49
s->old_in_data = s->data;
50
- for (i = 0; i < 8; i++) {
51
+ for (i = 0; i < N_GPIOS; i++) {
52
mask = 1 << i;
53
if (changed & mask) {
54
DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0);
55
@@ -XXX,XX +XXX,XX @@ static void pl061_init(Object *obj)
56
memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000);
57
sysbus_init_mmio(sbd, &s->iomem);
58
sysbus_init_irq(sbd, &s->irq);
59
- qdev_init_gpio_in(dev, pl061_set_irq, 8);
60
- qdev_init_gpio_out(dev, s->out, 8);
61
+ qdev_init_gpio_in(dev, pl061_set_irq, N_GPIOS);
62
+ qdev_init_gpio_out(dev, s->out, N_GPIOS);
63
}
64
65
static void pl061_class_init(ObjectClass *klass, void *data)
66
--
67
2.20.1
68
69
diff view generated by jsdifflib
[PULL 25/29] target/arm: Use tcg_gen_gvec_mov for clear_vec_high
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
The 8-byte store for the end a !is_q operation can be
4
merged with the other stores. Use a no-op vector move
5
to trigger the expand_clr portion of tcg_gen_gvec_mov.
6
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200519212453.28494-2-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-a64.c | 10 ++--------
13
1 file changed, 2 insertions(+), 8 deletions(-)
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
19
@@ -XXX,XX +XXX,XX @@ static void clear_vec_high(DisasContext *s, bool is_q, int rd)
20
unsigned ofs = fp_reg_offset(s, rd, MO_64);
21
unsigned vsz = vec_full_reg_size(s);
22
23
- if (!is_q) {
24
- TCGv_i64 tcg_zero = tcg_const_i64(0);
25
- tcg_gen_st_i64(tcg_zero, cpu_env, ofs + 8);
26
- tcg_temp_free_i64(tcg_zero);
27
- }
28
- if (vsz > 16) {
29
- tcg_gen_gvec_dup_imm(MO_64, ofs + 16, vsz - 16, vsz - 16, 0);
30
- }
31
+ /* Nop move, with side effect of clearing the tail. */
32
+ tcg_gen_gvec_mov(MO_64, ofs, ofs, is_q ? 16 : 8, vsz);
33
}
34
35
void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
36
--
37
2.20.1
38
39
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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