[PULL 00/29] target-arm queue
[PULL 00/35] target-arm queue
1
target-arm queue: nothing big, just a collection of minor things.
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The following changes since commit 5767815218efd3cbfd409505ed824d5f356044ae:
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2
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-- PMM
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Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2024-02-14 15:45:52 +0000)
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The following changes since commit ae3aa5da96f4ccf0c2a28851449d92db9fcfad71:
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7
Merge remote-tracking branch 'remotes/berrange/tags/socket-next-pull-request' into staging (2020-05-21 16:47:28 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200521
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240215
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for you to fetch changes up to 17b5df7b65d0192c5d775b5e1581518580774c77:
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for you to fetch changes up to f780e63fe731b058fe52d43653600d8729a1b5f2:
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15
linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 (2020-05-21 20:00:19 +0100)
11
docs: Add documentation for the mps3-an536 board (2024-02-15 14:32:39 +0000)
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12
17
----------------------------------------------------------------
13
----------------------------------------------------------------
18
target-arm queue:
14
target-arm queue:
19
* tests/acceptance: Add a test for the canon-a1100 machine
15
* hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
20
* docs/system: Document some of the Arm development boards
16
* linux-user/aarch64: Choose SYNC as the preferred MTE mode
21
* linux-user: make BKPT insn cause SIGTRAP, not be a syscall
17
* Fix some errors in SVE/SME handling of MTE tags
22
* target/arm: Remove unused GEN_NEON_INTEGER_OP macro
18
* hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
23
* fsl-imx25, fsl-imx31, fsl-imx6, fsl-imx6ul, fsl-imx7: implement watchdog
19
* hw/block/tc58128: Don't emit deprecation warning under qtest
24
* hw/arm: Use qemu_log_mask() instead of hw_error() in various places
20
* tests/qtest: Fix handling of npcm7xx and GMAC tests
25
* ARM: PL061: Introduce N_GPIOS
21
* hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
26
* target/arm: Improve clear_vec_high() usage
22
* tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
27
* target/arm: Allow user-mode code to write CPSR.E via MSR
23
* Don't assert on vmload/vmsave of M-profile CPUs
28
* linux-user/arm: Reset CPSR_E when entering a signal handler
24
* hw/arm/smmuv3: add support for stage 1 access fault
29
* linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32
25
* hw/arm/stellaris: QOM cleanups
26
* Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
27
* Improve Cortex_R52 IMPDEF sysreg modelling
28
* Allow access to SPSR_hyp from hyp mode
29
* New board model mps3-an536 (Cortex-R52)
30
30
31
----------------------------------------------------------------
31
----------------------------------------------------------------
32
Amanieu d'Antras (1):
32
Luc Michel (1):
33
linux-user/arm: Reset CPSR_E when entering a signal handler
33
hw/arm/smmuv3: add support for stage 1 access fault
34
34
35
Geert Uytterhoeven (1):
35
Nabih Estefan (1):
36
ARM: PL061: Introduce N_GPIOS
36
tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
37
37
38
Guenter Roeck (8):
38
Peter Maydell (22):
39
hw: Move i.MX watchdog driver to hw/watchdog
39
hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
40
hw/watchdog: Implement full i.MX watchdog support
40
hw/block/tc58128: Don't emit deprecation warning under qtest
41
hw/arm/fsl-imx25: Wire up watchdog
41
tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
42
hw/arm/fsl-imx31: Wire up watchdog
42
tests/qtest/bios-tables-test: Allow changes to virt GTDT
43
hw/arm/fsl-imx6: Connect watchdog interrupts
43
hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
44
hw/arm/fsl-imx6ul: Connect watchdog interrupts
44
tests/qtest/bios-tables-tests: Update virt golden reference
45
hw/arm/fsl-imx7: Instantiate various unimplemented devices
45
hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
46
hw/arm/fsl-imx7: Connect watchdog interrupts
46
tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
47
target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
48
target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
49
target/arm: The Cortex-R52 has a read-only CBAR
50
target/arm: Add Cortex-R52 IMPDEF sysregs
51
target/arm: Allow access to SPSR_hyp from hyp mode
52
hw/misc/mps2-scc: Fix condition for CFG3 register
53
hw/misc/mps2-scc: Factor out which-board conditionals
54
hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
55
hw/arm/mps3r: Initial skeleton for mps3-an536 board
56
hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
57
hw/arm/mps3r: Add UARTs
58
hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
59
hw/arm/mps3r: Add remaining devices
60
docs: Add documentation for the mps3-an536 board
47
61
48
Peter Maydell (12):
62
Philippe Mathieu-Daudé (5):
49
docs/system: Add 'Arm' to the Integrator/CP document title
63
hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
50
docs/system: Sort Arm board index into alphabetical order
64
hw/arm/stellaris: Convert ADC controller to Resettable interface
51
docs/system: Document Arm Versatile Express boards
65
hw/arm/stellaris: Convert I2C controller to Resettable interface
52
docs/system: Document the various MPS2 models
66
hw/arm/stellaris: Add missing QOM 'machine' parent
53
docs/system: Document Musca boards
67
hw/arm/stellaris: Add missing QOM 'SoC' parent
54
linux-user/arm: BKPT should cause SIGTRAP, not be a syscall
55
linux-user/arm: Remove bogus SVC 0xf0002 handling
56
linux-user/arm: Handle invalid arm-specific syscalls correctly
57
linux-user/arm: Fix identification of syscall numbers
58
target/arm: Remove unused GEN_NEON_INTEGER_OP macro
59
target/arm: Allow user-mode code to write CPSR.E via MSR
60
linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32
61
68
62
Philippe Mathieu-Daudé (4):
69
Richard Henderson (6):
63
hw/arm/integratorcp: Replace hw_error() by qemu_log_mask()
70
linux-user/aarch64: Choose SYNC as the preferred MTE mode
64
hw/arm/pxa2xx: Replace hw_error() by qemu_log_mask()
71
target/arm: Fix nregs computation in do_{ld,st}_zpa
65
hw/char/xilinx_uartlite: Replace hw_error() by qemu_log_mask()
72
target/arm: Adjust and validate mtedesc sizem1
66
hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask()
73
target/arm: Split out make_svemte_desc
74
target/arm: Handle mte in do_ldrq, do_ldro
75
target/arm: Fix SVE/SME gross MTE suppression checks
67
76
68
Richard Henderson (2):
77
MAINTAINERS | 3 +-
69
target/arm: Use tcg_gen_gvec_mov for clear_vec_high
78
docs/system/arm/mps2.rst | 37 +-
70
target/arm: Use clear_vec_high more effectively
79
configs/devices/arm-softmmu/default.mak | 1 +
80
hw/arm/smmuv3-internal.h | 1 +
81
include/hw/arm/smmu-common.h | 1 +
82
include/hw/arm/virt.h | 2 +
83
include/hw/misc/mps2-scc.h | 1 +
84
linux-user/aarch64/target_prctl.h | 29 +-
85
target/arm/internals.h | 2 +-
86
target/arm/tcg/translate-a64.h | 2 +
87
hw/arm/mps3r.c | 640 ++++++++++++++++++++++++++++++++
88
hw/arm/npcm7xx.c | 1 +
89
hw/arm/smmu-common.c | 11 +
90
hw/arm/smmuv3.c | 1 +
91
hw/arm/stellaris.c | 47 ++-
92
hw/arm/virt-acpi-build.c | 20 +-
93
hw/arm/virt.c | 60 ++-
94
hw/arm/xilinx_zynq.c | 2 +
95
hw/block/tc58128.c | 4 +-
96
hw/misc/mps2-scc.c | 138 ++++++-
97
hw/pci-host/raven.c | 1 +
98
target/arm/helper.c | 14 +-
99
target/arm/tcg/cpu32.c | 109 ++++++
100
target/arm/tcg/op_helper.c | 43 ++-
101
target/arm/tcg/sme_helper.c | 8 +-
102
target/arm/tcg/sve_helper.c | 12 +-
103
target/arm/tcg/translate-sme.c | 15 +-
104
target/arm/tcg/translate-sve.c | 83 +++--
105
target/arm/tcg/translate.c | 19 +-
106
tests/qtest/npcm7xx_emc-test.c | 5 +-
107
tests/qtest/npcm_gmac-test.c | 84 +----
108
hw/arm/Kconfig | 5 +
109
hw/arm/meson.build | 1 +
110
tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes
111
tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes
112
tests/qtest/meson.build | 4 +-
113
36 files changed, 1184 insertions(+), 222 deletions(-)
114
create mode 100644 hw/arm/mps3r.c
71
115
72
Thomas Huth (1):
73
tests/acceptance: Add a test for the canon-a1100 machine
74
75
docs/system/arm/integratorcp.rst | 4 +-
76
docs/system/arm/mps2.rst | 29 +++
77
docs/system/arm/musca.rst | 31 +++
78
docs/system/arm/vexpress.rst | 60 ++++++
79
docs/system/target-arm.rst | 20 +-
80
include/hw/arm/fsl-imx25.h | 5 +
81
include/hw/arm/fsl-imx31.h | 4 +
82
include/hw/arm/fsl-imx6.h | 2 +-
83
include/hw/arm/fsl-imx6ul.h | 2 +-
84
include/hw/arm/fsl-imx7.h | 23 ++-
85
include/hw/misc/imx2_wdt.h | 33 ----
86
include/hw/watchdog/wdt_imx2.h | 90 +++++++++
87
target/arm/cpu.h | 2 +-
88
hw/arm/fsl-imx25.c | 10 +
89
hw/arm/fsl-imx31.c | 6 +
90
hw/arm/fsl-imx6.c | 9 +
91
hw/arm/fsl-imx6ul.c | 10 +
92
hw/arm/fsl-imx7.c | 35 ++++
93
hw/arm/integratorcp.c | 23 ++-
94
hw/arm/pxa2xx_gpio.c | 7 +-
95
hw/char/xilinx_uartlite.c | 5 +-
96
hw/display/pxa2xx_lcd.c | 8 +-
97
hw/dma/pxa2xx_dma.c | 14 +-
98
hw/gpio/pl061.c | 12 +-
99
hw/misc/imx2_wdt.c | 90 ---------
100
hw/timer/exynos4210_mct.c | 12 +-
101
hw/watchdog/wdt_imx2.c | 303 +++++++++++++++++++++++++++++
102
linux-user/arm/cpu_loop.c | 145 ++++++++------
103
linux-user/arm/signal.c | 15 +-
104
target/arm/translate-a64.c | 63 +++---
105
target/arm/translate.c | 23 ---
106
MAINTAINERS | 6 +
107
hw/arm/Kconfig | 5 +
108
hw/misc/Makefile.objs | 1 -
109
hw/watchdog/Kconfig | 3 +
110
hw/watchdog/Makefile.objs | 1 +
111
tests/acceptance/machine_arm_canona1100.py | 35 ++++
112
37 files changed, 854 insertions(+), 292 deletions(-)
113
create mode 100644 docs/system/arm/mps2.rst
114
create mode 100644 docs/system/arm/musca.rst
115
create mode 100644 docs/system/arm/vexpress.rst
116
delete mode 100644 include/hw/misc/imx2_wdt.h
117
create mode 100644 include/hw/watchdog/wdt_imx2.h
118
delete mode 100644 hw/misc/imx2_wdt.c
119
create mode 100644 hw/watchdog/wdt_imx2.c
120
create mode 100644 tests/acceptance/machine_arm_canona1100.py
121
diff view generated by jsdifflib
[PULL 22/29] hw/char/xilinx_uartlite: Replace hw_error() by qemu_log_mask()
[PULL 01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
hw_error() calls exit(). This a bit overkill when we can log
3
Similarly to commits dadbb58f59..5ae79fe825 for other ARM boards,
4
the accesses as unimplemented or guest error.
4
connect FIQ output of the GIC CPU interfaces to the CPU.
5
5
6
When fuzzing the devices, we don't want the whole process to
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
exit. Replace some hw_error() calls by qemu_log_mask().
7
Message-id: 20240130152548.17855-1-philmd@linaro.org
8
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-id: 20200518140309.5220-4-f4bug@amsat.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
10
---
15
hw/char/xilinx_uartlite.c | 5 +++--
11
hw/arm/xilinx_zynq.c | 2 ++
16
1 file changed, 3 insertions(+), 2 deletions(-)
12
1 file changed, 2 insertions(+)
17
13
18
diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c
14
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/char/xilinx_uartlite.c
16
--- a/hw/arm/xilinx_zynq.c
21
+++ b/hw/char/xilinx_uartlite.c
17
+++ b/hw/arm/xilinx_zynq.c
22
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
23
*/
19
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
24
20
sysbus_connect_irq(busdev, 0,
25
#include "qemu/osdep.h"
21
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
26
-#include "hw/hw.h"
22
+ sysbus_connect_irq(busdev, 1,
27
+#include "qemu/log.h"
23
+ qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ));
28
#include "hw/irq.h"
24
29
#include "hw/qdev-properties.h"
25
for (n = 0; n < 64; n++) {
30
#include "hw/sysbus.h"
26
pic[n] = qdev_get_gpio_in(dev, n);
31
@@ -XXX,XX +XXX,XX @@ uart_write(void *opaque, hwaddr addr,
32
switch (addr)
33
{
34
case R_STATUS:
35
- hw_error("write to UART STATUS?\n");
36
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: write to UART STATUS\n",
37
+ __func__);
38
break;
39
40
case R_CTRL:
41
--
27
--
42
2.20.1
28
2.34.1
43
29
44
30
diff view generated by jsdifflib
New patch
[PULL 02/35] linux-user/aarch64: Choose SYNC as the preferred MTE mode
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The API does not generate an error for setting ASYNC | SYNC; that merely
4
constrains the selection vs the per-cpu default. For qemu linux-user,
5
choose SYNC as the default.
6
7
Cc: qemu-stable@nongnu.org
8
Reported-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
11
Message-id: 20240207025210.8837-2-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
linux-user/aarch64/target_prctl.h | 29 +++++++++++++++++------------
15
1 file changed, 17 insertions(+), 12 deletions(-)
16
17
diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/linux-user/aarch64/target_prctl.h
20
+++ b/linux-user/aarch64/target_prctl.h
21
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
22
env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
23
24
if (cpu_isar_feature(aa64_mte, cpu)) {
25
- switch (arg2 & PR_MTE_TCF_MASK) {
26
- case PR_MTE_TCF_NONE:
27
- case PR_MTE_TCF_SYNC:
28
- case PR_MTE_TCF_ASYNC:
29
- break;
30
- default:
31
- return -EINVAL;
32
- }
33
-
34
/*
35
* Write PR_MTE_TCF to SCTLR_EL1[TCF0].
36
- * Note that the syscall values are consistent with hw.
37
+ *
38
+ * The kernel has a per-cpu configuration for the sysadmin,
39
+ * /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred,
40
+ * which qemu does not implement.
41
+ *
42
+ * Because there is no performance difference between the modes, and
43
+ * because SYNC is most useful for debugging MTE errors, choose SYNC
44
+ * as the preferred mode. With this preference, and the way the API
45
+ * uses only two bits, there is no way for the program to select
46
+ * ASYMM mode.
47
*/
48
- env->cp15.sctlr_el[1] =
49
- deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT);
50
+ unsigned tcf = 0;
51
+ if (arg2 & PR_MTE_TCF_SYNC) {
52
+ tcf = 1;
53
+ } else if (arg2 & PR_MTE_TCF_ASYNC) {
54
+ tcf = 2;
55
+ }
56
+ env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf);
57
58
/*
59
* Write PR_MTE_TAG to GCR_EL1[Exclude].
60
--
61
2.34.1
diff view generated by jsdifflib
[PULL 14/29] hw/arm/fsl-imx25: Wire up watchdog
[PULL 03/35] target/arm: Fix nregs computation in do_{ld,st}_zpa
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
With this commit, the watchdog on imx25-pdk is fully operational,
3
The field is encoded as [0-3], which is convenient for
4
including pretimeout support.
4
indexing our array of function pointers, but the true
5
value is [1-4]. Adjust before calling do_mem_zpa.
5
6
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Add an assert, and move the comment re passing ZT to
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
the helper back next to the relevant code.
8
Message-id: 20200517162135.110364-4-linux@roeck-us.net
9
10
Cc: qemu-stable@nongnu.org
11
Fixes: 206adacfb8d ("target/arm: Add mte helpers for sve scalar + int loads")
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
14
Message-id: 20240207025210.8837-3-richard.henderson@linaro.org
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
17
---
11
include/hw/arm/fsl-imx25.h | 5 +++++
18
target/arm/tcg/translate-sve.c | 16 ++++++++--------
12
hw/arm/fsl-imx25.c | 10 ++++++++++
19
1 file changed, 8 insertions(+), 8 deletions(-)
13
hw/arm/Kconfig | 1 +
14
3 files changed, 16 insertions(+)
15
20
16
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
21
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/fsl-imx25.h
23
--- a/target/arm/tcg/translate-sve.c
19
+++ b/include/hw/arm/fsl-imx25.h
24
+++ b/target/arm/tcg/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
21
#include "hw/gpio/imx_gpio.h"
26
TCGv_ptr t_pg;
22
#include "hw/sd/sdhci.h"
27
int desc = 0;
23
#include "hw/usb/chipidea.h"
28
24
+#include "hw/watchdog/wdt_imx2.h"
29
- /*
25
#include "exec/memory.h"
30
- * For e.g. LD4, there are not enough arguments to pass all 4
26
#include "target/arm/cpu.h"
31
- * registers as pointers, so encode the regno into the data field.
27
32
- * For consistency, do this even for LD1.
28
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
33
- */
29
IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
34
+ assert(mte_n >= 1 && mte_n <= 4);
30
SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
35
if (s->mte_active[0]) {
31
ChipideaState usb[FSL_IMX25_NUM_USBS];
36
int msz = dtype_msz(dtype);
32
+ IMX2WdtState wdt;
37
33
MemoryRegion rom[2];
38
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
34
MemoryRegion iram;
39
addr = clean_data_tbi(s, addr);
35
MemoryRegion iram_alias;
36
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
37
#define FSL_IMX25_GPIO1_SIZE 0x4000
38
#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
39
#define FSL_IMX25_GPIO2_SIZE 0x4000
40
+#define FSL_IMX25_WDT_ADDR 0x53FDC000
41
+#define FSL_IMX25_WDT_SIZE 0x4000
42
#define FSL_IMX25_USB1_ADDR 0x53FF4000
43
#define FSL_IMX25_USB1_SIZE 0x0200
44
#define FSL_IMX25_USB2_ADDR 0x53FF4400
45
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
46
#define FSL_IMX25_ESDHC2_IRQ 8
47
#define FSL_IMX25_USB1_IRQ 37
48
#define FSL_IMX25_USB2_IRQ 35
49
+#define FSL_IMX25_WDT_IRQ 55
50
51
#endif /* FSL_IMX25_H */
52
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/arm/fsl-imx25.c
55
+++ b/hw/arm/fsl-imx25.c
56
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
57
TYPE_CHIPIDEA);
58
}
40
}
59
41
60
+ sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), TYPE_IMX2_WDT);
42
+ /*
43
+ * For e.g. LD4, there are not enough arguments to pass all 4
44
+ * registers as pointers, so encode the regno into the data field.
45
+ * For consistency, do this even for LD1.
46
+ */
47
desc = simd_desc(vsz, vsz, zt | desc);
48
t_pg = tcg_temp_new_ptr();
49
50
@@ -XXX,XX +XXX,XX @@ static void do_ld_zpa(DisasContext *s, int zt, int pg,
51
* accessible via the instruction encoding.
52
*/
53
assert(fn != NULL);
54
- do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn);
55
+ do_mem_zpa(s, zt, pg, addr, dtype, nreg + 1, false, fn);
61
}
56
}
62
57
63
static void fsl_imx25_realize(DeviceState *dev, Error **errp)
58
static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a)
64
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
59
@@ -XXX,XX +XXX,XX @@ static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
65
usb_table[i].irq));
60
if (nreg == 0) {
61
/* ST1 */
62
fn = fn_single[s->mte_active[0]][be][msz][esz];
63
- nreg = 1;
64
} else {
65
/* ST2, ST3, ST4 -- msz == esz, enforced by encoding */
66
assert(msz == esz);
67
fn = fn_multiple[s->mte_active[0]][be][nreg - 1][msz];
66
}
68
}
67
69
assert(fn != NULL);
68
+ /* Watchdog */
70
- do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg, true, fn);
69
+ object_property_set_bool(OBJECT(&s->wdt), true, "pretimeout-support",
71
+ do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg + 1, true, fn);
70
+ &error_abort);
72
}
71
+ object_property_set_bool(OBJECT(&s->wdt), true, "realized", &error_abort);
73
72
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX25_WDT_ADDR);
74
static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a)
73
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt), 0,
74
+ qdev_get_gpio_in(DEVICE(&s->avic),
75
+ FSL_IMX25_WDT_IRQ));
76
+
77
/* initialize 2 x 16 KB ROM */
78
memory_region_init_rom(&s->rom[0], OBJECT(dev), "imx25.rom0",
79
FSL_IMX25_ROM0_SIZE, &err);
80
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
81
index XXXXXXX..XXXXXXX 100644
82
--- a/hw/arm/Kconfig
83
+++ b/hw/arm/Kconfig
84
@@ -XXX,XX +XXX,XX @@ config FSL_IMX25
85
select IMX
86
select IMX_FEC
87
select IMX_I2C
88
+ select WDT_IMX2
89
select DS1338
90
91
config FSL_IMX31
92
--
75
--
93
2.20.1
76
2.34.1
94
95
diff view generated by jsdifflib
New patch
[PULL 04/35] target/arm: Adjust and validate mtedesc sizem1
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
When we added SVE_MTEDESC_SHIFT, we effectively limited the
4
maximum size of MTEDESC. Adjust SIZEM1 to consume the remaining
5
bits (32 - 10 - 5 - 12 == 5). Assert that the data to be stored
6
fits within the field (expecting 8 * 4 - 1 == 31, exact fit).
7
8
Cc: qemu-stable@nongnu.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
12
Message-id: 20240207025210.8837-4-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/internals.h | 2 +-
16
target/arm/tcg/translate-sve.c | 7 ++++---
17
2 files changed, 5 insertions(+), 4 deletions(-)
18
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/internals.h
22
+++ b/target/arm/internals.h
23
@@ -XXX,XX +XXX,XX @@ FIELD(MTEDESC, TBI, 4, 2)
24
FIELD(MTEDESC, TCMA, 6, 2)
25
FIELD(MTEDESC, WRITE, 8, 1)
26
FIELD(MTEDESC, ALIGN, 9, 3)
27
-FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - 12) /* size - 1 */
28
+FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - SVE_MTEDESC_SHIFT - 12) /* size - 1 */
29
30
bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr);
31
uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);
32
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/tcg/translate-sve.c
35
+++ b/target/arm/tcg/translate-sve.c
36
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
37
{
38
unsigned vsz = vec_full_reg_size(s);
39
TCGv_ptr t_pg;
40
+ uint32_t sizem1;
41
int desc = 0;
42
43
assert(mte_n >= 1 && mte_n <= 4);
44
+ sizem1 = (mte_n << dtype_msz(dtype)) - 1;
45
+ assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
46
if (s->mte_active[0]) {
47
- int msz = dtype_msz(dtype);
48
-
49
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
50
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
51
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
52
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
53
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1);
54
+ desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
55
desc <<= SVE_MTEDESC_SHIFT;
56
} else {
57
addr = clean_data_tbi(s, addr);
58
--
59
2.34.1
diff view generated by jsdifflib
[PULL 25/29] target/arm: Use tcg_gen_gvec_mov for clear_vec_high
[PULL 05/35] target/arm: Split out make_svemte_desc
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The 8-byte store for the end a !is_q operation can be
3
Share code that creates mtedesc and embeds within simd_desc.
4
merged with the other stores. Use a no-op vector move
5
to trigger the expand_clr portion of tcg_gen_gvec_mov.
6
4
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200519212453.28494-2-richard.henderson@linaro.org
8
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Message-id: 20240207025210.8837-5-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
target/arm/translate-a64.c | 10 ++--------
12
target/arm/tcg/translate-a64.h | 2 ++
13
1 file changed, 2 insertions(+), 8 deletions(-)
13
target/arm/tcg/translate-sme.c | 15 +++--------
14
target/arm/tcg/translate-sve.c | 47 ++++++++++++++++++----------------
15
3 files changed, 31 insertions(+), 33 deletions(-)
14
16
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
19
--- a/target/arm/tcg/translate-a64.h
18
+++ b/target/arm/translate-a64.c
20
+++ b/target/arm/tcg/translate-a64.h
19
@@ -XXX,XX +XXX,XX @@ static void clear_vec_high(DisasContext *s, bool is_q, int rd)
21
@@ -XXX,XX +XXX,XX @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
20
unsigned ofs = fp_reg_offset(s, rd, MO_64);
22
bool sve_access_check(DisasContext *s);
21
unsigned vsz = vec_full_reg_size(s);
23
bool sme_enabled_check(DisasContext *s);
22
24
bool sme_enabled_check_with_svcr(DisasContext *s, unsigned);
23
- if (!is_q) {
25
+uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
24
- TCGv_i64 tcg_zero = tcg_const_i64(0);
26
+ uint32_t msz, bool is_write, uint32_t data);
25
- tcg_gen_st_i64(tcg_zero, cpu_env, ofs + 8);
27
26
- tcg_temp_free_i64(tcg_zero);
28
/* This function corresponds to CheckStreamingSVEEnabled. */
29
static inline bool sme_sm_enabled_check(DisasContext *s)
30
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/tcg/translate-sme.c
33
+++ b/target/arm/tcg/translate-sme.c
34
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
35
36
TCGv_ptr t_za, t_pg;
37
TCGv_i64 addr;
38
- int svl, desc = 0;
39
+ uint32_t desc;
40
bool be = s->be_data == MO_BE;
41
bool mte = s->mte_active[0];
42
43
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
44
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz);
45
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
46
47
- if (mte) {
48
- desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
49
- desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
50
- desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
51
- desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st);
52
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1);
53
- desc <<= SVE_MTEDESC_SHIFT;
54
- } else {
55
+ if (!mte) {
56
addr = clean_data_tbi(s, addr);
57
}
58
- svl = streaming_vec_reg_size(s);
59
- desc = simd_desc(svl, svl, desc);
60
+
61
+ desc = make_svemte_desc(s, streaming_vec_reg_size(s), 1, a->esz, a->st, 0);
62
63
fns[a->esz][be][a->v][mte][a->st](tcg_env, t_za, t_pg, addr,
64
tcg_constant_i32(desc));
65
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/tcg/translate-sve.c
68
+++ b/target/arm/tcg/translate-sve.c
69
@@ -XXX,XX +XXX,XX @@ static const uint8_t dtype_esz[16] = {
70
3, 2, 1, 3
71
};
72
73
-static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
74
- int dtype, uint32_t mte_n, bool is_write,
75
- gen_helper_gvec_mem *fn)
76
+uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
77
+ uint32_t msz, bool is_write, uint32_t data)
78
{
79
- unsigned vsz = vec_full_reg_size(s);
80
- TCGv_ptr t_pg;
81
uint32_t sizem1;
82
- int desc = 0;
83
+ uint32_t desc = 0;
84
85
- assert(mte_n >= 1 && mte_n <= 4);
86
- sizem1 = (mte_n << dtype_msz(dtype)) - 1;
87
+ /* Assert all of the data fits, with or without MTE enabled. */
88
+ assert(nregs >= 1 && nregs <= 4);
89
+ sizem1 = (nregs << msz) - 1;
90
assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
91
+ assert(data < 1u << SVE_MTEDESC_SHIFT);
92
+
93
if (s->mte_active[0]) {
94
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
95
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
96
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
97
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
98
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
99
desc <<= SVE_MTEDESC_SHIFT;
100
- } else {
101
+ }
102
+ return simd_desc(vsz, vsz, desc | data);
103
+}
104
+
105
+static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
106
+ int dtype, uint32_t nregs, bool is_write,
107
+ gen_helper_gvec_mem *fn)
108
+{
109
+ TCGv_ptr t_pg;
110
+ uint32_t desc;
111
+
112
+ if (!s->mte_active[0]) {
113
addr = clean_data_tbi(s, addr);
114
}
115
116
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
117
* registers as pointers, so encode the regno into the data field.
118
* For consistency, do this even for LD1.
119
*/
120
- desc = simd_desc(vsz, vsz, zt | desc);
121
+ desc = make_svemte_desc(s, vec_full_reg_size(s), nregs,
122
+ dtype_msz(dtype), is_write, zt);
123
t_pg = tcg_temp_new_ptr();
124
125
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
126
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
127
int scale, TCGv_i64 scalar, int msz, bool is_write,
128
gen_helper_gvec_mem_scatter *fn)
129
{
130
- unsigned vsz = vec_full_reg_size(s);
131
TCGv_ptr t_zm = tcg_temp_new_ptr();
132
TCGv_ptr t_pg = tcg_temp_new_ptr();
133
TCGv_ptr t_zt = tcg_temp_new_ptr();
134
- int desc = 0;
135
-
136
- if (s->mte_active[0]) {
137
- desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
138
- desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
139
- desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
140
- desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
141
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1);
142
- desc <<= SVE_MTEDESC_SHIFT;
27
- }
143
- }
28
- if (vsz > 16) {
144
- desc = simd_desc(vsz, vsz, desc | scale);
29
- tcg_gen_gvec_dup_imm(MO_64, ofs + 16, vsz - 16, vsz - 16, 0);
145
+ uint32_t desc;
30
- }
146
31
+ /* Nop move, with side effect of clearing the tail. */
147
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
32
+ tcg_gen_gvec_mov(MO_64, ofs, ofs, is_q ? 16 : 8, vsz);
148
tcg_gen_addi_ptr(t_zm, tcg_env, vec_full_reg_offset(s, zm));
149
tcg_gen_addi_ptr(t_zt, tcg_env, vec_full_reg_offset(s, zt));
150
+
151
+ desc = make_svemte_desc(s, vec_full_reg_size(s), 1, msz, is_write, scale);
152
fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
33
}
153
}
34
154
35
void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
36
--
155
--
37
2.20.1
156
2.34.1
38
39
diff view generated by jsdifflib
[PULL 28/29] linux-user/arm: Reset CPSR_E when entering a signal handler
[PULL 06/35] target/arm: Handle mte in do_ldrq, do_ldro
1
From: Amanieu d'Antras <amanieu@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This fixes signal handlers running with the wrong endianness if the
3
These functions "use the standard load helpers", but
4
interrupted code used SETEND to dynamically switch endianness.
4
fail to clean_data_tbi or populate mtedesc.
5
5
6
Signed-off-by: Amanieu d'Antras <amanieu@gmail.com>
6
Cc: qemu-stable@nongnu.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20200511131117.2486486-1-amanieu@gmail.com
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
10
Message-id: 20240207025210.8837-6-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
linux-user/arm/signal.c | 8 +++++++-
13
target/arm/tcg/translate-sve.c | 15 +++++++++++++--
12
1 file changed, 7 insertions(+), 1 deletion(-)
14
1 file changed, 13 insertions(+), 2 deletions(-)
13
15
14
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
16
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/linux-user/arm/signal.c
18
--- a/target/arm/tcg/translate-sve.c
17
+++ b/linux-user/arm/signal.c
19
+++ b/target/arm/tcg/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ setup_return(CPUARMState *env, struct target_sigaction *ka,
20
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
19
} else {
21
unsigned vsz = vec_full_reg_size(s);
20
cpsr &= ~CPSR_T;
22
TCGv_ptr t_pg;
23
int poff;
24
+ uint32_t desc;
25
26
/* Load the first quadword using the normal predicated load helpers. */
27
+ if (!s->mte_active[0]) {
28
+ addr = clean_data_tbi(s, addr);
29
+ }
30
+
31
poff = pred_full_reg_offset(s, pg);
32
if (vsz > 16) {
33
/*
34
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
35
36
gen_helper_gvec_mem *fn
37
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
38
- fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt)));
39
+ desc = make_svemte_desc(s, 16, 1, dtype_msz(dtype), false, zt);
40
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
41
42
/* Replicate that first quadword. */
43
if (vsz > 16) {
44
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
45
unsigned vsz_r32;
46
TCGv_ptr t_pg;
47
int poff, doff;
48
+ uint32_t desc;
49
50
if (vsz < 32) {
51
/*
52
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
21
}
53
}
22
+ if (env->cp15.sctlr_el[1] & SCTLR_E0E) {
54
23
+ cpsr |= CPSR_E;
55
/* Load the first octaword using the normal predicated load helpers. */
24
+ } else {
56
+ if (!s->mte_active[0]) {
25
+ cpsr &= ~CPSR_E;
57
+ addr = clean_data_tbi(s, addr);
26
+ }
58
+ }
27
59
28
if (ka->sa_flags & TARGET_SA_RESTORER) {
60
poff = pred_full_reg_offset(s, pg);
29
if (is_fdpic) {
61
if (vsz > 32) {
30
@@ -XXX,XX +XXX,XX @@ setup_return(CPUARMState *env, struct target_sigaction *ka,
62
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
31
env->regs[13] = frame_addr;
63
32
env->regs[14] = retcode;
64
gen_helper_gvec_mem *fn
33
env->regs[15] = handler & (thumb ? ~1 : ~3);
65
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
34
- cpsr_write(env, cpsr, CPSR_IT | CPSR_T, CPSRWriteByInstr);
66
- fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt)));
35
+ cpsr_write(env, cpsr, CPSR_IT | CPSR_T | CPSR_E, CPSRWriteByInstr);
67
+ desc = make_svemte_desc(s, 32, 1, dtype_msz(dtype), false, zt);
36
+ arm_rebuild_hflags(env);
68
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
37
69
38
return 0;
70
/*
39
}
71
* Replicate that first octaword.
40
--
72
--
41
2.20.1
73
2.34.1
42
43
diff view generated by jsdifflib
[PULL 26/29] target/arm: Use clear_vec_high more effectively
[PULL 07/35] target/arm: Fix SVE/SME gross MTE suppression checks
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Do not explicitly store zero to the NEON high part
3
The TBI and TCMA bits are located within mtedesc, not desc.
4
when we can pass !is_q to clear_vec_high.
5
4
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200519212453.28494-3-richard.henderson@linaro.org
8
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Message-id: 20240207025210.8837-7-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
target/arm/translate-a64.c | 53 +++++++++++++++++++++++---------------
12
target/arm/tcg/sme_helper.c | 8 ++++----
12
1 file changed, 32 insertions(+), 21 deletions(-)
13
target/arm/tcg/sve_helper.c | 12 ++++++------
14
2 files changed, 10 insertions(+), 10 deletions(-)
13
15
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
18
--- a/target/arm/tcg/sme_helper.c
17
+++ b/target/arm/translate-a64.c
19
+++ b/target/arm/tcg/sme_helper.c
18
@@ -XXX,XX +XXX,XX @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
20
@@ -XXX,XX +XXX,XX @@ void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg,
19
{
21
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
20
/* This always zero-extends and writes to a full 128 bit wide vector */
22
21
TCGv_i64 tmplo = tcg_temp_new_i64();
23
/* Perform gross MTE suppression early. */
22
- TCGv_i64 tmphi;
24
- if (!tbi_check(desc, bit55) ||
23
+ TCGv_i64 tmphi = NULL;
25
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
24
26
+ if (!tbi_check(mtedesc, bit55) ||
25
if (size < 4) {
27
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
26
MemOp memop = s->be_data + size;
28
mtedesc = 0;
27
- tmphi = tcg_const_i64(0);
28
tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop);
29
} else {
30
bool be = s->be_data == MO_BE;
31
@@ -XXX,XX +XXX,XX @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
32
}
29
}
33
30
34
tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64));
31
@@ -XXX,XX +XXX,XX @@ void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr,
35
- tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx));
32
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
36
-
33
37
tcg_temp_free_i64(tmplo);
34
/* Perform gross MTE suppression early. */
38
- tcg_temp_free_i64(tmphi);
35
- if (!tbi_check(desc, bit55) ||
39
36
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
40
- clear_vec_high(s, true, destidx);
37
+ if (!tbi_check(mtedesc, bit55) ||
41
+ if (tmphi) {
38
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
42
+ tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx));
39
mtedesc = 0;
43
+ tcg_temp_free_i64(tmphi);
44
+ }
45
+ clear_vec_high(s, tmphi != NULL, destidx);
46
}
47
48
/*
49
@@ -XXX,XX +XXX,XX @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
50
read_vec_element(s, tcg_resh, rm, 0, MO_64);
51
do_ext64(s, tcg_resh, tcg_resl, pos);
52
}
53
- tcg_gen_movi_i64(tcg_resh, 0);
54
} else {
55
TCGv_i64 tcg_hh;
56
typedef struct {
57
@@ -XXX,XX +XXX,XX @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
58
59
write_vec_element(s, tcg_resl, rd, 0, MO_64);
60
tcg_temp_free_i64(tcg_resl);
61
- write_vec_element(s, tcg_resh, rd, 1, MO_64);
62
+ if (is_q) {
63
+ write_vec_element(s, tcg_resh, rd, 1, MO_64);
64
+ }
65
tcg_temp_free_i64(tcg_resh);
66
- clear_vec_high(s, true, rd);
67
+ clear_vec_high(s, is_q, rd);
68
}
69
70
/* TBL/TBX
71
@@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
72
* the input.
73
*/
74
tcg_resl = tcg_temp_new_i64();
75
- tcg_resh = tcg_temp_new_i64();
76
+ tcg_resh = NULL;
77
78
if (is_tblx) {
79
read_vec_element(s, tcg_resl, rd, 0, MO_64);
80
} else {
81
tcg_gen_movi_i64(tcg_resl, 0);
82
}
40
}
83
- if (is_tblx && is_q) {
41
84
- read_vec_element(s, tcg_resh, rd, 1, MO_64);
42
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
85
- } else {
43
index XXXXXXX..XXXXXXX 100644
86
- tcg_gen_movi_i64(tcg_resh, 0);
44
--- a/target/arm/tcg/sve_helper.c
87
+
45
+++ b/target/arm/tcg/sve_helper.c
88
+ if (is_q) {
46
@@ -XXX,XX +XXX,XX @@ void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
89
+ tcg_resh = tcg_temp_new_i64();
47
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
90
+ if (is_tblx) {
48
91
+ read_vec_element(s, tcg_resh, rd, 1, MO_64);
49
/* Perform gross MTE suppression early. */
92
+ } else {
50
- if (!tbi_check(desc, bit55) ||
93
+ tcg_gen_movi_i64(tcg_resh, 0);
51
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
94
+ }
52
+ if (!tbi_check(mtedesc, bit55) ||
53
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
54
mtedesc = 0;
95
}
55
}
96
56
97
tcg_idx = tcg_temp_new_i64();
57
@@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r_mte(CPUARMState *env, void *vg, target_ulong addr,
98
@@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
58
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
99
59
100
write_vec_element(s, tcg_resl, rd, 0, MO_64);
60
/* Perform gross MTE suppression early. */
101
tcg_temp_free_i64(tcg_resl);
61
- if (!tbi_check(desc, bit55) ||
102
- write_vec_element(s, tcg_resh, rd, 1, MO_64);
62
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
103
- tcg_temp_free_i64(tcg_resh);
63
+ if (!tbi_check(mtedesc, bit55) ||
104
- clear_vec_high(s, true, rd);
64
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
105
+
65
mtedesc = 0;
106
+ if (is_q) {
107
+ write_vec_element(s, tcg_resh, rd, 1, MO_64);
108
+ tcg_temp_free_i64(tcg_resh);
109
+ }
110
+ clear_vec_high(s, is_q, rd);
111
}
112
113
/* ZIP/UZP/TRN
114
@@ -XXX,XX +XXX,XX @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
115
}
66
}
116
67
117
tcg_resl = tcg_const_i64(0);
68
@@ -XXX,XX +XXX,XX @@ void sve_stN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
118
- tcg_resh = tcg_const_i64(0);
69
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
119
+ tcg_resh = is_q ? tcg_const_i64(0) : NULL;
70
120
tcg_res = tcg_temp_new_i64();
71
/* Perform gross MTE suppression early. */
121
72
- if (!tbi_check(desc, bit55) ||
122
for (i = 0; i < elements; i++) {
73
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
123
@@ -XXX,XX +XXX,XX @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
74
+ if (!tbi_check(mtedesc, bit55) ||
124
75
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
125
write_vec_element(s, tcg_resl, rd, 0, MO_64);
76
mtedesc = 0;
126
tcg_temp_free_i64(tcg_resl);
77
}
127
- write_vec_element(s, tcg_resh, rd, 1, MO_64);
78
128
- tcg_temp_free_i64(tcg_resh);
129
- clear_vec_high(s, true, rd);
130
+
131
+ if (is_q) {
132
+ write_vec_element(s, tcg_resh, rd, 1, MO_64);
133
+ tcg_temp_free_i64(tcg_resh);
134
+ }
135
+ clear_vec_high(s, is_q, rd);
136
}
137
138
/*
139
--
79
--
140
2.20.1
80
2.34.1
141
142
diff view generated by jsdifflib
[PULL 02/29] docs/system: Add 'Arm' to the Integrator/CP document title
[PULL 08/35] hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
1
Add 'Arm' to the Integrator/CP document title, for consistency with
1
The raven_io_ops MemoryRegionOps is the only one in the source tree
2
the titling of the other documentation of Arm devboard models
2
which sets .valid.unaligned to indicate that it should support
3
(versatile, realview).
3
unaligned accesses and which does not also set .impl.unaligned to
4
indicate that its read and write functions can do the unaligned
5
handling themselves. This is a problem, because at the moment the
6
core memory system does not implement the support for handling
7
unaligned accesses by doing a series of aligned accesses and
8
combining them (system/memory.c:access_with_adjusted_size() has a
9
TODO comment noting this).
4
10
11
Fortunately raven_io_read() and raven_io_write() will correctly deal
12
with the case of being passed an unaligned address, so we can fix the
13
missing unaligned access support by setting .impl.unaligned in the
14
MemoryRegionOps struct.
15
16
Fixes: 9a1839164c9c8f06 ("raven: Implement non-contiguous I/O region")
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
18
Tested-by: Cédric Le Goater <clg@redhat.com>
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
19
Reviewed-by: Cédric Le Goater <clg@redhat.com>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
20
Message-id: 20240112134640.1775041-1-peter.maydell@linaro.org
9
Message-id: 20200507151819.28444-2-peter.maydell@linaro.org
10
---
21
---
11
docs/system/arm/integratorcp.rst | 4 ++--
22
hw/pci-host/raven.c | 1 +
12
1 file changed, 2 insertions(+), 2 deletions(-)
23
1 file changed, 1 insertion(+)
13
24
14
diff --git a/docs/system/arm/integratorcp.rst b/docs/system/arm/integratorcp.rst
25
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
15
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/integratorcp.rst
27
--- a/hw/pci-host/raven.c
17
+++ b/docs/system/arm/integratorcp.rst
28
+++ b/hw/pci-host/raven.c
18
@@ -XXX,XX +XXX,XX @@
29
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps raven_io_ops = {
19
-Integrator/CP (``integratorcp``)
30
.write = raven_io_write,
20
-================================
31
.endianness = DEVICE_LITTLE_ENDIAN,
21
+Arm Integrator/CP (``integratorcp``)
32
.impl.max_access_size = 4,
22
+====================================
33
+ .impl.unaligned = true,
23
34
.valid.unaligned = true,
24
The Arm Integrator/CP board is emulated with the following devices:
35
};
25
36
26
--
37
--
27
2.20.1
38
2.34.1
28
39
29
40
diff view generated by jsdifflib
[PULL 10/29] linux-user/arm: Fix identification of syscall numbers
[PULL 09/35] hw/block/tc58128: Don't emit deprecation warning under qtest
1
Our code to identify syscall numbers has some issues:
1
Suppress the deprecation warning when we're running under qtest,
2
* for Thumb mode, we never need the immediate value from the insn,
2
to avoid "make check" including warning messages in its output.
3
but we always read it anyway
4
* bad immediate values in the svc insn should cause a SIGILL, but we
5
were abort()ing instead (via "goto error")
6
7
We can fix both these things by refactoring the code that identifies
8
the syscall number to more closely follow the kernel COMPAT_OABI code:
9
* for Thumb it is always r7
10
* for Arm, if the immediate value is 0, then this is an EABI call
11
with the syscall number in r7
12
* otherwise, we XOR the immediate value with 0x900000
13
(ARM_SYSCALL_BASE for QEMU; __NR_OABI_SYSCALL_BASE in the kernel),
14
which converts valid syscall immediates into the desired value,
15
and puts all invalid immediates in the range 0x100000 or above
16
* then we can just let the existing "value too large, deliver
17
SIGILL" case handle invalid numbers, and drop the 'goto error'
18
3
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
21
Message-id: 20200420212206.12776-5-peter.maydell@linaro.org
6
Message-id: 20240206154151.155620-1-peter.maydell@linaro.org
22
---
7
---
23
linux-user/arm/cpu_loop.c | 143 ++++++++++++++++++++------------------
8
hw/block/tc58128.c | 4 +++-
24
1 file changed, 77 insertions(+), 66 deletions(-)
9
1 file changed, 3 insertions(+), 1 deletion(-)
25
10
26
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
11
diff --git a/hw/block/tc58128.c b/hw/block/tc58128.c
27
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
28
--- a/linux-user/arm/cpu_loop.c
13
--- a/hw/block/tc58128.c
29
+++ b/linux-user/arm/cpu_loop.c
14
+++ b/hw/block/tc58128.c
30
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
15
@@ -XXX,XX +XXX,XX @@ static sh7750_io_device tc58128 = {
31
env->eabi = 1;
16
32
/* system call */
17
int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2)
33
if (env->thumb) {
18
{
34
- /* FIXME - what to do if get_user() fails? */
19
- warn_report_once("The TC58128 flash device is deprecated");
35
- get_user_code_u16(insn, env->regs[15] - 2, env);
20
+ if (!qtest_enabled()) {
36
- n = insn & 0xff;
21
+ warn_report_once("The TC58128 flash device is deprecated");
37
+ /* Thumb is always EABI style with syscall number in r7 */
22
+ }
38
+ n = env->regs[7];
23
init_dev(&tc58128_devs[0], zone1);
39
} else {
24
init_dev(&tc58128_devs[1], zone2);
40
+ /*
25
return sh7750_register_io_device(s, &tc58128);
41
+ * Equivalent of kernel CONFIG_OABI_COMPAT: read the
42
+ * Arm SVC insn to extract the immediate, which is the
43
+ * syscall number in OABI.
44
+ */
45
/* FIXME - what to do if get_user() fails? */
46
get_user_code_u32(insn, env->regs[15] - 4, env);
47
n = insn & 0xffffff;
48
- }
49
-
50
- if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
51
- /* linux syscall */
52
- if (env->thumb || n == 0) {
53
+ if (n == 0) {
54
+ /* zero immediate: EABI, syscall number in r7 */
55
n = env->regs[7];
56
} else {
57
- n -= ARM_SYSCALL_BASE;
58
+ /*
59
+ * This XOR matches the kernel code: an immediate
60
+ * in the valid range (0x900000 .. 0x9fffff) is
61
+ * converted into the correct EABI-style syscall
62
+ * number; invalid immediates end up as values
63
+ * > 0xfffff and are handled below as out-of-range.
64
+ */
65
+ n ^= ARM_SYSCALL_BASE;
66
env->eabi = 0;
67
}
68
- if ( n > ARM_NR_BASE) {
69
- switch (n) {
70
- case ARM_NR_cacheflush:
71
- /* nop */
72
- break;
73
- case ARM_NR_set_tls:
74
- cpu_set_tls(env, env->regs[0]);
75
- env->regs[0] = 0;
76
- break;
77
- case ARM_NR_breakpoint:
78
- env->regs[15] -= env->thumb ? 2 : 4;
79
- goto excp_debug;
80
- case ARM_NR_get_tls:
81
- env->regs[0] = cpu_get_tls(env);
82
- break;
83
- default:
84
- if (n < 0xf0800) {
85
- /*
86
- * Syscalls 0xf0000..0xf07ff (or 0x9f0000..
87
- * 0x9f07ff in OABI numbering) are defined
88
- * to return -ENOSYS rather than raising
89
- * SIGILL. Note that we have already
90
- * removed the 0x900000 prefix.
91
- */
92
- qemu_log_mask(LOG_UNIMP,
93
- "qemu: Unsupported ARM syscall: 0x%x\n",
94
- n);
95
- env->regs[0] = -TARGET_ENOSYS;
96
+ }
97
+
98
+ if (n > ARM_NR_BASE) {
99
+ switch (n) {
100
+ case ARM_NR_cacheflush:
101
+ /* nop */
102
+ break;
103
+ case ARM_NR_set_tls:
104
+ cpu_set_tls(env, env->regs[0]);
105
+ env->regs[0] = 0;
106
+ break;
107
+ case ARM_NR_breakpoint:
108
+ env->regs[15] -= env->thumb ? 2 : 4;
109
+ goto excp_debug;
110
+ case ARM_NR_get_tls:
111
+ env->regs[0] = cpu_get_tls(env);
112
+ break;
113
+ default:
114
+ if (n < 0xf0800) {
115
+ /*
116
+ * Syscalls 0xf0000..0xf07ff (or 0x9f0000..
117
+ * 0x9f07ff in OABI numbering) are defined
118
+ * to return -ENOSYS rather than raising
119
+ * SIGILL. Note that we have already
120
+ * removed the 0x900000 prefix.
121
+ */
122
+ qemu_log_mask(LOG_UNIMP,
123
+ "qemu: Unsupported ARM syscall: 0x%x\n",
124
+ n);
125
+ env->regs[0] = -TARGET_ENOSYS;
126
+ } else {
127
+ /*
128
+ * Otherwise SIGILL. This includes any SWI with
129
+ * immediate not originally 0x9fxxxx, because
130
+ * of the earlier XOR.
131
+ */
132
+ info.si_signo = TARGET_SIGILL;
133
+ info.si_errno = 0;
134
+ info.si_code = TARGET_ILL_ILLTRP;
135
+ info._sifields._sigfault._addr = env->regs[15];
136
+ if (env->thumb) {
137
+ info._sifields._sigfault._addr -= 2;
138
} else {
139
- /* Otherwise SIGILL */
140
- info.si_signo = TARGET_SIGILL;
141
- info.si_errno = 0;
142
- info.si_code = TARGET_ILL_ILLTRP;
143
- info._sifields._sigfault._addr = env->regs[15];
144
- if (env->thumb) {
145
- info._sifields._sigfault._addr -= 2;
146
- } else {
147
- info._sifields._sigfault._addr -= 4;
148
- }
149
- queue_signal(env, info.si_signo,
150
- QEMU_SI_FAULT, &info);
151
+ info._sifields._sigfault._addr -= 4;
152
}
153
- break;
154
- }
155
- } else {
156
- ret = do_syscall(env,
157
- n,
158
- env->regs[0],
159
- env->regs[1],
160
- env->regs[2],
161
- env->regs[3],
162
- env->regs[4],
163
- env->regs[5],
164
- 0, 0);
165
- if (ret == -TARGET_ERESTARTSYS) {
166
- env->regs[15] -= env->thumb ? 2 : 4;
167
- } else if (ret != -TARGET_QEMU_ESIGRETURN) {
168
- env->regs[0] = ret;
169
+ queue_signal(env, info.si_signo,
170
+ QEMU_SI_FAULT, &info);
171
}
172
+ break;
173
}
174
} else {
175
- goto error;
176
+ ret = do_syscall(env,
177
+ n,
178
+ env->regs[0],
179
+ env->regs[1],
180
+ env->regs[2],
181
+ env->regs[3],
182
+ env->regs[4],
183
+ env->regs[5],
184
+ 0, 0);
185
+ if (ret == -TARGET_ERESTARTSYS) {
186
+ env->regs[15] -= env->thumb ? 2 : 4;
187
+ } else if (ret != -TARGET_QEMU_ESIGRETURN) {
188
+ env->regs[0] = ret;
189
+ }
190
}
191
}
192
break;
193
--
26
--
194
2.20.1
27
2.34.1
195
28
196
29
diff view generated by jsdifflib
[PULL 09/29] linux-user/arm: Handle invalid arm-specific syscalls correctly
[PULL 10/35] tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
1
The kernel has different handling for syscalls with invalid
1
We deliberately don't include qtests_npcm7xx in qtests_aarch64,
2
numbers that are in the "arm-specific" range 0x9f0000 and up:
2
because we already get the coverage of those tests via qtests_arm,
3
* 0x9f0000..0x9f07ff return -ENOSYS if not implemented
3
and we don't want to use extra CI minutes testing them twice.
4
* other out of range syscalls cause a SIGILL
5
(see the kernel's arch/arm/kernel/traps.c:arm_syscall())
6
4
7
Implement this distinction. (Note that our code doesn't look
5
In commit 327b680877b79c4b we added it to qtests_aarch64; revert
8
quite like the kernel's, because we have removed the
6
that change.
9
0x900000 prefix by this point, whereas the kernel retains
10
it in arm_syscall().)
11
7
8
Fixes: 327b680877b79c4b ("tests/qtest: Creating qtest for GMAC Module")
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Message-id: 20200420212206.12776-4-peter.maydell@linaro.org
11
Message-id: 20240206163043.315535-1-peter.maydell@linaro.org
15
---
12
---
16
linux-user/arm/cpu_loop.c | 30 ++++++++++++++++++++++++++----
13
tests/qtest/meson.build | 1 -
17
1 file changed, 26 insertions(+), 4 deletions(-)
14
1 file changed, 1 deletion(-)
18
15
19
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
16
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
20
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
21
--- a/linux-user/arm/cpu_loop.c
18
--- a/tests/qtest/meson.build
22
+++ b/linux-user/arm/cpu_loop.c
19
+++ b/tests/qtest/meson.build
23
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
20
@@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
24
env->regs[0] = cpu_get_tls(env);
21
(config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
25
break;
22
(config_all_accel.has_key('CONFIG_TCG') and \
26
default:
23
config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
27
- qemu_log_mask(LOG_UNIMP,
24
- (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
28
- "qemu: Unsupported ARM syscall: 0x%x\n",
25
['arm-cpu-features',
29
- n);
26
'numa-test',
30
- env->regs[0] = -TARGET_ENOSYS;
27
'boot-serial-test',
31
+ if (n < 0xf0800) {
32
+ /*
33
+ * Syscalls 0xf0000..0xf07ff (or 0x9f0000..
34
+ * 0x9f07ff in OABI numbering) are defined
35
+ * to return -ENOSYS rather than raising
36
+ * SIGILL. Note that we have already
37
+ * removed the 0x900000 prefix.
38
+ */
39
+ qemu_log_mask(LOG_UNIMP,
40
+ "qemu: Unsupported ARM syscall: 0x%x\n",
41
+ n);
42
+ env->regs[0] = -TARGET_ENOSYS;
43
+ } else {
44
+ /* Otherwise SIGILL */
45
+ info.si_signo = TARGET_SIGILL;
46
+ info.si_errno = 0;
47
+ info.si_code = TARGET_ILL_ILLTRP;
48
+ info._sifields._sigfault._addr = env->regs[15];
49
+ if (env->thumb) {
50
+ info._sifields._sigfault._addr -= 2;
51
+ } else {
52
+ info._sifields._sigfault._addr -= 4;
53
+ }
54
+ queue_signal(env, info.si_signo,
55
+ QEMU_SI_FAULT, &info);
56
+ }
57
break;
58
}
59
} else {
60
--
28
--
61
2.20.1
29
2.34.1
62
30
63
31
diff view generated by jsdifflib
New patch
[PULL 11/35] tests/qtest/bios-tables-test: Allow changes to virt GTDT
1
Allow changes to the virt GTDT -- we are going to add the IRQ
2
entry for a new timer to it.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
6
Message-id: 20240122143537.233498-2-peter.maydell@linaro.org
7
---
8
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
9
1 file changed, 2 insertions(+)
10
11
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tests/qtest/bios-tables-test-allowed-diff.h
14
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
15
@@ -1 +1,3 @@
16
/* List of comma-separated changed AML files to ignore */
17
+"tests/data/acpi/virt/FACP",
18
+"tests/data/acpi/virt/GTDT",
19
--
20
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/35] hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
1
1
Armv8.1+ CPUs have the Virtual Host Extension (VHE) which adds a
2
non-secure EL2 virtual timer. We implemented the timer itself in the
3
CPU model, but never wired up its IRQ line to the GIC.
4
5
Wire up the IRQ line (this is always safe whether the CPU has the
6
interrupt or not, since it always creates the outbound IRQ line).
7
Report it to the guest via dtb and ACPI if the CPU has the feature.
8
9
The DTB binding is documented in the kernel's
10
Documentation/devicetree/bindings/timer/arm\,arch_timer.yaml
11
and the ACPI table entries are documented in the ACPI specification
12
version 6.3 or later.
13
14
Because the IRQ line ACPI binding is new in 6.3, we need to bump the
15
FADT table rev to show that we might be using 6.3 features.
16
17
Note that exposing this IRQ in the DTB will trigger a bug in EDK2
18
versions prior to edk2-stable202311, for users who use the virt board
19
with 'virtualization=on' to enable EL2 emulation and are booting an
20
EDK2 guest BIOS, if that EDK2 has assertions enabled. The effect is
21
that EDK2 will assert on bootup:
22
23
ASSERT [ArmTimerDxe] /home/kraxel/projects/qemu/roms/edk2/ArmVirtPkg/Library/ArmVirtTimerFdtClientLib/ArmVirtTimerFdtClientLib.c(72): PropSize == 36 || PropSize == 48
24
25
If you see that assertion you should do one of:
26
* update your EDK2 binaries to edk2-stable202311 or newer
27
* use the 'virt-8.2' versioned machine type
28
* not use 'virtualization=on'
29
30
(The versions shipped with QEMU itself have the fix.)
31
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
34
Message-id: 20240122143537.233498-3-peter.maydell@linaro.org
35
---
36
include/hw/arm/virt.h | 2 ++
37
hw/arm/virt-acpi-build.c | 20 ++++++++++----
38
hw/arm/virt.c | 60 ++++++++++++++++++++++++++++++++++------
39
3 files changed, 67 insertions(+), 15 deletions(-)
40
41
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
42
index XXXXXXX..XXXXXXX 100644
43
--- a/include/hw/arm/virt.h
44
+++ b/include/hw/arm/virt.h
45
@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
46
/* Machines < 6.2 have no support for describing cpu topology to guest */
47
bool no_cpu_topology;
48
bool no_tcg_lpa2;
49
+ bool no_ns_el2_virt_timer_irq;
50
};
51
52
struct VirtMachineState {
53
@@ -XXX,XX +XXX,XX @@ struct VirtMachineState {
54
PCIBus *bus;
55
char *oem_id;
56
char *oem_table_id;
57
+ bool ns_el2_virt_timer_irq;
58
};
59
60
#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
61
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/hw/arm/virt-acpi-build.c
64
+++ b/hw/arm/virt-acpi-build.c
65
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
66
}
67
68
/*
69
- * ACPI spec, Revision 5.1
70
- * 5.2.24 Generic Timer Description Table (GTDT)
71
+ * ACPI spec, Revision 6.5
72
+ * 5.2.25 Generic Timer Description Table (GTDT)
73
*/
74
static void
75
build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
76
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
77
uint32_t irqflags = vmc->claim_edge_triggered_timers ?
78
1 : /* Interrupt is Edge triggered */
79
0; /* Interrupt is Level triggered */
80
- AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id,
81
+ AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id,
82
.oem_table_id = vms->oem_table_id };
83
84
acpi_table_begin(&table, table_data);
85
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
86
build_append_int_noprefix(table_data, 0, 4);
87
/* Platform Timer Offset */
88
build_append_int_noprefix(table_data, 0, 4);
89
-
90
+ if (vms->ns_el2_virt_timer_irq) {
91
+ /* Virtual EL2 Timer GSIV */
92
+ build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4);
93
+ /* Virtual EL2 Timer Flags */
94
+ build_append_int_noprefix(table_data, irqflags, 4);
95
+ } else {
96
+ build_append_int_noprefix(table_data, 0, 4);
97
+ build_append_int_noprefix(table_data, 0, 4);
98
+ }
99
acpi_table_end(linker, &table);
100
}
101
102
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
103
static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
104
VirtMachineState *vms, unsigned dsdt_tbl_offset)
105
{
106
- /* ACPI v6.0 */
107
+ /* ACPI v6.3 */
108
AcpiFadtData fadt = {
109
.rev = 6,
110
- .minor_ver = 0,
111
+ .minor_ver = 3,
112
.flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
113
.xdsdt_tbl_offset = &dsdt_tbl_offset,
114
};
115
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
116
index XXXXXXX..XXXXXXX 100644
117
--- a/hw/arm/virt.c
118
+++ b/hw/arm/virt.c
119
@@ -XXX,XX +XXX,XX @@ static void create_randomness(MachineState *ms, const char *node)
120
qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
121
}
122
123
+/*
124
+ * The CPU object always exposes the NS EL2 virt timer IRQ line,
125
+ * but we don't want to advertise it to the guest in the dtb or ACPI
126
+ * table unless it's really going to do something.
127
+ */
128
+static bool ns_el2_virt_timer_present(void)
129
+{
130
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
131
+ CPUARMState *env = &cpu->env;
132
+
133
+ return arm_feature(env, ARM_FEATURE_AARCH64) &&
134
+ arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu);
135
+}
136
+
137
static void create_fdt(VirtMachineState *vms)
138
{
139
MachineState *ms = MACHINE(vms);
140
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
141
"arm,armv7-timer");
142
}
143
qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
144
- qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
145
- GIC_FDT_IRQ_TYPE_PPI,
146
- INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
147
- GIC_FDT_IRQ_TYPE_PPI,
148
- INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
149
- GIC_FDT_IRQ_TYPE_PPI,
150
- INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
151
- GIC_FDT_IRQ_TYPE_PPI,
152
- INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
153
+ if (vms->ns_el2_virt_timer_irq) {
154
+ qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
155
+ GIC_FDT_IRQ_TYPE_PPI,
156
+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
157
+ GIC_FDT_IRQ_TYPE_PPI,
158
+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
159
+ GIC_FDT_IRQ_TYPE_PPI,
160
+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
161
+ GIC_FDT_IRQ_TYPE_PPI,
162
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags,
163
+ GIC_FDT_IRQ_TYPE_PPI,
164
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags);
165
+ } else {
166
+ qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
167
+ GIC_FDT_IRQ_TYPE_PPI,
168
+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
169
+ GIC_FDT_IRQ_TYPE_PPI,
170
+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
171
+ GIC_FDT_IRQ_TYPE_PPI,
172
+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
173
+ GIC_FDT_IRQ_TYPE_PPI,
174
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
175
+ }
176
}
177
178
static void fdt_add_cpu_nodes(const VirtMachineState *vms)
179
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
180
[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
181
[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
182
[GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
183
+ [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
184
};
185
186
for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
187
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
188
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
189
object_unref(cpuobj);
190
}
191
+
192
+ /* Now we've created the CPUs we can see if they have the hypvirt timer */
193
+ vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() &&
194
+ !vmc->no_ns_el2_virt_timer_irq;
195
+
196
fdt_add_timer_nodes(vms);
197
fdt_add_cpu_nodes(vms);
198
199
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(9, 0)
200
201
static void virt_machine_8_2_options(MachineClass *mc)
202
{
203
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
204
+
205
virt_machine_9_0_options(mc);
206
compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
207
+ /*
208
+ * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and
209
+ * earlier machines. (Exposing it tickles a bug in older EDK2
210
+ * guest BIOS binaries.)
211
+ */
212
+ vmc->no_ns_el2_virt_timer_irq = true;
213
}
214
DEFINE_VIRT_MACHINE(8, 2)
215
216
--
217
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/35] tests/qtest/bios-tables-tests: Update virt golden reference
1
1
Update the virt golden reference files to say that the FACP is ACPI
2
v6.3, and the GTDT table is a revision 3 table with space for the
3
virtual EL2 timer.
4
5
Diffs from iasl:
6
7
@@ -XXX,XX +XXX,XX @@
8
/*
9
* Intel ACPI Component Architecture
10
* AML/ASL+ Disassembler version 20200925 (64-bit version)
11
* Copyright (c) 2000 - 2020 Intel Corporation
12
*
13
- * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 22 13:48:40 2024
14
+ * Disassembly of /tmp/aml-W8RZH2, Mon Jan 22 13:48:40 2024
15
*
16
* ACPI Data Table [FACP]
17
*
18
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
19
*/
20
21
[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
22
[004h 0004 4] Table Length : 00000114
23
[008h 0008 1] Revision : 06
24
-[009h 0009 1] Checksum : 15
25
+[009h 0009 1] Checksum : 12
26
[00Ah 0010 6] Oem ID : "BOCHS "
27
[010h 0016 8] Oem Table ID : "BXPC "
28
[018h 0024 4] Oem Revision : 00000001
29
[01Ch 0028 4] Asl Compiler ID : "BXPC"
30
[020h 0032 4] Asl Compiler Revision : 00000001
31
32
[024h 0036 4] FACS Address : 00000000
33
[028h 0040 4] DSDT Address : 00000000
34
[02Ch 0044 1] Model : 00
35
[02Dh 0045 1] PM Profile : 00 [Unspecified]
36
[02Eh 0046 2] SCI Interrupt : 0000
37
[030h 0048 4] SMI Command Port : 00000000
38
[034h 0052 1] ACPI Enable Value : 00
39
[035h 0053 1] ACPI Disable Value : 00
40
[036h 0054 1] S4BIOS Command : 00
41
[037h 0055 1] P-State Control : 00
42
@@ -XXX,XX +XXX,XX @@
43
Use APIC Physical Destination Mode (V4) : 0
44
Hardware Reduced (V5) : 1
45
Low Power S0 Idle (V5) : 0
46
47
[074h 0116 12] Reset Register : [Generic Address Structure]
48
[074h 0116 1] Space ID : 00 [SystemMemory]
49
[075h 0117 1] Bit Width : 00
50
[076h 0118 1] Bit Offset : 00
51
[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
52
[078h 0120 8] Address : 0000000000000000
53
54
[080h 0128 1] Value to cause reset : 00
55
[081h 0129 2] ARM Flags (decoded below) : 0003
56
PSCI Compliant : 1
57
Must use HVC for PSCI : 1
58
59
-[083h 0131 1] FADT Minor Revision : 00
60
+[083h 0131 1] FADT Minor Revision : 03
61
[084h 0132 8] FACS Address : 0000000000000000
62
[08Ch 0140 8] DSDT Address : 0000000000000000
63
[094h 0148 12] PM1A Event Block : [Generic Address Structure]
64
[094h 0148 1] Space ID : 00 [SystemMemory]
65
[095h 0149 1] Bit Width : 00
66
[096h 0150 1] Bit Offset : 00
67
[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
68
[098h 0152 8] Address : 0000000000000000
69
70
[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
71
[0A0h 0160 1] Space ID : 00 [SystemMemory]
72
[0A1h 0161 1] Bit Width : 00
73
[0A2h 0162 1] Bit Offset : 00
74
[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
75
[0A4h 0164 8] Address : 0000000000000000
76
77
@@ -XXX,XX +XXX,XX @@
78
[0F5h 0245 1] Bit Width : 00
79
[0F6h 0246 1] Bit Offset : 00
80
[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy]
81
[0F8h 0248 8] Address : 0000000000000000
82
83
[100h 0256 12] Sleep Status Register : [Generic Address Structure]
84
[100h 0256 1] Space ID : 00 [SystemMemory]
85
[101h 0257 1] Bit Width : 00
86
[102h 0258 1] Bit Offset : 00
87
[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy]
88
[104h 0260 8] Address : 0000000000000000
89
90
[10Ch 0268 8] Hypervisor ID : 00000000554D4551
91
92
Raw Table Data: Length 276 (0x114)
93
94
- 0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20 // FACP......BOCHS
95
+ 0000: 46 41 43 50 14 01 00 00 06 12 42 4F 43 48 53 20 // FACP......BOCHS
96
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
97
0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
98
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
99
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
100
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
101
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
102
0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
103
- 0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
104
+ 0080: 00 03 00 03 00 00 00 00 00 00 00 00 00 00 00 00 // ................
105
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
106
00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
107
00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
108
00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
109
00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
110
00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
111
00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
112
0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // ............QEMU
113
0110: 00 00 00 00 // ....
114
115
@@ -XXX,XX +XXX,XX @@
116
/*
117
* Intel ACPI Component Architecture
118
* AML/ASL+ Disassembler version 20200925 (64-bit version)
119
* Copyright (c) 2000 - 2020 Intel Corporation
120
*
121
- * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 22 13:48:40 2024
122
+ * Disassembly of /tmp/aml-XDSZH2, Mon Jan 22 13:48:40 2024
123
*
124
* ACPI Data Table [GTDT]
125
*
126
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
127
*/
128
129
[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table]
130
-[004h 0004 4] Table Length : 00000060
131
-[008h 0008 1] Revision : 02
132
-[009h 0009 1] Checksum : 9C
133
+[004h 0004 4] Table Length : 00000068
134
+[008h 0008 1] Revision : 03
135
+[009h 0009 1] Checksum : 93
136
[00Ah 0010 6] Oem ID : "BOCHS "
137
[010h 0016 8] Oem Table ID : "BXPC "
138
[018h 0024 4] Oem Revision : 00000001
139
[01Ch 0028 4] Asl Compiler ID : "BXPC"
140
[020h 0032 4] Asl Compiler Revision : 00000001
141
142
[024h 0036 8] Counter Block Address : FFFFFFFFFFFFFFFF
143
[02Ch 0044 4] Reserved : 00000000
144
145
[030h 0048 4] Secure EL1 Interrupt : 0000001D
146
[034h 0052 4] EL1 Flags (decoded below) : 00000000
147
Trigger Mode : 0
148
Polarity : 0
149
Always On : 0
150
151
[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E
152
@@ -XXX,XX +XXX,XX @@
153
154
[040h 0064 4] Virtual Timer Interrupt : 0000001B
155
[044h 0068 4] VT Flags (decoded below) : 00000000
156
Trigger Mode : 0
157
Polarity : 0
158
Always On : 0
159
160
[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A
161
[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000
162
Trigger Mode : 0
163
Polarity : 0
164
Always On : 0
165
[050h 0080 8] Counter Read Block Address : FFFFFFFFFFFFFFFF
166
167
[058h 0088 4] Platform Timer Count : 00000000
168
[05Ch 0092 4] Platform Timer Offset : 00000000
169
+[060h 0096 4] Virtual EL2 Timer GSIV : 00000000
170
+[064h 0100 4] Virtual EL2 Timer Flags : 00000000
171
172
-Raw Table Data: Length 96 (0x60)
173
+Raw Table Data: Length 104 (0x68)
174
175
- 0000: 47 54 44 54 60 00 00 00 02 9C 42 4F 43 48 53 20 // GTDT`.....BOCHS
176
+ 0000: 47 54 44 54 68 00 00 00 03 93 42 4F 43 48 53 20 // GTDTh.....BOCHS
177
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
178
0020: 01 00 00 00 FF FF FF FF FF FF FF FF 00 00 00 00 // ................
179
0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................
180
0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................
181
0050: FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 // ................
182
+ 0060: 00 00 00 00 00 00 00 00 // ........
183
184
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
185
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
186
Message-id: 20240122143537.233498-4-peter.maydell@linaro.org
187
---
188
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
189
tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes
190
tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes
191
3 files changed, 2 deletions(-)
192
193
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
194
index XXXXXXX..XXXXXXX 100644
195
--- a/tests/qtest/bios-tables-test-allowed-diff.h
196
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
197
@@ -1,3 +1 @@
198
/* List of comma-separated changed AML files to ignore */
199
-"tests/data/acpi/virt/FACP",
200
-"tests/data/acpi/virt/GTDT",
201
diff --git a/tests/data/acpi/virt/FACP b/tests/data/acpi/virt/FACP
202
index XXXXXXX..XXXXXXX 100644
203
GIT binary patch
204
delta 25
205
gcmbQjG=+)F&CxkPgpq-PO=u!l<;2F$$vli407<0<)c^nh
206
207
delta 28
208
kcmbQjG=+)F&CxkPgpq-PO>`nx<-|!<6Akz$^DuG%0AAS!ssI20
209
210
diff --git a/tests/data/acpi/virt/GTDT b/tests/data/acpi/virt/GTDT
211
index XXXXXXX..XXXXXXX 100644
212
GIT binary patch
213
delta 25
214
bcmYeu;BpUf3CUn!U|^m+kt>V?$N&QXMtB4L
215
216
delta 16
217
Xcmc~u;BpUf2}xjJU|^avkt+-UB60)u
218
219
--
220
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/35] hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
1
The patchset adding the GMAC ethernet to this SoC crossed in the
2
mail with the patchset cleaning up the NIC handling. When we
3
create the GMAC modules we must call qemu_configure_nic_device()
4
so that the user has the opportunity to use the -nic commandline
5
option to create a network backend and connect it to the GMACs.
1
6
7
Add the missing call.
8
9
Fixes: 21e5326a7c ("hw/arm: Add GMAC devices to NPCM7XX SoC")
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
12
Message-id: 20240206171231.396392-2-peter.maydell@linaro.org
13
---
14
hw/arm/npcm7xx.c | 1 +
15
1 file changed, 1 insertion(+)
16
17
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/npcm7xx.c
20
+++ b/hw/arm/npcm7xx.c
21
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
22
for (i = 0; i < ARRAY_SIZE(s->gmac); i++) {
23
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->gmac[i]);
24
25
+ qemu_configure_nic_device(DEVICE(sbd), false, NULL);
26
/*
27
* The device exists regardless of whether it's connected to a QEMU
28
* netdev backend. So always instantiate it even if there is no
29
--
30
2.34.1
diff view generated by jsdifflib
[PULL 08/29] linux-user/arm: Remove bogus SVC 0xf0002 handling
[PULL 15/35] tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
1
We incorrectly treat SVC 0xf0002 as a cacheflush request (which is a
1
Currently QEMU will warn if there is a NIC on the board that
2
NOP for QEMU). This is the wrong syscall number, because in the
2
is not connected to a backend. By default the '-nic user' will
3
svc-immediate OABI syscall numbers are all offset by the
3
get used for all NICs, but if you manually connect a specific
4
ARM_SYSCALL_BASE value and so the correct insn is SVC 0x9f0002.
4
NIC to a specific backend, then the other NICs on the board
5
(This is handled further down in the code with the other Arm-specific
5
have no backend and will be warned about:
6
syscalls like NR_breakpoint.)
7
6
8
When this code was initially added in commit 6f1f31c069b20611 in
7
qemu-system-arm: warning: nic npcm7xx-emc.1 has no peer
9
2004, ARM_NR_cacheflush was defined as (ARM_SYSCALL_BASE + 0xf0000 + 2)
8
qemu-system-arm: warning: nic npcm-gmac.0 has no peer
10
so the value in the comparison took account of the extra 0x900000
9
qemu-system-arm: warning: nic npcm-gmac.1 has no peer
11
offset. In commit fbb4a2e371f2fa7 in 2008, the ARM_SYSCALL_BASE
12
was removed from the definition of ARM_NR_cacheflush and handling
13
for this group of syscalls was added below the point where we subtract
14
ARM_SYSCALL_BASE from the SVC immediate value. However that commit
15
forgot to remove the now-obsolete earlier handling code.
16
10
17
Remove the spurious ARM_NR_cacheflush condition.
11
So suppress those warnings by manually connecting every NIC
12
on the board to some backend.
18
13
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
21
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
16
Reviewed-by: Thomas Huth <thuth@redhat.com>
22
Message-id: 20200420212206.12776-3-peter.maydell@linaro.org
17
Message-id: 20240206171231.396392-3-peter.maydell@linaro.org
23
---
18
---
24
linux-user/arm/cpu_loop.c | 4 +---
19
tests/qtest/npcm7xx_emc-test.c | 5 ++++-
25
1 file changed, 1 insertion(+), 3 deletions(-)
20
1 file changed, 4 insertions(+), 1 deletion(-)
26
21
27
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
22
diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c
28
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
29
--- a/linux-user/arm/cpu_loop.c
24
--- a/tests/qtest/npcm7xx_emc-test.c
30
+++ b/linux-user/arm/cpu_loop.c
25
+++ b/tests/qtest/npcm7xx_emc-test.c
31
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
26
@@ -XXX,XX +XXX,XX @@ static int *packet_test_init(int module_num, GString *cmd_line)
32
n = insn & 0xffffff;
27
* KISS and use -nic. The driver accepts 'emc0' and 'emc1' as aliases
33
}
28
* in the 'model' field to specify the device to match.
34
29
*/
35
- if (n == ARM_NR_cacheflush) {
30
- g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d ",
36
- /* nop */
31
+ g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d "
37
- } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
32
+ "-nic user,model=npcm7xx-emc "
38
+ if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
33
+ "-nic user,model=npcm-gmac "
39
/* linux syscall */
34
+ "-nic user,model=npcm-gmac",
40
if (env->thumb || n == 0) {
35
test_sockets[1], module_num);
41
n = env->regs[7];
36
37
g_test_queue_destroy(packet_test_clear, test_sockets);
42
--
38
--
43
2.20.1
39
2.34.1
44
45
diff view generated by jsdifflib
[PULL 17/29] hw/arm/fsl-imx6ul: Connect watchdog interrupts
[PULL 16/35] target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
1
From: Guenter Roeck <linux@roeck-us.net>
1
It doesn't make sense to read the value of MDCR_EL2 on a non-A-profile
2
CPU, and in fact if you try to do it we will assert:
2
3
3
With this commit, the watchdog on mcimx6ul-evk is fully operational,
4
#6 0x00007ffff4b95e96 in __GI___assert_fail
4
including pretimeout support.
5
(assertion=0x5555565a8c70 "!arm_feature(env, ARM_FEATURE_M)", file=0x5555565a6e5c "../../target/arm/helper.c", line=12600, function=0x5555565a9560 <__PRETTY_FUNCTION__.0> "arm_security_space_below_el3") at ./assert/assert.c:101
6
#7 0x0000555555ebf412 in arm_security_space_below_el3 (env=0x555557bc8190) at ../../target/arm/helper.c:12600
7
#8 0x0000555555ea6f89 in arm_is_el2_enabled (env=0x555557bc8190) at ../../target/arm/cpu.h:2595
8
#9 0x0000555555ea942f in arm_mdcr_el2_eff (env=0x555557bc8190) at ../../target/arm/internals.h:1512
5
9
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
We might call pmu_counter_enabled() on an M-profile CPU (for example
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
11
from the migration pre/post hooks in machine.c); this should always
8
Message-id: 20200517162135.110364-7-linux@roeck-us.net
12
return false because these CPUs don't set ARM_FEATURE_PMU.
13
14
Avoid the assertion by not calling arm_mdcr_el2_eff() before we
15
have done the early return for "PMU not present".
16
17
This fixes an assertion failure if you try to do a loadvm or
18
savevm for an M-profile board.
19
20
Cc: qemu-stable@nongnu.org
21
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2155
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Message-id: 20240208153346.970021-1-peter.maydell@linaro.org
10
---
26
---
11
hw/arm/fsl-imx6ul.c | 10 ++++++++++
27
target/arm/helper.c | 12 ++++++++++--
12
1 file changed, 10 insertions(+)
28
1 file changed, 10 insertions(+), 2 deletions(-)
13
29
14
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/fsl-imx6ul.c
32
--- a/target/arm/helper.c
17
+++ b/hw/arm/fsl-imx6ul.c
33
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
34
@@ -XXX,XX +XXX,XX @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
19
FSL_IMX6UL_WDOG2_ADDR,
35
bool enabled, prohibited = false, filtered;
20
FSL_IMX6UL_WDOG3_ADDR,
36
bool secure = arm_is_secure(env);
21
};
37
int el = arm_current_el(env);
22
+ static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
38
- uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
23
+ FSL_IMX6UL_WDOG1_IRQ,
39
- uint8_t hpmn = mdcr_el2 & MDCR_HPMN;
24
+ FSL_IMX6UL_WDOG2_IRQ,
40
+ uint64_t mdcr_el2;
25
+ FSL_IMX6UL_WDOG3_IRQ,
41
+ uint8_t hpmn;
26
+ };
42
27
43
+ /*
28
+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
44
+ * We might be called for M-profile cores where MDCR_EL2 doesn't
29
+ &error_abort);
45
+ * exist and arm_mdcr_el2_eff() will assert, so this early-exit check
30
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
46
+ * must be before we read that value.
31
&error_abort);
47
+ */
32
48
if (!arm_feature(env, ARM_FEATURE_PMU)) {
33
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
49
return false;
34
FSL_IMX6UL_WDOGn_ADDR[i]);
35
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
36
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
37
+ FSL_IMX6UL_WDOGn_IRQ[i]));
38
}
50
}
39
51
40
/*
52
+ mdcr_el2 = arm_mdcr_el2_eff(env);
53
+ hpmn = mdcr_el2 & MDCR_HPMN;
54
+
55
if (!arm_feature(env, ARM_FEATURE_EL2) ||
56
(counter < hpmn || counter == 31)) {
57
e = env->cp15.c9_pmcr & PMCRE;
41
--
58
--
42
2.20.1
59
2.34.1
43
60
44
61
diff view generated by jsdifflib
[PULL 24/29] ARM: PL061: Introduce N_GPIOS
[PULL 17/35] tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
1
From: Geert Uytterhoeven <geert+renesas@glider.be>
1
From: Nabih Estefan <nabihestefan@google.com>
2
2
3
Add a definition for the number of GPIO lines controlled by a PL061
3
Fix the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead
4
instance, and use it instead of the hardcoded magic value 8.
4
of 8xx. Also fix comments referencing this and values expecting 8xx.
5
5
6
Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Change-Id: Iabd0fba14910c3f1e883c4a9521350f3db9ffab8
7
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
7
Signed-Off-By: Nabih Estefan <nabihestefan@google.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
9
Message-id: 20200519085143.1376-1-geert+renesas@glider.be
9
Message-id: 20240208194759.2858582-2-nabihestefan@google.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: commit message tweaks]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
hw/gpio/pl061.c | 12 +++++++-----
14
tests/qtest/npcm_gmac-test.c | 84 +-----------------------------------
13
1 file changed, 7 insertions(+), 5 deletions(-)
15
tests/qtest/meson.build | 3 +-
16
2 files changed, 4 insertions(+), 83 deletions(-)
14
17
15
diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
18
diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c
16
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/gpio/pl061.c
20
--- a/tests/qtest/npcm_gmac-test.c
18
+++ b/hw/gpio/pl061.c
21
+++ b/tests/qtest/npcm_gmac-test.c
19
@@ -XXX,XX +XXX,XX @@ static const uint8_t pl061_id_luminary[12] =
22
@@ -XXX,XX +XXX,XX @@ typedef struct TestData {
20
#define TYPE_PL061 "pl061"
23
const GMACModule *module;
21
#define PL061(obj) OBJECT_CHECK(PL061State, (obj), TYPE_PL061)
24
} TestData;
22
25
23
+#define N_GPIOS 8
26
-/* Values extracted from hw/arm/npcm8xx.c */
24
+
27
+/* Values extracted from hw/arm/npcm7xx.c */
25
typedef struct PL061State {
28
static const GMACModule gmac_module_list[] = {
26
SysBusDevice parent_obj;
29
{
27
30
.irq = 14,
28
@@ -XXX,XX +XXX,XX @@ typedef struct PL061State {
31
@@ -XXX,XX +XXX,XX @@ static const GMACModule gmac_module_list[] = {
29
uint32_t cr;
32
.irq = 15,
30
uint32_t amsel;
33
.base_addr = 0xf0804000
31
qemu_irq irq;
34
},
32
- qemu_irq out[8];
35
- {
33
+ qemu_irq out[N_GPIOS];
36
- .irq = 16,
34
const unsigned char *id;
37
- .base_addr = 0xf0806000
35
uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */
38
- },
36
} PL061State;
39
- {
37
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
40
- .irq = 17,
38
changed = s->old_out_data ^ out;
41
- .base_addr = 0xf0808000
39
if (changed) {
42
- }
40
s->old_out_data = out;
43
};
41
- for (i = 0; i < 8; i++) {
44
42
+ for (i = 0; i < N_GPIOS; i++) {
45
/* Returns the index of the GMAC module. */
43
mask = 1 << i;
46
@@ -XXX,XX +XXX,XX @@ static uint32_t gmac_read(QTestState *qts, const GMACModule *mod,
44
if (changed & mask) {
47
return qtest_readl(qts, mod->base_addr + regno);
45
DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
46
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
47
changed = (s->old_in_data ^ s->data) & ~s->dir;
48
if (changed) {
49
s->old_in_data = s->data;
50
- for (i = 0; i < 8; i++) {
51
+ for (i = 0; i < N_GPIOS; i++) {
52
mask = 1 << i;
53
if (changed & mask) {
54
DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0);
55
@@ -XXX,XX +XXX,XX @@ static void pl061_init(Object *obj)
56
memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000);
57
sysbus_init_mmio(sbd, &s->iomem);
58
sysbus_init_irq(sbd, &s->irq);
59
- qdev_init_gpio_in(dev, pl061_set_irq, 8);
60
- qdev_init_gpio_out(dev, s->out, 8);
61
+ qdev_init_gpio_in(dev, pl061_set_irq, N_GPIOS);
62
+ qdev_init_gpio_out(dev, s->out, N_GPIOS);
63
}
48
}
64
49
65
static void pl061_class_init(ObjectClass *klass, void *data)
50
-static uint16_t pcs_read(QTestState *qts, const GMACModule *mod,
51
- NPCMRegister regno)
52
-{
53
- uint32_t write_value = (regno & 0x3ffe00) >> 9;
54
- qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value);
55
- uint32_t read_offset = regno & 0x1ff;
56
- return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset);
57
-}
58
-
59
/* Check that GMAC registers are reset to default value */
60
static void test_init(gconstpointer test_data)
61
{
62
const TestData *td = test_data;
63
const GMACModule *mod = td->module;
64
- QTestState *qts = qtest_init("-machine npcm845-evb");
65
+ QTestState *qts = qtest_init("-machine npcm750-evb");
66
67
#define CHECK_REG32(regno, value) \
68
do { \
69
g_assert_cmphex(gmac_read(qts, mod, (regno)), ==, (value)); \
70
} while (0)
71
72
-#define CHECK_REG_PCS(regno, value) \
73
- do { \
74
- g_assert_cmphex(pcs_read(qts, mod, (regno)), ==, (value)); \
75
- } while (0)
76
-
77
CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100);
78
CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0);
79
CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0);
80
@@ -XXX,XX +XXX,XX @@ static void test_init(gconstpointer test_data)
81
CHECK_REG32(NPCM_GMAC_PTP_TAR, 0);
82
CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0);
83
84
- /* TODO Add registers PCS */
85
- if (mod->base_addr == 0xf0802000) {
86
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e);
87
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0);
88
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000);
89
-
90
- CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140);
91
- CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109);
92
- CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e);
93
- CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0);
94
- CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020);
95
- CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0);
96
- CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0);
97
- CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000);
98
-
99
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003);
100
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038);
101
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0);
102
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038);
103
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0);
104
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058);
105
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0);
106
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048);
107
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0);
108
-
109
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400);
110
- CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0);
111
- CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a);
112
- CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0);
113
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0);
114
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c);
115
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0);
116
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0);
117
- CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0);
118
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0);
119
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010);
120
- CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0);
121
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0);
122
- CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0);
123
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a);
124
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f);
125
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001);
126
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0);
127
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0);
128
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100);
129
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100);
130
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e);
131
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100);
132
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032);
133
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001);
134
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0);
135
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019);
136
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0);
137
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0);
138
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0);
139
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0);
140
- }
141
-
142
qtest_quit(qts);
143
}
144
145
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
146
index XXXXXXX..XXXXXXX 100644
147
--- a/tests/qtest/meson.build
148
+++ b/tests/qtest/meson.build
149
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
150
'npcm7xx_sdhci-test',
151
'npcm7xx_smbus-test',
152
'npcm7xx_timer-test',
153
- 'npcm7xx_watchdog_timer-test'] + \
154
+ 'npcm7xx_watchdog_timer-test',
155
+ 'npcm_gmac-test'] + \
156
(slirp.found() ? ['npcm7xx_emc-test'] : [])
157
qtests_aspeed = \
158
['aspeed_hace-test',
66
--
159
--
67
2.20.1
160
2.34.1
68
69
diff view generated by jsdifflib
[PULL 12/29] hw: Move i.MX watchdog driver to hw/watchdog
[PULL 18/35] hw/arm/smmuv3: add support for stage 1 access fault
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Luc Michel <luc.michel@amd.com>
2
2
3
In preparation for a full implementation, move i.MX watchdog driver
3
An access fault is raised when the Access Flag is not set in the
4
from hw/misc to hw/watchdog. While at it, add the watchdog files
4
looked-up PTE and the AFFD field is not set in the corresponding context
5
to MAINTAINERS.
5
descriptor. This was already implemented for stage 2. Implement it for
6
stage 1 as well.
6
7
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Signed-off-by: Luc Michel <luc.michel@amd.com>
8
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
9
Reviewed-by: Mostafa Saleh <smostafa@google.com>
9
Message-id: 20200517162135.110364-2-linux@roeck-us.net
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
Tested-by: Mostafa Saleh <smostafa@google.com>
12
Message-id: 20240213082211.3330400-1-luc.michel@amd.com
13
[PMM: tweaked comment text]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
15
---
12
include/hw/arm/fsl-imx6.h | 2 +-
16
hw/arm/smmuv3-internal.h | 1 +
13
include/hw/arm/fsl-imx6ul.h | 2 +-
17
include/hw/arm/smmu-common.h | 1 +
14
include/hw/arm/fsl-imx7.h | 2 +-
18
hw/arm/smmu-common.c | 11 +++++++++++
15
include/hw/{misc/imx2_wdt.h => watchdog/wdt_imx2.h} | 0
19
hw/arm/smmuv3.c | 1 +
16
hw/{misc/imx2_wdt.c => watchdog/wdt_imx2.c} | 2 +-
20
4 files changed, 14 insertions(+)
17
MAINTAINERS | 2 ++
18
hw/arm/Kconfig | 3 +++
19
hw/misc/Makefile.objs | 1 -
20
hw/watchdog/Kconfig | 3 +++
21
hw/watchdog/Makefile.objs | 1 +
22
10 files changed, 13 insertions(+), 5 deletions(-)
23
rename include/hw/{misc/imx2_wdt.h => watchdog/wdt_imx2.h} (100%)
24
rename hw/{misc/imx2_wdt.c => watchdog/wdt_imx2.c} (98%)
25
21
26
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
22
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
27
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/arm/fsl-imx6.h
24
--- a/hw/arm/smmuv3-internal.h
29
+++ b/include/hw/arm/fsl-imx6.h
25
+++ b/hw/arm/smmuv3-internal.h
30
@@ -XXX,XX +XXX,XX @@
26
@@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste)
31
#include "hw/cpu/a9mpcore.h"
27
#define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1)
32
#include "hw/misc/imx6_ccm.h"
28
#define CD_ENDI(x) extract32((x)->word[0], 15, 1)
33
#include "hw/misc/imx6_src.h"
29
#define CD_IPS(x) extract32((x)->word[1], 0 , 3)
34
-#include "hw/misc/imx2_wdt.h"
30
+#define CD_AFFD(x) extract32((x)->word[1], 3 , 1)
35
+#include "hw/watchdog/wdt_imx2.h"
31
#define CD_TBI(x) extract32((x)->word[1], 6 , 2)
36
#include "hw/char/imx_serial.h"
32
#define CD_HD(x) extract32((x)->word[1], 10 , 1)
37
#include "hw/timer/imx_gpt.h"
33
#define CD_HA(x) extract32((x)->word[1], 11 , 1)
38
#include "hw/timer/imx_epit.h"
34
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
39
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
40
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
41
--- a/include/hw/arm/fsl-imx6ul.h
36
--- a/include/hw/arm/smmu-common.h
42
+++ b/include/hw/arm/fsl-imx6ul.h
37
+++ b/include/hw/arm/smmu-common.h
43
@@ -XXX,XX +XXX,XX @@
38
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg {
44
#include "hw/misc/imx7_snvs.h"
39
bool disabled; /* smmu is disabled */
45
#include "hw/misc/imx7_gpr.h"
40
bool bypassed; /* translation is bypassed */
46
#include "hw/intc/imx_gpcv2.h"
41
bool aborted; /* translation is aborted */
47
-#include "hw/misc/imx2_wdt.h"
42
+ bool affd; /* AF fault disable */
48
+#include "hw/watchdog/wdt_imx2.h"
43
uint32_t iotlb_hits; /* counts IOTLB hits */
49
#include "hw/gpio/imx_gpio.h"
44
uint32_t iotlb_misses; /* counts IOTLB misses*/
50
#include "hw/char/imx_serial.h"
45
/* Used by stage-1 only. */
51
#include "hw/timer/imx_gpt.h"
46
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
52
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
53
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
54
--- a/include/hw/arm/fsl-imx7.h
48
--- a/hw/arm/smmu-common.c
55
+++ b/include/hw/arm/fsl-imx7.h
49
+++ b/hw/arm/smmu-common.c
56
@@ -XXX,XX +XXX,XX @@
50
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
57
#include "hw/misc/imx7_snvs.h"
51
pte_addr, pte, iova, gpa,
58
#include "hw/misc/imx7_gpr.h"
52
block_size >> 20);
59
#include "hw/misc/imx6_src.h"
53
}
60
-#include "hw/misc/imx2_wdt.h"
54
+
61
+#include "hw/watchdog/wdt_imx2.h"
55
+ /*
62
#include "hw/gpio/imx_gpio.h"
56
+ * QEMU does not currently implement HTTU, so if AFFD and PTE.AF
63
#include "hw/char/imx_serial.h"
57
+ * are 0 we take an Access flag fault. (5.4. Context Descriptor)
64
#include "hw/timer/imx_gpt.h"
58
+ * An Access flag fault takes priority over a Permission fault.
65
diff --git a/include/hw/misc/imx2_wdt.h b/include/hw/watchdog/wdt_imx2.h
59
+ */
66
similarity index 100%
60
+ if (!PTE_AF(pte) && !cfg->affd) {
67
rename from include/hw/misc/imx2_wdt.h
61
+ info->type = SMMU_PTW_ERR_ACCESS;
68
rename to include/hw/watchdog/wdt_imx2.h
62
+ goto error;
69
diff --git a/hw/misc/imx2_wdt.c b/hw/watchdog/wdt_imx2.c
63
+ }
70
similarity index 98%
64
+
71
rename from hw/misc/imx2_wdt.c
65
ap = PTE_AP(pte);
72
rename to hw/watchdog/wdt_imx2.c
66
if (is_permission_fault(ap, perm)) {
67
info->type = SMMU_PTW_ERR_PERMISSION;
68
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
73
index XXXXXXX..XXXXXXX 100644
69
index XXXXXXX..XXXXXXX 100644
74
--- a/hw/misc/imx2_wdt.c
70
--- a/hw/arm/smmuv3.c
75
+++ b/hw/watchdog/wdt_imx2.c
71
+++ b/hw/arm/smmuv3.c
76
@@ -XXX,XX +XXX,XX @@
72
@@ -XXX,XX +XXX,XX @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
77
#include "qemu/module.h"
73
cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas);
78
#include "sysemu/watchdog.h"
74
cfg->tbi = CD_TBI(cd);
79
75
cfg->asid = CD_ASID(cd);
80
-#include "hw/misc/imx2_wdt.h"
76
+ cfg->affd = CD_AFFD(cd);
81
+#include "hw/watchdog/wdt_imx2.h"
77
82
78
trace_smmuv3_decode_cd(cfg->oas);
83
#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
79
84
#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
85
diff --git a/MAINTAINERS b/MAINTAINERS
86
index XXXXXXX..XXXXXXX 100644
87
--- a/MAINTAINERS
88
+++ b/MAINTAINERS
89
@@ -XXX,XX +XXX,XX @@ S: Odd Fixes
90
F: hw/arm/fsl-imx25.c
91
F: hw/arm/imx25_pdk.c
92
F: hw/misc/imx25_ccm.c
93
+F: hw/watchdog/wdt_imx2.c
94
F: include/hw/arm/fsl-imx25.h
95
F: include/hw/misc/imx25_ccm.h
96
+F: include/hw/watchdog/wdt_imx2.h
97
98
i.MX31 (kzm)
99
M: Peter Chubb <peter.chubb@nicta.com.au>
100
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
101
index XXXXXXX..XXXXXXX 100644
102
--- a/hw/arm/Kconfig
103
+++ b/hw/arm/Kconfig
104
@@ -XXX,XX +XXX,XX @@ config FSL_IMX6
105
select IMX_FEC
106
select IMX_I2C
107
select IMX_USBPHY
108
+ select WDT_IMX2
109
select SDHCI
110
111
config ASPEED_SOC
112
@@ -XXX,XX +XXX,XX @@ config FSL_IMX7
113
select IMX
114
select IMX_FEC
115
select IMX_I2C
116
+ select WDT_IMX2
117
select PCI_EXPRESS_DESIGNWARE
118
select SDHCI
119
select UNIMP
120
@@ -XXX,XX +XXX,XX @@ config FSL_IMX6UL
121
select IMX
122
select IMX_FEC
123
select IMX_I2C
124
+ select WDT_IMX2
125
select SDHCI
126
select UNIMP
127
128
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
129
index XXXXXXX..XXXXXXX 100644
130
--- a/hw/misc/Makefile.objs
131
+++ b/hw/misc/Makefile.objs
132
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IMX) += imx6_ccm.o
133
common-obj-$(CONFIG_IMX) += imx6ul_ccm.o
134
obj-$(CONFIG_IMX) += imx6_src.o
135
common-obj-$(CONFIG_IMX) += imx7_ccm.o
136
-common-obj-$(CONFIG_IMX) += imx2_wdt.o
137
common-obj-$(CONFIG_IMX) += imx7_snvs.o
138
common-obj-$(CONFIG_IMX) += imx7_gpr.o
139
common-obj-$(CONFIG_IMX) += imx_rngc.o
140
diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig
141
index XXXXXXX..XXXXXXX 100644
142
--- a/hw/watchdog/Kconfig
143
+++ b/hw/watchdog/Kconfig
144
@@ -XXX,XX +XXX,XX @@ config WDT_IB700
145
146
config WDT_DIAG288
147
bool
148
+
149
+config WDT_IMX2
150
+ bool
151
diff --git a/hw/watchdog/Makefile.objs b/hw/watchdog/Makefile.objs
152
index XXXXXXX..XXXXXXX 100644
153
--- a/hw/watchdog/Makefile.objs
154
+++ b/hw/watchdog/Makefile.objs
155
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_WDT_IB6300ESB) += wdt_i6300esb.o
156
common-obj-$(CONFIG_WDT_IB700) += wdt_ib700.o
157
common-obj-$(CONFIG_WDT_DIAG288) += wdt_diag288.o
158
common-obj-$(CONFIG_ASPEED_SOC) += wdt_aspeed.o
159
+common-obj-$(CONFIG_WDT_IMX2) += wdt_imx2.o
160
--
80
--
161
2.20.1
81
2.34.1
162
163
diff view generated by jsdifflib
[PULL 21/29] hw/arm/pxa2xx: Replace hw_error() by qemu_log_mask()
[PULL 19/35] hw/arm/stellaris: Convert ADC controller to Resettable interface
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
hw_error() calls exit(). This a bit overkill when we can log
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
the accesses as unimplemented or guest error.
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
5
Message-id: 20240213155214.13619-2-philmd@linaro.org
6
When fuzzing the devices, we don't want the whole process to
7
exit. Replace some hw_error() calls by qemu_log_mask().
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 20200518140309.5220-3-f4bug@amsat.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
7
---
14
hw/arm/pxa2xx_gpio.c | 7 ++++---
8
hw/arm/stellaris.c | 6 ++++--
15
hw/display/pxa2xx_lcd.c | 8 +++++---
9
1 file changed, 4 insertions(+), 2 deletions(-)
16
hw/dma/pxa2xx_dma.c | 14 +++++++++-----
17
3 files changed, 18 insertions(+), 11 deletions(-)
18
10
19
diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c
11
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
20
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/pxa2xx_gpio.c
13
--- a/hw/arm/stellaris.c
22
+++ b/hw/arm/pxa2xx_gpio.c
14
+++ b/hw/arm/stellaris.c
23
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
24
25
#include "qemu/osdep.h"
26
#include "cpu.h"
27
-#include "hw/hw.h"
28
#include "hw/irq.h"
29
#include "hw/qdev-properties.h"
30
#include "hw/sysbus.h"
31
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
32
return s->status[bank];
33
34
default:
35
- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
36
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
37
+ __func__, offset);
38
}
39
40
return 0;
41
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
42
break;
43
44
default:
45
- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
46
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
47
+ __func__, offset);
48
}
16
}
49
}
17
}
50
18
51
diff --git a/hw/display/pxa2xx_lcd.c b/hw/display/pxa2xx_lcd.c
19
-static void stellaris_adc_reset(StellarisADCState *s)
52
index XXXXXXX..XXXXXXX 100644
20
+static void stellaris_adc_reset_hold(Object *obj)
53
--- a/hw/display/pxa2xx_lcd.c
21
{
54
+++ b/hw/display/pxa2xx_lcd.c
22
+ StellarisADCState *s = STELLARIS_ADC(obj);
55
@@ -XXX,XX +XXX,XX @@
23
int n;
56
*/
24
57
25
for (n = 0; n < 4; n++) {
58
#include "qemu/osdep.h"
26
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj)
59
-#include "hw/hw.h"
27
memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
60
+#include "qemu/log.h"
28
"adc", 0x1000);
61
#include "hw/irq.h"
29
sysbus_init_mmio(sbd, &s->iomem);
62
#include "migration/vmstate.h"
30
- stellaris_adc_reset(s);
63
#include "ui/console.h"
31
qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
64
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_lcdc_read(void *opaque, hwaddr offset,
65
66
default:
67
fail:
68
- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
69
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
70
+ __func__, offset);
71
}
72
73
return 0;
74
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
75
76
default:
77
fail:
78
- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
79
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
80
+ __func__, offset);
81
}
82
}
32
}
83
33
84
diff --git a/hw/dma/pxa2xx_dma.c b/hw/dma/pxa2xx_dma.c
34
@@ -XXX,XX +XXX,XX @@ static const TypeInfo stellaris_i2c_info = {
85
index XXXXXXX..XXXXXXX 100644
35
static void stellaris_adc_class_init(ObjectClass *klass, void *data)
86
--- a/hw/dma/pxa2xx_dma.c
36
{
87
+++ b/hw/dma/pxa2xx_dma.c
37
DeviceClass *dc = DEVICE_CLASS(klass);
88
@@ -XXX,XX +XXX,XX @@
38
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
89
*/
39
90
40
+ rc->phases.hold = stellaris_adc_reset_hold;
91
#include "qemu/osdep.h"
41
dc->vmsd = &vmstate_stellaris_adc;
92
+#include "qemu/log.h"
93
#include "hw/hw.h"
94
#include "hw/irq.h"
95
#include "hw/qdev-properties.h"
96
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
97
unsigned int channel;
98
99
if (size != 4) {
100
- hw_error("%s: Bad access width\n", __func__);
101
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n",
102
+ __func__, size);
103
return 5;
104
}
105
106
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
107
return s->chan[channel].cmd;
108
}
109
}
110
-
111
- hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
112
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
113
+ __func__, offset);
114
return 7;
115
}
42
}
116
43
117
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset,
118
unsigned int channel;
119
120
if (size != 4) {
121
- hw_error("%s: Bad access width\n", __func__);
122
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n",
123
+ __func__, size);
124
return;
125
}
126
127
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset,
128
break;
129
}
130
fail:
131
- hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __func__, offset);
132
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
133
+ __func__, offset);
134
}
135
}
136
137
--
44
--
138
2.20.1
45
2.34.1
139
46
140
47
diff view generated by jsdifflib
[PULL 20/29] hw/arm/integratorcp: Replace hw_error() by qemu_log_mask()
[PULL 20/35] hw/arm/stellaris: Convert I2C controller to Resettable interface
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
hw_error() calls exit(). This a bit overkill when we can log
3
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
4
the accesses as unimplemented or guest error.
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
5
Message-id: 20240213155214.13619-3-philmd@linaro.org
6
When fuzzing the devices, we don't want the whole process to
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
exit. Replace some hw_error() calls by qemu_log_mask().
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 20200518140309.5220-2-f4bug@amsat.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
8
---
14
hw/arm/integratorcp.c | 23 +++++++++++++++--------
9
hw/arm/stellaris.c | 26 ++++++++++++++++++++++----
15
1 file changed, 15 insertions(+), 8 deletions(-)
10
1 file changed, 22 insertions(+), 4 deletions(-)
16
11
17
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
12
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
18
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/integratorcp.c
14
--- a/hw/arm/stellaris.c
20
+++ b/hw/arm/integratorcp.c
15
+++ b/hw/arm/stellaris.c
21
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ static void stellaris_sys_instance_init(Object *obj)
22
#include "exec/address-spaces.h"
17
s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
23
#include "sysemu/runstate.h"
24
#include "sysemu/sysemu.h"
25
+#include "qemu/log.h"
26
#include "qemu/error-report.h"
27
#include "hw/char/pl011.h"
28
#include "hw/hw.h"
29
@@ -XXX,XX +XXX,XX @@ static uint64_t integratorcm_read(void *opaque, hwaddr offset,
30
/* ??? Voltage control unimplemented. */
31
return 0;
32
default:
33
- hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
34
- (int)offset);
35
+ qemu_log_mask(LOG_UNIMP,
36
+ "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n",
37
+ __func__, offset);
38
return 0;
39
}
40
}
18
}
41
@@ -XXX,XX +XXX,XX @@ static void integratorcm_write(void *opaque, hwaddr offset,
19
42
/* ??? Voltage control unimplemented. */
20
-/* I2C controller. */
43
break;
21
+/*
44
default:
22
+ * I2C controller.
45
- hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
23
+ * ??? For now we only implement the master interface.
46
- (int)offset);
24
+ */
47
+ qemu_log_mask(LOG_UNIMP,
25
48
+ "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n",
26
#define TYPE_STELLARIS_I2C "stellaris-i2c"
49
+ __func__, offset);
27
OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
50
break;
28
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset,
51
}
29
stellaris_i2c_update(s);
52
}
30
}
53
@@ -XXX,XX +XXX,XX @@ static uint64_t icp_pic_read(void *opaque, hwaddr offset,
31
54
case 5: /* INT_SOFTCLR */
32
-static void stellaris_i2c_reset(stellaris_i2c_state *s)
55
case 11: /* FRQ_ENABLECLR */
33
+static void stellaris_i2c_reset_enter(Object *obj, ResetType type)
56
default:
34
{
57
- printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
35
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
58
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
36
+
59
+ __func__, offset);
37
if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
60
return 0;
38
i2c_end_transfer(s->bus);
61
}
39
+}
40
+
41
+static void stellaris_i2c_reset_hold(Object *obj)
42
+{
43
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
44
45
s->msa = 0;
46
s->mcs = 0;
47
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_reset(stellaris_i2c_state *s)
48
s->mimr = 0;
49
s->mris = 0;
50
s->mcr = 0;
51
+}
52
+
53
+static void stellaris_i2c_reset_exit(Object *obj)
54
+{
55
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
56
+
57
stellaris_i2c_update(s);
62
}
58
}
63
@@ -XXX,XX +XXX,XX @@ static void icp_pic_write(void *opaque, hwaddr offset,
59
64
case 8: /* FRQ_STATUS */
60
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_init(Object *obj)
65
case 9: /* FRQ_RAWSTAT */
61
memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
66
default:
62
"i2c", 0x1000);
67
- printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
63
sysbus_init_mmio(sbd, &s->iomem);
68
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
64
- /* ??? For now we only implement the master interface. */
69
+ __func__, offset);
65
- stellaris_i2c_reset(s);
70
return;
71
}
72
icp_pic_update(s);
73
@@ -XXX,XX +XXX,XX @@ static uint64_t icp_control_read(void *opaque, hwaddr offset,
74
case 3: /* CP_DECODE */
75
return 0x11;
76
default:
77
- hw_error("icp_control_read: Bad offset %x\n", (int)offset);
78
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
79
+ __func__, offset);
80
return 0;
81
}
82
}
66
}
83
@@ -XXX,XX +XXX,XX @@ static void icp_control_write(void *opaque, hwaddr offset,
67
84
/* Nothing interesting implemented yet. */
68
/* Analogue to Digital Converter. This is only partially implemented,
85
break;
69
@@ -XXX,XX +XXX,XX @@ type_init(stellaris_machine_init)
86
default:
70
static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
87
- hw_error("icp_control_write: Bad offset %x\n", (int)offset);
71
{
88
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
72
DeviceClass *dc = DEVICE_CLASS(klass);
89
+ __func__, offset);
73
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
90
}
74
75
+ rc->phases.enter = stellaris_i2c_reset_enter;
76
+ rc->phases.hold = stellaris_i2c_reset_hold;
77
+ rc->phases.exit = stellaris_i2c_reset_exit;
78
dc->vmsd = &vmstate_stellaris_i2c;
91
}
79
}
92
80
93
--
81
--
94
2.20.1
82
2.34.1
95
83
96
84
diff view generated by jsdifflib
[PULL 07/29] linux-user/arm: BKPT should cause SIGTRAP, not be a syscall
[PULL 21/35] hw/arm/stellaris: Add missing QOM 'machine' parent
1
In linux-user/arm/cpu-loop.c we incorrectly treat EXCP_BKPT similarly
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
to EXCP_SWI, which means that if the guest executes a BKPT insn then
3
QEMU will perform a syscall for it (which syscall depends on what
4
value happens to be in r7...). The correct behaviour is that the
5
guest process should take a SIGTRAP.
6
2
7
This code has been like this (more or less) since commit
3
QDev objects created with qdev_new() need to manually add
8
06c949e62a098f in 2006 which added BKPT in the first place. This is
4
their parent relationship with object_property_add_child().
9
probably because at the time the same code path was used to handle
10
both Linux syscalls and semihosting calls, and (on M profile) BKPT
11
with a suitable magic number is used for semihosting calls. But
12
these days we've moved handling of semihosting out to an entirely
13
different codepath, so we can fix this bug by simply removing this
14
handling of EXCP_BKPT and instead making it deliver a SIGTRAP like
15
EXCP_DEBUG (as we do already on aarch64).
16
5
17
Reported-by: <omerg681@gmail.com>
6
This commit plug the devices which aren't part of the SoC;
18
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
they will be plugged into a SoC container in the next one.
19
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
21
Message-id: 20200420212206.12776-2-peter.maydell@linaro.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
22
Fixes: https://bugs.launchpad.net/qemu/+bug/1873898
11
Message-id: 20240213155214.13619-4-philmd@linaro.org
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
---
13
---
25
linux-user/arm/cpu_loop.c | 30 ++++++++----------------------
14
hw/arm/stellaris.c | 4 ++++
26
1 file changed, 8 insertions(+), 22 deletions(-)
15
1 file changed, 4 insertions(+)
27
16
28
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
17
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
29
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
30
--- a/linux-user/arm/cpu_loop.c
19
--- a/hw/arm/stellaris.c
31
+++ b/linux-user/arm/cpu_loop.c
20
+++ b/hw/arm/stellaris.c
32
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
21
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
33
}
22
&error_fatal);
34
break;
23
35
case EXCP_SWI:
24
ssddev = qdev_new("ssd0323");
36
- case EXCP_BKPT:
25
+ object_property_add_child(OBJECT(ms), "oled", OBJECT(ssddev));
37
{
26
qdev_prop_set_uint8(ssddev, "cs", 1);
38
env->eabi = 1;
27
qdev_realize_and_unref(ssddev, bus, &error_fatal);
39
/* system call */
28
40
- if (trapnr == EXCP_BKPT) {
29
gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ);
41
- if (env->thumb) {
30
+ object_property_add_child(OBJECT(ms), "splitter",
42
- /* FIXME - what to do if get_user() fails? */
31
+ OBJECT(gpio_d_splitter));
43
- get_user_code_u16(insn, env->regs[15], env);
32
qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2);
44
- n = insn & 0xff;
33
qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal);
45
- env->regs[15] += 2;
34
qdev_connect_gpio_out(
46
- } else {
35
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
47
- /* FIXME - what to do if get_user() fails? */
36
DeviceState *gpad;
48
- get_user_code_u32(insn, env->regs[15], env);
37
49
- n = (insn & 0xf) | ((insn >> 4) & 0xff0);
38
gpad = qdev_new(TYPE_STELLARIS_GAMEPAD);
50
- env->regs[15] += 4;
39
+ object_property_add_child(OBJECT(ms), "gamepad", OBJECT(gpad));
51
- }
40
for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) {
52
+ if (env->thumb) {
41
qlist_append_int(gpad_keycode_list, gpad_keycode[i]);
53
+ /* FIXME - what to do if get_user() fails? */
42
}
54
+ get_user_code_u16(insn, env->regs[15] - 2, env);
55
+ n = insn & 0xff;
56
} else {
57
- if (env->thumb) {
58
- /* FIXME - what to do if get_user() fails? */
59
- get_user_code_u16(insn, env->regs[15] - 2, env);
60
- n = insn & 0xff;
61
- } else {
62
- /* FIXME - what to do if get_user() fails? */
63
- get_user_code_u32(insn, env->regs[15] - 4, env);
64
- n = insn & 0xffffff;
65
- }
66
+ /* FIXME - what to do if get_user() fails? */
67
+ get_user_code_u32(insn, env->regs[15] - 4, env);
68
+ n = insn & 0xffffff;
69
}
70
71
if (n == ARM_NR_cacheflush) {
72
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
73
}
74
break;
75
case EXCP_DEBUG:
76
+ case EXCP_BKPT:
77
excp_debug:
78
info.si_signo = TARGET_SIGTRAP;
79
info.si_errno = 0;
80
--
43
--
81
2.20.1
44
2.34.1
82
45
83
46
diff view generated by jsdifflib
[PULL 19/29] hw/arm/fsl-imx7: Connect watchdog interrupts
[PULL 22/35] hw/arm/stellaris: Add missing QOM 'SoC' parent
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
i.MX7 supports watchdog pretimeout interupts. With this commit,
3
QDev objects created with qdev_new() need to manually add
4
the watchdog in mcimx7d-sabre is fully operational, including
4
their parent relationship with object_property_add_child().
5
pretimeout support.
6
5
6
Since we don't model the SoC, just use a QOM container.
7
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
10
Message-id: 20240213155214.13619-5-philmd@linaro.org
9
Message-id: 20200517162135.110364-9-linux@roeck-us.net
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
---
12
include/hw/arm/fsl-imx7.h | 5 +++++
13
hw/arm/stellaris.c | 11 ++++++++++-
13
hw/arm/fsl-imx7.c | 11 +++++++++++
14
1 file changed, 10 insertions(+), 1 deletion(-)
14
2 files changed, 16 insertions(+)
15
15
16
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
16
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/fsl-imx7.h
18
--- a/hw/arm/stellaris.c
19
+++ b/include/hw/arm/fsl-imx7.h
19
+++ b/hw/arm/stellaris.c
20
@@ -XXX,XX +XXX,XX @@ enum FslIMX7IRQs {
20
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
21
FSL_IMX7_USB2_IRQ = 42,
21
* 400fe000 system control
22
FSL_IMX7_USB3_IRQ = 40,
22
*/
23
23
24
+ FSL_IMX7_WDOG1_IRQ = 78,
24
+ Object *soc_container;
25
+ FSL_IMX7_WDOG2_IRQ = 79,
25
DeviceState *gpio_dev[7], *nvic;
26
+ FSL_IMX7_WDOG3_IRQ = 10,
26
qemu_irq gpio_in[7][8];
27
+ FSL_IMX7_WDOG4_IRQ = 109,
27
qemu_irq gpio_out[7][8];
28
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
29
flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
30
sram_size = ((board->dc0 >> 18) + 1) * 1024;
31
32
+ soc_container = object_new("container");
33
+ object_property_add_child(OBJECT(ms), "soc", soc_container);
28
+
34
+
29
FSL_IMX7_PCI_INTA_IRQ = 125,
35
/* Flash programming is done via the SCU, so pretend it is ROM. */
30
FSL_IMX7_PCI_INTB_IRQ = 124,
36
memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
31
FSL_IMX7_PCI_INTC_IRQ = 123,
37
&error_fatal);
32
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
38
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
33
index XXXXXXX..XXXXXXX 100644
39
* need its sysclk output.
34
--- a/hw/arm/fsl-imx7.c
40
*/
35
+++ b/hw/arm/fsl-imx7.c
41
ssys_dev = qdev_new(TYPE_STELLARIS_SYS);
36
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
42
+ object_property_add_child(soc_container, "sys", OBJECT(ssys_dev));
37
FSL_IMX7_WDOG3_ADDR,
38
FSL_IMX7_WDOG4_ADDR,
39
};
40
+ static const int FSL_IMX7_WDOGn_IRQ[FSL_IMX7_NUM_WDTS] = {
41
+ FSL_IMX7_WDOG1_IRQ,
42
+ FSL_IMX7_WDOG2_IRQ,
43
+ FSL_IMX7_WDOG3_IRQ,
44
+ FSL_IMX7_WDOG4_IRQ,
45
+ };
46
47
+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
48
+ &error_abort);
49
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
50
&error_abort);
51
52
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);
53
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
54
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
55
+ FSL_IMX7_WDOGn_IRQ[i]));
56
}
57
43
58
/*
44
/*
45
* Most devices come preprogrammed with a MAC address in the user data.
46
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
47
sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
48
49
nvic = qdev_new(TYPE_ARMV7M);
50
+ object_property_add_child(soc_container, "v7m", OBJECT(nvic));
51
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
52
qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);
53
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
54
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
55
56
dev = qdev_new(TYPE_STELLARIS_GPTM);
57
sbd = SYS_BUS_DEVICE(dev);
58
+ object_property_add_child(soc_container, "gptm[*]", OBJECT(dev));
59
qdev_connect_clock_in(dev, "clk",
60
qdev_get_clock_out(ssys_dev, "SYSCLK"));
61
sysbus_realize_and_unref(sbd, &error_fatal);
62
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
63
64
if (board->dc1 & (1 << 3)) { /* watchdog present */
65
dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
66
-
67
+ object_property_add_child(soc_container, "wdg", OBJECT(dev));
68
qdev_connect_clock_in(dev, "WDOGCLK",
69
qdev_get_clock_out(ssys_dev, "SYSCLK"));
70
71
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
72
SysBusDevice *sbd;
73
74
dev = qdev_new("pl011_luminary");
75
+ object_property_add_child(soc_container, "uart[*]", OBJECT(dev));
76
sbd = SYS_BUS_DEVICE(dev);
77
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
78
sysbus_realize_and_unref(sbd, &error_fatal);
79
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
80
DeviceState *enet;
81
82
enet = qdev_new("stellaris_enet");
83
+ object_property_add_child(soc_container, "enet", OBJECT(enet));
84
if (nd) {
85
qdev_set_nic_properties(enet, nd);
86
} else {
59
--
87
--
60
2.20.1
88
2.34.1
61
89
62
90
diff view generated by jsdifflib
[PULL 06/29] docs/system: Document Musca boards
[PULL 23/35] target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
1
Provide a minimal documentation of the Musca boards.
1
We support two different encodings for the AArch32 IMPDEF
2
CBAR register -- older cores like the Cortex A9, A7, A15
3
have this at 4, c15, c0, 0; newer cores like the
4
Cortex A35, A53, A57 and A72 have it at 1 c15 c0 0.
5
6
When we implemented this we picked which encoding to
7
use based on whether the CPU set ARM_FEATURE_AARCH64.
8
However this isn't right for three cases:
9
* the qemu-system-arm 'max' CPU, which is supposed to be
10
a variant on a Cortex-A57; it ought to use the same
11
encoding the A57 does and which the AArch64 'max'
12
exposes to AArch32 guest code
13
* the Cortex-R52, which is AArch32-only but has the CBAR
14
at the newer encoding (and where we incorrectly are
15
not yet setting ARM_FEATURE_CBAR_RO anyway)
16
* any possible future support for other v8 AArch32
17
only CPUs, or for supporting "boot the CPU into
18
AArch32 mode" on our existing cores like the A57 etc
19
20
Make the decision of the encoding be based on whether
21
the CPU implements the ARM_FEATURE_V8 flag instead.
22
23
This changes the behaviour only for the qemu-system-arm
24
'-cpu max'. We don't expect anybody to be relying on the
25
old behaviour because:
26
* it's not what the real hardware Cortex-A57 does
27
(and that's what our ID register claims we are)
28
* we don't implement the memory-mapped GICv3 support
29
which is the only thing that exists at the peripheral
30
base address pointed to by the register
2
31
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
33
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
34
Message-id: 20240206132931.38376-2-peter.maydell@linaro.org
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20200507151819.28444-6-peter.maydell@linaro.org
8
---
35
---
9
docs/system/arm/musca.rst | 31 +++++++++++++++++++++++++++++++
36
target/arm/helper.c | 2 +-
10
docs/system/target-arm.rst | 1 +
37
1 file changed, 1 insertion(+), 1 deletion(-)
11
MAINTAINERS | 1 +
12
3 files changed, 33 insertions(+)
13
create mode 100644 docs/system/arm/musca.rst
14
38
15
diff --git a/docs/system/arm/musca.rst b/docs/system/arm/musca.rst
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
new file mode 100644
17
index XXXXXXX..XXXXXXX
18
--- /dev/null
19
+++ b/docs/system/arm/musca.rst
20
@@ -XXX,XX +XXX,XX @@
21
+Arm Musca boards (``musca-a``, ``musca-b1``)
22
+============================================
23
+
24
+The Arm Musca development boards are a reference implementation
25
+of a system using the SSE-200 Subsystem for Embedded. They are
26
+dual Cortex-M33 systems.
27
+
28
+QEMU provides models of the A and B1 variants of this board.
29
+
30
+Unimplemented devices:
31
+
32
+- SPI
33
+- |I2C|
34
+- |I2S|
35
+- PWM
36
+- QSPI
37
+- Timer
38
+- SCC
39
+- GPIO
40
+- eFlash
41
+- MHU
42
+- PVT
43
+- SDIO
44
+- CryptoCell
45
+
46
+Note that (like the real hardware) the Musca-A machine is
47
+asymmetric: CPU 0 does not have the FPU or DSP extensions,
48
+but CPU 1 does. Also like the real hardware, the memory maps
49
+for the A and B1 variants differ significantly, so guest
50
+software must be built for the right variant.
51
+
52
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
53
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
54
--- a/docs/system/target-arm.rst
41
--- a/target/arm/helper.c
55
+++ b/docs/system/target-arm.rst
42
+++ b/target/arm/helper.c
56
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
43
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
57
44
* AArch64 cores we might need to add a specific feature flag
58
arm/integratorcp
45
* to indicate cores with "flavour 2" CBAR.
59
arm/mps2
46
*/
60
+ arm/musca
47
- if (arm_feature(env, ARM_FEATURE_AARCH64)) {
61
arm/realview
48
+ if (arm_feature(env, ARM_FEATURE_V8)) {
62
arm/versatile
49
/* 32 bit view is [31:18] 0...0 [43:32]. */
63
arm/vexpress
50
uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
64
diff --git a/MAINTAINERS b/MAINTAINERS
51
| extract64(cpu->reset_cbar, 32, 12);
65
index XXXXXXX..XXXXXXX 100644
66
--- a/MAINTAINERS
67
+++ b/MAINTAINERS
68
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
69
L: qemu-arm@nongnu.org
70
S: Maintained
71
F: hw/arm/musca.c
72
+F: docs/system/arm/musca.rst
73
74
Musicpal
75
M: Jan Kiszka <jan.kiszka@web.de>
76
--
52
--
77
2.20.1
53
2.34.1
78
79
diff view generated by jsdifflib
[PULL 27/29] target/arm: Allow user-mode code to write CPSR.E via MSR
[PULL 24/35] target/arm: The Cortex-R52 has a read-only CBAR
1
Using the MSR instruction to write to CPSR.E is deprecated, but it is
1
The Cortex-R52 implements the Configuration Base Address Register
2
required to work from any mode including unprivileged code. We were
2
(CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU
3
incorrectly forbidding usermode code from writing it because
3
type, so that our implementation provides the register and the
4
CPSR_USER did not include the CPSR_E bit.
4
associated qdev property.
5
6
We use CPSR_USER in only three places:
7
* as the mask of what to allow userspace MSR to write to CPSR
8
* when deciding what bits a linux-user signal-return should be
9
able to write from the sigcontext structure
10
* in target_user_copy_regs() when we set up the initial
11
registers for the linux-user process
12
13
In the first two cases not being able to update CPSR.E is a bug, and
14
in the third case it doesn't matter because CPSR.E is always 0 there.
15
So we can fix both bugs by adding CPSR_E to CPSR_USER.
16
17
Because the cpsr_write() in restore_sigcontext() is now changing
18
a CPSR bit which is cached in hflags, we need to add an
19
arm_rebuild_hflags() call there; the callsite in
20
target_user_copy_regs() was already rebuilding hflags for other
21
reasons.
22
23
(The recommended way to change CPSR.E is to use the 'SETEND'
24
instruction, which we do correctly allow from usermode code.)
25
5
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
28
Message-id: 20200518142801.20503-1-peter.maydell@linaro.org
8
Message-id: 20240206132931.38376-3-peter.maydell@linaro.org
29
---
9
---
30
target/arm/cpu.h | 2 +-
10
target/arm/tcg/cpu32.c | 1 +
31
linux-user/arm/signal.c | 1 +
11
1 file changed, 1 insertion(+)
32
2 files changed, 2 insertions(+), 1 deletion(-)
33
12
34
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
13
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
35
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/cpu.h
15
--- a/target/arm/tcg/cpu32.c
37
+++ b/target/arm/cpu.h
16
+++ b/target/arm/tcg/cpu32.c
38
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
39
#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
18
set_feature(&cpu->env, ARM_FEATURE_PMSA);
40
| CPSR_NZCV)
19
set_feature(&cpu->env, ARM_FEATURE_NEON);
41
/* Bits writable in user mode. */
20
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
42
-#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
21
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
43
+#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
22
cpu->midr = 0x411fd133; /* r1p3 */
44
/* Execution state bits. MRS read as zero, MSR writes ignored. */
23
cpu->revidr = 0x00000000;
45
#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
24
cpu->reset_fpsid = 0x41034023;
46
47
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/linux-user/arm/signal.c
50
+++ b/linux-user/arm/signal.c
51
@@ -XXX,XX +XXX,XX @@ restore_sigcontext(CPUARMState *env, struct target_sigcontext *sc)
52
#ifdef TARGET_CONFIG_CPU_32
53
__get_user(cpsr, &sc->arm_cpsr);
54
cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr);
55
+ arm_rebuild_hflags(env);
56
#endif
57
58
err |= !valid_user_regs(env);
59
--
25
--
60
2.20.1
26
2.34.1
61
62
diff view generated by jsdifflib
[PULL 15/29] hw/arm/fsl-imx31: Wire up watchdog
[PULL 25/35] target/arm: Add Cortex-R52 IMPDEF sysregs
1
From: Guenter Roeck <linux@roeck-us.net>
1
Add the Cortex-R52 IMPDEF sysregs, by defining them here and
2
also by enabling the AUXCR feature which defines the ACTLR
3
and HACTLR registers. As is our usual practice, we make these
4
simple reads-as-zero stubs for now.
2
5
3
With this patch, the watchdog on i.MX31 emulations is fully operational.
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20240206132931.38376-4-peter.maydell@linaro.org
9
---
10
target/arm/tcg/cpu32.c | 108 +++++++++++++++++++++++++++++++++++++++++
11
1 file changed, 108 insertions(+)
4
12
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
6
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
7
Message-id: 20200517162135.110364-5-linux@roeck-us.net
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
include/hw/arm/fsl-imx31.h | 4 ++++
11
hw/arm/fsl-imx31.c | 6 ++++++
12
hw/arm/Kconfig | 1 +
13
3 files changed, 11 insertions(+)
14
15
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/fsl-imx31.h
15
--- a/target/arm/tcg/cpu32.c
18
+++ b/include/hw/arm/fsl-imx31.h
16
+++ b/target/arm/tcg/cpu32.c
19
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
20
#include "hw/timer/imx_epit.h"
18
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
21
#include "hw/i2c/imx_i2c.h"
19
}
22
#include "hw/gpio/imx_gpio.h"
20
23
+#include "hw/watchdog/wdt_imx2.h"
21
+static const ARMCPRegInfo cortex_r52_cp_reginfo[] = {
24
#include "exec/memory.h"
22
+ { .name = "CPUACTLR", .cp = 15, .opc1 = 0, .crm = 15,
25
#include "target/arm/cpu.h"
23
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
26
24
+ { .name = "IMP_ATCMREGIONR",
27
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX31State {
25
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
28
IMXEPITState epit[FSL_IMX31_NUM_EPITS];
26
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
29
IMXI2CState i2c[FSL_IMX31_NUM_I2CS];
27
+ { .name = "IMP_BTCMREGIONR",
30
IMXGPIOState gpio[FSL_IMX31_NUM_GPIOS];
28
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
31
+ IMX2WdtState wdt;
29
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
32
MemoryRegion secure_rom;
30
+ { .name = "IMP_CTCMREGIONR",
33
MemoryRegion rom;
31
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2,
34
MemoryRegion iram;
32
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
35
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX31State {
33
+ { .name = "IMP_CSCTLR",
36
#define FSL_IMX31_GPIO1_SIZE 0x4000
34
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0,
37
#define FSL_IMX31_GPIO2_ADDR 0x53FD0000
35
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
38
#define FSL_IMX31_GPIO2_SIZE 0x4000
36
+ { .name = "IMP_BPCTLR",
39
+#define FSL_IMX31_WDT_ADDR 0x53FDC000
37
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1,
40
+#define FSL_IMX31_WDT_SIZE 0x4000
38
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
41
#define FSL_IMX31_AVIC_ADDR 0x68000000
39
+ { .name = "IMP_MEMPROTCLR",
42
#define FSL_IMX31_AVIC_SIZE 0x100
40
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2,
43
#define FSL_IMX31_SDRAM0_ADDR 0x80000000
41
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
44
diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c
42
+ { .name = "IMP_SLAVEPCTLR",
45
index XXXXXXX..XXXXXXX 100644
43
+ .cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0,
46
--- a/hw/arm/fsl-imx31.c
44
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
47
+++ b/hw/arm/fsl-imx31.c
45
+ { .name = "IMP_PERIPHREGIONR",
48
@@ -XXX,XX +XXX,XX @@ static void fsl_imx31_init(Object *obj)
46
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
49
sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
47
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
50
TYPE_IMX_GPIO);
48
+ { .name = "IMP_FLASHIFREGIONR",
51
}
49
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1,
50
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
51
+ { .name = "IMP_BUILDOPTR",
52
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
53
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
54
+ { .name = "IMP_PINOPTR",
55
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
56
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
57
+ { .name = "IMP_QOSR",
58
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 1,
59
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
60
+ { .name = "IMP_BUSTIMEOUTR",
61
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 2,
62
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
63
+ { .name = "IMP_INTMONR",
64
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 4,
65
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
66
+ { .name = "IMP_ICERR0",
67
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 0,
68
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
69
+ { .name = "IMP_ICERR1",
70
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1,
71
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
72
+ { .name = "IMP_DCERR0",
73
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0,
74
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
75
+ { .name = "IMP_DCERR1",
76
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 1,
77
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
78
+ { .name = "IMP_TCMERR0",
79
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 0,
80
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
81
+ { .name = "IMP_TCMERR1",
82
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 1,
83
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
84
+ { .name = "IMP_TCMSYNDR0",
85
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 2,
86
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
87
+ { .name = "IMP_TCMSYNDR1",
88
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 3,
89
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
90
+ { .name = "IMP_FLASHERR0",
91
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 0,
92
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
93
+ { .name = "IMP_FLASHERR1",
94
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 1,
95
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
96
+ { .name = "IMP_CDBGDR0",
97
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 0,
98
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
99
+ { .name = "IMP_CBDGBR1",
100
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1,
101
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
102
+ { .name = "IMP_TESTR0",
103
+ .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 0,
104
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
105
+ { .name = "IMP_TESTR1",
106
+ .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1,
107
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
108
+ { .name = "IMP_CDBGDCI",
109
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 15, .opc2 = 0,
110
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
111
+ { .name = "IMP_CDBGDCT",
112
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 0,
113
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
114
+ { .name = "IMP_CDBGICT",
115
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 1,
116
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
117
+ { .name = "IMP_CDBGDCD",
118
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 0,
119
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
120
+ { .name = "IMP_CDBGICD",
121
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 1,
122
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
123
+};
52
+
124
+
53
+ sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), TYPE_IMX2_WDT);
125
+
126
static void cortex_r52_initfn(Object *obj)
127
{
128
ARMCPU *cpu = ARM_CPU(obj);
129
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
130
set_feature(&cpu->env, ARM_FEATURE_NEON);
131
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
132
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
133
+ set_feature(&cpu->env, ARM_FEATURE_AUXCR);
134
cpu->midr = 0x411fd133; /* r1p3 */
135
cpu->revidr = 0x00000000;
136
cpu->reset_fpsid = 0x41034023;
137
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
138
139
cpu->pmsav7_dregion = 16;
140
cpu->pmsav8r_hdregion = 16;
141
+
142
+ define_arm_cp_regs(cpu, cortex_r52_cp_reginfo);
54
}
143
}
55
144
56
static void fsl_imx31_realize(DeviceState *dev, Error **errp)
145
static void cortex_r5f_initfn(Object *obj)
57
@@ -XXX,XX +XXX,XX @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
58
gpio_table[i].irq));
59
}
60
61
+ /* Watchdog */
62
+ object_property_set_bool(OBJECT(&s->wdt), true, "realized", &error_abort);
63
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX31_WDT_ADDR);
64
+
65
/* On a real system, the first 16k is a `secure boot rom' */
66
memory_region_init_rom(&s->secure_rom, OBJECT(dev), "imx31.secure_rom",
67
FSL_IMX31_SECURE_ROM_SIZE, &err);
68
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/arm/Kconfig
71
+++ b/hw/arm/Kconfig
72
@@ -XXX,XX +XXX,XX @@ config FSL_IMX31
73
select SERIAL
74
select IMX
75
select IMX_I2C
76
+ select WDT_IMX2
77
select LAN9118
78
79
config FSL_IMX6
80
--
146
--
81
2.20.1
147
2.34.1
82
83
diff view generated by jsdifflib
[PULL 11/29] target/arm: Remove unused GEN_NEON_INTEGER_OP macro
[PULL 26/35] target/arm: Allow access to SPSR_hyp from hyp mode
1
The GEN_NEON_INTEGER_OP macro is no longer used; remove it.
1
Architecturally, the AArch32 MSR/MRS to/from banked register
2
instructions are UNPREDICTABLE for attempts to access a banked
3
register that the guest could access in a more direct way (e.g.
4
using this insn to access r8_fiq when already in FIQ mode). QEMU has
5
chosen to UNDEF on all of these.
6
7
However, for the case of accessing SPSR_hyp from hyp mode, it turns
8
out that real hardware permits this, with the same effect as if the
9
guest had directly written to SPSR. Further, there is some
10
guest code out there that assumes it can do this, because it
11
happens to work on hardware: an example Cortex-R52 startup code
12
fragment uses this, and it got copied into various other places,
13
including Zephyr. Zephyr was fixed to not use this:
14
https://github.com/zephyrproject-rtos/zephyr/issues/47330
15
but other examples are still out there, like the selftest
16
binary for the MPS3-AN536.
17
18
For convenience of being able to run guest code, permit
19
this UNPREDICTABLE access instead of UNDEFing it.
2
20
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Message-id: 20240206132931.38376-5-peter.maydell@linaro.org
5
---
24
---
6
target/arm/translate.c | 23 -----------------------
25
target/arm/tcg/op_helper.c | 43 ++++++++++++++++++++++++++------------
7
1 file changed, 23 deletions(-)
26
target/arm/tcg/translate.c | 19 +++++++++++------
27
2 files changed, 43 insertions(+), 19 deletions(-)
8
28
9
diff --git a/target/arm/translate.c b/target/arm/translate.c
29
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
10
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
11
--- a/target/arm/translate.c
31
--- a/target/arm/tcg/op_helper.c
12
+++ b/target/arm/translate.c
32
+++ b/target/arm/tcg/op_helper.c
13
@@ -XXX,XX +XXX,XX @@ static inline void gen_neon_rsb(int size, TCGv_i32 t0, TCGv_i32 t1)
33
@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
14
default: return 1; \
34
*/
15
}} while (0)
35
int curmode = env->uncached_cpsr & CPSR_M;
16
36
17
-#define GEN_NEON_INTEGER_OP(name) do { \
37
- if (regno == 17) {
18
- switch ((size << 1) | u) { \
38
- /* ELR_Hyp: a special case because access from tgtmode is OK */
19
- case 0: \
39
- if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
20
- gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
40
- goto undef;
21
- break; \
41
+ if (tgtmode == ARM_CPU_MODE_HYP) {
22
- case 1: \
42
+ /*
23
- gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
43
+ * Handle Hyp target regs first because some are special cases
24
- break; \
44
+ * which don't want the usual "not accessible from tgtmode" check.
25
- case 2: \
45
+ */
26
- gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
46
+ switch (regno) {
27
- break; \
47
+ case 16 ... 17: /* ELR_Hyp, SPSR_Hyp */
28
- case 3: \
48
+ if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
29
- gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
49
+ goto undef;
30
- break; \
50
+ }
31
- case 4: \
51
+ break;
32
- gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
52
+ case 13:
33
- break; \
53
+ if (curmode != ARM_CPU_MODE_MON) {
34
- case 5: \
54
+ goto undef;
35
- gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
55
+ }
36
- break; \
56
+ break;
37
- default: return 1; \
57
+ default:
38
- }} while (0)
58
+ g_assert_not_reached();
59
}
60
return;
61
}
62
@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
63
}
64
}
65
66
- if (tgtmode == ARM_CPU_MODE_HYP) {
67
- /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */
68
- if (curmode != ARM_CPU_MODE_MON) {
69
- goto undef;
70
- }
71
- }
39
-
72
-
40
static TCGv_i32 neon_load_scratch(int scratch)
73
return;
41
{
74
42
TCGv_i32 tmp = tcg_temp_new_i32();
75
undef:
76
@@ -XXX,XX +XXX,XX @@ void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode,
77
78
switch (regno) {
79
case 16: /* SPSRs */
80
- env->banked_spsr[bank_number(tgtmode)] = value;
81
+ if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
82
+ /* Only happens for SPSR_Hyp access in Hyp mode */
83
+ env->spsr = value;
84
+ } else {
85
+ env->banked_spsr[bank_number(tgtmode)] = value;
86
+ }
87
break;
88
case 17: /* ELR_Hyp */
89
env->elr_el[2] = value;
90
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno)
91
92
switch (regno) {
93
case 16: /* SPSRs */
94
- return env->banked_spsr[bank_number(tgtmode)];
95
+ if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
96
+ /* Only happens for SPSR_Hyp access in Hyp mode */
97
+ return env->spsr;
98
+ } else {
99
+ return env->banked_spsr[bank_number(tgtmode)];
100
+ }
101
case 17: /* ELR_Hyp */
102
return env->elr_el[2];
103
case 13:
104
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/target/arm/tcg/translate.c
107
+++ b/target/arm/tcg/translate.c
108
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
109
break;
110
case ARM_CPU_MODE_HYP:
111
/*
112
- * SPSR_hyp and r13_hyp can only be accessed from Monitor mode
113
- * (and so we can forbid accesses from EL2 or below). elr_hyp
114
- * can be accessed also from Hyp mode, so forbid accesses from
115
- * EL0 or EL1.
116
+ * r13_hyp can only be accessed from Monitor mode, and so we
117
+ * can forbid accesses from EL2 or below.
118
+ * elr_hyp can be accessed also from Hyp mode, so forbid
119
+ * accesses from EL0 or EL1.
120
+ * SPSR_hyp is supposed to be in the same category as r13_hyp
121
+ * and UNPREDICTABLE if accessed from anything except Monitor
122
+ * mode. However there is some real-world code that will do
123
+ * it because at least some hardware happens to permit the
124
+ * access. (Notably a standard Cortex-R52 startup code fragment
125
+ * does this.) So we permit SPSR_hyp from Hyp mode also, to allow
126
+ * this (incorrect) guest code to run.
127
*/
128
- if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2 ||
129
- (s->current_el < 3 && *regno != 17)) {
130
+ if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2
131
+ || (s->current_el < 3 && *regno != 16 && *regno != 17)) {
132
goto undef;
133
}
134
break;
43
--
135
--
44
2.20.1
136
2.34.1
45
46
diff view generated by jsdifflib
[PULL 03/29] docs/system: Sort Arm board index into alphabetical order
[PULL 27/35] hw/misc/mps2-scc: Fix condition for CFG3 register
1
Sort the board index into alphabetical order. (Note that we need to
1
We currently guard the CFG3 register read with
2
sort alphabetically by the title text of each file, which isn't the
2
(scc_partno(s) == 0x524 && scc_partno(s) == 0x547)
3
same ordering as sorting by the filename.)
3
which is clearly wrong as it is never true.
4
4
5
This register is present on all board types except AN524
6
and AN527; correct the condition.
7
8
Fixes: 6ac80818941829c0 ("hw/misc/mps2-scc: Implement changes for AN547")
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 20240206132931.38376-6-peter.maydell@linaro.org
9
Message-id: 20200507151819.28444-3-peter.maydell@linaro.org
10
---
13
---
11
docs/system/target-arm.rst | 17 +++++++++++------
14
hw/misc/mps2-scc.c | 2 +-
12
1 file changed, 11 insertions(+), 6 deletions(-)
15
1 file changed, 1 insertion(+), 1 deletion(-)
13
16
14
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
17
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/target-arm.rst
19
--- a/hw/misc/mps2-scc.c
17
+++ b/docs/system/target-arm.rst
20
+++ b/hw/misc/mps2-scc.c
18
@@ -XXX,XX +XXX,XX @@ Unfortunately many of the Arm boards QEMU supports are currently
21
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
19
undocumented; you can get a complete list by running
22
r = s->cfg2;
20
``qemu-system-aarch64 --machine help``.
23
break;
21
24
case A_CFG3:
22
+..
25
- if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) {
23
+ This table of contents should be kept sorted alphabetically
26
+ if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
24
+ by the title text of each file, which isn't the same ordering
27
/* CFG3 reserved on AN524 */
25
+ as an alphabetical sort by filename.
28
goto bad_offset;
26
+
29
}
27
.. toctree::
28
:maxdepth: 1
29
30
arm/integratorcp
31
- arm/versatile
32
arm/realview
33
- arm/xscale
34
- arm/palm
35
- arm/nseries
36
- arm/stellaris
37
+ arm/versatile
38
arm/musicpal
39
- arm/sx1
40
+ arm/nseries
41
arm/orangepi
42
+ arm/palm
43
+ arm/xscale
44
+ arm/sx1
45
+ arm/stellaris
46
47
Arm CPU features
48
================
49
--
30
--
50
2.20.1
31
2.34.1
51
32
52
33
diff view generated by jsdifflib
[PULL 04/29] docs/system: Document Arm Versatile Express boards
[PULL 28/35] hw/misc/mps2-scc: Factor out which-board conditionals
1
Provide a minimal documentation of the Versatile Express boards
1
The MPS SCC device has a lot of different flavours for the various
2
(vexpress-a9, vexpress-a15).
2
different MPS FPGA images, which look mostly similar but have
3
differences in how particular registers are handled. Currently we
4
deal with this with a lot of open-coded checks on scc_partno(), but
5
as we add more board types this is getting a bit hard to read.
6
7
Factor out the conditions into some functions which we can
8
give more descriptive names to.
3
9
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
Message-id: 20240206132931.38376-7-peter.maydell@linaro.org
8
Message-id: 20200507151819.28444-4-peter.maydell@linaro.org
9
---
14
---
10
docs/system/arm/vexpress.rst | 60 ++++++++++++++++++++++++++++++++++++
15
hw/misc/mps2-scc.c | 45 +++++++++++++++++++++++++++++++--------------
11
docs/system/target-arm.rst | 1 +
16
1 file changed, 31 insertions(+), 14 deletions(-)
12
MAINTAINERS | 1 +
13
3 files changed, 62 insertions(+)
14
create mode 100644 docs/system/arm/vexpress.rst
15
17
16
diff --git a/docs/system/arm/vexpress.rst b/docs/system/arm/vexpress.rst
18
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
17
new file mode 100644
19
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX
20
--- a/hw/misc/mps2-scc.c
19
--- /dev/null
21
+++ b/hw/misc/mps2-scc.c
20
+++ b/docs/system/arm/vexpress.rst
22
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
21
@@ -XXX,XX +XXX,XX @@
23
return extract32(s->id, 4, 8);
22
+Arm Versatile Express boards (``vexpress-a9``, ``vexpress-a15``)
24
}
23
+================================================================
25
26
+/* Is CFG_REG2 present? */
27
+static bool have_cfg2(MPS2SCC *s)
28
+{
29
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
30
+}
24
+
31
+
25
+QEMU models two variants of the Arm Versatile Express development
32
+/* Is CFG_REG3 present? */
26
+board family:
33
+static bool have_cfg3(MPS2SCC *s)
34
+{
35
+ return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
36
+}
27
+
37
+
28
+- ``vexpress-a9`` models the combination of the Versatile Express
38
+/* Is CFG_REG5 present? */
29
+ motherboard and the CoreTile Express A9x4 daughterboard
39
+static bool have_cfg5(MPS2SCC *s)
30
+- ``vexpress-a15`` models the combination of the Versatile Express
40
+{
31
+ motherboard and the CoreTile Express A15x2 daughterboard
41
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
42
+}
32
+
43
+
33
+Note that as this hardware does not have PCI, IDE or SCSI,
44
+/* Is CFG_REG6 present? */
34
+the only available storage option is emulated SD card.
45
+static bool have_cfg6(MPS2SCC *s)
46
+{
47
+ return scc_partno(s) == 0x524;
48
+}
35
+
49
+
36
+Implemented devices:
50
/* Handle a write via the SYS_CFG channel to the specified function/device.
37
+
51
* Return false on error (reported to guest via SYS_CFGCTRL ERROR bit).
38
+- PL041 audio
52
*/
39
+- PL181 SD controller
53
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
40
+- PL050 keyboard and mouse
54
r = s->cfg1;
41
+- PL011 UARTs
55
break;
42
+- SP804 timers
56
case A_CFG2:
43
+- I2C controller
57
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
44
+- PL031 RTC
58
- /* CFG2 reserved on other boards */
45
+- PL111 LCD display controller
59
+ if (!have_cfg2(s)) {
46
+- Flash memory
60
goto bad_offset;
47
+- LAN9118 ethernet
61
}
48
+
62
r = s->cfg2;
49
+Unimplemented devices:
63
break;
50
+
64
case A_CFG3:
51
+- SP810 system control block
65
- if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
52
+- PCI-express
66
- /* CFG3 reserved on AN524 */
53
+- USB controller (Philips ISP1761)
67
+ if (!have_cfg3(s)) {
54
+- Local DAP ROM
68
goto bad_offset;
55
+- CoreSight interfaces
69
}
56
+- PL301 AXI interconnect
70
/* These are user-settable DIP switches on the board. We don't
57
+- SCC
71
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
58
+- System counter
72
r = s->cfg4;
59
+- HDLCD controller (``vexpress-a15``)
73
break;
60
+- SP805 watchdog
74
case A_CFG5:
61
+- PL341 dynamic memory controller
75
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
62
+- DMA330 DMA controller
76
- /* CFG5 reserved on other boards */
63
+- PL354 static memory controller
77
+ if (!have_cfg5(s)) {
64
+- BP147 TrustZone Protection Controller
78
goto bad_offset;
65
+- TrustZone Address Space Controller
79
}
66
+
80
r = s->cfg5;
67
+Other differences between the hardware and the QEMU model:
81
break;
68
+
82
case A_CFG6:
69
+- QEMU will default to creating one CPU unless you pass a different
83
- if (scc_partno(s) != 0x524) {
70
+ ``-smp`` argument
84
- /* CFG6 reserved on other boards */
71
+- QEMU allows the amount of RAM provided to be specified with the
85
+ if (!have_cfg6(s)) {
72
+ ``-m`` argument
86
goto bad_offset;
73
+- QEMU defaults to providing a CPU which does not provide either
87
}
74
+ TrustZone or the Virtualization Extensions: if you want these you
88
r = s->cfg6;
75
+ must enable them with ``-machine secure=on`` and ``-machine
89
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
76
+ virtualization=on``
90
}
77
+- QEMU provides 4 virtio-mmio virtio transports; these start at
91
break;
78
+ address ``0x10013000`` for ``vexpress-a9`` and at ``0x1c130000`` for
92
case A_CFG2:
79
+ ``vexpress-a15``, and have IRQs from 40 upwards. If a dtb is
93
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
80
+ provided on the command line then QEMU will edit it to include
94
- /* CFG2 reserved on other boards */
81
+ suitable entries describing these transports for the guest.
95
+ if (!have_cfg2(s)) {
82
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
96
goto bad_offset;
83
index XXXXXXX..XXXXXXX 100644
97
}
84
--- a/docs/system/target-arm.rst
98
/* AN524: QSPI Select signal */
85
+++ b/docs/system/target-arm.rst
99
s->cfg2 = value;
86
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
100
break;
87
arm/integratorcp
101
case A_CFG5:
88
arm/realview
102
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
89
arm/versatile
103
- /* CFG5 reserved on other boards */
90
+ arm/vexpress
104
+ if (!have_cfg5(s)) {
91
arm/musicpal
105
goto bad_offset;
92
arm/nseries
106
}
93
arm/orangepi
107
/* AN524: ACLK frequency in Hz */
94
diff --git a/MAINTAINERS b/MAINTAINERS
108
s->cfg5 = value;
95
index XXXXXXX..XXXXXXX 100644
109
break;
96
--- a/MAINTAINERS
110
case A_CFG6:
97
+++ b/MAINTAINERS
111
- if (scc_partno(s) != 0x524) {
98
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
112
- /* CFG6 reserved on other boards */
99
L: qemu-arm@nongnu.org
113
+ if (!have_cfg6(s)) {
100
S: Maintained
114
goto bad_offset;
101
F: hw/arm/vexpress.c
115
}
102
+F: docs/system/arm/vexpress.rst
116
/* AN524: Clock divider for BRAM */
103
104
Versatile PB
105
M: Peter Maydell <peter.maydell@linaro.org>
106
--
117
--
107
2.20.1
118
2.34.1
108
119
109
120
diff view generated by jsdifflib
[PULL 29/29] linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32
[PULL 29/35] hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
1
The Arm signal-handling code has some parts ifdeffed with a
1
The MPS2 SCC device is broadly the same for all FPGA images, but has
2
TARGET_CONFIG_CPU_32, which is always defined. This is a leftover
2
minor differences in the behaviour of the CFG registers depending on
3
from when this code's structure was based on the Linux kernel
3
the image. In many cases we don't really care about the functionality
4
signal handling code, where it was intended to support 26-bit
4
controlled by these registers and a reads-as-written or similar
5
Arm CPUs. The kernel dropped its CONFIG_CPU_32 in kernel commit
5
behaviour is sufficient for the moment.
6
4da8b8208eded0ba21e3 in 2009.
6
7
7
For the AN536 the required behaviour is:
8
QEMU has never had 26-bit CPU support and is unlikely to ever
8
9
add it; we certainly aren't going to support 26-bit Linux
9
* A_CFG0 has CPU reset and halt bits
10
binaries via linux-user mode. The ifdef is just unhelpful
10
- implement as reads-as-written for the moment
11
noise, so remove it entirely.
11
* A_CFG1 has flash or ATCM address 0 remap handling
12
- QEMU doesn't model this; implement as reads-as-written
13
* A_CFG2 has QSPI select (like AN524)
14
- implemented (no behaviour, as with AN524)
15
* A_CFG3 is MCC_MSB_ADDR "additional MCC addressing bits"
16
- QEMU doesn't care about these, so use the existing
17
RAZ behaviour for convenience
18
* A_CFG4 is board rev (like all other images)
19
- no change needed
20
* A_CFG5 is ACLK frq in hz (like AN524)
21
- implemented as reads-as-written, as for other boards
22
* A_CFG6 is core 0 vector table base address
23
- implemented as reads-as-written for the moment
24
* A_CFG7 is core 1 vector table base address
25
- implemented as reads-as-written for the moment
26
27
Make the changes necessary for this; leave TODO comments where
28
appropriate to indicate where we might want to come back and
29
implement things like CPU reset.
30
31
The other aspects of the device specific to this FPGA image (like the
32
values of the board ID and similar registers) will be set via the
33
device's qdev properties.
12
34
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
36
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20200518143014.20689-1-peter.maydell@linaro.org
37
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
38
Message-id: 20240206132931.38376-8-peter.maydell@linaro.org
16
---
39
---
17
linux-user/arm/signal.c | 6 ------
40
include/hw/misc/mps2-scc.h | 1 +
18
1 file changed, 6 deletions(-)
41
hw/misc/mps2-scc.c | 101 +++++++++++++++++++++++++++++++++----
19
42
2 files changed, 92 insertions(+), 10 deletions(-)
20
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
43
44
diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h
21
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
22
--- a/linux-user/arm/signal.c
46
--- a/include/hw/misc/mps2-scc.h
23
+++ b/linux-user/arm/signal.c
47
+++ b/include/hw/misc/mps2-scc.h
24
@@ -XXX,XX +XXX,XX @@ struct rt_sigframe_v2
48
@@ -XXX,XX +XXX,XX @@ struct MPS2SCC {
25
abi_ulong retcode[4];
49
uint32_t cfg4;
50
uint32_t cfg5;
51
uint32_t cfg6;
52
+ uint32_t cfg7;
53
uint32_t cfgdata_rtn;
54
uint32_t cfgdata_out;
55
uint32_t cfgctrl;
56
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/misc/mps2-scc.c
59
+++ b/hw/misc/mps2-scc.c
60
@@ -XXX,XX +XXX,XX @@ REG32(CFG3, 0xc)
61
REG32(CFG4, 0x10)
62
REG32(CFG5, 0x14)
63
REG32(CFG6, 0x18)
64
+REG32(CFG7, 0x1c)
65
REG32(CFGDATA_RTN, 0xa0)
66
REG32(CFGDATA_OUT, 0xa4)
67
REG32(CFGCTRL, 0xa8)
68
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
69
/* Is CFG_REG2 present? */
70
static bool have_cfg2(MPS2SCC *s)
71
{
72
- return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
73
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
74
+ scc_partno(s) == 0x536;
75
}
76
77
/* Is CFG_REG3 present? */
78
static bool have_cfg3(MPS2SCC *s)
79
{
80
- return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
81
+ return scc_partno(s) != 0x524 && scc_partno(s) != 0x547 &&
82
+ scc_partno(s) != 0x536;
83
}
84
85
/* Is CFG_REG5 present? */
86
static bool have_cfg5(MPS2SCC *s)
87
{
88
- return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
89
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
90
+ scc_partno(s) == 0x536;
91
}
92
93
/* Is CFG_REG6 present? */
94
static bool have_cfg6(MPS2SCC *s)
95
{
96
- return scc_partno(s) == 0x524;
97
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x536;
98
+}
99
+
100
+/* Is CFG_REG7 present? */
101
+static bool have_cfg7(MPS2SCC *s)
102
+{
103
+ return scc_partno(s) == 0x536;
104
+}
105
+
106
+/* Does CFG_REG0 drive the 'remap' GPIO output? */
107
+static bool cfg0_is_remap(MPS2SCC *s)
108
+{
109
+ return scc_partno(s) != 0x536;
110
+}
111
+
112
+/* Is CFG_REG1 driving a set of LEDs? */
113
+static bool cfg1_is_leds(MPS2SCC *s)
114
+{
115
+ return scc_partno(s) != 0x536;
116
}
117
118
/* Handle a write via the SYS_CFG channel to the specified function/device.
119
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
120
if (!have_cfg3(s)) {
121
goto bad_offset;
122
}
123
- /* These are user-settable DIP switches on the board. We don't
124
+ /*
125
+ * These are user-settable DIP switches on the board. We don't
126
* model that, so just return zeroes.
127
+ *
128
+ * TODO: for AN536 this is MCC_MSB_ADDR "additional MCC addressing
129
+ * bits". These change which part of the DDR4 the motherboard
130
+ * configuration controller can see in its memory map (see the
131
+ * appnote section 2.4). QEMU doesn't model the MCC at all, so these
132
+ * bits are not interesting to us; read-as-zero is as good as anything
133
+ * else.
134
*/
135
r = 0;
136
break;
137
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
138
}
139
r = s->cfg6;
140
break;
141
+ case A_CFG7:
142
+ if (!have_cfg7(s)) {
143
+ goto bad_offset;
144
+ }
145
+ r = s->cfg7;
146
+ break;
147
case A_CFGDATA_RTN:
148
r = s->cfgdata_rtn;
149
break;
150
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
151
* we always reflect bit 0 in the 'remap' GPIO output line,
152
* and let the board wire it up or not as it chooses.
153
* TODO on some boards bit 1 is CPU_WAIT.
154
+ *
155
+ * TODO: on the AN536 this register controls reset and halt
156
+ * for both CPUs. For the moment we don't implement this, so the
157
+ * register just reads as written.
158
*/
159
s->cfg0 = value;
160
- qemu_set_irq(s->remap, s->cfg0 & 1);
161
+ if (cfg0_is_remap(s)) {
162
+ qemu_set_irq(s->remap, s->cfg0 & 1);
163
+ }
164
break;
165
case A_CFG1:
166
s->cfg1 = value;
167
- for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
168
- led_set_state(s->led[i], extract32(value, i, 1));
169
+ /*
170
+ * On most boards this register drives LEDs.
171
+ *
172
+ * TODO: for AN536 this controls whether flash and ATCM are
173
+ * enabled or disabled on reset. QEMU doesn't model this, and
174
+ * always wires up RAM in the ATCM area and ROM in the flash area.
175
+ */
176
+ if (cfg1_is_leds(s)) {
177
+ for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
178
+ led_set_state(s->led[i], extract32(value, i, 1));
179
+ }
180
}
181
break;
182
case A_CFG2:
183
if (!have_cfg2(s)) {
184
goto bad_offset;
185
}
186
- /* AN524: QSPI Select signal */
187
+ /* AN524, AN536: QSPI Select signal */
188
s->cfg2 = value;
189
break;
190
case A_CFG5:
191
if (!have_cfg5(s)) {
192
goto bad_offset;
193
}
194
- /* AN524: ACLK frequency in Hz */
195
+ /* AN524, AN536: ACLK frequency in Hz */
196
s->cfg5 = value;
197
break;
198
case A_CFG6:
199
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
200
goto bad_offset;
201
}
202
/* AN524: Clock divider for BRAM */
203
+ /* AN536: Core 0 vector table base address */
204
+ s->cfg6 = value;
205
+ break;
206
+ case A_CFG7:
207
+ if (!have_cfg7(s)) {
208
+ goto bad_offset;
209
+ }
210
+ /* AN536: Core 1 vector table base address */
211
s->cfg6 = value;
212
break;
213
case A_CFGDATA_OUT:
214
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_finalize(Object *obj)
215
g_free(s->oscclk_reset);
216
}
217
218
+static bool cfg7_needed(void *opaque)
219
+{
220
+ MPS2SCC *s = opaque;
221
+
222
+ return have_cfg7(s);
223
+}
224
+
225
+static const VMStateDescription vmstate_cfg7 = {
226
+ .name = "mps2-scc/cfg7",
227
+ .version_id = 1,
228
+ .minimum_version_id = 1,
229
+ .needed = cfg7_needed,
230
+ .fields = (const VMStateField[]) {
231
+ VMSTATE_UINT32(cfg7, MPS2SCC),
232
+ VMSTATE_END_OF_LIST()
233
+ }
234
+};
235
+
236
static const VMStateDescription mps2_scc_vmstate = {
237
.name = "mps2-scc",
238
.version_id = 3,
239
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription mps2_scc_vmstate = {
240
VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk,
241
0, vmstate_info_uint32, uint32_t),
242
VMSTATE_END_OF_LIST()
243
+ },
244
+ .subsections = (const VMStateDescription * const []) {
245
+ &vmstate_cfg7,
246
+ NULL
247
}
26
};
248
};
27
249
28
-#define TARGET_CONFIG_CPU_32 1
29
-
30
/*
31
* For ARM syscalls, we encode the syscall number into the instruction.
32
*/
33
@@ -XXX,XX +XXX,XX @@ setup_sigcontext(struct target_sigcontext *sc, /*struct _fpstate *fpstate,*/
34
__put_user(env->regs[13], &sc->arm_sp);
35
__put_user(env->regs[14], &sc->arm_lr);
36
__put_user(env->regs[15], &sc->arm_pc);
37
-#ifdef TARGET_CONFIG_CPU_32
38
__put_user(cpsr_read(env), &sc->arm_cpsr);
39
-#endif
40
41
__put_user(/* current->thread.trap_no */ 0, &sc->trap_no);
42
__put_user(/* current->thread.error_code */ 0, &sc->error_code);
43
@@ -XXX,XX +XXX,XX @@ restore_sigcontext(CPUARMState *env, struct target_sigcontext *sc)
44
__get_user(env->regs[13], &sc->arm_sp);
45
__get_user(env->regs[14], &sc->arm_lr);
46
__get_user(env->regs[15], &sc->arm_pc);
47
-#ifdef TARGET_CONFIG_CPU_32
48
__get_user(cpsr, &sc->arm_cpsr);
49
cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr);
50
arm_rebuild_hflags(env);
51
-#endif
52
53
err |= !valid_user_regs(env);
54
55
--
250
--
56
2.20.1
251
2.34.1
57
252
58
253
diff view generated by jsdifflib
[PULL 01/29] tests/acceptance: Add a test for the canon-a1100 machine
[PULL 30/35] hw/arm/mps3r: Initial skeleton for mps3-an536 board
1
From: Thomas Huth <thuth@redhat.com>
1
The AN536 is another FPGA image for the MPS3 development board. Unlike
2
2
the existing FPGA images we already model, this board uses a Cortex-R
3
The canon-a1100 machine can be used with the Barebox firmware. The
3
family CPU, and it does not use any equivalent to the M-profile
4
QEMU Advent Calendar 2018 features a pre-compiled image which we
4
"Subsystem for Embedded" SoC-equivalent that we model in hw/arm/armsse.c.
5
can use for testing.
5
It's therefore more convenient for us to model it as a completely
6
6
separate C file.
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
This commit adds the basic skeleton of the board model, and the
9
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
9
code to create all the RAM and ROM. We assume that we're probably
10
Tested-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
10
going to want to add more images in future, so use the same
11
Signed-off-by: Thomas Huth <thuth@redhat.com>
11
base class/subclass setup that mps2-tz.c uses, even though at
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
the moment there's only a single subclass.
13
Message-id: 20200514190422.23645-1-f4bug@amsat.org
13
14
Message-Id: <20200129090420.13954-1-thuth@redhat.com>
14
Following commits will add the CPUs and the peripherals.
15
[PMD: Rebased MAINTAINERS]
15
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
18
Message-id: 20240206132931.38376-9-peter.maydell@linaro.org
18
---
19
---
19
MAINTAINERS | 1 +
20
MAINTAINERS | 3 +-
20
tests/acceptance/machine_arm_canona1100.py | 35 ++++++++++++++++++++++
21
configs/devices/arm-softmmu/default.mak | 1 +
21
2 files changed, 36 insertions(+)
22
hw/arm/mps3r.c | 239 ++++++++++++++++++++++++
22
create mode 100644 tests/acceptance/machine_arm_canona1100.py
23
hw/arm/Kconfig | 5 +
24
hw/arm/meson.build | 1 +
25
5 files changed, 248 insertions(+), 1 deletion(-)
26
create mode 100644 hw/arm/mps3r.c
23
27
24
diff --git a/MAINTAINERS b/MAINTAINERS
28
diff --git a/MAINTAINERS b/MAINTAINERS
25
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
26
--- a/MAINTAINERS
30
--- a/MAINTAINERS
27
+++ b/MAINTAINERS
31
+++ b/MAINTAINERS
28
@@ -XXX,XX +XXX,XX @@ S: Odd Fixes
32
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/imx7_*.h
29
F: include/hw/arm/digic.h
33
F: hw/pci-host/designware.c
30
F: hw/*/digic*
34
F: include/hw/pci-host/designware.h
31
F: include/hw/*/digic*
35
32
+F: tests/acceptance/machine_arm_canona1100.py
36
-MPS2
33
37
+MPS2 / MPS3
34
Goldfish RTC
38
M: Peter Maydell <peter.maydell@linaro.org>
35
M: Anup Patel <anup.patel@wdc.com>
39
L: qemu-arm@nongnu.org
36
diff --git a/tests/acceptance/machine_arm_canona1100.py b/tests/acceptance/machine_arm_canona1100.py
40
S: Maintained
41
F: hw/arm/mps2.c
42
F: hw/arm/mps2-tz.c
43
+F: hw/arm/mps3r.c
44
F: hw/misc/mps2-*.c
45
F: include/hw/misc/mps2-*.h
46
F: hw/arm/armsse.c
47
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
48
index XXXXXXX..XXXXXXX 100644
49
--- a/configs/devices/arm-softmmu/default.mak
50
+++ b/configs/devices/arm-softmmu/default.mak
51
@@ -XXX,XX +XXX,XX @@ CONFIG_ARM_VIRT=y
52
# CONFIG_INTEGRATOR=n
53
# CONFIG_FSL_IMX31=n
54
# CONFIG_MUSICPAL=n
55
+# CONFIG_MPS3R=n
56
# CONFIG_MUSCA=n
57
# CONFIG_CHEETAH=n
58
# CONFIG_SX1=n
59
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
37
new file mode 100644
60
new file mode 100644
38
index XXXXXXX..XXXXXXX
61
index XXXXXXX..XXXXXXX
39
--- /dev/null
62
--- /dev/null
40
+++ b/tests/acceptance/machine_arm_canona1100.py
63
+++ b/hw/arm/mps3r.c
41
@@ -XXX,XX +XXX,XX @@
64
@@ -XXX,XX +XXX,XX @@
42
+# Functional test that boots the canon-a1100 machine with firmware
65
+/*
43
+#
66
+ * Arm MPS3 board emulation for Cortex-R-based FPGA images.
44
+# Copyright (c) 2020 Red Hat, Inc.
67
+ * (For M-profile images see mps2.c and mps2tz.c.)
45
+#
68
+ *
46
+# Author:
69
+ * Copyright (c) 2017 Linaro Limited
47
+# Thomas Huth <thuth@redhat.com>
70
+ * Written by Peter Maydell
48
+#
71
+ *
49
+# This work is licensed under the terms of the GNU GPL, version 2 or
72
+ * This program is free software; you can redistribute it and/or modify
50
+# later. See the COPYING file in the top-level directory.
73
+ * it under the terms of the GNU General Public License version 2 or
51
+
74
+ * (at your option) any later version.
52
+from avocado_qemu import Test
75
+ */
53
+from avocado_qemu import wait_for_console_pattern
76
+
54
+from avocado.utils import archive
77
+/*
55
+
78
+ * The MPS3 is an FPGA based dev board. This file handles FPGA images
56
+class CanonA1100Machine(Test):
79
+ * which use the Cortex-R CPUs. We model these separately from the
57
+ """Boots the barebox firmware and checks that the console is operational"""
80
+ * M-profile images, because on M-profile the FPGA image is based on
58
+
81
+ * a "Subsystem for Embedded" which is similar to an SoC, whereas
59
+ timeout = 90
82
+ * the R-profile FPGA images don't have that abstraction layer.
60
+
83
+ *
61
+ def test_arm_canona1100(self):
84
+ * We model the following FPGA images here:
62
+ """
85
+ * "mps3-an536" -- dual Cortex-R52 as documented in Arm Application Note AN536
63
+ :avocado: tags=arch:arm
86
+ *
64
+ :avocado: tags=machine:canon-a1100
87
+ * Application Note AN536:
65
+ :avocado: tags=device:pflash_cfi02
88
+ * https://developer.arm.com/documentation/dai0536/latest/
66
+ """
89
+ */
67
+ tar_url = ('https://www.qemu-advent-calendar.org'
90
+
68
+ '/2018/download/day18.tar.xz')
91
+#include "qemu/osdep.h"
69
+ tar_hash = '068b5fc4242b29381acee94713509f8a876e9db6'
92
+#include "qemu/units.h"
70
+ file_path = self.fetch_asset(tar_url, asset_hash=tar_hash)
93
+#include "qapi/error.h"
71
+ archive.extract(file_path, self.workdir)
94
+#include "exec/address-spaces.h"
72
+ self.vm.set_console()
95
+#include "cpu.h"
73
+ self.vm.add_args('-bios',
96
+#include "hw/boards.h"
74
+ self.workdir + '/day18/barebox.canon-a1100.bin')
97
+#include "hw/arm/boot.h"
75
+ self.vm.launch()
98
+
76
+ wait_for_console_pattern(self, 'running /env/bin/init')
99
+/* Define the layout of RAM and ROM in a board */
100
+typedef struct RAMInfo {
101
+ const char *name;
102
+ hwaddr base;
103
+ hwaddr size;
104
+ int mrindex; /* index into rams[]; -1 for the system RAM block */
105
+ int flags;
106
+} RAMInfo;
107
+
108
+/*
109
+ * The MPS3 DDR is 3GiB, but on a 32-bit host QEMU doesn't permit
110
+ * emulation of that much guest RAM, so artificially make it smaller.
111
+ */
112
+#if HOST_LONG_BITS == 32
113
+#define MPS3_DDR_SIZE (1 * GiB)
114
+#else
115
+#define MPS3_DDR_SIZE (3 * GiB)
116
+#endif
117
+
118
+/*
119
+ * Flag values:
120
+ * IS_MAIN: this is the main machine RAM
121
+ * IS_ROM: this area is read-only
122
+ */
123
+#define IS_MAIN 1
124
+#define IS_ROM 2
125
+
126
+#define MPS3R_RAM_MAX 9
127
+
128
+typedef enum MPS3RFPGAType {
129
+ FPGA_AN536,
130
+} MPS3RFPGAType;
131
+
132
+struct MPS3RMachineClass {
133
+ MachineClass parent;
134
+ MPS3RFPGAType fpga_type;
135
+ const RAMInfo *raminfo;
136
+};
137
+
138
+struct MPS3RMachineState {
139
+ MachineState parent;
140
+ MemoryRegion ram[MPS3R_RAM_MAX];
141
+};
142
+
143
+#define TYPE_MPS3R_MACHINE "mps3r"
144
+#define TYPE_MPS3R_AN536_MACHINE MACHINE_TYPE_NAME("mps3-an536")
145
+
146
+OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
147
+
148
+static const RAMInfo an536_raminfo[] = {
149
+ {
150
+ .name = "ATCM",
151
+ .base = 0x00000000,
152
+ .size = 0x00008000,
153
+ .mrindex = 0,
154
+ }, {
155
+ /* We model the QSPI flash as simple ROM for now */
156
+ .name = "QSPI",
157
+ .base = 0x08000000,
158
+ .size = 0x00800000,
159
+ .flags = IS_ROM,
160
+ .mrindex = 1,
161
+ }, {
162
+ .name = "BRAM",
163
+ .base = 0x10000000,
164
+ .size = 0x00080000,
165
+ .mrindex = 2,
166
+ }, {
167
+ .name = "DDR",
168
+ .base = 0x20000000,
169
+ .size = MPS3_DDR_SIZE,
170
+ .mrindex = -1,
171
+ }, {
172
+ .name = "ATCM0",
173
+ .base = 0xee000000,
174
+ .size = 0x00008000,
175
+ .mrindex = 3,
176
+ }, {
177
+ .name = "BTCM0",
178
+ .base = 0xee100000,
179
+ .size = 0x00008000,
180
+ .mrindex = 4,
181
+ }, {
182
+ .name = "CTCM0",
183
+ .base = 0xee200000,
184
+ .size = 0x00008000,
185
+ .mrindex = 5,
186
+ }, {
187
+ .name = "ATCM1",
188
+ .base = 0xee400000,
189
+ .size = 0x00008000,
190
+ .mrindex = 6,
191
+ }, {
192
+ .name = "BTCM1",
193
+ .base = 0xee500000,
194
+ .size = 0x00008000,
195
+ .mrindex = 7,
196
+ }, {
197
+ .name = "CTCM1",
198
+ .base = 0xee600000,
199
+ .size = 0x00008000,
200
+ .mrindex = 8,
201
+ }, {
202
+ .name = NULL,
203
+ }
204
+};
205
+
206
+static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
207
+ const RAMInfo *raminfo)
208
+{
209
+ /* Return an initialized MemoryRegion for the RAMInfo. */
210
+ MemoryRegion *ram;
211
+
212
+ if (raminfo->mrindex < 0) {
213
+ /* Means this RAMInfo is for QEMU's "system memory" */
214
+ MachineState *machine = MACHINE(mms);
215
+ assert(!(raminfo->flags & IS_ROM));
216
+ return machine->ram;
217
+ }
218
+
219
+ assert(raminfo->mrindex < MPS3R_RAM_MAX);
220
+ ram = &mms->ram[raminfo->mrindex];
221
+
222
+ memory_region_init_ram(ram, NULL, raminfo->name,
223
+ raminfo->size, &error_fatal);
224
+ if (raminfo->flags & IS_ROM) {
225
+ memory_region_set_readonly(ram, true);
226
+ }
227
+ return ram;
228
+}
229
+
230
+static void mps3r_common_init(MachineState *machine)
231
+{
232
+ MPS3RMachineState *mms = MPS3R_MACHINE(machine);
233
+ MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
234
+ MemoryRegion *sysmem = get_system_memory();
235
+
236
+ for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
237
+ MemoryRegion *mr = mr_for_raminfo(mms, ri);
238
+ memory_region_add_subregion(sysmem, ri->base, mr);
239
+ }
240
+}
241
+
242
+static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
243
+{
244
+ /*
245
+ * Set mc->default_ram_size and default_ram_id from the
246
+ * information in mmc->raminfo.
247
+ */
248
+ MachineClass *mc = MACHINE_CLASS(mmc);
249
+ const RAMInfo *p;
250
+
251
+ for (p = mmc->raminfo; p->name; p++) {
252
+ if (p->mrindex < 0) {
253
+ /* Found the entry for "system memory" */
254
+ mc->default_ram_size = p->size;
255
+ mc->default_ram_id = p->name;
256
+ return;
257
+ }
258
+ }
259
+ g_assert_not_reached();
260
+}
261
+
262
+static void mps3r_class_init(ObjectClass *oc, void *data)
263
+{
264
+ MachineClass *mc = MACHINE_CLASS(oc);
265
+
266
+ mc->init = mps3r_common_init;
267
+}
268
+
269
+static void mps3r_an536_class_init(ObjectClass *oc, void *data)
270
+{
271
+ MachineClass *mc = MACHINE_CLASS(oc);
272
+ MPS3RMachineClass *mmc = MPS3R_MACHINE_CLASS(oc);
273
+ static const char * const valid_cpu_types[] = {
274
+ ARM_CPU_TYPE_NAME("cortex-r52"),
275
+ NULL
276
+ };
277
+
278
+ mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
279
+ mc->default_cpus = 2;
280
+ mc->min_cpus = mc->default_cpus;
281
+ mc->max_cpus = mc->default_cpus;
282
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
283
+ mc->valid_cpu_types = valid_cpu_types;
284
+ mmc->raminfo = an536_raminfo;
285
+ mps3r_set_default_ram_info(mmc);
286
+}
287
+
288
+static const TypeInfo mps3r_machine_types[] = {
289
+ {
290
+ .name = TYPE_MPS3R_MACHINE,
291
+ .parent = TYPE_MACHINE,
292
+ .abstract = true,
293
+ .instance_size = sizeof(MPS3RMachineState),
294
+ .class_size = sizeof(MPS3RMachineClass),
295
+ .class_init = mps3r_class_init,
296
+ }, {
297
+ .name = TYPE_MPS3R_AN536_MACHINE,
298
+ .parent = TYPE_MPS3R_MACHINE,
299
+ .class_init = mps3r_an536_class_init,
300
+ },
301
+};
302
+
303
+DEFINE_TYPES(mps3r_machine_types);
304
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
305
index XXXXXXX..XXXXXXX 100644
306
--- a/hw/arm/Kconfig
307
+++ b/hw/arm/Kconfig
308
@@ -XXX,XX +XXX,XX @@ config MAINSTONE
309
select PFLASH_CFI01
310
select SMC91C111
311
312
+config MPS3R
313
+ bool
314
+ default y
315
+ depends on TCG && ARM
316
+
317
config MUSCA
318
bool
319
default y
320
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
321
index XXXXXXX..XXXXXXX 100644
322
--- a/hw/arm/meson.build
323
+++ b/hw/arm/meson.build
324
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
325
arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
326
arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c'))
327
arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
328
+arm_ss.add(when: 'CONFIG_MPS3R', if_true: files('mps3r.c'))
329
arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
330
arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
331
arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
77
--
332
--
78
2.20.1
333
2.34.1
79
334
80
335
diff view generated by jsdifflib
[PULL 13/29] hw/watchdog: Implement full i.MX watchdog support
[PULL 31/35] hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
1
From: Guenter Roeck <linux@roeck-us.net>
1
Create the CPUs, the GIC, and the per-CPU RAM block for
2
the mps3-an536 board.
2
3
3
Implement full support for the watchdog in i.MX systems.
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Pretimeout support is optional because the watchdog hardware
5
Message-id: 20240206132931.38376-10-peter.maydell@linaro.org
5
on i.MX31 does not support pretimeouts.
6
---
7
hw/arm/mps3r.c | 180 ++++++++++++++++++++++++++++++++++++++++++++++++-
8
1 file changed, 177 insertions(+), 3 deletions(-)
6
9
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
10
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
8
Message-id: 20200517162135.110364-3-linux@roeck-us.net
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/watchdog/wdt_imx2.h | 61 ++++++++-
13
hw/watchdog/wdt_imx2.c | 239 +++++++++++++++++++++++++++++++--
14
2 files changed, 285 insertions(+), 15 deletions(-)
15
16
diff --git a/include/hw/watchdog/wdt_imx2.h b/include/hw/watchdog/wdt_imx2.h
17
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/watchdog/wdt_imx2.h
12
--- a/hw/arm/mps3r.c
19
+++ b/include/hw/watchdog/wdt_imx2.h
13
+++ b/hw/arm/mps3r.c
20
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@
21
#ifndef IMX2_WDT_H
15
#include "qemu/osdep.h"
22
#define IMX2_WDT_H
16
#include "qemu/units.h"
23
17
#include "qapi/error.h"
24
+#include "qemu/bitops.h"
18
+#include "qapi/qmp/qlist.h"
25
#include "hw/sysbus.h"
19
#include "exec/address-spaces.h"
26
+#include "hw/irq.h"
20
#include "cpu.h"
27
+#include "hw/ptimer.h"
21
#include "hw/boards.h"
28
22
+#include "hw/qdev-properties.h"
29
#define TYPE_IMX2_WDT "imx2.wdt"
23
#include "hw/arm/boot.h"
30
#define IMX2_WDT(obj) OBJECT_CHECK(IMX2WdtState, (obj), TYPE_IMX2_WDT)
24
+#include "hw/arm/bsa.h"
31
25
+#include "hw/intc/arm_gicv3.h"
32
enum IMX2WdtRegisters {
26
33
- IMX2_WDT_WCR = 0x0000,
27
/* Define the layout of RAM and ROM in a board */
34
- IMX2_WDT_REG_NUM = 0x0008 / sizeof(uint16_t) + 1,
28
typedef struct RAMInfo {
35
+ IMX2_WDT_WCR = 0x0000, /* Control Register */
29
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
36
+ IMX2_WDT_WSR = 0x0002, /* Service Register */
30
#define IS_ROM 2
37
+ IMX2_WDT_WRSR = 0x0004, /* Reset Status Register */
31
38
+ IMX2_WDT_WICR = 0x0006, /* Interrupt Control Register */
32
#define MPS3R_RAM_MAX 9
39
+ IMX2_WDT_WMCR = 0x0008, /* Misc Register */
33
+#define MPS3R_CPU_MAX 2
34
+
35
+#define PERIPHBASE 0xf0000000
36
+#define NUM_SPIS 96
37
38
typedef enum MPS3RFPGAType {
39
FPGA_AN536,
40
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineClass {
41
MachineClass parent;
42
MPS3RFPGAType fpga_type;
43
const RAMInfo *raminfo;
44
+ hwaddr loader_start;
40
};
45
};
41
46
42
+#define IMX2_WDT_MMIO_SIZE 0x000a
47
struct MPS3RMachineState {
43
+
48
MachineState parent;
44
+/* Control Register definitions */
49
+ struct arm_boot_info bootinfo;
45
+#define IMX2_WDT_WCR_WT (0xFF << 8) /* Watchdog Timeout Field */
50
MemoryRegion ram[MPS3R_RAM_MAX];
46
+#define IMX2_WDT_WCR_WDW BIT(7) /* WDOG Disable for Wait */
51
+ Object *cpu[MPS3R_CPU_MAX];
47
+#define IMX2_WDT_WCR_WDA BIT(5) /* WDOG Assertion */
52
+ MemoryRegion cpu_sysmem[MPS3R_CPU_MAX];
48
+#define IMX2_WDT_WCR_SRS BIT(4) /* Software Reset Signal */
53
+ MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
49
+#define IMX2_WDT_WCR_WDT BIT(3) /* WDOG Timeout Assertion */
54
+ MemoryRegion cpu_ram[MPS3R_CPU_MAX];
50
+#define IMX2_WDT_WCR_WDE BIT(2) /* Watchdog Enable */
55
+ GICv3State gic;
51
+#define IMX2_WDT_WCR_WDBG BIT(1) /* Watchdog Debug Enable */
56
};
52
+#define IMX2_WDT_WCR_WDZST BIT(0) /* Watchdog Timer Suspend */
57
53
+
58
#define TYPE_MPS3R_MACHINE "mps3r"
54
+#define IMX2_WDT_WCR_LOCK_MASK (IMX2_WDT_WCR_WDZST | IMX2_WDT_WCR_WDBG \
59
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
55
+ | IMX2_WDT_WCR_WDW)
60
return ram;
56
+
61
}
57
+/* Service Register definitions */
62
58
+#define IMX2_WDT_SEQ1 0x5555 /* service sequence 1 */
63
+/*
59
+#define IMX2_WDT_SEQ2 0xAAAA /* service sequence 2 */
64
+ * There is no defined secondary boot protocol for Linux for the AN536,
60
+
65
+ * because real hardware has a restriction that atomic operations between
61
+/* Reset Status Register definitions */
66
+ * the two CPUs do not function correctly, and so true SMP is not
62
+#define IMX2_WDT_WRSR_TOUT BIT(1) /* Reset due to Timeout */
67
+ * possible. Therefore for cases where the user is directly booting
63
+#define IMX2_WDT_WRSR_SFTW BIT(0) /* Reset due to software reset */
68
+ * a kernel, we treat the system as essentially uniprocessor, and
64
+
69
+ * put the secondary CPU into power-off state (as if the user on the
65
+/* Interrupt Control Register definitions */
70
+ * real hardware had configured the secondary to be halted via the
66
+#define IMX2_WDT_WICR_WIE BIT(15) /* Interrupt Enable */
71
+ * SCC config registers).
67
+#define IMX2_WDT_WICR_WTIS BIT(14) /* Interrupt Status */
72
+ *
68
+#define IMX2_WDT_WICR_WICT 0xff /* Interrupt Timeout */
73
+ * Note that the default secondary boot code would not work here anyway
69
+#define IMX2_WDT_WICR_WICT_DEF 0x04 /* Default interrupt timeout (2s) */
74
+ * as it assumes a GICv2, and we have a GICv3.
70
+
75
+ */
71
+#define IMX2_WDT_WICR_LOCK_MASK (IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT)
76
+static void mps3r_write_secondary_boot(ARMCPU *cpu,
72
+
77
+ const struct arm_boot_info *info)
73
+/* Misc Control Register definitions */
74
+#define IMX2_WDT_WMCR_PDE BIT(0) /* Power-Down Enable */
75
76
typedef struct IMX2WdtState {
77
/* <private> */
78
SysBusDevice parent_obj;
79
80
+ /*< public >*/
81
MemoryRegion mmio;
82
+ qemu_irq irq;
83
+
84
+ struct ptimer_state *timer;
85
+ struct ptimer_state *itimer;
86
+
87
+ bool pretimeout_support;
88
+ bool wicr_locked;
89
+
90
+ uint16_t wcr;
91
+ uint16_t wsr;
92
+ uint16_t wrsr;
93
+ uint16_t wicr;
94
+ uint16_t wmcr;
95
+
96
+ bool wcr_locked; /* affects WDZST, WDBG, and WDW */
97
+ bool wcr_wde_locked; /* affects WDE */
98
+ bool wcr_wdt_locked; /* affects WDT (never cleared) */
99
} IMX2WdtState;
100
101
#endif /* IMX2_WDT_H */
102
diff --git a/hw/watchdog/wdt_imx2.c b/hw/watchdog/wdt_imx2.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/hw/watchdog/wdt_imx2.c
105
+++ b/hw/watchdog/wdt_imx2.c
106
@@ -XXX,XX +XXX,XX @@
107
#include "qemu/bitops.h"
108
#include "qemu/module.h"
109
#include "sysemu/watchdog.h"
110
+#include "migration/vmstate.h"
111
+#include "hw/qdev-properties.h"
112
113
#include "hw/watchdog/wdt_imx2.h"
114
115
-#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
116
-#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
117
-
118
-static uint64_t imx2_wdt_read(void *opaque, hwaddr addr,
119
- unsigned int size)
120
+static void imx2_wdt_interrupt(void *opaque)
121
{
122
+ IMX2WdtState *s = IMX2_WDT(opaque);
123
+
124
+ s->wicr |= IMX2_WDT_WICR_WTIS;
125
+ qemu_set_irq(s->irq, 1);
126
+}
127
+
128
+static void imx2_wdt_expired(void *opaque)
129
+{
78
+{
130
+ IMX2WdtState *s = IMX2_WDT(opaque);
79
+ /*
131
+
80
+ * Power the secondary CPU off. This means we don't need to write any
132
+ s->wrsr = IMX2_WDT_WRSR_TOUT;
81
+ * boot code into guest memory. Note that the 'cpu' argument to this
133
+
82
+ * function is the primary CPU we passed to arm_load_kernel(), not
134
+ /* Perform watchdog action if watchdog is enabled */
83
+ * the secondary. Loop around all the other CPUs, as the boot.c
135
+ if (s->wcr & IMX2_WDT_WCR_WDE) {
84
+ * code does for the "disable secondaries if PSCI is enabled" case.
136
+ s->wrsr = IMX2_WDT_WRSR_TOUT;
85
+ */
137
+ watchdog_perform_action();
86
+ for (CPUState *cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
87
+ if (cs != first_cpu) {
88
+ object_property_set_bool(OBJECT(cs), "start-powered-off", true,
89
+ &error_abort);
90
+ }
138
+ }
91
+ }
139
+}
92
+}
140
+
93
+
141
+static void imx2_wdt_reset(DeviceState *dev)
94
+static void mps3r_secondary_cpu_reset(ARMCPU *cpu,
95
+ const struct arm_boot_info *info)
142
+{
96
+{
143
+ IMX2WdtState *s = IMX2_WDT(dev);
97
+ /* We don't need to do anything here because the CPU will be off */
144
+
145
+ ptimer_transaction_begin(s->timer);
146
+ ptimer_stop(s->timer);
147
+ ptimer_transaction_commit(s->timer);
148
+
149
+ if (s->pretimeout_support) {
150
+ ptimer_transaction_begin(s->itimer);
151
+ ptimer_stop(s->itimer);
152
+ ptimer_transaction_commit(s->itimer);
153
+ }
154
+
155
+ s->wicr_locked = false;
156
+ s->wcr_locked = false;
157
+ s->wcr_wde_locked = false;
158
+
159
+ s->wcr = IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS;
160
+ s->wsr = 0;
161
+ s->wrsr &= ~(IMX2_WDT_WRSR_TOUT | IMX2_WDT_WRSR_SFTW);
162
+ s->wicr = IMX2_WDT_WICR_WICT_DEF;
163
+ s->wmcr = IMX2_WDT_WMCR_PDE;
164
+}
98
+}
165
+
99
+
166
+static uint64_t imx2_wdt_read(void *opaque, hwaddr addr, unsigned int size)
100
+static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
167
+{
101
+{
168
+ IMX2WdtState *s = IMX2_WDT(opaque);
102
+ MachineState *machine = MACHINE(mms);
169
+
103
+ DeviceState *gicdev;
170
+ switch (addr) {
104
+ QList *redist_region_count;
171
+ case IMX2_WDT_WCR:
105
+
172
+ return s->wcr;
106
+ object_initialize_child(OBJECT(mms), "gic", &mms->gic, TYPE_ARM_GICV3);
173
+ case IMX2_WDT_WSR:
107
+ gicdev = DEVICE(&mms->gic);
174
+ return s->wsr;
108
+ qdev_prop_set_uint32(gicdev, "num-cpu", machine->smp.cpus);
175
+ case IMX2_WDT_WRSR:
109
+ qdev_prop_set_uint32(gicdev, "num-irq", NUM_SPIS + GIC_INTERNAL);
176
+ return s->wrsr;
110
+ redist_region_count = qlist_new();
177
+ case IMX2_WDT_WICR:
111
+ qlist_append_int(redist_region_count, machine->smp.cpus);
178
+ return s->wicr;
112
+ qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
179
+ case IMX2_WDT_WMCR:
113
+ object_property_set_link(OBJECT(&mms->gic), "sysmem",
180
+ return s->wmcr;
114
+ OBJECT(sysmem), &error_fatal);
181
+ }
115
+ sysbus_realize(SYS_BUS_DEVICE(&mms->gic), &error_fatal);
182
return 0;
116
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 0, PERIPHBASE);
183
}
117
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 1, PERIPHBASE + 0x100000);
184
118
+ /*
185
+static void imx_wdt2_update_itimer(IMX2WdtState *s, bool start)
119
+ * Wire the outputs from each CPU's generic timer and the GICv3
186
+{
120
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
187
+ bool running = (s->wcr & IMX2_WDT_WCR_WDE) && (s->wcr & IMX2_WDT_WCR_WT);
121
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
188
+ bool enabled = s->wicr & IMX2_WDT_WICR_WIE;
122
+ */
189
+
123
+ for (int i = 0; i < machine->smp.cpus; i++) {
190
+ ptimer_transaction_begin(s->itimer);
124
+ DeviceState *cpudev = DEVICE(mms->cpu[i]);
191
+ if (start || !enabled) {
125
+ SysBusDevice *gicsbd = SYS_BUS_DEVICE(&mms->gic);
192
+ ptimer_stop(s->itimer);
126
+ int intidbase = NUM_SPIS + i * GIC_INTERNAL;
193
+ }
127
+ int irq;
194
+ if (running && enabled) {
195
+ int count = ptimer_get_count(s->timer);
196
+ int pretimeout = s->wicr & IMX2_WDT_WICR_WICT;
197
+
198
+ /*
128
+ /*
199
+ * Only (re-)start pretimeout timer if its counter value is larger
129
+ * Mapping from the output timer irq lines from the CPU to the
200
+ * than 0. Otherwise it will fire right away and we'll get an
130
+ * GIC PPI inputs used for this board. This isn't a BSA board,
201
+ * interrupt loop.
131
+ * but it uses the standard convention for the PPI numbers.
202
+ */
132
+ */
203
+ if (count > pretimeout) {
133
+ const int timer_irq[] = {
204
+ ptimer_set_count(s->itimer, count - pretimeout);
134
+ [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
205
+ if (start) {
135
+ [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
206
+ ptimer_run(s->itimer, 1);
136
+ [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
207
+ }
137
+ };
138
+
139
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
140
+ qdev_connect_gpio_out(cpudev, irq,
141
+ qdev_get_gpio_in(gicdev,
142
+ intidbase + timer_irq[irq]));
208
+ }
143
+ }
209
+ }
144
+
210
+ ptimer_transaction_commit(s->itimer);
145
+ qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
211
+}
146
+ qdev_get_gpio_in(gicdev,
212
+
147
+ intidbase + ARCH_GIC_MAINT_IRQ));
213
+static void imx_wdt2_update_timer(IMX2WdtState *s, bool start)
148
+
214
+{
149
+ qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
215
+ ptimer_transaction_begin(s->timer);
150
+ qdev_get_gpio_in(gicdev,
216
+ if (start) {
151
+ intidbase + VIRTUAL_PMU_IRQ));
217
+ ptimer_stop(s->timer);
152
+
218
+ }
153
+ sysbus_connect_irq(gicsbd, i,
219
+ if ((s->wcr & IMX2_WDT_WCR_WDE) && (s->wcr & IMX2_WDT_WCR_WT)) {
154
+ qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
220
+ int count = (s->wcr & IMX2_WDT_WCR_WT) >> 8;
155
+ sysbus_connect_irq(gicsbd, i + machine->smp.cpus,
221
+
156
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
222
+ /* A value of 0 reflects one period (0.5s). */
157
+ sysbus_connect_irq(gicsbd, i + 2 * machine->smp.cpus,
223
+ ptimer_set_count(s->timer, count + 1);
158
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
224
+ if (start) {
159
+ sysbus_connect_irq(gicsbd, i + 3 * machine->smp.cpus,
225
+ ptimer_run(s->timer, 1);
160
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
226
+ }
227
+ }
228
+ ptimer_transaction_commit(s->timer);
229
+ if (s->pretimeout_support) {
230
+ imx_wdt2_update_itimer(s, start);
231
+ }
161
+ }
232
+}
162
+}
233
+
163
+
234
static void imx2_wdt_write(void *opaque, hwaddr addr,
164
static void mps3r_common_init(MachineState *machine)
235
uint64_t value, unsigned int size)
236
{
165
{
237
- if (addr == IMX2_WDT_WCR &&
166
MPS3RMachineState *mms = MPS3R_MACHINE(machine);
238
- (~value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS))) {
167
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
239
- watchdog_perform_action();
168
MemoryRegion *mr = mr_for_raminfo(mms, ri);
240
+ IMX2WdtState *s = IMX2_WDT(opaque);
169
memory_region_add_subregion(sysmem, ri->base, mr);
241
+
242
+ switch (addr) {
243
+ case IMX2_WDT_WCR:
244
+ if (s->wcr_locked) {
245
+ value &= ~IMX2_WDT_WCR_LOCK_MASK;
246
+ value |= (s->wicr & IMX2_WDT_WCR_LOCK_MASK);
247
+ }
248
+ s->wcr_locked = true;
249
+ if (s->wcr_wde_locked) {
250
+ value &= ~IMX2_WDT_WCR_WDE;
251
+ value |= (s->wicr & ~IMX2_WDT_WCR_WDE);
252
+ } else if (value & IMX2_WDT_WCR_WDE) {
253
+ s->wcr_wde_locked = true;
254
+ }
255
+ if (s->wcr_wdt_locked) {
256
+ value &= ~IMX2_WDT_WCR_WDT;
257
+ value |= (s->wicr & ~IMX2_WDT_WCR_WDT);
258
+ } else if (value & IMX2_WDT_WCR_WDT) {
259
+ s->wcr_wdt_locked = true;
260
+ }
261
+
262
+ s->wcr = value;
263
+ if (!(value & IMX2_WDT_WCR_SRS)) {
264
+ s->wrsr = IMX2_WDT_WRSR_SFTW;
265
+ }
266
+ if (!(value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS)) ||
267
+ (!(value & IMX2_WDT_WCR_WT) && (value & IMX2_WDT_WCR_WDE))) {
268
+ watchdog_perform_action();
269
+ }
270
+ s->wcr |= IMX2_WDT_WCR_SRS;
271
+ imx_wdt2_update_timer(s, true);
272
+ break;
273
+ case IMX2_WDT_WSR:
274
+ if (s->wsr == IMX2_WDT_SEQ1 && value == IMX2_WDT_SEQ2) {
275
+ imx_wdt2_update_timer(s, false);
276
+ }
277
+ s->wsr = value;
278
+ break;
279
+ case IMX2_WDT_WRSR:
280
+ break;
281
+ case IMX2_WDT_WICR:
282
+ if (!s->pretimeout_support) {
283
+ return;
284
+ }
285
+ value &= IMX2_WDT_WICR_LOCK_MASK | IMX2_WDT_WICR_WTIS;
286
+ if (s->wicr_locked) {
287
+ value &= IMX2_WDT_WICR_WTIS;
288
+ value |= (s->wicr & IMX2_WDT_WICR_LOCK_MASK);
289
+ }
290
+ s->wicr = value | (s->wicr & IMX2_WDT_WICR_WTIS);
291
+ if (value & IMX2_WDT_WICR_WTIS) {
292
+ s->wicr &= ~IMX2_WDT_WICR_WTIS;
293
+ qemu_set_irq(s->irq, 0);
294
+ }
295
+ imx_wdt2_update_itimer(s, true);
296
+ s->wicr_locked = true;
297
+ break;
298
+ case IMX2_WDT_WMCR:
299
+ s->wmcr = value & IMX2_WDT_WMCR_PDE;
300
+ break;
301
}
170
}
171
+
172
+ assert(machine->smp.cpus <= MPS3R_CPU_MAX);
173
+ for (int i = 0; i < machine->smp.cpus; i++) {
174
+ g_autofree char *sysmem_name = g_strdup_printf("cpu-%d-memory", i);
175
+ g_autofree char *ramname = g_strdup_printf("cpu-%d-memory", i);
176
+ g_autofree char *alias_name = g_strdup_printf("sysmem-alias-%d", i);
177
+
178
+ /*
179
+ * Each CPU has some private RAM/peripherals, so create the container
180
+ * which will house those, with the whole-machine system memory being
181
+ * used where there's no CPU-specific device. Note that we need the
182
+ * sysmem_alias aliases because we can't put one MR (the original
183
+ * 'sysmem') into more than one other MR.
184
+ */
185
+ memory_region_init(&mms->cpu_sysmem[i], OBJECT(machine),
186
+ sysmem_name, UINT64_MAX);
187
+ memory_region_init_alias(&mms->sysmem_alias[i], OBJECT(machine),
188
+ alias_name, sysmem, 0, UINT64_MAX);
189
+ memory_region_add_subregion_overlap(&mms->cpu_sysmem[i], 0,
190
+ &mms->sysmem_alias[i], -1);
191
+
192
+ mms->cpu[i] = object_new(machine->cpu_type);
193
+ object_property_set_link(mms->cpu[i], "memory",
194
+ OBJECT(&mms->cpu_sysmem[i]), &error_abort);
195
+ object_property_set_int(mms->cpu[i], "reset-cbar",
196
+ PERIPHBASE, &error_abort);
197
+ qdev_realize(DEVICE(mms->cpu[i]), NULL, &error_fatal);
198
+ object_unref(mms->cpu[i]);
199
+
200
+ /* Per-CPU RAM */
201
+ memory_region_init_ram(&mms->cpu_ram[i], NULL, ramname,
202
+ 0x1000, &error_fatal);
203
+ memory_region_add_subregion(&mms->cpu_sysmem[i], 0xe7c01000,
204
+ &mms->cpu_ram[i]);
205
+ }
206
+
207
+ create_gic(mms, sysmem);
208
+
209
+ mms->bootinfo.ram_size = machine->ram_size;
210
+ mms->bootinfo.board_id = -1;
211
+ mms->bootinfo.loader_start = mmc->loader_start;
212
+ mms->bootinfo.write_secondary_boot = mps3r_write_secondary_boot;
213
+ mms->bootinfo.secondary_cpu_reset_hook = mps3r_secondary_cpu_reset;
214
+ arm_load_kernel(ARM_CPU(mms->cpu[0]), machine, &mms->bootinfo);
302
}
215
}
303
216
304
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps imx2_wdt_ops = {
217
static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
305
* real device but in practice there is no reason for a guest
218
@@ -XXX,XX +XXX,XX @@ static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
306
* to access this device unaligned.
219
/* Found the entry for "system memory" */
307
*/
220
mc->default_ram_size = p->size;
308
- .min_access_size = 4,
221
mc->default_ram_id = p->name;
309
- .max_access_size = 4,
222
+ mmc->loader_start = p->base;
310
+ .min_access_size = 2,
223
return;
311
+ .max_access_size = 2,
224
}
312
.unaligned = false,
225
}
313
},
226
@@ -XXX,XX +XXX,XX @@ static void mps3r_an536_class_init(ObjectClass *oc, void *data)
314
};
227
};
315
228
316
+static const VMStateDescription vmstate_imx2_wdt = {
229
mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
317
+ .name = "imx2.wdt",
230
- mc->default_cpus = 2;
318
+ .fields = (VMStateField[]) {
231
- mc->min_cpus = mc->default_cpus;
319
+ VMSTATE_PTIMER(timer, IMX2WdtState),
232
- mc->max_cpus = mc->default_cpus;
320
+ VMSTATE_PTIMER(itimer, IMX2WdtState),
233
+ /*
321
+ VMSTATE_BOOL(wicr_locked, IMX2WdtState),
234
+ * In the real FPGA image there are always two cores, but the standard
322
+ VMSTATE_BOOL(wcr_locked, IMX2WdtState),
235
+ * initial setting for the SCC SYSCON 0x000 register is 0x21, meaning
323
+ VMSTATE_BOOL(wcr_wde_locked, IMX2WdtState),
236
+ * that the second core is held in reset and halted. Many images built for
324
+ VMSTATE_BOOL(wcr_wdt_locked, IMX2WdtState),
237
+ * the board do not expect the second core to run at startup (especially
325
+ VMSTATE_UINT16(wcr, IMX2WdtState),
238
+ * since on the real FPGA image it is not possible to use LDREX/STREX
326
+ VMSTATE_UINT16(wsr, IMX2WdtState),
239
+ * in RAM between the two cores, so a true SMP setup isn't supported).
327
+ VMSTATE_UINT16(wrsr, IMX2WdtState),
240
+ *
328
+ VMSTATE_UINT16(wmcr, IMX2WdtState),
241
+ * As QEMU's equivalent of this, we support both -smp 1 and -smp 2,
329
+ VMSTATE_UINT16(wicr, IMX2WdtState),
242
+ * with the default being -smp 1. This seems a more intuitive UI for
330
+ VMSTATE_END_OF_LIST()
243
+ * QEMU users than, for instance, having a machine property to allow
331
+ }
244
+ * the user to set the initial value of the SYSCON 0x000 register.
332
+};
245
+ */
333
+
246
+ mc->default_cpus = 1;
334
static void imx2_wdt_realize(DeviceState *dev, Error **errp)
247
+ mc->min_cpus = 1;
335
{
248
+ mc->max_cpus = 2;
336
IMX2WdtState *s = IMX2_WDT(dev);
249
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
337
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
250
mc->valid_cpu_types = valid_cpu_types;
338
251
mmc->raminfo = an536_raminfo;
339
memory_region_init_io(&s->mmio, OBJECT(dev),
340
&imx2_wdt_ops, s,
341
- TYPE_IMX2_WDT".mmio",
342
- IMX2_WDT_REG_NUM * sizeof(uint16_t));
343
- sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
344
+ TYPE_IMX2_WDT,
345
+ IMX2_WDT_MMIO_SIZE);
346
+ sysbus_init_mmio(sbd, &s->mmio);
347
+ sysbus_init_irq(sbd, &s->irq);
348
+
349
+ s->timer = ptimer_init(imx2_wdt_expired, s,
350
+ PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
351
+ PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
352
+ PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
353
+ ptimer_transaction_begin(s->timer);
354
+ ptimer_set_freq(s->timer, 2);
355
+ ptimer_set_limit(s->timer, 0xff, 1);
356
+ ptimer_transaction_commit(s->timer);
357
+ if (s->pretimeout_support) {
358
+ s->itimer = ptimer_init(imx2_wdt_interrupt, s,
359
+ PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
360
+ PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
361
+ PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
362
+ ptimer_transaction_begin(s->itimer);
363
+ ptimer_set_freq(s->itimer, 2);
364
+ ptimer_set_limit(s->itimer, 0xff, 1);
365
+ ptimer_transaction_commit(s->itimer);
366
+ }
367
}
368
369
+static Property imx2_wdt_properties[] = {
370
+ DEFINE_PROP_BOOL("pretimeout-support", IMX2WdtState, pretimeout_support,
371
+ false),
372
+};
373
+
374
static void imx2_wdt_class_init(ObjectClass *klass, void *data)
375
{
376
DeviceClass *dc = DEVICE_CLASS(klass);
377
378
+ device_class_set_props(dc, imx2_wdt_properties);
379
dc->realize = imx2_wdt_realize;
380
+ dc->reset = imx2_wdt_reset;
381
+ dc->vmsd = &vmstate_imx2_wdt;
382
+ dc->desc = "i.MX watchdog timer";
383
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
384
}
385
386
--
252
--
387
2.20.1
253
2.34.1
388
389
diff view generated by jsdifflib
[PULL 23/29] hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask()
[PULL 32/35] hw/arm/mps3r: Add UARTs
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
This board has a lot of UARTs: there is one UART per CPU in the
2
per-CPU peripheral part of the address map, whose interrupts are
3
connected as per-CPU interrupt lines. Then there are 4 UARTs in the
4
normal part of the peripheral space, whose interrupts are shared
5
peripheral interrupts.
2
6
3
hw_error() calls exit(). This a bit overkill when we can log
7
Connect and wire them all up; this involves some OR gates where
4
the accesses as unimplemented or guest error.
8
multiple overflow interrupts are wired into one GIC input.
5
9
6
When fuzzing the devices, we don't want the whole process to
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
exit. Replace some hw_error() calls by qemu_log_mask().
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Message-id: 20240206132931.38376-11-peter.maydell@linaro.org
13
---
14
hw/arm/mps3r.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++
15
1 file changed, 94 insertions(+)
8
16
9
Per the datasheet "Exynos 4412 RISC Microprocessor Rev 1.00"
17
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
10
Chapter 25 "Multi Core Timer (MCT)" figure 1 and table 4,
11
the default value on the APB bus is 0.
12
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Message-id: 20200518140309.5220-5-f4bug@amsat.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/timer/exynos4210_mct.c | 12 +++++-------
19
1 file changed, 5 insertions(+), 7 deletions(-)
20
21
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
22
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/timer/exynos4210_mct.c
19
--- a/hw/arm/mps3r.c
24
+++ b/hw/timer/exynos4210_mct.c
20
+++ b/hw/arm/mps3r.c
25
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@
26
22
#include "qapi/qmp/qlist.h"
27
#include "qemu/osdep.h"
23
#include "exec/address-spaces.h"
28
#include "qemu/log.h"
24
#include "cpu.h"
29
-#include "hw/hw.h"
25
+#include "sysemu/sysemu.h"
30
#include "hw/sysbus.h"
26
#include "hw/boards.h"
31
#include "migration/vmstate.h"
27
+#include "hw/or-irq.h"
32
#include "qemu/timer.h"
28
#include "hw/qdev-properties.h"
33
@@ -XXX,XX +XXX,XX @@
29
#include "hw/arm/boot.h"
34
#include "hw/ptimer.h"
30
#include "hw/arm/bsa.h"
35
31
+#include "hw/char/cmsdk-apb-uart.h"
36
#include "hw/arm/exynos4210.h"
32
#include "hw/intc/arm_gicv3.h"
37
-#include "hw/hw.h"
33
38
#include "hw/irq.h"
34
/* Define the layout of RAM and ROM in a board */
39
35
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
40
//#define DEBUG_MCT
36
41
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
37
#define MPS3R_RAM_MAX 9
42
int index;
38
#define MPS3R_CPU_MAX 2
43
int shift;
39
+#define MPS3R_UART_MAX 4 /* shared UART count */
44
uint64_t count;
40
45
- uint32_t value;
41
#define PERIPHBASE 0xf0000000
46
+ uint32_t value = 0;
42
#define NUM_SPIS 96
47
int lt_i;
43
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
48
44
MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
49
switch (offset) {
45
MemoryRegion cpu_ram[MPS3R_CPU_MAX];
50
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
46
GICv3State gic;
51
break;
47
+ /* per-CPU UARTs followed by the shared UARTs */
52
48
+ CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
53
default:
49
+ OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
54
- hw_error("exynos4210.mct: bad read offset "
50
+ OrIRQState uart_oflow;
55
- TARGET_FMT_plx "\n", offset);
51
};
56
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
52
57
+ __func__, offset);
53
#define TYPE_MPS3R_MACHINE "mps3r"
58
break;
54
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
59
}
55
60
return value;
56
OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
61
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
57
62
break;
58
+/*
63
59
+ * Main clock frequency CLK in Hz (50MHz). In the image there are also
64
default:
60
+ * ACLK, MCLK, GPUCLK and PERIPHCLK at the same frequency; for our
65
- hw_error("exynos4210.mct: bad write offset "
61
+ * model we just roll them all into one.
66
- TARGET_FMT_plx "\n", offset);
62
+ */
67
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
63
+#define CLK_FRQ 50000000
68
+ __func__, offset);
64
+
69
break;
65
static const RAMInfo an536_raminfo[] = {
66
{
67
.name = "ATCM",
68
@@ -XXX,XX +XXX,XX @@ static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
70
}
69
}
71
}
70
}
71
72
+/*
73
+ * Create UART uartno, and map it into the MemoryRegion mem at address baseaddr.
74
+ * The qemu_irq arguments are where we connect the various IRQs from the UART.
75
+ */
76
+static void create_uart(MPS3RMachineState *mms, int uartno, MemoryRegion *mem,
77
+ hwaddr baseaddr, qemu_irq txirq, qemu_irq rxirq,
78
+ qemu_irq txoverirq, qemu_irq rxoverirq,
79
+ qemu_irq combirq)
80
+{
81
+ g_autofree char *s = g_strdup_printf("uart%d", uartno);
82
+ SysBusDevice *sbd;
83
+
84
+ assert(uartno < ARRAY_SIZE(mms->uart));
85
+ object_initialize_child(OBJECT(mms), s, &mms->uart[uartno],
86
+ TYPE_CMSDK_APB_UART);
87
+ qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ);
88
+ qdev_prop_set_chr(DEVICE(&mms->uart[uartno]), "chardev", serial_hd(uartno));
89
+ sbd = SYS_BUS_DEVICE(&mms->uart[uartno]);
90
+ sysbus_realize(sbd, &error_fatal);
91
+ memory_region_add_subregion(mem, baseaddr,
92
+ sysbus_mmio_get_region(sbd, 0));
93
+ sysbus_connect_irq(sbd, 0, txirq);
94
+ sysbus_connect_irq(sbd, 1, rxirq);
95
+ sysbus_connect_irq(sbd, 2, txoverirq);
96
+ sysbus_connect_irq(sbd, 3, rxoverirq);
97
+ sysbus_connect_irq(sbd, 4, combirq);
98
+}
99
+
100
static void mps3r_common_init(MachineState *machine)
101
{
102
MPS3RMachineState *mms = MPS3R_MACHINE(machine);
103
MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
104
MemoryRegion *sysmem = get_system_memory();
105
+ DeviceState *gicdev;
106
107
for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
108
MemoryRegion *mr = mr_for_raminfo(mms, ri);
109
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
110
}
111
112
create_gic(mms, sysmem);
113
+ gicdev = DEVICE(&mms->gic);
114
+
115
+ /*
116
+ * UARTs 0 and 1 are per-CPU; their interrupts are wired to
117
+ * the relevant CPU's PPI 0..3, aka INTID 16..19
118
+ */
119
+ for (int i = 0; i < machine->smp.cpus; i++) {
120
+ int intidbase = NUM_SPIS + i * GIC_INTERNAL;
121
+ g_autofree char *s = g_strdup_printf("cpu-uart-oflow-orgate%d", i);
122
+ DeviceState *orgate;
123
+
124
+ /* The two overflow IRQs from the UART are ORed together into PPI 3 */
125
+ object_initialize_child(OBJECT(mms), s, &mms->cpu_uart_oflow[i],
126
+ TYPE_OR_IRQ);
127
+ orgate = DEVICE(&mms->cpu_uart_oflow[i]);
128
+ qdev_prop_set_uint32(orgate, "num-lines", 2);
129
+ qdev_realize(orgate, NULL, &error_fatal);
130
+ qdev_connect_gpio_out(orgate, 0,
131
+ qdev_get_gpio_in(gicdev, intidbase + 19));
132
+
133
+ create_uart(mms, i, &mms->cpu_sysmem[i], 0xe7c00000,
134
+ qdev_get_gpio_in(gicdev, intidbase + 17), /* tx */
135
+ qdev_get_gpio_in(gicdev, intidbase + 16), /* rx */
136
+ qdev_get_gpio_in(orgate, 0), /* txover */
137
+ qdev_get_gpio_in(orgate, 1), /* rxover */
138
+ qdev_get_gpio_in(gicdev, intidbase + 18) /* combined */);
139
+ }
140
+ /*
141
+ * UARTs 2 to 5 are whole-system; all overflow IRQs are ORed
142
+ * together into IRQ 17
143
+ */
144
+ object_initialize_child(OBJECT(mms), "uart-oflow-orgate",
145
+ &mms->uart_oflow, TYPE_OR_IRQ);
146
+ qdev_prop_set_uint32(DEVICE(&mms->uart_oflow), "num-lines",
147
+ MPS3R_UART_MAX * 2);
148
+ qdev_realize(DEVICE(&mms->uart_oflow), NULL, &error_fatal);
149
+ qdev_connect_gpio_out(DEVICE(&mms->uart_oflow), 0,
150
+ qdev_get_gpio_in(gicdev, 17));
151
+
152
+ for (int i = 0; i < MPS3R_UART_MAX; i++) {
153
+ hwaddr baseaddr = 0xe0205000 + i * 0x1000;
154
+ int rxirq = 5 + i * 2, txirq = 6 + i * 2, combirq = 13 + i;
155
+
156
+ create_uart(mms, i + MPS3R_CPU_MAX, sysmem, baseaddr,
157
+ qdev_get_gpio_in(gicdev, txirq),
158
+ qdev_get_gpio_in(gicdev, rxirq),
159
+ qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2),
160
+ qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2 + 1),
161
+ qdev_get_gpio_in(gicdev, combirq));
162
+ }
163
164
mms->bootinfo.ram_size = machine->ram_size;
165
mms->bootinfo.board_id = -1;
72
--
166
--
73
2.20.1
167
2.34.1
74
168
75
169
diff view generated by jsdifflib
[PULL 16/29] hw/arm/fsl-imx6: Connect watchdog interrupts
[PULL 33/35] hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
1
From: Guenter Roeck <linux@roeck-us.net>
1
Add the GPIO, watchdog, dual-timer and I2C devices to the mps3-an536
2
board. These are all simple devices that just need to be created and
3
wired up.
2
4
3
With this patch applied, the watchdog in the sabrelite emulation
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
is fully operational, including pretimeout support.
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20240206132931.38376-12-peter.maydell@linaro.org
8
---
9
hw/arm/mps3r.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
10
1 file changed, 59 insertions(+)
5
11
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20200517162135.110364-6-linux@roeck-us.net
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/fsl-imx6.c | 9 +++++++++
12
1 file changed, 9 insertions(+)
13
14
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/fsl-imx6.c
14
--- a/hw/arm/mps3r.c
17
+++ b/hw/arm/fsl-imx6.c
15
+++ b/hw/arm/mps3r.c
18
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
16
@@ -XXX,XX +XXX,XX @@
19
FSL_IMX6_WDOG1_ADDR,
17
#include "sysemu/sysemu.h"
20
FSL_IMX6_WDOG2_ADDR,
18
#include "hw/boards.h"
21
};
19
#include "hw/or-irq.h"
22
+ static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = {
20
+#include "hw/qdev-clock.h"
23
+ FSL_IMX6_WDOG1_IRQ,
21
#include "hw/qdev-properties.h"
24
+ FSL_IMX6_WDOG2_IRQ,
22
#include "hw/arm/boot.h"
25
+ };
23
#include "hw/arm/bsa.h"
26
24
#include "hw/char/cmsdk-apb-uart.h"
27
+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
25
+#include "hw/i2c/arm_sbcon_i2c.h"
28
+ &error_abort);
26
#include "hw/intc/arm_gicv3.h"
29
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
27
+#include "hw/misc/unimp.h"
30
&error_abort);
28
+#include "hw/timer/cmsdk-apb-dualtimer.h"
31
29
+#include "hw/watchdog/cmsdk-apb-watchdog.h"
32
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
30
33
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
31
/* Define the layout of RAM and ROM in a board */
34
+ qdev_get_gpio_in(DEVICE(&s->a9mpcore),
32
typedef struct RAMInfo {
35
+ FSL_IMX6_WDOGn_IRQ[i]));
33
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
34
CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
35
OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
36
OrIRQState uart_oflow;
37
+ CMSDKAPBWatchdog watchdog;
38
+ CMSDKAPBDualTimer dualtimer;
39
+ ArmSbconI2CState i2c[5];
40
+ Clock *clk;
41
};
42
43
#define TYPE_MPS3R_MACHINE "mps3r"
44
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
45
MemoryRegion *sysmem = get_system_memory();
46
DeviceState *gicdev;
47
48
+ mms->clk = clock_new(OBJECT(machine), "CLK");
49
+ clock_set_hz(mms->clk, CLK_FRQ);
50
+
51
for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
52
MemoryRegion *mr = mr_for_raminfo(mms, ri);
53
memory_region_add_subregion(sysmem, ri->base, mr);
54
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
55
qdev_get_gpio_in(gicdev, combirq));
36
}
56
}
37
57
38
/* ROM memory */
58
+ for (int i = 0; i < 4; i++) {
59
+ /* CMSDK GPIO controllers */
60
+ g_autofree char *s = g_strdup_printf("gpio%d", i);
61
+ create_unimplemented_device(s, 0xe0000000 + i * 0x1000, 0x1000);
62
+ }
63
+
64
+ object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
65
+ TYPE_CMSDK_APB_WATCHDOG);
66
+ qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->clk);
67
+ sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
68
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
69
+ qdev_get_gpio_in(gicdev, 0));
70
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0xe0100000);
71
+
72
+ object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
73
+ TYPE_CMSDK_APB_DUALTIMER);
74
+ qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->clk);
75
+ sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
76
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
77
+ qdev_get_gpio_in(gicdev, 3));
78
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 1,
79
+ qdev_get_gpio_in(gicdev, 1));
80
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 2,
81
+ qdev_get_gpio_in(gicdev, 2));
82
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0xe0101000);
83
+
84
+ for (int i = 0; i < ARRAY_SIZE(mms->i2c); i++) {
85
+ static const hwaddr i2cbase[] = {0xe0102000, /* Touch */
86
+ 0xe0103000, /* Audio */
87
+ 0xe0107000, /* Shield0 */
88
+ 0xe0108000, /* Shield1 */
89
+ 0xe0109000}; /* DDR4 EEPROM */
90
+ g_autofree char *s = g_strdup_printf("i2c%d", i);
91
+
92
+ object_initialize_child(OBJECT(mms), s, &mms->i2c[i],
93
+ TYPE_ARM_SBCON_I2C);
94
+ sysbus_realize(SYS_BUS_DEVICE(&mms->i2c[i]), &error_fatal);
95
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->i2c[i]), 0, i2cbase[i]);
96
+ if (i != 2 && i != 3) {
97
+ /*
98
+ * internal-only bus: mark it full to avoid user-created
99
+ * i2c devices being plugged into it.
100
+ */
101
+ qbus_mark_full(qdev_get_child_bus(DEVICE(&mms->i2c[i]), "i2c"));
102
+ }
103
+ }
104
+
105
mms->bootinfo.ram_size = machine->ram_size;
106
mms->bootinfo.board_id = -1;
107
mms->bootinfo.loader_start = mmc->loader_start;
39
--
108
--
40
2.20.1
109
2.34.1
41
110
42
111
diff view generated by jsdifflib
[PULL 18/29] hw/arm/fsl-imx7: Instantiate various unimplemented devices
[PULL 34/35] hw/arm/mps3r: Add remaining devices
1
From: Guenter Roeck <linux@roeck-us.net>
1
Add the remaining devices (or unimplemented-device stubs) for
2
this board: SPI controllers, SCC, FPGAIO, I2S, RTC, the
3
QSPI write-config block, and ethernet.
2
4
3
Instantiating PWM, CAN, CAAM, and OCOTP devices is necessary to avoid
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
crashes when booting mainline Linux.
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20240206132931.38376-13-peter.maydell@linaro.org
8
---
9
hw/arm/mps3r.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++
10
1 file changed, 74 insertions(+)
5
11
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20200517162135.110364-8-linux@roeck-us.net
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/fsl-imx7.h | 16 ++++++++++++++++
12
hw/arm/fsl-imx7.c | 24 ++++++++++++++++++++++++
13
2 files changed, 40 insertions(+)
14
15
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/fsl-imx7.h
14
--- a/hw/arm/mps3r.c
18
+++ b/include/hw/arm/fsl-imx7.h
15
+++ b/hw/arm/mps3r.c
19
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
16
@@ -XXX,XX +XXX,XX @@
20
FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000,
17
#include "hw/char/cmsdk-apb-uart.h"
21
FSL_IMX7_IOMUXCn_SIZE = 0x1000,
18
#include "hw/i2c/arm_sbcon_i2c.h"
22
19
#include "hw/intc/arm_gicv3.h"
23
+ FSL_IMX7_OCOTP_ADDR = 0x30350000,
20
+#include "hw/misc/mps2-scc.h"
24
+ FSL_IMX7_OCOTP_SIZE = 0x10000,
21
+#include "hw/misc/mps2-fpgaio.h"
22
#include "hw/misc/unimp.h"
23
+#include "hw/net/lan9118.h"
24
+#include "hw/rtc/pl031.h"
25
+#include "hw/ssi/pl022.h"
26
#include "hw/timer/cmsdk-apb-dualtimer.h"
27
#include "hw/watchdog/cmsdk-apb-watchdog.h"
28
29
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
30
CMSDKAPBWatchdog watchdog;
31
CMSDKAPBDualTimer dualtimer;
32
ArmSbconI2CState i2c[5];
33
+ PL022State spi[3];
34
+ MPS2SCC scc;
35
+ MPS2FPGAIO fpgaio;
36
+ UnimplementedDeviceState i2s_audio;
37
+ PL031State rtc;
38
Clock *clk;
39
};
40
41
@@ -XXX,XX +XXX,XX @@ static const RAMInfo an536_raminfo[] = {
42
}
43
};
44
45
+static const int an536_oscclk[] = {
46
+ 24000000, /* 24MHz reference for RTC and timers */
47
+ 50000000, /* 50MHz ACLK */
48
+ 50000000, /* 50MHz MCLK */
49
+ 50000000, /* 50MHz GPUCLK */
50
+ 24576000, /* 24.576MHz AUDCLK */
51
+ 23750000, /* 23.75MHz HDLCDCLK */
52
+ 100000000, /* 100MHz DDR4_REF_CLK */
53
+};
25
+
54
+
26
FSL_IMX7_ANALOG_ADDR = 0x30360000,
55
static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
27
FSL_IMX7_SNVS_ADDR = 0x30370000,
56
const RAMInfo *raminfo)
28
FSL_IMX7_CCM_ADDR = 0x30380000,
57
{
29
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
58
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
30
FSL_IMX7_ADC2_ADDR = 0x30620000,
59
MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
31
FSL_IMX7_ADCn_SIZE = 0x1000,
60
MemoryRegion *sysmem = get_system_memory();
32
61
DeviceState *gicdev;
33
+ FSL_IMX7_PWM1_ADDR = 0x30660000,
62
+ QList *oscclk;
34
+ FSL_IMX7_PWM2_ADDR = 0x30670000,
63
35
+ FSL_IMX7_PWM3_ADDR = 0x30680000,
64
mms->clk = clock_new(OBJECT(machine), "CLK");
36
+ FSL_IMX7_PWM4_ADDR = 0x30690000,
65
clock_set_hz(mms->clk, CLK_FRQ);
37
+ FSL_IMX7_PWMn_SIZE = 0x10000,
66
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
67
}
68
}
69
70
+ for (int i = 0; i < ARRAY_SIZE(mms->spi); i++) {
71
+ g_autofree char *s = g_strdup_printf("spi%d", i);
72
+ hwaddr baseaddr = 0xe0104000 + i * 0x1000;
38
+
73
+
39
FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
74
+ object_initialize_child(OBJECT(mms), s, &mms->spi[i], TYPE_PL022);
40
FSL_IMX7_PCIE_PHY_SIZE = 0x10000,
75
+ sysbus_realize(SYS_BUS_DEVICE(&mms->spi[i]), &error_fatal);
41
76
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->spi[i]), 0, baseaddr);
42
FSL_IMX7_GPC_ADDR = 0x303A0000,
77
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->spi[i]), 0,
43
78
+ qdev_get_gpio_in(gicdev, 22 + i));
44
+ FSL_IMX7_CAAM_ADDR = 0x30900000,
79
+ }
45
+ FSL_IMX7_CAAM_SIZE = 0x40000,
46
+
80
+
47
+ FSL_IMX7_CAN1_ADDR = 0x30A00000,
81
+ object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
48
+ FSL_IMX7_CAN2_ADDR = 0x30A10000,
82
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg0", 0);
49
+ FSL_IMX7_CANn_SIZE = 0x10000,
83
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg4", 0x2);
84
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-aid", 0x00200008);
85
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-id", 0x41055360);
86
+ oscclk = qlist_new();
87
+ for (int i = 0; i < ARRAY_SIZE(an536_oscclk); i++) {
88
+ qlist_append_int(oscclk, an536_oscclk[i]);
89
+ }
90
+ qdev_prop_set_array(DEVICE(&mms->scc), "oscclk", oscclk);
91
+ sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
92
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->scc), 0, 0xe0200000);
50
+
93
+
51
FSL_IMX7_I2C1_ADDR = 0x30A20000,
94
+ create_unimplemented_device("i2s-audio", 0xe0201000, 0x1000);
52
FSL_IMX7_I2C2_ADDR = 0x30A30000,
95
+
53
FSL_IMX7_I2C3_ADDR = 0x30A40000,
96
+ object_initialize_child(OBJECT(mms), "fpgaio", &mms->fpgaio,
54
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
97
+ TYPE_MPS2_FPGAIO);
55
index XXXXXXX..XXXXXXX 100644
98
+ qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", an536_oscclk[1]);
56
--- a/hw/arm/fsl-imx7.c
99
+ qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "num-leds", 10);
57
+++ b/hw/arm/fsl-imx7.c
100
+ qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-switches", true);
58
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
101
+ qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-dbgctrl", false);
59
*/
102
+ sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
60
create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR, FSL_IMX7_SDMA_SIZE);
103
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0xe0202000);
61
104
+
62
+ /*
105
+ create_unimplemented_device("clcd", 0xe0209000, 0x1000);
63
+ * CAAM
106
+
64
+ */
107
+ object_initialize_child(OBJECT(mms), "rtc", &mms->rtc, TYPE_PL031);
65
+ create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
108
+ sysbus_realize(SYS_BUS_DEVICE(&mms->rtc), &error_fatal);
109
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->rtc), 0, 0xe020a000);
110
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->rtc), 0,
111
+ qdev_get_gpio_in(gicdev, 4));
66
+
112
+
67
+ /*
113
+ /*
68
+ * PWM
114
+ * In hardware this is a LAN9220; the LAN9118 is software compatible
115
+ * except that it doesn't support the checksum-offload feature.
69
+ */
116
+ */
70
+ create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
117
+ lan9118_init(0xe0300000,
71
+ create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
118
+ qdev_get_gpio_in(gicdev, 18));
72
+ create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
73
+ create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
74
+
119
+
75
+ /*
120
+ create_unimplemented_device("usb", 0xe0301000, 0x1000);
76
+ * CAN
121
+ create_unimplemented_device("qspi-write-config", 0xe0600000, 0x1000);
77
+ */
78
+ create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
79
+ create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
80
+
122
+
81
+ /*
123
mms->bootinfo.ram_size = machine->ram_size;
82
+ * OCOTP
124
mms->bootinfo.board_id = -1;
83
+ */
125
mms->bootinfo.loader_start = mmc->loader_start;
84
+ create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
85
+ FSL_IMX7_OCOTP_SIZE);
86
87
object_property_set_bool(OBJECT(&s->gpr), true, "realized",
88
&error_abort);
89
--
126
--
90
2.20.1
127
2.34.1
91
128
92
129
diff view generated by jsdifflib
[PULL 05/29] docs/system: Document the various MPS2 models
[PULL 35/35] docs: Add documentation for the mps3-an536 board
1
Add basic documentation of the MPS2 board models.
1
Add documentation for the mps3-an536 board type.
2
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
5
Message-id: 20240206132931.38376-14-peter.maydell@linaro.org
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20200507151819.28444-5-peter.maydell@linaro.org
8
---
6
---
9
docs/system/arm/mps2.rst | 29 +++++++++++++++++++++++++++++
7
docs/system/arm/mps2.rst | 37 ++++++++++++++++++++++++++++++++++---
10
docs/system/target-arm.rst | 1 +
8
1 file changed, 34 insertions(+), 3 deletions(-)
11
MAINTAINERS | 1 +
12
3 files changed, 31 insertions(+)
13
create mode 100644 docs/system/arm/mps2.rst
14
9
15
diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
10
diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
16
new file mode 100644
11
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX
12
--- a/docs/system/arm/mps2.rst
18
--- /dev/null
19
+++ b/docs/system/arm/mps2.rst
13
+++ b/docs/system/arm/mps2.rst
20
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@
21
+Arm MPS2 boards (``mps2-an385``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
15
-Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an547``)
22
+================================================================================
16
-=========================================================================================================================================================
17
+Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an536``, ``mps3-an547``)
18
+=========================================================================================================================================================================
19
20
-These board models all use Arm M-profile CPUs.
21
+These board models use Arm M-profile or R-profile CPUs.
22
23
The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
24
bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
25
@@ -XXX,XX +XXX,XX @@ FPGA image.
26
27
QEMU models the following FPGA images:
28
29
+FPGA images using M-profile CPUs:
23
+
30
+
24
+These board models all use Arm M-profile CPUs.
31
``mps2-an385``
32
Cortex-M3 as documented in Arm Application Note AN385
33
``mps2-an386``
34
@@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images:
35
``mps3-an547``
36
Cortex-M55 on an MPS3, as documented in Arm Application Note AN547
37
38
+FPGA images using R-profile CPUs:
25
+
39
+
26
+The Arm MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
40
+``mps3-an536``
27
+FPGA but is otherwise the same as the 2). Since the CPU itself
41
+ Dual Cortex-R52 on an MPS3, as documented in Arm Application Note AN536
28
+and most of the devices are in the FPGA, the details of the board
29
+as seen by the guest depend significantly on the FPGA image.
30
+
42
+
31
+QEMU models the following FPGA images:
43
Differences between QEMU and real hardware:
44
45
- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
46
@@ -XXX,XX +XXX,XX @@ Differences between QEMU and real hardware:
47
flash, but only as simple ROM, so attempting to rewrite the flash
48
from the guest will fail
49
- QEMU does not model the USB controller in MPS3 boards
50
+- AN536 does not support runtime control of CPU reset and halt via
51
+ the SCC CFG_REG0 register.
52
+- AN536 does not support enabling or disabling the flash and ATCM
53
+ interfaces via the SCC CFG_REG1 register.
54
+- AN536 does not support setting of the initial vector table
55
+ base address via the SCC CFG_REG6 and CFG_REG7 register config,
56
+ and does not provide a mechanism for specifying these values at
57
+ startup, so all guest images must be built to start from TCM
58
+ (i.e. to expect the interrupt vector base at 0 from reset).
59
+- AN536 defaults to only creating a single CPU; this is the equivalent
60
+ of the way the real FPGA image usually runs with the second Cortex-R52
61
+ held in halt via the initial SCC CFG_REG0 register setting. You can
62
+ create the second CPU with ``-smp 2``; both CPUs will then start
63
+ execution immediately on startup.
32
+
64
+
33
+``mps2-an385``
65
+Note that for the AN536 the first UART is accessible only by
34
+ Cortex-M3 as documented in ARM Application Note AN385
66
+CPU0, and the second UART is accessible only by CPU1. The
35
+``mps2-an511``
67
+first UART accessible shared between both CPUs is the third
36
+ Cortex-M3 'DesignStart' as documented in AN511
68
+UART. Guest software might therefore be built to use either
37
+``mps2-an505``
69
+the first UART or the third UART; if you don't see any output
38
+ Cortex-M33 as documented in ARM Application Note AN505
70
+from the UART you are looking at, try one of the others.
39
+``mps2-an521``
71
+(Even if the AN536 machine is started with a single CPU and so
40
+ Dual Cortex-M33 as documented in Application Note AN521
72
+no "CPU1-only UART", the UART numbering remains the same,
41
+
73
+with the third UART being the first of the shared ones.)
42
+Differences between QEMU and real hardware:
74
43
+
75
Machine-specific options
44
+- AN385 remapping of low 16K of memory to either ZBT SSRAM1 or to
76
""""""""""""""""""""""""
45
+ block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as
46
+ if zbt_boot_ctrl is always zero)
47
+- QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest
48
+ visible difference is that the LAN9118 doesn't support checksum
49
+ offloading
50
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
51
index XXXXXXX..XXXXXXX 100644
52
--- a/docs/system/target-arm.rst
53
+++ b/docs/system/target-arm.rst
54
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
55
:maxdepth: 1
56
57
arm/integratorcp
58
+ arm/mps2
59
arm/realview
60
arm/versatile
61
arm/vexpress
62
diff --git a/MAINTAINERS b/MAINTAINERS
63
index XXXXXXX..XXXXXXX 100644
64
--- a/MAINTAINERS
65
+++ b/MAINTAINERS
66
@@ -XXX,XX +XXX,XX @@ F: hw/misc/armsse-cpuid.c
67
F: include/hw/misc/armsse-cpuid.h
68
F: hw/misc/armsse-mhu.c
69
F: include/hw/misc/armsse-mhu.h
70
+F: docs/system/arm/mps2.rst
71
72
Musca
73
M: Peter Maydell <peter.maydell@linaro.org>
74
--
77
--
75
2.20.1
78
2.34.1
76
79
77
80
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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