target-arm queue: nothing big, just a collection of minor things.

The following changes since commit ae3aa5da96f4ccf0c2a28851449d92db9fcfad71:

Merge remote-tracking branch 'remotes/berrange/tags/socket-next-pull-request' into staging (2020-05-21 16:47:28 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200521

for you to fetch changes up to 17b5df7b65d0192c5d775b5e1581518580774c77:

linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 (2020-05-21 20:00:19 +0100)

* tests/acceptance: Add a test for the canon-a1100 machine

* docs/system: Document some of the Arm development boards

* linux-user: make BKPT insn cause SIGTRAP, not be a syscall

* target/arm: Remove unused GEN_NEON_INTEGER_OP macro

* fsl-imx25, fsl-imx31, fsl-imx6, fsl-imx6ul, fsl-imx7: implement watchdog

* hw/arm: Use qemu_log_mask() instead of hw_error() in various places

* ARM: PL061: Introduce N_GPIOS

* target/arm: Improve clear_vec_high() usage

* target/arm: Allow user-mode code to write CPSR.E via MSR

* linux-user/arm: Reset CPSR_E when entering a signal handler

* linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32

Amanieu d'Antras (1):

linux-user/arm: Reset CPSR_E when entering a signal handler

Geert Uytterhoeven (1):

ARM: PL061: Introduce N_GPIOS

Guenter Roeck (8):

hw: Move i.MX watchdog driver to hw/watchdog

hw/watchdog: Implement full i.MX watchdog support

hw/arm/fsl-imx25: Wire up watchdog

hw/arm/fsl-imx31: Wire up watchdog

hw/arm/fsl-imx6: Connect watchdog interrupts

hw/arm/fsl-imx6ul: Connect watchdog interrupts

hw/arm/fsl-imx7: Instantiate various unimplemented devices

hw/arm/fsl-imx7: Connect watchdog interrupts

Peter Maydell (12):

docs/system: Add 'Arm' to the Integrator/CP document title

docs/system: Sort Arm board index into alphabetical order

docs/system: Document Arm Versatile Express boards

docs/system: Document the various MPS2 models

docs/system: Document Musca boards

linux-user/arm: BKPT should cause SIGTRAP, not be a syscall

linux-user/arm: Remove bogus SVC 0xf0002 handling

linux-user/arm: Handle invalid arm-specific syscalls correctly

linux-user/arm: Fix identification of syscall numbers

target/arm: Remove unused GEN_NEON_INTEGER_OP macro

target/arm: Allow user-mode code to write CPSR.E via MSR

linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32

Philippe Mathieu-Daudé (4):

hw/arm/integratorcp: Replace hw_error() by qemu_log_mask()

hw/arm/pxa2xx: Replace hw_error() by qemu_log_mask()

hw/char/xilinx_uartlite: Replace hw_error() by qemu_log_mask()

hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask()

Richard Henderson (2):

target/arm: Use tcg_gen_gvec_mov for clear_vec_high

target/arm: Use clear_vec_high more effectively

From: Guenter Roeck <linux@roeck-us.net>

In preparation for a full implementation, move i.MX watchdog driver

from hw/misc to hw/watchdog. While at it, add the watchdog files

to MAINTAINERS.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>

Message-id: 20200517162135.110364-2-linux@roeck-us.net

include/hw/arm/fsl-imx6.h | 2 +-

include/hw/arm/fsl-imx6ul.h | 2 +-

include/hw/arm/fsl-imx7.h | 2 +-

include/hw/{misc/imx2_wdt.h => watchdog/wdt_imx2.h} | 0

hw/{misc/imx2_wdt.c => watchdog/wdt_imx2.c} | 2 +-

MAINTAINERS | 2 ++

hw/arm/Kconfig | 3 +++

hw/misc/Makefile.objs | 1 -

hw/watchdog/Kconfig | 3 +++

hw/watchdog/Makefile.objs | 1 +

10 files changed, 13 insertions(+), 5 deletions(-)

rename include/hw/{misc/imx2_wdt.h => watchdog/wdt_imx2.h} (100%)

rename hw/{misc/imx2_wdt.c => watchdog/wdt_imx2.c} (98%)

@@ -XXX,XX +XXX,XX @@ config FSL_IMX6

select IMX_FEC

select IMX_I2C

select IMX_USBPHY

+ select WDT_IMX2

select SDHCI

config ASPEED_SOC

@@ -XXX,XX +XXX,XX @@ config FSL_IMX7

select IMX

select IMX_FEC

select IMX_I2C

+ select WDT_IMX2

select PCI_EXPRESS_DESIGNWARE

select SDHCI

select UNIMP

@@ -XXX,XX +XXX,XX @@ config FSL_IMX6UL

select IMX

select IMX_FEC

select IMX_I2C

+ select WDT_IMX2

select SDHCI

select UNIMP

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/Makefile.objs

+++ b/hw/misc/Makefile.objs

@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IMX) += imx6_ccm.o

common-obj-$(CONFIG_IMX) += imx6ul_ccm.o

obj-$(CONFIG_IMX) += imx6_src.o

common-obj-$(CONFIG_IMX) += imx7_ccm.o

-common-obj-$(CONFIG_IMX) += imx2_wdt.o

common-obj-$(CONFIG_IMX) += imx7_snvs.o

common-obj-$(CONFIG_IMX) += imx7_gpr.o

common-obj-$(CONFIG_IMX) += imx_rngc.o

diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig

index XXXXXXX..XXXXXXX 100644

--- a/hw/watchdog/Kconfig

+++ b/hw/watchdog/Kconfig

@@ -XXX,XX +XXX,XX @@ config WDT_IB700

config WDT_DIAG288

bool

+

+config WDT_IMX2

+ bool

diff --git a/hw/watchdog/Makefile.objs b/hw/watchdog/Makefile.objs

index XXXXXXX..XXXXXXX 100644

--- a/hw/watchdog/Makefile.objs

+++ b/hw/watchdog/Makefile.objs

@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_WDT_IB6300ESB) += wdt_i6300esb.o

common-obj-$(CONFIG_WDT_IB700) += wdt_ib700.o

common-obj-$(CONFIG_WDT_DIAG288) += wdt_diag288.o

common-obj-$(CONFIG_ASPEED_SOC) += wdt_aspeed.o

+common-obj-$(CONFIG_WDT_IMX2) += wdt_imx2.o

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

hw_error() calls exit(). This a bit overkill when we can log

the accesses as unimplemented or guest error.

When fuzzing the devices, we don't want the whole process to

exit. Replace some hw_error() calls by qemu_log_mask().

Per the datasheet "Exynos 4412 RISC Microprocessor Rev 1.00"

Chapter 25 "Multi Core Timer (MCT)" figure 1 and table 4,

the default value on the APB bus is 0.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20200518140309.5220-5-f4bug@amsat.org

hw/timer/exynos4210_mct.c | 12 +++++-------

1 file changed, 5 insertions(+), 7 deletions(-)

@@ -XXX,XX +XXX,XX @@

#include "qemu/osdep.h"

#include "qemu/log.h"

-#include "hw/hw.h"

#include "hw/sysbus.h"

#include "migration/vmstate.h"

#include "qemu/timer.h"

@@ -XXX,XX +XXX,XX @@

#include "hw/ptimer.h"

#include "hw/arm/exynos4210.h"

-#include "hw/hw.h"

#include "hw/irq.h"

//#define DEBUG_MCT

@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,

int index;

int shift;

uint64_t count;

- uint32_t value;

+ uint32_t value = 0;

int lt_i;

switch (offset) {

@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,

break;

default:

- hw_error("exynos4210.mct: bad read offset "

- TARGET_FMT_plx "\n", offset);

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",

+ __func__, offset);

break;

}

return value;

@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,

break;

default:

- hw_error("exynos4210.mct: bad write offset "

- TARGET_FMT_plx "\n", offset);

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",

+ __func__, offset);

break;

Add basic documentation of the MPS2 board models.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20200507151819.28444-5-peter.maydell@linaro.org

docs/system/arm/mps2.rst | 29 +++++++++++++++++++++++++++++

docs/system/target-arm.rst | 1 +

MAINTAINERS | 1 +

3 files changed, 31 insertions(+)

create mode 100644 docs/system/arm/mps2.rst

diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/docs/system/arm/mps2.rst

+Arm MPS2 boards (``mps2-an385``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)

+================================================================================

+

+These board models all use Arm M-profile CPUs.

+

+The Arm MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger

+FPGA but is otherwise the same as the 2). Since the CPU itself

+and most of the devices are in the FPGA, the details of the board

+as seen by the guest depend significantly on the FPGA image.

+

+QEMU models the following FPGA images:

+

+``mps2-an385``

+ Cortex-M3 as documented in ARM Application Note AN385

+``mps2-an511``

+ Cortex-M3 'DesignStart' as documented in AN511

+``mps2-an505``

+ Cortex-M33 as documented in ARM Application Note AN505

+``mps2-an521``

+ Dual Cortex-M33 as documented in Application Note AN521

+

+Differences between QEMU and real hardware:

+

+- AN385 remapping of low 16K of memory to either ZBT SSRAM1 or to

+ block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as

+ if zbt_boot_ctrl is always zero)

+- QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest

+ visible difference is that the LAN9118 doesn't support checksum

+ offloading

diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/system/target-arm.rst

+++ b/docs/system/target-arm.rst

@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running

:maxdepth: 1

arm/integratorcp

+ arm/mps2

arm/realview

arm/versatile

arm/vexpress

diff --git a/MAINTAINERS b/MAINTAINERS

index XXXXXXX..XXXXXXX 100644

--- a/MAINTAINERS

+++ b/MAINTAINERS

@@ -XXX,XX +XXX,XX @@ F: hw/misc/armsse-cpuid.c

F: include/hw/misc/armsse-cpuid.h

F: hw/misc/armsse-mhu.c

F: include/hw/misc/armsse-mhu.h

+F: docs/system/arm/mps2.rst

Musca

M: Peter Maydell <peter.maydell@linaro.org>

The Arm signal-handling code has some parts ifdeffed with a

TARGET_CONFIG_CPU_32, which is always defined. This is a leftover

from when this code's structure was based on the Linux kernel

signal handling code, where it was intended to support 26-bit

Arm CPUs. The kernel dropped its CONFIG_CPU_32 in kernel commit

4da8b8208eded0ba21e3 in 2009.

QEMU has never had 26-bit CPU support and is unlikely to ever

add it; we certainly aren't going to support 26-bit Linux

binaries via linux-user mode. The ifdef is just unhelpful

noise, so remove it entirely.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20200518143014.20689-1-peter.maydell@linaro.org

linux-user/arm/signal.c | 6 ------

1 file changed, 6 deletions(-)

diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c

--- a/linux-user/arm/signal.c

+++ b/linux-user/arm/signal.c

@@ -XXX,XX +XXX,XX @@ struct rt_sigframe_v2

abi_ulong retcode[4];

};

-#define TARGET_CONFIG_CPU_32 1

-

/*

* For ARM syscalls, we encode the syscall number into the instruction.

*/

@@ -XXX,XX +XXX,XX @@ setup_sigcontext(struct target_sigcontext *sc, /*struct _fpstate *fpstate,*/

__put_user(env->regs[13], &sc->arm_sp);

__put_user(env->regs[14], &sc->arm_lr);

__put_user(env->regs[15], &sc->arm_pc);

-#ifdef TARGET_CONFIG_CPU_32

__put_user(cpsr_read(env), &sc->arm_cpsr);

-#endif

__put_user(/* current->thread.trap_no */ 0, &sc->trap_no);

__put_user(/* current->thread.error_code */ 0, &sc->error_code);

@@ -XXX,XX +XXX,XX @@ restore_sigcontext(CPUARMState *env, struct target_sigcontext *sc)

__get_user(env->regs[13], &sc->arm_sp);

__get_user(env->regs[14], &sc->arm_lr);

__get_user(env->regs[15], &sc->arm_pc);

-#ifdef TARGET_CONFIG_CPU_32

__get_user(cpsr, &sc->arm_cpsr);

cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr);

arm_rebuild_hflags(env);

-#endif

err |= !valid_user_regs(env);

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

hw_error() calls exit(). This a bit overkill when we can log

the accesses as unimplemented or guest error.

When fuzzing the devices, we don't want the whole process to

exit. Replace some hw_error() calls by qemu_log_mask().

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20200518140309.5220-3-f4bug@amsat.org

hw/arm/pxa2xx_gpio.c | 7 ++++---

hw/display/pxa2xx_lcd.c | 8 +++++---

hw/dma/pxa2xx_dma.c | 14 +++++++++-----

3 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c

--- a/hw/arm/pxa2xx_gpio.c

+++ b/hw/arm/pxa2xx_gpio.c

@@ -XXX,XX +XXX,XX @@

#include "qemu/osdep.h"

#include "cpu.h"

-#include "hw/hw.h"

#include "hw/irq.h"

#include "hw/qdev-properties.h"

#include "hw/sysbus.h"

@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,

return s->status[bank];

default:

- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",

+ __func__, offset);

}

return 0;

@@ -XXX,XX +XXX,XX @@ static void pxa2xx_gpio_write(void *opaque, hwaddr offset,

break;

default:

- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",

+ __func__, offset);

}

}

diff --git a/hw/display/pxa2xx_lcd.c b/hw/display/pxa2xx_lcd.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/display/pxa2xx_lcd.c

+++ b/hw/display/pxa2xx_lcd.c

@@ -XXX,XX +XXX,XX @@

*/

#include "qemu/osdep.h"

-#include "hw/hw.h"

+#include "qemu/log.h"

#include "hw/irq.h"

#include "migration/vmstate.h"

#include "ui/console.h"

@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_lcdc_read(void *opaque, hwaddr offset,

default:

fail:

- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",

+ __func__, offset);

}

return 0;

@@ -XXX,XX +XXX,XX @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,

default:

fail:

- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",

+ __func__, offset);

}

}

diff --git a/hw/dma/pxa2xx_dma.c b/hw/dma/pxa2xx_dma.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/dma/pxa2xx_dma.c

+++ b/hw/dma/pxa2xx_dma.c

@@ -XXX,XX +XXX,XX @@

*/

#include "qemu/osdep.h"

+#include "qemu/log.h"

#include "hw/hw.h"

#include "hw/irq.h"

#include "hw/qdev-properties.h"

@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,

unsigned int channel;

if (size != 4) {

- hw_error("%s: Bad access width\n", __func__);

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n",

+ __func__, size);

return 5;

}

@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,

return s->chan[channel].cmd;

}

}

- hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",

+ __func__, offset);

return 7;

}

@@ -XXX,XX +XXX,XX @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset,

unsigned int channel;

if (size != 4) {

- hw_error("%s: Bad access width\n", __func__);

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n",

+ __func__, size);

return;

}

@@ -XXX,XX +XXX,XX @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset,

break;

}

fail:

- hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __func__, offset);

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",

+ __func__, offset);

}

}

hw_error() calls exit(). This a bit overkill when we can log

the accesses as unimplemented or guest error.

When fuzzing the devices, we don't want the whole process to

exit. Replace some hw_error() calls by qemu_log_mask().

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20200518140309.5220-4-f4bug@amsat.org

hw/char/xilinx_uartlite.c | 5 +++--

1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c

--- a/hw/char/xilinx_uartlite.c

+++ b/hw/char/xilinx_uartlite.c

@@ -XXX,XX +XXX,XX @@

*/

#include "qemu/osdep.h"

-#include "hw/hw.h"

+#include "qemu/log.h"

#include "hw/irq.h"

#include "hw/qdev-properties.h"

#include "hw/sysbus.h"

@@ -XXX,XX +XXX,XX @@ uart_write(void *opaque, hwaddr addr,

switch (addr)

{

case R_STATUS:

- hw_error("write to UART STATUS?\n");

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: write to UART STATUS\n",

+ __func__);

break;

case R_CTRL:

Using the MSR instruction to write to CPSR.E is deprecated, but it is

required to work from any mode including unprivileged code. We were

incorrectly forbidding usermode code from writing it because

CPSR_USER did not include the CPSR_E bit.

We use CPSR_USER in only three places:

* as the mask of what to allow userspace MSR to write to CPSR

* when deciding what bits a linux-user signal-return should be

able to write from the sigcontext structure

* in target_user_copy_regs() when we set up the initial

registers for the linux-user process

In the first two cases not being able to update CPSR.E is a bug, and

in the third case it doesn't matter because CPSR.E is always 0 there.

So we can fix both bugs by adding CPSR_E to CPSR_USER.

Because the cpsr_write() in restore_sigcontext() is now changing

a CPSR bit which is cached in hflags, we need to add an

arm_rebuild_hflags() call there; the callsite in

target_user_copy_regs() was already rebuilding hflags for other

reasons.

(The recommended way to change CPSR.E is to use the 'SETEND'

instruction, which we do correctly allow from usermode code.)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20200518142801.20503-1-peter.maydell@linaro.org

target/arm/cpu.h | 2 +-

linux-user/arm/signal.c | 1 +

2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);

#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \

| CPSR_NZCV)

/* Bits writable in user mode. */

-#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)

+#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)

/* Execution state bits. MRS read as zero, MSR writes ignored. */

#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)

diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c

index XXXXXXX..XXXXXXX 100644

--- a/linux-user/arm/signal.c

+++ b/linux-user/arm/signal.c

@@ -XXX,XX +XXX,XX @@ restore_sigcontext(CPUARMState *env, struct target_sigcontext *sc)

#ifdef TARGET_CONFIG_CPU_32

__get_user(cpsr, &sc->arm_cpsr);

cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr);

+ arm_rebuild_hflags(env);

#endif

err |= !valid_user_regs(env);

Add 'Arm' to the Integrator/CP document title, for consistency with

the titling of the other documentation of Arm devboard models

(versatile, realview).

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20200507151819.28444-2-peter.maydell@linaro.org

docs/system/arm/integratorcp.rst | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/integratorcp.rst b/docs/system/arm/integratorcp.rst

--- a/docs/system/arm/integratorcp.rst

+++ b/docs/system/arm/integratorcp.rst

@@ -XXX,XX +XXX,XX @@

-Integrator/CP (``integratorcp``)

-================================

+Arm Integrator/CP (``integratorcp``)

+====================================

The Arm Integrator/CP board is emulated with the following devices: