1
target-arm queue: nothing big, just a collection of minor things.
1
Patches for rc1: nothing major, just some minor bugfixes and
2
code cleanups.
2
3
3
-- PMM
4
-- PMM
4
5
5
The following changes since commit ae3aa5da96f4ccf0c2a28851449d92db9fcfad71:
6
The following changes since commit f7e1914adad8885a5d4c70239ab90d901ed97e9f:
6
7
7
Merge remote-tracking branch 'remotes/berrange/tags/socket-next-pull-request' into staging (2020-05-21 16:47:28 +0100)
8
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging (2020-11-10 09:24:56 +0000)
8
9
9
are available in the Git repository at:
10
are available in the Git repository at:
10
11
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200521
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201110
12
13
13
for you to fetch changes up to 17b5df7b65d0192c5d775b5e1581518580774c77:
14
for you to fetch changes up to b6c56c8a9a4064ea783f352f43c5df6231a110fa:
14
15
15
linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 (2020-05-21 20:00:19 +0100)
16
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check (2020-11-10 11:03:48 +0000)
16
17
17
----------------------------------------------------------------
18
----------------------------------------------------------------
18
target-arm queue:
19
target-arm queue:
19
* tests/acceptance: Add a test for the canon-a1100 machine
20
* hw/arm/Kconfig: ARM_V7M depends on PTIMER
20
* docs/system: Document some of the Arm development boards
21
* Minor coding style fixes
21
* linux-user: make BKPT insn cause SIGTRAP, not be a syscall
22
* docs: add some notes on the sbsa-ref machine
22
* target/arm: Remove unused GEN_NEON_INTEGER_OP macro
23
* hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
23
* fsl-imx25, fsl-imx31, fsl-imx6, fsl-imx6ul, fsl-imx7: implement watchdog
24
* target/arm: Fix neon VTBL/VTBX for len > 1
24
* hw/arm: Use qemu_log_mask() instead of hw_error() in various places
25
* hw/arm/armsse: Correct expansion MPC interrupt lines
25
* ARM: PL061: Introduce N_GPIOS
26
* hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
26
* target/arm: Improve clear_vec_high() usage
27
* hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
27
* target/arm: Allow user-mode code to write CPSR.E via MSR
28
* hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
28
* linux-user/arm: Reset CPSR_E when entering a signal handler
29
* hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
29
* linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32
30
* hw/arm/nseries: Check return value from load_image_targphys()
31
* tests/qtest/npcm7xx_rng-test: count runs properly
32
* target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
30
33
31
----------------------------------------------------------------
34
----------------------------------------------------------------
32
Amanieu d'Antras (1):
35
Alex Bennée (1):
33
linux-user/arm: Reset CPSR_E when entering a signal handler
36
docs: add some notes on the sbsa-ref machine
34
37
35
Geert Uytterhoeven (1):
38
AlexChen (1):
36
ARM: PL061: Introduce N_GPIOS
39
ssi: Fix bad printf format specifiers
37
40
38
Guenter Roeck (8):
41
Andrew Jones (1):
39
hw: Move i.MX watchdog driver to hw/watchdog
42
hw/arm/Kconfig: ARM_V7M depends on PTIMER
40
hw/watchdog: Implement full i.MX watchdog support
41
hw/arm/fsl-imx25: Wire up watchdog
42
hw/arm/fsl-imx31: Wire up watchdog
43
hw/arm/fsl-imx6: Connect watchdog interrupts
44
hw/arm/fsl-imx6ul: Connect watchdog interrupts
45
hw/arm/fsl-imx7: Instantiate various unimplemented devices
46
hw/arm/fsl-imx7: Connect watchdog interrupts
47
43
48
Peter Maydell (12):
44
Havard Skinnemoen (1):
49
docs/system: Add 'Arm' to the Integrator/CP document title
45
tests/qtest/npcm7xx_rng-test: count runs properly
50
docs/system: Sort Arm board index into alphabetical order
51
docs/system: Document Arm Versatile Express boards
52
docs/system: Document the various MPS2 models
53
docs/system: Document Musca boards
54
linux-user/arm: BKPT should cause SIGTRAP, not be a syscall
55
linux-user/arm: Remove bogus SVC 0xf0002 handling
56
linux-user/arm: Handle invalid arm-specific syscalls correctly
57
linux-user/arm: Fix identification of syscall numbers
58
target/arm: Remove unused GEN_NEON_INTEGER_OP macro
59
target/arm: Allow user-mode code to write CPSR.E via MSR
60
linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32
61
46
62
Philippe Mathieu-Daudé (4):
47
Peter Maydell (2):
63
hw/arm/integratorcp: Replace hw_error() by qemu_log_mask()
48
hw/arm/nseries: Check return value from load_image_targphys()
64
hw/arm/pxa2xx: Replace hw_error() by qemu_log_mask()
49
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
65
hw/char/xilinx_uartlite: Replace hw_error() by qemu_log_mask()
66
hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask()
67
50
68
Richard Henderson (2):
51
Philippe Mathieu-Daudé (6):
69
target/arm: Use tcg_gen_gvec_mov for clear_vec_high
52
hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
70
target/arm: Use clear_vec_high more effectively
53
hw/arm/armsse: Correct expansion MPC interrupt lines
54
hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
55
hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
56
hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
57
hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
71
58
72
Thomas Huth (1):
59
Richard Henderson (1):
73
tests/acceptance: Add a test for the canon-a1100 machine
60
target/arm: Fix neon VTBL/VTBX for len > 1
74
61
75
docs/system/arm/integratorcp.rst | 4 +-
62
Xinhao Zhang (3):
76
docs/system/arm/mps2.rst | 29 +++
63
target/arm: add spaces around operator
77
docs/system/arm/musca.rst | 31 +++
64
target/arm: Don't use '#' flag of printf format
78
docs/system/arm/vexpress.rst | 60 ++++++
65
target/arm: add space before the open parenthesis '('
79
docs/system/target-arm.rst | 20 +-
80
include/hw/arm/fsl-imx25.h | 5 +
81
include/hw/arm/fsl-imx31.h | 4 +
82
include/hw/arm/fsl-imx6.h | 2 +-
83
include/hw/arm/fsl-imx6ul.h | 2 +-
84
include/hw/arm/fsl-imx7.h | 23 ++-
85
include/hw/misc/imx2_wdt.h | 33 ----
86
include/hw/watchdog/wdt_imx2.h | 90 +++++++++
87
target/arm/cpu.h | 2 +-
88
hw/arm/fsl-imx25.c | 10 +
89
hw/arm/fsl-imx31.c | 6 +
90
hw/arm/fsl-imx6.c | 9 +
91
hw/arm/fsl-imx6ul.c | 10 +
92
hw/arm/fsl-imx7.c | 35 ++++
93
hw/arm/integratorcp.c | 23 ++-
94
hw/arm/pxa2xx_gpio.c | 7 +-
95
hw/char/xilinx_uartlite.c | 5 +-
96
hw/display/pxa2xx_lcd.c | 8 +-
97
hw/dma/pxa2xx_dma.c | 14 +-
98
hw/gpio/pl061.c | 12 +-
99
hw/misc/imx2_wdt.c | 90 ---------
100
hw/timer/exynos4210_mct.c | 12 +-
101
hw/watchdog/wdt_imx2.c | 303 +++++++++++++++++++++++++++++
102
linux-user/arm/cpu_loop.c | 145 ++++++++------
103
linux-user/arm/signal.c | 15 +-
104
target/arm/translate-a64.c | 63 +++---
105
target/arm/translate.c | 23 ---
106
MAINTAINERS | 6 +
107
hw/arm/Kconfig | 5 +
108
hw/misc/Makefile.objs | 1 -
109
hw/watchdog/Kconfig | 3 +
110
hw/watchdog/Makefile.objs | 1 +
111
tests/acceptance/machine_arm_canona1100.py | 35 ++++
112
37 files changed, 854 insertions(+), 292 deletions(-)
113
create mode 100644 docs/system/arm/mps2.rst
114
create mode 100644 docs/system/arm/musca.rst
115
create mode 100644 docs/system/arm/vexpress.rst
116
delete mode 100644 include/hw/misc/imx2_wdt.h
117
create mode 100644 include/hw/watchdog/wdt_imx2.h
118
delete mode 100644 hw/misc/imx2_wdt.c
119
create mode 100644 hw/watchdog/wdt_imx2.c
120
create mode 100644 tests/acceptance/machine_arm_canona1100.py
121
66
67
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++
68
docs/system/target-arm.rst | 1 +
69
include/hw/misc/stm32f2xx_syscfg.h | 2 --
70
target/arm/helper.h | 2 +-
71
hw/arm/armsse.c | 3 +-
72
hw/arm/musicpal.c | 40 +++++++++++++++++----------
73
hw/arm/nseries.c | 26 ++++++++----------
74
hw/arm/stm32f205_soc.c | 1 -
75
hw/misc/stm32f2xx_syscfg.c | 2 --
76
hw/ssi/imx_spi.c | 2 +-
77
hw/ssi/xilinx_spi.c | 2 +-
78
target/arm/arch_dump.c | 8 +++---
79
target/arm/arm-semi.c | 8 +++---
80
target/arm/helper.c | 2 +-
81
target/arm/op_helper.c | 23 +++++++++-------
82
target/arm/translate-a64.c | 4 +--
83
target/arm/translate.c | 2 +-
84
tests/qtest/npcm7xx_rng-test.c | 2 +-
85
hw/arm/Kconfig | 3 +-
86
target/arm/translate-neon.c.inc | 56 ++++++++++++++------------------------
87
20 files changed, 123 insertions(+), 98 deletions(-)
88
create mode 100644 docs/system/arm/sbsa.rst
89
diff view generated by jsdifflib
Deleted patch
1
From: Thomas Huth <thuth@redhat.com>
2
1
3
The canon-a1100 machine can be used with the Barebox firmware. The
4
QEMU Advent Calendar 2018 features a pre-compiled image which we
5
can use for testing.
6
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
10
Tested-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
11
Signed-off-by: Thomas Huth <thuth@redhat.com>
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20200514190422.23645-1-f4bug@amsat.org
14
Message-Id: <20200129090420.13954-1-thuth@redhat.com>
15
[PMD: Rebased MAINTAINERS]
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
MAINTAINERS | 1 +
20
tests/acceptance/machine_arm_canona1100.py | 35 ++++++++++++++++++++++
21
2 files changed, 36 insertions(+)
22
create mode 100644 tests/acceptance/machine_arm_canona1100.py
23
24
diff --git a/MAINTAINERS b/MAINTAINERS
25
index XXXXXXX..XXXXXXX 100644
26
--- a/MAINTAINERS
27
+++ b/MAINTAINERS
28
@@ -XXX,XX +XXX,XX @@ S: Odd Fixes
29
F: include/hw/arm/digic.h
30
F: hw/*/digic*
31
F: include/hw/*/digic*
32
+F: tests/acceptance/machine_arm_canona1100.py
33
34
Goldfish RTC
35
M: Anup Patel <anup.patel@wdc.com>
36
diff --git a/tests/acceptance/machine_arm_canona1100.py b/tests/acceptance/machine_arm_canona1100.py
37
new file mode 100644
38
index XXXXXXX..XXXXXXX
39
--- /dev/null
40
+++ b/tests/acceptance/machine_arm_canona1100.py
41
@@ -XXX,XX +XXX,XX @@
42
+# Functional test that boots the canon-a1100 machine with firmware
43
+#
44
+# Copyright (c) 2020 Red Hat, Inc.
45
+#
46
+# Author:
47
+# Thomas Huth <thuth@redhat.com>
48
+#
49
+# This work is licensed under the terms of the GNU GPL, version 2 or
50
+# later. See the COPYING file in the top-level directory.
51
+
52
+from avocado_qemu import Test
53
+from avocado_qemu import wait_for_console_pattern
54
+from avocado.utils import archive
55
+
56
+class CanonA1100Machine(Test):
57
+ """Boots the barebox firmware and checks that the console is operational"""
58
+
59
+ timeout = 90
60
+
61
+ def test_arm_canona1100(self):
62
+ """
63
+ :avocado: tags=arch:arm
64
+ :avocado: tags=machine:canon-a1100
65
+ :avocado: tags=device:pflash_cfi02
66
+ """
67
+ tar_url = ('https://www.qemu-advent-calendar.org'
68
+ '/2018/download/day18.tar.xz')
69
+ tar_hash = '068b5fc4242b29381acee94713509f8a876e9db6'
70
+ file_path = self.fetch_asset(tar_url, asset_hash=tar_hash)
71
+ archive.extract(file_path, self.workdir)
72
+ self.vm.set_console()
73
+ self.vm.add_args('-bios',
74
+ self.workdir + '/day18/barebox.canon-a1100.bin')
75
+ self.vm.launch()
76
+ wait_for_console_pattern(self, 'running /env/bin/init')
77
--
78
2.20.1
79
80
diff view generated by jsdifflib
Deleted patch
1
Add 'Arm' to the Integrator/CP document title, for consistency with
2
the titling of the other documentation of Arm devboard models
3
(versatile, realview).
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20200507151819.28444-2-peter.maydell@linaro.org
10
---
11
docs/system/arm/integratorcp.rst | 4 ++--
12
1 file changed, 2 insertions(+), 2 deletions(-)
13
14
diff --git a/docs/system/arm/integratorcp.rst b/docs/system/arm/integratorcp.rst
15
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/integratorcp.rst
17
+++ b/docs/system/arm/integratorcp.rst
18
@@ -XXX,XX +XXX,XX @@
19
-Integrator/CP (``integratorcp``)
20
-================================
21
+Arm Integrator/CP (``integratorcp``)
22
+====================================
23
24
The Arm Integrator/CP board is emulated with the following devices:
25
26
--
27
2.20.1
28
29
diff view generated by jsdifflib
Deleted patch
1
Sort the board index into alphabetical order. (Note that we need to
2
sort alphabetically by the title text of each file, which isn't the
3
same ordering as sorting by the filename.)
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20200507151819.28444-3-peter.maydell@linaro.org
10
---
11
docs/system/target-arm.rst | 17 +++++++++++------
12
1 file changed, 11 insertions(+), 6 deletions(-)
13
14
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
15
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/target-arm.rst
17
+++ b/docs/system/target-arm.rst
18
@@ -XXX,XX +XXX,XX @@ Unfortunately many of the Arm boards QEMU supports are currently
19
undocumented; you can get a complete list by running
20
``qemu-system-aarch64 --machine help``.
21
22
+..
23
+ This table of contents should be kept sorted alphabetically
24
+ by the title text of each file, which isn't the same ordering
25
+ as an alphabetical sort by filename.
26
+
27
.. toctree::
28
:maxdepth: 1
29
30
arm/integratorcp
31
- arm/versatile
32
arm/realview
33
- arm/xscale
34
- arm/palm
35
- arm/nseries
36
- arm/stellaris
37
+ arm/versatile
38
arm/musicpal
39
- arm/sx1
40
+ arm/nseries
41
arm/orangepi
42
+ arm/palm
43
+ arm/xscale
44
+ arm/sx1
45
+ arm/stellaris
46
47
Arm CPU features
48
================
49
--
50
2.20.1
51
52
diff view generated by jsdifflib
Deleted patch
1
Provide a minimal documentation of the Versatile Express boards
2
(vexpress-a9, vexpress-a15).
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20200507151819.28444-4-peter.maydell@linaro.org
9
---
10
docs/system/arm/vexpress.rst | 60 ++++++++++++++++++++++++++++++++++++
11
docs/system/target-arm.rst | 1 +
12
MAINTAINERS | 1 +
13
3 files changed, 62 insertions(+)
14
create mode 100644 docs/system/arm/vexpress.rst
15
16
diff --git a/docs/system/arm/vexpress.rst b/docs/system/arm/vexpress.rst
17
new file mode 100644
18
index XXXXXXX..XXXXXXX
19
--- /dev/null
20
+++ b/docs/system/arm/vexpress.rst
21
@@ -XXX,XX +XXX,XX @@
22
+Arm Versatile Express boards (``vexpress-a9``, ``vexpress-a15``)
23
+================================================================
24
+
25
+QEMU models two variants of the Arm Versatile Express development
26
+board family:
27
+
28
+- ``vexpress-a9`` models the combination of the Versatile Express
29
+ motherboard and the CoreTile Express A9x4 daughterboard
30
+- ``vexpress-a15`` models the combination of the Versatile Express
31
+ motherboard and the CoreTile Express A15x2 daughterboard
32
+
33
+Note that as this hardware does not have PCI, IDE or SCSI,
34
+the only available storage option is emulated SD card.
35
+
36
+Implemented devices:
37
+
38
+- PL041 audio
39
+- PL181 SD controller
40
+- PL050 keyboard and mouse
41
+- PL011 UARTs
42
+- SP804 timers
43
+- I2C controller
44
+- PL031 RTC
45
+- PL111 LCD display controller
46
+- Flash memory
47
+- LAN9118 ethernet
48
+
49
+Unimplemented devices:
50
+
51
+- SP810 system control block
52
+- PCI-express
53
+- USB controller (Philips ISP1761)
54
+- Local DAP ROM
55
+- CoreSight interfaces
56
+- PL301 AXI interconnect
57
+- SCC
58
+- System counter
59
+- HDLCD controller (``vexpress-a15``)
60
+- SP805 watchdog
61
+- PL341 dynamic memory controller
62
+- DMA330 DMA controller
63
+- PL354 static memory controller
64
+- BP147 TrustZone Protection Controller
65
+- TrustZone Address Space Controller
66
+
67
+Other differences between the hardware and the QEMU model:
68
+
69
+- QEMU will default to creating one CPU unless you pass a different
70
+ ``-smp`` argument
71
+- QEMU allows the amount of RAM provided to be specified with the
72
+ ``-m`` argument
73
+- QEMU defaults to providing a CPU which does not provide either
74
+ TrustZone or the Virtualization Extensions: if you want these you
75
+ must enable them with ``-machine secure=on`` and ``-machine
76
+ virtualization=on``
77
+- QEMU provides 4 virtio-mmio virtio transports; these start at
78
+ address ``0x10013000`` for ``vexpress-a9`` and at ``0x1c130000`` for
79
+ ``vexpress-a15``, and have IRQs from 40 upwards. If a dtb is
80
+ provided on the command line then QEMU will edit it to include
81
+ suitable entries describing these transports for the guest.
82
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
83
index XXXXXXX..XXXXXXX 100644
84
--- a/docs/system/target-arm.rst
85
+++ b/docs/system/target-arm.rst
86
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
87
arm/integratorcp
88
arm/realview
89
arm/versatile
90
+ arm/vexpress
91
arm/musicpal
92
arm/nseries
93
arm/orangepi
94
diff --git a/MAINTAINERS b/MAINTAINERS
95
index XXXXXXX..XXXXXXX 100644
96
--- a/MAINTAINERS
97
+++ b/MAINTAINERS
98
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
99
L: qemu-arm@nongnu.org
100
S: Maintained
101
F: hw/arm/vexpress.c
102
+F: docs/system/arm/vexpress.rst
103
104
Versatile PB
105
M: Peter Maydell <peter.maydell@linaro.org>
106
--
107
2.20.1
108
109
diff view generated by jsdifflib
Deleted patch
1
Add basic documentation of the MPS2 board models.
2
1
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20200507151819.28444-5-peter.maydell@linaro.org
8
---
9
docs/system/arm/mps2.rst | 29 +++++++++++++++++++++++++++++
10
docs/system/target-arm.rst | 1 +
11
MAINTAINERS | 1 +
12
3 files changed, 31 insertions(+)
13
create mode 100644 docs/system/arm/mps2.rst
14
15
diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
16
new file mode 100644
17
index XXXXXXX..XXXXXXX
18
--- /dev/null
19
+++ b/docs/system/arm/mps2.rst
20
@@ -XXX,XX +XXX,XX @@
21
+Arm MPS2 boards (``mps2-an385``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
22
+================================================================================
23
+
24
+These board models all use Arm M-profile CPUs.
25
+
26
+The Arm MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
27
+FPGA but is otherwise the same as the 2). Since the CPU itself
28
+and most of the devices are in the FPGA, the details of the board
29
+as seen by the guest depend significantly on the FPGA image.
30
+
31
+QEMU models the following FPGA images:
32
+
33
+``mps2-an385``
34
+ Cortex-M3 as documented in ARM Application Note AN385
35
+``mps2-an511``
36
+ Cortex-M3 'DesignStart' as documented in AN511
37
+``mps2-an505``
38
+ Cortex-M33 as documented in ARM Application Note AN505
39
+``mps2-an521``
40
+ Dual Cortex-M33 as documented in Application Note AN521
41
+
42
+Differences between QEMU and real hardware:
43
+
44
+- AN385 remapping of low 16K of memory to either ZBT SSRAM1 or to
45
+ block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as
46
+ if zbt_boot_ctrl is always zero)
47
+- QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest
48
+ visible difference is that the LAN9118 doesn't support checksum
49
+ offloading
50
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
51
index XXXXXXX..XXXXXXX 100644
52
--- a/docs/system/target-arm.rst
53
+++ b/docs/system/target-arm.rst
54
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
55
:maxdepth: 1
56
57
arm/integratorcp
58
+ arm/mps2
59
arm/realview
60
arm/versatile
61
arm/vexpress
62
diff --git a/MAINTAINERS b/MAINTAINERS
63
index XXXXXXX..XXXXXXX 100644
64
--- a/MAINTAINERS
65
+++ b/MAINTAINERS
66
@@ -XXX,XX +XXX,XX @@ F: hw/misc/armsse-cpuid.c
67
F: include/hw/misc/armsse-cpuid.h
68
F: hw/misc/armsse-mhu.c
69
F: include/hw/misc/armsse-mhu.h
70
+F: docs/system/arm/mps2.rst
71
72
Musca
73
M: Peter Maydell <peter.maydell@linaro.org>
74
--
75
2.20.1
76
77
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
With this patch, the watchdog on i.MX31 emulations is fully operational.
3
commit 32bd322a0134 ("hw/timer/armv7m_systick: Rewrite to use ptimers")
4
changed armv7m_systick to build on ptimers. Make sure we have ptimers
5
in the build when building armv7m_systick.
4
6
7
Signed-off-by: Andrew Jones <drjones@redhat.com>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
9
Message-id: 20201104103343.30392-1-drjones@redhat.com
7
Message-id: 20200517162135.110364-5-linux@roeck-us.net
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
include/hw/arm/fsl-imx31.h | 4 ++++
12
hw/arm/Kconfig | 1 +
11
hw/arm/fsl-imx31.c | 6 ++++++
13
1 file changed, 1 insertion(+)
12
hw/arm/Kconfig | 1 +
13
3 files changed, 11 insertions(+)
14
14
15
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/fsl-imx31.h
18
+++ b/include/hw/arm/fsl-imx31.h
19
@@ -XXX,XX +XXX,XX @@
20
#include "hw/timer/imx_epit.h"
21
#include "hw/i2c/imx_i2c.h"
22
#include "hw/gpio/imx_gpio.h"
23
+#include "hw/watchdog/wdt_imx2.h"
24
#include "exec/memory.h"
25
#include "target/arm/cpu.h"
26
27
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX31State {
28
IMXEPITState epit[FSL_IMX31_NUM_EPITS];
29
IMXI2CState i2c[FSL_IMX31_NUM_I2CS];
30
IMXGPIOState gpio[FSL_IMX31_NUM_GPIOS];
31
+ IMX2WdtState wdt;
32
MemoryRegion secure_rom;
33
MemoryRegion rom;
34
MemoryRegion iram;
35
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX31State {
36
#define FSL_IMX31_GPIO1_SIZE 0x4000
37
#define FSL_IMX31_GPIO2_ADDR 0x53FD0000
38
#define FSL_IMX31_GPIO2_SIZE 0x4000
39
+#define FSL_IMX31_WDT_ADDR 0x53FDC000
40
+#define FSL_IMX31_WDT_SIZE 0x4000
41
#define FSL_IMX31_AVIC_ADDR 0x68000000
42
#define FSL_IMX31_AVIC_SIZE 0x100
43
#define FSL_IMX31_SDRAM0_ADDR 0x80000000
44
diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/arm/fsl-imx31.c
47
+++ b/hw/arm/fsl-imx31.c
48
@@ -XXX,XX +XXX,XX @@ static void fsl_imx31_init(Object *obj)
49
sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
50
TYPE_IMX_GPIO);
51
}
52
+
53
+ sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), TYPE_IMX2_WDT);
54
}
55
56
static void fsl_imx31_realize(DeviceState *dev, Error **errp)
57
@@ -XXX,XX +XXX,XX @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
58
gpio_table[i].irq));
59
}
60
61
+ /* Watchdog */
62
+ object_property_set_bool(OBJECT(&s->wdt), true, "realized", &error_abort);
63
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX31_WDT_ADDR);
64
+
65
/* On a real system, the first 16k is a `secure boot rom' */
66
memory_region_init_rom(&s->secure_rom, OBJECT(dev), "imx31.secure_rom",
67
FSL_IMX31_SECURE_ROM_SIZE, &err);
68
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
15
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
69
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/arm/Kconfig
17
--- a/hw/arm/Kconfig
71
+++ b/hw/arm/Kconfig
18
+++ b/hw/arm/Kconfig
72
@@ -XXX,XX +XXX,XX @@ config FSL_IMX31
19
@@ -XXX,XX +XXX,XX @@ config ZYNQ
73
select SERIAL
20
74
select IMX
21
config ARM_V7M
75
select IMX_I2C
22
bool
76
+ select WDT_IMX2
23
+ select PTIMER
77
select LAN9118
24
78
25
config ALLWINNER_A10
79
config FSL_IMX6
26
bool
80
--
27
--
81
2.20.1
28
2.20.1
82
29
83
30
diff view generated by jsdifflib
1
From: Amanieu d'Antras <amanieu@gmail.com>
1
From: AlexChen <alex.chen@huawei.com>
2
2
3
This fixes signal handlers running with the wrong endianness if the
3
We should use printf format specifier "%u" instead of "%d" for
4
interrupted code used SETEND to dynamically switch endianness.
4
argument of type "unsigned int".
5
5
6
Signed-off-by: Amanieu d'Antras <amanieu@gmail.com>
6
Reported-by: Euler Robot <euler.robot@huawei.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
8
Message-id: 20200511131117.2486486-1-amanieu@gmail.com
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 5FA280F5.8060902@huawei.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
linux-user/arm/signal.c | 8 +++++++-
12
hw/ssi/imx_spi.c | 2 +-
12
1 file changed, 7 insertions(+), 1 deletion(-)
13
hw/ssi/xilinx_spi.c | 2 +-
14
2 files changed, 2 insertions(+), 2 deletions(-)
13
15
14
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
16
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/linux-user/arm/signal.c
18
--- a/hw/ssi/imx_spi.c
17
+++ b/linux-user/arm/signal.c
19
+++ b/hw/ssi/imx_spi.c
18
@@ -XXX,XX +XXX,XX @@ setup_return(CPUARMState *env, struct target_sigaction *ka,
20
@@ -XXX,XX +XXX,XX @@ static const char *imx_spi_reg_name(uint32_t reg)
19
} else {
21
case ECSPI_MSGDATA:
20
cpsr &= ~CPSR_T;
22
return "ECSPI_MSGDATA";
23
default:
24
- sprintf(unknown, "%d ?", reg);
25
+ sprintf(unknown, "%u ?", reg);
26
return unknown;
21
}
27
}
22
+ if (env->cp15.sctlr_el[1] & SCTLR_E0E) {
23
+ cpsr |= CPSR_E;
24
+ } else {
25
+ cpsr &= ~CPSR_E;
26
+ }
27
28
if (ka->sa_flags & TARGET_SA_RESTORER) {
29
if (is_fdpic) {
30
@@ -XXX,XX +XXX,XX @@ setup_return(CPUARMState *env, struct target_sigaction *ka,
31
env->regs[13] = frame_addr;
32
env->regs[14] = retcode;
33
env->regs[15] = handler & (thumb ? ~1 : ~3);
34
- cpsr_write(env, cpsr, CPSR_IT | CPSR_T, CPSRWriteByInstr);
35
+ cpsr_write(env, cpsr, CPSR_IT | CPSR_T | CPSR_E, CPSRWriteByInstr);
36
+ arm_rebuild_hflags(env);
37
38
return 0;
39
}
28
}
29
diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/ssi/xilinx_spi.c
32
+++ b/hw/ssi/xilinx_spi.c
33
@@ -XXX,XX +XXX,XX @@ static void xlx_spi_update_irq(XilinxSPI *s)
34
irq chain unless things really changed. */
35
if (pending != s->irqline) {
36
s->irqline = pending;
37
- DB_PRINT("irq_change of state %d ISR:%x IER:%X\n",
38
+ DB_PRINT("irq_change of state %u ISR:%x IER:%X\n",
39
pending, s->regs[R_IPISR], s->regs[R_IPIER]);
40
qemu_set_irq(s->irq, pending);
41
}
40
--
42
--
41
2.20.1
43
2.20.1
42
44
43
45
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
2
2
3
With this commit, the watchdog on mcimx6ul-evk is fully operational,
3
Fix code style. Operator needs spaces both sides.
4
including pretimeout support.
5
4
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
8
Message-id: 20200517162135.110364-7-linux@roeck-us.net
7
Message-id: 20201103114529.638233-1-zhangxinhao1@huawei.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
hw/arm/fsl-imx6ul.c | 10 ++++++++++
11
target/arm/arch_dump.c | 8 ++++----
12
1 file changed, 10 insertions(+)
12
target/arm/arm-semi.c | 8 ++++----
13
target/arm/helper.c | 2 +-
14
3 files changed, 9 insertions(+), 9 deletions(-)
13
15
14
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
16
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/fsl-imx6ul.c
18
--- a/target/arm/arch_dump.c
17
+++ b/hw/arm/fsl-imx6ul.c
19
+++ b/target/arm/arch_dump.c
18
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
20
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
19
FSL_IMX6UL_WDOG2_ADDR,
21
20
FSL_IMX6UL_WDOG3_ADDR,
22
for (i = 0; i < 32; ++i) {
21
};
23
uint64_t *q = aa64_vfp_qreg(env, i);
22
+ static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
24
- note.vfp.vregs[2*i + 0] = cpu_to_dump64(s, q[0]);
23
+ FSL_IMX6UL_WDOG1_IRQ,
25
- note.vfp.vregs[2*i + 1] = cpu_to_dump64(s, q[1]);
24
+ FSL_IMX6UL_WDOG2_IRQ,
26
+ note.vfp.vregs[2 * i + 0] = cpu_to_dump64(s, q[0]);
25
+ FSL_IMX6UL_WDOG3_IRQ,
27
+ note.vfp.vregs[2 * i + 1] = cpu_to_dump64(s, q[1]);
26
+ };
27
28
+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
29
+ &error_abort);
30
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
31
&error_abort);
32
33
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
34
FSL_IMX6UL_WDOGn_ADDR[i]);
35
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
36
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
37
+ FSL_IMX6UL_WDOGn_IRQ[i]));
38
}
28
}
39
29
40
/*
30
if (s->dump_info.d_endian == ELFDATA2MSB) {
31
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
32
*/
33
for (i = 0; i < 32; ++i) {
34
uint64_t tmp = note.vfp.vregs[2*i];
35
- note.vfp.vregs[2*i] = note.vfp.vregs[2*i+1];
36
- note.vfp.vregs[2*i+1] = tmp;
37
+ note.vfp.vregs[2 * i] = note.vfp.vregs[2 * i + 1];
38
+ note.vfp.vregs[2 * i + 1] = tmp;
39
}
40
}
41
42
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/arm-semi.c
45
+++ b/target/arm/arm-semi.c
46
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
47
if (use_gdb_syscalls()) {
48
arm_semi_open_guestfd = guestfd;
49
ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0,
50
- (int)arg2+1, gdb_open_modeflags[arg1]);
51
+ (int)arg2 + 1, gdb_open_modeflags[arg1]);
52
} else {
53
ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644));
54
if (ret == (uint32_t)-1) {
55
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
56
GET_ARG(1);
57
if (use_gdb_syscalls()) {
58
ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s",
59
- arg0, (int)arg1+1);
60
+ arg0, (int)arg1 + 1);
61
} else {
62
s = lock_user_string(arg0);
63
if (!s) {
64
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
65
GET_ARG(3);
66
if (use_gdb_syscalls()) {
67
return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s",
68
- arg0, (int)arg1+1, arg2, (int)arg3+1);
69
+ arg0, (int)arg1 + 1, arg2, (int)arg3 + 1);
70
} else {
71
char *s2;
72
s = lock_user_string(arg0);
73
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
74
GET_ARG(1);
75
if (use_gdb_syscalls()) {
76
return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s",
77
- arg0, (int)arg1+1);
78
+ arg0, (int)arg1 + 1);
79
} else {
80
s = lock_user_string(arg0);
81
if (!s) {
82
diff --git a/target/arm/helper.c b/target/arm/helper.c
83
index XXXXXXX..XXXXXXX 100644
84
--- a/target/arm/helper.c
85
+++ b/target/arm/helper.c
86
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
87
uint32_t sum;
88
sum = do_usad(a, b);
89
sum += do_usad(a >> 8, b >> 8);
90
- sum += do_usad(a >> 16, b >>16);
91
+ sum += do_usad(a >> 16, b >> 16);
92
sum += do_usad(a >> 24, b >> 24);
93
return sum;
94
}
41
--
95
--
42
2.20.1
96
2.20.1
43
97
44
98
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
2
2
3
Do not explicitly store zero to the NEON high part
3
Fix code style. Don't use '#' flag of printf format ('%#') in
4
when we can pass !is_q to clear_vec_high.
4
format strings, use '0x' prefix instead
5
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Kai Deng <dengkai1@huawei.com>
8
Message-id: 20200519212453.28494-3-richard.henderson@linaro.org
8
Message-id: 20201103114529.638233-2-zhangxinhao1@huawei.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
target/arm/translate-a64.c | 53 +++++++++++++++++++++++---------------
12
target/arm/translate-a64.c | 4 ++--
12
1 file changed, 32 insertions(+), 21 deletions(-)
13
1 file changed, 2 insertions(+), 2 deletions(-)
13
14
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
17
--- a/target/arm/translate-a64.c
17
+++ b/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
19
{
20
gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
20
/* This always zero-extends and writes to a full 128 bit wide vector */
21
break;
21
TCGv_i64 tmplo = tcg_temp_new_i64();
22
default:
22
- TCGv_i64 tmphi;
23
- fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
23
+ TCGv_i64 tmphi = NULL;
24
+ fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n",
24
25
__func__, insn, fpopcode, s->pc_curr);
25
if (size < 4) {
26
g_assert_not_reached();
26
MemOp memop = s->be_data + size;
27
}
27
- tmphi = tcg_const_i64(0);
28
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
28
tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop);
29
case 0x7f: /* FSQRT (vector) */
29
} else {
30
break;
30
bool be = s->be_data == MO_BE;
31
default:
31
@@ -XXX,XX +XXX,XX @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
32
- fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
33
+ fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop);
34
g_assert_not_reached();
32
}
35
}
33
36
34
tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64));
35
- tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx));
36
-
37
tcg_temp_free_i64(tmplo);
38
- tcg_temp_free_i64(tmphi);
39
40
- clear_vec_high(s, true, destidx);
41
+ if (tmphi) {
42
+ tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx));
43
+ tcg_temp_free_i64(tmphi);
44
+ }
45
+ clear_vec_high(s, tmphi != NULL, destidx);
46
}
47
48
/*
49
@@ -XXX,XX +XXX,XX @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
50
read_vec_element(s, tcg_resh, rm, 0, MO_64);
51
do_ext64(s, tcg_resh, tcg_resl, pos);
52
}
53
- tcg_gen_movi_i64(tcg_resh, 0);
54
} else {
55
TCGv_i64 tcg_hh;
56
typedef struct {
57
@@ -XXX,XX +XXX,XX @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
58
59
write_vec_element(s, tcg_resl, rd, 0, MO_64);
60
tcg_temp_free_i64(tcg_resl);
61
- write_vec_element(s, tcg_resh, rd, 1, MO_64);
62
+ if (is_q) {
63
+ write_vec_element(s, tcg_resh, rd, 1, MO_64);
64
+ }
65
tcg_temp_free_i64(tcg_resh);
66
- clear_vec_high(s, true, rd);
67
+ clear_vec_high(s, is_q, rd);
68
}
69
70
/* TBL/TBX
71
@@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
72
* the input.
73
*/
74
tcg_resl = tcg_temp_new_i64();
75
- tcg_resh = tcg_temp_new_i64();
76
+ tcg_resh = NULL;
77
78
if (is_tblx) {
79
read_vec_element(s, tcg_resl, rd, 0, MO_64);
80
} else {
81
tcg_gen_movi_i64(tcg_resl, 0);
82
}
83
- if (is_tblx && is_q) {
84
- read_vec_element(s, tcg_resh, rd, 1, MO_64);
85
- } else {
86
- tcg_gen_movi_i64(tcg_resh, 0);
87
+
88
+ if (is_q) {
89
+ tcg_resh = tcg_temp_new_i64();
90
+ if (is_tblx) {
91
+ read_vec_element(s, tcg_resh, rd, 1, MO_64);
92
+ } else {
93
+ tcg_gen_movi_i64(tcg_resh, 0);
94
+ }
95
}
96
97
tcg_idx = tcg_temp_new_i64();
98
@@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
99
100
write_vec_element(s, tcg_resl, rd, 0, MO_64);
101
tcg_temp_free_i64(tcg_resl);
102
- write_vec_element(s, tcg_resh, rd, 1, MO_64);
103
- tcg_temp_free_i64(tcg_resh);
104
- clear_vec_high(s, true, rd);
105
+
106
+ if (is_q) {
107
+ write_vec_element(s, tcg_resh, rd, 1, MO_64);
108
+ tcg_temp_free_i64(tcg_resh);
109
+ }
110
+ clear_vec_high(s, is_q, rd);
111
}
112
113
/* ZIP/UZP/TRN
114
@@ -XXX,XX +XXX,XX @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
115
}
116
117
tcg_resl = tcg_const_i64(0);
118
- tcg_resh = tcg_const_i64(0);
119
+ tcg_resh = is_q ? tcg_const_i64(0) : NULL;
120
tcg_res = tcg_temp_new_i64();
121
122
for (i = 0; i < elements; i++) {
123
@@ -XXX,XX +XXX,XX @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
124
125
write_vec_element(s, tcg_resl, rd, 0, MO_64);
126
tcg_temp_free_i64(tcg_resl);
127
- write_vec_element(s, tcg_resh, rd, 1, MO_64);
128
- tcg_temp_free_i64(tcg_resh);
129
- clear_vec_high(s, true, rd);
130
+
131
+ if (is_q) {
132
+ write_vec_element(s, tcg_resh, rd, 1, MO_64);
133
+ tcg_temp_free_i64(tcg_resh);
134
+ }
135
+ clear_vec_high(s, is_q, rd);
136
}
137
138
/*
139
--
37
--
140
2.20.1
38
2.20.1
141
39
142
40
diff view generated by jsdifflib
1
The GEN_NEON_INTEGER_OP macro is no longer used; remove it.
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
2
2
3
Fix code style. Space required before the open parenthesis '('.
4
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
7
Message-id: 20201103114529.638233-3-zhangxinhao1@huawei.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
---
10
---
6
target/arm/translate.c | 23 -----------------------
11
target/arm/translate.c | 2 +-
7
1 file changed, 23 deletions(-)
12
1 file changed, 1 insertion(+), 1 deletion(-)
8
13
9
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
10
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
11
--- a/target/arm/translate.c
16
--- a/target/arm/translate.c
12
+++ b/target/arm/translate.c
17
+++ b/target/arm/translate.c
13
@@ -XXX,XX +XXX,XX @@ static inline void gen_neon_rsb(int size, TCGv_i32 t0, TCGv_i32 t1)
18
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
14
default: return 1; \
19
- Hardware watchpoints.
15
}} while (0)
20
Hardware breakpoints have already been handled and skip this code.
16
21
*/
17
-#define GEN_NEON_INTEGER_OP(name) do { \
22
- switch(dc->base.is_jmp) {
18
- switch ((size << 1) | u) { \
23
+ switch (dc->base.is_jmp) {
19
- case 0: \
24
case DISAS_NEXT:
20
- gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
25
case DISAS_TOO_MANY:
21
- break; \
26
gen_goto_tb(dc, 1, dc->base.pc_next);
22
- case 1: \
23
- gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
24
- break; \
25
- case 2: \
26
- gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
27
- break; \
28
- case 3: \
29
- gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
30
- break; \
31
- case 4: \
32
- gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
33
- break; \
34
- case 5: \
35
- gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
36
- break; \
37
- default: return 1; \
38
- }} while (0)
39
-
40
static TCGv_i32 neon_load_scratch(int scratch)
41
{
42
TCGv_i32 tmp = tcg_temp_new_i32();
43
--
27
--
44
2.20.1
28
2.20.1
45
29
46
30
diff view generated by jsdifflib
1
Provide a minimal documentation of the Musca boards.
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
We should at least document what this machine is about.
4
5
Reviewed-by: Graeme Gregory <graeme@nuviainc.com>
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20201104165254.24822-1-alex.bennee@linaro.org
8
Cc: Leif Lindholm <leif@nuviainc.com>
9
Cc: Shashi Mallela <shashi.mallela@linaro.org>
10
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
11
[PMM: fixed filename mismatch]
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20200507151819.28444-6-peter.maydell@linaro.org
8
---
13
---
9
docs/system/arm/musca.rst | 31 +++++++++++++++++++++++++++++++
14
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++++++++++++
10
docs/system/target-arm.rst | 1 +
15
docs/system/target-arm.rst | 1 +
11
MAINTAINERS | 1 +
16
2 files changed, 33 insertions(+)
12
3 files changed, 33 insertions(+)
17
create mode 100644 docs/system/arm/sbsa.rst
13
create mode 100644 docs/system/arm/musca.rst
14
18
15
diff --git a/docs/system/arm/musca.rst b/docs/system/arm/musca.rst
19
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
16
new file mode 100644
20
new file mode 100644
17
index XXXXXXX..XXXXXXX
21
index XXXXXXX..XXXXXXX
18
--- /dev/null
22
--- /dev/null
19
+++ b/docs/system/arm/musca.rst
23
+++ b/docs/system/arm/sbsa.rst
20
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@
21
+Arm Musca boards (``musca-a``, ``musca-b1``)
25
+Arm Server Base System Architecture Reference board (``sbsa-ref``)
22
+============================================
26
+==================================================================
23
+
27
+
24
+The Arm Musca development boards are a reference implementation
28
+While the `virt` board is a generic board platform that doesn't match
25
+of a system using the SSE-200 Subsystem for Embedded. They are
29
+any real hardware the `sbsa-ref` board intends to look like real
26
+dual Cortex-M33 systems.
30
+hardware. The `Server Base System Architecture
31
+<https://developer.arm.com/documentation/den0029/latest>` defines a
32
+minimum base line of hardware support and importantly how the firmware
33
+reports that to any operating system. It is a static system that
34
+reports a very minimal DT to the firmware for non-discoverable
35
+information about components affected by the qemu command line (i.e.
36
+cpus and memory). As a result it must have a firmware specifically
37
+built to expect a certain hardware layout (as you would in a real
38
+machine).
27
+
39
+
28
+QEMU provides models of the A and B1 variants of this board.
40
+It is intended to be a machine for developing firmware and testing
41
+standards compliance with operating systems.
29
+
42
+
30
+Unimplemented devices:
43
+Supported devices
44
+"""""""""""""""""
31
+
45
+
32
+- SPI
46
+The sbsa-ref board supports:
33
+- |I2C|
34
+- |I2S|
35
+- PWM
36
+- QSPI
37
+- Timer
38
+- SCC
39
+- GPIO
40
+- eFlash
41
+- MHU
42
+- PVT
43
+- SDIO
44
+- CryptoCell
45
+
47
+
46
+Note that (like the real hardware) the Musca-A machine is
48
+ - A configurable number of AArch64 CPUs
47
+asymmetric: CPU 0 does not have the FPU or DSP extensions,
49
+ - GIC version 3
48
+but CPU 1 does. Also like the real hardware, the memory maps
50
+ - System bus AHCI controller
49
+for the A and B1 variants differ significantly, so guest
51
+ - System bus EHCI controller
50
+software must be built for the right variant.
52
+ - CDROM and hard disc on AHCI bus
53
+ - E1000E ethernet card on PCIe bus
54
+ - VGA display adaptor on PCIe bus
55
+ - A generic SBSA watchdog device
51
+
56
+
52
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
57
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
53
index XXXXXXX..XXXXXXX 100644
58
index XXXXXXX..XXXXXXX 100644
54
--- a/docs/system/target-arm.rst
59
--- a/docs/system/target-arm.rst
55
+++ b/docs/system/target-arm.rst
60
+++ b/docs/system/target-arm.rst
56
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
61
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
57
58
arm/integratorcp
59
arm/mps2
62
arm/mps2
60
+ arm/musca
63
arm/musca
61
arm/realview
64
arm/realview
65
+ arm/sbsa
62
arm/versatile
66
arm/versatile
63
arm/vexpress
67
arm/vexpress
64
diff --git a/MAINTAINERS b/MAINTAINERS
68
arm/aspeed
65
index XXXXXXX..XXXXXXX 100644
66
--- a/MAINTAINERS
67
+++ b/MAINTAINERS
68
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
69
L: qemu-arm@nongnu.org
70
S: Maintained
71
F: hw/arm/musca.c
72
+F: docs/system/arm/musca.rst
73
74
Musicpal
75
M: Jan Kiszka <jan.kiszka@web.de>
76
--
69
--
77
2.20.1
70
2.20.1
78
71
79
72
diff view generated by jsdifflib
Deleted patch
1
In linux-user/arm/cpu-loop.c we incorrectly treat EXCP_BKPT similarly
2
to EXCP_SWI, which means that if the guest executes a BKPT insn then
3
QEMU will perform a syscall for it (which syscall depends on what
4
value happens to be in r7...). The correct behaviour is that the
5
guest process should take a SIGTRAP.
6
1
7
This code has been like this (more or less) since commit
8
06c949e62a098f in 2006 which added BKPT in the first place. This is
9
probably because at the time the same code path was used to handle
10
both Linux syscalls and semihosting calls, and (on M profile) BKPT
11
with a suitable magic number is used for semihosting calls. But
12
these days we've moved handling of semihosting out to an entirely
13
different codepath, so we can fix this bug by simply removing this
14
handling of EXCP_BKPT and instead making it deliver a SIGTRAP like
15
EXCP_DEBUG (as we do already on aarch64).
16
17
Reported-by: <omerg681@gmail.com>
18
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
19
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Message-id: 20200420212206.12776-2-peter.maydell@linaro.org
22
Fixes: https://bugs.launchpad.net/qemu/+bug/1873898
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
---
25
linux-user/arm/cpu_loop.c | 30 ++++++++----------------------
26
1 file changed, 8 insertions(+), 22 deletions(-)
27
28
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/linux-user/arm/cpu_loop.c
31
+++ b/linux-user/arm/cpu_loop.c
32
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
33
}
34
break;
35
case EXCP_SWI:
36
- case EXCP_BKPT:
37
{
38
env->eabi = 1;
39
/* system call */
40
- if (trapnr == EXCP_BKPT) {
41
- if (env->thumb) {
42
- /* FIXME - what to do if get_user() fails? */
43
- get_user_code_u16(insn, env->regs[15], env);
44
- n = insn & 0xff;
45
- env->regs[15] += 2;
46
- } else {
47
- /* FIXME - what to do if get_user() fails? */
48
- get_user_code_u32(insn, env->regs[15], env);
49
- n = (insn & 0xf) | ((insn >> 4) & 0xff0);
50
- env->regs[15] += 4;
51
- }
52
+ if (env->thumb) {
53
+ /* FIXME - what to do if get_user() fails? */
54
+ get_user_code_u16(insn, env->regs[15] - 2, env);
55
+ n = insn & 0xff;
56
} else {
57
- if (env->thumb) {
58
- /* FIXME - what to do if get_user() fails? */
59
- get_user_code_u16(insn, env->regs[15] - 2, env);
60
- n = insn & 0xff;
61
- } else {
62
- /* FIXME - what to do if get_user() fails? */
63
- get_user_code_u32(insn, env->regs[15] - 4, env);
64
- n = insn & 0xffffff;
65
- }
66
+ /* FIXME - what to do if get_user() fails? */
67
+ get_user_code_u32(insn, env->regs[15] - 4, env);
68
+ n = insn & 0xffffff;
69
}
70
71
if (n == ARM_NR_cacheflush) {
72
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
73
}
74
break;
75
case EXCP_DEBUG:
76
+ case EXCP_BKPT:
77
excp_debug:
78
info.si_signo = TARGET_SIGTRAP;
79
info.si_errno = 0;
80
--
81
2.20.1
82
83
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
With this commit, the watchdog on imx25-pdk is fully operational,
3
When using a Cortex-A15, the Virt machine does not use any
4
including pretimeout support.
4
MPCore peripherals. Remove the dependency.
5
5
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Fixes: 7951c7b7c05 ("hw/arm: Express dependencies of the virt machine with Kconfig")
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
7
Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
8
Message-id: 20200517162135.110364-4-linux@roeck-us.net
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20201107114852.271922-1-philmd@redhat.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
include/hw/arm/fsl-imx25.h | 5 +++++
13
hw/arm/Kconfig | 1 -
12
hw/arm/fsl-imx25.c | 10 ++++++++++
14
1 file changed, 1 deletion(-)
13
hw/arm/Kconfig | 1 +
14
3 files changed, 16 insertions(+)
15
15
16
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/fsl-imx25.h
19
+++ b/include/hw/arm/fsl-imx25.h
20
@@ -XXX,XX +XXX,XX @@
21
#include "hw/gpio/imx_gpio.h"
22
#include "hw/sd/sdhci.h"
23
#include "hw/usb/chipidea.h"
24
+#include "hw/watchdog/wdt_imx2.h"
25
#include "exec/memory.h"
26
#include "target/arm/cpu.h"
27
28
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
29
IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
30
SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
31
ChipideaState usb[FSL_IMX25_NUM_USBS];
32
+ IMX2WdtState wdt;
33
MemoryRegion rom[2];
34
MemoryRegion iram;
35
MemoryRegion iram_alias;
36
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
37
#define FSL_IMX25_GPIO1_SIZE 0x4000
38
#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
39
#define FSL_IMX25_GPIO2_SIZE 0x4000
40
+#define FSL_IMX25_WDT_ADDR 0x53FDC000
41
+#define FSL_IMX25_WDT_SIZE 0x4000
42
#define FSL_IMX25_USB1_ADDR 0x53FF4000
43
#define FSL_IMX25_USB1_SIZE 0x0200
44
#define FSL_IMX25_USB2_ADDR 0x53FF4400
45
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
46
#define FSL_IMX25_ESDHC2_IRQ 8
47
#define FSL_IMX25_USB1_IRQ 37
48
#define FSL_IMX25_USB2_IRQ 35
49
+#define FSL_IMX25_WDT_IRQ 55
50
51
#endif /* FSL_IMX25_H */
52
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/arm/fsl-imx25.c
55
+++ b/hw/arm/fsl-imx25.c
56
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
57
TYPE_CHIPIDEA);
58
}
59
60
+ sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), TYPE_IMX2_WDT);
61
}
62
63
static void fsl_imx25_realize(DeviceState *dev, Error **errp)
64
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
65
usb_table[i].irq));
66
}
67
68
+ /* Watchdog */
69
+ object_property_set_bool(OBJECT(&s->wdt), true, "pretimeout-support",
70
+ &error_abort);
71
+ object_property_set_bool(OBJECT(&s->wdt), true, "realized", &error_abort);
72
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX25_WDT_ADDR);
73
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt), 0,
74
+ qdev_get_gpio_in(DEVICE(&s->avic),
75
+ FSL_IMX25_WDT_IRQ));
76
+
77
/* initialize 2 x 16 KB ROM */
78
memory_region_init_rom(&s->rom[0], OBJECT(dev), "imx25.rom0",
79
FSL_IMX25_ROM0_SIZE, &err);
80
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
16
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
81
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
82
--- a/hw/arm/Kconfig
18
--- a/hw/arm/Kconfig
83
+++ b/hw/arm/Kconfig
19
+++ b/hw/arm/Kconfig
84
@@ -XXX,XX +XXX,XX @@ config FSL_IMX25
20
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
85
select IMX
21
imply VFIO_PLATFORM
86
select IMX_FEC
22
imply VFIO_XGMAC
87
select IMX_I2C
23
imply TPM_TIS_SYSBUS
88
+ select WDT_IMX2
24
- select A15MPCORE
89
select DS1338
25
select ACPI
90
26
select ARM_SMMUV3
91
config FSL_IMX31
27
select GPIO_KEY
92
--
28
--
93
2.20.1
29
2.20.1
94
30
95
31
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The 8-byte store for the end a !is_q operation can be
3
The helper function did not get updated when we reorganized
4
merged with the other stores. Use a no-op vector move
4
the vector register file for SVE. Since then, the neon dregs
5
to trigger the expand_clr portion of tcg_gen_gvec_mov.
5
are non-sequential and cannot be simply indexed.
6
6
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
At the same time, make the helper function operate on 64-bit
8
quantities so that we do not have to call it twice.
9
10
Fixes: c39c2b9043e
11
Reported-by: Ard Biesheuvel <ardb@kernel.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200519212453.28494-2-richard.henderson@linaro.org
13
[PMM: use aa32_vfp_dreg() rather than opencoding]
14
Message-id: 20201105171126.88014-1-richard.henderson@linaro.org
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
17
---
12
target/arm/translate-a64.c | 10 ++--------
18
target/arm/helper.h | 2 +-
13
1 file changed, 2 insertions(+), 8 deletions(-)
19
target/arm/op_helper.c | 23 +++++++++--------
20
target/arm/translate-neon.c.inc | 44 +++++++++++----------------------
21
3 files changed, 29 insertions(+), 40 deletions(-)
14
22
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
23
diff --git a/target/arm/helper.h b/target/arm/helper.h
16
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
25
--- a/target/arm/helper.h
18
+++ b/target/arm/translate-a64.c
26
+++ b/target/arm/helper.h
19
@@ -XXX,XX +XXX,XX @@ static void clear_vec_high(DisasContext *s, bool is_q, int rd)
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
20
unsigned ofs = fp_reg_offset(s, rd, MO_64);
28
DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
21
unsigned vsz = vec_full_reg_size(s);
29
DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32)
22
30
DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32)
23
- if (!is_q) {
31
-DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32)
24
- TCGv_i64 tcg_zero = tcg_const_i64(0);
32
+DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64)
25
- tcg_gen_st_i64(tcg_zero, cpu_env, ofs + 8);
33
26
- tcg_temp_free_i64(tcg_zero);
34
DEF_HELPER_3(shl_cc, i32, env, i32, i32)
35
DEF_HELPER_3(shr_cc, i32, env, i32, i32)
36
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/op_helper.c
39
+++ b/target/arm/op_helper.c
40
@@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
41
cpu_loop_exit_restore(cs, ra);
42
}
43
44
-uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,
45
- uint32_t maxindex)
46
+uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc,
47
+ uint64_t ireg, uint64_t def)
48
{
49
- uint32_t val, shift;
50
- uint64_t *table = vn;
51
+ uint64_t tmp, val = 0;
52
+ uint32_t maxindex = ((desc & 3) + 1) * 8;
53
+ uint32_t base_reg = desc >> 2;
54
+ uint32_t shift, index, reg;
55
56
- val = 0;
57
- for (shift = 0; shift < 32; shift += 8) {
58
- uint32_t index = (ireg >> shift) & 0xff;
59
+ for (shift = 0; shift < 64; shift += 8) {
60
+ index = (ireg >> shift) & 0xff;
61
if (index < maxindex) {
62
- uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
63
- val |= tmp << shift;
64
+ reg = base_reg + (index >> 3);
65
+ tmp = *aa32_vfp_dreg(env, reg);
66
+ tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift;
67
} else {
68
- val |= def & (0xff << shift);
69
+ tmp = def & (0xffull << shift);
70
}
71
+ val |= tmp;
72
}
73
return val;
74
}
75
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/translate-neon.c.inc
78
+++ b/target/arm/translate-neon.c.inc
79
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
80
81
static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
82
{
83
- int n;
84
- TCGv_i32 tmp, tmp2, tmp3, tmp4;
85
- TCGv_ptr ptr1;
86
+ TCGv_i64 val, def;
87
+ TCGv_i32 desc;
88
89
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
90
return false;
91
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
92
return true;
93
}
94
95
- n = a->len + 1;
96
- if ((a->vn + n) > 32) {
97
+ if ((a->vn + a->len + 1) > 32) {
98
/*
99
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
100
* helper function running off the end of the register file.
101
*/
102
return false;
103
}
104
- n <<= 3;
105
- tmp = tcg_temp_new_i32();
106
- if (a->op) {
107
- read_neon_element32(tmp, a->vd, 0, MO_32);
108
- } else {
109
- tcg_gen_movi_i32(tmp, 0);
27
- }
110
- }
28
- if (vsz > 16) {
111
- tmp2 = tcg_temp_new_i32();
29
- tcg_gen_gvec_dup_imm(MO_64, ofs + 16, vsz - 16, vsz - 16, 0);
112
- read_neon_element32(tmp2, a->vm, 0, MO_32);
30
- }
113
- ptr1 = vfp_reg_ptr(true, a->vn);
31
+ /* Nop move, with side effect of clearing the tail. */
114
- tmp4 = tcg_const_i32(n);
32
+ tcg_gen_gvec_mov(MO_64, ofs, ofs, is_q ? 16 : 8, vsz);
115
- gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);
116
117
+ desc = tcg_const_i32((a->vn << 2) | a->len);
118
+ def = tcg_temp_new_i64();
119
if (a->op) {
120
- read_neon_element32(tmp, a->vd, 1, MO_32);
121
+ read_neon_element64(def, a->vd, 0, MO_64);
122
} else {
123
- tcg_gen_movi_i32(tmp, 0);
124
+ tcg_gen_movi_i64(def, 0);
125
}
126
- tmp3 = tcg_temp_new_i32();
127
- read_neon_element32(tmp3, a->vm, 1, MO_32);
128
- gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);
129
- tcg_temp_free_i32(tmp);
130
- tcg_temp_free_i32(tmp4);
131
- tcg_temp_free_ptr(ptr1);
132
+ val = tcg_temp_new_i64();
133
+ read_neon_element64(val, a->vm, 0, MO_64);
134
135
- write_neon_element32(tmp2, a->vd, 0, MO_32);
136
- write_neon_element32(tmp3, a->vd, 1, MO_32);
137
- tcg_temp_free_i32(tmp2);
138
- tcg_temp_free_i32(tmp3);
139
+ gen_helper_neon_tbl(val, cpu_env, desc, val, def);
140
+ write_neon_element64(val, a->vd, 0, MO_64);
141
+
142
+ tcg_temp_free_i64(def);
143
+ tcg_temp_free_i64(val);
144
+ tcg_temp_free_i32(desc);
145
return true;
33
}
146
}
34
147
35
void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
36
--
148
--
37
2.20.1
149
2.20.1
38
150
39
151
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
hw_error() calls exit(). This a bit overkill when we can log
3
We can use one MPC per SRAM bank, but we currently only wire the
4
the accesses as unimplemented or guest error.
4
IRQ from the first expansion MPC to the IRQ splitter. Fix that.
5
5
6
When fuzzing the devices, we don't want the whole process to
6
Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines")
7
exit. Replace some hw_error() calls by qemu_log_mask().
8
9
Per the datasheet "Exynos 4412 RISC Microprocessor Rev 1.00"
10
Chapter 25 "Multi Core Timer (MCT)" figure 1 and table 4,
11
the default value on the APB bus is 0.
12
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20201107193403.436146-2-f4bug@amsat.org
15
Message-id: 20200518140309.5220-5-f4bug@amsat.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
11
---
18
hw/timer/exynos4210_mct.c | 12 +++++-------
12
hw/arm/armsse.c | 3 ++-
19
1 file changed, 5 insertions(+), 7 deletions(-)
13
1 file changed, 2 insertions(+), 1 deletion(-)
20
14
21
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
15
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
22
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/timer/exynos4210_mct.c
17
--- a/hw/arm/armsse.c
24
+++ b/hw/timer/exynos4210_mct.c
18
+++ b/hw/arm/armsse.c
25
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
26
20
qdev_get_gpio_in(dev_splitter, 0));
27
#include "qemu/osdep.h"
21
qdev_connect_gpio_out(dev_splitter, 0,
28
#include "qemu/log.h"
22
qdev_get_gpio_in_named(dev_secctl,
29
-#include "hw/hw.h"
23
- "mpc_status", 0));
30
#include "hw/sysbus.h"
24
+ "mpc_status",
31
#include "migration/vmstate.h"
25
+ i - IOTS_NUM_EXP_MPC));
32
#include "qemu/timer.h"
26
}
33
@@ -XXX,XX +XXX,XX @@
27
34
#include "hw/ptimer.h"
28
qdev_connect_gpio_out(dev_splitter, 1,
35
36
#include "hw/arm/exynos4210.h"
37
-#include "hw/hw.h"
38
#include "hw/irq.h"
39
40
//#define DEBUG_MCT
41
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
42
int index;
43
int shift;
44
uint64_t count;
45
- uint32_t value;
46
+ uint32_t value = 0;
47
int lt_i;
48
49
switch (offset) {
50
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
51
break;
52
53
default:
54
- hw_error("exynos4210.mct: bad read offset "
55
- TARGET_FMT_plx "\n", offset);
56
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
57
+ __func__, offset);
58
break;
59
}
60
return value;
61
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
62
break;
63
64
default:
65
- hw_error("exynos4210.mct: bad write offset "
66
- TARGET_FMT_plx "\n", offset);
67
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
68
+ __func__, offset);
69
break;
70
}
71
}
72
--
29
--
73
2.20.1
30
2.20.1
74
31
75
32
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
hw_error() calls exit(). This a bit overkill when we can log
3
The system configuration controller (SYSCFG) doesn't have
4
the accesses as unimplemented or guest error.
4
any output IRQ (and the INTC input #71 belongs to the UART6).
5
Remove the invalid code.
5
6
6
When fuzzing the devices, we don't want the whole process to
7
Fixes: db635521a02 ("stm32f205: Add the stm32f205 SoC")
7
exit. Replace some hw_error() calls by qemu_log_mask().
8
9
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20201107193403.436146-3-f4bug@amsat.org
12
Message-id: 20200518140309.5220-4-f4bug@amsat.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
12
---
15
hw/char/xilinx_uartlite.c | 5 +++--
13
include/hw/misc/stm32f2xx_syscfg.h | 2 --
16
1 file changed, 3 insertions(+), 2 deletions(-)
14
hw/arm/stm32f205_soc.c | 1 -
15
hw/misc/stm32f2xx_syscfg.c | 2 --
16
3 files changed, 5 deletions(-)
17
17
18
diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c
18
diff --git a/include/hw/misc/stm32f2xx_syscfg.h b/include/hw/misc/stm32f2xx_syscfg.h
19
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/char/xilinx_uartlite.c
20
--- a/include/hw/misc/stm32f2xx_syscfg.h
21
+++ b/hw/char/xilinx_uartlite.c
21
+++ b/include/hw/misc/stm32f2xx_syscfg.h
22
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ struct STM32F2XXSyscfgState {
23
*/
23
uint32_t syscfg_exticr3;
24
24
uint32_t syscfg_exticr4;
25
#include "qemu/osdep.h"
25
uint32_t syscfg_cmpcr;
26
-#include "hw/hw.h"
26
-
27
+#include "qemu/log.h"
27
- qemu_irq irq;
28
#include "hw/irq.h"
28
};
29
#include "hw/qdev-properties.h"
29
30
#include "hw/sysbus.h"
30
#endif /* HW_STM32F2XX_SYSCFG_H */
31
@@ -XXX,XX +XXX,XX @@ uart_write(void *opaque, hwaddr addr,
31
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
32
switch (addr)
32
index XXXXXXX..XXXXXXX 100644
33
{
33
--- a/hw/arm/stm32f205_soc.c
34
case R_STATUS:
34
+++ b/hw/arm/stm32f205_soc.c
35
- hw_error("write to UART STATUS?\n");
35
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
36
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: write to UART STATUS\n",
36
}
37
+ __func__);
37
busdev = SYS_BUS_DEVICE(dev);
38
break;
38
sysbus_mmio_map(busdev, 0, 0x40013800);
39
39
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
40
case R_CTRL:
40
41
/* Attach UART (uses USART registers) and USART controllers */
42
for (i = 0; i < STM_NUM_USARTS; i++) {
43
diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/misc/stm32f2xx_syscfg.c
46
+++ b/hw/misc/stm32f2xx_syscfg.c
47
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_syscfg_init(Object *obj)
48
{
49
STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj);
50
51
- sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
52
-
53
memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s,
54
TYPE_STM32F2XX_SYSCFG, 0x400);
55
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
41
--
56
--
42
2.20.1
57
2.20.1
43
58
44
59
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
hw_error() calls exit(). This a bit overkill when we can log
3
omap2420_mpu_init() introduced in commit 827df9f3c5f ("Add basic
4
the accesses as unimplemented or guest error.
4
OMAP2 chip support") takes care of creating the 3 UARTs.
5
5
6
When fuzzing the devices, we don't want the whole process to
6
Then commit 58a26b477e9 ("Emulate a serial bluetooth HCI with H4+
7
exit. Replace some hw_error() calls by qemu_log_mask().
7
extensions and attach to n8x0's UART") added n8x0_uart_setup()
8
which create the UART and connects it to an IRQ output,
9
overwritting the existing peripheral and its IRQ connection.
10
This is incorrect.
11
12
Fortunately we don't need to fix this, because commit 6da68df7f9b
13
("hw/arm/nseries: Replace the bluetooth chardev with a "null"
14
chardev") removed the use of this peripheral. We can simply
15
remove the code.
8
16
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
18
Message-id: 20201107193403.436146-4-f4bug@amsat.org
11
Message-id: 20200518140309.5220-3-f4bug@amsat.org
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
21
---
14
hw/arm/pxa2xx_gpio.c | 7 ++++---
22
hw/arm/nseries.c | 11 -----------
15
hw/display/pxa2xx_lcd.c | 8 +++++---
23
1 file changed, 11 deletions(-)
16
hw/dma/pxa2xx_dma.c | 14 +++++++++-----
17
3 files changed, 18 insertions(+), 11 deletions(-)
18
24
19
diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c
25
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
20
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/pxa2xx_gpio.c
27
--- a/hw/arm/nseries.c
22
+++ b/hw/arm/pxa2xx_gpio.c
28
+++ b/hw/arm/nseries.c
23
@@ -XXX,XX +XXX,XX @@
29
@@ -XXX,XX +XXX,XX @@ static void n8x0_cbus_setup(struct n800_s *s)
24
30
cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
25
#include "qemu/osdep.h"
31
}
26
#include "cpu.h"
32
27
-#include "hw/hw.h"
33
-static void n8x0_uart_setup(struct n800_s *s)
28
#include "hw/irq.h"
34
-{
29
#include "hw/qdev-properties.h"
35
- Chardev *radio = qemu_chr_new("bt-dummy-uart", "null", NULL);
30
#include "hw/sysbus.h"
36
- /*
31
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
37
- * Note: We used to connect N8X0_BT_RESET_GPIO and N8X0_BT_WKUP_GPIO
32
return s->status[bank];
38
- * here, but this code has been removed with the bluetooth backend.
33
39
- */
34
default:
40
- omap_uart_attach(s->mpu->uart[BT_UART], radio);
35
- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
41
-}
36
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
42
-
37
+ __func__, offset);
43
static void n8x0_usb_setup(struct n800_s *s)
44
{
45
SysBusDevice *dev;
46
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
47
n8x0_spi_setup(s);
48
n8x0_dss_setup(s);
49
n8x0_cbus_setup(s);
50
- n8x0_uart_setup(s);
51
if (machine_usb(machine)) {
52
n8x0_usb_setup(s);
38
}
53
}
39
40
return 0;
41
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
42
break;
43
44
default:
45
- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
46
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
47
+ __func__, offset);
48
}
49
}
50
51
diff --git a/hw/display/pxa2xx_lcd.c b/hw/display/pxa2xx_lcd.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/display/pxa2xx_lcd.c
54
+++ b/hw/display/pxa2xx_lcd.c
55
@@ -XXX,XX +XXX,XX @@
56
*/
57
58
#include "qemu/osdep.h"
59
-#include "hw/hw.h"
60
+#include "qemu/log.h"
61
#include "hw/irq.h"
62
#include "migration/vmstate.h"
63
#include "ui/console.h"
64
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_lcdc_read(void *opaque, hwaddr offset,
65
66
default:
67
fail:
68
- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
69
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
70
+ __func__, offset);
71
}
72
73
return 0;
74
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
75
76
default:
77
fail:
78
- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
79
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
80
+ __func__, offset);
81
}
82
}
83
84
diff --git a/hw/dma/pxa2xx_dma.c b/hw/dma/pxa2xx_dma.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/hw/dma/pxa2xx_dma.c
87
+++ b/hw/dma/pxa2xx_dma.c
88
@@ -XXX,XX +XXX,XX @@
89
*/
90
91
#include "qemu/osdep.h"
92
+#include "qemu/log.h"
93
#include "hw/hw.h"
94
#include "hw/irq.h"
95
#include "hw/qdev-properties.h"
96
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
97
unsigned int channel;
98
99
if (size != 4) {
100
- hw_error("%s: Bad access width\n", __func__);
101
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n",
102
+ __func__, size);
103
return 5;
104
}
105
106
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
107
return s->chan[channel].cmd;
108
}
109
}
110
-
111
- hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
112
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
113
+ __func__, offset);
114
return 7;
115
}
116
117
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset,
118
unsigned int channel;
119
120
if (size != 4) {
121
- hw_error("%s: Bad access width\n", __func__);
122
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n",
123
+ __func__, size);
124
return;
125
}
126
127
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset,
128
break;
129
}
130
fail:
131
- hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __func__, offset);
132
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
133
+ __func__, offset);
134
}
135
}
136
137
--
54
--
138
2.20.1
55
2.20.1
139
56
140
57
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
In preparation for a full implementation, move i.MX watchdog driver
3
The MusicPal board code connects both of the IRQ outputs of the UART
4
from hw/misc to hw/watchdog. While at it, add the watchdog files
4
to the same INTC qemu_irq. Connecting two qemu_irqs outputs directly
5
to MAINTAINERS.
5
to the same input is not valid as it produces subtly wrong behaviour
6
(for instance if both the IRQ lines are high, and then one goes
7
low, the INTC input will see this as a high-to-low transition
8
even though the second IRQ line should still be holding it high).
6
9
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
This kind of wiring needs an explicitly created OR gate; add one.
8
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
11
9
Message-id: 20200517162135.110364-2-linux@roeck-us.net
12
Inspired-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20201107193403.436146-5-f4bug@amsat.org
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
17
---
12
include/hw/arm/fsl-imx6.h | 2 +-
18
hw/arm/musicpal.c | 17 +++++++++++++----
13
include/hw/arm/fsl-imx6ul.h | 2 +-
19
hw/arm/Kconfig | 1 +
14
include/hw/arm/fsl-imx7.h | 2 +-
20
2 files changed, 14 insertions(+), 4 deletions(-)
15
include/hw/{misc/imx2_wdt.h => watchdog/wdt_imx2.h} | 0
16
hw/{misc/imx2_wdt.c => watchdog/wdt_imx2.c} | 2 +-
17
MAINTAINERS | 2 ++
18
hw/arm/Kconfig | 3 +++
19
hw/misc/Makefile.objs | 1 -
20
hw/watchdog/Kconfig | 3 +++
21
hw/watchdog/Makefile.objs | 1 +
22
10 files changed, 13 insertions(+), 5 deletions(-)
23
rename include/hw/{misc/imx2_wdt.h => watchdog/wdt_imx2.h} (100%)
24
rename hw/{misc/imx2_wdt.c => watchdog/wdt_imx2.c} (98%)
25
21
26
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
22
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
27
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/arm/fsl-imx6.h
24
--- a/hw/arm/musicpal.c
29
+++ b/include/hw/arm/fsl-imx6.h
25
+++ b/hw/arm/musicpal.c
30
@@ -XXX,XX +XXX,XX @@
26
@@ -XXX,XX +XXX,XX @@
31
#include "hw/cpu/a9mpcore.h"
27
#include "ui/console.h"
32
#include "hw/misc/imx6_ccm.h"
28
#include "hw/i2c/i2c.h"
33
#include "hw/misc/imx6_src.h"
29
#include "hw/irq.h"
34
-#include "hw/misc/imx2_wdt.h"
30
+#include "hw/or-irq.h"
35
+#include "hw/watchdog/wdt_imx2.h"
31
#include "hw/audio/wm8750.h"
36
#include "hw/char/imx_serial.h"
32
#include "sysemu/block-backend.h"
37
#include "hw/timer/imx_gpt.h"
33
#include "sysemu/runstate.h"
38
#include "hw/timer/imx_epit.h"
39
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/include/hw/arm/fsl-imx6ul.h
42
+++ b/include/hw/arm/fsl-imx6ul.h
43
@@ -XXX,XX +XXX,XX @@
34
@@ -XXX,XX +XXX,XX @@
44
#include "hw/misc/imx7_snvs.h"
35
#define MP_TIMER4_IRQ 7
45
#include "hw/misc/imx7_gpr.h"
36
#define MP_EHCI_IRQ 8
46
#include "hw/intc/imx_gpcv2.h"
37
#define MP_ETH_IRQ 9
47
-#include "hw/misc/imx2_wdt.h"
38
-#define MP_UART1_IRQ 11
48
+#include "hw/watchdog/wdt_imx2.h"
39
-#define MP_UART2_IRQ 11
49
#include "hw/gpio/imx_gpio.h"
40
+#define MP_UART_SHARED_IRQ 11
50
#include "hw/char/imx_serial.h"
41
#define MP_GPIO_IRQ 12
51
#include "hw/timer/imx_gpt.h"
42
#define MP_RTC_IRQ 28
52
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
43
#define MP_AUDIO_IRQ 30
53
index XXXXXXX..XXXXXXX 100644
44
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
54
--- a/include/hw/arm/fsl-imx7.h
45
ARMCPU *cpu;
55
+++ b/include/hw/arm/fsl-imx7.h
46
qemu_irq pic[32];
56
@@ -XXX,XX +XXX,XX @@
47
DeviceState *dev;
57
#include "hw/misc/imx7_snvs.h"
48
+ DeviceState *uart_orgate;
58
#include "hw/misc/imx7_gpr.h"
49
DeviceState *i2c_dev;
59
#include "hw/misc/imx6_src.h"
50
DeviceState *lcd_dev;
60
-#include "hw/misc/imx2_wdt.h"
51
DeviceState *key_dev;
61
+#include "hw/watchdog/wdt_imx2.h"
52
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
62
#include "hw/gpio/imx_gpio.h"
53
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
63
#include "hw/char/imx_serial.h"
54
pic[MP_TIMER4_IRQ], NULL);
64
#include "hw/timer/imx_gpt.h"
55
65
diff --git a/include/hw/misc/imx2_wdt.h b/include/hw/watchdog/wdt_imx2.h
56
- serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
66
similarity index 100%
57
+ /* Logically OR both UART IRQs together */
67
rename from include/hw/misc/imx2_wdt.h
58
+ uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
68
rename to include/hw/watchdog/wdt_imx2.h
59
+ object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
69
diff --git a/hw/misc/imx2_wdt.c b/hw/watchdog/wdt_imx2.c
60
+ qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
70
similarity index 98%
61
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
71
rename from hw/misc/imx2_wdt.c
62
+
72
rename to hw/watchdog/wdt_imx2.c
63
+ serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
73
index XXXXXXX..XXXXXXX 100644
64
+ qdev_get_gpio_in(uart_orgate, 0),
74
--- a/hw/misc/imx2_wdt.c
65
1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
75
+++ b/hw/watchdog/wdt_imx2.c
66
- serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
76
@@ -XXX,XX +XXX,XX @@
67
+ serial_mm_init(address_space_mem, MP_UART2_BASE, 2,
77
#include "qemu/module.h"
68
+ qdev_get_gpio_in(uart_orgate, 1),
78
#include "sysemu/watchdog.h"
69
1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
79
70
80
-#include "hw/misc/imx2_wdt.h"
71
/* Register flash */
81
+#include "hw/watchdog/wdt_imx2.h"
82
83
#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
84
#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
85
diff --git a/MAINTAINERS b/MAINTAINERS
86
index XXXXXXX..XXXXXXX 100644
87
--- a/MAINTAINERS
88
+++ b/MAINTAINERS
89
@@ -XXX,XX +XXX,XX @@ S: Odd Fixes
90
F: hw/arm/fsl-imx25.c
91
F: hw/arm/imx25_pdk.c
92
F: hw/misc/imx25_ccm.c
93
+F: hw/watchdog/wdt_imx2.c
94
F: include/hw/arm/fsl-imx25.h
95
F: include/hw/misc/imx25_ccm.h
96
+F: include/hw/watchdog/wdt_imx2.h
97
98
i.MX31 (kzm)
99
M: Peter Chubb <peter.chubb@nicta.com.au>
100
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
72
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
101
index XXXXXXX..XXXXXXX 100644
73
index XXXXXXX..XXXXXXX 100644
102
--- a/hw/arm/Kconfig
74
--- a/hw/arm/Kconfig
103
+++ b/hw/arm/Kconfig
75
+++ b/hw/arm/Kconfig
104
@@ -XXX,XX +XXX,XX @@ config FSL_IMX6
76
@@ -XXX,XX +XXX,XX @@ config MUSCA
105
select IMX_FEC
77
106
select IMX_I2C
78
config MUSICPAL
107
select IMX_USBPHY
108
+ select WDT_IMX2
109
select SDHCI
110
111
config ASPEED_SOC
112
@@ -XXX,XX +XXX,XX @@ config FSL_IMX7
113
select IMX
114
select IMX_FEC
115
select IMX_I2C
116
+ select WDT_IMX2
117
select PCI_EXPRESS_DESIGNWARE
118
select SDHCI
119
select UNIMP
120
@@ -XXX,XX +XXX,XX @@ config FSL_IMX6UL
121
select IMX
122
select IMX_FEC
123
select IMX_I2C
124
+ select WDT_IMX2
125
select SDHCI
126
select UNIMP
127
128
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
129
index XXXXXXX..XXXXXXX 100644
130
--- a/hw/misc/Makefile.objs
131
+++ b/hw/misc/Makefile.objs
132
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IMX) += imx6_ccm.o
133
common-obj-$(CONFIG_IMX) += imx6ul_ccm.o
134
obj-$(CONFIG_IMX) += imx6_src.o
135
common-obj-$(CONFIG_IMX) += imx7_ccm.o
136
-common-obj-$(CONFIG_IMX) += imx2_wdt.o
137
common-obj-$(CONFIG_IMX) += imx7_snvs.o
138
common-obj-$(CONFIG_IMX) += imx7_gpr.o
139
common-obj-$(CONFIG_IMX) += imx_rngc.o
140
diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig
141
index XXXXXXX..XXXXXXX 100644
142
--- a/hw/watchdog/Kconfig
143
+++ b/hw/watchdog/Kconfig
144
@@ -XXX,XX +XXX,XX @@ config WDT_IB700
145
146
config WDT_DIAG288
147
bool
79
bool
148
+
80
+ select OR_IRQ
149
+config WDT_IMX2
81
select BITBANG_I2C
150
+ bool
82
select MARVELL_88W8618
151
diff --git a/hw/watchdog/Makefile.objs b/hw/watchdog/Makefile.objs
83
select PTIMER
152
index XXXXXXX..XXXXXXX 100644
153
--- a/hw/watchdog/Makefile.objs
154
+++ b/hw/watchdog/Makefile.objs
155
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_WDT_IB6300ESB) += wdt_i6300esb.o
156
common-obj-$(CONFIG_WDT_IB700) += wdt_ib700.o
157
common-obj-$(CONFIG_WDT_DIAG288) += wdt_diag288.o
158
common-obj-$(CONFIG_ASPEED_SOC) += wdt_aspeed.o
159
+common-obj-$(CONFIG_WDT_IMX2) += wdt_imx2.o
160
--
84
--
161
2.20.1
85
2.20.1
162
86
163
87
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
hw_error() calls exit(). This a bit overkill when we can log
3
We don't need to fill the full pic[] array if we only use
4
the accesses as unimplemented or guest error.
4
few of the interrupt lines. Directly call qdev_get_gpio_in()
5
5
when necessary.
6
When fuzzing the devices, we don't want the whole process to
7
exit. Replace some hw_error() calls by qemu_log_mask().
8
6
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20201107193403.436146-6-f4bug@amsat.org
11
Message-id: 20200518140309.5220-2-f4bug@amsat.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
11
---
14
hw/arm/integratorcp.c | 23 +++++++++++++++--------
12
hw/arm/musicpal.c | 25 +++++++++++++------------
15
1 file changed, 15 insertions(+), 8 deletions(-)
13
1 file changed, 13 insertions(+), 12 deletions(-)
16
14
17
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
15
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/integratorcp.c
17
--- a/hw/arm/musicpal.c
20
+++ b/hw/arm/integratorcp.c
18
+++ b/hw/arm/musicpal.c
21
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info musicpal_binfo = {
22
#include "exec/address-spaces.h"
20
static void musicpal_init(MachineState *machine)
23
#include "sysemu/runstate.h"
21
{
24
#include "sysemu/sysemu.h"
22
ARMCPU *cpu;
25
+#include "qemu/log.h"
23
- qemu_irq pic[32];
26
#include "qemu/error-report.h"
24
DeviceState *dev;
27
#include "hw/char/pl011.h"
25
+ DeviceState *pic;
28
#include "hw/hw.h"
26
DeviceState *uart_orgate;
29
@@ -XXX,XX +XXX,XX @@ static uint64_t integratorcm_read(void *opaque, hwaddr offset,
27
DeviceState *i2c_dev;
30
/* ??? Voltage control unimplemented. */
28
DeviceState *lcd_dev;
31
return 0;
29
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
32
default:
30
&error_fatal);
33
- hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
31
memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
34
- (int)offset);
32
35
+ qemu_log_mask(LOG_UNIMP,
33
- dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
36
+ "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n",
34
+ pic = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
37
+ __func__, offset);
35
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
38
return 0;
36
- for (i = 0; i < 32; i++) {
39
}
37
- pic[i] = qdev_get_gpio_in(dev, i);
40
}
38
- }
41
@@ -XXX,XX +XXX,XX @@ static void integratorcm_write(void *opaque, hwaddr offset,
39
- sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ],
42
/* ??? Voltage control unimplemented. */
40
- pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
43
break;
41
- pic[MP_TIMER4_IRQ], NULL);
44
default:
42
+ sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE,
45
- hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
43
+ qdev_get_gpio_in(pic, MP_TIMER1_IRQ),
46
- (int)offset);
44
+ qdev_get_gpio_in(pic, MP_TIMER2_IRQ),
47
+ qemu_log_mask(LOG_UNIMP,
45
+ qdev_get_gpio_in(pic, MP_TIMER3_IRQ),
48
+ "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n",
46
+ qdev_get_gpio_in(pic, MP_TIMER4_IRQ), NULL);
49
+ __func__, offset);
47
50
break;
48
/* Logically OR both UART IRQs together */
51
}
49
uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
52
}
50
object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
53
@@ -XXX,XX +XXX,XX @@ static uint64_t icp_pic_read(void *opaque, hwaddr offset,
51
qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
54
case 5: /* INT_SOFTCLR */
52
- qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
55
case 11: /* FRQ_ENABLECLR */
53
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0,
56
default:
54
+ qdev_get_gpio_in(pic, MP_UART_SHARED_IRQ));
57
- printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
55
58
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
56
serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
59
+ __func__, offset);
57
qdev_get_gpio_in(uart_orgate, 0),
60
return 0;
58
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
61
}
59
OBJECT(get_system_memory()), &error_fatal);
62
}
60
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
63
@@ -XXX,XX +XXX,XX @@ static void icp_pic_write(void *opaque, hwaddr offset,
61
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
64
case 8: /* FRQ_STATUS */
62
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
65
case 9: /* FRQ_RAWSTAT */
63
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
66
default:
64
+ qdev_get_gpio_in(pic, MP_ETH_IRQ));
67
- printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
65
68
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
66
sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
69
+ __func__, offset);
67
70
return;
68
sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL);
71
}
69
72
icp_pic_update(s);
70
dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE,
73
@@ -XXX,XX +XXX,XX @@ static uint64_t icp_control_read(void *opaque, hwaddr offset,
71
- pic[MP_GPIO_IRQ]);
74
case 3: /* CP_DECODE */
72
+ qdev_get_gpio_in(pic, MP_GPIO_IRQ));
75
return 0x11;
73
i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
76
default:
74
i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c");
77
- hw_error("icp_control_read: Bad offset %x\n", (int)offset);
75
78
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
76
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
79
+ __func__, offset);
77
NULL);
80
return 0;
78
sysbus_realize_and_unref(s, &error_fatal);
81
}
79
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
82
}
80
- sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
83
@@ -XXX,XX +XXX,XX @@ static void icp_control_write(void *opaque, hwaddr offset,
81
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ));
84
/* Nothing interesting implemented yet. */
82
85
break;
83
musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
86
default:
84
arm_load_kernel(cpu, machine, &musicpal_binfo);
87
- hw_error("icp_control_write: Bad offset %x\n", (int)offset);
88
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
89
+ __func__, offset);
90
}
91
}
92
93
--
85
--
94
2.20.1
86
2.20.1
95
87
96
88
diff view generated by jsdifflib
1
We incorrectly treat SVC 0xf0002 as a cacheflush request (which is a
1
The nseries machines have a codepath that allows them to load a
2
NOP for QEMU). This is the wrong syscall number, because in the
2
secondary bootloader. This code wasn't checking that the
3
svc-immediate OABI syscall numbers are all offset by the
3
load_image_targphys() succeeded. Check the return value and report
4
ARM_SYSCALL_BASE value and so the correct insn is SVC 0x9f0002.
4
the error to the user.
5
(This is handled further down in the code with the other Arm-specific
6
syscalls like NR_breakpoint.)
7
5
8
When this code was initially added in commit 6f1f31c069b20611 in
6
While we're in the vicinity, fix the comment style of the
9
2004, ARM_NR_cacheflush was defined as (ARM_SYSCALL_BASE + 0xf0000 + 2)
7
comment documenting what this image load is doing.
10
so the value in the comparison took account of the extra 0x900000
11
offset. In commit fbb4a2e371f2fa7 in 2008, the ARM_SYSCALL_BASE
12
was removed from the definition of ARM_NR_cacheflush and handling
13
for this group of syscalls was added below the point where we subtract
14
ARM_SYSCALL_BASE from the SVC immediate value. However that commit
15
forgot to remove the now-obsolete earlier handling code.
16
8
17
Remove the spurious ARM_NR_cacheflush condition.
9
Fixes: Coverity CID 1192904
18
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
12
Message-id: 20201103114918.11807-1-peter.maydell@linaro.org
22
Message-id: 20200420212206.12776-3-peter.maydell@linaro.org
23
---
13
---
24
linux-user/arm/cpu_loop.c | 4 +---
14
hw/arm/nseries.c | 15 +++++++++++----
25
1 file changed, 1 insertion(+), 3 deletions(-)
15
1 file changed, 11 insertions(+), 4 deletions(-)
26
16
27
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
17
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
28
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
29
--- a/linux-user/arm/cpu_loop.c
19
--- a/hw/arm/nseries.c
30
+++ b/linux-user/arm/cpu_loop.c
20
+++ b/hw/arm/nseries.c
31
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
21
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
32
n = insn & 0xffffff;
22
/* No, wait, better start at the ROM. */
33
}
23
s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
34
24
35
- if (n == ARM_NR_cacheflush) {
25
- /* This is intended for loading the `secondary.bin' program from
36
- /* nop */
26
+ /*
37
- } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
27
+ * This is intended for loading the `secondary.bin' program from
38
+ if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
28
* Nokia images (the NOLO bootloader). The entry point seems
39
/* linux syscall */
29
* to be at OMAP2_Q2_BASE + 0x400000.
40
if (env->thumb || n == 0) {
30
*
41
n = env->regs[7];
31
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
32
* for them the entry point needs to be set to OMAP2_SRAM_BASE.
33
*
34
* The code above is for loading the `zImage' file from Nokia
35
- * images. */
36
- load_image_targphys(option_rom[0].name, OMAP2_Q2_BASE + 0x400000,
37
- machine->ram_size - 0x400000);
38
+ * images.
39
+ */
40
+ if (load_image_targphys(option_rom[0].name,
41
+ OMAP2_Q2_BASE + 0x400000,
42
+ machine->ram_size - 0x400000) < 0) {
43
+ error_report("Failed to load secondary bootloader %s",
44
+ option_rom[0].name);
45
+ exit(EXIT_FAILURE);
46
+ }
47
48
n800_setup_nolo_tags(nolo_tags);
49
cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
42
--
50
--
43
2.20.1
51
2.20.1
44
52
45
53
diff view generated by jsdifflib
Deleted patch
1
The kernel has different handling for syscalls with invalid
2
numbers that are in the "arm-specific" range 0x9f0000 and up:
3
* 0x9f0000..0x9f07ff return -ENOSYS if not implemented
4
* other out of range syscalls cause a SIGILL
5
(see the kernel's arch/arm/kernel/traps.c:arm_syscall())
6
1
7
Implement this distinction. (Note that our code doesn't look
8
quite like the kernel's, because we have removed the
9
0x900000 prefix by this point, whereas the kernel retains
10
it in arm_syscall().)
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20200420212206.12776-4-peter.maydell@linaro.org
15
---
16
linux-user/arm/cpu_loop.c | 30 ++++++++++++++++++++++++++----
17
1 file changed, 26 insertions(+), 4 deletions(-)
18
19
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/linux-user/arm/cpu_loop.c
22
+++ b/linux-user/arm/cpu_loop.c
23
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
24
env->regs[0] = cpu_get_tls(env);
25
break;
26
default:
27
- qemu_log_mask(LOG_UNIMP,
28
- "qemu: Unsupported ARM syscall: 0x%x\n",
29
- n);
30
- env->regs[0] = -TARGET_ENOSYS;
31
+ if (n < 0xf0800) {
32
+ /*
33
+ * Syscalls 0xf0000..0xf07ff (or 0x9f0000..
34
+ * 0x9f07ff in OABI numbering) are defined
35
+ * to return -ENOSYS rather than raising
36
+ * SIGILL. Note that we have already
37
+ * removed the 0x900000 prefix.
38
+ */
39
+ qemu_log_mask(LOG_UNIMP,
40
+ "qemu: Unsupported ARM syscall: 0x%x\n",
41
+ n);
42
+ env->regs[0] = -TARGET_ENOSYS;
43
+ } else {
44
+ /* Otherwise SIGILL */
45
+ info.si_signo = TARGET_SIGILL;
46
+ info.si_errno = 0;
47
+ info.si_code = TARGET_ILL_ILLTRP;
48
+ info._sifields._sigfault._addr = env->regs[15];
49
+ if (env->thumb) {
50
+ info._sifields._sigfault._addr -= 2;
51
+ } else {
52
+ info._sifields._sigfault._addr -= 4;
53
+ }
54
+ queue_signal(env, info.si_signo,
55
+ QEMU_SI_FAULT, &info);
56
+ }
57
break;
58
}
59
} else {
60
--
61
2.20.1
62
63
diff view generated by jsdifflib
Deleted patch
1
Our code to identify syscall numbers has some issues:
2
* for Thumb mode, we never need the immediate value from the insn,
3
but we always read it anyway
4
* bad immediate values in the svc insn should cause a SIGILL, but we
5
were abort()ing instead (via "goto error")
6
1
7
We can fix both these things by refactoring the code that identifies
8
the syscall number to more closely follow the kernel COMPAT_OABI code:
9
* for Thumb it is always r7
10
* for Arm, if the immediate value is 0, then this is an EABI call
11
with the syscall number in r7
12
* otherwise, we XOR the immediate value with 0x900000
13
(ARM_SYSCALL_BASE for QEMU; __NR_OABI_SYSCALL_BASE in the kernel),
14
which converts valid syscall immediates into the desired value,
15
and puts all invalid immediates in the range 0x100000 or above
16
* then we can just let the existing "value too large, deliver
17
SIGILL" case handle invalid numbers, and drop the 'goto error'
18
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
21
Message-id: 20200420212206.12776-5-peter.maydell@linaro.org
22
---
23
linux-user/arm/cpu_loop.c | 143 ++++++++++++++++++++------------------
24
1 file changed, 77 insertions(+), 66 deletions(-)
25
26
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/linux-user/arm/cpu_loop.c
29
+++ b/linux-user/arm/cpu_loop.c
30
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
31
env->eabi = 1;
32
/* system call */
33
if (env->thumb) {
34
- /* FIXME - what to do if get_user() fails? */
35
- get_user_code_u16(insn, env->regs[15] - 2, env);
36
- n = insn & 0xff;
37
+ /* Thumb is always EABI style with syscall number in r7 */
38
+ n = env->regs[7];
39
} else {
40
+ /*
41
+ * Equivalent of kernel CONFIG_OABI_COMPAT: read the
42
+ * Arm SVC insn to extract the immediate, which is the
43
+ * syscall number in OABI.
44
+ */
45
/* FIXME - what to do if get_user() fails? */
46
get_user_code_u32(insn, env->regs[15] - 4, env);
47
n = insn & 0xffffff;
48
- }
49
-
50
- if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
51
- /* linux syscall */
52
- if (env->thumb || n == 0) {
53
+ if (n == 0) {
54
+ /* zero immediate: EABI, syscall number in r7 */
55
n = env->regs[7];
56
} else {
57
- n -= ARM_SYSCALL_BASE;
58
+ /*
59
+ * This XOR matches the kernel code: an immediate
60
+ * in the valid range (0x900000 .. 0x9fffff) is
61
+ * converted into the correct EABI-style syscall
62
+ * number; invalid immediates end up as values
63
+ * > 0xfffff and are handled below as out-of-range.
64
+ */
65
+ n ^= ARM_SYSCALL_BASE;
66
env->eabi = 0;
67
}
68
- if ( n > ARM_NR_BASE) {
69
- switch (n) {
70
- case ARM_NR_cacheflush:
71
- /* nop */
72
- break;
73
- case ARM_NR_set_tls:
74
- cpu_set_tls(env, env->regs[0]);
75
- env->regs[0] = 0;
76
- break;
77
- case ARM_NR_breakpoint:
78
- env->regs[15] -= env->thumb ? 2 : 4;
79
- goto excp_debug;
80
- case ARM_NR_get_tls:
81
- env->regs[0] = cpu_get_tls(env);
82
- break;
83
- default:
84
- if (n < 0xf0800) {
85
- /*
86
- * Syscalls 0xf0000..0xf07ff (or 0x9f0000..
87
- * 0x9f07ff in OABI numbering) are defined
88
- * to return -ENOSYS rather than raising
89
- * SIGILL. Note that we have already
90
- * removed the 0x900000 prefix.
91
- */
92
- qemu_log_mask(LOG_UNIMP,
93
- "qemu: Unsupported ARM syscall: 0x%x\n",
94
- n);
95
- env->regs[0] = -TARGET_ENOSYS;
96
+ }
97
+
98
+ if (n > ARM_NR_BASE) {
99
+ switch (n) {
100
+ case ARM_NR_cacheflush:
101
+ /* nop */
102
+ break;
103
+ case ARM_NR_set_tls:
104
+ cpu_set_tls(env, env->regs[0]);
105
+ env->regs[0] = 0;
106
+ break;
107
+ case ARM_NR_breakpoint:
108
+ env->regs[15] -= env->thumb ? 2 : 4;
109
+ goto excp_debug;
110
+ case ARM_NR_get_tls:
111
+ env->regs[0] = cpu_get_tls(env);
112
+ break;
113
+ default:
114
+ if (n < 0xf0800) {
115
+ /*
116
+ * Syscalls 0xf0000..0xf07ff (or 0x9f0000..
117
+ * 0x9f07ff in OABI numbering) are defined
118
+ * to return -ENOSYS rather than raising
119
+ * SIGILL. Note that we have already
120
+ * removed the 0x900000 prefix.
121
+ */
122
+ qemu_log_mask(LOG_UNIMP,
123
+ "qemu: Unsupported ARM syscall: 0x%x\n",
124
+ n);
125
+ env->regs[0] = -TARGET_ENOSYS;
126
+ } else {
127
+ /*
128
+ * Otherwise SIGILL. This includes any SWI with
129
+ * immediate not originally 0x9fxxxx, because
130
+ * of the earlier XOR.
131
+ */
132
+ info.si_signo = TARGET_SIGILL;
133
+ info.si_errno = 0;
134
+ info.si_code = TARGET_ILL_ILLTRP;
135
+ info._sifields._sigfault._addr = env->regs[15];
136
+ if (env->thumb) {
137
+ info._sifields._sigfault._addr -= 2;
138
} else {
139
- /* Otherwise SIGILL */
140
- info.si_signo = TARGET_SIGILL;
141
- info.si_errno = 0;
142
- info.si_code = TARGET_ILL_ILLTRP;
143
- info._sifields._sigfault._addr = env->regs[15];
144
- if (env->thumb) {
145
- info._sifields._sigfault._addr -= 2;
146
- } else {
147
- info._sifields._sigfault._addr -= 4;
148
- }
149
- queue_signal(env, info.si_signo,
150
- QEMU_SI_FAULT, &info);
151
+ info._sifields._sigfault._addr -= 4;
152
}
153
- break;
154
- }
155
- } else {
156
- ret = do_syscall(env,
157
- n,
158
- env->regs[0],
159
- env->regs[1],
160
- env->regs[2],
161
- env->regs[3],
162
- env->regs[4],
163
- env->regs[5],
164
- 0, 0);
165
- if (ret == -TARGET_ERESTARTSYS) {
166
- env->regs[15] -= env->thumb ? 2 : 4;
167
- } else if (ret != -TARGET_QEMU_ESIGRETURN) {
168
- env->regs[0] = ret;
169
+ queue_signal(env, info.si_signo,
170
+ QEMU_SI_FAULT, &info);
171
}
172
+ break;
173
}
174
} else {
175
- goto error;
176
+ ret = do_syscall(env,
177
+ n,
178
+ env->regs[0],
179
+ env->regs[1],
180
+ env->regs[2],
181
+ env->regs[3],
182
+ env->regs[4],
183
+ env->regs[5],
184
+ 0, 0);
185
+ if (ret == -TARGET_ERESTARTSYS) {
186
+ env->regs[15] -= env->thumb ? 2 : 4;
187
+ } else if (ret != -TARGET_QEMU_ESIGRETURN) {
188
+ env->regs[0] = ret;
189
+ }
190
}
191
}
192
break;
193
--
194
2.20.1
195
196
diff view generated by jsdifflib
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
Implement full support for the watchdog in i.MX systems.
4
Pretimeout support is optional because the watchdog hardware
5
on i.MX31 does not support pretimeouts.
6
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20200517162135.110364-3-linux@roeck-us.net
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/watchdog/wdt_imx2.h | 61 ++++++++-
13
hw/watchdog/wdt_imx2.c | 239 +++++++++++++++++++++++++++++++--
14
2 files changed, 285 insertions(+), 15 deletions(-)
15
16
diff --git a/include/hw/watchdog/wdt_imx2.h b/include/hw/watchdog/wdt_imx2.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/watchdog/wdt_imx2.h
19
+++ b/include/hw/watchdog/wdt_imx2.h
20
@@ -XXX,XX +XXX,XX @@
21
#ifndef IMX2_WDT_H
22
#define IMX2_WDT_H
23
24
+#include "qemu/bitops.h"
25
#include "hw/sysbus.h"
26
+#include "hw/irq.h"
27
+#include "hw/ptimer.h"
28
29
#define TYPE_IMX2_WDT "imx2.wdt"
30
#define IMX2_WDT(obj) OBJECT_CHECK(IMX2WdtState, (obj), TYPE_IMX2_WDT)
31
32
enum IMX2WdtRegisters {
33
- IMX2_WDT_WCR = 0x0000,
34
- IMX2_WDT_REG_NUM = 0x0008 / sizeof(uint16_t) + 1,
35
+ IMX2_WDT_WCR = 0x0000, /* Control Register */
36
+ IMX2_WDT_WSR = 0x0002, /* Service Register */
37
+ IMX2_WDT_WRSR = 0x0004, /* Reset Status Register */
38
+ IMX2_WDT_WICR = 0x0006, /* Interrupt Control Register */
39
+ IMX2_WDT_WMCR = 0x0008, /* Misc Register */
40
};
41
42
+#define IMX2_WDT_MMIO_SIZE 0x000a
43
+
44
+/* Control Register definitions */
45
+#define IMX2_WDT_WCR_WT (0xFF << 8) /* Watchdog Timeout Field */
46
+#define IMX2_WDT_WCR_WDW BIT(7) /* WDOG Disable for Wait */
47
+#define IMX2_WDT_WCR_WDA BIT(5) /* WDOG Assertion */
48
+#define IMX2_WDT_WCR_SRS BIT(4) /* Software Reset Signal */
49
+#define IMX2_WDT_WCR_WDT BIT(3) /* WDOG Timeout Assertion */
50
+#define IMX2_WDT_WCR_WDE BIT(2) /* Watchdog Enable */
51
+#define IMX2_WDT_WCR_WDBG BIT(1) /* Watchdog Debug Enable */
52
+#define IMX2_WDT_WCR_WDZST BIT(0) /* Watchdog Timer Suspend */
53
+
54
+#define IMX2_WDT_WCR_LOCK_MASK (IMX2_WDT_WCR_WDZST | IMX2_WDT_WCR_WDBG \
55
+ | IMX2_WDT_WCR_WDW)
56
+
57
+/* Service Register definitions */
58
+#define IMX2_WDT_SEQ1 0x5555 /* service sequence 1 */
59
+#define IMX2_WDT_SEQ2 0xAAAA /* service sequence 2 */
60
+
61
+/* Reset Status Register definitions */
62
+#define IMX2_WDT_WRSR_TOUT BIT(1) /* Reset due to Timeout */
63
+#define IMX2_WDT_WRSR_SFTW BIT(0) /* Reset due to software reset */
64
+
65
+/* Interrupt Control Register definitions */
66
+#define IMX2_WDT_WICR_WIE BIT(15) /* Interrupt Enable */
67
+#define IMX2_WDT_WICR_WTIS BIT(14) /* Interrupt Status */
68
+#define IMX2_WDT_WICR_WICT 0xff /* Interrupt Timeout */
69
+#define IMX2_WDT_WICR_WICT_DEF 0x04 /* Default interrupt timeout (2s) */
70
+
71
+#define IMX2_WDT_WICR_LOCK_MASK (IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT)
72
+
73
+/* Misc Control Register definitions */
74
+#define IMX2_WDT_WMCR_PDE BIT(0) /* Power-Down Enable */
75
76
typedef struct IMX2WdtState {
77
/* <private> */
78
SysBusDevice parent_obj;
79
80
+ /*< public >*/
81
MemoryRegion mmio;
82
+ qemu_irq irq;
83
+
84
+ struct ptimer_state *timer;
85
+ struct ptimer_state *itimer;
86
+
87
+ bool pretimeout_support;
88
+ bool wicr_locked;
89
+
90
+ uint16_t wcr;
91
+ uint16_t wsr;
92
+ uint16_t wrsr;
93
+ uint16_t wicr;
94
+ uint16_t wmcr;
95
+
96
+ bool wcr_locked; /* affects WDZST, WDBG, and WDW */
97
+ bool wcr_wde_locked; /* affects WDE */
98
+ bool wcr_wdt_locked; /* affects WDT (never cleared) */
99
} IMX2WdtState;
100
101
#endif /* IMX2_WDT_H */
102
diff --git a/hw/watchdog/wdt_imx2.c b/hw/watchdog/wdt_imx2.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/hw/watchdog/wdt_imx2.c
105
+++ b/hw/watchdog/wdt_imx2.c
106
@@ -XXX,XX +XXX,XX @@
107
#include "qemu/bitops.h"
108
#include "qemu/module.h"
109
#include "sysemu/watchdog.h"
110
+#include "migration/vmstate.h"
111
+#include "hw/qdev-properties.h"
112
113
#include "hw/watchdog/wdt_imx2.h"
114
115
-#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
116
-#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
117
-
118
-static uint64_t imx2_wdt_read(void *opaque, hwaddr addr,
119
- unsigned int size)
120
+static void imx2_wdt_interrupt(void *opaque)
121
{
122
+ IMX2WdtState *s = IMX2_WDT(opaque);
123
+
124
+ s->wicr |= IMX2_WDT_WICR_WTIS;
125
+ qemu_set_irq(s->irq, 1);
126
+}
127
+
128
+static void imx2_wdt_expired(void *opaque)
129
+{
130
+ IMX2WdtState *s = IMX2_WDT(opaque);
131
+
132
+ s->wrsr = IMX2_WDT_WRSR_TOUT;
133
+
134
+ /* Perform watchdog action if watchdog is enabled */
135
+ if (s->wcr & IMX2_WDT_WCR_WDE) {
136
+ s->wrsr = IMX2_WDT_WRSR_TOUT;
137
+ watchdog_perform_action();
138
+ }
139
+}
140
+
141
+static void imx2_wdt_reset(DeviceState *dev)
142
+{
143
+ IMX2WdtState *s = IMX2_WDT(dev);
144
+
145
+ ptimer_transaction_begin(s->timer);
146
+ ptimer_stop(s->timer);
147
+ ptimer_transaction_commit(s->timer);
148
+
149
+ if (s->pretimeout_support) {
150
+ ptimer_transaction_begin(s->itimer);
151
+ ptimer_stop(s->itimer);
152
+ ptimer_transaction_commit(s->itimer);
153
+ }
154
+
155
+ s->wicr_locked = false;
156
+ s->wcr_locked = false;
157
+ s->wcr_wde_locked = false;
158
+
159
+ s->wcr = IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS;
160
+ s->wsr = 0;
161
+ s->wrsr &= ~(IMX2_WDT_WRSR_TOUT | IMX2_WDT_WRSR_SFTW);
162
+ s->wicr = IMX2_WDT_WICR_WICT_DEF;
163
+ s->wmcr = IMX2_WDT_WMCR_PDE;
164
+}
165
+
166
+static uint64_t imx2_wdt_read(void *opaque, hwaddr addr, unsigned int size)
167
+{
168
+ IMX2WdtState *s = IMX2_WDT(opaque);
169
+
170
+ switch (addr) {
171
+ case IMX2_WDT_WCR:
172
+ return s->wcr;
173
+ case IMX2_WDT_WSR:
174
+ return s->wsr;
175
+ case IMX2_WDT_WRSR:
176
+ return s->wrsr;
177
+ case IMX2_WDT_WICR:
178
+ return s->wicr;
179
+ case IMX2_WDT_WMCR:
180
+ return s->wmcr;
181
+ }
182
return 0;
183
}
184
185
+static void imx_wdt2_update_itimer(IMX2WdtState *s, bool start)
186
+{
187
+ bool running = (s->wcr & IMX2_WDT_WCR_WDE) && (s->wcr & IMX2_WDT_WCR_WT);
188
+ bool enabled = s->wicr & IMX2_WDT_WICR_WIE;
189
+
190
+ ptimer_transaction_begin(s->itimer);
191
+ if (start || !enabled) {
192
+ ptimer_stop(s->itimer);
193
+ }
194
+ if (running && enabled) {
195
+ int count = ptimer_get_count(s->timer);
196
+ int pretimeout = s->wicr & IMX2_WDT_WICR_WICT;
197
+
198
+ /*
199
+ * Only (re-)start pretimeout timer if its counter value is larger
200
+ * than 0. Otherwise it will fire right away and we'll get an
201
+ * interrupt loop.
202
+ */
203
+ if (count > pretimeout) {
204
+ ptimer_set_count(s->itimer, count - pretimeout);
205
+ if (start) {
206
+ ptimer_run(s->itimer, 1);
207
+ }
208
+ }
209
+ }
210
+ ptimer_transaction_commit(s->itimer);
211
+}
212
+
213
+static void imx_wdt2_update_timer(IMX2WdtState *s, bool start)
214
+{
215
+ ptimer_transaction_begin(s->timer);
216
+ if (start) {
217
+ ptimer_stop(s->timer);
218
+ }
219
+ if ((s->wcr & IMX2_WDT_WCR_WDE) && (s->wcr & IMX2_WDT_WCR_WT)) {
220
+ int count = (s->wcr & IMX2_WDT_WCR_WT) >> 8;
221
+
222
+ /* A value of 0 reflects one period (0.5s). */
223
+ ptimer_set_count(s->timer, count + 1);
224
+ if (start) {
225
+ ptimer_run(s->timer, 1);
226
+ }
227
+ }
228
+ ptimer_transaction_commit(s->timer);
229
+ if (s->pretimeout_support) {
230
+ imx_wdt2_update_itimer(s, start);
231
+ }
232
+}
233
+
234
static void imx2_wdt_write(void *opaque, hwaddr addr,
235
uint64_t value, unsigned int size)
236
{
237
- if (addr == IMX2_WDT_WCR &&
238
- (~value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS))) {
239
- watchdog_perform_action();
240
+ IMX2WdtState *s = IMX2_WDT(opaque);
241
+
242
+ switch (addr) {
243
+ case IMX2_WDT_WCR:
244
+ if (s->wcr_locked) {
245
+ value &= ~IMX2_WDT_WCR_LOCK_MASK;
246
+ value |= (s->wicr & IMX2_WDT_WCR_LOCK_MASK);
247
+ }
248
+ s->wcr_locked = true;
249
+ if (s->wcr_wde_locked) {
250
+ value &= ~IMX2_WDT_WCR_WDE;
251
+ value |= (s->wicr & ~IMX2_WDT_WCR_WDE);
252
+ } else if (value & IMX2_WDT_WCR_WDE) {
253
+ s->wcr_wde_locked = true;
254
+ }
255
+ if (s->wcr_wdt_locked) {
256
+ value &= ~IMX2_WDT_WCR_WDT;
257
+ value |= (s->wicr & ~IMX2_WDT_WCR_WDT);
258
+ } else if (value & IMX2_WDT_WCR_WDT) {
259
+ s->wcr_wdt_locked = true;
260
+ }
261
+
262
+ s->wcr = value;
263
+ if (!(value & IMX2_WDT_WCR_SRS)) {
264
+ s->wrsr = IMX2_WDT_WRSR_SFTW;
265
+ }
266
+ if (!(value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS)) ||
267
+ (!(value & IMX2_WDT_WCR_WT) && (value & IMX2_WDT_WCR_WDE))) {
268
+ watchdog_perform_action();
269
+ }
270
+ s->wcr |= IMX2_WDT_WCR_SRS;
271
+ imx_wdt2_update_timer(s, true);
272
+ break;
273
+ case IMX2_WDT_WSR:
274
+ if (s->wsr == IMX2_WDT_SEQ1 && value == IMX2_WDT_SEQ2) {
275
+ imx_wdt2_update_timer(s, false);
276
+ }
277
+ s->wsr = value;
278
+ break;
279
+ case IMX2_WDT_WRSR:
280
+ break;
281
+ case IMX2_WDT_WICR:
282
+ if (!s->pretimeout_support) {
283
+ return;
284
+ }
285
+ value &= IMX2_WDT_WICR_LOCK_MASK | IMX2_WDT_WICR_WTIS;
286
+ if (s->wicr_locked) {
287
+ value &= IMX2_WDT_WICR_WTIS;
288
+ value |= (s->wicr & IMX2_WDT_WICR_LOCK_MASK);
289
+ }
290
+ s->wicr = value | (s->wicr & IMX2_WDT_WICR_WTIS);
291
+ if (value & IMX2_WDT_WICR_WTIS) {
292
+ s->wicr &= ~IMX2_WDT_WICR_WTIS;
293
+ qemu_set_irq(s->irq, 0);
294
+ }
295
+ imx_wdt2_update_itimer(s, true);
296
+ s->wicr_locked = true;
297
+ break;
298
+ case IMX2_WDT_WMCR:
299
+ s->wmcr = value & IMX2_WDT_WMCR_PDE;
300
+ break;
301
}
302
}
303
304
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps imx2_wdt_ops = {
305
* real device but in practice there is no reason for a guest
306
* to access this device unaligned.
307
*/
308
- .min_access_size = 4,
309
- .max_access_size = 4,
310
+ .min_access_size = 2,
311
+ .max_access_size = 2,
312
.unaligned = false,
313
},
314
};
315
316
+static const VMStateDescription vmstate_imx2_wdt = {
317
+ .name = "imx2.wdt",
318
+ .fields = (VMStateField[]) {
319
+ VMSTATE_PTIMER(timer, IMX2WdtState),
320
+ VMSTATE_PTIMER(itimer, IMX2WdtState),
321
+ VMSTATE_BOOL(wicr_locked, IMX2WdtState),
322
+ VMSTATE_BOOL(wcr_locked, IMX2WdtState),
323
+ VMSTATE_BOOL(wcr_wde_locked, IMX2WdtState),
324
+ VMSTATE_BOOL(wcr_wdt_locked, IMX2WdtState),
325
+ VMSTATE_UINT16(wcr, IMX2WdtState),
326
+ VMSTATE_UINT16(wsr, IMX2WdtState),
327
+ VMSTATE_UINT16(wrsr, IMX2WdtState),
328
+ VMSTATE_UINT16(wmcr, IMX2WdtState),
329
+ VMSTATE_UINT16(wicr, IMX2WdtState),
330
+ VMSTATE_END_OF_LIST()
331
+ }
332
+};
333
+
334
static void imx2_wdt_realize(DeviceState *dev, Error **errp)
335
{
336
IMX2WdtState *s = IMX2_WDT(dev);
337
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
338
339
memory_region_init_io(&s->mmio, OBJECT(dev),
340
&imx2_wdt_ops, s,
341
- TYPE_IMX2_WDT".mmio",
342
- IMX2_WDT_REG_NUM * sizeof(uint16_t));
343
- sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
344
+ TYPE_IMX2_WDT,
345
+ IMX2_WDT_MMIO_SIZE);
346
+ sysbus_init_mmio(sbd, &s->mmio);
347
+ sysbus_init_irq(sbd, &s->irq);
348
+
349
+ s->timer = ptimer_init(imx2_wdt_expired, s,
350
+ PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
351
+ PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
352
+ PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
353
+ ptimer_transaction_begin(s->timer);
354
+ ptimer_set_freq(s->timer, 2);
355
+ ptimer_set_limit(s->timer, 0xff, 1);
356
+ ptimer_transaction_commit(s->timer);
357
+ if (s->pretimeout_support) {
358
+ s->itimer = ptimer_init(imx2_wdt_interrupt, s,
359
+ PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
360
+ PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
361
+ PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
362
+ ptimer_transaction_begin(s->itimer);
363
+ ptimer_set_freq(s->itimer, 2);
364
+ ptimer_set_limit(s->itimer, 0xff, 1);
365
+ ptimer_transaction_commit(s->itimer);
366
+ }
367
}
368
369
+static Property imx2_wdt_properties[] = {
370
+ DEFINE_PROP_BOOL("pretimeout-support", IMX2WdtState, pretimeout_support,
371
+ false),
372
+};
373
+
374
static void imx2_wdt_class_init(ObjectClass *klass, void *data)
375
{
376
DeviceClass *dc = DEVICE_CLASS(klass);
377
378
+ device_class_set_props(dc, imx2_wdt_properties);
379
dc->realize = imx2_wdt_realize;
380
+ dc->reset = imx2_wdt_reset;
381
+ dc->vmsd = &vmstate_imx2_wdt;
382
+ dc->desc = "i.MX watchdog timer";
383
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
384
}
385
386
--
387
2.20.1
388
389
diff view generated by jsdifflib
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
With this patch applied, the watchdog in the sabrelite emulation
4
is fully operational, including pretimeout support.
5
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20200517162135.110364-6-linux@roeck-us.net
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/fsl-imx6.c | 9 +++++++++
12
1 file changed, 9 insertions(+)
13
14
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/fsl-imx6.c
17
+++ b/hw/arm/fsl-imx6.c
18
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
19
FSL_IMX6_WDOG1_ADDR,
20
FSL_IMX6_WDOG2_ADDR,
21
};
22
+ static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = {
23
+ FSL_IMX6_WDOG1_IRQ,
24
+ FSL_IMX6_WDOG2_IRQ,
25
+ };
26
27
+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
28
+ &error_abort);
29
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
30
&error_abort);
31
32
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
33
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
34
+ qdev_get_gpio_in(DEVICE(&s->a9mpcore),
35
+ FSL_IMX6_WDOGn_IRQ[i]));
36
}
37
38
/* ROM memory */
39
--
40
2.20.1
41
42
diff view generated by jsdifflib
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
Instantiating PWM, CAN, CAAM, and OCOTP devices is necessary to avoid
4
crashes when booting mainline Linux.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20200517162135.110364-8-linux@roeck-us.net
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/fsl-imx7.h | 16 ++++++++++++++++
12
hw/arm/fsl-imx7.c | 24 ++++++++++++++++++++++++
13
2 files changed, 40 insertions(+)
14
15
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/fsl-imx7.h
18
+++ b/include/hw/arm/fsl-imx7.h
19
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
20
FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000,
21
FSL_IMX7_IOMUXCn_SIZE = 0x1000,
22
23
+ FSL_IMX7_OCOTP_ADDR = 0x30350000,
24
+ FSL_IMX7_OCOTP_SIZE = 0x10000,
25
+
26
FSL_IMX7_ANALOG_ADDR = 0x30360000,
27
FSL_IMX7_SNVS_ADDR = 0x30370000,
28
FSL_IMX7_CCM_ADDR = 0x30380000,
29
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
30
FSL_IMX7_ADC2_ADDR = 0x30620000,
31
FSL_IMX7_ADCn_SIZE = 0x1000,
32
33
+ FSL_IMX7_PWM1_ADDR = 0x30660000,
34
+ FSL_IMX7_PWM2_ADDR = 0x30670000,
35
+ FSL_IMX7_PWM3_ADDR = 0x30680000,
36
+ FSL_IMX7_PWM4_ADDR = 0x30690000,
37
+ FSL_IMX7_PWMn_SIZE = 0x10000,
38
+
39
FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
40
FSL_IMX7_PCIE_PHY_SIZE = 0x10000,
41
42
FSL_IMX7_GPC_ADDR = 0x303A0000,
43
44
+ FSL_IMX7_CAAM_ADDR = 0x30900000,
45
+ FSL_IMX7_CAAM_SIZE = 0x40000,
46
+
47
+ FSL_IMX7_CAN1_ADDR = 0x30A00000,
48
+ FSL_IMX7_CAN2_ADDR = 0x30A10000,
49
+ FSL_IMX7_CANn_SIZE = 0x10000,
50
+
51
FSL_IMX7_I2C1_ADDR = 0x30A20000,
52
FSL_IMX7_I2C2_ADDR = 0x30A30000,
53
FSL_IMX7_I2C3_ADDR = 0x30A40000,
54
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/arm/fsl-imx7.c
57
+++ b/hw/arm/fsl-imx7.c
58
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
59
*/
60
create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR, FSL_IMX7_SDMA_SIZE);
61
62
+ /*
63
+ * CAAM
64
+ */
65
+ create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
66
+
67
+ /*
68
+ * PWM
69
+ */
70
+ create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
71
+ create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
72
+ create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
73
+ create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
74
+
75
+ /*
76
+ * CAN
77
+ */
78
+ create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
79
+ create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
80
+
81
+ /*
82
+ * OCOTP
83
+ */
84
+ create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
85
+ FSL_IMX7_OCOTP_SIZE);
86
87
object_property_set_bool(OBJECT(&s->gpr), true, "realized",
88
&error_abort);
89
--
90
2.20.1
91
92
diff view generated by jsdifflib
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
i.MX7 supports watchdog pretimeout interupts. With this commit,
4
the watchdog in mcimx7d-sabre is fully operational, including
5
pretimeout support.
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
9
Message-id: 20200517162135.110364-9-linux@roeck-us.net
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/arm/fsl-imx7.h | 5 +++++
13
hw/arm/fsl-imx7.c | 11 +++++++++++
14
2 files changed, 16 insertions(+)
15
16
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/fsl-imx7.h
19
+++ b/include/hw/arm/fsl-imx7.h
20
@@ -XXX,XX +XXX,XX @@ enum FslIMX7IRQs {
21
FSL_IMX7_USB2_IRQ = 42,
22
FSL_IMX7_USB3_IRQ = 40,
23
24
+ FSL_IMX7_WDOG1_IRQ = 78,
25
+ FSL_IMX7_WDOG2_IRQ = 79,
26
+ FSL_IMX7_WDOG3_IRQ = 10,
27
+ FSL_IMX7_WDOG4_IRQ = 109,
28
+
29
FSL_IMX7_PCI_INTA_IRQ = 125,
30
FSL_IMX7_PCI_INTB_IRQ = 124,
31
FSL_IMX7_PCI_INTC_IRQ = 123,
32
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/fsl-imx7.c
35
+++ b/hw/arm/fsl-imx7.c
36
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
37
FSL_IMX7_WDOG3_ADDR,
38
FSL_IMX7_WDOG4_ADDR,
39
};
40
+ static const int FSL_IMX7_WDOGn_IRQ[FSL_IMX7_NUM_WDTS] = {
41
+ FSL_IMX7_WDOG1_IRQ,
42
+ FSL_IMX7_WDOG2_IRQ,
43
+ FSL_IMX7_WDOG3_IRQ,
44
+ FSL_IMX7_WDOG4_IRQ,
45
+ };
46
47
+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
48
+ &error_abort);
49
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
50
&error_abort);
51
52
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);
53
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
54
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
55
+ FSL_IMX7_WDOGn_IRQ[i]));
56
}
57
58
/*
59
--
60
2.20.1
61
62
diff view generated by jsdifflib
Deleted patch
1
From: Geert Uytterhoeven <geert+renesas@glider.be>
2
1
3
Add a definition for the number of GPIO lines controlled by a PL061
4
instance, and use it instead of the hardcoded magic value 8.
5
6
Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20200519085143.1376-1-geert+renesas@glider.be
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/gpio/pl061.c | 12 +++++++-----
13
1 file changed, 7 insertions(+), 5 deletions(-)
14
15
diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/gpio/pl061.c
18
+++ b/hw/gpio/pl061.c
19
@@ -XXX,XX +XXX,XX @@ static const uint8_t pl061_id_luminary[12] =
20
#define TYPE_PL061 "pl061"
21
#define PL061(obj) OBJECT_CHECK(PL061State, (obj), TYPE_PL061)
22
23
+#define N_GPIOS 8
24
+
25
typedef struct PL061State {
26
SysBusDevice parent_obj;
27
28
@@ -XXX,XX +XXX,XX @@ typedef struct PL061State {
29
uint32_t cr;
30
uint32_t amsel;
31
qemu_irq irq;
32
- qemu_irq out[8];
33
+ qemu_irq out[N_GPIOS];
34
const unsigned char *id;
35
uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */
36
} PL061State;
37
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
38
changed = s->old_out_data ^ out;
39
if (changed) {
40
s->old_out_data = out;
41
- for (i = 0; i < 8; i++) {
42
+ for (i = 0; i < N_GPIOS; i++) {
43
mask = 1 << i;
44
if (changed & mask) {
45
DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
46
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
47
changed = (s->old_in_data ^ s->data) & ~s->dir;
48
if (changed) {
49
s->old_in_data = s->data;
50
- for (i = 0; i < 8; i++) {
51
+ for (i = 0; i < N_GPIOS; i++) {
52
mask = 1 << i;
53
if (changed & mask) {
54
DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0);
55
@@ -XXX,XX +XXX,XX @@ static void pl061_init(Object *obj)
56
memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000);
57
sysbus_init_mmio(sbd, &s->iomem);
58
sysbus_init_irq(sbd, &s->irq);
59
- qdev_init_gpio_in(dev, pl061_set_irq, 8);
60
- qdev_init_gpio_out(dev, s->out, 8);
61
+ qdev_init_gpio_in(dev, pl061_set_irq, N_GPIOS);
62
+ qdev_init_gpio_out(dev, s->out, N_GPIOS);
63
}
64
65
static void pl061_class_init(ObjectClass *klass, void *data)
66
--
67
2.20.1
68
69
diff view generated by jsdifflib
1
The Arm signal-handling code has some parts ifdeffed with a
1
From: Havard Skinnemoen <hskinnemoen@google.com>
2
TARGET_CONFIG_CPU_32, which is always defined. This is a leftover
3
from when this code's structure was based on the Linux kernel
4
signal handling code, where it was intended to support 26-bit
5
Arm CPUs. The kernel dropped its CONFIG_CPU_32 in kernel commit
6
4da8b8208eded0ba21e3 in 2009.
7
2
8
QEMU has never had 26-bit CPU support and is unlikely to ever
3
The number of runs is equal to the number of 0-1 and 1-0 transitions,
9
add it; we certainly aren't going to support 26-bit Linux
4
plus one. Currently, it's counting the number of times these transitions
10
binaries via linux-user mode. The ifdef is just unhelpful
5
do _not_ happen, plus one.
11
noise, so remove it entirely.
12
6
7
Source:
8
https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-22r1a.pdf
9
section 2.3.4 point (3).
10
11
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
12
Message-id: 20201103011457.2959989-2-hskinnemoen@google.com
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20200518143014.20689-1-peter.maydell@linaro.org
16
---
15
---
17
linux-user/arm/signal.c | 6 ------
16
tests/qtest/npcm7xx_rng-test.c | 2 +-
18
1 file changed, 6 deletions(-)
17
1 file changed, 1 insertion(+), 1 deletion(-)
19
18
20
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
19
diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
21
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
22
--- a/linux-user/arm/signal.c
21
--- a/tests/qtest/npcm7xx_rng-test.c
23
+++ b/linux-user/arm/signal.c
22
+++ b/tests/qtest/npcm7xx_rng-test.c
24
@@ -XXX,XX +XXX,XX @@ struct rt_sigframe_v2
23
@@ -XXX,XX +XXX,XX @@ static double calc_runs_p(const unsigned long *buf, unsigned int nr_bits)
25
abi_ulong retcode[4];
24
pi = (double)nr_ones / nr_bits;
26
};
25
27
26
for (k = 0; k < nr_bits - 1; k++) {
28
-#define TARGET_CONFIG_CPU_32 1
27
- vn_obs += !(test_bit(k, buf) ^ test_bit(k + 1, buf));
29
-
28
+ vn_obs += (test_bit(k, buf) ^ test_bit(k + 1, buf));
30
/*
29
}
31
* For ARM syscalls, we encode the syscall number into the instruction.
30
vn_obs += 1;
32
*/
33
@@ -XXX,XX +XXX,XX @@ setup_sigcontext(struct target_sigcontext *sc, /*struct _fpstate *fpstate,*/
34
__put_user(env->regs[13], &sc->arm_sp);
35
__put_user(env->regs[14], &sc->arm_lr);
36
__put_user(env->regs[15], &sc->arm_pc);
37
-#ifdef TARGET_CONFIG_CPU_32
38
__put_user(cpsr_read(env), &sc->arm_cpsr);
39
-#endif
40
41
__put_user(/* current->thread.trap_no */ 0, &sc->trap_no);
42
__put_user(/* current->thread.error_code */ 0, &sc->error_code);
43
@@ -XXX,XX +XXX,XX @@ restore_sigcontext(CPUARMState *env, struct target_sigcontext *sc)
44
__get_user(env->regs[13], &sc->arm_sp);
45
__get_user(env->regs[14], &sc->arm_lr);
46
__get_user(env->regs[15], &sc->arm_pc);
47
-#ifdef TARGET_CONFIG_CPU_32
48
__get_user(cpsr, &sc->arm_cpsr);
49
cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr);
50
arm_rebuild_hflags(env);
51
-#endif
52
53
err |= !valid_user_regs(env);
54
31
55
--
32
--
56
2.20.1
33
2.20.1
57
34
58
35
diff view generated by jsdifflib
1
Using the MSR instruction to write to CPSR.E is deprecated, but it is
1
Checks for UNDEF cases should go before the "is VFP enabled?" access
2
required to work from any mode including unprivileged code. We were
2
check, except in special cases. Move a stray UNDEF check in the VTBL
3
incorrectly forbidding usermode code from writing it because
3
trans function up above the access check.
4
CPSR_USER did not include the CPSR_E bit.
5
6
We use CPSR_USER in only three places:
7
* as the mask of what to allow userspace MSR to write to CPSR
8
* when deciding what bits a linux-user signal-return should be
9
able to write from the sigcontext structure
10
* in target_user_copy_regs() when we set up the initial
11
registers for the linux-user process
12
13
In the first two cases not being able to update CPSR.E is a bug, and
14
in the third case it doesn't matter because CPSR.E is always 0 there.
15
So we can fix both bugs by adding CPSR_E to CPSR_USER.
16
17
Because the cpsr_write() in restore_sigcontext() is now changing
18
a CPSR bit which is cached in hflags, we need to add an
19
arm_rebuild_hflags() call there; the callsite in
20
target_user_copy_regs() was already rebuilding hflags for other
21
reasons.
22
23
(The recommended way to change CPSR.E is to use the 'SETEND'
24
instruction, which we do correctly allow from usermode code.)
25
4
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
28
Message-id: 20200518142801.20503-1-peter.maydell@linaro.org
7
Message-id: 20201109145324.2859-1-peter.maydell@linaro.org
29
---
8
---
30
target/arm/cpu.h | 2 +-
9
target/arm/translate-neon.c.inc | 8 ++++----
31
linux-user/arm/signal.c | 1 +
10
1 file changed, 4 insertions(+), 4 deletions(-)
32
2 files changed, 2 insertions(+), 1 deletion(-)
33
11
34
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
12
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
35
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/cpu.h
14
--- a/target/arm/translate-neon.c.inc
37
+++ b/target/arm/cpu.h
15
+++ b/target/arm/translate-neon.c.inc
38
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
16
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
39
#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
17
return false;
40
| CPSR_NZCV)
18
}
41
/* Bits writable in user mode. */
19
42
-#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
20
- if (!vfp_access_check(s)) {
43
+#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
21
- return true;
44
/* Execution state bits. MRS read as zero, MSR writes ignored. */
22
- }
45
#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
23
-
46
24
if ((a->vn + a->len + 1) > 32) {
47
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
25
/*
48
index XXXXXXX..XXXXXXX 100644
26
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
49
--- a/linux-user/arm/signal.c
27
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
50
+++ b/linux-user/arm/signal.c
28
return false;
51
@@ -XXX,XX +XXX,XX @@ restore_sigcontext(CPUARMState *env, struct target_sigcontext *sc)
29
}
52
#ifdef TARGET_CONFIG_CPU_32
30
53
__get_user(cpsr, &sc->arm_cpsr);
31
+ if (!vfp_access_check(s)) {
54
cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr);
32
+ return true;
55
+ arm_rebuild_hflags(env);
33
+ }
56
#endif
34
+
57
35
desc = tcg_const_i32((a->vn << 2) | a->len);
58
err |= !valid_user_regs(env);
36
def = tcg_temp_new_i64();
37
if (a->op) {
59
--
38
--
60
2.20.1
39
2.20.1
61
40
62
41
diff view generated by jsdifflib