[PATCH v8 00/62] target/riscv: support vector extension v0.7.1

LIU Zhiwei posted 62 patches 1 week ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/20200521094413.10425-1-zhiwei_liu@c-sky.com
Maintainers: Sagar Karandikar <sagark@eecs.berkeley.edu>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
target/riscv/Makefile.objs              |    2 +-
target/riscv/cpu.c                      |   49 +
target/riscv/cpu.h                      |   82 +-
target/riscv/cpu_bits.h                 |   15 +
target/riscv/csr.c                      |   82 +-
target/riscv/fpu_helper.c               |   52 +-
target/riscv/helper.h                   | 1068 +++++
target/riscv/insn32-64.decode           |   11 +
target/riscv/insn32.decode              |  372 ++
target/riscv/insn_trans/trans_rvv.inc.c | 2884 +++++++++++++
target/riscv/internals.h                |   44 +
target/riscv/translate.c                |   27 +-
target/riscv/vector_helper.c            | 4898 +++++++++++++++++++++++
13 files changed, 9537 insertions(+), 49 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
create mode 100644 target/riscv/internals.h
create mode 100644 target/riscv/vector_helper.c

[PATCH v8 00/62] target/riscv: support vector extension v0.7.1

Posted by LIU Zhiwei 1 week ago
This patchset implements the vector extension for RISC-V on QEMU.

You can also find the patchset and all *test cases* in
my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v8).
All the test cases are in the directory qemu/tests/riscv/vector/. They are
riscv64 linux user mode programs.

You can test the patchset by the script qemu/tests/riscv/vector/runcase.sh.

Features:
  * support specification riscv-v-spec-0.7.1.(https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1/)
  * support basic vector extension.
  * support Zvlsseg.
  * support Zvamo.
  * not support Zvediv as it is changing.
  * SLEN always equals VLEN.
  * element width support 8bit, 16bit, 32bit, 64bit.

Changelog:
v8
  * support different float rounding modes for vector instructions.
  * use lastest released TCG GVEC DUP IR.
  * set RV_VLEN_MAX to 256 bits, as GVEC IR uses simd_desc.

v7
  * move vl == 0 check to translation time by add a global cpu_vl.
  * implement vector element inline load and store function by TCG IR.
  * based on vec_element_load(store), implement some permutation instructions.
  * implement rsubs GVEC IR.
  * fixup vsmul, vmfne, vfmerge, vslidedown.
  * some other small bugs and indentation errors.

v6
  * use gvec_dup Gvec IR to accellerate move and merge.
  * a better way to implement fixed point instructions.
  * a global check when vl == 0.
  * limit some macros to only one inline function call.
  * fixup sew error when use Gvec IR.
  * fixup bugs for corner cases.

v5
  * fixup a bug in tb flags.

v4
  * no change

v3
  * move check code from execution-time to translation-time
  * use a continous memory block for vector register description.
  * vector registers as direct fields in RISCVCPUState.
  * support VLEN configure from qemu command line.
  * support ELEN configure from qemu command line.
  * support vector specification version configure from qemu command line.
  * probe pages before real load or store access.
  * use probe_page_check for no-fault operations in linux user mode.
  * generation atomic exit exception when in parallel environment.
  * fixup a lot of concrete bugs.

V2
  * use float16_compare{_quiet}
  * only use GETPC() in outer most helper
  * add ctx.ext_v Property

LIU Zhiwei (62):
  target/riscv: add vector extension field in CPURISCVState
  target/riscv: implementation-defined constant parameters
  target/riscv: support vector extension csr
  target/riscv: add vector configure instruction
  target/riscv: add an internals.h header
  target/riscv: add vector stride load and store instructions
  target/riscv: add vector index load and store instructions
  target/riscv: add fault-only-first unit stride load
  target/riscv: add vector amo operations
  target/riscv: vector single-width integer add and subtract
  target/riscv: vector widening integer add and subtract
  target/riscv: vector integer add-with-carry / subtract-with-borrow
    instructions
  target/riscv: vector bitwise logical instructions
  target/riscv: vector single-width bit shift instructions
  target/riscv: vector narrowing integer right shift instructions
  target/riscv: vector integer comparison instructions
  target/riscv: vector integer min/max instructions
  target/riscv: vector single-width integer multiply instructions
  target/riscv: vector integer divide instructions
  target/riscv: vector widening integer multiply instructions
  target/riscv: vector single-width integer multiply-add instructions
  target/riscv: vector widening integer multiply-add instructions
  target/riscv: vector integer merge and move instructions
  target/riscv: vector single-width saturating add and subtract
  target/riscv: vector single-width averaging add and subtract
  target/riscv: vector single-width fractional multiply with rounding
    and saturation
  target/riscv: vector widening saturating scaled multiply-add
  target/riscv: vector single-width scaling shift instructions
  target/riscv: vector narrowing fixed-point clip instructions
  target/riscv: Update fp_status when float rounding mode changes
  target/riscv: vector single-width floating-point add/subtract
    instructions
  target/riscv: vector widening floating-point add/subtract instructions
  target/riscv: vector single-width floating-point multiply/divide
    instructions
  target/riscv: vector widening floating-point multiply
  target/riscv: vector single-width floating-point fused multiply-add
    instructions
  target/riscv: vector widening floating-point fused multiply-add
    instructions
  target/riscv: vector floating-point square-root instruction
  target/riscv: vector floating-point min/max instructions
  target/riscv: vector floating-point sign-injection instructions
  target/riscv: vector floating-point compare instructions
  target/riscv: vector floating-point classify instructions
  target/riscv: vector floating-point merge instructions
  target/riscv: vector floating-point/integer type-convert instructions
  target/riscv: widening floating-point/integer type-convert
    instructions
  target/riscv: narrowing floating-point/integer type-convert
    instructions
  target/riscv: vector single-width integer reduction instructions
  target/riscv: vector wideing integer reduction instructions
  target/riscv: vector single-width floating-point reduction
    instructions
  target/riscv: vector widening floating-point reduction instructions
  target/riscv: vector mask-register logical instructions
  target/riscv: vector mask population count vmpopc
  target/riscv: vmfirst find-first-set mask bit
  target/riscv: set-X-first mask bit
  target/riscv: vector iota instruction
  target/riscv: vector element index instruction
  target/riscv: integer extract instruction
  target/riscv: integer scalar move instruction
  target/riscv: floating-point scalar move instructions
  target/riscv: vector slide instructions
  target/riscv: vector register gather instruction
  target/riscv: vector compress instruction
  target/riscv: configure and turn on vector extension from command line

 target/riscv/Makefile.objs              |    2 +-
 target/riscv/cpu.c                      |   49 +
 target/riscv/cpu.h                      |   82 +-
 target/riscv/cpu_bits.h                 |   15 +
 target/riscv/csr.c                      |   82 +-
 target/riscv/fpu_helper.c               |   52 +-
 target/riscv/helper.h                   | 1068 +++++
 target/riscv/insn32-64.decode           |   11 +
 target/riscv/insn32.decode              |  372 ++
 target/riscv/insn_trans/trans_rvv.inc.c | 2884 +++++++++++++
 target/riscv/internals.h                |   44 +
 target/riscv/translate.c                |   27 +-
 target/riscv/vector_helper.c            | 4898 +++++++++++++++++++++++
 13 files changed, 9537 insertions(+), 49 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
 create mode 100644 target/riscv/internals.h
 create mode 100644 target/riscv/vector_helper.c

-- 
2.23.0


Re: [PATCH v8 00/62] target/riscv: support vector extension v0.7.1

Posted by no-reply@patchew.org 1 week ago
Patchew URL: https://patchew.org/QEMU/20200521094413.10425-1-zhiwei_liu@c-sky.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 20200521094413.10425-1-zhiwei_liu@c-sky.com
Subject: [PATCH v8 00/62] target/riscv: support vector extension v0.7.1
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20200508062456.23344-1-philmd@redhat.com -> patchew/20200508062456.23344-1-philmd@redhat.com
 * [new tag]         patchew/20200521124535.5329-1-pbonzini@redhat.com -> patchew/20200521124535.5329-1-pbonzini@redhat.com
Switched to a new branch 'test'
f9abd33 target/riscv: configure and turn on vector extension from command line
e088614 target/riscv: vector compress instruction
d1b3db1 target/riscv: vector register gather instruction
a5c33e2 target/riscv: vector slide instructions
83d6aa1 target/riscv: floating-point scalar move instructions
c194278 target/riscv: integer scalar move instruction
6e96feb target/riscv: integer extract instruction
cc30923 target/riscv: vector element index instruction
45ebe3f target/riscv: vector iota instruction
6432ffc target/riscv: set-X-first mask bit
1cca4dd target/riscv: vmfirst find-first-set mask bit
db3707d target/riscv: vector mask population count vmpopc
4b69dd9 target/riscv: vector mask-register logical instructions
de67e1f target/riscv: vector widening floating-point reduction instructions
99c09b5 target/riscv: vector single-width floating-point reduction instructions
4f84068 target/riscv: vector wideing integer reduction instructions
fdecd19 target/riscv: vector single-width integer reduction instructions
97e2de2 target/riscv: narrowing floating-point/integer type-convert instructions
0685b2e target/riscv: widening floating-point/integer type-convert instructions
76ad956 target/riscv: vector floating-point/integer type-convert instructions
52398ce target/riscv: vector floating-point merge instructions
9c05ec5 target/riscv: vector floating-point classify instructions
b4b7f43 target/riscv: vector floating-point compare instructions
c683aeb target/riscv: vector floating-point sign-injection instructions
4f7d197 target/riscv: vector floating-point min/max instructions
734ab9f target/riscv: vector floating-point square-root instruction
a8aee4f target/riscv: vector widening floating-point fused multiply-add instructions
f395b2d target/riscv: vector single-width floating-point fused multiply-add instructions
3a09cfc target/riscv: vector widening floating-point multiply
e139ba0 target/riscv: vector single-width floating-point multiply/divide instructions
1d91e29 target/riscv: vector widening floating-point add/subtract instructions
3a0ce08 target/riscv: vector single-width floating-point add/subtract instructions
d79a027 target/riscv: Update fp_status when float rounding mode changes
06e36a5 target/riscv: vector narrowing fixed-point clip instructions
8999be2 target/riscv: vector single-width scaling shift instructions
962977c target/riscv: vector widening saturating scaled multiply-add
11cb3b6 target/riscv: vector single-width fractional multiply with rounding and saturation
5952065 target/riscv: vector single-width averaging add and subtract
15cb820 target/riscv: vector single-width saturating add and subtract
82b5f92 target/riscv: vector integer merge and move instructions
62a3fc7 target/riscv: vector widening integer multiply-add instructions
68cd050 target/riscv: vector single-width integer multiply-add instructions
b573c82 target/riscv: vector widening integer multiply instructions
1137624 target/riscv: vector integer divide instructions
2f5acaf target/riscv: vector single-width integer multiply instructions
75ddc24 target/riscv: vector integer min/max instructions
584b570 target/riscv: vector integer comparison instructions
0a1111d target/riscv: vector narrowing integer right shift instructions
8790e02 target/riscv: vector single-width bit shift instructions
924f10b target/riscv: vector bitwise logical instructions
d5b75ff target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
b965818 target/riscv: vector widening integer add and subtract
7a60896 target/riscv: vector single-width integer add and subtract
d02648b target/riscv: add vector amo operations
5e0f9b6 target/riscv: add fault-only-first unit stride load
d60d784 target/riscv: add vector index load and store instructions
fe14d75 target/riscv: add vector stride load and store instructions
f686f76 target/riscv: add an internals.h header
f5e6072 target/riscv: add vector configure instruction
a05c6f8 target/riscv: support vector extension csr
cad7fb3 target/riscv: implementation-defined constant parameters
e62d7b0 target/riscv: add vector extension field in CPURISCVState

=== OUTPUT BEGIN ===
1/62 Checking commit e62d7b0253e8 (target/riscv: add vector extension field in CPURISCVState)
2/62 Checking commit cad7fb36cdd5 (target/riscv: implementation-defined constant parameters)
3/62 Checking commit a05c6f86f429 (target/riscv: support vector extension csr)
4/62 Checking commit f5e607241dd8 (target/riscv: add vector configure instruction)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#160: 
new file mode 100644

total: 0 errors, 1 warnings, 294 lines checked

Patch 4/62 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/62 Checking commit f686f76d75bf (target/riscv: add an internals.h header)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16: 
new file mode 100644

total: 0 errors, 1 warnings, 24 lines checked

Patch 5/62 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/62 Checking commit fe14d753e891 (target/riscv: add vector stride load and store instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#274: FILE: target/riscv/insn_trans/trans_rvv.inc.c:143:
+static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
                                                         ^

ERROR: spaces required around that '*' (ctx:WxV)
#835: FILE: target/riscv/vector_helper.c:260:
+                 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                    ^

ERROR: spaces required around that '*' (ctx:WxV)
#835: FILE: target/riscv/vector_helper.c:260:
+                 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                                         ^

ERROR: spaces required around that '*' (ctx:WxV)
#937: FILE: target/riscv/vector_helper.c:362:
+             vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                ^

ERROR: spaces required around that '*' (ctx:WxV)
#937: FILE: target/riscv/vector_helper.c:362:
+             vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                                     ^

total: 5 errors, 0 warnings, 982 lines checked

Patch 6/62 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

7/62 Checking commit d60d78401e2a (target/riscv: add vector index load and store instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#251: FILE: target/riscv/vector_helper.c:487:
+                vext_ldst_elem_fn *ldst_elem,
                                   ^

ERROR: spaces required around that '*' (ctx:WxV)
#252: FILE: target/riscv/vector_helper.c:488:
+                clear_fn *clear_elem,
                          ^

total: 2 errors, 0 warnings, 308 lines checked

Patch 7/62 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

8/62 Checking commit 5e0f9b62d751 (target/riscv: add fault-only-first unit stride load)
ERROR: spaces required around that '*' (ctx:WxV)
#161: FILE: target/riscv/vector_helper.c:587:
+          vext_ldst_elem_fn *ldst_elem,
                             ^

ERROR: spaces required around that '*' (ctx:WxV)
#162: FILE: target/riscv/vector_helper.c:588:
+          clear_fn *clear_elem,
                    ^

total: 2 errors, 0 warnings, 226 lines checked

Patch 8/62 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

9/62 Checking commit d02648b58b16 (target/riscv: add vector amo operations)
ERROR: spaces required around that '*' (ctx:WxV)
#365: FILE: target/riscv/vector_helper.c:769:
+                  vext_amo_noatomic_fn *noatomic_op,
                                        ^

ERROR: spaces required around that '*' (ctx:WxV)
#366: FILE: target/riscv/vector_helper.c:770:
+                  clear_fn *clear_elem,
                            ^

total: 2 errors, 0 warnings, 382 lines checked

Patch 9/62 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

10/62 Checking commit 7a60896f475f (target/riscv: vector single-width integer add and subtract)
ERROR: spaces required around that '*' (ctx:WxV)
#93: FILE: target/riscv/insn_trans/trans_rvv.inc.c:781:
+static bool opivv_check(DisasContext *s, arg_rmrr *a)
                                                   ^

ERROR: spaces required around that '*' (ctx:WxV)
#425: FILE: target/riscv/vector_helper.c:875:
+                       opivv2_fn *fn, clear_fn *clearfn)
                                  ^

ERROR: spaces required around that '*' (ctx:WxV)
#425: FILE: target/riscv/vector_helper.c:875:
+                       opivv2_fn *fn, clear_fn *clearfn)
                                                ^

ERROR: spaces required around that '*' (ctx:WxV)
#490: FILE: target/riscv/vector_helper.c:940:
+                       opivx2_fn fn, clear_fn *clearfn)
                                               ^

total: 4 errors, 0 warnings, 535 lines checked

Patch 10/62 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

11/62 Checking commit b965818e8bdf (target/riscv: vector widening integer add and subtract)
12/62 Checking commit d5b75ff0860d (target/riscv: vector integer add-with-carry / subtract-with-borrow instructions)
13/62 Checking commit 924f10b70e12 (target/riscv: vector bitwise logical instructions)
14/62 Checking commit 8790e02693f1 (target/riscv: vector single-width bit shift instructions)
15/62 Checking commit 0a1111deba32 (target/riscv: vector narrowing integer right shift instructions)
16/62 Checking commit 584b5705fb10 (target/riscv: vector integer comparison instructions)
17/62 Checking commit 75ddc247639c (target/riscv: vector integer min/max instructions)
18/62 Checking commit 2f5acaffdb60 (target/riscv: vector single-width integer multiply instructions)
19/62 Checking commit 11376240ecbd (target/riscv: vector integer divide instructions)
20/62 Checking commit b573c827e511 (target/riscv: vector widening integer multiply instructions)
21/62 Checking commit 68cd0509154c (target/riscv: vector single-width integer multiply-add instructions)
22/62 Checking commit 62a3fc706fe9 (target/riscv: vector widening integer multiply-add instructions)
23/62 Checking commit 82b5f9298281 (target/riscv: vector integer merge and move instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#72: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1623:
+static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
                                                        ^

total: 1 errors, 0 warnings, 246 lines checked

Patch 23/62 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

24/62 Checking commit 15cb82094af3 (target/riscv: vector single-width saturating add and subtract)
25/62 Checking commit 5952065cfd7b (target/riscv: vector single-width averaging add and subtract)
26/62 Checking commit 11cb3b663972 (target/riscv: vector single-width fractional multiply with rounding and saturation)
27/62 Checking commit 962977c9f358 (target/riscv: vector widening saturating scaled multiply-add)
28/62 Checking commit 8999be27a01d (target/riscv: vector single-width scaling shift instructions)
29/62 Checking commit 06e36a5067dc (target/riscv: vector narrowing fixed-point clip instructions)
30/62 Checking commit d79a0275fbb7 (target/riscv: Update fp_status when float rounding mode changes)
31/62 Checking commit 3a0ce08c8d29 (target/riscv: vector single-width floating-point add/subtract instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#281: FILE: target/riscv/vector_helper.c:3259:
+static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
                                                                   ^

total: 1 errors, 0 warnings, 269 lines checked

Patch 31/62 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

32/62 Checking commit 1d91e29df22f (target/riscv: vector widening floating-point add/subtract instructions)
33/62 Checking commit e139ba0283f0 (target/riscv: vector single-width floating-point multiply/divide instructions)
34/62 Checking commit 3a09cfc1cb43 (target/riscv: vector widening floating-point multiply)
35/62 Checking commit f395b2dda5b6 (target/riscv: vector single-width floating-point fused multiply-add instructions)
36/62 Checking commit a8aee4f5af45 (target/riscv: vector widening floating-point fused multiply-add instructions)
37/62 Checking commit 734ab9f1a0f8 (target/riscv: vector floating-point square-root instruction)
ERROR: spaces required around that '*' (ctx:WxV)
#67: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2093:
+static bool opfv_check(DisasContext *s, arg_rmr *a)
                                                 ^

ERROR: spaces required around that '*' (ctx:WxV)
#77: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2103:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 119 lines checked

Patch 37/62 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

38/62 Checking commit 4f7d1979bc97 (target/riscv: vector floating-point min/max instructions)
39/62 Checking commit c683aebeeb2e (target/riscv: vector floating-point sign-injection instructions)
40/62 Checking commit b4b7f43be247 (target/riscv: vector floating-point compare instructions)
41/62 Checking commit 9c05ec5445dc (target/riscv: vector floating-point classify instructions)
42/62 Checking commit 52398cea5e34 (target/riscv: vector floating-point merge instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#47: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2184:
+static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
                                                          ^

total: 1 errors, 0 warnings, 83 lines checked

Patch 42/62 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

43/62 Checking commit 76ad956bcbe4 (target/riscv: vector floating-point/integer type-convert instructions)
44/62 Checking commit 0685b2e1a927 (target/riscv: widening floating-point/integer type-convert instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#61: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2231:
+static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
                                                       ^

ERROR: spaces required around that '*' (ctx:WxV)
#73: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2243:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 120 lines checked

Patch 44/62 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

45/62 Checking commit 97e2de2ade10 (target/riscv: narrowing floating-point/integer type-convert instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#61: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2278:
+static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
                                                        ^

ERROR: spaces required around that '*' (ctx:WxV)
#73: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2290:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 117 lines checked

Patch 45/62 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

46/62 Checking commit fdecd19f05c9 (target/riscv: vector single-width integer reduction instructions)
47/62 Checking commit 4f840681273f (target/riscv: vector wideing integer reduction instructions)
48/62 Checking commit 99c09b56c650 (target/riscv: vector single-width floating-point reduction instructions)
49/62 Checking commit de67e1f879cf (target/riscv: vector widening floating-point reduction instructions)
50/62 Checking commit 4b69dd9d111f (target/riscv: vector mask-register logical instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#62: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2355:
+static bool trans_##NAME(DisasContext *s, arg_r *a)                \
                                                 ^

total: 1 errors, 0 warnings, 107 lines checked

Patch 50/62 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

51/62 Checking commit db3707d48a59 (target/riscv: vector mask population count vmpopc)
ERROR: spaces required around that '*' (ctx:WxV)
#43: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2385:
+static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
                                                     ^

total: 1 errors, 0 warnings, 70 lines checked

Patch 51/62 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

52/62 Checking commit 1cca4dd763db (target/riscv: vmfirst find-first-set mask bit)
53/62 Checking commit 6432ffc3393f (target/riscv: set-X-first mask bit)
54/62 Checking commit 45ebe3f50f88 (target/riscv: vector iota instruction)
ERROR: spaces required around that '*' (ctx:WxV)
#46: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2477:
+static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
                                                        ^

total: 1 errors, 0 warnings, 77 lines checked

Patch 54/62 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

55/62 Checking commit cc309232863e (target/riscv: vector element index instruction)
56/62 Checking commit 6e96feb89207 (target/riscv: integer extract instruction)
57/62 Checking commit c19427846645 (target/riscv: integer scalar move instruction)
58/62 Checking commit 83d6aa140f8c (target/riscv: floating-point scalar move instructions)
59/62 Checking commit a5c33e280ce7 (target/riscv: vector slide instructions)
60/62 Checking commit d1b3db18ac7e (target/riscv: vector register gather instruction)
61/62 Checking commit e088614f8998 (target/riscv: vector compress instruction)
62/62 Checking commit f9abd33d2f0d (target/riscv: configure and turn on vector extension from command line)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20200521094413.10425-1-zhiwei_liu@c-sky.com/testing.checkpatch/?type=message.
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