[PULL 00/34] target-arm queue
[PULL 00/72] target-arm queue
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The following changes since commit c88f1ffc19e38008a1c33ae039482a860aa7418c:
1
First arm pullreq of the cycle; this is mostly my softfloat NaN
2
handling series. (Lots more in my to-review queue, but I don't
3
like pullreqs growing too close to a hundred patches at a time :-))
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4
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Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2020-05-08 14:29:18 +0100)
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thanks
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-- PMM
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The following changes since commit 97f2796a3736ed37a1b85dc1c76a6c45b829dd17:
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10
Open 10.0 development tree (2024-12-10 17:41:17 +0000)
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11
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200511
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241211
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15
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for you to fetch changes up to 7e17d50ebd359ee5fa3d65d7fdc0fe0336d60694:
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for you to fetch changes up to 1abe28d519239eea5cf9620bb13149423e5665f8:
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17
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target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed) (2020-05-11 14:22:54 +0100)
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MAINTAINERS: Add correct email address for Vikram Garhwal (2024-12-11 15:31:09 +0000)
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19
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----------------------------------------------------------------
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----------------------------------------------------------------
14
target-arm queue:
21
target-arm queue:
15
aspeed: Add boot stub for smp booting
22
* hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs
16
target/arm: Drop access_el3_aa32ns_aa64any()
23
* fpu: Make muladd NaN handling runtime-selected, not compile-time
17
aspeed: Support AST2600A1 silicon revision
24
* fpu: Make default NaN pattern runtime-selected, not compile-time
18
aspeed: sdmc: Implement AST2600 locking behaviour
25
* fpu: Minor NaN-related cleanups
19
nrf51: Tracing cleanups
26
* MAINTAINERS: email address updates
20
target/arm: Improve handling of SVE loads and stores
21
target/arm: Don't show TCG-only CPUs in KVM-only QEMU builds
22
hw/arm/musicpal: Map the UART devices unconditionally
23
target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)
24
target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
25
27
26
----------------------------------------------------------------
28
----------------------------------------------------------------
27
Edgar E. Iglesias (1):
29
Bernhard Beschow (5):
28
target/arm: Drop access_el3_aa32ns_aa64any()
30
hw/net/lan9118: Extract lan9118_phy
31
hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
32
hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
33
hw/net/lan9118_phy: Reuse MII constants
34
hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
29
35
30
Joel Stanley (3):
36
Leif Lindholm (1):
31
aspeed: Add boot stub for smp booting
37
MAINTAINERS: update email address for Leif Lindholm
32
aspeed: Support AST2600A1 silicon revision
33
aspeed: sdmc: Implement AST2600 locking behaviour
34
38
35
Philippe Mathieu-Daudé (8):
39
Peter Maydell (54):
36
hw/arm/nrf51: Add NRF51_PERIPHERAL_SIZE definition
40
fpu: handle raising Invalid for infzero in pick_nan_muladd
37
hw/timer/nrf51_timer: Display timer ID in trace events
41
fpu: Check for default_nan_mode before calling pickNaNMulAdd
38
hw/timer/nrf51_timer: Add trace event of counter value update
42
softfloat: Allow runtime choice of inf * 0 + NaN result
39
target/arm/kvm: Inline set_feature() calls
43
tests/fp: Explicitly set inf-zero-nan rule
40
target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]
44
target/arm: Set FloatInfZeroNaNRule explicitly
41
target/arm/cpu: Restrict v8M IDAU interface to Aarch32 CPUs
45
target/s390: Set FloatInfZeroNaNRule explicitly
42
target/arm: Restrict TCG cpus to TCG accel
46
target/ppc: Set FloatInfZeroNaNRule explicitly
43
hw/arm/musicpal: Map the UART devices unconditionally
47
target/mips: Set FloatInfZeroNaNRule explicitly
48
target/sparc: Set FloatInfZeroNaNRule explicitly
49
target/xtensa: Set FloatInfZeroNaNRule explicitly
50
target/x86: Set FloatInfZeroNaNRule explicitly
51
target/loongarch: Set FloatInfZeroNaNRule explicitly
52
target/hppa: Set FloatInfZeroNaNRule explicitly
53
softfloat: Pass have_snan to pickNaNMulAdd
54
softfloat: Allow runtime choice of NaN propagation for muladd
55
tests/fp: Explicitly set 3-NaN propagation rule
56
target/arm: Set Float3NaNPropRule explicitly
57
target/loongarch: Set Float3NaNPropRule explicitly
58
target/ppc: Set Float3NaNPropRule explicitly
59
target/s390x: Set Float3NaNPropRule explicitly
60
target/sparc: Set Float3NaNPropRule explicitly
61
target/mips: Set Float3NaNPropRule explicitly
62
target/xtensa: Set Float3NaNPropRule explicitly
63
target/i386: Set Float3NaNPropRule explicitly
64
target/hppa: Set Float3NaNPropRule explicitly
65
fpu: Remove use_first_nan field from float_status
66
target/m68k: Don't pass NULL float_status to floatx80_default_nan()
67
softfloat: Create floatx80 default NaN from parts64_default_nan
68
target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
69
target/m68k: In frem helper, initialize local float_status from env->fp_status
70
target/m68k: Init local float_status from env fp_status in gdb get/set reg
71
target/sparc: Initialize local scratch float_status from env->fp_status
72
target/ppc: Use env->fp_status in helper_compute_fprf functions
73
fpu: Allow runtime choice of default NaN value
74
tests/fp: Set default NaN pattern explicitly
75
target/microblaze: Set default NaN pattern explicitly
76
target/i386: Set default NaN pattern explicitly
77
target/hppa: Set default NaN pattern explicitly
78
target/alpha: Set default NaN pattern explicitly
79
target/arm: Set default NaN pattern explicitly
80
target/loongarch: Set default NaN pattern explicitly
81
target/m68k: Set default NaN pattern explicitly
82
target/mips: Set default NaN pattern explicitly
83
target/openrisc: Set default NaN pattern explicitly
84
target/ppc: Set default NaN pattern explicitly
85
target/sh4: Set default NaN pattern explicitly
86
target/rx: Set default NaN pattern explicitly
87
target/s390x: Set default NaN pattern explicitly
88
target/sparc: Set default NaN pattern explicitly
89
target/xtensa: Set default NaN pattern explicitly
90
target/hexagon: Set default NaN pattern explicitly
91
target/riscv: Set default NaN pattern explicitly
92
target/tricore: Set default NaN pattern explicitly
93
fpu: Remove default handling for dnan_pattern
44
94
45
Richard Henderson (21):
95
Richard Henderson (11):
46
exec: Add block comments for watchpoint routines
96
target/arm: Copy entire float_status in is_ebf
47
exec: Fix cpu_watchpoint_address_matches address length
97
softfloat: Inline pickNaNMulAdd
48
accel/tcg: Add block comment for probe_access
98
softfloat: Use goto for default nan case in pick_nan_muladd
49
accel/tcg: Adjust probe_access call to page_check_range
99
softfloat: Remove which from parts_pick_nan_muladd
50
accel/tcg: Add probe_access_flags
100
softfloat: Pad array size in pick_nan_muladd
51
accel/tcg: Add endian-specific cpu_{ld, st}* operations
101
softfloat: Move propagateFloatx80NaN to softfloat.c
52
target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn
102
softfloat: Use parts_pick_nan in propagateFloatx80NaN
53
target/arm: Drop manual handling of set/clear_helper_retaddr
103
softfloat: Inline pickNaN
54
target/arm: Add sve infrastructure for page lookup
104
softfloat: Share code between parts_pick_nan cases
55
target/arm: Adjust interface of sve_ld1_host_fn
105
softfloat: Sink frac_cmp in parts_pick_nan until needed
56
target/arm: Use SVEContLdSt in sve_ld1_r
106
softfloat: Replace WHICH with RET in parts_pick_nan
57
target/arm: Handle watchpoints in sve_ld1_r
58
target/arm: Use SVEContLdSt for multi-register contiguous loads
59
target/arm: Update contiguous first-fault and no-fault loads
60
target/arm: Use SVEContLdSt for contiguous stores
61
target/arm: Reuse sve_probe_page for gather first-fault loads
62
target/arm: Reuse sve_probe_page for scatter stores
63
target/arm: Reuse sve_probe_page for gather loads
64
target/arm: Remove sve_memopidx
65
target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
66
target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)
67
107
68
Thomas Huth (1):
108
Vikram Garhwal (1):
69
target/arm: Make set_feature() available for other files
109
MAINTAINERS: Add correct email address for Vikram Garhwal
70
110
71
docs/devel/loads-stores.rst | 39 +-
111
MAINTAINERS | 4 +-
72
include/exec/cpu-all.h | 13 +-
112
include/fpu/softfloat-helpers.h | 38 +++-
73
include/exec/cpu_ldst.h | 283 +++--
113
include/fpu/softfloat-types.h | 89 +++++++-
74
include/exec/exec-all.h | 39 +
114
include/hw/net/imx_fec.h | 9 +-
75
include/hw/arm/nrf51.h | 3 +-
115
include/hw/net/lan9118_phy.h | 37 ++++
76
include/hw/core/cpu.h | 23 +
116
include/hw/net/mii.h | 6 +
77
include/hw/i2c/microbit_i2c.h | 2 +-
117
target/mips/fpu_helper.h | 20 ++
78
include/hw/misc/aspeed_scu.h | 1 +
118
target/sparc/helper.h | 4 +-
79
include/hw/timer/nrf51_timer.h | 1 +
119
fpu/softfloat.c | 19 ++
80
target/arm/cpu.h | 10 +
120
hw/net/imx_fec.c | 146 ++------------
81
target/arm/helper-sve.h | 45 +-
121
hw/net/lan9118.c | 137 ++-----------
82
target/arm/internals.h | 5 -
122
hw/net/lan9118_phy.c | 222 ++++++++++++++++++++
83
accel/tcg/cputlb.c | 413 ++++---
123
linux-user/arm/nwfpe/fpa11.c | 5 +
84
accel/tcg/user-exec.c | 256 ++++-
124
target/alpha/cpu.c | 2 +
85
exec.c | 2 +-
125
target/arm/cpu.c | 10 +
86
hw/arm/aspeed.c | 73 +-
126
target/arm/tcg/vec_helper.c | 20 +-
87
hw/arm/aspeed_ast2600.c | 6 +-
127
target/hexagon/cpu.c | 2 +
88
hw/arm/musicpal.c | 12 +-
128
target/hppa/fpu_helper.c | 12 ++
89
hw/arm/nrf51_soc.c | 9 +-
129
target/i386/tcg/fpu_helper.c | 12 ++
90
hw/i2c/microbit_i2c.c | 2 +-
130
target/loongarch/tcg/fpu_helper.c | 14 +-
91
hw/misc/aspeed_scu.c | 11 +-
131
target/m68k/cpu.c | 14 +-
92
hw/misc/aspeed_sdmc.c | 55 +-
132
target/m68k/fpu_helper.c | 6 +-
93
hw/timer/nrf51_timer.c | 14 +-
133
target/m68k/helper.c | 6 +-
94
target/arm/cpu.c | 662 +----------
134
target/microblaze/cpu.c | 2 +
95
target/arm/cpu64.c | 18 +-
135
target/mips/msa.c | 10 +
96
target/arm/cpu_tcg.c | 664 +++++++++++
136
target/openrisc/cpu.c | 2 +
97
target/arm/helper.c | 30 +-
137
target/ppc/cpu_init.c | 19 ++
98
target/arm/kvm32.c | 13 +-
138
target/ppc/fpu_helper.c | 3 +-
99
target/arm/kvm64.c | 22 +-
139
target/riscv/cpu.c | 2 +
100
target/arm/sve_helper.c | 2398 +++++++++++++++++++++-------------------
140
target/rx/cpu.c | 2 +
101
target/arm/translate-sve.c | 93 +-
141
target/s390x/cpu.c | 5 +
102
hw/timer/trace-events | 5 +-
142
target/sh4/cpu.c | 2 +
103
target/arm/Makefile.objs | 1 +
143
target/sparc/cpu.c | 6 +
104
33 files changed, 2975 insertions(+), 2248 deletions(-)
144
target/sparc/fop_helper.c | 8 +-
105
create mode 100644 target/arm/cpu_tcg.c
145
target/sparc/translate.c | 4 +-
106
146
target/tricore/helper.c | 2 +
147
target/xtensa/cpu.c | 4 +
148
target/xtensa/fpu_helper.c | 3 +-
149
tests/fp/fp-bench.c | 7 +
150
tests/fp/fp-test-log2.c | 1 +
151
tests/fp/fp-test.c | 7 +
152
fpu/softfloat-parts.c.inc | 152 +++++++++++---
153
fpu/softfloat-specialize.c.inc | 412 ++------------------------------------
154
.mailmap | 5 +-
155
hw/net/Kconfig | 5 +
156
hw/net/meson.build | 1 +
157
hw/net/trace-events | 10 +-
158
47 files changed, 778 insertions(+), 730 deletions(-)
159
create mode 100644 include/hw/net/lan9118_phy.h
160
create mode 100644 hw/net/lan9118_phy.c
diff view generated by jsdifflib
[PULL 27/34] target/arm/kvm: Inline set_feature() calls
[PULL 01/72] hw/net/lan9118: Extract lan9118_phy
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
We want to move the inlined declarations of set_feature()
3
A very similar implementation of the same device exists in imx_fec. Prepare for
4
from cpu*.c to cpu.h. To avoid clashing with the KVM
4
a common implementation by extracting a device model into its own files.
5
declarations, inline the few KVM calls.
6
5
7
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
6
Some migration state has been moved into the new device model which breaks
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
migration compatibility for the following machines:
9
Message-id: 20200504172448.9402-2-philmd@redhat.com
8
* smdkc210
9
* realview-*
10
* vexpress-*
11
* kzm
12
* mps2-*
13
14
While breaking migration ABI, fix the size of the MII registers to be 16 bit,
15
as defined by IEEE 802.3u.
16
17
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
18
Tested-by: Guenter Roeck <linux@roeck-us.net>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Message-id: 20241102125724.532843-2-shentey@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
22
---
12
target/arm/kvm32.c | 13 ++++---------
23
include/hw/net/lan9118_phy.h | 37 ++++++++
13
target/arm/kvm64.c | 22 ++++++----------------
24
hw/net/lan9118.c | 137 +++++-----------------------
14
2 files changed, 10 insertions(+), 25 deletions(-)
25
hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++
26
hw/net/Kconfig | 4 +
27
hw/net/meson.build | 1 +
28
5 files changed, 233 insertions(+), 115 deletions(-)
29
create mode 100644 include/hw/net/lan9118_phy.h
30
create mode 100644 hw/net/lan9118_phy.c
15
31
16
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
32
diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h
33
new file mode 100644
34
index XXXXXXX..XXXXXXX
35
--- /dev/null
36
+++ b/include/hw/net/lan9118_phy.h
37
@@ -XXX,XX +XXX,XX @@
38
+/*
39
+ * SMSC LAN9118 PHY emulation
40
+ *
41
+ * Copyright (c) 2009 CodeSourcery, LLC.
42
+ * Written by Paul Brook
43
+ *
44
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
45
+ * See the COPYING file in the top-level directory.
46
+ */
47
+
48
+#ifndef HW_NET_LAN9118_PHY_H
49
+#define HW_NET_LAN9118_PHY_H
50
+
51
+#include "qom/object.h"
52
+#include "hw/sysbus.h"
53
+
54
+#define TYPE_LAN9118_PHY "lan9118-phy"
55
+OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY)
56
+
57
+typedef struct Lan9118PhyState {
58
+ SysBusDevice parent_obj;
59
+
60
+ uint16_t status;
61
+ uint16_t control;
62
+ uint16_t advertise;
63
+ uint16_t ints;
64
+ uint16_t int_mask;
65
+ qemu_irq irq;
66
+ bool link_down;
67
+} Lan9118PhyState;
68
+
69
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down);
70
+void lan9118_phy_reset(Lan9118PhyState *s);
71
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg);
72
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val);
73
+
74
+#endif
75
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
17
index XXXXXXX..XXXXXXX 100644
76
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/kvm32.c
77
--- a/hw/net/lan9118.c
19
+++ b/target/arm/kvm32.c
78
+++ b/hw/net/lan9118.c
20
@@ -XXX,XX +XXX,XX @@
79
@@ -XXX,XX +XXX,XX @@
21
#include "internals.h"
80
#include "net/net.h"
22
#include "qemu/log.h"
81
#include "net/eth.h"
23
82
#include "hw/irq.h"
24
-static inline void set_feature(uint64_t *features, int feature)
83
+#include "hw/net/lan9118_phy.h"
84
#include "hw/net/lan9118.h"
85
#include "hw/ptimer.h"
86
#include "hw/qdev-properties.h"
87
@@ -XXX,XX +XXX,XX @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
88
#define MAC_CR_RXEN 0x00000004
89
#define MAC_CR_RESERVED 0x7f404213
90
91
-#define PHY_INT_ENERGYON 0x80
92
-#define PHY_INT_AUTONEG_COMPLETE 0x40
93
-#define PHY_INT_FAULT 0x20
94
-#define PHY_INT_DOWN 0x10
95
-#define PHY_INT_AUTONEG_LP 0x08
96
-#define PHY_INT_PARFAULT 0x04
97
-#define PHY_INT_AUTONEG_PAGE 0x02
98
-
99
#define GPT_TIMER_EN 0x20000000
100
101
/*
102
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
103
uint32_t mac_mii_data;
104
uint32_t mac_flow;
105
106
- uint32_t phy_status;
107
- uint32_t phy_control;
108
- uint32_t phy_advertise;
109
- uint32_t phy_int;
110
- uint32_t phy_int_mask;
111
+ Lan9118PhyState mii;
112
+ IRQState mii_irq;
113
114
int32_t eeprom_writable;
115
uint8_t eeprom[128];
116
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
117
118
static const VMStateDescription vmstate_lan9118 = {
119
.name = "lan9118",
120
- .version_id = 2,
121
- .minimum_version_id = 1,
122
+ .version_id = 3,
123
+ .minimum_version_id = 3,
124
.fields = (const VMStateField[]) {
125
VMSTATE_PTIMER(timer, lan9118_state),
126
VMSTATE_UINT32(irq_cfg, lan9118_state),
127
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118 = {
128
VMSTATE_UINT32(mac_mii_acc, lan9118_state),
129
VMSTATE_UINT32(mac_mii_data, lan9118_state),
130
VMSTATE_UINT32(mac_flow, lan9118_state),
131
- VMSTATE_UINT32(phy_status, lan9118_state),
132
- VMSTATE_UINT32(phy_control, lan9118_state),
133
- VMSTATE_UINT32(phy_advertise, lan9118_state),
134
- VMSTATE_UINT32(phy_int, lan9118_state),
135
- VMSTATE_UINT32(phy_int_mask, lan9118_state),
136
VMSTATE_INT32(eeprom_writable, lan9118_state),
137
VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
138
VMSTATE_INT32(tx_fifo_size, lan9118_state),
139
@@ -XXX,XX +XXX,XX @@ static void lan9118_reload_eeprom(lan9118_state *s)
140
lan9118_mac_changed(s);
141
}
142
143
-static void phy_update_irq(lan9118_state *s)
144
+static void lan9118_update_irq(void *opaque, int n, int level)
145
{
146
- if (s->phy_int & s->phy_int_mask) {
147
+ lan9118_state *s = opaque;
148
+
149
+ if (level) {
150
s->int_sts |= PHY_INT;
151
} else {
152
s->int_sts &= ~PHY_INT;
153
@@ -XXX,XX +XXX,XX @@ static void phy_update_irq(lan9118_state *s)
154
lan9118_update(s);
155
}
156
157
-static void phy_update_link(lan9118_state *s)
25
-{
158
-{
26
- *features |= 1ULL << feature;
159
- /* Autonegotiation status mirrors link status. */
160
- if (qemu_get_queue(s->nic)->link_down) {
161
- s->phy_status &= ~0x0024;
162
- s->phy_int |= PHY_INT_DOWN;
163
- } else {
164
- s->phy_status |= 0x0024;
165
- s->phy_int |= PHY_INT_ENERGYON;
166
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
167
- }
168
- phy_update_irq(s);
27
-}
169
-}
28
-
170
-
29
static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
171
static void lan9118_set_link(NetClientState *nc)
30
{
172
{
31
struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
173
- phy_update_link(qemu_get_nic_opaque(nc));
32
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
174
-}
33
* timers; this in turn implies most of the other feature
175
-
34
* bits, but a few must be tested.
176
-static void phy_reset(lan9118_state *s)
35
*/
177
-{
36
- set_feature(&features, ARM_FEATURE_V7VE);
178
- s->phy_status = 0x7809;
37
- set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
179
- s->phy_control = 0x3000;
38
+ features |= 1ULL << ARM_FEATURE_V7VE;
180
- s->phy_advertise = 0x01e1;
39
+ features |= 1ULL << ARM_FEATURE_GENERIC_TIMER;
181
- s->phy_int_mask = 0;
40
182
- s->phy_int = 0;
41
if (extract32(id_pfr0, 12, 4) == 1) {
183
- phy_update_link(s);
42
- set_feature(&features, ARM_FEATURE_THUMB2EE);
184
+ lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii,
43
+ features |= 1ULL << ARM_FEATURE_THUMB2EE;
185
+ nc->link_down);
44
}
186
}
45
if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
187
46
- set_feature(&features, ARM_FEATURE_NEON);
188
static void lan9118_reset(DeviceState *d)
47
+ features |= 1ULL << ARM_FEATURE_NEON;
189
@@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d)
48
}
190
s->read_word_n = 0;
49
191
s->write_word_n = 0;
50
ahcf->features = features;
192
51
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
193
- phy_reset(s);
52
index XXXXXXX..XXXXXXX 100644
194
-
53
--- a/target/arm/kvm64.c
195
s->eeprom_writable = 0;
54
+++ b/target/arm/kvm64.c
196
lan9118_reload_eeprom(s);
55
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
197
}
198
@@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s)
199
uint32_t status;
200
201
/* FIXME: Honor TX disable, and allow queueing of packets. */
202
- if (s->phy_control & 0x4000) {
203
+ if (s->mii.control & 0x4000) {
204
/* This assumes the receive routine doesn't touch the VLANClient. */
205
qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
206
} else {
207
@@ -XXX,XX +XXX,XX @@ static void tx_fifo_push(lan9118_state *s, uint32_t val)
56
}
208
}
57
}
209
}
58
210
59
-static inline void set_feature(uint64_t *features, int feature)
211
-static uint32_t do_phy_read(lan9118_state *s, int reg)
60
-{
212
-{
61
- *features |= 1ULL << feature;
213
- uint32_t val;
214
-
215
- switch (reg) {
216
- case 0: /* Basic Control */
217
- return s->phy_control;
218
- case 1: /* Basic Status */
219
- return s->phy_status;
220
- case 2: /* ID1 */
221
- return 0x0007;
222
- case 3: /* ID2 */
223
- return 0xc0d1;
224
- case 4: /* Auto-neg advertisement */
225
- return s->phy_advertise;
226
- case 5: /* Auto-neg Link Partner Ability */
227
- return 0x0f71;
228
- case 6: /* Auto-neg Expansion */
229
- return 1;
230
- /* TODO 17, 18, 27, 29, 30, 31 */
231
- case 29: /* Interrupt source. */
232
- val = s->phy_int;
233
- s->phy_int = 0;
234
- phy_update_irq(s);
235
- return val;
236
- case 30: /* Interrupt mask */
237
- return s->phy_int_mask;
238
- default:
239
- qemu_log_mask(LOG_GUEST_ERROR,
240
- "do_phy_read: PHY read reg %d\n", reg);
241
- return 0;
242
- }
62
-}
243
-}
63
-
244
-
64
-static inline void unset_feature(uint64_t *features, int feature)
245
-static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
65
-{
246
-{
66
- *features &= ~(1ULL << feature);
247
- switch (reg) {
248
- case 0: /* Basic Control */
249
- if (val & 0x8000) {
250
- phy_reset(s);
251
- break;
252
- }
253
- s->phy_control = val & 0x7980;
254
- /* Complete autonegotiation immediately. */
255
- if (val & 0x1000) {
256
- s->phy_status |= 0x0020;
257
- }
258
- break;
259
- case 4: /* Auto-neg advertisement */
260
- s->phy_advertise = (val & 0x2d7f) | 0x80;
261
- break;
262
- /* TODO 17, 18, 27, 31 */
263
- case 30: /* Interrupt mask */
264
- s->phy_int_mask = val & 0xff;
265
- phy_update_irq(s);
266
- break;
267
- default:
268
- qemu_log_mask(LOG_GUEST_ERROR,
269
- "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
270
- }
67
-}
271
-}
68
-
272
-
69
static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
273
static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
70
{
274
{
71
uint64_t ret;
275
switch (reg) {
72
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
276
@@ -XXX,XX +XXX,XX @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
73
* with VFPv4+Neon; this in turn implies most of the other
277
if (val & 2) {
74
* feature bits.
278
DPRINTF("PHY write %d = 0x%04x\n",
75
*/
279
(val >> 6) & 0x1f, s->mac_mii_data);
76
- set_feature(&features, ARM_FEATURE_V8);
280
- do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
77
- set_feature(&features, ARM_FEATURE_NEON);
281
+ lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data);
78
- set_feature(&features, ARM_FEATURE_AARCH64);
282
} else {
79
- set_feature(&features, ARM_FEATURE_PMU);
283
- s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
80
- set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
284
+ s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f);
81
+ features |= 1ULL << ARM_FEATURE_V8;
285
DPRINTF("PHY read %d = 0x%04x\n",
82
+ features |= 1ULL << ARM_FEATURE_NEON;
286
(val >> 6) & 0x1f, s->mac_mii_data);
83
+ features |= 1ULL << ARM_FEATURE_AARCH64;
287
}
84
+ features |= 1ULL << ARM_FEATURE_PMU;
288
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
85
+ features |= 1ULL << ARM_FEATURE_GENERIC_TIMER;
289
break;
86
290
case CSR_PMT_CTRL:
87
ahcf->features = features;
291
if (val & 0x400) {
88
292
- phy_reset(s);
89
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
293
+ lan9118_phy_reset(&s->mii);
90
if (cpu->has_pmu) {
294
}
91
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
295
s->pmt_ctrl &= ~0x34e;
92
} else {
296
s->pmt_ctrl |= (val & 0x34e);
93
- unset_feature(&env->features, ARM_FEATURE_PMU);
297
@@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp)
94
+ env->features &= ~(1ULL << ARM_FEATURE_PMU);
298
const MemoryRegionOps *mem_ops =
95
}
299
s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops;
96
if (cpu_isar_feature(aa64_sve, cpu)) {
300
97
assert(kvm_arm_sve_supported(cs));
301
+ qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0);
302
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
303
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
304
+ return;
305
+ }
306
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
307
+
308
memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s,
309
"lan9118-mmio", 0x100);
310
sysbus_init_mmio(sbd, &s->mmio);
311
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
312
new file mode 100644
313
index XXXXXXX..XXXXXXX
314
--- /dev/null
315
+++ b/hw/net/lan9118_phy.c
316
@@ -XXX,XX +XXX,XX @@
317
+/*
318
+ * SMSC LAN9118 PHY emulation
319
+ *
320
+ * Copyright (c) 2009 CodeSourcery, LLC.
321
+ * Written by Paul Brook
322
+ *
323
+ * This code is licensed under the GNU GPL v2
324
+ *
325
+ * Contributions after 2012-01-13 are licensed under the terms of the
326
+ * GNU GPL, version 2 or (at your option) any later version.
327
+ */
328
+
329
+#include "qemu/osdep.h"
330
+#include "hw/net/lan9118_phy.h"
331
+#include "hw/irq.h"
332
+#include "hw/resettable.h"
333
+#include "migration/vmstate.h"
334
+#include "qemu/log.h"
335
+
336
+#define PHY_INT_ENERGYON (1 << 7)
337
+#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
338
+#define PHY_INT_FAULT (1 << 5)
339
+#define PHY_INT_DOWN (1 << 4)
340
+#define PHY_INT_AUTONEG_LP (1 << 3)
341
+#define PHY_INT_PARFAULT (1 << 2)
342
+#define PHY_INT_AUTONEG_PAGE (1 << 1)
343
+
344
+static void lan9118_phy_update_irq(Lan9118PhyState *s)
345
+{
346
+ qemu_set_irq(s->irq, !!(s->ints & s->int_mask));
347
+}
348
+
349
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
350
+{
351
+ uint16_t val;
352
+
353
+ switch (reg) {
354
+ case 0: /* Basic Control */
355
+ return s->control;
356
+ case 1: /* Basic Status */
357
+ return s->status;
358
+ case 2: /* ID1 */
359
+ return 0x0007;
360
+ case 3: /* ID2 */
361
+ return 0xc0d1;
362
+ case 4: /* Auto-neg advertisement */
363
+ return s->advertise;
364
+ case 5: /* Auto-neg Link Partner Ability */
365
+ return 0x0f71;
366
+ case 6: /* Auto-neg Expansion */
367
+ return 1;
368
+ /* TODO 17, 18, 27, 29, 30, 31 */
369
+ case 29: /* Interrupt source. */
370
+ val = s->ints;
371
+ s->ints = 0;
372
+ lan9118_phy_update_irq(s);
373
+ return val;
374
+ case 30: /* Interrupt mask */
375
+ return s->int_mask;
376
+ default:
377
+ qemu_log_mask(LOG_GUEST_ERROR,
378
+ "lan9118_phy_read: PHY read reg %d\n", reg);
379
+ return 0;
380
+ }
381
+}
382
+
383
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
384
+{
385
+ switch (reg) {
386
+ case 0: /* Basic Control */
387
+ if (val & 0x8000) {
388
+ lan9118_phy_reset(s);
389
+ break;
390
+ }
391
+ s->control = val & 0x7980;
392
+ /* Complete autonegotiation immediately. */
393
+ if (val & 0x1000) {
394
+ s->status |= 0x0020;
395
+ }
396
+ break;
397
+ case 4: /* Auto-neg advertisement */
398
+ s->advertise = (val & 0x2d7f) | 0x80;
399
+ break;
400
+ /* TODO 17, 18, 27, 31 */
401
+ case 30: /* Interrupt mask */
402
+ s->int_mask = val & 0xff;
403
+ lan9118_phy_update_irq(s);
404
+ break;
405
+ default:
406
+ qemu_log_mask(LOG_GUEST_ERROR,
407
+ "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
408
+ }
409
+}
410
+
411
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
412
+{
413
+ s->link_down = link_down;
414
+
415
+ /* Autonegotiation status mirrors link status. */
416
+ if (link_down) {
417
+ s->status &= ~0x0024;
418
+ s->ints |= PHY_INT_DOWN;
419
+ } else {
420
+ s->status |= 0x0024;
421
+ s->ints |= PHY_INT_ENERGYON;
422
+ s->ints |= PHY_INT_AUTONEG_COMPLETE;
423
+ }
424
+ lan9118_phy_update_irq(s);
425
+}
426
+
427
+void lan9118_phy_reset(Lan9118PhyState *s)
428
+{
429
+ s->control = 0x3000;
430
+ s->status = 0x7809;
431
+ s->advertise = 0x01e1;
432
+ s->int_mask = 0;
433
+ s->ints = 0;
434
+ lan9118_phy_update_link(s, s->link_down);
435
+}
436
+
437
+static void lan9118_phy_reset_hold(Object *obj, ResetType type)
438
+{
439
+ Lan9118PhyState *s = LAN9118_PHY(obj);
440
+
441
+ lan9118_phy_reset(s);
442
+}
443
+
444
+static void lan9118_phy_init(Object *obj)
445
+{
446
+ Lan9118PhyState *s = LAN9118_PHY(obj);
447
+
448
+ qdev_init_gpio_out(DEVICE(s), &s->irq, 1);
449
+}
450
+
451
+static const VMStateDescription vmstate_lan9118_phy = {
452
+ .name = "lan9118-phy",
453
+ .version_id = 1,
454
+ .minimum_version_id = 1,
455
+ .fields = (const VMStateField[]) {
456
+ VMSTATE_UINT16(control, Lan9118PhyState),
457
+ VMSTATE_UINT16(status, Lan9118PhyState),
458
+ VMSTATE_UINT16(advertise, Lan9118PhyState),
459
+ VMSTATE_UINT16(ints, Lan9118PhyState),
460
+ VMSTATE_UINT16(int_mask, Lan9118PhyState),
461
+ VMSTATE_BOOL(link_down, Lan9118PhyState),
462
+ VMSTATE_END_OF_LIST()
463
+ }
464
+};
465
+
466
+static void lan9118_phy_class_init(ObjectClass *klass, void *data)
467
+{
468
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
469
+ DeviceClass *dc = DEVICE_CLASS(klass);
470
+
471
+ rc->phases.hold = lan9118_phy_reset_hold;
472
+ dc->vmsd = &vmstate_lan9118_phy;
473
+}
474
+
475
+static const TypeInfo types[] = {
476
+ {
477
+ .name = TYPE_LAN9118_PHY,
478
+ .parent = TYPE_SYS_BUS_DEVICE,
479
+ .instance_size = sizeof(Lan9118PhyState),
480
+ .instance_init = lan9118_phy_init,
481
+ .class_init = lan9118_phy_class_init,
482
+ }
483
+};
484
+
485
+DEFINE_TYPES(types)
486
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
487
index XXXXXXX..XXXXXXX 100644
488
--- a/hw/net/Kconfig
489
+++ b/hw/net/Kconfig
490
@@ -XXX,XX +XXX,XX @@ config VMXNET3_PCI
491
config SMC91C111
492
bool
493
494
+config LAN9118_PHY
495
+ bool
496
+
497
config LAN9118
498
bool
499
+ select LAN9118_PHY
500
select PTIMER
501
502
config NE2000_ISA
503
diff --git a/hw/net/meson.build b/hw/net/meson.build
504
index XXXXXXX..XXXXXXX 100644
505
--- a/hw/net/meson.build
506
+++ b/hw/net/meson.build
507
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c'))
508
509
system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c'))
510
system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c'))
511
+system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c'))
512
system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c'))
513
system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c'))
514
system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c'))
98
--
515
--
99
2.20.1
516
2.34.1
100
101
diff view generated by jsdifflib
[PULL 04/34] aspeed: sdmc: Implement AST2600 locking behaviour
[PULL 02/72] hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
1
From: Joel Stanley <joel@jms.id.au>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
The AST2600 handles this differently with the extra 'hardlock' state, so
3
imx_fec models the same PHY as lan9118_phy. The code is almost the same with
4
move the testing to the soc specific class' write callback.
4
imx_fec having more logging and tracing. Merge these improvements into
5
lan9118_phy and reuse in imx_fec to fix the code duplication.
5
6
6
Signed-off-by: Joel Stanley <joel@jms.id.au>
7
Some migration state how resides in the new device model which breaks migration
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
compatibility for the following machines:
8
Message-id: 20200505090136.341426-1-joel@jms.id.au
9
* imx25-pdk
10
* sabrelite
11
* mcimx7d-sabre
12
* mcimx6ul-evk
13
14
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
15
Tested-by: Guenter Roeck <linux@roeck-us.net>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 20241102125724.532843-3-shentey@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
19
---
11
hw/misc/aspeed_sdmc.c | 55 +++++++++++++++++++++++++++++++++++--------
20
include/hw/net/imx_fec.h | 9 ++-
12
1 file changed, 45 insertions(+), 10 deletions(-)
21
hw/net/imx_fec.c | 146 ++++-----------------------------------
22
hw/net/lan9118_phy.c | 82 ++++++++++++++++------
23
hw/net/Kconfig | 1 +
24
hw/net/trace-events | 10 +--
25
5 files changed, 85 insertions(+), 163 deletions(-)
13
26
14
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
27
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
15
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/misc/aspeed_sdmc.c
29
--- a/include/hw/net/imx_fec.h
17
+++ b/hw/misc/aspeed_sdmc.c
30
+++ b/include/hw/net/imx_fec.h
18
@@ -XXX,XX +XXX,XX @@
31
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC)
19
32
#define TYPE_IMX_ENET "imx.enet"
20
/* Protection Key Register */
33
21
#define R_PROT (0x00 / 4)
34
#include "hw/sysbus.h"
22
+#define PROT_UNLOCKED 0x01
35
+#include "hw/net/lan9118_phy.h"
23
+#define PROT_HARDLOCKED 0x10 /* AST2600 */
36
+#include "hw/irq.h"
24
+#define PROT_SOFTLOCKED 0x00
37
#include "net/net.h"
25
+
38
26
#define PROT_KEY_UNLOCK 0xFC600309
39
#define ENET_EIR 1
27
+#define PROT_KEY_HARDLOCK 0xDEADDEAD /* AST2600 */
40
@@ -XXX,XX +XXX,XX @@ struct IMXFECState {
28
41
uint32_t tx_descriptor[ENET_TX_RING_NUM];
29
/* Configuration Register */
42
uint32_t tx_ring_num;
30
#define R_CONF (0x04 / 4)
43
31
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
44
- uint32_t phy_status;
32
return;
45
- uint32_t phy_control;
33
}
46
- uint32_t phy_advertise;
34
47
- uint32_t phy_int;
35
- if (addr == R_PROT) {
48
- uint32_t phy_int_mask;
36
- s->regs[addr] = (data == PROT_KEY_UNLOCK) ? 1 : 0;
49
+ Lan9118PhyState mii;
37
- return;
50
+ IRQState mii_irq;
51
uint32_t phy_num;
52
bool phy_connected;
53
struct IMXFECState *phy_consumer;
54
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/net/imx_fec.c
57
+++ b/hw/net/imx_fec.c
58
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth_txdescs = {
59
60
static const VMStateDescription vmstate_imx_eth = {
61
.name = TYPE_IMX_FEC,
62
- .version_id = 2,
63
- .minimum_version_id = 2,
64
+ .version_id = 3,
65
+ .minimum_version_id = 3,
66
.fields = (const VMStateField[]) {
67
VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX),
68
VMSTATE_UINT32(rx_descriptor, IMXFECState),
69
VMSTATE_UINT32(tx_descriptor[0], IMXFECState),
70
- VMSTATE_UINT32(phy_status, IMXFECState),
71
- VMSTATE_UINT32(phy_control, IMXFECState),
72
- VMSTATE_UINT32(phy_advertise, IMXFECState),
73
- VMSTATE_UINT32(phy_int, IMXFECState),
74
- VMSTATE_UINT32(phy_int_mask, IMXFECState),
75
VMSTATE_END_OF_LIST()
76
},
77
.subsections = (const VMStateDescription * const []) {
78
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth = {
79
},
80
};
81
82
-#define PHY_INT_ENERGYON (1 << 7)
83
-#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
84
-#define PHY_INT_FAULT (1 << 5)
85
-#define PHY_INT_DOWN (1 << 4)
86
-#define PHY_INT_AUTONEG_LP (1 << 3)
87
-#define PHY_INT_PARFAULT (1 << 2)
88
-#define PHY_INT_AUTONEG_PAGE (1 << 1)
89
-
90
static void imx_eth_update(IMXFECState *s);
91
92
/*
93
@@ -XXX,XX +XXX,XX @@ static void imx_eth_update(IMXFECState *s);
94
* For now we don't handle any GPIO/interrupt line, so the OS will
95
* have to poll for the PHY status.
96
*/
97
-static void imx_phy_update_irq(IMXFECState *s)
98
+static void imx_phy_update_irq(void *opaque, int n, int level)
99
{
100
- imx_eth_update(s);
101
-}
102
-
103
-static void imx_phy_update_link(IMXFECState *s)
104
-{
105
- /* Autonegotiation status mirrors link status. */
106
- if (qemu_get_queue(s->nic)->link_down) {
107
- trace_imx_phy_update_link("down");
108
- s->phy_status &= ~0x0024;
109
- s->phy_int |= PHY_INT_DOWN;
110
- } else {
111
- trace_imx_phy_update_link("up");
112
- s->phy_status |= 0x0024;
113
- s->phy_int |= PHY_INT_ENERGYON;
114
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
38
- }
115
- }
39
-
116
- imx_phy_update_irq(s);
40
- if (!s->regs[R_PROT]) {
117
+ imx_eth_update(opaque);
41
- qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
118
}
42
- return;
119
120
static void imx_eth_set_link(NetClientState *nc)
121
{
122
- imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc)));
123
-}
124
-
125
-static void imx_phy_reset(IMXFECState *s)
126
-{
127
- trace_imx_phy_reset();
128
-
129
- s->phy_status = 0x7809;
130
- s->phy_control = 0x3000;
131
- s->phy_advertise = 0x01e1;
132
- s->phy_int_mask = 0;
133
- s->phy_int = 0;
134
- imx_phy_update_link(s);
135
+ lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii,
136
+ nc->link_down);
137
}
138
139
static uint32_t imx_phy_read(IMXFECState *s, int reg)
140
{
141
- uint32_t val;
142
uint32_t phy = reg / 32;
143
144
if (!s->phy_connected) {
145
@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
146
147
reg %= 32;
148
149
- switch (reg) {
150
- case 0: /* Basic Control */
151
- val = s->phy_control;
152
- break;
153
- case 1: /* Basic Status */
154
- val = s->phy_status;
155
- break;
156
- case 2: /* ID1 */
157
- val = 0x0007;
158
- break;
159
- case 3: /* ID2 */
160
- val = 0xc0d1;
161
- break;
162
- case 4: /* Auto-neg advertisement */
163
- val = s->phy_advertise;
164
- break;
165
- case 5: /* Auto-neg Link Partner Ability */
166
- val = 0x0f71;
167
- break;
168
- case 6: /* Auto-neg Expansion */
169
- val = 1;
170
- break;
171
- case 29: /* Interrupt source. */
172
- val = s->phy_int;
173
- s->phy_int = 0;
174
- imx_phy_update_irq(s);
175
- break;
176
- case 30: /* Interrupt mask */
177
- val = s->phy_int_mask;
178
- break;
179
- case 17:
180
- case 18:
181
- case 27:
182
- case 31:
183
- qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n",
184
- TYPE_IMX_FEC, __func__, reg);
185
- val = 0;
186
- break;
187
- default:
188
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
189
- TYPE_IMX_FEC, __func__, reg);
190
- val = 0;
191
- break;
43
- }
192
- }
44
-
193
-
45
asc->write(s, addr, data);
194
- trace_imx_phy_read(val, phy, reg);
46
}
195
-
47
196
- return val;
48
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
197
+ return lan9118_phy_read(&s->mii, reg);
49
static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg,
198
}
50
uint32_t data)
199
51
{
200
static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
52
+ if (reg == R_PROT) {
201
@@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
53
+ s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
202
203
reg %= 32;
204
205
- trace_imx_phy_write(val, phy, reg);
206
-
207
- switch (reg) {
208
- case 0: /* Basic Control */
209
- if (val & 0x8000) {
210
- imx_phy_reset(s);
211
- } else {
212
- s->phy_control = val & 0x7980;
213
- /* Complete autonegotiation immediately. */
214
- if (val & 0x1000) {
215
- s->phy_status |= 0x0020;
216
- }
217
- }
218
- break;
219
- case 4: /* Auto-neg advertisement */
220
- s->phy_advertise = (val & 0x2d7f) | 0x80;
221
- break;
222
- case 30: /* Interrupt mask */
223
- s->phy_int_mask = val & 0xff;
224
- imx_phy_update_irq(s);
225
- break;
226
- case 17:
227
- case 18:
228
- case 27:
229
- case 31:
230
- qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n",
231
- TYPE_IMX_FEC, __func__, reg);
232
- break;
233
- default:
234
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
235
- TYPE_IMX_FEC, __func__, reg);
236
- break;
237
- }
238
+ lan9118_phy_write(&s->mii, reg, val);
239
}
240
241
static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr)
242
@@ -XXX,XX +XXX,XX @@ static void imx_eth_reset(DeviceState *d)
243
244
s->rx_descriptor = 0;
245
memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor));
246
-
247
- /* We also reset the PHY */
248
- imx_phy_reset(s);
249
}
250
251
static uint32_t imx_default_read(IMXFECState *s, uint32_t index)
252
@@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
253
sysbus_init_irq(sbd, &s->irq[0]);
254
sysbus_init_irq(sbd, &s->irq[1]);
255
256
+ qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0);
257
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
258
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
54
+ return;
259
+ return;
55
+ }
260
+ }
56
+
261
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
57
+ if (!s->regs[R_PROT]) {
262
+
58
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
263
qemu_macaddr_default_if_unset(&s->conf.macaddr);
59
+ return;
264
60
+ }
265
s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf,
61
+
266
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
267
index XXXXXXX..XXXXXXX 100644
268
--- a/hw/net/lan9118_phy.c
269
+++ b/hw/net/lan9118_phy.c
270
@@ -XXX,XX +XXX,XX @@
271
* Copyright (c) 2009 CodeSourcery, LLC.
272
* Written by Paul Brook
273
*
274
+ * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
275
+ *
276
* This code is licensed under the GNU GPL v2
277
*
278
* Contributions after 2012-01-13 are licensed under the terms of the
279
@@ -XXX,XX +XXX,XX @@
280
#include "hw/resettable.h"
281
#include "migration/vmstate.h"
282
#include "qemu/log.h"
283
+#include "trace.h"
284
285
#define PHY_INT_ENERGYON (1 << 7)
286
#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
287
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
288
62
switch (reg) {
289
switch (reg) {
63
case R_CONF:
290
case 0: /* Basic Control */
64
data = aspeed_2400_sdmc_compute_conf(s, data);
291
- return s->control;
65
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
292
+ val = s->control;
66
static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg,
293
+ break;
67
uint32_t data)
294
case 1: /* Basic Status */
295
- return s->status;
296
+ val = s->status;
297
+ break;
298
case 2: /* ID1 */
299
- return 0x0007;
300
+ val = 0x0007;
301
+ break;
302
case 3: /* ID2 */
303
- return 0xc0d1;
304
+ val = 0xc0d1;
305
+ break;
306
case 4: /* Auto-neg advertisement */
307
- return s->advertise;
308
+ val = s->advertise;
309
+ break;
310
case 5: /* Auto-neg Link Partner Ability */
311
- return 0x0f71;
312
+ val = 0x0f71;
313
+ break;
314
case 6: /* Auto-neg Expansion */
315
- return 1;
316
- /* TODO 17, 18, 27, 29, 30, 31 */
317
+ val = 1;
318
+ break;
319
case 29: /* Interrupt source. */
320
val = s->ints;
321
s->ints = 0;
322
lan9118_phy_update_irq(s);
323
- return val;
324
+ break;
325
case 30: /* Interrupt mask */
326
- return s->int_mask;
327
+ val = s->int_mask;
328
+ break;
329
+ case 17:
330
+ case 18:
331
+ case 27:
332
+ case 31:
333
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
334
+ __func__, reg);
335
+ val = 0;
336
+ break;
337
default:
338
- qemu_log_mask(LOG_GUEST_ERROR,
339
- "lan9118_phy_read: PHY read reg %d\n", reg);
340
- return 0;
341
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
342
+ __func__, reg);
343
+ val = 0;
344
+ break;
345
}
346
+
347
+ trace_lan9118_phy_read(val, reg);
348
+
349
+ return val;
350
}
351
352
void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
68
{
353
{
69
+ if (reg == R_PROT) {
354
+ trace_lan9118_phy_write(val, reg);
70
+ s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
71
+ return;
72
+ }
73
+
74
+ if (!s->regs[R_PROT]) {
75
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
76
+ return;
77
+ }
78
+
355
+
79
switch (reg) {
356
switch (reg) {
80
case R_CONF:
357
case 0: /* Basic Control */
81
data = aspeed_2500_sdmc_compute_conf(s, data);
358
if (val & 0x8000) {
82
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
359
lan9118_phy_reset(s);
83
static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,
360
- break;
84
uint32_t data)
361
- }
362
- s->control = val & 0x7980;
363
- /* Complete autonegotiation immediately. */
364
- if (val & 0x1000) {
365
- s->status |= 0x0020;
366
+ } else {
367
+ s->control = val & 0x7980;
368
+ /* Complete autonegotiation immediately. */
369
+ if (val & 0x1000) {
370
+ s->status |= 0x0020;
371
+ }
372
}
373
break;
374
case 4: /* Auto-neg advertisement */
375
s->advertise = (val & 0x2d7f) | 0x80;
376
break;
377
- /* TODO 17, 18, 27, 31 */
378
case 30: /* Interrupt mask */
379
s->int_mask = val & 0xff;
380
lan9118_phy_update_irq(s);
381
break;
382
+ case 17:
383
+ case 18:
384
+ case 27:
385
+ case 31:
386
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
387
+ __func__, reg);
388
+ break;
389
default:
390
- qemu_log_mask(LOG_GUEST_ERROR,
391
- "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
392
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
393
+ __func__, reg);
394
+ break;
395
}
396
}
397
398
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
399
400
/* Autonegotiation status mirrors link status. */
401
if (link_down) {
402
+ trace_lan9118_phy_update_link("down");
403
s->status &= ~0x0024;
404
s->ints |= PHY_INT_DOWN;
405
} else {
406
+ trace_lan9118_phy_update_link("up");
407
s->status |= 0x0024;
408
s->ints |= PHY_INT_ENERGYON;
409
s->ints |= PHY_INT_AUTONEG_COMPLETE;
410
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
411
412
void lan9118_phy_reset(Lan9118PhyState *s)
85
{
413
{
86
+ if (s->regs[R_PROT] == PROT_HARDLOCKED) {
414
+ trace_lan9118_phy_reset();
87
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n",
415
+
88
+ __func__);
416
s->control = 0x3000;
89
+ return;
417
s->status = 0x7809;
90
+ }
418
s->advertise = 0x01e1;
91
+
419
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118_phy = {
92
+ if (reg != R_PROT && s->regs[R_PROT] == PROT_SOFTLOCKED) {
420
.version_id = 1,
93
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
421
.minimum_version_id = 1,
94
+ return;
422
.fields = (const VMStateField[]) {
95
+ }
423
- VMSTATE_UINT16(control, Lan9118PhyState),
96
+
424
VMSTATE_UINT16(status, Lan9118PhyState),
97
switch (reg) {
425
+ VMSTATE_UINT16(control, Lan9118PhyState),
98
+ case R_PROT:
426
VMSTATE_UINT16(advertise, Lan9118PhyState),
99
+ if (data == PROT_KEY_UNLOCK) {
427
VMSTATE_UINT16(ints, Lan9118PhyState),
100
+ data = PROT_UNLOCKED;
428
VMSTATE_UINT16(int_mask, Lan9118PhyState),
101
+ } else if (data == PROT_KEY_HARDLOCK) {
429
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
102
+ data = PROT_HARDLOCKED;
430
index XXXXXXX..XXXXXXX 100644
103
+ } else {
431
--- a/hw/net/Kconfig
104
+ data = PROT_SOFTLOCKED;
432
+++ b/hw/net/Kconfig
105
+ }
433
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_SUN8I_EMAC
106
+ break;
434
107
case R_CONF:
435
config IMX_FEC
108
data = aspeed_2600_sdmc_compute_conf(s, data);
436
bool
109
break;
437
+ select LAN9118_PHY
438
439
config CADENCE
440
bool
441
diff --git a/hw/net/trace-events b/hw/net/trace-events
442
index XXXXXXX..XXXXXXX 100644
443
--- a/hw/net/trace-events
444
+++ b/hw/net/trace-events
445
@@ -XXX,XX +XXX,XX @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
446
allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
447
allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
448
449
+# lan9118_phy.c
450
+lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16
451
+lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16
452
+lan9118_phy_update_link(const char *s) "%s"
453
+lan9118_phy_reset(void) ""
454
+
455
# lance.c
456
lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x"
457
lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x"
458
@@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
459
i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
460
461
# imx_fec.c
462
-imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
463
imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)"
464
-imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
465
imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)"
466
-imx_phy_update_link(const char *s) "%s"
467
-imx_phy_reset(void) ""
468
imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
469
imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x"
470
imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit"
110
--
471
--
111
2.20.1
472
2.34.1
112
113
diff view generated by jsdifflib
[PULL 30/34] target/arm/cpu: Restrict v8M IDAU interface to Aarch32 CPUs
[PULL 03/72] hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
As IDAU is a v8M feature, restrict it to the Aarch32 CPUs.
3
Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and
4
fixes the MSB of selector field to be zero, as specified in the datasheet.
4
5
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Fixes: 2a424990170b "LAN9118 emulation"
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
7
Message-id: 20200504172448.9402-5-philmd@redhat.com
8
Tested-by: Guenter Roeck <linux@roeck-us.net>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20241102125724.532843-4-shentey@gmail.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
target/arm/cpu.c | 2 +-
13
hw/net/lan9118_phy.c | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
12
15
13
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.c
18
--- a/hw/net/lan9118_phy.c
16
+++ b/target/arm/cpu.c
19
+++ b/hw/net/lan9118_phy.c
17
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void)
20
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
18
const size_t cpu_count = ARRAY_SIZE(arm_cpus);
21
val = s->advertise;
19
22
break;
20
type_register_static(&arm_cpu_type_info);
23
case 5: /* Auto-neg Link Partner Ability */
21
- type_register_static(&idau_interface_type_info);
24
- val = 0x0f71;
22
25
+ val = 0x0fe1;
23
#ifdef CONFIG_KVM
26
break;
24
type_register_static(&host_arm_cpu_type_info);
27
case 6: /* Auto-neg Expansion */
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void)
28
val = 1;
26
if (cpu_count) {
27
size_t i;
28
29
+ type_register_static(&idau_interface_type_info);
30
for (i = 0; i < cpu_count; ++i) {
31
arm_cpu_register(&arm_cpus[i]);
32
}
33
--
29
--
34
2.20.1
30
2.34.1
35
36
diff view generated by jsdifflib
[PULL 18/34] target/arm: Use SVEContLdSt in sve_ld1_r
[PULL 04/72] hw/net/lan9118_phy: Reuse MII constants
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
First use of the new helper functions, so we can remove the
3
Prefer named constants over magic values for better readability.
4
unused markup. No longer need a scratch for user-only, as
5
we completely probe the page set before reading; system mode
6
still requires a scratch for MMIO.
7
4
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
10
Message-id: 20200508154359.7494-12-richard.henderson@linaro.org
7
Tested-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20241102125724.532843-5-shentey@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
target/arm/sve_helper.c | 188 +++++++++++++++++++++-------------------
11
include/hw/net/mii.h | 6 +++++
14
1 file changed, 97 insertions(+), 91 deletions(-)
12
hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++----------------
13
2 files changed, 46 insertions(+), 23 deletions(-)
15
14
16
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
15
diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sve_helper.c
17
--- a/include/hw/net/mii.h
19
+++ b/target/arm/sve_helper.c
18
+++ b/include/hw/net/mii.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct {
19
@@ -XXX,XX +XXX,XX @@
21
* final element on each page. Identify any single element that spans
20
#define MII_BMSR_JABBER (1 << 1) /* Jabber detected */
22
* the page boundary. Return true if there are any active elements.
21
#define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */
23
*/
22
24
-static bool __attribute__((unused))
23
+#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */
25
-sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg,
24
#define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */
26
- intptr_t reg_max, int esz, int msize)
25
#define MII_ANAR_PAUSE (1 << 10) /* Try for pause */
27
+static bool sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr,
26
#define MII_ANAR_TXFD (1 << 8)
28
+ uint64_t *vg, intptr_t reg_max,
27
@@ -XXX,XX +XXX,XX @@
29
+ int esz, int msize)
28
#define MII_ANAR_10FD (1 << 6)
30
{
29
#define MII_ANAR_10 (1 << 5)
31
const int esize = 1 << esz;
30
#define MII_ANAR_CSMACD (1 << 0)
32
const uint64_t pg_mask = pred_esz_masks[esz];
31
+#define MII_ANAR_SELECT (0x001f) /* Selector bits */
33
@@ -XXX,XX +XXX,XX @@ sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg,
32
34
* Control the generation of page faults with @fault. Return false if
33
#define MII_ANLPAR_ACK (1 << 14)
35
* there is no work to do, which can only happen with @fault == FAULT_NO.
34
#define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */
36
*/
35
@@ -XXX,XX +XXX,XX @@
37
-static bool __attribute__((unused))
36
#define RTL8201CP_PHYID1 0x0000
38
-sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, CPUARMState *env,
37
#define RTL8201CP_PHYID2 0x8201
39
- target_ulong addr, MMUAccessType access_type,
38
40
- uintptr_t retaddr)
39
+/* SMSC LAN9118 */
41
+static bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault,
40
+#define SMSCLAN9118_PHYID1 0x0007
42
+ CPUARMState *env, target_ulong addr,
41
+#define SMSCLAN9118_PHYID2 0xc0d1
43
+ MMUAccessType access_type, uintptr_t retaddr)
42
+
44
{
43
/* RealTek 8211E */
45
int mmu_idx = cpu_mmu_index(env, false);
44
#define RTL8211E_PHYID1 0x001c
46
int mem_off = info->mem_off_first[0];
45
#define RTL8211E_PHYID2 0xc915
47
@@ -XXX,XX +XXX,XX @@ static inline bool test_host_page(void *host)
46
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
48
/*
47
index XXXXXXX..XXXXXXX 100644
49
* Common helper for all contiguous one-register predicated loads.
48
--- a/hw/net/lan9118_phy.c
50
*/
49
+++ b/hw/net/lan9118_phy.c
51
-static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
50
@@ -XXX,XX +XXX,XX @@
52
- uint32_t desc, const uintptr_t retaddr,
51
53
- const int esz, const int msz,
52
#include "qemu/osdep.h"
54
- sve_ldst1_host_fn *host_fn,
53
#include "hw/net/lan9118_phy.h"
55
- sve_ldst1_tlb_fn *tlb_fn)
54
+#include "hw/net/mii.h"
56
+static inline QEMU_ALWAYS_INLINE
55
#include "hw/irq.h"
57
+void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
56
#include "hw/resettable.h"
58
+ uint32_t desc, const uintptr_t retaddr,
57
#include "migration/vmstate.h"
59
+ const int esz, const int msz,
58
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
60
+ sve_ldst1_host_fn *host_fn,
59
uint16_t val;
61
+ sve_ldst1_tlb_fn *tlb_fn)
60
62
{
61
switch (reg) {
63
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
62
- case 0: /* Basic Control */
64
- const int mmu_idx = get_mmuidx(oi);
63
+ case MII_BMCR:
65
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
64
val = s->control;
66
void *vd = &env->vfp.zregs[rd];
65
break;
67
- const int diffsz = esz - msz;
66
- case 1: /* Basic Status */
68
const intptr_t reg_max = simd_oprsz(desc);
67
+ case MII_BMSR:
69
- const intptr_t mem_max = reg_max >> diffsz;
68
val = s->status;
70
- ARMVectorReg scratch;
69
break;
71
+ intptr_t reg_off, reg_last, mem_off;
70
- case 2: /* ID1 */
72
+ SVEContLdSt info;
71
- val = 0x0007;
73
void *host;
72
+ case MII_PHYID1:
74
- intptr_t split, reg_off, mem_off;
73
+ val = SMSCLAN9118_PHYID1;
75
+ int flags;
74
break;
76
75
- case 3: /* ID2 */
77
- /* Find the first active element. */
76
- val = 0xc0d1;
78
- reg_off = find_next_active(vg, 0, reg_max, esz);
77
+ case MII_PHYID2:
79
- if (unlikely(reg_off == reg_max)) {
78
+ val = SMSCLAN9118_PHYID2;
80
+ /* Find the active elements. */
79
break;
81
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, 1 << msz)) {
80
- case 4: /* Auto-neg advertisement */
82
/* The entire predicate was false; no load occurs. */
81
+ case MII_ANAR:
83
memset(vd, 0, reg_max);
82
val = s->advertise;
84
return;
83
break;
85
}
84
- case 5: /* Auto-neg Link Partner Ability */
86
- mem_off = reg_off >> diffsz;
85
- val = 0x0fe1;
87
86
+ case MII_ANLPAR:
88
- /*
87
+ val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 |
89
- * If the (remaining) load is entirely within a single page, then:
88
+ MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD |
90
- * For softmmu, and the tlb hits, then no faults will occur;
89
+ MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
91
- * For user-only, either the first load will fault or none will.
90
break;
92
- * We can thus perform the load directly to the destination and
91
- case 6: /* Auto-neg Expansion */
93
- * Vd will be unmodified on any exception path.
92
- val = 1;
94
- */
93
+ case MII_ANER:
95
- split = max_for_page(addr, mem_off, mem_max);
94
+ val = MII_ANER_NWAY;
96
- if (likely(split == mem_max)) {
95
break;
97
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
96
case 29: /* Interrupt source. */
98
- if (test_host_page(host)) {
97
val = s->ints;
99
- intptr_t i = reg_off;
98
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
100
- host -= mem_off;
99
trace_lan9118_phy_write(val, reg);
101
- do {
100
102
- host_fn(vd, i, host + (i >> diffsz));
101
switch (reg) {
103
- i = find_next_active(vg, i + (1 << esz), reg_max, esz);
102
- case 0: /* Basic Control */
104
- } while (i < reg_max);
103
- if (val & 0x8000) {
105
- /* After having taken any fault, zero leading inactive elements. */
104
+ case MII_BMCR:
106
- swap_memzero(vd, reg_off);
105
+ if (val & MII_BMCR_RESET) {
107
- return;
106
lan9118_phy_reset(s);
108
- }
107
} else {
109
- }
108
- s->control = val & 0x7980;
110
+ /* Probe the page(s). Exit with exception for any invalid page. */
109
+ s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 |
111
+ sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, retaddr);
110
+ MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD |
112
111
+ MII_BMCR_CTST);
113
- /*
112
/* Complete autonegotiation immediately. */
114
- * Perform the predicated read into a temporary, thus ensuring
113
- if (val & 0x1000) {
115
- * if the load of the last element faults, Vd is not modified.
114
- s->status |= 0x0020;
116
- */
115
+ if (val & MII_BMCR_AUTOEN) {
117
+ flags = info.page[0].flags | info.page[1].flags;
116
+ s->status |= MII_BMSR_AN_COMP;
118
+ if (unlikely(flags != 0)) {
119
#ifdef CONFIG_USER_ONLY
120
- swap_memzero(&scratch, reg_off);
121
- host = g2h(addr);
122
- do {
123
- host_fn(&scratch, reg_off, host + (reg_off >> diffsz));
124
- reg_off += 1 << esz;
125
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
126
- } while (reg_off < reg_max);
127
+ g_assert_not_reached();
128
#else
129
- memset(&scratch, 0, reg_max);
130
- goto start;
131
- while (1) {
132
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
133
- if (reg_off >= reg_max) {
134
- break;
135
- }
136
- mem_off = reg_off >> diffsz;
137
- split = max_for_page(addr, mem_off, mem_max);
138
+ /*
139
+ * At least one page includes MMIO (or watchpoints).
140
+ * Any bus operation can fail with cpu_transaction_failed,
141
+ * which for ARM will raise SyncExternal. Perform the load
142
+ * into scratch memory to preserve register state until the end.
143
+ */
144
+ ARMVectorReg scratch;
145
146
- start:
147
- if (split - mem_off >= (1 << msz)) {
148
- /* At least one whole element on this page. */
149
- host = tlb_vaddr_to_host(env, addr + mem_off,
150
- MMU_DATA_LOAD, mmu_idx);
151
- if (host) {
152
- host -= mem_off;
153
- do {
154
- host_fn(&scratch, reg_off, host + mem_off);
155
- reg_off += 1 << esz;
156
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
157
- mem_off = reg_off >> diffsz;
158
- } while (split - mem_off >= (1 << msz));
159
- continue;
160
+ memset(&scratch, 0, reg_max);
161
+ mem_off = info.mem_off_first[0];
162
+ reg_off = info.reg_off_first[0];
163
+ reg_last = info.reg_off_last[1];
164
+ if (reg_last < 0) {
165
+ reg_last = info.reg_off_split;
166
+ if (reg_last < 0) {
167
+ reg_last = info.reg_off_last[0];
168
}
117
}
169
}
118
}
170
119
break;
171
- /*
120
- case 4: /* Auto-neg advertisement */
172
- * Perform one normal read. This may fault, longjmping out to the
121
- s->advertise = (val & 0x2d7f) | 0x80;
173
- * main loop in order to raise an exception. It may succeed, and
122
+ case MII_ANAR:
174
- * as a side-effect load the TLB entry for the next round. Finally,
123
+ s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
175
- * in the extremely unlikely case we're performing this operation
124
+ MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
176
- * on I/O memory, it may succeed but not bring in the TLB entry.
125
+ MII_ANAR_SELECT))
177
- * But even then we have still made forward progress.
126
+ | MII_ANAR_TX;
178
- */
127
break;
179
- tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
128
case 30: /* Interrupt mask */
180
- reg_off += 1 << esz;
129
s->int_mask = val & 0xff;
181
- }
130
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
182
-#endif
131
/* Autonegotiation status mirrors link status. */
183
+ do {
132
if (link_down) {
184
+ uint64_t pg = vg[reg_off >> 6];
133
trace_lan9118_phy_update_link("down");
185
+ do {
134
- s->status &= ~0x0024;
186
+ if ((pg >> (reg_off & 63)) & 1) {
135
+ s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST);
187
+ tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
136
s->ints |= PHY_INT_DOWN;
188
+ }
137
} else {
189
+ reg_off += 1 << esz;
138
trace_lan9118_phy_update_link("up");
190
+ mem_off += 1 << msz;
139
- s->status |= 0x0024;
191
+ } while (reg_off & 63);
140
+ s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST;
192
+ } while (reg_off <= reg_last);
141
s->ints |= PHY_INT_ENERGYON;
193
142
s->ints |= PHY_INT_AUTONEG_COMPLETE;
194
- memcpy(vd, &scratch, reg_max);
143
}
195
+ memcpy(vd, &scratch, reg_max);
144
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_reset(Lan9118PhyState *s)
196
+ return;
145
{
197
+#endif
146
trace_lan9118_phy_reset();
198
+ }
147
199
+
148
- s->control = 0x3000;
200
+ /* The entire operation is in RAM, on valid pages. */
149
- s->status = 0x7809;
201
+
150
- s->advertise = 0x01e1;
202
+ memset(vd, 0, reg_max);
151
+ s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100;
203
+ mem_off = info.mem_off_first[0];
152
+ s->status = MII_BMSR_100TX_FD
204
+ reg_off = info.reg_off_first[0];
153
+ | MII_BMSR_100TX_HD
205
+ reg_last = info.reg_off_last[0];
154
+ | MII_BMSR_10T_FD
206
+ host = info.page[0].host;
155
+ | MII_BMSR_10T_HD
207
+
156
+ | MII_BMSR_AUTONEG
208
+ while (reg_off <= reg_last) {
157
+ | MII_BMSR_EXTCAP;
209
+ uint64_t pg = vg[reg_off >> 6];
158
+ s->advertise = MII_ANAR_TXFD
210
+ do {
159
+ | MII_ANAR_TX
211
+ if ((pg >> (reg_off & 63)) & 1) {
160
+ | MII_ANAR_10FD
212
+ host_fn(vd, reg_off, host + mem_off);
161
+ | MII_ANAR_10
213
+ }
162
+ | MII_ANAR_CSMACD;
214
+ reg_off += 1 << esz;
163
s->int_mask = 0;
215
+ mem_off += 1 << msz;
164
s->ints = 0;
216
+ } while (reg_off <= reg_last && (reg_off & 63));
165
lan9118_phy_update_link(s, s->link_down);
217
+ }
218
+
219
+ /*
220
+ * Use the slow path to manage the cross-page misalignment.
221
+ * But we know this is RAM and cannot trap.
222
+ */
223
+ mem_off = info.mem_off_split;
224
+ if (unlikely(mem_off >= 0)) {
225
+ tlb_fn(env, vd, info.reg_off_split, addr + mem_off, retaddr);
226
+ }
227
+
228
+ mem_off = info.mem_off_first[1];
229
+ if (unlikely(mem_off >= 0)) {
230
+ reg_off = info.reg_off_first[1];
231
+ reg_last = info.reg_off_last[1];
232
+ host = info.page[1].host;
233
+
234
+ do {
235
+ uint64_t pg = vg[reg_off >> 6];
236
+ do {
237
+ if ((pg >> (reg_off & 63)) & 1) {
238
+ host_fn(vd, reg_off, host + mem_off);
239
+ }
240
+ reg_off += 1 << esz;
241
+ mem_off += 1 << msz;
242
+ } while (reg_off & 63);
243
+ } while (reg_off <= reg_last);
244
+ }
245
}
246
247
#define DO_LD1_1(NAME, ESZ) \
248
--
166
--
249
2.20.1
167
2.34.1
250
251
diff view generated by jsdifflib
[PULL 26/34] target/arm: Remove sve_memopidx
[PULL 05/72] hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
None of the sve helpers use TCGMemOpIdx any longer, so we can
3
The real device advertises this mode and the device model already advertises
4
stop passing it.
4
100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to
5
make the model more realistic.
5
6
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
8
Message-id: 20200508154359.7494-20-richard.henderson@linaro.org
9
Tested-by: Guenter Roeck <linux@roeck-us.net>
10
Message-id: 20241102125724.532843-6-shentey@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
target/arm/internals.h | 5 -----
13
hw/net/lan9118_phy.c | 4 ++--
12
target/arm/sve_helper.c | 14 +++++++-------
14
1 file changed, 2 insertions(+), 2 deletions(-)
13
target/arm/translate-sve.c | 17 +++--------------
14
3 files changed, 10 insertions(+), 26 deletions(-)
15
15
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/internals.h
18
--- a/hw/net/lan9118_phy.c
19
+++ b/target/arm/internals.h
19
+++ b/hw/net/lan9118_phy.c
20
@@ -XXX,XX +XXX,XX @@ static inline int arm_num_ctx_cmps(ARMCPU *cpu)
20
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
21
}
21
break;
22
}
22
case MII_ANAR:
23
23
s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
24
-/* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3.
24
- MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
25
- * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits.
25
- MII_ANAR_SELECT))
26
- */
26
+ MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD |
27
-#define MEMOPIDX_SHIFT 8
27
+ MII_ANAR_10 | MII_ANAR_SELECT))
28
-
28
| MII_ANAR_TX;
29
/**
29
break;
30
* v7m_using_psp: Return true if using process stack pointer
30
case 30: /* Interrupt mask */
31
* Return true if the CPU is currently using the process stack
32
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/sve_helper.c
35
+++ b/target/arm/sve_helper.c
36
@@ -XXX,XX +XXX,XX @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
37
sve_ldst1_host_fn *host_fn,
38
sve_ldst1_tlb_fn *tlb_fn)
39
{
40
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
41
+ const unsigned rd = simd_data(desc);
42
const intptr_t reg_max = simd_oprsz(desc);
43
intptr_t reg_off, reg_last, mem_off;
44
SVEContLdSt info;
45
@@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
46
sve_ldst1_host_fn *host_fn,
47
sve_ldst1_tlb_fn *tlb_fn)
48
{
49
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
50
+ const unsigned rd = simd_data(desc);
51
void *vd = &env->vfp.zregs[rd];
52
const intptr_t reg_max = simd_oprsz(desc);
53
intptr_t reg_off, mem_off, reg_last;
54
@@ -XXX,XX +XXX,XX @@ void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, uint32_t desc,
55
sve_ldst1_host_fn *host_fn,
56
sve_ldst1_tlb_fn *tlb_fn)
57
{
58
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
59
+ const unsigned rd = simd_data(desc);
60
const intptr_t reg_max = simd_oprsz(desc);
61
intptr_t reg_off, reg_last, mem_off;
62
SVEContLdSt info;
63
@@ -XXX,XX +XXX,XX @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
64
sve_ldst1_host_fn *host_fn,
65
sve_ldst1_tlb_fn *tlb_fn)
66
{
67
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
68
const int mmu_idx = cpu_mmu_index(env, false);
69
const intptr_t reg_max = simd_oprsz(desc);
70
+ const int scale = simd_data(desc);
71
ARMVectorReg scratch;
72
intptr_t reg_off;
73
SVEHostPage info, info2;
74
@@ -XXX,XX +XXX,XX @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
75
sve_ldst1_tlb_fn *tlb_fn)
76
{
77
const int mmu_idx = cpu_mmu_index(env, false);
78
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
79
+ const intptr_t reg_max = simd_oprsz(desc);
80
+ const int scale = simd_data(desc);
81
const int esize = 1 << esz;
82
const int msize = 1 << msz;
83
- const intptr_t reg_max = simd_oprsz(desc);
84
intptr_t reg_off;
85
SVEHostPage info;
86
target_ulong addr, in_page;
87
@@ -XXX,XX +XXX,XX @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
88
sve_ldst1_host_fn *host_fn,
89
sve_ldst1_tlb_fn *tlb_fn)
90
{
91
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
92
const int mmu_idx = cpu_mmu_index(env, false);
93
const intptr_t reg_max = simd_oprsz(desc);
94
+ const int scale = simd_data(desc);
95
void *host[ARM_MAX_VQ * 4];
96
intptr_t reg_off, i;
97
SVEHostPage info, info2;
98
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/translate-sve.c
101
+++ b/target/arm/translate-sve.c
102
@@ -XXX,XX +XXX,XX @@ static const uint8_t dtype_esz[16] = {
103
3, 2, 1, 3
104
};
105
106
-static TCGMemOpIdx sve_memopidx(DisasContext *s, int dtype)
107
-{
108
- return make_memop_idx(s->be_data | dtype_mop[dtype], get_mem_index(s));
109
-}
110
-
111
static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
112
int dtype, gen_helper_gvec_mem *fn)
113
{
114
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
115
* registers as pointers, so encode the regno into the data field.
116
* For consistency, do this even for LD1.
117
*/
118
- desc = sve_memopidx(s, dtype);
119
- desc |= zt << MEMOPIDX_SHIFT;
120
- desc = simd_desc(vsz, vsz, desc);
121
+ desc = simd_desc(vsz, vsz, zt);
122
t_desc = tcg_const_i32(desc);
123
t_pg = tcg_temp_new_ptr();
124
125
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int msz)
126
int desc, poff;
127
128
/* Load the first quadword using the normal predicated load helpers. */
129
- desc = sve_memopidx(s, msz_dtype(s, msz));
130
- desc |= zt << MEMOPIDX_SHIFT;
131
- desc = simd_desc(16, 16, desc);
132
+ desc = simd_desc(16, 16, zt);
133
t_desc = tcg_const_i32(desc);
134
135
poff = pred_full_reg_offset(s, pg);
136
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
137
TCGv_i32 t_desc;
138
int desc;
139
140
- desc = sve_memopidx(s, msz_dtype(s, msz));
141
- desc |= scale << MEMOPIDX_SHIFT;
142
- desc = simd_desc(vsz, vsz, desc);
143
+ desc = simd_desc(vsz, vsz, scale);
144
t_desc = tcg_const_i32(desc);
145
146
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
147
--
31
--
148
2.20.1
32
2.34.1
149
150
diff view generated by jsdifflib
New patch
[PULL 06/72] fpu: handle raising Invalid for infzero in pick_nan_muladd
1
For IEEE fused multiply-add, the (0 * inf) + NaN case should raise
2
Invalid for the multiplication of 0 by infinity. Currently we handle
3
this in the per-architecture ifdef ladder in pickNaNMulAdd().
4
However, since this isn't really architecture specific we can hoist
5
it up to the generic code.
1
6
7
For the cases where the infzero test in pickNaNMulAdd was
8
returning 2, we can delete the check entirely and allow the
9
code to fall into the normal pick-a-NaN handling, because this
10
will return 2 anyway (input 'c' being the only NaN in this case).
11
For the cases where infzero was returning 3 to indicate "return
12
the default NaN", we must retain that "return 3".
13
14
For Arm, this looks like it might be a behaviour change because we
15
used to set float_flag_invalid | float_flag_invalid_imz only if C is
16
a quiet NaN. However, it is not, because Arm target code never looks
17
at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we
18
already raised float_flag_invalid via the "abc_mask &
19
float_cmask_snan" check in pick_nan_muladd.
20
21
For any target architecture using the "default implementation" at the
22
bottom of the ifdef, this is a behaviour change but will be fixing a
23
bug (where we failed to raise the Invalid exception for (0 * inf +
24
QNaN). The architectures using the default case are:
25
* hppa
26
* i386
27
* sh4
28
* tricore
29
30
The x86, Tricore and SH4 CPU architecture manuals are clear that this
31
should have raised Invalid; HPPA is a bit vaguer but still seems
32
clear enough.
33
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
36
Message-id: 20241202131347.498124-2-peter.maydell@linaro.org
37
---
38
fpu/softfloat-parts.c.inc | 13 +++++++------
39
fpu/softfloat-specialize.c.inc | 29 +----------------------------
40
2 files changed, 8 insertions(+), 34 deletions(-)
41
42
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
43
index XXXXXXX..XXXXXXX 100644
44
--- a/fpu/softfloat-parts.c.inc
45
+++ b/fpu/softfloat-parts.c.inc
46
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
47
int ab_mask, int abc_mask)
48
{
49
int which;
50
+ bool infzero = (ab_mask == float_cmask_infzero);
51
52
if (unlikely(abc_mask & float_cmask_snan)) {
53
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
54
}
55
56
- which = pickNaNMulAdd(a->cls, b->cls, c->cls,
57
- ab_mask == float_cmask_infzero, s);
58
+ if (infzero) {
59
+ /* This is (0 * inf) + NaN or (inf * 0) + NaN */
60
+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
61
+ }
62
+
63
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
64
65
if (s->default_nan_mode || which == 3) {
66
- /*
67
- * Note that this check is after pickNaNMulAdd so that function
68
- * has an opportunity to set the Invalid flag for infzero.
69
- */
70
parts_default_nan(a, s);
71
return a;
72
}
73
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
74
index XXXXXXX..XXXXXXX 100644
75
--- a/fpu/softfloat-specialize.c.inc
76
+++ b/fpu/softfloat-specialize.c.inc
77
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
78
* the default NaN
79
*/
80
if (infzero && is_qnan(c_cls)) {
81
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
82
return 3;
83
}
84
85
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
86
* case sets InvalidOp and returns the default NaN
87
*/
88
if (infzero) {
89
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
90
return 3;
91
}
92
/* Prefer sNaN over qNaN, in the a, b, c order. */
93
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
94
* For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
95
* case sets InvalidOp and returns the input value 'c'
96
*/
97
- if (infzero) {
98
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
99
- return 2;
100
- }
101
/* Prefer sNaN over qNaN, in the c, a, b order. */
102
if (is_snan(c_cls)) {
103
return 2;
104
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
105
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
106
* case sets InvalidOp and returns the input value 'c'
107
*/
108
- if (infzero) {
109
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
110
- return 2;
111
- }
112
+
113
/* Prefer sNaN over qNaN, in the c, a, b order. */
114
if (is_snan(c_cls)) {
115
return 2;
116
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
117
* to return an input NaN if we have one (ie c) rather than generating
118
* a default NaN
119
*/
120
- if (infzero) {
121
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
122
- return 2;
123
- }
124
125
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
126
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
127
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
128
return 1;
129
}
130
#elif defined(TARGET_RISCV)
131
- /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
132
- if (infzero) {
133
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
134
- }
135
return 3; /* default NaN */
136
#elif defined(TARGET_S390X)
137
if (infzero) {
138
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
139
return 3;
140
}
141
142
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
143
return 2;
144
}
145
#elif defined(TARGET_SPARC)
146
- /* For (inf,0,nan) return c. */
147
- if (infzero) {
148
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
149
- return 2;
150
- }
151
/* Prefer SNaN over QNaN, order C, B, A. */
152
if (is_snan(c_cls)) {
153
return 2;
154
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
155
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
156
* an input NaN if we have one (ie c).
157
*/
158
- if (infzero) {
159
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
160
- return 2;
161
- }
162
if (status->use_first_nan) {
163
if (is_nan(a_cls)) {
164
return 0;
165
--
166
2.34.1
diff view generated by jsdifflib
New patch
[PULL 07/72] fpu: Check for default_nan_mode before calling pickNaNMulAdd
1
If the target sets default_nan_mode then we're always going to return
2
the default NaN, and pickNaNMulAdd() no longer has any side effects.
3
For consistency with pickNaN(), check for default_nan_mode before
4
calling pickNaNMulAdd().
1
5
6
When we convert pickNaNMulAdd() to allow runtime selection of the NaN
7
propagation rule, this means we won't have to make the targets which
8
use default_nan_mode also set a propagation rule.
9
10
Since RiscV always uses default_nan_mode, this allows us to remove
11
its ifdef case from pickNaNMulAdd().
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-3-peter.maydell@linaro.org
16
---
17
fpu/softfloat-parts.c.inc | 8 ++++++--
18
fpu/softfloat-specialize.c.inc | 9 +++++++--
19
2 files changed, 13 insertions(+), 4 deletions(-)
20
21
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
22
index XXXXXXX..XXXXXXX 100644
23
--- a/fpu/softfloat-parts.c.inc
24
+++ b/fpu/softfloat-parts.c.inc
25
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
26
float_raise(float_flag_invalid | float_flag_invalid_imz, s);
27
}
28
29
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
30
+ if (s->default_nan_mode) {
31
+ which = 3;
32
+ } else {
33
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ }
35
36
- if (s->default_nan_mode || which == 3) {
37
+ if (which == 3) {
38
parts_default_nan(a, s);
39
return a;
40
}
41
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
42
index XXXXXXX..XXXXXXX 100644
43
--- a/fpu/softfloat-specialize.c.inc
44
+++ b/fpu/softfloat-specialize.c.inc
45
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
46
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
47
bool infzero, float_status *status)
48
{
49
+ /*
50
+ * We guarantee not to require the target to tell us how to
51
+ * pick a NaN if we're always returning the default NaN.
52
+ * But if we're not in default-NaN mode then the target must
53
+ * specify.
54
+ */
55
+ assert(!status->default_nan_mode);
56
#if defined(TARGET_ARM)
57
/* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
58
* the default NaN
59
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
60
} else {
61
return 1;
62
}
63
-#elif defined(TARGET_RISCV)
64
- return 3; /* default NaN */
65
#elif defined(TARGET_S390X)
66
if (infzero) {
67
return 3;
68
--
69
2.34.1
diff view generated by jsdifflib
[PULL 19/34] target/arm: Handle watchpoints in sve_ld1_r
[PULL 08/72] softfloat: Allow runtime choice of inf * 0 + NaN result
1
From: Richard Henderson <richard.henderson@linaro.org>
1
IEEE 758 does not define a fixed rule for what NaN to return in
2
2
the case of a fused multiply-add of inf * 0 + NaN. Different
3
Handle all of the watchpoints for active elements all at once,
3
architectures thus do different things:
4
before we've modified the vector register. This removes the
4
* some return the default NaN
5
TLB_WATCHPOINT bit from page[].flags, which means that we can
5
* some return the input NaN
6
use the normal fast path via RAM.
6
* Arm returns the default NaN if the input NaN is quiet,
7
7
and the input NaN if it is signalling
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
We want to make this logic be runtime selected rather than
10
Message-id: 20200508154359.7494-13-richard.henderson@linaro.org
10
hardcoded into the binary, because:
11
* this will let us have multiple targets in one QEMU binary
12
* the Arm FEAT_AFP architectural feature includes letting
13
the guest select a NaN propagation rule at runtime
14
15
In this commit we add an enum for the propagation rule, the field in
16
float_status, and the corresponding getters and setters. We change
17
pickNaNMulAdd to honour this, but because all targets still leave
18
this field at its default 0 value, the fallback logic will pick the
19
rule type with the old ifdef ladder.
20
21
Note that four architectures both use the muladd softfloat functions
22
and did not have a branch of the ifdef ladder to specify their
23
behaviour (and so were ending up with the "default" case, probably
24
wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set
25
default_nan_mode, and so will never get into pickNaNMulAdd(). For
26
HPPA and i386 we retain the same behaviour as the old default-case,
27
which is to not ever return the default NaN. This might not be
28
correct but it is not a behaviour change.
29
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
32
Message-id: 20241202131347.498124-4-peter.maydell@linaro.org
12
---
33
---
13
target/arm/sve_helper.c | 72 ++++++++++++++++++++++++++++++++++++++++-
34
include/fpu/softfloat-helpers.h | 11 ++++
14
1 file changed, 71 insertions(+), 1 deletion(-)
35
include/fpu/softfloat-types.h | 23 +++++++++
15
36
fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++-----------
16
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
37
3 files changed, 95 insertions(+), 30 deletions(-)
38
39
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
17
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sve_helper.c
41
--- a/include/fpu/softfloat-helpers.h
19
+++ b/target/arm/sve_helper.c
42
+++ b/include/fpu/softfloat-helpers.h
20
@@ -XXX,XX +XXX,XX @@ static bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault,
43
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
21
return have_work;
44
status->float_2nan_prop_rule = rule;
22
}
45
}
23
46
24
+static void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env,
47
+static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
25
+ uint64_t *vg, target_ulong addr,
48
+ float_status *status)
26
+ int esize, int msize, int wp_access,
27
+ uintptr_t retaddr)
28
+{
49
+{
29
+#ifndef CONFIG_USER_ONLY
50
+ status->float_infzeronan_rule = rule;
30
+ intptr_t mem_off, reg_off, reg_last;
51
+}
31
+ int flags0 = info->page[0].flags;
52
+
32
+ int flags1 = info->page[1].flags;
53
static inline void set_flush_to_zero(bool val, float_status *status)
33
+
54
{
34
+ if (likely(!((flags0 | flags1) & TLB_WATCHPOINT))) {
55
status->flush_to_zero = val;
35
+ return;
56
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
36
+ }
57
return status->float_2nan_prop_rule;
37
+
58
}
38
+ /* Indicate that watchpoints are handled. */
59
39
+ info->page[0].flags = flags0 & ~TLB_WATCHPOINT;
60
+static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
40
+ info->page[1].flags = flags1 & ~TLB_WATCHPOINT;
61
+{
41
+
62
+ return status->float_infzeronan_rule;
42
+ if (flags0 & TLB_WATCHPOINT) {
63
+}
43
+ mem_off = info->mem_off_first[0];
64
+
44
+ reg_off = info->reg_off_first[0];
65
static inline bool get_flush_to_zero(float_status *status)
45
+ reg_last = info->reg_off_last[0];
66
{
46
+
67
return status->flush_to_zero;
47
+ while (reg_off <= reg_last) {
68
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
48
+ uint64_t pg = vg[reg_off >> 6];
69
index XXXXXXX..XXXXXXX 100644
49
+ do {
70
--- a/include/fpu/softfloat-types.h
50
+ if ((pg >> (reg_off & 63)) & 1) {
71
+++ b/include/fpu/softfloat-types.h
51
+ cpu_check_watchpoint(env_cpu(env), addr + mem_off,
72
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
52
+ msize, info->page[0].attrs,
73
float_2nan_prop_x87,
53
+ wp_access, retaddr);
74
} Float2NaNPropRule;
54
+ }
75
55
+ reg_off += esize;
76
+/*
56
+ mem_off += msize;
77
+ * Rule for result of fused multiply-add 0 * Inf + NaN.
57
+ } while (reg_off <= reg_last && (reg_off & 63));
78
+ * This must be a NaN, but implementations differ on whether this
79
+ * is the input NaN or the default NaN.
80
+ *
81
+ * You don't need to set this if default_nan_mode is enabled.
82
+ * When not in default-NaN mode, it is an error for the target
83
+ * not to set the rule in float_status if it uses muladd, and we
84
+ * will assert if we need to handle an input NaN and no rule was
85
+ * selected.
86
+ */
87
+typedef enum __attribute__((__packed__)) {
88
+ /* No propagation rule specified */
89
+ float_infzeronan_none = 0,
90
+ /* Result is never the default NaN (so always the input NaN) */
91
+ float_infzeronan_dnan_never,
92
+ /* Result is always the default NaN */
93
+ float_infzeronan_dnan_always,
94
+ /* Result is the default NaN if the input NaN is quiet */
95
+ float_infzeronan_dnan_if_qnan,
96
+} FloatInfZeroNaNRule;
97
+
98
/*
99
* Floating Point Status. Individual architectures may maintain
100
* several versions of float_status for different functions. The
101
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
102
FloatRoundMode float_rounding_mode;
103
FloatX80RoundPrec floatx80_rounding_precision;
104
Float2NaNPropRule float_2nan_prop_rule;
105
+ FloatInfZeroNaNRule float_infzeronan_rule;
106
bool tininess_before_rounding;
107
/* should denormalised results go to zero and set the inexact flag? */
108
bool flush_to_zero;
109
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
110
index XXXXXXX..XXXXXXX 100644
111
--- a/fpu/softfloat-specialize.c.inc
112
+++ b/fpu/softfloat-specialize.c.inc
113
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
114
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
115
bool infzero, float_status *status)
116
{
117
+ FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
118
+
119
/*
120
* We guarantee not to require the target to tell us how to
121
* pick a NaN if we're always returning the default NaN.
122
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
123
* specify.
124
*/
125
assert(!status->default_nan_mode);
126
+
127
+ if (rule == float_infzeronan_none) {
128
+ /*
129
+ * Temporarily fall back to ifdef ladder
130
+ */
131
#if defined(TARGET_ARM)
132
- /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
133
- * the default NaN
134
- */
135
- if (infzero && is_qnan(c_cls)) {
136
- return 3;
137
+ /*
138
+ * For ARM, the (inf,zero,qnan) case returns the default NaN,
139
+ * but (inf,zero,snan) returns the input NaN.
140
+ */
141
+ rule = float_infzeronan_dnan_if_qnan;
142
+#elif defined(TARGET_MIPS)
143
+ if (snan_bit_is_one(status)) {
144
+ /*
145
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
146
+ * case sets InvalidOp and returns the default NaN
147
+ */
148
+ rule = float_infzeronan_dnan_always;
149
+ } else {
150
+ /*
151
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
152
+ * case sets InvalidOp and returns the input value 'c'
153
+ */
154
+ rule = float_infzeronan_dnan_never;
155
+ }
156
+#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
157
+ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
158
+ defined(TARGET_I386) || defined(TARGET_LOONGARCH)
159
+ /*
160
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
161
+ * case sets InvalidOp and returns the input value 'c'
162
+ */
163
+ /*
164
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
165
+ * to return an input NaN if we have one (ie c) rather than generating
166
+ * a default NaN
167
+ */
168
+ rule = float_infzeronan_dnan_never;
169
+#elif defined(TARGET_S390X)
170
+ rule = float_infzeronan_dnan_always;
171
+#endif
172
}
173
174
+ if (infzero) {
175
+ /*
176
+ * Inf * 0 + NaN -- some implementations return the default NaN here,
177
+ * and some return the input NaN.
178
+ */
179
+ switch (rule) {
180
+ case float_infzeronan_dnan_never:
181
+ return 2;
182
+ case float_infzeronan_dnan_always:
183
+ return 3;
184
+ case float_infzeronan_dnan_if_qnan:
185
+ return is_qnan(c_cls) ? 3 : 2;
186
+ default:
187
+ g_assert_not_reached();
58
+ }
188
+ }
59
+ }
189
+ }
60
+
190
+
61
+ mem_off = info->mem_off_split;
191
+#if defined(TARGET_ARM)
62
+ if (mem_off >= 0) {
192
+
63
+ cpu_check_watchpoint(env_cpu(env), addr + mem_off, msize,
193
/* This looks different from the ARM ARM pseudocode, because the ARM ARM
64
+ info->page[0].attrs, wp_access, retaddr);
194
* puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
65
+ }
195
*/
66
+
196
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
67
+ mem_off = info->mem_off_first[1];
197
}
68
+ if ((flags1 & TLB_WATCHPOINT) && mem_off >= 0) {
198
#elif defined(TARGET_MIPS)
69
+ reg_off = info->reg_off_first[1];
199
if (snan_bit_is_one(status)) {
70
+ reg_last = info->reg_off_last[1];
200
- /*
71
+
201
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
72
+ do {
202
- * case sets InvalidOp and returns the default NaN
73
+ uint64_t pg = vg[reg_off >> 6];
203
- */
74
+ do {
204
- if (infzero) {
75
+ if ((pg >> (reg_off & 63)) & 1) {
205
- return 3;
76
+ cpu_check_watchpoint(env_cpu(env), addr + mem_off,
206
- }
77
+ msize, info->page[1].attrs,
207
/* Prefer sNaN over qNaN, in the a, b, c order. */
78
+ wp_access, retaddr);
208
if (is_snan(a_cls)) {
79
+ }
209
return 0;
80
+ reg_off += esize;
210
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
81
+ mem_off += msize;
211
return 2;
82
+ } while (reg_off & 63);
212
}
83
+ } while (reg_off <= reg_last);
213
} else {
84
+ }
214
- /*
85
+#endif
215
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
86
+}
216
- * case sets InvalidOp and returns the input value 'c'
87
+
217
- */
88
/*
218
/* Prefer sNaN over qNaN, in the c, a, b order. */
89
* The result of tlb_vaddr_to_host for user-only is just g2h(x),
219
if (is_snan(c_cls)) {
90
* which is always non-null. Elide the useless test.
220
return 2;
91
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
221
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
92
/* Probe the page(s). Exit with exception for any invalid page. */
222
}
93
sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, retaddr);
223
}
94
224
#elif defined(TARGET_LOONGARCH64)
95
+ /* Handle watchpoints for all active elements. */
225
- /*
96
+ sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, 1 << msz,
226
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
97
+ BP_MEM_READ, retaddr);
227
- * case sets InvalidOp and returns the input value 'c'
98
+
228
- */
99
+ /* TODO: MTE check. */
229
-
100
+
230
/* Prefer sNaN over qNaN, in the c, a, b order. */
101
flags = info.page[0].flags | info.page[1].flags;
231
if (is_snan(c_cls)) {
102
if (unlikely(flags != 0)) {
232
return 2;
103
#ifdef CONFIG_USER_ONLY
233
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
104
g_assert_not_reached();
234
return 1;
105
#else
235
}
106
/*
236
#elif defined(TARGET_PPC)
107
- * At least one page includes MMIO (or watchpoints).
237
- /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
108
+ * At least one page includes MMIO.
238
- * to return an input NaN if we have one (ie c) rather than generating
109
* Any bus operation can fail with cpu_transaction_failed,
239
- * a default NaN
110
* which for ARM will raise SyncExternal. Perform the load
240
- */
111
* into scratch memory to preserve register state until the end.
241
-
242
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
243
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
244
*/
245
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
246
return 1;
247
}
248
#elif defined(TARGET_S390X)
249
- if (infzero) {
250
- return 3;
251
- }
252
-
253
if (is_snan(a_cls)) {
254
return 0;
255
} else if (is_snan(b_cls)) {
112
--
256
--
113
2.20.1
257
2.34.1
114
115
diff view generated by jsdifflib
New patch
[PULL 09/72] tests/fp: Explicitly set inf-zero-nan rule
1
Explicitly set a rule in the softfloat tests for the inf-zero-nan
2
muladd special case. In meson.build we put -DTARGET_ARM in fpcflags,
3
and so we should select here the Arm rule of
4
float_infzeronan_dnan_if_qnan.
1
5
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241202131347.498124-5-peter.maydell@linaro.org
9
---
10
tests/fp/fp-bench.c | 5 +++++
11
tests/fp/fp-test.c | 5 +++++
12
2 files changed, 10 insertions(+)
13
14
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tests/fp/fp-bench.c
17
+++ b/tests/fp/fp-bench.c
18
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
19
{
20
bench_func_t f;
21
22
+ /*
23
+ * These implementation-defined choices for various things IEEE
24
+ * doesn't specify match those used by the Arm architecture.
25
+ */
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
28
29
f = bench_funcs[operation][precision];
30
g_assert(f);
31
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/tests/fp/fp-test.c
34
+++ b/tests/fp/fp-test.c
35
@@ -XXX,XX +XXX,XX @@ void run_test(void)
36
{
37
unsigned int i;
38
39
+ /*
40
+ * These implementation-defined choices for various things IEEE
41
+ * doesn't specify match those used by the Arm architecture.
42
+ */
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
44
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
45
46
genCases_setLevel(test_level);
47
verCases_maxErrorCount = n_max_errors;
48
--
49
2.34.1
diff view generated by jsdifflib
[PULL 31/34] target/arm: Restrict TCG cpus to TCG accel
[PULL 10/72] target/arm: Set FloatInfZeroNaNRule explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the FloatInfZeroNaNRule explicitly for the Arm target,
2
so we can remove the ifdef from pickNaNMulAdd().
2
3
3
A KVM-only build won't be able to run TCG cpus.
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Message-id: 20241202131347.498124-6-peter.maydell@linaro.org
7
Message-id: 20200504172448.9402-6-philmd@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
7
---
10
target/arm/cpu.c | 634 -------------------------------------
8
target/arm/cpu.c | 3 +++
11
target/arm/cpu_tcg.c | 664 +++++++++++++++++++++++++++++++++++++++
9
fpu/softfloat-specialize.c.inc | 8 +-------
12
target/arm/Makefile.objs | 1 +
10
2 files changed, 4 insertions(+), 7 deletions(-)
13
3 files changed, 665 insertions(+), 634 deletions(-)
14
create mode 100644 target/arm/cpu_tcg.c
15
11
16
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.c
14
--- a/target/arm/cpu.c
19
+++ b/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
20
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
21
return true;
17
* * tininess-before-rounding
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
20
+ * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
21
+ * and the input NaN if it is signalling
22
*/
23
static void arm_set_default_fp_behaviours(float_status *s)
24
{
25
set_float_detect_tininess(float_tininess_before_rounding, s);
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
22
}
28
}
23
29
24
-#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
30
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
25
-static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
-{
27
- CPUClass *cc = CPU_GET_CLASS(cs);
28
- ARMCPU *cpu = ARM_CPU(cs);
29
- CPUARMState *env = &cpu->env;
30
- bool ret = false;
31
-
32
- /*
33
- * ARMv7-M interrupt masking works differently than -A or -R.
34
- * There is no FIQ/IRQ distinction. Instead of I and F bits
35
- * masking FIQ and IRQ interrupts, an exception is taken only
36
- * if it is higher priority than the current execution priority
37
- * (which depends on state like BASEPRI, FAULTMASK and the
38
- * currently active exception).
39
- */
40
- if (interrupt_request & CPU_INTERRUPT_HARD
41
- && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
42
- cs->exception_index = EXCP_IRQ;
43
- cc->do_interrupt(cs);
44
- ret = true;
45
- }
46
- return ret;
47
-}
48
-#endif
49
-
50
void arm_cpu_update_virq(ARMCPU *cpu)
51
{
52
/*
53
@@ -XXX,XX +XXX,XX @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
54
/* CPU models. These are not needed for the AArch64 linux-user build. */
55
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
56
57
-static void arm926_initfn(Object *obj)
58
-{
59
- ARMCPU *cpu = ARM_CPU(obj);
60
-
61
- cpu->dtb_compatible = "arm,arm926";
62
- set_feature(&cpu->env, ARM_FEATURE_V5);
63
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
64
- set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
65
- cpu->midr = 0x41069265;
66
- cpu->reset_fpsid = 0x41011090;
67
- cpu->ctr = 0x1dd20d2;
68
- cpu->reset_sctlr = 0x00090078;
69
-
70
- /*
71
- * ARMv5 does not have the ID_ISAR registers, but we can still
72
- * set the field to indicate Jazelle support within QEMU.
73
- */
74
- cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
75
- /*
76
- * Similarly, we need to set MVFR0 fields to enable vfp and short vector
77
- * support even though ARMv5 doesn't have this register.
78
- */
79
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
80
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
81
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
82
-}
83
-
84
-static void arm946_initfn(Object *obj)
85
-{
86
- ARMCPU *cpu = ARM_CPU(obj);
87
-
88
- cpu->dtb_compatible = "arm,arm946";
89
- set_feature(&cpu->env, ARM_FEATURE_V5);
90
- set_feature(&cpu->env, ARM_FEATURE_PMSA);
91
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
92
- cpu->midr = 0x41059461;
93
- cpu->ctr = 0x0f004006;
94
- cpu->reset_sctlr = 0x00000078;
95
-}
96
-
97
-static void arm1026_initfn(Object *obj)
98
-{
99
- ARMCPU *cpu = ARM_CPU(obj);
100
-
101
- cpu->dtb_compatible = "arm,arm1026";
102
- set_feature(&cpu->env, ARM_FEATURE_V5);
103
- set_feature(&cpu->env, ARM_FEATURE_AUXCR);
104
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
105
- set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
106
- cpu->midr = 0x4106a262;
107
- cpu->reset_fpsid = 0x410110a0;
108
- cpu->ctr = 0x1dd20d2;
109
- cpu->reset_sctlr = 0x00090078;
110
- cpu->reset_auxcr = 1;
111
-
112
- /*
113
- * ARMv5 does not have the ID_ISAR registers, but we can still
114
- * set the field to indicate Jazelle support within QEMU.
115
- */
116
- cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
117
- /*
118
- * Similarly, we need to set MVFR0 fields to enable vfp and short vector
119
- * support even though ARMv5 doesn't have this register.
120
- */
121
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
122
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
123
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
124
-
125
- {
126
- /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
127
- ARMCPRegInfo ifar = {
128
- .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
129
- .access = PL1_RW,
130
- .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
131
- .resetvalue = 0
132
- };
133
- define_one_arm_cp_reg(cpu, &ifar);
134
- }
135
-}
136
-
137
-static void arm1136_r2_initfn(Object *obj)
138
-{
139
- ARMCPU *cpu = ARM_CPU(obj);
140
- /*
141
- * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
142
- * older core than plain "arm1136". In particular this does not
143
- * have the v6K features.
144
- * These ID register values are correct for 1136 but may be wrong
145
- * for 1136_r2 (in particular r0p2 does not actually implement most
146
- * of the ID registers).
147
- */
148
-
149
- cpu->dtb_compatible = "arm,arm1136";
150
- set_feature(&cpu->env, ARM_FEATURE_V6);
151
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
152
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
153
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
154
- cpu->midr = 0x4107b362;
155
- cpu->reset_fpsid = 0x410120b4;
156
- cpu->isar.mvfr0 = 0x11111111;
157
- cpu->isar.mvfr1 = 0x00000000;
158
- cpu->ctr = 0x1dd20d2;
159
- cpu->reset_sctlr = 0x00050078;
160
- cpu->id_pfr0 = 0x111;
161
- cpu->id_pfr1 = 0x1;
162
- cpu->isar.id_dfr0 = 0x2;
163
- cpu->id_afr0 = 0x3;
164
- cpu->isar.id_mmfr0 = 0x01130003;
165
- cpu->isar.id_mmfr1 = 0x10030302;
166
- cpu->isar.id_mmfr2 = 0x01222110;
167
- cpu->isar.id_isar0 = 0x00140011;
168
- cpu->isar.id_isar1 = 0x12002111;
169
- cpu->isar.id_isar2 = 0x11231111;
170
- cpu->isar.id_isar3 = 0x01102131;
171
- cpu->isar.id_isar4 = 0x141;
172
- cpu->reset_auxcr = 7;
173
-}
174
-
175
-static void arm1136_initfn(Object *obj)
176
-{
177
- ARMCPU *cpu = ARM_CPU(obj);
178
-
179
- cpu->dtb_compatible = "arm,arm1136";
180
- set_feature(&cpu->env, ARM_FEATURE_V6K);
181
- set_feature(&cpu->env, ARM_FEATURE_V6);
182
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
183
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
184
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
185
- cpu->midr = 0x4117b363;
186
- cpu->reset_fpsid = 0x410120b4;
187
- cpu->isar.mvfr0 = 0x11111111;
188
- cpu->isar.mvfr1 = 0x00000000;
189
- cpu->ctr = 0x1dd20d2;
190
- cpu->reset_sctlr = 0x00050078;
191
- cpu->id_pfr0 = 0x111;
192
- cpu->id_pfr1 = 0x1;
193
- cpu->isar.id_dfr0 = 0x2;
194
- cpu->id_afr0 = 0x3;
195
- cpu->isar.id_mmfr0 = 0x01130003;
196
- cpu->isar.id_mmfr1 = 0x10030302;
197
- cpu->isar.id_mmfr2 = 0x01222110;
198
- cpu->isar.id_isar0 = 0x00140011;
199
- cpu->isar.id_isar1 = 0x12002111;
200
- cpu->isar.id_isar2 = 0x11231111;
201
- cpu->isar.id_isar3 = 0x01102131;
202
- cpu->isar.id_isar4 = 0x141;
203
- cpu->reset_auxcr = 7;
204
-}
205
-
206
-static void arm1176_initfn(Object *obj)
207
-{
208
- ARMCPU *cpu = ARM_CPU(obj);
209
-
210
- cpu->dtb_compatible = "arm,arm1176";
211
- set_feature(&cpu->env, ARM_FEATURE_V6K);
212
- set_feature(&cpu->env, ARM_FEATURE_VAPA);
213
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
214
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
215
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
216
- set_feature(&cpu->env, ARM_FEATURE_EL3);
217
- cpu->midr = 0x410fb767;
218
- cpu->reset_fpsid = 0x410120b5;
219
- cpu->isar.mvfr0 = 0x11111111;
220
- cpu->isar.mvfr1 = 0x00000000;
221
- cpu->ctr = 0x1dd20d2;
222
- cpu->reset_sctlr = 0x00050078;
223
- cpu->id_pfr0 = 0x111;
224
- cpu->id_pfr1 = 0x11;
225
- cpu->isar.id_dfr0 = 0x33;
226
- cpu->id_afr0 = 0;
227
- cpu->isar.id_mmfr0 = 0x01130003;
228
- cpu->isar.id_mmfr1 = 0x10030302;
229
- cpu->isar.id_mmfr2 = 0x01222100;
230
- cpu->isar.id_isar0 = 0x0140011;
231
- cpu->isar.id_isar1 = 0x12002111;
232
- cpu->isar.id_isar2 = 0x11231121;
233
- cpu->isar.id_isar3 = 0x01102131;
234
- cpu->isar.id_isar4 = 0x01141;
235
- cpu->reset_auxcr = 7;
236
-}
237
-
238
-static void arm11mpcore_initfn(Object *obj)
239
-{
240
- ARMCPU *cpu = ARM_CPU(obj);
241
-
242
- cpu->dtb_compatible = "arm,arm11mpcore";
243
- set_feature(&cpu->env, ARM_FEATURE_V6K);
244
- set_feature(&cpu->env, ARM_FEATURE_VAPA);
245
- set_feature(&cpu->env, ARM_FEATURE_MPIDR);
246
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
247
- cpu->midr = 0x410fb022;
248
- cpu->reset_fpsid = 0x410120b4;
249
- cpu->isar.mvfr0 = 0x11111111;
250
- cpu->isar.mvfr1 = 0x00000000;
251
- cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
252
- cpu->id_pfr0 = 0x111;
253
- cpu->id_pfr1 = 0x1;
254
- cpu->isar.id_dfr0 = 0;
255
- cpu->id_afr0 = 0x2;
256
- cpu->isar.id_mmfr0 = 0x01100103;
257
- cpu->isar.id_mmfr1 = 0x10020302;
258
- cpu->isar.id_mmfr2 = 0x01222000;
259
- cpu->isar.id_isar0 = 0x00100011;
260
- cpu->isar.id_isar1 = 0x12002111;
261
- cpu->isar.id_isar2 = 0x11221011;
262
- cpu->isar.id_isar3 = 0x01102131;
263
- cpu->isar.id_isar4 = 0x141;
264
- cpu->reset_auxcr = 1;
265
-}
266
-
267
-static void cortex_m0_initfn(Object *obj)
268
-{
269
- ARMCPU *cpu = ARM_CPU(obj);
270
- set_feature(&cpu->env, ARM_FEATURE_V6);
271
- set_feature(&cpu->env, ARM_FEATURE_M);
272
-
273
- cpu->midr = 0x410cc200;
274
-}
275
-
276
-static void cortex_m3_initfn(Object *obj)
277
-{
278
- ARMCPU *cpu = ARM_CPU(obj);
279
- set_feature(&cpu->env, ARM_FEATURE_V7);
280
- set_feature(&cpu->env, ARM_FEATURE_M);
281
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
282
- cpu->midr = 0x410fc231;
283
- cpu->pmsav7_dregion = 8;
284
- cpu->id_pfr0 = 0x00000030;
285
- cpu->id_pfr1 = 0x00000200;
286
- cpu->isar.id_dfr0 = 0x00100000;
287
- cpu->id_afr0 = 0x00000000;
288
- cpu->isar.id_mmfr0 = 0x00000030;
289
- cpu->isar.id_mmfr1 = 0x00000000;
290
- cpu->isar.id_mmfr2 = 0x00000000;
291
- cpu->isar.id_mmfr3 = 0x00000000;
292
- cpu->isar.id_isar0 = 0x01141110;
293
- cpu->isar.id_isar1 = 0x02111000;
294
- cpu->isar.id_isar2 = 0x21112231;
295
- cpu->isar.id_isar3 = 0x01111110;
296
- cpu->isar.id_isar4 = 0x01310102;
297
- cpu->isar.id_isar5 = 0x00000000;
298
- cpu->isar.id_isar6 = 0x00000000;
299
-}
300
-
301
-static void cortex_m4_initfn(Object *obj)
302
-{
303
- ARMCPU *cpu = ARM_CPU(obj);
304
-
305
- set_feature(&cpu->env, ARM_FEATURE_V7);
306
- set_feature(&cpu->env, ARM_FEATURE_M);
307
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
308
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
309
- cpu->midr = 0x410fc240; /* r0p0 */
310
- cpu->pmsav7_dregion = 8;
311
- cpu->isar.mvfr0 = 0x10110021;
312
- cpu->isar.mvfr1 = 0x11000011;
313
- cpu->isar.mvfr2 = 0x00000000;
314
- cpu->id_pfr0 = 0x00000030;
315
- cpu->id_pfr1 = 0x00000200;
316
- cpu->isar.id_dfr0 = 0x00100000;
317
- cpu->id_afr0 = 0x00000000;
318
- cpu->isar.id_mmfr0 = 0x00000030;
319
- cpu->isar.id_mmfr1 = 0x00000000;
320
- cpu->isar.id_mmfr2 = 0x00000000;
321
- cpu->isar.id_mmfr3 = 0x00000000;
322
- cpu->isar.id_isar0 = 0x01141110;
323
- cpu->isar.id_isar1 = 0x02111000;
324
- cpu->isar.id_isar2 = 0x21112231;
325
- cpu->isar.id_isar3 = 0x01111110;
326
- cpu->isar.id_isar4 = 0x01310102;
327
- cpu->isar.id_isar5 = 0x00000000;
328
- cpu->isar.id_isar6 = 0x00000000;
329
-}
330
-
331
-static void cortex_m7_initfn(Object *obj)
332
-{
333
- ARMCPU *cpu = ARM_CPU(obj);
334
-
335
- set_feature(&cpu->env, ARM_FEATURE_V7);
336
- set_feature(&cpu->env, ARM_FEATURE_M);
337
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
338
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
339
- cpu->midr = 0x411fc272; /* r1p2 */
340
- cpu->pmsav7_dregion = 8;
341
- cpu->isar.mvfr0 = 0x10110221;
342
- cpu->isar.mvfr1 = 0x12000011;
343
- cpu->isar.mvfr2 = 0x00000040;
344
- cpu->id_pfr0 = 0x00000030;
345
- cpu->id_pfr1 = 0x00000200;
346
- cpu->isar.id_dfr0 = 0x00100000;
347
- cpu->id_afr0 = 0x00000000;
348
- cpu->isar.id_mmfr0 = 0x00100030;
349
- cpu->isar.id_mmfr1 = 0x00000000;
350
- cpu->isar.id_mmfr2 = 0x01000000;
351
- cpu->isar.id_mmfr3 = 0x00000000;
352
- cpu->isar.id_isar0 = 0x01101110;
353
- cpu->isar.id_isar1 = 0x02112000;
354
- cpu->isar.id_isar2 = 0x20232231;
355
- cpu->isar.id_isar3 = 0x01111131;
356
- cpu->isar.id_isar4 = 0x01310132;
357
- cpu->isar.id_isar5 = 0x00000000;
358
- cpu->isar.id_isar6 = 0x00000000;
359
-}
360
-
361
-static void cortex_m33_initfn(Object *obj)
362
-{
363
- ARMCPU *cpu = ARM_CPU(obj);
364
-
365
- set_feature(&cpu->env, ARM_FEATURE_V8);
366
- set_feature(&cpu->env, ARM_FEATURE_M);
367
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
368
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
369
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
370
- cpu->midr = 0x410fd213; /* r0p3 */
371
- cpu->pmsav7_dregion = 16;
372
- cpu->sau_sregion = 8;
373
- cpu->isar.mvfr0 = 0x10110021;
374
- cpu->isar.mvfr1 = 0x11000011;
375
- cpu->isar.mvfr2 = 0x00000040;
376
- cpu->id_pfr0 = 0x00000030;
377
- cpu->id_pfr1 = 0x00000210;
378
- cpu->isar.id_dfr0 = 0x00200000;
379
- cpu->id_afr0 = 0x00000000;
380
- cpu->isar.id_mmfr0 = 0x00101F40;
381
- cpu->isar.id_mmfr1 = 0x00000000;
382
- cpu->isar.id_mmfr2 = 0x01000000;
383
- cpu->isar.id_mmfr3 = 0x00000000;
384
- cpu->isar.id_isar0 = 0x01101110;
385
- cpu->isar.id_isar1 = 0x02212000;
386
- cpu->isar.id_isar2 = 0x20232232;
387
- cpu->isar.id_isar3 = 0x01111131;
388
- cpu->isar.id_isar4 = 0x01310132;
389
- cpu->isar.id_isar5 = 0x00000000;
390
- cpu->isar.id_isar6 = 0x00000000;
391
- cpu->clidr = 0x00000000;
392
- cpu->ctr = 0x8000c000;
393
-}
394
-
395
-static void arm_v7m_class_init(ObjectClass *oc, void *data)
396
-{
397
- ARMCPUClass *acc = ARM_CPU_CLASS(oc);
398
- CPUClass *cc = CPU_CLASS(oc);
399
-
400
- acc->info = data;
401
-#ifndef CONFIG_USER_ONLY
402
- cc->do_interrupt = arm_v7m_cpu_do_interrupt;
403
-#endif
404
-
405
- cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
406
-}
407
-
408
-static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
409
- /* Dummy the TCM region regs for the moment */
410
- { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
411
- .access = PL1_RW, .type = ARM_CP_CONST },
412
- { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
413
- .access = PL1_RW, .type = ARM_CP_CONST },
414
- { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
415
- .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
416
- REGINFO_SENTINEL
417
-};
418
-
419
-static void cortex_r5_initfn(Object *obj)
420
-{
421
- ARMCPU *cpu = ARM_CPU(obj);
422
-
423
- set_feature(&cpu->env, ARM_FEATURE_V7);
424
- set_feature(&cpu->env, ARM_FEATURE_V7MP);
425
- set_feature(&cpu->env, ARM_FEATURE_PMSA);
426
- set_feature(&cpu->env, ARM_FEATURE_PMU);
427
- cpu->midr = 0x411fc153; /* r1p3 */
428
- cpu->id_pfr0 = 0x0131;
429
- cpu->id_pfr1 = 0x001;
430
- cpu->isar.id_dfr0 = 0x010400;
431
- cpu->id_afr0 = 0x0;
432
- cpu->isar.id_mmfr0 = 0x0210030;
433
- cpu->isar.id_mmfr1 = 0x00000000;
434
- cpu->isar.id_mmfr2 = 0x01200000;
435
- cpu->isar.id_mmfr3 = 0x0211;
436
- cpu->isar.id_isar0 = 0x02101111;
437
- cpu->isar.id_isar1 = 0x13112111;
438
- cpu->isar.id_isar2 = 0x21232141;
439
- cpu->isar.id_isar3 = 0x01112131;
440
- cpu->isar.id_isar4 = 0x0010142;
441
- cpu->isar.id_isar5 = 0x0;
442
- cpu->isar.id_isar6 = 0x0;
443
- cpu->mp_is_up = true;
444
- cpu->pmsav7_dregion = 16;
445
- define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
446
-}
447
-
448
-static void cortex_r5f_initfn(Object *obj)
449
-{
450
- ARMCPU *cpu = ARM_CPU(obj);
451
-
452
- cortex_r5_initfn(obj);
453
- cpu->isar.mvfr0 = 0x10110221;
454
- cpu->isar.mvfr1 = 0x00000011;
455
-}
456
-
457
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
458
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
459
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
460
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
461
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
462
}
463
464
-static void ti925t_initfn(Object *obj)
465
-{
466
- ARMCPU *cpu = ARM_CPU(obj);
467
- set_feature(&cpu->env, ARM_FEATURE_V4T);
468
- set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
469
- cpu->midr = ARM_CPUID_TI925T;
470
- cpu->ctr = 0x5109149;
471
- cpu->reset_sctlr = 0x00000070;
472
-}
473
-
474
-static void sa1100_initfn(Object *obj)
475
-{
476
- ARMCPU *cpu = ARM_CPU(obj);
477
-
478
- cpu->dtb_compatible = "intel,sa1100";
479
- set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
480
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
481
- cpu->midr = 0x4401A11B;
482
- cpu->reset_sctlr = 0x00000070;
483
-}
484
-
485
-static void sa1110_initfn(Object *obj)
486
-{
487
- ARMCPU *cpu = ARM_CPU(obj);
488
- set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
489
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
490
- cpu->midr = 0x6901B119;
491
- cpu->reset_sctlr = 0x00000070;
492
-}
493
-
494
-static void pxa250_initfn(Object *obj)
495
-{
496
- ARMCPU *cpu = ARM_CPU(obj);
497
-
498
- cpu->dtb_compatible = "marvell,xscale";
499
- set_feature(&cpu->env, ARM_FEATURE_V5);
500
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
501
- cpu->midr = 0x69052100;
502
- cpu->ctr = 0xd172172;
503
- cpu->reset_sctlr = 0x00000078;
504
-}
505
-
506
-static void pxa255_initfn(Object *obj)
507
-{
508
- ARMCPU *cpu = ARM_CPU(obj);
509
-
510
- cpu->dtb_compatible = "marvell,xscale";
511
- set_feature(&cpu->env, ARM_FEATURE_V5);
512
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
513
- cpu->midr = 0x69052d00;
514
- cpu->ctr = 0xd172172;
515
- cpu->reset_sctlr = 0x00000078;
516
-}
517
-
518
-static void pxa260_initfn(Object *obj)
519
-{
520
- ARMCPU *cpu = ARM_CPU(obj);
521
-
522
- cpu->dtb_compatible = "marvell,xscale";
523
- set_feature(&cpu->env, ARM_FEATURE_V5);
524
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
525
- cpu->midr = 0x69052903;
526
- cpu->ctr = 0xd172172;
527
- cpu->reset_sctlr = 0x00000078;
528
-}
529
-
530
-static void pxa261_initfn(Object *obj)
531
-{
532
- ARMCPU *cpu = ARM_CPU(obj);
533
-
534
- cpu->dtb_compatible = "marvell,xscale";
535
- set_feature(&cpu->env, ARM_FEATURE_V5);
536
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
537
- cpu->midr = 0x69052d05;
538
- cpu->ctr = 0xd172172;
539
- cpu->reset_sctlr = 0x00000078;
540
-}
541
-
542
-static void pxa262_initfn(Object *obj)
543
-{
544
- ARMCPU *cpu = ARM_CPU(obj);
545
-
546
- cpu->dtb_compatible = "marvell,xscale";
547
- set_feature(&cpu->env, ARM_FEATURE_V5);
548
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
549
- cpu->midr = 0x69052d06;
550
- cpu->ctr = 0xd172172;
551
- cpu->reset_sctlr = 0x00000078;
552
-}
553
-
554
-static void pxa270a0_initfn(Object *obj)
555
-{
556
- ARMCPU *cpu = ARM_CPU(obj);
557
-
558
- cpu->dtb_compatible = "marvell,xscale";
559
- set_feature(&cpu->env, ARM_FEATURE_V5);
560
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
561
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
562
- cpu->midr = 0x69054110;
563
- cpu->ctr = 0xd172172;
564
- cpu->reset_sctlr = 0x00000078;
565
-}
566
-
567
-static void pxa270a1_initfn(Object *obj)
568
-{
569
- ARMCPU *cpu = ARM_CPU(obj);
570
-
571
- cpu->dtb_compatible = "marvell,xscale";
572
- set_feature(&cpu->env, ARM_FEATURE_V5);
573
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
574
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
575
- cpu->midr = 0x69054111;
576
- cpu->ctr = 0xd172172;
577
- cpu->reset_sctlr = 0x00000078;
578
-}
579
-
580
-static void pxa270b0_initfn(Object *obj)
581
-{
582
- ARMCPU *cpu = ARM_CPU(obj);
583
-
584
- cpu->dtb_compatible = "marvell,xscale";
585
- set_feature(&cpu->env, ARM_FEATURE_V5);
586
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
587
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
588
- cpu->midr = 0x69054112;
589
- cpu->ctr = 0xd172172;
590
- cpu->reset_sctlr = 0x00000078;
591
-}
592
-
593
-static void pxa270b1_initfn(Object *obj)
594
-{
595
- ARMCPU *cpu = ARM_CPU(obj);
596
-
597
- cpu->dtb_compatible = "marvell,xscale";
598
- set_feature(&cpu->env, ARM_FEATURE_V5);
599
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
600
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
601
- cpu->midr = 0x69054113;
602
- cpu->ctr = 0xd172172;
603
- cpu->reset_sctlr = 0x00000078;
604
-}
605
-
606
-static void pxa270c0_initfn(Object *obj)
607
-{
608
- ARMCPU *cpu = ARM_CPU(obj);
609
-
610
- cpu->dtb_compatible = "marvell,xscale";
611
- set_feature(&cpu->env, ARM_FEATURE_V5);
612
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
613
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
614
- cpu->midr = 0x69054114;
615
- cpu->ctr = 0xd172172;
616
- cpu->reset_sctlr = 0x00000078;
617
-}
618
-
619
-static void pxa270c5_initfn(Object *obj)
620
-{
621
- ARMCPU *cpu = ARM_CPU(obj);
622
-
623
- cpu->dtb_compatible = "marvell,xscale";
624
- set_feature(&cpu->env, ARM_FEATURE_V5);
625
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
626
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
627
- cpu->midr = 0x69054117;
628
- cpu->ctr = 0xd172172;
629
- cpu->reset_sctlr = 0x00000078;
630
-}
631
-
632
#ifndef TARGET_AARCH64
633
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
634
* otherwise, a CPU with as many features enabled as our emulation supports.
635
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
636
637
static const ARMCPUInfo arm_cpus[] = {
638
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
639
- { .name = "arm926", .initfn = arm926_initfn },
640
- { .name = "arm946", .initfn = arm946_initfn },
641
- { .name = "arm1026", .initfn = arm1026_initfn },
642
- /*
643
- * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
644
- * older core than plain "arm1136". In particular this does not
645
- * have the v6K features.
646
- */
647
- { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
648
- { .name = "arm1136", .initfn = arm1136_initfn },
649
- { .name = "arm1176", .initfn = arm1176_initfn },
650
- { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
651
- { .name = "cortex-m0", .initfn = cortex_m0_initfn,
652
- .class_init = arm_v7m_class_init },
653
- { .name = "cortex-m3", .initfn = cortex_m3_initfn,
654
- .class_init = arm_v7m_class_init },
655
- { .name = "cortex-m4", .initfn = cortex_m4_initfn,
656
- .class_init = arm_v7m_class_init },
657
- { .name = "cortex-m7", .initfn = cortex_m7_initfn,
658
- .class_init = arm_v7m_class_init },
659
- { .name = "cortex-m33", .initfn = cortex_m33_initfn,
660
- .class_init = arm_v7m_class_init },
661
- { .name = "cortex-r5", .initfn = cortex_r5_initfn },
662
- { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
663
{ .name = "cortex-a7", .initfn = cortex_a7_initfn },
664
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
665
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
666
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
667
- { .name = "ti925t", .initfn = ti925t_initfn },
668
- { .name = "sa1100", .initfn = sa1100_initfn },
669
- { .name = "sa1110", .initfn = sa1110_initfn },
670
- { .name = "pxa250", .initfn = pxa250_initfn },
671
- { .name = "pxa255", .initfn = pxa255_initfn },
672
- { .name = "pxa260", .initfn = pxa260_initfn },
673
- { .name = "pxa261", .initfn = pxa261_initfn },
674
- { .name = "pxa262", .initfn = pxa262_initfn },
675
- /* "pxa270" is an alias for "pxa270-a0" */
676
- { .name = "pxa270", .initfn = pxa270a0_initfn },
677
- { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
678
- { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
679
- { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
680
- { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
681
- { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
682
- { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
683
#ifndef TARGET_AARCH64
684
{ .name = "max", .initfn = arm_max_initfn },
685
#endif
686
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
687
new file mode 100644
688
index XXXXXXX..XXXXXXX
689
--- /dev/null
690
+++ b/target/arm/cpu_tcg.c
691
@@ -XXX,XX +XXX,XX @@
692
+/*
693
+ * QEMU ARM TCG CPUs.
694
+ *
695
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
696
+ *
697
+ * This code is licensed under the GNU GPL v2 or later.
698
+ *
699
+ * SPDX-License-Identifier: GPL-2.0-or-later
700
+ */
701
+
702
+#include "qemu/osdep.h"
703
+#include "cpu.h"
704
+#include "internals.h"
705
+
706
+/* CPU models. These are not needed for the AArch64 linux-user build. */
707
+#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
708
+
709
+static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
710
+{
711
+ CPUClass *cc = CPU_GET_CLASS(cs);
712
+ ARMCPU *cpu = ARM_CPU(cs);
713
+ CPUARMState *env = &cpu->env;
714
+ bool ret = false;
715
+
716
+ /*
717
+ * ARMv7-M interrupt masking works differently than -A or -R.
718
+ * There is no FIQ/IRQ distinction. Instead of I and F bits
719
+ * masking FIQ and IRQ interrupts, an exception is taken only
720
+ * if it is higher priority than the current execution priority
721
+ * (which depends on state like BASEPRI, FAULTMASK and the
722
+ * currently active exception).
723
+ */
724
+ if (interrupt_request & CPU_INTERRUPT_HARD
725
+ && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
726
+ cs->exception_index = EXCP_IRQ;
727
+ cc->do_interrupt(cs);
728
+ ret = true;
729
+ }
730
+ return ret;
731
+}
732
+
733
+static void arm926_initfn(Object *obj)
734
+{
735
+ ARMCPU *cpu = ARM_CPU(obj);
736
+
737
+ cpu->dtb_compatible = "arm,arm926";
738
+ set_feature(&cpu->env, ARM_FEATURE_V5);
739
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
740
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
741
+ cpu->midr = 0x41069265;
742
+ cpu->reset_fpsid = 0x41011090;
743
+ cpu->ctr = 0x1dd20d2;
744
+ cpu->reset_sctlr = 0x00090078;
745
+
746
+ /*
747
+ * ARMv5 does not have the ID_ISAR registers, but we can still
748
+ * set the field to indicate Jazelle support within QEMU.
749
+ */
750
+ cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
751
+ /*
752
+ * Similarly, we need to set MVFR0 fields to enable vfp and short vector
753
+ * support even though ARMv5 doesn't have this register.
754
+ */
755
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
756
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
757
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
758
+}
759
+
760
+static void arm946_initfn(Object *obj)
761
+{
762
+ ARMCPU *cpu = ARM_CPU(obj);
763
+
764
+ cpu->dtb_compatible = "arm,arm946";
765
+ set_feature(&cpu->env, ARM_FEATURE_V5);
766
+ set_feature(&cpu->env, ARM_FEATURE_PMSA);
767
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
768
+ cpu->midr = 0x41059461;
769
+ cpu->ctr = 0x0f004006;
770
+ cpu->reset_sctlr = 0x00000078;
771
+}
772
+
773
+static void arm1026_initfn(Object *obj)
774
+{
775
+ ARMCPU *cpu = ARM_CPU(obj);
776
+
777
+ cpu->dtb_compatible = "arm,arm1026";
778
+ set_feature(&cpu->env, ARM_FEATURE_V5);
779
+ set_feature(&cpu->env, ARM_FEATURE_AUXCR);
780
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
781
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
782
+ cpu->midr = 0x4106a262;
783
+ cpu->reset_fpsid = 0x410110a0;
784
+ cpu->ctr = 0x1dd20d2;
785
+ cpu->reset_sctlr = 0x00090078;
786
+ cpu->reset_auxcr = 1;
787
+
788
+ /*
789
+ * ARMv5 does not have the ID_ISAR registers, but we can still
790
+ * set the field to indicate Jazelle support within QEMU.
791
+ */
792
+ cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
793
+ /*
794
+ * Similarly, we need to set MVFR0 fields to enable vfp and short vector
795
+ * support even though ARMv5 doesn't have this register.
796
+ */
797
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
798
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
799
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
800
+
801
+ {
802
+ /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
803
+ ARMCPRegInfo ifar = {
804
+ .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
805
+ .access = PL1_RW,
806
+ .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
807
+ .resetvalue = 0
808
+ };
809
+ define_one_arm_cp_reg(cpu, &ifar);
810
+ }
811
+}
812
+
813
+static void arm1136_r2_initfn(Object *obj)
814
+{
815
+ ARMCPU *cpu = ARM_CPU(obj);
816
+ /*
817
+ * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
818
+ * older core than plain "arm1136". In particular this does not
819
+ * have the v6K features.
820
+ * These ID register values are correct for 1136 but may be wrong
821
+ * for 1136_r2 (in particular r0p2 does not actually implement most
822
+ * of the ID registers).
823
+ */
824
+
825
+ cpu->dtb_compatible = "arm,arm1136";
826
+ set_feature(&cpu->env, ARM_FEATURE_V6);
827
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
828
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
829
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
830
+ cpu->midr = 0x4107b362;
831
+ cpu->reset_fpsid = 0x410120b4;
832
+ cpu->isar.mvfr0 = 0x11111111;
833
+ cpu->isar.mvfr1 = 0x00000000;
834
+ cpu->ctr = 0x1dd20d2;
835
+ cpu->reset_sctlr = 0x00050078;
836
+ cpu->id_pfr0 = 0x111;
837
+ cpu->id_pfr1 = 0x1;
838
+ cpu->isar.id_dfr0 = 0x2;
839
+ cpu->id_afr0 = 0x3;
840
+ cpu->isar.id_mmfr0 = 0x01130003;
841
+ cpu->isar.id_mmfr1 = 0x10030302;
842
+ cpu->isar.id_mmfr2 = 0x01222110;
843
+ cpu->isar.id_isar0 = 0x00140011;
844
+ cpu->isar.id_isar1 = 0x12002111;
845
+ cpu->isar.id_isar2 = 0x11231111;
846
+ cpu->isar.id_isar3 = 0x01102131;
847
+ cpu->isar.id_isar4 = 0x141;
848
+ cpu->reset_auxcr = 7;
849
+}
850
+
851
+static void arm1136_initfn(Object *obj)
852
+{
853
+ ARMCPU *cpu = ARM_CPU(obj);
854
+
855
+ cpu->dtb_compatible = "arm,arm1136";
856
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
857
+ set_feature(&cpu->env, ARM_FEATURE_V6);
858
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
859
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
860
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
861
+ cpu->midr = 0x4117b363;
862
+ cpu->reset_fpsid = 0x410120b4;
863
+ cpu->isar.mvfr0 = 0x11111111;
864
+ cpu->isar.mvfr1 = 0x00000000;
865
+ cpu->ctr = 0x1dd20d2;
866
+ cpu->reset_sctlr = 0x00050078;
867
+ cpu->id_pfr0 = 0x111;
868
+ cpu->id_pfr1 = 0x1;
869
+ cpu->isar.id_dfr0 = 0x2;
870
+ cpu->id_afr0 = 0x3;
871
+ cpu->isar.id_mmfr0 = 0x01130003;
872
+ cpu->isar.id_mmfr1 = 0x10030302;
873
+ cpu->isar.id_mmfr2 = 0x01222110;
874
+ cpu->isar.id_isar0 = 0x00140011;
875
+ cpu->isar.id_isar1 = 0x12002111;
876
+ cpu->isar.id_isar2 = 0x11231111;
877
+ cpu->isar.id_isar3 = 0x01102131;
878
+ cpu->isar.id_isar4 = 0x141;
879
+ cpu->reset_auxcr = 7;
880
+}
881
+
882
+static void arm1176_initfn(Object *obj)
883
+{
884
+ ARMCPU *cpu = ARM_CPU(obj);
885
+
886
+ cpu->dtb_compatible = "arm,arm1176";
887
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
888
+ set_feature(&cpu->env, ARM_FEATURE_VAPA);
889
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
890
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
891
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
892
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
893
+ cpu->midr = 0x410fb767;
894
+ cpu->reset_fpsid = 0x410120b5;
895
+ cpu->isar.mvfr0 = 0x11111111;
896
+ cpu->isar.mvfr1 = 0x00000000;
897
+ cpu->ctr = 0x1dd20d2;
898
+ cpu->reset_sctlr = 0x00050078;
899
+ cpu->id_pfr0 = 0x111;
900
+ cpu->id_pfr1 = 0x11;
901
+ cpu->isar.id_dfr0 = 0x33;
902
+ cpu->id_afr0 = 0;
903
+ cpu->isar.id_mmfr0 = 0x01130003;
904
+ cpu->isar.id_mmfr1 = 0x10030302;
905
+ cpu->isar.id_mmfr2 = 0x01222100;
906
+ cpu->isar.id_isar0 = 0x0140011;
907
+ cpu->isar.id_isar1 = 0x12002111;
908
+ cpu->isar.id_isar2 = 0x11231121;
909
+ cpu->isar.id_isar3 = 0x01102131;
910
+ cpu->isar.id_isar4 = 0x01141;
911
+ cpu->reset_auxcr = 7;
912
+}
913
+
914
+static void arm11mpcore_initfn(Object *obj)
915
+{
916
+ ARMCPU *cpu = ARM_CPU(obj);
917
+
918
+ cpu->dtb_compatible = "arm,arm11mpcore";
919
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
920
+ set_feature(&cpu->env, ARM_FEATURE_VAPA);
921
+ set_feature(&cpu->env, ARM_FEATURE_MPIDR);
922
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
923
+ cpu->midr = 0x410fb022;
924
+ cpu->reset_fpsid = 0x410120b4;
925
+ cpu->isar.mvfr0 = 0x11111111;
926
+ cpu->isar.mvfr1 = 0x00000000;
927
+ cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
928
+ cpu->id_pfr0 = 0x111;
929
+ cpu->id_pfr1 = 0x1;
930
+ cpu->isar.id_dfr0 = 0;
931
+ cpu->id_afr0 = 0x2;
932
+ cpu->isar.id_mmfr0 = 0x01100103;
933
+ cpu->isar.id_mmfr1 = 0x10020302;
934
+ cpu->isar.id_mmfr2 = 0x01222000;
935
+ cpu->isar.id_isar0 = 0x00100011;
936
+ cpu->isar.id_isar1 = 0x12002111;
937
+ cpu->isar.id_isar2 = 0x11221011;
938
+ cpu->isar.id_isar3 = 0x01102131;
939
+ cpu->isar.id_isar4 = 0x141;
940
+ cpu->reset_auxcr = 1;
941
+}
942
+
943
+static void cortex_m0_initfn(Object *obj)
944
+{
945
+ ARMCPU *cpu = ARM_CPU(obj);
946
+ set_feature(&cpu->env, ARM_FEATURE_V6);
947
+ set_feature(&cpu->env, ARM_FEATURE_M);
948
+
949
+ cpu->midr = 0x410cc200;
950
+}
951
+
952
+static void cortex_m3_initfn(Object *obj)
953
+{
954
+ ARMCPU *cpu = ARM_CPU(obj);
955
+ set_feature(&cpu->env, ARM_FEATURE_V7);
956
+ set_feature(&cpu->env, ARM_FEATURE_M);
957
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
958
+ cpu->midr = 0x410fc231;
959
+ cpu->pmsav7_dregion = 8;
960
+ cpu->id_pfr0 = 0x00000030;
961
+ cpu->id_pfr1 = 0x00000200;
962
+ cpu->isar.id_dfr0 = 0x00100000;
963
+ cpu->id_afr0 = 0x00000000;
964
+ cpu->isar.id_mmfr0 = 0x00000030;
965
+ cpu->isar.id_mmfr1 = 0x00000000;
966
+ cpu->isar.id_mmfr2 = 0x00000000;
967
+ cpu->isar.id_mmfr3 = 0x00000000;
968
+ cpu->isar.id_isar0 = 0x01141110;
969
+ cpu->isar.id_isar1 = 0x02111000;
970
+ cpu->isar.id_isar2 = 0x21112231;
971
+ cpu->isar.id_isar3 = 0x01111110;
972
+ cpu->isar.id_isar4 = 0x01310102;
973
+ cpu->isar.id_isar5 = 0x00000000;
974
+ cpu->isar.id_isar6 = 0x00000000;
975
+}
976
+
977
+static void cortex_m4_initfn(Object *obj)
978
+{
979
+ ARMCPU *cpu = ARM_CPU(obj);
980
+
981
+ set_feature(&cpu->env, ARM_FEATURE_V7);
982
+ set_feature(&cpu->env, ARM_FEATURE_M);
983
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
984
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
985
+ cpu->midr = 0x410fc240; /* r0p0 */
986
+ cpu->pmsav7_dregion = 8;
987
+ cpu->isar.mvfr0 = 0x10110021;
988
+ cpu->isar.mvfr1 = 0x11000011;
989
+ cpu->isar.mvfr2 = 0x00000000;
990
+ cpu->id_pfr0 = 0x00000030;
991
+ cpu->id_pfr1 = 0x00000200;
992
+ cpu->isar.id_dfr0 = 0x00100000;
993
+ cpu->id_afr0 = 0x00000000;
994
+ cpu->isar.id_mmfr0 = 0x00000030;
995
+ cpu->isar.id_mmfr1 = 0x00000000;
996
+ cpu->isar.id_mmfr2 = 0x00000000;
997
+ cpu->isar.id_mmfr3 = 0x00000000;
998
+ cpu->isar.id_isar0 = 0x01141110;
999
+ cpu->isar.id_isar1 = 0x02111000;
1000
+ cpu->isar.id_isar2 = 0x21112231;
1001
+ cpu->isar.id_isar3 = 0x01111110;
1002
+ cpu->isar.id_isar4 = 0x01310102;
1003
+ cpu->isar.id_isar5 = 0x00000000;
1004
+ cpu->isar.id_isar6 = 0x00000000;
1005
+}
1006
+
1007
+static void cortex_m7_initfn(Object *obj)
1008
+{
1009
+ ARMCPU *cpu = ARM_CPU(obj);
1010
+
1011
+ set_feature(&cpu->env, ARM_FEATURE_V7);
1012
+ set_feature(&cpu->env, ARM_FEATURE_M);
1013
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1014
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1015
+ cpu->midr = 0x411fc272; /* r1p2 */
1016
+ cpu->pmsav7_dregion = 8;
1017
+ cpu->isar.mvfr0 = 0x10110221;
1018
+ cpu->isar.mvfr1 = 0x12000011;
1019
+ cpu->isar.mvfr2 = 0x00000040;
1020
+ cpu->id_pfr0 = 0x00000030;
1021
+ cpu->id_pfr1 = 0x00000200;
1022
+ cpu->isar.id_dfr0 = 0x00100000;
1023
+ cpu->id_afr0 = 0x00000000;
1024
+ cpu->isar.id_mmfr0 = 0x00100030;
1025
+ cpu->isar.id_mmfr1 = 0x00000000;
1026
+ cpu->isar.id_mmfr2 = 0x01000000;
1027
+ cpu->isar.id_mmfr3 = 0x00000000;
1028
+ cpu->isar.id_isar0 = 0x01101110;
1029
+ cpu->isar.id_isar1 = 0x02112000;
1030
+ cpu->isar.id_isar2 = 0x20232231;
1031
+ cpu->isar.id_isar3 = 0x01111131;
1032
+ cpu->isar.id_isar4 = 0x01310132;
1033
+ cpu->isar.id_isar5 = 0x00000000;
1034
+ cpu->isar.id_isar6 = 0x00000000;
1035
+}
1036
+
1037
+static void cortex_m33_initfn(Object *obj)
1038
+{
1039
+ ARMCPU *cpu = ARM_CPU(obj);
1040
+
1041
+ set_feature(&cpu->env, ARM_FEATURE_V8);
1042
+ set_feature(&cpu->env, ARM_FEATURE_M);
1043
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1044
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
1045
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1046
+ cpu->midr = 0x410fd213; /* r0p3 */
1047
+ cpu->pmsav7_dregion = 16;
1048
+ cpu->sau_sregion = 8;
1049
+ cpu->isar.mvfr0 = 0x10110021;
1050
+ cpu->isar.mvfr1 = 0x11000011;
1051
+ cpu->isar.mvfr2 = 0x00000040;
1052
+ cpu->id_pfr0 = 0x00000030;
1053
+ cpu->id_pfr1 = 0x00000210;
1054
+ cpu->isar.id_dfr0 = 0x00200000;
1055
+ cpu->id_afr0 = 0x00000000;
1056
+ cpu->isar.id_mmfr0 = 0x00101F40;
1057
+ cpu->isar.id_mmfr1 = 0x00000000;
1058
+ cpu->isar.id_mmfr2 = 0x01000000;
1059
+ cpu->isar.id_mmfr3 = 0x00000000;
1060
+ cpu->isar.id_isar0 = 0x01101110;
1061
+ cpu->isar.id_isar1 = 0x02212000;
1062
+ cpu->isar.id_isar2 = 0x20232232;
1063
+ cpu->isar.id_isar3 = 0x01111131;
1064
+ cpu->isar.id_isar4 = 0x01310132;
1065
+ cpu->isar.id_isar5 = 0x00000000;
1066
+ cpu->isar.id_isar6 = 0x00000000;
1067
+ cpu->clidr = 0x00000000;
1068
+ cpu->ctr = 0x8000c000;
1069
+}
1070
+
1071
+static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
1072
+ /* Dummy the TCM region regs for the moment */
1073
+ { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1074
+ .access = PL1_RW, .type = ARM_CP_CONST },
1075
+ { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1076
+ .access = PL1_RW, .type = ARM_CP_CONST },
1077
+ { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
1078
+ .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
1079
+ REGINFO_SENTINEL
1080
+};
1081
+
1082
+static void cortex_r5_initfn(Object *obj)
1083
+{
1084
+ ARMCPU *cpu = ARM_CPU(obj);
1085
+
1086
+ set_feature(&cpu->env, ARM_FEATURE_V7);
1087
+ set_feature(&cpu->env, ARM_FEATURE_V7MP);
1088
+ set_feature(&cpu->env, ARM_FEATURE_PMSA);
1089
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
1090
+ cpu->midr = 0x411fc153; /* r1p3 */
1091
+ cpu->id_pfr0 = 0x0131;
1092
+ cpu->id_pfr1 = 0x001;
1093
+ cpu->isar.id_dfr0 = 0x010400;
1094
+ cpu->id_afr0 = 0x0;
1095
+ cpu->isar.id_mmfr0 = 0x0210030;
1096
+ cpu->isar.id_mmfr1 = 0x00000000;
1097
+ cpu->isar.id_mmfr2 = 0x01200000;
1098
+ cpu->isar.id_mmfr3 = 0x0211;
1099
+ cpu->isar.id_isar0 = 0x02101111;
1100
+ cpu->isar.id_isar1 = 0x13112111;
1101
+ cpu->isar.id_isar2 = 0x21232141;
1102
+ cpu->isar.id_isar3 = 0x01112131;
1103
+ cpu->isar.id_isar4 = 0x0010142;
1104
+ cpu->isar.id_isar5 = 0x0;
1105
+ cpu->isar.id_isar6 = 0x0;
1106
+ cpu->mp_is_up = true;
1107
+ cpu->pmsav7_dregion = 16;
1108
+ define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
1109
+}
1110
+
1111
+static void cortex_r5f_initfn(Object *obj)
1112
+{
1113
+ ARMCPU *cpu = ARM_CPU(obj);
1114
+
1115
+ cortex_r5_initfn(obj);
1116
+ cpu->isar.mvfr0 = 0x10110221;
1117
+ cpu->isar.mvfr1 = 0x00000011;
1118
+}
1119
+
1120
+static void ti925t_initfn(Object *obj)
1121
+{
1122
+ ARMCPU *cpu = ARM_CPU(obj);
1123
+ set_feature(&cpu->env, ARM_FEATURE_V4T);
1124
+ set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1125
+ cpu->midr = ARM_CPUID_TI925T;
1126
+ cpu->ctr = 0x5109149;
1127
+ cpu->reset_sctlr = 0x00000070;
1128
+}
1129
+
1130
+static void sa1100_initfn(Object *obj)
1131
+{
1132
+ ARMCPU *cpu = ARM_CPU(obj);
1133
+
1134
+ cpu->dtb_compatible = "intel,sa1100";
1135
+ set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1136
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1137
+ cpu->midr = 0x4401A11B;
1138
+ cpu->reset_sctlr = 0x00000070;
1139
+}
1140
+
1141
+static void sa1110_initfn(Object *obj)
1142
+{
1143
+ ARMCPU *cpu = ARM_CPU(obj);
1144
+ set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1145
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1146
+ cpu->midr = 0x6901B119;
1147
+ cpu->reset_sctlr = 0x00000070;
1148
+}
1149
+
1150
+static void pxa250_initfn(Object *obj)
1151
+{
1152
+ ARMCPU *cpu = ARM_CPU(obj);
1153
+
1154
+ cpu->dtb_compatible = "marvell,xscale";
1155
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1156
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1157
+ cpu->midr = 0x69052100;
1158
+ cpu->ctr = 0xd172172;
1159
+ cpu->reset_sctlr = 0x00000078;
1160
+}
1161
+
1162
+static void pxa255_initfn(Object *obj)
1163
+{
1164
+ ARMCPU *cpu = ARM_CPU(obj);
1165
+
1166
+ cpu->dtb_compatible = "marvell,xscale";
1167
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1168
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1169
+ cpu->midr = 0x69052d00;
1170
+ cpu->ctr = 0xd172172;
1171
+ cpu->reset_sctlr = 0x00000078;
1172
+}
1173
+
1174
+static void pxa260_initfn(Object *obj)
1175
+{
1176
+ ARMCPU *cpu = ARM_CPU(obj);
1177
+
1178
+ cpu->dtb_compatible = "marvell,xscale";
1179
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1180
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1181
+ cpu->midr = 0x69052903;
1182
+ cpu->ctr = 0xd172172;
1183
+ cpu->reset_sctlr = 0x00000078;
1184
+}
1185
+
1186
+static void pxa261_initfn(Object *obj)
1187
+{
1188
+ ARMCPU *cpu = ARM_CPU(obj);
1189
+
1190
+ cpu->dtb_compatible = "marvell,xscale";
1191
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1192
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1193
+ cpu->midr = 0x69052d05;
1194
+ cpu->ctr = 0xd172172;
1195
+ cpu->reset_sctlr = 0x00000078;
1196
+}
1197
+
1198
+static void pxa262_initfn(Object *obj)
1199
+{
1200
+ ARMCPU *cpu = ARM_CPU(obj);
1201
+
1202
+ cpu->dtb_compatible = "marvell,xscale";
1203
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1204
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1205
+ cpu->midr = 0x69052d06;
1206
+ cpu->ctr = 0xd172172;
1207
+ cpu->reset_sctlr = 0x00000078;
1208
+}
1209
+
1210
+static void pxa270a0_initfn(Object *obj)
1211
+{
1212
+ ARMCPU *cpu = ARM_CPU(obj);
1213
+
1214
+ cpu->dtb_compatible = "marvell,xscale";
1215
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1216
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1217
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1218
+ cpu->midr = 0x69054110;
1219
+ cpu->ctr = 0xd172172;
1220
+ cpu->reset_sctlr = 0x00000078;
1221
+}
1222
+
1223
+static void pxa270a1_initfn(Object *obj)
1224
+{
1225
+ ARMCPU *cpu = ARM_CPU(obj);
1226
+
1227
+ cpu->dtb_compatible = "marvell,xscale";
1228
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1229
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1230
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1231
+ cpu->midr = 0x69054111;
1232
+ cpu->ctr = 0xd172172;
1233
+ cpu->reset_sctlr = 0x00000078;
1234
+}
1235
+
1236
+static void pxa270b0_initfn(Object *obj)
1237
+{
1238
+ ARMCPU *cpu = ARM_CPU(obj);
1239
+
1240
+ cpu->dtb_compatible = "marvell,xscale";
1241
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1242
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1243
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1244
+ cpu->midr = 0x69054112;
1245
+ cpu->ctr = 0xd172172;
1246
+ cpu->reset_sctlr = 0x00000078;
1247
+}
1248
+
1249
+static void pxa270b1_initfn(Object *obj)
1250
+{
1251
+ ARMCPU *cpu = ARM_CPU(obj);
1252
+
1253
+ cpu->dtb_compatible = "marvell,xscale";
1254
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1255
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1256
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1257
+ cpu->midr = 0x69054113;
1258
+ cpu->ctr = 0xd172172;
1259
+ cpu->reset_sctlr = 0x00000078;
1260
+}
1261
+
1262
+static void pxa270c0_initfn(Object *obj)
1263
+{
1264
+ ARMCPU *cpu = ARM_CPU(obj);
1265
+
1266
+ cpu->dtb_compatible = "marvell,xscale";
1267
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1268
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1269
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1270
+ cpu->midr = 0x69054114;
1271
+ cpu->ctr = 0xd172172;
1272
+ cpu->reset_sctlr = 0x00000078;
1273
+}
1274
+
1275
+static void pxa270c5_initfn(Object *obj)
1276
+{
1277
+ ARMCPU *cpu = ARM_CPU(obj);
1278
+
1279
+ cpu->dtb_compatible = "marvell,xscale";
1280
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1281
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1282
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1283
+ cpu->midr = 0x69054117;
1284
+ cpu->ctr = 0xd172172;
1285
+ cpu->reset_sctlr = 0x00000078;
1286
+}
1287
+
1288
+static void arm_v7m_class_init(ObjectClass *oc, void *data)
1289
+{
1290
+ ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1291
+ CPUClass *cc = CPU_CLASS(oc);
1292
+
1293
+ acc->info = data;
1294
+#ifndef CONFIG_USER_ONLY
1295
+ cc->do_interrupt = arm_v7m_cpu_do_interrupt;
1296
+#endif
1297
+
1298
+ cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
1299
+}
1300
+
1301
+static const ARMCPUInfo arm_tcg_cpus[] = {
1302
+ { .name = "arm926", .initfn = arm926_initfn },
1303
+ { .name = "arm946", .initfn = arm946_initfn },
1304
+ { .name = "arm1026", .initfn = arm1026_initfn },
1305
+ /*
1306
+ * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1307
+ * older core than plain "arm1136". In particular this does not
1308
+ * have the v6K features.
1309
+ */
1310
+ { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1311
+ { .name = "arm1136", .initfn = arm1136_initfn },
1312
+ { .name = "arm1176", .initfn = arm1176_initfn },
1313
+ { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1314
+ { .name = "cortex-m0", .initfn = cortex_m0_initfn,
1315
+ .class_init = arm_v7m_class_init },
1316
+ { .name = "cortex-m3", .initfn = cortex_m3_initfn,
1317
+ .class_init = arm_v7m_class_init },
1318
+ { .name = "cortex-m4", .initfn = cortex_m4_initfn,
1319
+ .class_init = arm_v7m_class_init },
1320
+ { .name = "cortex-m7", .initfn = cortex_m7_initfn,
1321
+ .class_init = arm_v7m_class_init },
1322
+ { .name = "cortex-m33", .initfn = cortex_m33_initfn,
1323
+ .class_init = arm_v7m_class_init },
1324
+ { .name = "cortex-r5", .initfn = cortex_r5_initfn },
1325
+ { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
1326
+ { .name = "ti925t", .initfn = ti925t_initfn },
1327
+ { .name = "sa1100", .initfn = sa1100_initfn },
1328
+ { .name = "sa1110", .initfn = sa1110_initfn },
1329
+ { .name = "pxa250", .initfn = pxa250_initfn },
1330
+ { .name = "pxa255", .initfn = pxa255_initfn },
1331
+ { .name = "pxa260", .initfn = pxa260_initfn },
1332
+ { .name = "pxa261", .initfn = pxa261_initfn },
1333
+ { .name = "pxa262", .initfn = pxa262_initfn },
1334
+ /* "pxa270" is an alias for "pxa270-a0" */
1335
+ { .name = "pxa270", .initfn = pxa270a0_initfn },
1336
+ { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1337
+ { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1338
+ { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1339
+ { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1340
+ { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1341
+ { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
1342
+};
1343
+
1344
+static void arm_tcg_cpu_register_types(void)
1345
+{
1346
+ size_t i;
1347
+
1348
+ for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
1349
+ arm_cpu_register(&arm_tcg_cpus[i]);
1350
+ }
1351
+}
1352
+
1353
+type_init(arm_tcg_cpu_register_types)
1354
+
1355
+#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
1356
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
1357
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
1358
--- a/target/arm/Makefile.objs
33
--- a/fpu/softfloat-specialize.c.inc
1359
+++ b/target/arm/Makefile.objs
34
+++ b/fpu/softfloat-specialize.c.inc
1360
@@ -XXX,XX +XXX,XX @@ obj-y += translate.o op_helper.o
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
1361
obj-y += crypto_helper.o
36
/*
1362
obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
37
* Temporarily fall back to ifdef ladder
1363
obj-y += m_helper.o
38
*/
1364
+obj-y += cpu_tcg.o
39
-#if defined(TARGET_ARM)
1365
40
- /*
1366
obj-$(CONFIG_SOFTMMU) += psci.o
41
- * For ARM, the (inf,zero,qnan) case returns the default NaN,
1367
42
- * but (inf,zero,snan) returns the input NaN.
43
- */
44
- rule = float_infzeronan_dnan_if_qnan;
45
-#elif defined(TARGET_MIPS)
46
+#if defined(TARGET_MIPS)
47
if (snan_bit_is_one(status)) {
48
/*
49
* For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
1368
--
50
--
1369
2.20.1
51
2.34.1
1370
1371
diff view generated by jsdifflib
New patch
[PULL 11/72] target/s390: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for s390, so we
2
can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-7-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_infzeronan_rule(float_infzeronan_dnan_always,
21
+ &env->fpu_status);
22
/* fall through */
23
case RESET_TYPE_S390_CPU_NORMAL:
24
env->psw.mask &= ~PSW_MASK_RI;
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
* a default NaN
31
*/
32
rule = float_infzeronan_dnan_never;
33
-#elif defined(TARGET_S390X)
34
- rule = float_infzeronan_dnan_always;
35
#endif
36
}
37
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/72] target/ppc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the PPC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-8-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 7 +++++++
9
fpu/softfloat-specialize.c.inc | 7 +------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
22
+ * to return an input NaN if we have one (ie c) rather than generating
23
+ * a default NaN
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
27
28
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
29
ppc_spr_t *spr = &env->spr_cb[i];
30
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
31
index XXXXXXX..XXXXXXX 100644
32
--- a/fpu/softfloat-specialize.c.inc
33
+++ b/fpu/softfloat-specialize.c.inc
34
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
*/
36
rule = float_infzeronan_dnan_never;
37
}
38
-#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
39
+#elif defined(TARGET_SPARC) || \
40
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
41
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
42
/*
43
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
44
* case sets InvalidOp and returns the input value 'c'
45
*/
46
- /*
47
- * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
48
- * to return an input NaN if we have one (ie c) rather than generating
49
- * a default NaN
50
- */
51
rule = float_infzeronan_dnan_never;
52
#endif
53
}
54
--
55
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/72] target/mips: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the MIPS target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-9-peter.maydell@linaro.org
7
---
8
target/mips/fpu_helper.h | 9 +++++++++
9
target/mips/msa.c | 4 ++++
10
fpu/softfloat-specialize.c.inc | 16 +---------------
11
3 files changed, 14 insertions(+), 15 deletions(-)
12
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/mips/fpu_helper.h
16
+++ b/target/mips/fpu_helper.h
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_flush_mode(CPUMIPSState *env)
18
static inline void restore_snan_bit_mode(CPUMIPSState *env)
19
{
20
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
21
+ FloatInfZeroNaNRule izn_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status);
28
set_default_nan_mode(!nan2008, &env->active_fpu.fp_status);
29
+ /*
30
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
31
+ * case sets InvalidOp and returns the default NaN.
32
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
33
+ * case sets InvalidOp and returns the input value 'c'.
34
+ */
35
+ izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
36
+ set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
37
}
38
39
static inline void restore_fp_status(CPUMIPSState *env)
40
diff --git a/target/mips/msa.c b/target/mips/msa.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/mips/msa.c
43
+++ b/target/mips/msa.c
44
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
45
46
/* set proper signanling bit meaning ("1" means "quiet") */
47
set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
48
+
49
+ /* Inf * 0 + NaN returns the input NaN */
50
+ set_float_infzeronan_rule(float_infzeronan_dnan_never,
51
+ &env->active_tc.msa_fp_status);
52
}
53
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
54
index XXXXXXX..XXXXXXX 100644
55
--- a/fpu/softfloat-specialize.c.inc
56
+++ b/fpu/softfloat-specialize.c.inc
57
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
58
/*
59
* Temporarily fall back to ifdef ladder
60
*/
61
-#if defined(TARGET_MIPS)
62
- if (snan_bit_is_one(status)) {
63
- /*
64
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
65
- * case sets InvalidOp and returns the default NaN
66
- */
67
- rule = float_infzeronan_dnan_always;
68
- } else {
69
- /*
70
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
71
- * case sets InvalidOp and returns the input value 'c'
72
- */
73
- rule = float_infzeronan_dnan_never;
74
- }
75
-#elif defined(TARGET_SPARC) || \
76
+#if defined(TARGET_SPARC) || \
77
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
78
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
79
/*
80
--
81
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/72] target/sparc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the SPARC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-10-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_SPARC) || \
34
- defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
35
+#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
36
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
37
/*
38
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/72] target/xtensa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the xtensa target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-11-peter.maydell@linaro.org
7
---
8
target/xtensa/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 +-
10
2 files changed, 3 insertions(+), 1 deletion(-)
11
12
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/xtensa/cpu.c
15
+++ b/target/xtensa/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
17
reset_mmu(env);
18
cs->halted = env->runstall;
19
#endif
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
set_no_signaling_nans(!dfpu, &env->fp_status);
23
xtensa_use_first_nan(env, !dfpu);
24
}
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
34
+#if defined(TARGET_HPPA) || \
35
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
36
/*
37
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 16/72] target/x86: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the x86 target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-12-peter.maydell@linaro.org
6
---
7
target/i386/tcg/fpu_helper.c | 7 +++++++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 8 insertions(+), 1 deletion(-)
10
11
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/i386/tcg/fpu_helper.c
14
+++ b/target/i386/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status);
18
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status);
19
+ /*
20
+ * Only SSE has multiply-add instructions. In the SDM Section 14.5.2
21
+ * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is
22
+ * specified -- for 0 * inf + NaN the input NaN is selected, and if
23
+ * there are multiple input NaNs they are selected in the order a, b, c.
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
26
}
27
28
static inline uint8_t save_exception_flags(CPUX86State *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
34
* Temporarily fall back to ifdef ladder
35
*/
36
#if defined(TARGET_HPPA) || \
37
- defined(TARGET_I386) || defined(TARGET_LOONGARCH)
38
+ defined(TARGET_LOONGARCH)
39
/*
40
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
41
* case sets InvalidOp and returns the input value 'c'
42
--
43
2.34.1
diff view generated by jsdifflib
New patch
[PULL 17/72] target/loongarch: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the loongarch target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-13-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 5 +++++
8
fpu/softfloat-specialize.c.inc | 7 +------
9
2 files changed, 6 insertions(+), 6 deletions(-)
10
11
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/loongarch/tcg/fpu_helper.c
14
+++ b/target/loongarch/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
16
&env->fp_status);
17
set_flush_to_zero(0, &env->fp_status);
18
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
19
+ /*
20
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
21
+ * case sets InvalidOp and returns the input value 'c'
22
+ */
23
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
}
25
26
int ieee_ex_to_loongarch(int xcpt)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
32
/*
33
* Temporarily fall back to ifdef ladder
34
*/
35
-#if defined(TARGET_HPPA) || \
36
- defined(TARGET_LOONGARCH)
37
- /*
38
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
- * case sets InvalidOp and returns the input value 'c'
40
- */
41
+#if defined(TARGET_HPPA)
42
rule = float_infzeronan_dnan_never;
43
#endif
44
}
45
--
46
2.34.1
diff view generated by jsdifflib
New patch
[PULL 18/72] target/hppa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the HPPA target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
As this is the last target to be converted to explicitly setting
5
the rule, we can remove the fallback code in pickNaNMulAdd()
6
entirely.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20241202131347.498124-14-peter.maydell@linaro.org
11
---
12
target/hppa/fpu_helper.c | 2 ++
13
fpu/softfloat-specialize.c.inc | 13 +------------
14
2 files changed, 3 insertions(+), 12 deletions(-)
15
16
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/hppa/fpu_helper.c
19
+++ b/target/hppa/fpu_helper.c
20
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
21
* HPPA does note implement a CPU reset method at all...
22
*/
23
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
24
+ /* For inf * 0 + NaN, return the input NaN */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
}
27
28
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
34
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
bool infzero, float_status *status)
36
{
37
- FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
38
-
39
/*
40
* We guarantee not to require the target to tell us how to
41
* pick a NaN if we're always returning the default NaN.
42
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
43
*/
44
assert(!status->default_nan_mode);
45
46
- if (rule == float_infzeronan_none) {
47
- /*
48
- * Temporarily fall back to ifdef ladder
49
- */
50
-#if defined(TARGET_HPPA)
51
- rule = float_infzeronan_dnan_never;
52
-#endif
53
- }
54
-
55
if (infzero) {
56
/*
57
* Inf * 0 + NaN -- some implementations return the default NaN here,
58
* and some return the input NaN.
59
*/
60
- switch (rule) {
61
+ switch (status->float_infzeronan_rule) {
62
case float_infzeronan_dnan_never:
63
return 2;
64
case float_infzeronan_dnan_always:
65
--
66
2.34.1
diff view generated by jsdifflib
New patch
[PULL 19/72] softfloat: Pass have_snan to pickNaNMulAdd
1
The new implementation of pickNaNMulAdd() will find it convenient
2
to know whether at least one of the three arguments to the muladd
3
was a signaling NaN. We already calculate that in the caller,
4
so pass it in as a new bool have_snan.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-15-peter.maydell@linaro.org
9
---
10
fpu/softfloat-parts.c.inc | 5 +++--
11
fpu/softfloat-specialize.c.inc | 2 +-
12
2 files changed, 4 insertions(+), 3 deletions(-)
13
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
16
--- a/fpu/softfloat-parts.c.inc
17
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
{
20
int which;
21
bool infzero = (ab_mask == float_cmask_infzero);
22
+ bool have_snan = (abc_mask & float_cmask_snan);
23
24
- if (unlikely(abc_mask & float_cmask_snan)) {
25
+ if (unlikely(have_snan)) {
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
27
}
28
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
30
if (s->default_nan_mode) {
31
which = 3;
32
} else {
33
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
35
}
36
37
if (which == 3) {
38
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
39
index XXXXXXX..XXXXXXX 100644
40
--- a/fpu/softfloat-specialize.c.inc
41
+++ b/fpu/softfloat-specialize.c.inc
42
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
43
| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
44
*----------------------------------------------------------------------------*/
45
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
46
- bool infzero, float_status *status)
47
+ bool infzero, bool have_snan, float_status *status)
48
{
49
/*
50
* We guarantee not to require the target to tell us how to
51
--
52
2.34.1
diff view generated by jsdifflib
[PULL 01/34] aspeed: Add boot stub for smp booting
[PULL 20/72] softfloat: Allow runtime choice of NaN propagation for muladd
1
From: Joel Stanley <joel@jms.id.au>
1
IEEE 758 does not define a fixed rule for which NaN to pick as the
2
2
result if both operands of a 3-operand fused multiply-add operation
3
This is a boot stub that is similar to the code u-boot runs, allowing
3
are NaNs. As a result different architectures have ended up with
4
the kernel to boot the secondary CPU.
4
different rules for propagating NaNs.
5
5
6
u-boot works as follows:
6
QEMU currently hardcodes the NaN propagation logic into the binary
7
7
because pickNaNMulAdd() has an ifdef ladder for different targets.
8
1. Initialises the SMP mailbox area in the SCU at 0x1e6e2180 with default values
8
We want to make the propagation rule instead be selectable at
9
9
runtime, because:
10
2. Copies a stub named 'mailbox_insn' from flash to the SCU, just above the
10
* this will let us have multiple targets in one QEMU binary
11
mailbox area
11
* the Arm FEAT_AFP architectural feature includes letting
12
12
the guest select a NaN propagation rule at runtime
13
3. Sets AST_SMP_MBOX_FIELD_READY to a magic value to indicate the
13
14
secondary can begin execution from the stub
14
In this commit we add an enum for the propagation rule, the field in
15
15
float_status, and the corresponding getters and setters. We change
16
4. The stub waits until the AST_SMP_MBOX_FIELD_GOSIGN register is set to
16
pickNaNMulAdd to honour this, but because all targets still leave
17
a magic value
17
this field at its default 0 value, the fallback logic will pick the
18
18
rule type with the old ifdef ladder.
19
5. Jumps to the address in AST_SMP_MBOX_FIELD_ENTRY, starting Linux
19
20
20
It's valid not to set a propagation rule if default_nan_mode is
21
Linux indicates it is ready by writing the address of its entrypoint
21
enabled, because in that case there's no need to pick a NaN; all the
22
function to AST_SMP_MBOX_FIELD_ENTRY and the 'go' magic number to
22
callers of pickNaNMulAdd() catch this case and skip calling it.
23
AST_SMP_MBOX_FIELD_GOSIGN. The secondary CPU sees this at step 4 and
23
24
breaks out of it's loop.
25
26
To be compatible, a fixed qemu stub is loaded into the mailbox area. As
27
qemu can ensure the stub is loaded before execution starts, we do not
28
need to emulate the AST_SMP_MBOX_FIELD_READY behaviour of u-boot. The
29
secondary CPU's program counter points to the beginning of the stub,
30
allowing qemu to start secondaries at step four.
31
32
Reboot behaviour is preserved by resetting AST_SMP_MBOX_FIELD_GOSIGN
33
when the secondaries are reset.
34
35
This is only configured when the system is booted with -kernel and qemu
36
does not execute u-boot first.
37
38
Reviewed-by: Cédric Le Goater <clg@kaod.org>
39
Tested-by: Cédric Le Goater <clg@kaod.org>
40
Signed-off-by: Joel Stanley <joel@jms.id.au>
41
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20241202131347.498124-16-peter.maydell@linaro.org
42
---
27
---
43
hw/arm/aspeed.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++++
28
include/fpu/softfloat-helpers.h | 11 +++
44
1 file changed, 65 insertions(+)
29
include/fpu/softfloat-types.h | 55 +++++++++++
45
30
fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------
46
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
31
3 files changed, 107 insertions(+), 126 deletions(-)
32
33
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
47
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/aspeed.c
35
--- a/include/fpu/softfloat-helpers.h
49
+++ b/hw/arm/aspeed.c
36
+++ b/include/fpu/softfloat-helpers.h
50
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps max_ram_ops = {
37
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
51
.endianness = DEVICE_NATIVE_ENDIAN,
38
status->float_2nan_prop_rule = rule;
52
};
39
}
53
40
54
+#define AST_SMP_MAILBOX_BASE 0x1e6e2180
41
+static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule,
55
+#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
42
+ float_status *status)
56
+#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
57
+#define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
58
+#define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
59
+#define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
60
+#define AST_SMP_MBOX_GOSIGN 0xabbaab00
61
+
62
+static void aspeed_write_smpboot(ARMCPU *cpu,
63
+ const struct arm_boot_info *info)
64
+{
43
+{
65
+ static const uint32_t poll_mailbox_ready[] = {
44
+ status->float_3nan_prop_rule = rule;
66
+ /*
67
+ * r2 = per-cpu go sign value
68
+ * r1 = AST_SMP_MBOX_FIELD_ENTRY
69
+ * r0 = AST_SMP_MBOX_FIELD_GOSIGN
70
+ */
71
+ 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
72
+ 0xe21000ff, /* ands r0, r0, #255 */
73
+ 0xe59f201c, /* ldr r2, [pc, #28] */
74
+ 0xe1822000, /* orr r2, r2, r0 */
75
+
76
+ 0xe59f1018, /* ldr r1, [pc, #24] */
77
+ 0xe59f0018, /* ldr r0, [pc, #24] */
78
+
79
+ 0xe320f002, /* wfe */
80
+ 0xe5904000, /* ldr r4, [r0] */
81
+ 0xe1520004, /* cmp r2, r4 */
82
+ 0x1afffffb, /* bne <wfe> */
83
+ 0xe591f000, /* ldr pc, [r1] */
84
+ AST_SMP_MBOX_GOSIGN,
85
+ AST_SMP_MBOX_FIELD_ENTRY,
86
+ AST_SMP_MBOX_FIELD_GOSIGN,
87
+ };
88
+
89
+ rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
90
+ sizeof(poll_mailbox_ready),
91
+ info->smp_loader_start);
92
+}
45
+}
93
+
46
+
94
+static void aspeed_reset_secondary(ARMCPU *cpu,
47
static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
95
+ const struct arm_boot_info *info)
48
float_status *status)
49
{
50
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
51
return status->float_2nan_prop_rule;
52
}
53
54
+static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status)
96
+{
55
+{
97
+ AddressSpace *as = arm_boot_address_space(cpu, info);
56
+ return status->float_3nan_prop_rule;
98
+ CPUState *cs = CPU(cpu);
99
+
100
+ /* info->smp_bootreg_addr */
101
+ address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
102
+ MEMTXATTRS_UNSPECIFIED, NULL);
103
+ cpu_set_pc(cs, info->smp_loader_start);
104
+}
57
+}
105
+
58
+
106
#define FIRMWARE_ADDR 0x0
59
static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
107
60
{
108
static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
61
return status->float_infzeronan_rule;
109
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
62
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/include/fpu/softfloat-types.h
65
+++ b/include/fpu/softfloat-types.h
66
@@ -XXX,XX +XXX,XX @@ this code that are retained.
67
#ifndef SOFTFLOAT_TYPES_H
68
#define SOFTFLOAT_TYPES_H
69
70
+#include "hw/registerfields.h"
71
+
72
/*
73
* Software IEC/IEEE floating-point types.
74
*/
75
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
76
float_2nan_prop_x87,
77
} Float2NaNPropRule;
78
79
+/*
80
+ * 3-input NaN propagation rule, for fused multiply-add. Individual
81
+ * architectures have different rules for which input NaN is
82
+ * propagated to the output when there is more than one NaN on the
83
+ * input.
84
+ *
85
+ * If default_nan_mode is enabled then it is valid not to set a NaN
86
+ * propagation rule, because the softfloat code guarantees not to try
87
+ * to pick a NaN to propagate in default NaN mode. When not in
88
+ * default-NaN mode, it is an error for the target not to set the rule
89
+ * in float_status if it uses a muladd, and we will assert if we need
90
+ * to handle an input NaN and no rule was selected.
91
+ *
92
+ * The naming scheme for Float3NaNPropRule values is:
93
+ * float_3nan_prop_s_abc:
94
+ * = "Prefer SNaN over QNaN, then operand A over B over C"
95
+ * float_3nan_prop_abc:
96
+ * = "Prefer A over B over C regardless of SNaN vs QNAN"
97
+ *
98
+ * For QEMU, the multiply-add operation is A * B + C.
99
+ */
100
+
101
+/*
102
+ * We set the Float3NaNPropRule enum values up so we can select the
103
+ * right value in pickNaNMulAdd in a data driven way.
104
+ */
105
+FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */
106
+FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */
107
+FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */
108
+FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */
109
+
110
+#define PROPRULE(X, Y, Z) \
111
+ ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT))
112
+
113
+typedef enum __attribute__((__packed__)) {
114
+ float_3nan_prop_none = 0, /* No propagation rule specified */
115
+ float_3nan_prop_abc = PROPRULE(0, 1, 2),
116
+ float_3nan_prop_acb = PROPRULE(0, 2, 1),
117
+ float_3nan_prop_bac = PROPRULE(1, 0, 2),
118
+ float_3nan_prop_bca = PROPRULE(1, 2, 0),
119
+ float_3nan_prop_cab = PROPRULE(2, 0, 1),
120
+ float_3nan_prop_cba = PROPRULE(2, 1, 0),
121
+ float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK,
122
+ float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK,
123
+ float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK,
124
+ float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK,
125
+ float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK,
126
+ float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK,
127
+} Float3NaNPropRule;
128
+
129
+#undef PROPRULE
130
+
131
/*
132
* Rule for result of fused multiply-add 0 * Inf + NaN.
133
* This must be a NaN, but implementations differ on whether this
134
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
135
FloatRoundMode float_rounding_mode;
136
FloatX80RoundPrec floatx80_rounding_precision;
137
Float2NaNPropRule float_2nan_prop_rule;
138
+ Float3NaNPropRule float_3nan_prop_rule;
139
FloatInfZeroNaNRule float_infzeronan_rule;
140
bool tininess_before_rounding;
141
/* should denormalised results go to zero and set the inexact flag? */
142
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
143
index XXXXXXX..XXXXXXX 100644
144
--- a/fpu/softfloat-specialize.c.inc
145
+++ b/fpu/softfloat-specialize.c.inc
146
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
147
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
148
bool infzero, bool have_snan, float_status *status)
149
{
150
+ FloatClass cls[3] = { a_cls, b_cls, c_cls };
151
+ Float3NaNPropRule rule = status->float_3nan_prop_rule;
152
+ int which;
153
+
154
/*
155
* We guarantee not to require the target to tell us how to
156
* pick a NaN if we're always returning the default NaN.
157
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
110
}
158
}
111
}
159
}
112
160
113
+ if (machine->kernel_filename && bmc->soc.num_cpus > 1) {
161
+ if (rule == float_3nan_prop_none) {
114
+ /* With no u-boot we must set up a boot stub for the secondary CPU */
162
#if defined(TARGET_ARM)
115
+ MemoryRegion *smpboot = g_new(MemoryRegion, 1);
163
-
116
+ memory_region_init_ram(smpboot, OBJECT(bmc), "aspeed.smpboot",
164
- /* This looks different from the ARM ARM pseudocode, because the ARM ARM
117
+ 0x80, &error_abort);
165
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
118
+ memory_region_add_subregion(get_system_memory(),
166
- */
119
+ AST_SMP_MAILBOX_BASE, smpboot);
167
- if (is_snan(c_cls)) {
120
+
168
- return 2;
121
+ aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
169
- } else if (is_snan(a_cls)) {
122
+ aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
170
- return 0;
123
+ aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
171
- } else if (is_snan(b_cls)) {
172
- return 1;
173
- } else if (is_qnan(c_cls)) {
174
- return 2;
175
- } else if (is_qnan(a_cls)) {
176
- return 0;
177
- } else {
178
- return 1;
179
- }
180
+ /*
181
+ * This looks different from the ARM ARM pseudocode, because the ARM ARM
182
+ * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
183
+ */
184
+ rule = float_3nan_prop_s_cab;
185
#elif defined(TARGET_MIPS)
186
- if (snan_bit_is_one(status)) {
187
- /* Prefer sNaN over qNaN, in the a, b, c order. */
188
- if (is_snan(a_cls)) {
189
- return 0;
190
- } else if (is_snan(b_cls)) {
191
- return 1;
192
- } else if (is_snan(c_cls)) {
193
- return 2;
194
- } else if (is_qnan(a_cls)) {
195
- return 0;
196
- } else if (is_qnan(b_cls)) {
197
- return 1;
198
+ if (snan_bit_is_one(status)) {
199
+ rule = float_3nan_prop_s_abc;
200
} else {
201
- return 2;
202
+ rule = float_3nan_prop_s_cab;
203
}
204
- } else {
205
- /* Prefer sNaN over qNaN, in the c, a, b order. */
206
- if (is_snan(c_cls)) {
207
- return 2;
208
- } else if (is_snan(a_cls)) {
209
- return 0;
210
- } else if (is_snan(b_cls)) {
211
- return 1;
212
- } else if (is_qnan(c_cls)) {
213
- return 2;
214
- } else if (is_qnan(a_cls)) {
215
- return 0;
216
- } else {
217
- return 1;
218
- }
219
- }
220
#elif defined(TARGET_LOONGARCH64)
221
- /* Prefer sNaN over qNaN, in the c, a, b order. */
222
- if (is_snan(c_cls)) {
223
- return 2;
224
- } else if (is_snan(a_cls)) {
225
- return 0;
226
- } else if (is_snan(b_cls)) {
227
- return 1;
228
- } else if (is_qnan(c_cls)) {
229
- return 2;
230
- } else if (is_qnan(a_cls)) {
231
- return 0;
232
- } else {
233
- return 1;
234
- }
235
+ rule = float_3nan_prop_s_cab;
236
#elif defined(TARGET_PPC)
237
- /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
238
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
239
- */
240
- if (is_nan(a_cls)) {
241
- return 0;
242
- } else if (is_nan(c_cls)) {
243
- return 2;
244
- } else {
245
- return 1;
246
- }
247
+ /*
248
+ * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
249
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
250
+ */
251
+ rule = float_3nan_prop_acb;
252
#elif defined(TARGET_S390X)
253
- if (is_snan(a_cls)) {
254
- return 0;
255
- } else if (is_snan(b_cls)) {
256
- return 1;
257
- } else if (is_snan(c_cls)) {
258
- return 2;
259
- } else if (is_qnan(a_cls)) {
260
- return 0;
261
- } else if (is_qnan(b_cls)) {
262
- return 1;
263
- } else {
264
- return 2;
265
- }
266
+ rule = float_3nan_prop_s_abc;
267
#elif defined(TARGET_SPARC)
268
- /* Prefer SNaN over QNaN, order C, B, A. */
269
- if (is_snan(c_cls)) {
270
- return 2;
271
- } else if (is_snan(b_cls)) {
272
- return 1;
273
- } else if (is_snan(a_cls)) {
274
- return 0;
275
- } else if (is_qnan(c_cls)) {
276
- return 2;
277
- } else if (is_qnan(b_cls)) {
278
- return 1;
279
- } else {
280
- return 0;
281
- }
282
+ rule = float_3nan_prop_s_cba;
283
#elif defined(TARGET_XTENSA)
284
- /*
285
- * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
286
- * an input NaN if we have one (ie c).
287
- */
288
- if (status->use_first_nan) {
289
- if (is_nan(a_cls)) {
290
- return 0;
291
- } else if (is_nan(b_cls)) {
292
- return 1;
293
+ if (status->use_first_nan) {
294
+ rule = float_3nan_prop_abc;
295
} else {
296
- return 2;
297
+ rule = float_3nan_prop_cba;
298
}
299
- } else {
300
- if (is_nan(c_cls)) {
301
- return 2;
302
- } else if (is_nan(b_cls)) {
303
- return 1;
304
- } else {
305
- return 0;
306
- }
307
- }
308
#else
309
- /* A default implementation: prefer a to b to c.
310
- * This is unlikely to actually match any real implementation.
311
- */
312
- if (is_nan(a_cls)) {
313
- return 0;
314
- } else if (is_nan(b_cls)) {
315
- return 1;
316
- } else {
317
- return 2;
318
- }
319
+ rule = float_3nan_prop_abc;
320
#endif
124
+ }
321
+ }
125
+
322
+
126
aspeed_board_binfo.ram_size = ram_size;
323
+ assert(rule != float_3nan_prop_none);
127
aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM];
324
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
128
aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus;
325
+ /* We have at least one SNaN input and should prefer it */
326
+ do {
327
+ which = rule & R_3NAN_1ST_MASK;
328
+ rule >>= R_3NAN_1ST_LENGTH;
329
+ } while (!is_snan(cls[which]));
330
+ } else {
331
+ do {
332
+ which = rule & R_3NAN_1ST_MASK;
333
+ rule >>= R_3NAN_1ST_LENGTH;
334
+ } while (!is_nan(cls[which]));
335
+ }
336
+ return which;
337
}
338
339
/*----------------------------------------------------------------------------
129
--
340
--
130
2.20.1
341
2.34.1
131
132
diff view generated by jsdifflib
New patch
[PULL 21/72] tests/fp: Explicitly set 3-NaN propagation rule
1
Explicitly set a rule in the softfloat tests for propagating NaNs in
2
the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and
3
so we should select here the Arm rule of float_3nan_prop_s_cab.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-17-peter.maydell@linaro.org
8
---
9
tests/fp/fp-bench.c | 1 +
10
tests/fp/fp-test.c | 1 +
11
2 files changed, 2 insertions(+)
12
13
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/tests/fp/fp-bench.c
16
+++ b/tests/fp/fp-bench.c
17
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
18
* doesn't specify match those used by the Arm architecture.
19
*/
20
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
22
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
23
24
f = bench_funcs[operation][precision];
25
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/tests/fp/fp-test.c
28
+++ b/tests/fp/fp-test.c
29
@@ -XXX,XX +XXX,XX @@ void run_test(void)
30
* doesn't specify match those used by the Arm architecture.
31
*/
32
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
33
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
34
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
35
36
genCases_setLevel(test_level);
37
--
38
2.34.1
diff view generated by jsdifflib
[PULL 29/34] target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]
[PULL 22/72] target/arm: Set Float3NaNPropRule explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Use ARRAY_SIZE() to iterate over ARMCPUInfo[].
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
5
Since on the aarch64-linux-user build, arm_cpus[] is empty, add
6
the cpu_count variable and only iterate when it is non-zero.
7
8
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Message-id: 20241202131347.498124-18-peter.maydell@linaro.org
11
Message-id: 20200504172448.9402-4-philmd@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
7
---
14
target/arm/cpu.c | 16 +++++++++-------
8
target/arm/cpu.c | 5 +++++
15
target/arm/cpu64.c | 8 +++-----
9
fpu/softfloat-specialize.c.inc | 8 +-------
16
2 files changed, 12 insertions(+), 12 deletions(-)
10
2 files changed, 6 insertions(+), 7 deletions(-)
17
11
18
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
19
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.c
14
--- a/target/arm/cpu.c
21
+++ b/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
22
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
23
{ .name = "any", .initfn = arm_max_initfn },
17
* * tininess-before-rounding
24
#endif
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
25
#endif
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
26
- { .name = NULL }
20
+ * * 3-input NaN propagation prefers SNaN over QNaN, and then
27
};
21
+ * operand C over A over B (see FPProcessNaNs3() pseudocode,
28
22
+ * but note that for QEMU muladd is a * b + c, whereas for
29
static Property arm_cpu_properties[] = {
23
+ * the pseudocode function the arguments are in the order c, a, b.
30
@@ -XXX,XX +XXX,XX @@ static const TypeInfo idau_interface_type_info = {
24
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
31
25
* and the input NaN if it is signalling
32
static void arm_cpu_register_types(void)
26
*/
27
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
33
{
28
{
34
- const ARMCPUInfo *info = arm_cpus;
29
set_float_detect_tininess(float_tininess_before_rounding, s);
35
+ const size_t cpu_count = ARRAY_SIZE(arm_cpus);
30
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
36
31
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
37
type_register_static(&arm_cpu_type_info);
32
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
38
type_register_static(&idau_interface_type_info);
39
40
- while (info->name) {
41
- arm_cpu_register(info);
42
- info++;
43
- }
44
-
45
#ifdef CONFIG_KVM
46
type_register_static(&host_arm_cpu_type_info);
47
#endif
48
+
49
+ if (cpu_count) {
50
+ size_t i;
51
+
52
+ for (i = 0; i < cpu_count; ++i) {
53
+ arm_cpu_register(&arm_cpus[i]);
54
+ }
55
+ }
56
}
33
}
57
34
58
type_init(arm_cpu_register_types)
35
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
59
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
60
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
61
--- a/target/arm/cpu64.c
37
--- a/fpu/softfloat-specialize.c.inc
62
+++ b/target/arm/cpu64.c
38
+++ b/fpu/softfloat-specialize.c.inc
63
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
39
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
64
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
65
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
66
{ .name = "max", .initfn = aarch64_max_initfn },
67
- { .name = NULL }
68
};
69
70
static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
71
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aarch64_cpu_type_info = {
72
73
static void aarch64_cpu_register_types(void)
74
{
75
- const ARMCPUInfo *info = aarch64_cpus;
76
+ size_t i;
77
78
type_register_static(&aarch64_cpu_type_info);
79
80
- while (info->name) {
81
- aarch64_cpu_register(info);
82
- info++;
83
+ for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
84
+ aarch64_cpu_register(&aarch64_cpus[i]);
85
}
40
}
86
}
41
87
42
if (rule == float_3nan_prop_none) {
43
-#if defined(TARGET_ARM)
44
- /*
45
- * This looks different from the ARM ARM pseudocode, because the ARM ARM
46
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
47
- */
48
- rule = float_3nan_prop_s_cab;
49
-#elif defined(TARGET_MIPS)
50
+#if defined(TARGET_MIPS)
51
if (snan_bit_is_one(status)) {
52
rule = float_3nan_prop_s_abc;
53
} else {
88
--
54
--
89
2.20.1
55
2.34.1
90
91
diff view generated by jsdifflib
New patch
[PULL 23/72] target/loongarch: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for loongarch, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-19-peter.maydell@linaro.org
7
---
8
target/loongarch/tcg/fpu_helper.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/loongarch/tcg/fpu_helper.c
15
+++ b/target/loongarch/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
17
* case sets InvalidOp and returns the input value 'c'
18
*/
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
21
}
22
23
int ieee_ex_to_loongarch(int xcpt)
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_LOONGARCH64)
33
- rule = float_3nan_prop_s_cab;
34
#elif defined(TARGET_PPC)
35
/*
36
* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 24/72] target/ppc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for PPC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-20-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 8 ++++++++
9
fpu/softfloat-specialize.c.inc | 6 ------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * NaN propagation for fused multiply-add:
22
+ * if fRA is a NaN return it; otherwise if fRB is a NaN return it;
23
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
24
+ * whereas QEMU labels the operands as (a * b) + c.
25
+ */
26
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status);
27
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status);
28
/*
29
* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
30
* to return an input NaN if we have one (ie c) rather than generating
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
32
index XXXXXXX..XXXXXXX 100644
33
--- a/fpu/softfloat-specialize.c.inc
34
+++ b/fpu/softfloat-specialize.c.inc
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
36
} else {
37
rule = float_3nan_prop_s_cab;
38
}
39
-#elif defined(TARGET_PPC)
40
- /*
41
- * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
42
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
43
- */
44
- rule = float_3nan_prop_acb;
45
#elif defined(TARGET_S390X)
46
rule = float_3nan_prop_s_abc;
47
#elif defined(TARGET_SPARC)
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 25/72] target/s390x: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for s390x, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-21-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
21
set_float_infzeronan_rule(float_infzeronan_dnan_always,
22
&env->fpu_status);
23
/* fall through */
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_S390X)
33
- rule = float_3nan_prop_s_abc;
34
#elif defined(TARGET_SPARC)
35
rule = float_3nan_prop_s_cba;
36
#elif defined(TARGET_XTENSA)
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 26/72] target/sparc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for SPARC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-22-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
22
/* For inf * 0 + NaN, return the input NaN */
23
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
} else {
31
rule = float_3nan_prop_s_cab;
32
}
33
-#elif defined(TARGET_SPARC)
34
- rule = float_3nan_prop_s_cba;
35
#elif defined(TARGET_XTENSA)
36
if (status->use_first_nan) {
37
rule = float_3nan_prop_abc;
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 27/72] target/mips: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-23-peter.maydell@linaro.org
7
---
8
target/mips/fpu_helper.h | 4 ++++
9
target/mips/msa.c | 3 +++
10
fpu/softfloat-specialize.c.inc | 8 +-------
11
3 files changed, 8 insertions(+), 7 deletions(-)
12
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/mips/fpu_helper.h
16
+++ b/target/mips/fpu_helper.h
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
18
{
19
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
20
FloatInfZeroNaNRule izn_rule;
21
+ Float3NaNPropRule nan3_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
28
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
29
+ nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
30
+ set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
31
+
32
}
33
34
static inline void restore_fp_status(CPUMIPSState *env)
35
diff --git a/target/mips/msa.c b/target/mips/msa.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/mips/msa.c
38
+++ b/target/mips/msa.c
39
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
40
set_float_2nan_prop_rule(float_2nan_prop_s_ab,
41
&env->active_tc.msa_fp_status);
42
43
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab,
44
+ &env->active_tc.msa_fp_status);
45
+
46
/* clear float_status exception flags */
47
set_float_exception_flags(0, &env->active_tc.msa_fp_status);
48
49
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
50
index XXXXXXX..XXXXXXX 100644
51
--- a/fpu/softfloat-specialize.c.inc
52
+++ b/fpu/softfloat-specialize.c.inc
53
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
54
}
55
56
if (rule == float_3nan_prop_none) {
57
-#if defined(TARGET_MIPS)
58
- if (snan_bit_is_one(status)) {
59
- rule = float_3nan_prop_s_abc;
60
- } else {
61
- rule = float_3nan_prop_s_cab;
62
- }
63
-#elif defined(TARGET_XTENSA)
64
+#if defined(TARGET_XTENSA)
65
if (status->use_first_nan) {
66
rule = float_3nan_prop_abc;
67
} else {
68
--
69
2.34.1
diff view generated by jsdifflib
New patch
[PULL 28/72] target/xtensa: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for xtensa, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-24-peter.maydell@linaro.org
7
---
8
target/xtensa/fpu_helper.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 8 --------
10
2 files changed, 2 insertions(+), 8 deletions(-)
11
12
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/xtensa/fpu_helper.c
15
+++ b/target/xtensa/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
17
set_use_first_nan(use_first, &env->fp_status);
18
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
19
&env->fp_status);
20
+ set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
21
+ &env->fp_status);
22
}
23
24
void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v)
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
}
31
32
if (rule == float_3nan_prop_none) {
33
-#if defined(TARGET_XTENSA)
34
- if (status->use_first_nan) {
35
- rule = float_3nan_prop_abc;
36
- } else {
37
- rule = float_3nan_prop_cba;
38
- }
39
-#else
40
rule = float_3nan_prop_abc;
41
-#endif
42
}
43
44
assert(rule != float_3nan_prop_none);
45
--
46
2.34.1
diff view generated by jsdifflib
New patch
[PULL 29/72] target/i386: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for i386. We had no
2
i386-specific behaviour in the old ifdef ladder, so we were using the
3
default "prefer a then b then c" fallback; this is actually the
4
correct per-the-spec handling for i386.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-25-peter.maydell@linaro.org
9
---
10
target/i386/tcg/fpu_helper.c | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/i386/tcg/fpu_helper.c
16
+++ b/target/i386/tcg/fpu_helper.c
17
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
18
* there are multiple input NaNs they are selected in the order a, b, c.
19
*/
20
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
22
}
23
24
static inline uint8_t save_exception_flags(CPUX86State *env)
25
--
26
2.34.1
diff view generated by jsdifflib
New patch
[PULL 30/72] target/hppa: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for HPPA, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
HPPA is the only target that was using the default branch of the
5
ifdef ladder (other targets either do not use muladd or set
6
default_nan_mode), so we can remove the ifdef fallback entirely now
7
(allowing the "rule not set" case to fall into the default of the
8
switch statement and assert).
9
10
We add a TODO note that the HPPA rule is probably wrong; this is
11
not a behavioural change for this refactoring.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-26-peter.maydell@linaro.org
16
---
17
target/hppa/fpu_helper.c | 8 ++++++++
18
fpu/softfloat-specialize.c.inc | 4 ----
19
2 files changed, 8 insertions(+), 4 deletions(-)
20
21
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/hppa/fpu_helper.c
24
+++ b/target/hppa/fpu_helper.c
25
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
26
* HPPA does note implement a CPU reset method at all...
27
*/
28
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
29
+ /*
30
+ * TODO: The HPPA architecture reference only documents its NaN
31
+ * propagation rule for 2-operand operations. Testing on real hardware
32
+ * might be necessary to confirm whether this order for muladd is correct.
33
+ * Not preferring the SNaN is almost certainly incorrect as it diverges
34
+ * from the documented rules for 2-operand operations.
35
+ */
36
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
37
/* For inf * 0 + NaN, return the input NaN */
38
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
39
}
40
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
41
index XXXXXXX..XXXXXXX 100644
42
--- a/fpu/softfloat-specialize.c.inc
43
+++ b/fpu/softfloat-specialize.c.inc
44
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
45
}
46
}
47
48
- if (rule == float_3nan_prop_none) {
49
- rule = float_3nan_prop_abc;
50
- }
51
-
52
assert(rule != float_3nan_prop_none);
53
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
54
/* We have at least one SNaN input and should prefer it */
55
--
56
2.34.1
diff view generated by jsdifflib
[PULL 13/34] accel/tcg: Add endian-specific cpu_{ld, st}* operations
[PULL 31/72] fpu: Remove use_first_nan field from float_status
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The use_first_nan field in float_status was an xtensa-specific way to
2
select at runtime from two different NaN propagation rules. Now that
3
xtensa is using the target-agnostic NaN propagation rule selection
4
that we've just added, we can remove use_first_nan, because there is
5
no longer any code that reads it.
2
6
3
We currently have target-endian versions of these operations,
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
but no easy way to force a specific endianness. This can be
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
helpful if the target has endian-specific operations, or a mode
9
Message-id: 20241202131347.498124-27-peter.maydell@linaro.org
6
that swaps endianness.
10
---
11
include/fpu/softfloat-helpers.h | 5 -----
12
include/fpu/softfloat-types.h | 1 -
13
target/xtensa/fpu_helper.c | 1 -
14
3 files changed, 7 deletions(-)
7
15
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-7-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
docs/devel/loads-stores.rst | 39 +++--
14
include/exec/cpu_ldst.h | 283 +++++++++++++++++++++++++++---------
15
accel/tcg/cputlb.c | 236 ++++++++++++++++++++++--------
16
accel/tcg/user-exec.c | 211 ++++++++++++++++++++++-----
17
4 files changed, 587 insertions(+), 182 deletions(-)
18
19
diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst
20
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
21
--- a/docs/devel/loads-stores.rst
18
--- a/include/fpu/softfloat-helpers.h
22
+++ b/docs/devel/loads-stores.rst
19
+++ b/include/fpu/softfloat-helpers.h
23
@@ -XXX,XX +XXX,XX @@ function, which is a return address into the generated code.
20
@@ -XXX,XX +XXX,XX @@ static inline void set_snan_bit_is_one(bool val, float_status *status)
24
21
status->snan_bit_is_one = val;
25
Function names follow the pattern:
26
27
-load: ``cpu_ld{sign}{size}_mmuidx_ra(env, ptr, mmuidx, retaddr)``
28
+load: ``cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmuidx, retaddr)``
29
30
-store: ``cpu_st{size}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
31
+store: ``cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
32
33
``sign``
34
- (empty) : for 32 or 64 bit sizes
35
@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
36
- ``l`` : 32 bits
37
- ``q`` : 64 bits
38
39
+``end``
40
+ - (empty) : for target endian, or 8 bit sizes
41
+ - ``_be`` : big endian
42
+ - ``_le`` : little endian
43
+
44
Regexes for git grep:
45
- - ``\<cpu_ld[us]\?[bwlq]_mmuidx_ra\>``
46
- - ``\<cpu_st[bwlq]_mmuidx_ra\>``
47
+ - ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_mmuidx_ra\>``
48
+ - ``\<cpu_st[bwlq](_[bl]e)\?_mmuidx_ra\>``
49
50
``cpu_{ld,st}*_data_ra``
51
~~~~~~~~~~~~~~~~~~~~~~~~
52
@@ -XXX,XX +XXX,XX @@ be performed with a context other than the default.
53
54
Function names follow the pattern:
55
56
-load: ``cpu_ld{sign}{size}_data_ra(env, ptr, ra)``
57
+load: ``cpu_ld{sign}{size}{end}_data_ra(env, ptr, ra)``
58
59
-store: ``cpu_st{size}_data_ra(env, ptr, val, ra)``
60
+store: ``cpu_st{size}{end}_data_ra(env, ptr, val, ra)``
61
62
``sign``
63
- (empty) : for 32 or 64 bit sizes
64
@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}_data_ra(env, ptr, val, ra)``
65
- ``l`` : 32 bits
66
- ``q`` : 64 bits
67
68
+``end``
69
+ - (empty) : for target endian, or 8 bit sizes
70
+ - ``_be`` : big endian
71
+ - ``_le`` : little endian
72
+
73
Regexes for git grep:
74
- - ``\<cpu_ld[us]\?[bwlq]_data_ra\>``
75
- - ``\<cpu_st[bwlq]_data_ra\>``
76
+ - ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_data_ra\>``
77
+ - ``\<cpu_st[bwlq](_[bl]e)\?_data_ra\>``
78
79
``cpu_{ld,st}*_data``
80
~~~~~~~~~~~~~~~~~~~~~
81
@@ -XXX,XX +XXX,XX @@ the CPU state anyway.
82
83
Function names follow the pattern:
84
85
-load: ``cpu_ld{sign}{size}_data(env, ptr)``
86
+load: ``cpu_ld{sign}{size}{end}_data(env, ptr)``
87
88
-store: ``cpu_st{size}_data(env, ptr, val)``
89
+store: ``cpu_st{size}{end}_data(env, ptr, val)``
90
91
``sign``
92
- (empty) : for 32 or 64 bit sizes
93
@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}_data(env, ptr, val)``
94
- ``l`` : 32 bits
95
- ``q`` : 64 bits
96
97
+``end``
98
+ - (empty) : for target endian, or 8 bit sizes
99
+ - ``_be`` : big endian
100
+ - ``_le`` : little endian
101
+
102
Regexes for git grep
103
- - ``\<cpu_ld[us]\?[bwlq]_data\>``
104
- - ``\<cpu_st[bwlq]_data\+\>``
105
+ - ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_data\>``
106
+ - ``\<cpu_st[bwlq](_[bl]e)\?_data\+\>``
107
108
``cpu_ld*_code``
109
~~~~~~~~~~~~~~~~
110
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
111
index XXXXXXX..XXXXXXX 100644
112
--- a/include/exec/cpu_ldst.h
113
+++ b/include/exec/cpu_ldst.h
114
@@ -XXX,XX +XXX,XX @@
115
*
116
* The syntax for the accessors is:
117
*
118
- * load: cpu_ld{sign}{size}_{mmusuffix}(env, ptr)
119
- * cpu_ld{sign}{size}_{mmusuffix}_ra(env, ptr, retaddr)
120
- * cpu_ld{sign}{size}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
121
+ * load: cpu_ld{sign}{size}{end}_{mmusuffix}(env, ptr)
122
+ * cpu_ld{sign}{size}{end}_{mmusuffix}_ra(env, ptr, retaddr)
123
+ * cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
124
*
125
- * store: cpu_st{size}_{mmusuffix}(env, ptr, val)
126
- * cpu_st{size}_{mmusuffix}_ra(env, ptr, val, retaddr)
127
- * cpu_st{size}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
128
+ * store: cpu_st{size}{end}_{mmusuffix}(env, ptr, val)
129
+ * cpu_st{size}{end}_{mmusuffix}_ra(env, ptr, val, retaddr)
130
+ * cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
131
*
132
* sign is:
133
* (empty): for 32 and 64 bit sizes
134
@@ -XXX,XX +XXX,XX @@
135
* l: 32 bits
136
* q: 64 bits
137
*
138
+ * end is:
139
+ * (empty): for target native endian, or for 8 bit access
140
+ * _be: for forced big endian
141
+ * _le: for forced little endian
142
+ *
143
* mmusuffix is one of the generic suffixes "data" or "code", or "mmuidx".
144
* The "mmuidx" suffix carries an extra mmu_idx argument that specifies
145
* the index to use; the "data" and "code" suffixes take the index from
146
@@ -XXX,XX +XXX,XX @@ typedef target_ulong abi_ptr;
147
#endif
148
149
uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
150
-uint32_t cpu_lduw_data(CPUArchState *env, abi_ptr ptr);
151
-uint32_t cpu_ldl_data(CPUArchState *env, abi_ptr ptr);
152
-uint64_t cpu_ldq_data(CPUArchState *env, abi_ptr ptr);
153
int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr);
154
-int cpu_ldsw_data(CPUArchState *env, abi_ptr ptr);
155
156
-uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
157
-uint32_t cpu_lduw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
158
-uint32_t cpu_ldl_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
159
-uint64_t cpu_ldq_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
160
-int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
161
-int cpu_ldsw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
162
+uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr);
163
+int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr);
164
+uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr);
165
+uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr);
166
+
167
+uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr);
168
+int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr);
169
+uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr);
170
+uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr);
171
+
172
+uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
173
+int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
174
+
175
+uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
176
+int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
177
+uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
178
+uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
179
+
180
+uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
181
+int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
182
+uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
183
+uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
184
185
void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
186
-void cpu_stw_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
187
-void cpu_stl_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
188
-void cpu_stq_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
189
+
190
+void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
191
+void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
192
+void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
193
+
194
+void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
195
+void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
196
+void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
197
198
void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
199
- uint32_t val, uintptr_t retaddr);
200
-void cpu_stw_data_ra(CPUArchState *env, abi_ptr ptr,
201
- uint32_t val, uintptr_t retaddr);
202
-void cpu_stl_data_ra(CPUArchState *env, abi_ptr ptr,
203
- uint32_t val, uintptr_t retaddr);
204
-void cpu_stq_data_ra(CPUArchState *env, abi_ptr ptr,
205
- uint64_t val, uintptr_t retaddr);
206
+ uint32_t val, uintptr_t ra);
207
+
208
+void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
209
+ uint32_t val, uintptr_t ra);
210
+void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
211
+ uint32_t val, uintptr_t ra);
212
+void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
213
+ uint64_t val, uintptr_t ra);
214
+
215
+void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
216
+ uint32_t val, uintptr_t ra);
217
+void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
218
+ uint32_t val, uintptr_t ra);
219
+void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
220
+ uint64_t val, uintptr_t ra);
221
222
#if defined(CONFIG_USER_ONLY)
223
224
@@ -XXX,XX +XXX,XX @@ static inline uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
225
return cpu_ldub_data_ra(env, addr, ra);
226
}
22
}
227
23
228
-static inline uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
24
-static inline void set_use_first_nan(bool val, float_status *status)
229
- int mmu_idx, uintptr_t ra)
230
-{
25
-{
231
- return cpu_lduw_data_ra(env, addr, ra);
26
- status->use_first_nan = val;
232
-}
27
-}
233
-
28
-
234
-static inline uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
29
static inline void set_no_signaling_nans(bool val, float_status *status)
235
- int mmu_idx, uintptr_t ra)
236
-{
237
- return cpu_ldl_data_ra(env, addr, ra);
238
-}
239
-
240
-static inline uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
241
- int mmu_idx, uintptr_t ra)
242
-{
243
- return cpu_ldq_data_ra(env, addr, ra);
244
-}
245
-
246
static inline int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
247
int mmu_idx, uintptr_t ra)
248
{
30
{
249
return cpu_ldsb_data_ra(env, addr, ra);
31
status->no_signaling_nans = val;
250
}
32
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
251
33
index XXXXXXX..XXXXXXX 100644
252
-static inline int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
34
--- a/include/fpu/softfloat-types.h
253
- int mmu_idx, uintptr_t ra)
35
+++ b/include/fpu/softfloat-types.h
254
+static inline uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
36
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
255
+ int mmu_idx, uintptr_t ra)
37
* softfloat-specialize.inc.c)
38
*/
39
bool snan_bit_is_one;
40
- bool use_first_nan;
41
bool no_signaling_nans;
42
/* should overflowed results subtract re_bias to its exponent? */
43
bool rebias_overflow;
44
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/xtensa/fpu_helper.c
47
+++ b/target/xtensa/fpu_helper.c
48
@@ -XXX,XX +XXX,XX @@ static const struct {
49
50
void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
256
{
51
{
257
- return cpu_ldsw_data_ra(env, addr, ra);
52
- set_use_first_nan(use_first, &env->fp_status);
258
+ return cpu_lduw_be_data_ra(env, addr, ra);
53
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
259
+}
54
&env->fp_status);
260
+
55
set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
261
+static inline int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
262
+ int mmu_idx, uintptr_t ra)
263
+{
264
+ return cpu_ldsw_be_data_ra(env, addr, ra);
265
+}
266
+
267
+static inline uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
268
+ int mmu_idx, uintptr_t ra)
269
+{
270
+ return cpu_ldl_be_data_ra(env, addr, ra);
271
+}
272
+
273
+static inline uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
274
+ int mmu_idx, uintptr_t ra)
275
+{
276
+ return cpu_ldq_be_data_ra(env, addr, ra);
277
+}
278
+
279
+static inline uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
280
+ int mmu_idx, uintptr_t ra)
281
+{
282
+ return cpu_lduw_le_data_ra(env, addr, ra);
283
+}
284
+
285
+static inline int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
286
+ int mmu_idx, uintptr_t ra)
287
+{
288
+ return cpu_ldsw_le_data_ra(env, addr, ra);
289
+}
290
+
291
+static inline uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
292
+ int mmu_idx, uintptr_t ra)
293
+{
294
+ return cpu_ldl_le_data_ra(env, addr, ra);
295
+}
296
+
297
+static inline uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
298
+ int mmu_idx, uintptr_t ra)
299
+{
300
+ return cpu_ldq_le_data_ra(env, addr, ra);
301
}
302
303
static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
304
@@ -XXX,XX +XXX,XX @@ static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
305
cpu_stb_data_ra(env, addr, val, ra);
306
}
307
308
-static inline void cpu_stw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
309
- uint32_t val, int mmu_idx, uintptr_t ra)
310
+static inline void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
311
+ uint32_t val, int mmu_idx,
312
+ uintptr_t ra)
313
{
314
- cpu_stw_data_ra(env, addr, val, ra);
315
+ cpu_stw_be_data_ra(env, addr, val, ra);
316
}
317
318
-static inline void cpu_stl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
319
- uint32_t val, int mmu_idx, uintptr_t ra)
320
+static inline void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
321
+ uint32_t val, int mmu_idx,
322
+ uintptr_t ra)
323
{
324
- cpu_stl_data_ra(env, addr, val, ra);
325
+ cpu_stl_be_data_ra(env, addr, val, ra);
326
}
327
328
-static inline void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
329
- uint64_t val, int mmu_idx, uintptr_t ra)
330
+static inline void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
331
+ uint64_t val, int mmu_idx,
332
+ uintptr_t ra)
333
{
334
- cpu_stq_data_ra(env, addr, val, ra);
335
+ cpu_stq_be_data_ra(env, addr, val, ra);
336
+}
337
+
338
+static inline void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
339
+ uint32_t val, int mmu_idx,
340
+ uintptr_t ra)
341
+{
342
+ cpu_stw_le_data_ra(env, addr, val, ra);
343
+}
344
+
345
+static inline void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
346
+ uint32_t val, int mmu_idx,
347
+ uintptr_t ra)
348
+{
349
+ cpu_stl_le_data_ra(env, addr, val, ra);
350
+}
351
+
352
+static inline void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
353
+ uint64_t val, int mmu_idx,
354
+ uintptr_t ra)
355
+{
356
+ cpu_stq_le_data_ra(env, addr, val, ra);
357
}
358
359
#else
360
@@ -XXX,XX +XXX,XX @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
361
362
uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
363
int mmu_idx, uintptr_t ra);
364
-uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
365
- int mmu_idx, uintptr_t ra);
366
-uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
367
- int mmu_idx, uintptr_t ra);
368
-uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
369
- int mmu_idx, uintptr_t ra);
370
-
371
int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
372
int mmu_idx, uintptr_t ra);
373
-int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
374
- int mmu_idx, uintptr_t ra);
375
+
376
+uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
377
+ int mmu_idx, uintptr_t ra);
378
+int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
379
+ int mmu_idx, uintptr_t ra);
380
+uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
381
+ int mmu_idx, uintptr_t ra);
382
+uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
383
+ int mmu_idx, uintptr_t ra);
384
+
385
+uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
386
+ int mmu_idx, uintptr_t ra);
387
+int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
388
+ int mmu_idx, uintptr_t ra);
389
+uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
390
+ int mmu_idx, uintptr_t ra);
391
+uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
392
+ int mmu_idx, uintptr_t ra);
393
394
void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
395
int mmu_idx, uintptr_t retaddr);
396
-void cpu_stw_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
397
- int mmu_idx, uintptr_t retaddr);
398
-void cpu_stl_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
399
- int mmu_idx, uintptr_t retaddr);
400
-void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
401
- int mmu_idx, uintptr_t retaddr);
402
+
403
+void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
404
+ int mmu_idx, uintptr_t retaddr);
405
+void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
406
+ int mmu_idx, uintptr_t retaddr);
407
+void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
408
+ int mmu_idx, uintptr_t retaddr);
409
+
410
+void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
411
+ int mmu_idx, uintptr_t retaddr);
412
+void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
413
+ int mmu_idx, uintptr_t retaddr);
414
+void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
415
+ int mmu_idx, uintptr_t retaddr);
416
417
#endif /* defined(CONFIG_USER_ONLY) */
418
419
+#ifdef TARGET_WORDS_BIGENDIAN
420
+# define cpu_lduw_data cpu_lduw_be_data
421
+# define cpu_ldsw_data cpu_ldsw_be_data
422
+# define cpu_ldl_data cpu_ldl_be_data
423
+# define cpu_ldq_data cpu_ldq_be_data
424
+# define cpu_lduw_data_ra cpu_lduw_be_data_ra
425
+# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra
426
+# define cpu_ldl_data_ra cpu_ldl_be_data_ra
427
+# define cpu_ldq_data_ra cpu_ldq_be_data_ra
428
+# define cpu_lduw_mmuidx_ra cpu_lduw_be_mmuidx_ra
429
+# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra
430
+# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra
431
+# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra
432
+# define cpu_stw_data cpu_stw_be_data
433
+# define cpu_stl_data cpu_stl_be_data
434
+# define cpu_stq_data cpu_stq_be_data
435
+# define cpu_stw_data_ra cpu_stw_be_data_ra
436
+# define cpu_stl_data_ra cpu_stl_be_data_ra
437
+# define cpu_stq_data_ra cpu_stq_be_data_ra
438
+# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra
439
+# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra
440
+# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra
441
+#else
442
+# define cpu_lduw_data cpu_lduw_le_data
443
+# define cpu_ldsw_data cpu_ldsw_le_data
444
+# define cpu_ldl_data cpu_ldl_le_data
445
+# define cpu_ldq_data cpu_ldq_le_data
446
+# define cpu_lduw_data_ra cpu_lduw_le_data_ra
447
+# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra
448
+# define cpu_ldl_data_ra cpu_ldl_le_data_ra
449
+# define cpu_ldq_data_ra cpu_ldq_le_data_ra
450
+# define cpu_lduw_mmuidx_ra cpu_lduw_le_mmuidx_ra
451
+# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra
452
+# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra
453
+# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra
454
+# define cpu_stw_data cpu_stw_le_data
455
+# define cpu_stl_data cpu_stl_le_data
456
+# define cpu_stq_data cpu_stq_le_data
457
+# define cpu_stw_data_ra cpu_stw_le_data_ra
458
+# define cpu_stl_data_ra cpu_stl_le_data_ra
459
+# define cpu_stq_data_ra cpu_stq_le_data_ra
460
+# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra
461
+# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra
462
+# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra
463
+#endif
464
+
465
uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
466
uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr);
467
uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr);
468
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
469
index XXXXXXX..XXXXXXX 100644
470
--- a/accel/tcg/cputlb.c
471
+++ b/accel/tcg/cputlb.c
472
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
473
full_ldub_mmu);
474
}
475
476
-uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
477
- int mmu_idx, uintptr_t ra)
478
+uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
479
+ int mmu_idx, uintptr_t ra)
480
{
481
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_TEUW,
482
- MO_TE == MO_LE
483
- ? full_le_lduw_mmu : full_be_lduw_mmu);
484
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUW, full_be_lduw_mmu);
485
}
486
487
-int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
488
- int mmu_idx, uintptr_t ra)
489
+int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
490
+ int mmu_idx, uintptr_t ra)
491
{
492
- return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_TESW,
493
- MO_TE == MO_LE
494
- ? full_le_lduw_mmu : full_be_lduw_mmu);
495
+ return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_BESW,
496
+ full_be_lduw_mmu);
497
}
498
499
-uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
500
- int mmu_idx, uintptr_t ra)
501
+uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
502
+ int mmu_idx, uintptr_t ra)
503
{
504
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_TEUL,
505
- MO_TE == MO_LE
506
- ? full_le_ldul_mmu : full_be_ldul_mmu);
507
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUL, full_be_ldul_mmu);
508
}
509
510
-uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
511
- int mmu_idx, uintptr_t ra)
512
+uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
513
+ int mmu_idx, uintptr_t ra)
514
{
515
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_TEQ,
516
- MO_TE == MO_LE
517
- ? helper_le_ldq_mmu : helper_be_ldq_mmu);
518
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEQ, helper_be_ldq_mmu);
519
+}
520
+
521
+uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
522
+ int mmu_idx, uintptr_t ra)
523
+{
524
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUW, full_le_lduw_mmu);
525
+}
526
+
527
+int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
528
+ int mmu_idx, uintptr_t ra)
529
+{
530
+ return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_LESW,
531
+ full_le_lduw_mmu);
532
+}
533
+
534
+uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
535
+ int mmu_idx, uintptr_t ra)
536
+{
537
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUL, full_le_ldul_mmu);
538
+}
539
+
540
+uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
541
+ int mmu_idx, uintptr_t ra)
542
+{
543
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEQ, helper_le_ldq_mmu);
544
}
545
546
uint32_t cpu_ldub_data_ra(CPUArchState *env, target_ulong ptr,
547
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
548
return cpu_ldsb_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
549
}
550
551
-uint32_t cpu_lduw_data_ra(CPUArchState *env, target_ulong ptr,
552
- uintptr_t retaddr)
553
+uint32_t cpu_lduw_be_data_ra(CPUArchState *env, target_ulong ptr,
554
+ uintptr_t retaddr)
555
{
556
- return cpu_lduw_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
557
+ return cpu_lduw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
558
}
559
560
-int cpu_ldsw_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
561
+int cpu_ldsw_be_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
562
{
563
- return cpu_ldsw_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
564
+ return cpu_ldsw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
565
}
566
567
-uint32_t cpu_ldl_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
568
+uint32_t cpu_ldl_be_data_ra(CPUArchState *env, target_ulong ptr,
569
+ uintptr_t retaddr)
570
{
571
- return cpu_ldl_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
572
+ return cpu_ldl_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
573
}
574
575
-uint64_t cpu_ldq_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
576
+uint64_t cpu_ldq_be_data_ra(CPUArchState *env, target_ulong ptr,
577
+ uintptr_t retaddr)
578
{
579
- return cpu_ldq_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
580
+ return cpu_ldq_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
581
+}
582
+
583
+uint32_t cpu_lduw_le_data_ra(CPUArchState *env, target_ulong ptr,
584
+ uintptr_t retaddr)
585
+{
586
+ return cpu_lduw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
587
+}
588
+
589
+int cpu_ldsw_le_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
590
+{
591
+ return cpu_ldsw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
592
+}
593
+
594
+uint32_t cpu_ldl_le_data_ra(CPUArchState *env, target_ulong ptr,
595
+ uintptr_t retaddr)
596
+{
597
+ return cpu_ldl_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
598
+}
599
+
600
+uint64_t cpu_ldq_le_data_ra(CPUArchState *env, target_ulong ptr,
601
+ uintptr_t retaddr)
602
+{
603
+ return cpu_ldq_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
604
}
605
606
uint32_t cpu_ldub_data(CPUArchState *env, target_ulong ptr)
607
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data(CPUArchState *env, target_ulong ptr)
608
return cpu_ldsb_data_ra(env, ptr, 0);
609
}
610
611
-uint32_t cpu_lduw_data(CPUArchState *env, target_ulong ptr)
612
+uint32_t cpu_lduw_be_data(CPUArchState *env, target_ulong ptr)
613
{
614
- return cpu_lduw_data_ra(env, ptr, 0);
615
+ return cpu_lduw_be_data_ra(env, ptr, 0);
616
}
617
618
-int cpu_ldsw_data(CPUArchState *env, target_ulong ptr)
619
+int cpu_ldsw_be_data(CPUArchState *env, target_ulong ptr)
620
{
621
- return cpu_ldsw_data_ra(env, ptr, 0);
622
+ return cpu_ldsw_be_data_ra(env, ptr, 0);
623
}
624
625
-uint32_t cpu_ldl_data(CPUArchState *env, target_ulong ptr)
626
+uint32_t cpu_ldl_be_data(CPUArchState *env, target_ulong ptr)
627
{
628
- return cpu_ldl_data_ra(env, ptr, 0);
629
+ return cpu_ldl_be_data_ra(env, ptr, 0);
630
}
631
632
-uint64_t cpu_ldq_data(CPUArchState *env, target_ulong ptr)
633
+uint64_t cpu_ldq_be_data(CPUArchState *env, target_ulong ptr)
634
{
635
- return cpu_ldq_data_ra(env, ptr, 0);
636
+ return cpu_ldq_be_data_ra(env, ptr, 0);
637
+}
638
+
639
+uint32_t cpu_lduw_le_data(CPUArchState *env, target_ulong ptr)
640
+{
641
+ return cpu_lduw_le_data_ra(env, ptr, 0);
642
+}
643
+
644
+int cpu_ldsw_le_data(CPUArchState *env, target_ulong ptr)
645
+{
646
+ return cpu_ldsw_le_data_ra(env, ptr, 0);
647
+}
648
+
649
+uint32_t cpu_ldl_le_data(CPUArchState *env, target_ulong ptr)
650
+{
651
+ return cpu_ldl_le_data_ra(env, ptr, 0);
652
+}
653
+
654
+uint64_t cpu_ldq_le_data(CPUArchState *env, target_ulong ptr)
655
+{
656
+ return cpu_ldq_le_data_ra(env, ptr, 0);
657
}
658
659
/*
660
@@ -XXX,XX +XXX,XX @@ void cpu_stb_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
661
cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_UB);
662
}
663
664
-void cpu_stw_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
665
- int mmu_idx, uintptr_t retaddr)
666
+void cpu_stw_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
667
+ int mmu_idx, uintptr_t retaddr)
668
{
669
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEUW);
670
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUW);
671
}
672
673
-void cpu_stl_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
674
- int mmu_idx, uintptr_t retaddr)
675
+void cpu_stl_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
676
+ int mmu_idx, uintptr_t retaddr)
677
{
678
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEUL);
679
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUL);
680
}
681
682
-void cpu_stq_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
683
- int mmu_idx, uintptr_t retaddr)
684
+void cpu_stq_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
685
+ int mmu_idx, uintptr_t retaddr)
686
{
687
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEQ);
688
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEQ);
689
+}
690
+
691
+void cpu_stw_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
692
+ int mmu_idx, uintptr_t retaddr)
693
+{
694
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUW);
695
+}
696
+
697
+void cpu_stl_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
698
+ int mmu_idx, uintptr_t retaddr)
699
+{
700
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUL);
701
+}
702
+
703
+void cpu_stq_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
704
+ int mmu_idx, uintptr_t retaddr)
705
+{
706
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEQ);
707
}
708
709
void cpu_stb_data_ra(CPUArchState *env, target_ulong ptr,
710
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data_ra(CPUArchState *env, target_ulong ptr,
711
cpu_stb_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
712
}
713
714
-void cpu_stw_data_ra(CPUArchState *env, target_ulong ptr,
715
- uint32_t val, uintptr_t retaddr)
716
+void cpu_stw_be_data_ra(CPUArchState *env, target_ulong ptr,
717
+ uint32_t val, uintptr_t retaddr)
718
{
719
- cpu_stw_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
720
+ cpu_stw_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
721
}
722
723
-void cpu_stl_data_ra(CPUArchState *env, target_ulong ptr,
724
- uint32_t val, uintptr_t retaddr)
725
+void cpu_stl_be_data_ra(CPUArchState *env, target_ulong ptr,
726
+ uint32_t val, uintptr_t retaddr)
727
{
728
- cpu_stl_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
729
+ cpu_stl_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
730
}
731
732
-void cpu_stq_data_ra(CPUArchState *env, target_ulong ptr,
733
- uint64_t val, uintptr_t retaddr)
734
+void cpu_stq_be_data_ra(CPUArchState *env, target_ulong ptr,
735
+ uint64_t val, uintptr_t retaddr)
736
{
737
- cpu_stq_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
738
+ cpu_stq_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
739
+}
740
+
741
+void cpu_stw_le_data_ra(CPUArchState *env, target_ulong ptr,
742
+ uint32_t val, uintptr_t retaddr)
743
+{
744
+ cpu_stw_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
745
+}
746
+
747
+void cpu_stl_le_data_ra(CPUArchState *env, target_ulong ptr,
748
+ uint32_t val, uintptr_t retaddr)
749
+{
750
+ cpu_stl_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
751
+}
752
+
753
+void cpu_stq_le_data_ra(CPUArchState *env, target_ulong ptr,
754
+ uint64_t val, uintptr_t retaddr)
755
+{
756
+ cpu_stq_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
757
}
758
759
void cpu_stb_data(CPUArchState *env, target_ulong ptr, uint32_t val)
760
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data(CPUArchState *env, target_ulong ptr, uint32_t val)
761
cpu_stb_data_ra(env, ptr, val, 0);
762
}
763
764
-void cpu_stw_data(CPUArchState *env, target_ulong ptr, uint32_t val)
765
+void cpu_stw_be_data(CPUArchState *env, target_ulong ptr, uint32_t val)
766
{
767
- cpu_stw_data_ra(env, ptr, val, 0);
768
+ cpu_stw_be_data_ra(env, ptr, val, 0);
769
}
770
771
-void cpu_stl_data(CPUArchState *env, target_ulong ptr, uint32_t val)
772
+void cpu_stl_be_data(CPUArchState *env, target_ulong ptr, uint32_t val)
773
{
774
- cpu_stl_data_ra(env, ptr, val, 0);
775
+ cpu_stl_be_data_ra(env, ptr, val, 0);
776
}
777
778
-void cpu_stq_data(CPUArchState *env, target_ulong ptr, uint64_t val)
779
+void cpu_stq_be_data(CPUArchState *env, target_ulong ptr, uint64_t val)
780
{
781
- cpu_stq_data_ra(env, ptr, val, 0);
782
+ cpu_stq_be_data_ra(env, ptr, val, 0);
783
+}
784
+
785
+void cpu_stw_le_data(CPUArchState *env, target_ulong ptr, uint32_t val)
786
+{
787
+ cpu_stw_le_data_ra(env, ptr, val, 0);
788
+}
789
+
790
+void cpu_stl_le_data(CPUArchState *env, target_ulong ptr, uint32_t val)
791
+{
792
+ cpu_stl_le_data_ra(env, ptr, val, 0);
793
+}
794
+
795
+void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val)
796
+{
797
+ cpu_stq_le_data_ra(env, ptr, val, 0);
798
}
799
800
/* First set of helpers allows passing in of OI and RETADDR. This makes
801
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
802
index XXXXXXX..XXXXXXX 100644
803
--- a/accel/tcg/user-exec.c
804
+++ b/accel/tcg/user-exec.c
805
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr)
806
return ret;
807
}
808
809
-uint32_t cpu_lduw_data(CPUArchState *env, abi_ptr ptr)
810
+uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr)
811
{
812
uint32_t ret;
813
- uint16_t meminfo = trace_mem_get_info(MO_TEUW, MMU_USER_IDX, false);
814
+ uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, false);
815
816
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
817
- ret = lduw_p(g2h(ptr));
818
+ ret = lduw_be_p(g2h(ptr));
819
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
820
return ret;
821
}
822
823
-int cpu_ldsw_data(CPUArchState *env, abi_ptr ptr)
824
+int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr)
825
{
826
int ret;
827
- uint16_t meminfo = trace_mem_get_info(MO_TESW, MMU_USER_IDX, false);
828
+ uint16_t meminfo = trace_mem_get_info(MO_BESW, MMU_USER_IDX, false);
829
830
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
831
- ret = ldsw_p(g2h(ptr));
832
+ ret = ldsw_be_p(g2h(ptr));
833
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
834
return ret;
835
}
836
837
-uint32_t cpu_ldl_data(CPUArchState *env, abi_ptr ptr)
838
+uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
839
{
840
uint32_t ret;
841
- uint16_t meminfo = trace_mem_get_info(MO_TEUL, MMU_USER_IDX, false);
842
+ uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, false);
843
844
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
845
- ret = ldl_p(g2h(ptr));
846
+ ret = ldl_be_p(g2h(ptr));
847
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
848
return ret;
849
}
850
851
-uint64_t cpu_ldq_data(CPUArchState *env, abi_ptr ptr)
852
+uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr)
853
{
854
uint64_t ret;
855
- uint16_t meminfo = trace_mem_get_info(MO_TEQ, MMU_USER_IDX, false);
856
+ uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, false);
857
858
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
859
- ret = ldq_p(g2h(ptr));
860
+ ret = ldq_be_p(g2h(ptr));
861
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
862
+ return ret;
863
+}
864
+
865
+uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr)
866
+{
867
+ uint32_t ret;
868
+ uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, false);
869
+
870
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
871
+ ret = lduw_le_p(g2h(ptr));
872
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
873
+ return ret;
874
+}
875
+
876
+int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr)
877
+{
878
+ int ret;
879
+ uint16_t meminfo = trace_mem_get_info(MO_LESW, MMU_USER_IDX, false);
880
+
881
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
882
+ ret = ldsw_le_p(g2h(ptr));
883
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
884
+ return ret;
885
+}
886
+
887
+uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
888
+{
889
+ uint32_t ret;
890
+ uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, false);
891
+
892
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
893
+ ret = ldl_le_p(g2h(ptr));
894
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
895
+ return ret;
896
+}
897
+
898
+uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr)
899
+{
900
+ uint64_t ret;
901
+ uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, false);
902
+
903
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
904
+ ret = ldq_le_p(g2h(ptr));
905
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
906
return ret;
907
}
908
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
909
return ret;
910
}
911
912
-uint32_t cpu_lduw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
913
+uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
914
{
915
uint32_t ret;
916
917
set_helper_retaddr(retaddr);
918
- ret = cpu_lduw_data(env, ptr);
919
+ ret = cpu_lduw_be_data(env, ptr);
920
clear_helper_retaddr();
921
return ret;
922
}
923
924
-int cpu_ldsw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
925
+int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
926
{
927
int ret;
928
929
set_helper_retaddr(retaddr);
930
- ret = cpu_ldsw_data(env, ptr);
931
+ ret = cpu_ldsw_be_data(env, ptr);
932
clear_helper_retaddr();
933
return ret;
934
}
935
936
-uint32_t cpu_ldl_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
937
+uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
938
{
939
uint32_t ret;
940
941
set_helper_retaddr(retaddr);
942
- ret = cpu_ldl_data(env, ptr);
943
+ ret = cpu_ldl_be_data(env, ptr);
944
clear_helper_retaddr();
945
return ret;
946
}
947
948
-uint64_t cpu_ldq_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
949
+uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
950
{
951
uint64_t ret;
952
953
set_helper_retaddr(retaddr);
954
- ret = cpu_ldq_data(env, ptr);
955
+ ret = cpu_ldq_be_data(env, ptr);
956
+ clear_helper_retaddr();
957
+ return ret;
958
+}
959
+
960
+uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
961
+{
962
+ uint32_t ret;
963
+
964
+ set_helper_retaddr(retaddr);
965
+ ret = cpu_lduw_le_data(env, ptr);
966
+ clear_helper_retaddr();
967
+ return ret;
968
+}
969
+
970
+int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
971
+{
972
+ int ret;
973
+
974
+ set_helper_retaddr(retaddr);
975
+ ret = cpu_ldsw_le_data(env, ptr);
976
+ clear_helper_retaddr();
977
+ return ret;
978
+}
979
+
980
+uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
981
+{
982
+ uint32_t ret;
983
+
984
+ set_helper_retaddr(retaddr);
985
+ ret = cpu_ldl_le_data(env, ptr);
986
+ clear_helper_retaddr();
987
+ return ret;
988
+}
989
+
990
+uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
991
+{
992
+ uint64_t ret;
993
+
994
+ set_helper_retaddr(retaddr);
995
+ ret = cpu_ldq_le_data(env, ptr);
996
clear_helper_retaddr();
997
return ret;
998
}
999
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1000
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1001
}
1002
1003
-void cpu_stw_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1004
+void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1005
{
1006
- uint16_t meminfo = trace_mem_get_info(MO_TEUW, MMU_USER_IDX, true);
1007
+ uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, true);
1008
1009
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1010
- stw_p(g2h(ptr), val);
1011
+ stw_be_p(g2h(ptr), val);
1012
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1013
}
1014
1015
-void cpu_stl_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1016
+void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1017
{
1018
- uint16_t meminfo = trace_mem_get_info(MO_TEUL, MMU_USER_IDX, true);
1019
+ uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, true);
1020
1021
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1022
- stl_p(g2h(ptr), val);
1023
+ stl_be_p(g2h(ptr), val);
1024
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1025
}
1026
1027
-void cpu_stq_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
1028
+void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
1029
{
1030
- uint16_t meminfo = trace_mem_get_info(MO_TEQ, MMU_USER_IDX, true);
1031
+ uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, true);
1032
1033
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1034
- stq_p(g2h(ptr), val);
1035
+ stq_be_p(g2h(ptr), val);
1036
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1037
+}
1038
+
1039
+void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1040
+{
1041
+ uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, true);
1042
+
1043
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1044
+ stw_le_p(g2h(ptr), val);
1045
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1046
+}
1047
+
1048
+void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1049
+{
1050
+ uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, true);
1051
+
1052
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1053
+ stl_le_p(g2h(ptr), val);
1054
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1055
+}
1056
+
1057
+void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
1058
+{
1059
+ uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, true);
1060
+
1061
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1062
+ stq_le_p(g2h(ptr), val);
1063
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1064
}
1065
1066
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
1067
clear_helper_retaddr();
1068
}
1069
1070
-void cpu_stw_data_ra(CPUArchState *env, abi_ptr ptr,
1071
- uint32_t val, uintptr_t retaddr)
1072
+void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
1073
+ uint32_t val, uintptr_t retaddr)
1074
{
1075
set_helper_retaddr(retaddr);
1076
- cpu_stw_data(env, ptr, val);
1077
+ cpu_stw_be_data(env, ptr, val);
1078
clear_helper_retaddr();
1079
}
1080
1081
-void cpu_stl_data_ra(CPUArchState *env, abi_ptr ptr,
1082
- uint32_t val, uintptr_t retaddr)
1083
+void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
1084
+ uint32_t val, uintptr_t retaddr)
1085
{
1086
set_helper_retaddr(retaddr);
1087
- cpu_stl_data(env, ptr, val);
1088
+ cpu_stl_be_data(env, ptr, val);
1089
clear_helper_retaddr();
1090
}
1091
1092
-void cpu_stq_data_ra(CPUArchState *env, abi_ptr ptr,
1093
- uint64_t val, uintptr_t retaddr)
1094
+void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
1095
+ uint64_t val, uintptr_t retaddr)
1096
{
1097
set_helper_retaddr(retaddr);
1098
- cpu_stq_data(env, ptr, val);
1099
+ cpu_stq_be_data(env, ptr, val);
1100
+ clear_helper_retaddr();
1101
+}
1102
+
1103
+void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
1104
+ uint32_t val, uintptr_t retaddr)
1105
+{
1106
+ set_helper_retaddr(retaddr);
1107
+ cpu_stw_le_data(env, ptr, val);
1108
+ clear_helper_retaddr();
1109
+}
1110
+
1111
+void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
1112
+ uint32_t val, uintptr_t retaddr)
1113
+{
1114
+ set_helper_retaddr(retaddr);
1115
+ cpu_stl_le_data(env, ptr, val);
1116
+ clear_helper_retaddr();
1117
+}
1118
+
1119
+void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
1120
+ uint64_t val, uintptr_t retaddr)
1121
+{
1122
+ set_helper_retaddr(retaddr);
1123
+ cpu_stq_le_data(env, ptr, val);
1124
clear_helper_retaddr();
1125
}
1126
1127
--
56
--
1128
2.20.1
57
2.34.1
1129
1130
diff view generated by jsdifflib
New patch
[PULL 32/72] target/m68k: Don't pass NULL float_status to floatx80_default_nan()
1
Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL)
2
to get the NaN bit pattern to reset the FPU registers. This
3
works because it happens that our implementation of
4
floatx80_default_nan() doesn't actually look at the float_status
5
pointer except for TARGET_MIPS. However, this isn't guaranteed,
6
and to be able to remove the ifdef in floatx80_default_nan()
7
we're going to need a real float_status here.
1
8
9
Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status
10
earlier, and thus can pass it to floatx80_default_nan().
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20241202131347.498124-28-peter.maydell@linaro.org
15
---
16
target/m68k/cpu.c | 12 +++++++-----
17
1 file changed, 7 insertions(+), 5 deletions(-)
18
19
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/m68k/cpu.c
22
+++ b/target/m68k/cpu.c
23
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
24
CPUState *cs = CPU(obj);
25
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj);
26
CPUM68KState *env = cpu_env(cs);
27
- floatx80 nan = floatx80_default_nan(NULL);
28
+ floatx80 nan;
29
int i;
30
31
if (mcc->parent_phases.hold) {
32
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
33
#else
34
cpu_m68k_set_sr(env, SR_S | SR_I);
35
#endif
36
- for (i = 0; i < 8; i++) {
37
- env->fregs[i].d = nan;
38
- }
39
- cpu_m68k_set_fpcr(env, 0);
40
/*
41
* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
42
* 3.4 FLOATING-POINT INSTRUCTION DETAILS
43
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
44
* preceding paragraph for nonsignaling NaNs.
45
*/
46
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
47
+
48
+ nan = floatx80_default_nan(&env->fp_status);
49
+ for (i = 0; i < 8; i++) {
50
+ env->fregs[i].d = nan;
51
+ }
52
+ cpu_m68k_set_fpcr(env, 0);
53
env->fpsr = 0;
54
55
/* TODO: We should set PC from the interrupt vector. */
56
--
57
2.34.1
diff view generated by jsdifflib
[PULL 06/34] hw/timer/nrf51_timer: Display timer ID in trace events
[PULL 33/72] softfloat: Create floatx80 default NaN from parts64_default_nan
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
We create our 128-bit default NaN by calling parts64_default_nan()
2
and then adjusting the result. We can do the same trick for creating
3
the floatx80 default NaN, which lets us drop a target ifdef.
2
4
3
The NRF51 series SoC have 3 timer peripherals, each having
5
floatx80 is used only by:
4
4 counters. To help differentiate which peripheral is accessed,
6
i386
5
display the timer ID in the trace events.
7
m68k
8
arm nwfpe old floating-point emulation emulation support
9
(which is essentially dead, especially the parts involving floatx80)
10
PPC (only in the xsrqpxp instruction, which just rounds an input
11
value by converting to floatx80 and back, so will never generate
12
the default NaN)
6
13
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
The floatx80 default NaN as currently implemented is:
15
m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1
16
i386: sign = 1, exp = 1...1, int = 1, frac = 10...0
17
18
These are the same as the parts64_default_nan for these architectures.
19
20
This is technically a possible behaviour change for arm linux-user
21
nwfpe emulation emulation, because the default NaN will now have the
22
sign bit clear. But we were already generating a different floatx80
23
default NaN from the real kernel emulation we are supposedly
24
following, which appears to use an all-bits-1 value:
25
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267
26
27
This won't affect the only "real" use of the nwfpe emulation, which
28
is ancient binaries that used it as part of the old floating point
29
calling convention; that only uses loads and stores of 32 and 64 bit
30
floats, not any of the floatx80 behaviour the original hardware had.
31
We also get the nwfpe float64 default NaN value wrong:
32
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166
33
so if we ever cared about this obscure corner the right fix would be
34
to correct that so nwfpe used its own default-NaN setting rather
35
than the Arm VFP one.
36
37
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
38
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200504072822.18799-4-f4bug@amsat.org
39
Message-id: 20241202131347.498124-29-peter.maydell@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
40
---
12
include/hw/timer/nrf51_timer.h | 1 +
41
fpu/softfloat-specialize.c.inc | 20 ++++++++++----------
13
hw/arm/nrf51_soc.c | 5 +++++
42
1 file changed, 10 insertions(+), 10 deletions(-)
14
hw/timer/nrf51_timer.c | 11 +++++++++--
15
hw/timer/trace-events | 4 ++--
16
4 files changed, 17 insertions(+), 4 deletions(-)
17
43
18
diff --git a/include/hw/timer/nrf51_timer.h b/include/hw/timer/nrf51_timer.h
44
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
19
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/timer/nrf51_timer.h
46
--- a/fpu/softfloat-specialize.c.inc
21
+++ b/include/hw/timer/nrf51_timer.h
47
+++ b/fpu/softfloat-specialize.c.inc
22
@@ -XXX,XX +XXX,XX @@ typedef struct NRF51TimerState {
48
@@ -XXX,XX +XXX,XX @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status)
23
MemoryRegion iomem;
49
floatx80 floatx80_default_nan(float_status *status)
24
qemu_irq irq;
50
{
25
51
floatx80 r;
26
+ uint8_t id;
52
+ /*
27
QEMUTimer timer;
53
+ * Extrapolate from the choices made by parts64_default_nan to fill
28
int64_t timer_start_ns;
54
+ * in the floatx80 format. We assume that floatx80's explicit
29
int64_t update_counter_ns;
55
+ * integer bit is always set (this is true for i386 and m68k,
30
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
56
+ * which are the only real users of this format).
31
index XXXXXXX..XXXXXXX 100644
57
+ */
32
--- a/hw/arm/nrf51_soc.c
58
+ FloatParts64 p64;
33
+++ b/hw/arm/nrf51_soc.c
59
+ parts64_default_nan(&p64, status);
34
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
60
35
61
- /* None of the targets that have snan_bit_is_one use floatx80. */
36
/* TIMER */
62
- assert(!snan_bit_is_one(status));
37
for (i = 0; i < NRF51_NUM_TIMERS; i++) {
63
-#if defined(TARGET_M68K)
38
+ object_property_set_uint(OBJECT(&s->timer[i]), i, "id", &err);
64
- r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
39
+ if (err) {
65
- r.high = 0x7FFF;
40
+ error_propagate(errp, err);
66
-#else
41
+ return;
67
- /* X86 */
42
+ }
68
- r.low = UINT64_C(0xC000000000000000);
43
object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
69
- r.high = 0xFFFF;
44
if (err) {
70
-#endif
45
error_propagate(errp, err);
71
+ r.high = 0x7FFF | (p64.sign << 15);
46
diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c
72
+ r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac;
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/timer/nrf51_timer.c
49
+++ b/hw/timer/nrf51_timer.c
50
@@ -XXX,XX +XXX,XX @@
51
#include "hw/arm/nrf51.h"
52
#include "hw/irq.h"
53
#include "hw/timer/nrf51_timer.h"
54
+#include "hw/qdev-properties.h"
55
#include "migration/vmstate.h"
56
#include "trace.h"
57
58
@@ -XXX,XX +XXX,XX @@ static uint64_t nrf51_timer_read(void *opaque, hwaddr offset, unsigned int size)
59
__func__, offset);
60
}
61
62
- trace_nrf51_timer_read(offset, r, size);
63
+ trace_nrf51_timer_read(s->id, offset, r, size);
64
65
return r;
73
return r;
66
}
74
}
67
@@ -XXX,XX +XXX,XX @@ static void nrf51_timer_write(void *opaque, hwaddr offset,
75
68
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
69
size_t idx;
70
71
- trace_nrf51_timer_write(offset, value, size);
72
+ trace_nrf51_timer_write(s->id, offset, value, size);
73
74
switch (offset) {
75
case NRF51_TIMER_TASK_START:
76
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nrf51_timer = {
77
}
78
};
79
80
+static Property nrf51_timer_properties[] = {
81
+ DEFINE_PROP_UINT8("id", NRF51TimerState, id, 0),
82
+ DEFINE_PROP_END_OF_LIST(),
83
+};
84
+
85
static void nrf51_timer_class_init(ObjectClass *klass, void *data)
86
{
87
DeviceClass *dc = DEVICE_CLASS(klass);
88
89
dc->reset = nrf51_timer_reset;
90
dc->vmsd = &vmstate_nrf51_timer;
91
+ device_class_set_props(dc, nrf51_timer_properties);
92
}
93
94
static const TypeInfo nrf51_timer_info = {
95
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
96
index XXXXXXX..XXXXXXX 100644
97
--- a/hw/timer/trace-events
98
+++ b/hw/timer/trace-events
99
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK
100
cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
101
102
# nrf51_timer.c
103
-nrf51_timer_read(uint64_t addr, uint32_t value, unsigned size) "read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
104
-nrf51_timer_write(uint64_t addr, uint32_t value, unsigned size) "write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
105
+nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
106
+nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
107
108
# bcm2835_systmr.c
109
bcm2835_systmr_irq(bool enable) "timer irq state %u"
110
--
76
--
111
2.20.1
77
2.34.1
112
113
diff view generated by jsdifflib
New patch
[PULL 34/72] target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
1
In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass
2
a zero-initialized float_status struct to float32_is_quiet_nan() and
3
float64_is_quiet_nan(), with the cryptic comment "for
4
snan_bit_is_one".
1
5
6
This pattern appears to have been copied from target/riscv, where it
7
is used because the functions there do not have ready access to the
8
CPU state struct. The comment presumably refers to the fact that the
9
main reason the is_quiet_nan() functions want the float_state is
10
because they want to know about the snan_bit_is_one config.
11
12
In the loongarch helpers, though, we have the CPU state struct
13
to hand. Use the usual env->fp_status here. This avoids our needing
14
to track that we need to update the initializer of the local
15
float_status structs when the core softfloat code adds new
16
options for targets to configure their behaviour.
17
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20241202131347.498124-30-peter.maydell@linaro.org
21
---
22
target/loongarch/tcg/fpu_helper.c | 6 ++----
23
1 file changed, 2 insertions(+), 4 deletions(-)
24
25
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/loongarch/tcg/fpu_helper.c
28
+++ b/target/loongarch/tcg/fpu_helper.c
29
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj)
30
} else if (float32_is_zero_or_denormal(f)) {
31
return sign ? 1 << 4 : 1 << 8;
32
} else if (float32_is_any_nan(f)) {
33
- float_status s = { }; /* for snan_bit_is_one */
34
- return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
35
+ return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
36
} else {
37
return sign ? 1 << 3 : 1 << 7;
38
}
39
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj)
40
} else if (float64_is_zero_or_denormal(f)) {
41
return sign ? 1 << 4 : 1 << 8;
42
} else if (float64_is_any_nan(f)) {
43
- float_status s = { }; /* for snan_bit_is_one */
44
- return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
45
+ return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
46
} else {
47
return sign ? 1 << 3 : 1 << 7;
48
}
49
--
50
2.34.1
diff view generated by jsdifflib
New patch
[PULL 35/72] target/m68k: In frem helper, initialize local float_status from env->fp_status
1
In the frem helper, we have a local float_status because we want to
2
execute the floatx80_div() with a custom rounding mode. Instead of
3
zero-initializing the local float_status and then having to set it up
4
with the m68k standard behaviour (including the NaN propagation rule
5
and copying the rounding precision from env->fp_status), initialize
6
it as a complete copy of env->fp_status. This will avoid our having
7
to add new code in this function for every new config knob we add
8
to fp_status.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-31-peter.maydell@linaro.org
13
---
14
target/m68k/fpu_helper.c | 6 ++----
15
1 file changed, 2 insertions(+), 4 deletions(-)
16
17
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/m68k/fpu_helper.c
20
+++ b/target/m68k/fpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
22
23
fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status);
24
if (!floatx80_is_any_nan(fp_rem)) {
25
- float_status fp_status = { };
26
+ /* Use local temporary fp_status to set different rounding mode */
27
+ float_status fp_status = env->fp_status;
28
uint32_t quotient;
29
int sign;
30
31
/* Calculate quotient directly using round to nearest mode */
32
- set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status);
33
set_float_rounding_mode(float_round_nearest_even, &fp_status);
34
- set_floatx80_rounding_precision(
35
- get_floatx80_rounding_precision(&env->fp_status), &fp_status);
36
fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status);
37
38
sign = extractFloatx80Sign(fp_quot.d);
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 36/72] target/m68k: Init local float_status from env fp_status in gdb get/set reg
1
In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion
2
from float64 to floatx80 using a scratch float_status, because we
3
don't want the conversion to affect the CPU's floating point exception
4
status. Currently we use a zero-initialized float_status. This will
5
get steadily more awkward as we add config knobs to float_status
6
that the target must initialize. Avoid having to add any of that
7
configuration here by instead initializing our local float_status
8
from the env->fp_status.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-32-peter.maydell@linaro.org
13
---
14
target/m68k/helper.c | 6 ++++--
15
1 file changed, 4 insertions(+), 2 deletions(-)
16
17
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/m68k/helper.c
20
+++ b/target/m68k/helper.c
21
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n)
22
CPUM68KState *env = &cpu->env;
23
24
if (n < 8) {
25
- float_status s = {};
26
+ /* Use scratch float_status so any exceptions don't change CPU state */
27
+ float_status s = env->fp_status;
28
return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s));
29
}
30
switch (n) {
31
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n)
32
CPUM68KState *env = &cpu->env;
33
34
if (n < 8) {
35
- float_status s = {};
36
+ /* Use scratch float_status so any exceptions don't change CPU state */
37
+ float_status s = env->fp_status;
38
env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s);
39
return 8;
40
}
41
--
42
2.34.1
diff view generated by jsdifflib
[PULL 15/34] target/arm: Drop manual handling of set/clear_helper_retaddr
[PULL 37/72] target/sparc: Initialize local scratch float_status from env->fp_status
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In the helper functions flcmps and flcmpd we use a scratch float_status
2
so that we don't change the CPU state if the comparison raises any
3
floating point exception flags. Instead of zero-initializing this
4
scratch float_status, initialize it as a copy of env->fp_status. This
5
avoids the need to explicitly initialize settings like the NaN
6
propagation rule or others we might add to softfloat in future.
2
7
3
Since we converted back to cpu_*_data_ra, we do not need to
8
To do this we need to pass the CPU env pointer in to the helper.
4
do this ourselves.
5
9
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200508154359.7494-9-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-33-peter.maydell@linaro.org
10
---
13
---
11
target/arm/sve_helper.c | 38 --------------------------------------
14
target/sparc/helper.h | 4 ++--
12
1 file changed, 38 deletions(-)
15
target/sparc/fop_helper.c | 8 ++++----
16
target/sparc/translate.c | 4 ++--
17
3 files changed, 8 insertions(+), 8 deletions(-)
13
18
14
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
19
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
15
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/sve_helper.c
21
--- a/target/sparc/helper.h
17
+++ b/target/arm/sve_helper.c
22
+++ b/target/sparc/helper.h
18
@@ -XXX,XX +XXX,XX @@ static intptr_t max_for_page(target_ulong base, intptr_t mem_off,
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64)
19
return MIN(split, mem_max - mem_off) + mem_off;
24
DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64)
25
DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128)
26
DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128)
27
-DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32)
28
-DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64)
29
+DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32)
30
+DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64)
31
DEF_HELPER_2(raise_exception, noreturn, env, int)
32
33
DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64)
34
diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/sparc/fop_helper.c
37
+++ b/target/sparc/fop_helper.c
38
@@ -XXX,XX +XXX,XX @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2)
39
return finish_fcmp(env, r, GETPC());
20
}
40
}
21
41
22
-#ifndef CONFIG_USER_ONLY
42
-uint32_t helper_flcmps(float32 src1, float32 src2)
23
-/* These are normally defined only for CONFIG_USER_ONLY in <exec/cpu_ldst.h> */
43
+uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2)
24
-static inline void set_helper_retaddr(uintptr_t ra) { }
44
{
25
-static inline void clear_helper_retaddr(void) { }
26
-#endif
27
-
28
/*
29
* The result of tlb_vaddr_to_host for user-only is just g2h(x),
30
* which is always non-null. Elide the useless test.
31
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
32
return;
33
}
34
mem_off = reg_off >> diffsz;
35
- set_helper_retaddr(retaddr);
36
37
/*
45
/*
38
* If the (remaining) load is entirely within a single page, then:
46
* FLCMP never raises an exception nor modifies any FSR fields.
39
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
47
* Perform the comparison with a dummy fp environment.
40
if (test_host_page(host)) {
48
*/
41
mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
49
- float_status discard = { };
42
tcg_debug_assert(mem_off == mem_max);
50
+ float_status discard = env->fp_status;
43
- clear_helper_retaddr();
51
FloatRelation r;
44
/* After having taken any fault, zero leading inactive elements. */
52
45
swap_memzero(vd, reg_off);
53
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
46
return;
54
@@ -XXX,XX +XXX,XX @@ uint32_t helper_flcmps(float32 src1, float32 src2)
47
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
55
g_assert_not_reached();
48
}
49
#endif
50
51
- clear_helper_retaddr();
52
memcpy(vd, &scratch, reg_max);
53
}
56
}
54
57
55
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
58
-uint32_t helper_flcmpd(float64 src1, float64 src2)
56
intptr_t i, oprsz = simd_oprsz(desc);
59
+uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2)
57
ARMVectorReg scratch[2] = { };
60
{
58
61
- float_status discard = { };
59
- set_helper_retaddr(ra);
62
+ float_status discard = env->fp_status;
60
for (i = 0; i < oprsz; ) {
63
FloatRelation r;
61
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
64
62
do {
65
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
63
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
66
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
64
addr += 2 * size;
67
index XXXXXXX..XXXXXXX 100644
65
} while (i & 15);
68
--- a/target/sparc/translate.c
66
}
69
+++ b/target/sparc/translate.c
67
- clear_helper_retaddr();
70
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a)
68
71
69
/* Wait until all exceptions have been raised to write back. */
72
src1 = gen_load_fpr_F(dc, a->rs1);
70
memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
73
src2 = gen_load_fpr_F(dc, a->rs2);
71
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
74
- gen_helper_flcmps(cpu_fcc[a->cc], src1, src2);
72
intptr_t i, oprsz = simd_oprsz(desc);
75
+ gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2);
73
ARMVectorReg scratch[3] = { };
76
return advance_pc(dc);
74
75
- set_helper_retaddr(ra);
76
for (i = 0; i < oprsz; ) {
77
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
78
do {
79
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
80
addr += 3 * size;
81
} while (i & 15);
82
}
83
- clear_helper_retaddr();
84
85
/* Wait until all exceptions have been raised to write back. */
86
memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
87
@@ -XXX,XX +XXX,XX @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
88
intptr_t i, oprsz = simd_oprsz(desc);
89
ARMVectorReg scratch[4] = { };
90
91
- set_helper_retaddr(ra);
92
for (i = 0; i < oprsz; ) {
93
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
94
do {
95
@@ -XXX,XX +XXX,XX @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
96
addr += 4 * size;
97
} while (i & 15);
98
}
99
- clear_helper_retaddr();
100
101
/* Wait until all exceptions have been raised to write back. */
102
memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
103
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
104
return;
105
}
106
mem_off = reg_off >> diffsz;
107
- set_helper_retaddr(retaddr);
108
109
/*
110
* If the (remaining) load is entirely within a single page, then:
111
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
112
if (test_host_page(host)) {
113
mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
114
tcg_debug_assert(mem_off == mem_max);
115
- clear_helper_retaddr();
116
/* After any fault, zero any leading inactive elements. */
117
swap_memzero(vd, reg_off);
118
return;
119
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
120
}
121
#endif
122
123
- clear_helper_retaddr();
124
record_fault(env, reg_off, reg_max);
125
}
77
}
126
78
127
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
79
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a)
128
intptr_t i, oprsz = simd_oprsz(desc);
80
129
void *vd = &env->vfp.zregs[rd];
81
src1 = gen_load_fpr_D(dc, a->rs1);
130
82
src2 = gen_load_fpr_D(dc, a->rs2);
131
- set_helper_retaddr(ra);
83
- gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2);
132
for (i = 0; i < oprsz; ) {
84
+ gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2);
133
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
85
return advance_pc(dc);
134
do {
135
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
136
addr += msize;
137
} while (i & 15);
138
}
139
- clear_helper_retaddr();
140
}
86
}
141
87
142
static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
143
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
144
void *d1 = &env->vfp.zregs[rd];
145
void *d2 = &env->vfp.zregs[(rd + 1) & 31];
146
147
- set_helper_retaddr(ra);
148
for (i = 0; i < oprsz; ) {
149
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
150
do {
151
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
152
addr += 2 * msize;
153
} while (i & 15);
154
}
155
- clear_helper_retaddr();
156
}
157
158
static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
159
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
160
void *d2 = &env->vfp.zregs[(rd + 1) & 31];
161
void *d3 = &env->vfp.zregs[(rd + 2) & 31];
162
163
- set_helper_retaddr(ra);
164
for (i = 0; i < oprsz; ) {
165
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
166
do {
167
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
168
addr += 3 * msize;
169
} while (i & 15);
170
}
171
- clear_helper_retaddr();
172
}
173
174
static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
175
@@ -XXX,XX +XXX,XX @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
176
void *d3 = &env->vfp.zregs[(rd + 2) & 31];
177
void *d4 = &env->vfp.zregs[(rd + 3) & 31];
178
179
- set_helper_retaddr(ra);
180
for (i = 0; i < oprsz; ) {
181
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
182
do {
183
@@ -XXX,XX +XXX,XX @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
184
addr += 4 * msize;
185
} while (i & 15);
186
}
187
- clear_helper_retaddr();
188
}
189
190
#define DO_STN_1(N, NAME, ESIZE) \
191
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
192
intptr_t i, oprsz = simd_oprsz(desc);
193
ARMVectorReg scratch = { };
194
195
- set_helper_retaddr(ra);
196
for (i = 0; i < oprsz; ) {
197
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
198
do {
199
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
200
i += 4, pg >>= 4;
201
} while (i & 15);
202
}
203
- clear_helper_retaddr();
204
205
/* Wait until all exceptions have been raised to write back. */
206
memcpy(vd, &scratch, oprsz);
207
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
208
intptr_t i, oprsz = simd_oprsz(desc) / 8;
209
ARMVectorReg scratch = { };
210
211
- set_helper_retaddr(ra);
212
for (i = 0; i < oprsz; i++) {
213
uint8_t pg = *(uint8_t *)(vg + H1(i));
214
if (likely(pg & 1)) {
215
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
216
tlb_fn(env, &scratch, i * 8, base + (off << scale), ra);
217
}
218
}
219
- clear_helper_retaddr();
220
221
/* Wait until all exceptions have been raised to write back. */
222
memcpy(vd, &scratch, oprsz * 8);
223
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
224
reg_off = find_next_active(vg, 0, reg_max, MO_32);
225
if (likely(reg_off < reg_max)) {
226
/* Perform one normal read, which will fault or not. */
227
- set_helper_retaddr(ra);
228
addr = off_fn(vm, reg_off);
229
addr = base + (addr << scale);
230
tlb_fn(env, vd, reg_off, addr, ra);
231
232
/* The rest of the reads will be non-faulting. */
233
- clear_helper_retaddr();
234
}
235
236
/* After any fault, zero the leading predicated false elements. */
237
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
238
reg_off = find_next_active(vg, 0, reg_max, MO_64);
239
if (likely(reg_off < reg_max)) {
240
/* Perform one normal read, which will fault or not. */
241
- set_helper_retaddr(ra);
242
addr = off_fn(vm, reg_off);
243
addr = base + (addr << scale);
244
tlb_fn(env, vd, reg_off, addr, ra);
245
246
/* The rest of the reads will be non-faulting. */
247
- clear_helper_retaddr();
248
}
249
250
/* After any fault, zero the leading predicated false elements. */
251
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
252
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
253
intptr_t i, oprsz = simd_oprsz(desc);
254
255
- set_helper_retaddr(ra);
256
for (i = 0; i < oprsz; ) {
257
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
258
do {
259
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
260
i += 4, pg >>= 4;
261
} while (i & 15);
262
}
263
- clear_helper_retaddr();
264
}
265
266
static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
267
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
268
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
269
intptr_t i, oprsz = simd_oprsz(desc) / 8;
270
271
- set_helper_retaddr(ra);
272
for (i = 0; i < oprsz; i++) {
273
uint8_t pg = *(uint8_t *)(vg + H1(i));
274
if (likely(pg & 1)) {
275
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
276
tlb_fn(env, vd, i * 8, base + (off << scale), ra);
277
}
278
}
279
- clear_helper_retaddr();
280
}
281
282
#define DO_ST1_ZPZ_S(MEM, OFS) \
283
--
88
--
284
2.20.1
89
2.34.1
285
286
diff view generated by jsdifflib
New patch
[PULL 38/72] target/ppc: Use env->fp_status in helper_compute_fprf functions
1
In the helper_compute_fprf functions, we pass a dummy float_status
2
in to the is_signaling_nan() function. This is unnecessary, because
3
we have convenient access to the CPU env pointer here and that
4
is already set up with the correct values for the snan_bit_is_one
5
and no_signaling_nans config settings. is_signaling_nan() doesn't
6
ever update the fp_status with any exception flags, so there is
7
no reason not to use env->fp_status here.
1
8
9
Use env->fp_status instead of the dummy fp_status.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20241202131347.498124-34-peter.maydell@linaro.org
14
---
15
target/ppc/fpu_helper.c | 3 +--
16
1 file changed, 1 insertion(+), 2 deletions(-)
17
18
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/ppc/fpu_helper.c
21
+++ b/target/ppc/fpu_helper.c
22
@@ -XXX,XX +XXX,XX @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
23
} else if (tp##_is_infinity(arg)) { \
24
fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \
25
} else { \
26
- float_status dummy = { }; /* snan_bit_is_one = 0 */ \
27
- if (tp##_is_signaling_nan(arg, &dummy)) { \
28
+ if (tp##_is_signaling_nan(arg, &env->fp_status)) { \
29
fprf = 0x00 << FPSCR_FPRF; \
30
} else { \
31
fprf = 0x11 << FPSCR_FPRF; \
32
--
33
2.34.1
diff view generated by jsdifflib
[PULL 33/34] target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
[PULL 39/72] target/arm: Copy entire float_status in is_ebf
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Now that we can pass 7 parameters, do not encode register
3
Now that float_status has a bunch of fp parameters,
4
operands within simd_data.
4
it is easier to copy an existing structure than create
5
one from scratch. Begin by copying the structure that
6
corresponds to the FPSR and make only the adjustments
7
required for BFloat16 semantics.
5
8
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200507172352.15418-2-richard.henderson@linaro.org
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20241203203949.483774-2-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
14
---
12
target/arm/helper-sve.h | 45 +++++++----
15
target/arm/tcg/vec_helper.c | 20 +++++++-------------
13
target/arm/sve_helper.c | 157 ++++++++++++++-----------------------
16
1 file changed, 7 insertions(+), 13 deletions(-)
14
target/arm/translate-sve.c | 70 ++++++-----------
15
3 files changed, 114 insertions(+), 158 deletions(-)
16
17
17
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
18
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper-sve.h
20
--- a/target/arm/tcg/vec_helper.c
20
+++ b/target/arm/helper-sve.h
21
+++ b/target/arm/tcg/vec_helper.c
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_6(sve_fcadd_s, TCG_CALL_NO_RWG,
22
@@ -XXX,XX +XXX,XX @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp)
22
DEF_HELPER_FLAGS_6(sve_fcadd_d, TCG_CALL_NO_RWG,
23
* no effect on AArch32 instructions.
23
void, ptr, ptr, ptr, ptr, ptr, i32)
24
*/
24
25
bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF;
25
-DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
26
- *statusp = (float_status){
26
-DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
27
- .tininess_before_rounding = float_tininess_before_rounding,
27
-DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
28
- .float_rounding_mode = float_round_to_odd_inf,
28
+DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG,
29
- .flush_to_zero = true,
29
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
30
- .flush_inputs_to_zero = true,
30
+DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG,
31
- .default_nan_mode = true,
31
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
32
- };
32
+DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG,
33
+
33
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
34
+ *statusp = env->vfp.fp_status;
34
35
+ set_default_nan_mode(true, statusp);
35
-DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
36
36
-DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
37
if (ebf) {
37
-DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
38
- float_status *fpst = &env->vfp.fp_status;
38
+DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG,
39
- set_flush_to_zero(get_flush_to_zero(fpst), statusp);
39
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
40
- set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp);
40
+DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG,
41
- set_float_rounding_mode(get_float_rounding_mode(fpst), statusp);
41
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
42
+DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG,
43
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
44
45
-DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
46
-DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
47
-DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
48
+DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG,
49
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
50
+DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG,
51
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
52
+DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG,
53
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
54
55
-DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
56
-DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
57
-DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
58
+DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG,
59
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
60
+DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG,
61
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
62
+DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG,
63
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
64
65
-DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
66
-DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
67
-DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
68
+DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG,
69
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
70
+DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG,
71
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
72
+DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG,
73
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
74
75
DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
76
DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
77
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/target/arm/sve_helper.c
80
+++ b/target/arm/sve_helper.c
81
@@ -XXX,XX +XXX,XX @@ DO_ZPZ_FP(sve_ucvt_dd, uint64_t, , uint64_to_float64)
82
83
#undef DO_ZPZ_FP
84
85
-/* 4-operand predicated multiply-add. This requires 7 operands to pass
86
- * "properly", so we need to encode some of the registers into DESC.
87
- */
88
-QEMU_BUILD_BUG_ON(SIMD_DATA_SHIFT + 20 > 32);
89
-
42
-
90
-static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
43
/* EBF=1 needs to do a step with round-to-odd semantics */
91
+static void do_fmla_zpzzz_h(void *vd, void *vn, void *vm, void *va, void *vg,
44
*oddstatusp = *statusp;
92
+ float_status *status, uint32_t desc,
45
set_float_rounding_mode(float_round_to_odd, oddstatusp);
93
uint16_t neg1, uint16_t neg3)
46
+ } else {
94
{
47
+ set_flush_to_zero(true, statusp);
95
intptr_t i = simd_oprsz(desc);
48
+ set_flush_inputs_to_zero(true, statusp);
96
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
49
+ set_float_rounding_mode(float_round_to_odd_inf, statusp);
97
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
98
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
99
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
100
- void *vd = &env->vfp.zregs[rd];
101
- void *vn = &env->vfp.zregs[rn];
102
- void *vm = &env->vfp.zregs[rm];
103
- void *va = &env->vfp.zregs[ra];
104
uint64_t *g = vg;
105
106
do {
107
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
108
e1 = *(uint16_t *)(vn + H1_2(i)) ^ neg1;
109
e2 = *(uint16_t *)(vm + H1_2(i));
110
e3 = *(uint16_t *)(va + H1_2(i)) ^ neg3;
111
- r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status_f16);
112
+ r = float16_muladd(e1, e2, e3, 0, status);
113
*(uint16_t *)(vd + H1_2(i)) = r;
114
}
115
} while (i & 63);
116
} while (i != 0);
117
}
118
119
-void HELPER(sve_fmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
120
+void HELPER(sve_fmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
121
+ void *vg, void *status, uint32_t desc)
122
{
123
- do_fmla_zpzzz_h(env, vg, desc, 0, 0);
124
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0);
125
}
126
127
-void HELPER(sve_fmls_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
128
+void HELPER(sve_fmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
129
+ void *vg, void *status, uint32_t desc)
130
{
131
- do_fmla_zpzzz_h(env, vg, desc, 0x8000, 0);
132
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0);
133
}
134
135
-void HELPER(sve_fnmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
136
+void HELPER(sve_fnmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
137
+ void *vg, void *status, uint32_t desc)
138
{
139
- do_fmla_zpzzz_h(env, vg, desc, 0x8000, 0x8000);
140
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0x8000);
141
}
142
143
-void HELPER(sve_fnmls_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
144
+void HELPER(sve_fnmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
145
+ void *vg, void *status, uint32_t desc)
146
{
147
- do_fmla_zpzzz_h(env, vg, desc, 0, 0x8000);
148
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0x8000);
149
}
150
151
-static void do_fmla_zpzzz_s(CPUARMState *env, void *vg, uint32_t desc,
152
+static void do_fmla_zpzzz_s(void *vd, void *vn, void *vm, void *va, void *vg,
153
+ float_status *status, uint32_t desc,
154
uint32_t neg1, uint32_t neg3)
155
{
156
intptr_t i = simd_oprsz(desc);
157
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
158
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
159
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
160
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
161
- void *vd = &env->vfp.zregs[rd];
162
- void *vn = &env->vfp.zregs[rn];
163
- void *vm = &env->vfp.zregs[rm];
164
- void *va = &env->vfp.zregs[ra];
165
uint64_t *g = vg;
166
167
do {
168
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_s(CPUARMState *env, void *vg, uint32_t desc,
169
e1 = *(uint32_t *)(vn + H1_4(i)) ^ neg1;
170
e2 = *(uint32_t *)(vm + H1_4(i));
171
e3 = *(uint32_t *)(va + H1_4(i)) ^ neg3;
172
- r = float32_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
173
+ r = float32_muladd(e1, e2, e3, 0, status);
174
*(uint32_t *)(vd + H1_4(i)) = r;
175
}
176
} while (i & 63);
177
} while (i != 0);
178
}
179
180
-void HELPER(sve_fmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
181
+void HELPER(sve_fmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
182
+ void *vg, void *status, uint32_t desc)
183
{
184
- do_fmla_zpzzz_s(env, vg, desc, 0, 0);
185
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0);
186
}
187
188
-void HELPER(sve_fmls_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
189
+void HELPER(sve_fmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
190
+ void *vg, void *status, uint32_t desc)
191
{
192
- do_fmla_zpzzz_s(env, vg, desc, 0x80000000, 0);
193
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0);
194
}
195
196
-void HELPER(sve_fnmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
197
+void HELPER(sve_fnmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
198
+ void *vg, void *status, uint32_t desc)
199
{
200
- do_fmla_zpzzz_s(env, vg, desc, 0x80000000, 0x80000000);
201
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0x80000000);
202
}
203
204
-void HELPER(sve_fnmls_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
205
+void HELPER(sve_fnmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
206
+ void *vg, void *status, uint32_t desc)
207
{
208
- do_fmla_zpzzz_s(env, vg, desc, 0, 0x80000000);
209
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0x80000000);
210
}
211
212
-static void do_fmla_zpzzz_d(CPUARMState *env, void *vg, uint32_t desc,
213
+static void do_fmla_zpzzz_d(void *vd, void *vn, void *vm, void *va, void *vg,
214
+ float_status *status, uint32_t desc,
215
uint64_t neg1, uint64_t neg3)
216
{
217
intptr_t i = simd_oprsz(desc);
218
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
219
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
220
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
221
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
222
- void *vd = &env->vfp.zregs[rd];
223
- void *vn = &env->vfp.zregs[rn];
224
- void *vm = &env->vfp.zregs[rm];
225
- void *va = &env->vfp.zregs[ra];
226
uint64_t *g = vg;
227
228
do {
229
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_d(CPUARMState *env, void *vg, uint32_t desc,
230
e1 = *(uint64_t *)(vn + i) ^ neg1;
231
e2 = *(uint64_t *)(vm + i);
232
e3 = *(uint64_t *)(va + i) ^ neg3;
233
- r = float64_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
234
+ r = float64_muladd(e1, e2, e3, 0, status);
235
*(uint64_t *)(vd + i) = r;
236
}
237
} while (i & 63);
238
} while (i != 0);
239
}
240
241
-void HELPER(sve_fmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
242
+void HELPER(sve_fmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
243
+ void *vg, void *status, uint32_t desc)
244
{
245
- do_fmla_zpzzz_d(env, vg, desc, 0, 0);
246
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, 0);
247
}
248
249
-void HELPER(sve_fmls_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
250
+void HELPER(sve_fmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
251
+ void *vg, void *status, uint32_t desc)
252
{
253
- do_fmla_zpzzz_d(env, vg, desc, INT64_MIN, 0);
254
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, 0);
255
}
256
257
-void HELPER(sve_fnmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
258
+void HELPER(sve_fnmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
259
+ void *vg, void *status, uint32_t desc)
260
{
261
- do_fmla_zpzzz_d(env, vg, desc, INT64_MIN, INT64_MIN);
262
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, INT64_MIN);
263
}
264
265
-void HELPER(sve_fnmls_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
266
+void HELPER(sve_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
267
+ void *vg, void *status, uint32_t desc)
268
{
269
- do_fmla_zpzzz_d(env, vg, desc, 0, INT64_MIN);
270
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, INT64_MIN);
271
}
272
273
/* Two operand floating-point comparison controlled by a predicate.
274
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
275
* FP Complex Multiply
276
*/
277
278
-QEMU_BUILD_BUG_ON(SIMD_DATA_SHIFT + 22 > 32);
279
-
280
-void HELPER(sve_fcmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
281
+void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
282
+ void *vg, void *status, uint32_t desc)
283
{
284
intptr_t j, i = simd_oprsz(desc);
285
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
286
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
287
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
288
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
289
- unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
290
+ unsigned rot = simd_data(desc);
291
bool flip = rot & 1;
292
float16 neg_imag, neg_real;
293
- void *vd = &env->vfp.zregs[rd];
294
- void *vn = &env->vfp.zregs[rn];
295
- void *vm = &env->vfp.zregs[rm];
296
- void *va = &env->vfp.zregs[ra];
297
uint64_t *g = vg;
298
299
neg_imag = float16_set_sign(0, (rot & 2) != 0);
300
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
301
302
if (likely((pg >> (i & 63)) & 1)) {
303
d = *(float16 *)(va + H1_2(i));
304
- d = float16_muladd(e2, e1, d, 0, &env->vfp.fp_status_f16);
305
+ d = float16_muladd(e2, e1, d, 0, status);
306
*(float16 *)(vd + H1_2(i)) = d;
307
}
308
if (likely((pg >> (j & 63)) & 1)) {
309
d = *(float16 *)(va + H1_2(j));
310
- d = float16_muladd(e4, e3, d, 0, &env->vfp.fp_status_f16);
311
+ d = float16_muladd(e4, e3, d, 0, status);
312
*(float16 *)(vd + H1_2(j)) = d;
313
}
314
} while (i & 63);
315
} while (i != 0);
316
}
317
318
-void HELPER(sve_fcmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
319
+void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
320
+ void *vg, void *status, uint32_t desc)
321
{
322
intptr_t j, i = simd_oprsz(desc);
323
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
324
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
325
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
326
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
327
- unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
328
+ unsigned rot = simd_data(desc);
329
bool flip = rot & 1;
330
float32 neg_imag, neg_real;
331
- void *vd = &env->vfp.zregs[rd];
332
- void *vn = &env->vfp.zregs[rn];
333
- void *vm = &env->vfp.zregs[rm];
334
- void *va = &env->vfp.zregs[ra];
335
uint64_t *g = vg;
336
337
neg_imag = float32_set_sign(0, (rot & 2) != 0);
338
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
339
340
if (likely((pg >> (i & 63)) & 1)) {
341
d = *(float32 *)(va + H1_2(i));
342
- d = float32_muladd(e2, e1, d, 0, &env->vfp.fp_status);
343
+ d = float32_muladd(e2, e1, d, 0, status);
344
*(float32 *)(vd + H1_2(i)) = d;
345
}
346
if (likely((pg >> (j & 63)) & 1)) {
347
d = *(float32 *)(va + H1_2(j));
348
- d = float32_muladd(e4, e3, d, 0, &env->vfp.fp_status);
349
+ d = float32_muladd(e4, e3, d, 0, status);
350
*(float32 *)(vd + H1_2(j)) = d;
351
}
352
} while (i & 63);
353
} while (i != 0);
354
}
355
356
-void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
357
+void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
358
+ void *vg, void *status, uint32_t desc)
359
{
360
intptr_t j, i = simd_oprsz(desc);
361
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
362
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
363
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
364
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
365
- unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
366
+ unsigned rot = simd_data(desc);
367
bool flip = rot & 1;
368
float64 neg_imag, neg_real;
369
- void *vd = &env->vfp.zregs[rd];
370
- void *vn = &env->vfp.zregs[rn];
371
- void *vm = &env->vfp.zregs[rm];
372
- void *va = &env->vfp.zregs[ra];
373
uint64_t *g = vg;
374
375
neg_imag = float64_set_sign(0, (rot & 2) != 0);
376
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
377
378
if (likely((pg >> (i & 63)) & 1)) {
379
d = *(float64 *)(va + H1_2(i));
380
- d = float64_muladd(e2, e1, d, 0, &env->vfp.fp_status);
381
+ d = float64_muladd(e2, e1, d, 0, status);
382
*(float64 *)(vd + H1_2(i)) = d;
383
}
384
if (likely((pg >> (j & 63)) & 1)) {
385
d = *(float64 *)(va + H1_2(j));
386
- d = float64_muladd(e4, e3, d, 0, &env->vfp.fp_status);
387
+ d = float64_muladd(e4, e3, d, 0, status);
388
*(float64 *)(vd + H1_2(j)) = d;
389
}
390
} while (i & 63);
391
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
392
index XXXXXXX..XXXXXXX 100644
393
--- a/target/arm/translate-sve.c
394
+++ b/target/arm/translate-sve.c
395
@@ -XXX,XX +XXX,XX @@ static bool trans_FCADD(DisasContext *s, arg_FCADD *a)
396
return true;
397
}
398
399
-typedef void gen_helper_sve_fmla(TCGv_env, TCGv_ptr, TCGv_i32);
400
-
401
-static bool do_fmla(DisasContext *s, arg_rprrr_esz *a, gen_helper_sve_fmla *fn)
402
+static bool do_fmla(DisasContext *s, arg_rprrr_esz *a,
403
+ gen_helper_gvec_5_ptr *fn)
404
{
405
- if (fn == NULL) {
406
+ if (a->esz == 0) {
407
return false;
408
}
409
- if (!sve_access_check(s)) {
410
- return true;
411
+ if (sve_access_check(s)) {
412
+ unsigned vsz = vec_full_reg_size(s);
413
+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
414
+ tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd),
415
+ vec_full_reg_offset(s, a->rn),
416
+ vec_full_reg_offset(s, a->rm),
417
+ vec_full_reg_offset(s, a->ra),
418
+ pred_full_reg_offset(s, a->pg),
419
+ status, vsz, vsz, 0, fn);
420
+ tcg_temp_free_ptr(status);
421
}
50
}
422
-
51
-
423
- unsigned vsz = vec_full_reg_size(s);
52
return ebf;
424
- unsigned desc;
425
- TCGv_i32 t_desc;
426
- TCGv_ptr pg = tcg_temp_new_ptr();
427
-
428
- /* We would need 7 operands to pass these arguments "properly".
429
- * So we encode all the register numbers into the descriptor.
430
- */
431
- desc = deposit32(a->rd, 5, 5, a->rn);
432
- desc = deposit32(desc, 10, 5, a->rm);
433
- desc = deposit32(desc, 15, 5, a->ra);
434
- desc = simd_desc(vsz, vsz, desc);
435
-
436
- t_desc = tcg_const_i32(desc);
437
- tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
438
- fn(cpu_env, pg, t_desc);
439
- tcg_temp_free_i32(t_desc);
440
- tcg_temp_free_ptr(pg);
441
return true;
442
}
53
}
443
54
444
#define DO_FMLA(NAME, name) \
445
static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a) \
446
{ \
447
- static gen_helper_sve_fmla * const fns[4] = { \
448
+ static gen_helper_gvec_5_ptr * const fns[4] = { \
449
NULL, gen_helper_sve_##name##_h, \
450
gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \
451
}; \
452
@@ -XXX,XX +XXX,XX @@ DO_FMLA(FNMLS_zpzzz, fnmls_zpzzz)
453
454
static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
455
{
456
- static gen_helper_sve_fmla * const fns[3] = {
457
+ static gen_helper_gvec_5_ptr * const fns[4] = {
458
+ NULL,
459
gen_helper_sve_fcmla_zpzzz_h,
460
gen_helper_sve_fcmla_zpzzz_s,
461
gen_helper_sve_fcmla_zpzzz_d,
462
@@ -XXX,XX +XXX,XX @@ static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
463
}
464
if (sve_access_check(s)) {
465
unsigned vsz = vec_full_reg_size(s);
466
- unsigned desc;
467
- TCGv_i32 t_desc;
468
- TCGv_ptr pg = tcg_temp_new_ptr();
469
-
470
- /* We would need 7 operands to pass these arguments "properly".
471
- * So we encode all the register numbers into the descriptor.
472
- */
473
- desc = deposit32(a->rd, 5, 5, a->rn);
474
- desc = deposit32(desc, 10, 5, a->rm);
475
- desc = deposit32(desc, 15, 5, a->ra);
476
- desc = deposit32(desc, 20, 2, a->rot);
477
- desc = sextract32(desc, 0, 22);
478
- desc = simd_desc(vsz, vsz, desc);
479
-
480
- t_desc = tcg_const_i32(desc);
481
- tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
482
- fns[a->esz - 1](cpu_env, pg, t_desc);
483
- tcg_temp_free_i32(t_desc);
484
- tcg_temp_free_ptr(pg);
485
+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
486
+ tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd),
487
+ vec_full_reg_offset(s, a->rn),
488
+ vec_full_reg_offset(s, a->rm),
489
+ vec_full_reg_offset(s, a->ra),
490
+ pred_full_reg_offset(s, a->pg),
491
+ status, vsz, vsz, a->rot, fns[a->esz]);
492
+ tcg_temp_free_ptr(status);
493
}
494
return true;
495
}
496
--
55
--
497
2.20.1
56
2.34.1
498
57
499
58
diff view generated by jsdifflib
[PULL 16/34] target/arm: Add sve infrastructure for page lookup
[PULL 40/72] fpu: Allow runtime choice of default NaN value
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Currently we hardcode the default NaN value in parts64_default_nan()
2
using a compile-time ifdef ladder. This is awkward for two cases:
3
* for single-QEMU-binary we can't hard-code target-specifics like this
4
* for Arm FEAT_AFP the default NaN value depends on FPCR.AH
5
(specifically the sign bit is different)
2
6
3
For contiguous predicated memory operations, we want to
7
Add a field to float_status to specify the default NaN value; fall
4
minimize the number of tlb lookups performed. We have
8
back to the old ifdef behaviour if these are not set.
5
open-coded this for sve_ld1_r, but for correctness with
6
MTE we will need this for all of the memory operations.
7
9
8
Create a structure that holds the bounds of active elements,
10
The default NaN value is specified by setting a uint8_t to a
9
and metadata for two pages. Add routines to find those
11
pattern corresponding to the sign and upper fraction parts of
10
active elements, lookup the pages, and run watchpoints
12
the NaN; the lower bits of the fraction are set from bit 0 of
11
for those pages.
13
the pattern.
12
14
13
Temporarily mark the functions unused to avoid Werror.
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20241202131347.498124-35-peter.maydell@linaro.org
18
---
19
include/fpu/softfloat-helpers.h | 11 +++++++
20
include/fpu/softfloat-types.h | 10 ++++++
21
fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++-------------
22
3 files changed, 54 insertions(+), 22 deletions(-)
14
23
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20200508154359.7494-10-richard.henderson@linaro.org
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
target/arm/sve_helper.c | 263 +++++++++++++++++++++++++++++++++++++++-
21
1 file changed, 261 insertions(+), 2 deletions(-)
22
23
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
24
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/sve_helper.c
26
--- a/include/fpu/softfloat-helpers.h
26
+++ b/target/arm/sve_helper.c
27
+++ b/include/fpu/softfloat-helpers.h
27
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_cpy_z_d)(void *vd, void *vg, uint64_t val, uint32_t desc)
28
@@ -XXX,XX +XXX,XX @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
28
}
29
status->float_infzeronan_rule = rule;
29
}
30
}
30
31
31
-/* Big-endian hosts need to frob the byte indicies. If the copy
32
+static inline void set_float_default_nan_pattern(uint8_t dnan_pattern,
32
+/* Big-endian hosts need to frob the byte indices. If the copy
33
+ float_status *status)
33
* happens to be 8-byte aligned, then no frobbing necessary.
34
*/
35
static void swap_memmove(void *vd, void *vs, size_t n)
36
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
37
/*
38
* Load elements into @vd, controlled by @vg, from @host + @mem_ofs.
39
* Memory is valid through @host + @mem_max. The register element
40
- * indicies are inferred from @mem_ofs, as modified by the types for
41
+ * indices are inferred from @mem_ofs, as modified by the types for
42
* which the helper is built. Return the @mem_ofs of the first element
43
* not loaded (which is @mem_max if they are all loaded).
44
*
45
@@ -XXX,XX +XXX,XX @@ static intptr_t max_for_page(target_ulong base, intptr_t mem_off,
46
return MIN(split, mem_max - mem_off) + mem_off;
47
}
48
49
+/*
50
+ * Resolve the guest virtual address to info->host and info->flags.
51
+ * If @nofault, return false if the page is invalid, otherwise
52
+ * exit via page fault exception.
53
+ */
54
+
55
+typedef struct {
56
+ void *host;
57
+ int flags;
58
+ MemTxAttrs attrs;
59
+} SVEHostPage;
60
+
61
+static bool sve_probe_page(SVEHostPage *info, bool nofault,
62
+ CPUARMState *env, target_ulong addr,
63
+ int mem_off, MMUAccessType access_type,
64
+ int mmu_idx, uintptr_t retaddr)
65
+{
34
+{
66
+ int flags;
35
+ status->default_nan_pattern = dnan_pattern;
67
+
68
+ addr += mem_off;
69
+ flags = probe_access_flags(env, addr, access_type, mmu_idx, nofault,
70
+ &info->host, retaddr);
71
+ info->flags = flags;
72
+
73
+ if (flags & TLB_INVALID_MASK) {
74
+ g_assert(nofault);
75
+ return false;
76
+ }
77
+
78
+ /* Ensure that info->host[] is relative to addr, not addr + mem_off. */
79
+ info->host -= mem_off;
80
+
81
+#ifdef CONFIG_USER_ONLY
82
+ memset(&info->attrs, 0, sizeof(info->attrs));
83
+#else
84
+ /*
85
+ * Find the iotlbentry for addr and return the transaction attributes.
86
+ * This *must* be present in the TLB because we just found the mapping.
87
+ */
88
+ {
89
+ uintptr_t index = tlb_index(env, mmu_idx, addr);
90
+
91
+# ifdef CONFIG_DEBUG_TCG
92
+ CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
93
+ target_ulong comparator = (access_type == MMU_DATA_LOAD
94
+ ? entry->addr_read
95
+ : tlb_addr_write(entry));
96
+ g_assert(tlb_hit(comparator, addr));
97
+# endif
98
+
99
+ CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
100
+ info->attrs = iotlbentry->attrs;
101
+ }
102
+#endif
103
+
104
+ return true;
105
+}
36
+}
106
+
37
+
107
+
38
static inline void set_flush_to_zero(bool val, float_status *status)
108
+/*
39
{
109
+ * Analyse contiguous data, protected by a governing predicate.
40
status->flush_to_zero = val;
110
+ */
41
@@ -XXX,XX +XXX,XX @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status
111
+
42
return status->float_infzeronan_rule;
112
+typedef enum {
43
}
113
+ FAULT_NO,
44
114
+ FAULT_FIRST,
45
+static inline uint8_t get_float_default_nan_pattern(float_status *status)
115
+ FAULT_ALL,
116
+} SVEContFault;
117
+
118
+typedef struct {
119
+ /*
120
+ * First and last element wholly contained within the two pages.
121
+ * mem_off_first[0] and reg_off_first[0] are always set >= 0.
122
+ * reg_off_last[0] may be < 0 if the first element crosses pages.
123
+ * All of mem_off_first[1], reg_off_first[1] and reg_off_last[1]
124
+ * are set >= 0 only if there are complete elements on a second page.
125
+ *
126
+ * The reg_off_* offsets are relative to the internal vector register.
127
+ * The mem_off_first offset is relative to the memory address; the
128
+ * two offsets are different when a load operation extends, a store
129
+ * operation truncates, or for multi-register operations.
130
+ */
131
+ int16_t mem_off_first[2];
132
+ int16_t reg_off_first[2];
133
+ int16_t reg_off_last[2];
134
+
135
+ /*
136
+ * One element that is misaligned and spans both pages,
137
+ * or -1 if there is no such active element.
138
+ */
139
+ int16_t mem_off_split;
140
+ int16_t reg_off_split;
141
+
142
+ /*
143
+ * The byte offset at which the entire operation crosses a page boundary.
144
+ * Set >= 0 if and only if the entire operation spans two pages.
145
+ */
146
+ int16_t page_split;
147
+
148
+ /* TLB data for the two pages. */
149
+ SVEHostPage page[2];
150
+} SVEContLdSt;
151
+
152
+/*
153
+ * Find first active element on each page, and a loose bound for the
154
+ * final element on each page. Identify any single element that spans
155
+ * the page boundary. Return true if there are any active elements.
156
+ */
157
+static bool __attribute__((unused))
158
+sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg,
159
+ intptr_t reg_max, int esz, int msize)
160
+{
46
+{
161
+ const int esize = 1 << esz;
47
+ return status->default_nan_pattern;
162
+ const uint64_t pg_mask = pred_esz_masks[esz];
163
+ intptr_t reg_off_first = -1, reg_off_last = -1, reg_off_split;
164
+ intptr_t mem_off_last, mem_off_split;
165
+ intptr_t page_split, elt_split;
166
+ intptr_t i;
167
+
168
+ /* Set all of the element indices to -1, and the TLB data to 0. */
169
+ memset(info, -1, offsetof(SVEContLdSt, page));
170
+ memset(info->page, 0, sizeof(info->page));
171
+
172
+ /* Gross scan over the entire predicate to find bounds. */
173
+ i = 0;
174
+ do {
175
+ uint64_t pg = vg[i] & pg_mask;
176
+ if (pg) {
177
+ reg_off_last = i * 64 + 63 - clz64(pg);
178
+ if (reg_off_first < 0) {
179
+ reg_off_first = i * 64 + ctz64(pg);
180
+ }
181
+ }
182
+ } while (++i * 64 < reg_max);
183
+
184
+ if (unlikely(reg_off_first < 0)) {
185
+ /* No active elements, no pages touched. */
186
+ return false;
187
+ }
188
+ tcg_debug_assert(reg_off_last >= 0 && reg_off_last < reg_max);
189
+
190
+ info->reg_off_first[0] = reg_off_first;
191
+ info->mem_off_first[0] = (reg_off_first >> esz) * msize;
192
+ mem_off_last = (reg_off_last >> esz) * msize;
193
+
194
+ page_split = -(addr | TARGET_PAGE_MASK);
195
+ if (likely(mem_off_last + msize <= page_split)) {
196
+ /* The entire operation fits within a single page. */
197
+ info->reg_off_last[0] = reg_off_last;
198
+ return true;
199
+ }
200
+
201
+ info->page_split = page_split;
202
+ elt_split = page_split / msize;
203
+ reg_off_split = elt_split << esz;
204
+ mem_off_split = elt_split * msize;
205
+
206
+ /*
207
+ * This is the last full element on the first page, but it is not
208
+ * necessarily active. If there is no full element, i.e. the first
209
+ * active element is the one that's split, this value remains -1.
210
+ * It is useful as iteration bounds.
211
+ */
212
+ if (elt_split != 0) {
213
+ info->reg_off_last[0] = reg_off_split - esize;
214
+ }
215
+
216
+ /* Determine if an unaligned element spans the pages. */
217
+ if (page_split % msize != 0) {
218
+ /* It is helpful to know if the split element is active. */
219
+ if ((vg[reg_off_split >> 6] >> (reg_off_split & 63)) & 1) {
220
+ info->reg_off_split = reg_off_split;
221
+ info->mem_off_split = mem_off_split;
222
+
223
+ if (reg_off_split == reg_off_last) {
224
+ /* The page crossing element is last. */
225
+ return true;
226
+ }
227
+ }
228
+ reg_off_split += esize;
229
+ mem_off_split += msize;
230
+ }
231
+
232
+ /*
233
+ * We do want the first active element on the second page, because
234
+ * this may affect the address reported in an exception.
235
+ */
236
+ reg_off_split = find_next_active(vg, reg_off_split, reg_max, esz);
237
+ tcg_debug_assert(reg_off_split <= reg_off_last);
238
+ info->reg_off_first[1] = reg_off_split;
239
+ info->mem_off_first[1] = (reg_off_split >> esz) * msize;
240
+ info->reg_off_last[1] = reg_off_last;
241
+ return true;
242
+}
48
+}
243
+
49
+
244
+/*
50
static inline bool get_flush_to_zero(float_status *status)
245
+ * Resolve the guest virtual addresses to info->page[].
51
{
246
+ * Control the generation of page faults with @fault. Return false if
52
return status->flush_to_zero;
247
+ * there is no work to do, which can only happen with @fault == FAULT_NO.
53
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
248
+ */
54
index XXXXXXX..XXXXXXX 100644
249
+static bool __attribute__((unused))
55
--- a/include/fpu/softfloat-types.h
250
+sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, CPUARMState *env,
56
+++ b/include/fpu/softfloat-types.h
251
+ target_ulong addr, MMUAccessType access_type,
57
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
252
+ uintptr_t retaddr)
58
/* should denormalised inputs go to zero and set the input_denormal flag? */
253
+{
59
bool flush_inputs_to_zero;
254
+ int mmu_idx = cpu_mmu_index(env, false);
60
bool default_nan_mode;
255
+ int mem_off = info->mem_off_first[0];
61
+ /*
256
+ bool nofault = fault == FAULT_NO;
62
+ * The pattern to use for the default NaN. Here the high bit specifies
257
+ bool have_work = true;
63
+ * the default NaN's sign bit, and bits 6..0 specify the high bits of the
64
+ * fractional part. The low bits of the fractional part are copies of bit 0.
65
+ * The exponent of the default NaN is (as for any NaN) always all 1s.
66
+ * Note that a value of 0 here is not a valid NaN. The target must set
67
+ * this to the correct non-zero value, or we will assert when trying to
68
+ * create a default NaN.
69
+ */
70
+ uint8_t default_nan_pattern;
71
/*
72
* The flags below are not used on all specializations and may
73
* constant fold away (see snan_bit_is_one()/no_signalling_nans() in
74
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
75
index XXXXXXX..XXXXXXX 100644
76
--- a/fpu/softfloat-specialize.c.inc
77
+++ b/fpu/softfloat-specialize.c.inc
78
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
79
{
80
bool sign = 0;
81
uint64_t frac;
82
+ uint8_t dnan_pattern = status->default_nan_pattern;
83
84
+ if (dnan_pattern == 0) {
85
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
86
- /* !snan_bit_is_one, set all bits */
87
- frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
88
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
89
+ /* Sign bit clear, all frac bits set */
90
+ dnan_pattern = 0b01111111;
91
+#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
92
|| defined(TARGET_MICROBLAZE)
93
- /* !snan_bit_is_one, set sign and msb */
94
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
95
- sign = 1;
96
+ /* Sign bit set, most significant frac bit set */
97
+ dnan_pattern = 0b11000000;
98
#elif defined(TARGET_HPPA)
99
- /* snan_bit_is_one, set msb-1. */
100
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
101
+ /* Sign bit clear, msb-1 frac bit set */
102
+ dnan_pattern = 0b00100000;
103
#elif defined(TARGET_HEXAGON)
104
- sign = 1;
105
- frac = ~0ULL;
106
+ /* Sign bit set, all frac bits set. */
107
+ dnan_pattern = 0b11111111;
108
#else
109
- /*
110
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
111
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
112
- * do not have floating-point.
113
- */
114
- if (snan_bit_is_one(status)) {
115
- /* set all bits other than msb */
116
- frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
117
- } else {
118
- /* set msb */
119
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
120
- }
121
+ /*
122
+ * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
123
+ * S390, SH4, TriCore, and Xtensa. Our other supported targets
124
+ * do not have floating-point.
125
+ */
126
+ if (snan_bit_is_one(status)) {
127
+ /* sign bit clear, set all frac bits other than msb */
128
+ dnan_pattern = 0b00111111;
129
+ } else {
130
+ /* sign bit clear, set frac msb */
131
+ dnan_pattern = 0b01000000;
132
+ }
133
#endif
134
+ }
135
+ assert(dnan_pattern != 0);
258
+
136
+
259
+ if (!sve_probe_page(&info->page[0], nofault, env, addr, mem_off,
137
+ sign = dnan_pattern >> 7;
260
+ access_type, mmu_idx, retaddr)) {
261
+ /* No work to be done. */
262
+ return false;
263
+ }
264
+
265
+ if (likely(info->page_split < 0)) {
266
+ /* The entire operation was on the one page. */
267
+ return true;
268
+ }
269
+
270
+ /*
138
+ /*
271
+ * If the second page is invalid, then we want the fault address to be
139
+ * Place default_nan_pattern [6:0] into bits [62:56],
272
+ * the first byte on that page which is accessed.
140
+ * and replecate bit [0] down into [55:0]
273
+ */
141
+ */
274
+ if (info->mem_off_split >= 0) {
142
+ frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern);
275
+ /*
143
+ frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1));
276
+ * There is an element split across the pages. The fault address
144
277
+ * should be the first byte of the second page.
145
*p = (FloatParts64) {
278
+ */
146
.cls = float_class_qnan,
279
+ mem_off = info->page_split;
280
+ /*
281
+ * If the split element is also the first active element
282
+ * of the vector, then: For first-fault we should continue
283
+ * to generate faults for the second page. For no-fault,
284
+ * we have work only if the second page is valid.
285
+ */
286
+ if (info->mem_off_first[0] < info->mem_off_split) {
287
+ nofault = FAULT_FIRST;
288
+ have_work = false;
289
+ }
290
+ } else {
291
+ /*
292
+ * There is no element split across the pages. The fault address
293
+ * should be the first active element on the second page.
294
+ */
295
+ mem_off = info->mem_off_first[1];
296
+ /*
297
+ * There must have been one active element on the first page,
298
+ * so we're out of first-fault territory.
299
+ */
300
+ nofault = fault != FAULT_ALL;
301
+ }
302
+
303
+ have_work |= sve_probe_page(&info->page[1], nofault, env, addr, mem_off,
304
+ access_type, mmu_idx, retaddr);
305
+ return have_work;
306
+}
307
+
308
/*
309
* The result of tlb_vaddr_to_host for user-only is just g2h(x),
310
* which is always non-null. Elide the useless test.
311
--
147
--
312
2.20.1
148
2.34.1
313
314
diff view generated by jsdifflib
New patch
[PULL 41/72] tests/fp: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the tests/fp code.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-36-peter.maydell@linaro.org
6
---
7
tests/fp/fp-bench.c | 1 +
8
tests/fp/fp-test-log2.c | 1 +
9
tests/fp/fp-test.c | 1 +
10
3 files changed, 3 insertions(+)
11
12
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tests/fp/fp-bench.c
15
+++ b/tests/fp/fp-bench.c
16
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
17
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
18
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
19
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
20
+ set_float_default_nan_pattern(0b01000000, &soft_status);
21
22
f = bench_funcs[operation][precision];
23
g_assert(f);
24
diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/tests/fp/fp-test-log2.c
27
+++ b/tests/fp/fp-test-log2.c
28
@@ -XXX,XX +XXX,XX @@ int main(int ac, char **av)
29
int i;
30
31
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
32
+ set_float_default_nan_pattern(0b01000000, &qsf);
33
set_float_rounding_mode(float_round_nearest_even, &qsf);
34
35
test.d = 0.0;
36
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/tests/fp/fp-test.c
39
+++ b/tests/fp/fp-test.c
40
@@ -XXX,XX +XXX,XX @@ void run_test(void)
41
*/
42
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
43
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
44
+ set_float_default_nan_pattern(0b01000000, &qsf);
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
46
47
genCases_setLevel(test_level);
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 42/72] target/microblaze: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-37-peter.maydell@linaro.org
7
---
8
target/microblaze/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/microblaze/cpu.c
15
+++ b/target/microblaze/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj, ResetType type)
17
* this architecture.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
23
#if defined(CONFIG_USER_ONLY)
24
/* start in user mode with interrupts enabled. */
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
34
- || defined(TARGET_MICROBLAZE)
35
+#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
/* Sign bit set, most significant frac bit set */
37
dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 43/72] target/i386: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-38-peter.maydell@linaro.org
7
---
8
target/i386/tcg/fpu_helper.c | 4 ++++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 4 insertions(+), 3 deletions(-)
11
12
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/i386/tcg/fpu_helper.c
15
+++ b/target/i386/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
17
*/
18
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
19
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
+ set_float_default_nan_pattern(0b11000000, &env->mmx_status);
23
+ set_float_default_nan_pattern(0b11000000, &env->sse_status);
24
}
25
26
static inline uint8_t save_exception_flags(CPUX86State *env)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
32
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
/* Sign bit clear, all frac bits set */
34
dnan_pattern = 0b01111111;
35
-#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
- /* Sign bit set, most significant frac bit set */
37
- dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
/* Sign bit clear, msb-1 frac bit set */
40
dnan_pattern = 0b00100000;
41
--
42
2.34.1
diff view generated by jsdifflib
New patch
[PULL 44/72] target/hppa: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-39-peter.maydell@linaro.org
7
---
8
target/hppa/fpu_helper.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 2 insertions(+), 3 deletions(-)
11
12
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/hppa/fpu_helper.c
15
+++ b/target/hppa/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
17
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN: sign bit clear, msb-1 frac bit set */
21
+ set_float_default_nan_pattern(0b00100000, &env->fp_status);
22
}
23
24
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_HPPA)
34
- /* Sign bit clear, msb-1 frac bit set */
35
- dnan_pattern = 0b00100000;
36
#elif defined(TARGET_HEXAGON)
37
/* Sign bit set, all frac bits set. */
38
dnan_pattern = 0b11111111;
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 45/72] target/alpha: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the alpha target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-40-peter.maydell@linaro.org
6
---
7
target/alpha/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/alpha/cpu.c
13
+++ b/target/alpha/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj)
15
* operand in Fa. That is float_2nan_prop_ba.
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
18
+ /* Default NaN: sign bit clear, msb frac bit set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
#if defined(CONFIG_USER_ONLY)
21
env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
22
cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD
23
--
24
2.34.1
diff view generated by jsdifflib
[PULL 28/34] target/arm: Make set_feature() available for other files
[PULL 46/72] target/arm: Set default NaN pattern explicitly
1
From: Thomas Huth <thuth@redhat.com>
1
Set the default NaN pattern explicitly for the arm target.
2
This includes setting it for the old linux-user nwfpe emulation.
3
For nwfpe, our default doesn't match the real kernel, but we
4
avoid making a behaviour change in this commit.
2
5
3
Move the common set_feature() and unset_feature() functions
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
from cpu.c and cpu64.c to cpu.h.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-41-peter.maydell@linaro.org
9
---
10
linux-user/arm/nwfpe/fpa11.c | 5 +++++
11
target/arm/cpu.c | 2 ++
12
2 files changed, 7 insertions(+)
5
13
6
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
14
diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c
7
Signed-off-by: Thomas Huth <thuth@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20200504172448.9402-3-philmd@redhat.com
12
Message-ID: <20190921150420.30743-2-thuth@redhat.com>
13
[PMD: Split Thomas's patch in two: set_feature, cpu_register]
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/cpu.h | 10 ++++++++++
18
target/arm/cpu.c | 10 ----------
19
target/arm/cpu64.c | 10 ----------
20
3 files changed, 10 insertions(+), 20 deletions(-)
21
22
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
23
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/cpu.h
16
--- a/linux-user/arm/nwfpe/fpa11.c
25
+++ b/target/arm/cpu.h
17
+++ b/linux-user/arm/nwfpe/fpa11.c
26
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
18
@@ -XXX,XX +XXX,XX @@ void resetFPA11(void)
27
void *gicv3state;
19
* this late date.
28
} CPUARMState;
20
*/
29
21
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status);
30
+static inline void set_feature(CPUARMState *env, int feature)
22
+ /*
31
+{
23
+ * Use the same default NaN value as Arm VFP. This doesn't match
32
+ env->features |= 1ULL << feature;
24
+ * the Linux kernel's nwfpe emulation, which uses an all-1s value.
33
+}
25
+ */
34
+
26
+ set_float_default_nan_pattern(0b01000000, &fpa11->fp_status);
35
+static inline void unset_feature(CPUARMState *env, int feature)
27
}
36
+{
28
37
+ env->features &= ~(1ULL << feature);
29
void SetRoundingMode(const unsigned int opcode)
38
+}
39
+
40
/**
41
* ARMELChangeHookFn:
42
* type of a function which can be registered via arm_register_el_change_hook()
43
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
30
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
44
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/cpu.c
32
--- a/target/arm/cpu.c
46
+++ b/target/arm/cpu.c
33
+++ b/target/arm/cpu.c
47
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
34
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
48
35
* the pseudocode function the arguments are in the order c, a, b.
49
#endif
36
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
50
37
* and the input NaN if it is signalling
51
-static inline void set_feature(CPUARMState *env, int feature)
38
+ * * Default NaN has sign bit clear, msb frac bit set
52
-{
39
*/
53
- env->features |= 1ULL << feature;
40
static void arm_set_default_fp_behaviours(float_status *s)
54
-}
55
-
56
-static inline void unset_feature(CPUARMState *env, int feature)
57
-{
58
- env->features &= ~(1ULL << feature);
59
-}
60
-
61
static int
62
print_insn_thumb1(bfd_vma pc, disassemble_info *info)
63
{
41
{
64
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
42
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
65
index XXXXXXX..XXXXXXX 100644
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
66
--- a/target/arm/cpu64.c
44
set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
67
+++ b/target/arm/cpu64.c
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
68
@@ -XXX,XX +XXX,XX @@
46
+ set_float_default_nan_pattern(0b01000000, s);
69
#include "kvm_arm.h"
47
}
70
#include "qapi/visitor.h"
48
71
49
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
72
-static inline void set_feature(CPUARMState *env, int feature)
73
-{
74
- env->features |= 1ULL << feature;
75
-}
76
-
77
-static inline void unset_feature(CPUARMState *env, int feature)
78
-{
79
- env->features &= ~(1ULL << feature);
80
-}
81
-
82
#ifndef CONFIG_USER_ONLY
83
static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
84
{
85
--
50
--
86
2.20.1
51
2.34.1
87
88
diff view generated by jsdifflib
New patch
[PULL 47/72] target/loongarch: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for loongarch.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-42-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/loongarch/tcg/fpu_helper.c
13
+++ b/target/loongarch/tcg/fpu_helper.c
14
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
15
*/
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
17
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
18
+ /* Default NaN: sign bit clear, msb frac bit set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
}
21
22
int ieee_ex_to_loongarch(int xcpt)
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 48/72] target/m68k: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for m68k.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-43-peter.maydell@linaro.org
6
---
7
target/m68k/cpu.c | 2 ++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 3 insertions(+), 1 deletion(-)
10
11
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/m68k/cpu.c
14
+++ b/target/m68k/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
16
* preceding paragraph for nonsignaling NaNs.
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
+ /* Default NaN: sign bit clear, all frac bits set */
20
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
21
22
nan = floatx80_default_nan(&env->fp_status);
23
for (i = 0; i < 8; i++) {
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
29
uint8_t dnan_pattern = status->default_nan_pattern;
30
31
if (dnan_pattern == 0) {
32
-#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
+#if defined(TARGET_SPARC)
34
/* Sign bit clear, all frac bits set */
35
dnan_pattern = 0b01111111;
36
#elif defined(TARGET_HEXAGON)
37
--
38
2.34.1
diff view generated by jsdifflib
[PULL 24/34] target/arm: Reuse sve_probe_page for scatter stores
[PULL 49/72] target/mips: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for MIPS. Note that this
2
is our only target which currently changes the default NaN
3
at runtime (which it was previously doing indirectly when it
4
changed the snan_bit_is_one setting).
2
5
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200508154359.7494-18-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-44-peter.maydell@linaro.org
7
---
9
---
8
target/arm/sve_helper.c | 182 ++++++++++++++++++++++++----------------
10
target/mips/fpu_helper.h | 7 +++++++
9
1 file changed, 111 insertions(+), 71 deletions(-)
11
target/mips/msa.c | 3 +++
12
2 files changed, 10 insertions(+)
10
13
11
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
14
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/sve_helper.c
16
--- a/target/mips/fpu_helper.h
14
+++ b/target/arm/sve_helper.c
17
+++ b/target/mips/fpu_helper.h
15
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_ZPZ_D(dd_be, zd, MO_64)
18
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
16
19
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
17
/* Stores with a vector index. */
20
nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
18
21
set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
19
-static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
20
- target_ulong base, uint32_t desc, uintptr_t ra,
21
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
22
+static inline QEMU_ALWAYS_INLINE
23
+void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
24
+ target_ulong base, uint32_t desc, uintptr_t retaddr,
25
+ int esize, int msize, zreg_off_fn *off_fn,
26
+ sve_ldst1_host_fn *host_fn,
27
+ sve_ldst1_tlb_fn *tlb_fn)
28
{
29
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
30
- intptr_t i, oprsz = simd_oprsz(desc);
31
+ const int mmu_idx = cpu_mmu_index(env, false);
32
+ const intptr_t reg_max = simd_oprsz(desc);
33
+ void *host[ARM_MAX_VQ * 4];
34
+ intptr_t reg_off, i;
35
+ SVEHostPage info, info2;
36
37
- for (i = 0; i < oprsz; ) {
38
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
39
+ /*
22
+ /*
40
+ * Probe all of the elements for host addresses and flags.
23
+ * With nan2008, the default NaN value has the sign bit clear and the
24
+ * frac msb set; with the older mode, the sign bit is clear, and all
25
+ * frac bits except the msb are set.
41
+ */
26
+ */
42
+ i = reg_off = 0;
27
+ set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111,
43
+ do {
28
+ &env->active_fpu.fp_status);
44
+ uint64_t pg = vg[reg_off >> 6];
29
45
do {
46
- if (likely(pg & 1)) {
47
- target_ulong off = off_fn(vm, i);
48
- tlb_fn(env, vd, i, base + (off << scale), ra);
49
+ target_ulong addr = base + (off_fn(vm, reg_off) << scale);
50
+ target_ulong in_page = -(addr | TARGET_PAGE_MASK);
51
+
52
+ host[i] = NULL;
53
+ if (likely((pg >> (reg_off & 63)) & 1)) {
54
+ if (likely(in_page >= msize)) {
55
+ sve_probe_page(&info, false, env, addr, 0, MMU_DATA_STORE,
56
+ mmu_idx, retaddr);
57
+ host[i] = info.host;
58
+ } else {
59
+ /*
60
+ * Element crosses the page boundary.
61
+ * Probe both pages, but do not record the host address,
62
+ * so that we use the slow path.
63
+ */
64
+ sve_probe_page(&info, false, env, addr, 0,
65
+ MMU_DATA_STORE, mmu_idx, retaddr);
66
+ sve_probe_page(&info2, false, env, addr + in_page, 0,
67
+ MMU_DATA_STORE, mmu_idx, retaddr);
68
+ info.flags |= info2.flags;
69
+ }
70
+
71
+ if (unlikely(info.flags & TLB_WATCHPOINT)) {
72
+ cpu_check_watchpoint(env_cpu(env), addr, msize,
73
+ info.attrs, BP_MEM_WRITE, retaddr);
74
+ }
75
+ /* TODO: MTE check. */
76
}
77
- i += 4, pg >>= 4;
78
- } while (i & 15);
79
- }
80
-}
81
+ i += 1;
82
+ reg_off += esize;
83
+ } while (reg_off & 63);
84
+ } while (reg_off < reg_max);
85
86
-static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
87
- target_ulong base, uint32_t desc, uintptr_t ra,
88
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
89
-{
90
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
91
- intptr_t i, oprsz = simd_oprsz(desc) / 8;
92
-
93
- for (i = 0; i < oprsz; i++) {
94
- uint8_t pg = *(uint8_t *)(vg + H1(i));
95
- if (likely(pg & 1)) {
96
- target_ulong off = off_fn(vm, i * 8);
97
- tlb_fn(env, vd, i * 8, base + (off << scale), ra);
98
+ /*
99
+ * Now that we have recognized all exceptions except SyncExternal
100
+ * (from TLB_MMIO), which we cannot avoid, perform all of the stores.
101
+ *
102
+ * Note for the common case of an element in RAM, not crossing a page
103
+ * boundary, we have stored the host address in host[]. This doubles
104
+ * as a first-level check against the predicate, since only enabled
105
+ * elements have non-null host addresses.
106
+ */
107
+ i = reg_off = 0;
108
+ do {
109
+ void *h = host[i];
110
+ if (likely(h != NULL)) {
111
+ host_fn(vd, reg_off, h);
112
+ } else if ((vg[reg_off >> 6] >> (reg_off & 63)) & 1) {
113
+ target_ulong addr = base + (off_fn(vm, reg_off) << scale);
114
+ tlb_fn(env, vd, reg_off, addr, retaddr);
115
}
116
- }
117
+ i += 1;
118
+ reg_off += esize;
119
+ } while (reg_off < reg_max);
120
}
30
}
121
31
122
-#define DO_ST1_ZPZ_S(MEM, OFS) \
32
diff --git a/target/mips/msa.c b/target/mips/msa.c
123
-void QEMU_FLATTEN HELPER(sve_st##MEM##_##OFS) \
33
index XXXXXXX..XXXXXXX 100644
124
- (CPUARMState *env, void *vd, void *vg, void *vm, \
34
--- a/target/mips/msa.c
125
- target_ulong base, uint32_t desc) \
35
+++ b/target/mips/msa.c
126
-{ \
36
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
127
- sve_st1_zs(env, vd, vg, vm, base, desc, GETPC(), \
37
/* Inf * 0 + NaN returns the input NaN */
128
- off_##OFS##_s, sve_st1##MEM##_tlb); \
38
set_float_infzeronan_rule(float_infzeronan_dnan_never,
129
+#define DO_ST1_ZPZ_S(MEM, OFS, MSZ) \
39
&env->active_tc.msa_fp_status);
130
+void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
40
+ /* Default NaN: sign bit clear, frac msb set */
131
+ void *vm, target_ulong base, uint32_t desc) \
41
+ set_float_default_nan_pattern(0b01000000,
132
+{ \
42
+ &env->active_tc.msa_fp_status);
133
+ sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, \
134
+ off_##OFS##_s, sve_st1##MEM##_host, sve_st1##MEM##_tlb); \
135
}
43
}
136
137
-#define DO_ST1_ZPZ_D(MEM, OFS) \
138
-void QEMU_FLATTEN HELPER(sve_st##MEM##_##OFS) \
139
- (CPUARMState *env, void *vd, void *vg, void *vm, \
140
- target_ulong base, uint32_t desc) \
141
-{ \
142
- sve_st1_zd(env, vd, vg, vm, base, desc, GETPC(), \
143
- off_##OFS##_d, sve_st1##MEM##_tlb); \
144
+#define DO_ST1_ZPZ_D(MEM, OFS, MSZ) \
145
+void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
146
+ void *vm, target_ulong base, uint32_t desc) \
147
+{ \
148
+ sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, \
149
+ off_##OFS##_d, sve_st1##MEM##_host, sve_st1##MEM##_tlb); \
150
}
151
152
-DO_ST1_ZPZ_S(bs, zsu)
153
-DO_ST1_ZPZ_S(hs_le, zsu)
154
-DO_ST1_ZPZ_S(hs_be, zsu)
155
-DO_ST1_ZPZ_S(ss_le, zsu)
156
-DO_ST1_ZPZ_S(ss_be, zsu)
157
+DO_ST1_ZPZ_S(bs, zsu, MO_8)
158
+DO_ST1_ZPZ_S(hs_le, zsu, MO_16)
159
+DO_ST1_ZPZ_S(hs_be, zsu, MO_16)
160
+DO_ST1_ZPZ_S(ss_le, zsu, MO_32)
161
+DO_ST1_ZPZ_S(ss_be, zsu, MO_32)
162
163
-DO_ST1_ZPZ_S(bs, zss)
164
-DO_ST1_ZPZ_S(hs_le, zss)
165
-DO_ST1_ZPZ_S(hs_be, zss)
166
-DO_ST1_ZPZ_S(ss_le, zss)
167
-DO_ST1_ZPZ_S(ss_be, zss)
168
+DO_ST1_ZPZ_S(bs, zss, MO_8)
169
+DO_ST1_ZPZ_S(hs_le, zss, MO_16)
170
+DO_ST1_ZPZ_S(hs_be, zss, MO_16)
171
+DO_ST1_ZPZ_S(ss_le, zss, MO_32)
172
+DO_ST1_ZPZ_S(ss_be, zss, MO_32)
173
174
-DO_ST1_ZPZ_D(bd, zsu)
175
-DO_ST1_ZPZ_D(hd_le, zsu)
176
-DO_ST1_ZPZ_D(hd_be, zsu)
177
-DO_ST1_ZPZ_D(sd_le, zsu)
178
-DO_ST1_ZPZ_D(sd_be, zsu)
179
-DO_ST1_ZPZ_D(dd_le, zsu)
180
-DO_ST1_ZPZ_D(dd_be, zsu)
181
+DO_ST1_ZPZ_D(bd, zsu, MO_8)
182
+DO_ST1_ZPZ_D(hd_le, zsu, MO_16)
183
+DO_ST1_ZPZ_D(hd_be, zsu, MO_16)
184
+DO_ST1_ZPZ_D(sd_le, zsu, MO_32)
185
+DO_ST1_ZPZ_D(sd_be, zsu, MO_32)
186
+DO_ST1_ZPZ_D(dd_le, zsu, MO_64)
187
+DO_ST1_ZPZ_D(dd_be, zsu, MO_64)
188
189
-DO_ST1_ZPZ_D(bd, zss)
190
-DO_ST1_ZPZ_D(hd_le, zss)
191
-DO_ST1_ZPZ_D(hd_be, zss)
192
-DO_ST1_ZPZ_D(sd_le, zss)
193
-DO_ST1_ZPZ_D(sd_be, zss)
194
-DO_ST1_ZPZ_D(dd_le, zss)
195
-DO_ST1_ZPZ_D(dd_be, zss)
196
+DO_ST1_ZPZ_D(bd, zss, MO_8)
197
+DO_ST1_ZPZ_D(hd_le, zss, MO_16)
198
+DO_ST1_ZPZ_D(hd_be, zss, MO_16)
199
+DO_ST1_ZPZ_D(sd_le, zss, MO_32)
200
+DO_ST1_ZPZ_D(sd_be, zss, MO_32)
201
+DO_ST1_ZPZ_D(dd_le, zss, MO_64)
202
+DO_ST1_ZPZ_D(dd_be, zss, MO_64)
203
204
-DO_ST1_ZPZ_D(bd, zd)
205
-DO_ST1_ZPZ_D(hd_le, zd)
206
-DO_ST1_ZPZ_D(hd_be, zd)
207
-DO_ST1_ZPZ_D(sd_le, zd)
208
-DO_ST1_ZPZ_D(sd_be, zd)
209
-DO_ST1_ZPZ_D(dd_le, zd)
210
-DO_ST1_ZPZ_D(dd_be, zd)
211
+DO_ST1_ZPZ_D(bd, zd, MO_8)
212
+DO_ST1_ZPZ_D(hd_le, zd, MO_16)
213
+DO_ST1_ZPZ_D(hd_be, zd, MO_16)
214
+DO_ST1_ZPZ_D(sd_le, zd, MO_32)
215
+DO_ST1_ZPZ_D(sd_be, zd, MO_32)
216
+DO_ST1_ZPZ_D(dd_le, zd, MO_64)
217
+DO_ST1_ZPZ_D(dd_be, zd, MO_64)
218
219
#undef DO_ST1_ZPZ_S
220
#undef DO_ST1_ZPZ_D
221
--
44
--
222
2.20.1
45
2.34.1
223
224
diff view generated by jsdifflib
New patch
[PULL 50/72] target/openrisc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for openrisc.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-45-peter.maydell@linaro.org
6
---
7
target/openrisc/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/openrisc/cpu.c
13
+++ b/target/openrisc/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type)
15
*/
16
set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status);
17
18
+ /* Default NaN: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status);
20
21
#ifndef CONFIG_USER_ONLY
22
cpu->env.picmr = 0x00000000;
23
--
24
2.34.1
diff view generated by jsdifflib
[PULL 10/34] accel/tcg: Add block comment for probe_access
[PULL 51/72] target/ppc: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for ppc.
2
2
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200508154359.7494-4-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-46-peter.maydell@linaro.org
7
---
6
---
8
include/exec/exec-all.h | 17 +++++++++++++++++
7
target/ppc/cpu_init.c | 4 ++++
9
1 file changed, 17 insertions(+)
8
1 file changed, 4 insertions(+)
10
9
11
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
10
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/include/exec/exec-all.h
12
--- a/target/ppc/cpu_init.c
14
+++ b/include/exec/exec-all.h
13
+++ b/target/ppc/cpu_init.c
15
@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
14
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
16
{
15
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
17
}
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
18
#endif
17
19
+/**
18
+ /* Default NaN: sign bit clear, set frac msb */
20
+ * probe_access:
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
21
+ * @env: CPUArchState
20
+ set_float_default_nan_pattern(0b01000000, &env->vec_status);
22
+ * @addr: guest virtual address to look up
21
+
23
+ * @size: size of the access
22
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
24
+ * @access_type: read, write or execute permission
23
ppc_spr_t *spr = &env->spr_cb[i];
25
+ * @mmu_idx: MMU index to use for lookup
26
+ * @retaddr: return address for unwinding
27
+ *
28
+ * Look up the guest virtual address @addr. Raise an exception if the
29
+ * page does not satisfy @access_type. Raise an exception if the
30
+ * access (@addr, @size) hits a watchpoint. For writes, mark a clean
31
+ * page as dirty.
32
+ *
33
+ * Finally, return the host address for a page that is backed by RAM,
34
+ * or NULL if the page requires I/O.
35
+ */
36
void *probe_access(CPUArchState *env, target_ulong addr, int size,
37
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
38
24
39
--
25
--
40
2.20.1
26
2.34.1
41
42
diff view generated by jsdifflib
[PULL 14/34] target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn
[PULL 52/72] target/sh4: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for sh4. Note that sh4
2
is one of the only three targets (the others being HPPA and
3
sometimes MIPS) that has snan_bit_is_one set.
2
4
3
Use the "normal" memory access functions, rather than the
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
softmmu internal helper functions directly.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-47-peter.maydell@linaro.org
8
---
9
target/sh4/cpu.c | 2 ++
10
1 file changed, 2 insertions(+)
5
11
6
Since fb901c905dc3, cpu_mem_index is now a simple extract
12
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
7
from env->hflags and not a large computation. Which means
8
that it's now more work to pass around this value than it
9
is to recompute it.
10
11
This only adjusts the primitives, and does not clean up
12
all of the uses within sve_helper.c.
13
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 20200508154359.7494-8-richard.henderson@linaro.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
target/arm/sve_helper.c | 221 ++++++++++++++++------------------------
20
1 file changed, 86 insertions(+), 135 deletions(-)
21
22
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
23
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/sve_helper.c
14
--- a/target/sh4/cpu.c
25
+++ b/target/arm/sve_helper.c
15
+++ b/target/sh4/cpu.c
26
@@ -XXX,XX +XXX,XX @@ typedef intptr_t sve_ld1_host_fn(void *vd, void *vg, void *host,
16
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
27
* Load one element into @vd + @reg_off from (@env, @vaddr, @ra).
17
set_flush_to_zero(1, &env->fp_status);
28
* The controlling predicate is known to be true.
18
#endif
29
*/
19
set_default_nan_mode(1, &env->fp_status);
30
-typedef void sve_ld1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
20
+ /* sign bit clear, set all frac bits other than msb */
31
- target_ulong vaddr, TCGMemOpIdx oi, uintptr_t ra);
21
+ set_float_default_nan_pattern(0b00111111, &env->fp_status);
32
-typedef sve_ld1_tlb_fn sve_st1_tlb_fn;
33
+typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
34
+ target_ulong vaddr, uintptr_t retaddr);
35
36
/*
37
* Generate the above primitives.
38
@@ -XXX,XX +XXX,XX @@ static intptr_t sve_##NAME##_host(void *vd, void *vg, void *host, \
39
return mem_off; \
40
}
22
}
41
23
42
-#ifdef CONFIG_SOFTMMU
24
static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
43
-#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, HOST, MOEND, TLB) \
44
+#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \
45
static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
46
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
47
+ target_ulong addr, uintptr_t ra) \
48
{ \
49
- TYPEM val = TLB(env, addr, oi, ra); \
50
- *(TYPEE *)(vd + H(reg_off)) = val; \
51
+ *(TYPEE *)(vd + H(reg_off)) = (TYPEM)TLB(env, addr, ra); \
52
}
53
-#else
54
-#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, HOST, MOEND, TLB) \
55
+
56
+#define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \
57
static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
58
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
59
+ target_ulong addr, uintptr_t ra) \
60
{ \
61
- TYPEM val = HOST(g2h(addr)); \
62
- *(TYPEE *)(vd + H(reg_off)) = val; \
63
+ TLB(env, addr, (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); \
64
}
65
-#endif
66
67
#define DO_LD_PRIM_1(NAME, H, TE, TM) \
68
DO_LD_HOST(NAME, H, TE, TM, ldub_p) \
69
- DO_LD_TLB(NAME, H, TE, TM, ldub_p, 0, helper_ret_ldub_mmu)
70
+ DO_LD_TLB(NAME, H, TE, TM, cpu_ldub_data_ra)
71
72
DO_LD_PRIM_1(ld1bb, H1, uint8_t, uint8_t)
73
DO_LD_PRIM_1(ld1bhu, H1_2, uint16_t, uint8_t)
74
@@ -XXX,XX +XXX,XX @@ DO_LD_PRIM_1(ld1bss, H1_4, uint32_t, int8_t)
75
DO_LD_PRIM_1(ld1bdu, , uint64_t, uint8_t)
76
DO_LD_PRIM_1(ld1bds, , uint64_t, int8_t)
77
78
-#define DO_LD_PRIM_2(NAME, end, MOEND, H, TE, TM, PH, PT) \
79
- DO_LD_HOST(NAME##_##end, H, TE, TM, PH##_##end##_p) \
80
- DO_LD_TLB(NAME##_##end, H, TE, TM, PH##_##end##_p, \
81
- MOEND, helper_##end##_##PT##_mmu)
82
+#define DO_ST_PRIM_1(NAME, H, TE, TM) \
83
+ DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra)
84
85
-DO_LD_PRIM_2(ld1hh, le, MO_LE, H1_2, uint16_t, uint16_t, lduw, lduw)
86
-DO_LD_PRIM_2(ld1hsu, le, MO_LE, H1_4, uint32_t, uint16_t, lduw, lduw)
87
-DO_LD_PRIM_2(ld1hss, le, MO_LE, H1_4, uint32_t, int16_t, lduw, lduw)
88
-DO_LD_PRIM_2(ld1hdu, le, MO_LE, , uint64_t, uint16_t, lduw, lduw)
89
-DO_LD_PRIM_2(ld1hds, le, MO_LE, , uint64_t, int16_t, lduw, lduw)
90
+DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t)
91
+DO_ST_PRIM_1(bh, H1_2, uint16_t, uint8_t)
92
+DO_ST_PRIM_1(bs, H1_4, uint32_t, uint8_t)
93
+DO_ST_PRIM_1(bd, , uint64_t, uint8_t)
94
95
-DO_LD_PRIM_2(ld1ss, le, MO_LE, H1_4, uint32_t, uint32_t, ldl, ldul)
96
-DO_LD_PRIM_2(ld1sdu, le, MO_LE, , uint64_t, uint32_t, ldl, ldul)
97
-DO_LD_PRIM_2(ld1sds, le, MO_LE, , uint64_t, int32_t, ldl, ldul)
98
+#define DO_LD_PRIM_2(NAME, H, TE, TM, LD) \
99
+ DO_LD_HOST(ld1##NAME##_be, H, TE, TM, LD##_be_p) \
100
+ DO_LD_HOST(ld1##NAME##_le, H, TE, TM, LD##_le_p) \
101
+ DO_LD_TLB(ld1##NAME##_be, H, TE, TM, cpu_##LD##_be_data_ra) \
102
+ DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra)
103
104
-DO_LD_PRIM_2(ld1dd, le, MO_LE, , uint64_t, uint64_t, ldq, ldq)
105
+#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \
106
+ DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \
107
+ DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra)
108
109
-DO_LD_PRIM_2(ld1hh, be, MO_BE, H1_2, uint16_t, uint16_t, lduw, lduw)
110
-DO_LD_PRIM_2(ld1hsu, be, MO_BE, H1_4, uint32_t, uint16_t, lduw, lduw)
111
-DO_LD_PRIM_2(ld1hss, be, MO_BE, H1_4, uint32_t, int16_t, lduw, lduw)
112
-DO_LD_PRIM_2(ld1hdu, be, MO_BE, , uint64_t, uint16_t, lduw, lduw)
113
-DO_LD_PRIM_2(ld1hds, be, MO_BE, , uint64_t, int16_t, lduw, lduw)
114
+DO_LD_PRIM_2(hh, H1_2, uint16_t, uint16_t, lduw)
115
+DO_LD_PRIM_2(hsu, H1_4, uint32_t, uint16_t, lduw)
116
+DO_LD_PRIM_2(hss, H1_4, uint32_t, int16_t, lduw)
117
+DO_LD_PRIM_2(hdu, , uint64_t, uint16_t, lduw)
118
+DO_LD_PRIM_2(hds, , uint64_t, int16_t, lduw)
119
120
-DO_LD_PRIM_2(ld1ss, be, MO_BE, H1_4, uint32_t, uint32_t, ldl, ldul)
121
-DO_LD_PRIM_2(ld1sdu, be, MO_BE, , uint64_t, uint32_t, ldl, ldul)
122
-DO_LD_PRIM_2(ld1sds, be, MO_BE, , uint64_t, int32_t, ldl, ldul)
123
+DO_ST_PRIM_2(hh, H1_2, uint16_t, uint16_t, stw)
124
+DO_ST_PRIM_2(hs, H1_4, uint32_t, uint16_t, stw)
125
+DO_ST_PRIM_2(hd, , uint64_t, uint16_t, stw)
126
127
-DO_LD_PRIM_2(ld1dd, be, MO_BE, , uint64_t, uint64_t, ldq, ldq)
128
+DO_LD_PRIM_2(ss, H1_4, uint32_t, uint32_t, ldl)
129
+DO_LD_PRIM_2(sdu, , uint64_t, uint32_t, ldl)
130
+DO_LD_PRIM_2(sds, , uint64_t, int32_t, ldl)
131
+
132
+DO_ST_PRIM_2(ss, H1_4, uint32_t, uint32_t, stl)
133
+DO_ST_PRIM_2(sd, , uint64_t, uint32_t, stl)
134
+
135
+DO_LD_PRIM_2(dd, , uint64_t, uint64_t, ldq)
136
+DO_ST_PRIM_2(dd, , uint64_t, uint64_t, stq)
137
138
#undef DO_LD_TLB
139
+#undef DO_ST_TLB
140
#undef DO_LD_HOST
141
#undef DO_LD_PRIM_1
142
+#undef DO_ST_PRIM_1
143
#undef DO_LD_PRIM_2
144
+#undef DO_ST_PRIM_2
145
146
/*
147
* Skip through a sequence of inactive elements in the guarding predicate @vg,
148
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
149
uint32_t desc, const uintptr_t retaddr,
150
const int esz, const int msz,
151
sve_ld1_host_fn *host_fn,
152
- sve_ld1_tlb_fn *tlb_fn)
153
+ sve_ldst1_tlb_fn *tlb_fn)
154
{
155
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
156
const int mmu_idx = get_mmuidx(oi);
157
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
158
* on I/O memory, it may succeed but not bring in the TLB entry.
159
* But even then we have still made forward progress.
160
*/
161
- tlb_fn(env, &scratch, reg_off, addr + mem_off, oi, retaddr);
162
+ tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
163
reg_off += 1 << esz;
164
}
165
#endif
166
@@ -XXX,XX +XXX,XX @@ DO_LD1_2(ld1dd, 3, 3)
167
*/
168
static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
169
uint32_t desc, int size, uintptr_t ra,
170
- sve_ld1_tlb_fn *tlb_fn)
171
+ sve_ldst1_tlb_fn *tlb_fn)
172
{
173
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
174
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
175
intptr_t i, oprsz = simd_oprsz(desc);
176
ARMVectorReg scratch[2] = { };
177
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
178
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
179
do {
180
if (pg & 1) {
181
- tlb_fn(env, &scratch[0], i, addr, oi, ra);
182
- tlb_fn(env, &scratch[1], i, addr + size, oi, ra);
183
+ tlb_fn(env, &scratch[0], i, addr, ra);
184
+ tlb_fn(env, &scratch[1], i, addr + size, ra);
185
}
186
i += size, pg >>= size;
187
addr += 2 * size;
188
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
189
190
static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
191
uint32_t desc, int size, uintptr_t ra,
192
- sve_ld1_tlb_fn *tlb_fn)
193
+ sve_ldst1_tlb_fn *tlb_fn)
194
{
195
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
196
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
197
intptr_t i, oprsz = simd_oprsz(desc);
198
ARMVectorReg scratch[3] = { };
199
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
200
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
201
do {
202
if (pg & 1) {
203
- tlb_fn(env, &scratch[0], i, addr, oi, ra);
204
- tlb_fn(env, &scratch[1], i, addr + size, oi, ra);
205
- tlb_fn(env, &scratch[2], i, addr + 2 * size, oi, ra);
206
+ tlb_fn(env, &scratch[0], i, addr, ra);
207
+ tlb_fn(env, &scratch[1], i, addr + size, ra);
208
+ tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
209
}
210
i += size, pg >>= size;
211
addr += 3 * size;
212
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
213
214
static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
215
uint32_t desc, int size, uintptr_t ra,
216
- sve_ld1_tlb_fn *tlb_fn)
217
+ sve_ldst1_tlb_fn *tlb_fn)
218
{
219
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
220
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
221
intptr_t i, oprsz = simd_oprsz(desc);
222
ARMVectorReg scratch[4] = { };
223
@@ -XXX,XX +XXX,XX @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
224
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
225
do {
226
if (pg & 1) {
227
- tlb_fn(env, &scratch[0], i, addr, oi, ra);
228
- tlb_fn(env, &scratch[1], i, addr + size, oi, ra);
229
- tlb_fn(env, &scratch[2], i, addr + 2 * size, oi, ra);
230
- tlb_fn(env, &scratch[3], i, addr + 3 * size, oi, ra);
231
+ tlb_fn(env, &scratch[0], i, addr, ra);
232
+ tlb_fn(env, &scratch[1], i, addr + size, ra);
233
+ tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
234
+ tlb_fn(env, &scratch[3], i, addr + 3 * size, ra);
235
}
236
i += size, pg >>= size;
237
addr += 4 * size;
238
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
239
uint32_t desc, const uintptr_t retaddr,
240
const int esz, const int msz,
241
sve_ld1_host_fn *host_fn,
242
- sve_ld1_tlb_fn *tlb_fn)
243
+ sve_ldst1_tlb_fn *tlb_fn)
244
{
245
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
246
const int mmu_idx = get_mmuidx(oi);
247
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
248
* Perform one normal read, which will fault or not.
249
* But it is likely to bring the page into the tlb.
250
*/
251
- tlb_fn(env, vd, reg_off, addr + mem_off, oi, retaddr);
252
+ tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
253
254
/* After any fault, zero any leading predicated false elts. */
255
swap_memzero(vd, reg_off);
256
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_LDNF1_2(dd, 3, 3)
257
#undef DO_LDFF1_LDNF1_1
258
#undef DO_LDFF1_LDNF1_2
259
260
-/*
261
- * Store contiguous data, protected by a governing predicate.
262
- */
263
-
264
-#ifdef CONFIG_SOFTMMU
265
-#define DO_ST_TLB(NAME, H, TYPEM, HOST, MOEND, TLB) \
266
-static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
267
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
268
-{ \
269
- TLB(env, addr, *(TYPEM *)(vd + H(reg_off)), oi, ra); \
270
-}
271
-#else
272
-#define DO_ST_TLB(NAME, H, TYPEM, HOST, MOEND, TLB) \
273
-static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
274
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
275
-{ \
276
- HOST(g2h(addr), *(TYPEM *)(vd + H(reg_off))); \
277
-}
278
-#endif
279
-
280
-DO_ST_TLB(st1bb, H1, uint8_t, stb_p, 0, helper_ret_stb_mmu)
281
-DO_ST_TLB(st1bh, H1_2, uint16_t, stb_p, 0, helper_ret_stb_mmu)
282
-DO_ST_TLB(st1bs, H1_4, uint32_t, stb_p, 0, helper_ret_stb_mmu)
283
-DO_ST_TLB(st1bd, , uint64_t, stb_p, 0, helper_ret_stb_mmu)
284
-
285
-DO_ST_TLB(st1hh_le, H1_2, uint16_t, stw_le_p, MO_LE, helper_le_stw_mmu)
286
-DO_ST_TLB(st1hs_le, H1_4, uint32_t, stw_le_p, MO_LE, helper_le_stw_mmu)
287
-DO_ST_TLB(st1hd_le, , uint64_t, stw_le_p, MO_LE, helper_le_stw_mmu)
288
-
289
-DO_ST_TLB(st1ss_le, H1_4, uint32_t, stl_le_p, MO_LE, helper_le_stl_mmu)
290
-DO_ST_TLB(st1sd_le, , uint64_t, stl_le_p, MO_LE, helper_le_stl_mmu)
291
-
292
-DO_ST_TLB(st1dd_le, , uint64_t, stq_le_p, MO_LE, helper_le_stq_mmu)
293
-
294
-DO_ST_TLB(st1hh_be, H1_2, uint16_t, stw_be_p, MO_BE, helper_be_stw_mmu)
295
-DO_ST_TLB(st1hs_be, H1_4, uint32_t, stw_be_p, MO_BE, helper_be_stw_mmu)
296
-DO_ST_TLB(st1hd_be, , uint64_t, stw_be_p, MO_BE, helper_be_stw_mmu)
297
-
298
-DO_ST_TLB(st1ss_be, H1_4, uint32_t, stl_be_p, MO_BE, helper_be_stl_mmu)
299
-DO_ST_TLB(st1sd_be, , uint64_t, stl_be_p, MO_BE, helper_be_stl_mmu)
300
-
301
-DO_ST_TLB(st1dd_be, , uint64_t, stq_be_p, MO_BE, helper_be_stq_mmu)
302
-
303
-#undef DO_ST_TLB
304
-
305
/*
306
* Common helpers for all contiguous 1,2,3,4-register predicated stores.
307
*/
308
static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
309
uint32_t desc, const uintptr_t ra,
310
const int esize, const int msize,
311
- sve_st1_tlb_fn *tlb_fn)
312
+ sve_ldst1_tlb_fn *tlb_fn)
313
{
314
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
315
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
316
intptr_t i, oprsz = simd_oprsz(desc);
317
void *vd = &env->vfp.zregs[rd];
318
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
319
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
320
do {
321
if (pg & 1) {
322
- tlb_fn(env, vd, i, addr, oi, ra);
323
+ tlb_fn(env, vd, i, addr, ra);
324
}
325
i += esize, pg >>= esize;
326
addr += msize;
327
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
328
static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
329
uint32_t desc, const uintptr_t ra,
330
const int esize, const int msize,
331
- sve_st1_tlb_fn *tlb_fn)
332
+ sve_ldst1_tlb_fn *tlb_fn)
333
{
334
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
335
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
336
intptr_t i, oprsz = simd_oprsz(desc);
337
void *d1 = &env->vfp.zregs[rd];
338
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
339
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
340
do {
341
if (pg & 1) {
342
- tlb_fn(env, d1, i, addr, oi, ra);
343
- tlb_fn(env, d2, i, addr + msize, oi, ra);
344
+ tlb_fn(env, d1, i, addr, ra);
345
+ tlb_fn(env, d2, i, addr + msize, ra);
346
}
347
i += esize, pg >>= esize;
348
addr += 2 * msize;
349
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
350
static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
351
uint32_t desc, const uintptr_t ra,
352
const int esize, const int msize,
353
- sve_st1_tlb_fn *tlb_fn)
354
+ sve_ldst1_tlb_fn *tlb_fn)
355
{
356
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
357
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
358
intptr_t i, oprsz = simd_oprsz(desc);
359
void *d1 = &env->vfp.zregs[rd];
360
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
361
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
362
do {
363
if (pg & 1) {
364
- tlb_fn(env, d1, i, addr, oi, ra);
365
- tlb_fn(env, d2, i, addr + msize, oi, ra);
366
- tlb_fn(env, d3, i, addr + 2 * msize, oi, ra);
367
+ tlb_fn(env, d1, i, addr, ra);
368
+ tlb_fn(env, d2, i, addr + msize, ra);
369
+ tlb_fn(env, d3, i, addr + 2 * msize, ra);
370
}
371
i += esize, pg >>= esize;
372
addr += 3 * msize;
373
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
374
static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
375
uint32_t desc, const uintptr_t ra,
376
const int esize, const int msize,
377
- sve_st1_tlb_fn *tlb_fn)
378
+ sve_ldst1_tlb_fn *tlb_fn)
379
{
380
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
381
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
382
intptr_t i, oprsz = simd_oprsz(desc);
383
void *d1 = &env->vfp.zregs[rd];
384
@@ -XXX,XX +XXX,XX @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
385
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
386
do {
387
if (pg & 1) {
388
- tlb_fn(env, d1, i, addr, oi, ra);
389
- tlb_fn(env, d2, i, addr + msize, oi, ra);
390
- tlb_fn(env, d3, i, addr + 2 * msize, oi, ra);
391
- tlb_fn(env, d4, i, addr + 3 * msize, oi, ra);
392
+ tlb_fn(env, d1, i, addr, ra);
393
+ tlb_fn(env, d2, i, addr + msize, ra);
394
+ tlb_fn(env, d3, i, addr + 2 * msize, ra);
395
+ tlb_fn(env, d4, i, addr + 3 * msize, ra);
396
}
397
i += esize, pg >>= esize;
398
addr += 4 * msize;
399
@@ -XXX,XX +XXX,XX @@ static target_ulong off_zd_d(void *reg, intptr_t reg_ofs)
400
401
static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
402
target_ulong base, uint32_t desc, uintptr_t ra,
403
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
404
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
405
{
406
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
407
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
408
intptr_t i, oprsz = simd_oprsz(desc);
409
ARMVectorReg scratch = { };
410
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
411
do {
412
if (likely(pg & 1)) {
413
target_ulong off = off_fn(vm, i);
414
- tlb_fn(env, &scratch, i, base + (off << scale), oi, ra);
415
+ tlb_fn(env, &scratch, i, base + (off << scale), ra);
416
}
417
i += 4, pg >>= 4;
418
} while (i & 15);
419
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
420
421
static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
422
target_ulong base, uint32_t desc, uintptr_t ra,
423
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
424
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
425
{
426
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
427
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
428
intptr_t i, oprsz = simd_oprsz(desc) / 8;
429
ARMVectorReg scratch = { };
430
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
431
uint8_t pg = *(uint8_t *)(vg + H1(i));
432
if (likely(pg & 1)) {
433
target_ulong off = off_fn(vm, i * 8);
434
- tlb_fn(env, &scratch, i * 8, base + (off << scale), oi, ra);
435
+ tlb_fn(env, &scratch, i * 8, base + (off << scale), ra);
436
}
437
}
438
clear_helper_retaddr();
439
@@ -XXX,XX +XXX,XX @@ DO_LD_NF(dd_be, , uint64_t, uint64_t, ldq_be_p)
440
*/
441
static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
442
target_ulong base, uint32_t desc, uintptr_t ra,
443
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn,
444
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
445
sve_ld1_nf_fn *nonfault_fn)
446
{
447
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
448
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
449
set_helper_retaddr(ra);
450
addr = off_fn(vm, reg_off);
451
addr = base + (addr << scale);
452
- tlb_fn(env, vd, reg_off, addr, oi, ra);
453
+ tlb_fn(env, vd, reg_off, addr, ra);
454
455
/* The rest of the reads will be non-faulting. */
456
clear_helper_retaddr();
457
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
458
459
static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
460
target_ulong base, uint32_t desc, uintptr_t ra,
461
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn,
462
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
463
sve_ld1_nf_fn *nonfault_fn)
464
{
465
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
466
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
467
set_helper_retaddr(ra);
468
addr = off_fn(vm, reg_off);
469
addr = base + (addr << scale);
470
- tlb_fn(env, vd, reg_off, addr, oi, ra);
471
+ tlb_fn(env, vd, reg_off, addr, ra);
472
473
/* The rest of the reads will be non-faulting. */
474
clear_helper_retaddr();
475
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_ZPZ_D(dd_be, zd)
476
477
static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
478
target_ulong base, uint32_t desc, uintptr_t ra,
479
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
480
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
481
{
482
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
483
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
484
intptr_t i, oprsz = simd_oprsz(desc);
485
486
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
487
do {
488
if (likely(pg & 1)) {
489
target_ulong off = off_fn(vm, i);
490
- tlb_fn(env, vd, i, base + (off << scale), oi, ra);
491
+ tlb_fn(env, vd, i, base + (off << scale), ra);
492
}
493
i += 4, pg >>= 4;
494
} while (i & 15);
495
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
496
497
static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
498
target_ulong base, uint32_t desc, uintptr_t ra,
499
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
500
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
501
{
502
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
503
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
504
intptr_t i, oprsz = simd_oprsz(desc) / 8;
505
506
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
507
uint8_t pg = *(uint8_t *)(vg + H1(i));
508
if (likely(pg & 1)) {
509
target_ulong off = off_fn(vm, i * 8);
510
- tlb_fn(env, vd, i * 8, base + (off << scale), oi, ra);
511
+ tlb_fn(env, vd, i * 8, base + (off << scale), ra);
512
}
513
}
514
clear_helper_retaddr();
515
--
25
--
516
2.20.1
26
2.34.1
517
518
diff view generated by jsdifflib
[PULL 03/34] aspeed: Support AST2600A1 silicon revision
[PULL 53/72] target/rx: Set default NaN pattern explicitly
1
From: Joel Stanley <joel@jms.id.au>
1
Set the default NaN pattern explicitly for rx.
2
2
3
There are minimal differences from Qemu's point of view between the A0
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
and A1 silicon revisions.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-48-peter.maydell@linaro.org
6
---
7
target/rx/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
5
9
6
As the A1 exercises different code paths in u-boot it is desirable to
10
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
7
emulate that instead.
8
9
Signed-off-by: Joel Stanley <joel@jms.id.au>
10
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
11
Reviewed-by: Cédric Le Goater <clg@kaod.org>
12
Message-id: 20200504093703.261135-1-joel@jms.id.au
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
include/hw/misc/aspeed_scu.h | 1 +
16
hw/arm/aspeed.c | 8 ++++----
17
hw/arm/aspeed_ast2600.c | 6 +++---
18
hw/misc/aspeed_scu.c | 11 +++++------
19
4 files changed, 13 insertions(+), 13 deletions(-)
20
21
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
22
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/misc/aspeed_scu.h
12
--- a/target/rx/cpu.c
24
+++ b/include/hw/misc/aspeed_scu.h
13
+++ b/target/rx/cpu.c
25
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSCUState {
14
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj, ResetType type)
26
#define AST2500_A0_SILICON_REV 0x04000303U
15
* then prefer dest over source", which is float_2nan_prop_s_ab.
27
#define AST2500_A1_SILICON_REV 0x04010303U
16
*/
28
#define AST2600_A0_SILICON_REV 0x05000303U
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
29
+#define AST2600_A1_SILICON_REV 0x05010303U
18
+ /* Default NaN value: sign bit clear, set frac msb */
30
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
31
#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
32
33
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/arm/aspeed.c
36
+++ b/hw/arm/aspeed.c
37
@@ -XXX,XX +XXX,XX @@ struct AspeedBoardState {
38
39
/* Tacoma hardware value */
40
#define TACOMA_BMC_HW_STRAP1 0x00000000
41
-#define TACOMA_BMC_HW_STRAP2 0x00000000
42
+#define TACOMA_BMC_HW_STRAP2 0x00000040
43
44
/*
45
* The max ram region is for firmwares that scan the address space
46
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
47
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
48
49
mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
50
- amc->soc_name = "ast2600-a0";
51
+ amc->soc_name = "ast2600-a1";
52
amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
53
amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
54
amc->fmc_model = "w25q512jv";
55
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
56
MachineClass *mc = MACHINE_CLASS(oc);
57
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
58
59
- mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
60
- amc->soc_name = "ast2600-a0";
61
+ mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)";
62
+ amc->soc_name = "ast2600-a1";
63
amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
64
amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
65
amc->fmc_model = "mx66l1g45g";
66
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/hw/arm/aspeed_ast2600.c
69
+++ b/hw/arm/aspeed_ast2600.c
70
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
71
72
dc->realize = aspeed_soc_ast2600_realize;
73
74
- sc->name = "ast2600-a0";
75
+ sc->name = "ast2600-a1";
76
sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
77
- sc->silicon_rev = AST2600_A0_SILICON_REV;
78
+ sc->silicon_rev = AST2600_A1_SILICON_REV;
79
sc->sram_size = 0x10000;
80
sc->spis_num = 2;
81
sc->ehcis_num = 2;
82
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
83
}
20
}
84
21
85
static const TypeInfo aspeed_soc_ast2600_type_info = {
22
static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
86
- .name = "ast2600-a0",
87
+ .name = "ast2600-a1",
88
.parent = TYPE_ASPEED_SOC,
89
.instance_size = sizeof(AspeedSoCState),
90
.instance_init = aspeed_soc_ast2600_init,
91
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/hw/misc/aspeed_scu.c
94
+++ b/hw/misc/aspeed_scu.c
95
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_silicon_revs[] = {
96
AST2500_A0_SILICON_REV,
97
AST2500_A1_SILICON_REV,
98
AST2600_A0_SILICON_REV,
99
+ AST2600_A1_SILICON_REV,
100
};
101
102
bool is_supported_silicon_rev(uint32_t silicon_rev)
103
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = {
104
.valid.unaligned = false,
105
};
106
107
-static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = {
108
- [AST2600_SILICON_REV] = AST2600_SILICON_REV,
109
- [AST2600_SILICON_REV2] = AST2600_SILICON_REV,
110
- [AST2600_SYS_RST_CTRL] = 0xF7CFFEDC | 0x100,
111
+static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = {
112
+ [AST2600_SYS_RST_CTRL] = 0xF7C3FED8,
113
[AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC,
114
- [AST2600_CLK_STOP_CTRL] = 0xEFF43E8B,
115
+ [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A,
116
[AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0,
117
[AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */
118
[AST2600_HPLL_PARAM] = 0x1000405F,
119
@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data)
120
121
dc->desc = "ASPEED 2600 System Control Unit";
122
dc->reset = aspeed_ast2600_scu_reset;
123
- asc->resets = ast2600_a0_resets;
124
+ asc->resets = ast2600_a1_resets;
125
asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */
126
asc->apb_divider = 4;
127
asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
128
--
23
--
129
2.20.1
24
2.34.1
130
131
diff view generated by jsdifflib
New patch
[PULL 54/72] target/s390x: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for s390x.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-49-peter.maydell@linaro.org
6
---
7
target/s390x/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/s390x/cpu.c
13
+++ b/target/s390x/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
15
set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
16
set_float_infzeronan_rule(float_infzeronan_dnan_always,
17
&env->fpu_status);
18
+ /* Default NaN value: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fpu_status);
20
/* fall through */
21
case RESET_TYPE_S390_CPU_NORMAL:
22
env->psw.mask &= ~PSW_MASK_RI;
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 55/72] target/sparc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for SPARC, and remove
2
the ifdef from parts64_default_nan.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-50-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 5 +----
10
2 files changed, 3 insertions(+), 4 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN value: sign bit clear, all frac bits set */
21
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
uint8_t dnan_pattern = status->default_nan_pattern;
31
32
if (dnan_pattern == 0) {
33
-#if defined(TARGET_SPARC)
34
- /* Sign bit clear, all frac bits set */
35
- dnan_pattern = 0b01111111;
36
-#elif defined(TARGET_HEXAGON)
37
+#if defined(TARGET_HEXAGON)
38
/* Sign bit set, all frac bits set. */
39
dnan_pattern = 0b11111111;
40
#else
41
--
42
2.34.1
diff view generated by jsdifflib
[PULL 02/34] target/arm: Drop access_el3_aa32ns_aa64any()
[PULL 56/72] target/xtensa: Set default NaN pattern explicitly
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
Set the default NaN pattern explicitly for xtensa.
2
2
3
Calling access_el3_aa32ns() works for AArch32 only cores
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
but it does not handle 32-bit EL2 on top of 64-bit EL3
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
for mixed 32/64-bit cores.
5
Message-id: 20241202131347.498124-51-peter.maydell@linaro.org
6
---
7
target/xtensa/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
6
9
7
Merge access_el3_aa32ns_aa64any() into access_el3_aa32ns()
10
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
8
and only use the latter.
9
10
Fixes: 68e9c2fe65 ("target-arm: Add VTCR_EL2")
11
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
12
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
13
Message-id: 20200505141729.31930-2-edgar.iglesias@gmail.com
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/helper.c | 30 +++++++-----------------------
18
1 file changed, 7 insertions(+), 23 deletions(-)
19
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
21
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper.c
12
--- a/target/xtensa/cpu.c
23
+++ b/target/arm/helper.c
13
+++ b/target/xtensa/cpu.c
24
@@ -XXX,XX +XXX,XX @@ void init_cpreg_list(ARMCPU *cpu)
14
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
15
/* For inf * 0 + NaN, return the input NaN */
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
17
set_no_signaling_nans(!dfpu, &env->fp_status);
18
+ /* Default NaN value: sign bit clear, set frac msb */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
xtensa_use_first_nan(env, !dfpu);
25
}
21
}
26
22
27
/*
28
- * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
29
- * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
30
- *
31
- * access_el3_aa32ns: Used to check AArch32 register views.
32
- * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
33
+ * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
34
*/
35
static CPAccessResult access_el3_aa32ns(CPUARMState *env,
36
const ARMCPRegInfo *ri,
37
bool isread)
38
{
39
- bool secure = arm_is_secure_below_el3(env);
40
-
41
- assert(!arm_el_is_aa64(env, 3));
42
- if (secure) {
43
+ if (!is_a64(env) && arm_current_el(env) == 3 &&
44
+ arm_is_secure_below_el3(env)) {
45
return CP_ACCESS_TRAP_UNCATEGORIZED;
46
}
47
return CP_ACCESS_OK;
48
}
49
50
-static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
51
- const ARMCPRegInfo *ri,
52
- bool isread)
53
-{
54
- if (!arm_el_is_aa64(env, 3)) {
55
- return access_el3_aa32ns(env, ri, isread);
56
- }
57
- return CP_ACCESS_OK;
58
-}
59
-
60
/* Some secure-only AArch32 registers trap to EL3 if used from
61
* Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
62
* Note that an access from Secure EL1 can only happen if EL3 is AArch64.
63
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
64
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
65
{ .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
66
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
67
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
68
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
69
.type = ARM_CP_CONST, .resetvalue = 0 },
70
{ .name = "VTTBR", .state = ARM_CP_STATE_AA32,
71
.cp = 15, .opc1 = 6, .crm = 2,
72
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
73
.type = ARM_CP_CONST, .resetvalue = 0 },
74
{ .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
75
.opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
76
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
77
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
78
.type = ARM_CP_CONST, .resetvalue = 0 },
79
{ .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
80
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
81
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
82
ARMCPRegInfo vpidr_regs[] = {
83
{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
84
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
85
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
86
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
87
.type = ARM_CP_CONST, .resetvalue = cpu->midr,
88
.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
89
{ .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
90
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
91
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
92
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
93
.type = ARM_CP_NO_RAW,
94
.writefn = arm_cp_write_ignore, .readfn = mpidr_read },
95
REGINFO_SENTINEL
96
--
23
--
97
2.20.1
24
2.34.1
98
99
diff view generated by jsdifflib
[PULL 17/34] target/arm: Adjust interface of sve_ld1_host_fn
[PULL 57/72] target/hexagon: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for hexagon.
2
Remove the ifdef from parts64_default_nan(); the only
3
remaining unconverted targets all use the default case.
2
4
3
The current interface includes a loop; change it to load a
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
single element. We will then be able to use the function
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
for ld{2,3,4} where individual vector elements are not adjacent.
7
Message-id: 20241202131347.498124-52-peter.maydell@linaro.org
8
---
9
target/hexagon/cpu.c | 2 ++
10
fpu/softfloat-specialize.c.inc | 5 -----
11
2 files changed, 2 insertions(+), 5 deletions(-)
6
12
7
Replace each call with the simplest possible loop over active
13
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
8
elements.
9
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200508154359.7494-11-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/sve_helper.c | 124 ++++++++++++++++++++--------------------
16
1 file changed, 63 insertions(+), 61 deletions(-)
17
18
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
19
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/sve_helper.c
15
--- a/target/hexagon/cpu.c
21
+++ b/target/arm/sve_helper.c
16
+++ b/target/hexagon/cpu.c
22
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
17
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
23
*/
18
24
19
set_default_nan_mode(1, &env->fp_status);
25
/*
20
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
26
- * Load elements into @vd, controlled by @vg, from @host + @mem_ofs.
21
+ /* Default NaN value: sign bit set, all frac bits set */
27
- * Memory is valid through @host + @mem_max. The register element
22
+ set_float_default_nan_pattern(0b11111111, &env->fp_status);
28
- * indices are inferred from @mem_ofs, as modified by the types for
29
- * which the helper is built. Return the @mem_ofs of the first element
30
- * not loaded (which is @mem_max if they are all loaded).
31
- *
32
- * For softmmu, we have fully validated the guest page. For user-only,
33
- * we cannot fully validate without taking the mmap lock, but since we
34
- * know the access is within one host page, if any access is valid they
35
- * all must be valid. However, when @vg is all false, it may be that
36
- * no access is valid.
37
+ * Load one element into @vd + @reg_off from @host.
38
+ * The controlling predicate is known to be true.
39
*/
40
-typedef intptr_t sve_ld1_host_fn(void *vd, void *vg, void *host,
41
- intptr_t mem_ofs, intptr_t mem_max);
42
+typedef void sve_ldst1_host_fn(void *vd, intptr_t reg_off, void *host);
43
44
/*
45
* Load one element into @vd + @reg_off from (@env, @vaddr, @ra).
46
@@ -XXX,XX +XXX,XX @@ typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
47
*/
48
49
#define DO_LD_HOST(NAME, H, TYPEE, TYPEM, HOST) \
50
-static intptr_t sve_##NAME##_host(void *vd, void *vg, void *host, \
51
- intptr_t mem_off, const intptr_t mem_max) \
52
-{ \
53
- intptr_t reg_off = mem_off * (sizeof(TYPEE) / sizeof(TYPEM)); \
54
- uint64_t *pg = vg; \
55
- while (mem_off + sizeof(TYPEM) <= mem_max) { \
56
- TYPEM val = 0; \
57
- if (likely((pg[reg_off >> 6] >> (reg_off & 63)) & 1)) { \
58
- val = HOST(host + mem_off); \
59
- } \
60
- *(TYPEE *)(vd + H(reg_off)) = val; \
61
- mem_off += sizeof(TYPEM), reg_off += sizeof(TYPEE); \
62
- } \
63
- return mem_off; \
64
+static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
65
+{ \
66
+ TYPEM val = HOST(host); \
67
+ *(TYPEE *)(vd + H(reg_off)) = val; \
68
}
23
}
69
24
70
#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \
25
static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
71
@@ -XXX,XX +XXX,XX @@ static inline bool test_host_page(void *host)
26
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
72
static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
27
index XXXXXXX..XXXXXXX 100644
73
uint32_t desc, const uintptr_t retaddr,
28
--- a/fpu/softfloat-specialize.c.inc
74
const int esz, const int msz,
29
+++ b/fpu/softfloat-specialize.c.inc
75
- sve_ld1_host_fn *host_fn,
30
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
76
+ sve_ldst1_host_fn *host_fn,
31
uint8_t dnan_pattern = status->default_nan_pattern;
77
sve_ldst1_tlb_fn *tlb_fn)
32
78
{
33
if (dnan_pattern == 0) {
79
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
34
-#if defined(TARGET_HEXAGON)
80
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
35
- /* Sign bit set, all frac bits set. */
81
if (likely(split == mem_max)) {
36
- dnan_pattern = 0b11111111;
82
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
37
-#else
83
if (test_host_page(host)) {
38
/*
84
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
39
* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
85
- tcg_debug_assert(mem_off == mem_max);
40
* S390, SH4, TriCore, and Xtensa. Our other supported targets
86
+ intptr_t i = reg_off;
41
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
87
+ host -= mem_off;
42
/* sign bit clear, set frac msb */
88
+ do {
43
dnan_pattern = 0b01000000;
89
+ host_fn(vd, i, host + (i >> diffsz));
90
+ i = find_next_active(vg, i + (1 << esz), reg_max, esz);
91
+ } while (i < reg_max);
92
/* After having taken any fault, zero leading inactive elements. */
93
swap_memzero(vd, reg_off);
94
return;
95
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
96
*/
97
#ifdef CONFIG_USER_ONLY
98
swap_memzero(&scratch, reg_off);
99
- host_fn(&scratch, vg, g2h(addr), mem_off, mem_max);
100
+ host = g2h(addr);
101
+ do {
102
+ host_fn(&scratch, reg_off, host + (reg_off >> diffsz));
103
+ reg_off += 1 << esz;
104
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
105
+ } while (reg_off < reg_max);
106
#else
107
memset(&scratch, 0, reg_max);
108
goto start;
109
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
110
host = tlb_vaddr_to_host(env, addr + mem_off,
111
MMU_DATA_LOAD, mmu_idx);
112
if (host) {
113
- mem_off = host_fn(&scratch, vg, host - mem_off,
114
- mem_off, split);
115
- reg_off = mem_off << diffsz;
116
+ host -= mem_off;
117
+ do {
118
+ host_fn(&scratch, reg_off, host + mem_off);
119
+ reg_off += 1 << esz;
120
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
121
+ mem_off = reg_off >> diffsz;
122
+ } while (split - mem_off >= (1 << msz));
123
continue;
124
}
125
}
44
}
126
@@ -XXX,XX +XXX,XX @@ static void record_fault(CPUARMState *env, uintptr_t i, uintptr_t oprsz)
45
-#endif
127
static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
128
uint32_t desc, const uintptr_t retaddr,
129
const int esz, const int msz,
130
- sve_ld1_host_fn *host_fn,
131
+ sve_ldst1_host_fn *host_fn,
132
sve_ldst1_tlb_fn *tlb_fn)
133
{
134
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
135
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
136
const int diffsz = esz - msz;
137
const intptr_t reg_max = simd_oprsz(desc);
138
const intptr_t mem_max = reg_max >> diffsz;
139
- intptr_t split, reg_off, mem_off;
140
+ intptr_t split, reg_off, mem_off, i;
141
void *host;
142
143
/* Skip to the first active element. */
144
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
145
if (likely(split == mem_max)) {
146
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
147
if (test_host_page(host)) {
148
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
149
- tcg_debug_assert(mem_off == mem_max);
150
+ i = reg_off;
151
+ host -= mem_off;
152
+ do {
153
+ host_fn(vd, i, host + (i >> diffsz));
154
+ i = find_next_active(vg, i + (1 << esz), reg_max, esz);
155
+ } while (i < reg_max);
156
/* After any fault, zero any leading inactive elements. */
157
swap_memzero(vd, reg_off);
158
return;
159
}
160
}
46
}
161
47
assert(dnan_pattern != 0);
162
-#ifdef CONFIG_USER_ONLY
163
- /*
164
- * The page(s) containing this first element at ADDR+MEM_OFF must
165
- * be valid. Considering that this first element may be misaligned
166
- * and cross a page boundary itself, take the rest of the page from
167
- * the last byte of the element.
168
- */
169
- split = max_for_page(addr, mem_off + (1 << msz) - 1, mem_max);
170
- mem_off = host_fn(vd, vg, g2h(addr), mem_off, split);
171
-
172
- /* After any fault, zero any leading inactive elements. */
173
- swap_memzero(vd, reg_off);
174
- reg_off = mem_off << diffsz;
175
-#else
176
/*
177
* Perform one normal read, which will fault or not.
178
* But it is likely to bring the page into the tlb.
179
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
180
if (split >= (1 << msz)) {
181
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
182
if (host) {
183
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, split);
184
- reg_off = mem_off << diffsz;
185
+ host -= mem_off;
186
+ do {
187
+ host_fn(vd, reg_off, host + mem_off);
188
+ reg_off += 1 << esz;
189
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
190
+ mem_off = reg_off >> diffsz;
191
+ } while (split - mem_off >= (1 << msz));
192
}
193
}
194
-#endif
195
196
record_fault(env, reg_off, reg_max);
197
}
198
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
199
*/
200
static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
201
uint32_t desc, const int esz, const int msz,
202
- sve_ld1_host_fn *host_fn)
203
+ sve_ldst1_host_fn *host_fn)
204
{
205
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
206
void *vd = &env->vfp.zregs[rd];
207
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
208
host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_idx);
209
if (likely(page_check_range(addr, mem_max, PAGE_READ) == 0)) {
210
/* The entire operation is valid and will not fault. */
211
- host_fn(vd, vg, host, 0, mem_max);
212
+ reg_off = 0;
213
+ do {
214
+ mem_off = reg_off >> diffsz;
215
+ host_fn(vd, reg_off, host + mem_off);
216
+ reg_off += 1 << esz;
217
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
218
+ } while (reg_off < reg_max);
219
return;
220
}
221
#endif
222
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
223
if (page_check_range(addr + mem_off, 1 << msz, PAGE_READ) == 0) {
224
/* At least one load is valid; take the rest of the page. */
225
split = max_for_page(addr, mem_off + (1 << msz) - 1, mem_max);
226
- mem_off = host_fn(vd, vg, host, mem_off, split);
227
- reg_off = mem_off << diffsz;
228
+ do {
229
+ host_fn(vd, reg_off, host + mem_off);
230
+ reg_off += 1 << esz;
231
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
232
+ mem_off = reg_off >> diffsz;
233
+ } while (split - mem_off >= (1 << msz));
234
}
235
#else
236
/*
237
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
238
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
239
split = max_for_page(addr, mem_off, mem_max);
240
if (host && split >= (1 << msz)) {
241
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, split);
242
- reg_off = mem_off << diffsz;
243
+ host -= mem_off;
244
+ do {
245
+ host_fn(vd, reg_off, host + mem_off);
246
+ reg_off += 1 << esz;
247
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
248
+ mem_off = reg_off >> diffsz;
249
+ } while (split - mem_off >= (1 << msz));
250
}
251
#endif
252
48
253
--
49
--
254
2.20.1
50
2.34.1
255
256
diff view generated by jsdifflib
New patch
[PULL 58/72] target/riscv: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for riscv.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-53-peter.maydell@linaro.org
6
---
7
target/riscv/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/riscv/cpu.c
13
+++ b/target/riscv/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
15
cs->exception_index = RISCV_EXCP_NONE;
16
env->load_res = -1;
17
set_default_nan_mode(1, &env->fp_status);
18
+ /* Default NaN value: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
env->vill = true;
21
22
#ifndef CONFIG_USER_ONLY
23
--
24
2.34.1
diff view generated by jsdifflib
[PULL 05/34] hw/arm/nrf51: Add NRF51_PERIPHERAL_SIZE definition
[PULL 59/72] target/tricore: Set default NaN pattern explicitly
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Set the default NaN pattern explicitly for tricore.
2
2
3
On the NRF51 series, all peripherals have a fixed I/O size
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
of 4KiB. Define NRF51_PERIPHERAL_SIZE and use it.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-54-peter.maydell@linaro.org
6
---
7
target/tricore/helper.c | 2 ++
8
1 file changed, 2 insertions(+)
5
9
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200504072822.18799-2-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/nrf51.h | 3 +--
12
include/hw/i2c/microbit_i2c.h | 2 +-
13
hw/arm/nrf51_soc.c | 4 ++--
14
hw/i2c/microbit_i2c.c | 2 +-
15
hw/timer/nrf51_timer.c | 2 +-
16
5 files changed, 6 insertions(+), 7 deletions(-)
17
18
diff --git a/include/hw/arm/nrf51.h b/include/hw/arm/nrf51.h
19
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/nrf51.h
12
--- a/target/tricore/helper.c
21
+++ b/include/hw/arm/nrf51.h
13
+++ b/target/tricore/helper.c
22
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@ void fpu_set_state(CPUTriCoreState *env)
23
#define NRF51_IOMEM_BASE 0x40000000
15
set_flush_to_zero(1, &env->fp_status);
24
#define NRF51_IOMEM_SIZE 0x20000000
16
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
25
17
set_default_nan_mode(1, &env->fp_status);
26
+#define NRF51_PERIPHERAL_SIZE 0x00001000
18
+ /* Default NaN pattern: sign bit clear, frac msb set */
27
#define NRF51_UART_BASE 0x40002000
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
28
#define NRF51_TWI_BASE 0x40003000
29
-#define NRF51_TWI_SIZE 0x00001000
30
#define NRF51_TIMER_BASE 0x40008000
31
-#define NRF51_TIMER_SIZE 0x00001000
32
#define NRF51_RNG_BASE 0x4000D000
33
#define NRF51_NVMC_BASE 0x4001E000
34
#define NRF51_GPIO_BASE 0x50000000
35
diff --git a/include/hw/i2c/microbit_i2c.h b/include/hw/i2c/microbit_i2c.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/include/hw/i2c/microbit_i2c.h
38
+++ b/include/hw/i2c/microbit_i2c.h
39
@@ -XXX,XX +XXX,XX @@
40
#define MICROBIT_I2C(obj) \
41
OBJECT_CHECK(MicrobitI2CState, (obj), TYPE_MICROBIT_I2C)
42
43
-#define MICROBIT_I2C_NREGS (NRF51_TWI_SIZE / sizeof(uint32_t))
44
+#define MICROBIT_I2C_NREGS (NRF51_PERIPHERAL_SIZE / sizeof(uint32_t))
45
46
typedef struct {
47
SysBusDevice parent_obj;
48
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/arm/nrf51_soc.c
51
+++ b/hw/arm/nrf51_soc.c
52
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
53
return;
54
}
55
56
- base_addr = NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE;
57
+ base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE;
58
59
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
60
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
61
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
62
63
/* STUB Peripherals */
64
memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL,
65
- "nrf51_soc.clock", 0x1000);
66
+ "nrf51_soc.clock", NRF51_PERIPHERAL_SIZE);
67
memory_region_add_subregion_overlap(&s->container,
68
NRF51_IOMEM_BASE, &s->clock, -1);
69
70
diff --git a/hw/i2c/microbit_i2c.c b/hw/i2c/microbit_i2c.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/i2c/microbit_i2c.c
73
+++ b/hw/i2c/microbit_i2c.c
74
@@ -XXX,XX +XXX,XX @@ static void microbit_i2c_realize(DeviceState *dev, Error **errp)
75
MicrobitI2CState *s = MICROBIT_I2C(dev);
76
77
memory_region_init_io(&s->iomem, OBJECT(s), &microbit_i2c_ops, s,
78
- "microbit.twi", NRF51_TWI_SIZE);
79
+ "microbit.twi", NRF51_PERIPHERAL_SIZE);
80
sysbus_init_mmio(sbd, &s->iomem);
81
}
20
}
82
21
83
diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c
22
uint32_t psw_read(CPUTriCoreState *env)
84
index XXXXXXX..XXXXXXX 100644
85
--- a/hw/timer/nrf51_timer.c
86
+++ b/hw/timer/nrf51_timer.c
87
@@ -XXX,XX +XXX,XX @@ static void nrf51_timer_init(Object *obj)
88
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
89
90
memory_region_init_io(&s->iomem, obj, &rng_ops, s,
91
- TYPE_NRF51_TIMER, NRF51_TIMER_SIZE);
92
+ TYPE_NRF51_TIMER, NRF51_PERIPHERAL_SIZE);
93
sysbus_init_mmio(sbd, &s->iomem);
94
sysbus_init_irq(sbd, &s->irq);
95
96
--
23
--
97
2.20.1
24
2.34.1
98
99
diff view generated by jsdifflib
New patch
[PULL 60/72] fpu: Remove default handling for dnan_pattern
1
Now that all our targets have bene converted to explicitly specify
2
their pattern for the default NaN value we can remove the remaining
3
fallback code in parts64_default_nan().
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-55-peter.maydell@linaro.org
8
---
9
fpu/softfloat-specialize.c.inc | 14 --------------
10
1 file changed, 14 deletions(-)
11
12
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
13
index XXXXXXX..XXXXXXX 100644
14
--- a/fpu/softfloat-specialize.c.inc
15
+++ b/fpu/softfloat-specialize.c.inc
16
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
17
uint64_t frac;
18
uint8_t dnan_pattern = status->default_nan_pattern;
19
20
- if (dnan_pattern == 0) {
21
- /*
22
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
23
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
24
- * do not have floating-point.
25
- */
26
- if (snan_bit_is_one(status)) {
27
- /* sign bit clear, set all frac bits other than msb */
28
- dnan_pattern = 0b00111111;
29
- } else {
30
- /* sign bit clear, set frac msb */
31
- dnan_pattern = 0b01000000;
32
- }
33
- }
34
assert(dnan_pattern != 0);
35
36
sign = dnan_pattern >> 7;
37
--
38
2.34.1
diff view generated by jsdifflib
[PULL 20/34] target/arm: Use SVEContLdSt for multi-register contiguous loads
[PULL 61/72] softfloat: Inline pickNaNMulAdd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Inline pickNaNMulAdd into its only caller. This makes
4
one assert redundant with the immediately preceding IF.
5
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200508154359.7494-14-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20241203203949.483774-3-richard.henderson@linaro.org
9
[PMM: keep comment from old code in new location]
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
11
---
8
target/arm/sve_helper.c | 223 ++++++++++++++--------------------------
12
fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++-
9
1 file changed, 79 insertions(+), 144 deletions(-)
13
fpu/softfloat-specialize.c.inc | 54 ----------------------------------
14
2 files changed, 40 insertions(+), 55 deletions(-)
10
15
11
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
12
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/sve_helper.c
18
--- a/fpu/softfloat-parts.c.inc
14
+++ b/target/arm/sve_helper.c
19
+++ b/fpu/softfloat-parts.c.inc
15
@@ -XXX,XX +XXX,XX @@ static inline bool test_host_page(void *host)
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
16
}
21
}
17
22
18
/*
23
if (s->default_nan_mode) {
19
- * Common helper for all contiguous one-register predicated loads.
24
+ /*
20
+ * Common helper for all contiguous 1,2,3,4-register predicated stores.
25
+ * We guarantee not to require the target to tell us how to
21
*/
26
+ * pick a NaN if we're always returning the default NaN.
22
static inline QEMU_ALWAYS_INLINE
27
+ * But if we're not in default-NaN mode then the target must
23
-void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
28
+ * specify.
24
+void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
29
+ */
25
uint32_t desc, const uintptr_t retaddr,
30
which = 3;
26
- const int esz, const int msz,
31
+ } else if (infzero) {
27
+ const int esz, const int msz, const int N,
32
+ /*
28
sve_ldst1_host_fn *host_fn,
33
+ * Inf * 0 + NaN -- some implementations return the
29
sve_ldst1_tlb_fn *tlb_fn)
34
+ * default NaN here, and some return the input NaN.
30
{
35
+ */
31
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
36
+ switch (s->float_infzeronan_rule) {
32
- void *vd = &env->vfp.zregs[rd];
37
+ case float_infzeronan_dnan_never:
33
const intptr_t reg_max = simd_oprsz(desc);
38
+ which = 2;
34
intptr_t reg_off, reg_last, mem_off;
39
+ break;
35
SVEContLdSt info;
40
+ case float_infzeronan_dnan_always:
36
void *host;
41
+ which = 3;
37
- int flags;
42
+ break;
38
+ int flags, i;
43
+ case float_infzeronan_dnan_if_qnan:
39
44
+ which = is_qnan(c->cls) ? 3 : 2;
40
/* Find the active elements. */
45
+ break;
41
- if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, 1 << msz)) {
46
+ default:
42
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, N << msz)) {
47
+ g_assert_not_reached();
43
/* The entire predicate was false; no load occurs. */
44
- memset(vd, 0, reg_max);
45
+ for (i = 0; i < N; ++i) {
46
+ memset(&env->vfp.zregs[(rd + i) & 31], 0, reg_max);
47
+ }
48
+ }
48
return;
49
} else {
49
}
50
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
50
51
+ FloatClass cls[3] = { a->cls, b->cls, c->cls };
51
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
52
+ Float3NaNPropRule rule = s->float_3nan_prop_rule;
52
sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, retaddr);
53
54
/* Handle watchpoints for all active elements. */
55
- sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, 1 << msz,
56
+ sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, N << msz,
57
BP_MEM_READ, retaddr);
58
59
/* TODO: MTE check. */
60
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
61
* which for ARM will raise SyncExternal. Perform the load
62
* into scratch memory to preserve register state until the end.
63
*/
64
- ARMVectorReg scratch;
65
+ ARMVectorReg scratch[4] = { };
66
67
- memset(&scratch, 0, reg_max);
68
mem_off = info.mem_off_first[0];
69
reg_off = info.reg_off_first[0];
70
reg_last = info.reg_off_last[1];
71
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
72
uint64_t pg = vg[reg_off >> 6];
73
do {
74
if ((pg >> (reg_off & 63)) & 1) {
75
- tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
76
+ for (i = 0; i < N; ++i) {
77
+ tlb_fn(env, &scratch[i], reg_off,
78
+ addr + mem_off + (i << msz), retaddr);
79
+ }
80
}
81
reg_off += 1 << esz;
82
- mem_off += 1 << msz;
83
+ mem_off += N << msz;
84
} while (reg_off & 63);
85
} while (reg_off <= reg_last);
86
87
- memcpy(vd, &scratch, reg_max);
88
+ for (i = 0; i < N; ++i) {
89
+ memcpy(&env->vfp.zregs[(rd + i) & 31], &scratch[i], reg_max);
90
+ }
91
return;
92
#endif
93
}
94
95
/* The entire operation is in RAM, on valid pages. */
96
97
- memset(vd, 0, reg_max);
98
+ for (i = 0; i < N; ++i) {
99
+ memset(&env->vfp.zregs[(rd + i) & 31], 0, reg_max);
100
+ }
101
+
53
+
102
mem_off = info.mem_off_first[0];
54
+ assert(rule != float_3nan_prop_none);
103
reg_off = info.reg_off_first[0];
55
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
104
reg_last = info.reg_off_last[0];
56
+ /* We have at least one SNaN input and should prefer it */
105
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
57
+ do {
106
uint64_t pg = vg[reg_off >> 6];
58
+ which = rule & R_3NAN_1ST_MASK;
107
do {
59
+ rule >>= R_3NAN_1ST_LENGTH;
108
if ((pg >> (reg_off & 63)) & 1) {
60
+ } while (!is_snan(cls[which]));
109
- host_fn(vd, reg_off, host + mem_off);
61
+ } else {
110
+ for (i = 0; i < N; ++i) {
62
+ do {
111
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
63
+ which = rule & R_3NAN_1ST_MASK;
112
+ host + mem_off + (i << msz));
64
+ rule >>= R_3NAN_1ST_LENGTH;
113
+ }
65
+ } while (!is_nan(cls[which]));
114
}
115
reg_off += 1 << esz;
116
- mem_off += 1 << msz;
117
+ mem_off += N << msz;
118
} while (reg_off <= reg_last && (reg_off & 63));
119
}
120
121
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
122
*/
123
mem_off = info.mem_off_split;
124
if (unlikely(mem_off >= 0)) {
125
- tlb_fn(env, vd, info.reg_off_split, addr + mem_off, retaddr);
126
+ reg_off = info.reg_off_split;
127
+ for (i = 0; i < N; ++i) {
128
+ tlb_fn(env, &env->vfp.zregs[(rd + i) & 31], reg_off,
129
+ addr + mem_off + (i << msz), retaddr);
130
+ }
66
+ }
131
}
67
}
132
68
133
mem_off = info.mem_off_first[1];
69
if (which == 3) {
134
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
70
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
135
uint64_t pg = vg[reg_off >> 6];
71
index XXXXXXX..XXXXXXX 100644
136
do {
72
--- a/fpu/softfloat-specialize.c.inc
137
if ((pg >> (reg_off & 63)) & 1) {
73
+++ b/fpu/softfloat-specialize.c.inc
138
- host_fn(vd, reg_off, host + mem_off);
74
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
139
+ for (i = 0; i < N; ++i) {
140
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
141
+ host + mem_off + (i << msz));
142
+ }
143
}
144
reg_off += 1 << esz;
145
- mem_off += 1 << msz;
146
+ mem_off += N << msz;
147
} while (reg_off & 63);
148
} while (reg_off <= reg_last);
149
}
75
}
150
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
151
void HELPER(sve_##NAME##_r)(CPUARMState *env, void *vg, \
152
target_ulong addr, uint32_t desc) \
153
{ \
154
- sve_ld1_r(env, vg, addr, desc, GETPC(), ESZ, 0, \
155
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, 1, \
156
sve_##NAME##_host, sve_##NAME##_tlb); \
157
}
76
}
158
77
159
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_##NAME##_r)(CPUARMState *env, void *vg, \
78
-/*----------------------------------------------------------------------------
160
void HELPER(sve_##NAME##_le_r)(CPUARMState *env, void *vg, \
79
-| Select which NaN to propagate for a three-input operation.
161
target_ulong addr, uint32_t desc) \
80
-| For the moment we assume that no CPU needs the 'larger significand'
162
{ \
81
-| information.
163
- sve_ld1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
82
-| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
164
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \
83
-*----------------------------------------------------------------------------*/
165
sve_##NAME##_le_host, sve_##NAME##_le_tlb); \
84
-static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
166
} \
85
- bool infzero, bool have_snan, float_status *status)
167
void HELPER(sve_##NAME##_be_r)(CPUARMState *env, void *vg, \
168
target_ulong addr, uint32_t desc) \
169
{ \
170
- sve_ld1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
171
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \
172
sve_##NAME##_be_host, sve_##NAME##_be_tlb); \
173
}
174
175
-DO_LD1_1(ld1bb, 0)
176
-DO_LD1_1(ld1bhu, 1)
177
-DO_LD1_1(ld1bhs, 1)
178
-DO_LD1_1(ld1bsu, 2)
179
-DO_LD1_1(ld1bss, 2)
180
-DO_LD1_1(ld1bdu, 3)
181
-DO_LD1_1(ld1bds, 3)
182
+DO_LD1_1(ld1bb, MO_8)
183
+DO_LD1_1(ld1bhu, MO_16)
184
+DO_LD1_1(ld1bhs, MO_16)
185
+DO_LD1_1(ld1bsu, MO_32)
186
+DO_LD1_1(ld1bss, MO_32)
187
+DO_LD1_1(ld1bdu, MO_64)
188
+DO_LD1_1(ld1bds, MO_64)
189
190
-DO_LD1_2(ld1hh, 1, 1)
191
-DO_LD1_2(ld1hsu, 2, 1)
192
-DO_LD1_2(ld1hss, 2, 1)
193
-DO_LD1_2(ld1hdu, 3, 1)
194
-DO_LD1_2(ld1hds, 3, 1)
195
+DO_LD1_2(ld1hh, MO_16, MO_16)
196
+DO_LD1_2(ld1hsu, MO_32, MO_16)
197
+DO_LD1_2(ld1hss, MO_32, MO_16)
198
+DO_LD1_2(ld1hdu, MO_64, MO_16)
199
+DO_LD1_2(ld1hds, MO_64, MO_16)
200
201
-DO_LD1_2(ld1ss, 2, 2)
202
-DO_LD1_2(ld1sdu, 3, 2)
203
-DO_LD1_2(ld1sds, 3, 2)
204
+DO_LD1_2(ld1ss, MO_32, MO_32)
205
+DO_LD1_2(ld1sdu, MO_64, MO_32)
206
+DO_LD1_2(ld1sds, MO_64, MO_32)
207
208
-DO_LD1_2(ld1dd, 3, 3)
209
+DO_LD1_2(ld1dd, MO_64, MO_64)
210
211
#undef DO_LD1_1
212
#undef DO_LD1_2
213
214
-/*
215
- * Common helpers for all contiguous 2,3,4-register predicated loads.
216
- */
217
-static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
218
- uint32_t desc, int size, uintptr_t ra,
219
- sve_ldst1_tlb_fn *tlb_fn)
220
-{
86
-{
221
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
87
- FloatClass cls[3] = { a_cls, b_cls, c_cls };
222
- intptr_t i, oprsz = simd_oprsz(desc);
88
- Float3NaNPropRule rule = status->float_3nan_prop_rule;
223
- ARMVectorReg scratch[2] = { };
89
- int which;
224
-
90
-
225
- for (i = 0; i < oprsz; ) {
91
- /*
226
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
92
- * We guarantee not to require the target to tell us how to
227
- do {
93
- * pick a NaN if we're always returning the default NaN.
228
- if (pg & 1) {
94
- * But if we're not in default-NaN mode then the target must
229
- tlb_fn(env, &scratch[0], i, addr, ra);
95
- * specify.
230
- tlb_fn(env, &scratch[1], i, addr + size, ra);
96
- */
231
- }
97
- assert(!status->default_nan_mode);
232
- i += size, pg >>= size;
98
-
233
- addr += 2 * size;
99
- if (infzero) {
234
- } while (i & 15);
100
- /*
101
- * Inf * 0 + NaN -- some implementations return the default NaN here,
102
- * and some return the input NaN.
103
- */
104
- switch (status->float_infzeronan_rule) {
105
- case float_infzeronan_dnan_never:
106
- return 2;
107
- case float_infzeronan_dnan_always:
108
- return 3;
109
- case float_infzeronan_dnan_if_qnan:
110
- return is_qnan(c_cls) ? 3 : 2;
111
- default:
112
- g_assert_not_reached();
113
- }
235
- }
114
- }
236
-
115
-
237
- /* Wait until all exceptions have been raised to write back. */
116
- assert(rule != float_3nan_prop_none);
238
- memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
117
- if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
239
- memcpy(&env->vfp.zregs[(rd + 1) & 31], &scratch[1], oprsz);
118
- /* We have at least one SNaN input and should prefer it */
119
- do {
120
- which = rule & R_3NAN_1ST_MASK;
121
- rule >>= R_3NAN_1ST_LENGTH;
122
- } while (!is_snan(cls[which]));
123
- } else {
124
- do {
125
- which = rule & R_3NAN_1ST_MASK;
126
- rule >>= R_3NAN_1ST_LENGTH;
127
- } while (!is_nan(cls[which]));
128
- }
129
- return which;
240
-}
130
-}
241
-
131
-
242
-static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
132
/*----------------------------------------------------------------------------
243
- uint32_t desc, int size, uintptr_t ra,
133
| Returns 1 if the double-precision floating-point value `a' is a quiet
244
- sve_ldst1_tlb_fn *tlb_fn)
134
| NaN; otherwise returns 0.
245
-{
246
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
247
- intptr_t i, oprsz = simd_oprsz(desc);
248
- ARMVectorReg scratch[3] = { };
249
-
250
- for (i = 0; i < oprsz; ) {
251
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
252
- do {
253
- if (pg & 1) {
254
- tlb_fn(env, &scratch[0], i, addr, ra);
255
- tlb_fn(env, &scratch[1], i, addr + size, ra);
256
- tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
257
- }
258
- i += size, pg >>= size;
259
- addr += 3 * size;
260
- } while (i & 15);
261
- }
262
-
263
- /* Wait until all exceptions have been raised to write back. */
264
- memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
265
- memcpy(&env->vfp.zregs[(rd + 1) & 31], &scratch[1], oprsz);
266
- memcpy(&env->vfp.zregs[(rd + 2) & 31], &scratch[2], oprsz);
267
-}
268
-
269
-static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
270
- uint32_t desc, int size, uintptr_t ra,
271
- sve_ldst1_tlb_fn *tlb_fn)
272
-{
273
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
274
- intptr_t i, oprsz = simd_oprsz(desc);
275
- ARMVectorReg scratch[4] = { };
276
-
277
- for (i = 0; i < oprsz; ) {
278
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
279
- do {
280
- if (pg & 1) {
281
- tlb_fn(env, &scratch[0], i, addr, ra);
282
- tlb_fn(env, &scratch[1], i, addr + size, ra);
283
- tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
284
- tlb_fn(env, &scratch[3], i, addr + 3 * size, ra);
285
- }
286
- i += size, pg >>= size;
287
- addr += 4 * size;
288
- } while (i & 15);
289
- }
290
-
291
- /* Wait until all exceptions have been raised to write back. */
292
- memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
293
- memcpy(&env->vfp.zregs[(rd + 1) & 31], &scratch[1], oprsz);
294
- memcpy(&env->vfp.zregs[(rd + 2) & 31], &scratch[2], oprsz);
295
- memcpy(&env->vfp.zregs[(rd + 3) & 31], &scratch[3], oprsz);
296
-}
297
-
298
#define DO_LDN_1(N) \
299
-void QEMU_FLATTEN HELPER(sve_ld##N##bb_r) \
300
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
301
-{ \
302
- sve_ld##N##_r(env, vg, addr, desc, 1, GETPC(), sve_ld1bb_tlb); \
303
+void HELPER(sve_ld##N##bb_r)(CPUARMState *env, void *vg, \
304
+ target_ulong addr, uint32_t desc) \
305
+{ \
306
+ sve_ldN_r(env, vg, addr, desc, GETPC(), MO_8, MO_8, N, \
307
+ sve_ld1bb_host, sve_ld1bb_tlb); \
308
}
309
310
-#define DO_LDN_2(N, SUFF, SIZE) \
311
-void QEMU_FLATTEN HELPER(sve_ld##N##SUFF##_le_r) \
312
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
313
+#define DO_LDN_2(N, SUFF, ESZ) \
314
+void HELPER(sve_ld##N##SUFF##_le_r)(CPUARMState *env, void *vg, \
315
+ target_ulong addr, uint32_t desc) \
316
{ \
317
- sve_ld##N##_r(env, vg, addr, desc, SIZE, GETPC(), \
318
- sve_ld1##SUFF##_le_tlb); \
319
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \
320
+ sve_ld1##SUFF##_le_host, sve_ld1##SUFF##_le_tlb); \
321
} \
322
-void QEMU_FLATTEN HELPER(sve_ld##N##SUFF##_be_r) \
323
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
324
+void HELPER(sve_ld##N##SUFF##_be_r)(CPUARMState *env, void *vg, \
325
+ target_ulong addr, uint32_t desc) \
326
{ \
327
- sve_ld##N##_r(env, vg, addr, desc, SIZE, GETPC(), \
328
- sve_ld1##SUFF##_be_tlb); \
329
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \
330
+ sve_ld1##SUFF##_be_host, sve_ld1##SUFF##_be_tlb); \
331
}
332
333
DO_LDN_1(2)
334
DO_LDN_1(3)
335
DO_LDN_1(4)
336
337
-DO_LDN_2(2, hh, 2)
338
-DO_LDN_2(3, hh, 2)
339
-DO_LDN_2(4, hh, 2)
340
+DO_LDN_2(2, hh, MO_16)
341
+DO_LDN_2(3, hh, MO_16)
342
+DO_LDN_2(4, hh, MO_16)
343
344
-DO_LDN_2(2, ss, 4)
345
-DO_LDN_2(3, ss, 4)
346
-DO_LDN_2(4, ss, 4)
347
+DO_LDN_2(2, ss, MO_32)
348
+DO_LDN_2(3, ss, MO_32)
349
+DO_LDN_2(4, ss, MO_32)
350
351
-DO_LDN_2(2, dd, 8)
352
-DO_LDN_2(3, dd, 8)
353
-DO_LDN_2(4, dd, 8)
354
+DO_LDN_2(2, dd, MO_64)
355
+DO_LDN_2(3, dd, MO_64)
356
+DO_LDN_2(4, dd, MO_64)
357
358
#undef DO_LDN_1
359
#undef DO_LDN_2
360
--
135
--
361
2.20.1
136
2.34.1
362
137
363
138
diff view generated by jsdifflib
[PULL 21/34] target/arm: Update contiguous first-fault and no-fault loads
[PULL 62/72] softfloat: Use goto for default nan case in pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
With sve_cont_ldst_pages, the differences between first-fault and no-fault
3
Remove "3" as a special case for which and simply
4
are minimal, so unify the routines. With cpu_probe_watchpoint, we are able
4
branch to return the desired value.
5
to make progress through pages with TLB_WATCHPOINT set when the watchpoint
6
does not actually fire.
7
5
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-15-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20241203203949.483774-4-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
target/arm/sve_helper.c | 346 +++++++++++++++++++---------------------
11
fpu/softfloat-parts.c.inc | 20 ++++++++++----------
14
1 file changed, 162 insertions(+), 184 deletions(-)
12
1 file changed, 10 insertions(+), 10 deletions(-)
15
13
16
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sve_helper.c
16
--- a/fpu/softfloat-parts.c.inc
19
+++ b/target/arm/sve_helper.c
17
+++ b/fpu/softfloat-parts.c.inc
20
@@ -XXX,XX +XXX,XX @@ static intptr_t find_next_active(uint64_t *vg, intptr_t reg_off,
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
21
return reg_off;
19
* But if we're not in default-NaN mode then the target must
22
}
20
* specify.
23
21
*/
24
-/*
22
- which = 3;
25
- * Return the maximum offset <= @mem_max which is still within the page
23
+ goto default_nan;
26
- * referenced by @base + @mem_off.
24
} else if (infzero) {
27
- */
25
/*
28
-static intptr_t max_for_page(target_ulong base, intptr_t mem_off,
26
* Inf * 0 + NaN -- some implementations return the
29
- intptr_t mem_max)
27
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
30
-{
28
*/
31
- target_ulong addr = base + mem_off;
29
switch (s->float_infzeronan_rule) {
32
- intptr_t split = -(intptr_t)(addr | TARGET_PAGE_MASK);
30
case float_infzeronan_dnan_never:
33
- return MIN(split, mem_max - mem_off) + mem_off;
31
- which = 2;
34
-}
32
break;
35
-
33
case float_infzeronan_dnan_always:
36
/*
34
- which = 3;
37
* Resolve the guest virtual address to info->host and info->flags.
35
- break;
38
* If @nofault, return false if the page is invalid, otherwise
36
+ goto default_nan;
39
@@ -XXX,XX +XXX,XX @@ static void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env,
37
case float_infzeronan_dnan_if_qnan:
40
#endif
38
- which = is_qnan(c->cls) ? 3 : 2;
41
}
39
+ if (is_qnan(c->cls)) {
42
40
+ goto default_nan;
43
-/*
44
- * The result of tlb_vaddr_to_host for user-only is just g2h(x),
45
- * which is always non-null. Elide the useless test.
46
- */
47
-static inline bool test_host_page(void *host)
48
-{
49
-#ifdef CONFIG_USER_ONLY
50
- return true;
51
-#else
52
- return likely(host != NULL);
53
-#endif
54
-}
55
-
56
/*
57
* Common helper for all contiguous 1,2,3,4-register predicated stores.
58
*/
59
@@ -XXX,XX +XXX,XX @@ static void record_fault(CPUARMState *env, uintptr_t i, uintptr_t oprsz)
60
}
61
62
/*
63
- * Common helper for all contiguous first-fault loads.
64
+ * Common helper for all contiguous no-fault and first-fault loads.
65
*/
66
-static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
67
- uint32_t desc, const uintptr_t retaddr,
68
- const int esz, const int msz,
69
- sve_ldst1_host_fn *host_fn,
70
- sve_ldst1_tlb_fn *tlb_fn)
71
+static inline QEMU_ALWAYS_INLINE
72
+void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
73
+ uint32_t desc, const uintptr_t retaddr,
74
+ const int esz, const int msz, const SVEContFault fault,
75
+ sve_ldst1_host_fn *host_fn,
76
+ sve_ldst1_tlb_fn *tlb_fn)
77
{
78
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
79
- const int mmu_idx = get_mmuidx(oi);
80
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
81
void *vd = &env->vfp.zregs[rd];
82
- const int diffsz = esz - msz;
83
const intptr_t reg_max = simd_oprsz(desc);
84
- const intptr_t mem_max = reg_max >> diffsz;
85
- intptr_t split, reg_off, mem_off, i;
86
+ intptr_t reg_off, mem_off, reg_last;
87
+ SVEContLdSt info;
88
+ int flags;
89
void *host;
90
91
- /* Skip to the first active element. */
92
- reg_off = find_next_active(vg, 0, reg_max, esz);
93
- if (unlikely(reg_off == reg_max)) {
94
+ /* Find the active elements. */
95
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, 1 << msz)) {
96
/* The entire predicate was false; no load occurs. */
97
memset(vd, 0, reg_max);
98
return;
99
}
100
- mem_off = reg_off >> diffsz;
101
+ reg_off = info.reg_off_first[0];
102
103
- /*
104
- * If the (remaining) load is entirely within a single page, then:
105
- * For softmmu, and the tlb hits, then no faults will occur;
106
- * For user-only, either the first load will fault or none will.
107
- * We can thus perform the load directly to the destination and
108
- * Vd will be unmodified on any exception path.
109
- */
110
- split = max_for_page(addr, mem_off, mem_max);
111
- if (likely(split == mem_max)) {
112
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
113
- if (test_host_page(host)) {
114
- i = reg_off;
115
- host -= mem_off;
116
- do {
117
- host_fn(vd, i, host + (i >> diffsz));
118
- i = find_next_active(vg, i + (1 << esz), reg_max, esz);
119
- } while (i < reg_max);
120
- /* After any fault, zero any leading inactive elements. */
121
+ /* Probe the page(s). */
122
+ if (!sve_cont_ldst_pages(&info, fault, env, addr, MMU_DATA_LOAD, retaddr)) {
123
+ /* Fault on first element. */
124
+ tcg_debug_assert(fault == FAULT_NO);
125
+ memset(vd, 0, reg_max);
126
+ goto do_fault;
127
+ }
128
+
129
+ mem_off = info.mem_off_first[0];
130
+ flags = info.page[0].flags;
131
+
132
+ if (fault == FAULT_FIRST) {
133
+ /*
134
+ * Special handling of the first active element,
135
+ * if it crosses a page boundary or is MMIO.
136
+ */
137
+ bool is_split = mem_off == info.mem_off_split;
138
+ /* TODO: MTE check. */
139
+ if (unlikely(flags != 0) || unlikely(is_split)) {
140
+ /*
141
+ * Use the slow path for cross-page handling.
142
+ * Might trap for MMIO or watchpoints.
143
+ */
144
+ tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
145
+
146
+ /* After any fault, zero the other elements. */
147
swap_memzero(vd, reg_off);
148
- return;
149
+ reg_off += 1 << esz;
150
+ mem_off += 1 << msz;
151
+ swap_memzero(vd + reg_off, reg_max - reg_off);
152
+
153
+ if (is_split) {
154
+ goto second_page;
155
+ }
41
+ }
156
+ } else {
42
break;
157
+ memset(vd, 0, reg_max);
43
default:
158
+ }
44
g_assert_not_reached();
159
+ } else {
45
}
160
+ memset(vd, 0, reg_max);
46
+ which = 2;
161
+ if (unlikely(mem_off == info.mem_off_split)) {
47
} else {
162
+ /* The first active element crosses a page boundary. */
48
FloatClass cls[3] = { a->cls, b->cls, c->cls };
163
+ flags |= info.page[1].flags;
49
Float3NaNPropRule rule = s->float_3nan_prop_rule;
164
+ if (unlikely(flags & TLB_MMIO)) {
50
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
165
+ /* Some page is MMIO, see below. */
166
+ goto do_fault;
167
+ }
168
+ if (unlikely(flags & TLB_WATCHPOINT) &&
169
+ (cpu_watchpoint_address_matches
170
+ (env_cpu(env), addr + mem_off, 1 << msz)
171
+ & BP_MEM_READ)) {
172
+ /* Watchpoint hit, see below. */
173
+ goto do_fault;
174
+ }
175
+ /* TODO: MTE check. */
176
+ /*
177
+ * Use the slow path for cross-page handling.
178
+ * This is RAM, without a watchpoint, and will not trap.
179
+ */
180
+ tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
181
+ goto second_page;
182
}
51
}
183
}
52
}
184
53
185
/*
54
- if (which == 3) {
186
- * Perform one normal read, which will fault or not.
55
- parts_default_nan(a, s);
187
- * But it is likely to bring the page into the tlb.
56
- return a;
188
+ * From this point on, all memory operations are MemSingleNF.
189
+ *
190
+ * Per the MemSingleNF pseudocode, a no-fault load from Device memory
191
+ * must not actually hit the bus -- it returns (UNKNOWN, FAULT) instead.
192
+ *
193
+ * Unfortuately we do not have access to the memory attributes from the
194
+ * PTE to tell Device memory from Normal memory. So we make a mostly
195
+ * correct check, and indicate (UNKNOWN, FAULT) for any MMIO.
196
+ * This gives the right answer for the common cases of "Normal memory,
197
+ * backed by host RAM" and "Device memory, backed by MMIO".
198
+ * The architecture allows us to suppress an NF load and return
199
+ * (UNKNOWN, FAULT) for any reason, so our behaviour for the corner
200
+ * case of "Normal memory, backed by MMIO" is permitted. The case we
201
+ * get wrong is "Device memory, backed by host RAM", for which we
202
+ * should return (UNKNOWN, FAULT) for but do not.
203
+ *
204
+ * Similarly, CPU_BP breakpoints would raise exceptions, and so
205
+ * return (UNKNOWN, FAULT). For simplicity, we consider gdb and
206
+ * architectural breakpoints the same.
207
*/
208
- tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
209
+ if (unlikely(flags & TLB_MMIO)) {
210
+ goto do_fault;
211
+ }
212
213
- /* After any fault, zero any leading predicated false elts. */
214
- swap_memzero(vd, reg_off);
215
- mem_off += 1 << msz;
216
- reg_off += 1 << esz;
217
+ reg_last = info.reg_off_last[0];
218
+ host = info.page[0].host;
219
220
- /* Try again to read the balance of the page. */
221
- split = max_for_page(addr, mem_off - 1, mem_max);
222
- if (split >= (1 << msz)) {
223
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
224
- if (host) {
225
- host -= mem_off;
226
- do {
227
+ do {
228
+ uint64_t pg = *(uint64_t *)(vg + (reg_off >> 3));
229
+ do {
230
+ if ((pg >> (reg_off & 63)) & 1) {
231
+ if (unlikely(flags & TLB_WATCHPOINT) &&
232
+ (cpu_watchpoint_address_matches
233
+ (env_cpu(env), addr + mem_off, 1 << msz)
234
+ & BP_MEM_READ)) {
235
+ goto do_fault;
236
+ }
237
+ /* TODO: MTE check. */
238
host_fn(vd, reg_off, host + mem_off);
239
- reg_off += 1 << esz;
240
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
241
- mem_off = reg_off >> diffsz;
242
- } while (split - mem_off >= (1 << msz));
243
- }
244
- }
57
- }
245
-
58
-
246
- record_fault(env, reg_off, reg_max);
59
switch (which) {
247
-}
60
case 0:
248
-
61
break;
249
-/*
62
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
250
- * Common helper for all contiguous no-fault loads.
63
parts_silence_nan(a, s);
251
- */
252
-static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
253
- uint32_t desc, const int esz, const int msz,
254
- sve_ldst1_host_fn *host_fn)
255
-{
256
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
257
- void *vd = &env->vfp.zregs[rd];
258
- const int diffsz = esz - msz;
259
- const intptr_t reg_max = simd_oprsz(desc);
260
- const intptr_t mem_max = reg_max >> diffsz;
261
- const int mmu_idx = cpu_mmu_index(env, false);
262
- intptr_t split, reg_off, mem_off;
263
- void *host;
264
-
265
-#ifdef CONFIG_USER_ONLY
266
- host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_idx);
267
- if (likely(page_check_range(addr, mem_max, PAGE_READ) == 0)) {
268
- /* The entire operation is valid and will not fault. */
269
- reg_off = 0;
270
- do {
271
- mem_off = reg_off >> diffsz;
272
- host_fn(vd, reg_off, host + mem_off);
273
+ }
274
reg_off += 1 << esz;
275
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
276
- } while (reg_off < reg_max);
277
- return;
278
- }
279
-#endif
280
+ mem_off += 1 << msz;
281
+ } while (reg_off <= reg_last && (reg_off & 63));
282
+ } while (reg_off <= reg_last);
283
284
- /* There will be no fault, so we may modify in advance. */
285
- memset(vd, 0, reg_max);
286
-
287
- /* Skip to the first active element. */
288
- reg_off = find_next_active(vg, 0, reg_max, esz);
289
- if (unlikely(reg_off == reg_max)) {
290
- /* The entire predicate was false; no load occurs. */
291
- return;
292
- }
293
- mem_off = reg_off >> diffsz;
294
-
295
-#ifdef CONFIG_USER_ONLY
296
- if (page_check_range(addr + mem_off, 1 << msz, PAGE_READ) == 0) {
297
- /* At least one load is valid; take the rest of the page. */
298
- split = max_for_page(addr, mem_off + (1 << msz) - 1, mem_max);
299
- do {
300
- host_fn(vd, reg_off, host + mem_off);
301
- reg_off += 1 << esz;
302
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
303
- mem_off = reg_off >> diffsz;
304
- } while (split - mem_off >= (1 << msz));
305
- }
306
-#else
307
/*
308
- * If the address is not in the TLB, we have no way to bring the
309
- * entry into the TLB without also risking a fault. Note that
310
- * the corollary is that we never load from an address not in RAM.
311
- *
312
- * This last is out of spec, in a weird corner case.
313
- * Per the MemNF/MemSingleNF pseudocode, a NF load from Device memory
314
- * must not actually hit the bus -- it returns UNKNOWN data instead.
315
- * But if you map non-RAM with Normal memory attributes and do a NF
316
- * load then it should access the bus. (Nobody ought actually do this
317
- * in the real world, obviously.)
318
- *
319
- * Then there are the annoying special cases with watchpoints...
320
- * TODO: Add a form of non-faulting loads using cc->tlb_fill(probe=true).
321
+ * MemSingleNF is allowed to fail for any reason. We have special
322
+ * code above to handle the first element crossing a page boundary.
323
+ * As an implementation choice, decline to handle a cross-page element
324
+ * in any other position.
325
*/
326
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
327
- split = max_for_page(addr, mem_off, mem_max);
328
- if (host && split >= (1 << msz)) {
329
- host -= mem_off;
330
- do {
331
- host_fn(vd, reg_off, host + mem_off);
332
- reg_off += 1 << esz;
333
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
334
- mem_off = reg_off >> diffsz;
335
- } while (split - mem_off >= (1 << msz));
336
+ reg_off = info.reg_off_split;
337
+ if (reg_off >= 0) {
338
+ goto do_fault;
339
}
64
}
340
-#endif
65
return a;
341
342
+ second_page:
343
+ reg_off = info.reg_off_first[1];
344
+ if (likely(reg_off < 0)) {
345
+ /* No active elements on the second page. All done. */
346
+ return;
347
+ }
348
+
66
+
349
+ /*
67
+ default_nan:
350
+ * MemSingleNF is allowed to fail for any reason. As an implementation
68
+ parts_default_nan(a, s);
351
+ * choice, decline to handle elements on the second page. This should
69
+ return a;
352
+ * be low frequency as the guest walks through memory -- the next
353
+ * iteration of the guest's loop should be aligned on the page boundary,
354
+ * and then all following iterations will stay aligned.
355
+ */
356
+
357
+ do_fault:
358
record_fault(env, reg_off, reg_max);
359
}
70
}
360
71
361
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
72
/*
362
void HELPER(sve_ldff1##PART##_r)(CPUARMState *env, void *vg, \
363
target_ulong addr, uint32_t desc) \
364
{ \
365
- sve_ldff1_r(env, vg, addr, desc, GETPC(), ESZ, 0, \
366
- sve_ld1##PART##_host, sve_ld1##PART##_tlb); \
367
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, FAULT_FIRST, \
368
+ sve_ld1##PART##_host, sve_ld1##PART##_tlb); \
369
} \
370
void HELPER(sve_ldnf1##PART##_r)(CPUARMState *env, void *vg, \
371
target_ulong addr, uint32_t desc) \
372
{ \
373
- sve_ldnf1_r(env, vg, addr, desc, ESZ, 0, sve_ld1##PART##_host); \
374
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, FAULT_NO, \
375
+ sve_ld1##PART##_host, sve_ld1##PART##_tlb); \
376
}
377
378
#define DO_LDFF1_LDNF1_2(PART, ESZ, MSZ) \
379
void HELPER(sve_ldff1##PART##_le_r)(CPUARMState *env, void *vg, \
380
target_ulong addr, uint32_t desc) \
381
{ \
382
- sve_ldff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
383
- sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \
384
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_FIRST, \
385
+ sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \
386
} \
387
void HELPER(sve_ldnf1##PART##_le_r)(CPUARMState *env, void *vg, \
388
target_ulong addr, uint32_t desc) \
389
{ \
390
- sve_ldnf1_r(env, vg, addr, desc, ESZ, MSZ, sve_ld1##PART##_le_host); \
391
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_NO, \
392
+ sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \
393
} \
394
void HELPER(sve_ldff1##PART##_be_r)(CPUARMState *env, void *vg, \
395
target_ulong addr, uint32_t desc) \
396
{ \
397
- sve_ldff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
398
- sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \
399
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_FIRST, \
400
+ sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \
401
} \
402
void HELPER(sve_ldnf1##PART##_be_r)(CPUARMState *env, void *vg, \
403
target_ulong addr, uint32_t desc) \
404
{ \
405
- sve_ldnf1_r(env, vg, addr, desc, ESZ, MSZ, sve_ld1##PART##_be_host); \
406
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_NO, \
407
+ sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \
408
}
409
410
-DO_LDFF1_LDNF1_1(bb, 0)
411
-DO_LDFF1_LDNF1_1(bhu, 1)
412
-DO_LDFF1_LDNF1_1(bhs, 1)
413
-DO_LDFF1_LDNF1_1(bsu, 2)
414
-DO_LDFF1_LDNF1_1(bss, 2)
415
-DO_LDFF1_LDNF1_1(bdu, 3)
416
-DO_LDFF1_LDNF1_1(bds, 3)
417
+DO_LDFF1_LDNF1_1(bb, MO_8)
418
+DO_LDFF1_LDNF1_1(bhu, MO_16)
419
+DO_LDFF1_LDNF1_1(bhs, MO_16)
420
+DO_LDFF1_LDNF1_1(bsu, MO_32)
421
+DO_LDFF1_LDNF1_1(bss, MO_32)
422
+DO_LDFF1_LDNF1_1(bdu, MO_64)
423
+DO_LDFF1_LDNF1_1(bds, MO_64)
424
425
-DO_LDFF1_LDNF1_2(hh, 1, 1)
426
-DO_LDFF1_LDNF1_2(hsu, 2, 1)
427
-DO_LDFF1_LDNF1_2(hss, 2, 1)
428
-DO_LDFF1_LDNF1_2(hdu, 3, 1)
429
-DO_LDFF1_LDNF1_2(hds, 3, 1)
430
+DO_LDFF1_LDNF1_2(hh, MO_16, MO_16)
431
+DO_LDFF1_LDNF1_2(hsu, MO_32, MO_16)
432
+DO_LDFF1_LDNF1_2(hss, MO_32, MO_16)
433
+DO_LDFF1_LDNF1_2(hdu, MO_64, MO_16)
434
+DO_LDFF1_LDNF1_2(hds, MO_64, MO_16)
435
436
-DO_LDFF1_LDNF1_2(ss, 2, 2)
437
-DO_LDFF1_LDNF1_2(sdu, 3, 2)
438
-DO_LDFF1_LDNF1_2(sds, 3, 2)
439
+DO_LDFF1_LDNF1_2(ss, MO_32, MO_32)
440
+DO_LDFF1_LDNF1_2(sdu, MO_64, MO_32)
441
+DO_LDFF1_LDNF1_2(sds, MO_64, MO_32)
442
443
-DO_LDFF1_LDNF1_2(dd, 3, 3)
444
+DO_LDFF1_LDNF1_2(dd, MO_64, MO_64)
445
446
#undef DO_LDFF1_LDNF1_1
447
#undef DO_LDFF1_LDNF1_2
448
--
73
--
449
2.20.1
74
2.34.1
450
75
451
76
diff view generated by jsdifflib
[PULL 34/34] target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)
[PULL 63/72] softfloat: Remove which from parts_pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
DUP (indexed) can duplicate 128-bit elements, so using esz
3
Assign the pointer return value to 'a' directly,
4
unconditionally can assert in tcg_gen_gvec_dup_imm.
4
rather than going through an intermediary index.
5
5
6
Fixes: 8711e71f9cbb
7
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
Message-id: 20241203203949.483774-5-richard.henderson@linaro.org
11
Message-id: 20200507172352.15418-5-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
target/arm/translate-sve.c | 6 +++++-
11
fpu/softfloat-parts.c.inc | 32 ++++++++++----------------------
15
1 file changed, 5 insertions(+), 1 deletion(-)
12
1 file changed, 10 insertions(+), 22 deletions(-)
16
13
17
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate-sve.c
16
--- a/fpu/softfloat-parts.c.inc
20
+++ b/target/arm/translate-sve.c
17
+++ b/fpu/softfloat-parts.c.inc
21
@@ -XXX,XX +XXX,XX @@ static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a)
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
22
unsigned nofs = vec_reg_offset(s, a->rn, index, esz);
19
FloatPartsN *c, float_status *s,
23
tcg_gen_gvec_dup_mem(esz, dofs, nofs, vsz, vsz);
20
int ab_mask, int abc_mask)
21
{
22
- int which;
23
bool infzero = (ab_mask == float_cmask_infzero);
24
bool have_snan = (abc_mask & float_cmask_snan);
25
+ FloatPartsN *ret;
26
27
if (unlikely(have_snan)) {
28
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
30
default:
31
g_assert_not_reached();
32
}
33
- which = 2;
34
+ ret = c;
35
} else {
36
- FloatClass cls[3] = { a->cls, b->cls, c->cls };
37
+ FloatPartsN *val[3] = { a, b, c };
38
Float3NaNPropRule rule = s->float_3nan_prop_rule;
39
40
assert(rule != float_3nan_prop_none);
41
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
42
/* We have at least one SNaN input and should prefer it */
43
do {
44
- which = rule & R_3NAN_1ST_MASK;
45
+ ret = val[rule & R_3NAN_1ST_MASK];
46
rule >>= R_3NAN_1ST_LENGTH;
47
- } while (!is_snan(cls[which]));
48
+ } while (!is_snan(ret->cls));
24
} else {
49
} else {
25
- tcg_gen_gvec_dup_imm(esz, dofs, vsz, vsz, 0);
50
do {
26
+ /*
51
- which = rule & R_3NAN_1ST_MASK;
27
+ * While dup_mem handles 128-bit elements, dup_imm does not.
52
+ ret = val[rule & R_3NAN_1ST_MASK];
28
+ * Thankfully element size doesn't matter for splatting zero.
53
rule >>= R_3NAN_1ST_LENGTH;
29
+ */
54
- } while (!is_nan(cls[which]));
30
+ tcg_gen_gvec_dup_imm(MO_64, dofs, vsz, vsz, 0);
55
+ } while (!is_nan(ret->cls));
31
}
56
}
32
}
57
}
33
return true;
58
59
- switch (which) {
60
- case 0:
61
- break;
62
- case 1:
63
- a = b;
64
- break;
65
- case 2:
66
- a = c;
67
- break;
68
- default:
69
- g_assert_not_reached();
70
+ if (is_snan(ret->cls)) {
71
+ parts_silence_nan(ret, s);
72
}
73
- if (is_snan(a->cls)) {
74
- parts_silence_nan(a, s);
75
- }
76
- return a;
77
+ return ret;
78
79
default_nan:
80
parts_default_nan(a, s);
34
--
81
--
35
2.20.1
82
2.34.1
36
83
37
84
diff view generated by jsdifflib
[PULL 09/34] exec: Fix cpu_watchpoint_address_matches address length
[PULL 64/72] softfloat: Pad array size in pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The only caller of cpu_watchpoint_address_matches passes
3
While all indices into val[] should be in [0-2], the mask
4
TARGET_PAGE_SIZE, so the bug is not currently visible.
4
applied is two bits. To help static analysis see there is
5
no possibility of read beyond the end of the array, pad the
6
array to 4 entries, with the final being (implicitly) NULL.
5
7
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20200508154359.7494-3-richard.henderson@linaro.org
10
Message-id: 20241203203949.483774-6-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
---
12
exec.c | 2 +-
13
fpu/softfloat-parts.c.inc | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
15
diff --git a/exec.c b/exec.c
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/exec.c
18
--- a/fpu/softfloat-parts.c.inc
18
+++ b/exec.c
19
+++ b/fpu/softfloat-parts.c.inc
19
@@ -XXX,XX +XXX,XX @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
20
int ret = 0;
21
22
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
23
- if (watchpoint_address_matches(wp, addr, TARGET_PAGE_SIZE)) {
24
+ if (watchpoint_address_matches(wp, addr, len)) {
25
ret |= wp->flags;
26
}
21
}
27
}
22
ret = c;
23
} else {
24
- FloatPartsN *val[3] = { a, b, c };
25
+ FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c };
26
Float3NaNPropRule rule = s->float_3nan_prop_rule;
27
28
assert(rule != float_3nan_prop_none);
28
--
29
--
29
2.20.1
30
2.34.1
30
31
31
32
diff view generated by jsdifflib
[PULL 22/34] target/arm: Use SVEContLdSt for contiguous stores
[PULL 65/72] softfloat: Move propagateFloatx80NaN to softfloat.c
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Follow the model set up for contiguous loads. This handles
3
This function is part of the public interface and
4
watchpoints correctly for contiguous stores, recognizing the
4
is not "specialized" to any target in any way.
5
exception before any changes to memory.
6
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241203203949.483774-7-richard.henderson@linaro.org
9
Message-id: 20200508154359.7494-16-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/sve_helper.c | 285 ++++++++++++++++++++++------------------
11
fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++
13
1 file changed, 159 insertions(+), 126 deletions(-)
12
fpu/softfloat-specialize.c.inc | 52 ----------------------------------
13
2 files changed, 52 insertions(+), 52 deletions(-)
14
14
15
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/sve_helper.c
17
--- a/fpu/softfloat.c
18
+++ b/target/arm/sve_helper.c
18
+++ b/fpu/softfloat.c
19
@@ -XXX,XX +XXX,XX @@ static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
20
*(TYPEE *)(vd + H(reg_off)) = val; \
20
*zExpPtr = 1 - shiftCount;
21
}
21
}
22
22
23
+#define DO_ST_HOST(NAME, H, TYPEE, TYPEM, HOST) \
23
+/*----------------------------------------------------------------------------
24
+static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
24
+| Takes two extended double-precision floating-point values `a' and `b', one
25
+{ HOST(host, (TYPEM)*(TYPEE *)(vd + H(reg_off))); }
25
+| of which is a NaN, and returns the appropriate NaN result. If either `a' or
26
+| `b' is a signaling NaN, the invalid exception is raised.
27
+*----------------------------------------------------------------------------*/
26
+
28
+
27
#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \
29
+floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
28
static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
30
+{
29
target_ulong addr, uintptr_t ra) \
31
+ bool aIsLargerSignificand;
30
@@ -XXX,XX +XXX,XX @@ DO_LD_PRIM_1(ld1bdu, , uint64_t, uint8_t)
32
+ FloatClass a_cls, b_cls;
31
DO_LD_PRIM_1(ld1bds, , uint64_t, int8_t)
32
33
#define DO_ST_PRIM_1(NAME, H, TE, TM) \
34
+ DO_ST_HOST(st1##NAME, H, TE, TM, stb_p) \
35
DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra)
36
37
DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t)
38
@@ -XXX,XX +XXX,XX @@ DO_ST_PRIM_1(bd, , uint64_t, uint8_t)
39
DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra)
40
41
#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \
42
+ DO_ST_HOST(st1##NAME##_be, H, TE, TM, ST##_be_p) \
43
+ DO_ST_HOST(st1##NAME##_le, H, TE, TM, ST##_le_p) \
44
DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \
45
DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra)
46
47
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_LDNF1_2(dd, MO_64, MO_64)
48
#undef DO_LDFF1_LDNF1_2
49
50
/*
51
- * Common helpers for all contiguous 1,2,3,4-register predicated stores.
52
+ * Common helper for all contiguous 1,2,3,4-register predicated stores.
53
*/
54
-static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
55
- uint32_t desc, const uintptr_t ra,
56
- const int esize, const int msize,
57
- sve_ldst1_tlb_fn *tlb_fn)
58
+
33
+
59
+static inline QEMU_ALWAYS_INLINE
34
+ /* This is not complete, but is good enough for pickNaN. */
60
+void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, uint32_t desc,
35
+ a_cls = (!floatx80_is_any_nan(a)
61
+ const uintptr_t retaddr, const int esz,
36
+ ? float_class_normal
62
+ const int msz, const int N,
37
+ : floatx80_is_signaling_nan(a, status)
63
+ sve_ldst1_host_fn *host_fn,
38
+ ? float_class_snan
64
+ sve_ldst1_tlb_fn *tlb_fn)
39
+ : float_class_qnan);
65
{
40
+ b_cls = (!floatx80_is_any_nan(b)
66
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
41
+ ? float_class_normal
67
- intptr_t i, oprsz = simd_oprsz(desc);
42
+ : floatx80_is_signaling_nan(b, status)
68
- void *vd = &env->vfp.zregs[rd];
43
+ ? float_class_snan
69
+ const intptr_t reg_max = simd_oprsz(desc);
44
+ : float_class_qnan);
70
+ intptr_t reg_off, reg_last, mem_off;
45
+
71
+ SVEContLdSt info;
46
+ if (is_snan(a_cls) || is_snan(b_cls)) {
72
+ void *host;
47
+ float_raise(float_flag_invalid, status);
73
+ int i, flags;
74
75
- for (i = 0; i < oprsz; ) {
76
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
77
- do {
78
- if (pg & 1) {
79
- tlb_fn(env, vd, i, addr, ra);
80
+ /* Find the active elements. */
81
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, N << msz)) {
82
+ /* The entire predicate was false; no store occurs. */
83
+ return;
84
+ }
48
+ }
85
+
49
+
86
+ /* Probe the page(s). Exit with exception for any invalid page. */
50
+ if (status->default_nan_mode) {
87
+ sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_STORE, retaddr);
51
+ return floatx80_default_nan(status);
88
+
89
+ /* Handle watchpoints for all active elements. */
90
+ sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, N << msz,
91
+ BP_MEM_WRITE, retaddr);
92
+
93
+ /* TODO: MTE check. */
94
+
95
+ flags = info.page[0].flags | info.page[1].flags;
96
+ if (unlikely(flags != 0)) {
97
+#ifdef CONFIG_USER_ONLY
98
+ g_assert_not_reached();
99
+#else
100
+ /*
101
+ * At least one page includes MMIO.
102
+ * Any bus operation can fail with cpu_transaction_failed,
103
+ * which for ARM will raise SyncExternal. We cannot avoid
104
+ * this fault and will leave with the store incomplete.
105
+ */
106
+ mem_off = info.mem_off_first[0];
107
+ reg_off = info.reg_off_first[0];
108
+ reg_last = info.reg_off_last[1];
109
+ if (reg_last < 0) {
110
+ reg_last = info.reg_off_split;
111
+ if (reg_last < 0) {
112
+ reg_last = info.reg_off_last[0];
113
}
114
- i += esize, pg >>= esize;
115
- addr += msize;
116
- } while (i & 15);
117
+ }
118
+
119
+ do {
120
+ uint64_t pg = vg[reg_off >> 6];
121
+ do {
122
+ if ((pg >> (reg_off & 63)) & 1) {
123
+ for (i = 0; i < N; ++i) {
124
+ tlb_fn(env, &env->vfp.zregs[(rd + i) & 31], reg_off,
125
+ addr + mem_off + (i << msz), retaddr);
126
+ }
127
+ }
128
+ reg_off += 1 << esz;
129
+ mem_off += N << msz;
130
+ } while (reg_off & 63);
131
+ } while (reg_off <= reg_last);
132
+ return;
133
+#endif
134
+ }
52
+ }
135
+
53
+
136
+ mem_off = info.mem_off_first[0];
54
+ if (a.low < b.low) {
137
+ reg_off = info.reg_off_first[0];
55
+ aIsLargerSignificand = 0;
138
+ reg_last = info.reg_off_last[0];
56
+ } else if (b.low < a.low) {
139
+ host = info.page[0].host;
57
+ aIsLargerSignificand = 1;
140
+
58
+ } else {
141
+ while (reg_off <= reg_last) {
59
+ aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
142
+ uint64_t pg = vg[reg_off >> 6];
143
+ do {
144
+ if ((pg >> (reg_off & 63)) & 1) {
145
+ for (i = 0; i < N; ++i) {
146
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
147
+ host + mem_off + (i << msz));
148
+ }
149
+ }
150
+ reg_off += 1 << esz;
151
+ mem_off += N << msz;
152
+ } while (reg_off <= reg_last && (reg_off & 63));
153
+ }
60
+ }
154
+
61
+
155
+ /*
62
+ if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
156
+ * Use the slow path to manage the cross-page misalignment.
63
+ if (is_snan(b_cls)) {
157
+ * But we know this is RAM and cannot trap.
64
+ return floatx80_silence_nan(b, status);
158
+ */
159
+ mem_off = info.mem_off_split;
160
+ if (unlikely(mem_off >= 0)) {
161
+ reg_off = info.reg_off_split;
162
+ for (i = 0; i < N; ++i) {
163
+ tlb_fn(env, &env->vfp.zregs[(rd + i) & 31], reg_off,
164
+ addr + mem_off + (i << msz), retaddr);
165
+ }
65
+ }
66
+ return b;
67
+ } else {
68
+ if (is_snan(a_cls)) {
69
+ return floatx80_silence_nan(a, status);
70
+ }
71
+ return a;
166
+ }
72
+ }
73
+}
167
+
74
+
168
+ mem_off = info.mem_off_first[1];
75
/*----------------------------------------------------------------------------
169
+ if (unlikely(mem_off >= 0)) {
76
| Takes an abstract floating-point value having sign `zSign', exponent `zExp',
170
+ reg_off = info.reg_off_first[1];
77
| and extended significand formed by the concatenation of `zSig0' and `zSig1',
171
+ reg_last = info.reg_off_last[1];
78
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
172
+ host = info.page[1].host;
79
index XXXXXXX..XXXXXXX 100644
173
+
80
--- a/fpu/softfloat-specialize.c.inc
174
+ do {
81
+++ b/fpu/softfloat-specialize.c.inc
175
+ uint64_t pg = vg[reg_off >> 6];
82
@@ -XXX,XX +XXX,XX @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
176
+ do {
83
return a;
177
+ if ((pg >> (reg_off & 63)) & 1) {
178
+ for (i = 0; i < N; ++i) {
179
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
180
+ host + mem_off + (i << msz));
181
+ }
182
+ }
183
+ reg_off += 1 << esz;
184
+ mem_off += N << msz;
185
+ } while (reg_off & 63);
186
+ } while (reg_off <= reg_last);
187
}
188
}
84
}
189
85
190
-static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
86
-/*----------------------------------------------------------------------------
191
- uint32_t desc, const uintptr_t ra,
87
-| Takes two extended double-precision floating-point values `a' and `b', one
192
- const int esize, const int msize,
88
-| of which is a NaN, and returns the appropriate NaN result. If either `a' or
193
- sve_ldst1_tlb_fn *tlb_fn)
89
-| `b' is a signaling NaN, the invalid exception is raised.
90
-*----------------------------------------------------------------------------*/
91
-
92
-floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
194
-{
93
-{
195
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
94
- bool aIsLargerSignificand;
196
- intptr_t i, oprsz = simd_oprsz(desc);
95
- FloatClass a_cls, b_cls;
197
- void *d1 = &env->vfp.zregs[rd];
198
- void *d2 = &env->vfp.zregs[(rd + 1) & 31];
199
-
96
-
200
- for (i = 0; i < oprsz; ) {
97
- /* This is not complete, but is good enough for pickNaN. */
201
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
98
- a_cls = (!floatx80_is_any_nan(a)
202
- do {
99
- ? float_class_normal
203
- if (pg & 1) {
100
- : floatx80_is_signaling_nan(a, status)
204
- tlb_fn(env, d1, i, addr, ra);
101
- ? float_class_snan
205
- tlb_fn(env, d2, i, addr + msize, ra);
102
- : float_class_qnan);
206
- }
103
- b_cls = (!floatx80_is_any_nan(b)
207
- i += esize, pg >>= esize;
104
- ? float_class_normal
208
- addr += 2 * msize;
105
- : floatx80_is_signaling_nan(b, status)
209
- } while (i & 15);
106
- ? float_class_snan
107
- : float_class_qnan);
108
-
109
- if (is_snan(a_cls) || is_snan(b_cls)) {
110
- float_raise(float_flag_invalid, status);
111
- }
112
-
113
- if (status->default_nan_mode) {
114
- return floatx80_default_nan(status);
115
- }
116
-
117
- if (a.low < b.low) {
118
- aIsLargerSignificand = 0;
119
- } else if (b.low < a.low) {
120
- aIsLargerSignificand = 1;
121
- } else {
122
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
123
- }
124
-
125
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
126
- if (is_snan(b_cls)) {
127
- return floatx80_silence_nan(b, status);
128
- }
129
- return b;
130
- } else {
131
- if (is_snan(a_cls)) {
132
- return floatx80_silence_nan(a, status);
133
- }
134
- return a;
210
- }
135
- }
211
-}
136
-}
212
-
137
-
213
-static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
138
/*----------------------------------------------------------------------------
214
- uint32_t desc, const uintptr_t ra,
139
| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
215
- const int esize, const int msize,
140
| NaN; otherwise returns 0.
216
- sve_ldst1_tlb_fn *tlb_fn)
217
-{
218
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
219
- intptr_t i, oprsz = simd_oprsz(desc);
220
- void *d1 = &env->vfp.zregs[rd];
221
- void *d2 = &env->vfp.zregs[(rd + 1) & 31];
222
- void *d3 = &env->vfp.zregs[(rd + 2) & 31];
223
-
224
- for (i = 0; i < oprsz; ) {
225
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
226
- do {
227
- if (pg & 1) {
228
- tlb_fn(env, d1, i, addr, ra);
229
- tlb_fn(env, d2, i, addr + msize, ra);
230
- tlb_fn(env, d3, i, addr + 2 * msize, ra);
231
- }
232
- i += esize, pg >>= esize;
233
- addr += 3 * msize;
234
- } while (i & 15);
235
- }
236
-}
237
-
238
-static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
239
- uint32_t desc, const uintptr_t ra,
240
- const int esize, const int msize,
241
- sve_ldst1_tlb_fn *tlb_fn)
242
-{
243
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
244
- intptr_t i, oprsz = simd_oprsz(desc);
245
- void *d1 = &env->vfp.zregs[rd];
246
- void *d2 = &env->vfp.zregs[(rd + 1) & 31];
247
- void *d3 = &env->vfp.zregs[(rd + 2) & 31];
248
- void *d4 = &env->vfp.zregs[(rd + 3) & 31];
249
-
250
- for (i = 0; i < oprsz; ) {
251
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
252
- do {
253
- if (pg & 1) {
254
- tlb_fn(env, d1, i, addr, ra);
255
- tlb_fn(env, d2, i, addr + msize, ra);
256
- tlb_fn(env, d3, i, addr + 2 * msize, ra);
257
- tlb_fn(env, d4, i, addr + 3 * msize, ra);
258
- }
259
- i += esize, pg >>= esize;
260
- addr += 4 * msize;
261
- } while (i & 15);
262
- }
263
-}
264
-
265
-#define DO_STN_1(N, NAME, ESIZE) \
266
-void QEMU_FLATTEN HELPER(sve_st##N##NAME##_r) \
267
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
268
+#define DO_STN_1(N, NAME, ESZ) \
269
+void HELPER(sve_st##N##NAME##_r)(CPUARMState *env, void *vg, \
270
+ target_ulong addr, uint32_t desc) \
271
{ \
272
- sve_st##N##_r(env, vg, addr, desc, GETPC(), ESIZE, 1, \
273
- sve_st1##NAME##_tlb); \
274
+ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, N, \
275
+ sve_st1##NAME##_host, sve_st1##NAME##_tlb); \
276
}
277
278
-#define DO_STN_2(N, NAME, ESIZE, MSIZE) \
279
-void QEMU_FLATTEN HELPER(sve_st##N##NAME##_le_r) \
280
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
281
+#define DO_STN_2(N, NAME, ESZ, MSZ) \
282
+void HELPER(sve_st##N##NAME##_le_r)(CPUARMState *env, void *vg, \
283
+ target_ulong addr, uint32_t desc) \
284
{ \
285
- sve_st##N##_r(env, vg, addr, desc, GETPC(), ESIZE, MSIZE, \
286
- sve_st1##NAME##_le_tlb); \
287
+ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, \
288
+ sve_st1##NAME##_le_host, sve_st1##NAME##_le_tlb); \
289
} \
290
-void QEMU_FLATTEN HELPER(sve_st##N##NAME##_be_r) \
291
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
292
+void HELPER(sve_st##N##NAME##_be_r)(CPUARMState *env, void *vg, \
293
+ target_ulong addr, uint32_t desc) \
294
{ \
295
- sve_st##N##_r(env, vg, addr, desc, GETPC(), ESIZE, MSIZE, \
296
- sve_st1##NAME##_be_tlb); \
297
+ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, \
298
+ sve_st1##NAME##_be_host, sve_st1##NAME##_be_tlb); \
299
}
300
301
-DO_STN_1(1, bb, 1)
302
-DO_STN_1(1, bh, 2)
303
-DO_STN_1(1, bs, 4)
304
-DO_STN_1(1, bd, 8)
305
-DO_STN_1(2, bb, 1)
306
-DO_STN_1(3, bb, 1)
307
-DO_STN_1(4, bb, 1)
308
+DO_STN_1(1, bb, MO_8)
309
+DO_STN_1(1, bh, MO_16)
310
+DO_STN_1(1, bs, MO_32)
311
+DO_STN_1(1, bd, MO_64)
312
+DO_STN_1(2, bb, MO_8)
313
+DO_STN_1(3, bb, MO_8)
314
+DO_STN_1(4, bb, MO_8)
315
316
-DO_STN_2(1, hh, 2, 2)
317
-DO_STN_2(1, hs, 4, 2)
318
-DO_STN_2(1, hd, 8, 2)
319
-DO_STN_2(2, hh, 2, 2)
320
-DO_STN_2(3, hh, 2, 2)
321
-DO_STN_2(4, hh, 2, 2)
322
+DO_STN_2(1, hh, MO_16, MO_16)
323
+DO_STN_2(1, hs, MO_32, MO_16)
324
+DO_STN_2(1, hd, MO_64, MO_16)
325
+DO_STN_2(2, hh, MO_16, MO_16)
326
+DO_STN_2(3, hh, MO_16, MO_16)
327
+DO_STN_2(4, hh, MO_16, MO_16)
328
329
-DO_STN_2(1, ss, 4, 4)
330
-DO_STN_2(1, sd, 8, 4)
331
-DO_STN_2(2, ss, 4, 4)
332
-DO_STN_2(3, ss, 4, 4)
333
-DO_STN_2(4, ss, 4, 4)
334
+DO_STN_2(1, ss, MO_32, MO_32)
335
+DO_STN_2(1, sd, MO_64, MO_32)
336
+DO_STN_2(2, ss, MO_32, MO_32)
337
+DO_STN_2(3, ss, MO_32, MO_32)
338
+DO_STN_2(4, ss, MO_32, MO_32)
339
340
-DO_STN_2(1, dd, 8, 8)
341
-DO_STN_2(2, dd, 8, 8)
342
-DO_STN_2(3, dd, 8, 8)
343
-DO_STN_2(4, dd, 8, 8)
344
+DO_STN_2(1, dd, MO_64, MO_64)
345
+DO_STN_2(2, dd, MO_64, MO_64)
346
+DO_STN_2(3, dd, MO_64, MO_64)
347
+DO_STN_2(4, dd, MO_64, MO_64)
348
349
#undef DO_STN_1
350
#undef DO_STN_2
351
--
141
--
352
2.20.1
142
2.34.1
353
354
diff view generated by jsdifflib
[PULL 25/34] target/arm: Reuse sve_probe_page for gather loads
[PULL 66/72] softfloat: Use parts_pick_nan in propagateFloatx80NaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Unpacking and repacking the parts may be slightly more work
4
than we did before, but we get to reuse more code. For a
5
code path handling exceptional values, this is an improvement.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241203203949.483774-8-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200508154359.7494-19-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
11
---
8
target/arm/sve_helper.c | 208 +++++++++++++++++++++-------------------
12
fpu/softfloat.c | 43 +++++--------------------------------------
9
1 file changed, 109 insertions(+), 99 deletions(-)
13
1 file changed, 5 insertions(+), 38 deletions(-)
10
14
11
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/sve_helper.c
17
--- a/fpu/softfloat.c
14
+++ b/target/arm/sve_helper.c
18
+++ b/fpu/softfloat.c
15
@@ -XXX,XX +XXX,XX @@ static target_ulong off_zd_d(void *reg, intptr_t reg_ofs)
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
16
return *(uint64_t *)(reg + reg_ofs);
20
17
}
21
floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
18
19
-static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
20
- target_ulong base, uint32_t desc, uintptr_t ra,
21
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
22
+static inline QEMU_ALWAYS_INLINE
23
+void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
24
+ target_ulong base, uint32_t desc, uintptr_t retaddr,
25
+ int esize, int msize, zreg_off_fn *off_fn,
26
+ sve_ldst1_host_fn *host_fn,
27
+ sve_ldst1_tlb_fn *tlb_fn)
28
{
22
{
29
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
23
- bool aIsLargerSignificand;
30
- intptr_t i, oprsz = simd_oprsz(desc);
24
- FloatClass a_cls, b_cls;
31
- ARMVectorReg scratch = { };
25
+ FloatParts128 pa, pb, *pr;
32
+ const int mmu_idx = cpu_mmu_index(env, false);
26
33
+ const intptr_t reg_max = simd_oprsz(desc);
27
- /* This is not complete, but is good enough for pickNaN. */
34
+ ARMVectorReg scratch;
28
- a_cls = (!floatx80_is_any_nan(a)
35
+ intptr_t reg_off;
29
- ? float_class_normal
36
+ SVEHostPage info, info2;
30
- : floatx80_is_signaling_nan(a, status)
37
31
- ? float_class_snan
38
- for (i = 0; i < oprsz; ) {
32
- : float_class_qnan);
39
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
33
- b_cls = (!floatx80_is_any_nan(b)
40
+ memset(&scratch, 0, reg_max);
34
- ? float_class_normal
41
+ reg_off = 0;
35
- : floatx80_is_signaling_nan(b, status)
42
+ do {
36
- ? float_class_snan
43
+ uint64_t pg = vg[reg_off >> 6];
37
- : float_class_qnan);
44
do {
45
if (likely(pg & 1)) {
46
- target_ulong off = off_fn(vm, i);
47
- tlb_fn(env, &scratch, i, base + (off << scale), ra);
48
+ target_ulong addr = base + (off_fn(vm, reg_off) << scale);
49
+ target_ulong in_page = -(addr | TARGET_PAGE_MASK);
50
+
51
+ sve_probe_page(&info, false, env, addr, 0, MMU_DATA_LOAD,
52
+ mmu_idx, retaddr);
53
+
54
+ if (likely(in_page >= msize)) {
55
+ if (unlikely(info.flags & TLB_WATCHPOINT)) {
56
+ cpu_check_watchpoint(env_cpu(env), addr, msize,
57
+ info.attrs, BP_MEM_READ, retaddr);
58
+ }
59
+ /* TODO: MTE check */
60
+ host_fn(&scratch, reg_off, info.host);
61
+ } else {
62
+ /* Element crosses the page boundary. */
63
+ sve_probe_page(&info2, false, env, addr + in_page, 0,
64
+ MMU_DATA_LOAD, mmu_idx, retaddr);
65
+ if (unlikely((info.flags | info2.flags) & TLB_WATCHPOINT)) {
66
+ cpu_check_watchpoint(env_cpu(env), addr,
67
+ msize, info.attrs,
68
+ BP_MEM_READ, retaddr);
69
+ }
70
+ /* TODO: MTE check */
71
+ tlb_fn(env, &scratch, reg_off, addr, retaddr);
72
+ }
73
}
74
- i += 4, pg >>= 4;
75
- } while (i & 15);
76
- }
77
+ reg_off += esize;
78
+ pg >>= esize;
79
+ } while (reg_off & 63);
80
+ } while (reg_off < reg_max);
81
82
/* Wait until all exceptions have been raised to write back. */
83
- memcpy(vd, &scratch, oprsz);
84
+ memcpy(vd, &scratch, reg_max);
85
}
86
87
-static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
88
- target_ulong base, uint32_t desc, uintptr_t ra,
89
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
90
-{
91
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
92
- intptr_t i, oprsz = simd_oprsz(desc) / 8;
93
- ARMVectorReg scratch = { };
94
-
38
-
95
- for (i = 0; i < oprsz; i++) {
39
- if (is_snan(a_cls) || is_snan(b_cls)) {
96
- uint8_t pg = *(uint8_t *)(vg + H1(i));
40
- float_raise(float_flag_invalid, status);
97
- if (likely(pg & 1)) {
98
- target_ulong off = off_fn(vm, i * 8);
99
- tlb_fn(env, &scratch, i * 8, base + (off << scale), ra);
100
- }
101
- }
41
- }
102
-
42
-
103
- /* Wait until all exceptions have been raised to write back. */
43
- if (status->default_nan_mode) {
104
- memcpy(vd, &scratch, oprsz * 8);
44
+ if (!floatx80_unpack_canonical(&pa, a, status) ||
105
+#define DO_LD1_ZPZ_S(MEM, OFS, MSZ) \
45
+ !floatx80_unpack_canonical(&pb, b, status)) {
106
+void HELPER(sve_ld##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
46
return floatx80_default_nan(status);
107
+ void *vm, target_ulong base, uint32_t desc) \
47
}
108
+{ \
48
109
+ sve_ld1_z(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, \
49
- if (a.low < b.low) {
110
+ off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
50
- aIsLargerSignificand = 0;
51
- } else if (b.low < a.low) {
52
- aIsLargerSignificand = 1;
53
- } else {
54
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
55
- }
56
-
57
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
58
- if (is_snan(b_cls)) {
59
- return floatx80_silence_nan(b, status);
60
- }
61
- return b;
62
- } else {
63
- if (is_snan(a_cls)) {
64
- return floatx80_silence_nan(a, status);
65
- }
66
- return a;
67
- }
68
+ pr = parts_pick_nan(&pa, &pb, status);
69
+ return floatx80_round_pack_canonical(pr, status);
111
}
70
}
112
71
113
-#define DO_LD1_ZPZ_S(MEM, OFS) \
72
/*----------------------------------------------------------------------------
114
-void QEMU_FLATTEN HELPER(sve_ld##MEM##_##OFS) \
115
- (CPUARMState *env, void *vd, void *vg, void *vm, \
116
- target_ulong base, uint32_t desc) \
117
-{ \
118
- sve_ld1_zs(env, vd, vg, vm, base, desc, GETPC(), \
119
- off_##OFS##_s, sve_ld1##MEM##_tlb); \
120
+#define DO_LD1_ZPZ_D(MEM, OFS, MSZ) \
121
+void HELPER(sve_ld##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
122
+ void *vm, target_ulong base, uint32_t desc) \
123
+{ \
124
+ sve_ld1_z(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, \
125
+ off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
126
}
127
128
-#define DO_LD1_ZPZ_D(MEM, OFS) \
129
-void QEMU_FLATTEN HELPER(sve_ld##MEM##_##OFS) \
130
- (CPUARMState *env, void *vd, void *vg, void *vm, \
131
- target_ulong base, uint32_t desc) \
132
-{ \
133
- sve_ld1_zd(env, vd, vg, vm, base, desc, GETPC(), \
134
- off_##OFS##_d, sve_ld1##MEM##_tlb); \
135
-}
136
+DO_LD1_ZPZ_S(bsu, zsu, MO_8)
137
+DO_LD1_ZPZ_S(bsu, zss, MO_8)
138
+DO_LD1_ZPZ_D(bdu, zsu, MO_8)
139
+DO_LD1_ZPZ_D(bdu, zss, MO_8)
140
+DO_LD1_ZPZ_D(bdu, zd, MO_8)
141
142
-DO_LD1_ZPZ_S(bsu, zsu)
143
-DO_LD1_ZPZ_S(bsu, zss)
144
-DO_LD1_ZPZ_D(bdu, zsu)
145
-DO_LD1_ZPZ_D(bdu, zss)
146
-DO_LD1_ZPZ_D(bdu, zd)
147
+DO_LD1_ZPZ_S(bss, zsu, MO_8)
148
+DO_LD1_ZPZ_S(bss, zss, MO_8)
149
+DO_LD1_ZPZ_D(bds, zsu, MO_8)
150
+DO_LD1_ZPZ_D(bds, zss, MO_8)
151
+DO_LD1_ZPZ_D(bds, zd, MO_8)
152
153
-DO_LD1_ZPZ_S(bss, zsu)
154
-DO_LD1_ZPZ_S(bss, zss)
155
-DO_LD1_ZPZ_D(bds, zsu)
156
-DO_LD1_ZPZ_D(bds, zss)
157
-DO_LD1_ZPZ_D(bds, zd)
158
+DO_LD1_ZPZ_S(hsu_le, zsu, MO_16)
159
+DO_LD1_ZPZ_S(hsu_le, zss, MO_16)
160
+DO_LD1_ZPZ_D(hdu_le, zsu, MO_16)
161
+DO_LD1_ZPZ_D(hdu_le, zss, MO_16)
162
+DO_LD1_ZPZ_D(hdu_le, zd, MO_16)
163
164
-DO_LD1_ZPZ_S(hsu_le, zsu)
165
-DO_LD1_ZPZ_S(hsu_le, zss)
166
-DO_LD1_ZPZ_D(hdu_le, zsu)
167
-DO_LD1_ZPZ_D(hdu_le, zss)
168
-DO_LD1_ZPZ_D(hdu_le, zd)
169
+DO_LD1_ZPZ_S(hsu_be, zsu, MO_16)
170
+DO_LD1_ZPZ_S(hsu_be, zss, MO_16)
171
+DO_LD1_ZPZ_D(hdu_be, zsu, MO_16)
172
+DO_LD1_ZPZ_D(hdu_be, zss, MO_16)
173
+DO_LD1_ZPZ_D(hdu_be, zd, MO_16)
174
175
-DO_LD1_ZPZ_S(hsu_be, zsu)
176
-DO_LD1_ZPZ_S(hsu_be, zss)
177
-DO_LD1_ZPZ_D(hdu_be, zsu)
178
-DO_LD1_ZPZ_D(hdu_be, zss)
179
-DO_LD1_ZPZ_D(hdu_be, zd)
180
+DO_LD1_ZPZ_S(hss_le, zsu, MO_16)
181
+DO_LD1_ZPZ_S(hss_le, zss, MO_16)
182
+DO_LD1_ZPZ_D(hds_le, zsu, MO_16)
183
+DO_LD1_ZPZ_D(hds_le, zss, MO_16)
184
+DO_LD1_ZPZ_D(hds_le, zd, MO_16)
185
186
-DO_LD1_ZPZ_S(hss_le, zsu)
187
-DO_LD1_ZPZ_S(hss_le, zss)
188
-DO_LD1_ZPZ_D(hds_le, zsu)
189
-DO_LD1_ZPZ_D(hds_le, zss)
190
-DO_LD1_ZPZ_D(hds_le, zd)
191
+DO_LD1_ZPZ_S(hss_be, zsu, MO_16)
192
+DO_LD1_ZPZ_S(hss_be, zss, MO_16)
193
+DO_LD1_ZPZ_D(hds_be, zsu, MO_16)
194
+DO_LD1_ZPZ_D(hds_be, zss, MO_16)
195
+DO_LD1_ZPZ_D(hds_be, zd, MO_16)
196
197
-DO_LD1_ZPZ_S(hss_be, zsu)
198
-DO_LD1_ZPZ_S(hss_be, zss)
199
-DO_LD1_ZPZ_D(hds_be, zsu)
200
-DO_LD1_ZPZ_D(hds_be, zss)
201
-DO_LD1_ZPZ_D(hds_be, zd)
202
+DO_LD1_ZPZ_S(ss_le, zsu, MO_32)
203
+DO_LD1_ZPZ_S(ss_le, zss, MO_32)
204
+DO_LD1_ZPZ_D(sdu_le, zsu, MO_32)
205
+DO_LD1_ZPZ_D(sdu_le, zss, MO_32)
206
+DO_LD1_ZPZ_D(sdu_le, zd, MO_32)
207
208
-DO_LD1_ZPZ_S(ss_le, zsu)
209
-DO_LD1_ZPZ_S(ss_le, zss)
210
-DO_LD1_ZPZ_D(sdu_le, zsu)
211
-DO_LD1_ZPZ_D(sdu_le, zss)
212
-DO_LD1_ZPZ_D(sdu_le, zd)
213
+DO_LD1_ZPZ_S(ss_be, zsu, MO_32)
214
+DO_LD1_ZPZ_S(ss_be, zss, MO_32)
215
+DO_LD1_ZPZ_D(sdu_be, zsu, MO_32)
216
+DO_LD1_ZPZ_D(sdu_be, zss, MO_32)
217
+DO_LD1_ZPZ_D(sdu_be, zd, MO_32)
218
219
-DO_LD1_ZPZ_S(ss_be, zsu)
220
-DO_LD1_ZPZ_S(ss_be, zss)
221
-DO_LD1_ZPZ_D(sdu_be, zsu)
222
-DO_LD1_ZPZ_D(sdu_be, zss)
223
-DO_LD1_ZPZ_D(sdu_be, zd)
224
+DO_LD1_ZPZ_D(sds_le, zsu, MO_32)
225
+DO_LD1_ZPZ_D(sds_le, zss, MO_32)
226
+DO_LD1_ZPZ_D(sds_le, zd, MO_32)
227
228
-DO_LD1_ZPZ_D(sds_le, zsu)
229
-DO_LD1_ZPZ_D(sds_le, zss)
230
-DO_LD1_ZPZ_D(sds_le, zd)
231
+DO_LD1_ZPZ_D(sds_be, zsu, MO_32)
232
+DO_LD1_ZPZ_D(sds_be, zss, MO_32)
233
+DO_LD1_ZPZ_D(sds_be, zd, MO_32)
234
235
-DO_LD1_ZPZ_D(sds_be, zsu)
236
-DO_LD1_ZPZ_D(sds_be, zss)
237
-DO_LD1_ZPZ_D(sds_be, zd)
238
+DO_LD1_ZPZ_D(dd_le, zsu, MO_64)
239
+DO_LD1_ZPZ_D(dd_le, zss, MO_64)
240
+DO_LD1_ZPZ_D(dd_le, zd, MO_64)
241
242
-DO_LD1_ZPZ_D(dd_le, zsu)
243
-DO_LD1_ZPZ_D(dd_le, zss)
244
-DO_LD1_ZPZ_D(dd_le, zd)
245
-
246
-DO_LD1_ZPZ_D(dd_be, zsu)
247
-DO_LD1_ZPZ_D(dd_be, zss)
248
-DO_LD1_ZPZ_D(dd_be, zd)
249
+DO_LD1_ZPZ_D(dd_be, zsu, MO_64)
250
+DO_LD1_ZPZ_D(dd_be, zss, MO_64)
251
+DO_LD1_ZPZ_D(dd_be, zd, MO_64)
252
253
#undef DO_LD1_ZPZ_S
254
#undef DO_LD1_ZPZ_D
255
--
73
--
256
2.20.1
74
2.34.1
257
258
diff view generated by jsdifflib
[PULL 12/34] accel/tcg: Add probe_access_flags
[PULL 67/72] softfloat: Inline pickNaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This new interface will allow targets to probe for a page
3
Inline pickNaN into its only caller. This makes one assert
4
and then handle watchpoints themselves. This will be most
4
redundant with the immediately preceding IF.
5
useful for vector predicated memory operations, where one
6
page lookup can be used for many operations, and one test
7
can avoid many watchpoint checks.
8
5
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-6-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-9-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
include/exec/cpu-all.h | 13 ++-
11
fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++----
15
include/exec/exec-all.h | 22 +++++
12
fpu/softfloat-specialize.c.inc | 96 ----------------------------------
16
accel/tcg/cputlb.c | 177 ++++++++++++++++++++--------------------
13
2 files changed, 73 insertions(+), 105 deletions(-)
17
accel/tcg/user-exec.c | 43 ++++++++--
14
18
4 files changed, 158 insertions(+), 97 deletions(-)
15
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
19
20
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
21
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
22
--- a/include/exec/cpu-all.h
17
--- a/fpu/softfloat-parts.c.inc
23
+++ b/include/exec/cpu-all.h
18
+++ b/fpu/softfloat-parts.c.inc
24
@@ -XXX,XX +XXX,XX @@ CPUArchState *cpu_copy(CPUArchState *env);
19
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
25
| CPU_INTERRUPT_TGT_EXT_3 \
20
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
26
| CPU_INTERRUPT_TGT_EXT_4)
21
float_status *s)
27
22
{
28
-#if !defined(CONFIG_USER_ONLY)
23
+ int cmp, which;
29
+#ifdef CONFIG_USER_ONLY
30
+
24
+
31
+/*
25
if (is_snan(a->cls) || is_snan(b->cls)) {
32
+ * Allow some level of source compatibility with softmmu. We do not
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
33
+ * support any of the more exotic features, so only invalid pages may
27
}
34
+ * be signaled by probe_access_flags().
28
35
+ */
29
if (s->default_nan_mode) {
36
+#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
30
parts_default_nan(a, s);
37
+#define TLB_MMIO 0
31
- } else {
38
+#define TLB_WATCHPOINT 0
32
- int cmp = frac_cmp(a, b);
33
- if (cmp == 0) {
34
- cmp = a->sign < b->sign;
35
- }
36
+ return a;
37
+ }
38
39
- if (pickNaN(a->cls, b->cls, cmp > 0, s)) {
40
- a = b;
41
- }
42
+ cmp = frac_cmp(a, b);
43
+ if (cmp == 0) {
44
+ cmp = a->sign < b->sign;
45
+ }
39
+
46
+
40
+#else
47
+ switch (s->float_2nan_prop_rule) {
41
48
+ case float_2nan_prop_s_ab:
42
/*
49
if (is_snan(a->cls)) {
43
* Flags stored in the low bits of the TLB virtual address.
50
- parts_silence_nan(a, s);
44
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
51
+ which = 0;
52
+ } else if (is_snan(b->cls)) {
53
+ which = 1;
54
+ } else if (is_qnan(a->cls)) {
55
+ which = 0;
56
+ } else {
57
+ which = 1;
58
}
59
+ break;
60
+ case float_2nan_prop_s_ba:
61
+ if (is_snan(b->cls)) {
62
+ which = 1;
63
+ } else if (is_snan(a->cls)) {
64
+ which = 0;
65
+ } else if (is_qnan(b->cls)) {
66
+ which = 1;
67
+ } else {
68
+ which = 0;
69
+ }
70
+ break;
71
+ case float_2nan_prop_ab:
72
+ which = is_nan(a->cls) ? 0 : 1;
73
+ break;
74
+ case float_2nan_prop_ba:
75
+ which = is_nan(b->cls) ? 1 : 0;
76
+ break;
77
+ case float_2nan_prop_x87:
78
+ /*
79
+ * This implements x87 NaN propagation rules:
80
+ * SNaN + QNaN => return the QNaN
81
+ * two SNaNs => return the one with the larger significand, silenced
82
+ * two QNaNs => return the one with the larger significand
83
+ * SNaN and a non-NaN => return the SNaN, silenced
84
+ * QNaN and a non-NaN => return the QNaN
85
+ *
86
+ * If we get down to comparing significands and they are the same,
87
+ * return the NaN with the positive sign bit (if any).
88
+ */
89
+ if (is_snan(a->cls)) {
90
+ if (is_snan(b->cls)) {
91
+ which = cmp > 0 ? 0 : 1;
92
+ } else {
93
+ which = is_qnan(b->cls) ? 1 : 0;
94
+ }
95
+ } else if (is_qnan(a->cls)) {
96
+ if (is_snan(b->cls) || !is_qnan(b->cls)) {
97
+ which = 0;
98
+ } else {
99
+ which = cmp > 0 ? 0 : 1;
100
+ }
101
+ } else {
102
+ which = 1;
103
+ }
104
+ break;
105
+ default:
106
+ g_assert_not_reached();
107
+ }
108
+
109
+ if (which) {
110
+ a = b;
111
+ }
112
+ if (is_snan(a->cls)) {
113
+ parts_silence_nan(a, s);
114
}
115
return a;
116
}
117
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
45
index XXXXXXX..XXXXXXX 100644
118
index XXXXXXX..XXXXXXX 100644
46
--- a/include/exec/exec-all.h
119
--- a/fpu/softfloat-specialize.c.inc
47
+++ b/include/exec/exec-all.h
120
+++ b/fpu/softfloat-specialize.c.inc
48
@@ -XXX,XX +XXX,XX @@ static inline void *probe_read(CPUArchState *env, target_ulong addr, int size,
121
@@ -XXX,XX +XXX,XX @@ bool float32_is_signaling_nan(float32 a_, float_status *status)
49
return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
50
}
51
52
+/**
53
+ * probe_access_flags:
54
+ * @env: CPUArchState
55
+ * @addr: guest virtual address to look up
56
+ * @access_type: read, write or execute permission
57
+ * @mmu_idx: MMU index to use for lookup
58
+ * @nonfault: suppress the fault
59
+ * @phost: return value for host address
60
+ * @retaddr: return address for unwinding
61
+ *
62
+ * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for
63
+ * the page, and storing the host address for RAM in @phost.
64
+ *
65
+ * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK.
66
+ * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags.
67
+ * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags.
68
+ * For simplicity, all "mmio-like" flags are folded to TLB_MMIO.
69
+ */
70
+int probe_access_flags(CPUArchState *env, target_ulong addr,
71
+ MMUAccessType access_type, int mmu_idx,
72
+ bool nonfault, void **phost, uintptr_t retaddr);
73
+
74
#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
75
76
/* Estimated block size for TB allocation. */
77
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/accel/tcg/cputlb.c
80
+++ b/accel/tcg/cputlb.c
81
@@ -XXX,XX +XXX,XX @@ static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size,
82
}
122
}
83
}
123
}
84
124
85
-/*
125
-/*----------------------------------------------------------------------------
86
- * Probe for whether the specified guest access is permitted. If it is not
126
-| Select which NaN to propagate for a two-input operation.
87
- * permitted then an exception will be taken in the same way as if this
127
-| IEEE754 doesn't specify all the details of this, so the
88
- * were a real access (and we will not return).
128
-| algorithm is target-specific.
89
- * If the size is 0 or the page requires I/O access, returns NULL; otherwise,
129
-| The routine is passed various bits of information about the
90
- * returns the address of the host page similar to tlb_vaddr_to_host().
130
-| two NaNs and should return 0 to select NaN a and 1 for NaN b.
91
- */
131
-| Note that signalling NaNs are always squashed to quiet NaNs
92
-void *probe_access(CPUArchState *env, target_ulong addr, int size,
132
-| by the caller, by calling floatXX_silence_nan() before
93
- MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
133
-| returning them.
94
+static int probe_access_internal(CPUArchState *env, target_ulong addr,
134
-|
95
+ int fault_size, MMUAccessType access_type,
135
-| aIsLargerSignificand is only valid if both a and b are NaNs
96
+ int mmu_idx, bool nonfault,
136
-| of some kind, and is true if a has the larger significand,
97
+ void **phost, uintptr_t retaddr)
137
-| or if both a and b have the same significand but a is
98
{
138
-| positive but b is negative. It is only needed for the x87
99
uintptr_t index = tlb_index(env, mmu_idx, addr);
139
-| tie-break rule.
100
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
140
-*----------------------------------------------------------------------------*/
101
- target_ulong tlb_addr;
102
- size_t elt_ofs;
103
- int wp_access;
104
-
141
-
105
- g_assert(-(addr | TARGET_PAGE_MASK) >= size);
142
-static int pickNaN(FloatClass a_cls, FloatClass b_cls,
143
- bool aIsLargerSignificand, float_status *status)
144
-{
145
- /*
146
- * We guarantee not to require the target to tell us how to
147
- * pick a NaN if we're always returning the default NaN.
148
- * But if we're not in default-NaN mode then the target must
149
- * specify via set_float_2nan_prop_rule().
150
- */
151
- assert(!status->default_nan_mode);
106
-
152
-
107
- switch (access_type) {
153
- switch (status->float_2nan_prop_rule) {
108
- case MMU_DATA_LOAD:
154
- case float_2nan_prop_s_ab:
109
- elt_ofs = offsetof(CPUTLBEntry, addr_read);
155
- if (is_snan(a_cls)) {
110
- wp_access = BP_MEM_READ;
156
- return 0;
111
- break;
157
- } else if (is_snan(b_cls)) {
112
- case MMU_DATA_STORE:
158
- return 1;
113
- elt_ofs = offsetof(CPUTLBEntry, addr_write);
159
- } else if (is_qnan(a_cls)) {
114
- wp_access = BP_MEM_WRITE;
160
- return 0;
115
- break;
161
- } else {
116
- case MMU_INST_FETCH:
162
- return 1;
117
- elt_ofs = offsetof(CPUTLBEntry, addr_code);
163
- }
118
- wp_access = BP_MEM_READ;
164
- break;
119
- break;
165
- case float_2nan_prop_s_ba:
166
- if (is_snan(b_cls)) {
167
- return 1;
168
- } else if (is_snan(a_cls)) {
169
- return 0;
170
- } else if (is_qnan(b_cls)) {
171
- return 1;
172
- } else {
173
- return 0;
174
- }
175
- break;
176
- case float_2nan_prop_ab:
177
- if (is_nan(a_cls)) {
178
- return 0;
179
- } else {
180
- return 1;
181
- }
182
- break;
183
- case float_2nan_prop_ba:
184
- if (is_nan(b_cls)) {
185
- return 1;
186
- } else {
187
- return 0;
188
- }
189
- break;
190
- case float_2nan_prop_x87:
191
- /*
192
- * This implements x87 NaN propagation rules:
193
- * SNaN + QNaN => return the QNaN
194
- * two SNaNs => return the one with the larger significand, silenced
195
- * two QNaNs => return the one with the larger significand
196
- * SNaN and a non-NaN => return the SNaN, silenced
197
- * QNaN and a non-NaN => return the QNaN
198
- *
199
- * If we get down to comparing significands and they are the same,
200
- * return the NaN with the positive sign bit (if any).
201
- */
202
- if (is_snan(a_cls)) {
203
- if (is_snan(b_cls)) {
204
- return aIsLargerSignificand ? 0 : 1;
205
- }
206
- return is_qnan(b_cls) ? 1 : 0;
207
- } else if (is_qnan(a_cls)) {
208
- if (is_snan(b_cls) || !is_qnan(b_cls)) {
209
- return 0;
210
- } else {
211
- return aIsLargerSignificand ? 0 : 1;
212
- }
213
- } else {
214
- return 1;
215
- }
120
- default:
216
- default:
121
- g_assert_not_reached();
217
- g_assert_not_reached();
122
- }
218
- }
123
- tlb_addr = tlb_read_ofs(entry, elt_ofs);
124
-
125
- if (unlikely(!tlb_hit(tlb_addr, addr))) {
126
- if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs,
127
- addr & TARGET_PAGE_MASK)) {
128
- tlb_fill(env_cpu(env), addr, size, access_type, mmu_idx, retaddr);
129
- /* TLB resize via tlb_fill may have moved the entry. */
130
- index = tlb_index(env, mmu_idx, addr);
131
- entry = tlb_entry(env, mmu_idx, addr);
132
- }
133
- tlb_addr = tlb_read_ofs(entry, elt_ofs);
134
- }
135
-
136
- if (!size) {
137
- return NULL;
138
- }
139
-
140
- if (unlikely(tlb_addr & TLB_FLAGS_MASK)) {
141
- CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
142
-
143
- /* Reject I/O access, or other required slow-path. */
144
- if (tlb_addr & (TLB_MMIO | TLB_BSWAP | TLB_DISCARD_WRITE)) {
145
- return NULL;
146
- }
147
-
148
- /* Handle watchpoints. */
149
- if (tlb_addr & TLB_WATCHPOINT) {
150
- cpu_check_watchpoint(env_cpu(env), addr, size,
151
- iotlbentry->attrs, wp_access, retaddr);
152
- }
153
-
154
- /* Handle clean RAM pages. */
155
- if (tlb_addr & TLB_NOTDIRTY) {
156
- notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr);
157
- }
158
- }
159
-
160
- return (void *)((uintptr_t)addr + entry->addend);
161
-}
219
-}
162
-
220
-
163
-void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
221
/*----------------------------------------------------------------------------
164
- MMUAccessType access_type, int mmu_idx)
222
| Returns 1 if the double-precision floating-point value `a' is a quiet
165
-{
223
| NaN; otherwise returns 0.
166
- CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
167
- target_ulong tlb_addr, page;
168
+ target_ulong tlb_addr, page_addr;
169
size_t elt_ofs;
170
+ int flags;
171
172
switch (access_type) {
173
case MMU_DATA_LOAD:
174
@@ -XXX,XX +XXX,XX @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
175
default:
176
g_assert_not_reached();
177
}
178
-
179
- page = addr & TARGET_PAGE_MASK;
180
tlb_addr = tlb_read_ofs(entry, elt_ofs);
181
182
- if (!tlb_hit_page(tlb_addr, page)) {
183
- uintptr_t index = tlb_index(env, mmu_idx, addr);
184
-
185
- if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page)) {
186
+ page_addr = addr & TARGET_PAGE_MASK;
187
+ if (!tlb_hit_page(tlb_addr, page_addr)) {
188
+ if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) {
189
CPUState *cs = env_cpu(env);
190
CPUClass *cc = CPU_GET_CLASS(cs);
191
192
- if (!cc->tlb_fill(cs, addr, 0, access_type, mmu_idx, true, 0)) {
193
+ if (!cc->tlb_fill(cs, addr, fault_size, access_type,
194
+ mmu_idx, nonfault, retaddr)) {
195
/* Non-faulting page table read failed. */
196
- return NULL;
197
+ *phost = NULL;
198
+ return TLB_INVALID_MASK;
199
}
200
201
/* TLB resize via tlb_fill may have moved the entry. */
202
@@ -XXX,XX +XXX,XX @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
203
}
204
tlb_addr = tlb_read_ofs(entry, elt_ofs);
205
}
206
+ flags = tlb_addr & TLB_FLAGS_MASK;
207
208
- if (tlb_addr & ~TARGET_PAGE_MASK) {
209
- /* IO access */
210
+ /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */
211
+ if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) {
212
+ *phost = NULL;
213
+ return TLB_MMIO;
214
+ }
215
+
216
+ /* Everything else is RAM. */
217
+ *phost = (void *)((uintptr_t)addr + entry->addend);
218
+ return flags;
219
+}
220
+
221
+int probe_access_flags(CPUArchState *env, target_ulong addr,
222
+ MMUAccessType access_type, int mmu_idx,
223
+ bool nonfault, void **phost, uintptr_t retaddr)
224
+{
225
+ int flags;
226
+
227
+ flags = probe_access_internal(env, addr, 0, access_type, mmu_idx,
228
+ nonfault, phost, retaddr);
229
+
230
+ /* Handle clean RAM pages. */
231
+ if (unlikely(flags & TLB_NOTDIRTY)) {
232
+ uintptr_t index = tlb_index(env, mmu_idx, addr);
233
+ CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
234
+
235
+ notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr);
236
+ flags &= ~TLB_NOTDIRTY;
237
+ }
238
+
239
+ return flags;
240
+}
241
+
242
+void *probe_access(CPUArchState *env, target_ulong addr, int size,
243
+ MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
244
+{
245
+ void *host;
246
+ int flags;
247
+
248
+ g_assert(-(addr | TARGET_PAGE_MASK) >= size);
249
+
250
+ flags = probe_access_internal(env, addr, size, access_type, mmu_idx,
251
+ false, &host, retaddr);
252
+
253
+ /* Per the interface, size == 0 merely faults the access. */
254
+ if (size == 0) {
255
return NULL;
256
}
257
258
- return (void *)((uintptr_t)addr + entry->addend);
259
+ if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) {
260
+ uintptr_t index = tlb_index(env, mmu_idx, addr);
261
+ CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
262
+
263
+ /* Handle watchpoints. */
264
+ if (flags & TLB_WATCHPOINT) {
265
+ int wp_access = (access_type == MMU_DATA_STORE
266
+ ? BP_MEM_WRITE : BP_MEM_READ);
267
+ cpu_check_watchpoint(env_cpu(env), addr, size,
268
+ iotlbentry->attrs, wp_access, retaddr);
269
+ }
270
+
271
+ /* Handle clean RAM pages. */
272
+ if (flags & TLB_NOTDIRTY) {
273
+ notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr);
274
+ }
275
+ }
276
+
277
+ return host;
278
}
279
280
+void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
281
+ MMUAccessType access_type, int mmu_idx)
282
+{
283
+ void *host;
284
+ int flags;
285
+
286
+ flags = probe_access_internal(env, addr, 0, access_type,
287
+ mmu_idx, true, &host, 0);
288
+
289
+ /* No combination of flags are expected by the caller. */
290
+ return flags ? NULL : host;
291
+}
292
293
#ifdef CONFIG_PLUGIN
294
/*
295
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
296
index XXXXXXX..XXXXXXX 100644
297
--- a/accel/tcg/user-exec.c
298
+++ b/accel/tcg/user-exec.c
299
@@ -XXX,XX +XXX,XX @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
300
g_assert_not_reached();
301
}
302
303
-void *probe_access(CPUArchState *env, target_ulong addr, int size,
304
- MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
305
+static int probe_access_internal(CPUArchState *env, target_ulong addr,
306
+ int fault_size, MMUAccessType access_type,
307
+ bool nonfault, uintptr_t ra)
308
{
309
int flags;
310
311
- g_assert(-(addr | TARGET_PAGE_MASK) >= size);
312
-
313
switch (access_type) {
314
case MMU_DATA_STORE:
315
flags = PAGE_WRITE;
316
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
317
}
318
319
if (!guest_addr_valid(addr) || page_check_range(addr, 1, flags) < 0) {
320
- CPUState *cpu = env_cpu(env);
321
- CPUClass *cc = CPU_GET_CLASS(cpu);
322
- cc->tlb_fill(cpu, addr, size, access_type, MMU_USER_IDX, false,
323
- retaddr);
324
- g_assert_not_reached();
325
+ if (nonfault) {
326
+ return TLB_INVALID_MASK;
327
+ } else {
328
+ CPUState *cpu = env_cpu(env);
329
+ CPUClass *cc = CPU_GET_CLASS(cpu);
330
+ cc->tlb_fill(cpu, addr, fault_size, access_type,
331
+ MMU_USER_IDX, false, ra);
332
+ g_assert_not_reached();
333
+ }
334
}
335
+ return 0;
336
+}
337
+
338
+int probe_access_flags(CPUArchState *env, target_ulong addr,
339
+ MMUAccessType access_type, int mmu_idx,
340
+ bool nonfault, void **phost, uintptr_t ra)
341
+{
342
+ int flags;
343
+
344
+ flags = probe_access_internal(env, addr, 0, access_type, nonfault, ra);
345
+ *phost = flags ? NULL : g2h(addr);
346
+ return flags;
347
+}
348
+
349
+void *probe_access(CPUArchState *env, target_ulong addr, int size,
350
+ MMUAccessType access_type, int mmu_idx, uintptr_t ra)
351
+{
352
+ int flags;
353
+
354
+ g_assert(-(addr | TARGET_PAGE_MASK) >= size);
355
+ flags = probe_access_internal(env, addr, size, access_type, false, ra);
356
+ g_assert(flags == 0);
357
358
return size ? g2h(addr) : NULL;
359
}
360
--
224
--
361
2.20.1
225
2.34.1
362
226
363
227
diff view generated by jsdifflib
[PULL 08/34] exec: Add block comments for watchpoint routines
[PULL 68/72] softfloat: Share code between parts_pick_nan cases
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Remember if there was an SNaN, and use that to simplify
4
float_2nan_prop_s_{ab,ba} to only the snan component.
5
Then, fall through to the corresponding
6
float_2nan_prop_{ab,ba} case to handle any remaining
7
nans, which must be quiet.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20241203203949.483774-10-richard.henderson@linaro.org
5
Message-id: 20200508154359.7494-2-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
13
---
8
include/hw/core/cpu.h | 23 +++++++++++++++++++++++
14
fpu/softfloat-parts.c.inc | 32 ++++++++++++--------------------
9
1 file changed, 23 insertions(+)
15
1 file changed, 12 insertions(+), 20 deletions(-)
10
16
11
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/core/cpu.h
19
--- a/fpu/softfloat-parts.c.inc
14
+++ b/include/hw/core/cpu.h
20
+++ b/fpu/softfloat-parts.c.inc
15
@@ -XXX,XX +XXX,XX @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
21
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
16
vaddr len, int flags);
22
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
17
void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
23
float_status *s)
18
void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
24
{
19
+
25
+ bool have_snan = false;
20
+/**
26
int cmp, which;
21
+ * cpu_check_watchpoint:
27
22
+ * @cpu: cpu context
28
if (is_snan(a->cls) || is_snan(b->cls)) {
23
+ * @addr: guest virtual address
29
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
24
+ * @len: access length
30
+ have_snan = true;
25
+ * @attrs: memory access attributes
31
}
26
+ * @flags: watchpoint access type
32
27
+ * @ra: unwind return address
33
if (s->default_nan_mode) {
28
+ *
34
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
29
+ * Check for a watchpoint hit in [addr, addr+len) of the type
35
30
+ * specified by @flags. Exit via exception with a hit.
36
switch (s->float_2nan_prop_rule) {
31
+ */
37
case float_2nan_prop_s_ab:
32
void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
38
- if (is_snan(a->cls)) {
33
MemTxAttrs attrs, int flags, uintptr_t ra);
39
- which = 0;
34
+
40
- } else if (is_snan(b->cls)) {
35
+/**
41
- which = 1;
36
+ * cpu_watchpoint_address_matches:
42
- } else if (is_qnan(a->cls)) {
37
+ * @cpu: cpu context
43
- which = 0;
38
+ * @addr: guest virtual address
44
- } else {
39
+ * @len: access length
45
- which = 1;
40
+ *
46
+ if (have_snan) {
41
+ * Return the watchpoint flags that apply to [addr, addr+len).
47
+ which = is_snan(a->cls) ? 0 : 1;
42
+ * If no watchpoint is registered for the range, the result is 0.
48
+ break;
43
+ */
49
}
44
int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len);
50
- break;
45
#endif
51
- case float_2nan_prop_s_ba:
46
52
- if (is_snan(b->cls)) {
53
- which = 1;
54
- } else if (is_snan(a->cls)) {
55
- which = 0;
56
- } else if (is_qnan(b->cls)) {
57
- which = 1;
58
- } else {
59
- which = 0;
60
- }
61
- break;
62
+ /* fall through */
63
case float_2nan_prop_ab:
64
which = is_nan(a->cls) ? 0 : 1;
65
break;
66
+ case float_2nan_prop_s_ba:
67
+ if (have_snan) {
68
+ which = is_snan(b->cls) ? 1 : 0;
69
+ break;
70
+ }
71
+ /* fall through */
72
case float_2nan_prop_ba:
73
which = is_nan(b->cls) ? 1 : 0;
74
break;
47
--
75
--
48
2.20.1
76
2.34.1
49
50
diff view generated by jsdifflib
[PULL 23/34] target/arm: Reuse sve_probe_page for gather first-fault loads
[PULL 69/72] softfloat: Sink frac_cmp in parts_pick_nan until needed
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This avoids the need for a separate set of helpers to implement
3
Move the fractional comparison to the end of the
4
no-fault semantics, and will enable MTE in the future.
4
float_2nan_prop_x87 case. This is not required for
5
any other 2nan propagation rule. Reorganize the
6
x87 case itself to break out of the switch when the
7
fractional comparison is not required.
5
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20241203203949.483774-11-richard.henderson@linaro.org
8
Message-id: 20200508154359.7494-17-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
13
---
11
target/arm/sve_helper.c | 323 ++++++++++++++++------------------------
14
fpu/softfloat-parts.c.inc | 19 +++++++++----------
12
1 file changed, 127 insertions(+), 196 deletions(-)
15
1 file changed, 9 insertions(+), 10 deletions(-)
13
16
14
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/sve_helper.c
19
--- a/fpu/softfloat-parts.c.inc
17
+++ b/target/arm/sve_helper.c
20
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ DO_LD1_ZPZ_D(dd_be, zd)
21
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
19
22
return a;
20
/* First fault loads with a vector index. */
21
22
-/* Load one element into VD+REG_OFF from (ENV,VADDR) without faulting.
23
- * The controlling predicate is known to be true. Return true if the
24
- * load was successful.
25
- */
26
-typedef bool sve_ld1_nf_fn(CPUARMState *env, void *vd, intptr_t reg_off,
27
- target_ulong vaddr, int mmu_idx);
28
-
29
-#ifdef CONFIG_SOFTMMU
30
-#define DO_LD_NF(NAME, H, TYPEE, TYPEM, HOST) \
31
-static bool sve_ld##NAME##_nf(CPUARMState *env, void *vd, intptr_t reg_off, \
32
- target_ulong addr, int mmu_idx) \
33
-{ \
34
- target_ulong next_page = -(addr | TARGET_PAGE_MASK); \
35
- if (likely(next_page - addr >= sizeof(TYPEM))) { \
36
- void *host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_idx); \
37
- if (likely(host)) { \
38
- TYPEM val = HOST(host); \
39
- *(TYPEE *)(vd + H(reg_off)) = val; \
40
- return true; \
41
- } \
42
- } \
43
- return false; \
44
-}
45
-#else
46
-#define DO_LD_NF(NAME, H, TYPEE, TYPEM, HOST) \
47
-static bool sve_ld##NAME##_nf(CPUARMState *env, void *vd, intptr_t reg_off, \
48
- target_ulong addr, int mmu_idx) \
49
-{ \
50
- if (likely(page_check_range(addr, sizeof(TYPEM), PAGE_READ))) { \
51
- TYPEM val = HOST(g2h(addr)); \
52
- *(TYPEE *)(vd + H(reg_off)) = val; \
53
- return true; \
54
- } \
55
- return false; \
56
-}
57
-#endif
58
-
59
-DO_LD_NF(bsu, H1_4, uint32_t, uint8_t, ldub_p)
60
-DO_LD_NF(bss, H1_4, uint32_t, int8_t, ldsb_p)
61
-DO_LD_NF(bdu, , uint64_t, uint8_t, ldub_p)
62
-DO_LD_NF(bds, , uint64_t, int8_t, ldsb_p)
63
-
64
-DO_LD_NF(hsu_le, H1_4, uint32_t, uint16_t, lduw_le_p)
65
-DO_LD_NF(hss_le, H1_4, uint32_t, int16_t, ldsw_le_p)
66
-DO_LD_NF(hsu_be, H1_4, uint32_t, uint16_t, lduw_be_p)
67
-DO_LD_NF(hss_be, H1_4, uint32_t, int16_t, ldsw_be_p)
68
-DO_LD_NF(hdu_le, , uint64_t, uint16_t, lduw_le_p)
69
-DO_LD_NF(hds_le, , uint64_t, int16_t, ldsw_le_p)
70
-DO_LD_NF(hdu_be, , uint64_t, uint16_t, lduw_be_p)
71
-DO_LD_NF(hds_be, , uint64_t, int16_t, ldsw_be_p)
72
-
73
-DO_LD_NF(ss_le, H1_4, uint32_t, uint32_t, ldl_le_p)
74
-DO_LD_NF(ss_be, H1_4, uint32_t, uint32_t, ldl_be_p)
75
-DO_LD_NF(sdu_le, , uint64_t, uint32_t, ldl_le_p)
76
-DO_LD_NF(sds_le, , uint64_t, int32_t, ldl_le_p)
77
-DO_LD_NF(sdu_be, , uint64_t, uint32_t, ldl_be_p)
78
-DO_LD_NF(sds_be, , uint64_t, int32_t, ldl_be_p)
79
-
80
-DO_LD_NF(dd_le, , uint64_t, uint64_t, ldq_le_p)
81
-DO_LD_NF(dd_be, , uint64_t, uint64_t, ldq_be_p)
82
-
83
/*
84
- * Common helper for all gather first-faulting loads.
85
+ * Common helpers for all gather first-faulting loads.
86
*/
87
-static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
88
- target_ulong base, uint32_t desc, uintptr_t ra,
89
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
90
- sve_ld1_nf_fn *nonfault_fn)
91
+
92
+static inline QEMU_ALWAYS_INLINE
93
+void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
94
+ target_ulong base, uint32_t desc, uintptr_t retaddr,
95
+ const int esz, const int msz, zreg_off_fn *off_fn,
96
+ sve_ldst1_host_fn *host_fn,
97
+ sve_ldst1_tlb_fn *tlb_fn)
98
{
99
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
100
- const int mmu_idx = get_mmuidx(oi);
101
+ const int mmu_idx = cpu_mmu_index(env, false);
102
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
103
- intptr_t reg_off, reg_max = simd_oprsz(desc);
104
- target_ulong addr;
105
+ const int esize = 1 << esz;
106
+ const int msize = 1 << msz;
107
+ const intptr_t reg_max = simd_oprsz(desc);
108
+ intptr_t reg_off;
109
+ SVEHostPage info;
110
+ target_ulong addr, in_page;
111
112
/* Skip to the first true predicate. */
113
- reg_off = find_next_active(vg, 0, reg_max, MO_32);
114
- if (likely(reg_off < reg_max)) {
115
- /* Perform one normal read, which will fault or not. */
116
- addr = off_fn(vm, reg_off);
117
- addr = base + (addr << scale);
118
- tlb_fn(env, vd, reg_off, addr, ra);
119
-
120
- /* The rest of the reads will be non-faulting. */
121
+ reg_off = find_next_active(vg, 0, reg_max, esz);
122
+ if (unlikely(reg_off >= reg_max)) {
123
+ /* The entire predicate was false; no load occurs. */
124
+ memset(vd, 0, reg_max);
125
+ return;
126
}
23
}
127
24
128
- /* After any fault, zero the leading predicated false elements. */
25
- cmp = frac_cmp(a, b);
129
+ /*
26
- if (cmp == 0) {
130
+ * Probe the first element, allowing faults.
27
- cmp = a->sign < b->sign;
131
+ */
132
+ addr = base + (off_fn(vm, reg_off) << scale);
133
+ tlb_fn(env, vd, reg_off, addr, retaddr);
134
+
135
+ /* After any fault, zero the other elements. */
136
swap_memzero(vd, reg_off);
137
+ reg_off += esize;
138
+ swap_memzero(vd + reg_off, reg_max - reg_off);
139
140
- while (likely((reg_off += 4) < reg_max)) {
141
- uint64_t pg = *(uint64_t *)(vg + (reg_off >> 6) * 8);
142
- if (likely((pg >> (reg_off & 63)) & 1)) {
143
- addr = off_fn(vm, reg_off);
144
- addr = base + (addr << scale);
145
- if (!nonfault_fn(env, vd, reg_off, addr, mmu_idx)) {
146
- record_fault(env, reg_off, reg_max);
147
- break;
148
+ /*
149
+ * Probe the remaining elements, not allowing faults.
150
+ */
151
+ while (reg_off < reg_max) {
152
+ uint64_t pg = vg[reg_off >> 6];
153
+ do {
154
+ if (likely((pg >> (reg_off & 63)) & 1)) {
155
+ addr = base + (off_fn(vm, reg_off) << scale);
156
+ in_page = -(addr | TARGET_PAGE_MASK);
157
+
158
+ if (unlikely(in_page < msize)) {
159
+ /* Stop if the element crosses a page boundary. */
160
+ goto fault;
161
+ }
162
+
163
+ sve_probe_page(&info, true, env, addr, 0, MMU_DATA_LOAD,
164
+ mmu_idx, retaddr);
165
+ if (unlikely(info.flags & (TLB_INVALID_MASK | TLB_MMIO))) {
166
+ goto fault;
167
+ }
168
+ if (unlikely(info.flags & TLB_WATCHPOINT) &&
169
+ (cpu_watchpoint_address_matches
170
+ (env_cpu(env), addr, msize) & BP_MEM_READ)) {
171
+ goto fault;
172
+ }
173
+ /* TODO: MTE check. */
174
+
175
+ host_fn(vd, reg_off, info.host);
176
}
177
- } else {
178
- *(uint32_t *)(vd + H1_4(reg_off)) = 0;
179
- }
180
+ reg_off += esize;
181
+ } while (reg_off & 63);
182
}
183
+ return;
184
+
185
+ fault:
186
+ record_fault(env, reg_off, reg_max);
187
}
188
189
-static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
190
- target_ulong base, uint32_t desc, uintptr_t ra,
191
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
192
- sve_ld1_nf_fn *nonfault_fn)
193
-{
194
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
195
- const int mmu_idx = get_mmuidx(oi);
196
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
197
- intptr_t reg_off, reg_max = simd_oprsz(desc);
198
- target_ulong addr;
199
-
200
- /* Skip to the first true predicate. */
201
- reg_off = find_next_active(vg, 0, reg_max, MO_64);
202
- if (likely(reg_off < reg_max)) {
203
- /* Perform one normal read, which will fault or not. */
204
- addr = off_fn(vm, reg_off);
205
- addr = base + (addr << scale);
206
- tlb_fn(env, vd, reg_off, addr, ra);
207
-
208
- /* The rest of the reads will be non-faulting. */
209
- }
28
- }
210
-
29
-
211
- /* After any fault, zero the leading predicated false elements. */
30
switch (s->float_2nan_prop_rule) {
212
- swap_memzero(vd, reg_off);
31
case float_2nan_prop_s_ab:
213
-
32
if (have_snan) {
214
- while (likely((reg_off += 8) < reg_max)) {
33
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
215
- uint8_t pg = *(uint8_t *)(vg + H1(reg_off >> 3));
34
* return the NaN with the positive sign bit (if any).
216
- if (likely(pg & 1)) {
35
*/
217
- addr = off_fn(vm, reg_off);
36
if (is_snan(a->cls)) {
218
- addr = base + (addr << scale);
37
- if (is_snan(b->cls)) {
219
- if (!nonfault_fn(env, vd, reg_off, addr, mmu_idx)) {
38
- which = cmp > 0 ? 0 : 1;
220
- record_fault(env, reg_off, reg_max);
39
- } else {
221
- break;
40
+ if (!is_snan(b->cls)) {
222
- }
41
which = is_qnan(b->cls) ? 1 : 0;
223
- } else {
42
+ break;
224
- *(uint64_t *)(vd + reg_off) = 0;
43
}
225
- }
44
} else if (is_qnan(a->cls)) {
226
- }
45
if (is_snan(b->cls) || !is_qnan(b->cls)) {
227
+#define DO_LDFF1_ZPZ_S(MEM, OFS, MSZ) \
46
which = 0;
228
+void HELPER(sve_ldff##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
47
- } else {
229
+ void *vm, target_ulong base, uint32_t desc) \
48
- which = cmp > 0 ? 0 : 1;
230
+{ \
49
+ break;
231
+ sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), MO_32, MSZ, \
50
}
232
+ off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
51
} else {
233
}
52
which = 1;
234
53
+ break;
235
-#define DO_LDFF1_ZPZ_S(MEM, OFS) \
54
}
236
-void HELPER(sve_ldff##MEM##_##OFS) \
55
+ cmp = frac_cmp(a, b);
237
- (CPUARMState *env, void *vd, void *vg, void *vm, \
56
+ if (cmp == 0) {
238
- target_ulong base, uint32_t desc) \
57
+ cmp = a->sign < b->sign;
239
-{ \
58
+ }
240
- sve_ldff1_zs(env, vd, vg, vm, base, desc, GETPC(), \
59
+ which = cmp > 0 ? 0 : 1;
241
- off_##OFS##_s, sve_ld1##MEM##_tlb, sve_ld##MEM##_nf); \
60
break;
242
+#define DO_LDFF1_ZPZ_D(MEM, OFS, MSZ) \
61
default:
243
+void HELPER(sve_ldff##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
62
g_assert_not_reached();
244
+ void *vm, target_ulong base, uint32_t desc) \
245
+{ \
246
+ sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), MO_64, MSZ, \
247
+ off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
248
}
249
250
-#define DO_LDFF1_ZPZ_D(MEM, OFS) \
251
-void HELPER(sve_ldff##MEM##_##OFS) \
252
- (CPUARMState *env, void *vd, void *vg, void *vm, \
253
- target_ulong base, uint32_t desc) \
254
-{ \
255
- sve_ldff1_zd(env, vd, vg, vm, base, desc, GETPC(), \
256
- off_##OFS##_d, sve_ld1##MEM##_tlb, sve_ld##MEM##_nf); \
257
-}
258
+DO_LDFF1_ZPZ_S(bsu, zsu, MO_8)
259
+DO_LDFF1_ZPZ_S(bsu, zss, MO_8)
260
+DO_LDFF1_ZPZ_D(bdu, zsu, MO_8)
261
+DO_LDFF1_ZPZ_D(bdu, zss, MO_8)
262
+DO_LDFF1_ZPZ_D(bdu, zd, MO_8)
263
264
-DO_LDFF1_ZPZ_S(bsu, zsu)
265
-DO_LDFF1_ZPZ_S(bsu, zss)
266
-DO_LDFF1_ZPZ_D(bdu, zsu)
267
-DO_LDFF1_ZPZ_D(bdu, zss)
268
-DO_LDFF1_ZPZ_D(bdu, zd)
269
+DO_LDFF1_ZPZ_S(bss, zsu, MO_8)
270
+DO_LDFF1_ZPZ_S(bss, zss, MO_8)
271
+DO_LDFF1_ZPZ_D(bds, zsu, MO_8)
272
+DO_LDFF1_ZPZ_D(bds, zss, MO_8)
273
+DO_LDFF1_ZPZ_D(bds, zd, MO_8)
274
275
-DO_LDFF1_ZPZ_S(bss, zsu)
276
-DO_LDFF1_ZPZ_S(bss, zss)
277
-DO_LDFF1_ZPZ_D(bds, zsu)
278
-DO_LDFF1_ZPZ_D(bds, zss)
279
-DO_LDFF1_ZPZ_D(bds, zd)
280
+DO_LDFF1_ZPZ_S(hsu_le, zsu, MO_16)
281
+DO_LDFF1_ZPZ_S(hsu_le, zss, MO_16)
282
+DO_LDFF1_ZPZ_D(hdu_le, zsu, MO_16)
283
+DO_LDFF1_ZPZ_D(hdu_le, zss, MO_16)
284
+DO_LDFF1_ZPZ_D(hdu_le, zd, MO_16)
285
286
-DO_LDFF1_ZPZ_S(hsu_le, zsu)
287
-DO_LDFF1_ZPZ_S(hsu_le, zss)
288
-DO_LDFF1_ZPZ_D(hdu_le, zsu)
289
-DO_LDFF1_ZPZ_D(hdu_le, zss)
290
-DO_LDFF1_ZPZ_D(hdu_le, zd)
291
+DO_LDFF1_ZPZ_S(hsu_be, zsu, MO_16)
292
+DO_LDFF1_ZPZ_S(hsu_be, zss, MO_16)
293
+DO_LDFF1_ZPZ_D(hdu_be, zsu, MO_16)
294
+DO_LDFF1_ZPZ_D(hdu_be, zss, MO_16)
295
+DO_LDFF1_ZPZ_D(hdu_be, zd, MO_16)
296
297
-DO_LDFF1_ZPZ_S(hsu_be, zsu)
298
-DO_LDFF1_ZPZ_S(hsu_be, zss)
299
-DO_LDFF1_ZPZ_D(hdu_be, zsu)
300
-DO_LDFF1_ZPZ_D(hdu_be, zss)
301
-DO_LDFF1_ZPZ_D(hdu_be, zd)
302
+DO_LDFF1_ZPZ_S(hss_le, zsu, MO_16)
303
+DO_LDFF1_ZPZ_S(hss_le, zss, MO_16)
304
+DO_LDFF1_ZPZ_D(hds_le, zsu, MO_16)
305
+DO_LDFF1_ZPZ_D(hds_le, zss, MO_16)
306
+DO_LDFF1_ZPZ_D(hds_le, zd, MO_16)
307
308
-DO_LDFF1_ZPZ_S(hss_le, zsu)
309
-DO_LDFF1_ZPZ_S(hss_le, zss)
310
-DO_LDFF1_ZPZ_D(hds_le, zsu)
311
-DO_LDFF1_ZPZ_D(hds_le, zss)
312
-DO_LDFF1_ZPZ_D(hds_le, zd)
313
+DO_LDFF1_ZPZ_S(hss_be, zsu, MO_16)
314
+DO_LDFF1_ZPZ_S(hss_be, zss, MO_16)
315
+DO_LDFF1_ZPZ_D(hds_be, zsu, MO_16)
316
+DO_LDFF1_ZPZ_D(hds_be, zss, MO_16)
317
+DO_LDFF1_ZPZ_D(hds_be, zd, MO_16)
318
319
-DO_LDFF1_ZPZ_S(hss_be, zsu)
320
-DO_LDFF1_ZPZ_S(hss_be, zss)
321
-DO_LDFF1_ZPZ_D(hds_be, zsu)
322
-DO_LDFF1_ZPZ_D(hds_be, zss)
323
-DO_LDFF1_ZPZ_D(hds_be, zd)
324
+DO_LDFF1_ZPZ_S(ss_le, zsu, MO_32)
325
+DO_LDFF1_ZPZ_S(ss_le, zss, MO_32)
326
+DO_LDFF1_ZPZ_D(sdu_le, zsu, MO_32)
327
+DO_LDFF1_ZPZ_D(sdu_le, zss, MO_32)
328
+DO_LDFF1_ZPZ_D(sdu_le, zd, MO_32)
329
330
-DO_LDFF1_ZPZ_S(ss_le, zsu)
331
-DO_LDFF1_ZPZ_S(ss_le, zss)
332
-DO_LDFF1_ZPZ_D(sdu_le, zsu)
333
-DO_LDFF1_ZPZ_D(sdu_le, zss)
334
-DO_LDFF1_ZPZ_D(sdu_le, zd)
335
+DO_LDFF1_ZPZ_S(ss_be, zsu, MO_32)
336
+DO_LDFF1_ZPZ_S(ss_be, zss, MO_32)
337
+DO_LDFF1_ZPZ_D(sdu_be, zsu, MO_32)
338
+DO_LDFF1_ZPZ_D(sdu_be, zss, MO_32)
339
+DO_LDFF1_ZPZ_D(sdu_be, zd, MO_32)
340
341
-DO_LDFF1_ZPZ_S(ss_be, zsu)
342
-DO_LDFF1_ZPZ_S(ss_be, zss)
343
-DO_LDFF1_ZPZ_D(sdu_be, zsu)
344
-DO_LDFF1_ZPZ_D(sdu_be, zss)
345
-DO_LDFF1_ZPZ_D(sdu_be, zd)
346
+DO_LDFF1_ZPZ_D(sds_le, zsu, MO_32)
347
+DO_LDFF1_ZPZ_D(sds_le, zss, MO_32)
348
+DO_LDFF1_ZPZ_D(sds_le, zd, MO_32)
349
350
-DO_LDFF1_ZPZ_D(sds_le, zsu)
351
-DO_LDFF1_ZPZ_D(sds_le, zss)
352
-DO_LDFF1_ZPZ_D(sds_le, zd)
353
+DO_LDFF1_ZPZ_D(sds_be, zsu, MO_32)
354
+DO_LDFF1_ZPZ_D(sds_be, zss, MO_32)
355
+DO_LDFF1_ZPZ_D(sds_be, zd, MO_32)
356
357
-DO_LDFF1_ZPZ_D(sds_be, zsu)
358
-DO_LDFF1_ZPZ_D(sds_be, zss)
359
-DO_LDFF1_ZPZ_D(sds_be, zd)
360
+DO_LDFF1_ZPZ_D(dd_le, zsu, MO_64)
361
+DO_LDFF1_ZPZ_D(dd_le, zss, MO_64)
362
+DO_LDFF1_ZPZ_D(dd_le, zd, MO_64)
363
364
-DO_LDFF1_ZPZ_D(dd_le, zsu)
365
-DO_LDFF1_ZPZ_D(dd_le, zss)
366
-DO_LDFF1_ZPZ_D(dd_le, zd)
367
-
368
-DO_LDFF1_ZPZ_D(dd_be, zsu)
369
-DO_LDFF1_ZPZ_D(dd_be, zss)
370
-DO_LDFF1_ZPZ_D(dd_be, zd)
371
+DO_LDFF1_ZPZ_D(dd_be, zsu, MO_64)
372
+DO_LDFF1_ZPZ_D(dd_be, zss, MO_64)
373
+DO_LDFF1_ZPZ_D(dd_be, zd, MO_64)
374
375
/* Stores with a vector index. */
376
377
--
63
--
378
2.20.1
64
2.34.1
379
380
diff view generated by jsdifflib
[PULL 11/34] accel/tcg: Adjust probe_access call to page_check_range
[PULL 70/72] softfloat: Replace WHICH with RET in parts_pick_nan
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We have validated that addr+size does not cross a page boundary.
3
Replace the "index" selecting between A and B with a result variable
4
Therefore we need to validate exactly one page. We can achieve
4
of the proper type. This improves clarity within the function.
5
that passing any value 1 <= x <= size to page_check_range.
6
7
Passing 1 will simplify the next patch.
8
5
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-5-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-12-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
accel/tcg/user-exec.c | 2 +-
11
fpu/softfloat-parts.c.inc | 28 +++++++++++++---------------
15
1 file changed, 1 insertion(+), 1 deletion(-)
12
1 file changed, 13 insertions(+), 15 deletions(-)
16
13
17
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/accel/tcg/user-exec.c
16
--- a/fpu/softfloat-parts.c.inc
20
+++ b/accel/tcg/user-exec.c
17
+++ b/fpu/softfloat-parts.c.inc
21
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
19
float_status *s)
20
{
21
bool have_snan = false;
22
- int cmp, which;
23
+ FloatPartsN *ret;
24
+ int cmp;
25
26
if (is_snan(a->cls) || is_snan(b->cls)) {
27
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
28
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
29
switch (s->float_2nan_prop_rule) {
30
case float_2nan_prop_s_ab:
31
if (have_snan) {
32
- which = is_snan(a->cls) ? 0 : 1;
33
+ ret = is_snan(a->cls) ? a : b;
34
break;
35
}
36
/* fall through */
37
case float_2nan_prop_ab:
38
- which = is_nan(a->cls) ? 0 : 1;
39
+ ret = is_nan(a->cls) ? a : b;
40
break;
41
case float_2nan_prop_s_ba:
42
if (have_snan) {
43
- which = is_snan(b->cls) ? 1 : 0;
44
+ ret = is_snan(b->cls) ? b : a;
45
break;
46
}
47
/* fall through */
48
case float_2nan_prop_ba:
49
- which = is_nan(b->cls) ? 1 : 0;
50
+ ret = is_nan(b->cls) ? b : a;
51
break;
52
case float_2nan_prop_x87:
53
/*
54
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
55
*/
56
if (is_snan(a->cls)) {
57
if (!is_snan(b->cls)) {
58
- which = is_qnan(b->cls) ? 1 : 0;
59
+ ret = is_qnan(b->cls) ? b : a;
60
break;
61
}
62
} else if (is_qnan(a->cls)) {
63
if (is_snan(b->cls) || !is_qnan(b->cls)) {
64
- which = 0;
65
+ ret = a;
66
break;
67
}
68
} else {
69
- which = 1;
70
+ ret = b;
71
break;
72
}
73
cmp = frac_cmp(a, b);
74
if (cmp == 0) {
75
cmp = a->sign < b->sign;
76
}
77
- which = cmp > 0 ? 0 : 1;
78
+ ret = cmp > 0 ? a : b;
79
break;
80
default:
22
g_assert_not_reached();
81
g_assert_not_reached();
23
}
82
}
24
83
25
- if (!guest_addr_valid(addr) || page_check_range(addr, size, flags) < 0) {
84
- if (which) {
26
+ if (!guest_addr_valid(addr) || page_check_range(addr, 1, flags) < 0) {
85
- a = b;
27
CPUState *cpu = env_cpu(env);
86
+ if (is_snan(ret->cls)) {
28
CPUClass *cc = CPU_GET_CLASS(cpu);
87
+ parts_silence_nan(ret, s);
29
cc->tlb_fill(cpu, addr, size, access_type, MMU_USER_IDX, false,
88
}
89
- if (is_snan(a->cls)) {
90
- parts_silence_nan(a, s);
91
- }
92
- return a;
93
+ return ret;
94
}
95
96
static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
30
--
97
--
31
2.20.1
98
2.34.1
32
99
33
100
diff view generated by jsdifflib
[PULL 07/34] hw/timer/nrf51_timer: Add trace event of counter value update
[PULL 71/72] MAINTAINERS: update email address for Leif Lindholm
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
2
2
3
Add trace event to display timer's counter value updates.
3
I'm migrating to Qualcomm's new open source email infrastructure, so
4
update my email address, and update the mailmap to match.
4
5
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
7
Message-id: 20200504072822.18799-5-f4bug@amsat.org
8
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
13
---
10
hw/timer/nrf51_timer.c | 1 +
14
MAINTAINERS | 2 +-
11
hw/timer/trace-events | 1 +
15
.mailmap | 5 +++--
12
2 files changed, 2 insertions(+)
16
2 files changed, 4 insertions(+), 3 deletions(-)
13
17
14
diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c
18
diff --git a/MAINTAINERS b/MAINTAINERS
15
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/timer/nrf51_timer.c
20
--- a/MAINTAINERS
17
+++ b/hw/timer/nrf51_timer.c
21
+++ b/MAINTAINERS
18
@@ -XXX,XX +XXX,XX @@ static void nrf51_timer_write(void *opaque, hwaddr offset,
22
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
19
23
SBSA-REF
20
idx = (offset - NRF51_TIMER_TASK_CAPTURE_0) / 4;
24
M: Radoslaw Biernacki <rad@semihalf.com>
21
s->cc[idx] = s->counter;
25
M: Peter Maydell <peter.maydell@linaro.org>
22
+ trace_nrf51_timer_set_count(s->id, idx, s->counter);
26
-R: Leif Lindholm <quic_llindhol@quicinc.com>
23
}
27
+R: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
24
break;
28
R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
25
case NRF51_TIMER_EVENT_COMPARE_0 ... NRF51_TIMER_EVENT_COMPARE_3:
29
L: qemu-arm@nongnu.org
26
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
30
S: Maintained
31
diff --git a/.mailmap b/.mailmap
27
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/timer/trace-events
33
--- a/.mailmap
29
+++ b/hw/timer/trace-events
34
+++ b/.mailmap
30
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
35
@@ -XXX,XX +XXX,XX @@ Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
31
# nrf51_timer.c
36
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
32
nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
37
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
33
nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
38
Juan Quintela <quintela@trasno.org> <quintela@redhat.com>
34
+nrf51_timer_set_count(uint8_t timer_id, uint8_t counter_id, uint32_t value) "timer %u counter %u count 0x%" PRIx32
39
-Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
35
40
-Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
36
# bcm2835_systmr.c
41
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <quic_llindhol@quicinc.com>
37
bcm2835_systmr_irq(bool enable) "timer irq state %u"
42
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif.lindholm@linaro.org>
43
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif@nuviainc.com>
44
Luc Michel <luc@lmichel.fr> <luc.michel@git.antfield.fr>
45
Luc Michel <luc@lmichel.fr> <luc.michel@greensocs.com>
46
Luc Michel <luc@lmichel.fr> <lmichel@kalray.eu>
38
--
47
--
39
2.20.1
48
2.34.1
40
49
41
50
diff view generated by jsdifflib
[PULL 32/34] hw/arm/musicpal: Map the UART devices unconditionally
[PULL 72/72] MAINTAINERS: Add correct email address for Vikram Garhwal
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Vikram Garhwal <vikram.garhwal@bytedance.com>
2
2
3
I can't find proper documentation or datasheet, but it is likely
3
Previously, maintainer role was paused due to inactive email id. Commit id:
4
a MMIO mapped serial device mapped in the 0x80000000..0x8000ffff
4
c009d715721861984c4987bcc78b7ee183e86d75.
5
range belongs to the SoC address space, thus is always mapped in
6
the memory bus.
7
Map the devices on the bus regardless a chardev is attached to it.
8
5
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Vikram Garhwal <vikram.garhwal@bytedance.com>
10
Reviewed-by: Jan Kiszka <jan.kiszka@web.de>
7
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
11
Message-id: 20200505095945.23146-1-f4bug@amsat.org
8
Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
hw/arm/musicpal.c | 12 ++++--------
11
MAINTAINERS | 2 ++
15
1 file changed, 4 insertions(+), 8 deletions(-)
12
1 file changed, 2 insertions(+)
16
13
17
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
14
diff --git a/MAINTAINERS b/MAINTAINERS
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/musicpal.c
16
--- a/MAINTAINERS
20
+++ b/hw/arm/musicpal.c
17
+++ b/MAINTAINERS
21
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
18
@@ -XXX,XX +XXX,XX @@ F: tests/qtest/fuzz-sb16-test.c
22
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
19
23
pic[MP_TIMER4_IRQ], NULL);
20
Xilinx CAN
24
21
M: Francisco Iglesias <francisco.iglesias@amd.com>
25
- if (serial_hd(0)) {
22
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
26
- serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
23
S: Maintained
27
- 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
24
F: hw/net/can/xlnx-*
28
- }
25
F: include/hw/net/xlnx-*
29
- if (serial_hd(1)) {
26
@@ -XXX,XX +XXX,XX @@ F: include/hw/rx/
30
- serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
27
CAN bus subsystem and hardware
31
- 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
28
M: Pavel Pisa <pisa@cmp.felk.cvut.cz>
32
- }
29
M: Francisco Iglesias <francisco.iglesias@amd.com>
33
+ serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
30
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
34
+ 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
31
S: Maintained
35
+ serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
32
W: https://canbus.pages.fel.cvut.cz/
36
+ 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
33
F: net/can/*
37
38
/* Register flash */
39
dinfo = drive_get(IF_PFLASH, 0, 0);
40
--
34
--
41
2.20.1
35
2.34.1
42
43
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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