1
The following changes since commit c88f1ffc19e38008a1c33ae039482a860aa7418c:
1
Some arm patches; my to-review queue is by no means empty, but
2
this is a big enough set of patches to be getting on with...
2
3
3
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2020-05-08 14:29:18 +0100)
4
-- PMM
5
6
The following changes since commit cb9c6a8e5ad6a1f0ce164d352e3102df46986e22:
7
8
.gitlab-ci.d/windows: Work-around timeout and OpenGL problems of the MSYS2 jobs (2023-01-04 18:58:33 +0000)
4
9
5
are available in the Git repository at:
10
are available in the Git repository at:
6
11
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200511
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230105
8
13
9
for you to fetch changes up to 7e17d50ebd359ee5fa3d65d7fdc0fe0336d60694:
14
for you to fetch changes up to 93c9678de9dc7d2e68f9e8477da072bac30ef132:
10
15
11
target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed) (2020-05-11 14:22:54 +0100)
16
hw/net: Fix read of uninitialized memory in imx_fec. (2023-01-05 15:33:00 +0000)
12
17
13
----------------------------------------------------------------
18
----------------------------------------------------------------
14
target-arm queue:
19
target-arm queue:
15
aspeed: Add boot stub for smp booting
20
* Implement AArch32 ARMv8-R support
16
target/arm: Drop access_el3_aa32ns_aa64any()
21
* Add Cortex-R52 CPU
17
aspeed: Support AST2600A1 silicon revision
22
* fix handling of HLT semihosting in system mode
18
aspeed: sdmc: Implement AST2600 locking behaviour
23
* hw/timer/ixm_epit: cleanup and fix bug in compare handling
19
nrf51: Tracing cleanups
24
* target/arm: Coding style fixes
20
target/arm: Improve handling of SVE loads and stores
25
* target/arm: Clean up includes
21
target/arm: Don't show TCG-only CPUs in KVM-only QEMU builds
26
* nseries: minor code cleanups
22
hw/arm/musicpal: Map the UART devices unconditionally
27
* target/arm: align exposed ID registers with Linux
23
target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)
28
* hw/arm/smmu-common: remove unnecessary inlines
24
target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
29
* i.MX7D: Handle GPT timers
30
* i.MX7D: Connect IRQs to GPIO devices
31
* i.MX6UL: Add a specific GPT timer instance
32
* hw/net: Fix read of uninitialized memory in imx_fec
25
33
26
----------------------------------------------------------------
34
----------------------------------------------------------------
27
Edgar E. Iglesias (1):
35
Alex Bennée (1):
28
target/arm: Drop access_el3_aa32ns_aa64any()
36
target/arm: fix handling of HLT semihosting in system mode
29
37
30
Joel Stanley (3):
38
Axel Heider (8):
31
aspeed: Add boot stub for smp booting
39
hw/timer/imx_epit: improve comments
32
aspeed: Support AST2600A1 silicon revision
40
hw/timer/imx_epit: cleanup CR defines
33
aspeed: sdmc: Implement AST2600 locking behaviour
41
hw/timer/imx_epit: define SR_OCIF
42
hw/timer/imx_epit: update interrupt state on CR write access
43
hw/timer/imx_epit: hard reset initializes CR with 0
44
hw/timer/imx_epit: factor out register write handlers
45
hw/timer/imx_epit: remove explicit fields cnt and freq
46
hw/timer/imx_epit: fix compare timer handling
34
47
35
Philippe Mathieu-Daudé (8):
48
Claudio Fontana (1):
36
hw/arm/nrf51: Add NRF51_PERIPHERAL_SIZE definition
49
target/arm: cleanup cpu includes
37
hw/timer/nrf51_timer: Display timer ID in trace events
38
hw/timer/nrf51_timer: Add trace event of counter value update
39
target/arm/kvm: Inline set_feature() calls
40
target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]
41
target/arm/cpu: Restrict v8M IDAU interface to Aarch32 CPUs
42
target/arm: Restrict TCG cpus to TCG accel
43
hw/arm/musicpal: Map the UART devices unconditionally
44
50
45
Richard Henderson (21):
51
Fabiano Rosas (5):
46
exec: Add block comments for watchpoint routines
52
target/arm: Fix checkpatch comment style warnings in helper.c
47
exec: Fix cpu_watchpoint_address_matches address length
53
target/arm: Fix checkpatch space errors in helper.c
48
accel/tcg: Add block comment for probe_access
54
target/arm: Fix checkpatch brace errors in helper.c
49
accel/tcg: Adjust probe_access call to page_check_range
55
target/arm: Remove unused includes from m_helper.c
50
accel/tcg: Add probe_access_flags
56
target/arm: Remove unused includes from helper.c
51
accel/tcg: Add endian-specific cpu_{ld, st}* operations
52
target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn
53
target/arm: Drop manual handling of set/clear_helper_retaddr
54
target/arm: Add sve infrastructure for page lookup
55
target/arm: Adjust interface of sve_ld1_host_fn
56
target/arm: Use SVEContLdSt in sve_ld1_r
57
target/arm: Handle watchpoints in sve_ld1_r
58
target/arm: Use SVEContLdSt for multi-register contiguous loads
59
target/arm: Update contiguous first-fault and no-fault loads
60
target/arm: Use SVEContLdSt for contiguous stores
61
target/arm: Reuse sve_probe_page for gather first-fault loads
62
target/arm: Reuse sve_probe_page for scatter stores
63
target/arm: Reuse sve_probe_page for gather loads
64
target/arm: Remove sve_memopidx
65
target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
66
target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)
67
57
68
Thomas Huth (1):
58
Jean-Christophe Dubois (4):
69
target/arm: Make set_feature() available for other files
59
i.MX7D: Connect GPT timers to IRQ
60
i.MX7D: Compute clock frequency for the fixed frequency clocks.
61
i.MX6UL: Add a specific GPT timer instance for the i.MX6UL
62
i.MX7D: Connect IRQs to GPIO devices.
70
63
71
docs/devel/loads-stores.rst | 39 +-
64
Peter Maydell (1):
72
include/exec/cpu-all.h | 13 +-
65
target/arm:Set lg_page_size to 0 if either S1 or S2 asks for it
73
include/exec/cpu_ldst.h | 283 +++--
74
include/exec/exec-all.h | 39 +
75
include/hw/arm/nrf51.h | 3 +-
76
include/hw/core/cpu.h | 23 +
77
include/hw/i2c/microbit_i2c.h | 2 +-
78
include/hw/misc/aspeed_scu.h | 1 +
79
include/hw/timer/nrf51_timer.h | 1 +
80
target/arm/cpu.h | 10 +
81
target/arm/helper-sve.h | 45 +-
82
target/arm/internals.h | 5 -
83
accel/tcg/cputlb.c | 413 ++++---
84
accel/tcg/user-exec.c | 256 ++++-
85
exec.c | 2 +-
86
hw/arm/aspeed.c | 73 +-
87
hw/arm/aspeed_ast2600.c | 6 +-
88
hw/arm/musicpal.c | 12 +-
89
hw/arm/nrf51_soc.c | 9 +-
90
hw/i2c/microbit_i2c.c | 2 +-
91
hw/misc/aspeed_scu.c | 11 +-
92
hw/misc/aspeed_sdmc.c | 55 +-
93
hw/timer/nrf51_timer.c | 14 +-
94
target/arm/cpu.c | 662 +----------
95
target/arm/cpu64.c | 18 +-
96
target/arm/cpu_tcg.c | 664 +++++++++++
97
target/arm/helper.c | 30 +-
98
target/arm/kvm32.c | 13 +-
99
target/arm/kvm64.c | 22 +-
100
target/arm/sve_helper.c | 2398 +++++++++++++++++++++-------------------
101
target/arm/translate-sve.c | 93 +-
102
hw/timer/trace-events | 5 +-
103
target/arm/Makefile.objs | 1 +
104
33 files changed, 2975 insertions(+), 2248 deletions(-)
105
create mode 100644 target/arm/cpu_tcg.c
106
66
67
Philippe Mathieu-Daudé (5):
68
hw/input/tsc2xxx: Constify set_transform()'s MouseTransformInfo arg
69
hw/arm/nseries: Constify various read-only arrays
70
hw/arm/nseries: Silent -Wmissing-field-initializers warning
71
hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scope
72
hw/arm/smmu-common: Avoid using inlined functions with external linkage
73
74
Stephen Longfield (1):
75
hw/net: Fix read of uninitialized memory in imx_fec.
76
77
Tobias Röhmel (7):
78
target/arm: Don't add all MIDR aliases for cores that implement PMSA
79
target/arm: Make RVBAR available for all ARMv8 CPUs
80
target/arm: Make stage_2_format for cache attributes optional
81
target/arm: Enable TTBCR_EAE for ARMv8-R AArch32
82
target/arm: Add PMSAv8r registers
83
target/arm: Add PMSAv8r functionality
84
target/arm: Add ARM Cortex-R52 CPU
85
86
Zhuojia Shen (1):
87
target/arm: align exposed ID registers with Linux
88
89
include/hw/arm/fsl-imx7.h | 20 +
90
include/hw/arm/smmu-common.h | 3 -
91
include/hw/input/tsc2xxx.h | 4 +-
92
include/hw/timer/imx_epit.h | 8 +-
93
include/hw/timer/imx_gpt.h | 1 +
94
target/arm/cpu.h | 6 +
95
target/arm/internals.h | 4 +
96
hw/arm/fsl-imx6ul.c | 2 +-
97
hw/arm/fsl-imx7.c | 41 +-
98
hw/arm/nseries.c | 28 +-
99
hw/arm/smmu-common.c | 15 +-
100
hw/input/tsc2005.c | 2 +-
101
hw/input/tsc210x.c | 3 +-
102
hw/misc/imx6ul_ccm.c | 6 -
103
hw/misc/imx7_ccm.c | 49 ++-
104
hw/net/imx_fec.c | 8 +-
105
hw/timer/imx_epit.c | 376 +++++++++-------
106
hw/timer/imx_gpt.c | 25 ++
107
target/arm/cpu.c | 35 +-
108
target/arm/cpu64.c | 6 -
109
target/arm/cpu_tcg.c | 42 ++
110
target/arm/debug_helper.c | 3 +
111
target/arm/helper.c | 871 +++++++++++++++++++++++++++++---------
112
target/arm/m_helper.c | 16 -
113
target/arm/machine.c | 28 ++
114
target/arm/ptw.c | 152 +++++--
115
target/arm/tlb_helper.c | 4 +
116
target/arm/translate.c | 2 +-
117
tests/tcg/aarch64/sysregs.c | 24 +-
118
tests/tcg/aarch64/Makefile.target | 7 +-
119
30 files changed, 1330 insertions(+), 461 deletions(-)
120
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In get_phys_addr_twostage() we set the lg_page_size of the result to
2
the maximum of the stage 1 and stage 2 page sizes. This works for
3
the case where we do want to create a TLB entry, because we know the
4
common TLB code only creates entries of the TARGET_PAGE_SIZE and
5
asking for a size larger than that only means that invalidations
6
invalidate the whole larger area. However, if lg_page_size is
7
smaller than TARGET_PAGE_SIZE this effectively means "don't create a
8
TLB entry"; in this case if either S1 or S2 said "this covers less
9
than a page and can't go in a TLB" then the final result also should
10
be marked that way. Set the resulting page size to 0 if either
11
stage asked for a less-than-a-page entry, and expand the comment
12
to explain what's going on.
2
13
3
This avoids the need for a separate set of helpers to implement
14
This has no effect for VMSA because currently the VMSA lookup always
4
no-fault semantics, and will enable MTE in the future.
15
returns results that cover at least TARGET_PAGE_SIZE; however when we
16
add v8R support it will reuse this code path, and for v8R the S1 and
17
S2 results can be smaller than TARGET_PAGE_SIZE.
5
18
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200508154359.7494-17-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20221212142708.610090-1-peter.maydell@linaro.org
10
---
22
---
11
target/arm/sve_helper.c | 323 ++++++++++++++++------------------------
23
target/arm/ptw.c | 16 +++++++++++++---
12
1 file changed, 127 insertions(+), 196 deletions(-)
24
1 file changed, 13 insertions(+), 3 deletions(-)
13
25
14
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
26
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
15
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/sve_helper.c
28
--- a/target/arm/ptw.c
17
+++ b/target/arm/sve_helper.c
29
+++ b/target/arm/ptw.c
18
@@ -XXX,XX +XXX,XX @@ DO_LD1_ZPZ_D(dd_be, zd)
30
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
19
20
/* First fault loads with a vector index. */
21
22
-/* Load one element into VD+REG_OFF from (ENV,VADDR) without faulting.
23
- * The controlling predicate is known to be true. Return true if the
24
- * load was successful.
25
- */
26
-typedef bool sve_ld1_nf_fn(CPUARMState *env, void *vd, intptr_t reg_off,
27
- target_ulong vaddr, int mmu_idx);
28
-
29
-#ifdef CONFIG_SOFTMMU
30
-#define DO_LD_NF(NAME, H, TYPEE, TYPEM, HOST) \
31
-static bool sve_ld##NAME##_nf(CPUARMState *env, void *vd, intptr_t reg_off, \
32
- target_ulong addr, int mmu_idx) \
33
-{ \
34
- target_ulong next_page = -(addr | TARGET_PAGE_MASK); \
35
- if (likely(next_page - addr >= sizeof(TYPEM))) { \
36
- void *host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_idx); \
37
- if (likely(host)) { \
38
- TYPEM val = HOST(host); \
39
- *(TYPEE *)(vd + H(reg_off)) = val; \
40
- return true; \
41
- } \
42
- } \
43
- return false; \
44
-}
45
-#else
46
-#define DO_LD_NF(NAME, H, TYPEE, TYPEM, HOST) \
47
-static bool sve_ld##NAME##_nf(CPUARMState *env, void *vd, intptr_t reg_off, \
48
- target_ulong addr, int mmu_idx) \
49
-{ \
50
- if (likely(page_check_range(addr, sizeof(TYPEM), PAGE_READ))) { \
51
- TYPEM val = HOST(g2h(addr)); \
52
- *(TYPEE *)(vd + H(reg_off)) = val; \
53
- return true; \
54
- } \
55
- return false; \
56
-}
57
-#endif
58
-
59
-DO_LD_NF(bsu, H1_4, uint32_t, uint8_t, ldub_p)
60
-DO_LD_NF(bss, H1_4, uint32_t, int8_t, ldsb_p)
61
-DO_LD_NF(bdu, , uint64_t, uint8_t, ldub_p)
62
-DO_LD_NF(bds, , uint64_t, int8_t, ldsb_p)
63
-
64
-DO_LD_NF(hsu_le, H1_4, uint32_t, uint16_t, lduw_le_p)
65
-DO_LD_NF(hss_le, H1_4, uint32_t, int16_t, ldsw_le_p)
66
-DO_LD_NF(hsu_be, H1_4, uint32_t, uint16_t, lduw_be_p)
67
-DO_LD_NF(hss_be, H1_4, uint32_t, int16_t, ldsw_be_p)
68
-DO_LD_NF(hdu_le, , uint64_t, uint16_t, lduw_le_p)
69
-DO_LD_NF(hds_le, , uint64_t, int16_t, ldsw_le_p)
70
-DO_LD_NF(hdu_be, , uint64_t, uint16_t, lduw_be_p)
71
-DO_LD_NF(hds_be, , uint64_t, int16_t, ldsw_be_p)
72
-
73
-DO_LD_NF(ss_le, H1_4, uint32_t, uint32_t, ldl_le_p)
74
-DO_LD_NF(ss_be, H1_4, uint32_t, uint32_t, ldl_be_p)
75
-DO_LD_NF(sdu_le, , uint64_t, uint32_t, ldl_le_p)
76
-DO_LD_NF(sds_le, , uint64_t, int32_t, ldl_le_p)
77
-DO_LD_NF(sdu_be, , uint64_t, uint32_t, ldl_be_p)
78
-DO_LD_NF(sds_be, , uint64_t, int32_t, ldl_be_p)
79
-
80
-DO_LD_NF(dd_le, , uint64_t, uint64_t, ldq_le_p)
81
-DO_LD_NF(dd_be, , uint64_t, uint64_t, ldq_be_p)
82
-
83
/*
84
- * Common helper for all gather first-faulting loads.
85
+ * Common helpers for all gather first-faulting loads.
86
*/
87
-static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
88
- target_ulong base, uint32_t desc, uintptr_t ra,
89
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
90
- sve_ld1_nf_fn *nonfault_fn)
91
+
92
+static inline QEMU_ALWAYS_INLINE
93
+void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
94
+ target_ulong base, uint32_t desc, uintptr_t retaddr,
95
+ const int esz, const int msz, zreg_off_fn *off_fn,
96
+ sve_ldst1_host_fn *host_fn,
97
+ sve_ldst1_tlb_fn *tlb_fn)
98
{
99
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
100
- const int mmu_idx = get_mmuidx(oi);
101
+ const int mmu_idx = cpu_mmu_index(env, false);
102
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
103
- intptr_t reg_off, reg_max = simd_oprsz(desc);
104
- target_ulong addr;
105
+ const int esize = 1 << esz;
106
+ const int msize = 1 << msz;
107
+ const intptr_t reg_max = simd_oprsz(desc);
108
+ intptr_t reg_off;
109
+ SVEHostPage info;
110
+ target_ulong addr, in_page;
111
112
/* Skip to the first true predicate. */
113
- reg_off = find_next_active(vg, 0, reg_max, MO_32);
114
- if (likely(reg_off < reg_max)) {
115
- /* Perform one normal read, which will fault or not. */
116
- addr = off_fn(vm, reg_off);
117
- addr = base + (addr << scale);
118
- tlb_fn(env, vd, reg_off, addr, ra);
119
-
120
- /* The rest of the reads will be non-faulting. */
121
+ reg_off = find_next_active(vg, 0, reg_max, esz);
122
+ if (unlikely(reg_off >= reg_max)) {
123
+ /* The entire predicate was false; no load occurs. */
124
+ memset(vd, 0, reg_max);
125
+ return;
126
}
31
}
127
32
128
- /* After any fault, zero the leading predicated false elements. */
33
/*
129
+ /*
34
- * Use the maximum of the S1 & S2 page size, so that invalidation
130
+ * Probe the first element, allowing faults.
35
- * of pages > TARGET_PAGE_SIZE works correctly.
131
+ */
36
+ * If either S1 or S2 returned a result smaller than TARGET_PAGE_SIZE,
132
+ addr = base + (off_fn(vm, reg_off) << scale);
37
+ * this means "don't put this in the TLB"; in this case, return a
133
+ tlb_fn(env, vd, reg_off, addr, retaddr);
38
+ * result with lg_page_size == 0 to achieve that. Otherwise,
134
+
39
+ * use the maximum of the S1 & S2 page size, so that invalidation
135
+ /* After any fault, zero the other elements. */
40
+ * of pages > TARGET_PAGE_SIZE works correctly. (This works even though
136
swap_memzero(vd, reg_off);
41
+ * we know the combined result permissions etc only cover the minimum
137
+ reg_off += esize;
42
+ * of the S1 and S2 page size, because we know that the common TLB code
138
+ swap_memzero(vd + reg_off, reg_max - reg_off);
43
+ * never actually creates TLB entries bigger than TARGET_PAGE_SIZE,
139
44
+ * and passing a larger page size value only affects invalidations.)
140
- while (likely((reg_off += 4) < reg_max)) {
45
*/
141
- uint64_t pg = *(uint64_t *)(vg + (reg_off >> 6) * 8);
46
- if (result->f.lg_page_size < s1_lgpgsz) {
142
- if (likely((pg >> (reg_off & 63)) & 1)) {
47
+ if (result->f.lg_page_size < TARGET_PAGE_BITS ||
143
- addr = off_fn(vm, reg_off);
48
+ s1_lgpgsz < TARGET_PAGE_BITS) {
144
- addr = base + (addr << scale);
49
+ result->f.lg_page_size = 0;
145
- if (!nonfault_fn(env, vd, reg_off, addr, mmu_idx)) {
50
+ } else if (result->f.lg_page_size < s1_lgpgsz) {
146
- record_fault(env, reg_off, reg_max);
51
result->f.lg_page_size = s1_lgpgsz;
147
- break;
148
+ /*
149
+ * Probe the remaining elements, not allowing faults.
150
+ */
151
+ while (reg_off < reg_max) {
152
+ uint64_t pg = vg[reg_off >> 6];
153
+ do {
154
+ if (likely((pg >> (reg_off & 63)) & 1)) {
155
+ addr = base + (off_fn(vm, reg_off) << scale);
156
+ in_page = -(addr | TARGET_PAGE_MASK);
157
+
158
+ if (unlikely(in_page < msize)) {
159
+ /* Stop if the element crosses a page boundary. */
160
+ goto fault;
161
+ }
162
+
163
+ sve_probe_page(&info, true, env, addr, 0, MMU_DATA_LOAD,
164
+ mmu_idx, retaddr);
165
+ if (unlikely(info.flags & (TLB_INVALID_MASK | TLB_MMIO))) {
166
+ goto fault;
167
+ }
168
+ if (unlikely(info.flags & TLB_WATCHPOINT) &&
169
+ (cpu_watchpoint_address_matches
170
+ (env_cpu(env), addr, msize) & BP_MEM_READ)) {
171
+ goto fault;
172
+ }
173
+ /* TODO: MTE check. */
174
+
175
+ host_fn(vd, reg_off, info.host);
176
}
177
- } else {
178
- *(uint32_t *)(vd + H1_4(reg_off)) = 0;
179
- }
180
+ reg_off += esize;
181
+ } while (reg_off & 63);
182
}
52
}
183
+ return;
184
+
185
+ fault:
186
+ record_fault(env, reg_off, reg_max);
187
}
188
189
-static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
190
- target_ulong base, uint32_t desc, uintptr_t ra,
191
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
192
- sve_ld1_nf_fn *nonfault_fn)
193
-{
194
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
195
- const int mmu_idx = get_mmuidx(oi);
196
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
197
- intptr_t reg_off, reg_max = simd_oprsz(desc);
198
- target_ulong addr;
199
-
200
- /* Skip to the first true predicate. */
201
- reg_off = find_next_active(vg, 0, reg_max, MO_64);
202
- if (likely(reg_off < reg_max)) {
203
- /* Perform one normal read, which will fault or not. */
204
- addr = off_fn(vm, reg_off);
205
- addr = base + (addr << scale);
206
- tlb_fn(env, vd, reg_off, addr, ra);
207
-
208
- /* The rest of the reads will be non-faulting. */
209
- }
210
-
211
- /* After any fault, zero the leading predicated false elements. */
212
- swap_memzero(vd, reg_off);
213
-
214
- while (likely((reg_off += 8) < reg_max)) {
215
- uint8_t pg = *(uint8_t *)(vg + H1(reg_off >> 3));
216
- if (likely(pg & 1)) {
217
- addr = off_fn(vm, reg_off);
218
- addr = base + (addr << scale);
219
- if (!nonfault_fn(env, vd, reg_off, addr, mmu_idx)) {
220
- record_fault(env, reg_off, reg_max);
221
- break;
222
- }
223
- } else {
224
- *(uint64_t *)(vd + reg_off) = 0;
225
- }
226
- }
227
+#define DO_LDFF1_ZPZ_S(MEM, OFS, MSZ) \
228
+void HELPER(sve_ldff##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
229
+ void *vm, target_ulong base, uint32_t desc) \
230
+{ \
231
+ sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), MO_32, MSZ, \
232
+ off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
233
}
234
235
-#define DO_LDFF1_ZPZ_S(MEM, OFS) \
236
-void HELPER(sve_ldff##MEM##_##OFS) \
237
- (CPUARMState *env, void *vd, void *vg, void *vm, \
238
- target_ulong base, uint32_t desc) \
239
-{ \
240
- sve_ldff1_zs(env, vd, vg, vm, base, desc, GETPC(), \
241
- off_##OFS##_s, sve_ld1##MEM##_tlb, sve_ld##MEM##_nf); \
242
+#define DO_LDFF1_ZPZ_D(MEM, OFS, MSZ) \
243
+void HELPER(sve_ldff##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
244
+ void *vm, target_ulong base, uint32_t desc) \
245
+{ \
246
+ sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), MO_64, MSZ, \
247
+ off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
248
}
249
250
-#define DO_LDFF1_ZPZ_D(MEM, OFS) \
251
-void HELPER(sve_ldff##MEM##_##OFS) \
252
- (CPUARMState *env, void *vd, void *vg, void *vm, \
253
- target_ulong base, uint32_t desc) \
254
-{ \
255
- sve_ldff1_zd(env, vd, vg, vm, base, desc, GETPC(), \
256
- off_##OFS##_d, sve_ld1##MEM##_tlb, sve_ld##MEM##_nf); \
257
-}
258
+DO_LDFF1_ZPZ_S(bsu, zsu, MO_8)
259
+DO_LDFF1_ZPZ_S(bsu, zss, MO_8)
260
+DO_LDFF1_ZPZ_D(bdu, zsu, MO_8)
261
+DO_LDFF1_ZPZ_D(bdu, zss, MO_8)
262
+DO_LDFF1_ZPZ_D(bdu, zd, MO_8)
263
264
-DO_LDFF1_ZPZ_S(bsu, zsu)
265
-DO_LDFF1_ZPZ_S(bsu, zss)
266
-DO_LDFF1_ZPZ_D(bdu, zsu)
267
-DO_LDFF1_ZPZ_D(bdu, zss)
268
-DO_LDFF1_ZPZ_D(bdu, zd)
269
+DO_LDFF1_ZPZ_S(bss, zsu, MO_8)
270
+DO_LDFF1_ZPZ_S(bss, zss, MO_8)
271
+DO_LDFF1_ZPZ_D(bds, zsu, MO_8)
272
+DO_LDFF1_ZPZ_D(bds, zss, MO_8)
273
+DO_LDFF1_ZPZ_D(bds, zd, MO_8)
274
275
-DO_LDFF1_ZPZ_S(bss, zsu)
276
-DO_LDFF1_ZPZ_S(bss, zss)
277
-DO_LDFF1_ZPZ_D(bds, zsu)
278
-DO_LDFF1_ZPZ_D(bds, zss)
279
-DO_LDFF1_ZPZ_D(bds, zd)
280
+DO_LDFF1_ZPZ_S(hsu_le, zsu, MO_16)
281
+DO_LDFF1_ZPZ_S(hsu_le, zss, MO_16)
282
+DO_LDFF1_ZPZ_D(hdu_le, zsu, MO_16)
283
+DO_LDFF1_ZPZ_D(hdu_le, zss, MO_16)
284
+DO_LDFF1_ZPZ_D(hdu_le, zd, MO_16)
285
286
-DO_LDFF1_ZPZ_S(hsu_le, zsu)
287
-DO_LDFF1_ZPZ_S(hsu_le, zss)
288
-DO_LDFF1_ZPZ_D(hdu_le, zsu)
289
-DO_LDFF1_ZPZ_D(hdu_le, zss)
290
-DO_LDFF1_ZPZ_D(hdu_le, zd)
291
+DO_LDFF1_ZPZ_S(hsu_be, zsu, MO_16)
292
+DO_LDFF1_ZPZ_S(hsu_be, zss, MO_16)
293
+DO_LDFF1_ZPZ_D(hdu_be, zsu, MO_16)
294
+DO_LDFF1_ZPZ_D(hdu_be, zss, MO_16)
295
+DO_LDFF1_ZPZ_D(hdu_be, zd, MO_16)
296
297
-DO_LDFF1_ZPZ_S(hsu_be, zsu)
298
-DO_LDFF1_ZPZ_S(hsu_be, zss)
299
-DO_LDFF1_ZPZ_D(hdu_be, zsu)
300
-DO_LDFF1_ZPZ_D(hdu_be, zss)
301
-DO_LDFF1_ZPZ_D(hdu_be, zd)
302
+DO_LDFF1_ZPZ_S(hss_le, zsu, MO_16)
303
+DO_LDFF1_ZPZ_S(hss_le, zss, MO_16)
304
+DO_LDFF1_ZPZ_D(hds_le, zsu, MO_16)
305
+DO_LDFF1_ZPZ_D(hds_le, zss, MO_16)
306
+DO_LDFF1_ZPZ_D(hds_le, zd, MO_16)
307
308
-DO_LDFF1_ZPZ_S(hss_le, zsu)
309
-DO_LDFF1_ZPZ_S(hss_le, zss)
310
-DO_LDFF1_ZPZ_D(hds_le, zsu)
311
-DO_LDFF1_ZPZ_D(hds_le, zss)
312
-DO_LDFF1_ZPZ_D(hds_le, zd)
313
+DO_LDFF1_ZPZ_S(hss_be, zsu, MO_16)
314
+DO_LDFF1_ZPZ_S(hss_be, zss, MO_16)
315
+DO_LDFF1_ZPZ_D(hds_be, zsu, MO_16)
316
+DO_LDFF1_ZPZ_D(hds_be, zss, MO_16)
317
+DO_LDFF1_ZPZ_D(hds_be, zd, MO_16)
318
319
-DO_LDFF1_ZPZ_S(hss_be, zsu)
320
-DO_LDFF1_ZPZ_S(hss_be, zss)
321
-DO_LDFF1_ZPZ_D(hds_be, zsu)
322
-DO_LDFF1_ZPZ_D(hds_be, zss)
323
-DO_LDFF1_ZPZ_D(hds_be, zd)
324
+DO_LDFF1_ZPZ_S(ss_le, zsu, MO_32)
325
+DO_LDFF1_ZPZ_S(ss_le, zss, MO_32)
326
+DO_LDFF1_ZPZ_D(sdu_le, zsu, MO_32)
327
+DO_LDFF1_ZPZ_D(sdu_le, zss, MO_32)
328
+DO_LDFF1_ZPZ_D(sdu_le, zd, MO_32)
329
330
-DO_LDFF1_ZPZ_S(ss_le, zsu)
331
-DO_LDFF1_ZPZ_S(ss_le, zss)
332
-DO_LDFF1_ZPZ_D(sdu_le, zsu)
333
-DO_LDFF1_ZPZ_D(sdu_le, zss)
334
-DO_LDFF1_ZPZ_D(sdu_le, zd)
335
+DO_LDFF1_ZPZ_S(ss_be, zsu, MO_32)
336
+DO_LDFF1_ZPZ_S(ss_be, zss, MO_32)
337
+DO_LDFF1_ZPZ_D(sdu_be, zsu, MO_32)
338
+DO_LDFF1_ZPZ_D(sdu_be, zss, MO_32)
339
+DO_LDFF1_ZPZ_D(sdu_be, zd, MO_32)
340
341
-DO_LDFF1_ZPZ_S(ss_be, zsu)
342
-DO_LDFF1_ZPZ_S(ss_be, zss)
343
-DO_LDFF1_ZPZ_D(sdu_be, zsu)
344
-DO_LDFF1_ZPZ_D(sdu_be, zss)
345
-DO_LDFF1_ZPZ_D(sdu_be, zd)
346
+DO_LDFF1_ZPZ_D(sds_le, zsu, MO_32)
347
+DO_LDFF1_ZPZ_D(sds_le, zss, MO_32)
348
+DO_LDFF1_ZPZ_D(sds_le, zd, MO_32)
349
350
-DO_LDFF1_ZPZ_D(sds_le, zsu)
351
-DO_LDFF1_ZPZ_D(sds_le, zss)
352
-DO_LDFF1_ZPZ_D(sds_le, zd)
353
+DO_LDFF1_ZPZ_D(sds_be, zsu, MO_32)
354
+DO_LDFF1_ZPZ_D(sds_be, zss, MO_32)
355
+DO_LDFF1_ZPZ_D(sds_be, zd, MO_32)
356
357
-DO_LDFF1_ZPZ_D(sds_be, zsu)
358
-DO_LDFF1_ZPZ_D(sds_be, zss)
359
-DO_LDFF1_ZPZ_D(sds_be, zd)
360
+DO_LDFF1_ZPZ_D(dd_le, zsu, MO_64)
361
+DO_LDFF1_ZPZ_D(dd_le, zss, MO_64)
362
+DO_LDFF1_ZPZ_D(dd_le, zd, MO_64)
363
364
-DO_LDFF1_ZPZ_D(dd_le, zsu)
365
-DO_LDFF1_ZPZ_D(dd_le, zss)
366
-DO_LDFF1_ZPZ_D(dd_le, zd)
367
-
368
-DO_LDFF1_ZPZ_D(dd_be, zsu)
369
-DO_LDFF1_ZPZ_D(dd_be, zss)
370
-DO_LDFF1_ZPZ_D(dd_be, zd)
371
+DO_LDFF1_ZPZ_D(dd_be, zsu, MO_64)
372
+DO_LDFF1_ZPZ_D(dd_be, zss, MO_64)
373
+DO_LDFF1_ZPZ_D(dd_be, zd, MO_64)
374
375
/* Stores with a vector index. */
376
53
377
--
54
--
378
2.20.1
55
2.25.1
379
380
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
2
3
DUP (indexed) can duplicate 128-bit elements, so using esz
3
Cores with PMSA have the MPUIR register which has the
4
unconditionally can assert in tcg_gen_gvec_dup_imm.
4
same encoding as the MIDR alias with opc2=4. So we only
5
add that alias if we are not realizing a core that
6
implements PMSA.
5
7
6
Fixes: 8711e71f9cbb
8
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
7
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Message-id: 20221206102504.165775-2-tobias.roehmel@rwth-aachen.de
10
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Message-id: 20200507172352.15418-5-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
13
---
14
target/arm/translate-sve.c | 6 +++++-
14
target/arm/helper.c | 13 +++++++++----
15
1 file changed, 5 insertions(+), 1 deletion(-)
15
1 file changed, 9 insertions(+), 4 deletions(-)
16
16
17
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
18
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate-sve.c
19
--- a/target/arm/helper.c
20
+++ b/target/arm/translate-sve.c
20
+++ b/target/arm/helper.c
21
@@ -XXX,XX +XXX,XX @@ static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a)
21
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
22
unsigned nofs = vec_reg_offset(s, a->rn, index, esz);
22
.access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
23
tcg_gen_gvec_dup_mem(esz, dofs, nofs, vsz, vsz);
23
.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
24
.readfn = midr_read },
25
- /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
26
- { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
27
- .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
28
- .access = PL1_R, .resetvalue = cpu->midr },
29
+ /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
30
{ .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
31
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
32
.access = PL1_R, .resetvalue = cpu->midr },
33
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
34
.accessfn = access_aa64_tid1,
35
.type = ARM_CP_CONST, .resetvalue = cpu->revidr },
36
};
37
+ ARMCPRegInfo id_v8_midr_alias_cp_reginfo = {
38
+ .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
39
+ .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
40
+ .access = PL1_R, .resetvalue = cpu->midr
41
+ };
42
ARMCPRegInfo id_cp_reginfo[] = {
43
/* These are common to v8 and pre-v8 */
44
{ .name = "CTR",
45
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
46
}
47
if (arm_feature(env, ARM_FEATURE_V8)) {
48
define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
49
+ if (!arm_feature(env, ARM_FEATURE_PMSA)) {
50
+ define_one_arm_cp_reg(cpu, &id_v8_midr_alias_cp_reginfo);
51
+ }
24
} else {
52
} else {
25
- tcg_gen_gvec_dup_imm(esz, dofs, vsz, vsz, 0);
53
define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
26
+ /*
27
+ * While dup_mem handles 128-bit elements, dup_imm does not.
28
+ * Thankfully element size doesn't matter for splatting zero.
29
+ */
30
+ tcg_gen_gvec_dup_imm(MO_64, dofs, vsz, vsz, 0);
31
}
54
}
32
}
33
return true;
34
--
55
--
35
2.20.1
56
2.25.1
36
57
37
58
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
2
3
As IDAU is a v8M feature, restrict it to the Aarch32 CPUs.
3
RVBAR shadows RVBAR_ELx where x is the highest exception
4
level if the highest EL is not EL3. This patch also allows
5
ARMv8 CPUs to change the reset address with
6
the rvbar property.
4
7
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20200504172448.9402-5-philmd@redhat.com
10
Message-id: 20221206102504.165775-3-tobias.roehmel@rwth-aachen.de
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
target/arm/cpu.c | 2 +-
13
target/arm/cpu.c | 6 +++++-
11
1 file changed, 1 insertion(+), 1 deletion(-)
14
target/arm/helper.c | 21 ++++++++++++++-------
15
2 files changed, 19 insertions(+), 8 deletions(-)
12
16
13
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
17
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
14
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.c
19
--- a/target/arm/cpu.c
16
+++ b/target/arm/cpu.c
20
+++ b/target/arm/cpu.c
17
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void)
21
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
18
const size_t cpu_count = ARRAY_SIZE(arm_cpus);
22
env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
19
23
CPACR, CP11, 3);
20
type_register_static(&arm_cpu_type_info);
24
#endif
21
- type_register_static(&idau_interface_type_info);
25
+ if (arm_feature(env, ARM_FEATURE_V8)) {
22
26
+ env->cp15.rvbar = cpu->rvbar_prop;
23
#ifdef CONFIG_KVM
27
+ env->regs[15] = cpu->rvbar_prop;
24
type_register_static(&host_arm_cpu_type_info);
28
+ }
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void)
29
}
26
if (cpu_count) {
30
27
size_t i;
31
#if defined(CONFIG_USER_ONLY)
28
32
@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
29
+ type_register_static(&idau_interface_type_info);
33
qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
30
for (i = 0; i < cpu_count; ++i) {
34
}
31
arm_cpu_register(&arm_cpus[i]);
35
36
- if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
37
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
38
object_property_add_uint64_ptr(obj, "rvbar",
39
&cpu->rvbar_prop,
40
OBJ_PROP_FLAG_READWRITE);
41
diff --git a/target/arm/helper.c b/target/arm/helper.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/helper.c
44
+++ b/target/arm/helper.c
45
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
46
if (!arm_feature(env, ARM_FEATURE_EL3) &&
47
!arm_feature(env, ARM_FEATURE_EL2)) {
48
ARMCPRegInfo rvbar = {
49
- .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
50
+ .name = "RVBAR_EL1", .state = ARM_CP_STATE_BOTH,
51
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
52
.access = PL1_R,
53
.fieldoffset = offsetof(CPUARMState, cp15.rvbar),
54
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
32
}
55
}
56
/* RVBAR_EL2 is only implemented if EL2 is the highest EL */
57
if (!arm_feature(env, ARM_FEATURE_EL3)) {
58
- ARMCPRegInfo rvbar = {
59
- .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
60
- .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
61
- .access = PL2_R,
62
- .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
63
+ ARMCPRegInfo rvbar[] = {
64
+ {
65
+ .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
66
+ .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
67
+ .access = PL2_R,
68
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
69
+ },
70
+ { .name = "RVBAR", .type = ARM_CP_ALIAS,
71
+ .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
72
+ .access = PL2_R,
73
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
74
+ },
75
};
76
- define_one_arm_cp_reg(cpu, &rvbar);
77
+ define_arm_cp_regs(cpu, rvbar);
78
}
79
}
80
33
--
81
--
34
2.20.1
82
2.25.1
35
83
36
84
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
2
3
I can't find proper documentation or datasheet, but it is likely
3
The v8R PMSAv8 has a two-stage MPU translation process, but, unlike
4
a MMIO mapped serial device mapped in the 0x80000000..0x8000ffff
4
VMSAv8, the stage 2 attributes are in the same format as the stage 1
5
range belongs to the SoC address space, thus is always mapped in
5
attributes (8-bit MAIR format). Rather than converting the MAIR
6
the memory bus.
6
format to the format used for VMSA stage 2 (bits [5:2] of a VMSA
7
Map the devices on the bus regardless a chardev is attached to it.
7
stage 2 descriptor) and then converting back to do the attribute
8
combination, allow combined_attrs_nofwb() to accept s2 attributes
9
that are already in the MAIR format.
8
10
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
We move the assert() to combined_attrs_fwb(), because that function
10
Reviewed-by: Jan Kiszka <jan.kiszka@web.de>
12
really does require a VMSA stage 2 attribute format. (We will never
11
Message-id: 20200505095945.23146-1-f4bug@amsat.org
13
get there for v8R, because PMSAv8 does not implement FEAT_S2FWB.)
14
15
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 20221206102504.165775-4-tobias.roehmel@rwth-aachen.de
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
19
---
14
hw/arm/musicpal.c | 12 ++++--------
20
target/arm/ptw.c | 10 ++++++++--
15
1 file changed, 4 insertions(+), 8 deletions(-)
21
1 file changed, 8 insertions(+), 2 deletions(-)
16
22
17
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
23
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
18
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/musicpal.c
25
--- a/target/arm/ptw.c
20
+++ b/hw/arm/musicpal.c
26
+++ b/target/arm/ptw.c
21
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
27
@@ -XXX,XX +XXX,XX @@ static uint8_t combined_attrs_nofwb(uint64_t hcr,
22
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
28
{
23
pic[MP_TIMER4_IRQ], NULL);
29
uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs;
24
30
25
- if (serial_hd(0)) {
31
- s2_mair_attrs = convert_stage2_attrs(hcr, s2.attrs);
26
- serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
32
+ if (s2.is_s2_format) {
27
- 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
33
+ s2_mair_attrs = convert_stage2_attrs(hcr, s2.attrs);
28
- }
34
+ } else {
29
- if (serial_hd(1)) {
35
+ s2_mair_attrs = s2.attrs;
30
- serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
36
+ }
31
- 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
37
32
- }
38
s1lo = extract32(s1.attrs, 0, 4);
33
+ serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
39
s2lo = extract32(s2_mair_attrs, 0, 4);
34
+ 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
40
@@ -XXX,XX +XXX,XX @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr)
35
+ serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
41
*/
36
+ 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
42
static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2)
37
43
{
38
/* Register flash */
44
+ assert(s2.is_s2_format && !s1.is_s2_format);
39
dinfo = drive_get(IF_PFLASH, 0, 0);
45
+
46
switch (s2.attrs) {
47
case 7:
48
/* Use stage 1 attributes */
49
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
50
ARMCacheAttrs ret;
51
bool tagged = false;
52
53
- assert(s2.is_s2_format && !s1.is_s2_format);
54
+ assert(!s1.is_s2_format);
55
ret.is_s2_format = false;
56
57
if (s1.attrs == 0xf0) {
40
--
58
--
41
2.20.1
59
2.25.1
42
60
43
61
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
2
3
None of the sve helpers use TCGMemOpIdx any longer, so we can
3
ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even
4
stop passing it.
4
tough they don't have the TTBCR register.
5
See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R
6
AArch32 architecture profile Version:A.c section C1.2.
5
7
8
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20221206102504.165775-5-tobias.roehmel@rwth-aachen.de
8
Message-id: 20200508154359.7494-20-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
target/arm/internals.h | 5 -----
13
target/arm/internals.h | 4 ++++
12
target/arm/sve_helper.c | 14 +++++++-------
14
target/arm/debug_helper.c | 3 +++
13
target/arm/translate-sve.c | 17 +++--------------
15
target/arm/tlb_helper.c | 4 ++++
14
3 files changed, 10 insertions(+), 26 deletions(-)
16
3 files changed, 11 insertions(+)
15
17
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/internals.h
20
--- a/target/arm/internals.h
19
+++ b/target/arm/internals.h
21
+++ b/target/arm/internals.h
20
@@ -XXX,XX +XXX,XX @@ static inline int arm_num_ctx_cmps(ARMCPU *cpu)
22
@@ -XXX,XX +XXX,XX @@ unsigned int arm_pamax(ARMCPU *cpu);
23
static inline bool extended_addresses_enabled(CPUARMState *env)
24
{
25
uint64_t tcr = env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
26
+ if (arm_feature(env, ARM_FEATURE_PMSA) &&
27
+ arm_feature(env, ARM_FEATURE_V8)) {
28
+ return true;
29
+ }
30
return arm_el_is_aa64(env, 1) ||
31
(arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE));
32
}
33
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/debug_helper.c
36
+++ b/target/arm/debug_helper.c
37
@@ -XXX,XX +XXX,XX @@ static uint32_t arm_debug_exception_fsr(CPUARMState *env)
38
39
if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
40
using_lpae = true;
41
+ } else if (arm_feature(env, ARM_FEATURE_PMSA) &&
42
+ arm_feature(env, ARM_FEATURE_V8)) {
43
+ using_lpae = true;
44
} else {
45
if (arm_feature(env, ARM_FEATURE_LPAE) &&
46
(env->cp15.tcr_el[target_el] & TTBCR_EAE)) {
47
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/tlb_helper.c
50
+++ b/target/arm/tlb_helper.c
51
@@ -XXX,XX +XXX,XX @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
52
if (el == 2 || arm_el_is_aa64(env, el)) {
53
return true;
21
}
54
}
22
}
55
+ if (arm_feature(env, ARM_FEATURE_PMSA) &&
23
56
+ arm_feature(env, ARM_FEATURE_V8)) {
24
-/* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3.
57
+ return true;
25
- * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits.
58
+ }
26
- */
59
if (arm_feature(env, ARM_FEATURE_LPAE)
27
-#define MEMOPIDX_SHIFT 8
60
&& (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
28
-
61
return true;
29
/**
30
* v7m_using_psp: Return true if using process stack pointer
31
* Return true if the CPU is currently using the process stack
32
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/sve_helper.c
35
+++ b/target/arm/sve_helper.c
36
@@ -XXX,XX +XXX,XX @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
37
sve_ldst1_host_fn *host_fn,
38
sve_ldst1_tlb_fn *tlb_fn)
39
{
40
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
41
+ const unsigned rd = simd_data(desc);
42
const intptr_t reg_max = simd_oprsz(desc);
43
intptr_t reg_off, reg_last, mem_off;
44
SVEContLdSt info;
45
@@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
46
sve_ldst1_host_fn *host_fn,
47
sve_ldst1_tlb_fn *tlb_fn)
48
{
49
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
50
+ const unsigned rd = simd_data(desc);
51
void *vd = &env->vfp.zregs[rd];
52
const intptr_t reg_max = simd_oprsz(desc);
53
intptr_t reg_off, mem_off, reg_last;
54
@@ -XXX,XX +XXX,XX @@ void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, uint32_t desc,
55
sve_ldst1_host_fn *host_fn,
56
sve_ldst1_tlb_fn *tlb_fn)
57
{
58
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
59
+ const unsigned rd = simd_data(desc);
60
const intptr_t reg_max = simd_oprsz(desc);
61
intptr_t reg_off, reg_last, mem_off;
62
SVEContLdSt info;
63
@@ -XXX,XX +XXX,XX @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
64
sve_ldst1_host_fn *host_fn,
65
sve_ldst1_tlb_fn *tlb_fn)
66
{
67
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
68
const int mmu_idx = cpu_mmu_index(env, false);
69
const intptr_t reg_max = simd_oprsz(desc);
70
+ const int scale = simd_data(desc);
71
ARMVectorReg scratch;
72
intptr_t reg_off;
73
SVEHostPage info, info2;
74
@@ -XXX,XX +XXX,XX @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
75
sve_ldst1_tlb_fn *tlb_fn)
76
{
77
const int mmu_idx = cpu_mmu_index(env, false);
78
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
79
+ const intptr_t reg_max = simd_oprsz(desc);
80
+ const int scale = simd_data(desc);
81
const int esize = 1 << esz;
82
const int msize = 1 << msz;
83
- const intptr_t reg_max = simd_oprsz(desc);
84
intptr_t reg_off;
85
SVEHostPage info;
86
target_ulong addr, in_page;
87
@@ -XXX,XX +XXX,XX @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
88
sve_ldst1_host_fn *host_fn,
89
sve_ldst1_tlb_fn *tlb_fn)
90
{
91
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
92
const int mmu_idx = cpu_mmu_index(env, false);
93
const intptr_t reg_max = simd_oprsz(desc);
94
+ const int scale = simd_data(desc);
95
void *host[ARM_MAX_VQ * 4];
96
intptr_t reg_off, i;
97
SVEHostPage info, info2;
98
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/translate-sve.c
101
+++ b/target/arm/translate-sve.c
102
@@ -XXX,XX +XXX,XX @@ static const uint8_t dtype_esz[16] = {
103
3, 2, 1, 3
104
};
105
106
-static TCGMemOpIdx sve_memopidx(DisasContext *s, int dtype)
107
-{
108
- return make_memop_idx(s->be_data | dtype_mop[dtype], get_mem_index(s));
109
-}
110
-
111
static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
112
int dtype, gen_helper_gvec_mem *fn)
113
{
114
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
115
* registers as pointers, so encode the regno into the data field.
116
* For consistency, do this even for LD1.
117
*/
118
- desc = sve_memopidx(s, dtype);
119
- desc |= zt << MEMOPIDX_SHIFT;
120
- desc = simd_desc(vsz, vsz, desc);
121
+ desc = simd_desc(vsz, vsz, zt);
122
t_desc = tcg_const_i32(desc);
123
t_pg = tcg_temp_new_ptr();
124
125
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int msz)
126
int desc, poff;
127
128
/* Load the first quadword using the normal predicated load helpers. */
129
- desc = sve_memopidx(s, msz_dtype(s, msz));
130
- desc |= zt << MEMOPIDX_SHIFT;
131
- desc = simd_desc(16, 16, desc);
132
+ desc = simd_desc(16, 16, zt);
133
t_desc = tcg_const_i32(desc);
134
135
poff = pred_full_reg_offset(s, pg);
136
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
137
TCGv_i32 t_desc;
138
int desc;
139
140
- desc = sve_memopidx(s, msz_dtype(s, msz));
141
- desc |= scale << MEMOPIDX_SHIFT;
142
- desc = simd_desc(vsz, vsz, desc);
143
+ desc = simd_desc(vsz, vsz, scale);
144
t_desc = tcg_const_i32(desc);
145
146
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
147
--
62
--
148
2.20.1
63
2.25.1
149
64
150
65
diff view generated by jsdifflib
1
From: Thomas Huth <thuth@redhat.com>
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
2
3
Move the common set_feature() and unset_feature() functions
3
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
4
from cpu.c and cpu64.c to cpu.h.
4
Message-id: 20221206102504.165775-6-tobias.roehmel@rwth-aachen.de
5
6
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Thomas Huth <thuth@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20200504172448.9402-3-philmd@redhat.com
12
Message-ID: <20190921150420.30743-2-thuth@redhat.com>
13
[PMD: Split Thomas's patch in two: set_feature, cpu_register]
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
6
---
17
target/arm/cpu.h | 10 ++++++++++
7
target/arm/cpu.h | 6 +
18
target/arm/cpu.c | 10 ----------
8
target/arm/cpu.c | 28 +++-
19
target/arm/cpu64.c | 10 ----------
9
target/arm/helper.c | 302 +++++++++++++++++++++++++++++++++++++++++++
20
3 files changed, 10 insertions(+), 20 deletions(-)
10
target/arm/machine.c | 28 ++++
11
4 files changed, 360 insertions(+), 4 deletions(-)
21
12
22
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
23
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/cpu.h
15
--- a/target/arm/cpu.h
25
+++ b/target/arm/cpu.h
16
+++ b/target/arm/cpu.h
26
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
17
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
27
void *gicv3state;
18
};
28
} CPUARMState;
19
uint64_t sctlr_el[4];
29
20
};
30
+static inline void set_feature(CPUARMState *env, int feature)
21
+ uint64_t vsctlr; /* Virtualization System control register. */
31
+{
22
uint64_t cpacr_el1; /* Architectural feature access control register */
32
+ env->features |= 1ULL << feature;
23
uint64_t cptr_el[4]; /* ARMv8 feature trap registers */
33
+}
24
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
34
+
25
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
35
+static inline void unset_feature(CPUARMState *env, int feature)
26
*/
36
+{
27
uint32_t *rbar[M_REG_NUM_BANKS];
37
+ env->features &= ~(1ULL << feature);
28
uint32_t *rlar[M_REG_NUM_BANKS];
38
+}
29
+ uint32_t *hprbar;
39
+
30
+ uint32_t *hprlar;
40
/**
31
uint32_t mair0[M_REG_NUM_BANKS];
41
* ARMELChangeHookFn:
32
uint32_t mair1[M_REG_NUM_BANKS];
42
* type of a function which can be registered via arm_register_el_change_hook()
33
+ uint32_t hprselr;
34
} pmsav8;
35
36
/* v8M SAU */
37
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
38
bool has_mpu;
39
/* PMSAv7 MPU number of supported regions */
40
uint32_t pmsav7_dregion;
41
+ /* PMSAv8 MPU number of supported hyp regions */
42
+ uint32_t pmsav8r_hdregion;
43
/* v8M SAU number of supported regions */
44
uint32_t sau_sregion;
45
43
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
46
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
44
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/cpu.c
48
--- a/target/arm/cpu.c
46
+++ b/target/arm/cpu.c
49
+++ b/target/arm/cpu.c
47
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
50
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
48
51
sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
49
#endif
52
}
50
53
}
51
-static inline void set_feature(CPUARMState *env, int feature)
54
+
52
-{
55
+ if (cpu->pmsav8r_hdregion > 0) {
53
- env->features |= 1ULL << feature;
56
+ memset(env->pmsav8.hprbar, 0,
54
-}
57
+ sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion);
55
-
58
+ memset(env->pmsav8.hprlar, 0,
56
-static inline void unset_feature(CPUARMState *env, int feature)
59
+ sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion);
57
-{
60
+ }
58
- env->features &= ~(1ULL << feature);
61
+
59
-}
62
env->pmsav7.rnr[M_REG_NS] = 0;
60
-
63
env->pmsav7.rnr[M_REG_S] = 0;
61
static int
64
env->pmsav8.mair0[M_REG_NS] = 0;
62
print_insn_thumb1(bfd_vma pc, disassemble_info *info)
65
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
63
{
66
/* MPU can be configured out of a PMSA CPU either by setting has-mpu
64
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
67
* to false or by setting pmsav7-dregion to 0.
68
*/
69
- if (!cpu->has_mpu) {
70
- cpu->pmsav7_dregion = 0;
71
- }
72
- if (cpu->pmsav7_dregion == 0) {
73
+ if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) {
74
cpu->has_mpu = false;
75
+ cpu->pmsav7_dregion = 0;
76
+ cpu->pmsav8r_hdregion = 0;
77
}
78
79
if (arm_feature(env, ARM_FEATURE_PMSA) &&
80
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
81
env->pmsav7.dracr = g_new0(uint32_t, nr);
82
}
83
}
84
+
85
+ if (cpu->pmsav8r_hdregion > 0xff) {
86
+ error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32,
87
+ cpu->pmsav8r_hdregion);
88
+ return;
89
+ }
90
+
91
+ if (cpu->pmsav8r_hdregion) {
92
+ env->pmsav8.hprbar = g_new0(uint32_t,
93
+ cpu->pmsav8r_hdregion);
94
+ env->pmsav8.hprlar = g_new0(uint32_t,
95
+ cpu->pmsav8r_hdregion);
96
+ }
97
}
98
99
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
100
diff --git a/target/arm/helper.c b/target/arm/helper.c
65
index XXXXXXX..XXXXXXX 100644
101
index XXXXXXX..XXXXXXX 100644
66
--- a/target/arm/cpu64.c
102
--- a/target/arm/helper.c
67
+++ b/target/arm/cpu64.c
103
+++ b/target/arm/helper.c
68
@@ -XXX,XX +XXX,XX @@
104
@@ -XXX,XX +XXX,XX @@ static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
69
#include "kvm_arm.h"
105
raw_write(env, ri, value);
70
#include "qapi/visitor.h"
106
}
71
107
72
-static inline void set_feature(CPUARMState *env, int feature)
108
+static void prbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
73
-{
109
+ uint64_t value)
74
- env->features |= 1ULL << feature;
110
+{
75
-}
111
+ ARMCPU *cpu = env_archcpu(env);
76
-
112
+
77
-static inline void unset_feature(CPUARMState *env, int feature)
113
+ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
78
-{
114
+ env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value;
79
- env->features &= ~(1ULL << feature);
115
+}
80
-}
116
+
81
-
117
+static uint64_t prbar_read(CPUARMState *env, const ARMCPRegInfo *ri)
82
#ifndef CONFIG_USER_ONLY
118
+{
83
static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
119
+ return env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]];
84
{
120
+}
121
+
122
+static void prlar_write(CPUARMState *env, const ARMCPRegInfo *ri,
123
+ uint64_t value)
124
+{
125
+ ARMCPU *cpu = env_archcpu(env);
126
+
127
+ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
128
+ env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value;
129
+}
130
+
131
+static uint64_t prlar_read(CPUARMState *env, const ARMCPRegInfo *ri)
132
+{
133
+ return env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]];
134
+}
135
+
136
+static void prselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
137
+ uint64_t value)
138
+{
139
+ ARMCPU *cpu = env_archcpu(env);
140
+
141
+ /*
142
+ * Ignore writes that would select not implemented region.
143
+ * This is architecturally UNPREDICTABLE.
144
+ */
145
+ if (value >= cpu->pmsav7_dregion) {
146
+ return;
147
+ }
148
+
149
+ env->pmsav7.rnr[M_REG_NS] = value;
150
+}
151
+
152
+static void hprbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
153
+ uint64_t value)
154
+{
155
+ ARMCPU *cpu = env_archcpu(env);
156
+
157
+ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
158
+ env->pmsav8.hprbar[env->pmsav8.hprselr] = value;
159
+}
160
+
161
+static uint64_t hprbar_read(CPUARMState *env, const ARMCPRegInfo *ri)
162
+{
163
+ return env->pmsav8.hprbar[env->pmsav8.hprselr];
164
+}
165
+
166
+static void hprlar_write(CPUARMState *env, const ARMCPRegInfo *ri,
167
+ uint64_t value)
168
+{
169
+ ARMCPU *cpu = env_archcpu(env);
170
+
171
+ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
172
+ env->pmsav8.hprlar[env->pmsav8.hprselr] = value;
173
+}
174
+
175
+static uint64_t hprlar_read(CPUARMState *env, const ARMCPRegInfo *ri)
176
+{
177
+ return env->pmsav8.hprlar[env->pmsav8.hprselr];
178
+}
179
+
180
+static void hprenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
181
+ uint64_t value)
182
+{
183
+ uint32_t n;
184
+ uint32_t bit;
185
+ ARMCPU *cpu = env_archcpu(env);
186
+
187
+ /* Ignore writes to unimplemented regions */
188
+ int rmax = MIN(cpu->pmsav8r_hdregion, 32);
189
+ value &= MAKE_64BIT_MASK(0, rmax);
190
+
191
+ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
192
+
193
+ /* Register alias is only valid for first 32 indexes */
194
+ for (n = 0; n < rmax; ++n) {
195
+ bit = extract32(value, n, 1);
196
+ env->pmsav8.hprlar[n] = deposit32(
197
+ env->pmsav8.hprlar[n], 0, 1, bit);
198
+ }
199
+}
200
+
201
+static uint64_t hprenr_read(CPUARMState *env, const ARMCPRegInfo *ri)
202
+{
203
+ uint32_t n;
204
+ uint32_t result = 0x0;
205
+ ARMCPU *cpu = env_archcpu(env);
206
+
207
+ /* Register alias is only valid for first 32 indexes */
208
+ for (n = 0; n < MIN(cpu->pmsav8r_hdregion, 32); ++n) {
209
+ if (env->pmsav8.hprlar[n] & 0x1) {
210
+ result |= (0x1 << n);
211
+ }
212
+ }
213
+ return result;
214
+}
215
+
216
+static void hprselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
217
+ uint64_t value)
218
+{
219
+ ARMCPU *cpu = env_archcpu(env);
220
+
221
+ /*
222
+ * Ignore writes that would select not implemented region.
223
+ * This is architecturally UNPREDICTABLE.
224
+ */
225
+ if (value >= cpu->pmsav8r_hdregion) {
226
+ return;
227
+ }
228
+
229
+ env->pmsav8.hprselr = value;
230
+}
231
+
232
+static void pmsav8r_regn_write(CPUARMState *env, const ARMCPRegInfo *ri,
233
+ uint64_t value)
234
+{
235
+ ARMCPU *cpu = env_archcpu(env);
236
+ uint8_t index = (extract32(ri->opc0, 0, 1) << 4) |
237
+ (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1);
238
+
239
+ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
240
+
241
+ if (ri->opc1 & 4) {
242
+ if (index >= cpu->pmsav8r_hdregion) {
243
+ return;
244
+ }
245
+ if (ri->opc2 & 0x1) {
246
+ env->pmsav8.hprlar[index] = value;
247
+ } else {
248
+ env->pmsav8.hprbar[index] = value;
249
+ }
250
+ } else {
251
+ if (index >= cpu->pmsav7_dregion) {
252
+ return;
253
+ }
254
+ if (ri->opc2 & 0x1) {
255
+ env->pmsav8.rlar[M_REG_NS][index] = value;
256
+ } else {
257
+ env->pmsav8.rbar[M_REG_NS][index] = value;
258
+ }
259
+ }
260
+}
261
+
262
+static uint64_t pmsav8r_regn_read(CPUARMState *env, const ARMCPRegInfo *ri)
263
+{
264
+ ARMCPU *cpu = env_archcpu(env);
265
+ uint8_t index = (extract32(ri->opc0, 0, 1) << 4) |
266
+ (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1);
267
+
268
+ if (ri->opc1 & 4) {
269
+ if (index >= cpu->pmsav8r_hdregion) {
270
+ return 0x0;
271
+ }
272
+ if (ri->opc2 & 0x1) {
273
+ return env->pmsav8.hprlar[index];
274
+ } else {
275
+ return env->pmsav8.hprbar[index];
276
+ }
277
+ } else {
278
+ if (index >= cpu->pmsav7_dregion) {
279
+ return 0x0;
280
+ }
281
+ if (ri->opc2 & 0x1) {
282
+ return env->pmsav8.rlar[M_REG_NS][index];
283
+ } else {
284
+ return env->pmsav8.rbar[M_REG_NS][index];
285
+ }
286
+ }
287
+}
288
+
289
+static const ARMCPRegInfo pmsav8r_cp_reginfo[] = {
290
+ { .name = "PRBAR",
291
+ .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 0,
292
+ .access = PL1_RW, .type = ARM_CP_NO_RAW,
293
+ .accessfn = access_tvm_trvm,
294
+ .readfn = prbar_read, .writefn = prbar_write },
295
+ { .name = "PRLAR",
296
+ .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 1,
297
+ .access = PL1_RW, .type = ARM_CP_NO_RAW,
298
+ .accessfn = access_tvm_trvm,
299
+ .readfn = prlar_read, .writefn = prlar_write },
300
+ { .name = "PRSELR", .resetvalue = 0,
301
+ .cp = 15, .opc1 = 0, .crn = 6, .crm = 2, .opc2 = 1,
302
+ .access = PL1_RW, .accessfn = access_tvm_trvm,
303
+ .writefn = prselr_write,
304
+ .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]) },
305
+ { .name = "HPRBAR", .resetvalue = 0,
306
+ .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 0,
307
+ .access = PL2_RW, .type = ARM_CP_NO_RAW,
308
+ .readfn = hprbar_read, .writefn = hprbar_write },
309
+ { .name = "HPRLAR",
310
+ .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 1,
311
+ .access = PL2_RW, .type = ARM_CP_NO_RAW,
312
+ .readfn = hprlar_read, .writefn = hprlar_write },
313
+ { .name = "HPRSELR", .resetvalue = 0,
314
+ .cp = 15, .opc1 = 4, .crn = 6, .crm = 2, .opc2 = 1,
315
+ .access = PL2_RW,
316
+ .writefn = hprselr_write,
317
+ .fieldoffset = offsetof(CPUARMState, pmsav8.hprselr) },
318
+ { .name = "HPRENR",
319
+ .cp = 15, .opc1 = 4, .crn = 6, .crm = 1, .opc2 = 1,
320
+ .access = PL2_RW, .type = ARM_CP_NO_RAW,
321
+ .readfn = hprenr_read, .writefn = hprenr_write },
322
+};
323
+
324
static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
325
/* Reset for all these registers is handled in arm_cpu_reset(),
326
* because the PMSAv7 is also used by M-profile CPUs, which do
327
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
328
.access = PL1_R, .type = ARM_CP_CONST,
329
.resetvalue = cpu->pmsav7_dregion << 8
330
};
331
+ /* HMPUIR is specific to PMSA V8 */
332
+ ARMCPRegInfo id_hmpuir_reginfo = {
333
+ .name = "HMPUIR",
334
+ .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 4,
335
+ .access = PL2_R, .type = ARM_CP_CONST,
336
+ .resetvalue = cpu->pmsav8r_hdregion
337
+ };
338
static const ARMCPRegInfo crn0_wi_reginfo = {
339
.name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
340
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
341
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
342
define_arm_cp_regs(cpu, id_cp_reginfo);
343
if (!arm_feature(env, ARM_FEATURE_PMSA)) {
344
define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
345
+ } else if (arm_feature(env, ARM_FEATURE_PMSA) &&
346
+ arm_feature(env, ARM_FEATURE_V8)) {
347
+ uint32_t i = 0;
348
+ char *tmp_string;
349
+
350
+ define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
351
+ define_one_arm_cp_reg(cpu, &id_hmpuir_reginfo);
352
+ define_arm_cp_regs(cpu, pmsav8r_cp_reginfo);
353
+
354
+ /* Register alias is only valid for first 32 indexes */
355
+ for (i = 0; i < MIN(cpu->pmsav7_dregion, 32); ++i) {
356
+ uint8_t crm = 0b1000 | extract32(i, 1, 3);
357
+ uint8_t opc1 = extract32(i, 4, 1);
358
+ uint8_t opc2 = extract32(i, 0, 1) << 2;
359
+
360
+ tmp_string = g_strdup_printf("PRBAR%u", i);
361
+ ARMCPRegInfo tmp_prbarn_reginfo = {
362
+ .name = tmp_string, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW,
363
+ .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
364
+ .access = PL1_RW, .resetvalue = 0,
365
+ .accessfn = access_tvm_trvm,
366
+ .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
367
+ };
368
+ define_one_arm_cp_reg(cpu, &tmp_prbarn_reginfo);
369
+ g_free(tmp_string);
370
+
371
+ opc2 = extract32(i, 0, 1) << 2 | 0x1;
372
+ tmp_string = g_strdup_printf("PRLAR%u", i);
373
+ ARMCPRegInfo tmp_prlarn_reginfo = {
374
+ .name = tmp_string, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW,
375
+ .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
376
+ .access = PL1_RW, .resetvalue = 0,
377
+ .accessfn = access_tvm_trvm,
378
+ .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
379
+ };
380
+ define_one_arm_cp_reg(cpu, &tmp_prlarn_reginfo);
381
+ g_free(tmp_string);
382
+ }
383
+
384
+ /* Register alias is only valid for first 32 indexes */
385
+ for (i = 0; i < MIN(cpu->pmsav8r_hdregion, 32); ++i) {
386
+ uint8_t crm = 0b1000 | extract32(i, 1, 3);
387
+ uint8_t opc1 = 0b100 | extract32(i, 4, 1);
388
+ uint8_t opc2 = extract32(i, 0, 1) << 2;
389
+
390
+ tmp_string = g_strdup_printf("HPRBAR%u", i);
391
+ ARMCPRegInfo tmp_hprbarn_reginfo = {
392
+ .name = tmp_string,
393
+ .type = ARM_CP_NO_RAW,
394
+ .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
395
+ .access = PL2_RW, .resetvalue = 0,
396
+ .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
397
+ };
398
+ define_one_arm_cp_reg(cpu, &tmp_hprbarn_reginfo);
399
+ g_free(tmp_string);
400
+
401
+ opc2 = extract32(i, 0, 1) << 2 | 0x1;
402
+ tmp_string = g_strdup_printf("HPRLAR%u", i);
403
+ ARMCPRegInfo tmp_hprlarn_reginfo = {
404
+ .name = tmp_string,
405
+ .type = ARM_CP_NO_RAW,
406
+ .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
407
+ .access = PL2_RW, .resetvalue = 0,
408
+ .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
409
+ };
410
+ define_one_arm_cp_reg(cpu, &tmp_hprlarn_reginfo);
411
+ g_free(tmp_string);
412
+ }
413
} else if (arm_feature(env, ARM_FEATURE_V7)) {
414
define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
415
}
416
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
417
sctlr.type |= ARM_CP_SUPPRESS_TB_END;
418
}
419
define_one_arm_cp_reg(cpu, &sctlr);
420
+
421
+ if (arm_feature(env, ARM_FEATURE_PMSA) &&
422
+ arm_feature(env, ARM_FEATURE_V8)) {
423
+ ARMCPRegInfo vsctlr = {
424
+ .name = "VSCTLR", .state = ARM_CP_STATE_AA32,
425
+ .cp = 15, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
426
+ .access = PL2_RW, .resetvalue = 0x0,
427
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.vsctlr),
428
+ };
429
+ define_one_arm_cp_reg(cpu, &vsctlr);
430
+ }
431
}
432
433
if (cpu_isar_feature(aa64_lor, cpu)) {
434
diff --git a/target/arm/machine.c b/target/arm/machine.c
435
index XXXXXXX..XXXXXXX 100644
436
--- a/target/arm/machine.c
437
+++ b/target/arm/machine.c
438
@@ -XXX,XX +XXX,XX @@ static bool pmsav8_needed(void *opaque)
439
arm_feature(env, ARM_FEATURE_V8);
440
}
441
442
+static bool pmsav8r_needed(void *opaque)
443
+{
444
+ ARMCPU *cpu = opaque;
445
+ CPUARMState *env = &cpu->env;
446
+
447
+ return arm_feature(env, ARM_FEATURE_PMSA) &&
448
+ arm_feature(env, ARM_FEATURE_V8) &&
449
+ !arm_feature(env, ARM_FEATURE_M);
450
+}
451
+
452
+static const VMStateDescription vmstate_pmsav8r = {
453
+ .name = "cpu/pmsav8/pmsav8r",
454
+ .version_id = 1,
455
+ .minimum_version_id = 1,
456
+ .needed = pmsav8r_needed,
457
+ .fields = (VMStateField[]) {
458
+ VMSTATE_VARRAY_UINT32(env.pmsav8.hprbar, ARMCPU,
459
+ pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t),
460
+ VMSTATE_VARRAY_UINT32(env.pmsav8.hprlar, ARMCPU,
461
+ pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t),
462
+ VMSTATE_END_OF_LIST()
463
+ },
464
+};
465
+
466
static const VMStateDescription vmstate_pmsav8 = {
467
.name = "cpu/pmsav8",
468
.version_id = 1,
469
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav8 = {
470
VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU),
471
VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU),
472
VMSTATE_END_OF_LIST()
473
+ },
474
+ .subsections = (const VMStateDescription * []) {
475
+ &vmstate_pmsav8r,
476
+ NULL
477
}
478
};
479
85
--
480
--
86
2.20.1
481
2.25.1
87
482
88
483
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
2
3
We currently have target-endian versions of these operations,
3
Add PMSAv8r translation.
4
but no easy way to force a specific endianness. This can be
4
5
helpful if the target has endian-specific operations, or a mode
5
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
6
that swaps endianness.
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20221206102504.165775-7-tobias.roehmel@rwth-aachen.de
10
Message-id: 20200508154359.7494-7-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
9
---
13
docs/devel/loads-stores.rst | 39 +++--
10
target/arm/ptw.c | 126 ++++++++++++++++++++++++++++++++++++++---------
14
include/exec/cpu_ldst.h | 283 +++++++++++++++++++++++++++---------
11
1 file changed, 104 insertions(+), 22 deletions(-)
15
accel/tcg/cputlb.c | 236 ++++++++++++++++++++++--------
12
16
accel/tcg/user-exec.c | 211 ++++++++++++++++++++++-----
13
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
17
4 files changed, 587 insertions(+), 182 deletions(-)
18
19
diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst
20
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
21
--- a/docs/devel/loads-stores.rst
15
--- a/target/arm/ptw.c
22
+++ b/docs/devel/loads-stores.rst
16
+++ b/target/arm/ptw.c
23
@@ -XXX,XX +XXX,XX @@ function, which is a return address into the generated code.
17
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
24
18
25
Function names follow the pattern:
19
if (arm_feature(env, ARM_FEATURE_M)) {
26
20
return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
27
-load: ``cpu_ld{sign}{size}_mmuidx_ra(env, ptr, mmuidx, retaddr)``
21
- } else {
28
+load: ``cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmuidx, retaddr)``
22
- return regime_sctlr(env, mmu_idx) & SCTLR_BR;
29
23
}
30
-store: ``cpu_st{size}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
24
+
31
+store: ``cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
25
+ if (mmu_idx == ARMMMUIdx_Stage2) {
32
26
+ return false;
33
``sign``
27
+ }
34
- (empty) : for 32 or 64 bit sizes
28
+
35
@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
29
+ return regime_sctlr(env, mmu_idx) & SCTLR_BR;
36
- ``l`` : 32 bits
37
- ``q`` : 64 bits
38
39
+``end``
40
+ - (empty) : for target endian, or 8 bit sizes
41
+ - ``_be`` : big endian
42
+ - ``_le`` : little endian
43
+
44
Regexes for git grep:
45
- - ``\<cpu_ld[us]\?[bwlq]_mmuidx_ra\>``
46
- - ``\<cpu_st[bwlq]_mmuidx_ra\>``
47
+ - ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_mmuidx_ra\>``
48
+ - ``\<cpu_st[bwlq](_[bl]e)\?_mmuidx_ra\>``
49
50
``cpu_{ld,st}*_data_ra``
51
~~~~~~~~~~~~~~~~~~~~~~~~
52
@@ -XXX,XX +XXX,XX @@ be performed with a context other than the default.
53
54
Function names follow the pattern:
55
56
-load: ``cpu_ld{sign}{size}_data_ra(env, ptr, ra)``
57
+load: ``cpu_ld{sign}{size}{end}_data_ra(env, ptr, ra)``
58
59
-store: ``cpu_st{size}_data_ra(env, ptr, val, ra)``
60
+store: ``cpu_st{size}{end}_data_ra(env, ptr, val, ra)``
61
62
``sign``
63
- (empty) : for 32 or 64 bit sizes
64
@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}_data_ra(env, ptr, val, ra)``
65
- ``l`` : 32 bits
66
- ``q`` : 64 bits
67
68
+``end``
69
+ - (empty) : for target endian, or 8 bit sizes
70
+ - ``_be`` : big endian
71
+ - ``_le`` : little endian
72
+
73
Regexes for git grep:
74
- - ``\<cpu_ld[us]\?[bwlq]_data_ra\>``
75
- - ``\<cpu_st[bwlq]_data_ra\>``
76
+ - ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_data_ra\>``
77
+ - ``\<cpu_st[bwlq](_[bl]e)\?_data_ra\>``
78
79
``cpu_{ld,st}*_data``
80
~~~~~~~~~~~~~~~~~~~~~
81
@@ -XXX,XX +XXX,XX @@ the CPU state anyway.
82
83
Function names follow the pattern:
84
85
-load: ``cpu_ld{sign}{size}_data(env, ptr)``
86
+load: ``cpu_ld{sign}{size}{end}_data(env, ptr)``
87
88
-store: ``cpu_st{size}_data(env, ptr, val)``
89
+store: ``cpu_st{size}{end}_data(env, ptr, val)``
90
91
``sign``
92
- (empty) : for 32 or 64 bit sizes
93
@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}_data(env, ptr, val)``
94
- ``l`` : 32 bits
95
- ``q`` : 64 bits
96
97
+``end``
98
+ - (empty) : for target endian, or 8 bit sizes
99
+ - ``_be`` : big endian
100
+ - ``_le`` : little endian
101
+
102
Regexes for git grep
103
- - ``\<cpu_ld[us]\?[bwlq]_data\>``
104
- - ``\<cpu_st[bwlq]_data\+\>``
105
+ - ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_data\>``
106
+ - ``\<cpu_st[bwlq](_[bl]e)\?_data\+\>``
107
108
``cpu_ld*_code``
109
~~~~~~~~~~~~~~~~
110
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
111
index XXXXXXX..XXXXXXX 100644
112
--- a/include/exec/cpu_ldst.h
113
+++ b/include/exec/cpu_ldst.h
114
@@ -XXX,XX +XXX,XX @@
115
*
116
* The syntax for the accessors is:
117
*
118
- * load: cpu_ld{sign}{size}_{mmusuffix}(env, ptr)
119
- * cpu_ld{sign}{size}_{mmusuffix}_ra(env, ptr, retaddr)
120
- * cpu_ld{sign}{size}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
121
+ * load: cpu_ld{sign}{size}{end}_{mmusuffix}(env, ptr)
122
+ * cpu_ld{sign}{size}{end}_{mmusuffix}_ra(env, ptr, retaddr)
123
+ * cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
124
*
125
- * store: cpu_st{size}_{mmusuffix}(env, ptr, val)
126
- * cpu_st{size}_{mmusuffix}_ra(env, ptr, val, retaddr)
127
- * cpu_st{size}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
128
+ * store: cpu_st{size}{end}_{mmusuffix}(env, ptr, val)
129
+ * cpu_st{size}{end}_{mmusuffix}_ra(env, ptr, val, retaddr)
130
+ * cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
131
*
132
* sign is:
133
* (empty): for 32 and 64 bit sizes
134
@@ -XXX,XX +XXX,XX @@
135
* l: 32 bits
136
* q: 64 bits
137
*
138
+ * end is:
139
+ * (empty): for target native endian, or for 8 bit access
140
+ * _be: for forced big endian
141
+ * _le: for forced little endian
142
+ *
143
* mmusuffix is one of the generic suffixes "data" or "code", or "mmuidx".
144
* The "mmuidx" suffix carries an extra mmu_idx argument that specifies
145
* the index to use; the "data" and "code" suffixes take the index from
146
@@ -XXX,XX +XXX,XX @@ typedef target_ulong abi_ptr;
147
#endif
148
149
uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
150
-uint32_t cpu_lduw_data(CPUArchState *env, abi_ptr ptr);
151
-uint32_t cpu_ldl_data(CPUArchState *env, abi_ptr ptr);
152
-uint64_t cpu_ldq_data(CPUArchState *env, abi_ptr ptr);
153
int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr);
154
-int cpu_ldsw_data(CPUArchState *env, abi_ptr ptr);
155
156
-uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
157
-uint32_t cpu_lduw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
158
-uint32_t cpu_ldl_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
159
-uint64_t cpu_ldq_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
160
-int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
161
-int cpu_ldsw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
162
+uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr);
163
+int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr);
164
+uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr);
165
+uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr);
166
+
167
+uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr);
168
+int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr);
169
+uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr);
170
+uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr);
171
+
172
+uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
173
+int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
174
+
175
+uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
176
+int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
177
+uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
178
+uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
179
+
180
+uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
181
+int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
182
+uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
183
+uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
184
185
void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
186
-void cpu_stw_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
187
-void cpu_stl_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
188
-void cpu_stq_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
189
+
190
+void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
191
+void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
192
+void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
193
+
194
+void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
195
+void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
196
+void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
197
198
void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
199
- uint32_t val, uintptr_t retaddr);
200
-void cpu_stw_data_ra(CPUArchState *env, abi_ptr ptr,
201
- uint32_t val, uintptr_t retaddr);
202
-void cpu_stl_data_ra(CPUArchState *env, abi_ptr ptr,
203
- uint32_t val, uintptr_t retaddr);
204
-void cpu_stq_data_ra(CPUArchState *env, abi_ptr ptr,
205
- uint64_t val, uintptr_t retaddr);
206
+ uint32_t val, uintptr_t ra);
207
+
208
+void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
209
+ uint32_t val, uintptr_t ra);
210
+void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
211
+ uint32_t val, uintptr_t ra);
212
+void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
213
+ uint64_t val, uintptr_t ra);
214
+
215
+void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
216
+ uint32_t val, uintptr_t ra);
217
+void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
218
+ uint32_t val, uintptr_t ra);
219
+void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
220
+ uint64_t val, uintptr_t ra);
221
222
#if defined(CONFIG_USER_ONLY)
223
224
@@ -XXX,XX +XXX,XX @@ static inline uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
225
return cpu_ldub_data_ra(env, addr, ra);
226
}
30
}
227
31
228
-static inline uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
32
static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
229
- int mmu_idx, uintptr_t ra)
33
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
230
-{
34
return !(result->f.prot & (1 << access_type));
231
- return cpu_lduw_data_ra(env, addr, ra);
232
-}
233
-
234
-static inline uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
235
- int mmu_idx, uintptr_t ra)
236
-{
237
- return cpu_ldl_data_ra(env, addr, ra);
238
-}
239
-
240
-static inline uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
241
- int mmu_idx, uintptr_t ra)
242
-{
243
- return cpu_ldq_data_ra(env, addr, ra);
244
-}
245
-
246
static inline int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
247
int mmu_idx, uintptr_t ra)
248
{
249
return cpu_ldsb_data_ra(env, addr, ra);
250
}
35
}
251
36
252
-static inline int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
37
+static uint32_t *regime_rbar(CPUARMState *env, ARMMMUIdx mmu_idx,
253
- int mmu_idx, uintptr_t ra)
38
+ uint32_t secure)
254
+static inline uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
39
+{
255
+ int mmu_idx, uintptr_t ra)
40
+ if (regime_el(env, mmu_idx) == 2) {
256
{
41
+ return env->pmsav8.hprbar;
257
- return cpu_ldsw_data_ra(env, addr, ra);
42
+ } else {
258
+ return cpu_lduw_be_data_ra(env, addr, ra);
43
+ return env->pmsav8.rbar[secure];
44
+ }
259
+}
45
+}
260
+
46
+
261
+static inline int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
47
+static uint32_t *regime_rlar(CPUARMState *env, ARMMMUIdx mmu_idx,
262
+ int mmu_idx, uintptr_t ra)
48
+ uint32_t secure)
263
+{
49
+{
264
+ return cpu_ldsw_be_data_ra(env, addr, ra);
50
+ if (regime_el(env, mmu_idx) == 2) {
51
+ return env->pmsav8.hprlar;
52
+ } else {
53
+ return env->pmsav8.rlar[secure];
54
+ }
265
+}
55
+}
266
+
56
+
267
+static inline uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
57
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
268
+ int mmu_idx, uintptr_t ra)
58
MMUAccessType access_type, ARMMMUIdx mmu_idx,
269
+{
59
bool secure, GetPhysAddrResult *result,
270
+ return cpu_ldl_be_data_ra(env, addr, ra);
60
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
271
+}
61
bool hit = false;
272
+
62
uint32_t addr_page_base = address & TARGET_PAGE_MASK;
273
+static inline uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
63
uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
274
+ int mmu_idx, uintptr_t ra)
64
+ int region_counter;
275
+{
65
+
276
+ return cpu_ldq_be_data_ra(env, addr, ra);
66
+ if (regime_el(env, mmu_idx) == 2) {
277
+}
67
+ region_counter = cpu->pmsav8r_hdregion;
278
+
68
+ } else {
279
+static inline uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
69
+ region_counter = cpu->pmsav7_dregion;
280
+ int mmu_idx, uintptr_t ra)
70
+ }
281
+{
71
282
+ return cpu_lduw_le_data_ra(env, addr, ra);
72
result->f.lg_page_size = TARGET_PAGE_BITS;
283
+}
73
result->f.phys_addr = address;
284
+
74
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
285
+static inline int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
75
*mregion = -1;
286
+ int mmu_idx, uintptr_t ra)
76
}
287
+{
77
288
+ return cpu_ldsw_le_data_ra(env, addr, ra);
78
+ if (mmu_idx == ARMMMUIdx_Stage2) {
289
+}
79
+ fi->stage2 = true;
290
+
80
+ }
291
+static inline uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
81
+
292
+ int mmu_idx, uintptr_t ra)
82
/*
293
+{
83
* Unlike the ARM ARM pseudocode, we don't need to check whether this
294
+ return cpu_ldl_le_data_ra(env, addr, ra);
84
* was an exception vector read from the vector table (which is always
295
+}
85
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
296
+
86
hit = true;
297
+static inline uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
87
}
298
+ int mmu_idx, uintptr_t ra)
88
299
+{
89
- for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
300
+ return cpu_ldq_le_data_ra(env, addr, ra);
90
+ uint32_t bitmask;
91
+ if (arm_feature(env, ARM_FEATURE_M)) {
92
+ bitmask = 0x1f;
93
+ } else {
94
+ bitmask = 0x3f;
95
+ fi->level = 0;
96
+ }
97
+
98
+ for (n = region_counter - 1; n >= 0; n--) {
99
/* region search */
100
/*
101
- * Note that the base address is bits [31:5] from the register
102
- * with bits [4:0] all zeroes, but the limit address is bits
103
- * [31:5] from the register with bits [4:0] all ones.
104
+ * Note that the base address is bits [31:x] from the register
105
+ * with bits [x-1:0] all zeroes, but the limit address is bits
106
+ * [31:x] from the register with bits [x:0] all ones. Where x is
107
+ * 5 for Cortex-M and 6 for Cortex-R
108
*/
109
- uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f;
110
- uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f;
111
+ uint32_t base = regime_rbar(env, mmu_idx, secure)[n] & ~bitmask;
112
+ uint32_t limit = regime_rlar(env, mmu_idx, secure)[n] | bitmask;
113
114
- if (!(env->pmsav8.rlar[secure][n] & 0x1)) {
115
+ if (!(regime_rlar(env, mmu_idx, secure)[n] & 0x1)) {
116
/* Region disabled */
117
continue;
118
}
119
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
120
* PMSAv7 where highest-numbered-region wins)
121
*/
122
fi->type = ARMFault_Permission;
123
- fi->level = 1;
124
+ if (arm_feature(env, ARM_FEATURE_M)) {
125
+ fi->level = 1;
126
+ }
127
return true;
128
}
129
130
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
131
}
132
133
if (!hit) {
134
- /* background fault */
135
- fi->type = ARMFault_Background;
136
+ if (arm_feature(env, ARM_FEATURE_M)) {
137
+ fi->type = ARMFault_Background;
138
+ } else {
139
+ fi->type = ARMFault_Permission;
140
+ }
141
return true;
142
}
143
144
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
145
/* hit using the background region */
146
get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.prot);
147
} else {
148
- uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
149
- uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
150
+ uint32_t matched_rbar = regime_rbar(env, mmu_idx, secure)[matchregion];
151
+ uint32_t matched_rlar = regime_rlar(env, mmu_idx, secure)[matchregion];
152
+ uint32_t ap = extract32(matched_rbar, 1, 2);
153
+ uint32_t xn = extract32(matched_rbar, 0, 1);
154
bool pxn = false;
155
156
if (arm_feature(env, ARM_FEATURE_V8_1M)) {
157
- pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1);
158
+ pxn = extract32(matched_rlar, 4, 1);
159
}
160
161
if (m_is_system_region(env, address)) {
162
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
163
xn = 1;
164
}
165
166
- result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
167
+ if (regime_el(env, mmu_idx) == 2) {
168
+ result->f.prot = simple_ap_to_rw_prot_is_user(ap,
169
+ mmu_idx != ARMMMUIdx_E2);
170
+ } else {
171
+ result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
172
+ }
173
+
174
+ if (!arm_feature(env, ARM_FEATURE_M)) {
175
+ uint8_t attrindx = extract32(matched_rlar, 1, 3);
176
+ uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
177
+ uint8_t sh = extract32(matched_rlar, 3, 2);
178
+
179
+ if (regime_sctlr(env, mmu_idx) & SCTLR_WXN &&
180
+ result->f.prot & PAGE_WRITE && mmu_idx != ARMMMUIdx_Stage2) {
181
+ xn = 0x1;
182
+ }
183
+
184
+ if ((regime_el(env, mmu_idx) == 1) &&
185
+ regime_sctlr(env, mmu_idx) & SCTLR_UWXN && ap == 0x1) {
186
+ pxn = 0x1;
187
+ }
188
+
189
+ result->cacheattrs.is_s2_format = false;
190
+ result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
191
+ result->cacheattrs.shareability = sh;
192
+ }
193
+
194
if (result->f.prot && !xn && !(pxn && !is_user)) {
195
result->f.prot |= PAGE_EXEC;
196
}
197
- /*
198
- * We don't need to look the attribute up in the MAIR0/MAIR1
199
- * registers because that only tells us about cacheability.
200
- */
201
+
202
if (mregion) {
203
*mregion = matchregion;
204
}
205
}
206
207
fi->type = ARMFault_Permission;
208
- fi->level = 1;
209
+ if (arm_feature(env, ARM_FEATURE_M)) {
210
+ fi->level = 1;
211
+ }
212
return !(result->f.prot & (1 << access_type));
301
}
213
}
302
214
303
static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
215
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
304
@@ -XXX,XX +XXX,XX @@ static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
216
cacheattrs1 = result->cacheattrs;
305
cpu_stb_data_ra(env, addr, val, ra);
217
memset(result, 0, sizeof(*result));
306
}
218
307
219
- ret = get_phys_addr_lpae(env, ptw, ipa, access_type, is_el0, result, fi);
308
-static inline void cpu_stw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
220
+ if (arm_feature(env, ARM_FEATURE_PMSA)) {
309
- uint32_t val, int mmu_idx, uintptr_t ra)
221
+ ret = get_phys_addr_pmsav8(env, ipa, access_type,
310
+static inline void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
222
+ ptw->in_mmu_idx, is_secure, result, fi);
311
+ uint32_t val, int mmu_idx,
223
+ } else {
312
+ uintptr_t ra)
224
+ ret = get_phys_addr_lpae(env, ptw, ipa, access_type,
313
{
225
+ is_el0, result, fi);
314
- cpu_stw_data_ra(env, addr, val, ra);
226
+ }
315
+ cpu_stw_be_data_ra(env, addr, val, ra);
227
fi->s2addr = ipa;
316
}
228
317
229
/* Combine the S1 and S2 perms. */
318
-static inline void cpu_stl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
319
- uint32_t val, int mmu_idx, uintptr_t ra)
320
+static inline void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
321
+ uint32_t val, int mmu_idx,
322
+ uintptr_t ra)
323
{
324
- cpu_stl_data_ra(env, addr, val, ra);
325
+ cpu_stl_be_data_ra(env, addr, val, ra);
326
}
327
328
-static inline void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
329
- uint64_t val, int mmu_idx, uintptr_t ra)
330
+static inline void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
331
+ uint64_t val, int mmu_idx,
332
+ uintptr_t ra)
333
{
334
- cpu_stq_data_ra(env, addr, val, ra);
335
+ cpu_stq_be_data_ra(env, addr, val, ra);
336
+}
337
+
338
+static inline void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
339
+ uint32_t val, int mmu_idx,
340
+ uintptr_t ra)
341
+{
342
+ cpu_stw_le_data_ra(env, addr, val, ra);
343
+}
344
+
345
+static inline void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
346
+ uint32_t val, int mmu_idx,
347
+ uintptr_t ra)
348
+{
349
+ cpu_stl_le_data_ra(env, addr, val, ra);
350
+}
351
+
352
+static inline void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
353
+ uint64_t val, int mmu_idx,
354
+ uintptr_t ra)
355
+{
356
+ cpu_stq_le_data_ra(env, addr, val, ra);
357
}
358
359
#else
360
@@ -XXX,XX +XXX,XX @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
361
362
uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
363
int mmu_idx, uintptr_t ra);
364
-uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
365
- int mmu_idx, uintptr_t ra);
366
-uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
367
- int mmu_idx, uintptr_t ra);
368
-uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
369
- int mmu_idx, uintptr_t ra);
370
-
371
int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
372
int mmu_idx, uintptr_t ra);
373
-int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
374
- int mmu_idx, uintptr_t ra);
375
+
376
+uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
377
+ int mmu_idx, uintptr_t ra);
378
+int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
379
+ int mmu_idx, uintptr_t ra);
380
+uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
381
+ int mmu_idx, uintptr_t ra);
382
+uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
383
+ int mmu_idx, uintptr_t ra);
384
+
385
+uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
386
+ int mmu_idx, uintptr_t ra);
387
+int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
388
+ int mmu_idx, uintptr_t ra);
389
+uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
390
+ int mmu_idx, uintptr_t ra);
391
+uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
392
+ int mmu_idx, uintptr_t ra);
393
394
void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
395
int mmu_idx, uintptr_t retaddr);
396
-void cpu_stw_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
397
- int mmu_idx, uintptr_t retaddr);
398
-void cpu_stl_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
399
- int mmu_idx, uintptr_t retaddr);
400
-void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
401
- int mmu_idx, uintptr_t retaddr);
402
+
403
+void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
404
+ int mmu_idx, uintptr_t retaddr);
405
+void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
406
+ int mmu_idx, uintptr_t retaddr);
407
+void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
408
+ int mmu_idx, uintptr_t retaddr);
409
+
410
+void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
411
+ int mmu_idx, uintptr_t retaddr);
412
+void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
413
+ int mmu_idx, uintptr_t retaddr);
414
+void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
415
+ int mmu_idx, uintptr_t retaddr);
416
417
#endif /* defined(CONFIG_USER_ONLY) */
418
419
+#ifdef TARGET_WORDS_BIGENDIAN
420
+# define cpu_lduw_data cpu_lduw_be_data
421
+# define cpu_ldsw_data cpu_ldsw_be_data
422
+# define cpu_ldl_data cpu_ldl_be_data
423
+# define cpu_ldq_data cpu_ldq_be_data
424
+# define cpu_lduw_data_ra cpu_lduw_be_data_ra
425
+# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra
426
+# define cpu_ldl_data_ra cpu_ldl_be_data_ra
427
+# define cpu_ldq_data_ra cpu_ldq_be_data_ra
428
+# define cpu_lduw_mmuidx_ra cpu_lduw_be_mmuidx_ra
429
+# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra
430
+# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra
431
+# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra
432
+# define cpu_stw_data cpu_stw_be_data
433
+# define cpu_stl_data cpu_stl_be_data
434
+# define cpu_stq_data cpu_stq_be_data
435
+# define cpu_stw_data_ra cpu_stw_be_data_ra
436
+# define cpu_stl_data_ra cpu_stl_be_data_ra
437
+# define cpu_stq_data_ra cpu_stq_be_data_ra
438
+# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra
439
+# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra
440
+# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra
441
+#else
442
+# define cpu_lduw_data cpu_lduw_le_data
443
+# define cpu_ldsw_data cpu_ldsw_le_data
444
+# define cpu_ldl_data cpu_ldl_le_data
445
+# define cpu_ldq_data cpu_ldq_le_data
446
+# define cpu_lduw_data_ra cpu_lduw_le_data_ra
447
+# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra
448
+# define cpu_ldl_data_ra cpu_ldl_le_data_ra
449
+# define cpu_ldq_data_ra cpu_ldq_le_data_ra
450
+# define cpu_lduw_mmuidx_ra cpu_lduw_le_mmuidx_ra
451
+# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra
452
+# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra
453
+# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra
454
+# define cpu_stw_data cpu_stw_le_data
455
+# define cpu_stl_data cpu_stl_le_data
456
+# define cpu_stq_data cpu_stq_le_data
457
+# define cpu_stw_data_ra cpu_stw_le_data_ra
458
+# define cpu_stl_data_ra cpu_stl_le_data_ra
459
+# define cpu_stq_data_ra cpu_stq_le_data_ra
460
+# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra
461
+# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra
462
+# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra
463
+#endif
464
+
465
uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
466
uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr);
467
uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr);
468
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
469
index XXXXXXX..XXXXXXX 100644
470
--- a/accel/tcg/cputlb.c
471
+++ b/accel/tcg/cputlb.c
472
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
473
full_ldub_mmu);
474
}
475
476
-uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
477
- int mmu_idx, uintptr_t ra)
478
+uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
479
+ int mmu_idx, uintptr_t ra)
480
{
481
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_TEUW,
482
- MO_TE == MO_LE
483
- ? full_le_lduw_mmu : full_be_lduw_mmu);
484
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUW, full_be_lduw_mmu);
485
}
486
487
-int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
488
- int mmu_idx, uintptr_t ra)
489
+int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
490
+ int mmu_idx, uintptr_t ra)
491
{
492
- return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_TESW,
493
- MO_TE == MO_LE
494
- ? full_le_lduw_mmu : full_be_lduw_mmu);
495
+ return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_BESW,
496
+ full_be_lduw_mmu);
497
}
498
499
-uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
500
- int mmu_idx, uintptr_t ra)
501
+uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
502
+ int mmu_idx, uintptr_t ra)
503
{
504
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_TEUL,
505
- MO_TE == MO_LE
506
- ? full_le_ldul_mmu : full_be_ldul_mmu);
507
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUL, full_be_ldul_mmu);
508
}
509
510
-uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
511
- int mmu_idx, uintptr_t ra)
512
+uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
513
+ int mmu_idx, uintptr_t ra)
514
{
515
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_TEQ,
516
- MO_TE == MO_LE
517
- ? helper_le_ldq_mmu : helper_be_ldq_mmu);
518
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEQ, helper_be_ldq_mmu);
519
+}
520
+
521
+uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
522
+ int mmu_idx, uintptr_t ra)
523
+{
524
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUW, full_le_lduw_mmu);
525
+}
526
+
527
+int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
528
+ int mmu_idx, uintptr_t ra)
529
+{
530
+ return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_LESW,
531
+ full_le_lduw_mmu);
532
+}
533
+
534
+uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
535
+ int mmu_idx, uintptr_t ra)
536
+{
537
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUL, full_le_ldul_mmu);
538
+}
539
+
540
+uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
541
+ int mmu_idx, uintptr_t ra)
542
+{
543
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEQ, helper_le_ldq_mmu);
544
}
545
546
uint32_t cpu_ldub_data_ra(CPUArchState *env, target_ulong ptr,
547
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
548
return cpu_ldsb_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
549
}
550
551
-uint32_t cpu_lduw_data_ra(CPUArchState *env, target_ulong ptr,
552
- uintptr_t retaddr)
553
+uint32_t cpu_lduw_be_data_ra(CPUArchState *env, target_ulong ptr,
554
+ uintptr_t retaddr)
555
{
556
- return cpu_lduw_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
557
+ return cpu_lduw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
558
}
559
560
-int cpu_ldsw_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
561
+int cpu_ldsw_be_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
562
{
563
- return cpu_ldsw_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
564
+ return cpu_ldsw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
565
}
566
567
-uint32_t cpu_ldl_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
568
+uint32_t cpu_ldl_be_data_ra(CPUArchState *env, target_ulong ptr,
569
+ uintptr_t retaddr)
570
{
571
- return cpu_ldl_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
572
+ return cpu_ldl_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
573
}
574
575
-uint64_t cpu_ldq_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
576
+uint64_t cpu_ldq_be_data_ra(CPUArchState *env, target_ulong ptr,
577
+ uintptr_t retaddr)
578
{
579
- return cpu_ldq_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
580
+ return cpu_ldq_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
581
+}
582
+
583
+uint32_t cpu_lduw_le_data_ra(CPUArchState *env, target_ulong ptr,
584
+ uintptr_t retaddr)
585
+{
586
+ return cpu_lduw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
587
+}
588
+
589
+int cpu_ldsw_le_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
590
+{
591
+ return cpu_ldsw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
592
+}
593
+
594
+uint32_t cpu_ldl_le_data_ra(CPUArchState *env, target_ulong ptr,
595
+ uintptr_t retaddr)
596
+{
597
+ return cpu_ldl_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
598
+}
599
+
600
+uint64_t cpu_ldq_le_data_ra(CPUArchState *env, target_ulong ptr,
601
+ uintptr_t retaddr)
602
+{
603
+ return cpu_ldq_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
604
}
605
606
uint32_t cpu_ldub_data(CPUArchState *env, target_ulong ptr)
607
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data(CPUArchState *env, target_ulong ptr)
608
return cpu_ldsb_data_ra(env, ptr, 0);
609
}
610
611
-uint32_t cpu_lduw_data(CPUArchState *env, target_ulong ptr)
612
+uint32_t cpu_lduw_be_data(CPUArchState *env, target_ulong ptr)
613
{
614
- return cpu_lduw_data_ra(env, ptr, 0);
615
+ return cpu_lduw_be_data_ra(env, ptr, 0);
616
}
617
618
-int cpu_ldsw_data(CPUArchState *env, target_ulong ptr)
619
+int cpu_ldsw_be_data(CPUArchState *env, target_ulong ptr)
620
{
621
- return cpu_ldsw_data_ra(env, ptr, 0);
622
+ return cpu_ldsw_be_data_ra(env, ptr, 0);
623
}
624
625
-uint32_t cpu_ldl_data(CPUArchState *env, target_ulong ptr)
626
+uint32_t cpu_ldl_be_data(CPUArchState *env, target_ulong ptr)
627
{
628
- return cpu_ldl_data_ra(env, ptr, 0);
629
+ return cpu_ldl_be_data_ra(env, ptr, 0);
630
}
631
632
-uint64_t cpu_ldq_data(CPUArchState *env, target_ulong ptr)
633
+uint64_t cpu_ldq_be_data(CPUArchState *env, target_ulong ptr)
634
{
635
- return cpu_ldq_data_ra(env, ptr, 0);
636
+ return cpu_ldq_be_data_ra(env, ptr, 0);
637
+}
638
+
639
+uint32_t cpu_lduw_le_data(CPUArchState *env, target_ulong ptr)
640
+{
641
+ return cpu_lduw_le_data_ra(env, ptr, 0);
642
+}
643
+
644
+int cpu_ldsw_le_data(CPUArchState *env, target_ulong ptr)
645
+{
646
+ return cpu_ldsw_le_data_ra(env, ptr, 0);
647
+}
648
+
649
+uint32_t cpu_ldl_le_data(CPUArchState *env, target_ulong ptr)
650
+{
651
+ return cpu_ldl_le_data_ra(env, ptr, 0);
652
+}
653
+
654
+uint64_t cpu_ldq_le_data(CPUArchState *env, target_ulong ptr)
655
+{
656
+ return cpu_ldq_le_data_ra(env, ptr, 0);
657
}
658
659
/*
660
@@ -XXX,XX +XXX,XX @@ void cpu_stb_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
661
cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_UB);
662
}
663
664
-void cpu_stw_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
665
- int mmu_idx, uintptr_t retaddr)
666
+void cpu_stw_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
667
+ int mmu_idx, uintptr_t retaddr)
668
{
669
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEUW);
670
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUW);
671
}
672
673
-void cpu_stl_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
674
- int mmu_idx, uintptr_t retaddr)
675
+void cpu_stl_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
676
+ int mmu_idx, uintptr_t retaddr)
677
{
678
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEUL);
679
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUL);
680
}
681
682
-void cpu_stq_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
683
- int mmu_idx, uintptr_t retaddr)
684
+void cpu_stq_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
685
+ int mmu_idx, uintptr_t retaddr)
686
{
687
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEQ);
688
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEQ);
689
+}
690
+
691
+void cpu_stw_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
692
+ int mmu_idx, uintptr_t retaddr)
693
+{
694
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUW);
695
+}
696
+
697
+void cpu_stl_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
698
+ int mmu_idx, uintptr_t retaddr)
699
+{
700
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUL);
701
+}
702
+
703
+void cpu_stq_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
704
+ int mmu_idx, uintptr_t retaddr)
705
+{
706
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEQ);
707
}
708
709
void cpu_stb_data_ra(CPUArchState *env, target_ulong ptr,
710
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data_ra(CPUArchState *env, target_ulong ptr,
711
cpu_stb_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
712
}
713
714
-void cpu_stw_data_ra(CPUArchState *env, target_ulong ptr,
715
- uint32_t val, uintptr_t retaddr)
716
+void cpu_stw_be_data_ra(CPUArchState *env, target_ulong ptr,
717
+ uint32_t val, uintptr_t retaddr)
718
{
719
- cpu_stw_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
720
+ cpu_stw_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
721
}
722
723
-void cpu_stl_data_ra(CPUArchState *env, target_ulong ptr,
724
- uint32_t val, uintptr_t retaddr)
725
+void cpu_stl_be_data_ra(CPUArchState *env, target_ulong ptr,
726
+ uint32_t val, uintptr_t retaddr)
727
{
728
- cpu_stl_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
729
+ cpu_stl_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
730
}
731
732
-void cpu_stq_data_ra(CPUArchState *env, target_ulong ptr,
733
- uint64_t val, uintptr_t retaddr)
734
+void cpu_stq_be_data_ra(CPUArchState *env, target_ulong ptr,
735
+ uint64_t val, uintptr_t retaddr)
736
{
737
- cpu_stq_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
738
+ cpu_stq_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
739
+}
740
+
741
+void cpu_stw_le_data_ra(CPUArchState *env, target_ulong ptr,
742
+ uint32_t val, uintptr_t retaddr)
743
+{
744
+ cpu_stw_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
745
+}
746
+
747
+void cpu_stl_le_data_ra(CPUArchState *env, target_ulong ptr,
748
+ uint32_t val, uintptr_t retaddr)
749
+{
750
+ cpu_stl_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
751
+}
752
+
753
+void cpu_stq_le_data_ra(CPUArchState *env, target_ulong ptr,
754
+ uint64_t val, uintptr_t retaddr)
755
+{
756
+ cpu_stq_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
757
}
758
759
void cpu_stb_data(CPUArchState *env, target_ulong ptr, uint32_t val)
760
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data(CPUArchState *env, target_ulong ptr, uint32_t val)
761
cpu_stb_data_ra(env, ptr, val, 0);
762
}
763
764
-void cpu_stw_data(CPUArchState *env, target_ulong ptr, uint32_t val)
765
+void cpu_stw_be_data(CPUArchState *env, target_ulong ptr, uint32_t val)
766
{
767
- cpu_stw_data_ra(env, ptr, val, 0);
768
+ cpu_stw_be_data_ra(env, ptr, val, 0);
769
}
770
771
-void cpu_stl_data(CPUArchState *env, target_ulong ptr, uint32_t val)
772
+void cpu_stl_be_data(CPUArchState *env, target_ulong ptr, uint32_t val)
773
{
774
- cpu_stl_data_ra(env, ptr, val, 0);
775
+ cpu_stl_be_data_ra(env, ptr, val, 0);
776
}
777
778
-void cpu_stq_data(CPUArchState *env, target_ulong ptr, uint64_t val)
779
+void cpu_stq_be_data(CPUArchState *env, target_ulong ptr, uint64_t val)
780
{
781
- cpu_stq_data_ra(env, ptr, val, 0);
782
+ cpu_stq_be_data_ra(env, ptr, val, 0);
783
+}
784
+
785
+void cpu_stw_le_data(CPUArchState *env, target_ulong ptr, uint32_t val)
786
+{
787
+ cpu_stw_le_data_ra(env, ptr, val, 0);
788
+}
789
+
790
+void cpu_stl_le_data(CPUArchState *env, target_ulong ptr, uint32_t val)
791
+{
792
+ cpu_stl_le_data_ra(env, ptr, val, 0);
793
+}
794
+
795
+void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val)
796
+{
797
+ cpu_stq_le_data_ra(env, ptr, val, 0);
798
}
799
800
/* First set of helpers allows passing in of OI and RETADDR. This makes
801
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
802
index XXXXXXX..XXXXXXX 100644
803
--- a/accel/tcg/user-exec.c
804
+++ b/accel/tcg/user-exec.c
805
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr)
806
return ret;
807
}
808
809
-uint32_t cpu_lduw_data(CPUArchState *env, abi_ptr ptr)
810
+uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr)
811
{
812
uint32_t ret;
813
- uint16_t meminfo = trace_mem_get_info(MO_TEUW, MMU_USER_IDX, false);
814
+ uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, false);
815
816
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
817
- ret = lduw_p(g2h(ptr));
818
+ ret = lduw_be_p(g2h(ptr));
819
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
820
return ret;
821
}
822
823
-int cpu_ldsw_data(CPUArchState *env, abi_ptr ptr)
824
+int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr)
825
{
826
int ret;
827
- uint16_t meminfo = trace_mem_get_info(MO_TESW, MMU_USER_IDX, false);
828
+ uint16_t meminfo = trace_mem_get_info(MO_BESW, MMU_USER_IDX, false);
829
830
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
831
- ret = ldsw_p(g2h(ptr));
832
+ ret = ldsw_be_p(g2h(ptr));
833
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
834
return ret;
835
}
836
837
-uint32_t cpu_ldl_data(CPUArchState *env, abi_ptr ptr)
838
+uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
839
{
840
uint32_t ret;
841
- uint16_t meminfo = trace_mem_get_info(MO_TEUL, MMU_USER_IDX, false);
842
+ uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, false);
843
844
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
845
- ret = ldl_p(g2h(ptr));
846
+ ret = ldl_be_p(g2h(ptr));
847
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
848
return ret;
849
}
850
851
-uint64_t cpu_ldq_data(CPUArchState *env, abi_ptr ptr)
852
+uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr)
853
{
854
uint64_t ret;
855
- uint16_t meminfo = trace_mem_get_info(MO_TEQ, MMU_USER_IDX, false);
856
+ uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, false);
857
858
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
859
- ret = ldq_p(g2h(ptr));
860
+ ret = ldq_be_p(g2h(ptr));
861
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
862
+ return ret;
863
+}
864
+
865
+uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr)
866
+{
867
+ uint32_t ret;
868
+ uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, false);
869
+
870
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
871
+ ret = lduw_le_p(g2h(ptr));
872
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
873
+ return ret;
874
+}
875
+
876
+int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr)
877
+{
878
+ int ret;
879
+ uint16_t meminfo = trace_mem_get_info(MO_LESW, MMU_USER_IDX, false);
880
+
881
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
882
+ ret = ldsw_le_p(g2h(ptr));
883
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
884
+ return ret;
885
+}
886
+
887
+uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
888
+{
889
+ uint32_t ret;
890
+ uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, false);
891
+
892
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
893
+ ret = ldl_le_p(g2h(ptr));
894
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
895
+ return ret;
896
+}
897
+
898
+uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr)
899
+{
900
+ uint64_t ret;
901
+ uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, false);
902
+
903
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
904
+ ret = ldq_le_p(g2h(ptr));
905
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
906
return ret;
907
}
908
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
909
return ret;
910
}
911
912
-uint32_t cpu_lduw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
913
+uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
914
{
915
uint32_t ret;
916
917
set_helper_retaddr(retaddr);
918
- ret = cpu_lduw_data(env, ptr);
919
+ ret = cpu_lduw_be_data(env, ptr);
920
clear_helper_retaddr();
921
return ret;
922
}
923
924
-int cpu_ldsw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
925
+int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
926
{
927
int ret;
928
929
set_helper_retaddr(retaddr);
930
- ret = cpu_ldsw_data(env, ptr);
931
+ ret = cpu_ldsw_be_data(env, ptr);
932
clear_helper_retaddr();
933
return ret;
934
}
935
936
-uint32_t cpu_ldl_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
937
+uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
938
{
939
uint32_t ret;
940
941
set_helper_retaddr(retaddr);
942
- ret = cpu_ldl_data(env, ptr);
943
+ ret = cpu_ldl_be_data(env, ptr);
944
clear_helper_retaddr();
945
return ret;
946
}
947
948
-uint64_t cpu_ldq_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
949
+uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
950
{
951
uint64_t ret;
952
953
set_helper_retaddr(retaddr);
954
- ret = cpu_ldq_data(env, ptr);
955
+ ret = cpu_ldq_be_data(env, ptr);
956
+ clear_helper_retaddr();
957
+ return ret;
958
+}
959
+
960
+uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
961
+{
962
+ uint32_t ret;
963
+
964
+ set_helper_retaddr(retaddr);
965
+ ret = cpu_lduw_le_data(env, ptr);
966
+ clear_helper_retaddr();
967
+ return ret;
968
+}
969
+
970
+int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
971
+{
972
+ int ret;
973
+
974
+ set_helper_retaddr(retaddr);
975
+ ret = cpu_ldsw_le_data(env, ptr);
976
+ clear_helper_retaddr();
977
+ return ret;
978
+}
979
+
980
+uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
981
+{
982
+ uint32_t ret;
983
+
984
+ set_helper_retaddr(retaddr);
985
+ ret = cpu_ldl_le_data(env, ptr);
986
+ clear_helper_retaddr();
987
+ return ret;
988
+}
989
+
990
+uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
991
+{
992
+ uint64_t ret;
993
+
994
+ set_helper_retaddr(retaddr);
995
+ ret = cpu_ldq_le_data(env, ptr);
996
clear_helper_retaddr();
997
return ret;
998
}
999
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1000
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1001
}
1002
1003
-void cpu_stw_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1004
+void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1005
{
1006
- uint16_t meminfo = trace_mem_get_info(MO_TEUW, MMU_USER_IDX, true);
1007
+ uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, true);
1008
1009
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1010
- stw_p(g2h(ptr), val);
1011
+ stw_be_p(g2h(ptr), val);
1012
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1013
}
1014
1015
-void cpu_stl_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1016
+void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1017
{
1018
- uint16_t meminfo = trace_mem_get_info(MO_TEUL, MMU_USER_IDX, true);
1019
+ uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, true);
1020
1021
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1022
- stl_p(g2h(ptr), val);
1023
+ stl_be_p(g2h(ptr), val);
1024
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1025
}
1026
1027
-void cpu_stq_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
1028
+void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
1029
{
1030
- uint16_t meminfo = trace_mem_get_info(MO_TEQ, MMU_USER_IDX, true);
1031
+ uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, true);
1032
1033
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1034
- stq_p(g2h(ptr), val);
1035
+ stq_be_p(g2h(ptr), val);
1036
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1037
+}
1038
+
1039
+void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1040
+{
1041
+ uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, true);
1042
+
1043
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1044
+ stw_le_p(g2h(ptr), val);
1045
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1046
+}
1047
+
1048
+void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1049
+{
1050
+ uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, true);
1051
+
1052
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1053
+ stl_le_p(g2h(ptr), val);
1054
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1055
+}
1056
+
1057
+void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
1058
+{
1059
+ uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, true);
1060
+
1061
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1062
+ stq_le_p(g2h(ptr), val);
1063
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1064
}
1065
1066
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
1067
clear_helper_retaddr();
1068
}
1069
1070
-void cpu_stw_data_ra(CPUArchState *env, abi_ptr ptr,
1071
- uint32_t val, uintptr_t retaddr)
1072
+void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
1073
+ uint32_t val, uintptr_t retaddr)
1074
{
1075
set_helper_retaddr(retaddr);
1076
- cpu_stw_data(env, ptr, val);
1077
+ cpu_stw_be_data(env, ptr, val);
1078
clear_helper_retaddr();
1079
}
1080
1081
-void cpu_stl_data_ra(CPUArchState *env, abi_ptr ptr,
1082
- uint32_t val, uintptr_t retaddr)
1083
+void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
1084
+ uint32_t val, uintptr_t retaddr)
1085
{
1086
set_helper_retaddr(retaddr);
1087
- cpu_stl_data(env, ptr, val);
1088
+ cpu_stl_be_data(env, ptr, val);
1089
clear_helper_retaddr();
1090
}
1091
1092
-void cpu_stq_data_ra(CPUArchState *env, abi_ptr ptr,
1093
- uint64_t val, uintptr_t retaddr)
1094
+void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
1095
+ uint64_t val, uintptr_t retaddr)
1096
{
1097
set_helper_retaddr(retaddr);
1098
- cpu_stq_data(env, ptr, val);
1099
+ cpu_stq_be_data(env, ptr, val);
1100
+ clear_helper_retaddr();
1101
+}
1102
+
1103
+void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
1104
+ uint32_t val, uintptr_t retaddr)
1105
+{
1106
+ set_helper_retaddr(retaddr);
1107
+ cpu_stw_le_data(env, ptr, val);
1108
+ clear_helper_retaddr();
1109
+}
1110
+
1111
+void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
1112
+ uint32_t val, uintptr_t retaddr)
1113
+{
1114
+ set_helper_retaddr(retaddr);
1115
+ cpu_stl_le_data(env, ptr, val);
1116
+ clear_helper_retaddr();
1117
+}
1118
+
1119
+void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
1120
+ uint64_t val, uintptr_t retaddr)
1121
+{
1122
+ set_helper_retaddr(retaddr);
1123
+ cpu_stq_le_data(env, ptr, val);
1124
clear_helper_retaddr();
1125
}
1126
1127
--
230
--
1128
2.20.1
231
2.25.1
1129
232
1130
233
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
2
3
A KVM-only build won't be able to run TCG cpus.
3
All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3
4
4
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20200504172448.9402-6-philmd@redhat.com
7
Message-id: 20221206102504.165775-8-tobias.roehmel@rwth-aachen.de
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
9
---
10
target/arm/cpu.c | 634 -------------------------------------
10
target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++
11
target/arm/cpu_tcg.c | 664 +++++++++++++++++++++++++++++++++++++++
11
1 file changed, 42 insertions(+)
12
target/arm/Makefile.objs | 1 +
13
3 files changed, 665 insertions(+), 634 deletions(-)
14
create mode 100644 target/arm/cpu_tcg.c
15
12
16
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
13
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.c
15
--- a/target/arm/cpu_tcg.c
19
+++ b/target/arm/cpu.c
16
+++ b/target/arm/cpu_tcg.c
20
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
21
return true;
18
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
22
}
19
}
23
20
24
-#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
21
+static void cortex_r52_initfn(Object *obj)
25
-static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
26
-{
27
- CPUClass *cc = CPU_GET_CLASS(cs);
28
- ARMCPU *cpu = ARM_CPU(cs);
29
- CPUARMState *env = &cpu->env;
30
- bool ret = false;
31
-
32
- /*
33
- * ARMv7-M interrupt masking works differently than -A or -R.
34
- * There is no FIQ/IRQ distinction. Instead of I and F bits
35
- * masking FIQ and IRQ interrupts, an exception is taken only
36
- * if it is higher priority than the current execution priority
37
- * (which depends on state like BASEPRI, FAULTMASK and the
38
- * currently active exception).
39
- */
40
- if (interrupt_request & CPU_INTERRUPT_HARD
41
- && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
42
- cs->exception_index = EXCP_IRQ;
43
- cc->do_interrupt(cs);
44
- ret = true;
45
- }
46
- return ret;
47
-}
48
-#endif
49
-
50
void arm_cpu_update_virq(ARMCPU *cpu)
51
{
52
/*
53
@@ -XXX,XX +XXX,XX @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
54
/* CPU models. These are not needed for the AArch64 linux-user build. */
55
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
56
57
-static void arm926_initfn(Object *obj)
58
-{
59
- ARMCPU *cpu = ARM_CPU(obj);
60
-
61
- cpu->dtb_compatible = "arm,arm926";
62
- set_feature(&cpu->env, ARM_FEATURE_V5);
63
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
64
- set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
65
- cpu->midr = 0x41069265;
66
- cpu->reset_fpsid = 0x41011090;
67
- cpu->ctr = 0x1dd20d2;
68
- cpu->reset_sctlr = 0x00090078;
69
-
70
- /*
71
- * ARMv5 does not have the ID_ISAR registers, but we can still
72
- * set the field to indicate Jazelle support within QEMU.
73
- */
74
- cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
75
- /*
76
- * Similarly, we need to set MVFR0 fields to enable vfp and short vector
77
- * support even though ARMv5 doesn't have this register.
78
- */
79
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
80
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
81
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
82
-}
83
-
84
-static void arm946_initfn(Object *obj)
85
-{
86
- ARMCPU *cpu = ARM_CPU(obj);
87
-
88
- cpu->dtb_compatible = "arm,arm946";
89
- set_feature(&cpu->env, ARM_FEATURE_V5);
90
- set_feature(&cpu->env, ARM_FEATURE_PMSA);
91
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
92
- cpu->midr = 0x41059461;
93
- cpu->ctr = 0x0f004006;
94
- cpu->reset_sctlr = 0x00000078;
95
-}
96
-
97
-static void arm1026_initfn(Object *obj)
98
-{
99
- ARMCPU *cpu = ARM_CPU(obj);
100
-
101
- cpu->dtb_compatible = "arm,arm1026";
102
- set_feature(&cpu->env, ARM_FEATURE_V5);
103
- set_feature(&cpu->env, ARM_FEATURE_AUXCR);
104
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
105
- set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
106
- cpu->midr = 0x4106a262;
107
- cpu->reset_fpsid = 0x410110a0;
108
- cpu->ctr = 0x1dd20d2;
109
- cpu->reset_sctlr = 0x00090078;
110
- cpu->reset_auxcr = 1;
111
-
112
- /*
113
- * ARMv5 does not have the ID_ISAR registers, but we can still
114
- * set the field to indicate Jazelle support within QEMU.
115
- */
116
- cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
117
- /*
118
- * Similarly, we need to set MVFR0 fields to enable vfp and short vector
119
- * support even though ARMv5 doesn't have this register.
120
- */
121
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
122
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
123
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
124
-
125
- {
126
- /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
127
- ARMCPRegInfo ifar = {
128
- .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
129
- .access = PL1_RW,
130
- .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
131
- .resetvalue = 0
132
- };
133
- define_one_arm_cp_reg(cpu, &ifar);
134
- }
135
-}
136
-
137
-static void arm1136_r2_initfn(Object *obj)
138
-{
139
- ARMCPU *cpu = ARM_CPU(obj);
140
- /*
141
- * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
142
- * older core than plain "arm1136". In particular this does not
143
- * have the v6K features.
144
- * These ID register values are correct for 1136 but may be wrong
145
- * for 1136_r2 (in particular r0p2 does not actually implement most
146
- * of the ID registers).
147
- */
148
-
149
- cpu->dtb_compatible = "arm,arm1136";
150
- set_feature(&cpu->env, ARM_FEATURE_V6);
151
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
152
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
153
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
154
- cpu->midr = 0x4107b362;
155
- cpu->reset_fpsid = 0x410120b4;
156
- cpu->isar.mvfr0 = 0x11111111;
157
- cpu->isar.mvfr1 = 0x00000000;
158
- cpu->ctr = 0x1dd20d2;
159
- cpu->reset_sctlr = 0x00050078;
160
- cpu->id_pfr0 = 0x111;
161
- cpu->id_pfr1 = 0x1;
162
- cpu->isar.id_dfr0 = 0x2;
163
- cpu->id_afr0 = 0x3;
164
- cpu->isar.id_mmfr0 = 0x01130003;
165
- cpu->isar.id_mmfr1 = 0x10030302;
166
- cpu->isar.id_mmfr2 = 0x01222110;
167
- cpu->isar.id_isar0 = 0x00140011;
168
- cpu->isar.id_isar1 = 0x12002111;
169
- cpu->isar.id_isar2 = 0x11231111;
170
- cpu->isar.id_isar3 = 0x01102131;
171
- cpu->isar.id_isar4 = 0x141;
172
- cpu->reset_auxcr = 7;
173
-}
174
-
175
-static void arm1136_initfn(Object *obj)
176
-{
177
- ARMCPU *cpu = ARM_CPU(obj);
178
-
179
- cpu->dtb_compatible = "arm,arm1136";
180
- set_feature(&cpu->env, ARM_FEATURE_V6K);
181
- set_feature(&cpu->env, ARM_FEATURE_V6);
182
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
183
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
184
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
185
- cpu->midr = 0x4117b363;
186
- cpu->reset_fpsid = 0x410120b4;
187
- cpu->isar.mvfr0 = 0x11111111;
188
- cpu->isar.mvfr1 = 0x00000000;
189
- cpu->ctr = 0x1dd20d2;
190
- cpu->reset_sctlr = 0x00050078;
191
- cpu->id_pfr0 = 0x111;
192
- cpu->id_pfr1 = 0x1;
193
- cpu->isar.id_dfr0 = 0x2;
194
- cpu->id_afr0 = 0x3;
195
- cpu->isar.id_mmfr0 = 0x01130003;
196
- cpu->isar.id_mmfr1 = 0x10030302;
197
- cpu->isar.id_mmfr2 = 0x01222110;
198
- cpu->isar.id_isar0 = 0x00140011;
199
- cpu->isar.id_isar1 = 0x12002111;
200
- cpu->isar.id_isar2 = 0x11231111;
201
- cpu->isar.id_isar3 = 0x01102131;
202
- cpu->isar.id_isar4 = 0x141;
203
- cpu->reset_auxcr = 7;
204
-}
205
-
206
-static void arm1176_initfn(Object *obj)
207
-{
208
- ARMCPU *cpu = ARM_CPU(obj);
209
-
210
- cpu->dtb_compatible = "arm,arm1176";
211
- set_feature(&cpu->env, ARM_FEATURE_V6K);
212
- set_feature(&cpu->env, ARM_FEATURE_VAPA);
213
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
214
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
215
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
216
- set_feature(&cpu->env, ARM_FEATURE_EL3);
217
- cpu->midr = 0x410fb767;
218
- cpu->reset_fpsid = 0x410120b5;
219
- cpu->isar.mvfr0 = 0x11111111;
220
- cpu->isar.mvfr1 = 0x00000000;
221
- cpu->ctr = 0x1dd20d2;
222
- cpu->reset_sctlr = 0x00050078;
223
- cpu->id_pfr0 = 0x111;
224
- cpu->id_pfr1 = 0x11;
225
- cpu->isar.id_dfr0 = 0x33;
226
- cpu->id_afr0 = 0;
227
- cpu->isar.id_mmfr0 = 0x01130003;
228
- cpu->isar.id_mmfr1 = 0x10030302;
229
- cpu->isar.id_mmfr2 = 0x01222100;
230
- cpu->isar.id_isar0 = 0x0140011;
231
- cpu->isar.id_isar1 = 0x12002111;
232
- cpu->isar.id_isar2 = 0x11231121;
233
- cpu->isar.id_isar3 = 0x01102131;
234
- cpu->isar.id_isar4 = 0x01141;
235
- cpu->reset_auxcr = 7;
236
-}
237
-
238
-static void arm11mpcore_initfn(Object *obj)
239
-{
240
- ARMCPU *cpu = ARM_CPU(obj);
241
-
242
- cpu->dtb_compatible = "arm,arm11mpcore";
243
- set_feature(&cpu->env, ARM_FEATURE_V6K);
244
- set_feature(&cpu->env, ARM_FEATURE_VAPA);
245
- set_feature(&cpu->env, ARM_FEATURE_MPIDR);
246
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
247
- cpu->midr = 0x410fb022;
248
- cpu->reset_fpsid = 0x410120b4;
249
- cpu->isar.mvfr0 = 0x11111111;
250
- cpu->isar.mvfr1 = 0x00000000;
251
- cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
252
- cpu->id_pfr0 = 0x111;
253
- cpu->id_pfr1 = 0x1;
254
- cpu->isar.id_dfr0 = 0;
255
- cpu->id_afr0 = 0x2;
256
- cpu->isar.id_mmfr0 = 0x01100103;
257
- cpu->isar.id_mmfr1 = 0x10020302;
258
- cpu->isar.id_mmfr2 = 0x01222000;
259
- cpu->isar.id_isar0 = 0x00100011;
260
- cpu->isar.id_isar1 = 0x12002111;
261
- cpu->isar.id_isar2 = 0x11221011;
262
- cpu->isar.id_isar3 = 0x01102131;
263
- cpu->isar.id_isar4 = 0x141;
264
- cpu->reset_auxcr = 1;
265
-}
266
-
267
-static void cortex_m0_initfn(Object *obj)
268
-{
269
- ARMCPU *cpu = ARM_CPU(obj);
270
- set_feature(&cpu->env, ARM_FEATURE_V6);
271
- set_feature(&cpu->env, ARM_FEATURE_M);
272
-
273
- cpu->midr = 0x410cc200;
274
-}
275
-
276
-static void cortex_m3_initfn(Object *obj)
277
-{
278
- ARMCPU *cpu = ARM_CPU(obj);
279
- set_feature(&cpu->env, ARM_FEATURE_V7);
280
- set_feature(&cpu->env, ARM_FEATURE_M);
281
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
282
- cpu->midr = 0x410fc231;
283
- cpu->pmsav7_dregion = 8;
284
- cpu->id_pfr0 = 0x00000030;
285
- cpu->id_pfr1 = 0x00000200;
286
- cpu->isar.id_dfr0 = 0x00100000;
287
- cpu->id_afr0 = 0x00000000;
288
- cpu->isar.id_mmfr0 = 0x00000030;
289
- cpu->isar.id_mmfr1 = 0x00000000;
290
- cpu->isar.id_mmfr2 = 0x00000000;
291
- cpu->isar.id_mmfr3 = 0x00000000;
292
- cpu->isar.id_isar0 = 0x01141110;
293
- cpu->isar.id_isar1 = 0x02111000;
294
- cpu->isar.id_isar2 = 0x21112231;
295
- cpu->isar.id_isar3 = 0x01111110;
296
- cpu->isar.id_isar4 = 0x01310102;
297
- cpu->isar.id_isar5 = 0x00000000;
298
- cpu->isar.id_isar6 = 0x00000000;
299
-}
300
-
301
-static void cortex_m4_initfn(Object *obj)
302
-{
303
- ARMCPU *cpu = ARM_CPU(obj);
304
-
305
- set_feature(&cpu->env, ARM_FEATURE_V7);
306
- set_feature(&cpu->env, ARM_FEATURE_M);
307
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
308
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
309
- cpu->midr = 0x410fc240; /* r0p0 */
310
- cpu->pmsav7_dregion = 8;
311
- cpu->isar.mvfr0 = 0x10110021;
312
- cpu->isar.mvfr1 = 0x11000011;
313
- cpu->isar.mvfr2 = 0x00000000;
314
- cpu->id_pfr0 = 0x00000030;
315
- cpu->id_pfr1 = 0x00000200;
316
- cpu->isar.id_dfr0 = 0x00100000;
317
- cpu->id_afr0 = 0x00000000;
318
- cpu->isar.id_mmfr0 = 0x00000030;
319
- cpu->isar.id_mmfr1 = 0x00000000;
320
- cpu->isar.id_mmfr2 = 0x00000000;
321
- cpu->isar.id_mmfr3 = 0x00000000;
322
- cpu->isar.id_isar0 = 0x01141110;
323
- cpu->isar.id_isar1 = 0x02111000;
324
- cpu->isar.id_isar2 = 0x21112231;
325
- cpu->isar.id_isar3 = 0x01111110;
326
- cpu->isar.id_isar4 = 0x01310102;
327
- cpu->isar.id_isar5 = 0x00000000;
328
- cpu->isar.id_isar6 = 0x00000000;
329
-}
330
-
331
-static void cortex_m7_initfn(Object *obj)
332
-{
333
- ARMCPU *cpu = ARM_CPU(obj);
334
-
335
- set_feature(&cpu->env, ARM_FEATURE_V7);
336
- set_feature(&cpu->env, ARM_FEATURE_M);
337
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
338
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
339
- cpu->midr = 0x411fc272; /* r1p2 */
340
- cpu->pmsav7_dregion = 8;
341
- cpu->isar.mvfr0 = 0x10110221;
342
- cpu->isar.mvfr1 = 0x12000011;
343
- cpu->isar.mvfr2 = 0x00000040;
344
- cpu->id_pfr0 = 0x00000030;
345
- cpu->id_pfr1 = 0x00000200;
346
- cpu->isar.id_dfr0 = 0x00100000;
347
- cpu->id_afr0 = 0x00000000;
348
- cpu->isar.id_mmfr0 = 0x00100030;
349
- cpu->isar.id_mmfr1 = 0x00000000;
350
- cpu->isar.id_mmfr2 = 0x01000000;
351
- cpu->isar.id_mmfr3 = 0x00000000;
352
- cpu->isar.id_isar0 = 0x01101110;
353
- cpu->isar.id_isar1 = 0x02112000;
354
- cpu->isar.id_isar2 = 0x20232231;
355
- cpu->isar.id_isar3 = 0x01111131;
356
- cpu->isar.id_isar4 = 0x01310132;
357
- cpu->isar.id_isar5 = 0x00000000;
358
- cpu->isar.id_isar6 = 0x00000000;
359
-}
360
-
361
-static void cortex_m33_initfn(Object *obj)
362
-{
363
- ARMCPU *cpu = ARM_CPU(obj);
364
-
365
- set_feature(&cpu->env, ARM_FEATURE_V8);
366
- set_feature(&cpu->env, ARM_FEATURE_M);
367
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
368
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
369
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
370
- cpu->midr = 0x410fd213; /* r0p3 */
371
- cpu->pmsav7_dregion = 16;
372
- cpu->sau_sregion = 8;
373
- cpu->isar.mvfr0 = 0x10110021;
374
- cpu->isar.mvfr1 = 0x11000011;
375
- cpu->isar.mvfr2 = 0x00000040;
376
- cpu->id_pfr0 = 0x00000030;
377
- cpu->id_pfr1 = 0x00000210;
378
- cpu->isar.id_dfr0 = 0x00200000;
379
- cpu->id_afr0 = 0x00000000;
380
- cpu->isar.id_mmfr0 = 0x00101F40;
381
- cpu->isar.id_mmfr1 = 0x00000000;
382
- cpu->isar.id_mmfr2 = 0x01000000;
383
- cpu->isar.id_mmfr3 = 0x00000000;
384
- cpu->isar.id_isar0 = 0x01101110;
385
- cpu->isar.id_isar1 = 0x02212000;
386
- cpu->isar.id_isar2 = 0x20232232;
387
- cpu->isar.id_isar3 = 0x01111131;
388
- cpu->isar.id_isar4 = 0x01310132;
389
- cpu->isar.id_isar5 = 0x00000000;
390
- cpu->isar.id_isar6 = 0x00000000;
391
- cpu->clidr = 0x00000000;
392
- cpu->ctr = 0x8000c000;
393
-}
394
-
395
-static void arm_v7m_class_init(ObjectClass *oc, void *data)
396
-{
397
- ARMCPUClass *acc = ARM_CPU_CLASS(oc);
398
- CPUClass *cc = CPU_CLASS(oc);
399
-
400
- acc->info = data;
401
-#ifndef CONFIG_USER_ONLY
402
- cc->do_interrupt = arm_v7m_cpu_do_interrupt;
403
-#endif
404
-
405
- cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
406
-}
407
-
408
-static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
409
- /* Dummy the TCM region regs for the moment */
410
- { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
411
- .access = PL1_RW, .type = ARM_CP_CONST },
412
- { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
413
- .access = PL1_RW, .type = ARM_CP_CONST },
414
- { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
415
- .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
416
- REGINFO_SENTINEL
417
-};
418
-
419
-static void cortex_r5_initfn(Object *obj)
420
-{
421
- ARMCPU *cpu = ARM_CPU(obj);
422
-
423
- set_feature(&cpu->env, ARM_FEATURE_V7);
424
- set_feature(&cpu->env, ARM_FEATURE_V7MP);
425
- set_feature(&cpu->env, ARM_FEATURE_PMSA);
426
- set_feature(&cpu->env, ARM_FEATURE_PMU);
427
- cpu->midr = 0x411fc153; /* r1p3 */
428
- cpu->id_pfr0 = 0x0131;
429
- cpu->id_pfr1 = 0x001;
430
- cpu->isar.id_dfr0 = 0x010400;
431
- cpu->id_afr0 = 0x0;
432
- cpu->isar.id_mmfr0 = 0x0210030;
433
- cpu->isar.id_mmfr1 = 0x00000000;
434
- cpu->isar.id_mmfr2 = 0x01200000;
435
- cpu->isar.id_mmfr3 = 0x0211;
436
- cpu->isar.id_isar0 = 0x02101111;
437
- cpu->isar.id_isar1 = 0x13112111;
438
- cpu->isar.id_isar2 = 0x21232141;
439
- cpu->isar.id_isar3 = 0x01112131;
440
- cpu->isar.id_isar4 = 0x0010142;
441
- cpu->isar.id_isar5 = 0x0;
442
- cpu->isar.id_isar6 = 0x0;
443
- cpu->mp_is_up = true;
444
- cpu->pmsav7_dregion = 16;
445
- define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
446
-}
447
-
448
-static void cortex_r5f_initfn(Object *obj)
449
-{
450
- ARMCPU *cpu = ARM_CPU(obj);
451
-
452
- cortex_r5_initfn(obj);
453
- cpu->isar.mvfr0 = 0x10110221;
454
- cpu->isar.mvfr1 = 0x00000011;
455
-}
456
-
457
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
458
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
459
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
460
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
461
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
462
}
463
464
-static void ti925t_initfn(Object *obj)
465
-{
466
- ARMCPU *cpu = ARM_CPU(obj);
467
- set_feature(&cpu->env, ARM_FEATURE_V4T);
468
- set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
469
- cpu->midr = ARM_CPUID_TI925T;
470
- cpu->ctr = 0x5109149;
471
- cpu->reset_sctlr = 0x00000070;
472
-}
473
-
474
-static void sa1100_initfn(Object *obj)
475
-{
476
- ARMCPU *cpu = ARM_CPU(obj);
477
-
478
- cpu->dtb_compatible = "intel,sa1100";
479
- set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
480
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
481
- cpu->midr = 0x4401A11B;
482
- cpu->reset_sctlr = 0x00000070;
483
-}
484
-
485
-static void sa1110_initfn(Object *obj)
486
-{
487
- ARMCPU *cpu = ARM_CPU(obj);
488
- set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
489
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
490
- cpu->midr = 0x6901B119;
491
- cpu->reset_sctlr = 0x00000070;
492
-}
493
-
494
-static void pxa250_initfn(Object *obj)
495
-{
496
- ARMCPU *cpu = ARM_CPU(obj);
497
-
498
- cpu->dtb_compatible = "marvell,xscale";
499
- set_feature(&cpu->env, ARM_FEATURE_V5);
500
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
501
- cpu->midr = 0x69052100;
502
- cpu->ctr = 0xd172172;
503
- cpu->reset_sctlr = 0x00000078;
504
-}
505
-
506
-static void pxa255_initfn(Object *obj)
507
-{
508
- ARMCPU *cpu = ARM_CPU(obj);
509
-
510
- cpu->dtb_compatible = "marvell,xscale";
511
- set_feature(&cpu->env, ARM_FEATURE_V5);
512
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
513
- cpu->midr = 0x69052d00;
514
- cpu->ctr = 0xd172172;
515
- cpu->reset_sctlr = 0x00000078;
516
-}
517
-
518
-static void pxa260_initfn(Object *obj)
519
-{
520
- ARMCPU *cpu = ARM_CPU(obj);
521
-
522
- cpu->dtb_compatible = "marvell,xscale";
523
- set_feature(&cpu->env, ARM_FEATURE_V5);
524
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
525
- cpu->midr = 0x69052903;
526
- cpu->ctr = 0xd172172;
527
- cpu->reset_sctlr = 0x00000078;
528
-}
529
-
530
-static void pxa261_initfn(Object *obj)
531
-{
532
- ARMCPU *cpu = ARM_CPU(obj);
533
-
534
- cpu->dtb_compatible = "marvell,xscale";
535
- set_feature(&cpu->env, ARM_FEATURE_V5);
536
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
537
- cpu->midr = 0x69052d05;
538
- cpu->ctr = 0xd172172;
539
- cpu->reset_sctlr = 0x00000078;
540
-}
541
-
542
-static void pxa262_initfn(Object *obj)
543
-{
544
- ARMCPU *cpu = ARM_CPU(obj);
545
-
546
- cpu->dtb_compatible = "marvell,xscale";
547
- set_feature(&cpu->env, ARM_FEATURE_V5);
548
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
549
- cpu->midr = 0x69052d06;
550
- cpu->ctr = 0xd172172;
551
- cpu->reset_sctlr = 0x00000078;
552
-}
553
-
554
-static void pxa270a0_initfn(Object *obj)
555
-{
556
- ARMCPU *cpu = ARM_CPU(obj);
557
-
558
- cpu->dtb_compatible = "marvell,xscale";
559
- set_feature(&cpu->env, ARM_FEATURE_V5);
560
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
561
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
562
- cpu->midr = 0x69054110;
563
- cpu->ctr = 0xd172172;
564
- cpu->reset_sctlr = 0x00000078;
565
-}
566
-
567
-static void pxa270a1_initfn(Object *obj)
568
-{
569
- ARMCPU *cpu = ARM_CPU(obj);
570
-
571
- cpu->dtb_compatible = "marvell,xscale";
572
- set_feature(&cpu->env, ARM_FEATURE_V5);
573
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
574
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
575
- cpu->midr = 0x69054111;
576
- cpu->ctr = 0xd172172;
577
- cpu->reset_sctlr = 0x00000078;
578
-}
579
-
580
-static void pxa270b0_initfn(Object *obj)
581
-{
582
- ARMCPU *cpu = ARM_CPU(obj);
583
-
584
- cpu->dtb_compatible = "marvell,xscale";
585
- set_feature(&cpu->env, ARM_FEATURE_V5);
586
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
587
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
588
- cpu->midr = 0x69054112;
589
- cpu->ctr = 0xd172172;
590
- cpu->reset_sctlr = 0x00000078;
591
-}
592
-
593
-static void pxa270b1_initfn(Object *obj)
594
-{
595
- ARMCPU *cpu = ARM_CPU(obj);
596
-
597
- cpu->dtb_compatible = "marvell,xscale";
598
- set_feature(&cpu->env, ARM_FEATURE_V5);
599
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
600
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
601
- cpu->midr = 0x69054113;
602
- cpu->ctr = 0xd172172;
603
- cpu->reset_sctlr = 0x00000078;
604
-}
605
-
606
-static void pxa270c0_initfn(Object *obj)
607
-{
608
- ARMCPU *cpu = ARM_CPU(obj);
609
-
610
- cpu->dtb_compatible = "marvell,xscale";
611
- set_feature(&cpu->env, ARM_FEATURE_V5);
612
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
613
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
614
- cpu->midr = 0x69054114;
615
- cpu->ctr = 0xd172172;
616
- cpu->reset_sctlr = 0x00000078;
617
-}
618
-
619
-static void pxa270c5_initfn(Object *obj)
620
-{
621
- ARMCPU *cpu = ARM_CPU(obj);
622
-
623
- cpu->dtb_compatible = "marvell,xscale";
624
- set_feature(&cpu->env, ARM_FEATURE_V5);
625
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
626
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
627
- cpu->midr = 0x69054117;
628
- cpu->ctr = 0xd172172;
629
- cpu->reset_sctlr = 0x00000078;
630
-}
631
-
632
#ifndef TARGET_AARCH64
633
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
634
* otherwise, a CPU with as many features enabled as our emulation supports.
635
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
636
637
static const ARMCPUInfo arm_cpus[] = {
638
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
639
- { .name = "arm926", .initfn = arm926_initfn },
640
- { .name = "arm946", .initfn = arm946_initfn },
641
- { .name = "arm1026", .initfn = arm1026_initfn },
642
- /*
643
- * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
644
- * older core than plain "arm1136". In particular this does not
645
- * have the v6K features.
646
- */
647
- { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
648
- { .name = "arm1136", .initfn = arm1136_initfn },
649
- { .name = "arm1176", .initfn = arm1176_initfn },
650
- { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
651
- { .name = "cortex-m0", .initfn = cortex_m0_initfn,
652
- .class_init = arm_v7m_class_init },
653
- { .name = "cortex-m3", .initfn = cortex_m3_initfn,
654
- .class_init = arm_v7m_class_init },
655
- { .name = "cortex-m4", .initfn = cortex_m4_initfn,
656
- .class_init = arm_v7m_class_init },
657
- { .name = "cortex-m7", .initfn = cortex_m7_initfn,
658
- .class_init = arm_v7m_class_init },
659
- { .name = "cortex-m33", .initfn = cortex_m33_initfn,
660
- .class_init = arm_v7m_class_init },
661
- { .name = "cortex-r5", .initfn = cortex_r5_initfn },
662
- { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
663
{ .name = "cortex-a7", .initfn = cortex_a7_initfn },
664
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
665
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
666
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
667
- { .name = "ti925t", .initfn = ti925t_initfn },
668
- { .name = "sa1100", .initfn = sa1100_initfn },
669
- { .name = "sa1110", .initfn = sa1110_initfn },
670
- { .name = "pxa250", .initfn = pxa250_initfn },
671
- { .name = "pxa255", .initfn = pxa255_initfn },
672
- { .name = "pxa260", .initfn = pxa260_initfn },
673
- { .name = "pxa261", .initfn = pxa261_initfn },
674
- { .name = "pxa262", .initfn = pxa262_initfn },
675
- /* "pxa270" is an alias for "pxa270-a0" */
676
- { .name = "pxa270", .initfn = pxa270a0_initfn },
677
- { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
678
- { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
679
- { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
680
- { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
681
- { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
682
- { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
683
#ifndef TARGET_AARCH64
684
{ .name = "max", .initfn = arm_max_initfn },
685
#endif
686
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
687
new file mode 100644
688
index XXXXXXX..XXXXXXX
689
--- /dev/null
690
+++ b/target/arm/cpu_tcg.c
691
@@ -XXX,XX +XXX,XX @@
692
+/*
693
+ * QEMU ARM TCG CPUs.
694
+ *
695
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
696
+ *
697
+ * This code is licensed under the GNU GPL v2 or later.
698
+ *
699
+ * SPDX-License-Identifier: GPL-2.0-or-later
700
+ */
701
+
702
+#include "qemu/osdep.h"
703
+#include "cpu.h"
704
+#include "internals.h"
705
+
706
+/* CPU models. These are not needed for the AArch64 linux-user build. */
707
+#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
708
+
709
+static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
710
+{
711
+ CPUClass *cc = CPU_GET_CLASS(cs);
712
+ ARMCPU *cpu = ARM_CPU(cs);
713
+ CPUARMState *env = &cpu->env;
714
+ bool ret = false;
715
+
716
+ /*
717
+ * ARMv7-M interrupt masking works differently than -A or -R.
718
+ * There is no FIQ/IRQ distinction. Instead of I and F bits
719
+ * masking FIQ and IRQ interrupts, an exception is taken only
720
+ * if it is higher priority than the current execution priority
721
+ * (which depends on state like BASEPRI, FAULTMASK and the
722
+ * currently active exception).
723
+ */
724
+ if (interrupt_request & CPU_INTERRUPT_HARD
725
+ && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
726
+ cs->exception_index = EXCP_IRQ;
727
+ cc->do_interrupt(cs);
728
+ ret = true;
729
+ }
730
+ return ret;
731
+}
732
+
733
+static void arm926_initfn(Object *obj)
734
+{
735
+ ARMCPU *cpu = ARM_CPU(obj);
736
+
737
+ cpu->dtb_compatible = "arm,arm926";
738
+ set_feature(&cpu->env, ARM_FEATURE_V5);
739
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
740
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
741
+ cpu->midr = 0x41069265;
742
+ cpu->reset_fpsid = 0x41011090;
743
+ cpu->ctr = 0x1dd20d2;
744
+ cpu->reset_sctlr = 0x00090078;
745
+
746
+ /*
747
+ * ARMv5 does not have the ID_ISAR registers, but we can still
748
+ * set the field to indicate Jazelle support within QEMU.
749
+ */
750
+ cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
751
+ /*
752
+ * Similarly, we need to set MVFR0 fields to enable vfp and short vector
753
+ * support even though ARMv5 doesn't have this register.
754
+ */
755
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
756
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
757
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
758
+}
759
+
760
+static void arm946_initfn(Object *obj)
761
+{
762
+ ARMCPU *cpu = ARM_CPU(obj);
763
+
764
+ cpu->dtb_compatible = "arm,arm946";
765
+ set_feature(&cpu->env, ARM_FEATURE_V5);
766
+ set_feature(&cpu->env, ARM_FEATURE_PMSA);
767
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
768
+ cpu->midr = 0x41059461;
769
+ cpu->ctr = 0x0f004006;
770
+ cpu->reset_sctlr = 0x00000078;
771
+}
772
+
773
+static void arm1026_initfn(Object *obj)
774
+{
775
+ ARMCPU *cpu = ARM_CPU(obj);
776
+
777
+ cpu->dtb_compatible = "arm,arm1026";
778
+ set_feature(&cpu->env, ARM_FEATURE_V5);
779
+ set_feature(&cpu->env, ARM_FEATURE_AUXCR);
780
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
781
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
782
+ cpu->midr = 0x4106a262;
783
+ cpu->reset_fpsid = 0x410110a0;
784
+ cpu->ctr = 0x1dd20d2;
785
+ cpu->reset_sctlr = 0x00090078;
786
+ cpu->reset_auxcr = 1;
787
+
788
+ /*
789
+ * ARMv5 does not have the ID_ISAR registers, but we can still
790
+ * set the field to indicate Jazelle support within QEMU.
791
+ */
792
+ cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
793
+ /*
794
+ * Similarly, we need to set MVFR0 fields to enable vfp and short vector
795
+ * support even though ARMv5 doesn't have this register.
796
+ */
797
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
798
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
799
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
800
+
801
+ {
802
+ /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
803
+ ARMCPRegInfo ifar = {
804
+ .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
805
+ .access = PL1_RW,
806
+ .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
807
+ .resetvalue = 0
808
+ };
809
+ define_one_arm_cp_reg(cpu, &ifar);
810
+ }
811
+}
812
+
813
+static void arm1136_r2_initfn(Object *obj)
814
+{
815
+ ARMCPU *cpu = ARM_CPU(obj);
816
+ /*
817
+ * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
818
+ * older core than plain "arm1136". In particular this does not
819
+ * have the v6K features.
820
+ * These ID register values are correct for 1136 but may be wrong
821
+ * for 1136_r2 (in particular r0p2 does not actually implement most
822
+ * of the ID registers).
823
+ */
824
+
825
+ cpu->dtb_compatible = "arm,arm1136";
826
+ set_feature(&cpu->env, ARM_FEATURE_V6);
827
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
828
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
829
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
830
+ cpu->midr = 0x4107b362;
831
+ cpu->reset_fpsid = 0x410120b4;
832
+ cpu->isar.mvfr0 = 0x11111111;
833
+ cpu->isar.mvfr1 = 0x00000000;
834
+ cpu->ctr = 0x1dd20d2;
835
+ cpu->reset_sctlr = 0x00050078;
836
+ cpu->id_pfr0 = 0x111;
837
+ cpu->id_pfr1 = 0x1;
838
+ cpu->isar.id_dfr0 = 0x2;
839
+ cpu->id_afr0 = 0x3;
840
+ cpu->isar.id_mmfr0 = 0x01130003;
841
+ cpu->isar.id_mmfr1 = 0x10030302;
842
+ cpu->isar.id_mmfr2 = 0x01222110;
843
+ cpu->isar.id_isar0 = 0x00140011;
844
+ cpu->isar.id_isar1 = 0x12002111;
845
+ cpu->isar.id_isar2 = 0x11231111;
846
+ cpu->isar.id_isar3 = 0x01102131;
847
+ cpu->isar.id_isar4 = 0x141;
848
+ cpu->reset_auxcr = 7;
849
+}
850
+
851
+static void arm1136_initfn(Object *obj)
852
+{
853
+ ARMCPU *cpu = ARM_CPU(obj);
854
+
855
+ cpu->dtb_compatible = "arm,arm1136";
856
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
857
+ set_feature(&cpu->env, ARM_FEATURE_V6);
858
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
859
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
860
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
861
+ cpu->midr = 0x4117b363;
862
+ cpu->reset_fpsid = 0x410120b4;
863
+ cpu->isar.mvfr0 = 0x11111111;
864
+ cpu->isar.mvfr1 = 0x00000000;
865
+ cpu->ctr = 0x1dd20d2;
866
+ cpu->reset_sctlr = 0x00050078;
867
+ cpu->id_pfr0 = 0x111;
868
+ cpu->id_pfr1 = 0x1;
869
+ cpu->isar.id_dfr0 = 0x2;
870
+ cpu->id_afr0 = 0x3;
871
+ cpu->isar.id_mmfr0 = 0x01130003;
872
+ cpu->isar.id_mmfr1 = 0x10030302;
873
+ cpu->isar.id_mmfr2 = 0x01222110;
874
+ cpu->isar.id_isar0 = 0x00140011;
875
+ cpu->isar.id_isar1 = 0x12002111;
876
+ cpu->isar.id_isar2 = 0x11231111;
877
+ cpu->isar.id_isar3 = 0x01102131;
878
+ cpu->isar.id_isar4 = 0x141;
879
+ cpu->reset_auxcr = 7;
880
+}
881
+
882
+static void arm1176_initfn(Object *obj)
883
+{
884
+ ARMCPU *cpu = ARM_CPU(obj);
885
+
886
+ cpu->dtb_compatible = "arm,arm1176";
887
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
888
+ set_feature(&cpu->env, ARM_FEATURE_VAPA);
889
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
890
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
891
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
892
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
893
+ cpu->midr = 0x410fb767;
894
+ cpu->reset_fpsid = 0x410120b5;
895
+ cpu->isar.mvfr0 = 0x11111111;
896
+ cpu->isar.mvfr1 = 0x00000000;
897
+ cpu->ctr = 0x1dd20d2;
898
+ cpu->reset_sctlr = 0x00050078;
899
+ cpu->id_pfr0 = 0x111;
900
+ cpu->id_pfr1 = 0x11;
901
+ cpu->isar.id_dfr0 = 0x33;
902
+ cpu->id_afr0 = 0;
903
+ cpu->isar.id_mmfr0 = 0x01130003;
904
+ cpu->isar.id_mmfr1 = 0x10030302;
905
+ cpu->isar.id_mmfr2 = 0x01222100;
906
+ cpu->isar.id_isar0 = 0x0140011;
907
+ cpu->isar.id_isar1 = 0x12002111;
908
+ cpu->isar.id_isar2 = 0x11231121;
909
+ cpu->isar.id_isar3 = 0x01102131;
910
+ cpu->isar.id_isar4 = 0x01141;
911
+ cpu->reset_auxcr = 7;
912
+}
913
+
914
+static void arm11mpcore_initfn(Object *obj)
915
+{
916
+ ARMCPU *cpu = ARM_CPU(obj);
917
+
918
+ cpu->dtb_compatible = "arm,arm11mpcore";
919
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
920
+ set_feature(&cpu->env, ARM_FEATURE_VAPA);
921
+ set_feature(&cpu->env, ARM_FEATURE_MPIDR);
922
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
923
+ cpu->midr = 0x410fb022;
924
+ cpu->reset_fpsid = 0x410120b4;
925
+ cpu->isar.mvfr0 = 0x11111111;
926
+ cpu->isar.mvfr1 = 0x00000000;
927
+ cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
928
+ cpu->id_pfr0 = 0x111;
929
+ cpu->id_pfr1 = 0x1;
930
+ cpu->isar.id_dfr0 = 0;
931
+ cpu->id_afr0 = 0x2;
932
+ cpu->isar.id_mmfr0 = 0x01100103;
933
+ cpu->isar.id_mmfr1 = 0x10020302;
934
+ cpu->isar.id_mmfr2 = 0x01222000;
935
+ cpu->isar.id_isar0 = 0x00100011;
936
+ cpu->isar.id_isar1 = 0x12002111;
937
+ cpu->isar.id_isar2 = 0x11221011;
938
+ cpu->isar.id_isar3 = 0x01102131;
939
+ cpu->isar.id_isar4 = 0x141;
940
+ cpu->reset_auxcr = 1;
941
+}
942
+
943
+static void cortex_m0_initfn(Object *obj)
944
+{
945
+ ARMCPU *cpu = ARM_CPU(obj);
946
+ set_feature(&cpu->env, ARM_FEATURE_V6);
947
+ set_feature(&cpu->env, ARM_FEATURE_M);
948
+
949
+ cpu->midr = 0x410cc200;
950
+}
951
+
952
+static void cortex_m3_initfn(Object *obj)
953
+{
954
+ ARMCPU *cpu = ARM_CPU(obj);
955
+ set_feature(&cpu->env, ARM_FEATURE_V7);
956
+ set_feature(&cpu->env, ARM_FEATURE_M);
957
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
958
+ cpu->midr = 0x410fc231;
959
+ cpu->pmsav7_dregion = 8;
960
+ cpu->id_pfr0 = 0x00000030;
961
+ cpu->id_pfr1 = 0x00000200;
962
+ cpu->isar.id_dfr0 = 0x00100000;
963
+ cpu->id_afr0 = 0x00000000;
964
+ cpu->isar.id_mmfr0 = 0x00000030;
965
+ cpu->isar.id_mmfr1 = 0x00000000;
966
+ cpu->isar.id_mmfr2 = 0x00000000;
967
+ cpu->isar.id_mmfr3 = 0x00000000;
968
+ cpu->isar.id_isar0 = 0x01141110;
969
+ cpu->isar.id_isar1 = 0x02111000;
970
+ cpu->isar.id_isar2 = 0x21112231;
971
+ cpu->isar.id_isar3 = 0x01111110;
972
+ cpu->isar.id_isar4 = 0x01310102;
973
+ cpu->isar.id_isar5 = 0x00000000;
974
+ cpu->isar.id_isar6 = 0x00000000;
975
+}
976
+
977
+static void cortex_m4_initfn(Object *obj)
978
+{
979
+ ARMCPU *cpu = ARM_CPU(obj);
980
+
981
+ set_feature(&cpu->env, ARM_FEATURE_V7);
982
+ set_feature(&cpu->env, ARM_FEATURE_M);
983
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
984
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
985
+ cpu->midr = 0x410fc240; /* r0p0 */
986
+ cpu->pmsav7_dregion = 8;
987
+ cpu->isar.mvfr0 = 0x10110021;
988
+ cpu->isar.mvfr1 = 0x11000011;
989
+ cpu->isar.mvfr2 = 0x00000000;
990
+ cpu->id_pfr0 = 0x00000030;
991
+ cpu->id_pfr1 = 0x00000200;
992
+ cpu->isar.id_dfr0 = 0x00100000;
993
+ cpu->id_afr0 = 0x00000000;
994
+ cpu->isar.id_mmfr0 = 0x00000030;
995
+ cpu->isar.id_mmfr1 = 0x00000000;
996
+ cpu->isar.id_mmfr2 = 0x00000000;
997
+ cpu->isar.id_mmfr3 = 0x00000000;
998
+ cpu->isar.id_isar0 = 0x01141110;
999
+ cpu->isar.id_isar1 = 0x02111000;
1000
+ cpu->isar.id_isar2 = 0x21112231;
1001
+ cpu->isar.id_isar3 = 0x01111110;
1002
+ cpu->isar.id_isar4 = 0x01310102;
1003
+ cpu->isar.id_isar5 = 0x00000000;
1004
+ cpu->isar.id_isar6 = 0x00000000;
1005
+}
1006
+
1007
+static void cortex_m7_initfn(Object *obj)
1008
+{
1009
+ ARMCPU *cpu = ARM_CPU(obj);
1010
+
1011
+ set_feature(&cpu->env, ARM_FEATURE_V7);
1012
+ set_feature(&cpu->env, ARM_FEATURE_M);
1013
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1014
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1015
+ cpu->midr = 0x411fc272; /* r1p2 */
1016
+ cpu->pmsav7_dregion = 8;
1017
+ cpu->isar.mvfr0 = 0x10110221;
1018
+ cpu->isar.mvfr1 = 0x12000011;
1019
+ cpu->isar.mvfr2 = 0x00000040;
1020
+ cpu->id_pfr0 = 0x00000030;
1021
+ cpu->id_pfr1 = 0x00000200;
1022
+ cpu->isar.id_dfr0 = 0x00100000;
1023
+ cpu->id_afr0 = 0x00000000;
1024
+ cpu->isar.id_mmfr0 = 0x00100030;
1025
+ cpu->isar.id_mmfr1 = 0x00000000;
1026
+ cpu->isar.id_mmfr2 = 0x01000000;
1027
+ cpu->isar.id_mmfr3 = 0x00000000;
1028
+ cpu->isar.id_isar0 = 0x01101110;
1029
+ cpu->isar.id_isar1 = 0x02112000;
1030
+ cpu->isar.id_isar2 = 0x20232231;
1031
+ cpu->isar.id_isar3 = 0x01111131;
1032
+ cpu->isar.id_isar4 = 0x01310132;
1033
+ cpu->isar.id_isar5 = 0x00000000;
1034
+ cpu->isar.id_isar6 = 0x00000000;
1035
+}
1036
+
1037
+static void cortex_m33_initfn(Object *obj)
1038
+{
22
+{
1039
+ ARMCPU *cpu = ARM_CPU(obj);
23
+ ARMCPU *cpu = ARM_CPU(obj);
1040
+
24
+
1041
+ set_feature(&cpu->env, ARM_FEATURE_V8);
25
+ set_feature(&cpu->env, ARM_FEATURE_V8);
1042
+ set_feature(&cpu->env, ARM_FEATURE_M);
26
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
1043
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
27
+ set_feature(&cpu->env, ARM_FEATURE_PMSA);
1044
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
28
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
1045
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
29
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1046
+ cpu->midr = 0x410fd213; /* r0p3 */
30
+ cpu->midr = 0x411fd133; /* r1p3 */
31
+ cpu->revidr = 0x00000000;
32
+ cpu->reset_fpsid = 0x41034023;
33
+ cpu->isar.mvfr0 = 0x10110222;
34
+ cpu->isar.mvfr1 = 0x12111111;
35
+ cpu->isar.mvfr2 = 0x00000043;
36
+ cpu->ctr = 0x8144c004;
37
+ cpu->reset_sctlr = 0x30c50838;
38
+ cpu->isar.id_pfr0 = 0x00000131;
39
+ cpu->isar.id_pfr1 = 0x10111001;
40
+ cpu->isar.id_dfr0 = 0x03010006;
41
+ cpu->id_afr0 = 0x00000000;
42
+ cpu->isar.id_mmfr0 = 0x00211040;
43
+ cpu->isar.id_mmfr1 = 0x40000000;
44
+ cpu->isar.id_mmfr2 = 0x01200000;
45
+ cpu->isar.id_mmfr3 = 0xf0102211;
46
+ cpu->isar.id_mmfr4 = 0x00000010;
47
+ cpu->isar.id_isar0 = 0x02101110;
48
+ cpu->isar.id_isar1 = 0x13112111;
49
+ cpu->isar.id_isar2 = 0x21232142;
50
+ cpu->isar.id_isar3 = 0x01112131;
51
+ cpu->isar.id_isar4 = 0x00010142;
52
+ cpu->isar.id_isar5 = 0x00010001;
53
+ cpu->isar.dbgdidr = 0x77168000;
54
+ cpu->clidr = (1 << 27) | (1 << 24) | 0x3;
55
+ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
56
+ cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
57
+
1047
+ cpu->pmsav7_dregion = 16;
58
+ cpu->pmsav7_dregion = 16;
1048
+ cpu->sau_sregion = 8;
59
+ cpu->pmsav8r_hdregion = 16;
1049
+ cpu->isar.mvfr0 = 0x10110021;
1050
+ cpu->isar.mvfr1 = 0x11000011;
1051
+ cpu->isar.mvfr2 = 0x00000040;
1052
+ cpu->id_pfr0 = 0x00000030;
1053
+ cpu->id_pfr1 = 0x00000210;
1054
+ cpu->isar.id_dfr0 = 0x00200000;
1055
+ cpu->id_afr0 = 0x00000000;
1056
+ cpu->isar.id_mmfr0 = 0x00101F40;
1057
+ cpu->isar.id_mmfr1 = 0x00000000;
1058
+ cpu->isar.id_mmfr2 = 0x01000000;
1059
+ cpu->isar.id_mmfr3 = 0x00000000;
1060
+ cpu->isar.id_isar0 = 0x01101110;
1061
+ cpu->isar.id_isar1 = 0x02212000;
1062
+ cpu->isar.id_isar2 = 0x20232232;
1063
+ cpu->isar.id_isar3 = 0x01111131;
1064
+ cpu->isar.id_isar4 = 0x01310132;
1065
+ cpu->isar.id_isar5 = 0x00000000;
1066
+ cpu->isar.id_isar6 = 0x00000000;
1067
+ cpu->clidr = 0x00000000;
1068
+ cpu->ctr = 0x8000c000;
1069
+}
60
+}
1070
+
61
+
1071
+static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
62
static void cortex_r5f_initfn(Object *obj)
1072
+ /* Dummy the TCM region regs for the moment */
63
{
1073
+ { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
64
ARMCPU *cpu = ARM_CPU(obj);
1074
+ .access = PL1_RW, .type = ARM_CP_CONST },
65
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = {
1075
+ { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
66
.class_init = arm_v7m_class_init },
1076
+ .access = PL1_RW, .type = ARM_CP_CONST },
67
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
1077
+ { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
68
{ .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
1078
+ .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
69
+ { .name = "cortex-r52", .initfn = cortex_r52_initfn },
1079
+ REGINFO_SENTINEL
70
{ .name = "ti925t", .initfn = ti925t_initfn },
1080
+};
71
{ .name = "sa1100", .initfn = sa1100_initfn },
1081
+
72
{ .name = "sa1110", .initfn = sa1110_initfn },
1082
+static void cortex_r5_initfn(Object *obj)
1083
+{
1084
+ ARMCPU *cpu = ARM_CPU(obj);
1085
+
1086
+ set_feature(&cpu->env, ARM_FEATURE_V7);
1087
+ set_feature(&cpu->env, ARM_FEATURE_V7MP);
1088
+ set_feature(&cpu->env, ARM_FEATURE_PMSA);
1089
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
1090
+ cpu->midr = 0x411fc153; /* r1p3 */
1091
+ cpu->id_pfr0 = 0x0131;
1092
+ cpu->id_pfr1 = 0x001;
1093
+ cpu->isar.id_dfr0 = 0x010400;
1094
+ cpu->id_afr0 = 0x0;
1095
+ cpu->isar.id_mmfr0 = 0x0210030;
1096
+ cpu->isar.id_mmfr1 = 0x00000000;
1097
+ cpu->isar.id_mmfr2 = 0x01200000;
1098
+ cpu->isar.id_mmfr3 = 0x0211;
1099
+ cpu->isar.id_isar0 = 0x02101111;
1100
+ cpu->isar.id_isar1 = 0x13112111;
1101
+ cpu->isar.id_isar2 = 0x21232141;
1102
+ cpu->isar.id_isar3 = 0x01112131;
1103
+ cpu->isar.id_isar4 = 0x0010142;
1104
+ cpu->isar.id_isar5 = 0x0;
1105
+ cpu->isar.id_isar6 = 0x0;
1106
+ cpu->mp_is_up = true;
1107
+ cpu->pmsav7_dregion = 16;
1108
+ define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
1109
+}
1110
+
1111
+static void cortex_r5f_initfn(Object *obj)
1112
+{
1113
+ ARMCPU *cpu = ARM_CPU(obj);
1114
+
1115
+ cortex_r5_initfn(obj);
1116
+ cpu->isar.mvfr0 = 0x10110221;
1117
+ cpu->isar.mvfr1 = 0x00000011;
1118
+}
1119
+
1120
+static void ti925t_initfn(Object *obj)
1121
+{
1122
+ ARMCPU *cpu = ARM_CPU(obj);
1123
+ set_feature(&cpu->env, ARM_FEATURE_V4T);
1124
+ set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1125
+ cpu->midr = ARM_CPUID_TI925T;
1126
+ cpu->ctr = 0x5109149;
1127
+ cpu->reset_sctlr = 0x00000070;
1128
+}
1129
+
1130
+static void sa1100_initfn(Object *obj)
1131
+{
1132
+ ARMCPU *cpu = ARM_CPU(obj);
1133
+
1134
+ cpu->dtb_compatible = "intel,sa1100";
1135
+ set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1136
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1137
+ cpu->midr = 0x4401A11B;
1138
+ cpu->reset_sctlr = 0x00000070;
1139
+}
1140
+
1141
+static void sa1110_initfn(Object *obj)
1142
+{
1143
+ ARMCPU *cpu = ARM_CPU(obj);
1144
+ set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1145
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1146
+ cpu->midr = 0x6901B119;
1147
+ cpu->reset_sctlr = 0x00000070;
1148
+}
1149
+
1150
+static void pxa250_initfn(Object *obj)
1151
+{
1152
+ ARMCPU *cpu = ARM_CPU(obj);
1153
+
1154
+ cpu->dtb_compatible = "marvell,xscale";
1155
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1156
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1157
+ cpu->midr = 0x69052100;
1158
+ cpu->ctr = 0xd172172;
1159
+ cpu->reset_sctlr = 0x00000078;
1160
+}
1161
+
1162
+static void pxa255_initfn(Object *obj)
1163
+{
1164
+ ARMCPU *cpu = ARM_CPU(obj);
1165
+
1166
+ cpu->dtb_compatible = "marvell,xscale";
1167
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1168
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1169
+ cpu->midr = 0x69052d00;
1170
+ cpu->ctr = 0xd172172;
1171
+ cpu->reset_sctlr = 0x00000078;
1172
+}
1173
+
1174
+static void pxa260_initfn(Object *obj)
1175
+{
1176
+ ARMCPU *cpu = ARM_CPU(obj);
1177
+
1178
+ cpu->dtb_compatible = "marvell,xscale";
1179
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1180
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1181
+ cpu->midr = 0x69052903;
1182
+ cpu->ctr = 0xd172172;
1183
+ cpu->reset_sctlr = 0x00000078;
1184
+}
1185
+
1186
+static void pxa261_initfn(Object *obj)
1187
+{
1188
+ ARMCPU *cpu = ARM_CPU(obj);
1189
+
1190
+ cpu->dtb_compatible = "marvell,xscale";
1191
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1192
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1193
+ cpu->midr = 0x69052d05;
1194
+ cpu->ctr = 0xd172172;
1195
+ cpu->reset_sctlr = 0x00000078;
1196
+}
1197
+
1198
+static void pxa262_initfn(Object *obj)
1199
+{
1200
+ ARMCPU *cpu = ARM_CPU(obj);
1201
+
1202
+ cpu->dtb_compatible = "marvell,xscale";
1203
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1204
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1205
+ cpu->midr = 0x69052d06;
1206
+ cpu->ctr = 0xd172172;
1207
+ cpu->reset_sctlr = 0x00000078;
1208
+}
1209
+
1210
+static void pxa270a0_initfn(Object *obj)
1211
+{
1212
+ ARMCPU *cpu = ARM_CPU(obj);
1213
+
1214
+ cpu->dtb_compatible = "marvell,xscale";
1215
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1216
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1217
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1218
+ cpu->midr = 0x69054110;
1219
+ cpu->ctr = 0xd172172;
1220
+ cpu->reset_sctlr = 0x00000078;
1221
+}
1222
+
1223
+static void pxa270a1_initfn(Object *obj)
1224
+{
1225
+ ARMCPU *cpu = ARM_CPU(obj);
1226
+
1227
+ cpu->dtb_compatible = "marvell,xscale";
1228
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1229
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1230
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1231
+ cpu->midr = 0x69054111;
1232
+ cpu->ctr = 0xd172172;
1233
+ cpu->reset_sctlr = 0x00000078;
1234
+}
1235
+
1236
+static void pxa270b0_initfn(Object *obj)
1237
+{
1238
+ ARMCPU *cpu = ARM_CPU(obj);
1239
+
1240
+ cpu->dtb_compatible = "marvell,xscale";
1241
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1242
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1243
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1244
+ cpu->midr = 0x69054112;
1245
+ cpu->ctr = 0xd172172;
1246
+ cpu->reset_sctlr = 0x00000078;
1247
+}
1248
+
1249
+static void pxa270b1_initfn(Object *obj)
1250
+{
1251
+ ARMCPU *cpu = ARM_CPU(obj);
1252
+
1253
+ cpu->dtb_compatible = "marvell,xscale";
1254
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1255
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1256
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1257
+ cpu->midr = 0x69054113;
1258
+ cpu->ctr = 0xd172172;
1259
+ cpu->reset_sctlr = 0x00000078;
1260
+}
1261
+
1262
+static void pxa270c0_initfn(Object *obj)
1263
+{
1264
+ ARMCPU *cpu = ARM_CPU(obj);
1265
+
1266
+ cpu->dtb_compatible = "marvell,xscale";
1267
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1268
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1269
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1270
+ cpu->midr = 0x69054114;
1271
+ cpu->ctr = 0xd172172;
1272
+ cpu->reset_sctlr = 0x00000078;
1273
+}
1274
+
1275
+static void pxa270c5_initfn(Object *obj)
1276
+{
1277
+ ARMCPU *cpu = ARM_CPU(obj);
1278
+
1279
+ cpu->dtb_compatible = "marvell,xscale";
1280
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1281
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1282
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1283
+ cpu->midr = 0x69054117;
1284
+ cpu->ctr = 0xd172172;
1285
+ cpu->reset_sctlr = 0x00000078;
1286
+}
1287
+
1288
+static void arm_v7m_class_init(ObjectClass *oc, void *data)
1289
+{
1290
+ ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1291
+ CPUClass *cc = CPU_CLASS(oc);
1292
+
1293
+ acc->info = data;
1294
+#ifndef CONFIG_USER_ONLY
1295
+ cc->do_interrupt = arm_v7m_cpu_do_interrupt;
1296
+#endif
1297
+
1298
+ cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
1299
+}
1300
+
1301
+static const ARMCPUInfo arm_tcg_cpus[] = {
1302
+ { .name = "arm926", .initfn = arm926_initfn },
1303
+ { .name = "arm946", .initfn = arm946_initfn },
1304
+ { .name = "arm1026", .initfn = arm1026_initfn },
1305
+ /*
1306
+ * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1307
+ * older core than plain "arm1136". In particular this does not
1308
+ * have the v6K features.
1309
+ */
1310
+ { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1311
+ { .name = "arm1136", .initfn = arm1136_initfn },
1312
+ { .name = "arm1176", .initfn = arm1176_initfn },
1313
+ { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1314
+ { .name = "cortex-m0", .initfn = cortex_m0_initfn,
1315
+ .class_init = arm_v7m_class_init },
1316
+ { .name = "cortex-m3", .initfn = cortex_m3_initfn,
1317
+ .class_init = arm_v7m_class_init },
1318
+ { .name = "cortex-m4", .initfn = cortex_m4_initfn,
1319
+ .class_init = arm_v7m_class_init },
1320
+ { .name = "cortex-m7", .initfn = cortex_m7_initfn,
1321
+ .class_init = arm_v7m_class_init },
1322
+ { .name = "cortex-m33", .initfn = cortex_m33_initfn,
1323
+ .class_init = arm_v7m_class_init },
1324
+ { .name = "cortex-r5", .initfn = cortex_r5_initfn },
1325
+ { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
1326
+ { .name = "ti925t", .initfn = ti925t_initfn },
1327
+ { .name = "sa1100", .initfn = sa1100_initfn },
1328
+ { .name = "sa1110", .initfn = sa1110_initfn },
1329
+ { .name = "pxa250", .initfn = pxa250_initfn },
1330
+ { .name = "pxa255", .initfn = pxa255_initfn },
1331
+ { .name = "pxa260", .initfn = pxa260_initfn },
1332
+ { .name = "pxa261", .initfn = pxa261_initfn },
1333
+ { .name = "pxa262", .initfn = pxa262_initfn },
1334
+ /* "pxa270" is an alias for "pxa270-a0" */
1335
+ { .name = "pxa270", .initfn = pxa270a0_initfn },
1336
+ { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1337
+ { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1338
+ { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1339
+ { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1340
+ { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1341
+ { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
1342
+};
1343
+
1344
+static void arm_tcg_cpu_register_types(void)
1345
+{
1346
+ size_t i;
1347
+
1348
+ for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
1349
+ arm_cpu_register(&arm_tcg_cpus[i]);
1350
+ }
1351
+}
1352
+
1353
+type_init(arm_tcg_cpu_register_types)
1354
+
1355
+#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
1356
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
1357
index XXXXXXX..XXXXXXX 100644
1358
--- a/target/arm/Makefile.objs
1359
+++ b/target/arm/Makefile.objs
1360
@@ -XXX,XX +XXX,XX @@ obj-y += translate.o op_helper.o
1361
obj-y += crypto_helper.o
1362
obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
1363
obj-y += m_helper.o
1364
+obj-y += cpu_tcg.o
1365
1366
obj-$(CONFIG_SOFTMMU) += psci.o
1367
1368
--
73
--
1369
2.20.1
74
2.25.1
1370
75
1371
76
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
The only caller of cpu_watchpoint_address_matches passes
3
The check semihosting_enabled() wants to know if the guest is
4
TARGET_PAGE_SIZE, so the bug is not currently visible.
4
currently in user mode. Unlike the other cases the test was inverted
5
causing us to block semihosting calls in non-EL0 modes.
5
6
7
Cc: qemu-stable@nongnu.org
8
Fixes: 19b26317e9 (target/arm: Honour -semihosting-config userspace=on)
9
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20200508154359.7494-3-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
---
12
exec.c | 2 +-
13
target/arm/translate.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
15
diff --git a/exec.c b/exec.c
16
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/exec.c
18
--- a/target/arm/translate.c
18
+++ b/exec.c
19
+++ b/target/arm/translate.c
19
@@ -XXX,XX +XXX,XX @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
20
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
20
int ret = 0;
21
* semihosting, to provide some semblance of security
21
22
* (and for consistency with our 32-bit semihosting).
22
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
23
*/
23
- if (watchpoint_address_matches(wp, addr, TARGET_PAGE_SIZE)) {
24
- if (semihosting_enabled(s->current_el != 0) &&
24
+ if (watchpoint_address_matches(wp, addr, len)) {
25
+ if (semihosting_enabled(s->current_el == 0) &&
25
ret |= wp->flags;
26
(imm == (s->thumb ? 0x3c : 0xf000))) {
26
}
27
gen_exception_internal_insn(s, EXCP_SEMIHOST);
27
}
28
return;
28
--
29
--
29
2.20.1
30
2.25.1
30
31
31
32
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
2
3
We want to move the inlined declarations of set_feature()
3
Fix typos, add background information
4
from cpu*.c to cpu.h. To avoid clashing with the KVM
5
declarations, inline the few KVM calls.
6
4
7
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20200504172448.9402-2-philmd@redhat.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
8
---
12
target/arm/kvm32.c | 13 ++++---------
9
hw/timer/imx_epit.c | 20 ++++++++++++++++----
13
target/arm/kvm64.c | 22 ++++++----------------
10
1 file changed, 16 insertions(+), 4 deletions(-)
14
2 files changed, 10 insertions(+), 25 deletions(-)
15
11
16
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
12
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/kvm32.c
14
--- a/hw/timer/imx_epit.c
19
+++ b/target/arm/kvm32.c
15
+++ b/hw/timer/imx_epit.c
20
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ static void imx_epit_set_freq(IMXEPITState *s)
21
#include "internals.h"
22
#include "qemu/log.h"
23
24
-static inline void set_feature(uint64_t *features, int feature)
25
-{
26
- *features |= 1ULL << feature;
27
-}
28
-
29
static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
30
{
31
struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
32
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
33
* timers; this in turn implies most of the other feature
34
* bits, but a few must be tested.
35
*/
36
- set_feature(&features, ARM_FEATURE_V7VE);
37
- set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
38
+ features |= 1ULL << ARM_FEATURE_V7VE;
39
+ features |= 1ULL << ARM_FEATURE_GENERIC_TIMER;
40
41
if (extract32(id_pfr0, 12, 4) == 1) {
42
- set_feature(&features, ARM_FEATURE_THUMB2EE);
43
+ features |= 1ULL << ARM_FEATURE_THUMB2EE;
44
}
45
if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
46
- set_feature(&features, ARM_FEATURE_NEON);
47
+ features |= 1ULL << ARM_FEATURE_NEON;
48
}
49
50
ahcf->features = features;
51
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/kvm64.c
54
+++ b/target/arm/kvm64.c
55
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
56
}
17
}
57
}
18
}
58
19
59
-static inline void set_feature(uint64_t *features, int feature)
20
+/*
60
-{
21
+ * This is called both on hardware (device) reset and software reset.
61
- *features |= 1ULL << feature;
22
+ */
62
-}
23
static void imx_epit_reset(DeviceState *dev)
63
-
64
-static inline void unset_feature(uint64_t *features, int feature)
65
-{
66
- *features &= ~(1ULL << feature);
67
-}
68
-
69
static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
70
{
24
{
71
uint64_t ret;
25
IMXEPITState *s = IMX_EPIT(dev);
72
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
26
73
* with VFPv4+Neon; this in turn implies most of the other
27
- /*
74
* feature bits.
28
- * Soft reset doesn't touch some bits; hard reset clears them
75
*/
29
- */
76
- set_feature(&features, ARM_FEATURE_V8);
30
+ /* Soft reset doesn't touch some bits; hard reset clears them */
77
- set_feature(&features, ARM_FEATURE_NEON);
31
s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
78
- set_feature(&features, ARM_FEATURE_AARCH64);
32
s->sr = 0;
79
- set_feature(&features, ARM_FEATURE_PMU);
33
s->lr = EPIT_TIMER_MAX;
80
- set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
34
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
81
+ features |= 1ULL << ARM_FEATURE_V8;
35
ptimer_transaction_begin(s->timer_cmp);
82
+ features |= 1ULL << ARM_FEATURE_NEON;
36
ptimer_transaction_begin(s->timer_reload);
83
+ features |= 1ULL << ARM_FEATURE_AARCH64;
37
84
+ features |= 1ULL << ARM_FEATURE_PMU;
38
+ /* Update the frequency. Has been done already in case of a reset. */
85
+ features |= 1ULL << ARM_FEATURE_GENERIC_TIMER;
39
if (!(s->cr & CR_SWR)) {
86
40
imx_epit_set_freq(s);
87
ahcf->features = features;
41
}
88
42
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
89
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
43
break;
90
if (cpu->has_pmu) {
44
91
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
45
case 1: /* SR - ACK*/
92
} else {
46
- /* writing 1 to OCIF clear the OCIF bit */
93
- unset_feature(&env->features, ARM_FEATURE_PMU);
47
+ /* writing 1 to OCIF clears the OCIF bit */
94
+ env->features &= ~(1ULL << ARM_FEATURE_PMU);
48
if (value & 0x01) {
95
}
49
s->sr = 0;
96
if (cpu_isar_feature(aa64_sve, cpu)) {
50
imx_epit_update_int(s);
97
assert(kvm_arm_sve_supported(cs));
51
@@ -XXX,XX +XXX,XX @@ static void imx_epit_realize(DeviceState *dev, Error **errp)
52
0x00001000);
53
sysbus_init_mmio(sbd, &s->iomem);
54
55
+ /*
56
+ * The reload timer keeps running when the peripheral is enabled. It is a
57
+ * kind of wall clock that does not generate any interrupts. The callback
58
+ * needs to be provided, but it does nothing as the ptimer already supports
59
+ * all necessary reloading functionality.
60
+ */
61
s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_LEGACY);
62
63
+ /*
64
+ * The compare timer is running only when the peripheral configuration is
65
+ * in a state that will generate compare interrupts.
66
+ */
67
s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY);
68
}
69
98
--
70
--
99
2.20.1
71
2.25.1
100
101
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
2
3
remove unused defines, add needed defines
4
5
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200508154359.7494-18-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
---
8
target/arm/sve_helper.c | 182 ++++++++++++++++++++++++----------------
9
include/hw/timer/imx_epit.h | 4 ++--
9
1 file changed, 111 insertions(+), 71 deletions(-)
10
hw/timer/imx_epit.c | 4 ++--
11
2 files changed, 4 insertions(+), 4 deletions(-)
10
12
11
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
13
diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h
12
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/sve_helper.c
15
--- a/include/hw/timer/imx_epit.h
14
+++ b/target/arm/sve_helper.c
16
+++ b/include/hw/timer/imx_epit.h
15
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_ZPZ_D(dd_be, zd, MO_64)
17
@@ -XXX,XX +XXX,XX @@
16
18
#define CR_OCIEN (1 << 2)
17
/* Stores with a vector index. */
19
#define CR_RLD (1 << 3)
18
20
#define CR_PRESCALE_SHIFT (4)
19
-static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
21
-#define CR_PRESCALE_MASK (0xfff)
20
- target_ulong base, uint32_t desc, uintptr_t ra,
22
+#define CR_PRESCALE_BITS (12)
21
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
23
#define CR_SWR (1 << 16)
22
+static inline QEMU_ALWAYS_INLINE
24
#define CR_IOVW (1 << 17)
23
+void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
25
#define CR_DBGEN (1 << 18)
24
+ target_ulong base, uint32_t desc, uintptr_t retaddr,
26
@@ -XXX,XX +XXX,XX @@
25
+ int esize, int msize, zreg_off_fn *off_fn,
27
#define CR_DOZEN (1 << 20)
26
+ sve_ldst1_host_fn *host_fn,
28
#define CR_STOPEN (1 << 21)
27
+ sve_ldst1_tlb_fn *tlb_fn)
29
#define CR_CLKSRC_SHIFT (24)
28
{
30
-#define CR_CLKSRC_MASK (0x3 << CR_CLKSRC_SHIFT)
29
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
31
+#define CR_CLKSRC_BITS (2)
30
- intptr_t i, oprsz = simd_oprsz(desc);
32
31
+ const int mmu_idx = cpu_mmu_index(env, false);
33
#define EPIT_TIMER_MAX 0XFFFFFFFFUL
32
+ const intptr_t reg_max = simd_oprsz(desc);
34
33
+ void *host[ARM_MAX_VQ * 4];
35
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
34
+ intptr_t reg_off, i;
36
index XXXXXXX..XXXXXXX 100644
35
+ SVEHostPage info, info2;
37
--- a/hw/timer/imx_epit.c
36
38
+++ b/hw/timer/imx_epit.c
37
- for (i = 0; i < oprsz; ) {
39
@@ -XXX,XX +XXX,XX @@ static void imx_epit_set_freq(IMXEPITState *s)
38
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
40
uint32_t clksrc;
39
+ /*
41
uint32_t prescaler;
40
+ * Probe all of the elements for host addresses and flags.
42
41
+ */
43
- clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, 2);
42
+ i = reg_off = 0;
44
- prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, 12);
43
+ do {
45
+ clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS);
44
+ uint64_t pg = vg[reg_off >> 6];
46
+ prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS);
45
do {
47
46
- if (likely(pg & 1)) {
48
s->freq = imx_ccm_get_clock_frequency(s->ccm,
47
- target_ulong off = off_fn(vm, i);
49
imx_epit_clocks[clksrc]) / prescaler;
48
- tlb_fn(env, vd, i, base + (off << scale), ra);
49
+ target_ulong addr = base + (off_fn(vm, reg_off) << scale);
50
+ target_ulong in_page = -(addr | TARGET_PAGE_MASK);
51
+
52
+ host[i] = NULL;
53
+ if (likely((pg >> (reg_off & 63)) & 1)) {
54
+ if (likely(in_page >= msize)) {
55
+ sve_probe_page(&info, false, env, addr, 0, MMU_DATA_STORE,
56
+ mmu_idx, retaddr);
57
+ host[i] = info.host;
58
+ } else {
59
+ /*
60
+ * Element crosses the page boundary.
61
+ * Probe both pages, but do not record the host address,
62
+ * so that we use the slow path.
63
+ */
64
+ sve_probe_page(&info, false, env, addr, 0,
65
+ MMU_DATA_STORE, mmu_idx, retaddr);
66
+ sve_probe_page(&info2, false, env, addr + in_page, 0,
67
+ MMU_DATA_STORE, mmu_idx, retaddr);
68
+ info.flags |= info2.flags;
69
+ }
70
+
71
+ if (unlikely(info.flags & TLB_WATCHPOINT)) {
72
+ cpu_check_watchpoint(env_cpu(env), addr, msize,
73
+ info.attrs, BP_MEM_WRITE, retaddr);
74
+ }
75
+ /* TODO: MTE check. */
76
}
77
- i += 4, pg >>= 4;
78
- } while (i & 15);
79
- }
80
-}
81
+ i += 1;
82
+ reg_off += esize;
83
+ } while (reg_off & 63);
84
+ } while (reg_off < reg_max);
85
86
-static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
87
- target_ulong base, uint32_t desc, uintptr_t ra,
88
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
89
-{
90
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
91
- intptr_t i, oprsz = simd_oprsz(desc) / 8;
92
-
93
- for (i = 0; i < oprsz; i++) {
94
- uint8_t pg = *(uint8_t *)(vg + H1(i));
95
- if (likely(pg & 1)) {
96
- target_ulong off = off_fn(vm, i * 8);
97
- tlb_fn(env, vd, i * 8, base + (off << scale), ra);
98
+ /*
99
+ * Now that we have recognized all exceptions except SyncExternal
100
+ * (from TLB_MMIO), which we cannot avoid, perform all of the stores.
101
+ *
102
+ * Note for the common case of an element in RAM, not crossing a page
103
+ * boundary, we have stored the host address in host[]. This doubles
104
+ * as a first-level check against the predicate, since only enabled
105
+ * elements have non-null host addresses.
106
+ */
107
+ i = reg_off = 0;
108
+ do {
109
+ void *h = host[i];
110
+ if (likely(h != NULL)) {
111
+ host_fn(vd, reg_off, h);
112
+ } else if ((vg[reg_off >> 6] >> (reg_off & 63)) & 1) {
113
+ target_ulong addr = base + (off_fn(vm, reg_off) << scale);
114
+ tlb_fn(env, vd, reg_off, addr, retaddr);
115
}
116
- }
117
+ i += 1;
118
+ reg_off += esize;
119
+ } while (reg_off < reg_max);
120
}
121
122
-#define DO_ST1_ZPZ_S(MEM, OFS) \
123
-void QEMU_FLATTEN HELPER(sve_st##MEM##_##OFS) \
124
- (CPUARMState *env, void *vd, void *vg, void *vm, \
125
- target_ulong base, uint32_t desc) \
126
-{ \
127
- sve_st1_zs(env, vd, vg, vm, base, desc, GETPC(), \
128
- off_##OFS##_s, sve_st1##MEM##_tlb); \
129
+#define DO_ST1_ZPZ_S(MEM, OFS, MSZ) \
130
+void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
131
+ void *vm, target_ulong base, uint32_t desc) \
132
+{ \
133
+ sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, \
134
+ off_##OFS##_s, sve_st1##MEM##_host, sve_st1##MEM##_tlb); \
135
}
136
137
-#define DO_ST1_ZPZ_D(MEM, OFS) \
138
-void QEMU_FLATTEN HELPER(sve_st##MEM##_##OFS) \
139
- (CPUARMState *env, void *vd, void *vg, void *vm, \
140
- target_ulong base, uint32_t desc) \
141
-{ \
142
- sve_st1_zd(env, vd, vg, vm, base, desc, GETPC(), \
143
- off_##OFS##_d, sve_st1##MEM##_tlb); \
144
+#define DO_ST1_ZPZ_D(MEM, OFS, MSZ) \
145
+void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
146
+ void *vm, target_ulong base, uint32_t desc) \
147
+{ \
148
+ sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, \
149
+ off_##OFS##_d, sve_st1##MEM##_host, sve_st1##MEM##_tlb); \
150
}
151
152
-DO_ST1_ZPZ_S(bs, zsu)
153
-DO_ST1_ZPZ_S(hs_le, zsu)
154
-DO_ST1_ZPZ_S(hs_be, zsu)
155
-DO_ST1_ZPZ_S(ss_le, zsu)
156
-DO_ST1_ZPZ_S(ss_be, zsu)
157
+DO_ST1_ZPZ_S(bs, zsu, MO_8)
158
+DO_ST1_ZPZ_S(hs_le, zsu, MO_16)
159
+DO_ST1_ZPZ_S(hs_be, zsu, MO_16)
160
+DO_ST1_ZPZ_S(ss_le, zsu, MO_32)
161
+DO_ST1_ZPZ_S(ss_be, zsu, MO_32)
162
163
-DO_ST1_ZPZ_S(bs, zss)
164
-DO_ST1_ZPZ_S(hs_le, zss)
165
-DO_ST1_ZPZ_S(hs_be, zss)
166
-DO_ST1_ZPZ_S(ss_le, zss)
167
-DO_ST1_ZPZ_S(ss_be, zss)
168
+DO_ST1_ZPZ_S(bs, zss, MO_8)
169
+DO_ST1_ZPZ_S(hs_le, zss, MO_16)
170
+DO_ST1_ZPZ_S(hs_be, zss, MO_16)
171
+DO_ST1_ZPZ_S(ss_le, zss, MO_32)
172
+DO_ST1_ZPZ_S(ss_be, zss, MO_32)
173
174
-DO_ST1_ZPZ_D(bd, zsu)
175
-DO_ST1_ZPZ_D(hd_le, zsu)
176
-DO_ST1_ZPZ_D(hd_be, zsu)
177
-DO_ST1_ZPZ_D(sd_le, zsu)
178
-DO_ST1_ZPZ_D(sd_be, zsu)
179
-DO_ST1_ZPZ_D(dd_le, zsu)
180
-DO_ST1_ZPZ_D(dd_be, zsu)
181
+DO_ST1_ZPZ_D(bd, zsu, MO_8)
182
+DO_ST1_ZPZ_D(hd_le, zsu, MO_16)
183
+DO_ST1_ZPZ_D(hd_be, zsu, MO_16)
184
+DO_ST1_ZPZ_D(sd_le, zsu, MO_32)
185
+DO_ST1_ZPZ_D(sd_be, zsu, MO_32)
186
+DO_ST1_ZPZ_D(dd_le, zsu, MO_64)
187
+DO_ST1_ZPZ_D(dd_be, zsu, MO_64)
188
189
-DO_ST1_ZPZ_D(bd, zss)
190
-DO_ST1_ZPZ_D(hd_le, zss)
191
-DO_ST1_ZPZ_D(hd_be, zss)
192
-DO_ST1_ZPZ_D(sd_le, zss)
193
-DO_ST1_ZPZ_D(sd_be, zss)
194
-DO_ST1_ZPZ_D(dd_le, zss)
195
-DO_ST1_ZPZ_D(dd_be, zss)
196
+DO_ST1_ZPZ_D(bd, zss, MO_8)
197
+DO_ST1_ZPZ_D(hd_le, zss, MO_16)
198
+DO_ST1_ZPZ_D(hd_be, zss, MO_16)
199
+DO_ST1_ZPZ_D(sd_le, zss, MO_32)
200
+DO_ST1_ZPZ_D(sd_be, zss, MO_32)
201
+DO_ST1_ZPZ_D(dd_le, zss, MO_64)
202
+DO_ST1_ZPZ_D(dd_be, zss, MO_64)
203
204
-DO_ST1_ZPZ_D(bd, zd)
205
-DO_ST1_ZPZ_D(hd_le, zd)
206
-DO_ST1_ZPZ_D(hd_be, zd)
207
-DO_ST1_ZPZ_D(sd_le, zd)
208
-DO_ST1_ZPZ_D(sd_be, zd)
209
-DO_ST1_ZPZ_D(dd_le, zd)
210
-DO_ST1_ZPZ_D(dd_be, zd)
211
+DO_ST1_ZPZ_D(bd, zd, MO_8)
212
+DO_ST1_ZPZ_D(hd_le, zd, MO_16)
213
+DO_ST1_ZPZ_D(hd_be, zd, MO_16)
214
+DO_ST1_ZPZ_D(sd_le, zd, MO_32)
215
+DO_ST1_ZPZ_D(sd_be, zd, MO_32)
216
+DO_ST1_ZPZ_D(dd_le, zd, MO_64)
217
+DO_ST1_ZPZ_D(dd_be, zd, MO_64)
218
219
#undef DO_ST1_ZPZ_S
220
#undef DO_ST1_ZPZ_D
221
--
50
--
222
2.20.1
51
2.25.1
223
224
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
3
Handle all of the watchpoints for active elements all at once,
4
before we've modified the vector register. This removes the
5
TLB_WATCHPOINT bit from page[].flags, which means that we can
6
use the normal fast path via RAM.
7
2
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-13-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
5
---
13
target/arm/sve_helper.c | 72 ++++++++++++++++++++++++++++++++++++++++-
6
include/hw/timer/imx_epit.h | 2 ++
14
1 file changed, 71 insertions(+), 1 deletion(-)
7
hw/timer/imx_epit.c | 12 ++++++------
8
2 files changed, 8 insertions(+), 6 deletions(-)
15
9
16
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
10
diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h
17
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sve_helper.c
12
--- a/include/hw/timer/imx_epit.h
19
+++ b/target/arm/sve_helper.c
13
+++ b/include/hw/timer/imx_epit.h
20
@@ -XXX,XX +XXX,XX @@ static bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault,
14
@@ -XXX,XX +XXX,XX @@
21
return have_work;
15
#define CR_CLKSRC_SHIFT (24)
16
#define CR_CLKSRC_BITS (2)
17
18
+#define SR_OCIF (1 << 0)
19
+
20
#define EPIT_TIMER_MAX 0XFFFFFFFFUL
21
22
#define TYPE_IMX_EPIT "imx.epit"
23
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/timer/imx_epit.c
26
+++ b/hw/timer/imx_epit.c
27
@@ -XXX,XX +XXX,XX @@ static const IMXClk imx_epit_clocks[] = {
28
*/
29
static void imx_epit_update_int(IMXEPITState *s)
30
{
31
- if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
32
+ if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
33
qemu_irq_raise(s->irq);
34
} else {
35
qemu_irq_lower(s->irq);
36
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
37
break;
38
39
case 1: /* SR - ACK*/
40
- /* writing 1 to OCIF clears the OCIF bit */
41
- if (value & 0x01) {
42
- s->sr = 0;
43
+ /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
44
+ if (value & SR_OCIF) {
45
+ s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
46
imx_epit_update_int(s);
47
}
48
break;
49
@@ -XXX,XX +XXX,XX @@ static void imx_epit_cmp(void *opaque)
50
IMXEPITState *s = IMX_EPIT(opaque);
51
52
DPRINTF("sr was %d\n", s->sr);
53
-
54
- s->sr = 1;
55
+ /* Set interrupt status bit SR.OCIF and update the interrupt state */
56
+ s->sr |= SR_OCIF;
57
imx_epit_update_int(s);
22
}
58
}
23
59
24
+static void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env,
25
+ uint64_t *vg, target_ulong addr,
26
+ int esize, int msize, int wp_access,
27
+ uintptr_t retaddr)
28
+{
29
+#ifndef CONFIG_USER_ONLY
30
+ intptr_t mem_off, reg_off, reg_last;
31
+ int flags0 = info->page[0].flags;
32
+ int flags1 = info->page[1].flags;
33
+
34
+ if (likely(!((flags0 | flags1) & TLB_WATCHPOINT))) {
35
+ return;
36
+ }
37
+
38
+ /* Indicate that watchpoints are handled. */
39
+ info->page[0].flags = flags0 & ~TLB_WATCHPOINT;
40
+ info->page[1].flags = flags1 & ~TLB_WATCHPOINT;
41
+
42
+ if (flags0 & TLB_WATCHPOINT) {
43
+ mem_off = info->mem_off_first[0];
44
+ reg_off = info->reg_off_first[0];
45
+ reg_last = info->reg_off_last[0];
46
+
47
+ while (reg_off <= reg_last) {
48
+ uint64_t pg = vg[reg_off >> 6];
49
+ do {
50
+ if ((pg >> (reg_off & 63)) & 1) {
51
+ cpu_check_watchpoint(env_cpu(env), addr + mem_off,
52
+ msize, info->page[0].attrs,
53
+ wp_access, retaddr);
54
+ }
55
+ reg_off += esize;
56
+ mem_off += msize;
57
+ } while (reg_off <= reg_last && (reg_off & 63));
58
+ }
59
+ }
60
+
61
+ mem_off = info->mem_off_split;
62
+ if (mem_off >= 0) {
63
+ cpu_check_watchpoint(env_cpu(env), addr + mem_off, msize,
64
+ info->page[0].attrs, wp_access, retaddr);
65
+ }
66
+
67
+ mem_off = info->mem_off_first[1];
68
+ if ((flags1 & TLB_WATCHPOINT) && mem_off >= 0) {
69
+ reg_off = info->reg_off_first[1];
70
+ reg_last = info->reg_off_last[1];
71
+
72
+ do {
73
+ uint64_t pg = vg[reg_off >> 6];
74
+ do {
75
+ if ((pg >> (reg_off & 63)) & 1) {
76
+ cpu_check_watchpoint(env_cpu(env), addr + mem_off,
77
+ msize, info->page[1].attrs,
78
+ wp_access, retaddr);
79
+ }
80
+ reg_off += esize;
81
+ mem_off += msize;
82
+ } while (reg_off & 63);
83
+ } while (reg_off <= reg_last);
84
+ }
85
+#endif
86
+}
87
+
88
/*
89
* The result of tlb_vaddr_to_host for user-only is just g2h(x),
90
* which is always non-null. Elide the useless test.
91
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
92
/* Probe the page(s). Exit with exception for any invalid page. */
93
sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, retaddr);
94
95
+ /* Handle watchpoints for all active elements. */
96
+ sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, 1 << msz,
97
+ BP_MEM_READ, retaddr);
98
+
99
+ /* TODO: MTE check. */
100
+
101
flags = info.page[0].flags | info.page[1].flags;
102
if (unlikely(flags != 0)) {
103
#ifdef CONFIG_USER_ONLY
104
g_assert_not_reached();
105
#else
106
/*
107
- * At least one page includes MMIO (or watchpoints).
108
+ * At least one page includes MMIO.
109
* Any bus operation can fail with cpu_transaction_failed,
110
* which for ARM will raise SyncExternal. Perform the load
111
* into scratch memory to preserve register state until the end.
112
--
60
--
113
2.20.1
61
2.25.1
114
115
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
2
3
On the NRF51 series, all peripherals have a fixed I/O size
3
The interrupt state can change due to:
4
of 4KiB. Define NRF51_PERIPHERAL_SIZE and use it.
4
- reset clears both SR.OCIF and CR.OCIE
5
- write to CR.EN or CR.OCIE
5
6
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20200504072822.18799-2-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
include/hw/arm/nrf51.h | 3 +--
11
hw/timer/imx_epit.c | 16 ++++++++++++----
12
include/hw/i2c/microbit_i2c.h | 2 +-
12
1 file changed, 12 insertions(+), 4 deletions(-)
13
hw/arm/nrf51_soc.c | 4 ++--
14
hw/i2c/microbit_i2c.c | 2 +-
15
hw/timer/nrf51_timer.c | 2 +-
16
5 files changed, 6 insertions(+), 7 deletions(-)
17
13
18
diff --git a/include/hw/arm/nrf51.h b/include/hw/arm/nrf51.h
14
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/nrf51.h
16
--- a/hw/timer/imx_epit.c
21
+++ b/include/hw/arm/nrf51.h
17
+++ b/hw/timer/imx_epit.c
22
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
23
#define NRF51_IOMEM_BASE 0x40000000
19
if (s->cr & CR_SWR) {
24
#define NRF51_IOMEM_SIZE 0x20000000
20
/* handle the reset */
25
21
imx_epit_reset(DEVICE(s));
26
+#define NRF51_PERIPHERAL_SIZE 0x00001000
22
- /*
27
#define NRF51_UART_BASE 0x40002000
23
- * TODO: could we 'break' here? following operations appear
28
#define NRF51_TWI_BASE 0x40003000
24
- * to duplicate the work imx_epit_reset() already did.
29
-#define NRF51_TWI_SIZE 0x00001000
25
- */
30
#define NRF51_TIMER_BASE 0x40008000
31
-#define NRF51_TIMER_SIZE 0x00001000
32
#define NRF51_RNG_BASE 0x4000D000
33
#define NRF51_NVMC_BASE 0x4001E000
34
#define NRF51_GPIO_BASE 0x50000000
35
diff --git a/include/hw/i2c/microbit_i2c.h b/include/hw/i2c/microbit_i2c.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/include/hw/i2c/microbit_i2c.h
38
+++ b/include/hw/i2c/microbit_i2c.h
39
@@ -XXX,XX +XXX,XX @@
40
#define MICROBIT_I2C(obj) \
41
OBJECT_CHECK(MicrobitI2CState, (obj), TYPE_MICROBIT_I2C)
42
43
-#define MICROBIT_I2C_NREGS (NRF51_TWI_SIZE / sizeof(uint32_t))
44
+#define MICROBIT_I2C_NREGS (NRF51_PERIPHERAL_SIZE / sizeof(uint32_t))
45
46
typedef struct {
47
SysBusDevice parent_obj;
48
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/arm/nrf51_soc.c
51
+++ b/hw/arm/nrf51_soc.c
52
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
53
return;
54
}
26
}
55
27
56
- base_addr = NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE;
28
+ /*
57
+ base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE;
29
+ * The interrupt state can change due to:
58
30
+ * - reset clears both SR.OCIF and CR.OCIE
59
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
31
+ * - write to CR.EN or CR.OCIE
60
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
32
+ */
61
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
33
+ imx_epit_update_int(s);
62
34
+
63
/* STUB Peripherals */
35
+ /*
64
memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL,
36
+ * TODO: could we 'break' here for reset? following operations appear
65
- "nrf51_soc.clock", 0x1000);
37
+ * to duplicate the work imx_epit_reset() already did.
66
+ "nrf51_soc.clock", NRF51_PERIPHERAL_SIZE);
38
+ */
67
memory_region_add_subregion_overlap(&s->container,
39
+
68
NRF51_IOMEM_BASE, &s->clock, -1);
40
ptimer_transaction_begin(s->timer_cmp);
69
41
ptimer_transaction_begin(s->timer_reload);
70
diff --git a/hw/i2c/microbit_i2c.c b/hw/i2c/microbit_i2c.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/i2c/microbit_i2c.c
73
+++ b/hw/i2c/microbit_i2c.c
74
@@ -XXX,XX +XXX,XX @@ static void microbit_i2c_realize(DeviceState *dev, Error **errp)
75
MicrobitI2CState *s = MICROBIT_I2C(dev);
76
77
memory_region_init_io(&s->iomem, OBJECT(s), &microbit_i2c_ops, s,
78
- "microbit.twi", NRF51_TWI_SIZE);
79
+ "microbit.twi", NRF51_PERIPHERAL_SIZE);
80
sysbus_init_mmio(sbd, &s->iomem);
81
}
82
83
diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c
84
index XXXXXXX..XXXXXXX 100644
85
--- a/hw/timer/nrf51_timer.c
86
+++ b/hw/timer/nrf51_timer.c
87
@@ -XXX,XX +XXX,XX @@ static void nrf51_timer_init(Object *obj)
88
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
89
90
memory_region_init_io(&s->iomem, obj, &rng_ops, s,
91
- TYPE_NRF51_TIMER, NRF51_TIMER_SIZE);
92
+ TYPE_NRF51_TIMER, NRF51_PERIPHERAL_SIZE);
93
sysbus_init_mmio(sbd, &s->iomem);
94
sysbus_init_irq(sbd, &s->irq);
95
42
96
--
43
--
97
2.20.1
44
2.25.1
98
99
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
2
3
This new interface will allow targets to probe for a page
3
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
4
and then handle watchpoints themselves. This will be most
5
useful for vector predicated memory operations, where one
6
page lookup can be used for many operations, and one test
7
can avoid many watchpoint checks.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-6-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
6
---
14
include/exec/cpu-all.h | 13 ++-
7
hw/timer/imx_epit.c | 20 ++++++++++++++------
15
include/exec/exec-all.h | 22 +++++
8
1 file changed, 14 insertions(+), 6 deletions(-)
16
accel/tcg/cputlb.c | 177 ++++++++++++++++++++--------------------
17
accel/tcg/user-exec.c | 43 ++++++++--
18
4 files changed, 158 insertions(+), 97 deletions(-)
19
9
20
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
10
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
21
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
22
--- a/include/exec/cpu-all.h
12
--- a/hw/timer/imx_epit.c
23
+++ b/include/exec/cpu-all.h
13
+++ b/hw/timer/imx_epit.c
24
@@ -XXX,XX +XXX,XX @@ CPUArchState *cpu_copy(CPUArchState *env);
14
@@ -XXX,XX +XXX,XX @@ static void imx_epit_set_freq(IMXEPITState *s)
25
| CPU_INTERRUPT_TGT_EXT_3 \
26
| CPU_INTERRUPT_TGT_EXT_4)
27
28
-#if !defined(CONFIG_USER_ONLY)
29
+#ifdef CONFIG_USER_ONLY
30
+
31
+/*
32
+ * Allow some level of source compatibility with softmmu. We do not
33
+ * support any of the more exotic features, so only invalid pages may
34
+ * be signaled by probe_access_flags().
35
+ */
36
+#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
37
+#define TLB_MMIO 0
38
+#define TLB_WATCHPOINT 0
39
+
40
+#else
41
42
/*
15
/*
43
* Flags stored in the low bits of the TLB virtual address.
16
* This is called both on hardware (device) reset and software reset.
44
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
17
*/
45
index XXXXXXX..XXXXXXX 100644
18
-static void imx_epit_reset(DeviceState *dev)
46
--- a/include/exec/exec-all.h
19
+static void imx_epit_reset(IMXEPITState *s, bool is_hard_reset)
47
+++ b/include/exec/exec-all.h
20
{
48
@@ -XXX,XX +XXX,XX @@ static inline void *probe_read(CPUArchState *env, target_ulong addr, int size,
21
- IMXEPITState *s = IMX_EPIT(dev);
49
return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
22
-
23
/* Soft reset doesn't touch some bits; hard reset clears them */
24
- s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
25
+ if (is_hard_reset) {
26
+ s->cr = 0;
27
+ } else {
28
+ s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
29
+ }
30
s->sr = 0;
31
s->lr = EPIT_TIMER_MAX;
32
s->cmp = 0;
33
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
34
s->cr = value & 0x03ffffff;
35
if (s->cr & CR_SWR) {
36
/* handle the reset */
37
- imx_epit_reset(DEVICE(s));
38
+ imx_epit_reset(s, false);
39
}
40
41
/*
42
@@ -XXX,XX +XXX,XX @@ static void imx_epit_realize(DeviceState *dev, Error **errp)
43
s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY);
50
}
44
}
51
45
52
+/**
46
+static void imx_epit_dev_reset(DeviceState *dev)
53
+ * probe_access_flags:
47
+{
54
+ * @env: CPUArchState
48
+ IMXEPITState *s = IMX_EPIT(dev);
55
+ * @addr: guest virtual address to look up
49
+ imx_epit_reset(s, true);
56
+ * @access_type: read, write or execute permission
57
+ * @mmu_idx: MMU index to use for lookup
58
+ * @nonfault: suppress the fault
59
+ * @phost: return value for host address
60
+ * @retaddr: return address for unwinding
61
+ *
62
+ * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for
63
+ * the page, and storing the host address for RAM in @phost.
64
+ *
65
+ * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK.
66
+ * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags.
67
+ * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags.
68
+ * For simplicity, all "mmio-like" flags are folded to TLB_MMIO.
69
+ */
70
+int probe_access_flags(CPUArchState *env, target_ulong addr,
71
+ MMUAccessType access_type, int mmu_idx,
72
+ bool nonfault, void **phost, uintptr_t retaddr);
73
+
74
#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
75
76
/* Estimated block size for TB allocation. */
77
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/accel/tcg/cputlb.c
80
+++ b/accel/tcg/cputlb.c
81
@@ -XXX,XX +XXX,XX @@ static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size,
82
}
83
}
84
85
-/*
86
- * Probe for whether the specified guest access is permitted. If it is not
87
- * permitted then an exception will be taken in the same way as if this
88
- * were a real access (and we will not return).
89
- * If the size is 0 or the page requires I/O access, returns NULL; otherwise,
90
- * returns the address of the host page similar to tlb_vaddr_to_host().
91
- */
92
-void *probe_access(CPUArchState *env, target_ulong addr, int size,
93
- MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
94
+static int probe_access_internal(CPUArchState *env, target_ulong addr,
95
+ int fault_size, MMUAccessType access_type,
96
+ int mmu_idx, bool nonfault,
97
+ void **phost, uintptr_t retaddr)
98
{
99
uintptr_t index = tlb_index(env, mmu_idx, addr);
100
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
101
- target_ulong tlb_addr;
102
- size_t elt_ofs;
103
- int wp_access;
104
-
105
- g_assert(-(addr | TARGET_PAGE_MASK) >= size);
106
-
107
- switch (access_type) {
108
- case MMU_DATA_LOAD:
109
- elt_ofs = offsetof(CPUTLBEntry, addr_read);
110
- wp_access = BP_MEM_READ;
111
- break;
112
- case MMU_DATA_STORE:
113
- elt_ofs = offsetof(CPUTLBEntry, addr_write);
114
- wp_access = BP_MEM_WRITE;
115
- break;
116
- case MMU_INST_FETCH:
117
- elt_ofs = offsetof(CPUTLBEntry, addr_code);
118
- wp_access = BP_MEM_READ;
119
- break;
120
- default:
121
- g_assert_not_reached();
122
- }
123
- tlb_addr = tlb_read_ofs(entry, elt_ofs);
124
-
125
- if (unlikely(!tlb_hit(tlb_addr, addr))) {
126
- if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs,
127
- addr & TARGET_PAGE_MASK)) {
128
- tlb_fill(env_cpu(env), addr, size, access_type, mmu_idx, retaddr);
129
- /* TLB resize via tlb_fill may have moved the entry. */
130
- index = tlb_index(env, mmu_idx, addr);
131
- entry = tlb_entry(env, mmu_idx, addr);
132
- }
133
- tlb_addr = tlb_read_ofs(entry, elt_ofs);
134
- }
135
-
136
- if (!size) {
137
- return NULL;
138
- }
139
-
140
- if (unlikely(tlb_addr & TLB_FLAGS_MASK)) {
141
- CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
142
-
143
- /* Reject I/O access, or other required slow-path. */
144
- if (tlb_addr & (TLB_MMIO | TLB_BSWAP | TLB_DISCARD_WRITE)) {
145
- return NULL;
146
- }
147
-
148
- /* Handle watchpoints. */
149
- if (tlb_addr & TLB_WATCHPOINT) {
150
- cpu_check_watchpoint(env_cpu(env), addr, size,
151
- iotlbentry->attrs, wp_access, retaddr);
152
- }
153
-
154
- /* Handle clean RAM pages. */
155
- if (tlb_addr & TLB_NOTDIRTY) {
156
- notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr);
157
- }
158
- }
159
-
160
- return (void *)((uintptr_t)addr + entry->addend);
161
-}
162
-
163
-void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
164
- MMUAccessType access_type, int mmu_idx)
165
-{
166
- CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
167
- target_ulong tlb_addr, page;
168
+ target_ulong tlb_addr, page_addr;
169
size_t elt_ofs;
170
+ int flags;
171
172
switch (access_type) {
173
case MMU_DATA_LOAD:
174
@@ -XXX,XX +XXX,XX @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
175
default:
176
g_assert_not_reached();
177
}
178
-
179
- page = addr & TARGET_PAGE_MASK;
180
tlb_addr = tlb_read_ofs(entry, elt_ofs);
181
182
- if (!tlb_hit_page(tlb_addr, page)) {
183
- uintptr_t index = tlb_index(env, mmu_idx, addr);
184
-
185
- if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page)) {
186
+ page_addr = addr & TARGET_PAGE_MASK;
187
+ if (!tlb_hit_page(tlb_addr, page_addr)) {
188
+ if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) {
189
CPUState *cs = env_cpu(env);
190
CPUClass *cc = CPU_GET_CLASS(cs);
191
192
- if (!cc->tlb_fill(cs, addr, 0, access_type, mmu_idx, true, 0)) {
193
+ if (!cc->tlb_fill(cs, addr, fault_size, access_type,
194
+ mmu_idx, nonfault, retaddr)) {
195
/* Non-faulting page table read failed. */
196
- return NULL;
197
+ *phost = NULL;
198
+ return TLB_INVALID_MASK;
199
}
200
201
/* TLB resize via tlb_fill may have moved the entry. */
202
@@ -XXX,XX +XXX,XX @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
203
}
204
tlb_addr = tlb_read_ofs(entry, elt_ofs);
205
}
206
+ flags = tlb_addr & TLB_FLAGS_MASK;
207
208
- if (tlb_addr & ~TARGET_PAGE_MASK) {
209
- /* IO access */
210
+ /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */
211
+ if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) {
212
+ *phost = NULL;
213
+ return TLB_MMIO;
214
+ }
215
+
216
+ /* Everything else is RAM. */
217
+ *phost = (void *)((uintptr_t)addr + entry->addend);
218
+ return flags;
219
+}
50
+}
220
+
51
+
221
+int probe_access_flags(CPUArchState *env, target_ulong addr,
52
static void imx_epit_class_init(ObjectClass *klass, void *data)
222
+ MMUAccessType access_type, int mmu_idx,
223
+ bool nonfault, void **phost, uintptr_t retaddr)
224
+{
225
+ int flags;
226
+
227
+ flags = probe_access_internal(env, addr, 0, access_type, mmu_idx,
228
+ nonfault, phost, retaddr);
229
+
230
+ /* Handle clean RAM pages. */
231
+ if (unlikely(flags & TLB_NOTDIRTY)) {
232
+ uintptr_t index = tlb_index(env, mmu_idx, addr);
233
+ CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
234
+
235
+ notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr);
236
+ flags &= ~TLB_NOTDIRTY;
237
+ }
238
+
239
+ return flags;
240
+}
241
+
242
+void *probe_access(CPUArchState *env, target_ulong addr, int size,
243
+ MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
244
+{
245
+ void *host;
246
+ int flags;
247
+
248
+ g_assert(-(addr | TARGET_PAGE_MASK) >= size);
249
+
250
+ flags = probe_access_internal(env, addr, size, access_type, mmu_idx,
251
+ false, &host, retaddr);
252
+
253
+ /* Per the interface, size == 0 merely faults the access. */
254
+ if (size == 0) {
255
return NULL;
256
}
257
258
- return (void *)((uintptr_t)addr + entry->addend);
259
+ if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) {
260
+ uintptr_t index = tlb_index(env, mmu_idx, addr);
261
+ CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
262
+
263
+ /* Handle watchpoints. */
264
+ if (flags & TLB_WATCHPOINT) {
265
+ int wp_access = (access_type == MMU_DATA_STORE
266
+ ? BP_MEM_WRITE : BP_MEM_READ);
267
+ cpu_check_watchpoint(env_cpu(env), addr, size,
268
+ iotlbentry->attrs, wp_access, retaddr);
269
+ }
270
+
271
+ /* Handle clean RAM pages. */
272
+ if (flags & TLB_NOTDIRTY) {
273
+ notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr);
274
+ }
275
+ }
276
+
277
+ return host;
278
}
279
280
+void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
281
+ MMUAccessType access_type, int mmu_idx)
282
+{
283
+ void *host;
284
+ int flags;
285
+
286
+ flags = probe_access_internal(env, addr, 0, access_type,
287
+ mmu_idx, true, &host, 0);
288
+
289
+ /* No combination of flags are expected by the caller. */
290
+ return flags ? NULL : host;
291
+}
292
293
#ifdef CONFIG_PLUGIN
294
/*
295
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
296
index XXXXXXX..XXXXXXX 100644
297
--- a/accel/tcg/user-exec.c
298
+++ b/accel/tcg/user-exec.c
299
@@ -XXX,XX +XXX,XX @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
300
g_assert_not_reached();
301
}
302
303
-void *probe_access(CPUArchState *env, target_ulong addr, int size,
304
- MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
305
+static int probe_access_internal(CPUArchState *env, target_ulong addr,
306
+ int fault_size, MMUAccessType access_type,
307
+ bool nonfault, uintptr_t ra)
308
{
53
{
309
int flags;
54
DeviceClass *dc = DEVICE_CLASS(klass);
310
55
311
- g_assert(-(addr | TARGET_PAGE_MASK) >= size);
56
dc->realize = imx_epit_realize;
312
-
57
- dc->reset = imx_epit_reset;
313
switch (access_type) {
58
+ dc->reset = imx_epit_dev_reset;
314
case MMU_DATA_STORE:
59
dc->vmsd = &vmstate_imx_timer_epit;
315
flags = PAGE_WRITE;
60
dc->desc = "i.MX periodic timer";
316
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
317
}
318
319
if (!guest_addr_valid(addr) || page_check_range(addr, 1, flags) < 0) {
320
- CPUState *cpu = env_cpu(env);
321
- CPUClass *cc = CPU_GET_CLASS(cpu);
322
- cc->tlb_fill(cpu, addr, size, access_type, MMU_USER_IDX, false,
323
- retaddr);
324
- g_assert_not_reached();
325
+ if (nonfault) {
326
+ return TLB_INVALID_MASK;
327
+ } else {
328
+ CPUState *cpu = env_cpu(env);
329
+ CPUClass *cc = CPU_GET_CLASS(cpu);
330
+ cc->tlb_fill(cpu, addr, fault_size, access_type,
331
+ MMU_USER_IDX, false, ra);
332
+ g_assert_not_reached();
333
+ }
334
}
335
+ return 0;
336
+}
337
+
338
+int probe_access_flags(CPUArchState *env, target_ulong addr,
339
+ MMUAccessType access_type, int mmu_idx,
340
+ bool nonfault, void **phost, uintptr_t ra)
341
+{
342
+ int flags;
343
+
344
+ flags = probe_access_internal(env, addr, 0, access_type, nonfault, ra);
345
+ *phost = flags ? NULL : g2h(addr);
346
+ return flags;
347
+}
348
+
349
+void *probe_access(CPUArchState *env, target_ulong addr, int size,
350
+ MMUAccessType access_type, int mmu_idx, uintptr_t ra)
351
+{
352
+ int flags;
353
+
354
+ g_assert(-(addr | TARGET_PAGE_MASK) >= size);
355
+ flags = probe_access_internal(env, addr, size, access_type, false, ra);
356
+ g_assert(flags == 0);
357
358
return size ? g2h(addr) : NULL;
359
}
61
}
360
--
62
--
361
2.20.1
63
2.25.1
362
363
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
2
3
For contiguous predicated memory operations, we want to
3
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
4
minimize the number of tlb lookups performed. We have
5
open-coded this for sve_ld1_r, but for correctness with
6
MTE we will need this for all of the memory operations.
7
8
Create a structure that holds the bounds of active elements,
9
and metadata for two pages. Add routines to find those
10
active elements, lookup the pages, and run watchpoints
11
for those pages.
12
13
Temporarily mark the functions unused to avoid Werror.
14
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20200508154359.7494-10-richard.henderson@linaro.org
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
6
---
20
target/arm/sve_helper.c | 263 +++++++++++++++++++++++++++++++++++++++-
7
hw/timer/imx_epit.c | 215 ++++++++++++++++++++++++--------------------
21
1 file changed, 261 insertions(+), 2 deletions(-)
8
1 file changed, 117 insertions(+), 98 deletions(-)
22
9
23
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
10
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
24
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/sve_helper.c
12
--- a/hw/timer/imx_epit.c
26
+++ b/target/arm/sve_helper.c
13
+++ b/hw/timer/imx_epit.c
27
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_cpy_z_d)(void *vd, void *vg, uint64_t val, uint32_t desc)
14
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reload_compare_timer(IMXEPITState *s)
28
}
15
}
29
}
16
}
30
17
31
-/* Big-endian hosts need to frob the byte indicies. If the copy
18
+static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
32
+/* Big-endian hosts need to frob the byte indices. If the copy
19
+{
33
* happens to be 8-byte aligned, then no frobbing necessary.
20
+ uint32_t oldcr = s->cr;
34
*/
21
+
35
static void swap_memmove(void *vd, void *vs, size_t n)
22
+ s->cr = value & 0x03ffffff;
36
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
23
+
37
/*
24
+ if (s->cr & CR_SWR) {
38
* Load elements into @vd, controlled by @vg, from @host + @mem_ofs.
25
+ /* handle the reset */
39
* Memory is valid through @host + @mem_max. The register element
26
+ imx_epit_reset(s, false);
40
- * indicies are inferred from @mem_ofs, as modified by the types for
27
+ }
41
+ * indices are inferred from @mem_ofs, as modified by the types for
28
+
42
* which the helper is built. Return the @mem_ofs of the first element
43
* not loaded (which is @mem_max if they are all loaded).
44
*
45
@@ -XXX,XX +XXX,XX @@ static intptr_t max_for_page(target_ulong base, intptr_t mem_off,
46
return MIN(split, mem_max - mem_off) + mem_off;
47
}
48
49
+/*
50
+ * Resolve the guest virtual address to info->host and info->flags.
51
+ * If @nofault, return false if the page is invalid, otherwise
52
+ * exit via page fault exception.
53
+ */
54
+
55
+typedef struct {
56
+ void *host;
57
+ int flags;
58
+ MemTxAttrs attrs;
59
+} SVEHostPage;
60
+
61
+static bool sve_probe_page(SVEHostPage *info, bool nofault,
62
+ CPUARMState *env, target_ulong addr,
63
+ int mem_off, MMUAccessType access_type,
64
+ int mmu_idx, uintptr_t retaddr)
65
+{
66
+ int flags;
67
+
68
+ addr += mem_off;
69
+ flags = probe_access_flags(env, addr, access_type, mmu_idx, nofault,
70
+ &info->host, retaddr);
71
+ info->flags = flags;
72
+
73
+ if (flags & TLB_INVALID_MASK) {
74
+ g_assert(nofault);
75
+ return false;
76
+ }
77
+
78
+ /* Ensure that info->host[] is relative to addr, not addr + mem_off. */
79
+ info->host -= mem_off;
80
+
81
+#ifdef CONFIG_USER_ONLY
82
+ memset(&info->attrs, 0, sizeof(info->attrs));
83
+#else
84
+ /*
29
+ /*
85
+ * Find the iotlbentry for addr and return the transaction attributes.
30
+ * The interrupt state can change due to:
86
+ * This *must* be present in the TLB because we just found the mapping.
31
+ * - reset clears both SR.OCIF and CR.OCIE
32
+ * - write to CR.EN or CR.OCIE
87
+ */
33
+ */
88
+ {
34
+ imx_epit_update_int(s);
89
+ uintptr_t index = tlb_index(env, mmu_idx, addr);
35
+
90
+
91
+# ifdef CONFIG_DEBUG_TCG
92
+ CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
93
+ target_ulong comparator = (access_type == MMU_DATA_LOAD
94
+ ? entry->addr_read
95
+ : tlb_addr_write(entry));
96
+ g_assert(tlb_hit(comparator, addr));
97
+# endif
98
+
99
+ CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
100
+ info->attrs = iotlbentry->attrs;
101
+ }
102
+#endif
103
+
104
+ return true;
105
+}
106
+
107
+
108
+/*
109
+ * Analyse contiguous data, protected by a governing predicate.
110
+ */
111
+
112
+typedef enum {
113
+ FAULT_NO,
114
+ FAULT_FIRST,
115
+ FAULT_ALL,
116
+} SVEContFault;
117
+
118
+typedef struct {
119
+ /*
36
+ /*
120
+ * First and last element wholly contained within the two pages.
37
+ * TODO: could we 'break' here for reset? following operations appear
121
+ * mem_off_first[0] and reg_off_first[0] are always set >= 0.
38
+ * to duplicate the work imx_epit_reset() already did.
122
+ * reg_off_last[0] may be < 0 if the first element crosses pages.
123
+ * All of mem_off_first[1], reg_off_first[1] and reg_off_last[1]
124
+ * are set >= 0 only if there are complete elements on a second page.
125
+ *
126
+ * The reg_off_* offsets are relative to the internal vector register.
127
+ * The mem_off_first offset is relative to the memory address; the
128
+ * two offsets are different when a load operation extends, a store
129
+ * operation truncates, or for multi-register operations.
130
+ */
39
+ */
131
+ int16_t mem_off_first[2];
40
+
132
+ int16_t reg_off_first[2];
41
+ ptimer_transaction_begin(s->timer_cmp);
133
+ int16_t reg_off_last[2];
42
+ ptimer_transaction_begin(s->timer_reload);
134
+
43
+
135
+ /*
44
+ /* Update the frequency. Has been done already in case of a reset. */
136
+ * One element that is misaligned and spans both pages,
45
+ if (!(s->cr & CR_SWR)) {
137
+ * or -1 if there is no such active element.
46
+ imx_epit_set_freq(s);
138
+ */
47
+ }
139
+ int16_t mem_off_split;
48
+
140
+ int16_t reg_off_split;
49
+ if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
141
+
50
+ if (s->cr & CR_ENMOD) {
142
+ /*
51
+ if (s->cr & CR_RLD) {
143
+ * The byte offset at which the entire operation crosses a page boundary.
52
+ ptimer_set_limit(s->timer_reload, s->lr, 1);
144
+ * Set >= 0 if and only if the entire operation spans two pages.
53
+ ptimer_set_limit(s->timer_cmp, s->lr, 1);
145
+ */
54
+ } else {
146
+ int16_t page_split;
55
+ ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
147
+
56
+ ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
148
+ /* TLB data for the two pages. */
149
+ SVEHostPage page[2];
150
+} SVEContLdSt;
151
+
152
+/*
153
+ * Find first active element on each page, and a loose bound for the
154
+ * final element on each page. Identify any single element that spans
155
+ * the page boundary. Return true if there are any active elements.
156
+ */
157
+static bool __attribute__((unused))
158
+sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg,
159
+ intptr_t reg_max, int esz, int msize)
160
+{
161
+ const int esize = 1 << esz;
162
+ const uint64_t pg_mask = pred_esz_masks[esz];
163
+ intptr_t reg_off_first = -1, reg_off_last = -1, reg_off_split;
164
+ intptr_t mem_off_last, mem_off_split;
165
+ intptr_t page_split, elt_split;
166
+ intptr_t i;
167
+
168
+ /* Set all of the element indices to -1, and the TLB data to 0. */
169
+ memset(info, -1, offsetof(SVEContLdSt, page));
170
+ memset(info->page, 0, sizeof(info->page));
171
+
172
+ /* Gross scan over the entire predicate to find bounds. */
173
+ i = 0;
174
+ do {
175
+ uint64_t pg = vg[i] & pg_mask;
176
+ if (pg) {
177
+ reg_off_last = i * 64 + 63 - clz64(pg);
178
+ if (reg_off_first < 0) {
179
+ reg_off_first = i * 64 + ctz64(pg);
180
+ }
57
+ }
181
+ }
58
+ }
182
+ } while (++i * 64 < reg_max);
59
+
183
+
60
+ imx_epit_reload_compare_timer(s);
184
+ if (unlikely(reg_off_first < 0)) {
61
+ ptimer_run(s->timer_reload, 0);
185
+ /* No active elements, no pages touched. */
62
+ if (s->cr & CR_OCIEN) {
186
+ return false;
63
+ ptimer_run(s->timer_cmp, 0);
187
+ }
64
+ } else {
188
+ tcg_debug_assert(reg_off_last >= 0 && reg_off_last < reg_max);
65
+ ptimer_stop(s->timer_cmp);
189
+
190
+ info->reg_off_first[0] = reg_off_first;
191
+ info->mem_off_first[0] = (reg_off_first >> esz) * msize;
192
+ mem_off_last = (reg_off_last >> esz) * msize;
193
+
194
+ page_split = -(addr | TARGET_PAGE_MASK);
195
+ if (likely(mem_off_last + msize <= page_split)) {
196
+ /* The entire operation fits within a single page. */
197
+ info->reg_off_last[0] = reg_off_last;
198
+ return true;
199
+ }
200
+
201
+ info->page_split = page_split;
202
+ elt_split = page_split / msize;
203
+ reg_off_split = elt_split << esz;
204
+ mem_off_split = elt_split * msize;
205
+
206
+ /*
207
+ * This is the last full element on the first page, but it is not
208
+ * necessarily active. If there is no full element, i.e. the first
209
+ * active element is the one that's split, this value remains -1.
210
+ * It is useful as iteration bounds.
211
+ */
212
+ if (elt_split != 0) {
213
+ info->reg_off_last[0] = reg_off_split - esize;
214
+ }
215
+
216
+ /* Determine if an unaligned element spans the pages. */
217
+ if (page_split % msize != 0) {
218
+ /* It is helpful to know if the split element is active. */
219
+ if ((vg[reg_off_split >> 6] >> (reg_off_split & 63)) & 1) {
220
+ info->reg_off_split = reg_off_split;
221
+ info->mem_off_split = mem_off_split;
222
+
223
+ if (reg_off_split == reg_off_last) {
224
+ /* The page crossing element is last. */
225
+ return true;
226
+ }
227
+ }
66
+ }
228
+ reg_off_split += esize;
67
+ } else if (!(s->cr & CR_EN)) {
229
+ mem_off_split += msize;
68
+ /* stop both timers */
230
+ }
69
+ ptimer_stop(s->timer_reload);
231
+
70
+ ptimer_stop(s->timer_cmp);
232
+ /*
71
+ } else if (s->cr & CR_OCIEN) {
233
+ * We do want the first active element on the second page, because
72
+ if (!(oldcr & CR_OCIEN)) {
234
+ * this may affect the address reported in an exception.
73
+ imx_epit_reload_compare_timer(s);
235
+ */
74
+ ptimer_run(s->timer_cmp, 0);
236
+ reg_off_split = find_next_active(vg, reg_off_split, reg_max, esz);
237
+ tcg_debug_assert(reg_off_split <= reg_off_last);
238
+ info->reg_off_first[1] = reg_off_split;
239
+ info->mem_off_first[1] = (reg_off_split >> esz) * msize;
240
+ info->reg_off_last[1] = reg_off_last;
241
+ return true;
242
+}
243
+
244
+/*
245
+ * Resolve the guest virtual addresses to info->page[].
246
+ * Control the generation of page faults with @fault. Return false if
247
+ * there is no work to do, which can only happen with @fault == FAULT_NO.
248
+ */
249
+static bool __attribute__((unused))
250
+sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, CPUARMState *env,
251
+ target_ulong addr, MMUAccessType access_type,
252
+ uintptr_t retaddr)
253
+{
254
+ int mmu_idx = cpu_mmu_index(env, false);
255
+ int mem_off = info->mem_off_first[0];
256
+ bool nofault = fault == FAULT_NO;
257
+ bool have_work = true;
258
+
259
+ if (!sve_probe_page(&info->page[0], nofault, env, addr, mem_off,
260
+ access_type, mmu_idx, retaddr)) {
261
+ /* No work to be done. */
262
+ return false;
263
+ }
264
+
265
+ if (likely(info->page_split < 0)) {
266
+ /* The entire operation was on the one page. */
267
+ return true;
268
+ }
269
+
270
+ /*
271
+ * If the second page is invalid, then we want the fault address to be
272
+ * the first byte on that page which is accessed.
273
+ */
274
+ if (info->mem_off_split >= 0) {
275
+ /*
276
+ * There is an element split across the pages. The fault address
277
+ * should be the first byte of the second page.
278
+ */
279
+ mem_off = info->page_split;
280
+ /*
281
+ * If the split element is also the first active element
282
+ * of the vector, then: For first-fault we should continue
283
+ * to generate faults for the second page. For no-fault,
284
+ * we have work only if the second page is valid.
285
+ */
286
+ if (info->mem_off_first[0] < info->mem_off_split) {
287
+ nofault = FAULT_FIRST;
288
+ have_work = false;
289
+ }
75
+ }
290
+ } else {
76
+ } else {
291
+ /*
77
+ ptimer_stop(s->timer_cmp);
292
+ * There is no element split across the pages. The fault address
78
+ }
293
+ * should be the first active element on the second page.
79
+
294
+ */
80
+ ptimer_transaction_commit(s->timer_cmp);
295
+ mem_off = info->mem_off_first[1];
81
+ ptimer_transaction_commit(s->timer_reload);
296
+ /*
82
+}
297
+ * There must have been one active element on the first page,
83
+
298
+ * so we're out of first-fault territory.
84
+static void imx_epit_write_sr(IMXEPITState *s, uint32_t value)
299
+ */
85
+{
300
+ nofault = fault != FAULT_ALL;
86
+ /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
301
+ }
87
+ if (value & SR_OCIF) {
302
+
88
+ s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
303
+ have_work |= sve_probe_page(&info->page[1], nofault, env, addr, mem_off,
89
+ imx_epit_update_int(s);
304
+ access_type, mmu_idx, retaddr);
90
+ }
305
+ return have_work;
91
+}
306
+}
92
+
307
+
93
+static void imx_epit_write_lr(IMXEPITState *s, uint32_t value)
308
/*
94
+{
309
* The result of tlb_vaddr_to_host for user-only is just g2h(x),
95
+ s->lr = value;
310
* which is always non-null. Elide the useless test.
96
+
97
+ ptimer_transaction_begin(s->timer_cmp);
98
+ ptimer_transaction_begin(s->timer_reload);
99
+ if (s->cr & CR_RLD) {
100
+ /* Also set the limit if the LRD bit is set */
101
+ /* If IOVW bit is set then set the timer value */
102
+ ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
103
+ ptimer_set_limit(s->timer_cmp, s->lr, 0);
104
+ } else if (s->cr & CR_IOVW) {
105
+ /* If IOVW bit is set then set the timer value */
106
+ ptimer_set_count(s->timer_reload, s->lr);
107
+ }
108
+ /*
109
+ * Commit the change to s->timer_reload, so it can propagate. Otherwise
110
+ * the timer interrupt may not fire properly. The commit must happen
111
+ * before calling imx_epit_reload_compare_timer(), which reads
112
+ * s->timer_reload internally again.
113
+ */
114
+ ptimer_transaction_commit(s->timer_reload);
115
+ imx_epit_reload_compare_timer(s);
116
+ ptimer_transaction_commit(s->timer_cmp);
117
+}
118
+
119
+static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value)
120
+{
121
+ s->cmp = value;
122
+
123
+ ptimer_transaction_begin(s->timer_cmp);
124
+ imx_epit_reload_compare_timer(s);
125
+ ptimer_transaction_commit(s->timer_cmp);
126
+}
127
+
128
static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
129
unsigned size)
130
{
131
IMXEPITState *s = IMX_EPIT(opaque);
132
- uint64_t oldcr;
133
134
DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset >> 2),
135
(uint32_t)value);
136
137
switch (offset >> 2) {
138
case 0: /* CR */
139
-
140
- oldcr = s->cr;
141
- s->cr = value & 0x03ffffff;
142
- if (s->cr & CR_SWR) {
143
- /* handle the reset */
144
- imx_epit_reset(s, false);
145
- }
146
-
147
- /*
148
- * The interrupt state can change due to:
149
- * - reset clears both SR.OCIF and CR.OCIE
150
- * - write to CR.EN or CR.OCIE
151
- */
152
- imx_epit_update_int(s);
153
-
154
- /*
155
- * TODO: could we 'break' here for reset? following operations appear
156
- * to duplicate the work imx_epit_reset() already did.
157
- */
158
-
159
- ptimer_transaction_begin(s->timer_cmp);
160
- ptimer_transaction_begin(s->timer_reload);
161
-
162
- /* Update the frequency. Has been done already in case of a reset. */
163
- if (!(s->cr & CR_SWR)) {
164
- imx_epit_set_freq(s);
165
- }
166
-
167
- if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
168
- if (s->cr & CR_ENMOD) {
169
- if (s->cr & CR_RLD) {
170
- ptimer_set_limit(s->timer_reload, s->lr, 1);
171
- ptimer_set_limit(s->timer_cmp, s->lr, 1);
172
- } else {
173
- ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
174
- ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
175
- }
176
- }
177
-
178
- imx_epit_reload_compare_timer(s);
179
- ptimer_run(s->timer_reload, 0);
180
- if (s->cr & CR_OCIEN) {
181
- ptimer_run(s->timer_cmp, 0);
182
- } else {
183
- ptimer_stop(s->timer_cmp);
184
- }
185
- } else if (!(s->cr & CR_EN)) {
186
- /* stop both timers */
187
- ptimer_stop(s->timer_reload);
188
- ptimer_stop(s->timer_cmp);
189
- } else if (s->cr & CR_OCIEN) {
190
- if (!(oldcr & CR_OCIEN)) {
191
- imx_epit_reload_compare_timer(s);
192
- ptimer_run(s->timer_cmp, 0);
193
- }
194
- } else {
195
- ptimer_stop(s->timer_cmp);
196
- }
197
-
198
- ptimer_transaction_commit(s->timer_cmp);
199
- ptimer_transaction_commit(s->timer_reload);
200
+ imx_epit_write_cr(s, (uint32_t)value);
201
break;
202
203
- case 1: /* SR - ACK*/
204
- /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
205
- if (value & SR_OCIF) {
206
- s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
207
- imx_epit_update_int(s);
208
- }
209
+ case 1: /* SR */
210
+ imx_epit_write_sr(s, (uint32_t)value);
211
break;
212
213
- case 2: /* LR - set ticks */
214
- s->lr = value;
215
-
216
- ptimer_transaction_begin(s->timer_cmp);
217
- ptimer_transaction_begin(s->timer_reload);
218
- if (s->cr & CR_RLD) {
219
- /* Also set the limit if the LRD bit is set */
220
- /* If IOVW bit is set then set the timer value */
221
- ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
222
- ptimer_set_limit(s->timer_cmp, s->lr, 0);
223
- } else if (s->cr & CR_IOVW) {
224
- /* If IOVW bit is set then set the timer value */
225
- ptimer_set_count(s->timer_reload, s->lr);
226
- }
227
- /*
228
- * Commit the change to s->timer_reload, so it can propagate. Otherwise
229
- * the timer interrupt may not fire properly. The commit must happen
230
- * before calling imx_epit_reload_compare_timer(), which reads
231
- * s->timer_reload internally again.
232
- */
233
- ptimer_transaction_commit(s->timer_reload);
234
- imx_epit_reload_compare_timer(s);
235
- ptimer_transaction_commit(s->timer_cmp);
236
+ case 2: /* LR */
237
+ imx_epit_write_lr(s, (uint32_t)value);
238
break;
239
240
case 3: /* CMP */
241
- s->cmp = value;
242
-
243
- ptimer_transaction_begin(s->timer_cmp);
244
- imx_epit_reload_compare_timer(s);
245
- ptimer_transaction_commit(s->timer_cmp);
246
-
247
+ imx_epit_write_cmp(s, (uint32_t)value);
248
break;
249
250
default:
251
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
252
HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset);
253
-
254
break;
255
}
256
}
257
+
258
static void imx_epit_cmp(void *opaque)
259
{
260
IMXEPITState *s = IMX_EPIT(opaque);
311
--
261
--
312
2.20.1
262
2.25.1
313
314
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
2
3
Follow the model set up for contiguous loads. This handles
3
The CNT register is a read-only register. There is no need to
4
watchpoints correctly for contiguous stores, recognizing the
4
store it's value, it can be calculated on demand.
5
exception before any changes to memory.
5
The calculated frequency is needed temporarily only.
6
6
7
Note that this is a migration compatibility break for all boards
8
types that use the EPIT peripheral.
9
10
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200508154359.7494-16-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
target/arm/sve_helper.c | 285 ++++++++++++++++++++++------------------
14
include/hw/timer/imx_epit.h | 2 -
13
1 file changed, 159 insertions(+), 126 deletions(-)
15
hw/timer/imx_epit.c | 73 ++++++++++++++-----------------------
16
2 files changed, 28 insertions(+), 47 deletions(-)
14
17
15
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
18
diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h
16
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/sve_helper.c
20
--- a/include/hw/timer/imx_epit.h
18
+++ b/target/arm/sve_helper.c
21
+++ b/include/hw/timer/imx_epit.h
19
@@ -XXX,XX +XXX,XX @@ static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
22
@@ -XXX,XX +XXX,XX @@ struct IMXEPITState {
20
*(TYPEE *)(vd + H(reg_off)) = val; \
23
uint32_t sr;
24
uint32_t lr;
25
uint32_t cmp;
26
- uint32_t cnt;
27
28
- uint32_t freq;
29
qemu_irq irq;
30
};
31
32
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/timer/imx_epit.c
35
+++ b/hw/timer/imx_epit.c
36
@@ -XXX,XX +XXX,XX @@ static void imx_epit_update_int(IMXEPITState *s)
37
}
21
}
38
}
22
39
23
+#define DO_ST_HOST(NAME, H, TYPEE, TYPEM, HOST) \
40
-/*
24
+static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
41
- * Must be called from within a ptimer_transaction_begin/commit block
25
+{ HOST(host, (TYPEM)*(TYPEE *)(vd + H(reg_off))); }
42
- * for both s->timer_cmp and s->timer_reload.
26
+
43
- */
27
#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \
44
-static void imx_epit_set_freq(IMXEPITState *s)
28
static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
45
+static uint32_t imx_epit_get_freq(IMXEPITState *s)
29
target_ulong addr, uintptr_t ra) \
46
{
30
@@ -XXX,XX +XXX,XX @@ DO_LD_PRIM_1(ld1bdu, , uint64_t, uint8_t)
47
- uint32_t clksrc;
31
DO_LD_PRIM_1(ld1bds, , uint64_t, int8_t)
48
- uint32_t prescaler;
32
49
-
33
#define DO_ST_PRIM_1(NAME, H, TE, TM) \
50
- clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS);
34
+ DO_ST_HOST(st1##NAME, H, TE, TM, stb_p) \
51
- prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS);
35
DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra)
52
-
36
53
- s->freq = imx_ccm_get_clock_frequency(s->ccm,
37
DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t)
54
- imx_epit_clocks[clksrc]) / prescaler;
38
@@ -XXX,XX +XXX,XX @@ DO_ST_PRIM_1(bd, , uint64_t, uint8_t)
55
-
39
DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra)
56
- DPRINTF("Setting ptimer frequency to %u\n", s->freq);
40
57
-
41
#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \
58
- if (s->freq) {
42
+ DO_ST_HOST(st1##NAME##_be, H, TE, TM, ST##_be_p) \
59
- ptimer_set_freq(s->timer_reload, s->freq);
43
+ DO_ST_HOST(st1##NAME##_le, H, TE, TM, ST##_le_p) \
60
- ptimer_set_freq(s->timer_cmp, s->freq);
44
DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \
61
- }
45
DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra)
62
+ uint32_t clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS);
46
63
+ uint32_t prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS);
47
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_LDNF1_2(dd, MO_64, MO_64)
64
+ uint32_t f_in = imx_ccm_get_clock_frequency(s->ccm, imx_epit_clocks[clksrc]);
48
#undef DO_LDFF1_LDNF1_2
65
+ uint32_t freq = f_in / prescaler;
66
+ DPRINTF("ptimer frequency is %u\n", freq);
67
+ return freq;
68
}
49
69
50
/*
70
/*
51
- * Common helpers for all contiguous 1,2,3,4-register predicated stores.
71
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reset(IMXEPITState *s, bool is_hard_reset)
52
+ * Common helper for all contiguous 1,2,3,4-register predicated stores.
72
s->sr = 0;
53
*/
73
s->lr = EPIT_TIMER_MAX;
54
-static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
74
s->cmp = 0;
55
- uint32_t desc, const uintptr_t ra,
75
- s->cnt = 0;
56
- const int esize, const int msize,
76
ptimer_transaction_begin(s->timer_cmp);
57
- sve_ldst1_tlb_fn *tlb_fn)
77
ptimer_transaction_begin(s->timer_reload);
58
+
78
- /* stop both timers */
59
+static inline QEMU_ALWAYS_INLINE
60
+void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, uint32_t desc,
61
+ const uintptr_t retaddr, const int esz,
62
+ const int msz, const int N,
63
+ sve_ldst1_host_fn *host_fn,
64
+ sve_ldst1_tlb_fn *tlb_fn)
65
{
66
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
67
- intptr_t i, oprsz = simd_oprsz(desc);
68
- void *vd = &env->vfp.zregs[rd];
69
+ const intptr_t reg_max = simd_oprsz(desc);
70
+ intptr_t reg_off, reg_last, mem_off;
71
+ SVEContLdSt info;
72
+ void *host;
73
+ int i, flags;
74
75
- for (i = 0; i < oprsz; ) {
76
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
77
- do {
78
- if (pg & 1) {
79
- tlb_fn(env, vd, i, addr, ra);
80
+ /* Find the active elements. */
81
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, N << msz)) {
82
+ /* The entire predicate was false; no store occurs. */
83
+ return;
84
+ }
85
+
86
+ /* Probe the page(s). Exit with exception for any invalid page. */
87
+ sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_STORE, retaddr);
88
+
89
+ /* Handle watchpoints for all active elements. */
90
+ sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, N << msz,
91
+ BP_MEM_WRITE, retaddr);
92
+
93
+ /* TODO: MTE check. */
94
+
95
+ flags = info.page[0].flags | info.page[1].flags;
96
+ if (unlikely(flags != 0)) {
97
+#ifdef CONFIG_USER_ONLY
98
+ g_assert_not_reached();
99
+#else
100
+ /*
101
+ * At least one page includes MMIO.
102
+ * Any bus operation can fail with cpu_transaction_failed,
103
+ * which for ARM will raise SyncExternal. We cannot avoid
104
+ * this fault and will leave with the store incomplete.
105
+ */
106
+ mem_off = info.mem_off_first[0];
107
+ reg_off = info.reg_off_first[0];
108
+ reg_last = info.reg_off_last[1];
109
+ if (reg_last < 0) {
110
+ reg_last = info.reg_off_split;
111
+ if (reg_last < 0) {
112
+ reg_last = info.reg_off_last[0];
113
}
114
- i += esize, pg >>= esize;
115
- addr += msize;
116
- } while (i & 15);
117
+ }
118
+
119
+ do {
120
+ uint64_t pg = vg[reg_off >> 6];
121
+ do {
122
+ if ((pg >> (reg_off & 63)) & 1) {
123
+ for (i = 0; i < N; ++i) {
124
+ tlb_fn(env, &env->vfp.zregs[(rd + i) & 31], reg_off,
125
+ addr + mem_off + (i << msz), retaddr);
126
+ }
127
+ }
128
+ reg_off += 1 << esz;
129
+ mem_off += N << msz;
130
+ } while (reg_off & 63);
131
+ } while (reg_off <= reg_last);
132
+ return;
133
+#endif
134
+ }
135
+
136
+ mem_off = info.mem_off_first[0];
137
+ reg_off = info.reg_off_first[0];
138
+ reg_last = info.reg_off_last[0];
139
+ host = info.page[0].host;
140
+
141
+ while (reg_off <= reg_last) {
142
+ uint64_t pg = vg[reg_off >> 6];
143
+ do {
144
+ if ((pg >> (reg_off & 63)) & 1) {
145
+ for (i = 0; i < N; ++i) {
146
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
147
+ host + mem_off + (i << msz));
148
+ }
149
+ }
150
+ reg_off += 1 << esz;
151
+ mem_off += N << msz;
152
+ } while (reg_off <= reg_last && (reg_off & 63));
153
+ }
154
+
79
+
155
+ /*
80
+ /*
156
+ * Use the slow path to manage the cross-page misalignment.
81
+ * The reset switches off the input clock, so even if the CR.EN is still
157
+ * But we know this is RAM and cannot trap.
82
+ * set, the timers are no longer running.
158
+ */
83
+ */
159
+ mem_off = info.mem_off_split;
84
+ assert(imx_epit_get_freq(s) == 0);
160
+ if (unlikely(mem_off >= 0)) {
85
ptimer_stop(s->timer_cmp);
161
+ reg_off = info.reg_off_split;
86
ptimer_stop(s->timer_reload);
162
+ for (i = 0; i < N; ++i) {
87
- /* compute new frequency */
163
+ tlb_fn(env, &env->vfp.zregs[(rd + i) & 31], reg_off,
88
- imx_epit_set_freq(s);
164
+ addr + mem_off + (i << msz), retaddr);
89
/* init both timers to EPIT_TIMER_MAX */
165
+ }
90
ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
166
+ }
91
ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
167
+
92
- if (s->freq && (s->cr & CR_EN)) {
168
+ mem_off = info.mem_off_first[1];
93
- /* if the timer is still enabled, restart it */
169
+ if (unlikely(mem_off >= 0)) {
94
- ptimer_run(s->timer_reload, 0);
170
+ reg_off = info.reg_off_first[1];
95
- }
171
+ reg_last = info.reg_off_last[1];
96
ptimer_transaction_commit(s->timer_cmp);
172
+ host = info.page[1].host;
97
ptimer_transaction_commit(s->timer_reload);
173
+
174
+ do {
175
+ uint64_t pg = vg[reg_off >> 6];
176
+ do {
177
+ if ((pg >> (reg_off & 63)) & 1) {
178
+ for (i = 0; i < N; ++i) {
179
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
180
+ host + mem_off + (i << msz));
181
+ }
182
+ }
183
+ reg_off += 1 << esz;
184
+ mem_off += N << msz;
185
+ } while (reg_off & 63);
186
+ } while (reg_off <= reg_last);
187
}
188
}
98
}
189
99
190
-static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
100
-static uint32_t imx_epit_update_count(IMXEPITState *s)
191
- uint32_t desc, const uintptr_t ra,
192
- const int esize, const int msize,
193
- sve_ldst1_tlb_fn *tlb_fn)
194
-{
101
-{
195
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
102
- s->cnt = ptimer_get_count(s->timer_reload);
196
- intptr_t i, oprsz = simd_oprsz(desc);
197
- void *d1 = &env->vfp.zregs[rd];
198
- void *d2 = &env->vfp.zregs[(rd + 1) & 31];
199
-
103
-
200
- for (i = 0; i < oprsz; ) {
104
- return s->cnt;
201
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
202
- do {
203
- if (pg & 1) {
204
- tlb_fn(env, d1, i, addr, ra);
205
- tlb_fn(env, d2, i, addr + msize, ra);
206
- }
207
- i += esize, pg >>= esize;
208
- addr += 2 * msize;
209
- } while (i & 15);
210
- }
211
-}
105
-}
212
-
106
-
213
-static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
107
static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
214
- uint32_t desc, const uintptr_t ra,
108
{
215
- const int esize, const int msize,
109
IMXEPITState *s = IMX_EPIT(opaque);
216
- sve_ldst1_tlb_fn *tlb_fn)
110
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
217
-{
111
break;
218
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
112
219
- intptr_t i, oprsz = simd_oprsz(desc);
113
case 4: /* CNT */
220
- void *d1 = &env->vfp.zregs[rd];
114
- imx_epit_update_count(s);
221
- void *d2 = &env->vfp.zregs[(rd + 1) & 31];
115
- reg_value = s->cnt;
222
- void *d3 = &env->vfp.zregs[(rd + 2) & 31];
116
+ reg_value = ptimer_get_count(s->timer_reload);
223
-
117
break;
224
- for (i = 0; i < oprsz; ) {
118
225
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
119
default:
226
- do {
120
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reload_compare_timer(IMXEPITState *s)
227
- if (pg & 1) {
121
{
228
- tlb_fn(env, d1, i, addr, ra);
122
if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) {
229
- tlb_fn(env, d2, i, addr + msize, ra);
123
/* if the compare feature is on and timers are running */
230
- tlb_fn(env, d3, i, addr + 2 * msize, ra);
124
- uint32_t tmp = imx_epit_update_count(s);
231
- }
125
+ uint32_t tmp = ptimer_get_count(s->timer_reload);
232
- i += esize, pg >>= esize;
126
uint64_t next;
233
- addr += 3 * msize;
127
if (tmp > s->cmp) {
234
- } while (i & 15);
128
/* It'll fire in this round of the timer */
235
- }
129
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reload_compare_timer(IMXEPITState *s)
236
-}
130
237
-
131
static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
238
-static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
132
{
239
- uint32_t desc, const uintptr_t ra,
133
+ uint32_t freq = 0;
240
- const int esize, const int msize,
134
uint32_t oldcr = s->cr;
241
- sve_ldst1_tlb_fn *tlb_fn)
135
242
-{
136
s->cr = value & 0x03ffffff;
243
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
137
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
244
- intptr_t i, oprsz = simd_oprsz(desc);
138
ptimer_transaction_begin(s->timer_cmp);
245
- void *d1 = &env->vfp.zregs[rd];
139
ptimer_transaction_begin(s->timer_reload);
246
- void *d2 = &env->vfp.zregs[(rd + 1) & 31];
140
247
- void *d3 = &env->vfp.zregs[(rd + 2) & 31];
141
- /* Update the frequency. Has been done already in case of a reset. */
248
- void *d4 = &env->vfp.zregs[(rd + 3) & 31];
142
+ /*
249
-
143
+ * Update the frequency. In case of a reset the input clock was
250
- for (i = 0; i < oprsz; ) {
144
+ * switched off, so this can be skipped.
251
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
145
+ */
252
- do {
146
if (!(s->cr & CR_SWR)) {
253
- if (pg & 1) {
147
- imx_epit_set_freq(s);
254
- tlb_fn(env, d1, i, addr, ra);
148
+ freq = imx_epit_get_freq(s);
255
- tlb_fn(env, d2, i, addr + msize, ra);
149
+ if (freq) {
256
- tlb_fn(env, d3, i, addr + 2 * msize, ra);
150
+ ptimer_set_freq(s->timer_reload, freq);
257
- tlb_fn(env, d4, i, addr + 3 * msize, ra);
151
+ ptimer_set_freq(s->timer_cmp, freq);
258
- }
152
+ }
259
- i += esize, pg >>= esize;
153
}
260
- addr += 4 * msize;
154
261
- } while (i & 15);
155
- if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
262
- }
156
+ if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
263
-}
157
if (s->cr & CR_ENMOD) {
264
-
158
if (s->cr & CR_RLD) {
265
-#define DO_STN_1(N, NAME, ESIZE) \
159
ptimer_set_limit(s->timer_reload, s->lr, 1);
266
-void QEMU_FLATTEN HELPER(sve_st##N##NAME##_r) \
160
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps imx_epit_ops = {
267
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
161
268
+#define DO_STN_1(N, NAME, ESZ) \
162
static const VMStateDescription vmstate_imx_timer_epit = {
269
+void HELPER(sve_st##N##NAME##_r)(CPUARMState *env, void *vg, \
163
.name = TYPE_IMX_EPIT,
270
+ target_ulong addr, uint32_t desc) \
164
- .version_id = 2,
271
{ \
165
- .minimum_version_id = 2,
272
- sve_st##N##_r(env, vg, addr, desc, GETPC(), ESIZE, 1, \
166
+ .version_id = 3,
273
- sve_st1##NAME##_tlb); \
167
+ .minimum_version_id = 3,
274
+ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, N, \
168
.fields = (VMStateField[]) {
275
+ sve_st1##NAME##_host, sve_st1##NAME##_tlb); \
169
VMSTATE_UINT32(cr, IMXEPITState),
276
}
170
VMSTATE_UINT32(sr, IMXEPITState),
277
171
VMSTATE_UINT32(lr, IMXEPITState),
278
-#define DO_STN_2(N, NAME, ESIZE, MSIZE) \
172
VMSTATE_UINT32(cmp, IMXEPITState),
279
-void QEMU_FLATTEN HELPER(sve_st##N##NAME##_le_r) \
173
- VMSTATE_UINT32(cnt, IMXEPITState),
280
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
174
- VMSTATE_UINT32(freq, IMXEPITState),
281
+#define DO_STN_2(N, NAME, ESZ, MSZ) \
175
VMSTATE_PTIMER(timer_reload, IMXEPITState),
282
+void HELPER(sve_st##N##NAME##_le_r)(CPUARMState *env, void *vg, \
176
VMSTATE_PTIMER(timer_cmp, IMXEPITState),
283
+ target_ulong addr, uint32_t desc) \
177
VMSTATE_END_OF_LIST()
284
{ \
285
- sve_st##N##_r(env, vg, addr, desc, GETPC(), ESIZE, MSIZE, \
286
- sve_st1##NAME##_le_tlb); \
287
+ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, \
288
+ sve_st1##NAME##_le_host, sve_st1##NAME##_le_tlb); \
289
} \
290
-void QEMU_FLATTEN HELPER(sve_st##N##NAME##_be_r) \
291
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
292
+void HELPER(sve_st##N##NAME##_be_r)(CPUARMState *env, void *vg, \
293
+ target_ulong addr, uint32_t desc) \
294
{ \
295
- sve_st##N##_r(env, vg, addr, desc, GETPC(), ESIZE, MSIZE, \
296
- sve_st1##NAME##_be_tlb); \
297
+ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, \
298
+ sve_st1##NAME##_be_host, sve_st1##NAME##_be_tlb); \
299
}
300
301
-DO_STN_1(1, bb, 1)
302
-DO_STN_1(1, bh, 2)
303
-DO_STN_1(1, bs, 4)
304
-DO_STN_1(1, bd, 8)
305
-DO_STN_1(2, bb, 1)
306
-DO_STN_1(3, bb, 1)
307
-DO_STN_1(4, bb, 1)
308
+DO_STN_1(1, bb, MO_8)
309
+DO_STN_1(1, bh, MO_16)
310
+DO_STN_1(1, bs, MO_32)
311
+DO_STN_1(1, bd, MO_64)
312
+DO_STN_1(2, bb, MO_8)
313
+DO_STN_1(3, bb, MO_8)
314
+DO_STN_1(4, bb, MO_8)
315
316
-DO_STN_2(1, hh, 2, 2)
317
-DO_STN_2(1, hs, 4, 2)
318
-DO_STN_2(1, hd, 8, 2)
319
-DO_STN_2(2, hh, 2, 2)
320
-DO_STN_2(3, hh, 2, 2)
321
-DO_STN_2(4, hh, 2, 2)
322
+DO_STN_2(1, hh, MO_16, MO_16)
323
+DO_STN_2(1, hs, MO_32, MO_16)
324
+DO_STN_2(1, hd, MO_64, MO_16)
325
+DO_STN_2(2, hh, MO_16, MO_16)
326
+DO_STN_2(3, hh, MO_16, MO_16)
327
+DO_STN_2(4, hh, MO_16, MO_16)
328
329
-DO_STN_2(1, ss, 4, 4)
330
-DO_STN_2(1, sd, 8, 4)
331
-DO_STN_2(2, ss, 4, 4)
332
-DO_STN_2(3, ss, 4, 4)
333
-DO_STN_2(4, ss, 4, 4)
334
+DO_STN_2(1, ss, MO_32, MO_32)
335
+DO_STN_2(1, sd, MO_64, MO_32)
336
+DO_STN_2(2, ss, MO_32, MO_32)
337
+DO_STN_2(3, ss, MO_32, MO_32)
338
+DO_STN_2(4, ss, MO_32, MO_32)
339
340
-DO_STN_2(1, dd, 8, 8)
341
-DO_STN_2(2, dd, 8, 8)
342
-DO_STN_2(3, dd, 8, 8)
343
-DO_STN_2(4, dd, 8, 8)
344
+DO_STN_2(1, dd, MO_64, MO_64)
345
+DO_STN_2(2, dd, MO_64, MO_64)
346
+DO_STN_2(3, dd, MO_64, MO_64)
347
+DO_STN_2(4, dd, MO_64, MO_64)
348
349
#undef DO_STN_1
350
#undef DO_STN_2
351
--
178
--
352
2.20.1
179
2.25.1
353
354
diff view generated by jsdifflib
1
From: Joel Stanley <joel@jms.id.au>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
2
3
The AST2600 handles this differently with the extra 'hardlock' state, so
3
- fix #1263 for CR writes
4
move the testing to the soc specific class' write callback.
4
- rework compare time handling
5
- The compare timer has to run even if CR.OCIEN is not set,
6
as SR.OCIF must be updated.
7
- The compare timer fires exactly once when the
8
compare value is less than the current value, but the
9
reload values is less than the compare value.
10
- The compare timer will never fire if the reload value is
11
less than the compare value. Disable it in this case.
5
12
6
Signed-off-by: Joel Stanley <joel@jms.id.au>
13
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
14
[PMM: fixed minor style nits]
8
Message-id: 20200505090136.341426-1-joel@jms.id.au
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
17
---
11
hw/misc/aspeed_sdmc.c | 55 +++++++++++++++++++++++++++++++++++--------
18
hw/timer/imx_epit.c | 192 ++++++++++++++++++++++++++------------------
12
1 file changed, 45 insertions(+), 10 deletions(-)
19
1 file changed, 116 insertions(+), 76 deletions(-)
13
20
14
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
21
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
15
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/misc/aspeed_sdmc.c
23
--- a/hw/timer/imx_epit.c
17
+++ b/hw/misc/aspeed_sdmc.c
24
+++ b/hw/timer/imx_epit.c
18
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@
19
26
* Originally written by Hans Jiang
20
/* Protection Key Register */
27
* Updated by Peter Chubb
21
#define R_PROT (0x00 / 4)
28
* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
22
+#define PROT_UNLOCKED 0x01
29
+ * Updated by Axel Heider
23
+#define PROT_HARDLOCKED 0x10 /* AST2600 */
30
*
24
+#define PROT_SOFTLOCKED 0x00
31
* This code is licensed under GPL version 2 or later. See
25
+
32
* the COPYING file in the top-level directory.
26
#define PROT_KEY_UNLOCK 0xFC600309
33
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
27
+#define PROT_KEY_HARDLOCK 0xDEADDEAD /* AST2600 */
34
return reg_value;
28
35
}
29
/* Configuration Register */
36
30
#define R_CONF (0x04 / 4)
37
-/* Must be called from ptimer_transaction_begin/commit block for s->timer_cmp */
31
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
38
-static void imx_epit_reload_compare_timer(IMXEPITState *s)
32
return;
39
+/*
40
+ * Must be called from a ptimer_transaction_begin/commit block for
41
+ * s->timer_cmp, but outside of a transaction block of s->timer_reload,
42
+ * so the proper counter value is read.
43
+ */
44
+static void imx_epit_update_compare_timer(IMXEPITState *s)
45
{
46
- if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) {
47
- /* if the compare feature is on and timers are running */
48
- uint32_t tmp = ptimer_get_count(s->timer_reload);
49
- uint64_t next;
50
- if (tmp > s->cmp) {
51
- /* It'll fire in this round of the timer */
52
- next = tmp - s->cmp;
53
- } else { /* catch it next time around */
54
- next = tmp - s->cmp + ((s->cr & CR_RLD) ? EPIT_TIMER_MAX : s->lr);
55
+ uint64_t counter = 0;
56
+ bool is_oneshot = false;
57
+ /*
58
+ * The compare timer only has to run if the timer peripheral is active
59
+ * and there is an input clock, Otherwise it can be switched off.
60
+ */
61
+ bool is_active = (s->cr & CR_EN) && imx_epit_get_freq(s);
62
+ if (is_active) {
63
+ /*
64
+ * Calculate next timeout for compare timer. Reading the reload
65
+ * counter returns proper results only if pending transactions
66
+ * on it are committed here. Otherwise stale values are be read.
67
+ */
68
+ counter = ptimer_get_count(s->timer_reload);
69
+ uint64_t limit = ptimer_get_limit(s->timer_cmp);
70
+ /*
71
+ * The compare timer is a periodic timer if the limit is at least
72
+ * the compare value. Otherwise it may fire at most once in the
73
+ * current round.
74
+ */
75
+ bool is_oneshot = (limit >= s->cmp);
76
+ if (counter >= s->cmp) {
77
+ /* The compare timer fires in the current round. */
78
+ counter -= s->cmp;
79
+ } else if (!is_oneshot) {
80
+ /*
81
+ * The compare timer fires after a reload, as it is below the
82
+ * compare value already in this round. Note that the counter
83
+ * value calculated below can be above the 32-bit limit, which
84
+ * is legal here because the compare timer is an internal
85
+ * helper ptimer only.
86
+ */
87
+ counter += limit - s->cmp;
88
+ } else {
89
+ /*
90
+ * The compare timer won't fire in this round, and the limit is
91
+ * set to a value below the compare value. This practically means
92
+ * it will never fire, so it can be switched off.
93
+ */
94
+ is_active = false;
95
}
96
- ptimer_set_count(s->timer_cmp, next);
33
}
97
}
34
98
+
35
- if (addr == R_PROT) {
99
+ /*
36
- s->regs[addr] = (data == PROT_KEY_UNLOCK) ? 1 : 0;
100
+ * Set the compare timer and let it run, or stop it. This is agnostic
37
- return;
101
+ * of CR.OCIEN bit, as this bit affects interrupt generation only. The
102
+ * compare timer needs to run even if no interrupts are to be generated,
103
+ * because the SR.OCIF bit must be updated also.
104
+ * Note that the timer might already be stopped or be running with
105
+ * counter values. However, finding out when an update is needed and
106
+ * when not is not trivial. It's much easier applying the setting again,
107
+ * as this does not harm either and the overhead is negligible.
108
+ */
109
+ if (is_active) {
110
+ ptimer_set_count(s->timer_cmp, counter);
111
+ ptimer_run(s->timer_cmp, is_oneshot ? 1 : 0);
112
+ } else {
113
+ ptimer_stop(s->timer_cmp);
114
+ }
115
+
116
}
117
118
static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
119
{
120
- uint32_t freq = 0;
121
uint32_t oldcr = s->cr;
122
123
s->cr = value & 0x03ffffff;
124
125
if (s->cr & CR_SWR) {
126
- /* handle the reset */
127
+ /*
128
+ * Reset clears CR.SWR again. It does not touch CR.EN, but the timers
129
+ * are still stopped because the input clock is disabled.
130
+ */
131
imx_epit_reset(s, false);
132
+ } else {
133
+ uint32_t freq;
134
+ uint32_t toggled_cr_bits = oldcr ^ s->cr;
135
+ /* re-initialize the limits if CR.RLD has changed */
136
+ bool set_limit = toggled_cr_bits & CR_RLD;
137
+ /* set the counter if the timer got just enabled and CR.ENMOD is set */
138
+ bool is_switched_on = (toggled_cr_bits & s->cr) & CR_EN;
139
+ bool set_counter = is_switched_on && (s->cr & CR_ENMOD);
140
+
141
+ ptimer_transaction_begin(s->timer_cmp);
142
+ ptimer_transaction_begin(s->timer_reload);
143
+ freq = imx_epit_get_freq(s);
144
+ if (freq) {
145
+ ptimer_set_freq(s->timer_reload, freq);
146
+ ptimer_set_freq(s->timer_cmp, freq);
147
+ }
148
+
149
+ if (set_limit || set_counter) {
150
+ uint64_t limit = (s->cr & CR_RLD) ? s->lr : EPIT_TIMER_MAX;
151
+ ptimer_set_limit(s->timer_reload, limit, set_counter ? 1 : 0);
152
+ if (set_limit) {
153
+ ptimer_set_limit(s->timer_cmp, limit, 0);
154
+ }
155
+ }
156
+ /*
157
+ * If there is an input clock and the peripheral is enabled, then
158
+ * ensure the wall clock timer is ticking. Otherwise stop the timers.
159
+ * The compare timer will be updated later.
160
+ */
161
+ if (freq && (s->cr & CR_EN)) {
162
+ ptimer_run(s->timer_reload, 0);
163
+ } else {
164
+ ptimer_stop(s->timer_reload);
165
+ }
166
+ /* Commit changes to reload timer, so they can propagate. */
167
+ ptimer_transaction_commit(s->timer_reload);
168
+ /* Update compare timer based on the committed reload timer value. */
169
+ imx_epit_update_compare_timer(s);
170
+ ptimer_transaction_commit(s->timer_cmp);
171
}
172
173
/*
174
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
175
* - write to CR.EN or CR.OCIE
176
*/
177
imx_epit_update_int(s);
178
-
179
- /*
180
- * TODO: could we 'break' here for reset? following operations appear
181
- * to duplicate the work imx_epit_reset() already did.
182
- */
183
-
184
- ptimer_transaction_begin(s->timer_cmp);
185
- ptimer_transaction_begin(s->timer_reload);
186
-
187
- /*
188
- * Update the frequency. In case of a reset the input clock was
189
- * switched off, so this can be skipped.
190
- */
191
- if (!(s->cr & CR_SWR)) {
192
- freq = imx_epit_get_freq(s);
193
- if (freq) {
194
- ptimer_set_freq(s->timer_reload, freq);
195
- ptimer_set_freq(s->timer_cmp, freq);
196
- }
38
- }
197
- }
39
-
198
-
40
- if (!s->regs[R_PROT]) {
199
- if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
41
- qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
200
- if (s->cr & CR_ENMOD) {
42
- return;
201
- if (s->cr & CR_RLD) {
202
- ptimer_set_limit(s->timer_reload, s->lr, 1);
203
- ptimer_set_limit(s->timer_cmp, s->lr, 1);
204
- } else {
205
- ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
206
- ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
207
- }
208
- }
209
-
210
- imx_epit_reload_compare_timer(s);
211
- ptimer_run(s->timer_reload, 0);
212
- if (s->cr & CR_OCIEN) {
213
- ptimer_run(s->timer_cmp, 0);
214
- } else {
215
- ptimer_stop(s->timer_cmp);
216
- }
217
- } else if (!(s->cr & CR_EN)) {
218
- /* stop both timers */
219
- ptimer_stop(s->timer_reload);
220
- ptimer_stop(s->timer_cmp);
221
- } else if (s->cr & CR_OCIEN) {
222
- if (!(oldcr & CR_OCIEN)) {
223
- imx_epit_reload_compare_timer(s);
224
- ptimer_run(s->timer_cmp, 0);
225
- }
226
- } else {
227
- ptimer_stop(s->timer_cmp);
43
- }
228
- }
44
-
229
-
45
asc->write(s, addr, data);
230
- ptimer_transaction_commit(s->timer_cmp);
46
}
231
- ptimer_transaction_commit(s->timer_reload);
47
232
}
48
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
233
49
static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg,
234
static void imx_epit_write_sr(IMXEPITState *s, uint32_t value)
50
uint32_t data)
235
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_lr(IMXEPITState *s, uint32_t value)
51
{
236
/* If IOVW bit is set then set the timer value */
52
+ if (reg == R_PROT) {
237
ptimer_set_count(s->timer_reload, s->lr);
53
+ s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
238
}
54
+ return;
239
- /*
55
+ }
240
- * Commit the change to s->timer_reload, so it can propagate. Otherwise
56
+
241
- * the timer interrupt may not fire properly. The commit must happen
57
+ if (!s->regs[R_PROT]) {
242
- * before calling imx_epit_reload_compare_timer(), which reads
58
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
243
- * s->timer_reload internally again.
59
+ return;
244
- */
60
+ }
245
+ /* Commit the changes to s->timer_reload, so they can propagate. */
61
+
246
ptimer_transaction_commit(s->timer_reload);
62
switch (reg) {
247
- imx_epit_reload_compare_timer(s);
63
case R_CONF:
248
+ /* Update the compare timer based on the committed reload timer value. */
64
data = aspeed_2400_sdmc_compute_conf(s, data);
249
+ imx_epit_update_compare_timer(s);
65
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
250
ptimer_transaction_commit(s->timer_cmp);
66
static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg,
251
}
67
uint32_t data)
252
68
{
253
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value)
69
+ if (reg == R_PROT) {
254
{
70
+ s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
255
s->cmp = value;
71
+ return;
256
72
+ }
257
+ /* Update the compare timer based on the committed reload timer value. */
73
+
258
ptimer_transaction_begin(s->timer_cmp);
74
+ if (!s->regs[R_PROT]) {
259
- imx_epit_reload_compare_timer(s);
75
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
260
+ imx_epit_update_compare_timer(s);
76
+ return;
261
ptimer_transaction_commit(s->timer_cmp);
77
+ }
262
}
78
+
263
79
switch (reg) {
264
@@ -XXX,XX +XXX,XX @@ static void imx_epit_cmp(void *opaque)
80
case R_CONF:
265
{
81
data = aspeed_2500_sdmc_compute_conf(s, data);
266
IMXEPITState *s = IMX_EPIT(opaque);
82
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
267
83
static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,
268
+ /* The cmp ptimer can't be running when the peripheral is disabled */
84
uint32_t data)
269
+ assert(s->cr & CR_EN);
85
{
270
+
86
+ if (s->regs[R_PROT] == PROT_HARDLOCKED) {
271
DPRINTF("sr was %d\n", s->sr);
87
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n",
272
/* Set interrupt status bit SR.OCIF and update the interrupt state */
88
+ __func__);
273
s->sr |= SR_OCIF;
89
+ return;
90
+ }
91
+
92
+ if (reg != R_PROT && s->regs[R_PROT] == PROT_SOFTLOCKED) {
93
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
94
+ return;
95
+ }
96
+
97
switch (reg) {
98
+ case R_PROT:
99
+ if (data == PROT_KEY_UNLOCK) {
100
+ data = PROT_UNLOCKED;
101
+ } else if (data == PROT_KEY_HARDLOCK) {
102
+ data = PROT_HARDLOCKED;
103
+ } else {
104
+ data = PROT_SOFTLOCKED;
105
+ }
106
+ break;
107
case R_CONF:
108
data = aspeed_2600_sdmc_compute_conf(s, data);
109
break;
110
--
274
--
111
2.20.1
275
2.25.1
112
113
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
Calling access_el3_aa32ns() works for AArch32 only cores
3
Fix these:
4
but it does not handle 32-bit EL2 on top of 64-bit EL3
5
for mixed 32/64-bit cores.
6
4
7
Merge access_el3_aa32ns_aa64any() into access_el3_aa32ns()
5
WARNING: Block comments use a leading /* on a separate line
8
and only use the latter.
6
WARNING: Block comments use * on subsequent lines
7
WARNING: Block comments use a trailing */ on a separate line
9
8
10
Fixes: 68e9c2fe65 ("target-arm: Add VTCR_EL2")
9
Signed-off-by: Fabiano Rosas <farosas@suse.de>
11
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
Reviewed-by: Claudio Fontana <cfontana@suse.de>
12
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
11
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
13
Message-id: 20200505141729.31930-2-edgar.iglesias@gmail.com
12
Message-id: 20221213190537.511-2-farosas@suse.de
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
14
---
17
target/arm/helper.c | 30 +++++++-----------------------
15
target/arm/helper.c | 323 +++++++++++++++++++++++++++++---------------
18
1 file changed, 7 insertions(+), 23 deletions(-)
16
1 file changed, 215 insertions(+), 108 deletions(-)
19
17
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
18
diff --git a/target/arm/helper.c b/target/arm/helper.c
21
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper.c
20
--- a/target/arm/helper.c
23
+++ b/target/arm/helper.c
21
+++ b/target/arm/helper.c
24
@@ -XXX,XX +XXX,XX @@ void init_cpreg_list(ARMCPU *cpu)
22
@@ -XXX,XX +XXX,XX @@ uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
25
}
23
static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
26
24
uint64_t v)
27
/*
25
{
28
- * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
26
- /* Raw write of a coprocessor register (as needed for migration, etc).
29
- * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
27
+ /*
30
- *
28
+ * Raw write of a coprocessor register (as needed for migration, etc).
31
- * access_el3_aa32ns: Used to check AArch32 register views.
29
* Note that constant registers are treated as write-ignored; the
32
- * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
30
* caller should check for success by whether a readback gives the
33
+ * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
31
* value written.
34
*/
32
@@ -XXX,XX +XXX,XX @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
35
static CPAccessResult access_el3_aa32ns(CPUARMState *env,
33
36
const ARMCPRegInfo *ri,
34
static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
37
bool isread)
35
{
38
{
36
- /* Return true if the regdef would cause an assertion if you called
39
- bool secure = arm_is_secure_below_el3(env);
37
+ /*
40
-
38
+ * Return true if the regdef would cause an assertion if you called
41
- assert(!arm_el_is_aa64(env, 3));
39
* read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
42
- if (secure) {
40
* program bug for it not to have the NO_RAW flag).
43
+ if (!is_a64(env) && arm_current_el(env) == 3 &&
41
* NB that returning false here doesn't necessarily mean that calling
44
+ arm_is_secure_below_el3(env)) {
42
@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu)
45
return CP_ACCESS_TRAP_UNCATEGORIZED;
43
if (ri->type & ARM_CP_NO_RAW) {
46
}
44
continue;
45
}
46
- /* Write value and confirm it reads back as written
47
+ /*
48
+ * Write value and confirm it reads back as written
49
* (to catch read-only registers and partially read-only
50
* registers where the incoming migration value doesn't match)
51
*/
52
@@ -XXX,XX +XXX,XX @@ static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
53
54
void init_cpreg_list(ARMCPU *cpu)
55
{
56
- /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
57
+ /*
58
+ * Initialise the cpreg_tuples[] array based on the cp_regs hash.
59
* Note that we require cpreg_tuples[] to be sorted by key ID.
60
*/
61
GList *keys;
62
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_el3_aa32ns(CPUARMState *env,
47
return CP_ACCESS_OK;
63
return CP_ACCESS_OK;
48
}
64
}
49
65
50
-static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
66
-/* Some secure-only AArch32 registers trap to EL3 if used from
51
- const ARMCPRegInfo *ri,
67
+/*
52
- bool isread)
68
+ * Some secure-only AArch32 registers trap to EL3 if used from
53
-{
54
- if (!arm_el_is_aa64(env, 3)) {
55
- return access_el3_aa32ns(env, ri, isread);
56
- }
57
- return CP_ACCESS_OK;
58
-}
59
-
60
/* Some secure-only AArch32 registers trap to EL3 if used from
61
* Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
69
* Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
62
* Note that an access from Secure EL1 can only happen if EL3 is AArch64.
70
* Note that an access from Secure EL1 can only happen if EL3 is AArch64.
63
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
71
* We assume that the .access field is set to PL1_RW.
64
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
72
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
65
{ .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
73
return CP_ACCESS_TRAP_UNCATEGORIZED;
66
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
74
}
67
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
75
68
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
76
-/* Check for traps to performance monitor registers, which are controlled
77
+/*
78
+ * Check for traps to performance monitor registers, which are controlled
79
* by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
80
*/
81
static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
82
@@ -XXX,XX +XXX,XX @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
83
ARMCPU *cpu = env_archcpu(env);
84
85
if (raw_read(env, ri) != value) {
86
- /* Unlike real hardware the qemu TLB uses virtual addresses,
87
+ /*
88
+ * Unlike real hardware the qemu TLB uses virtual addresses,
89
* not modified virtual addresses, so this causes a TLB flush.
90
*/
91
tlb_flush(CPU(cpu));
92
@@ -XXX,XX +XXX,XX @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
93
94
if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA)
95
&& !extended_addresses_enabled(env)) {
96
- /* For VMSA (when not using the LPAE long descriptor page table
97
+ /*
98
+ * For VMSA (when not using the LPAE long descriptor page table
99
* format) this register includes the ASID, so do a TLB flush.
100
* For PMSA it is purely a process ID and no action is needed.
101
*/
102
@@ -XXX,XX +XXX,XX @@ static void tlbiipas2is_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
103
}
104
105
static const ARMCPRegInfo cp_reginfo[] = {
106
- /* Define the secure and non-secure FCSE identifier CP registers
107
+ /*
108
+ * Define the secure and non-secure FCSE identifier CP registers
109
* separately because there is no secure bank in V8 (no _EL3). This allows
110
* the secure register to be properly reset and migrated. There is also no
111
* v8 EL1 version of the register so the non-secure instance stands alone.
112
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
113
.access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
114
.fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
115
.resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
116
- /* Define the secure and non-secure context identifier CP registers
117
+ /*
118
+ * Define the secure and non-secure context identifier CP registers
119
* separately because there is no secure bank in V8 (no _EL3). This allows
120
* the secure register to be properly reset and migrated. In the
121
* non-secure case, the 32-bit register will have reset and migration
122
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
123
};
124
125
static const ARMCPRegInfo not_v8_cp_reginfo[] = {
126
- /* NB: Some of these registers exist in v8 but with more precise
127
+ /*
128
+ * NB: Some of these registers exist in v8 but with more precise
129
* definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
130
*/
131
/* MMU Domain access control / MPU write buffer control */
132
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
133
.writefn = dacr_write, .raw_writefn = raw_write,
134
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
135
offsetoflow32(CPUARMState, cp15.dacr_ns) } },
136
- /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
137
+ /*
138
+ * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
139
* For v6 and v5, these mappings are overly broad.
140
*/
141
{ .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
142
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
143
};
144
145
static const ARMCPRegInfo not_v6_cp_reginfo[] = {
146
- /* Not all pre-v6 cores implemented this WFI, so this is slightly
147
+ /*
148
+ * Not all pre-v6 cores implemented this WFI, so this is slightly
149
* over-broad.
150
*/
151
{ .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
152
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v6_cp_reginfo[] = {
153
};
154
155
static const ARMCPRegInfo not_v7_cp_reginfo[] = {
156
- /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
157
+ /*
158
+ * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
159
* is UNPREDICTABLE; we choose to NOP as most implementations do).
160
*/
161
{ .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
162
.access = PL1_W, .type = ARM_CP_WFI },
163
- /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
164
+ /*
165
+ * L1 cache lockdown. Not architectural in v6 and earlier but in practice
166
* implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
167
* OMAPCP will override this space.
168
*/
169
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
170
{ .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
171
.access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
172
.resetvalue = 0 },
173
- /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
174
+ /*
175
+ * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
176
* implementing it as RAZ means the "debug architecture version" bits
177
* will read as a reserved value, which should cause Linux to not try
178
* to use the debug hardware.
179
*/
180
{ .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
181
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
182
- /* MMU TLB control. Note that the wildcarding means we cover not just
183
+ /*
184
+ * MMU TLB control. Note that the wildcarding means we cover not just
185
* the unified TLB ops but also the dside/iside/inner-shareable variants.
186
*/
187
{ .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
188
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
189
190
/* In ARMv8 most bits of CPACR_EL1 are RES0. */
191
if (!arm_feature(env, ARM_FEATURE_V8)) {
192
- /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
193
+ /*
194
+ * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
195
* ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
196
* TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
197
*/
198
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
199
value |= R_CPACR_ASEDIS_MASK;
200
}
201
202
- /* VFPv3 and upwards with NEON implement 32 double precision
203
+ /*
204
+ * VFPv3 and upwards with NEON implement 32 double precision
205
* registers (D0-D31).
206
*/
207
if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) {
208
@@ -XXX,XX +XXX,XX @@ static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri)
209
210
static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
211
{
212
- /* Call cpacr_write() so that we reset with the correct RAO bits set
213
+ /*
214
+ * Call cpacr_write() so that we reset with the correct RAO bits set
215
* for our CPU features.
216
*/
217
cpacr_write(env, ri, 0);
218
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
219
{ .name = "MVA_prefetch",
220
.cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
221
.access = PL1_W, .type = ARM_CP_NOP },
222
- /* We need to break the TB after ISB to execute self-modifying code
223
+ /*
224
+ * We need to break the TB after ISB to execute self-modifying code
225
* correctly and also to take any pending interrupts immediately.
226
* So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
227
*/
228
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
229
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
230
offsetof(CPUARMState, cp15.ifar_ns) },
231
.resetvalue = 0, },
232
- /* Watchpoint Fault Address Register : should actually only be present
233
+ /*
234
+ * Watchpoint Fault Address Register : should actually only be present
235
* for 1136, 1176, 11MPCore.
236
*/
237
{ .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
238
@@ -XXX,XX +XXX,XX @@ static bool event_supported(uint16_t number)
239
static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
240
bool isread)
241
{
242
- /* Performance monitor registers user accessibility is controlled
243
+ /*
244
+ * Performance monitor registers user accessibility is controlled
245
* by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
246
* trapping to EL2 or EL3 for other accesses.
247
*/
248
@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
249
(MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP)
250
#define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD)
251
252
-/* Returns true if the counter (pass 31 for PMCCNTR) should count events using
253
+/*
254
+ * Returns true if the counter (pass 31 for PMCCNTR) should count events using
255
* the current EL, security state, and register configuration.
256
*/
257
static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
258
@@ -XXX,XX +XXX,XX @@ static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
259
static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
260
uint64_t value)
261
{
262
- /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
263
+ /*
264
+ * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
265
* PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
266
* meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
267
* accessed.
268
@@ -XXX,XX +XXX,XX @@ static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
269
env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK;
270
pmevcntr_op_finish(env, counter);
271
}
272
- /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
273
+ /*
274
+ * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
275
* PMSELR value is equal to or greater than the number of implemented
276
* counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
277
*/
278
@@ -XXX,XX +XXX,XX @@ static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri,
279
}
280
return ret;
281
} else {
282
- /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
283
- * are CONSTRAINED UNPREDICTABLE. */
284
+ /*
285
+ * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
286
+ * are CONSTRAINED UNPREDICTABLE.
287
+ */
288
return 0;
289
}
290
}
291
@@ -XXX,XX +XXX,XX @@ static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
292
static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
293
uint64_t value)
294
{
295
- /* Note that even though the AArch64 view of this register has bits
296
+ /*
297
+ * Note that even though the AArch64 view of this register has bits
298
* [10:0] all RES0 we can only mask the bottom 5, to comply with the
299
* architectural requirements for bits which are RES0 only in some
300
* contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
301
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
302
if (!arm_feature(env, ARM_FEATURE_EL2)) {
303
valid_mask &= ~SCR_HCE;
304
305
- /* On ARMv7, SMD (or SCD as it is called in v7) is only
306
+ /*
307
+ * On ARMv7, SMD (or SCD as it is called in v7) is only
308
* supported if EL2 exists. The bit is UNK/SBZP when
309
* EL2 is unavailable. In QEMU ARMv7, we force it to always zero
310
* when EL2 is unavailable.
311
@@ -XXX,XX +XXX,XX @@ static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
312
{
313
ARMCPU *cpu = env_archcpu(env);
314
315
- /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
316
+ /*
317
+ * Acquire the CSSELR index from the bank corresponding to the CCSIDR
318
* bank
319
*/
320
uint32_t index = A32_BANKED_REG_GET(env, csselr,
321
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
322
/* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
323
{ .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
324
.access = PL1_W, .type = ARM_CP_NOP },
325
- /* Performance monitors are implementation defined in v7,
326
+ /*
327
+ * Performance monitors are implementation defined in v7,
328
* but with an ARM recommended set of registers, which we
329
* follow.
330
*
331
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
332
.writefn = csselr_write, .resetvalue = 0,
333
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
334
offsetof(CPUARMState, cp15.csselr_ns) } },
335
- /* Auxiliary ID register: this actually has an IMPDEF value but for now
336
+ /*
337
+ * Auxiliary ID register: this actually has an IMPDEF value but for now
338
* just RAZ for all cores:
339
*/
340
{ .name = "AIDR", .state = ARM_CP_STATE_BOTH,
341
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
342
.access = PL1_R, .type = ARM_CP_CONST,
343
.accessfn = access_aa64_tid1,
344
.resetvalue = 0 },
345
- /* Auxiliary fault status registers: these also are IMPDEF, and we
346
+ /*
347
+ * Auxiliary fault status registers: these also are IMPDEF, and we
348
* choose to RAZ/WI for all cores.
349
*/
350
{ .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
351
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
352
.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
353
.access = PL1_RW, .accessfn = access_tvm_trvm,
69
.type = ARM_CP_CONST, .resetvalue = 0 },
354
.type = ARM_CP_CONST, .resetvalue = 0 },
70
{ .name = "VTTBR", .state = ARM_CP_STATE_AA32,
355
- /* MAIR can just read-as-written because we don't implement caches
71
.cp = 15, .opc1 = 6, .crm = 2,
356
+ /*
72
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
357
+ * MAIR can just read-as-written because we don't implement caches
73
.type = ARM_CP_CONST, .resetvalue = 0 },
358
* and so don't need to care about memory attributes.
74
{ .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
359
*/
75
.opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
360
{ .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
76
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
361
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
77
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
362
.opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
78
.type = ARM_CP_CONST, .resetvalue = 0 },
363
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
79
{ .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
364
.resetvalue = 0 },
80
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
365
- /* For non-long-descriptor page tables these are PRRR and NMRR;
366
+ /*
367
+ * For non-long-descriptor page tables these are PRRR and NMRR;
368
* regardless they still act as reads-as-written for QEMU.
369
*/
370
- /* MAIR0/1 are defined separately from their 64-bit counterpart which
371
+ /*
372
+ * MAIR0/1 are defined separately from their 64-bit counterpart which
373
* allows them to assign the correct fieldoffset based on the endianness
374
* handled in the field definitions.
375
*/
376
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
377
static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
378
bool isread)
379
{
380
- /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
381
+ /*
382
+ * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
383
* Writable only at the highest implemented exception level.
384
*/
385
int el = arm_current_el(env);
386
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
387
const ARMCPRegInfo *ri,
388
bool isread)
389
{
390
- /* The AArch64 register view of the secure physical timer is
391
+ /*
392
+ * The AArch64 register view of the secure physical timer is
393
* always accessible from EL3, and configurably accessible from
394
* Secure EL1.
395
*/
396
@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
397
ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
398
399
if (gt->ctl & 1) {
400
- /* Timer enabled: calculate and set current ISTATUS, irq, and
401
+ /*
402
+ * Timer enabled: calculate and set current ISTATUS, irq, and
403
* reset timer to when ISTATUS next has to change
404
*/
405
uint64_t offset = timeridx == GTIMER_VIRT ?
406
@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
407
/* Next transition is when we hit cval */
408
nexttick = gt->cval + offset;
409
}
410
- /* Note that the desired next expiry time might be beyond the
411
+ /*
412
+ * Note that the desired next expiry time might be beyond the
413
* signed-64-bit range of a QEMUTimer -- in this case we just
414
* set the timer for as far in the future as possible. When the
415
* timer expires we will reset the timer for any remaining period.
416
@@ -XXX,XX +XXX,XX @@ static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
417
/* Enable toggled */
418
gt_recalc_timer(cpu, timeridx);
419
} else if ((oldval ^ value) & 2) {
420
- /* IMASK toggled: don't need to recalculate,
421
+ /*
422
+ * IMASK toggled: don't need to recalculate,
423
* just set the interrupt line based on ISTATUS
424
*/
425
int irqstate = (oldval & 4) && !(value & 2);
426
@@ -XXX,XX +XXX,XX @@ static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
427
}
428
429
static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
430
- /* Note that CNTFRQ is purely reads-as-written for the benefit
431
+ /*
432
+ * Note that CNTFRQ is purely reads-as-written for the benefit
433
* of software; writing it doesn't actually change the timer frequency.
434
* Our reset value matches the fixed frequency we implement the timer at.
435
*/
436
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
437
.readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read,
438
.writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write,
439
},
440
- /* Secure timer -- this is actually restricted to only EL3
441
+ /*
442
+ * Secure timer -- this is actually restricted to only EL3
443
* and configurably Secure-EL1 via the accessfn.
444
*/
445
{ .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
446
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
447
448
#else
449
450
-/* In user-mode most of the generic timer registers are inaccessible
451
+/*
452
+ * In user-mode most of the generic timer registers are inaccessible
453
* however modern kernels (4.12+) allow access to cntvct_el0
454
*/
455
456
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
457
{
458
ARMCPU *cpu = env_archcpu(env);
459
460
- /* Currently we have no support for QEMUTimer in linux-user so we
461
+ /*
462
+ * Currently we have no support for QEMUTimer in linux-user so we
463
* can't call gt_get_countervalue(env), instead we directly
464
* call the lower level functions.
465
*/
466
@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
467
bool isread)
468
{
469
if (ri->opc2 & 4) {
470
- /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in
471
+ /*
472
+ * The ATS12NSO* operations must trap to EL3 or EL2 if executed in
473
* Secure EL1 (which can only happen if EL3 is AArch64).
474
* They are simply UNDEF if executed from NS EL1.
475
* They function normally from EL2 or EL3.
476
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
477
}
478
}
479
} else {
480
- /* fsr is a DFSR/IFSR value for the short descriptor
481
+ /*
482
+ * fsr is a DFSR/IFSR value for the short descriptor
483
* translation table format (with WnR always clear).
484
* Convert it to a 32-bit PAR.
485
*/
486
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav8r_cp_reginfo[] = {
487
};
488
489
static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
490
- /* Reset for all these registers is handled in arm_cpu_reset(),
491
+ /*
492
+ * Reset for all these registers is handled in arm_cpu_reset(),
493
* because the PMSAv7 is also used by M-profile CPUs, which do
494
* not register cpregs but still need the state to be reset.
495
*/
496
@@ -XXX,XX +XXX,XX @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
497
}
498
499
if (arm_feature(env, ARM_FEATURE_LPAE)) {
500
- /* With LPAE the TTBCR could result in a change of ASID
501
+ /*
502
+ * With LPAE the TTBCR could result in a change of ASID
503
* via the TTBCR.A1 bit, so do a TLB flush.
504
*/
505
tlb_flush(CPU(cpu));
506
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
507
offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
508
};
509
510
-/* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
511
+/*
512
+ * Note that unlike TTBCR, writing to TTBCR2 does not require flushing
513
* qemu tlbs nor adjusting cached masks.
514
*/
515
static const ARMCPRegInfo ttbcr2_reginfo = {
516
@@ -XXX,XX +XXX,XX @@ static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
517
static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
518
uint64_t value)
519
{
520
- /* On OMAP there are registers indicating the max/min index of dcache lines
521
+ /*
522
+ * On OMAP there are registers indicating the max/min index of dcache lines
523
* containing a dirty line; cache flush operations have to reset these.
524
*/
525
env->cp15.c15_i_max = 0x000;
526
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo omap_cp_reginfo[] = {
527
.crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
528
.type = ARM_CP_NO_RAW,
529
.readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
530
- /* TODO: Peripheral port remap register:
531
+ /*
532
+ * TODO: Peripheral port remap register:
533
* On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
534
* base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
535
* when MMU is off.
536
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
537
.cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
538
.fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
539
.resetvalue = 0, },
540
- /* XScale specific cache-lockdown: since we have no cache we NOP these
541
+ /*
542
+ * XScale specific cache-lockdown: since we have no cache we NOP these
543
* and hope the guest does not really rely on cache behaviour.
544
*/
545
{ .name = "XSCALE_LOCK_ICACHE_LINE",
546
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
547
};
548
549
static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
550
- /* RAZ/WI the whole crn=15 space, when we don't have a more specific
551
+ /*
552
+ * RAZ/WI the whole crn=15 space, when we don't have a more specific
553
* implementation of this implementation-defined space.
554
* Ideally this should eventually disappear in favour of actually
555
* implementing the correct behaviour for all cores.
556
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
557
};
558
559
static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
560
- /* The cache test-and-clean instructions always return (1 << 30)
561
+ /*
562
+ * The cache test-and-clean instructions always return (1 << 30)
563
* to indicate that there are no dirty cache lines.
564
*/
565
{ .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
566
@@ -XXX,XX +XXX,XX @@ static uint64_t mpidr_read_val(CPUARMState *env)
567
568
if (arm_feature(env, ARM_FEATURE_V7MP)) {
569
mpidr |= (1U << 31);
570
- /* Cores which are uniprocessor (non-coherent)
571
+ /*
572
+ * Cores which are uniprocessor (non-coherent)
573
* but still implement the MP extensions set
574
* bit 30. (For instance, Cortex-R5).
575
*/
576
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri,
577
return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU);
578
}
579
580
-/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
581
+/*
582
+ * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
583
* Page D4-1736 (DDI0487A.b)
584
*/
585
586
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
587
static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
588
uint64_t value)
589
{
590
- /* Invalidate by VA, EL2
591
+ /*
592
+ * Invalidate by VA, EL2
593
* Currently handles both VAE2 and VALE2, since we don't support
594
* flush-last-level-only.
595
*/
596
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
597
static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
598
uint64_t value)
599
{
600
- /* Invalidate by VA, EL3
601
+ /*
602
+ * Invalidate by VA, EL3
603
* Currently handles both VAE3 and VALE3, since we don't support
604
* flush-last-level-only.
605
*/
606
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
607
static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
608
uint64_t value)
609
{
610
- /* Invalidate by VA, EL1&0 (AArch64 version).
611
+ /*
612
+ * Invalidate by VA, EL1&0 (AArch64 version).
613
* Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
614
* since we don't support flush-for-specific-ASID-only or
615
* flush-last-level-only.
616
@@ -XXX,XX +XXX,XX @@ static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
617
bool isread)
618
{
619
if (!(env->pstate & PSTATE_SP)) {
620
- /* Access to SP_EL0 is undefined if it's being used as
621
+ /*
622
+ * Access to SP_EL0 is undefined if it's being used as
623
* the stack pointer.
624
*/
625
return CP_ACCESS_TRAP_UNCATEGORIZED;
626
@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
627
}
628
629
if (raw_read(env, ri) == value) {
630
- /* Skip the TLB flush if nothing actually changed; Linux likes
631
+ /*
632
+ * Skip the TLB flush if nothing actually changed; Linux likes
633
* to do a lot of pointless SCTLR writes.
634
*/
635
return;
636
@@ -XXX,XX +XXX,XX @@ static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
637
}
638
639
static const ARMCPRegInfo v8_cp_reginfo[] = {
640
- /* Minimal set of EL0-visible registers. This will need to be expanded
641
+ /*
642
+ * Minimal set of EL0-visible registers. This will need to be expanded
643
* significantly for system emulation of AArch64 CPUs.
644
*/
645
{ .name = "NZCV", .state = ARM_CP_STATE_AA64,
646
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
647
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
648
.access = PL1_RW,
649
.fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
650
- /* We rely on the access checks not allowing the guest to write to the
651
+ /*
652
+ * We rely on the access checks not allowing the guest to write to the
653
* state field when SPSel indicates that it's being used as the stack
654
* pointer.
655
*/
656
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
657
if (arm_feature(env, ARM_FEATURE_EL3)) {
658
valid_mask &= ~HCR_HCD;
659
} else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
660
- /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
661
+ /*
662
+ * Architecturally HCR.TSC is RES0 if EL3 is not implemented.
663
* However, if we're using the SMC PSCI conduit then QEMU is
664
* effectively acting like EL3 firmware and so the guest at
665
* EL2 should retain the ability to prevent EL1 from being
666
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
667
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
668
.writefn = tlbi_aa64_vae2is_write },
669
#ifndef CONFIG_USER_ONLY
670
- /* Unlike the other EL2-related AT operations, these must
671
+ /*
672
+ * Unlike the other EL2-related AT operations, these must
673
* UNDEF from EL3 if EL2 is not implemented, which is why we
674
* define them here rather than with the rest of the AT ops.
675
*/
676
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
677
.access = PL2_W, .accessfn = at_s1e2_access,
678
.type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
679
.writefn = ats_write64 },
680
- /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
681
+ /*
682
+ * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
683
* if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
684
* with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
685
* to behave as if SCR.NS was 1.
686
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
687
.writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
688
{ .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
689
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
690
- /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
691
+ /*
692
+ * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
693
* reset values as IMPDEF. We choose to reset to 3 to comply with
694
* both ARMv7 and ARMv8.
695
*/
696
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
697
static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
698
bool isread)
699
{
700
- /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
701
+ /*
702
+ * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
703
* At Secure EL1 it traps to EL3 or EL2.
704
*/
705
if (arm_current_el(env) == 3) {
706
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
707
}
708
}
709
710
-/* We don't know until after realize whether there's a GICv3
711
+/*
712
+ * We don't know until after realize whether there's a GICv3
713
* attached, and that is what registers the gicv3 sysregs.
714
* So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
715
* at runtime.
716
@@ -XXX,XX +XXX,XX @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
717
}
718
#endif
719
720
-/* Shared logic between LORID and the rest of the LOR* registers.
721
+/*
722
+ * Shared logic between LORID and the rest of the LOR* registers.
723
* Secure state exclusion has already been dealt with.
724
*/
725
static CPAccessResult access_lor_ns(CPUARMState *env,
81
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
726
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
82
ARMCPRegInfo vpidr_regs[] = {
727
83
{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
728
define_arm_cp_regs(cpu, cp_reginfo);
84
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
729
if (!arm_feature(env, ARM_FEATURE_V8)) {
85
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
730
- /* Must go early as it is full of wildcards that may be
86
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
731
+ /*
87
.type = ARM_CP_CONST, .resetvalue = cpu->midr,
732
+ * Must go early as it is full of wildcards that may be
88
.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
733
* overridden by later definitions.
89
{ .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
734
*/
90
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
735
define_arm_cp_regs(cpu, not_v8_cp_reginfo);
91
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
736
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
92
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
737
.access = PL1_R, .type = ARM_CP_CONST,
93
.type = ARM_CP_NO_RAW,
738
.accessfn = access_aa32_tid3,
94
.writefn = arm_cp_write_ignore, .readfn = mpidr_read },
739
.resetvalue = cpu->isar.id_pfr0 },
95
REGINFO_SENTINEL
740
- /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
741
+ /*
742
+ * ID_PFR1 is not a plain ARM_CP_CONST because we don't know
743
* the value of the GIC field until after we define these regs.
744
*/
745
{ .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
746
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
747
748
define_arm_cp_regs(cpu, el3_regs);
749
}
750
- /* The behaviour of NSACR is sufficiently various that we don't
751
+ /*
752
+ * The behaviour of NSACR is sufficiently various that we don't
753
* try to describe it in a single reginfo:
754
* if EL3 is 64 bit, then trap to EL3 from S EL1,
755
* reads as constant 0xc00 from NS EL1 and NS EL2
756
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
757
if (cpu_isar_feature(aa32_jazelle, cpu)) {
758
define_arm_cp_regs(cpu, jazelle_regs);
759
}
760
- /* Slightly awkwardly, the OMAP and StrongARM cores need all of
761
+ /*
762
+ * Slightly awkwardly, the OMAP and StrongARM cores need all of
763
* cp15 crn=0 to be writes-ignored, whereas for other cores they should
764
* be read-only (ie write causes UNDEF exception).
765
*/
766
{
767
ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
768
- /* Pre-v8 MIDR space.
769
+ /*
770
+ * Pre-v8 MIDR space.
771
* Note that the MIDR isn't a simple constant register because
772
* of the TI925 behaviour where writes to another register can
773
* cause the MIDR value to change.
774
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
775
if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
776
arm_feature(env, ARM_FEATURE_STRONGARM)) {
777
size_t i;
778
- /* Register the blanket "writes ignored" value first to cover the
779
+ /*
780
+ * Register the blanket "writes ignored" value first to cover the
781
* whole space. Then update the specific ID registers to allow write
782
* access, so that they ignore writes rather than causing them to
783
* UNDEF.
784
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
785
.raw_writefn = raw_write,
786
};
787
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
788
- /* Normally we would always end the TB on an SCTLR write, but Linux
789
+ /*
790
+ * Normally we would always end the TB on an SCTLR write, but Linux
791
* arch/arm/mach-pxa/sleep.S expects two instructions following
792
* an MMU enable to execute from cache. Imitate this behaviour.
793
*/
794
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
795
void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
796
const ARMCPRegInfo *r, void *opaque)
797
{
798
- /* Define implementations of coprocessor registers.
799
+ /*
800
+ * Define implementations of coprocessor registers.
801
* We store these in a hashtable because typically
802
* there are less than 150 registers in a space which
803
* is 16*16*16*8*8 = 262144 in size.
804
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
805
default:
806
g_assert_not_reached();
807
}
808
- /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
809
+ /*
810
+ * The AArch64 pseudocode CheckSystemAccess() specifies that op1
811
* encodes a minimum access level for the register. We roll this
812
* runtime check into our general permission check code, so check
813
* here that the reginfo's specified permissions are strict enough
814
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
815
assert((r->access & ~mask) == 0);
816
}
817
818
- /* Check that the register definition has enough info to handle
819
+ /*
820
+ * Check that the register definition has enough info to handle
821
* reads and writes if they are permitted.
822
*/
823
if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) {
824
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
825
continue;
826
}
827
if (state == ARM_CP_STATE_AA32) {
828
- /* Under AArch32 CP registers can be common
829
+ /*
830
+ * Under AArch32 CP registers can be common
831
* (same for secure and non-secure world) or banked.
832
*/
833
char *name;
834
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
835
g_assert_not_reached();
836
}
837
} else {
838
- /* AArch64 registers get mapped to non-secure instance
839
- * of AArch32 */
840
+ /*
841
+ * AArch64 registers get mapped to non-secure instance
842
+ * of AArch32
843
+ */
844
add_cpreg_to_hashtable(cpu, r, opaque, state,
845
ARM_CP_SECSTATE_NS,
846
crm, opc1, opc2, r->name);
847
@@ -XXX,XX +XXX,XX @@ void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
848
849
static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
850
{
851
- /* Return true if it is not valid for us to switch to
852
+ /*
853
+ * Return true if it is not valid for us to switch to
854
* this CPU mode (ie all the UNPREDICTABLE cases in
855
* the ARM ARM CPSRWriteByInstr pseudocode).
856
*/
857
@@ -XXX,XX +XXX,XX @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
858
case ARM_CPU_MODE_UND:
859
case ARM_CPU_MODE_IRQ:
860
case ARM_CPU_MODE_FIQ:
861
- /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
862
+ /*
863
+ * Note that we don't implement the IMPDEF NSACR.RFR which in v7
864
* allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
865
*/
866
- /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
867
+ /*
868
+ * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
869
* and CPS are treated as illegal mode changes.
870
*/
871
if (write_type == CPSRWriteByInstr &&
872
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
873
env->GE = (val >> 16) & 0xf;
874
}
875
876
- /* In a V7 implementation that includes the security extensions but does
877
+ /*
878
+ * In a V7 implementation that includes the security extensions but does
879
* not include Virtualization Extensions the SCR.FW and SCR.AW bits control
880
* whether non-secure software is allowed to change the CPSR_F and CPSR_A
881
* bits respectively.
882
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
883
changed_daif = (env->daif ^ val) & mask;
884
885
if (changed_daif & CPSR_A) {
886
- /* Check to see if we are allowed to change the masking of async
887
+ /*
888
+ * Check to see if we are allowed to change the masking of async
889
* abort exceptions from a non-secure state.
890
*/
891
if (!(env->cp15.scr_el3 & SCR_AW)) {
892
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
893
}
894
895
if (changed_daif & CPSR_F) {
896
- /* Check to see if we are allowed to change the masking of FIQ
897
+ /*
898
+ * Check to see if we are allowed to change the masking of FIQ
899
* exceptions from a non-secure state.
900
*/
901
if (!(env->cp15.scr_el3 & SCR_FW)) {
902
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
903
mask &= ~CPSR_F;
904
}
905
906
- /* Check whether non-maskable FIQ (NMFI) support is enabled.
907
+ /*
908
+ * Check whether non-maskable FIQ (NMFI) support is enabled.
909
* If this bit is set software is not allowed to mask
910
* FIQs, but is allowed to set CPSR_F to 0.
911
*/
912
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
913
if (write_type != CPSRWriteRaw &&
914
((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
915
if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) {
916
- /* Note that we can only get here in USR mode if this is a
917
+ /*
918
+ * Note that we can only get here in USR mode if this is a
919
* gdb stub write; for this case we follow the architectural
920
* behaviour for guest writes in USR mode of ignoring an attempt
921
* to switch mode. (Those are caught by translate.c for writes
922
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
923
*/
924
mask &= ~CPSR_M;
925
} else if (bad_mode_switch(env, val & CPSR_M, write_type)) {
926
- /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
927
+ /*
928
+ * Attempt to switch to an invalid mode: this is UNPREDICTABLE in
929
* v7, and has defined behaviour in v8:
930
* + leave CPSR.M untouched
931
* + allow changes to the other CPSR fields
932
@@ -XXX,XX +XXX,XX @@ static void switch_mode(CPUARMState *env, int mode)
933
env->regs[14] = env->banked_r14[r14_bank_number(mode)];
934
}
935
936
-/* Physical Interrupt Target EL Lookup Table
937
+/*
938
+ * Physical Interrupt Target EL Lookup Table
939
*
940
* [ From ARM ARM section G1.13.4 (Table G1-15) ]
941
*
942
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
943
if (arm_feature(env, ARM_FEATURE_EL3)) {
944
rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
945
} else {
946
- /* Either EL2 is the highest EL (and so the EL2 register width
947
+ /*
948
+ * Either EL2 is the highest EL (and so the EL2 register width
949
* is given by is64); or there is no EL2 or EL3, in which case
950
* the value of 'rw' does not affect the table lookup anyway.
951
*/
952
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_64_to_32(CPUARMState *env)
953
env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
954
}
955
956
- /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
957
+ /*
958
+ * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
959
* mode, then we can copy to r8-r14. Otherwise, we copy to the
960
* FIQ bank for r8-r14.
961
*/
962
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
963
/* High vectors. When enabled, base address cannot be remapped. */
964
addr += 0xffff0000;
965
} else {
966
- /* ARM v7 architectures provide a vector base address register to remap
967
+ /*
968
+ * ARM v7 architectures provide a vector base address register to remap
969
* the interrupt vector table.
970
* This register is only followed in non-monitor mode, and is banked.
971
* Note: only bits 31:5 are valid.
972
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
973
aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
974
975
if (cur_el < new_el) {
976
- /* Entry vector offset depends on whether the implemented EL
977
+ /*
978
+ * Entry vector offset depends on whether the implemented EL
979
* immediately lower than the target level is using AArch32 or AArch64
980
*/
981
bool is_aa64;
982
@@ -XXX,XX +XXX,XX @@ static void handle_semihosting(CPUState *cs)
983
}
984
#endif
985
986
-/* Handle a CPU exception for A and R profile CPUs.
987
+/*
988
+ * Handle a CPU exception for A and R profile CPUs.
989
* Do any appropriate logging, handle PSCI calls, and then hand off
990
* to the AArch64-entry or AArch32-entry function depending on the
991
* target exception level's register width.
992
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
993
}
994
#endif
995
996
- /* Hooks may change global state so BQL should be held, also the
997
+ /*
998
+ * Hooks may change global state so BQL should be held, also the
999
* BQL needs to be held for any modification of
1000
* cs->interrupt_request.
1001
*/
1002
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
1003
};
1004
}
1005
1006
-/* Note that signed overflow is undefined in C. The following routines are
1007
- careful to use unsigned types where modulo arithmetic is required.
1008
- Failure to do so _will_ break on newer gcc. */
1009
+/*
1010
+ * Note that signed overflow is undefined in C. The following routines are
1011
+ * careful to use unsigned types where modulo arithmetic is required.
1012
+ * Failure to do so _will_ break on newer gcc.
1013
+ */
1014
1015
/* Signed saturating arithmetic. */
1016
1017
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
1018
return (a & mask) | (b & ~mask);
1019
}
1020
1021
-/* CRC helpers.
1022
+/*
1023
+ * CRC helpers.
1024
* The upper bytes of val (above the number specified by 'bytes') must have
1025
* been zeroed out by the caller.
1026
*/
1027
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
1028
return crc32c(acc, buf, bytes) ^ 0xffffffff;
1029
}
1030
1031
-/* Return the exception level to which FP-disabled exceptions should
1032
+/*
1033
+ * Return the exception level to which FP-disabled exceptions should
1034
* be taken, or 0 if FP is enabled.
1035
*/
1036
int fp_exception_el(CPUARMState *env, int cur_el)
1037
@@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el)
1038
#ifndef CONFIG_USER_ONLY
1039
uint64_t hcr_el2;
1040
1041
- /* CPACR and the CPTR registers don't exist before v6, so FP is
1042
+ /*
1043
+ * CPACR and the CPTR registers don't exist before v6, so FP is
1044
* always accessible
1045
*/
1046
if (!arm_feature(env, ARM_FEATURE_V6)) {
1047
@@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el)
1048
1049
hcr_el2 = arm_hcr_el2_eff(env);
1050
1051
- /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
1052
+ /*
1053
+ * The CPACR controls traps to EL1, or PL1 if we're 32 bit:
1054
* 0, 2 : trap EL0 and EL1/PL1 accesses
1055
* 1 : trap only EL0 accesses
1056
* 3 : trap no accesses
96
--
1057
--
97
2.20.1
1058
2.25.1
98
99
diff view generated by jsdifflib
1
From: Joel Stanley <joel@jms.id.au>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
This is a boot stub that is similar to the code u-boot runs, allowing
3
Fix the following:
4
the kernel to boot the secondary CPU.
5
4
6
u-boot works as follows:
5
ERROR: spaces required around that '|' (ctx:VxV)
6
ERROR: space required before the open parenthesis '('
7
ERROR: spaces required around that '+' (ctx:VxB)
8
ERROR: space prohibited between function name and open parenthesis '('
7
9
8
1. Initialises the SMP mailbox area in the SCU at 0x1e6e2180 with default values
10
(the last two still have some occurrences in macros which I left
11
behind because it might impact readability)
9
12
10
2. Copies a stub named 'mailbox_insn' from flash to the SCU, just above the
13
Signed-off-by: Fabiano Rosas <farosas@suse.de>
11
mailbox area
14
Reviewed-by: Claudio Fontana <cfontana@suse.de>
12
15
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
13
3. Sets AST_SMP_MBOX_FIELD_READY to a magic value to indicate the
16
Message-id: 20221213190537.511-3-farosas@suse.de
14
secondary can begin execution from the stub
15
16
4. The stub waits until the AST_SMP_MBOX_FIELD_GOSIGN register is set to
17
a magic value
18
19
5. Jumps to the address in AST_SMP_MBOX_FIELD_ENTRY, starting Linux
20
21
Linux indicates it is ready by writing the address of its entrypoint
22
function to AST_SMP_MBOX_FIELD_ENTRY and the 'go' magic number to
23
AST_SMP_MBOX_FIELD_GOSIGN. The secondary CPU sees this at step 4 and
24
breaks out of it's loop.
25
26
To be compatible, a fixed qemu stub is loaded into the mailbox area. As
27
qemu can ensure the stub is loaded before execution starts, we do not
28
need to emulate the AST_SMP_MBOX_FIELD_READY behaviour of u-boot. The
29
secondary CPU's program counter points to the beginning of the stub,
30
allowing qemu to start secondaries at step four.
31
32
Reboot behaviour is preserved by resetting AST_SMP_MBOX_FIELD_GOSIGN
33
when the secondaries are reset.
34
35
This is only configured when the system is booted with -kernel and qemu
36
does not execute u-boot first.
37
38
Reviewed-by: Cédric Le Goater <clg@kaod.org>
39
Tested-by: Cédric Le Goater <clg@kaod.org>
40
Signed-off-by: Joel Stanley <joel@jms.id.au>
41
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
42
---
18
---
43
hw/arm/aspeed.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++++
19
target/arm/helper.c | 42 +++++++++++++++++++++---------------------
44
1 file changed, 65 insertions(+)
20
1 file changed, 21 insertions(+), 21 deletions(-)
45
21
46
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
22
diff --git a/target/arm/helper.c b/target/arm/helper.c
47
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/aspeed.c
24
--- a/target/arm/helper.c
49
+++ b/hw/arm/aspeed.c
25
+++ b/target/arm/helper.c
50
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps max_ram_ops = {
26
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_list(gpointer key, gpointer opaque)
51
.endianness = DEVICE_NATIVE_ENDIAN,
27
uint32_t regidx = (uintptr_t)key;
28
const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
29
30
- if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
31
+ if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
32
cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
33
/* The value array need not be initialized at this point */
34
cpu->cpreg_array_len++;
35
@@ -XXX,XX +XXX,XX @@ static void count_cpreg(gpointer key, gpointer opaque)
36
37
ri = g_hash_table_lookup(cpu->cp_regs, key);
38
39
- if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
40
+ if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
41
cpu->cpreg_array_len++;
42
}
43
}
44
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
45
.resetfn = arm_cp_reset_ignore },
46
{ .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
47
.opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
48
- .access = PL0_R|PL1_W,
49
+ .access = PL0_R | PL1_W,
50
.fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
51
.resetvalue = 0},
52
{ .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
53
- .access = PL0_R|PL1_W,
54
+ .access = PL0_R | PL1_W,
55
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
56
offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
57
.resetfn = arm_cp_reset_ignore },
58
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
59
.resetvalue = 0 },
60
/* The cache ops themselves: these all NOP for QEMU */
61
{ .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
62
- .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
63
+ .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
64
{ .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
65
- .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
66
+ .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
67
{ .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
68
- .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
69
+ .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
70
{ .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
71
- .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
72
+ .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
73
{ .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
74
- .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
75
+ .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
76
{ .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
77
- .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
78
+ .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
52
};
79
};
53
80
54
+#define AST_SMP_MAILBOX_BASE 0x1e6e2180
81
static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
55
+#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
82
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
56
+#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
83
ARMCPRegInfo cbar = {
57
+#define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
84
.name = "CBAR",
58
+#define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
85
.cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
59
+#define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
86
- .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
60
+#define AST_SMP_MBOX_GOSIGN 0xabbaab00
87
+ .access = PL1_R | PL3_W, .resetvalue = cpu->reset_cbar,
61
+
88
.fieldoffset = offsetof(CPUARMState,
62
+static void aspeed_write_smpboot(ARMCPU *cpu,
89
cp15.c15_config_base_address)
63
+ const struct arm_boot_info *info)
90
};
64
+{
91
@@ -XXX,XX +XXX,XX @@ static void switch_mode(CPUARMState *env, int mode)
65
+ static const uint32_t poll_mailbox_ready[] = {
92
return;
66
+ /*
93
67
+ * r2 = per-cpu go sign value
94
if (old_mode == ARM_CPU_MODE_FIQ) {
68
+ * r1 = AST_SMP_MBOX_FIELD_ENTRY
95
- memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
69
+ * r0 = AST_SMP_MBOX_FIELD_GOSIGN
96
- memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
70
+ */
97
+ memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
71
+ 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
98
+ memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
72
+ 0xe21000ff, /* ands r0, r0, #255 */
99
} else if (mode == ARM_CPU_MODE_FIQ) {
73
+ 0xe59f201c, /* ldr r2, [pc, #28] */
100
- memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
74
+ 0xe1822000, /* orr r2, r2, r0 */
101
- memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
75
+
102
+ memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
76
+ 0xe59f1018, /* ldr r1, [pc, #24] */
103
+ memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
77
+ 0xe59f0018, /* ldr r0, [pc, #24] */
78
+
79
+ 0xe320f002, /* wfe */
80
+ 0xe5904000, /* ldr r4, [r0] */
81
+ 0xe1520004, /* cmp r2, r4 */
82
+ 0x1afffffb, /* bne <wfe> */
83
+ 0xe591f000, /* ldr pc, [r1] */
84
+ AST_SMP_MBOX_GOSIGN,
85
+ AST_SMP_MBOX_FIELD_ENTRY,
86
+ AST_SMP_MBOX_FIELD_GOSIGN,
87
+ };
88
+
89
+ rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
90
+ sizeof(poll_mailbox_ready),
91
+ info->smp_loader_start);
92
+}
93
+
94
+static void aspeed_reset_secondary(ARMCPU *cpu,
95
+ const struct arm_boot_info *info)
96
+{
97
+ AddressSpace *as = arm_boot_address_space(cpu, info);
98
+ CPUState *cs = CPU(cpu);
99
+
100
+ /* info->smp_bootreg_addr */
101
+ address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
102
+ MEMTXATTRS_UNSPECIFIED, NULL);
103
+ cpu_set_pc(cs, info->smp_loader_start);
104
+}
105
+
106
#define FIRMWARE_ADDR 0x0
107
108
static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
109
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
110
}
111
}
104
}
112
105
113
+ if (machine->kernel_filename && bmc->soc.num_cpus > 1) {
106
i = bank_number(old_mode);
114
+ /* With no u-boot we must set up a boot stub for the secondary CPU */
107
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
115
+ MemoryRegion *smpboot = g_new(MemoryRegion, 1);
108
RESULT(sum, n, 16); \
116
+ memory_region_init_ram(smpboot, OBJECT(bmc), "aspeed.smpboot",
109
if (sum >= 0) \
117
+ 0x80, &error_abort);
110
ge |= 3 << (n * 2); \
118
+ memory_region_add_subregion(get_system_memory(),
111
- } while(0)
119
+ AST_SMP_MAILBOX_BASE, smpboot);
112
+ } while (0)
120
+
113
121
+ aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
114
#define SARITH8(a, b, n, op) do { \
122
+ aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
115
int32_t sum; \
123
+ aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
116
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
124
+ }
117
RESULT(sum, n, 8); \
125
+
118
if (sum >= 0) \
126
aspeed_board_binfo.ram_size = ram_size;
119
ge |= 1 << n; \
127
aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM];
120
- } while(0)
128
aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus;
121
+ } while (0)
122
123
124
#define ADD16(a, b, n) SARITH16(a, b, n, +)
125
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
126
RESULT(sum, n, 16); \
127
if ((sum >> 16) == 1) \
128
ge |= 3 << (n * 2); \
129
- } while(0)
130
+ } while (0)
131
132
#define ADD8(a, b, n) do { \
133
uint32_t sum; \
134
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
135
RESULT(sum, n, 8); \
136
if ((sum >> 8) == 1) \
137
ge |= 1 << n; \
138
- } while(0)
139
+ } while (0)
140
141
#define SUB16(a, b, n) do { \
142
uint32_t sum; \
143
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
144
RESULT(sum, n, 16); \
145
if ((sum >> 16) == 0) \
146
ge |= 3 << (n * 2); \
147
- } while(0)
148
+ } while (0)
149
150
#define SUB8(a, b, n) do { \
151
uint32_t sum; \
152
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
153
RESULT(sum, n, 8); \
154
if ((sum >> 8) == 0) \
155
ge |= 1 << n; \
156
- } while(0)
157
+ } while (0)
158
159
#define PFX u
160
#define ARITH_GE
129
--
161
--
130
2.20.1
162
2.25.1
131
132
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
Since we converted back to cpu_*_data_ra, we do not need to
3
Fix this:
4
do this ourselves.
4
ERROR: braces {} are necessary for all arms of this statement
5
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Fabiano Rosas <farosas@suse.de>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Claudio Fontana <cfontana@suse.de>
8
Message-id: 20200508154359.7494-9-richard.henderson@linaro.org
8
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
9
Message-id: 20221213190537.511-4-farosas@suse.de
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
target/arm/sve_helper.c | 38 --------------------------------------
12
target/arm/helper.c | 67 ++++++++++++++++++++++++++++-----------------
12
1 file changed, 38 deletions(-)
13
1 file changed, 42 insertions(+), 25 deletions(-)
13
14
14
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/sve_helper.c
17
--- a/target/arm/helper.c
17
+++ b/target/arm/sve_helper.c
18
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static intptr_t max_for_page(target_ulong base, intptr_t mem_off,
19
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
19
return MIN(split, mem_max - mem_off) + mem_off;
20
env->CF = (val >> 29) & 1;
21
env->VF = (val << 3) & 0x80000000;
22
}
23
- if (mask & CPSR_Q)
24
+ if (mask & CPSR_Q) {
25
env->QF = ((val & CPSR_Q) != 0);
26
- if (mask & CPSR_T)
27
+ }
28
+ if (mask & CPSR_T) {
29
env->thumb = ((val & CPSR_T) != 0);
30
+ }
31
if (mask & CPSR_IT_0_1) {
32
env->condexec_bits &= ~3;
33
env->condexec_bits |= (val >> 25) & 3;
34
@@ -XXX,XX +XXX,XX @@ static void switch_mode(CPUARMState *env, int mode)
35
int i;
36
37
old_mode = env->uncached_cpsr & CPSR_M;
38
- if (mode == old_mode)
39
+ if (mode == old_mode) {
40
return;
41
+ }
42
43
if (old_mode == ARM_CPU_MODE_FIQ) {
44
memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
45
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
46
new_mode = ARM_CPU_MODE_UND;
47
addr = 0x04;
48
mask = CPSR_I;
49
- if (env->thumb)
50
+ if (env->thumb) {
51
offset = 2;
52
- else
53
+ } else {
54
offset = 4;
55
+ }
56
break;
57
case EXCP_SWI:
58
new_mode = ARM_CPU_MODE_SVC;
59
@@ -XXX,XX +XXX,XX @@ static inline uint16_t add16_sat(uint16_t a, uint16_t b)
60
61
res = a + b;
62
if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
63
- if (a & 0x8000)
64
+ if (a & 0x8000) {
65
res = 0x8000;
66
- else
67
+ } else {
68
res = 0x7fff;
69
+ }
70
}
71
return res;
20
}
72
}
21
73
@@ -XXX,XX +XXX,XX @@ static inline uint8_t add8_sat(uint8_t a, uint8_t b)
22
-#ifndef CONFIG_USER_ONLY
74
23
-/* These are normally defined only for CONFIG_USER_ONLY in <exec/cpu_ldst.h> */
75
res = a + b;
24
-static inline void set_helper_retaddr(uintptr_t ra) { }
76
if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
25
-static inline void clear_helper_retaddr(void) { }
77
- if (a & 0x80)
26
-#endif
78
+ if (a & 0x80) {
27
-
79
res = 0x80;
28
/*
80
- else
29
* The result of tlb_vaddr_to_host for user-only is just g2h(x),
81
+ } else {
30
* which is always non-null. Elide the useless test.
82
res = 0x7f;
31
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
83
+ }
32
return;
33
}
84
}
34
mem_off = reg_off >> diffsz;
85
return res;
35
- set_helper_retaddr(retaddr);
86
}
36
87
@@ -XXX,XX +XXX,XX @@ static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
37
/*
88
38
* If the (remaining) load is entirely within a single page, then:
89
res = a - b;
39
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
90
if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
40
if (test_host_page(host)) {
91
- if (a & 0x8000)
41
mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
92
+ if (a & 0x8000) {
42
tcg_debug_assert(mem_off == mem_max);
93
res = 0x8000;
43
- clear_helper_retaddr();
94
- else
44
/* After having taken any fault, zero leading inactive elements. */
95
+ } else {
45
swap_memzero(vd, reg_off);
96
res = 0x7fff;
46
return;
97
+ }
47
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
48
}
98
}
49
#endif
99
return res;
50
51
- clear_helper_retaddr();
52
memcpy(vd, &scratch, reg_max);
53
}
100
}
54
101
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
55
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
102
56
intptr_t i, oprsz = simd_oprsz(desc);
103
res = a - b;
57
ARMVectorReg scratch[2] = { };
104
if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
58
105
- if (a & 0x80)
59
- set_helper_retaddr(ra);
106
+ if (a & 0x80) {
60
for (i = 0; i < oprsz; ) {
107
res = 0x80;
61
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
108
- else
62
do {
109
+ } else {
63
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
110
res = 0x7f;
64
addr += 2 * size;
111
+ }
65
} while (i & 15);
66
}
112
}
67
- clear_helper_retaddr();
113
return res;
68
69
/* Wait until all exceptions have been raised to write back. */
70
memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
71
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
72
intptr_t i, oprsz = simd_oprsz(desc);
73
ARMVectorReg scratch[3] = { };
74
75
- set_helper_retaddr(ra);
76
for (i = 0; i < oprsz; ) {
77
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
78
do {
79
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
80
addr += 3 * size;
81
} while (i & 15);
82
}
83
- clear_helper_retaddr();
84
85
/* Wait until all exceptions have been raised to write back. */
86
memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
87
@@ -XXX,XX +XXX,XX @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
88
intptr_t i, oprsz = simd_oprsz(desc);
89
ARMVectorReg scratch[4] = { };
90
91
- set_helper_retaddr(ra);
92
for (i = 0; i < oprsz; ) {
93
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
94
do {
95
@@ -XXX,XX +XXX,XX @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
96
addr += 4 * size;
97
} while (i & 15);
98
}
99
- clear_helper_retaddr();
100
101
/* Wait until all exceptions have been raised to write back. */
102
memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
103
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
104
return;
105
}
106
mem_off = reg_off >> diffsz;
107
- set_helper_retaddr(retaddr);
108
109
/*
110
* If the (remaining) load is entirely within a single page, then:
111
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
112
if (test_host_page(host)) {
113
mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
114
tcg_debug_assert(mem_off == mem_max);
115
- clear_helper_retaddr();
116
/* After any fault, zero any leading inactive elements. */
117
swap_memzero(vd, reg_off);
118
return;
119
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
120
}
121
#endif
122
123
- clear_helper_retaddr();
124
record_fault(env, reg_off, reg_max);
125
}
114
}
126
115
@@ -XXX,XX +XXX,XX @@ static inline uint16_t add16_usat(uint16_t a, uint16_t b)
127
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
116
{
128
intptr_t i, oprsz = simd_oprsz(desc);
117
uint16_t res;
129
void *vd = &env->vfp.zregs[rd];
118
res = a + b;
130
119
- if (res < a)
131
- set_helper_retaddr(ra);
120
+ if (res < a) {
132
for (i = 0; i < oprsz; ) {
121
res = 0xffff;
133
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
122
+ }
134
do {
123
return res;
135
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
136
addr += msize;
137
} while (i & 15);
138
}
139
- clear_helper_retaddr();
140
}
124
}
141
125
142
static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
126
static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
143
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
127
{
144
void *d1 = &env->vfp.zregs[rd];
128
- if (a > b)
145
void *d2 = &env->vfp.zregs[(rd + 1) & 31];
129
+ if (a > b) {
146
130
return a - b;
147
- set_helper_retaddr(ra);
131
- else
148
for (i = 0; i < oprsz; ) {
132
+ } else {
149
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
133
return 0;
150
do {
134
+ }
151
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
152
addr += 2 * msize;
153
} while (i & 15);
154
}
155
- clear_helper_retaddr();
156
}
135
}
157
136
158
static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
137
static inline uint8_t add8_usat(uint8_t a, uint8_t b)
159
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
138
{
160
void *d2 = &env->vfp.zregs[(rd + 1) & 31];
139
uint8_t res;
161
void *d3 = &env->vfp.zregs[(rd + 2) & 31];
140
res = a + b;
162
141
- if (res < a)
163
- set_helper_retaddr(ra);
142
+ if (res < a) {
164
for (i = 0; i < oprsz; ) {
143
res = 0xff;
165
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
144
+ }
166
do {
145
return res;
167
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
168
addr += 3 * msize;
169
} while (i & 15);
170
}
171
- clear_helper_retaddr();
172
}
146
}
173
147
174
static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
148
static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
175
@@ -XXX,XX +XXX,XX @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
149
{
176
void *d3 = &env->vfp.zregs[(rd + 2) & 31];
150
- if (a > b)
177
void *d4 = &env->vfp.zregs[(rd + 3) & 31];
151
+ if (a > b) {
178
152
return a - b;
179
- set_helper_retaddr(ra);
153
- else
180
for (i = 0; i < oprsz; ) {
154
+ } else {
181
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
155
return 0;
182
do {
156
+ }
183
@@ -XXX,XX +XXX,XX @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
184
addr += 4 * msize;
185
} while (i & 15);
186
}
187
- clear_helper_retaddr();
188
}
157
}
189
158
190
#define DO_STN_1(N, NAME, ESIZE) \
159
#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
191
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
160
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
192
intptr_t i, oprsz = simd_oprsz(desc);
161
193
ARMVectorReg scratch = { };
162
static inline uint8_t do_usad(uint8_t a, uint8_t b)
194
163
{
195
- set_helper_retaddr(ra);
164
- if (a > b)
196
for (i = 0; i < oprsz; ) {
165
+ if (a > b) {
197
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
166
return a - b;
198
do {
167
- else
199
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
168
+ } else {
200
i += 4, pg >>= 4;
169
return b - a;
201
} while (i & 15);
170
+ }
202
}
203
- clear_helper_retaddr();
204
205
/* Wait until all exceptions have been raised to write back. */
206
memcpy(vd, &scratch, oprsz);
207
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
208
intptr_t i, oprsz = simd_oprsz(desc) / 8;
209
ARMVectorReg scratch = { };
210
211
- set_helper_retaddr(ra);
212
for (i = 0; i < oprsz; i++) {
213
uint8_t pg = *(uint8_t *)(vg + H1(i));
214
if (likely(pg & 1)) {
215
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
216
tlb_fn(env, &scratch, i * 8, base + (off << scale), ra);
217
}
218
}
219
- clear_helper_retaddr();
220
221
/* Wait until all exceptions have been raised to write back. */
222
memcpy(vd, &scratch, oprsz * 8);
223
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
224
reg_off = find_next_active(vg, 0, reg_max, MO_32);
225
if (likely(reg_off < reg_max)) {
226
/* Perform one normal read, which will fault or not. */
227
- set_helper_retaddr(ra);
228
addr = off_fn(vm, reg_off);
229
addr = base + (addr << scale);
230
tlb_fn(env, vd, reg_off, addr, ra);
231
232
/* The rest of the reads will be non-faulting. */
233
- clear_helper_retaddr();
234
}
235
236
/* After any fault, zero the leading predicated false elements. */
237
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
238
reg_off = find_next_active(vg, 0, reg_max, MO_64);
239
if (likely(reg_off < reg_max)) {
240
/* Perform one normal read, which will fault or not. */
241
- set_helper_retaddr(ra);
242
addr = off_fn(vm, reg_off);
243
addr = base + (addr << scale);
244
tlb_fn(env, vd, reg_off, addr, ra);
245
246
/* The rest of the reads will be non-faulting. */
247
- clear_helper_retaddr();
248
}
249
250
/* After any fault, zero the leading predicated false elements. */
251
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
252
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
253
intptr_t i, oprsz = simd_oprsz(desc);
254
255
- set_helper_retaddr(ra);
256
for (i = 0; i < oprsz; ) {
257
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
258
do {
259
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
260
i += 4, pg >>= 4;
261
} while (i & 15);
262
}
263
- clear_helper_retaddr();
264
}
171
}
265
172
266
static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
173
/* Unsigned sum of absolute byte differences. */
267
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
174
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
268
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
175
uint32_t mask;
269
intptr_t i, oprsz = simd_oprsz(desc) / 8;
176
270
177
mask = 0;
271
- set_helper_retaddr(ra);
178
- if (flags & 1)
272
for (i = 0; i < oprsz; i++) {
179
+ if (flags & 1) {
273
uint8_t pg = *(uint8_t *)(vg + H1(i));
180
mask |= 0xff;
274
if (likely(pg & 1)) {
181
- if (flags & 2)
275
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
182
+ }
276
tlb_fn(env, vd, i * 8, base + (off << scale), ra);
183
+ if (flags & 2) {
277
}
184
mask |= 0xff00;
278
}
185
- if (flags & 4)
279
- clear_helper_retaddr();
186
+ }
187
+ if (flags & 4) {
188
mask |= 0xff0000;
189
- if (flags & 8)
190
+ }
191
+ if (flags & 8) {
192
mask |= 0xff000000;
193
+ }
194
return (a & mask) | (b & ~mask);
280
}
195
}
281
196
282
#define DO_ST1_ZPZ_S(MEM, OFS) \
283
--
197
--
284
2.20.1
198
2.25.1
285
286
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
Now that we can pass 7 parameters, do not encode register
3
Signed-off-by: Fabiano Rosas <farosas@suse.de>
4
operands within simd_data.
4
Reviewed-by: Claudio Fontana <cfontana@suse.de>
5
5
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Message-id: 20221213190537.511-5-farosas@suse.de
7
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200507172352.15418-2-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
8
---
12
target/arm/helper-sve.h | 45 +++++++----
9
target/arm/m_helper.c | 16 ----------------
13
target/arm/sve_helper.c | 157 ++++++++++++++-----------------------
10
1 file changed, 16 deletions(-)
14
target/arm/translate-sve.c | 70 ++++++-----------
15
3 files changed, 114 insertions(+), 158 deletions(-)
16
11
17
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
12
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
18
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper-sve.h
14
--- a/target/arm/m_helper.c
20
+++ b/target/arm/helper-sve.h
15
+++ b/target/arm/m_helper.c
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_6(sve_fcadd_s, TCG_CALL_NO_RWG,
16
@@ -XXX,XX +XXX,XX @@
22
DEF_HELPER_FLAGS_6(sve_fcadd_d, TCG_CALL_NO_RWG,
23
void, ptr, ptr, ptr, ptr, ptr, i32)
24
25
-DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
26
-DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
27
-DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
28
+DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG,
29
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG,
31
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG,
33
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
34
35
-DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
36
-DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
37
-DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
38
+DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG,
39
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG,
41
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
42
+DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG,
43
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
44
45
-DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
46
-DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
47
-DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
48
+DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG,
49
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
50
+DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG,
51
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
52
+DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG,
53
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
54
55
-DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
56
-DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
57
-DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
58
+DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG,
59
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
60
+DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG,
61
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
62
+DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG,
63
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
64
65
-DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
66
-DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
67
-DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
68
+DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG,
69
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
70
+DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG,
71
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
72
+DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG,
73
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
74
75
DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
76
DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
77
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/target/arm/sve_helper.c
80
+++ b/target/arm/sve_helper.c
81
@@ -XXX,XX +XXX,XX @@ DO_ZPZ_FP(sve_ucvt_dd, uint64_t, , uint64_to_float64)
82
83
#undef DO_ZPZ_FP
84
85
-/* 4-operand predicated multiply-add. This requires 7 operands to pass
86
- * "properly", so we need to encode some of the registers into DESC.
87
- */
88
-QEMU_BUILD_BUG_ON(SIMD_DATA_SHIFT + 20 > 32);
89
-
90
-static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
91
+static void do_fmla_zpzzz_h(void *vd, void *vn, void *vm, void *va, void *vg,
92
+ float_status *status, uint32_t desc,
93
uint16_t neg1, uint16_t neg3)
94
{
95
intptr_t i = simd_oprsz(desc);
96
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
97
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
98
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
99
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
100
- void *vd = &env->vfp.zregs[rd];
101
- void *vn = &env->vfp.zregs[rn];
102
- void *vm = &env->vfp.zregs[rm];
103
- void *va = &env->vfp.zregs[ra];
104
uint64_t *g = vg;
105
106
do {
107
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
108
e1 = *(uint16_t *)(vn + H1_2(i)) ^ neg1;
109
e2 = *(uint16_t *)(vm + H1_2(i));
110
e3 = *(uint16_t *)(va + H1_2(i)) ^ neg3;
111
- r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status_f16);
112
+ r = float16_muladd(e1, e2, e3, 0, status);
113
*(uint16_t *)(vd + H1_2(i)) = r;
114
}
115
} while (i & 63);
116
} while (i != 0);
117
}
118
119
-void HELPER(sve_fmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
120
+void HELPER(sve_fmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
121
+ void *vg, void *status, uint32_t desc)
122
{
123
- do_fmla_zpzzz_h(env, vg, desc, 0, 0);
124
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0);
125
}
126
127
-void HELPER(sve_fmls_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
128
+void HELPER(sve_fmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
129
+ void *vg, void *status, uint32_t desc)
130
{
131
- do_fmla_zpzzz_h(env, vg, desc, 0x8000, 0);
132
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0);
133
}
134
135
-void HELPER(sve_fnmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
136
+void HELPER(sve_fnmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
137
+ void *vg, void *status, uint32_t desc)
138
{
139
- do_fmla_zpzzz_h(env, vg, desc, 0x8000, 0x8000);
140
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0x8000);
141
}
142
143
-void HELPER(sve_fnmls_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
144
+void HELPER(sve_fnmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
145
+ void *vg, void *status, uint32_t desc)
146
{
147
- do_fmla_zpzzz_h(env, vg, desc, 0, 0x8000);
148
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0x8000);
149
}
150
151
-static void do_fmla_zpzzz_s(CPUARMState *env, void *vg, uint32_t desc,
152
+static void do_fmla_zpzzz_s(void *vd, void *vn, void *vm, void *va, void *vg,
153
+ float_status *status, uint32_t desc,
154
uint32_t neg1, uint32_t neg3)
155
{
156
intptr_t i = simd_oprsz(desc);
157
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
158
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
159
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
160
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
161
- void *vd = &env->vfp.zregs[rd];
162
- void *vn = &env->vfp.zregs[rn];
163
- void *vm = &env->vfp.zregs[rm];
164
- void *va = &env->vfp.zregs[ra];
165
uint64_t *g = vg;
166
167
do {
168
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_s(CPUARMState *env, void *vg, uint32_t desc,
169
e1 = *(uint32_t *)(vn + H1_4(i)) ^ neg1;
170
e2 = *(uint32_t *)(vm + H1_4(i));
171
e3 = *(uint32_t *)(va + H1_4(i)) ^ neg3;
172
- r = float32_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
173
+ r = float32_muladd(e1, e2, e3, 0, status);
174
*(uint32_t *)(vd + H1_4(i)) = r;
175
}
176
} while (i & 63);
177
} while (i != 0);
178
}
179
180
-void HELPER(sve_fmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
181
+void HELPER(sve_fmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
182
+ void *vg, void *status, uint32_t desc)
183
{
184
- do_fmla_zpzzz_s(env, vg, desc, 0, 0);
185
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0);
186
}
187
188
-void HELPER(sve_fmls_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
189
+void HELPER(sve_fmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
190
+ void *vg, void *status, uint32_t desc)
191
{
192
- do_fmla_zpzzz_s(env, vg, desc, 0x80000000, 0);
193
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0);
194
}
195
196
-void HELPER(sve_fnmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
197
+void HELPER(sve_fnmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
198
+ void *vg, void *status, uint32_t desc)
199
{
200
- do_fmla_zpzzz_s(env, vg, desc, 0x80000000, 0x80000000);
201
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0x80000000);
202
}
203
204
-void HELPER(sve_fnmls_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
205
+void HELPER(sve_fnmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
206
+ void *vg, void *status, uint32_t desc)
207
{
208
- do_fmla_zpzzz_s(env, vg, desc, 0, 0x80000000);
209
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0x80000000);
210
}
211
212
-static void do_fmla_zpzzz_d(CPUARMState *env, void *vg, uint32_t desc,
213
+static void do_fmla_zpzzz_d(void *vd, void *vn, void *vm, void *va, void *vg,
214
+ float_status *status, uint32_t desc,
215
uint64_t neg1, uint64_t neg3)
216
{
217
intptr_t i = simd_oprsz(desc);
218
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
219
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
220
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
221
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
222
- void *vd = &env->vfp.zregs[rd];
223
- void *vn = &env->vfp.zregs[rn];
224
- void *vm = &env->vfp.zregs[rm];
225
- void *va = &env->vfp.zregs[ra];
226
uint64_t *g = vg;
227
228
do {
229
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_d(CPUARMState *env, void *vg, uint32_t desc,
230
e1 = *(uint64_t *)(vn + i) ^ neg1;
231
e2 = *(uint64_t *)(vm + i);
232
e3 = *(uint64_t *)(va + i) ^ neg3;
233
- r = float64_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
234
+ r = float64_muladd(e1, e2, e3, 0, status);
235
*(uint64_t *)(vd + i) = r;
236
}
237
} while (i & 63);
238
} while (i != 0);
239
}
240
241
-void HELPER(sve_fmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
242
+void HELPER(sve_fmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
243
+ void *vg, void *status, uint32_t desc)
244
{
245
- do_fmla_zpzzz_d(env, vg, desc, 0, 0);
246
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, 0);
247
}
248
249
-void HELPER(sve_fmls_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
250
+void HELPER(sve_fmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
251
+ void *vg, void *status, uint32_t desc)
252
{
253
- do_fmla_zpzzz_d(env, vg, desc, INT64_MIN, 0);
254
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, 0);
255
}
256
257
-void HELPER(sve_fnmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
258
+void HELPER(sve_fnmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
259
+ void *vg, void *status, uint32_t desc)
260
{
261
- do_fmla_zpzzz_d(env, vg, desc, INT64_MIN, INT64_MIN);
262
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, INT64_MIN);
263
}
264
265
-void HELPER(sve_fnmls_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
266
+void HELPER(sve_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
267
+ void *vg, void *status, uint32_t desc)
268
{
269
- do_fmla_zpzzz_d(env, vg, desc, 0, INT64_MIN);
270
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, INT64_MIN);
271
}
272
273
/* Two operand floating-point comparison controlled by a predicate.
274
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
275
* FP Complex Multiply
276
*/
17
*/
277
18
278
-QEMU_BUILD_BUG_ON(SIMD_DATA_SHIFT + 22 > 32);
19
#include "qemu/osdep.h"
279
-
20
-#include "qemu/units.h"
280
-void HELPER(sve_fcmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
21
-#include "target/arm/idau.h"
281
+void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
22
-#include "trace.h"
282
+ void *vg, void *status, uint32_t desc)
23
#include "cpu.h"
283
{
24
#include "internals.h"
284
intptr_t j, i = simd_oprsz(desc);
25
-#include "exec/gdbstub.h"
285
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
26
#include "exec/helper-proto.h"
286
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
27
-#include "qemu/host-utils.h"
287
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
28
#include "qemu/main-loop.h"
288
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
29
#include "qemu/bitops.h"
289
- unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
30
-#include "qemu/crc32c.h"
290
+ unsigned rot = simd_data(desc);
31
-#include "qemu/qemu-print.h"
291
bool flip = rot & 1;
32
#include "qemu/log.h"
292
float16 neg_imag, neg_real;
33
#include "exec/exec-all.h"
293
- void *vd = &env->vfp.zregs[rd];
34
-#include <zlib.h> /* For crc32 */
294
- void *vn = &env->vfp.zregs[rn];
35
-#include "semihosting/semihost.h"
295
- void *vm = &env->vfp.zregs[rm];
36
-#include "sysemu/cpus.h"
296
- void *va = &env->vfp.zregs[ra];
37
-#include "sysemu/kvm.h"
297
uint64_t *g = vg;
38
-#include "qemu/range.h"
298
39
-#include "qapi/qapi-commands-machine-target.h"
299
neg_imag = float16_set_sign(0, (rot & 2) != 0);
40
-#include "qapi/error.h"
300
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
41
-#include "qemu/guest-random.h"
301
42
#ifdef CONFIG_TCG
302
if (likely((pg >> (i & 63)) & 1)) {
43
-#include "arm_ldst.h"
303
d = *(float16 *)(va + H1_2(i));
44
#include "exec/cpu_ldst.h"
304
- d = float16_muladd(e2, e1, d, 0, &env->vfp.fp_status_f16);
45
#include "semihosting/common-semi.h"
305
+ d = float16_muladd(e2, e1, d, 0, status);
46
#endif
306
*(float16 *)(vd + H1_2(i)) = d;
307
}
308
if (likely((pg >> (j & 63)) & 1)) {
309
d = *(float16 *)(va + H1_2(j));
310
- d = float16_muladd(e4, e3, d, 0, &env->vfp.fp_status_f16);
311
+ d = float16_muladd(e4, e3, d, 0, status);
312
*(float16 *)(vd + H1_2(j)) = d;
313
}
314
} while (i & 63);
315
} while (i != 0);
316
}
317
318
-void HELPER(sve_fcmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
319
+void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
320
+ void *vg, void *status, uint32_t desc)
321
{
322
intptr_t j, i = simd_oprsz(desc);
323
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
324
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
325
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
326
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
327
- unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
328
+ unsigned rot = simd_data(desc);
329
bool flip = rot & 1;
330
float32 neg_imag, neg_real;
331
- void *vd = &env->vfp.zregs[rd];
332
- void *vn = &env->vfp.zregs[rn];
333
- void *vm = &env->vfp.zregs[rm];
334
- void *va = &env->vfp.zregs[ra];
335
uint64_t *g = vg;
336
337
neg_imag = float32_set_sign(0, (rot & 2) != 0);
338
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
339
340
if (likely((pg >> (i & 63)) & 1)) {
341
d = *(float32 *)(va + H1_2(i));
342
- d = float32_muladd(e2, e1, d, 0, &env->vfp.fp_status);
343
+ d = float32_muladd(e2, e1, d, 0, status);
344
*(float32 *)(vd + H1_2(i)) = d;
345
}
346
if (likely((pg >> (j & 63)) & 1)) {
347
d = *(float32 *)(va + H1_2(j));
348
- d = float32_muladd(e4, e3, d, 0, &env->vfp.fp_status);
349
+ d = float32_muladd(e4, e3, d, 0, status);
350
*(float32 *)(vd + H1_2(j)) = d;
351
}
352
} while (i & 63);
353
} while (i != 0);
354
}
355
356
-void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
357
+void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
358
+ void *vg, void *status, uint32_t desc)
359
{
360
intptr_t j, i = simd_oprsz(desc);
361
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
362
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
363
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
364
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
365
- unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
366
+ unsigned rot = simd_data(desc);
367
bool flip = rot & 1;
368
float64 neg_imag, neg_real;
369
- void *vd = &env->vfp.zregs[rd];
370
- void *vn = &env->vfp.zregs[rn];
371
- void *vm = &env->vfp.zregs[rm];
372
- void *va = &env->vfp.zregs[ra];
373
uint64_t *g = vg;
374
375
neg_imag = float64_set_sign(0, (rot & 2) != 0);
376
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
377
378
if (likely((pg >> (i & 63)) & 1)) {
379
d = *(float64 *)(va + H1_2(i));
380
- d = float64_muladd(e2, e1, d, 0, &env->vfp.fp_status);
381
+ d = float64_muladd(e2, e1, d, 0, status);
382
*(float64 *)(vd + H1_2(i)) = d;
383
}
384
if (likely((pg >> (j & 63)) & 1)) {
385
d = *(float64 *)(va + H1_2(j));
386
- d = float64_muladd(e4, e3, d, 0, &env->vfp.fp_status);
387
+ d = float64_muladd(e4, e3, d, 0, status);
388
*(float64 *)(vd + H1_2(j)) = d;
389
}
390
} while (i & 63);
391
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
392
index XXXXXXX..XXXXXXX 100644
393
--- a/target/arm/translate-sve.c
394
+++ b/target/arm/translate-sve.c
395
@@ -XXX,XX +XXX,XX @@ static bool trans_FCADD(DisasContext *s, arg_FCADD *a)
396
return true;
397
}
398
399
-typedef void gen_helper_sve_fmla(TCGv_env, TCGv_ptr, TCGv_i32);
400
-
401
-static bool do_fmla(DisasContext *s, arg_rprrr_esz *a, gen_helper_sve_fmla *fn)
402
+static bool do_fmla(DisasContext *s, arg_rprrr_esz *a,
403
+ gen_helper_gvec_5_ptr *fn)
404
{
405
- if (fn == NULL) {
406
+ if (a->esz == 0) {
407
return false;
408
}
409
- if (!sve_access_check(s)) {
410
- return true;
411
+ if (sve_access_check(s)) {
412
+ unsigned vsz = vec_full_reg_size(s);
413
+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
414
+ tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd),
415
+ vec_full_reg_offset(s, a->rn),
416
+ vec_full_reg_offset(s, a->rm),
417
+ vec_full_reg_offset(s, a->ra),
418
+ pred_full_reg_offset(s, a->pg),
419
+ status, vsz, vsz, 0, fn);
420
+ tcg_temp_free_ptr(status);
421
}
422
-
423
- unsigned vsz = vec_full_reg_size(s);
424
- unsigned desc;
425
- TCGv_i32 t_desc;
426
- TCGv_ptr pg = tcg_temp_new_ptr();
427
-
428
- /* We would need 7 operands to pass these arguments "properly".
429
- * So we encode all the register numbers into the descriptor.
430
- */
431
- desc = deposit32(a->rd, 5, 5, a->rn);
432
- desc = deposit32(desc, 10, 5, a->rm);
433
- desc = deposit32(desc, 15, 5, a->ra);
434
- desc = simd_desc(vsz, vsz, desc);
435
-
436
- t_desc = tcg_const_i32(desc);
437
- tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
438
- fn(cpu_env, pg, t_desc);
439
- tcg_temp_free_i32(t_desc);
440
- tcg_temp_free_ptr(pg);
441
return true;
442
}
443
444
#define DO_FMLA(NAME, name) \
445
static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a) \
446
{ \
447
- static gen_helper_sve_fmla * const fns[4] = { \
448
+ static gen_helper_gvec_5_ptr * const fns[4] = { \
449
NULL, gen_helper_sve_##name##_h, \
450
gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \
451
}; \
452
@@ -XXX,XX +XXX,XX @@ DO_FMLA(FNMLS_zpzzz, fnmls_zpzzz)
453
454
static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
455
{
456
- static gen_helper_sve_fmla * const fns[3] = {
457
+ static gen_helper_gvec_5_ptr * const fns[4] = {
458
+ NULL,
459
gen_helper_sve_fcmla_zpzzz_h,
460
gen_helper_sve_fcmla_zpzzz_s,
461
gen_helper_sve_fcmla_zpzzz_d,
462
@@ -XXX,XX +XXX,XX @@ static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
463
}
464
if (sve_access_check(s)) {
465
unsigned vsz = vec_full_reg_size(s);
466
- unsigned desc;
467
- TCGv_i32 t_desc;
468
- TCGv_ptr pg = tcg_temp_new_ptr();
469
-
470
- /* We would need 7 operands to pass these arguments "properly".
471
- * So we encode all the register numbers into the descriptor.
472
- */
473
- desc = deposit32(a->rd, 5, 5, a->rn);
474
- desc = deposit32(desc, 10, 5, a->rm);
475
- desc = deposit32(desc, 15, 5, a->ra);
476
- desc = deposit32(desc, 20, 2, a->rot);
477
- desc = sextract32(desc, 0, 22);
478
- desc = simd_desc(vsz, vsz, desc);
479
-
480
- t_desc = tcg_const_i32(desc);
481
- tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
482
- fns[a->esz - 1](cpu_env, pg, t_desc);
483
- tcg_temp_free_i32(t_desc);
484
- tcg_temp_free_ptr(pg);
485
+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
486
+ tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd),
487
+ vec_full_reg_offset(s, a->rn),
488
+ vec_full_reg_offset(s, a->rm),
489
+ vec_full_reg_offset(s, a->ra),
490
+ pred_full_reg_offset(s, a->pg),
491
+ status, vsz, vsz, a->rot, fns[a->esz]);
492
+ tcg_temp_free_ptr(status);
493
}
494
return true;
495
}
496
--
47
--
497
2.20.1
48
2.25.1
498
499
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
Use the "normal" memory access functions, rather than the
3
Signed-off-by: Fabiano Rosas <farosas@suse.de>
4
softmmu internal helper functions directly.
4
Reviewed-by: Claudio Fontana <cfontana@suse.de>
5
5
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
6
Since fb901c905dc3, cpu_mem_index is now a simple extract
6
Message-id: 20221213190537.511-6-farosas@suse.de
7
from env->hflags and not a large computation. Which means
8
that it's now more work to pass around this value than it
9
is to recompute it.
10
11
This only adjusts the primitives, and does not clean up
12
all of the uses within sve_helper.c.
13
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 20200508154359.7494-8-richard.henderson@linaro.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
8
---
19
target/arm/sve_helper.c | 221 ++++++++++++++++------------------------
9
target/arm/helper.c | 7 -------
20
1 file changed, 86 insertions(+), 135 deletions(-)
10
1 file changed, 7 deletions(-)
21
11
22
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
12
diff --git a/target/arm/helper.c b/target/arm/helper.c
23
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/sve_helper.c
14
--- a/target/arm/helper.c
25
+++ b/target/arm/sve_helper.c
15
+++ b/target/arm/helper.c
26
@@ -XXX,XX +XXX,XX @@ typedef intptr_t sve_ld1_host_fn(void *vd, void *vg, void *host,
16
@@ -XXX,XX +XXX,XX @@
27
* Load one element into @vd + @reg_off from (@env, @vaddr, @ra).
28
* The controlling predicate is known to be true.
29
*/
17
*/
30
-typedef void sve_ld1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
18
31
- target_ulong vaddr, TCGMemOpIdx oi, uintptr_t ra);
19
#include "qemu/osdep.h"
32
-typedef sve_ld1_tlb_fn sve_st1_tlb_fn;
20
-#include "qemu/units.h"
33
+typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
21
#include "qemu/log.h"
34
+ target_ulong vaddr, uintptr_t retaddr);
22
#include "trace.h"
35
23
#include "cpu.h"
36
/*
24
#include "internals.h"
37
* Generate the above primitives.
25
#include "exec/helper-proto.h"
38
@@ -XXX,XX +XXX,XX @@ static intptr_t sve_##NAME##_host(void *vd, void *vg, void *host, \
26
-#include "qemu/host-utils.h"
39
return mem_off; \
27
#include "qemu/main-loop.h"
40
}
28
#include "qemu/timer.h"
41
29
#include "qemu/bitops.h"
42
-#ifdef CONFIG_SOFTMMU
30
@@ -XXX,XX +XXX,XX @@
43
-#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, HOST, MOEND, TLB) \
31
#include "exec/exec-all.h"
44
+#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \
32
#include <zlib.h> /* For crc32 */
45
static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
33
#include "hw/irq.h"
46
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
34
-#include "semihosting/semihost.h"
47
+ target_ulong addr, uintptr_t ra) \
35
-#include "sysemu/cpus.h"
48
{ \
36
#include "sysemu/cpu-timers.h"
49
- TYPEM val = TLB(env, addr, oi, ra); \
37
#include "sysemu/kvm.h"
50
- *(TYPEE *)(vd + H(reg_off)) = val; \
38
-#include "qemu/range.h"
51
+ *(TYPEE *)(vd + H(reg_off)) = (TYPEM)TLB(env, addr, ra); \
39
#include "qapi/qapi-commands-machine-target.h"
52
}
40
#include "qapi/error.h"
53
-#else
41
#include "qemu/guest-random.h"
54
-#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, HOST, MOEND, TLB) \
42
#ifdef CONFIG_TCG
55
+
43
-#include "arm_ldst.h"
56
+#define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \
44
-#include "exec/cpu_ldst.h"
57
static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
45
#include "semihosting/common-semi.h"
58
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
59
+ target_ulong addr, uintptr_t ra) \
60
{ \
61
- TYPEM val = HOST(g2h(addr)); \
62
- *(TYPEE *)(vd + H(reg_off)) = val; \
63
+ TLB(env, addr, (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); \
64
}
65
-#endif
66
67
#define DO_LD_PRIM_1(NAME, H, TE, TM) \
68
DO_LD_HOST(NAME, H, TE, TM, ldub_p) \
69
- DO_LD_TLB(NAME, H, TE, TM, ldub_p, 0, helper_ret_ldub_mmu)
70
+ DO_LD_TLB(NAME, H, TE, TM, cpu_ldub_data_ra)
71
72
DO_LD_PRIM_1(ld1bb, H1, uint8_t, uint8_t)
73
DO_LD_PRIM_1(ld1bhu, H1_2, uint16_t, uint8_t)
74
@@ -XXX,XX +XXX,XX @@ DO_LD_PRIM_1(ld1bss, H1_4, uint32_t, int8_t)
75
DO_LD_PRIM_1(ld1bdu, , uint64_t, uint8_t)
76
DO_LD_PRIM_1(ld1bds, , uint64_t, int8_t)
77
78
-#define DO_LD_PRIM_2(NAME, end, MOEND, H, TE, TM, PH, PT) \
79
- DO_LD_HOST(NAME##_##end, H, TE, TM, PH##_##end##_p) \
80
- DO_LD_TLB(NAME##_##end, H, TE, TM, PH##_##end##_p, \
81
- MOEND, helper_##end##_##PT##_mmu)
82
+#define DO_ST_PRIM_1(NAME, H, TE, TM) \
83
+ DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra)
84
85
-DO_LD_PRIM_2(ld1hh, le, MO_LE, H1_2, uint16_t, uint16_t, lduw, lduw)
86
-DO_LD_PRIM_2(ld1hsu, le, MO_LE, H1_4, uint32_t, uint16_t, lduw, lduw)
87
-DO_LD_PRIM_2(ld1hss, le, MO_LE, H1_4, uint32_t, int16_t, lduw, lduw)
88
-DO_LD_PRIM_2(ld1hdu, le, MO_LE, , uint64_t, uint16_t, lduw, lduw)
89
-DO_LD_PRIM_2(ld1hds, le, MO_LE, , uint64_t, int16_t, lduw, lduw)
90
+DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t)
91
+DO_ST_PRIM_1(bh, H1_2, uint16_t, uint8_t)
92
+DO_ST_PRIM_1(bs, H1_4, uint32_t, uint8_t)
93
+DO_ST_PRIM_1(bd, , uint64_t, uint8_t)
94
95
-DO_LD_PRIM_2(ld1ss, le, MO_LE, H1_4, uint32_t, uint32_t, ldl, ldul)
96
-DO_LD_PRIM_2(ld1sdu, le, MO_LE, , uint64_t, uint32_t, ldl, ldul)
97
-DO_LD_PRIM_2(ld1sds, le, MO_LE, , uint64_t, int32_t, ldl, ldul)
98
+#define DO_LD_PRIM_2(NAME, H, TE, TM, LD) \
99
+ DO_LD_HOST(ld1##NAME##_be, H, TE, TM, LD##_be_p) \
100
+ DO_LD_HOST(ld1##NAME##_le, H, TE, TM, LD##_le_p) \
101
+ DO_LD_TLB(ld1##NAME##_be, H, TE, TM, cpu_##LD##_be_data_ra) \
102
+ DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra)
103
104
-DO_LD_PRIM_2(ld1dd, le, MO_LE, , uint64_t, uint64_t, ldq, ldq)
105
+#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \
106
+ DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \
107
+ DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra)
108
109
-DO_LD_PRIM_2(ld1hh, be, MO_BE, H1_2, uint16_t, uint16_t, lduw, lduw)
110
-DO_LD_PRIM_2(ld1hsu, be, MO_BE, H1_4, uint32_t, uint16_t, lduw, lduw)
111
-DO_LD_PRIM_2(ld1hss, be, MO_BE, H1_4, uint32_t, int16_t, lduw, lduw)
112
-DO_LD_PRIM_2(ld1hdu, be, MO_BE, , uint64_t, uint16_t, lduw, lduw)
113
-DO_LD_PRIM_2(ld1hds, be, MO_BE, , uint64_t, int16_t, lduw, lduw)
114
+DO_LD_PRIM_2(hh, H1_2, uint16_t, uint16_t, lduw)
115
+DO_LD_PRIM_2(hsu, H1_4, uint32_t, uint16_t, lduw)
116
+DO_LD_PRIM_2(hss, H1_4, uint32_t, int16_t, lduw)
117
+DO_LD_PRIM_2(hdu, , uint64_t, uint16_t, lduw)
118
+DO_LD_PRIM_2(hds, , uint64_t, int16_t, lduw)
119
120
-DO_LD_PRIM_2(ld1ss, be, MO_BE, H1_4, uint32_t, uint32_t, ldl, ldul)
121
-DO_LD_PRIM_2(ld1sdu, be, MO_BE, , uint64_t, uint32_t, ldl, ldul)
122
-DO_LD_PRIM_2(ld1sds, be, MO_BE, , uint64_t, int32_t, ldl, ldul)
123
+DO_ST_PRIM_2(hh, H1_2, uint16_t, uint16_t, stw)
124
+DO_ST_PRIM_2(hs, H1_4, uint32_t, uint16_t, stw)
125
+DO_ST_PRIM_2(hd, , uint64_t, uint16_t, stw)
126
127
-DO_LD_PRIM_2(ld1dd, be, MO_BE, , uint64_t, uint64_t, ldq, ldq)
128
+DO_LD_PRIM_2(ss, H1_4, uint32_t, uint32_t, ldl)
129
+DO_LD_PRIM_2(sdu, , uint64_t, uint32_t, ldl)
130
+DO_LD_PRIM_2(sds, , uint64_t, int32_t, ldl)
131
+
132
+DO_ST_PRIM_2(ss, H1_4, uint32_t, uint32_t, stl)
133
+DO_ST_PRIM_2(sd, , uint64_t, uint32_t, stl)
134
+
135
+DO_LD_PRIM_2(dd, , uint64_t, uint64_t, ldq)
136
+DO_ST_PRIM_2(dd, , uint64_t, uint64_t, stq)
137
138
#undef DO_LD_TLB
139
+#undef DO_ST_TLB
140
#undef DO_LD_HOST
141
#undef DO_LD_PRIM_1
142
+#undef DO_ST_PRIM_1
143
#undef DO_LD_PRIM_2
144
+#undef DO_ST_PRIM_2
145
146
/*
147
* Skip through a sequence of inactive elements in the guarding predicate @vg,
148
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
149
uint32_t desc, const uintptr_t retaddr,
150
const int esz, const int msz,
151
sve_ld1_host_fn *host_fn,
152
- sve_ld1_tlb_fn *tlb_fn)
153
+ sve_ldst1_tlb_fn *tlb_fn)
154
{
155
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
156
const int mmu_idx = get_mmuidx(oi);
157
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
158
* on I/O memory, it may succeed but not bring in the TLB entry.
159
* But even then we have still made forward progress.
160
*/
161
- tlb_fn(env, &scratch, reg_off, addr + mem_off, oi, retaddr);
162
+ tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
163
reg_off += 1 << esz;
164
}
165
#endif
46
#endif
166
@@ -XXX,XX +XXX,XX @@ DO_LD1_2(ld1dd, 3, 3)
47
#include "cpregs.h"
167
*/
168
static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
169
uint32_t desc, int size, uintptr_t ra,
170
- sve_ld1_tlb_fn *tlb_fn)
171
+ sve_ldst1_tlb_fn *tlb_fn)
172
{
173
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
174
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
175
intptr_t i, oprsz = simd_oprsz(desc);
176
ARMVectorReg scratch[2] = { };
177
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
178
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
179
do {
180
if (pg & 1) {
181
- tlb_fn(env, &scratch[0], i, addr, oi, ra);
182
- tlb_fn(env, &scratch[1], i, addr + size, oi, ra);
183
+ tlb_fn(env, &scratch[0], i, addr, ra);
184
+ tlb_fn(env, &scratch[1], i, addr + size, ra);
185
}
186
i += size, pg >>= size;
187
addr += 2 * size;
188
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
189
190
static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
191
uint32_t desc, int size, uintptr_t ra,
192
- sve_ld1_tlb_fn *tlb_fn)
193
+ sve_ldst1_tlb_fn *tlb_fn)
194
{
195
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
196
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
197
intptr_t i, oprsz = simd_oprsz(desc);
198
ARMVectorReg scratch[3] = { };
199
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
200
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
201
do {
202
if (pg & 1) {
203
- tlb_fn(env, &scratch[0], i, addr, oi, ra);
204
- tlb_fn(env, &scratch[1], i, addr + size, oi, ra);
205
- tlb_fn(env, &scratch[2], i, addr + 2 * size, oi, ra);
206
+ tlb_fn(env, &scratch[0], i, addr, ra);
207
+ tlb_fn(env, &scratch[1], i, addr + size, ra);
208
+ tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
209
}
210
i += size, pg >>= size;
211
addr += 3 * size;
212
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
213
214
static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
215
uint32_t desc, int size, uintptr_t ra,
216
- sve_ld1_tlb_fn *tlb_fn)
217
+ sve_ldst1_tlb_fn *tlb_fn)
218
{
219
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
220
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
221
intptr_t i, oprsz = simd_oprsz(desc);
222
ARMVectorReg scratch[4] = { };
223
@@ -XXX,XX +XXX,XX @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
224
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
225
do {
226
if (pg & 1) {
227
- tlb_fn(env, &scratch[0], i, addr, oi, ra);
228
- tlb_fn(env, &scratch[1], i, addr + size, oi, ra);
229
- tlb_fn(env, &scratch[2], i, addr + 2 * size, oi, ra);
230
- tlb_fn(env, &scratch[3], i, addr + 3 * size, oi, ra);
231
+ tlb_fn(env, &scratch[0], i, addr, ra);
232
+ tlb_fn(env, &scratch[1], i, addr + size, ra);
233
+ tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
234
+ tlb_fn(env, &scratch[3], i, addr + 3 * size, ra);
235
}
236
i += size, pg >>= size;
237
addr += 4 * size;
238
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
239
uint32_t desc, const uintptr_t retaddr,
240
const int esz, const int msz,
241
sve_ld1_host_fn *host_fn,
242
- sve_ld1_tlb_fn *tlb_fn)
243
+ sve_ldst1_tlb_fn *tlb_fn)
244
{
245
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
246
const int mmu_idx = get_mmuidx(oi);
247
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
248
* Perform one normal read, which will fault or not.
249
* But it is likely to bring the page into the tlb.
250
*/
251
- tlb_fn(env, vd, reg_off, addr + mem_off, oi, retaddr);
252
+ tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
253
254
/* After any fault, zero any leading predicated false elts. */
255
swap_memzero(vd, reg_off);
256
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_LDNF1_2(dd, 3, 3)
257
#undef DO_LDFF1_LDNF1_1
258
#undef DO_LDFF1_LDNF1_2
259
260
-/*
261
- * Store contiguous data, protected by a governing predicate.
262
- */
263
-
264
-#ifdef CONFIG_SOFTMMU
265
-#define DO_ST_TLB(NAME, H, TYPEM, HOST, MOEND, TLB) \
266
-static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
267
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
268
-{ \
269
- TLB(env, addr, *(TYPEM *)(vd + H(reg_off)), oi, ra); \
270
-}
271
-#else
272
-#define DO_ST_TLB(NAME, H, TYPEM, HOST, MOEND, TLB) \
273
-static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
274
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
275
-{ \
276
- HOST(g2h(addr), *(TYPEM *)(vd + H(reg_off))); \
277
-}
278
-#endif
279
-
280
-DO_ST_TLB(st1bb, H1, uint8_t, stb_p, 0, helper_ret_stb_mmu)
281
-DO_ST_TLB(st1bh, H1_2, uint16_t, stb_p, 0, helper_ret_stb_mmu)
282
-DO_ST_TLB(st1bs, H1_4, uint32_t, stb_p, 0, helper_ret_stb_mmu)
283
-DO_ST_TLB(st1bd, , uint64_t, stb_p, 0, helper_ret_stb_mmu)
284
-
285
-DO_ST_TLB(st1hh_le, H1_2, uint16_t, stw_le_p, MO_LE, helper_le_stw_mmu)
286
-DO_ST_TLB(st1hs_le, H1_4, uint32_t, stw_le_p, MO_LE, helper_le_stw_mmu)
287
-DO_ST_TLB(st1hd_le, , uint64_t, stw_le_p, MO_LE, helper_le_stw_mmu)
288
-
289
-DO_ST_TLB(st1ss_le, H1_4, uint32_t, stl_le_p, MO_LE, helper_le_stl_mmu)
290
-DO_ST_TLB(st1sd_le, , uint64_t, stl_le_p, MO_LE, helper_le_stl_mmu)
291
-
292
-DO_ST_TLB(st1dd_le, , uint64_t, stq_le_p, MO_LE, helper_le_stq_mmu)
293
-
294
-DO_ST_TLB(st1hh_be, H1_2, uint16_t, stw_be_p, MO_BE, helper_be_stw_mmu)
295
-DO_ST_TLB(st1hs_be, H1_4, uint32_t, stw_be_p, MO_BE, helper_be_stw_mmu)
296
-DO_ST_TLB(st1hd_be, , uint64_t, stw_be_p, MO_BE, helper_be_stw_mmu)
297
-
298
-DO_ST_TLB(st1ss_be, H1_4, uint32_t, stl_be_p, MO_BE, helper_be_stl_mmu)
299
-DO_ST_TLB(st1sd_be, , uint64_t, stl_be_p, MO_BE, helper_be_stl_mmu)
300
-
301
-DO_ST_TLB(st1dd_be, , uint64_t, stq_be_p, MO_BE, helper_be_stq_mmu)
302
-
303
-#undef DO_ST_TLB
304
-
305
/*
306
* Common helpers for all contiguous 1,2,3,4-register predicated stores.
307
*/
308
static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
309
uint32_t desc, const uintptr_t ra,
310
const int esize, const int msize,
311
- sve_st1_tlb_fn *tlb_fn)
312
+ sve_ldst1_tlb_fn *tlb_fn)
313
{
314
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
315
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
316
intptr_t i, oprsz = simd_oprsz(desc);
317
void *vd = &env->vfp.zregs[rd];
318
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
319
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
320
do {
321
if (pg & 1) {
322
- tlb_fn(env, vd, i, addr, oi, ra);
323
+ tlb_fn(env, vd, i, addr, ra);
324
}
325
i += esize, pg >>= esize;
326
addr += msize;
327
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
328
static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
329
uint32_t desc, const uintptr_t ra,
330
const int esize, const int msize,
331
- sve_st1_tlb_fn *tlb_fn)
332
+ sve_ldst1_tlb_fn *tlb_fn)
333
{
334
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
335
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
336
intptr_t i, oprsz = simd_oprsz(desc);
337
void *d1 = &env->vfp.zregs[rd];
338
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
339
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
340
do {
341
if (pg & 1) {
342
- tlb_fn(env, d1, i, addr, oi, ra);
343
- tlb_fn(env, d2, i, addr + msize, oi, ra);
344
+ tlb_fn(env, d1, i, addr, ra);
345
+ tlb_fn(env, d2, i, addr + msize, ra);
346
}
347
i += esize, pg >>= esize;
348
addr += 2 * msize;
349
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
350
static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
351
uint32_t desc, const uintptr_t ra,
352
const int esize, const int msize,
353
- sve_st1_tlb_fn *tlb_fn)
354
+ sve_ldst1_tlb_fn *tlb_fn)
355
{
356
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
357
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
358
intptr_t i, oprsz = simd_oprsz(desc);
359
void *d1 = &env->vfp.zregs[rd];
360
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
361
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
362
do {
363
if (pg & 1) {
364
- tlb_fn(env, d1, i, addr, oi, ra);
365
- tlb_fn(env, d2, i, addr + msize, oi, ra);
366
- tlb_fn(env, d3, i, addr + 2 * msize, oi, ra);
367
+ tlb_fn(env, d1, i, addr, ra);
368
+ tlb_fn(env, d2, i, addr + msize, ra);
369
+ tlb_fn(env, d3, i, addr + 2 * msize, ra);
370
}
371
i += esize, pg >>= esize;
372
addr += 3 * msize;
373
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
374
static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
375
uint32_t desc, const uintptr_t ra,
376
const int esize, const int msize,
377
- sve_st1_tlb_fn *tlb_fn)
378
+ sve_ldst1_tlb_fn *tlb_fn)
379
{
380
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
381
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
382
intptr_t i, oprsz = simd_oprsz(desc);
383
void *d1 = &env->vfp.zregs[rd];
384
@@ -XXX,XX +XXX,XX @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
385
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
386
do {
387
if (pg & 1) {
388
- tlb_fn(env, d1, i, addr, oi, ra);
389
- tlb_fn(env, d2, i, addr + msize, oi, ra);
390
- tlb_fn(env, d3, i, addr + 2 * msize, oi, ra);
391
- tlb_fn(env, d4, i, addr + 3 * msize, oi, ra);
392
+ tlb_fn(env, d1, i, addr, ra);
393
+ tlb_fn(env, d2, i, addr + msize, ra);
394
+ tlb_fn(env, d3, i, addr + 2 * msize, ra);
395
+ tlb_fn(env, d4, i, addr + 3 * msize, ra);
396
}
397
i += esize, pg >>= esize;
398
addr += 4 * msize;
399
@@ -XXX,XX +XXX,XX @@ static target_ulong off_zd_d(void *reg, intptr_t reg_ofs)
400
401
static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
402
target_ulong base, uint32_t desc, uintptr_t ra,
403
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
404
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
405
{
406
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
407
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
408
intptr_t i, oprsz = simd_oprsz(desc);
409
ARMVectorReg scratch = { };
410
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
411
do {
412
if (likely(pg & 1)) {
413
target_ulong off = off_fn(vm, i);
414
- tlb_fn(env, &scratch, i, base + (off << scale), oi, ra);
415
+ tlb_fn(env, &scratch, i, base + (off << scale), ra);
416
}
417
i += 4, pg >>= 4;
418
} while (i & 15);
419
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
420
421
static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
422
target_ulong base, uint32_t desc, uintptr_t ra,
423
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
424
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
425
{
426
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
427
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
428
intptr_t i, oprsz = simd_oprsz(desc) / 8;
429
ARMVectorReg scratch = { };
430
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
431
uint8_t pg = *(uint8_t *)(vg + H1(i));
432
if (likely(pg & 1)) {
433
target_ulong off = off_fn(vm, i * 8);
434
- tlb_fn(env, &scratch, i * 8, base + (off << scale), oi, ra);
435
+ tlb_fn(env, &scratch, i * 8, base + (off << scale), ra);
436
}
437
}
438
clear_helper_retaddr();
439
@@ -XXX,XX +XXX,XX @@ DO_LD_NF(dd_be, , uint64_t, uint64_t, ldq_be_p)
440
*/
441
static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
442
target_ulong base, uint32_t desc, uintptr_t ra,
443
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn,
444
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
445
sve_ld1_nf_fn *nonfault_fn)
446
{
447
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
448
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
449
set_helper_retaddr(ra);
450
addr = off_fn(vm, reg_off);
451
addr = base + (addr << scale);
452
- tlb_fn(env, vd, reg_off, addr, oi, ra);
453
+ tlb_fn(env, vd, reg_off, addr, ra);
454
455
/* The rest of the reads will be non-faulting. */
456
clear_helper_retaddr();
457
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
458
459
static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
460
target_ulong base, uint32_t desc, uintptr_t ra,
461
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn,
462
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
463
sve_ld1_nf_fn *nonfault_fn)
464
{
465
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
466
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
467
set_helper_retaddr(ra);
468
addr = off_fn(vm, reg_off);
469
addr = base + (addr << scale);
470
- tlb_fn(env, vd, reg_off, addr, oi, ra);
471
+ tlb_fn(env, vd, reg_off, addr, ra);
472
473
/* The rest of the reads will be non-faulting. */
474
clear_helper_retaddr();
475
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_ZPZ_D(dd_be, zd)
476
477
static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
478
target_ulong base, uint32_t desc, uintptr_t ra,
479
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
480
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
481
{
482
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
483
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
484
intptr_t i, oprsz = simd_oprsz(desc);
485
486
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
487
do {
488
if (likely(pg & 1)) {
489
target_ulong off = off_fn(vm, i);
490
- tlb_fn(env, vd, i, base + (off << scale), oi, ra);
491
+ tlb_fn(env, vd, i, base + (off << scale), ra);
492
}
493
i += 4, pg >>= 4;
494
} while (i & 15);
495
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
496
497
static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
498
target_ulong base, uint32_t desc, uintptr_t ra,
499
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
500
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
501
{
502
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
503
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
504
intptr_t i, oprsz = simd_oprsz(desc) / 8;
505
506
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
507
uint8_t pg = *(uint8_t *)(vg + H1(i));
508
if (likely(pg & 1)) {
509
target_ulong off = off_fn(vm, i * 8);
510
- tlb_fn(env, vd, i * 8, base + (off << scale), oi, ra);
511
+ tlb_fn(env, vd, i * 8, base + (off << scale), ra);
512
}
513
}
514
clear_helper_retaddr();
515
--
48
--
516
2.20.1
49
2.25.1
517
518
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Claudio Fontana <cfontana@suse.de>
2
2
3
Use ARRAY_SIZE() to iterate over ARMCPUInfo[].
3
Remove some unused headers.
4
4
5
Since on the aarch64-linux-user build, arm_cpus[] is empty, add
5
Signed-off-by: Claudio Fontana <cfontana@suse.de>
6
the cpu_count variable and only iterate when it is non-zero.
6
Acked-by: Richard Henderson <richard.henderson@linaro.org>
7
7
Reviewed-by: Claudio Fontana <cfontana@suse.de>
8
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Fabiano Rosas <farosas@suse.de>
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20221213190537.511-7-farosas@suse.de
11
Message-id: 20200504172448.9402-4-philmd@redhat.com
11
[added back some includes that are still needed at this point]
12
Signed-off-by: Fabiano Rosas <farosas@suse.de>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
---
14
target/arm/cpu.c | 16 +++++++++-------
15
target/arm/cpu.c | 1 -
15
target/arm/cpu64.c | 8 +++-----
16
target/arm/cpu64.c | 6 ------
16
2 files changed, 12 insertions(+), 12 deletions(-)
17
2 files changed, 7 deletions(-)
17
18
18
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
19
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
19
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.c
21
--- a/target/arm/cpu.c
21
+++ b/target/arm/cpu.c
22
+++ b/target/arm/cpu.c
22
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {
23
@@ -XXX,XX +XXX,XX @@
23
{ .name = "any", .initfn = arm_max_initfn },
24
#include "target/arm/idau.h"
24
#endif
25
#include "qemu/module.h"
25
#endif
26
#include "qapi/error.h"
26
- { .name = NULL }
27
-#include "qapi/visitor.h"
27
};
28
#include "cpu.h"
28
29
#ifdef CONFIG_TCG
29
static Property arm_cpu_properties[] = {
30
#include "hw/core/tcg-cpu-ops.h"
30
@@ -XXX,XX +XXX,XX @@ static const TypeInfo idau_interface_type_info = {
31
32
static void arm_cpu_register_types(void)
33
{
34
- const ARMCPUInfo *info = arm_cpus;
35
+ const size_t cpu_count = ARRAY_SIZE(arm_cpus);
36
37
type_register_static(&arm_cpu_type_info);
38
type_register_static(&idau_interface_type_info);
39
40
- while (info->name) {
41
- arm_cpu_register(info);
42
- info++;
43
- }
44
-
45
#ifdef CONFIG_KVM
46
type_register_static(&host_arm_cpu_type_info);
47
#endif
48
+
49
+ if (cpu_count) {
50
+ size_t i;
51
+
52
+ for (i = 0; i < cpu_count; ++i) {
53
+ arm_cpu_register(&arm_cpus[i]);
54
+ }
55
+ }
56
}
57
58
type_init(arm_cpu_register_types)
59
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
31
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
60
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
61
--- a/target/arm/cpu64.c
33
--- a/target/arm/cpu64.c
62
+++ b/target/arm/cpu64.c
34
+++ b/target/arm/cpu64.c
63
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
35
@@ -XXX,XX +XXX,XX @@
64
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
36
#include "qemu/osdep.h"
65
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
37
#include "qapi/error.h"
66
{ .name = "max", .initfn = aarch64_max_initfn },
38
#include "cpu.h"
67
- { .name = NULL }
39
-#ifdef CONFIG_TCG
68
};
40
-#include "hw/core/tcg-cpu-ops.h"
69
41
-#endif /* CONFIG_TCG */
70
static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
42
#include "qemu/module.h"
71
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aarch64_cpu_type_info = {
43
-#if !defined(CONFIG_USER_ONLY)
72
44
-#include "hw/loader.h"
73
static void aarch64_cpu_register_types(void)
45
-#endif
74
{
46
#include "sysemu/kvm.h"
75
- const ARMCPUInfo *info = aarch64_cpus;
47
#include "sysemu/hvf.h"
76
+ size_t i;
48
#include "kvm_arm.h"
77
78
type_register_static(&aarch64_cpu_type_info);
79
80
- while (info->name) {
81
- aarch64_cpu_register(info);
82
- info++;
83
+ for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
84
+ aarch64_cpu_register(&aarch64_cpus[i]);
85
}
86
}
87
88
--
49
--
89
2.20.1
50
2.25.1
90
91
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
The pointed MouseTransformInfo structure is accessed read-only.
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
5
Message-id: 20200508154359.7494-4-richard.henderson@linaro.org
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20221220142520.24094-2-philmd@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
9
---
8
include/exec/exec-all.h | 17 +++++++++++++++++
10
include/hw/input/tsc2xxx.h | 4 ++--
9
1 file changed, 17 insertions(+)
11
hw/input/tsc2005.c | 2 +-
12
hw/input/tsc210x.c | 3 +--
13
3 files changed, 4 insertions(+), 5 deletions(-)
10
14
11
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
15
diff --git a/include/hw/input/tsc2xxx.h b/include/hw/input/tsc2xxx.h
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/include/exec/exec-all.h
17
--- a/include/hw/input/tsc2xxx.h
14
+++ b/include/exec/exec-all.h
18
+++ b/include/hw/input/tsc2xxx.h
15
@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
19
@@ -XXX,XX +XXX,XX @@ uWireSlave *tsc2102_init(qemu_irq pint);
20
uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav);
21
I2SCodec *tsc210x_codec(uWireSlave *chip);
22
uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len);
23
-void tsc210x_set_transform(uWireSlave *chip, MouseTransformInfo *info);
24
+void tsc210x_set_transform(uWireSlave *chip, const MouseTransformInfo *info);
25
void tsc210x_key_event(uWireSlave *chip, int key, int down);
26
27
/* tsc2005.c */
28
void *tsc2005_init(qemu_irq pintdav);
29
uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len);
30
-void tsc2005_set_transform(void *opaque, MouseTransformInfo *info);
31
+void tsc2005_set_transform(void *opaque, const MouseTransformInfo *info);
32
33
#endif
34
diff --git a/hw/input/tsc2005.c b/hw/input/tsc2005.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/input/tsc2005.c
37
+++ b/hw/input/tsc2005.c
38
@@ -XXX,XX +XXX,XX @@ void *tsc2005_init(qemu_irq pintdav)
39
* from the touchscreen. Assuming 12-bit precision was used during
40
* tslib calibration.
41
*/
42
-void tsc2005_set_transform(void *opaque, MouseTransformInfo *info)
43
+void tsc2005_set_transform(void *opaque, const MouseTransformInfo *info)
16
{
44
{
17
}
45
TSC2005State *s = (TSC2005State *) opaque;
18
#endif
46
19
+/**
47
diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c
20
+ * probe_access:
48
index XXXXXXX..XXXXXXX 100644
21
+ * @env: CPUArchState
49
--- a/hw/input/tsc210x.c
22
+ * @addr: guest virtual address to look up
50
+++ b/hw/input/tsc210x.c
23
+ * @size: size of the access
51
@@ -XXX,XX +XXX,XX @@ I2SCodec *tsc210x_codec(uWireSlave *chip)
24
+ * @access_type: read, write or execute permission
52
* from the touchscreen. Assuming 12-bit precision was used during
25
+ * @mmu_idx: MMU index to use for lookup
53
* tslib calibration.
26
+ * @retaddr: return address for unwinding
54
*/
27
+ *
55
-void tsc210x_set_transform(uWireSlave *chip,
28
+ * Look up the guest virtual address @addr. Raise an exception if the
56
- MouseTransformInfo *info)
29
+ * page does not satisfy @access_type. Raise an exception if the
57
+void tsc210x_set_transform(uWireSlave *chip, const MouseTransformInfo *info)
30
+ * access (@addr, @size) hits a watchpoint. For writes, mark a clean
58
{
31
+ * page as dirty.
59
TSC210xState *s = (TSC210xState *) chip->opaque;
32
+ *
60
#if 0
33
+ * Finally, return the host address for a page that is backed by RAM,
34
+ * or NULL if the page requires I/O.
35
+ */
36
void *probe_access(CPUArchState *env, target_ulong addr, int size,
37
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
38
39
--
61
--
40
2.20.1
62
2.25.1
41
63
42
64
diff view generated by jsdifflib
1
From: Joel Stanley <joel@jms.id.au>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
There are minimal differences from Qemu's point of view between the A0
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
and A1 silicon revisions.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
5
Message-id: 20221220142520.24094-3-philmd@linaro.org
6
As the A1 exercises different code paths in u-boot it is desirable to
7
emulate that instead.
8
9
Signed-off-by: Joel Stanley <joel@jms.id.au>
10
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
11
Reviewed-by: Cédric Le Goater <clg@kaod.org>
12
Message-id: 20200504093703.261135-1-joel@jms.id.au
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
7
---
15
include/hw/misc/aspeed_scu.h | 1 +
8
hw/arm/nseries.c | 18 +++++++++---------
16
hw/arm/aspeed.c | 8 ++++----
9
1 file changed, 9 insertions(+), 9 deletions(-)
17
hw/arm/aspeed_ast2600.c | 6 +++---
18
hw/misc/aspeed_scu.c | 11 +++++------
19
4 files changed, 13 insertions(+), 13 deletions(-)
20
10
21
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
11
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
22
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/misc/aspeed_scu.h
13
--- a/hw/arm/nseries.c
24
+++ b/include/hw/misc/aspeed_scu.h
14
+++ b/hw/arm/nseries.c
25
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSCUState {
15
@@ -XXX,XX +XXX,XX @@ static void n8x0_i2c_setup(struct n800_s *s)
26
#define AST2500_A0_SILICON_REV 0x04000303U
27
#define AST2500_A1_SILICON_REV 0x04010303U
28
#define AST2600_A0_SILICON_REV 0x05000303U
29
+#define AST2600_A1_SILICON_REV 0x05010303U
30
31
#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
32
33
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/arm/aspeed.c
36
+++ b/hw/arm/aspeed.c
37
@@ -XXX,XX +XXX,XX @@ struct AspeedBoardState {
38
39
/* Tacoma hardware value */
40
#define TACOMA_BMC_HW_STRAP1 0x00000000
41
-#define TACOMA_BMC_HW_STRAP2 0x00000000
42
+#define TACOMA_BMC_HW_STRAP2 0x00000040
43
44
/*
45
* The max ram region is for firmwares that scan the address space
46
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
47
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
48
49
mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
50
- amc->soc_name = "ast2600-a0";
51
+ amc->soc_name = "ast2600-a1";
52
amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
53
amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
54
amc->fmc_model = "w25q512jv";
55
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
56
MachineClass *mc = MACHINE_CLASS(oc);
57
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
58
59
- mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
60
- amc->soc_name = "ast2600-a0";
61
+ mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)";
62
+ amc->soc_name = "ast2600-a1";
63
amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
64
amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
65
amc->fmc_model = "mx66l1g45g";
66
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/hw/arm/aspeed_ast2600.c
69
+++ b/hw/arm/aspeed_ast2600.c
70
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
71
72
dc->realize = aspeed_soc_ast2600_realize;
73
74
- sc->name = "ast2600-a0";
75
+ sc->name = "ast2600-a1";
76
sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
77
- sc->silicon_rev = AST2600_A0_SILICON_REV;
78
+ sc->silicon_rev = AST2600_A1_SILICON_REV;
79
sc->sram_size = 0x10000;
80
sc->spis_num = 2;
81
sc->ehcis_num = 2;
82
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
83
}
16
}
84
17
85
static const TypeInfo aspeed_soc_ast2600_type_info = {
18
/* Touchscreen and keypad controller */
86
- .name = "ast2600-a0",
19
-static MouseTransformInfo n800_pointercal = {
87
+ .name = "ast2600-a1",
20
+static const MouseTransformInfo n800_pointercal = {
88
.parent = TYPE_ASPEED_SOC,
21
.x = 800,
89
.instance_size = sizeof(AspeedSoCState),
22
.y = 480,
90
.instance_init = aspeed_soc_ast2600_init,
23
.a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
91
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/hw/misc/aspeed_scu.c
94
+++ b/hw/misc/aspeed_scu.c
95
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_silicon_revs[] = {
96
AST2500_A0_SILICON_REV,
97
AST2500_A1_SILICON_REV,
98
AST2600_A0_SILICON_REV,
99
+ AST2600_A1_SILICON_REV,
100
};
24
};
101
25
102
bool is_supported_silicon_rev(uint32_t silicon_rev)
26
-static MouseTransformInfo n810_pointercal = {
103
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = {
27
+static const MouseTransformInfo n810_pointercal = {
104
.valid.unaligned = false,
28
.x = 800,
29
.y = 480,
30
.a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
31
@@ -XXX,XX +XXX,XX @@ static void n810_key_event(void *opaque, int keycode)
32
33
#define M    0
34
35
-static int n810_keys[0x80] = {
36
+static const int n810_keys[0x80] = {
37
[0x01] = 16,    /* Q */
38
[0x02] = 37,    /* K */
39
[0x03] = 24,    /* O */
40
@@ -XXX,XX +XXX,XX @@ static void n8x0_usb_setup(struct n800_s *s)
41
/* Setup done before the main bootloader starts by some early setup code
42
* - used when we want to run the main bootloader in emulation. This
43
* isn't documented. */
44
-static uint32_t n800_pinout[104] = {
45
+static const uint32_t n800_pinout[104] = {
46
0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
47
0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
48
0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
49
@@ -XXX,XX +XXX,XX @@ static void n8x0_boot_init(void *opaque)
50
#define OMAP_TAG_CBUS        0x4e03
51
#define OMAP_TAG_EM_ASIC_BB5    0x4e04
52
53
-static struct omap_gpiosw_info_s {
54
+static const struct omap_gpiosw_info_s {
55
const char *name;
56
int line;
57
int type;
58
@@ -XXX,XX +XXX,XX @@ static struct omap_gpiosw_info_s {
59
{ NULL }
105
};
60
};
106
61
107
-static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = {
62
-static struct omap_partition_info_s {
108
- [AST2600_SILICON_REV] = AST2600_SILICON_REV,
63
+static const struct omap_partition_info_s {
109
- [AST2600_SILICON_REV2] = AST2600_SILICON_REV,
64
uint32_t offset;
110
- [AST2600_SYS_RST_CTRL] = 0xF7CFFEDC | 0x100,
65
uint32_t size;
111
+static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = {
66
int mask;
112
+ [AST2600_SYS_RST_CTRL] = 0xF7C3FED8,
67
@@ -XXX,XX +XXX,XX @@ static struct omap_partition_info_s {
113
[AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC,
68
{ 0, 0, 0, NULL }
114
- [AST2600_CLK_STOP_CTRL] = 0xEFF43E8B,
69
};
115
+ [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A,
70
116
[AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0,
71
-static uint8_t n8x0_bd_addr[6] = { N8X0_BD_ADDR };
117
[AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */
72
+static const uint8_t n8x0_bd_addr[6] = { N8X0_BD_ADDR };
118
[AST2600_HPLL_PARAM] = 0x1000405F,
73
119
@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data)
74
static int n8x0_atag_setup(void *p, int model)
120
75
{
121
dc->desc = "ASPEED 2600 System Control Unit";
76
uint8_t *b;
122
dc->reset = aspeed_ast2600_scu_reset;
77
uint16_t *w;
123
- asc->resets = ast2600_a0_resets;
78
uint32_t *l;
124
+ asc->resets = ast2600_a1_resets;
79
- struct omap_gpiosw_info_s *gpiosw;
125
asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */
80
- struct omap_partition_info_s *partition;
126
asc->apb_divider = 4;
81
+ const struct omap_gpiosw_info_s *gpiosw;
127
asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
82
+ const struct omap_partition_info_s *partition;
83
const char *tag;
84
85
w = p;
128
--
86
--
129
2.20.1
87
2.25.1
130
88
131
89
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Silent when compiling with -Wextra:
4
5
../hw/arm/nseries.c:1081:12: warning: missing field 'line' initializer [-Wmissing-field-initializers]
6
{ NULL }
7
^
8
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-id: 20221220142520.24094-4-philmd@linaro.org
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200508154359.7494-2-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
13
---
8
include/hw/core/cpu.h | 23 +++++++++++++++++++++++
14
hw/arm/nseries.c | 10 ++++------
9
1 file changed, 23 insertions(+)
15
1 file changed, 4 insertions(+), 6 deletions(-)
10
16
11
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
17
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/core/cpu.h
19
--- a/hw/arm/nseries.c
14
+++ b/include/hw/core/cpu.h
20
+++ b/hw/arm/nseries.c
15
@@ -XXX,XX +XXX,XX @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
21
@@ -XXX,XX +XXX,XX @@ static const struct omap_gpiosw_info_s {
16
vaddr len, int flags);
22
"headphone", N8X0_HEADPHONE_GPIO,
17
void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
23
OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
18
void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
24
},
19
+
25
- { NULL }
20
+/**
26
+ { /* end of list */ }
21
+ * cpu_check_watchpoint:
27
}, n810_gpiosw_info[] = {
22
+ * @cpu: cpu context
28
{
23
+ * @addr: guest virtual address
29
"gps_reset", N810_GPS_RESET_GPIO,
24
+ * @len: access length
30
@@ -XXX,XX +XXX,XX @@ static const struct omap_gpiosw_info_s {
25
+ * @attrs: memory access attributes
31
"slide", N810_SLIDE_GPIO,
26
+ * @flags: watchpoint access type
32
OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
27
+ * @ra: unwind return address
33
},
28
+ *
34
- { NULL }
29
+ * Check for a watchpoint hit in [addr, addr+len) of the type
35
+ { /* end of list */ }
30
+ * specified by @flags. Exit via exception with a hit.
36
};
31
+ */
37
32
void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
38
static const struct omap_partition_info_s {
33
MemTxAttrs attrs, int flags, uintptr_t ra);
39
@@ -XXX,XX +XXX,XX @@ static const struct omap_partition_info_s {
34
+
40
{ 0x00080000, 0x00200000, 0x0, "kernel" },
35
+/**
41
{ 0x00280000, 0x00200000, 0x3, "initfs" },
36
+ * cpu_watchpoint_address_matches:
42
{ 0x00480000, 0x0fb80000, 0x3, "rootfs" },
37
+ * @cpu: cpu context
43
-
38
+ * @addr: guest virtual address
44
- { 0, 0, 0, NULL }
39
+ * @len: access length
45
+ { /* end of list */ }
40
+ *
46
}, n810_part_info[] = {
41
+ * Return the watchpoint flags that apply to [addr, addr+len).
47
{ 0x00000000, 0x00020000, 0x3, "bootloader" },
42
+ * If no watchpoint is registered for the range, the result is 0.
48
{ 0x00020000, 0x00060000, 0x0, "config" },
43
+ */
49
{ 0x00080000, 0x00220000, 0x0, "kernel" },
44
int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len);
50
{ 0x002a0000, 0x00400000, 0x0, "initfs" },
45
#endif
51
{ 0x006a0000, 0x0f960000, 0x0, "rootfs" },
46
52
-
53
- { 0, 0, 0, NULL }
54
+ { /* end of list */ }
55
};
56
57
static const uint8_t n8x0_bd_addr[6] = { N8X0_BD_ADDR };
47
--
58
--
48
2.20.1
59
2.25.1
49
60
50
61
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Zhuojia Shen <chaosdefinition@hotmail.com>
2
2
3
Add trace event to display timer's counter value updates.
3
In CPUID registers exposed to userspace, some registers were missing
4
4
and some fields were not exposed. This patch aligns exposed ID
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
registers and their fields with what the upstream kernel currently
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
exposes.
7
Message-id: 20200504072822.18799-5-f4bug@amsat.org
7
8
Specifically, the following new ID registers/fields are exposed to
9
userspace:
10
11
ID_AA64PFR1_EL1.BT: bits 3-0
12
ID_AA64PFR1_EL1.MTE: bits 11-8
13
ID_AA64PFR1_EL1.SME: bits 27-24
14
15
ID_AA64ZFR0_EL1.SVEver: bits 3-0
16
ID_AA64ZFR0_EL1.AES: bits 7-4
17
ID_AA64ZFR0_EL1.BitPerm: bits 19-16
18
ID_AA64ZFR0_EL1.BF16: bits 23-20
19
ID_AA64ZFR0_EL1.SHA3: bits 35-32
20
ID_AA64ZFR0_EL1.SM4: bits 43-40
21
ID_AA64ZFR0_EL1.I8MM: bits 47-44
22
ID_AA64ZFR0_EL1.F32MM: bits 55-52
23
ID_AA64ZFR0_EL1.F64MM: bits 59-56
24
25
ID_AA64SMFR0_EL1.F32F32: bit 32
26
ID_AA64SMFR0_EL1.B16F32: bit 34
27
ID_AA64SMFR0_EL1.F16F32: bit 35
28
ID_AA64SMFR0_EL1.I8I32: bits 39-36
29
ID_AA64SMFR0_EL1.F64F64: bit 48
30
ID_AA64SMFR0_EL1.I16I64: bits 55-52
31
ID_AA64SMFR0_EL1.FA64: bit 63
32
33
ID_AA64MMFR0_EL1.ECV: bits 63-60
34
35
ID_AA64MMFR1_EL1.AFP: bits 47-44
36
37
ID_AA64MMFR2_EL1.AT: bits 35-32
38
39
ID_AA64ISAR0_EL1.RNDR: bits 63-60
40
41
ID_AA64ISAR1_EL1.FRINTTS: bits 35-32
42
ID_AA64ISAR1_EL1.BF16: bits 47-44
43
ID_AA64ISAR1_EL1.DGH: bits 51-48
44
ID_AA64ISAR1_EL1.I8MM: bits 55-52
45
46
ID_AA64ISAR2_EL1.WFxT: bits 3-0
47
ID_AA64ISAR2_EL1.RPRES: bits 7-4
48
ID_AA64ISAR2_EL1.GPA3: bits 11-8
49
ID_AA64ISAR2_EL1.APA3: bits 15-12
50
51
The code is also refactored to use symbolic names for ID register fields
52
for better readability and maintainability.
53
54
The test case in tests/tcg/aarch64/sysregs.c is also updated to match
55
the intended behavior.
56
57
Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com>
58
Message-id: DS7PR12MB6309FB585E10772928F14271ACE79@DS7PR12MB6309.namprd12.prod.outlook.com
59
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
60
[PMM: use Sn_n_Cn_Cn_n syntax to work with older assemblers
61
that don't recognize id_aa64isar2_el1 and id_aa64mmfr2_el1]
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
62
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
63
---
10
hw/timer/nrf51_timer.c | 1 +
64
target/arm/helper.c | 96 +++++++++++++++++++++++++------
11
hw/timer/trace-events | 1 +
65
tests/tcg/aarch64/sysregs.c | 24 ++++++--
12
2 files changed, 2 insertions(+)
66
tests/tcg/aarch64/Makefile.target | 7 ++-
13
67
3 files changed, 103 insertions(+), 24 deletions(-)
14
diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c
68
69
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
70
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/timer/nrf51_timer.c
71
--- a/target/arm/helper.c
17
+++ b/hw/timer/nrf51_timer.c
72
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static void nrf51_timer_write(void *opaque, hwaddr offset,
73
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
19
74
#ifdef CONFIG_USER_ONLY
20
idx = (offset - NRF51_TIMER_TASK_CAPTURE_0) / 4;
75
static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
21
s->cc[idx] = s->counter;
76
{ .name = "ID_AA64PFR0_EL1",
22
+ trace_nrf51_timer_set_count(s->id, idx, s->counter);
77
- .exported_bits = 0x000f000f00ff0000,
23
}
78
- .fixed_bits = 0x0000000000000011 },
24
break;
79
+ .exported_bits = R_ID_AA64PFR0_FP_MASK |
25
case NRF51_TIMER_EVENT_COMPARE_0 ... NRF51_TIMER_EVENT_COMPARE_3:
80
+ R_ID_AA64PFR0_ADVSIMD_MASK |
26
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
81
+ R_ID_AA64PFR0_SVE_MASK |
82
+ R_ID_AA64PFR0_DIT_MASK,
83
+ .fixed_bits = (0x1u << R_ID_AA64PFR0_EL0_SHIFT) |
84
+ (0x1u << R_ID_AA64PFR0_EL1_SHIFT) },
85
{ .name = "ID_AA64PFR1_EL1",
86
- .exported_bits = 0x00000000000000f0 },
87
+ .exported_bits = R_ID_AA64PFR1_BT_MASK |
88
+ R_ID_AA64PFR1_SSBS_MASK |
89
+ R_ID_AA64PFR1_MTE_MASK |
90
+ R_ID_AA64PFR1_SME_MASK },
91
{ .name = "ID_AA64PFR*_EL1_RESERVED",
92
- .is_glob = true },
93
- { .name = "ID_AA64ZFR0_EL1" },
94
+ .is_glob = true },
95
+ { .name = "ID_AA64ZFR0_EL1",
96
+ .exported_bits = R_ID_AA64ZFR0_SVEVER_MASK |
97
+ R_ID_AA64ZFR0_AES_MASK |
98
+ R_ID_AA64ZFR0_BITPERM_MASK |
99
+ R_ID_AA64ZFR0_BFLOAT16_MASK |
100
+ R_ID_AA64ZFR0_SHA3_MASK |
101
+ R_ID_AA64ZFR0_SM4_MASK |
102
+ R_ID_AA64ZFR0_I8MM_MASK |
103
+ R_ID_AA64ZFR0_F32MM_MASK |
104
+ R_ID_AA64ZFR0_F64MM_MASK },
105
+ { .name = "ID_AA64SMFR0_EL1",
106
+ .exported_bits = R_ID_AA64SMFR0_F32F32_MASK |
107
+ R_ID_AA64SMFR0_B16F32_MASK |
108
+ R_ID_AA64SMFR0_F16F32_MASK |
109
+ R_ID_AA64SMFR0_I8I32_MASK |
110
+ R_ID_AA64SMFR0_F64F64_MASK |
111
+ R_ID_AA64SMFR0_I16I64_MASK |
112
+ R_ID_AA64SMFR0_FA64_MASK },
113
{ .name = "ID_AA64MMFR0_EL1",
114
- .fixed_bits = 0x00000000ff000000 },
115
- { .name = "ID_AA64MMFR1_EL1" },
116
+ .exported_bits = R_ID_AA64MMFR0_ECV_MASK,
117
+ .fixed_bits = (0xfu << R_ID_AA64MMFR0_TGRAN64_SHIFT) |
118
+ (0xfu << R_ID_AA64MMFR0_TGRAN4_SHIFT) },
119
+ { .name = "ID_AA64MMFR1_EL1",
120
+ .exported_bits = R_ID_AA64MMFR1_AFP_MASK },
121
+ { .name = "ID_AA64MMFR2_EL1",
122
+ .exported_bits = R_ID_AA64MMFR2_AT_MASK },
123
{ .name = "ID_AA64MMFR*_EL1_RESERVED",
124
- .is_glob = true },
125
+ .is_glob = true },
126
{ .name = "ID_AA64DFR0_EL1",
127
- .fixed_bits = 0x0000000000000006 },
128
- { .name = "ID_AA64DFR1_EL1" },
129
+ .fixed_bits = (0x6u << R_ID_AA64DFR0_DEBUGVER_SHIFT) },
130
+ { .name = "ID_AA64DFR1_EL1" },
131
{ .name = "ID_AA64DFR*_EL1_RESERVED",
132
- .is_glob = true },
133
+ .is_glob = true },
134
{ .name = "ID_AA64AFR*",
135
- .is_glob = true },
136
+ .is_glob = true },
137
{ .name = "ID_AA64ISAR0_EL1",
138
- .exported_bits = 0x00fffffff0fffff0 },
139
+ .exported_bits = R_ID_AA64ISAR0_AES_MASK |
140
+ R_ID_AA64ISAR0_SHA1_MASK |
141
+ R_ID_AA64ISAR0_SHA2_MASK |
142
+ R_ID_AA64ISAR0_CRC32_MASK |
143
+ R_ID_AA64ISAR0_ATOMIC_MASK |
144
+ R_ID_AA64ISAR0_RDM_MASK |
145
+ R_ID_AA64ISAR0_SHA3_MASK |
146
+ R_ID_AA64ISAR0_SM3_MASK |
147
+ R_ID_AA64ISAR0_SM4_MASK |
148
+ R_ID_AA64ISAR0_DP_MASK |
149
+ R_ID_AA64ISAR0_FHM_MASK |
150
+ R_ID_AA64ISAR0_TS_MASK |
151
+ R_ID_AA64ISAR0_RNDR_MASK },
152
{ .name = "ID_AA64ISAR1_EL1",
153
- .exported_bits = 0x000000f0ffffffff },
154
+ .exported_bits = R_ID_AA64ISAR1_DPB_MASK |
155
+ R_ID_AA64ISAR1_APA_MASK |
156
+ R_ID_AA64ISAR1_API_MASK |
157
+ R_ID_AA64ISAR1_JSCVT_MASK |
158
+ R_ID_AA64ISAR1_FCMA_MASK |
159
+ R_ID_AA64ISAR1_LRCPC_MASK |
160
+ R_ID_AA64ISAR1_GPA_MASK |
161
+ R_ID_AA64ISAR1_GPI_MASK |
162
+ R_ID_AA64ISAR1_FRINTTS_MASK |
163
+ R_ID_AA64ISAR1_SB_MASK |
164
+ R_ID_AA64ISAR1_BF16_MASK |
165
+ R_ID_AA64ISAR1_DGH_MASK |
166
+ R_ID_AA64ISAR1_I8MM_MASK },
167
+ { .name = "ID_AA64ISAR2_EL1",
168
+ .exported_bits = R_ID_AA64ISAR2_WFXT_MASK |
169
+ R_ID_AA64ISAR2_RPRES_MASK |
170
+ R_ID_AA64ISAR2_GPA3_MASK |
171
+ R_ID_AA64ISAR2_APA3_MASK },
172
{ .name = "ID_AA64ISAR*_EL1_RESERVED",
173
- .is_glob = true },
174
+ .is_glob = true },
175
};
176
modify_arm_cp_regs(v8_idregs, v8_user_idregs);
177
#endif
178
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
179
#ifdef CONFIG_USER_ONLY
180
static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
181
{ .name = "MIDR_EL1",
182
- .exported_bits = 0x00000000ffffffff },
183
- { .name = "REVIDR_EL1" },
184
+ .exported_bits = R_MIDR_EL1_REVISION_MASK |
185
+ R_MIDR_EL1_PARTNUM_MASK |
186
+ R_MIDR_EL1_ARCHITECTURE_MASK |
187
+ R_MIDR_EL1_VARIANT_MASK |
188
+ R_MIDR_EL1_IMPLEMENTER_MASK },
189
+ { .name = "REVIDR_EL1" },
190
};
191
modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
192
#endif
193
diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c
27
index XXXXXXX..XXXXXXX 100644
194
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/timer/trace-events
195
--- a/tests/tcg/aarch64/sysregs.c
29
+++ b/hw/timer/trace-events
196
+++ b/tests/tcg/aarch64/sysregs.c
30
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
197
@@ -XXX,XX +XXX,XX @@
31
# nrf51_timer.c
198
#define HWCAP_CPUID (1 << 11)
32
nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
199
#endif
33
nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
200
34
+nrf51_timer_set_count(uint8_t timer_id, uint8_t counter_id, uint32_t value) "timer %u counter %u count 0x%" PRIx32
201
+/*
35
202
+ * Older assemblers don't recognize newer system register names,
36
# bcm2835_systmr.c
203
+ * but we can still access them by the Sn_n_Cn_Cn_n syntax.
37
bcm2835_systmr_irq(bool enable) "timer irq state %u"
204
+ */
205
+#define SYS_ID_AA64ISAR2_EL1 S3_0_C0_C6_2
206
+#define SYS_ID_AA64MMFR2_EL1 S3_0_C0_C7_2
207
+
208
int failed_bit_count;
209
210
/* Read and print system register `id' value */
211
@@ -XXX,XX +XXX,XX @@ int main(void)
212
* minimum valid fields - for the purposes of this check allowed
213
* to have non-zero values.
214
*/
215
- get_cpu_reg_check_mask(id_aa64isar0_el1, _m(00ff,ffff,f0ff,fff0));
216
- get_cpu_reg_check_mask(id_aa64isar1_el1, _m(0000,00f0,ffff,ffff));
217
+ get_cpu_reg_check_mask(id_aa64isar0_el1, _m(f0ff,ffff,f0ff,fff0));
218
+ get_cpu_reg_check_mask(id_aa64isar1_el1, _m(00ff,f0ff,ffff,ffff));
219
+ get_cpu_reg_check_mask(SYS_ID_AA64ISAR2_EL1, _m(0000,0000,0000,ffff));
220
/* TGran4 & TGran64 as pegged to -1 */
221
- get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(0000,0000,ff00,0000));
222
- get_cpu_reg_check_zero(id_aa64mmfr1_el1);
223
+ get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(f000,0000,ff00,0000));
224
+ get_cpu_reg_check_mask(id_aa64mmfr1_el1, _m(0000,f000,0000,0000));
225
+ get_cpu_reg_check_mask(SYS_ID_AA64MMFR2_EL1, _m(0000,000f,0000,0000));
226
/* EL1/EL0 reported as AA64 only */
227
get_cpu_reg_check_mask(id_aa64pfr0_el1, _m(000f,000f,00ff,0011));
228
- get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0000,00f0));
229
+ get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0f00,0fff));
230
/* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */
231
get_cpu_reg_check_mask(id_aa64dfr0_el1, _m(0000,0000,0000,0006));
232
get_cpu_reg_check_zero(id_aa64dfr1_el1);
233
- get_cpu_reg_check_zero(id_aa64zfr0_el1);
234
+ get_cpu_reg_check_mask(id_aa64zfr0_el1, _m(0ff0,ff0f,00ff,00ff));
235
+#ifdef HAS_ARMV9_SME
236
+ get_cpu_reg_check_mask(id_aa64smfr0_el1, _m(80f1,00fd,0000,0000));
237
+#endif
238
239
get_cpu_reg_check_zero(id_aa64afr0_el1);
240
get_cpu_reg_check_zero(id_aa64afr1_el1);
241
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
242
index XXXXXXX..XXXXXXX 100644
243
--- a/tests/tcg/aarch64/Makefile.target
244
+++ b/tests/tcg/aarch64/Makefile.target
245
@@ -XXX,XX +XXX,XX @@ config-cc.mak: Makefile
246
     $(call cc-option,-march=armv8.1-a+sve2, CROSS_CC_HAS_SVE2); \
247
     $(call cc-option,-march=armv8.3-a, CROSS_CC_HAS_ARMV8_3); \
248
     $(call cc-option,-mbranch-protection=standard, CROSS_CC_HAS_ARMV8_BTI); \
249
-     $(call cc-option,-march=armv8.5-a+memtag, CROSS_CC_HAS_ARMV8_MTE)) 3> config-cc.mak
250
+     $(call cc-option,-march=armv8.5-a+memtag, CROSS_CC_HAS_ARMV8_MTE); \
251
+     $(call cc-option,-march=armv9-a+sme, CROSS_CC_HAS_ARMV9_SME)) 3> config-cc.mak
252
-include config-cc.mak
253
254
# Pauth Tests
255
@@ -XXX,XX +XXX,XX @@ endif
256
ifneq ($(CROSS_CC_HAS_SVE),)
257
# System Registers Tests
258
AARCH64_TESTS += sysregs
259
+ifneq ($(CROSS_CC_HAS_ARMV9_SME),)
260
+sysregs: CFLAGS+=-march=armv9-a+sme -DHAS_ARMV9_SME
261
+else
262
sysregs: CFLAGS+=-march=armv8.1-a+sve
263
+endif
264
265
# SVE ioctl test
266
AARCH64_TESTS += sve-ioctls
38
--
267
--
39
2.20.1
268
2.25.1
40
41
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
The current interface includes a loop; change it to load a
3
This function is not used anywhere outside this file,
4
single element. We will then be able to use the function
4
so we can make the function "static void".
5
for ld{2,3,4} where individual vector elements are not adjacent.
6
5
7
Replace each call with the simplest possible loop over active
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
elements.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20221216214924.4711-2-philmd@linaro.org
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200508154359.7494-11-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
11
---
15
target/arm/sve_helper.c | 124 ++++++++++++++++++++--------------------
12
include/hw/arm/smmu-common.h | 3 ---
16
1 file changed, 63 insertions(+), 61 deletions(-)
13
hw/arm/smmu-common.c | 2 +-
14
2 files changed, 1 insertion(+), 4 deletions(-)
17
15
18
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
16
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
19
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/sve_helper.c
18
--- a/include/hw/arm/smmu-common.h
21
+++ b/target/arm/sve_helper.c
19
+++ b/include/hw/arm/smmu-common.h
22
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
20
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
23
*/
21
/* Unmap the range of all the notifiers registered to any IOMMU mr */
24
22
void smmu_inv_notifiers_all(SMMUState *s);
25
/*
23
26
- * Load elements into @vd, controlled by @vg, from @host + @mem_ofs.
24
-/* Unmap the range of all the notifiers registered to @mr */
27
- * Memory is valid through @host + @mem_max. The register element
25
-void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr);
28
- * indices are inferred from @mem_ofs, as modified by the types for
26
-
29
- * which the helper is built. Return the @mem_ofs of the first element
27
#endif /* HW_ARM_SMMU_COMMON_H */
30
- * not loaded (which is @mem_max if they are all loaded).
28
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
31
- *
29
index XXXXXXX..XXXXXXX 100644
32
- * For softmmu, we have fully validated the guest page. For user-only,
30
--- a/hw/arm/smmu-common.c
33
- * we cannot fully validate without taking the mmap lock, but since we
31
+++ b/hw/arm/smmu-common.c
34
- * know the access is within one host page, if any access is valid they
32
@@ -XXX,XX +XXX,XX @@ static void smmu_unmap_notifier_range(IOMMUNotifier *n)
35
- * all must be valid. However, when @vg is all false, it may be that
36
- * no access is valid.
37
+ * Load one element into @vd + @reg_off from @host.
38
+ * The controlling predicate is known to be true.
39
*/
40
-typedef intptr_t sve_ld1_host_fn(void *vd, void *vg, void *host,
41
- intptr_t mem_ofs, intptr_t mem_max);
42
+typedef void sve_ldst1_host_fn(void *vd, intptr_t reg_off, void *host);
43
44
/*
45
* Load one element into @vd + @reg_off from (@env, @vaddr, @ra).
46
@@ -XXX,XX +XXX,XX @@ typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
47
*/
48
49
#define DO_LD_HOST(NAME, H, TYPEE, TYPEM, HOST) \
50
-static intptr_t sve_##NAME##_host(void *vd, void *vg, void *host, \
51
- intptr_t mem_off, const intptr_t mem_max) \
52
-{ \
53
- intptr_t reg_off = mem_off * (sizeof(TYPEE) / sizeof(TYPEM)); \
54
- uint64_t *pg = vg; \
55
- while (mem_off + sizeof(TYPEM) <= mem_max) { \
56
- TYPEM val = 0; \
57
- if (likely((pg[reg_off >> 6] >> (reg_off & 63)) & 1)) { \
58
- val = HOST(host + mem_off); \
59
- } \
60
- *(TYPEE *)(vd + H(reg_off)) = val; \
61
- mem_off += sizeof(TYPEM), reg_off += sizeof(TYPEE); \
62
- } \
63
- return mem_off; \
64
+static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
65
+{ \
66
+ TYPEM val = HOST(host); \
67
+ *(TYPEE *)(vd + H(reg_off)) = val; \
68
}
33
}
69
34
70
#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \
35
/* Unmap all notifiers attached to @mr */
71
@@ -XXX,XX +XXX,XX @@ static inline bool test_host_page(void *host)
36
-inline void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr)
72
static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
37
+static void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr)
73
uint32_t desc, const uintptr_t retaddr,
74
const int esz, const int msz,
75
- sve_ld1_host_fn *host_fn,
76
+ sve_ldst1_host_fn *host_fn,
77
sve_ldst1_tlb_fn *tlb_fn)
78
{
38
{
79
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
39
IOMMUNotifier *n;
80
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
81
if (likely(split == mem_max)) {
82
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
83
if (test_host_page(host)) {
84
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
85
- tcg_debug_assert(mem_off == mem_max);
86
+ intptr_t i = reg_off;
87
+ host -= mem_off;
88
+ do {
89
+ host_fn(vd, i, host + (i >> diffsz));
90
+ i = find_next_active(vg, i + (1 << esz), reg_max, esz);
91
+ } while (i < reg_max);
92
/* After having taken any fault, zero leading inactive elements. */
93
swap_memzero(vd, reg_off);
94
return;
95
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
96
*/
97
#ifdef CONFIG_USER_ONLY
98
swap_memzero(&scratch, reg_off);
99
- host_fn(&scratch, vg, g2h(addr), mem_off, mem_max);
100
+ host = g2h(addr);
101
+ do {
102
+ host_fn(&scratch, reg_off, host + (reg_off >> diffsz));
103
+ reg_off += 1 << esz;
104
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
105
+ } while (reg_off < reg_max);
106
#else
107
memset(&scratch, 0, reg_max);
108
goto start;
109
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
110
host = tlb_vaddr_to_host(env, addr + mem_off,
111
MMU_DATA_LOAD, mmu_idx);
112
if (host) {
113
- mem_off = host_fn(&scratch, vg, host - mem_off,
114
- mem_off, split);
115
- reg_off = mem_off << diffsz;
116
+ host -= mem_off;
117
+ do {
118
+ host_fn(&scratch, reg_off, host + mem_off);
119
+ reg_off += 1 << esz;
120
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
121
+ mem_off = reg_off >> diffsz;
122
+ } while (split - mem_off >= (1 << msz));
123
continue;
124
}
125
}
126
@@ -XXX,XX +XXX,XX @@ static void record_fault(CPUARMState *env, uintptr_t i, uintptr_t oprsz)
127
static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
128
uint32_t desc, const uintptr_t retaddr,
129
const int esz, const int msz,
130
- sve_ld1_host_fn *host_fn,
131
+ sve_ldst1_host_fn *host_fn,
132
sve_ldst1_tlb_fn *tlb_fn)
133
{
134
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
135
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
136
const int diffsz = esz - msz;
137
const intptr_t reg_max = simd_oprsz(desc);
138
const intptr_t mem_max = reg_max >> diffsz;
139
- intptr_t split, reg_off, mem_off;
140
+ intptr_t split, reg_off, mem_off, i;
141
void *host;
142
143
/* Skip to the first active element. */
144
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
145
if (likely(split == mem_max)) {
146
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
147
if (test_host_page(host)) {
148
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
149
- tcg_debug_assert(mem_off == mem_max);
150
+ i = reg_off;
151
+ host -= mem_off;
152
+ do {
153
+ host_fn(vd, i, host + (i >> diffsz));
154
+ i = find_next_active(vg, i + (1 << esz), reg_max, esz);
155
+ } while (i < reg_max);
156
/* After any fault, zero any leading inactive elements. */
157
swap_memzero(vd, reg_off);
158
return;
159
}
160
}
161
162
-#ifdef CONFIG_USER_ONLY
163
- /*
164
- * The page(s) containing this first element at ADDR+MEM_OFF must
165
- * be valid. Considering that this first element may be misaligned
166
- * and cross a page boundary itself, take the rest of the page from
167
- * the last byte of the element.
168
- */
169
- split = max_for_page(addr, mem_off + (1 << msz) - 1, mem_max);
170
- mem_off = host_fn(vd, vg, g2h(addr), mem_off, split);
171
-
172
- /* After any fault, zero any leading inactive elements. */
173
- swap_memzero(vd, reg_off);
174
- reg_off = mem_off << diffsz;
175
-#else
176
/*
177
* Perform one normal read, which will fault or not.
178
* But it is likely to bring the page into the tlb.
179
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
180
if (split >= (1 << msz)) {
181
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
182
if (host) {
183
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, split);
184
- reg_off = mem_off << diffsz;
185
+ host -= mem_off;
186
+ do {
187
+ host_fn(vd, reg_off, host + mem_off);
188
+ reg_off += 1 << esz;
189
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
190
+ mem_off = reg_off >> diffsz;
191
+ } while (split - mem_off >= (1 << msz));
192
}
193
}
194
-#endif
195
196
record_fault(env, reg_off, reg_max);
197
}
198
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
199
*/
200
static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
201
uint32_t desc, const int esz, const int msz,
202
- sve_ld1_host_fn *host_fn)
203
+ sve_ldst1_host_fn *host_fn)
204
{
205
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
206
void *vd = &env->vfp.zregs[rd];
207
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
208
host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_idx);
209
if (likely(page_check_range(addr, mem_max, PAGE_READ) == 0)) {
210
/* The entire operation is valid and will not fault. */
211
- host_fn(vd, vg, host, 0, mem_max);
212
+ reg_off = 0;
213
+ do {
214
+ mem_off = reg_off >> diffsz;
215
+ host_fn(vd, reg_off, host + mem_off);
216
+ reg_off += 1 << esz;
217
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
218
+ } while (reg_off < reg_max);
219
return;
220
}
221
#endif
222
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
223
if (page_check_range(addr + mem_off, 1 << msz, PAGE_READ) == 0) {
224
/* At least one load is valid; take the rest of the page. */
225
split = max_for_page(addr, mem_off + (1 << msz) - 1, mem_max);
226
- mem_off = host_fn(vd, vg, host, mem_off, split);
227
- reg_off = mem_off << diffsz;
228
+ do {
229
+ host_fn(vd, reg_off, host + mem_off);
230
+ reg_off += 1 << esz;
231
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
232
+ mem_off = reg_off >> diffsz;
233
+ } while (split - mem_off >= (1 << msz));
234
}
235
#else
236
/*
237
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
238
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
239
split = max_for_page(addr, mem_off, mem_max);
240
if (host && split >= (1 << msz)) {
241
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, split);
242
- reg_off = mem_off << diffsz;
243
+ host -= mem_off;
244
+ do {
245
+ host_fn(vd, reg_off, host + mem_off);
246
+ reg_off += 1 << esz;
247
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
248
+ mem_off = reg_off >> diffsz;
249
+ } while (split - mem_off >= (1 << msz));
250
}
251
#endif
252
40
253
--
41
--
254
2.20.1
42
2.25.1
255
43
256
44
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
When using Clang ("Apple clang version 14.0.0 (clang-1400.0.29.202)")
4
and building with -Wall we get:
5
6
hw/arm/smmu-common.c:173:33: warning: static function 'smmu_hash_remove_by_asid_iova' is used in an inline function with external linkage [-Wstatic-in-inline]
7
hw/arm/smmu-common.h:170:1: note: use 'static' to give inline function 'smmu_iotlb_inv_iova' internal linkage
8
void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
9
^
10
static
11
12
None of our code base require / use inlined functions with external
13
linkage. Some places use internal inlining in the hot path. These
14
two functions are certainly not in any hot path and don't justify
15
any inlining, so these are likely oversights rather than intentional.
16
17
Reported-by: Stefan Weil <sw@weilnetz.de>
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
19
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20200508154359.7494-19-richard.henderson@linaro.org
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Reviewed-by: Eric Auger <eric.auger@redhat.com>
22
Message-id: 20221216214924.4711-3-philmd@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
24
---
8
target/arm/sve_helper.c | 208 +++++++++++++++++++++-------------------
25
hw/arm/smmu-common.c | 13 ++++++-------
9
1 file changed, 109 insertions(+), 99 deletions(-)
26
1 file changed, 6 insertions(+), 7 deletions(-)
10
27
11
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
28
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
12
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/sve_helper.c
30
--- a/hw/arm/smmu-common.c
14
+++ b/target/arm/sve_helper.c
31
+++ b/hw/arm/smmu-common.c
15
@@ -XXX,XX +XXX,XX @@ static target_ulong off_zd_d(void *reg, intptr_t reg_ofs)
32
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *new)
16
return *(uint64_t *)(reg + reg_ofs);
33
g_hash_table_insert(bs->iotlb, key, new);
17
}
34
}
18
35
19
-static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
36
-inline void smmu_iotlb_inv_all(SMMUState *s)
20
- target_ulong base, uint32_t desc, uintptr_t ra,
37
+void smmu_iotlb_inv_all(SMMUState *s)
21
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
22
+static inline QEMU_ALWAYS_INLINE
23
+void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
24
+ target_ulong base, uint32_t desc, uintptr_t retaddr,
25
+ int esize, int msize, zreg_off_fn *off_fn,
26
+ sve_ldst1_host_fn *host_fn,
27
+ sve_ldst1_tlb_fn *tlb_fn)
28
{
38
{
29
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
39
trace_smmu_iotlb_inv_all();
30
- intptr_t i, oprsz = simd_oprsz(desc);
40
g_hash_table_remove_all(s->iotlb);
31
- ARMVectorReg scratch = { };
41
@@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value,
32
+ const int mmu_idx = cpu_mmu_index(env, false);
42
((entry->iova & ~info->mask) == info->iova);
33
+ const intptr_t reg_max = simd_oprsz(desc);
34
+ ARMVectorReg scratch;
35
+ intptr_t reg_off;
36
+ SVEHostPage info, info2;
37
38
- for (i = 0; i < oprsz; ) {
39
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
40
+ memset(&scratch, 0, reg_max);
41
+ reg_off = 0;
42
+ do {
43
+ uint64_t pg = vg[reg_off >> 6];
44
do {
45
if (likely(pg & 1)) {
46
- target_ulong off = off_fn(vm, i);
47
- tlb_fn(env, &scratch, i, base + (off << scale), ra);
48
+ target_ulong addr = base + (off_fn(vm, reg_off) << scale);
49
+ target_ulong in_page = -(addr | TARGET_PAGE_MASK);
50
+
51
+ sve_probe_page(&info, false, env, addr, 0, MMU_DATA_LOAD,
52
+ mmu_idx, retaddr);
53
+
54
+ if (likely(in_page >= msize)) {
55
+ if (unlikely(info.flags & TLB_WATCHPOINT)) {
56
+ cpu_check_watchpoint(env_cpu(env), addr, msize,
57
+ info.attrs, BP_MEM_READ, retaddr);
58
+ }
59
+ /* TODO: MTE check */
60
+ host_fn(&scratch, reg_off, info.host);
61
+ } else {
62
+ /* Element crosses the page boundary. */
63
+ sve_probe_page(&info2, false, env, addr + in_page, 0,
64
+ MMU_DATA_LOAD, mmu_idx, retaddr);
65
+ if (unlikely((info.flags | info2.flags) & TLB_WATCHPOINT)) {
66
+ cpu_check_watchpoint(env_cpu(env), addr,
67
+ msize, info.attrs,
68
+ BP_MEM_READ, retaddr);
69
+ }
70
+ /* TODO: MTE check */
71
+ tlb_fn(env, &scratch, reg_off, addr, retaddr);
72
+ }
73
}
74
- i += 4, pg >>= 4;
75
- } while (i & 15);
76
- }
77
+ reg_off += esize;
78
+ pg >>= esize;
79
+ } while (reg_off & 63);
80
+ } while (reg_off < reg_max);
81
82
/* Wait until all exceptions have been raised to write back. */
83
- memcpy(vd, &scratch, oprsz);
84
+ memcpy(vd, &scratch, reg_max);
85
}
43
}
86
44
87
-static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
45
-inline void
88
- target_ulong base, uint32_t desc, uintptr_t ra,
46
-smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
89
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
47
- uint8_t tg, uint64_t num_pages, uint8_t ttl)
90
-{
48
+void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
91
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
49
+ uint8_t tg, uint64_t num_pages, uint8_t ttl)
92
- intptr_t i, oprsz = simd_oprsz(desc) / 8;
50
{
93
- ARMVectorReg scratch = { };
51
/* if tg is not set we use 4KB range invalidation */
94
-
52
uint8_t granule = tg ? tg * 2 + 10 : 12;
95
- for (i = 0; i < oprsz; i++) {
53
@@ -XXX,XX +XXX,XX @@ smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
96
- uint8_t pg = *(uint8_t *)(vg + H1(i));
54
&info);
97
- if (likely(pg & 1)) {
98
- target_ulong off = off_fn(vm, i * 8);
99
- tlb_fn(env, &scratch, i * 8, base + (off << scale), ra);
100
- }
101
- }
102
-
103
- /* Wait until all exceptions have been raised to write back. */
104
- memcpy(vd, &scratch, oprsz * 8);
105
+#define DO_LD1_ZPZ_S(MEM, OFS, MSZ) \
106
+void HELPER(sve_ld##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
107
+ void *vm, target_ulong base, uint32_t desc) \
108
+{ \
109
+ sve_ld1_z(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, \
110
+ off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
111
}
55
}
112
56
113
-#define DO_LD1_ZPZ_S(MEM, OFS) \
57
-inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
114
-void QEMU_FLATTEN HELPER(sve_ld##MEM##_##OFS) \
58
+void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
115
- (CPUARMState *env, void *vd, void *vg, void *vm, \
59
{
116
- target_ulong base, uint32_t desc) \
60
trace_smmu_iotlb_inv_asid(asid);
117
-{ \
61
g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid);
118
- sve_ld1_zs(env, vd, vg, vm, base, desc, GETPC(), \
62
@@ -XXX,XX +XXX,XX @@ error:
119
- off_##OFS##_s, sve_ld1##MEM##_tlb); \
63
*
120
+#define DO_LD1_ZPZ_D(MEM, OFS, MSZ) \
64
* return 0 on success
121
+void HELPER(sve_ld##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
65
*/
122
+ void *vm, target_ulong base, uint32_t desc) \
66
-inline int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
123
+{ \
67
- SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
124
+ sve_ld1_z(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, \
68
+int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
125
+ off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
69
+ SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
126
}
70
{
127
71
if (!cfg->aa64) {
128
-#define DO_LD1_ZPZ_D(MEM, OFS) \
72
/*
129
-void QEMU_FLATTEN HELPER(sve_ld##MEM##_##OFS) \
130
- (CPUARMState *env, void *vd, void *vg, void *vm, \
131
- target_ulong base, uint32_t desc) \
132
-{ \
133
- sve_ld1_zd(env, vd, vg, vm, base, desc, GETPC(), \
134
- off_##OFS##_d, sve_ld1##MEM##_tlb); \
135
-}
136
+DO_LD1_ZPZ_S(bsu, zsu, MO_8)
137
+DO_LD1_ZPZ_S(bsu, zss, MO_8)
138
+DO_LD1_ZPZ_D(bdu, zsu, MO_8)
139
+DO_LD1_ZPZ_D(bdu, zss, MO_8)
140
+DO_LD1_ZPZ_D(bdu, zd, MO_8)
141
142
-DO_LD1_ZPZ_S(bsu, zsu)
143
-DO_LD1_ZPZ_S(bsu, zss)
144
-DO_LD1_ZPZ_D(bdu, zsu)
145
-DO_LD1_ZPZ_D(bdu, zss)
146
-DO_LD1_ZPZ_D(bdu, zd)
147
+DO_LD1_ZPZ_S(bss, zsu, MO_8)
148
+DO_LD1_ZPZ_S(bss, zss, MO_8)
149
+DO_LD1_ZPZ_D(bds, zsu, MO_8)
150
+DO_LD1_ZPZ_D(bds, zss, MO_8)
151
+DO_LD1_ZPZ_D(bds, zd, MO_8)
152
153
-DO_LD1_ZPZ_S(bss, zsu)
154
-DO_LD1_ZPZ_S(bss, zss)
155
-DO_LD1_ZPZ_D(bds, zsu)
156
-DO_LD1_ZPZ_D(bds, zss)
157
-DO_LD1_ZPZ_D(bds, zd)
158
+DO_LD1_ZPZ_S(hsu_le, zsu, MO_16)
159
+DO_LD1_ZPZ_S(hsu_le, zss, MO_16)
160
+DO_LD1_ZPZ_D(hdu_le, zsu, MO_16)
161
+DO_LD1_ZPZ_D(hdu_le, zss, MO_16)
162
+DO_LD1_ZPZ_D(hdu_le, zd, MO_16)
163
164
-DO_LD1_ZPZ_S(hsu_le, zsu)
165
-DO_LD1_ZPZ_S(hsu_le, zss)
166
-DO_LD1_ZPZ_D(hdu_le, zsu)
167
-DO_LD1_ZPZ_D(hdu_le, zss)
168
-DO_LD1_ZPZ_D(hdu_le, zd)
169
+DO_LD1_ZPZ_S(hsu_be, zsu, MO_16)
170
+DO_LD1_ZPZ_S(hsu_be, zss, MO_16)
171
+DO_LD1_ZPZ_D(hdu_be, zsu, MO_16)
172
+DO_LD1_ZPZ_D(hdu_be, zss, MO_16)
173
+DO_LD1_ZPZ_D(hdu_be, zd, MO_16)
174
175
-DO_LD1_ZPZ_S(hsu_be, zsu)
176
-DO_LD1_ZPZ_S(hsu_be, zss)
177
-DO_LD1_ZPZ_D(hdu_be, zsu)
178
-DO_LD1_ZPZ_D(hdu_be, zss)
179
-DO_LD1_ZPZ_D(hdu_be, zd)
180
+DO_LD1_ZPZ_S(hss_le, zsu, MO_16)
181
+DO_LD1_ZPZ_S(hss_le, zss, MO_16)
182
+DO_LD1_ZPZ_D(hds_le, zsu, MO_16)
183
+DO_LD1_ZPZ_D(hds_le, zss, MO_16)
184
+DO_LD1_ZPZ_D(hds_le, zd, MO_16)
185
186
-DO_LD1_ZPZ_S(hss_le, zsu)
187
-DO_LD1_ZPZ_S(hss_le, zss)
188
-DO_LD1_ZPZ_D(hds_le, zsu)
189
-DO_LD1_ZPZ_D(hds_le, zss)
190
-DO_LD1_ZPZ_D(hds_le, zd)
191
+DO_LD1_ZPZ_S(hss_be, zsu, MO_16)
192
+DO_LD1_ZPZ_S(hss_be, zss, MO_16)
193
+DO_LD1_ZPZ_D(hds_be, zsu, MO_16)
194
+DO_LD1_ZPZ_D(hds_be, zss, MO_16)
195
+DO_LD1_ZPZ_D(hds_be, zd, MO_16)
196
197
-DO_LD1_ZPZ_S(hss_be, zsu)
198
-DO_LD1_ZPZ_S(hss_be, zss)
199
-DO_LD1_ZPZ_D(hds_be, zsu)
200
-DO_LD1_ZPZ_D(hds_be, zss)
201
-DO_LD1_ZPZ_D(hds_be, zd)
202
+DO_LD1_ZPZ_S(ss_le, zsu, MO_32)
203
+DO_LD1_ZPZ_S(ss_le, zss, MO_32)
204
+DO_LD1_ZPZ_D(sdu_le, zsu, MO_32)
205
+DO_LD1_ZPZ_D(sdu_le, zss, MO_32)
206
+DO_LD1_ZPZ_D(sdu_le, zd, MO_32)
207
208
-DO_LD1_ZPZ_S(ss_le, zsu)
209
-DO_LD1_ZPZ_S(ss_le, zss)
210
-DO_LD1_ZPZ_D(sdu_le, zsu)
211
-DO_LD1_ZPZ_D(sdu_le, zss)
212
-DO_LD1_ZPZ_D(sdu_le, zd)
213
+DO_LD1_ZPZ_S(ss_be, zsu, MO_32)
214
+DO_LD1_ZPZ_S(ss_be, zss, MO_32)
215
+DO_LD1_ZPZ_D(sdu_be, zsu, MO_32)
216
+DO_LD1_ZPZ_D(sdu_be, zss, MO_32)
217
+DO_LD1_ZPZ_D(sdu_be, zd, MO_32)
218
219
-DO_LD1_ZPZ_S(ss_be, zsu)
220
-DO_LD1_ZPZ_S(ss_be, zss)
221
-DO_LD1_ZPZ_D(sdu_be, zsu)
222
-DO_LD1_ZPZ_D(sdu_be, zss)
223
-DO_LD1_ZPZ_D(sdu_be, zd)
224
+DO_LD1_ZPZ_D(sds_le, zsu, MO_32)
225
+DO_LD1_ZPZ_D(sds_le, zss, MO_32)
226
+DO_LD1_ZPZ_D(sds_le, zd, MO_32)
227
228
-DO_LD1_ZPZ_D(sds_le, zsu)
229
-DO_LD1_ZPZ_D(sds_le, zss)
230
-DO_LD1_ZPZ_D(sds_le, zd)
231
+DO_LD1_ZPZ_D(sds_be, zsu, MO_32)
232
+DO_LD1_ZPZ_D(sds_be, zss, MO_32)
233
+DO_LD1_ZPZ_D(sds_be, zd, MO_32)
234
235
-DO_LD1_ZPZ_D(sds_be, zsu)
236
-DO_LD1_ZPZ_D(sds_be, zss)
237
-DO_LD1_ZPZ_D(sds_be, zd)
238
+DO_LD1_ZPZ_D(dd_le, zsu, MO_64)
239
+DO_LD1_ZPZ_D(dd_le, zss, MO_64)
240
+DO_LD1_ZPZ_D(dd_le, zd, MO_64)
241
242
-DO_LD1_ZPZ_D(dd_le, zsu)
243
-DO_LD1_ZPZ_D(dd_le, zss)
244
-DO_LD1_ZPZ_D(dd_le, zd)
245
-
246
-DO_LD1_ZPZ_D(dd_be, zsu)
247
-DO_LD1_ZPZ_D(dd_be, zss)
248
-DO_LD1_ZPZ_D(dd_be, zd)
249
+DO_LD1_ZPZ_D(dd_be, zsu, MO_64)
250
+DO_LD1_ZPZ_D(dd_be, zss, MO_64)
251
+DO_LD1_ZPZ_D(dd_be, zd, MO_64)
252
253
#undef DO_LD1_ZPZ_S
254
#undef DO_LD1_ZPZ_D
255
--
73
--
256
2.20.1
74
2.25.1
257
75
258
76
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
We have validated that addr+size does not cross a page boundary.
3
So far the GPT timers were unable to raise IRQs to the processor.
4
Therefore we need to validate exactly one page. We can achieve
5
that passing any value 1 <= x <= size to page_check_range.
6
4
7
Passing 1 will simplify the next patch.
5
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-5-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
8
---
14
accel/tcg/user-exec.c | 2 +-
9
include/hw/arm/fsl-imx7.h | 5 +++++
15
1 file changed, 1 insertion(+), 1 deletion(-)
10
hw/arm/fsl-imx7.c | 10 ++++++++++
11
2 files changed, 15 insertions(+)
16
12
17
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
13
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
18
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
19
--- a/accel/tcg/user-exec.c
15
--- a/include/hw/arm/fsl-imx7.h
20
+++ b/accel/tcg/user-exec.c
16
+++ b/include/hw/arm/fsl-imx7.h
21
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
17
@@ -XXX,XX +XXX,XX @@ enum FslIMX7IRQs {
22
g_assert_not_reached();
18
FSL_IMX7_USB2_IRQ = 42,
19
FSL_IMX7_USB3_IRQ = 40,
20
21
+ FSL_IMX7_GPT1_IRQ = 55,
22
+ FSL_IMX7_GPT2_IRQ = 54,
23
+ FSL_IMX7_GPT3_IRQ = 53,
24
+ FSL_IMX7_GPT4_IRQ = 52,
25
+
26
FSL_IMX7_WDOG1_IRQ = 78,
27
FSL_IMX7_WDOG2_IRQ = 79,
28
FSL_IMX7_WDOG3_IRQ = 10,
29
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/arm/fsl-imx7.c
32
+++ b/hw/arm/fsl-imx7.c
33
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
34
FSL_IMX7_GPT4_ADDR,
35
};
36
37
+ static const int FSL_IMX7_GPTn_IRQ[FSL_IMX7_NUM_GPTS] = {
38
+ FSL_IMX7_GPT1_IRQ,
39
+ FSL_IMX7_GPT2_IRQ,
40
+ FSL_IMX7_GPT3_IRQ,
41
+ FSL_IMX7_GPT4_IRQ,
42
+ };
43
+
44
s->gpt[i].ccm = IMX_CCM(&s->ccm);
45
sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
46
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]);
47
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
48
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
49
+ FSL_IMX7_GPTn_IRQ[i]));
23
}
50
}
24
51
25
- if (!guest_addr_valid(addr) || page_check_range(addr, size, flags) < 0) {
52
for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
26
+ if (!guest_addr_valid(addr) || page_check_range(addr, 1, flags) < 0) {
27
CPUState *cpu = env_cpu(env);
28
CPUClass *cc = CPU_GET_CLASS(cpu);
29
cc->tlb_fill(cpu, addr, size, access_type, MMU_USER_IDX, false,
30
--
53
--
31
2.20.1
54
2.25.1
32
33
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
First use of the new helper functions, so we can remove the
3
CCM derived clocks will have to be added later.
4
unused markup. No longer need a scratch for user-only, as
5
we completely probe the page set before reading; system mode
6
still requires a scratch for MMIO.
7
4
5
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-12-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
8
---
13
target/arm/sve_helper.c | 188 +++++++++++++++++++++-------------------
9
hw/misc/imx7_ccm.c | 49 +++++++++++++++++++++++++++++++++++++---------
14
1 file changed, 97 insertions(+), 91 deletions(-)
10
1 file changed, 40 insertions(+), 9 deletions(-)
15
11
16
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
12
diff --git a/hw/misc/imx7_ccm.c b/hw/misc/imx7_ccm.c
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sve_helper.c
14
--- a/hw/misc/imx7_ccm.c
19
+++ b/target/arm/sve_helper.c
15
+++ b/hw/misc/imx7_ccm.c
20
@@ -XXX,XX +XXX,XX @@ typedef struct {
16
@@ -XXX,XX +XXX,XX @@
21
* final element on each page. Identify any single element that spans
17
#include "hw/misc/imx7_ccm.h"
22
* the page boundary. Return true if there are any active elements.
18
#include "migration/vmstate.h"
23
*/
19
24
-static bool __attribute__((unused))
20
+#include "trace.h"
25
-sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg,
21
+
26
- intptr_t reg_max, int esz, int msize)
22
+#define CKIH_FREQ 24000000 /* 24MHz crystal input */
27
+static bool sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr,
23
+
28
+ uint64_t *vg, intptr_t reg_max,
24
static void imx7_analog_reset(DeviceState *dev)
29
+ int esz, int msize)
30
{
25
{
31
const int esize = 1 << esz;
26
IMX7AnalogState *s = IMX7_ANALOG(dev);
32
const uint64_t pg_mask = pred_esz_masks[esz];
27
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx7_ccm = {
33
@@ -XXX,XX +XXX,XX @@ sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg,
28
static uint32_t imx7_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
34
* Control the generation of page faults with @fault. Return false if
35
* there is no work to do, which can only happen with @fault == FAULT_NO.
36
*/
37
-static bool __attribute__((unused))
38
-sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, CPUARMState *env,
39
- target_ulong addr, MMUAccessType access_type,
40
- uintptr_t retaddr)
41
+static bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault,
42
+ CPUARMState *env, target_ulong addr,
43
+ MMUAccessType access_type, uintptr_t retaddr)
44
{
29
{
45
int mmu_idx = cpu_mmu_index(env, false);
30
/*
46
int mem_off = info->mem_off_first[0];
31
- * This function is "consumed" by GPT emulation code, however on
47
@@ -XXX,XX +XXX,XX @@ static inline bool test_host_page(void *host)
32
- * i.MX7 each GPT block can have their own clock root. This means
48
/*
33
- * that this functions needs somehow to know requester's identity
49
* Common helper for all contiguous one-register predicated loads.
34
- * and the way to pass it: be it via additional IMXClk constants
50
*/
35
- * or by adding another argument to this method needs to be
51
-static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
36
- * figured out
52
- uint32_t desc, const uintptr_t retaddr,
37
+ * This function is "consumed" by GPT emulation code. Some clocks
53
- const int esz, const int msz,
38
+ * have fixed frequencies and we can provide requested frequency
54
- sve_ldst1_host_fn *host_fn,
39
+ * easily. However for CCM provided clocks (like IPG) each GPT
55
- sve_ldst1_tlb_fn *tlb_fn)
40
+ * timer can have its own clock root.
56
+static inline QEMU_ALWAYS_INLINE
41
+ * This means we need additionnal information when calling this
57
+void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
42
+ * function to know the requester's identity.
58
+ uint32_t desc, const uintptr_t retaddr,
43
*/
59
+ const int esz, const int msz,
44
- qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Not implemented\n",
60
+ sve_ldst1_host_fn *host_fn,
45
- TYPE_IMX7_CCM, __func__);
61
+ sve_ldst1_tlb_fn *tlb_fn)
46
- return 0;
62
{
47
+ uint32_t freq = 0;
63
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
48
+
64
- const int mmu_idx = get_mmuidx(oi);
49
+ switch (clock) {
65
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
50
+ case CLK_NONE:
66
void *vd = &env->vfp.zregs[rd];
51
+ break;
67
- const int diffsz = esz - msz;
52
+ case CLK_32k:
68
const intptr_t reg_max = simd_oprsz(desc);
53
+ freq = CKIL_FREQ;
69
- const intptr_t mem_max = reg_max >> diffsz;
54
+ break;
70
- ARMVectorReg scratch;
55
+ case CLK_HIGH:
71
+ intptr_t reg_off, reg_last, mem_off;
56
+ freq = CKIH_FREQ;
72
+ SVEContLdSt info;
57
+ break;
73
void *host;
58
+ case CLK_IPG:
74
- intptr_t split, reg_off, mem_off;
59
+ case CLK_IPG_HIGH:
75
+ int flags;
76
77
- /* Find the first active element. */
78
- reg_off = find_next_active(vg, 0, reg_max, esz);
79
- if (unlikely(reg_off == reg_max)) {
80
+ /* Find the active elements. */
81
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, 1 << msz)) {
82
/* The entire predicate was false; no load occurs. */
83
memset(vd, 0, reg_max);
84
return;
85
}
86
- mem_off = reg_off >> diffsz;
87
88
- /*
89
- * If the (remaining) load is entirely within a single page, then:
90
- * For softmmu, and the tlb hits, then no faults will occur;
91
- * For user-only, either the first load will fault or none will.
92
- * We can thus perform the load directly to the destination and
93
- * Vd will be unmodified on any exception path.
94
- */
95
- split = max_for_page(addr, mem_off, mem_max);
96
- if (likely(split == mem_max)) {
97
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
98
- if (test_host_page(host)) {
99
- intptr_t i = reg_off;
100
- host -= mem_off;
101
- do {
102
- host_fn(vd, i, host + (i >> diffsz));
103
- i = find_next_active(vg, i + (1 << esz), reg_max, esz);
104
- } while (i < reg_max);
105
- /* After having taken any fault, zero leading inactive elements. */
106
- swap_memzero(vd, reg_off);
107
- return;
108
- }
109
- }
110
+ /* Probe the page(s). Exit with exception for any invalid page. */
111
+ sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, retaddr);
112
113
- /*
114
- * Perform the predicated read into a temporary, thus ensuring
115
- * if the load of the last element faults, Vd is not modified.
116
- */
117
+ flags = info.page[0].flags | info.page[1].flags;
118
+ if (unlikely(flags != 0)) {
119
#ifdef CONFIG_USER_ONLY
120
- swap_memzero(&scratch, reg_off);
121
- host = g2h(addr);
122
- do {
123
- host_fn(&scratch, reg_off, host + (reg_off >> diffsz));
124
- reg_off += 1 << esz;
125
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
126
- } while (reg_off < reg_max);
127
+ g_assert_not_reached();
128
#else
129
- memset(&scratch, 0, reg_max);
130
- goto start;
131
- while (1) {
132
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
133
- if (reg_off >= reg_max) {
134
- break;
135
- }
136
- mem_off = reg_off >> diffsz;
137
- split = max_for_page(addr, mem_off, mem_max);
138
+ /*
60
+ /*
139
+ * At least one page includes MMIO (or watchpoints).
61
+ * For now we don't have a way to figure out the device this
140
+ * Any bus operation can fail with cpu_transaction_failed,
62
+ * function is called for. Until then the IPG derived clocks
141
+ * which for ARM will raise SyncExternal. Perform the load
63
+ * are left unimplemented.
142
+ * into scratch memory to preserve register state until the end.
143
+ */
64
+ */
144
+ ARMVectorReg scratch;
65
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Clock %d Not implemented\n",
145
66
+ TYPE_IMX7_CCM, __func__, clock);
146
- start:
67
+ break;
147
- if (split - mem_off >= (1 << msz)) {
68
+ default:
148
- /* At least one whole element on this page. */
69
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
149
- host = tlb_vaddr_to_host(env, addr + mem_off,
70
+ TYPE_IMX7_CCM, __func__, clock);
150
- MMU_DATA_LOAD, mmu_idx);
71
+ break;
151
- if (host) {
152
- host -= mem_off;
153
- do {
154
- host_fn(&scratch, reg_off, host + mem_off);
155
- reg_off += 1 << esz;
156
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
157
- mem_off = reg_off >> diffsz;
158
- } while (split - mem_off >= (1 << msz));
159
- continue;
160
+ memset(&scratch, 0, reg_max);
161
+ mem_off = info.mem_off_first[0];
162
+ reg_off = info.reg_off_first[0];
163
+ reg_last = info.reg_off_last[1];
164
+ if (reg_last < 0) {
165
+ reg_last = info.reg_off_split;
166
+ if (reg_last < 0) {
167
+ reg_last = info.reg_off_last[0];
168
}
169
}
170
171
- /*
172
- * Perform one normal read. This may fault, longjmping out to the
173
- * main loop in order to raise an exception. It may succeed, and
174
- * as a side-effect load the TLB entry for the next round. Finally,
175
- * in the extremely unlikely case we're performing this operation
176
- * on I/O memory, it may succeed but not bring in the TLB entry.
177
- * But even then we have still made forward progress.
178
- */
179
- tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
180
- reg_off += 1 << esz;
181
- }
182
-#endif
183
+ do {
184
+ uint64_t pg = vg[reg_off >> 6];
185
+ do {
186
+ if ((pg >> (reg_off & 63)) & 1) {
187
+ tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
188
+ }
189
+ reg_off += 1 << esz;
190
+ mem_off += 1 << msz;
191
+ } while (reg_off & 63);
192
+ } while (reg_off <= reg_last);
193
194
- memcpy(vd, &scratch, reg_max);
195
+ memcpy(vd, &scratch, reg_max);
196
+ return;
197
+#endif
198
+ }
72
+ }
199
+
73
+
200
+ /* The entire operation is in RAM, on valid pages. */
74
+ trace_ccm_clock_freq(clock, freq);
201
+
75
+
202
+ memset(vd, 0, reg_max);
76
+ return freq;
203
+ mem_off = info.mem_off_first[0];
204
+ reg_off = info.reg_off_first[0];
205
+ reg_last = info.reg_off_last[0];
206
+ host = info.page[0].host;
207
+
208
+ while (reg_off <= reg_last) {
209
+ uint64_t pg = vg[reg_off >> 6];
210
+ do {
211
+ if ((pg >> (reg_off & 63)) & 1) {
212
+ host_fn(vd, reg_off, host + mem_off);
213
+ }
214
+ reg_off += 1 << esz;
215
+ mem_off += 1 << msz;
216
+ } while (reg_off <= reg_last && (reg_off & 63));
217
+ }
218
+
219
+ /*
220
+ * Use the slow path to manage the cross-page misalignment.
221
+ * But we know this is RAM and cannot trap.
222
+ */
223
+ mem_off = info.mem_off_split;
224
+ if (unlikely(mem_off >= 0)) {
225
+ tlb_fn(env, vd, info.reg_off_split, addr + mem_off, retaddr);
226
+ }
227
+
228
+ mem_off = info.mem_off_first[1];
229
+ if (unlikely(mem_off >= 0)) {
230
+ reg_off = info.reg_off_first[1];
231
+ reg_last = info.reg_off_last[1];
232
+ host = info.page[1].host;
233
+
234
+ do {
235
+ uint64_t pg = vg[reg_off >> 6];
236
+ do {
237
+ if ((pg >> (reg_off & 63)) & 1) {
238
+ host_fn(vd, reg_off, host + mem_off);
239
+ }
240
+ reg_off += 1 << esz;
241
+ mem_off += 1 << msz;
242
+ } while (reg_off & 63);
243
+ } while (reg_off <= reg_last);
244
+ }
245
}
77
}
246
78
247
#define DO_LD1_1(NAME, ESZ) \
79
static void imx7_ccm_class_init(ObjectClass *klass, void *data)
248
--
80
--
249
2.20.1
81
2.25.1
250
251
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
The NRF51 series SoC have 3 timer peripherals, each having
3
The i.MX6UL doesn't support CLK_HIGH ou CLK_HIGH_DIV clock source.
4
4 counters. To help differentiate which peripheral is accessed,
5
display the timer ID in the trace events.
6
4
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20200504072822.18799-4-f4bug@amsat.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
8
---
12
include/hw/timer/nrf51_timer.h | 1 +
9
include/hw/timer/imx_gpt.h | 1 +
13
hw/arm/nrf51_soc.c | 5 +++++
10
hw/arm/fsl-imx6ul.c | 2 +-
14
hw/timer/nrf51_timer.c | 11 +++++++++--
11
hw/misc/imx6ul_ccm.c | 6 ------
15
hw/timer/trace-events | 4 ++--
12
hw/timer/imx_gpt.c | 25 +++++++++++++++++++++++++
16
4 files changed, 17 insertions(+), 4 deletions(-)
13
4 files changed, 27 insertions(+), 7 deletions(-)
17
14
18
diff --git a/include/hw/timer/nrf51_timer.h b/include/hw/timer/nrf51_timer.h
15
diff --git a/include/hw/timer/imx_gpt.h b/include/hw/timer/imx_gpt.h
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/timer/nrf51_timer.h
17
--- a/include/hw/timer/imx_gpt.h
21
+++ b/include/hw/timer/nrf51_timer.h
18
+++ b/include/hw/timer/imx_gpt.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct NRF51TimerState {
19
@@ -XXX,XX +XXX,XX @@
23
MemoryRegion iomem;
20
#define TYPE_IMX25_GPT "imx25.gpt"
24
qemu_irq irq;
21
#define TYPE_IMX31_GPT "imx31.gpt"
25
22
#define TYPE_IMX6_GPT "imx6.gpt"
26
+ uint8_t id;
23
+#define TYPE_IMX6UL_GPT "imx6ul.gpt"
27
QEMUTimer timer;
24
#define TYPE_IMX7_GPT "imx7.gpt"
28
int64_t timer_start_ns;
25
29
int64_t update_counter_ns;
26
#define TYPE_IMX_GPT TYPE_IMX25_GPT
30
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
27
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
31
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/arm/nrf51_soc.c
29
--- a/hw/arm/fsl-imx6ul.c
33
+++ b/hw/arm/nrf51_soc.c
30
+++ b/hw/arm/fsl-imx6ul.c
34
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
31
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
35
32
*/
36
/* TIMER */
33
for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
37
for (i = 0; i < NRF51_NUM_TIMERS; i++) {
34
snprintf(name, NAME_SIZE, "gpt%d", i);
38
+ object_property_set_uint(OBJECT(&s->timer[i]), i, "id", &err);
35
- object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT);
39
+ if (err) {
36
+ object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX6UL_GPT);
40
+ error_propagate(errp, err);
37
}
41
+ return;
38
42
+ }
39
/*
43
object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
40
diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c
44
if (err) {
45
error_propagate(errp, err);
46
diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c
47
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/timer/nrf51_timer.c
42
--- a/hw/misc/imx6ul_ccm.c
49
+++ b/hw/timer/nrf51_timer.c
43
+++ b/hw/misc/imx6ul_ccm.c
50
@@ -XXX,XX +XXX,XX @@
44
@@ -XXX,XX +XXX,XX @@ static uint32_t imx6ul_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
51
#include "hw/arm/nrf51.h"
45
case CLK_32k:
52
#include "hw/irq.h"
46
freq = CKIL_FREQ;
53
#include "hw/timer/nrf51_timer.h"
47
break;
54
+#include "hw/qdev-properties.h"
48
- case CLK_HIGH:
55
#include "migration/vmstate.h"
49
- freq = CKIH_FREQ;
56
#include "trace.h"
50
- break;
57
51
- case CLK_HIGH_DIV:
58
@@ -XXX,XX +XXX,XX @@ static uint64_t nrf51_timer_read(void *opaque, hwaddr offset, unsigned int size)
52
- freq = CKIH_FREQ / 8;
59
__func__, offset);
53
- break;
60
}
54
default:
61
55
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
62
- trace_nrf51_timer_read(offset, r, size);
56
TYPE_IMX6UL_CCM, __func__, clock);
63
+ trace_nrf51_timer_read(s->id, offset, r, size);
57
diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
64
58
index XXXXXXX..XXXXXXX 100644
65
return r;
59
--- a/hw/timer/imx_gpt.c
66
}
60
+++ b/hw/timer/imx_gpt.c
67
@@ -XXX,XX +XXX,XX @@ static void nrf51_timer_write(void *opaque, hwaddr offset,
61
@@ -XXX,XX +XXX,XX @@ static const IMXClk imx6_gpt_clocks[] = {
68
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
62
CLK_HIGH, /* 111 reference clock */
69
size_t idx;
70
71
- trace_nrf51_timer_write(offset, value, size);
72
+ trace_nrf51_timer_write(s->id, offset, value, size);
73
74
switch (offset) {
75
case NRF51_TIMER_TASK_START:
76
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nrf51_timer = {
77
}
78
};
63
};
79
64
80
+static Property nrf51_timer_properties[] = {
65
+static const IMXClk imx6ul_gpt_clocks[] = {
81
+ DEFINE_PROP_UINT8("id", NRF51TimerState, id, 0),
66
+ CLK_NONE, /* 000 No clock source */
82
+ DEFINE_PROP_END_OF_LIST(),
67
+ CLK_IPG, /* 001 ipg_clk, 532MHz*/
68
+ CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
69
+ CLK_EXT, /* 011 External clock */
70
+ CLK_32k, /* 100 ipg_clk_32k */
71
+ CLK_NONE, /* 101 not defined */
72
+ CLK_NONE, /* 110 not defined */
73
+ CLK_NONE, /* 111 not defined */
83
+};
74
+};
84
+
75
+
85
static void nrf51_timer_class_init(ObjectClass *klass, void *data)
76
static const IMXClk imx7_gpt_clocks[] = {
77
CLK_NONE, /* 000 No clock source */
78
CLK_IPG, /* 001 ipg_clk, 532MHz*/
79
@@ -XXX,XX +XXX,XX @@ static void imx6_gpt_init(Object *obj)
80
s->clocks = imx6_gpt_clocks;
81
}
82
83
+static void imx6ul_gpt_init(Object *obj)
84
+{
85
+ IMXGPTState *s = IMX_GPT(obj);
86
+
87
+ s->clocks = imx6ul_gpt_clocks;
88
+}
89
+
90
static void imx7_gpt_init(Object *obj)
86
{
91
{
87
DeviceClass *dc = DEVICE_CLASS(klass);
92
IMXGPTState *s = IMX_GPT(obj);
88
93
@@ -XXX,XX +XXX,XX @@ static const TypeInfo imx6_gpt_info = {
89
dc->reset = nrf51_timer_reset;
94
.instance_init = imx6_gpt_init,
90
dc->vmsd = &vmstate_nrf51_timer;
95
};
91
+ device_class_set_props(dc, nrf51_timer_properties);
96
97
+static const TypeInfo imx6ul_gpt_info = {
98
+ .name = TYPE_IMX6UL_GPT,
99
+ .parent = TYPE_IMX25_GPT,
100
+ .instance_init = imx6ul_gpt_init,
101
+};
102
+
103
static const TypeInfo imx7_gpt_info = {
104
.name = TYPE_IMX7_GPT,
105
.parent = TYPE_IMX25_GPT,
106
@@ -XXX,XX +XXX,XX @@ static void imx_gpt_register_types(void)
107
type_register_static(&imx25_gpt_info);
108
type_register_static(&imx31_gpt_info);
109
type_register_static(&imx6_gpt_info);
110
+ type_register_static(&imx6ul_gpt_info);
111
type_register_static(&imx7_gpt_info);
92
}
112
}
93
113
94
static const TypeInfo nrf51_timer_info = {
95
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
96
index XXXXXXX..XXXXXXX 100644
97
--- a/hw/timer/trace-events
98
+++ b/hw/timer/trace-events
99
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK
100
cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
101
102
# nrf51_timer.c
103
-nrf51_timer_read(uint64_t addr, uint32_t value, unsigned size) "read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
104
-nrf51_timer_write(uint64_t addr, uint32_t value, unsigned size) "write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
105
+nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
106
+nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
107
108
# bcm2835_systmr.c
109
bcm2835_systmr_irq(bool enable) "timer irq state %u"
110
--
114
--
111
2.20.1
115
2.25.1
112
113
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
With sve_cont_ldst_pages, the differences between first-fault and no-fault
3
IRQs were not associated to the various GPIO devices inside i.MX7D.
4
are minimal, so unify the routines. With cpu_probe_watchpoint, we are able
4
This patch brings the i.MX7D on par with i.MX6.
5
to make progress through pages with TLB_WATCHPOINT set when the watchpoint
6
does not actually fire.
7
5
6
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
7
Message-id: 20221226101418.415170-1-jcd@tribudubois.net
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-15-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
target/arm/sve_helper.c | 346 +++++++++++++++++++---------------------
11
include/hw/arm/fsl-imx7.h | 15 +++++++++++++++
14
1 file changed, 162 insertions(+), 184 deletions(-)
12
hw/arm/fsl-imx7.c | 31 ++++++++++++++++++++++++++++++-
13
2 files changed, 45 insertions(+), 1 deletion(-)
15
14
16
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
15
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sve_helper.c
17
--- a/include/hw/arm/fsl-imx7.h
19
+++ b/target/arm/sve_helper.c
18
+++ b/include/hw/arm/fsl-imx7.h
20
@@ -XXX,XX +XXX,XX @@ static intptr_t find_next_active(uint64_t *vg, intptr_t reg_off,
19
@@ -XXX,XX +XXX,XX @@ enum FslIMX7IRQs {
21
return reg_off;
20
FSL_IMX7_GPT3_IRQ = 53,
22
}
21
FSL_IMX7_GPT4_IRQ = 52,
23
22
24
-/*
23
+ FSL_IMX7_GPIO1_LOW_IRQ = 64,
25
- * Return the maximum offset <= @mem_max which is still within the page
24
+ FSL_IMX7_GPIO1_HIGH_IRQ = 65,
26
- * referenced by @base + @mem_off.
25
+ FSL_IMX7_GPIO2_LOW_IRQ = 66,
27
- */
26
+ FSL_IMX7_GPIO2_HIGH_IRQ = 67,
28
-static intptr_t max_for_page(target_ulong base, intptr_t mem_off,
27
+ FSL_IMX7_GPIO3_LOW_IRQ = 68,
29
- intptr_t mem_max)
28
+ FSL_IMX7_GPIO3_HIGH_IRQ = 69,
30
-{
29
+ FSL_IMX7_GPIO4_LOW_IRQ = 70,
31
- target_ulong addr = base + mem_off;
30
+ FSL_IMX7_GPIO4_HIGH_IRQ = 71,
32
- intptr_t split = -(intptr_t)(addr | TARGET_PAGE_MASK);
31
+ FSL_IMX7_GPIO5_LOW_IRQ = 72,
33
- return MIN(split, mem_max - mem_off) + mem_off;
32
+ FSL_IMX7_GPIO5_HIGH_IRQ = 73,
34
-}
33
+ FSL_IMX7_GPIO6_LOW_IRQ = 74,
35
-
34
+ FSL_IMX7_GPIO6_HIGH_IRQ = 75,
36
/*
35
+ FSL_IMX7_GPIO7_LOW_IRQ = 76,
37
* Resolve the guest virtual address to info->host and info->flags.
36
+ FSL_IMX7_GPIO7_HIGH_IRQ = 77,
38
* If @nofault, return false if the page is invalid, otherwise
37
+
39
@@ -XXX,XX +XXX,XX @@ static void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env,
38
FSL_IMX7_WDOG1_IRQ = 78,
40
#endif
39
FSL_IMX7_WDOG2_IRQ = 79,
41
}
40
FSL_IMX7_WDOG3_IRQ = 10,
42
41
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
43
-/*
42
index XXXXXXX..XXXXXXX 100644
44
- * The result of tlb_vaddr_to_host for user-only is just g2h(x),
43
--- a/hw/arm/fsl-imx7.c
45
- * which is always non-null. Elide the useless test.
44
+++ b/hw/arm/fsl-imx7.c
46
- */
45
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
47
-static inline bool test_host_page(void *host)
46
FSL_IMX7_GPIO7_ADDR,
48
-{
47
};
49
-#ifdef CONFIG_USER_ONLY
48
50
- return true;
49
+ static const int FSL_IMX7_GPIOn_LOW_IRQ[FSL_IMX7_NUM_GPIOS] = {
51
-#else
50
+ FSL_IMX7_GPIO1_LOW_IRQ,
52
- return likely(host != NULL);
51
+ FSL_IMX7_GPIO2_LOW_IRQ,
53
-#endif
52
+ FSL_IMX7_GPIO3_LOW_IRQ,
54
-}
53
+ FSL_IMX7_GPIO4_LOW_IRQ,
55
-
54
+ FSL_IMX7_GPIO5_LOW_IRQ,
56
/*
55
+ FSL_IMX7_GPIO6_LOW_IRQ,
57
* Common helper for all contiguous 1,2,3,4-register predicated stores.
56
+ FSL_IMX7_GPIO7_LOW_IRQ,
58
*/
57
+ };
59
@@ -XXX,XX +XXX,XX @@ static void record_fault(CPUARMState *env, uintptr_t i, uintptr_t oprsz)
58
+
60
}
59
+ static const int FSL_IMX7_GPIOn_HIGH_IRQ[FSL_IMX7_NUM_GPIOS] = {
61
60
+ FSL_IMX7_GPIO1_HIGH_IRQ,
62
/*
61
+ FSL_IMX7_GPIO2_HIGH_IRQ,
63
- * Common helper for all contiguous first-fault loads.
62
+ FSL_IMX7_GPIO3_HIGH_IRQ,
64
+ * Common helper for all contiguous no-fault and first-fault loads.
63
+ FSL_IMX7_GPIO4_HIGH_IRQ,
65
*/
64
+ FSL_IMX7_GPIO5_HIGH_IRQ,
66
-static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
65
+ FSL_IMX7_GPIO6_HIGH_IRQ,
67
- uint32_t desc, const uintptr_t retaddr,
66
+ FSL_IMX7_GPIO7_HIGH_IRQ,
68
- const int esz, const int msz,
67
+ };
69
- sve_ldst1_host_fn *host_fn,
68
+
70
- sve_ldst1_tlb_fn *tlb_fn)
69
sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
71
+static inline QEMU_ALWAYS_INLINE
70
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, FSL_IMX7_GPIOn_ADDR[i]);
72
+void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
71
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
73
+ uint32_t desc, const uintptr_t retaddr,
72
+ FSL_IMX7_GPIOn_ADDR[i]);
74
+ const int esz, const int msz, const SVEContFault fault,
73
+
75
+ sve_ldst1_host_fn *host_fn,
74
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
76
+ sve_ldst1_tlb_fn *tlb_fn)
75
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
77
{
76
+ FSL_IMX7_GPIOn_LOW_IRQ[i]));
78
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
77
+
79
- const int mmu_idx = get_mmuidx(oi);
78
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
80
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
79
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
81
void *vd = &env->vfp.zregs[rd];
80
+ FSL_IMX7_GPIOn_HIGH_IRQ[i]));
82
- const int diffsz = esz - msz;
83
const intptr_t reg_max = simd_oprsz(desc);
84
- const intptr_t mem_max = reg_max >> diffsz;
85
- intptr_t split, reg_off, mem_off, i;
86
+ intptr_t reg_off, mem_off, reg_last;
87
+ SVEContLdSt info;
88
+ int flags;
89
void *host;
90
91
- /* Skip to the first active element. */
92
- reg_off = find_next_active(vg, 0, reg_max, esz);
93
- if (unlikely(reg_off == reg_max)) {
94
+ /* Find the active elements. */
95
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, 1 << msz)) {
96
/* The entire predicate was false; no load occurs. */
97
memset(vd, 0, reg_max);
98
return;
99
}
81
}
100
- mem_off = reg_off >> diffsz;
101
+ reg_off = info.reg_off_first[0];
102
103
- /*
104
- * If the (remaining) load is entirely within a single page, then:
105
- * For softmmu, and the tlb hits, then no faults will occur;
106
- * For user-only, either the first load will fault or none will.
107
- * We can thus perform the load directly to the destination and
108
- * Vd will be unmodified on any exception path.
109
- */
110
- split = max_for_page(addr, mem_off, mem_max);
111
- if (likely(split == mem_max)) {
112
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
113
- if (test_host_page(host)) {
114
- i = reg_off;
115
- host -= mem_off;
116
- do {
117
- host_fn(vd, i, host + (i >> diffsz));
118
- i = find_next_active(vg, i + (1 << esz), reg_max, esz);
119
- } while (i < reg_max);
120
- /* After any fault, zero any leading inactive elements. */
121
+ /* Probe the page(s). */
122
+ if (!sve_cont_ldst_pages(&info, fault, env, addr, MMU_DATA_LOAD, retaddr)) {
123
+ /* Fault on first element. */
124
+ tcg_debug_assert(fault == FAULT_NO);
125
+ memset(vd, 0, reg_max);
126
+ goto do_fault;
127
+ }
128
+
129
+ mem_off = info.mem_off_first[0];
130
+ flags = info.page[0].flags;
131
+
132
+ if (fault == FAULT_FIRST) {
133
+ /*
134
+ * Special handling of the first active element,
135
+ * if it crosses a page boundary or is MMIO.
136
+ */
137
+ bool is_split = mem_off == info.mem_off_split;
138
+ /* TODO: MTE check. */
139
+ if (unlikely(flags != 0) || unlikely(is_split)) {
140
+ /*
141
+ * Use the slow path for cross-page handling.
142
+ * Might trap for MMIO or watchpoints.
143
+ */
144
+ tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
145
+
146
+ /* After any fault, zero the other elements. */
147
swap_memzero(vd, reg_off);
148
- return;
149
+ reg_off += 1 << esz;
150
+ mem_off += 1 << msz;
151
+ swap_memzero(vd + reg_off, reg_max - reg_off);
152
+
153
+ if (is_split) {
154
+ goto second_page;
155
+ }
156
+ } else {
157
+ memset(vd, 0, reg_max);
158
+ }
159
+ } else {
160
+ memset(vd, 0, reg_max);
161
+ if (unlikely(mem_off == info.mem_off_split)) {
162
+ /* The first active element crosses a page boundary. */
163
+ flags |= info.page[1].flags;
164
+ if (unlikely(flags & TLB_MMIO)) {
165
+ /* Some page is MMIO, see below. */
166
+ goto do_fault;
167
+ }
168
+ if (unlikely(flags & TLB_WATCHPOINT) &&
169
+ (cpu_watchpoint_address_matches
170
+ (env_cpu(env), addr + mem_off, 1 << msz)
171
+ & BP_MEM_READ)) {
172
+ /* Watchpoint hit, see below. */
173
+ goto do_fault;
174
+ }
175
+ /* TODO: MTE check. */
176
+ /*
177
+ * Use the slow path for cross-page handling.
178
+ * This is RAM, without a watchpoint, and will not trap.
179
+ */
180
+ tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
181
+ goto second_page;
182
}
183
}
184
82
185
/*
83
/*
186
- * Perform one normal read, which will fault or not.
187
- * But it is likely to bring the page into the tlb.
188
+ * From this point on, all memory operations are MemSingleNF.
189
+ *
190
+ * Per the MemSingleNF pseudocode, a no-fault load from Device memory
191
+ * must not actually hit the bus -- it returns (UNKNOWN, FAULT) instead.
192
+ *
193
+ * Unfortuately we do not have access to the memory attributes from the
194
+ * PTE to tell Device memory from Normal memory. So we make a mostly
195
+ * correct check, and indicate (UNKNOWN, FAULT) for any MMIO.
196
+ * This gives the right answer for the common cases of "Normal memory,
197
+ * backed by host RAM" and "Device memory, backed by MMIO".
198
+ * The architecture allows us to suppress an NF load and return
199
+ * (UNKNOWN, FAULT) for any reason, so our behaviour for the corner
200
+ * case of "Normal memory, backed by MMIO" is permitted. The case we
201
+ * get wrong is "Device memory, backed by host RAM", for which we
202
+ * should return (UNKNOWN, FAULT) for but do not.
203
+ *
204
+ * Similarly, CPU_BP breakpoints would raise exceptions, and so
205
+ * return (UNKNOWN, FAULT). For simplicity, we consider gdb and
206
+ * architectural breakpoints the same.
207
*/
208
- tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
209
+ if (unlikely(flags & TLB_MMIO)) {
210
+ goto do_fault;
211
+ }
212
213
- /* After any fault, zero any leading predicated false elts. */
214
- swap_memzero(vd, reg_off);
215
- mem_off += 1 << msz;
216
- reg_off += 1 << esz;
217
+ reg_last = info.reg_off_last[0];
218
+ host = info.page[0].host;
219
220
- /* Try again to read the balance of the page. */
221
- split = max_for_page(addr, mem_off - 1, mem_max);
222
- if (split >= (1 << msz)) {
223
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
224
- if (host) {
225
- host -= mem_off;
226
- do {
227
+ do {
228
+ uint64_t pg = *(uint64_t *)(vg + (reg_off >> 3));
229
+ do {
230
+ if ((pg >> (reg_off & 63)) & 1) {
231
+ if (unlikely(flags & TLB_WATCHPOINT) &&
232
+ (cpu_watchpoint_address_matches
233
+ (env_cpu(env), addr + mem_off, 1 << msz)
234
+ & BP_MEM_READ)) {
235
+ goto do_fault;
236
+ }
237
+ /* TODO: MTE check. */
238
host_fn(vd, reg_off, host + mem_off);
239
- reg_off += 1 << esz;
240
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
241
- mem_off = reg_off >> diffsz;
242
- } while (split - mem_off >= (1 << msz));
243
- }
244
- }
245
-
246
- record_fault(env, reg_off, reg_max);
247
-}
248
-
249
-/*
250
- * Common helper for all contiguous no-fault loads.
251
- */
252
-static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
253
- uint32_t desc, const int esz, const int msz,
254
- sve_ldst1_host_fn *host_fn)
255
-{
256
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
257
- void *vd = &env->vfp.zregs[rd];
258
- const int diffsz = esz - msz;
259
- const intptr_t reg_max = simd_oprsz(desc);
260
- const intptr_t mem_max = reg_max >> diffsz;
261
- const int mmu_idx = cpu_mmu_index(env, false);
262
- intptr_t split, reg_off, mem_off;
263
- void *host;
264
-
265
-#ifdef CONFIG_USER_ONLY
266
- host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_idx);
267
- if (likely(page_check_range(addr, mem_max, PAGE_READ) == 0)) {
268
- /* The entire operation is valid and will not fault. */
269
- reg_off = 0;
270
- do {
271
- mem_off = reg_off >> diffsz;
272
- host_fn(vd, reg_off, host + mem_off);
273
+ }
274
reg_off += 1 << esz;
275
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
276
- } while (reg_off < reg_max);
277
- return;
278
- }
279
-#endif
280
+ mem_off += 1 << msz;
281
+ } while (reg_off <= reg_last && (reg_off & 63));
282
+ } while (reg_off <= reg_last);
283
284
- /* There will be no fault, so we may modify in advance. */
285
- memset(vd, 0, reg_max);
286
-
287
- /* Skip to the first active element. */
288
- reg_off = find_next_active(vg, 0, reg_max, esz);
289
- if (unlikely(reg_off == reg_max)) {
290
- /* The entire predicate was false; no load occurs. */
291
- return;
292
- }
293
- mem_off = reg_off >> diffsz;
294
-
295
-#ifdef CONFIG_USER_ONLY
296
- if (page_check_range(addr + mem_off, 1 << msz, PAGE_READ) == 0) {
297
- /* At least one load is valid; take the rest of the page. */
298
- split = max_for_page(addr, mem_off + (1 << msz) - 1, mem_max);
299
- do {
300
- host_fn(vd, reg_off, host + mem_off);
301
- reg_off += 1 << esz;
302
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
303
- mem_off = reg_off >> diffsz;
304
- } while (split - mem_off >= (1 << msz));
305
- }
306
-#else
307
/*
308
- * If the address is not in the TLB, we have no way to bring the
309
- * entry into the TLB without also risking a fault. Note that
310
- * the corollary is that we never load from an address not in RAM.
311
- *
312
- * This last is out of spec, in a weird corner case.
313
- * Per the MemNF/MemSingleNF pseudocode, a NF load from Device memory
314
- * must not actually hit the bus -- it returns UNKNOWN data instead.
315
- * But if you map non-RAM with Normal memory attributes and do a NF
316
- * load then it should access the bus. (Nobody ought actually do this
317
- * in the real world, obviously.)
318
- *
319
- * Then there are the annoying special cases with watchpoints...
320
- * TODO: Add a form of non-faulting loads using cc->tlb_fill(probe=true).
321
+ * MemSingleNF is allowed to fail for any reason. We have special
322
+ * code above to handle the first element crossing a page boundary.
323
+ * As an implementation choice, decline to handle a cross-page element
324
+ * in any other position.
325
*/
326
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
327
- split = max_for_page(addr, mem_off, mem_max);
328
- if (host && split >= (1 << msz)) {
329
- host -= mem_off;
330
- do {
331
- host_fn(vd, reg_off, host + mem_off);
332
- reg_off += 1 << esz;
333
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
334
- mem_off = reg_off >> diffsz;
335
- } while (split - mem_off >= (1 << msz));
336
+ reg_off = info.reg_off_split;
337
+ if (reg_off >= 0) {
338
+ goto do_fault;
339
}
340
-#endif
341
342
+ second_page:
343
+ reg_off = info.reg_off_first[1];
344
+ if (likely(reg_off < 0)) {
345
+ /* No active elements on the second page. All done. */
346
+ return;
347
+ }
348
+
349
+ /*
350
+ * MemSingleNF is allowed to fail for any reason. As an implementation
351
+ * choice, decline to handle elements on the second page. This should
352
+ * be low frequency as the guest walks through memory -- the next
353
+ * iteration of the guest's loop should be aligned on the page boundary,
354
+ * and then all following iterations will stay aligned.
355
+ */
356
+
357
+ do_fault:
358
record_fault(env, reg_off, reg_max);
359
}
360
361
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
362
void HELPER(sve_ldff1##PART##_r)(CPUARMState *env, void *vg, \
363
target_ulong addr, uint32_t desc) \
364
{ \
365
- sve_ldff1_r(env, vg, addr, desc, GETPC(), ESZ, 0, \
366
- sve_ld1##PART##_host, sve_ld1##PART##_tlb); \
367
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, FAULT_FIRST, \
368
+ sve_ld1##PART##_host, sve_ld1##PART##_tlb); \
369
} \
370
void HELPER(sve_ldnf1##PART##_r)(CPUARMState *env, void *vg, \
371
target_ulong addr, uint32_t desc) \
372
{ \
373
- sve_ldnf1_r(env, vg, addr, desc, ESZ, 0, sve_ld1##PART##_host); \
374
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, FAULT_NO, \
375
+ sve_ld1##PART##_host, sve_ld1##PART##_tlb); \
376
}
377
378
#define DO_LDFF1_LDNF1_2(PART, ESZ, MSZ) \
379
void HELPER(sve_ldff1##PART##_le_r)(CPUARMState *env, void *vg, \
380
target_ulong addr, uint32_t desc) \
381
{ \
382
- sve_ldff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
383
- sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \
384
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_FIRST, \
385
+ sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \
386
} \
387
void HELPER(sve_ldnf1##PART##_le_r)(CPUARMState *env, void *vg, \
388
target_ulong addr, uint32_t desc) \
389
{ \
390
- sve_ldnf1_r(env, vg, addr, desc, ESZ, MSZ, sve_ld1##PART##_le_host); \
391
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_NO, \
392
+ sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \
393
} \
394
void HELPER(sve_ldff1##PART##_be_r)(CPUARMState *env, void *vg, \
395
target_ulong addr, uint32_t desc) \
396
{ \
397
- sve_ldff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
398
- sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \
399
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_FIRST, \
400
+ sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \
401
} \
402
void HELPER(sve_ldnf1##PART##_be_r)(CPUARMState *env, void *vg, \
403
target_ulong addr, uint32_t desc) \
404
{ \
405
- sve_ldnf1_r(env, vg, addr, desc, ESZ, MSZ, sve_ld1##PART##_be_host); \
406
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_NO, \
407
+ sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \
408
}
409
410
-DO_LDFF1_LDNF1_1(bb, 0)
411
-DO_LDFF1_LDNF1_1(bhu, 1)
412
-DO_LDFF1_LDNF1_1(bhs, 1)
413
-DO_LDFF1_LDNF1_1(bsu, 2)
414
-DO_LDFF1_LDNF1_1(bss, 2)
415
-DO_LDFF1_LDNF1_1(bdu, 3)
416
-DO_LDFF1_LDNF1_1(bds, 3)
417
+DO_LDFF1_LDNF1_1(bb, MO_8)
418
+DO_LDFF1_LDNF1_1(bhu, MO_16)
419
+DO_LDFF1_LDNF1_1(bhs, MO_16)
420
+DO_LDFF1_LDNF1_1(bsu, MO_32)
421
+DO_LDFF1_LDNF1_1(bss, MO_32)
422
+DO_LDFF1_LDNF1_1(bdu, MO_64)
423
+DO_LDFF1_LDNF1_1(bds, MO_64)
424
425
-DO_LDFF1_LDNF1_2(hh, 1, 1)
426
-DO_LDFF1_LDNF1_2(hsu, 2, 1)
427
-DO_LDFF1_LDNF1_2(hss, 2, 1)
428
-DO_LDFF1_LDNF1_2(hdu, 3, 1)
429
-DO_LDFF1_LDNF1_2(hds, 3, 1)
430
+DO_LDFF1_LDNF1_2(hh, MO_16, MO_16)
431
+DO_LDFF1_LDNF1_2(hsu, MO_32, MO_16)
432
+DO_LDFF1_LDNF1_2(hss, MO_32, MO_16)
433
+DO_LDFF1_LDNF1_2(hdu, MO_64, MO_16)
434
+DO_LDFF1_LDNF1_2(hds, MO_64, MO_16)
435
436
-DO_LDFF1_LDNF1_2(ss, 2, 2)
437
-DO_LDFF1_LDNF1_2(sdu, 3, 2)
438
-DO_LDFF1_LDNF1_2(sds, 3, 2)
439
+DO_LDFF1_LDNF1_2(ss, MO_32, MO_32)
440
+DO_LDFF1_LDNF1_2(sdu, MO_64, MO_32)
441
+DO_LDFF1_LDNF1_2(sds, MO_64, MO_32)
442
443
-DO_LDFF1_LDNF1_2(dd, 3, 3)
444
+DO_LDFF1_LDNF1_2(dd, MO_64, MO_64)
445
446
#undef DO_LDFF1_LDNF1_1
447
#undef DO_LDFF1_LDNF1_2
448
--
84
--
449
2.20.1
85
2.25.1
450
451
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Stephen Longfield <slongfield@google.com>
2
2
3
Size is used at lines 1088/1188 for the loop, which reads the last 4
4
bytes from the crc_ptr so it does need to get increased, however it
5
shouldn't be increased before the buffer is passed to CRC computation,
6
or the crc32 function will access uninitialized memory.
7
8
This was pointed out to me by clg@kaod.org during the code review of
9
a similar patch to hw/net/ftgmac100.c
10
11
Change-Id: Ib0464303b191af1e28abeb2f5105eb25aadb5e9b
12
Signed-off-by: Stephen Longfield <slongfield@google.com>
13
Reviewed-by: Patrick Venture <venture@google.com>
14
Message-id: 20221221183202.3788132-1-slongfield@google.com
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200508154359.7494-14-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
17
---
8
target/arm/sve_helper.c | 223 ++++++++++++++--------------------------
18
hw/net/imx_fec.c | 8 ++++----
9
1 file changed, 79 insertions(+), 144 deletions(-)
19
1 file changed, 4 insertions(+), 4 deletions(-)
10
20
11
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
21
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
12
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/sve_helper.c
23
--- a/hw/net/imx_fec.c
14
+++ b/target/arm/sve_helper.c
24
+++ b/hw/net/imx_fec.c
15
@@ -XXX,XX +XXX,XX @@ static inline bool test_host_page(void *host)
25
@@ -XXX,XX +XXX,XX @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf,
16
}
26
return 0;
17
18
/*
19
- * Common helper for all contiguous one-register predicated loads.
20
+ * Common helper for all contiguous 1,2,3,4-register predicated stores.
21
*/
22
static inline QEMU_ALWAYS_INLINE
23
-void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
24
+void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
25
uint32_t desc, const uintptr_t retaddr,
26
- const int esz, const int msz,
27
+ const int esz, const int msz, const int N,
28
sve_ldst1_host_fn *host_fn,
29
sve_ldst1_tlb_fn *tlb_fn)
30
{
31
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
32
- void *vd = &env->vfp.zregs[rd];
33
const intptr_t reg_max = simd_oprsz(desc);
34
intptr_t reg_off, reg_last, mem_off;
35
SVEContLdSt info;
36
void *host;
37
- int flags;
38
+ int flags, i;
39
40
/* Find the active elements. */
41
- if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, 1 << msz)) {
42
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, N << msz)) {
43
/* The entire predicate was false; no load occurs. */
44
- memset(vd, 0, reg_max);
45
+ for (i = 0; i < N; ++i) {
46
+ memset(&env->vfp.zregs[(rd + i) & 31], 0, reg_max);
47
+ }
48
return;
49
}
27
}
50
28
51
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
29
- /* 4 bytes for the CRC. */
52
sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, retaddr);
30
- size += 4;
53
31
crc = cpu_to_be32(crc32(~0, buf, size));
54
/* Handle watchpoints for all active elements. */
32
+ /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr. */
55
- sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, 1 << msz,
33
+ size += 4;
56
+ sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, N << msz,
34
crc_ptr = (uint8_t *) &crc;
57
BP_MEM_READ, retaddr);
35
58
36
/* Huge frames are truncated. */
59
/* TODO: MTE check. */
37
@@ -XXX,XX +XXX,XX @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
60
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
38
return 0;
61
* which for ARM will raise SyncExternal. Perform the load
62
* into scratch memory to preserve register state until the end.
63
*/
64
- ARMVectorReg scratch;
65
+ ARMVectorReg scratch[4] = { };
66
67
- memset(&scratch, 0, reg_max);
68
mem_off = info.mem_off_first[0];
69
reg_off = info.reg_off_first[0];
70
reg_last = info.reg_off_last[1];
71
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
72
uint64_t pg = vg[reg_off >> 6];
73
do {
74
if ((pg >> (reg_off & 63)) & 1) {
75
- tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
76
+ for (i = 0; i < N; ++i) {
77
+ tlb_fn(env, &scratch[i], reg_off,
78
+ addr + mem_off + (i << msz), retaddr);
79
+ }
80
}
81
reg_off += 1 << esz;
82
- mem_off += 1 << msz;
83
+ mem_off += N << msz;
84
} while (reg_off & 63);
85
} while (reg_off <= reg_last);
86
87
- memcpy(vd, &scratch, reg_max);
88
+ for (i = 0; i < N; ++i) {
89
+ memcpy(&env->vfp.zregs[(rd + i) & 31], &scratch[i], reg_max);
90
+ }
91
return;
92
#endif
93
}
39
}
94
40
95
/* The entire operation is in RAM, on valid pages. */
41
- /* 4 bytes for the CRC. */
96
42
- size += 4;
97
- memset(vd, 0, reg_max);
43
crc = cpu_to_be32(crc32(~0, buf, size));
98
+ for (i = 0; i < N; ++i) {
44
+ /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr. */
99
+ memset(&env->vfp.zregs[(rd + i) & 31], 0, reg_max);
45
+ size += 4;
100
+ }
46
crc_ptr = (uint8_t *) &crc;
101
+
47
102
mem_off = info.mem_off_first[0];
48
if (shift16) {
103
reg_off = info.reg_off_first[0];
104
reg_last = info.reg_off_last[0];
105
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
106
uint64_t pg = vg[reg_off >> 6];
107
do {
108
if ((pg >> (reg_off & 63)) & 1) {
109
- host_fn(vd, reg_off, host + mem_off);
110
+ for (i = 0; i < N; ++i) {
111
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
112
+ host + mem_off + (i << msz));
113
+ }
114
}
115
reg_off += 1 << esz;
116
- mem_off += 1 << msz;
117
+ mem_off += N << msz;
118
} while (reg_off <= reg_last && (reg_off & 63));
119
}
120
121
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
122
*/
123
mem_off = info.mem_off_split;
124
if (unlikely(mem_off >= 0)) {
125
- tlb_fn(env, vd, info.reg_off_split, addr + mem_off, retaddr);
126
+ reg_off = info.reg_off_split;
127
+ for (i = 0; i < N; ++i) {
128
+ tlb_fn(env, &env->vfp.zregs[(rd + i) & 31], reg_off,
129
+ addr + mem_off + (i << msz), retaddr);
130
+ }
131
}
132
133
mem_off = info.mem_off_first[1];
134
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
135
uint64_t pg = vg[reg_off >> 6];
136
do {
137
if ((pg >> (reg_off & 63)) & 1) {
138
- host_fn(vd, reg_off, host + mem_off);
139
+ for (i = 0; i < N; ++i) {
140
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
141
+ host + mem_off + (i << msz));
142
+ }
143
}
144
reg_off += 1 << esz;
145
- mem_off += 1 << msz;
146
+ mem_off += N << msz;
147
} while (reg_off & 63);
148
} while (reg_off <= reg_last);
149
}
150
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
151
void HELPER(sve_##NAME##_r)(CPUARMState *env, void *vg, \
152
target_ulong addr, uint32_t desc) \
153
{ \
154
- sve_ld1_r(env, vg, addr, desc, GETPC(), ESZ, 0, \
155
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, 1, \
156
sve_##NAME##_host, sve_##NAME##_tlb); \
157
}
158
159
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_##NAME##_r)(CPUARMState *env, void *vg, \
160
void HELPER(sve_##NAME##_le_r)(CPUARMState *env, void *vg, \
161
target_ulong addr, uint32_t desc) \
162
{ \
163
- sve_ld1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
164
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \
165
sve_##NAME##_le_host, sve_##NAME##_le_tlb); \
166
} \
167
void HELPER(sve_##NAME##_be_r)(CPUARMState *env, void *vg, \
168
target_ulong addr, uint32_t desc) \
169
{ \
170
- sve_ld1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
171
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \
172
sve_##NAME##_be_host, sve_##NAME##_be_tlb); \
173
}
174
175
-DO_LD1_1(ld1bb, 0)
176
-DO_LD1_1(ld1bhu, 1)
177
-DO_LD1_1(ld1bhs, 1)
178
-DO_LD1_1(ld1bsu, 2)
179
-DO_LD1_1(ld1bss, 2)
180
-DO_LD1_1(ld1bdu, 3)
181
-DO_LD1_1(ld1bds, 3)
182
+DO_LD1_1(ld1bb, MO_8)
183
+DO_LD1_1(ld1bhu, MO_16)
184
+DO_LD1_1(ld1bhs, MO_16)
185
+DO_LD1_1(ld1bsu, MO_32)
186
+DO_LD1_1(ld1bss, MO_32)
187
+DO_LD1_1(ld1bdu, MO_64)
188
+DO_LD1_1(ld1bds, MO_64)
189
190
-DO_LD1_2(ld1hh, 1, 1)
191
-DO_LD1_2(ld1hsu, 2, 1)
192
-DO_LD1_2(ld1hss, 2, 1)
193
-DO_LD1_2(ld1hdu, 3, 1)
194
-DO_LD1_2(ld1hds, 3, 1)
195
+DO_LD1_2(ld1hh, MO_16, MO_16)
196
+DO_LD1_2(ld1hsu, MO_32, MO_16)
197
+DO_LD1_2(ld1hss, MO_32, MO_16)
198
+DO_LD1_2(ld1hdu, MO_64, MO_16)
199
+DO_LD1_2(ld1hds, MO_64, MO_16)
200
201
-DO_LD1_2(ld1ss, 2, 2)
202
-DO_LD1_2(ld1sdu, 3, 2)
203
-DO_LD1_2(ld1sds, 3, 2)
204
+DO_LD1_2(ld1ss, MO_32, MO_32)
205
+DO_LD1_2(ld1sdu, MO_64, MO_32)
206
+DO_LD1_2(ld1sds, MO_64, MO_32)
207
208
-DO_LD1_2(ld1dd, 3, 3)
209
+DO_LD1_2(ld1dd, MO_64, MO_64)
210
211
#undef DO_LD1_1
212
#undef DO_LD1_2
213
214
-/*
215
- * Common helpers for all contiguous 2,3,4-register predicated loads.
216
- */
217
-static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
218
- uint32_t desc, int size, uintptr_t ra,
219
- sve_ldst1_tlb_fn *tlb_fn)
220
-{
221
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
222
- intptr_t i, oprsz = simd_oprsz(desc);
223
- ARMVectorReg scratch[2] = { };
224
-
225
- for (i = 0; i < oprsz; ) {
226
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
227
- do {
228
- if (pg & 1) {
229
- tlb_fn(env, &scratch[0], i, addr, ra);
230
- tlb_fn(env, &scratch[1], i, addr + size, ra);
231
- }
232
- i += size, pg >>= size;
233
- addr += 2 * size;
234
- } while (i & 15);
235
- }
236
-
237
- /* Wait until all exceptions have been raised to write back. */
238
- memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
239
- memcpy(&env->vfp.zregs[(rd + 1) & 31], &scratch[1], oprsz);
240
-}
241
-
242
-static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
243
- uint32_t desc, int size, uintptr_t ra,
244
- sve_ldst1_tlb_fn *tlb_fn)
245
-{
246
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
247
- intptr_t i, oprsz = simd_oprsz(desc);
248
- ARMVectorReg scratch[3] = { };
249
-
250
- for (i = 0; i < oprsz; ) {
251
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
252
- do {
253
- if (pg & 1) {
254
- tlb_fn(env, &scratch[0], i, addr, ra);
255
- tlb_fn(env, &scratch[1], i, addr + size, ra);
256
- tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
257
- }
258
- i += size, pg >>= size;
259
- addr += 3 * size;
260
- } while (i & 15);
261
- }
262
-
263
- /* Wait until all exceptions have been raised to write back. */
264
- memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
265
- memcpy(&env->vfp.zregs[(rd + 1) & 31], &scratch[1], oprsz);
266
- memcpy(&env->vfp.zregs[(rd + 2) & 31], &scratch[2], oprsz);
267
-}
268
-
269
-static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
270
- uint32_t desc, int size, uintptr_t ra,
271
- sve_ldst1_tlb_fn *tlb_fn)
272
-{
273
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
274
- intptr_t i, oprsz = simd_oprsz(desc);
275
- ARMVectorReg scratch[4] = { };
276
-
277
- for (i = 0; i < oprsz; ) {
278
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
279
- do {
280
- if (pg & 1) {
281
- tlb_fn(env, &scratch[0], i, addr, ra);
282
- tlb_fn(env, &scratch[1], i, addr + size, ra);
283
- tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
284
- tlb_fn(env, &scratch[3], i, addr + 3 * size, ra);
285
- }
286
- i += size, pg >>= size;
287
- addr += 4 * size;
288
- } while (i & 15);
289
- }
290
-
291
- /* Wait until all exceptions have been raised to write back. */
292
- memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
293
- memcpy(&env->vfp.zregs[(rd + 1) & 31], &scratch[1], oprsz);
294
- memcpy(&env->vfp.zregs[(rd + 2) & 31], &scratch[2], oprsz);
295
- memcpy(&env->vfp.zregs[(rd + 3) & 31], &scratch[3], oprsz);
296
-}
297
-
298
#define DO_LDN_1(N) \
299
-void QEMU_FLATTEN HELPER(sve_ld##N##bb_r) \
300
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
301
-{ \
302
- sve_ld##N##_r(env, vg, addr, desc, 1, GETPC(), sve_ld1bb_tlb); \
303
+void HELPER(sve_ld##N##bb_r)(CPUARMState *env, void *vg, \
304
+ target_ulong addr, uint32_t desc) \
305
+{ \
306
+ sve_ldN_r(env, vg, addr, desc, GETPC(), MO_8, MO_8, N, \
307
+ sve_ld1bb_host, sve_ld1bb_tlb); \
308
}
309
310
-#define DO_LDN_2(N, SUFF, SIZE) \
311
-void QEMU_FLATTEN HELPER(sve_ld##N##SUFF##_le_r) \
312
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
313
+#define DO_LDN_2(N, SUFF, ESZ) \
314
+void HELPER(sve_ld##N##SUFF##_le_r)(CPUARMState *env, void *vg, \
315
+ target_ulong addr, uint32_t desc) \
316
{ \
317
- sve_ld##N##_r(env, vg, addr, desc, SIZE, GETPC(), \
318
- sve_ld1##SUFF##_le_tlb); \
319
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \
320
+ sve_ld1##SUFF##_le_host, sve_ld1##SUFF##_le_tlb); \
321
} \
322
-void QEMU_FLATTEN HELPER(sve_ld##N##SUFF##_be_r) \
323
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
324
+void HELPER(sve_ld##N##SUFF##_be_r)(CPUARMState *env, void *vg, \
325
+ target_ulong addr, uint32_t desc) \
326
{ \
327
- sve_ld##N##_r(env, vg, addr, desc, SIZE, GETPC(), \
328
- sve_ld1##SUFF##_be_tlb); \
329
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \
330
+ sve_ld1##SUFF##_be_host, sve_ld1##SUFF##_be_tlb); \
331
}
332
333
DO_LDN_1(2)
334
DO_LDN_1(3)
335
DO_LDN_1(4)
336
337
-DO_LDN_2(2, hh, 2)
338
-DO_LDN_2(3, hh, 2)
339
-DO_LDN_2(4, hh, 2)
340
+DO_LDN_2(2, hh, MO_16)
341
+DO_LDN_2(3, hh, MO_16)
342
+DO_LDN_2(4, hh, MO_16)
343
344
-DO_LDN_2(2, ss, 4)
345
-DO_LDN_2(3, ss, 4)
346
-DO_LDN_2(4, ss, 4)
347
+DO_LDN_2(2, ss, MO_32)
348
+DO_LDN_2(3, ss, MO_32)
349
+DO_LDN_2(4, ss, MO_32)
350
351
-DO_LDN_2(2, dd, 8)
352
-DO_LDN_2(3, dd, 8)
353
-DO_LDN_2(4, dd, 8)
354
+DO_LDN_2(2, dd, MO_64)
355
+DO_LDN_2(3, dd, MO_64)
356
+DO_LDN_2(4, dd, MO_64)
357
358
#undef DO_LDN_1
359
#undef DO_LDN_2
360
--
49
--
361
2.20.1
50
2.25.1
362
363
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