[PULL 00/34] target-arm queue
[PULL 00/24] target-arm queue
1
The following changes since commit c88f1ffc19e38008a1c33ae039482a860aa7418c:
1
The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:
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2
3
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2020-05-08 14:29:18 +0100)
3
Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200511
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702
8
8
9
for you to fetch changes up to 7e17d50ebd359ee5fa3d65d7fdc0fe0336d60694:
9
for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
10
10
11
target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed) (2020-05-11 14:22:54 +0100)
11
target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
target-arm queue:
14
target-arm queue:
15
aspeed: Add boot stub for smp booting
15
* more MVE instructions
16
target/arm: Drop access_el3_aa32ns_aa64any()
16
* hw/gpio/gpio_pwr: use shutdown function for reboot
17
aspeed: Support AST2600A1 silicon revision
17
* target/arm: Check NaN mode before silencing NaN
18
aspeed: sdmc: Implement AST2600 locking behaviour
18
* tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
19
nrf51: Tracing cleanups
19
* hw/arm: Add basic power management to raspi.
20
target/arm: Improve handling of SVE loads and stores
20
* docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
21
target/arm: Don't show TCG-only CPUs in KVM-only QEMU builds
22
hw/arm/musicpal: Map the UART devices unconditionally
23
target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)
24
target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
25
21
26
----------------------------------------------------------------
22
----------------------------------------------------------------
27
Edgar E. Iglesias (1):
23
Joe Komlodi (1):
28
target/arm: Drop access_el3_aa32ns_aa64any()
24
target/arm: Check NaN mode before silencing NaN
29
25
30
Joel Stanley (3):
26
Maxim Uvarov (1):
31
aspeed: Add boot stub for smp booting
27
hw/gpio/gpio_pwr: use shutdown function for reboot
32
aspeed: Support AST2600A1 silicon revision
33
aspeed: sdmc: Implement AST2600 locking behaviour
34
28
35
Philippe Mathieu-Daudé (8):
29
Nolan Leake (1):
36
hw/arm/nrf51: Add NRF51_PERIPHERAL_SIZE definition
30
hw/arm: Add basic power management to raspi.
37
hw/timer/nrf51_timer: Display timer ID in trace events
38
hw/timer/nrf51_timer: Add trace event of counter value update
39
target/arm/kvm: Inline set_feature() calls
40
target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]
41
target/arm/cpu: Restrict v8M IDAU interface to Aarch32 CPUs
42
target/arm: Restrict TCG cpus to TCG accel
43
hw/arm/musicpal: Map the UART devices unconditionally
44
31
45
Richard Henderson (21):
32
Patrick Venture (2):
46
exec: Add block comments for watchpoint routines
33
docs/system/arm: Add quanta-q7l1-bmc reference
47
exec: Fix cpu_watchpoint_address_matches address length
34
docs/system/arm: Add quanta-gbs-bmc reference
48
accel/tcg: Add block comment for probe_access
49
accel/tcg: Adjust probe_access call to page_check_range
50
accel/tcg: Add probe_access_flags
51
accel/tcg: Add endian-specific cpu_{ld, st}* operations
52
target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn
53
target/arm: Drop manual handling of set/clear_helper_retaddr
54
target/arm: Add sve infrastructure for page lookup
55
target/arm: Adjust interface of sve_ld1_host_fn
56
target/arm: Use SVEContLdSt in sve_ld1_r
57
target/arm: Handle watchpoints in sve_ld1_r
58
target/arm: Use SVEContLdSt for multi-register contiguous loads
59
target/arm: Update contiguous first-fault and no-fault loads
60
target/arm: Use SVEContLdSt for contiguous stores
61
target/arm: Reuse sve_probe_page for gather first-fault loads
62
target/arm: Reuse sve_probe_page for scatter stores
63
target/arm: Reuse sve_probe_page for gather loads
64
target/arm: Remove sve_memopidx
65
target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
66
target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)
67
35
68
Thomas Huth (1):
36
Peter Maydell (18):
69
target/arm: Make set_feature() available for other files
37
target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
38
target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
39
target/arm: Make asimd_imm_const() public
40
target/arm: Use asimd_imm_const for A64 decode
41
target/arm: Use dup_const() instead of bitfield_replicate()
42
target/arm: Implement MVE logical immediate insns
43
target/arm: Implement MVE vector shift left by immediate insns
44
target/arm: Implement MVE vector shift right by immediate insns
45
target/arm: Implement MVE VSHLL
46
target/arm: Implement MVE VSRI, VSLI
47
target/arm: Implement MVE VSHRN, VRSHRN
48
target/arm: Implement MVE saturating narrowing shifts
49
target/arm: Implement MVE VSHLC
50
target/arm: Implement MVE VADDLV
51
target/arm: Implement MVE long shifts by immediate
52
target/arm: Implement MVE long shifts by register
53
target/arm: Implement MVE shifts by immediate
54
target/arm: Implement MVE shifts by register
70
55
71
docs/devel/loads-stores.rst | 39 +-
56
Philippe Mathieu-Daudé (1):
72
include/exec/cpu-all.h | 13 +-
57
tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
73
include/exec/cpu_ldst.h | 283 +++--
74
include/exec/exec-all.h | 39 +
75
include/hw/arm/nrf51.h | 3 +-
76
include/hw/core/cpu.h | 23 +
77
include/hw/i2c/microbit_i2c.h | 2 +-
78
include/hw/misc/aspeed_scu.h | 1 +
79
include/hw/timer/nrf51_timer.h | 1 +
80
target/arm/cpu.h | 10 +
81
target/arm/helper-sve.h | 45 +-
82
target/arm/internals.h | 5 -
83
accel/tcg/cputlb.c | 413 ++++---
84
accel/tcg/user-exec.c | 256 ++++-
85
exec.c | 2 +-
86
hw/arm/aspeed.c | 73 +-
87
hw/arm/aspeed_ast2600.c | 6 +-
88
hw/arm/musicpal.c | 12 +-
89
hw/arm/nrf51_soc.c | 9 +-
90
hw/i2c/microbit_i2c.c | 2 +-
91
hw/misc/aspeed_scu.c | 11 +-
92
hw/misc/aspeed_sdmc.c | 55 +-
93
hw/timer/nrf51_timer.c | 14 +-
94
target/arm/cpu.c | 662 +----------
95
target/arm/cpu64.c | 18 +-
96
target/arm/cpu_tcg.c | 664 +++++++++++
97
target/arm/helper.c | 30 +-
98
target/arm/kvm32.c | 13 +-
99
target/arm/kvm64.c | 22 +-
100
target/arm/sve_helper.c | 2398 +++++++++++++++++++++-------------------
101
target/arm/translate-sve.c | 93 +-
102
hw/timer/trace-events | 5 +-
103
target/arm/Makefile.objs | 1 +
104
33 files changed, 2975 insertions(+), 2248 deletions(-)
105
create mode 100644 target/arm/cpu_tcg.c
106
58
59
docs/system/arm/aspeed.rst | 1 +
60
docs/system/arm/nuvoton.rst | 5 +-
61
include/hw/arm/bcm2835_peripherals.h | 3 +-
62
include/hw/misc/bcm2835_powermgt.h | 29 ++
63
target/arm/helper-mve.h | 108 +++++++
64
target/arm/translate.h | 41 +++
65
target/arm/mve.decode | 177 ++++++++++-
66
target/arm/t32.decode | 71 ++++-
67
hw/arm/bcm2835_peripherals.c | 13 +-
68
hw/gpio/gpio_pwr.c | 2 +-
69
hw/misc/bcm2835_powermgt.c | 160 ++++++++++
70
target/arm/helper-a64.c | 12 +-
71
target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++--
72
target/arm/translate-a64.c | 86 +-----
73
target/arm/translate-mve.c | 261 +++++++++++++++-
74
target/arm/translate-neon.c | 81 -----
75
target/arm/translate.c | 327 +++++++++++++++++++-
76
target/arm/vfp_helper.c | 24 +-
77
hw/misc/meson.build | 1 +
78
tests/acceptance/boot_linux_console.py | 43 +++
79
20 files changed, 1760 insertions(+), 209 deletions(-)
80
create mode 100644 include/hw/misc/bcm2835_powermgt.h
81
create mode 100644 hw/misc/bcm2835_powermgt.c
82
diff view generated by jsdifflib
[PULL 23/34] target/arm: Reuse sve_probe_page for gather first-fault loads
[PULL 01/24] docs/system/arm: Add quanta-q7l1-bmc reference
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Patrick Venture <venture@google.com>
2
2
3
This avoids the need for a separate set of helpers to implement
3
Adds a line-item reference to the supported quanta-q71l-bmc aspeed
4
no-fault semantics, and will enable MTE in the future.
4
entry.
5
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Patrick Venture <venture@google.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 20200508154359.7494-17-richard.henderson@linaro.org
8
Message-id: 20210615192848.1065297-2-venture@google.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/sve_helper.c | 323 ++++++++++++++++------------------------
11
docs/system/arm/aspeed.rst | 1 +
12
1 file changed, 127 insertions(+), 196 deletions(-)
12
1 file changed, 1 insertion(+)
13
13
14
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/sve_helper.c
16
--- a/docs/system/arm/aspeed.rst
17
+++ b/target/arm/sve_helper.c
17
+++ b/docs/system/arm/aspeed.rst
18
@@ -XXX,XX +XXX,XX @@ DO_LD1_ZPZ_D(dd_be, zd)
18
@@ -XXX,XX +XXX,XX @@ etc.
19
19
AST2400 SoC based machines :
20
/* First fault loads with a vector index. */
20
21
21
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
22
-/* Load one element into VD+REG_OFF from (ENV,VADDR) without faulting.
22
+- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
23
- * The controlling predicate is known to be true. Return true if the
23
24
- * load was successful.
24
AST2500 SoC based machines :
25
- */
26
-typedef bool sve_ld1_nf_fn(CPUARMState *env, void *vd, intptr_t reg_off,
27
- target_ulong vaddr, int mmu_idx);
28
-
29
-#ifdef CONFIG_SOFTMMU
30
-#define DO_LD_NF(NAME, H, TYPEE, TYPEM, HOST) \
31
-static bool sve_ld##NAME##_nf(CPUARMState *env, void *vd, intptr_t reg_off, \
32
- target_ulong addr, int mmu_idx) \
33
-{ \
34
- target_ulong next_page = -(addr | TARGET_PAGE_MASK); \
35
- if (likely(next_page - addr >= sizeof(TYPEM))) { \
36
- void *host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_idx); \
37
- if (likely(host)) { \
38
- TYPEM val = HOST(host); \
39
- *(TYPEE *)(vd + H(reg_off)) = val; \
40
- return true; \
41
- } \
42
- } \
43
- return false; \
44
-}
45
-#else
46
-#define DO_LD_NF(NAME, H, TYPEE, TYPEM, HOST) \
47
-static bool sve_ld##NAME##_nf(CPUARMState *env, void *vd, intptr_t reg_off, \
48
- target_ulong addr, int mmu_idx) \
49
-{ \
50
- if (likely(page_check_range(addr, sizeof(TYPEM), PAGE_READ))) { \
51
- TYPEM val = HOST(g2h(addr)); \
52
- *(TYPEE *)(vd + H(reg_off)) = val; \
53
- return true; \
54
- } \
55
- return false; \
56
-}
57
-#endif
58
-
59
-DO_LD_NF(bsu, H1_4, uint32_t, uint8_t, ldub_p)
60
-DO_LD_NF(bss, H1_4, uint32_t, int8_t, ldsb_p)
61
-DO_LD_NF(bdu, , uint64_t, uint8_t, ldub_p)
62
-DO_LD_NF(bds, , uint64_t, int8_t, ldsb_p)
63
-
64
-DO_LD_NF(hsu_le, H1_4, uint32_t, uint16_t, lduw_le_p)
65
-DO_LD_NF(hss_le, H1_4, uint32_t, int16_t, ldsw_le_p)
66
-DO_LD_NF(hsu_be, H1_4, uint32_t, uint16_t, lduw_be_p)
67
-DO_LD_NF(hss_be, H1_4, uint32_t, int16_t, ldsw_be_p)
68
-DO_LD_NF(hdu_le, , uint64_t, uint16_t, lduw_le_p)
69
-DO_LD_NF(hds_le, , uint64_t, int16_t, ldsw_le_p)
70
-DO_LD_NF(hdu_be, , uint64_t, uint16_t, lduw_be_p)
71
-DO_LD_NF(hds_be, , uint64_t, int16_t, ldsw_be_p)
72
-
73
-DO_LD_NF(ss_le, H1_4, uint32_t, uint32_t, ldl_le_p)
74
-DO_LD_NF(ss_be, H1_4, uint32_t, uint32_t, ldl_be_p)
75
-DO_LD_NF(sdu_le, , uint64_t, uint32_t, ldl_le_p)
76
-DO_LD_NF(sds_le, , uint64_t, int32_t, ldl_le_p)
77
-DO_LD_NF(sdu_be, , uint64_t, uint32_t, ldl_be_p)
78
-DO_LD_NF(sds_be, , uint64_t, int32_t, ldl_be_p)
79
-
80
-DO_LD_NF(dd_le, , uint64_t, uint64_t, ldq_le_p)
81
-DO_LD_NF(dd_be, , uint64_t, uint64_t, ldq_be_p)
82
-
83
/*
84
- * Common helper for all gather first-faulting loads.
85
+ * Common helpers for all gather first-faulting loads.
86
*/
87
-static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
88
- target_ulong base, uint32_t desc, uintptr_t ra,
89
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
90
- sve_ld1_nf_fn *nonfault_fn)
91
+
92
+static inline QEMU_ALWAYS_INLINE
93
+void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
94
+ target_ulong base, uint32_t desc, uintptr_t retaddr,
95
+ const int esz, const int msz, zreg_off_fn *off_fn,
96
+ sve_ldst1_host_fn *host_fn,
97
+ sve_ldst1_tlb_fn *tlb_fn)
98
{
99
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
100
- const int mmu_idx = get_mmuidx(oi);
101
+ const int mmu_idx = cpu_mmu_index(env, false);
102
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
103
- intptr_t reg_off, reg_max = simd_oprsz(desc);
104
- target_ulong addr;
105
+ const int esize = 1 << esz;
106
+ const int msize = 1 << msz;
107
+ const intptr_t reg_max = simd_oprsz(desc);
108
+ intptr_t reg_off;
109
+ SVEHostPage info;
110
+ target_ulong addr, in_page;
111
112
/* Skip to the first true predicate. */
113
- reg_off = find_next_active(vg, 0, reg_max, MO_32);
114
- if (likely(reg_off < reg_max)) {
115
- /* Perform one normal read, which will fault or not. */
116
- addr = off_fn(vm, reg_off);
117
- addr = base + (addr << scale);
118
- tlb_fn(env, vd, reg_off, addr, ra);
119
-
120
- /* The rest of the reads will be non-faulting. */
121
+ reg_off = find_next_active(vg, 0, reg_max, esz);
122
+ if (unlikely(reg_off >= reg_max)) {
123
+ /* The entire predicate was false; no load occurs. */
124
+ memset(vd, 0, reg_max);
125
+ return;
126
}
127
128
- /* After any fault, zero the leading predicated false elements. */
129
+ /*
130
+ * Probe the first element, allowing faults.
131
+ */
132
+ addr = base + (off_fn(vm, reg_off) << scale);
133
+ tlb_fn(env, vd, reg_off, addr, retaddr);
134
+
135
+ /* After any fault, zero the other elements. */
136
swap_memzero(vd, reg_off);
137
+ reg_off += esize;
138
+ swap_memzero(vd + reg_off, reg_max - reg_off);
139
140
- while (likely((reg_off += 4) < reg_max)) {
141
- uint64_t pg = *(uint64_t *)(vg + (reg_off >> 6) * 8);
142
- if (likely((pg >> (reg_off & 63)) & 1)) {
143
- addr = off_fn(vm, reg_off);
144
- addr = base + (addr << scale);
145
- if (!nonfault_fn(env, vd, reg_off, addr, mmu_idx)) {
146
- record_fault(env, reg_off, reg_max);
147
- break;
148
+ /*
149
+ * Probe the remaining elements, not allowing faults.
150
+ */
151
+ while (reg_off < reg_max) {
152
+ uint64_t pg = vg[reg_off >> 6];
153
+ do {
154
+ if (likely((pg >> (reg_off & 63)) & 1)) {
155
+ addr = base + (off_fn(vm, reg_off) << scale);
156
+ in_page = -(addr | TARGET_PAGE_MASK);
157
+
158
+ if (unlikely(in_page < msize)) {
159
+ /* Stop if the element crosses a page boundary. */
160
+ goto fault;
161
+ }
162
+
163
+ sve_probe_page(&info, true, env, addr, 0, MMU_DATA_LOAD,
164
+ mmu_idx, retaddr);
165
+ if (unlikely(info.flags & (TLB_INVALID_MASK | TLB_MMIO))) {
166
+ goto fault;
167
+ }
168
+ if (unlikely(info.flags & TLB_WATCHPOINT) &&
169
+ (cpu_watchpoint_address_matches
170
+ (env_cpu(env), addr, msize) & BP_MEM_READ)) {
171
+ goto fault;
172
+ }
173
+ /* TODO: MTE check. */
174
+
175
+ host_fn(vd, reg_off, info.host);
176
}
177
- } else {
178
- *(uint32_t *)(vd + H1_4(reg_off)) = 0;
179
- }
180
+ reg_off += esize;
181
+ } while (reg_off & 63);
182
}
183
+ return;
184
+
185
+ fault:
186
+ record_fault(env, reg_off, reg_max);
187
}
188
189
-static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
190
- target_ulong base, uint32_t desc, uintptr_t ra,
191
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
192
- sve_ld1_nf_fn *nonfault_fn)
193
-{
194
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
195
- const int mmu_idx = get_mmuidx(oi);
196
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
197
- intptr_t reg_off, reg_max = simd_oprsz(desc);
198
- target_ulong addr;
199
-
200
- /* Skip to the first true predicate. */
201
- reg_off = find_next_active(vg, 0, reg_max, MO_64);
202
- if (likely(reg_off < reg_max)) {
203
- /* Perform one normal read, which will fault or not. */
204
- addr = off_fn(vm, reg_off);
205
- addr = base + (addr << scale);
206
- tlb_fn(env, vd, reg_off, addr, ra);
207
-
208
- /* The rest of the reads will be non-faulting. */
209
- }
210
-
211
- /* After any fault, zero the leading predicated false elements. */
212
- swap_memzero(vd, reg_off);
213
-
214
- while (likely((reg_off += 8) < reg_max)) {
215
- uint8_t pg = *(uint8_t *)(vg + H1(reg_off >> 3));
216
- if (likely(pg & 1)) {
217
- addr = off_fn(vm, reg_off);
218
- addr = base + (addr << scale);
219
- if (!nonfault_fn(env, vd, reg_off, addr, mmu_idx)) {
220
- record_fault(env, reg_off, reg_max);
221
- break;
222
- }
223
- } else {
224
- *(uint64_t *)(vd + reg_off) = 0;
225
- }
226
- }
227
+#define DO_LDFF1_ZPZ_S(MEM, OFS, MSZ) \
228
+void HELPER(sve_ldff##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
229
+ void *vm, target_ulong base, uint32_t desc) \
230
+{ \
231
+ sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), MO_32, MSZ, \
232
+ off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
233
}
234
235
-#define DO_LDFF1_ZPZ_S(MEM, OFS) \
236
-void HELPER(sve_ldff##MEM##_##OFS) \
237
- (CPUARMState *env, void *vd, void *vg, void *vm, \
238
- target_ulong base, uint32_t desc) \
239
-{ \
240
- sve_ldff1_zs(env, vd, vg, vm, base, desc, GETPC(), \
241
- off_##OFS##_s, sve_ld1##MEM##_tlb, sve_ld##MEM##_nf); \
242
+#define DO_LDFF1_ZPZ_D(MEM, OFS, MSZ) \
243
+void HELPER(sve_ldff##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
244
+ void *vm, target_ulong base, uint32_t desc) \
245
+{ \
246
+ sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), MO_64, MSZ, \
247
+ off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
248
}
249
250
-#define DO_LDFF1_ZPZ_D(MEM, OFS) \
251
-void HELPER(sve_ldff##MEM##_##OFS) \
252
- (CPUARMState *env, void *vd, void *vg, void *vm, \
253
- target_ulong base, uint32_t desc) \
254
-{ \
255
- sve_ldff1_zd(env, vd, vg, vm, base, desc, GETPC(), \
256
- off_##OFS##_d, sve_ld1##MEM##_tlb, sve_ld##MEM##_nf); \
257
-}
258
+DO_LDFF1_ZPZ_S(bsu, zsu, MO_8)
259
+DO_LDFF1_ZPZ_S(bsu, zss, MO_8)
260
+DO_LDFF1_ZPZ_D(bdu, zsu, MO_8)
261
+DO_LDFF1_ZPZ_D(bdu, zss, MO_8)
262
+DO_LDFF1_ZPZ_D(bdu, zd, MO_8)
263
264
-DO_LDFF1_ZPZ_S(bsu, zsu)
265
-DO_LDFF1_ZPZ_S(bsu, zss)
266
-DO_LDFF1_ZPZ_D(bdu, zsu)
267
-DO_LDFF1_ZPZ_D(bdu, zss)
268
-DO_LDFF1_ZPZ_D(bdu, zd)
269
+DO_LDFF1_ZPZ_S(bss, zsu, MO_8)
270
+DO_LDFF1_ZPZ_S(bss, zss, MO_8)
271
+DO_LDFF1_ZPZ_D(bds, zsu, MO_8)
272
+DO_LDFF1_ZPZ_D(bds, zss, MO_8)
273
+DO_LDFF1_ZPZ_D(bds, zd, MO_8)
274
275
-DO_LDFF1_ZPZ_S(bss, zsu)
276
-DO_LDFF1_ZPZ_S(bss, zss)
277
-DO_LDFF1_ZPZ_D(bds, zsu)
278
-DO_LDFF1_ZPZ_D(bds, zss)
279
-DO_LDFF1_ZPZ_D(bds, zd)
280
+DO_LDFF1_ZPZ_S(hsu_le, zsu, MO_16)
281
+DO_LDFF1_ZPZ_S(hsu_le, zss, MO_16)
282
+DO_LDFF1_ZPZ_D(hdu_le, zsu, MO_16)
283
+DO_LDFF1_ZPZ_D(hdu_le, zss, MO_16)
284
+DO_LDFF1_ZPZ_D(hdu_le, zd, MO_16)
285
286
-DO_LDFF1_ZPZ_S(hsu_le, zsu)
287
-DO_LDFF1_ZPZ_S(hsu_le, zss)
288
-DO_LDFF1_ZPZ_D(hdu_le, zsu)
289
-DO_LDFF1_ZPZ_D(hdu_le, zss)
290
-DO_LDFF1_ZPZ_D(hdu_le, zd)
291
+DO_LDFF1_ZPZ_S(hsu_be, zsu, MO_16)
292
+DO_LDFF1_ZPZ_S(hsu_be, zss, MO_16)
293
+DO_LDFF1_ZPZ_D(hdu_be, zsu, MO_16)
294
+DO_LDFF1_ZPZ_D(hdu_be, zss, MO_16)
295
+DO_LDFF1_ZPZ_D(hdu_be, zd, MO_16)
296
297
-DO_LDFF1_ZPZ_S(hsu_be, zsu)
298
-DO_LDFF1_ZPZ_S(hsu_be, zss)
299
-DO_LDFF1_ZPZ_D(hdu_be, zsu)
300
-DO_LDFF1_ZPZ_D(hdu_be, zss)
301
-DO_LDFF1_ZPZ_D(hdu_be, zd)
302
+DO_LDFF1_ZPZ_S(hss_le, zsu, MO_16)
303
+DO_LDFF1_ZPZ_S(hss_le, zss, MO_16)
304
+DO_LDFF1_ZPZ_D(hds_le, zsu, MO_16)
305
+DO_LDFF1_ZPZ_D(hds_le, zss, MO_16)
306
+DO_LDFF1_ZPZ_D(hds_le, zd, MO_16)
307
308
-DO_LDFF1_ZPZ_S(hss_le, zsu)
309
-DO_LDFF1_ZPZ_S(hss_le, zss)
310
-DO_LDFF1_ZPZ_D(hds_le, zsu)
311
-DO_LDFF1_ZPZ_D(hds_le, zss)
312
-DO_LDFF1_ZPZ_D(hds_le, zd)
313
+DO_LDFF1_ZPZ_S(hss_be, zsu, MO_16)
314
+DO_LDFF1_ZPZ_S(hss_be, zss, MO_16)
315
+DO_LDFF1_ZPZ_D(hds_be, zsu, MO_16)
316
+DO_LDFF1_ZPZ_D(hds_be, zss, MO_16)
317
+DO_LDFF1_ZPZ_D(hds_be, zd, MO_16)
318
319
-DO_LDFF1_ZPZ_S(hss_be, zsu)
320
-DO_LDFF1_ZPZ_S(hss_be, zss)
321
-DO_LDFF1_ZPZ_D(hds_be, zsu)
322
-DO_LDFF1_ZPZ_D(hds_be, zss)
323
-DO_LDFF1_ZPZ_D(hds_be, zd)
324
+DO_LDFF1_ZPZ_S(ss_le, zsu, MO_32)
325
+DO_LDFF1_ZPZ_S(ss_le, zss, MO_32)
326
+DO_LDFF1_ZPZ_D(sdu_le, zsu, MO_32)
327
+DO_LDFF1_ZPZ_D(sdu_le, zss, MO_32)
328
+DO_LDFF1_ZPZ_D(sdu_le, zd, MO_32)
329
330
-DO_LDFF1_ZPZ_S(ss_le, zsu)
331
-DO_LDFF1_ZPZ_S(ss_le, zss)
332
-DO_LDFF1_ZPZ_D(sdu_le, zsu)
333
-DO_LDFF1_ZPZ_D(sdu_le, zss)
334
-DO_LDFF1_ZPZ_D(sdu_le, zd)
335
+DO_LDFF1_ZPZ_S(ss_be, zsu, MO_32)
336
+DO_LDFF1_ZPZ_S(ss_be, zss, MO_32)
337
+DO_LDFF1_ZPZ_D(sdu_be, zsu, MO_32)
338
+DO_LDFF1_ZPZ_D(sdu_be, zss, MO_32)
339
+DO_LDFF1_ZPZ_D(sdu_be, zd, MO_32)
340
341
-DO_LDFF1_ZPZ_S(ss_be, zsu)
342
-DO_LDFF1_ZPZ_S(ss_be, zss)
343
-DO_LDFF1_ZPZ_D(sdu_be, zsu)
344
-DO_LDFF1_ZPZ_D(sdu_be, zss)
345
-DO_LDFF1_ZPZ_D(sdu_be, zd)
346
+DO_LDFF1_ZPZ_D(sds_le, zsu, MO_32)
347
+DO_LDFF1_ZPZ_D(sds_le, zss, MO_32)
348
+DO_LDFF1_ZPZ_D(sds_le, zd, MO_32)
349
350
-DO_LDFF1_ZPZ_D(sds_le, zsu)
351
-DO_LDFF1_ZPZ_D(sds_le, zss)
352
-DO_LDFF1_ZPZ_D(sds_le, zd)
353
+DO_LDFF1_ZPZ_D(sds_be, zsu, MO_32)
354
+DO_LDFF1_ZPZ_D(sds_be, zss, MO_32)
355
+DO_LDFF1_ZPZ_D(sds_be, zd, MO_32)
356
357
-DO_LDFF1_ZPZ_D(sds_be, zsu)
358
-DO_LDFF1_ZPZ_D(sds_be, zss)
359
-DO_LDFF1_ZPZ_D(sds_be, zd)
360
+DO_LDFF1_ZPZ_D(dd_le, zsu, MO_64)
361
+DO_LDFF1_ZPZ_D(dd_le, zss, MO_64)
362
+DO_LDFF1_ZPZ_D(dd_le, zd, MO_64)
363
364
-DO_LDFF1_ZPZ_D(dd_le, zsu)
365
-DO_LDFF1_ZPZ_D(dd_le, zss)
366
-DO_LDFF1_ZPZ_D(dd_le, zd)
367
-
368
-DO_LDFF1_ZPZ_D(dd_be, zsu)
369
-DO_LDFF1_ZPZ_D(dd_be, zss)
370
-DO_LDFF1_ZPZ_D(dd_be, zd)
371
+DO_LDFF1_ZPZ_D(dd_be, zsu, MO_64)
372
+DO_LDFF1_ZPZ_D(dd_be, zss, MO_64)
373
+DO_LDFF1_ZPZ_D(dd_be, zd, MO_64)
374
375
/* Stores with a vector index. */
376
25
377
--
26
--
378
2.20.1
27
2.20.1
379
28
380
29
diff view generated by jsdifflib
[PULL 34/34] target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)
[PULL 02/24] docs/system/arm: Add quanta-gbs-bmc reference
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Patrick Venture <venture@google.com>
2
2
3
DUP (indexed) can duplicate 128-bit elements, so using esz
3
Add line item reference to quanta-gbs-bmc machine.
4
unconditionally can assert in tcg_gen_gvec_dup_imm.
5
4
6
Fixes: 8711e71f9cbb
5
Signed-off-by: Patrick Venture <venture@google.com>
7
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210615192848.1065297-3-venture@google.com
9
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
[PMM: fixed underline Sphinx warning]
10
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Message-id: 20200507172352.15418-5-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
target/arm/translate-sve.c | 6 +++++-
11
docs/system/arm/nuvoton.rst | 5 +++--
15
1 file changed, 5 insertions(+), 1 deletion(-)
12
1 file changed, 3 insertions(+), 2 deletions(-)
16
13
17
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate-sve.c
16
--- a/docs/system/arm/nuvoton.rst
20
+++ b/target/arm/translate-sve.c
17
+++ b/docs/system/arm/nuvoton.rst
21
@@ -XXX,XX +XXX,XX @@ static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a)
18
@@ -XXX,XX +XXX,XX @@
22
unsigned nofs = vec_reg_offset(s, a->rn, index, esz);
19
-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
23
tcg_gen_gvec_dup_mem(esz, dofs, nofs, vsz, vsz);
20
-=====================================================
24
} else {
21
+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
25
- tcg_gen_gvec_dup_imm(esz, dofs, vsz, vsz, 0);
22
+================================================================
26
+ /*
23
27
+ * While dup_mem handles 128-bit elements, dup_imm does not.
24
The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
28
+ * Thankfully element size doesn't matter for splatting zero.
25
designed to be used as Baseboard Management Controllers (BMCs) in various
29
+ */
26
@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
30
+ tcg_gen_gvec_dup_imm(MO_64, dofs, vsz, vsz, 0);
27
The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
31
}
28
Hyperscale applications. The following machines are based on this chip :
32
}
29
33
return true;
30
+- ``quanta-gbs-bmc`` Quanta GBS server BMC
31
- ``quanta-gsj`` Quanta GSJ server BMC
32
33
There are also two more SoCs, NPCM710 and NPCM705, which are single-core
34
--
34
--
35
2.20.1
35
2.20.1
36
36
37
37
diff view generated by jsdifflib
[PULL 04/34] aspeed: sdmc: Implement AST2600 locking behaviour
[PULL 03/24] hw/arm: Add basic power management to raspi.
1
From: Joel Stanley <joel@jms.id.au>
1
From: Nolan Leake <nolan@sigbus.net>
2
2
3
The AST2600 handles this differently with the extra 'hardlock' state, so
3
This is just enough to make reboot and poweroff work. Works for
4
move the testing to the soc specific class' write callback.
4
linux, u-boot, and the arm trusted firmware. Not tested, but should
5
5
work for plan9, and bare-metal/hobby OSes, since they seem to generally
6
Signed-off-by: Joel Stanley <joel@jms.id.au>
6
do what linux does for reset.
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
7
8
Message-id: 20200505090136.341426-1-joel@jms.id.au
8
The watchdog timer functionality is not yet implemented.
9
10
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
11
Signed-off-by: Nolan Leake <nolan@sigbus.net>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
15
[PMM: tweaked commit title; fixed region size to 0x200;
16
moved header file to include/]
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
18
---
11
hw/misc/aspeed_sdmc.c | 55 +++++++++++++++++++++++++++++++++++--------
19
include/hw/arm/bcm2835_peripherals.h | 3 +-
12
1 file changed, 45 insertions(+), 10 deletions(-)
20
include/hw/misc/bcm2835_powermgt.h | 29 +++++
13
21
hw/arm/bcm2835_peripherals.c | 13 ++-
14
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
22
hw/misc/bcm2835_powermgt.c | 160 +++++++++++++++++++++++++++
23
hw/misc/meson.build | 1 +
24
5 files changed, 204 insertions(+), 2 deletions(-)
25
create mode 100644 include/hw/misc/bcm2835_powermgt.h
26
create mode 100644 hw/misc/bcm2835_powermgt.c
27
28
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
15
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/misc/aspeed_sdmc.c
30
--- a/include/hw/arm/bcm2835_peripherals.h
17
+++ b/hw/misc/aspeed_sdmc.c
31
+++ b/include/hw/arm/bcm2835_peripherals.h
18
@@ -XXX,XX +XXX,XX @@
32
@@ -XXX,XX +XXX,XX @@
19
33
#include "hw/misc/bcm2835_mphi.h"
20
/* Protection Key Register */
34
#include "hw/misc/bcm2835_thermal.h"
21
#define R_PROT (0x00 / 4)
35
#include "hw/misc/bcm2835_cprman.h"
22
+#define PROT_UNLOCKED 0x01
36
+#include "hw/misc/bcm2835_powermgt.h"
23
+#define PROT_HARDLOCKED 0x10 /* AST2600 */
37
#include "hw/sd/sdhci.h"
24
+#define PROT_SOFTLOCKED 0x00
38
#include "hw/sd/bcm2835_sdhost.h"
25
+
39
#include "hw/gpio/bcm2835_gpio.h"
26
#define PROT_KEY_UNLOCK 0xFC600309
40
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
27
+#define PROT_KEY_HARDLOCK 0xDEADDEAD /* AST2600 */
41
BCM2835MphiState mphi;
28
42
UnimplementedDeviceState txp;
29
/* Configuration Register */
43
UnimplementedDeviceState armtmr;
30
#define R_CONF (0x04 / 4)
44
- UnimplementedDeviceState powermgt;
31
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
45
+ BCM2835PowerMgtState powermgt;
32
return;
46
BCM2835CprmanState cprman;
33
}
47
PL011State uart0;
34
48
BCM2835AuxState aux;
35
- if (addr == R_PROT) {
49
diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
36
- s->regs[addr] = (data == PROT_KEY_UNLOCK) ? 1 : 0;
50
new file mode 100644
37
- return;
51
index XXXXXXX..XXXXXXX
38
- }
52
--- /dev/null
39
-
53
+++ b/include/hw/misc/bcm2835_powermgt.h
40
- if (!s->regs[R_PROT]) {
54
@@ -XXX,XX +XXX,XX @@
41
- qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
55
+/*
42
- return;
56
+ * BCM2835 Power Management emulation
43
- }
57
+ *
44
-
58
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
45
asc->write(s, addr, data);
59
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
60
+ *
61
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
62
+ * See the COPYING file in the top-level directory.
63
+ */
64
+
65
+#ifndef BCM2835_POWERMGT_H
66
+#define BCM2835_POWERMGT_H
67
+
68
+#include "hw/sysbus.h"
69
+#include "qom/object.h"
70
+
71
+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
72
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
73
+
74
+struct BCM2835PowerMgtState {
75
+ SysBusDevice busdev;
76
+ MemoryRegion iomem;
77
+
78
+ uint32_t rstc;
79
+ uint32_t rsts;
80
+ uint32_t wdog;
81
+};
82
+
83
+#endif
84
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/hw/arm/bcm2835_peripherals.c
87
+++ b/hw/arm/bcm2835_peripherals.c
88
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
89
90
object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
91
OBJECT(&s->gpu_bus_mr));
92
+
93
+ /* Power Management */
94
+ object_initialize_child(obj, "powermgt", &s->powermgt,
95
+ TYPE_BCM2835_POWERMGT);
46
}
96
}
47
97
48
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
98
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
49
static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg,
99
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
50
uint32_t data)
100
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
51
{
101
INTERRUPT_USB));
52
+ if (reg == R_PROT) {
102
53
+ s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
103
+ /* Power Management */
104
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
54
+ return;
105
+ return;
55
+ }
106
+ }
56
+
107
+
57
+ if (!s->regs[R_PROT]) {
108
+ memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
58
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
109
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
110
+
111
create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
112
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
113
- create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
114
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
115
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
116
create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
117
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
118
new file mode 100644
119
index XXXXXXX..XXXXXXX
120
--- /dev/null
121
+++ b/hw/misc/bcm2835_powermgt.c
122
@@ -XXX,XX +XXX,XX @@
123
+/*
124
+ * BCM2835 Power Management emulation
125
+ *
126
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
127
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
128
+ *
129
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
130
+ * See the COPYING file in the top-level directory.
131
+ */
132
+
133
+#include "qemu/osdep.h"
134
+#include "qemu/log.h"
135
+#include "qemu/module.h"
136
+#include "hw/misc/bcm2835_powermgt.h"
137
+#include "migration/vmstate.h"
138
+#include "sysemu/runstate.h"
139
+
140
+#define PASSWORD 0x5a000000
141
+#define PASSWORD_MASK 0xff000000
142
+
143
+#define R_RSTC 0x1c
144
+#define V_RSTC_RESET 0x20
145
+#define R_RSTS 0x20
146
+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
147
+#define R_WDOG 0x24
148
+
149
+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
150
+ unsigned size)
151
+{
152
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
153
+ uint32_t res = 0;
154
+
155
+ switch (offset) {
156
+ case R_RSTC:
157
+ res = s->rstc;
158
+ break;
159
+ case R_RSTS:
160
+ res = s->rsts;
161
+ break;
162
+ case R_WDOG:
163
+ res = s->wdog;
164
+ break;
165
+
166
+ default:
167
+ qemu_log_mask(LOG_UNIMP,
168
+ "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
169
+ "\n", offset);
170
+ res = 0;
171
+ break;
172
+ }
173
+
174
+ return res;
175
+}
176
+
177
+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
178
+ uint64_t value, unsigned size)
179
+{
180
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
181
+
182
+ if ((value & PASSWORD_MASK) != PASSWORD) {
183
+ qemu_log_mask(LOG_GUEST_ERROR,
184
+ "bcm2835_powermgt_write: Bad password 0x%"PRIx64
185
+ " at offset 0x%08"HWADDR_PRIx"\n",
186
+ value, offset);
59
+ return;
187
+ return;
60
+ }
188
+ }
61
+
189
+
62
switch (reg) {
190
+ value = value & ~PASSWORD_MASK;
63
case R_CONF:
191
+
64
data = aspeed_2400_sdmc_compute_conf(s, data);
192
+ switch (offset) {
65
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
193
+ case R_RSTC:
66
static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg,
194
+ s->rstc = value;
67
uint32_t data)
195
+ if (value & V_RSTC_RESET) {
68
{
196
+ if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
69
+ if (reg == R_PROT) {
197
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
70
+ s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
198
+ } else {
71
+ return;
199
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
72
+ }
200
+ }
73
+
74
+ if (!s->regs[R_PROT]) {
75
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
76
+ return;
77
+ }
78
+
79
switch (reg) {
80
case R_CONF:
81
data = aspeed_2500_sdmc_compute_conf(s, data);
82
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
83
static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,
84
uint32_t data)
85
{
86
+ if (s->regs[R_PROT] == PROT_HARDLOCKED) {
87
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n",
88
+ __func__);
89
+ return;
90
+ }
91
+
92
+ if (reg != R_PROT && s->regs[R_PROT] == PROT_SOFTLOCKED) {
93
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
94
+ return;
95
+ }
96
+
97
switch (reg) {
98
+ case R_PROT:
99
+ if (data == PROT_KEY_UNLOCK) {
100
+ data = PROT_UNLOCKED;
101
+ } else if (data == PROT_KEY_HARDLOCK) {
102
+ data = PROT_HARDLOCKED;
103
+ } else {
104
+ data = PROT_SOFTLOCKED;
105
+ }
201
+ }
106
+ break;
202
+ break;
107
case R_CONF:
203
+ case R_RSTS:
108
data = aspeed_2600_sdmc_compute_conf(s, data);
204
+ qemu_log_mask(LOG_UNIMP,
109
break;
205
+ "bcm2835_powermgt_write: RSTS\n");
206
+ s->rsts = value;
207
+ break;
208
+ case R_WDOG:
209
+ qemu_log_mask(LOG_UNIMP,
210
+ "bcm2835_powermgt_write: WDOG\n");
211
+ s->wdog = value;
212
+ break;
213
+
214
+ default:
215
+ qemu_log_mask(LOG_UNIMP,
216
+ "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
217
+ "\n", offset);
218
+ break;
219
+ }
220
+}
221
+
222
+static const MemoryRegionOps bcm2835_powermgt_ops = {
223
+ .read = bcm2835_powermgt_read,
224
+ .write = bcm2835_powermgt_write,
225
+ .endianness = DEVICE_NATIVE_ENDIAN,
226
+ .impl.min_access_size = 4,
227
+ .impl.max_access_size = 4,
228
+};
229
+
230
+static const VMStateDescription vmstate_bcm2835_powermgt = {
231
+ .name = TYPE_BCM2835_POWERMGT,
232
+ .version_id = 1,
233
+ .minimum_version_id = 1,
234
+ .fields = (VMStateField[]) {
235
+ VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
236
+ VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
237
+ VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
238
+ VMSTATE_END_OF_LIST()
239
+ }
240
+};
241
+
242
+static void bcm2835_powermgt_init(Object *obj)
243
+{
244
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
245
+
246
+ memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
247
+ TYPE_BCM2835_POWERMGT, 0x200);
248
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
249
+}
250
+
251
+static void bcm2835_powermgt_reset(DeviceState *dev)
252
+{
253
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
254
+
255
+ /* https://elinux.org/BCM2835_registers#PM */
256
+ s->rstc = 0x00000102;
257
+ s->rsts = 0x00001000;
258
+ s->wdog = 0x00000000;
259
+}
260
+
261
+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
262
+{
263
+ DeviceClass *dc = DEVICE_CLASS(klass);
264
+
265
+ dc->reset = bcm2835_powermgt_reset;
266
+ dc->vmsd = &vmstate_bcm2835_powermgt;
267
+}
268
+
269
+static TypeInfo bcm2835_powermgt_info = {
270
+ .name = TYPE_BCM2835_POWERMGT,
271
+ .parent = TYPE_SYS_BUS_DEVICE,
272
+ .instance_size = sizeof(BCM2835PowerMgtState),
273
+ .class_init = bcm2835_powermgt_class_init,
274
+ .instance_init = bcm2835_powermgt_init,
275
+};
276
+
277
+static void bcm2835_powermgt_register_types(void)
278
+{
279
+ type_register_static(&bcm2835_powermgt_info);
280
+}
281
+
282
+type_init(bcm2835_powermgt_register_types)
283
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
284
index XXXXXXX..XXXXXXX 100644
285
--- a/hw/misc/meson.build
286
+++ b/hw/misc/meson.build
287
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
288
'bcm2835_rng.c',
289
'bcm2835_thermal.c',
290
'bcm2835_cprman.c',
291
+ 'bcm2835_powermgt.c',
292
))
293
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
294
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
110
--
295
--
111
2.20.1
296
2.20.1
112
297
113
298
diff view generated by jsdifflib
[PULL 32/34] hw/arm/musicpal: Map the UART devices unconditionally
[PULL 04/24] tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
I can't find proper documentation or datasheet, but it is likely
3
Add a test booting and quickly shutdown a raspi2 machine,
4
a MMIO mapped serial device mapped in the 0x80000000..0x8000ffff
4
to test the power management model:
5
range belongs to the SoC address space, thus is always mapped in
5
6
the memory bus.
6
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
7
Map the devices on the bus regardless a chardev is attached to it.
7
console: [ 0.000000] Booting Linux on physical CPU 0xf00
8
console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
9
console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
10
console: [ 0.000000] CPU: div instructions available: patching division code
11
console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
12
console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
13
...
14
console: Boot successful.
15
console: cat /proc/cpuinfo
16
console: / # cat /proc/cpuinfo
17
...
18
console: processor : 3
19
console: model name : ARMv7 Processor rev 5 (v7l)
20
console: BogoMIPS : 125.00
21
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
22
console: CPU implementer : 0x41
23
console: CPU architecture: 7
24
console: CPU variant : 0x0
25
console: CPU part : 0xc07
26
console: CPU revision : 5
27
console: Hardware : BCM2835
28
console: Revision : 0000
29
console: Serial : 0000000000000000
30
console: cat /proc/iomem
31
console: / # cat /proc/iomem
32
console: 00000000-3bffffff : System RAM
33
console: 00008000-00afffff : Kernel code
34
console: 00c00000-00d468ef : Kernel data
35
console: 3f006000-3f006fff : dwc_otg
36
console: 3f007000-3f007eff : /soc/dma@7e007000
37
console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
38
console: 3f100000-3f100027 : /soc/watchdog@7e100000
39
console: 3f101000-3f102fff : /soc/cprman@7e101000
40
console: 3f200000-3f2000b3 : /soc/gpio@7e200000
41
PASS (24.59 s)
42
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
43
JOB TIME : 25.02 s
8
44
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
45
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Jan Kiszka <jan.kiszka@web.de>
46
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
11
Message-id: 20200505095945.23146-1-f4bug@amsat.org
47
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
48
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
49
---
14
hw/arm/musicpal.c | 12 ++++--------
50
tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
15
1 file changed, 4 insertions(+), 8 deletions(-)
51
1 file changed, 43 insertions(+)
16
52
17
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
53
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
18
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/musicpal.c
55
--- a/tests/acceptance/boot_linux_console.py
20
+++ b/hw/arm/musicpal.c
56
+++ b/tests/acceptance/boot_linux_console.py
21
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
57
@@ -XXX,XX +XXX,XX @@
22
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
58
from avocado import skip
23
pic[MP_TIMER4_IRQ], NULL);
59
from avocado import skipUnless
24
60
from avocado_qemu import Test
25
- if (serial_hd(0)) {
61
+from avocado_qemu import exec_command
26
- serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
62
from avocado_qemu import exec_command_and_wait_for_pattern
27
- 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
63
from avocado_qemu import interrupt_interactive_console_until_pattern
28
- }
64
from avocado_qemu import wait_for_console_pattern
29
- if (serial_hd(1)) {
65
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
30
- serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
66
"""
31
- 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
67
self.do_test_arm_raspi2(0)
32
- }
68
33
+ serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
69
+ def test_arm_raspi2_initrd(self):
34
+ 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
70
+ """
35
+ serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
71
+ :avocado: tags=arch:arm
36
+ 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
72
+ :avocado: tags=machine:raspi2
37
73
+ """
38
/* Register flash */
74
+ deb_url = ('http://archive.raspberrypi.org/debian/'
39
dinfo = drive_get(IF_PFLASH, 0, 0);
75
+ 'pool/main/r/raspberrypi-firmware/'
76
+ 'raspberrypi-kernel_1.20190215-1_armhf.deb')
77
+ deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
78
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
79
+ kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
80
+ dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
81
+
82
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
83
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
84
+ 'arm/rootfs-armv7a.cpio.gz')
85
+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
86
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
87
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
88
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
89
+
90
+ self.vm.set_console()
91
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
92
+ 'earlycon=pl011,0x3f201000 console=ttyAMA0 '
93
+ 'panic=-1 noreboot ' +
94
+ 'dwc_otg.fiq_fsm_enable=0')
95
+ self.vm.add_args('-kernel', kernel_path,
96
+ '-dtb', dtb_path,
97
+ '-initrd', initrd_path,
98
+ '-append', kernel_command_line,
99
+ '-no-reboot')
100
+ self.vm.launch()
101
+ self.wait_for_console_pattern('Boot successful.')
102
+
103
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
104
+ 'BCM2835')
105
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
106
+ '/soc/cprman@7e101000')
107
+ exec_command(self, 'halt')
108
+ # Wait for VM to shut down gracefully
109
+ self.vm.wait()
110
+
111
def test_arm_exynos4210_initrd(self):
112
"""
113
:avocado: tags=arch:arm
40
--
114
--
41
2.20.1
115
2.20.1
42
116
43
117
diff view generated by jsdifflib
[PULL 11/34] accel/tcg: Adjust probe_access call to page_check_range
[PULL 05/24] target/arm: Check NaN mode before silencing NaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Joe Komlodi <joe.komlodi@xilinx.com>
2
2
3
We have validated that addr+size does not cross a page boundary.
3
If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
4
Therefore we need to validate exactly one page. We can achieve
4
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
5
that passing any value 1 <= x <= size to page_check_range.
5
assert due to fpst->default_nan_mode being set.
6
6
7
Passing 1 will simplify the next patch.
7
To avoid this, we check to see what NaN mode we're running in before we call
8
floatxx_silence_nan().
8
9
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
10
Message-id: 20200508154359.7494-5-richard.henderson@linaro.org
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
15
---
14
accel/tcg/user-exec.c | 2 +-
16
target/arm/helper-a64.c | 12 +++++++++---
15
1 file changed, 1 insertion(+), 1 deletion(-)
17
target/arm/vfp_helper.c | 24 ++++++++++++++++++------
18
2 files changed, 27 insertions(+), 9 deletions(-)
16
19
17
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
20
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
18
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
19
--- a/accel/tcg/user-exec.c
22
--- a/target/arm/helper-a64.c
20
+++ b/accel/tcg/user-exec.c
23
+++ b/target/arm/helper-a64.c
21
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
24
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
22
g_assert_not_reached();
25
float16 nan = a;
23
}
26
if (float16_is_signaling_nan(a, fpst)) {
24
27
float_raise(float_flag_invalid, fpst);
25
- if (!guest_addr_valid(addr) || page_check_range(addr, size, flags) < 0) {
28
- nan = float16_silence_nan(a, fpst);
26
+ if (!guest_addr_valid(addr) || page_check_range(addr, 1, flags) < 0) {
29
+ if (!fpst->default_nan_mode) {
27
CPUState *cpu = env_cpu(env);
30
+ nan = float16_silence_nan(a, fpst);
28
CPUClass *cc = CPU_GET_CLASS(cpu);
31
+ }
29
cc->tlb_fill(cpu, addr, size, access_type, MMU_USER_IDX, false,
32
}
33
if (fpst->default_nan_mode) {
34
nan = float16_default_nan(fpst);
35
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
36
float32 nan = a;
37
if (float32_is_signaling_nan(a, fpst)) {
38
float_raise(float_flag_invalid, fpst);
39
- nan = float32_silence_nan(a, fpst);
40
+ if (!fpst->default_nan_mode) {
41
+ nan = float32_silence_nan(a, fpst);
42
+ }
43
}
44
if (fpst->default_nan_mode) {
45
nan = float32_default_nan(fpst);
46
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
47
float64 nan = a;
48
if (float64_is_signaling_nan(a, fpst)) {
49
float_raise(float_flag_invalid, fpst);
50
- nan = float64_silence_nan(a, fpst);
51
+ if (!fpst->default_nan_mode) {
52
+ nan = float64_silence_nan(a, fpst);
53
+ }
54
}
55
if (fpst->default_nan_mode) {
56
nan = float64_default_nan(fpst);
57
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/vfp_helper.c
60
+++ b/target/arm/vfp_helper.c
61
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
62
float16 nan = f16;
63
if (float16_is_signaling_nan(f16, fpst)) {
64
float_raise(float_flag_invalid, fpst);
65
- nan = float16_silence_nan(f16, fpst);
66
+ if (!fpst->default_nan_mode) {
67
+ nan = float16_silence_nan(f16, fpst);
68
+ }
69
}
70
if (fpst->default_nan_mode) {
71
nan = float16_default_nan(fpst);
72
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
73
float32 nan = f32;
74
if (float32_is_signaling_nan(f32, fpst)) {
75
float_raise(float_flag_invalid, fpst);
76
- nan = float32_silence_nan(f32, fpst);
77
+ if (!fpst->default_nan_mode) {
78
+ nan = float32_silence_nan(f32, fpst);
79
+ }
80
}
81
if (fpst->default_nan_mode) {
82
nan = float32_default_nan(fpst);
83
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
84
float64 nan = f64;
85
if (float64_is_signaling_nan(f64, fpst)) {
86
float_raise(float_flag_invalid, fpst);
87
- nan = float64_silence_nan(f64, fpst);
88
+ if (!fpst->default_nan_mode) {
89
+ nan = float64_silence_nan(f64, fpst);
90
+ }
91
}
92
if (fpst->default_nan_mode) {
93
nan = float64_default_nan(fpst);
94
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
95
float16 nan = f16;
96
if (float16_is_signaling_nan(f16, s)) {
97
float_raise(float_flag_invalid, s);
98
- nan = float16_silence_nan(f16, s);
99
+ if (!s->default_nan_mode) {
100
+ nan = float16_silence_nan(f16, fpstp);
101
+ }
102
}
103
if (s->default_nan_mode) {
104
nan = float16_default_nan(s);
105
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
106
float32 nan = f32;
107
if (float32_is_signaling_nan(f32, s)) {
108
float_raise(float_flag_invalid, s);
109
- nan = float32_silence_nan(f32, s);
110
+ if (!s->default_nan_mode) {
111
+ nan = float32_silence_nan(f32, fpstp);
112
+ }
113
}
114
if (s->default_nan_mode) {
115
nan = float32_default_nan(s);
116
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
117
float64 nan = f64;
118
if (float64_is_signaling_nan(f64, s)) {
119
float_raise(float_flag_invalid, s);
120
- nan = float64_silence_nan(f64, s);
121
+ if (!s->default_nan_mode) {
122
+ nan = float64_silence_nan(f64, fpstp);
123
+ }
124
}
125
if (s->default_nan_mode) {
126
nan = float64_default_nan(s);
30
--
127
--
31
2.20.1
128
2.20.1
32
129
33
130
diff view generated by jsdifflib
[PULL 27/34] target/arm/kvm: Inline set_feature() calls
[PULL 06/24] hw/gpio/gpio_pwr: use shutdown function for reboot
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Maxim Uvarov <maxim.uvarov@linaro.org>
2
2
3
We want to move the inlined declarations of set_feature()
3
qemu has 2 type of functions: shutdown and reboot. Shutdown
4
from cpu*.c to cpu.h. To avoid clashing with the KVM
4
function has to be used for machine shutdown. Otherwise we cause
5
declarations, inline the few KVM calls.
5
a reset with a bogus "cause" value, when we intended a shutdown.
6
6
7
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20200504172448.9402-2-philmd@redhat.com
9
Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
10
[PMM: tweaked commit message]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
---
12
target/arm/kvm32.c | 13 ++++---------
13
hw/gpio/gpio_pwr.c | 2 +-
13
target/arm/kvm64.c | 22 ++++++----------------
14
1 file changed, 1 insertion(+), 1 deletion(-)
14
2 files changed, 10 insertions(+), 25 deletions(-)
15
15
16
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
16
diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/kvm32.c
18
--- a/hw/gpio/gpio_pwr.c
19
+++ b/target/arm/kvm32.c
19
+++ b/hw/gpio/gpio_pwr.c
20
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
21
#include "internals.h"
21
static void gpio_pwr_shutdown(void *opaque, int n, int level)
22
#include "qemu/log.h"
23
24
-static inline void set_feature(uint64_t *features, int feature)
25
-{
26
- *features |= 1ULL << feature;
27
-}
28
-
29
static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
30
{
22
{
31
struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
23
if (level) {
32
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
24
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
33
* timers; this in turn implies most of the other feature
25
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
34
* bits, but a few must be tested.
35
*/
36
- set_feature(&features, ARM_FEATURE_V7VE);
37
- set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
38
+ features |= 1ULL << ARM_FEATURE_V7VE;
39
+ features |= 1ULL << ARM_FEATURE_GENERIC_TIMER;
40
41
if (extract32(id_pfr0, 12, 4) == 1) {
42
- set_feature(&features, ARM_FEATURE_THUMB2EE);
43
+ features |= 1ULL << ARM_FEATURE_THUMB2EE;
44
}
45
if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
46
- set_feature(&features, ARM_FEATURE_NEON);
47
+ features |= 1ULL << ARM_FEATURE_NEON;
48
}
49
50
ahcf->features = features;
51
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/kvm64.c
54
+++ b/target/arm/kvm64.c
55
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
56
}
26
}
57
}
27
}
58
28
59
-static inline void set_feature(uint64_t *features, int feature)
60
-{
61
- *features |= 1ULL << feature;
62
-}
63
-
64
-static inline void unset_feature(uint64_t *features, int feature)
65
-{
66
- *features &= ~(1ULL << feature);
67
-}
68
-
69
static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
70
{
71
uint64_t ret;
72
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
73
* with VFPv4+Neon; this in turn implies most of the other
74
* feature bits.
75
*/
76
- set_feature(&features, ARM_FEATURE_V8);
77
- set_feature(&features, ARM_FEATURE_NEON);
78
- set_feature(&features, ARM_FEATURE_AARCH64);
79
- set_feature(&features, ARM_FEATURE_PMU);
80
- set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
81
+ features |= 1ULL << ARM_FEATURE_V8;
82
+ features |= 1ULL << ARM_FEATURE_NEON;
83
+ features |= 1ULL << ARM_FEATURE_AARCH64;
84
+ features |= 1ULL << ARM_FEATURE_PMU;
85
+ features |= 1ULL << ARM_FEATURE_GENERIC_TIMER;
86
87
ahcf->features = features;
88
89
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
90
if (cpu->has_pmu) {
91
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
92
} else {
93
- unset_feature(&env->features, ARM_FEATURE_PMU);
94
+ env->features &= ~(1ULL << ARM_FEATURE_PMU);
95
}
96
if (cpu_isar_feature(aa64_sve, cpu)) {
97
assert(kvm_arm_sve_supported(cs));
98
--
29
--
99
2.20.1
30
2.20.1
100
31
101
32
diff view generated by jsdifflib
[PULL 22/34] target/arm: Use SVEContLdSt for contiguous stores
[PULL 07/24] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In do_ldst(), the calculation of the offset needs to be based on the
2
size of the memory access, not the size of the elements in the
3
vector. This meant we were getting it wrong for the widening and
4
narrowing variants of the various VLDR and VSTR insns.
2
5
3
Follow the model set up for contiguous loads. This handles
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
watchpoints correctly for contiguous stores, recognizing the
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
exception before any changes to memory.
8
Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
9
---
10
target/arm/translate-mve.c | 17 +++++++++--------
11
1 file changed, 9 insertions(+), 8 deletions(-)
6
12
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200508154359.7494-16-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/sve_helper.c | 285 ++++++++++++++++++++++------------------
13
1 file changed, 159 insertions(+), 126 deletions(-)
14
15
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/sve_helper.c
15
--- a/target/arm/translate-mve.c
18
+++ b/target/arm/sve_helper.c
16
+++ b/target/arm/translate-mve.c
19
@@ -XXX,XX +XXX,XX @@ static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
17
@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
20
*(TYPEE *)(vd + H(reg_off)) = val; \
21
}
22
23
+#define DO_ST_HOST(NAME, H, TYPEE, TYPEM, HOST) \
24
+static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
25
+{ HOST(host, (TYPEM)*(TYPEE *)(vd + H(reg_off))); }
26
+
27
#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \
28
static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
29
target_ulong addr, uintptr_t ra) \
30
@@ -XXX,XX +XXX,XX @@ DO_LD_PRIM_1(ld1bdu, , uint64_t, uint8_t)
31
DO_LD_PRIM_1(ld1bds, , uint64_t, int8_t)
32
33
#define DO_ST_PRIM_1(NAME, H, TE, TM) \
34
+ DO_ST_HOST(st1##NAME, H, TE, TM, stb_p) \
35
DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra)
36
37
DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t)
38
@@ -XXX,XX +XXX,XX @@ DO_ST_PRIM_1(bd, , uint64_t, uint8_t)
39
DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra)
40
41
#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \
42
+ DO_ST_HOST(st1##NAME##_be, H, TE, TM, ST##_be_p) \
43
+ DO_ST_HOST(st1##NAME##_le, H, TE, TM, ST##_le_p) \
44
DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \
45
DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra)
46
47
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_LDNF1_2(dd, MO_64, MO_64)
48
#undef DO_LDFF1_LDNF1_2
49
50
/*
51
- * Common helpers for all contiguous 1,2,3,4-register predicated stores.
52
+ * Common helper for all contiguous 1,2,3,4-register predicated stores.
53
*/
54
-static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
55
- uint32_t desc, const uintptr_t ra,
56
- const int esize, const int msize,
57
- sve_ldst1_tlb_fn *tlb_fn)
58
+
59
+static inline QEMU_ALWAYS_INLINE
60
+void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, uint32_t desc,
61
+ const uintptr_t retaddr, const int esz,
62
+ const int msz, const int N,
63
+ sve_ldst1_host_fn *host_fn,
64
+ sve_ldst1_tlb_fn *tlb_fn)
65
{
66
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
67
- intptr_t i, oprsz = simd_oprsz(desc);
68
- void *vd = &env->vfp.zregs[rd];
69
+ const intptr_t reg_max = simd_oprsz(desc);
70
+ intptr_t reg_off, reg_last, mem_off;
71
+ SVEContLdSt info;
72
+ void *host;
73
+ int i, flags;
74
75
- for (i = 0; i < oprsz; ) {
76
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
77
- do {
78
- if (pg & 1) {
79
- tlb_fn(env, vd, i, addr, ra);
80
+ /* Find the active elements. */
81
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, N << msz)) {
82
+ /* The entire predicate was false; no store occurs. */
83
+ return;
84
+ }
85
+
86
+ /* Probe the page(s). Exit with exception for any invalid page. */
87
+ sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_STORE, retaddr);
88
+
89
+ /* Handle watchpoints for all active elements. */
90
+ sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, N << msz,
91
+ BP_MEM_WRITE, retaddr);
92
+
93
+ /* TODO: MTE check. */
94
+
95
+ flags = info.page[0].flags | info.page[1].flags;
96
+ if (unlikely(flags != 0)) {
97
+#ifdef CONFIG_USER_ONLY
98
+ g_assert_not_reached();
99
+#else
100
+ /*
101
+ * At least one page includes MMIO.
102
+ * Any bus operation can fail with cpu_transaction_failed,
103
+ * which for ARM will raise SyncExternal. We cannot avoid
104
+ * this fault and will leave with the store incomplete.
105
+ */
106
+ mem_off = info.mem_off_first[0];
107
+ reg_off = info.reg_off_first[0];
108
+ reg_last = info.reg_off_last[1];
109
+ if (reg_last < 0) {
110
+ reg_last = info.reg_off_split;
111
+ if (reg_last < 0) {
112
+ reg_last = info.reg_off_last[0];
113
}
114
- i += esize, pg >>= esize;
115
- addr += msize;
116
- } while (i & 15);
117
+ }
118
+
119
+ do {
120
+ uint64_t pg = vg[reg_off >> 6];
121
+ do {
122
+ if ((pg >> (reg_off & 63)) & 1) {
123
+ for (i = 0; i < N; ++i) {
124
+ tlb_fn(env, &env->vfp.zregs[(rd + i) & 31], reg_off,
125
+ addr + mem_off + (i << msz), retaddr);
126
+ }
127
+ }
128
+ reg_off += 1 << esz;
129
+ mem_off += N << msz;
130
+ } while (reg_off & 63);
131
+ } while (reg_off <= reg_last);
132
+ return;
133
+#endif
134
+ }
135
+
136
+ mem_off = info.mem_off_first[0];
137
+ reg_off = info.reg_off_first[0];
138
+ reg_last = info.reg_off_last[0];
139
+ host = info.page[0].host;
140
+
141
+ while (reg_off <= reg_last) {
142
+ uint64_t pg = vg[reg_off >> 6];
143
+ do {
144
+ if ((pg >> (reg_off & 63)) & 1) {
145
+ for (i = 0; i < N; ++i) {
146
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
147
+ host + mem_off + (i << msz));
148
+ }
149
+ }
150
+ reg_off += 1 << esz;
151
+ mem_off += N << msz;
152
+ } while (reg_off <= reg_last && (reg_off & 63));
153
+ }
154
+
155
+ /*
156
+ * Use the slow path to manage the cross-page misalignment.
157
+ * But we know this is RAM and cannot trap.
158
+ */
159
+ mem_off = info.mem_off_split;
160
+ if (unlikely(mem_off >= 0)) {
161
+ reg_off = info.reg_off_split;
162
+ for (i = 0; i < N; ++i) {
163
+ tlb_fn(env, &env->vfp.zregs[(rd + i) & 31], reg_off,
164
+ addr + mem_off + (i << msz), retaddr);
165
+ }
166
+ }
167
+
168
+ mem_off = info.mem_off_first[1];
169
+ if (unlikely(mem_off >= 0)) {
170
+ reg_off = info.reg_off_first[1];
171
+ reg_last = info.reg_off_last[1];
172
+ host = info.page[1].host;
173
+
174
+ do {
175
+ uint64_t pg = vg[reg_off >> 6];
176
+ do {
177
+ if ((pg >> (reg_off & 63)) & 1) {
178
+ for (i = 0; i < N; ++i) {
179
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
180
+ host + mem_off + (i << msz));
181
+ }
182
+ }
183
+ reg_off += 1 << esz;
184
+ mem_off += N << msz;
185
+ } while (reg_off & 63);
186
+ } while (reg_off <= reg_last);
187
}
18
}
188
}
19
}
189
20
190
-static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
21
-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
191
- uint32_t desc, const uintptr_t ra,
22
+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
192
- const int esize, const int msize,
23
+ unsigned msize)
193
- sve_ldst1_tlb_fn *tlb_fn)
24
{
194
-{
25
TCGv_i32 addr;
195
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
26
uint32_t offset;
196
- intptr_t i, oprsz = simd_oprsz(desc);
27
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
197
- void *d1 = &env->vfp.zregs[rd];
28
return true;
198
- void *d2 = &env->vfp.zregs[(rd + 1) & 31];
29
}
199
-
30
200
- for (i = 0; i < oprsz; ) {
31
- offset = a->imm << a->size;
201
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
32
+ offset = a->imm << msize;
202
- do {
33
if (!a->a) {
203
- if (pg & 1) {
34
offset = -offset;
204
- tlb_fn(env, d1, i, addr, ra);
35
}
205
- tlb_fn(env, d2, i, addr + msize, ra);
36
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
206
- }
37
{ gen_helper_mve_vstrw, gen_helper_mve_vldrw },
207
- i += esize, pg >>= esize;
38
{ NULL, NULL }
208
- addr += 2 * msize;
39
};
209
- } while (i & 15);
40
- return do_ldst(s, a, ldstfns[a->size][a->l]);
210
- }
41
+ return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
211
-}
212
-
213
-static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
214
- uint32_t desc, const uintptr_t ra,
215
- const int esize, const int msize,
216
- sve_ldst1_tlb_fn *tlb_fn)
217
-{
218
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
219
- intptr_t i, oprsz = simd_oprsz(desc);
220
- void *d1 = &env->vfp.zregs[rd];
221
- void *d2 = &env->vfp.zregs[(rd + 1) & 31];
222
- void *d3 = &env->vfp.zregs[(rd + 2) & 31];
223
-
224
- for (i = 0; i < oprsz; ) {
225
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
226
- do {
227
- if (pg & 1) {
228
- tlb_fn(env, d1, i, addr, ra);
229
- tlb_fn(env, d2, i, addr + msize, ra);
230
- tlb_fn(env, d3, i, addr + 2 * msize, ra);
231
- }
232
- i += esize, pg >>= esize;
233
- addr += 3 * msize;
234
- } while (i & 15);
235
- }
236
-}
237
-
238
-static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
239
- uint32_t desc, const uintptr_t ra,
240
- const int esize, const int msize,
241
- sve_ldst1_tlb_fn *tlb_fn)
242
-{
243
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
244
- intptr_t i, oprsz = simd_oprsz(desc);
245
- void *d1 = &env->vfp.zregs[rd];
246
- void *d2 = &env->vfp.zregs[(rd + 1) & 31];
247
- void *d3 = &env->vfp.zregs[(rd + 2) & 31];
248
- void *d4 = &env->vfp.zregs[(rd + 3) & 31];
249
-
250
- for (i = 0; i < oprsz; ) {
251
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
252
- do {
253
- if (pg & 1) {
254
- tlb_fn(env, d1, i, addr, ra);
255
- tlb_fn(env, d2, i, addr + msize, ra);
256
- tlb_fn(env, d3, i, addr + 2 * msize, ra);
257
- tlb_fn(env, d4, i, addr + 3 * msize, ra);
258
- }
259
- i += esize, pg >>= esize;
260
- addr += 4 * msize;
261
- } while (i & 15);
262
- }
263
-}
264
-
265
-#define DO_STN_1(N, NAME, ESIZE) \
266
-void QEMU_FLATTEN HELPER(sve_st##N##NAME##_r) \
267
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
268
+#define DO_STN_1(N, NAME, ESZ) \
269
+void HELPER(sve_st##N##NAME##_r)(CPUARMState *env, void *vg, \
270
+ target_ulong addr, uint32_t desc) \
271
{ \
272
- sve_st##N##_r(env, vg, addr, desc, GETPC(), ESIZE, 1, \
273
- sve_st1##NAME##_tlb); \
274
+ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, N, \
275
+ sve_st1##NAME##_host, sve_st1##NAME##_tlb); \
276
}
42
}
277
43
278
-#define DO_STN_2(N, NAME, ESIZE, MSIZE) \
44
-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \
279
-void QEMU_FLATTEN HELPER(sve_st##N##NAME##_le_r) \
45
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \
280
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
46
static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \
281
+#define DO_STN_2(N, NAME, ESZ, MSZ) \
47
{ \
282
+void HELPER(sve_st##N##NAME##_le_r)(CPUARMState *env, void *vg, \
48
static MVEGenLdStFn * const ldstfns[2][2] = { \
283
+ target_ulong addr, uint32_t desc) \
49
{ gen_helper_mve_##ST, gen_helper_mve_##SLD }, \
284
{ \
50
{ NULL, gen_helper_mve_##ULD }, \
285
- sve_st##N##_r(env, vg, addr, desc, GETPC(), ESIZE, MSIZE, \
51
}; \
286
- sve_st1##NAME##_le_tlb); \
52
- return do_ldst(s, a, ldstfns[a->u][a->l]); \
287
+ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, \
53
+ return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \
288
+ sve_st1##NAME##_le_host, sve_st1##NAME##_le_tlb); \
54
}
289
} \
55
290
-void QEMU_FLATTEN HELPER(sve_st##N##NAME##_be_r) \
56
-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
291
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
57
-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
292
+void HELPER(sve_st##N##NAME##_be_r)(CPUARMState *env, void *vg, \
58
-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
293
+ target_ulong addr, uint32_t desc) \
59
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
294
{ \
60
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
295
- sve_st##N##_r(env, vg, addr, desc, GETPC(), ESIZE, MSIZE, \
61
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
296
- sve_st1##NAME##_be_tlb); \
62
297
+ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, \
63
static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
298
+ sve_st1##NAME##_be_host, sve_st1##NAME##_be_tlb); \
64
{
299
}
300
301
-DO_STN_1(1, bb, 1)
302
-DO_STN_1(1, bh, 2)
303
-DO_STN_1(1, bs, 4)
304
-DO_STN_1(1, bd, 8)
305
-DO_STN_1(2, bb, 1)
306
-DO_STN_1(3, bb, 1)
307
-DO_STN_1(4, bb, 1)
308
+DO_STN_1(1, bb, MO_8)
309
+DO_STN_1(1, bh, MO_16)
310
+DO_STN_1(1, bs, MO_32)
311
+DO_STN_1(1, bd, MO_64)
312
+DO_STN_1(2, bb, MO_8)
313
+DO_STN_1(3, bb, MO_8)
314
+DO_STN_1(4, bb, MO_8)
315
316
-DO_STN_2(1, hh, 2, 2)
317
-DO_STN_2(1, hs, 4, 2)
318
-DO_STN_2(1, hd, 8, 2)
319
-DO_STN_2(2, hh, 2, 2)
320
-DO_STN_2(3, hh, 2, 2)
321
-DO_STN_2(4, hh, 2, 2)
322
+DO_STN_2(1, hh, MO_16, MO_16)
323
+DO_STN_2(1, hs, MO_32, MO_16)
324
+DO_STN_2(1, hd, MO_64, MO_16)
325
+DO_STN_2(2, hh, MO_16, MO_16)
326
+DO_STN_2(3, hh, MO_16, MO_16)
327
+DO_STN_2(4, hh, MO_16, MO_16)
328
329
-DO_STN_2(1, ss, 4, 4)
330
-DO_STN_2(1, sd, 8, 4)
331
-DO_STN_2(2, ss, 4, 4)
332
-DO_STN_2(3, ss, 4, 4)
333
-DO_STN_2(4, ss, 4, 4)
334
+DO_STN_2(1, ss, MO_32, MO_32)
335
+DO_STN_2(1, sd, MO_64, MO_32)
336
+DO_STN_2(2, ss, MO_32, MO_32)
337
+DO_STN_2(3, ss, MO_32, MO_32)
338
+DO_STN_2(4, ss, MO_32, MO_32)
339
340
-DO_STN_2(1, dd, 8, 8)
341
-DO_STN_2(2, dd, 8, 8)
342
-DO_STN_2(3, dd, 8, 8)
343
-DO_STN_2(4, dd, 8, 8)
344
+DO_STN_2(1, dd, MO_64, MO_64)
345
+DO_STN_2(2, dd, MO_64, MO_64)
346
+DO_STN_2(3, dd, MO_64, MO_64)
347
+DO_STN_2(4, dd, MO_64, MO_64)
348
349
#undef DO_STN_1
350
#undef DO_STN_2
351
--
65
--
352
2.20.1
66
2.20.1
353
67
354
68
diff view generated by jsdifflib
[PULL 17/34] target/arm: Adjust interface of sve_ld1_host_fn
[PULL 08/24] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
2
insns had some bugs:
3
* the 32x32 multiply of elements was being done as 32x32->32,
4
not 32x32->64
5
* we were incorrectly maintaining the accumulator in its full
6
72-bit form across all 4 beats of the insn; in the pseudocode
7
it is squashed back into the 64 bits of the RdaHi:RdaLo
8
registers after each beat
2
9
3
The current interface includes a loop; change it to load a
10
In particular, fixing the second of these allows us to recast
4
single element. We will then be able to use the function
11
the implementation to avoid 128-bit arithmetic entirely.
5
for ld{2,3,4} where individual vector elements are not adjacent.
6
12
7
Replace each call with the simplest possible loop over active
13
Since the element size here is always 4, we can also drop the
8
elements.
14
parameterization of ESIZE to make the code a little more readable.
9
15
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200508154359.7494-11-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
14
---
20
---
15
target/arm/sve_helper.c | 124 ++++++++++++++++++++--------------------
21
target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
16
1 file changed, 63 insertions(+), 61 deletions(-)
22
1 file changed, 21 insertions(+), 17 deletions(-)
17
23
18
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
24
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
19
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/sve_helper.c
26
--- a/target/arm/mve_helper.c
21
+++ b/target/arm/sve_helper.c
27
+++ b/target/arm/mve_helper.c
22
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
28
@@ -XXX,XX +XXX,XX @@
23
*/
29
*/
24
30
31
#include "qemu/osdep.h"
32
-#include "qemu/int128.h"
33
#include "cpu.h"
34
#include "internals.h"
35
#include "vec_internal.h"
36
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
37
DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
38
25
/*
39
/*
26
- * Load elements into @vd, controlled by @vg, from @host + @mem_ofs.
40
- * Rounding multiply add long dual accumulate high: we must keep
27
- * Memory is valid through @host + @mem_max. The register element
41
- * a 72-bit internal accumulator value and return the top 64 bits.
28
- * indices are inferred from @mem_ofs, as modified by the types for
42
+ * Rounding multiply add long dual accumulate high. In the pseudocode
29
- * which the helper is built. Return the @mem_ofs of the first element
43
+ * this is implemented with a 72-bit internal accumulator value of which
30
- * not loaded (which is @mem_max if they are all loaded).
44
+ * the top 64 bits are returned. We optimize this to avoid having to
31
- *
45
+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
32
- * For softmmu, we have fully validated the guest page. For user-only,
46
+ * is squashed back into 64-bits after each beat.
33
- * we cannot fully validate without taking the mmap lock, but since we
34
- * know the access is within one host page, if any access is valid they
35
- * all must be valid. However, when @vg is all false, it may be that
36
- * no access is valid.
37
+ * Load one element into @vd + @reg_off from @host.
38
+ * The controlling predicate is known to be true.
39
*/
47
*/
40
-typedef intptr_t sve_ld1_host_fn(void *vd, void *vg, void *host,
48
-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \
41
- intptr_t mem_ofs, intptr_t mem_max);
49
+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \
42
+typedef void sve_ldst1_host_fn(void *vd, intptr_t reg_off, void *host);
50
uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
43
51
void *vm, uint64_t a) \
44
/*
52
{ \
45
* Load one element into @vd + @reg_off from (@env, @vaddr, @ra).
53
uint16_t mask = mve_element_mask(env); \
46
@@ -XXX,XX +XXX,XX @@ typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
54
unsigned e; \
47
*/
55
TYPE *n = vn, *m = vm; \
48
56
- Int128 acc = int128_lshift(TO128(a), 8); \
49
#define DO_LD_HOST(NAME, H, TYPEE, TYPEM, HOST) \
57
- for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
50
-static intptr_t sve_##NAME##_host(void *vd, void *vg, void *host, \
58
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
51
- intptr_t mem_off, const intptr_t mem_max) \
59
if (mask & 1) { \
52
-{ \
60
+ LTYPE mul; \
53
- intptr_t reg_off = mem_off * (sizeof(TYPEE) / sizeof(TYPEM)); \
61
if (e & 1) { \
54
- uint64_t *pg = vg; \
62
- acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
55
- while (mem_off + sizeof(TYPEM) <= mem_max) { \
63
- m[H##ESIZE(e)])); \
56
- TYPEM val = 0; \
64
+ mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \
57
- if (likely((pg[reg_off >> 6] >> (reg_off & 63)) & 1)) { \
65
+ if (SUB) { \
58
- val = HOST(host + mem_off); \
66
+ mul = -mul; \
59
- } \
67
+ } \
60
- *(TYPEE *)(vd + H(reg_off)) = val; \
68
} else { \
61
- mem_off += sizeof(TYPEM), reg_off += sizeof(TYPEE); \
69
- acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
62
- } \
70
- m[H##ESIZE(e)])); \
63
- return mem_off; \
71
+ mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \
64
+static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
72
} \
65
+{ \
73
- acc = int128_add(acc, int128_make64(1 << 7)); \
66
+ TYPEM val = HOST(host); \
74
+ mul = (mul >> 8) + ((mul >> 7) & 1); \
67
+ *(TYPEE *)(vd + H(reg_off)) = val; \
75
+ a += mul; \
68
}
76
} \
69
77
} \
70
#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \
78
mve_advance_vpt(env); \
71
@@ -XXX,XX +XXX,XX @@ static inline bool test_host_page(void *host)
79
- return int128_getlo(int128_rshift(acc, 8)); \
72
static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
80
+ return a; \
73
uint32_t desc, const uintptr_t retaddr,
74
const int esz, const int msz,
75
- sve_ld1_host_fn *host_fn,
76
+ sve_ldst1_host_fn *host_fn,
77
sve_ldst1_tlb_fn *tlb_fn)
78
{
79
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
80
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
81
if (likely(split == mem_max)) {
82
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
83
if (test_host_page(host)) {
84
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
85
- tcg_debug_assert(mem_off == mem_max);
86
+ intptr_t i = reg_off;
87
+ host -= mem_off;
88
+ do {
89
+ host_fn(vd, i, host + (i >> diffsz));
90
+ i = find_next_active(vg, i + (1 << esz), reg_max, esz);
91
+ } while (i < reg_max);
92
/* After having taken any fault, zero leading inactive elements. */
93
swap_memzero(vd, reg_off);
94
return;
95
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
96
*/
97
#ifdef CONFIG_USER_ONLY
98
swap_memzero(&scratch, reg_off);
99
- host_fn(&scratch, vg, g2h(addr), mem_off, mem_max);
100
+ host = g2h(addr);
101
+ do {
102
+ host_fn(&scratch, reg_off, host + (reg_off >> diffsz));
103
+ reg_off += 1 << esz;
104
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
105
+ } while (reg_off < reg_max);
106
#else
107
memset(&scratch, 0, reg_max);
108
goto start;
109
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
110
host = tlb_vaddr_to_host(env, addr + mem_off,
111
MMU_DATA_LOAD, mmu_idx);
112
if (host) {
113
- mem_off = host_fn(&scratch, vg, host - mem_off,
114
- mem_off, split);
115
- reg_off = mem_off << diffsz;
116
+ host -= mem_off;
117
+ do {
118
+ host_fn(&scratch, reg_off, host + mem_off);
119
+ reg_off += 1 << esz;
120
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
121
+ mem_off = reg_off >> diffsz;
122
+ } while (split - mem_off >= (1 << msz));
123
continue;
124
}
125
}
126
@@ -XXX,XX +XXX,XX @@ static void record_fault(CPUARMState *env, uintptr_t i, uintptr_t oprsz)
127
static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
128
uint32_t desc, const uintptr_t retaddr,
129
const int esz, const int msz,
130
- sve_ld1_host_fn *host_fn,
131
+ sve_ldst1_host_fn *host_fn,
132
sve_ldst1_tlb_fn *tlb_fn)
133
{
134
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
135
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
136
const int diffsz = esz - msz;
137
const intptr_t reg_max = simd_oprsz(desc);
138
const intptr_t mem_max = reg_max >> diffsz;
139
- intptr_t split, reg_off, mem_off;
140
+ intptr_t split, reg_off, mem_off, i;
141
void *host;
142
143
/* Skip to the first active element. */
144
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
145
if (likely(split == mem_max)) {
146
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
147
if (test_host_page(host)) {
148
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
149
- tcg_debug_assert(mem_off == mem_max);
150
+ i = reg_off;
151
+ host -= mem_off;
152
+ do {
153
+ host_fn(vd, i, host + (i >> diffsz));
154
+ i = find_next_active(vg, i + (1 << esz), reg_max, esz);
155
+ } while (i < reg_max);
156
/* After any fault, zero any leading inactive elements. */
157
swap_memzero(vd, reg_off);
158
return;
159
}
160
}
81
}
161
82
162
-#ifdef CONFIG_USER_ONLY
83
-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
163
- /*
84
-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
164
- * The page(s) containing this first element at ADDR+MEM_OFF must
85
+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
165
- * be valid. Considering that this first element may be misaligned
86
+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
166
- * and cross a page boundary itself, take the rest of the page from
87
167
- * the last byte of the element.
88
-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
168
- */
89
+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
169
- split = max_for_page(addr, mem_off + (1 << msz) - 1, mem_max);
90
170
- mem_off = host_fn(vd, vg, g2h(addr), mem_off, split);
91
-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
171
-
92
-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
172
- /* After any fault, zero any leading inactive elements. */
93
+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
173
- swap_memzero(vd, reg_off);
94
+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
174
- reg_off = mem_off << diffsz;
95
175
-#else
96
/* Vector add across vector */
176
/*
97
#define DO_VADDV(OP, ESIZE, TYPE) \
177
* Perform one normal read, which will fault or not.
178
* But it is likely to bring the page into the tlb.
179
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
180
if (split >= (1 << msz)) {
181
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
182
if (host) {
183
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, split);
184
- reg_off = mem_off << diffsz;
185
+ host -= mem_off;
186
+ do {
187
+ host_fn(vd, reg_off, host + mem_off);
188
+ reg_off += 1 << esz;
189
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
190
+ mem_off = reg_off >> diffsz;
191
+ } while (split - mem_off >= (1 << msz));
192
}
193
}
194
-#endif
195
196
record_fault(env, reg_off, reg_max);
197
}
198
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
199
*/
200
static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
201
uint32_t desc, const int esz, const int msz,
202
- sve_ld1_host_fn *host_fn)
203
+ sve_ldst1_host_fn *host_fn)
204
{
205
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
206
void *vd = &env->vfp.zregs[rd];
207
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
208
host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_idx);
209
if (likely(page_check_range(addr, mem_max, PAGE_READ) == 0)) {
210
/* The entire operation is valid and will not fault. */
211
- host_fn(vd, vg, host, 0, mem_max);
212
+ reg_off = 0;
213
+ do {
214
+ mem_off = reg_off >> diffsz;
215
+ host_fn(vd, reg_off, host + mem_off);
216
+ reg_off += 1 << esz;
217
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
218
+ } while (reg_off < reg_max);
219
return;
220
}
221
#endif
222
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
223
if (page_check_range(addr + mem_off, 1 << msz, PAGE_READ) == 0) {
224
/* At least one load is valid; take the rest of the page. */
225
split = max_for_page(addr, mem_off + (1 << msz) - 1, mem_max);
226
- mem_off = host_fn(vd, vg, host, mem_off, split);
227
- reg_off = mem_off << diffsz;
228
+ do {
229
+ host_fn(vd, reg_off, host + mem_off);
230
+ reg_off += 1 << esz;
231
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
232
+ mem_off = reg_off >> diffsz;
233
+ } while (split - mem_off >= (1 << msz));
234
}
235
#else
236
/*
237
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
238
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
239
split = max_for_page(addr, mem_off, mem_max);
240
if (host && split >= (1 << msz)) {
241
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, split);
242
- reg_off = mem_off << diffsz;
243
+ host -= mem_off;
244
+ do {
245
+ host_fn(vd, reg_off, host + mem_off);
246
+ reg_off += 1 << esz;
247
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
248
+ mem_off = reg_off >> diffsz;
249
+ } while (split - mem_off >= (1 << msz));
250
}
251
#endif
252
253
--
98
--
254
2.20.1
99
2.20.1
255
100
256
101
diff view generated by jsdifflib
[PULL 21/34] target/arm: Update contiguous first-fault and no-fault loads
[PULL 09/24] target/arm: Make asimd_imm_const() public
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The function asimd_imm_const() in translate-neon.c is an
2
implementation of the pseudocode AdvSIMDExpandImm(), which we will
3
also want for MVE. Move the implementation to translate.c, with a
4
prototype in translate.h.
2
5
3
With sve_cont_ldst_pages, the differences between first-fault and no-fault
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
are minimal, so unify the routines. With cpu_probe_watchpoint, we are able
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
to make progress through pages with TLB_WATCHPOINT set when the watchpoint
8
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
6
does not actually fire.
9
---
10
target/arm/translate.h | 16 ++++++++++
11
target/arm/translate-neon.c | 63 -------------------------------------
12
target/arm/translate.c | 57 +++++++++++++++++++++++++++++++++
13
3 files changed, 73 insertions(+), 63 deletions(-)
7
14
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-15-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/sve_helper.c | 346 +++++++++++++++++++---------------------
14
1 file changed, 162 insertions(+), 184 deletions(-)
15
16
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sve_helper.c
17
--- a/target/arm/translate.h
19
+++ b/target/arm/sve_helper.c
18
+++ b/target/arm/translate.h
20
@@ -XXX,XX +XXX,XX @@ static intptr_t find_next_active(uint64_t *vg, intptr_t reg_off,
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
21
return reg_off;
20
return opc | s->be_data;
22
}
21
}
23
22
24
-/*
23
+/**
25
- * Return the maximum offset <= @mem_max which is still within the page
24
+ * asimd_imm_const: Expand an encoded SIMD constant value
26
- * referenced by @base + @mem_off.
25
+ *
27
- */
26
+ * Expand a SIMD constant value. This is essentially the pseudocode
28
-static intptr_t max_for_page(target_ulong base, intptr_t mem_off,
27
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
29
- intptr_t mem_max)
28
+ * VMVN and VBIC (when cmode < 14 && op == 1).
29
+ *
30
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
31
+ * callers must catch this.
32
+ *
33
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
34
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
35
+ * we produce an immediate constant value of 0 in these cases.
36
+ */
37
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
38
+
39
#endif /* TARGET_ARM_TRANSLATE_H */
40
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/translate-neon.c
43
+++ b/target/arm/translate-neon.c
44
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
45
DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
46
DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
47
48
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
30
-{
49
-{
31
- target_ulong addr = base + mem_off;
50
- /*
32
- intptr_t split = -(intptr_t)(addr | TARGET_PAGE_MASK);
51
- * Expand the encoded constant.
33
- return MIN(split, mem_max - mem_off) + mem_off;
52
- * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
53
- * We choose to not special-case this and will behave as if a
54
- * valid constant encoding of 0 had been given.
55
- * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
56
- */
57
- switch (cmode) {
58
- case 0: case 1:
59
- /* no-op */
60
- break;
61
- case 2: case 3:
62
- imm <<= 8;
63
- break;
64
- case 4: case 5:
65
- imm <<= 16;
66
- break;
67
- case 6: case 7:
68
- imm <<= 24;
69
- break;
70
- case 8: case 9:
71
- imm |= imm << 16;
72
- break;
73
- case 10: case 11:
74
- imm = (imm << 8) | (imm << 24);
75
- break;
76
- case 12:
77
- imm = (imm << 8) | 0xff;
78
- break;
79
- case 13:
80
- imm = (imm << 16) | 0xffff;
81
- break;
82
- case 14:
83
- if (op) {
84
- /*
85
- * This is the only case where the top and bottom 32 bits
86
- * of the encoded constant differ.
87
- */
88
- uint64_t imm64 = 0;
89
- int n;
90
-
91
- for (n = 0; n < 8; n++) {
92
- if (imm & (1 << n)) {
93
- imm64 |= (0xffULL << (n * 8));
94
- }
95
- }
96
- return imm64;
97
- }
98
- imm |= (imm << 8) | (imm << 16) | (imm << 24);
99
- break;
100
- case 15:
101
- imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
102
- | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
103
- break;
104
- }
105
- if (op) {
106
- imm = ~imm;
107
- }
108
- return dup_const(MO_32, imm);
34
-}
109
-}
35
-
110
-
36
/*
111
static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
37
* Resolve the guest virtual address to info->host and info->flags.
112
GVecGen2iFn *fn)
38
* If @nofault, return false if the page is invalid, otherwise
113
{
39
@@ -XXX,XX +XXX,XX @@ static void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env,
114
diff --git a/target/arm/translate.c b/target/arm/translate.c
40
#endif
115
index XXXXXXX..XXXXXXX 100644
116
--- a/target/arm/translate.c
117
+++ b/target/arm/translate.c
118
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
119
a64_translate_init();
41
}
120
}
42
121
43
-/*
122
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
44
- * The result of tlb_vaddr_to_host for user-only is just g2h(x),
123
+{
45
- * which is always non-null. Elide the useless test.
124
+ /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
46
- */
125
+ switch (cmode) {
47
-static inline bool test_host_page(void *host)
126
+ case 0: case 1:
48
-{
127
+ /* no-op */
49
-#ifdef CONFIG_USER_ONLY
128
+ break;
50
- return true;
129
+ case 2: case 3:
51
-#else
130
+ imm <<= 8;
52
- return likely(host != NULL);
131
+ break;
53
-#endif
132
+ case 4: case 5:
54
-}
133
+ imm <<= 16;
55
-
134
+ break;
56
/*
135
+ case 6: case 7:
57
* Common helper for all contiguous 1,2,3,4-register predicated stores.
136
+ imm <<= 24;
58
*/
137
+ break;
59
@@ -XXX,XX +XXX,XX @@ static void record_fault(CPUARMState *env, uintptr_t i, uintptr_t oprsz)
138
+ case 8: case 9:
60
}
139
+ imm |= imm << 16;
61
140
+ break;
62
/*
141
+ case 10: case 11:
63
- * Common helper for all contiguous first-fault loads.
142
+ imm = (imm << 8) | (imm << 24);
64
+ * Common helper for all contiguous no-fault and first-fault loads.
143
+ break;
65
*/
144
+ case 12:
66
-static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
145
+ imm = (imm << 8) | 0xff;
67
- uint32_t desc, const uintptr_t retaddr,
146
+ break;
68
- const int esz, const int msz,
147
+ case 13:
69
- sve_ldst1_host_fn *host_fn,
148
+ imm = (imm << 16) | 0xffff;
70
- sve_ldst1_tlb_fn *tlb_fn)
149
+ break;
71
+static inline QEMU_ALWAYS_INLINE
150
+ case 14:
72
+void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
151
+ if (op) {
73
+ uint32_t desc, const uintptr_t retaddr,
152
+ /*
74
+ const int esz, const int msz, const SVEContFault fault,
153
+ * This is the only case where the top and bottom 32 bits
75
+ sve_ldst1_host_fn *host_fn,
154
+ * of the encoded constant differ.
76
+ sve_ldst1_tlb_fn *tlb_fn)
155
+ */
156
+ uint64_t imm64 = 0;
157
+ int n;
158
+
159
+ for (n = 0; n < 8; n++) {
160
+ if (imm & (1 << n)) {
161
+ imm64 |= (0xffULL << (n * 8));
162
+ }
163
+ }
164
+ return imm64;
165
+ }
166
+ imm |= (imm << 8) | (imm << 16) | (imm << 24);
167
+ break;
168
+ case 15:
169
+ imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
170
+ | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
171
+ break;
172
+ }
173
+ if (op) {
174
+ imm = ~imm;
175
+ }
176
+ return dup_const(MO_32, imm);
177
+}
178
+
179
/* Generate a label used for skipping this instruction */
180
void arm_gen_condlabel(DisasContext *s)
77
{
181
{
78
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
79
- const int mmu_idx = get_mmuidx(oi);
80
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
81
void *vd = &env->vfp.zregs[rd];
82
- const int diffsz = esz - msz;
83
const intptr_t reg_max = simd_oprsz(desc);
84
- const intptr_t mem_max = reg_max >> diffsz;
85
- intptr_t split, reg_off, mem_off, i;
86
+ intptr_t reg_off, mem_off, reg_last;
87
+ SVEContLdSt info;
88
+ int flags;
89
void *host;
90
91
- /* Skip to the first active element. */
92
- reg_off = find_next_active(vg, 0, reg_max, esz);
93
- if (unlikely(reg_off == reg_max)) {
94
+ /* Find the active elements. */
95
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, 1 << msz)) {
96
/* The entire predicate was false; no load occurs. */
97
memset(vd, 0, reg_max);
98
return;
99
}
100
- mem_off = reg_off >> diffsz;
101
+ reg_off = info.reg_off_first[0];
102
103
- /*
104
- * If the (remaining) load is entirely within a single page, then:
105
- * For softmmu, and the tlb hits, then no faults will occur;
106
- * For user-only, either the first load will fault or none will.
107
- * We can thus perform the load directly to the destination and
108
- * Vd will be unmodified on any exception path.
109
- */
110
- split = max_for_page(addr, mem_off, mem_max);
111
- if (likely(split == mem_max)) {
112
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
113
- if (test_host_page(host)) {
114
- i = reg_off;
115
- host -= mem_off;
116
- do {
117
- host_fn(vd, i, host + (i >> diffsz));
118
- i = find_next_active(vg, i + (1 << esz), reg_max, esz);
119
- } while (i < reg_max);
120
- /* After any fault, zero any leading inactive elements. */
121
+ /* Probe the page(s). */
122
+ if (!sve_cont_ldst_pages(&info, fault, env, addr, MMU_DATA_LOAD, retaddr)) {
123
+ /* Fault on first element. */
124
+ tcg_debug_assert(fault == FAULT_NO);
125
+ memset(vd, 0, reg_max);
126
+ goto do_fault;
127
+ }
128
+
129
+ mem_off = info.mem_off_first[0];
130
+ flags = info.page[0].flags;
131
+
132
+ if (fault == FAULT_FIRST) {
133
+ /*
134
+ * Special handling of the first active element,
135
+ * if it crosses a page boundary or is MMIO.
136
+ */
137
+ bool is_split = mem_off == info.mem_off_split;
138
+ /* TODO: MTE check. */
139
+ if (unlikely(flags != 0) || unlikely(is_split)) {
140
+ /*
141
+ * Use the slow path for cross-page handling.
142
+ * Might trap for MMIO or watchpoints.
143
+ */
144
+ tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
145
+
146
+ /* After any fault, zero the other elements. */
147
swap_memzero(vd, reg_off);
148
- return;
149
+ reg_off += 1 << esz;
150
+ mem_off += 1 << msz;
151
+ swap_memzero(vd + reg_off, reg_max - reg_off);
152
+
153
+ if (is_split) {
154
+ goto second_page;
155
+ }
156
+ } else {
157
+ memset(vd, 0, reg_max);
158
+ }
159
+ } else {
160
+ memset(vd, 0, reg_max);
161
+ if (unlikely(mem_off == info.mem_off_split)) {
162
+ /* The first active element crosses a page boundary. */
163
+ flags |= info.page[1].flags;
164
+ if (unlikely(flags & TLB_MMIO)) {
165
+ /* Some page is MMIO, see below. */
166
+ goto do_fault;
167
+ }
168
+ if (unlikely(flags & TLB_WATCHPOINT) &&
169
+ (cpu_watchpoint_address_matches
170
+ (env_cpu(env), addr + mem_off, 1 << msz)
171
+ & BP_MEM_READ)) {
172
+ /* Watchpoint hit, see below. */
173
+ goto do_fault;
174
+ }
175
+ /* TODO: MTE check. */
176
+ /*
177
+ * Use the slow path for cross-page handling.
178
+ * This is RAM, without a watchpoint, and will not trap.
179
+ */
180
+ tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
181
+ goto second_page;
182
}
183
}
184
185
/*
186
- * Perform one normal read, which will fault or not.
187
- * But it is likely to bring the page into the tlb.
188
+ * From this point on, all memory operations are MemSingleNF.
189
+ *
190
+ * Per the MemSingleNF pseudocode, a no-fault load from Device memory
191
+ * must not actually hit the bus -- it returns (UNKNOWN, FAULT) instead.
192
+ *
193
+ * Unfortuately we do not have access to the memory attributes from the
194
+ * PTE to tell Device memory from Normal memory. So we make a mostly
195
+ * correct check, and indicate (UNKNOWN, FAULT) for any MMIO.
196
+ * This gives the right answer for the common cases of "Normal memory,
197
+ * backed by host RAM" and "Device memory, backed by MMIO".
198
+ * The architecture allows us to suppress an NF load and return
199
+ * (UNKNOWN, FAULT) for any reason, so our behaviour for the corner
200
+ * case of "Normal memory, backed by MMIO" is permitted. The case we
201
+ * get wrong is "Device memory, backed by host RAM", for which we
202
+ * should return (UNKNOWN, FAULT) for but do not.
203
+ *
204
+ * Similarly, CPU_BP breakpoints would raise exceptions, and so
205
+ * return (UNKNOWN, FAULT). For simplicity, we consider gdb and
206
+ * architectural breakpoints the same.
207
*/
208
- tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
209
+ if (unlikely(flags & TLB_MMIO)) {
210
+ goto do_fault;
211
+ }
212
213
- /* After any fault, zero any leading predicated false elts. */
214
- swap_memzero(vd, reg_off);
215
- mem_off += 1 << msz;
216
- reg_off += 1 << esz;
217
+ reg_last = info.reg_off_last[0];
218
+ host = info.page[0].host;
219
220
- /* Try again to read the balance of the page. */
221
- split = max_for_page(addr, mem_off - 1, mem_max);
222
- if (split >= (1 << msz)) {
223
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
224
- if (host) {
225
- host -= mem_off;
226
- do {
227
+ do {
228
+ uint64_t pg = *(uint64_t *)(vg + (reg_off >> 3));
229
+ do {
230
+ if ((pg >> (reg_off & 63)) & 1) {
231
+ if (unlikely(flags & TLB_WATCHPOINT) &&
232
+ (cpu_watchpoint_address_matches
233
+ (env_cpu(env), addr + mem_off, 1 << msz)
234
+ & BP_MEM_READ)) {
235
+ goto do_fault;
236
+ }
237
+ /* TODO: MTE check. */
238
host_fn(vd, reg_off, host + mem_off);
239
- reg_off += 1 << esz;
240
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
241
- mem_off = reg_off >> diffsz;
242
- } while (split - mem_off >= (1 << msz));
243
- }
244
- }
245
-
246
- record_fault(env, reg_off, reg_max);
247
-}
248
-
249
-/*
250
- * Common helper for all contiguous no-fault loads.
251
- */
252
-static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
253
- uint32_t desc, const int esz, const int msz,
254
- sve_ldst1_host_fn *host_fn)
255
-{
256
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
257
- void *vd = &env->vfp.zregs[rd];
258
- const int diffsz = esz - msz;
259
- const intptr_t reg_max = simd_oprsz(desc);
260
- const intptr_t mem_max = reg_max >> diffsz;
261
- const int mmu_idx = cpu_mmu_index(env, false);
262
- intptr_t split, reg_off, mem_off;
263
- void *host;
264
-
265
-#ifdef CONFIG_USER_ONLY
266
- host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_idx);
267
- if (likely(page_check_range(addr, mem_max, PAGE_READ) == 0)) {
268
- /* The entire operation is valid and will not fault. */
269
- reg_off = 0;
270
- do {
271
- mem_off = reg_off >> diffsz;
272
- host_fn(vd, reg_off, host + mem_off);
273
+ }
274
reg_off += 1 << esz;
275
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
276
- } while (reg_off < reg_max);
277
- return;
278
- }
279
-#endif
280
+ mem_off += 1 << msz;
281
+ } while (reg_off <= reg_last && (reg_off & 63));
282
+ } while (reg_off <= reg_last);
283
284
- /* There will be no fault, so we may modify in advance. */
285
- memset(vd, 0, reg_max);
286
-
287
- /* Skip to the first active element. */
288
- reg_off = find_next_active(vg, 0, reg_max, esz);
289
- if (unlikely(reg_off == reg_max)) {
290
- /* The entire predicate was false; no load occurs. */
291
- return;
292
- }
293
- mem_off = reg_off >> diffsz;
294
-
295
-#ifdef CONFIG_USER_ONLY
296
- if (page_check_range(addr + mem_off, 1 << msz, PAGE_READ) == 0) {
297
- /* At least one load is valid; take the rest of the page. */
298
- split = max_for_page(addr, mem_off + (1 << msz) - 1, mem_max);
299
- do {
300
- host_fn(vd, reg_off, host + mem_off);
301
- reg_off += 1 << esz;
302
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
303
- mem_off = reg_off >> diffsz;
304
- } while (split - mem_off >= (1 << msz));
305
- }
306
-#else
307
/*
308
- * If the address is not in the TLB, we have no way to bring the
309
- * entry into the TLB without also risking a fault. Note that
310
- * the corollary is that we never load from an address not in RAM.
311
- *
312
- * This last is out of spec, in a weird corner case.
313
- * Per the MemNF/MemSingleNF pseudocode, a NF load from Device memory
314
- * must not actually hit the bus -- it returns UNKNOWN data instead.
315
- * But if you map non-RAM with Normal memory attributes and do a NF
316
- * load then it should access the bus. (Nobody ought actually do this
317
- * in the real world, obviously.)
318
- *
319
- * Then there are the annoying special cases with watchpoints...
320
- * TODO: Add a form of non-faulting loads using cc->tlb_fill(probe=true).
321
+ * MemSingleNF is allowed to fail for any reason. We have special
322
+ * code above to handle the first element crossing a page boundary.
323
+ * As an implementation choice, decline to handle a cross-page element
324
+ * in any other position.
325
*/
326
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
327
- split = max_for_page(addr, mem_off, mem_max);
328
- if (host && split >= (1 << msz)) {
329
- host -= mem_off;
330
- do {
331
- host_fn(vd, reg_off, host + mem_off);
332
- reg_off += 1 << esz;
333
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
334
- mem_off = reg_off >> diffsz;
335
- } while (split - mem_off >= (1 << msz));
336
+ reg_off = info.reg_off_split;
337
+ if (reg_off >= 0) {
338
+ goto do_fault;
339
}
340
-#endif
341
342
+ second_page:
343
+ reg_off = info.reg_off_first[1];
344
+ if (likely(reg_off < 0)) {
345
+ /* No active elements on the second page. All done. */
346
+ return;
347
+ }
348
+
349
+ /*
350
+ * MemSingleNF is allowed to fail for any reason. As an implementation
351
+ * choice, decline to handle elements on the second page. This should
352
+ * be low frequency as the guest walks through memory -- the next
353
+ * iteration of the guest's loop should be aligned on the page boundary,
354
+ * and then all following iterations will stay aligned.
355
+ */
356
+
357
+ do_fault:
358
record_fault(env, reg_off, reg_max);
359
}
360
361
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
362
void HELPER(sve_ldff1##PART##_r)(CPUARMState *env, void *vg, \
363
target_ulong addr, uint32_t desc) \
364
{ \
365
- sve_ldff1_r(env, vg, addr, desc, GETPC(), ESZ, 0, \
366
- sve_ld1##PART##_host, sve_ld1##PART##_tlb); \
367
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, FAULT_FIRST, \
368
+ sve_ld1##PART##_host, sve_ld1##PART##_tlb); \
369
} \
370
void HELPER(sve_ldnf1##PART##_r)(CPUARMState *env, void *vg, \
371
target_ulong addr, uint32_t desc) \
372
{ \
373
- sve_ldnf1_r(env, vg, addr, desc, ESZ, 0, sve_ld1##PART##_host); \
374
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, FAULT_NO, \
375
+ sve_ld1##PART##_host, sve_ld1##PART##_tlb); \
376
}
377
378
#define DO_LDFF1_LDNF1_2(PART, ESZ, MSZ) \
379
void HELPER(sve_ldff1##PART##_le_r)(CPUARMState *env, void *vg, \
380
target_ulong addr, uint32_t desc) \
381
{ \
382
- sve_ldff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
383
- sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \
384
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_FIRST, \
385
+ sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \
386
} \
387
void HELPER(sve_ldnf1##PART##_le_r)(CPUARMState *env, void *vg, \
388
target_ulong addr, uint32_t desc) \
389
{ \
390
- sve_ldnf1_r(env, vg, addr, desc, ESZ, MSZ, sve_ld1##PART##_le_host); \
391
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_NO, \
392
+ sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \
393
} \
394
void HELPER(sve_ldff1##PART##_be_r)(CPUARMState *env, void *vg, \
395
target_ulong addr, uint32_t desc) \
396
{ \
397
- sve_ldff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
398
- sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \
399
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_FIRST, \
400
+ sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \
401
} \
402
void HELPER(sve_ldnf1##PART##_be_r)(CPUARMState *env, void *vg, \
403
target_ulong addr, uint32_t desc) \
404
{ \
405
- sve_ldnf1_r(env, vg, addr, desc, ESZ, MSZ, sve_ld1##PART##_be_host); \
406
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_NO, \
407
+ sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \
408
}
409
410
-DO_LDFF1_LDNF1_1(bb, 0)
411
-DO_LDFF1_LDNF1_1(bhu, 1)
412
-DO_LDFF1_LDNF1_1(bhs, 1)
413
-DO_LDFF1_LDNF1_1(bsu, 2)
414
-DO_LDFF1_LDNF1_1(bss, 2)
415
-DO_LDFF1_LDNF1_1(bdu, 3)
416
-DO_LDFF1_LDNF1_1(bds, 3)
417
+DO_LDFF1_LDNF1_1(bb, MO_8)
418
+DO_LDFF1_LDNF1_1(bhu, MO_16)
419
+DO_LDFF1_LDNF1_1(bhs, MO_16)
420
+DO_LDFF1_LDNF1_1(bsu, MO_32)
421
+DO_LDFF1_LDNF1_1(bss, MO_32)
422
+DO_LDFF1_LDNF1_1(bdu, MO_64)
423
+DO_LDFF1_LDNF1_1(bds, MO_64)
424
425
-DO_LDFF1_LDNF1_2(hh, 1, 1)
426
-DO_LDFF1_LDNF1_2(hsu, 2, 1)
427
-DO_LDFF1_LDNF1_2(hss, 2, 1)
428
-DO_LDFF1_LDNF1_2(hdu, 3, 1)
429
-DO_LDFF1_LDNF1_2(hds, 3, 1)
430
+DO_LDFF1_LDNF1_2(hh, MO_16, MO_16)
431
+DO_LDFF1_LDNF1_2(hsu, MO_32, MO_16)
432
+DO_LDFF1_LDNF1_2(hss, MO_32, MO_16)
433
+DO_LDFF1_LDNF1_2(hdu, MO_64, MO_16)
434
+DO_LDFF1_LDNF1_2(hds, MO_64, MO_16)
435
436
-DO_LDFF1_LDNF1_2(ss, 2, 2)
437
-DO_LDFF1_LDNF1_2(sdu, 3, 2)
438
-DO_LDFF1_LDNF1_2(sds, 3, 2)
439
+DO_LDFF1_LDNF1_2(ss, MO_32, MO_32)
440
+DO_LDFF1_LDNF1_2(sdu, MO_64, MO_32)
441
+DO_LDFF1_LDNF1_2(sds, MO_64, MO_32)
442
443
-DO_LDFF1_LDNF1_2(dd, 3, 3)
444
+DO_LDFF1_LDNF1_2(dd, MO_64, MO_64)
445
446
#undef DO_LDFF1_LDNF1_1
447
#undef DO_LDFF1_LDNF1_2
448
--
182
--
449
2.20.1
183
2.20.1
450
184
451
185
diff view generated by jsdifflib
[PULL 20/34] target/arm: Use SVEContLdSt for multi-register contiguous loads
[PULL 10/24] target/arm: Use asimd_imm_const for A64 decode
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The A64 AdvSIMD modified-immediate grouping uses almost the same
2
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
3
which we add the AArch64-specific case for cmode 15 op 1) instead of
4
reimplementing it all.
2
5
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200508154359.7494-14-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
7
---
9
---
8
target/arm/sve_helper.c | 223 ++++++++++++++--------------------------
10
target/arm/translate.h | 3 +-
9
1 file changed, 79 insertions(+), 144 deletions(-)
11
target/arm/translate-a64.c | 86 ++++----------------------------------
12
target/arm/translate.c | 17 +++++++-
13
3 files changed, 24 insertions(+), 82 deletions(-)
10
14
11
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/sve_helper.c
17
--- a/target/arm/translate.h
14
+++ b/target/arm/sve_helper.c
18
+++ b/target/arm/translate.h
15
@@ -XXX,XX +XXX,XX @@ static inline bool test_host_page(void *host)
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
16
}
20
* VMVN and VBIC (when cmode < 14 && op == 1).
17
21
*
18
/*
22
* The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
19
- * Common helper for all contiguous one-register predicated loads.
23
- * callers must catch this.
20
+ * Common helper for all contiguous 1,2,3,4-register predicated stores.
24
+ * callers must catch this; we return the 64-bit constant value defined
21
*/
25
+ * for AArch64.
22
static inline QEMU_ALWAYS_INLINE
26
*
23
-void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
27
* cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
24
+void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
28
* is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
25
uint32_t desc, const uintptr_t retaddr,
29
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
26
- const int esz, const int msz,
30
index XXXXXXX..XXXXXXX 100644
27
+ const int esz, const int msz, const int N,
31
--- a/target/arm/translate-a64.c
28
sve_ldst1_host_fn *host_fn,
32
+++ b/target/arm/translate-a64.c
29
sve_ldst1_tlb_fn *tlb_fn)
33
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
30
{
34
{
31
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
35
int rd = extract32(insn, 0, 5);
32
- void *vd = &env->vfp.zregs[rd];
36
int cmode = extract32(insn, 12, 4);
33
const intptr_t reg_max = simd_oprsz(desc);
37
- int cmode_3_1 = extract32(cmode, 1, 3);
34
intptr_t reg_off, reg_last, mem_off;
38
- int cmode_0 = extract32(cmode, 0, 1);
35
SVEContLdSt info;
39
int o2 = extract32(insn, 11, 1);
36
void *host;
40
uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
37
- int flags;
41
bool is_neg = extract32(insn, 29, 1);
38
+ int flags, i;
42
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
39
40
/* Find the active elements. */
41
- if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, 1 << msz)) {
42
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, N << msz)) {
43
/* The entire predicate was false; no load occurs. */
44
- memset(vd, 0, reg_max);
45
+ for (i = 0; i < N; ++i) {
46
+ memset(&env->vfp.zregs[(rd + i) & 31], 0, reg_max);
47
+ }
48
return;
43
return;
49
}
44
}
50
45
51
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
46
- /* See AdvSIMDExpandImm() in ARM ARM */
52
sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, retaddr);
47
- switch (cmode_3_1) {
53
48
- case 0: /* Replicate(Zeros(24):imm8, 2) */
54
/* Handle watchpoints for all active elements. */
49
- case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
55
- sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, 1 << msz,
50
- case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
56
+ sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, N << msz,
51
- case 3: /* Replicate(imm8:Zeros(24), 2) */
57
BP_MEM_READ, retaddr);
52
- {
58
53
- int shift = cmode_3_1 * 8;
59
/* TODO: MTE check. */
54
- imm = bitfield_replicate(abcdefgh << shift, 32);
60
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
55
- break;
61
* which for ARM will raise SyncExternal. Perform the load
56
- }
62
* into scratch memory to preserve register state until the end.
57
- case 4: /* Replicate(Zeros(8):imm8, 4) */
63
*/
58
- case 5: /* Replicate(imm8:Zeros(8), 4) */
64
- ARMVectorReg scratch;
59
- {
65
+ ARMVectorReg scratch[4] = { };
60
- int shift = (cmode_3_1 & 0x1) * 8;
66
61
- imm = bitfield_replicate(abcdefgh << shift, 16);
67
- memset(&scratch, 0, reg_max);
62
- break;
68
mem_off = info.mem_off_first[0];
63
- }
69
reg_off = info.reg_off_first[0];
64
- case 6:
70
reg_last = info.reg_off_last[1];
65
- if (cmode_0) {
71
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
66
- /* Replicate(Zeros(8):imm8:Ones(16), 2) */
72
uint64_t pg = vg[reg_off >> 6];
67
- imm = (abcdefgh << 16) | 0xffff;
73
do {
68
- } else {
74
if ((pg >> (reg_off & 63)) & 1) {
69
- /* Replicate(Zeros(16):imm8:Ones(8), 2) */
75
- tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
70
- imm = (abcdefgh << 8) | 0xff;
76
+ for (i = 0; i < N; ++i) {
71
- }
77
+ tlb_fn(env, &scratch[i], reg_off,
72
- imm = bitfield_replicate(imm, 32);
78
+ addr + mem_off + (i << msz), retaddr);
73
- break;
79
+ }
74
- case 7:
80
}
75
- if (!cmode_0 && !is_neg) {
81
reg_off += 1 << esz;
76
- imm = bitfield_replicate(abcdefgh, 8);
82
- mem_off += 1 << msz;
77
- } else if (!cmode_0 && is_neg) {
83
+ mem_off += N << msz;
78
- int i;
84
} while (reg_off & 63);
79
- imm = 0;
85
} while (reg_off <= reg_last);
80
- for (i = 0; i < 8; i++) {
86
81
- if ((abcdefgh) & (1 << i)) {
87
- memcpy(vd, &scratch, reg_max);
82
- imm |= 0xffULL << (i * 8);
88
+ for (i = 0; i < N; ++i) {
83
- }
89
+ memcpy(&env->vfp.zregs[(rd + i) & 31], &scratch[i], reg_max);
90
+ }
91
return;
92
#endif
93
}
94
95
/* The entire operation is in RAM, on valid pages. */
96
97
- memset(vd, 0, reg_max);
98
+ for (i = 0; i < N; ++i) {
99
+ memset(&env->vfp.zregs[(rd + i) & 31], 0, reg_max);
100
+ }
101
+
102
mem_off = info.mem_off_first[0];
103
reg_off = info.reg_off_first[0];
104
reg_last = info.reg_off_last[0];
105
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
106
uint64_t pg = vg[reg_off >> 6];
107
do {
108
if ((pg >> (reg_off & 63)) & 1) {
109
- host_fn(vd, reg_off, host + mem_off);
110
+ for (i = 0; i < N; ++i) {
111
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
112
+ host + mem_off + (i << msz));
113
+ }
114
}
115
reg_off += 1 << esz;
116
- mem_off += 1 << msz;
117
+ mem_off += N << msz;
118
} while (reg_off <= reg_last && (reg_off & 63));
119
}
120
121
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
122
*/
123
mem_off = info.mem_off_split;
124
if (unlikely(mem_off >= 0)) {
125
- tlb_fn(env, vd, info.reg_off_split, addr + mem_off, retaddr);
126
+ reg_off = info.reg_off_split;
127
+ for (i = 0; i < N; ++i) {
128
+ tlb_fn(env, &env->vfp.zregs[(rd + i) & 31], reg_off,
129
+ addr + mem_off + (i << msz), retaddr);
130
+ }
131
}
132
133
mem_off = info.mem_off_first[1];
134
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
135
uint64_t pg = vg[reg_off >> 6];
136
do {
137
if ((pg >> (reg_off & 63)) & 1) {
138
- host_fn(vd, reg_off, host + mem_off);
139
+ for (i = 0; i < N; ++i) {
140
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
141
+ host + mem_off + (i << msz));
142
+ }
143
}
144
reg_off += 1 << esz;
145
- mem_off += 1 << msz;
146
+ mem_off += N << msz;
147
} while (reg_off & 63);
148
} while (reg_off <= reg_last);
149
}
150
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
151
void HELPER(sve_##NAME##_r)(CPUARMState *env, void *vg, \
152
target_ulong addr, uint32_t desc) \
153
{ \
154
- sve_ld1_r(env, vg, addr, desc, GETPC(), ESZ, 0, \
155
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, 1, \
156
sve_##NAME##_host, sve_##NAME##_tlb); \
157
}
158
159
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_##NAME##_r)(CPUARMState *env, void *vg, \
160
void HELPER(sve_##NAME##_le_r)(CPUARMState *env, void *vg, \
161
target_ulong addr, uint32_t desc) \
162
{ \
163
- sve_ld1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
164
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \
165
sve_##NAME##_le_host, sve_##NAME##_le_tlb); \
166
} \
167
void HELPER(sve_##NAME##_be_r)(CPUARMState *env, void *vg, \
168
target_ulong addr, uint32_t desc) \
169
{ \
170
- sve_ld1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
171
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \
172
sve_##NAME##_be_host, sve_##NAME##_be_tlb); \
173
}
174
175
-DO_LD1_1(ld1bb, 0)
176
-DO_LD1_1(ld1bhu, 1)
177
-DO_LD1_1(ld1bhs, 1)
178
-DO_LD1_1(ld1bsu, 2)
179
-DO_LD1_1(ld1bss, 2)
180
-DO_LD1_1(ld1bdu, 3)
181
-DO_LD1_1(ld1bds, 3)
182
+DO_LD1_1(ld1bb, MO_8)
183
+DO_LD1_1(ld1bhu, MO_16)
184
+DO_LD1_1(ld1bhs, MO_16)
185
+DO_LD1_1(ld1bsu, MO_32)
186
+DO_LD1_1(ld1bss, MO_32)
187
+DO_LD1_1(ld1bdu, MO_64)
188
+DO_LD1_1(ld1bds, MO_64)
189
190
-DO_LD1_2(ld1hh, 1, 1)
191
-DO_LD1_2(ld1hsu, 2, 1)
192
-DO_LD1_2(ld1hss, 2, 1)
193
-DO_LD1_2(ld1hdu, 3, 1)
194
-DO_LD1_2(ld1hds, 3, 1)
195
+DO_LD1_2(ld1hh, MO_16, MO_16)
196
+DO_LD1_2(ld1hsu, MO_32, MO_16)
197
+DO_LD1_2(ld1hss, MO_32, MO_16)
198
+DO_LD1_2(ld1hdu, MO_64, MO_16)
199
+DO_LD1_2(ld1hds, MO_64, MO_16)
200
201
-DO_LD1_2(ld1ss, 2, 2)
202
-DO_LD1_2(ld1sdu, 3, 2)
203
-DO_LD1_2(ld1sds, 3, 2)
204
+DO_LD1_2(ld1ss, MO_32, MO_32)
205
+DO_LD1_2(ld1sdu, MO_64, MO_32)
206
+DO_LD1_2(ld1sds, MO_64, MO_32)
207
208
-DO_LD1_2(ld1dd, 3, 3)
209
+DO_LD1_2(ld1dd, MO_64, MO_64)
210
211
#undef DO_LD1_1
212
#undef DO_LD1_2
213
214
-/*
215
- * Common helpers for all contiguous 2,3,4-register predicated loads.
216
- */
217
-static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
218
- uint32_t desc, int size, uintptr_t ra,
219
- sve_ldst1_tlb_fn *tlb_fn)
220
-{
221
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
222
- intptr_t i, oprsz = simd_oprsz(desc);
223
- ARMVectorReg scratch[2] = { };
224
-
225
- for (i = 0; i < oprsz; ) {
226
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
227
- do {
228
- if (pg & 1) {
229
- tlb_fn(env, &scratch[0], i, addr, ra);
230
- tlb_fn(env, &scratch[1], i, addr + size, ra);
231
- }
84
- }
232
- i += size, pg >>= size;
85
- } else if (cmode_0) {
233
- addr += 2 * size;
86
- if (is_neg) {
234
- } while (i & 15);
87
- imm = (abcdefgh & 0x3f) << 48;
88
- if (abcdefgh & 0x80) {
89
- imm |= 0x8000000000000000ULL;
90
- }
91
- if (abcdefgh & 0x40) {
92
- imm |= 0x3fc0000000000000ULL;
93
- } else {
94
- imm |= 0x4000000000000000ULL;
95
- }
96
- } else {
97
- if (o2) {
98
- /* FMOV (vector, immediate) - half-precision */
99
- imm = vfp_expand_imm(MO_16, abcdefgh);
100
- /* now duplicate across the lanes */
101
- imm = bitfield_replicate(imm, 16);
102
- } else {
103
- imm = (abcdefgh & 0x3f) << 19;
104
- if (abcdefgh & 0x80) {
105
- imm |= 0x80000000;
106
- }
107
- if (abcdefgh & 0x40) {
108
- imm |= 0x3e000000;
109
- } else {
110
- imm |= 0x40000000;
111
- }
112
- imm |= (imm << 32);
113
- }
114
- }
115
- }
116
- break;
117
- default:
118
- g_assert_not_reached();
235
- }
119
- }
236
-
120
-
237
- /* Wait until all exceptions have been raised to write back. */
121
- if (cmode_3_1 != 7 && is_neg) {
238
- memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
122
- imm = ~imm;
239
- memcpy(&env->vfp.zregs[(rd + 1) & 31], &scratch[1], oprsz);
123
+ if (cmode == 15 && o2 && !is_neg) {
240
-}
124
+ /* FMOV (vector, immediate) - half-precision */
241
-
125
+ imm = vfp_expand_imm(MO_16, abcdefgh);
242
-static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
126
+ /* now duplicate across the lanes */
243
- uint32_t desc, int size, uintptr_t ra,
127
+ imm = bitfield_replicate(imm, 16);
244
- sve_ldst1_tlb_fn *tlb_fn)
128
+ } else {
245
-{
129
+ imm = asimd_imm_const(abcdefgh, cmode, is_neg);
246
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
130
}
247
- intptr_t i, oprsz = simd_oprsz(desc);
131
248
- ARMVectorReg scratch[3] = { };
132
if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
249
-
133
diff --git a/target/arm/translate.c b/target/arm/translate.c
250
- for (i = 0; i < oprsz; ) {
134
index XXXXXXX..XXXXXXX 100644
251
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
135
--- a/target/arm/translate.c
252
- do {
136
+++ b/target/arm/translate.c
253
- if (pg & 1) {
137
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
254
- tlb_fn(env, &scratch[0], i, addr, ra);
138
case 14:
255
- tlb_fn(env, &scratch[1], i, addr + size, ra);
139
if (op) {
256
- tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
140
/*
257
- }
141
- * This is the only case where the top and bottom 32 bits
258
- i += size, pg >>= size;
142
- * of the encoded constant differ.
259
- addr += 3 * size;
143
+ * This and cmode == 15 op == 1 are the only cases where
260
- } while (i & 15);
144
+ * the top and bottom 32 bits of the encoded constant differ.
261
- }
145
*/
262
-
146
uint64_t imm64 = 0;
263
- /* Wait until all exceptions have been raised to write back. */
147
int n;
264
- memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
148
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
265
- memcpy(&env->vfp.zregs[(rd + 1) & 31], &scratch[1], oprsz);
149
imm |= (imm << 8) | (imm << 16) | (imm << 24);
266
- memcpy(&env->vfp.zregs[(rd + 2) & 31], &scratch[2], oprsz);
150
break;
267
-}
151
case 15:
268
-
152
+ if (op) {
269
-static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
153
+ /* Reserved encoding for AArch32; valid for AArch64 */
270
- uint32_t desc, int size, uintptr_t ra,
154
+ uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
271
- sve_ldst1_tlb_fn *tlb_fn)
155
+ if (imm & 0x80) {
272
-{
156
+ imm64 |= 0x8000000000000000ULL;
273
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
157
+ }
274
- intptr_t i, oprsz = simd_oprsz(desc);
158
+ if (imm & 0x40) {
275
- ARMVectorReg scratch[4] = { };
159
+ imm64 |= 0x3fc0000000000000ULL;
276
-
160
+ } else {
277
- for (i = 0; i < oprsz; ) {
161
+ imm64 |= 0x4000000000000000ULL;
278
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
162
+ }
279
- do {
163
+ return imm64;
280
- if (pg & 1) {
164
+ }
281
- tlb_fn(env, &scratch[0], i, addr, ra);
165
imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
282
- tlb_fn(env, &scratch[1], i, addr + size, ra);
166
| ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
283
- tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
167
break;
284
- tlb_fn(env, &scratch[3], i, addr + 3 * size, ra);
285
- }
286
- i += size, pg >>= size;
287
- addr += 4 * size;
288
- } while (i & 15);
289
- }
290
-
291
- /* Wait until all exceptions have been raised to write back. */
292
- memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
293
- memcpy(&env->vfp.zregs[(rd + 1) & 31], &scratch[1], oprsz);
294
- memcpy(&env->vfp.zregs[(rd + 2) & 31], &scratch[2], oprsz);
295
- memcpy(&env->vfp.zregs[(rd + 3) & 31], &scratch[3], oprsz);
296
-}
297
-
298
#define DO_LDN_1(N) \
299
-void QEMU_FLATTEN HELPER(sve_ld##N##bb_r) \
300
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
301
-{ \
302
- sve_ld##N##_r(env, vg, addr, desc, 1, GETPC(), sve_ld1bb_tlb); \
303
+void HELPER(sve_ld##N##bb_r)(CPUARMState *env, void *vg, \
304
+ target_ulong addr, uint32_t desc) \
305
+{ \
306
+ sve_ldN_r(env, vg, addr, desc, GETPC(), MO_8, MO_8, N, \
307
+ sve_ld1bb_host, sve_ld1bb_tlb); \
308
}
309
310
-#define DO_LDN_2(N, SUFF, SIZE) \
311
-void QEMU_FLATTEN HELPER(sve_ld##N##SUFF##_le_r) \
312
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
313
+#define DO_LDN_2(N, SUFF, ESZ) \
314
+void HELPER(sve_ld##N##SUFF##_le_r)(CPUARMState *env, void *vg, \
315
+ target_ulong addr, uint32_t desc) \
316
{ \
317
- sve_ld##N##_r(env, vg, addr, desc, SIZE, GETPC(), \
318
- sve_ld1##SUFF##_le_tlb); \
319
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \
320
+ sve_ld1##SUFF##_le_host, sve_ld1##SUFF##_le_tlb); \
321
} \
322
-void QEMU_FLATTEN HELPER(sve_ld##N##SUFF##_be_r) \
323
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
324
+void HELPER(sve_ld##N##SUFF##_be_r)(CPUARMState *env, void *vg, \
325
+ target_ulong addr, uint32_t desc) \
326
{ \
327
- sve_ld##N##_r(env, vg, addr, desc, SIZE, GETPC(), \
328
- sve_ld1##SUFF##_be_tlb); \
329
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \
330
+ sve_ld1##SUFF##_be_host, sve_ld1##SUFF##_be_tlb); \
331
}
332
333
DO_LDN_1(2)
334
DO_LDN_1(3)
335
DO_LDN_1(4)
336
337
-DO_LDN_2(2, hh, 2)
338
-DO_LDN_2(3, hh, 2)
339
-DO_LDN_2(4, hh, 2)
340
+DO_LDN_2(2, hh, MO_16)
341
+DO_LDN_2(3, hh, MO_16)
342
+DO_LDN_2(4, hh, MO_16)
343
344
-DO_LDN_2(2, ss, 4)
345
-DO_LDN_2(3, ss, 4)
346
-DO_LDN_2(4, ss, 4)
347
+DO_LDN_2(2, ss, MO_32)
348
+DO_LDN_2(3, ss, MO_32)
349
+DO_LDN_2(4, ss, MO_32)
350
351
-DO_LDN_2(2, dd, 8)
352
-DO_LDN_2(3, dd, 8)
353
-DO_LDN_2(4, dd, 8)
354
+DO_LDN_2(2, dd, MO_64)
355
+DO_LDN_2(3, dd, MO_64)
356
+DO_LDN_2(4, dd, MO_64)
357
358
#undef DO_LDN_1
359
#undef DO_LDN_2
360
--
168
--
361
2.20.1
169
2.20.1
362
170
363
171
diff view generated by jsdifflib
[PULL 09/34] exec: Fix cpu_watchpoint_address_matches address length
[PULL 11/24] target/arm: Use dup_const() instead of bitfield_replicate()
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Use dup_const() instead of bitfield_replicate() in
2
disas_simd_mod_imm().
2
3
3
The only caller of cpu_watchpoint_address_matches passes
4
(We can't replace the other use of bitfield_replicate() in this file,
4
TARGET_PAGE_SIZE, so the bug is not currently visible.
5
in logic_imm_decode_wmask(), because that location needs to handle 2
6
and 4 bit elements, which dup_const() cannot.)
5
7
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20200508154359.7494-3-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
11
---
11
---
12
exec.c | 2 +-
12
target/arm/translate-a64.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
14
15
diff --git a/exec.c b/exec.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/exec.c
17
--- a/target/arm/translate-a64.c
18
+++ b/exec.c
18
+++ b/target/arm/translate-a64.c
19
@@ -XXX,XX +XXX,XX @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
20
int ret = 0;
20
/* FMOV (vector, immediate) - half-precision */
21
21
imm = vfp_expand_imm(MO_16, abcdefgh);
22
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
22
/* now duplicate across the lanes */
23
- if (watchpoint_address_matches(wp, addr, TARGET_PAGE_SIZE)) {
23
- imm = bitfield_replicate(imm, 16);
24
+ if (watchpoint_address_matches(wp, addr, len)) {
24
+ imm = dup_const(MO_16, imm);
25
ret |= wp->flags;
25
} else {
26
}
26
imm = asimd_imm_const(abcdefgh, cmode, is_neg);
27
}
27
}
28
--
28
--
29
2.20.1
29
2.20.1
30
30
31
31
diff view generated by jsdifflib
[PULL 33/34] target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
[PULL 12/24] target/arm: Implement MVE logical immediate insns
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the MVE logical-immediate insns (VMOV, VMVN,
2
VORR and VBIC). These have essentially the same encoding
3
as their Neon equivalents, and we implement the decode
4
in the same way.
2
5
3
Now that we can pass 7 parameters, do not encode register
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
operands within simd_data.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
9
---
10
target/arm/helper-mve.h | 4 +++
11
target/arm/mve.decode | 17 +++++++++++++
12
target/arm/mve_helper.c | 24 ++++++++++++++++++
13
target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
14
4 files changed, 95 insertions(+)
5
15
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
7
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200507172352.15418-2-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/helper-sve.h | 45 +++++++----
13
target/arm/sve_helper.c | 157 ++++++++++++++-----------------------
14
target/arm/translate-sve.c | 70 ++++++-----------
15
3 files changed, 114 insertions(+), 158 deletions(-)
16
17
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
18
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper-sve.h
18
--- a/target/arm/helper-mve.h
20
+++ b/target/arm/helper-sve.h
19
+++ b/target/arm/helper-mve.h
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_6(sve_fcadd_s, TCG_CALL_NO_RWG,
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
DEF_HELPER_FLAGS_6(sve_fcadd_d, TCG_CALL_NO_RWG,
21
DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
23
void, ptr, ptr, ptr, ptr, ptr, i32)
22
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
24
23
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
25
-DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
24
+
26
-DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
25
+DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
27
-DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
26
+DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
28
+DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG,
27
+DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
29
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
28
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
30
+DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG,
31
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG,
33
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
34
35
-DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
36
-DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
37
-DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
38
+DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG,
39
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG,
41
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
42
+DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG,
43
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
44
45
-DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
46
-DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
47
-DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
48
+DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG,
49
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
50
+DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG,
51
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
52
+DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG,
53
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
54
55
-DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
56
-DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
57
-DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
58
+DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG,
59
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
60
+DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG,
61
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
62
+DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG,
63
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
64
65
-DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
66
-DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
67
-DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
68
+DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG,
69
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
70
+DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG,
71
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
72
+DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG,
73
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
74
75
DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
76
DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
77
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
78
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
79
--- a/target/arm/sve_helper.c
30
--- a/target/arm/mve.decode
80
+++ b/target/arm/sve_helper.c
31
+++ b/target/arm/mve.decode
81
@@ -XXX,XX +XXX,XX @@ DO_ZPZ_FP(sve_ucvt_dd, uint64_t, , uint64_to_float64)
32
@@ -XXX,XX +XXX,XX @@
82
33
# VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
83
#undef DO_ZPZ_FP
34
%size_28 28:1 !function=plus_1
84
35
85
-/* 4-operand predicated multiply-add. This requires 7 operands to pass
36
+# 1imm format immediate
86
- * "properly", so we need to encode some of the registers into DESC.
37
+%imm_28_16_0 28:1 16:3 0:4
87
- */
38
+
88
-QEMU_BUILD_BUG_ON(SIMD_DATA_SHIFT + 20 > 32);
39
&vldr_vstr rn qd imm p a w size l u
89
-
40
&1op qd qm size
90
-static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
41
&2op qd qm qn size
91
+static void do_fmla_zpzzz_h(void *vd, void *vn, void *vm, void *va, void *vg,
42
&2scalar qd qn rm size
92
+ float_status *status, uint32_t desc,
43
+&1imm qd imm cmode op
93
uint16_t neg1, uint16_t neg3)
44
94
{
45
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
95
intptr_t i = simd_oprsz(desc);
46
# Note that both Rn and Qd are 3 bits only (no D bit)
96
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
47
@@ -XXX,XX +XXX,XX @@
97
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
48
@2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
98
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
49
@2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \
99
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
50
size=%size_28
100
- void *vd = &env->vfp.zregs[rd];
51
+@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0
101
- void *vn = &env->vfp.zregs[rn];
52
102
- void *vm = &env->vfp.zregs[rm];
53
# The _rev suffix indicates that Vn and Vm are reversed. This is
103
- void *va = &env->vfp.zregs[ra];
54
# the case for shifts. In the Arm ARM these insns are documented
104
uint64_t *g = vg;
55
@@ -XXX,XX +XXX,XX @@ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd
105
56
# Predicate operations
106
do {
57
%mask_22_13 22:1 13:3
107
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
58
VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
108
e1 = *(uint16_t *)(vn + H1_2(i)) ^ neg1;
59
+
109
e2 = *(uint16_t *)(vm + H1_2(i));
60
+# Logical immediate operations (1 reg and modified-immediate)
110
e3 = *(uint16_t *)(va + H1_2(i)) ^ neg3;
61
+
111
- r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status_f16);
62
+# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
112
+ r = float16_muladd(e1, e2, e3, 0, status);
63
+# not in a way we can conveniently represent in decodetree without
113
*(uint16_t *)(vd + H1_2(i)) = r;
64
+# a lot of repetition:
114
}
65
+# VORR: op=0, (cmode & 1) && cmode < 12
115
} while (i & 63);
66
+# VBIC: op=1, (cmode & 1) && cmode < 12
116
} while (i != 0);
67
+# VMOV: everything else
117
}
68
+# So we have a single decode line and check the cmode/op in the
118
69
+# trans function.
119
-void HELPER(sve_fmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
70
+Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
120
+void HELPER(sve_fmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
71
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
121
+ void *vg, void *status, uint32_t desc)
122
{
123
- do_fmla_zpzzz_h(env, vg, desc, 0, 0);
124
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0);
125
}
126
127
-void HELPER(sve_fmls_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
128
+void HELPER(sve_fmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
129
+ void *vg, void *status, uint32_t desc)
130
{
131
- do_fmla_zpzzz_h(env, vg, desc, 0x8000, 0);
132
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0);
133
}
134
135
-void HELPER(sve_fnmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
136
+void HELPER(sve_fnmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
137
+ void *vg, void *status, uint32_t desc)
138
{
139
- do_fmla_zpzzz_h(env, vg, desc, 0x8000, 0x8000);
140
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0x8000);
141
}
142
143
-void HELPER(sve_fnmls_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
144
+void HELPER(sve_fnmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
145
+ void *vg, void *status, uint32_t desc)
146
{
147
- do_fmla_zpzzz_h(env, vg, desc, 0, 0x8000);
148
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0x8000);
149
}
150
151
-static void do_fmla_zpzzz_s(CPUARMState *env, void *vg, uint32_t desc,
152
+static void do_fmla_zpzzz_s(void *vd, void *vn, void *vm, void *va, void *vg,
153
+ float_status *status, uint32_t desc,
154
uint32_t neg1, uint32_t neg3)
155
{
156
intptr_t i = simd_oprsz(desc);
157
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
158
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
159
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
160
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
161
- void *vd = &env->vfp.zregs[rd];
162
- void *vn = &env->vfp.zregs[rn];
163
- void *vm = &env->vfp.zregs[rm];
164
- void *va = &env->vfp.zregs[ra];
165
uint64_t *g = vg;
166
167
do {
168
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_s(CPUARMState *env, void *vg, uint32_t desc,
169
e1 = *(uint32_t *)(vn + H1_4(i)) ^ neg1;
170
e2 = *(uint32_t *)(vm + H1_4(i));
171
e3 = *(uint32_t *)(va + H1_4(i)) ^ neg3;
172
- r = float32_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
173
+ r = float32_muladd(e1, e2, e3, 0, status);
174
*(uint32_t *)(vd + H1_4(i)) = r;
175
}
176
} while (i & 63);
177
} while (i != 0);
178
}
179
180
-void HELPER(sve_fmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
181
+void HELPER(sve_fmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
182
+ void *vg, void *status, uint32_t desc)
183
{
184
- do_fmla_zpzzz_s(env, vg, desc, 0, 0);
185
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0);
186
}
187
188
-void HELPER(sve_fmls_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
189
+void HELPER(sve_fmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
190
+ void *vg, void *status, uint32_t desc)
191
{
192
- do_fmla_zpzzz_s(env, vg, desc, 0x80000000, 0);
193
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0);
194
}
195
196
-void HELPER(sve_fnmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
197
+void HELPER(sve_fnmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
198
+ void *vg, void *status, uint32_t desc)
199
{
200
- do_fmla_zpzzz_s(env, vg, desc, 0x80000000, 0x80000000);
201
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0x80000000);
202
}
203
204
-void HELPER(sve_fnmls_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
205
+void HELPER(sve_fnmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
206
+ void *vg, void *status, uint32_t desc)
207
{
208
- do_fmla_zpzzz_s(env, vg, desc, 0, 0x80000000);
209
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0x80000000);
210
}
211
212
-static void do_fmla_zpzzz_d(CPUARMState *env, void *vg, uint32_t desc,
213
+static void do_fmla_zpzzz_d(void *vd, void *vn, void *vm, void *va, void *vg,
214
+ float_status *status, uint32_t desc,
215
uint64_t neg1, uint64_t neg3)
216
{
217
intptr_t i = simd_oprsz(desc);
218
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
219
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
220
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
221
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
222
- void *vd = &env->vfp.zregs[rd];
223
- void *vn = &env->vfp.zregs[rn];
224
- void *vm = &env->vfp.zregs[rm];
225
- void *va = &env->vfp.zregs[ra];
226
uint64_t *g = vg;
227
228
do {
229
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_d(CPUARMState *env, void *vg, uint32_t desc,
230
e1 = *(uint64_t *)(vn + i) ^ neg1;
231
e2 = *(uint64_t *)(vm + i);
232
e3 = *(uint64_t *)(va + i) ^ neg3;
233
- r = float64_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
234
+ r = float64_muladd(e1, e2, e3, 0, status);
235
*(uint64_t *)(vd + i) = r;
236
}
237
} while (i & 63);
238
} while (i != 0);
239
}
240
241
-void HELPER(sve_fmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
242
+void HELPER(sve_fmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
243
+ void *vg, void *status, uint32_t desc)
244
{
245
- do_fmla_zpzzz_d(env, vg, desc, 0, 0);
246
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, 0);
247
}
248
249
-void HELPER(sve_fmls_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
250
+void HELPER(sve_fmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
251
+ void *vg, void *status, uint32_t desc)
252
{
253
- do_fmla_zpzzz_d(env, vg, desc, INT64_MIN, 0);
254
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, 0);
255
}
256
257
-void HELPER(sve_fnmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
258
+void HELPER(sve_fnmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
259
+ void *vg, void *status, uint32_t desc)
260
{
261
- do_fmla_zpzzz_d(env, vg, desc, INT64_MIN, INT64_MIN);
262
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, INT64_MIN);
263
}
264
265
-void HELPER(sve_fnmls_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
266
+void HELPER(sve_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
267
+ void *vg, void *status, uint32_t desc)
268
{
269
- do_fmla_zpzzz_d(env, vg, desc, 0, INT64_MIN);
270
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, INT64_MIN);
271
}
272
273
/* Two operand floating-point comparison controlled by a predicate.
274
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
275
* FP Complex Multiply
276
*/
277
278
-QEMU_BUILD_BUG_ON(SIMD_DATA_SHIFT + 22 > 32);
279
-
280
-void HELPER(sve_fcmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
281
+void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
282
+ void *vg, void *status, uint32_t desc)
283
{
284
intptr_t j, i = simd_oprsz(desc);
285
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
286
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
287
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
288
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
289
- unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
290
+ unsigned rot = simd_data(desc);
291
bool flip = rot & 1;
292
float16 neg_imag, neg_real;
293
- void *vd = &env->vfp.zregs[rd];
294
- void *vn = &env->vfp.zregs[rn];
295
- void *vm = &env->vfp.zregs[rm];
296
- void *va = &env->vfp.zregs[ra];
297
uint64_t *g = vg;
298
299
neg_imag = float16_set_sign(0, (rot & 2) != 0);
300
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
301
302
if (likely((pg >> (i & 63)) & 1)) {
303
d = *(float16 *)(va + H1_2(i));
304
- d = float16_muladd(e2, e1, d, 0, &env->vfp.fp_status_f16);
305
+ d = float16_muladd(e2, e1, d, 0, status);
306
*(float16 *)(vd + H1_2(i)) = d;
307
}
308
if (likely((pg >> (j & 63)) & 1)) {
309
d = *(float16 *)(va + H1_2(j));
310
- d = float16_muladd(e4, e3, d, 0, &env->vfp.fp_status_f16);
311
+ d = float16_muladd(e4, e3, d, 0, status);
312
*(float16 *)(vd + H1_2(j)) = d;
313
}
314
} while (i & 63);
315
} while (i != 0);
316
}
317
318
-void HELPER(sve_fcmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
319
+void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
320
+ void *vg, void *status, uint32_t desc)
321
{
322
intptr_t j, i = simd_oprsz(desc);
323
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
324
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
325
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
326
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
327
- unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
328
+ unsigned rot = simd_data(desc);
329
bool flip = rot & 1;
330
float32 neg_imag, neg_real;
331
- void *vd = &env->vfp.zregs[rd];
332
- void *vn = &env->vfp.zregs[rn];
333
- void *vm = &env->vfp.zregs[rm];
334
- void *va = &env->vfp.zregs[ra];
335
uint64_t *g = vg;
336
337
neg_imag = float32_set_sign(0, (rot & 2) != 0);
338
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
339
340
if (likely((pg >> (i & 63)) & 1)) {
341
d = *(float32 *)(va + H1_2(i));
342
- d = float32_muladd(e2, e1, d, 0, &env->vfp.fp_status);
343
+ d = float32_muladd(e2, e1, d, 0, status);
344
*(float32 *)(vd + H1_2(i)) = d;
345
}
346
if (likely((pg >> (j & 63)) & 1)) {
347
d = *(float32 *)(va + H1_2(j));
348
- d = float32_muladd(e4, e3, d, 0, &env->vfp.fp_status);
349
+ d = float32_muladd(e4, e3, d, 0, status);
350
*(float32 *)(vd + H1_2(j)) = d;
351
}
352
} while (i & 63);
353
} while (i != 0);
354
}
355
356
-void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
357
+void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
358
+ void *vg, void *status, uint32_t desc)
359
{
360
intptr_t j, i = simd_oprsz(desc);
361
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
362
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
363
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
364
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
365
- unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
366
+ unsigned rot = simd_data(desc);
367
bool flip = rot & 1;
368
float64 neg_imag, neg_real;
369
- void *vd = &env->vfp.zregs[rd];
370
- void *vn = &env->vfp.zregs[rn];
371
- void *vm = &env->vfp.zregs[rm];
372
- void *va = &env->vfp.zregs[ra];
373
uint64_t *g = vg;
374
375
neg_imag = float64_set_sign(0, (rot & 2) != 0);
376
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
377
378
if (likely((pg >> (i & 63)) & 1)) {
379
d = *(float64 *)(va + H1_2(i));
380
- d = float64_muladd(e2, e1, d, 0, &env->vfp.fp_status);
381
+ d = float64_muladd(e2, e1, d, 0, status);
382
*(float64 *)(vd + H1_2(i)) = d;
383
}
384
if (likely((pg >> (j & 63)) & 1)) {
385
d = *(float64 *)(va + H1_2(j));
386
- d = float64_muladd(e4, e3, d, 0, &env->vfp.fp_status);
387
+ d = float64_muladd(e4, e3, d, 0, status);
388
*(float64 *)(vd + H1_2(j)) = d;
389
}
390
} while (i & 63);
391
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
392
index XXXXXXX..XXXXXXX 100644
72
index XXXXXXX..XXXXXXX 100644
393
--- a/target/arm/translate-sve.c
73
--- a/target/arm/mve_helper.c
394
+++ b/target/arm/translate-sve.c
74
+++ b/target/arm/mve_helper.c
395
@@ -XXX,XX +XXX,XX @@ static bool trans_FCADD(DisasContext *s, arg_FCADD *a)
75
@@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG)
76
DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
77
DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
78
79
+/*
80
+ * 1 operand immediates: Vda is destination and possibly also one source.
81
+ * All these insns work at 64-bit widths.
82
+ */
83
+#define DO_1OP_IMM(OP, FN) \
84
+ void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \
85
+ { \
86
+ uint64_t *da = vda; \
87
+ uint16_t mask = mve_element_mask(env); \
88
+ unsigned e; \
89
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
90
+ mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \
91
+ } \
92
+ mve_advance_vpt(env); \
93
+ }
94
+
95
+#define DO_MOVI(N, I) (I)
96
+#define DO_ANDI(N, I) ((N) & (I))
97
+#define DO_ORRI(N, I) ((N) | (I))
98
+
99
+DO_1OP_IMM(vmovi, DO_MOVI)
100
+DO_1OP_IMM(vandi, DO_ANDI)
101
+DO_1OP_IMM(vorri, DO_ORRI)
102
+
103
#define DO_2OP(OP, ESIZE, TYPE, FN) \
104
void HELPER(glue(mve_, OP))(CPUARMState *env, \
105
void *vd, void *vn, void *vm) \
106
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/translate-mve.c
109
+++ b/target/arm/translate-mve.c
110
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
111
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
112
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
113
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
114
+typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
115
116
/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
117
static inline long mve_qreg_offset(unsigned reg)
118
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
119
mve_update_eci(s);
396
return true;
120
return true;
397
}
121
}
398
122
+
399
-typedef void gen_helper_sve_fmla(TCGv_env, TCGv_ptr, TCGv_i32);
123
+static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
400
-
124
+{
401
-static bool do_fmla(DisasContext *s, arg_rprrr_esz *a, gen_helper_sve_fmla *fn)
125
+ TCGv_ptr qd;
402
+static bool do_fmla(DisasContext *s, arg_rprrr_esz *a,
126
+ uint64_t imm;
403
+ gen_helper_gvec_5_ptr *fn)
127
+
404
{
128
+ if (!dc_isar_feature(aa32_mve, s) ||
405
- if (fn == NULL) {
129
+ !mve_check_qreg_bank(s, a->qd) ||
406
+ if (a->esz == 0) {
130
+ !fn) {
407
return false;
131
+ return false;
408
}
132
+ }
409
- if (!sve_access_check(s)) {
133
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
410
- return true;
134
+ return true;
411
+ if (sve_access_check(s)) {
135
+ }
412
+ unsigned vsz = vec_full_reg_size(s);
136
+
413
+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
137
+ imm = asimd_imm_const(a->imm, a->cmode, a->op);
414
+ tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd),
138
+
415
+ vec_full_reg_offset(s, a->rn),
139
+ qd = mve_qreg_ptr(a->qd);
416
+ vec_full_reg_offset(s, a->rm),
140
+ fn(cpu_env, qd, tcg_constant_i64(imm));
417
+ vec_full_reg_offset(s, a->ra),
141
+ tcg_temp_free_ptr(qd);
418
+ pred_full_reg_offset(s, a->pg),
142
+ mve_update_eci(s);
419
+ status, vsz, vsz, 0, fn);
143
+ return true;
420
+ tcg_temp_free_ptr(status);
144
+}
421
}
145
+
422
-
146
+static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
423
- unsigned vsz = vec_full_reg_size(s);
147
+{
424
- unsigned desc;
148
+ /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
425
- TCGv_i32 t_desc;
149
+ MVEGenOneOpImmFn *fn;
426
- TCGv_ptr pg = tcg_temp_new_ptr();
150
+
427
-
151
+ if ((a->cmode & 1) && a->cmode < 12) {
428
- /* We would need 7 operands to pass these arguments "properly".
152
+ if (a->op) {
429
- * So we encode all the register numbers into the descriptor.
153
+ /*
430
- */
154
+ * For op=1, the immediate will be inverted by asimd_imm_const(),
431
- desc = deposit32(a->rd, 5, 5, a->rn);
155
+ * so the VBIC becomes a logical AND operation.
432
- desc = deposit32(desc, 10, 5, a->rm);
156
+ */
433
- desc = deposit32(desc, 15, 5, a->ra);
157
+ fn = gen_helper_mve_vandi;
434
- desc = simd_desc(vsz, vsz, desc);
158
+ } else {
435
-
159
+ fn = gen_helper_mve_vorri;
436
- t_desc = tcg_const_i32(desc);
160
+ }
437
- tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
161
+ } else {
438
- fn(cpu_env, pg, t_desc);
162
+ /* There is one unallocated cmode/op combination in this space */
439
- tcg_temp_free_i32(t_desc);
163
+ if (a->cmode == 15 && a->op == 1) {
440
- tcg_temp_free_ptr(pg);
164
+ return false;
441
return true;
165
+ }
442
}
166
+ /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
443
167
+ fn = gen_helper_mve_vmovi;
444
#define DO_FMLA(NAME, name) \
168
+ }
445
static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a) \
169
+ return do_1imm(s, a, fn);
446
{ \
170
+}
447
- static gen_helper_sve_fmla * const fns[4] = { \
448
+ static gen_helper_gvec_5_ptr * const fns[4] = { \
449
NULL, gen_helper_sve_##name##_h, \
450
gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \
451
}; \
452
@@ -XXX,XX +XXX,XX @@ DO_FMLA(FNMLS_zpzzz, fnmls_zpzzz)
453
454
static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
455
{
456
- static gen_helper_sve_fmla * const fns[3] = {
457
+ static gen_helper_gvec_5_ptr * const fns[4] = {
458
+ NULL,
459
gen_helper_sve_fcmla_zpzzz_h,
460
gen_helper_sve_fcmla_zpzzz_s,
461
gen_helper_sve_fcmla_zpzzz_d,
462
@@ -XXX,XX +XXX,XX @@ static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
463
}
464
if (sve_access_check(s)) {
465
unsigned vsz = vec_full_reg_size(s);
466
- unsigned desc;
467
- TCGv_i32 t_desc;
468
- TCGv_ptr pg = tcg_temp_new_ptr();
469
-
470
- /* We would need 7 operands to pass these arguments "properly".
471
- * So we encode all the register numbers into the descriptor.
472
- */
473
- desc = deposit32(a->rd, 5, 5, a->rn);
474
- desc = deposit32(desc, 10, 5, a->rm);
475
- desc = deposit32(desc, 15, 5, a->ra);
476
- desc = deposit32(desc, 20, 2, a->rot);
477
- desc = sextract32(desc, 0, 22);
478
- desc = simd_desc(vsz, vsz, desc);
479
-
480
- t_desc = tcg_const_i32(desc);
481
- tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
482
- fns[a->esz - 1](cpu_env, pg, t_desc);
483
- tcg_temp_free_i32(t_desc);
484
- tcg_temp_free_ptr(pg);
485
+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
486
+ tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd),
487
+ vec_full_reg_offset(s, a->rn),
488
+ vec_full_reg_offset(s, a->rm),
489
+ vec_full_reg_offset(s, a->ra),
490
+ pred_full_reg_offset(s, a->pg),
491
+ status, vsz, vsz, a->rot, fns[a->esz]);
492
+ tcg_temp_free_ptr(status);
493
}
494
return true;
495
}
496
--
171
--
497
2.20.1
172
2.20.1
498
173
499
174
diff view generated by jsdifflib
[PULL 18/34] target/arm: Use SVEContLdSt in sve_ld1_r
[PULL 13/24] target/arm: Implement MVE vector shift left by immediate insns
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
2
2
and VQSHLU.
3
First use of the new helper functions, so we can remove the
3
4
unused markup. No longer need a scratch for user-only, as
4
The size-and-immediate encoding here is the same as Neon, and we
5
we completely probe the page set before reading; system mode
5
handle it the same way neon-dp.decode does.
6
still requires a scratch for MMIO.
6
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-12-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
12
---
10
---
13
target/arm/sve_helper.c | 188 +++++++++++++++++++++-------------------
11
target/arm/helper-mve.h | 16 +++++++++++
14
1 file changed, 97 insertions(+), 91 deletions(-)
12
target/arm/mve.decode | 23 +++++++++++++++
15
13
target/arm/mve_helper.c | 57 ++++++++++++++++++++++++++++++++++++++
16
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
14
target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
17
index XXXXXXX..XXXXXXX 100644
15
4 files changed, 147 insertions(+)
18
--- a/target/arm/sve_helper.c
16
19
+++ b/target/arm/sve_helper.c
17
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct {
18
index XXXXXXX..XXXXXXX 100644
21
* final element on each page. Identify any single element that spans
19
--- a/target/arm/helper-mve.h
22
* the page boundary. Return true if there are any active elements.
20
+++ b/target/arm/helper-mve.h
23
*/
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
24
-static bool __attribute__((unused))
22
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
25
-sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg,
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
26
- intptr_t reg_max, int esz, int msize)
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
27
+static bool sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr,
25
+
28
+ uint64_t *vg, intptr_t reg_max,
26
+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+ int esz, int msize)
27
+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
{
28
+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
const int esize = 1 << esz;
29
+
32
const uint64_t pg_mask = pred_esz_masks[esz];
30
+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
@@ -XXX,XX +XXX,XX @@ sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg,
31
+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
* Control the generation of page faults with @fault. Return false if
32
+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
* there is no work to do, which can only happen with @fault == FAULT_NO.
33
+
36
*/
34
+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
-static bool __attribute__((unused))
35
+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
-sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, CPUARMState *env,
36
+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
- target_ulong addr, MMUAccessType access_type,
37
+
40
- uintptr_t retaddr)
38
+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+static bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault,
39
+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
+ CPUARMState *env, target_ulong addr,
40
+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+ MMUAccessType access_type, uintptr_t retaddr)
41
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
44
{
42
index XXXXXXX..XXXXXXX 100644
45
int mmu_idx = cpu_mmu_index(env, false);
43
--- a/target/arm/mve.decode
46
int mem_off = info->mem_off_first[0];
44
+++ b/target/arm/mve.decode
47
@@ -XXX,XX +XXX,XX @@ static inline bool test_host_page(void *host)
45
@@ -XXX,XX +XXX,XX @@
48
/*
46
&2op qd qm qn size
49
* Common helper for all contiguous one-register predicated loads.
47
&2scalar qd qn rm size
50
*/
48
&1imm qd imm cmode op
51
-static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
49
+&2shift qd qm shift size
52
- uint32_t desc, const uintptr_t retaddr,
50
53
- const int esz, const int msz,
51
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
54
- sve_ldst1_host_fn *host_fn,
52
# Note that both Rn and Qd are 3 bits only (no D bit)
55
- sve_ldst1_tlb_fn *tlb_fn)
53
@@ -XXX,XX +XXX,XX @@
56
+static inline QEMU_ALWAYS_INLINE
54
@2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
57
+void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
55
@2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
58
+ uint32_t desc, const uintptr_t retaddr,
56
59
+ const int esz, const int msz,
57
+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
60
+ sve_ldst1_host_fn *host_fn,
58
+@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
61
+ sve_ldst1_tlb_fn *tlb_fn)
59
+@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
62
{
60
+
63
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
61
# Vector loads and stores
64
- const int mmu_idx = get_mmuidx(oi);
62
65
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
63
# Widening loads and narrowing stores:
66
void *vd = &env->vfp.zregs[rd];
64
@@ -XXX,XX +XXX,XX @@ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
67
- const int diffsz = esz - msz;
65
# So we have a single decode line and check the cmode/op in the
68
const intptr_t reg_max = simd_oprsz(desc);
66
# trans function.
69
- const intptr_t mem_max = reg_max >> diffsz;
67
Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
70
- ARMVectorReg scratch;
68
+
71
+ intptr_t reg_off, reg_last, mem_off;
69
+# Shifts by immediate
72
+ SVEContLdSt info;
70
+
73
void *host;
71
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
74
- intptr_t split, reg_off, mem_off;
72
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
75
+ int flags;
73
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
76
74
+
77
- /* Find the first active element. */
75
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
78
- reg_off = find_next_active(vg, 0, reg_max, esz);
76
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
79
- if (unlikely(reg_off == reg_max)) {
77
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
80
+ /* Find the active elements. */
78
+
81
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, 1 << msz)) {
79
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
82
/* The entire predicate was false; no load occurs. */
80
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
83
memset(vd, 0, reg_max);
81
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
84
return;
82
+
83
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
84
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
85
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
86
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/target/arm/mve_helper.c
89
+++ b/target/arm/mve_helper.c
90
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
91
WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
92
#define DO_UQRSHL_OP(N, M, satp) \
93
WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
94
+#define DO_SUQSHL_OP(N, M, satp) \
95
+ WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
96
97
DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
98
DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
99
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
100
DO_VADDV(vaddvub, 1, uint8_t)
101
DO_VADDV(vaddvuh, 2, uint16_t)
102
DO_VADDV(vaddvuw, 4, uint32_t)
103
+
104
+/* Shifts by immediate */
105
+#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
106
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
107
+ void *vm, uint32_t shift) \
108
+ { \
109
+ TYPE *d = vd, *m = vm; \
110
+ uint16_t mask = mve_element_mask(env); \
111
+ unsigned e; \
112
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
113
+ mergemask(&d[H##ESIZE(e)], \
114
+ FN(m[H##ESIZE(e)], shift), mask); \
115
+ } \
116
+ mve_advance_vpt(env); \
117
+ }
118
+
119
+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \
120
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
121
+ void *vm, uint32_t shift) \
122
+ { \
123
+ TYPE *d = vd, *m = vm; \
124
+ uint16_t mask = mve_element_mask(env); \
125
+ unsigned e; \
126
+ bool qc = false; \
127
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
128
+ bool sat = false; \
129
+ mergemask(&d[H##ESIZE(e)], \
130
+ FN(m[H##ESIZE(e)], shift, &sat), mask); \
131
+ qc |= sat & mask & 1; \
132
+ } \
133
+ if (qc) { \
134
+ env->vfp.qc[0] = qc; \
135
+ } \
136
+ mve_advance_vpt(env); \
137
+ }
138
+
139
+/* provide unsigned 2-op shift helpers for all sizes */
140
+#define DO_2SHIFT_U(OP, FN) \
141
+ DO_2SHIFT(OP##b, 1, uint8_t, FN) \
142
+ DO_2SHIFT(OP##h, 2, uint16_t, FN) \
143
+ DO_2SHIFT(OP##w, 4, uint32_t, FN)
144
+
145
+#define DO_2SHIFT_SAT_U(OP, FN) \
146
+ DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
147
+ DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \
148
+ DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
149
+#define DO_2SHIFT_SAT_S(OP, FN) \
150
+ DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \
151
+ DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \
152
+ DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
153
+
154
+DO_2SHIFT_U(vshli_u, DO_VSHLU)
155
+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
156
+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
157
+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
158
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
159
index XXXXXXX..XXXXXXX 100644
160
--- a/target/arm/translate-mve.c
161
+++ b/target/arm/translate-mve.c
162
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
163
typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
164
typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
165
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
166
+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
167
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
168
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
169
typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
170
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
85
}
171
}
86
- mem_off = reg_off >> diffsz;
172
return do_1imm(s, a, fn);
87
173
}
88
- /*
174
+
89
- * If the (remaining) load is entirely within a single page, then:
175
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
90
- * For softmmu, and the tlb hits, then no faults will occur;
176
+ bool negateshift)
91
- * For user-only, either the first load will fault or none will.
177
+{
92
- * We can thus perform the load directly to the destination and
178
+ TCGv_ptr qd, qm;
93
- * Vd will be unmodified on any exception path.
179
+ int shift = a->shift;
94
- */
180
+
95
- split = max_for_page(addr, mem_off, mem_max);
181
+ if (!dc_isar_feature(aa32_mve, s) ||
96
- if (likely(split == mem_max)) {
182
+ !mve_check_qreg_bank(s, a->qd | a->qm) ||
97
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
183
+ !fn) {
98
- if (test_host_page(host)) {
184
+ return false;
99
- intptr_t i = reg_off;
185
+ }
100
- host -= mem_off;
186
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
101
- do {
187
+ return true;
102
- host_fn(vd, i, host + (i >> diffsz));
103
- i = find_next_active(vg, i + (1 << esz), reg_max, esz);
104
- } while (i < reg_max);
105
- /* After having taken any fault, zero leading inactive elements. */
106
- swap_memzero(vd, reg_off);
107
- return;
108
- }
109
- }
110
+ /* Probe the page(s). Exit with exception for any invalid page. */
111
+ sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, retaddr);
112
113
- /*
114
- * Perform the predicated read into a temporary, thus ensuring
115
- * if the load of the last element faults, Vd is not modified.
116
- */
117
+ flags = info.page[0].flags | info.page[1].flags;
118
+ if (unlikely(flags != 0)) {
119
#ifdef CONFIG_USER_ONLY
120
- swap_memzero(&scratch, reg_off);
121
- host = g2h(addr);
122
- do {
123
- host_fn(&scratch, reg_off, host + (reg_off >> diffsz));
124
- reg_off += 1 << esz;
125
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
126
- } while (reg_off < reg_max);
127
+ g_assert_not_reached();
128
#else
129
- memset(&scratch, 0, reg_max);
130
- goto start;
131
- while (1) {
132
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
133
- if (reg_off >= reg_max) {
134
- break;
135
- }
136
- mem_off = reg_off >> diffsz;
137
- split = max_for_page(addr, mem_off, mem_max);
138
+ /*
139
+ * At least one page includes MMIO (or watchpoints).
140
+ * Any bus operation can fail with cpu_transaction_failed,
141
+ * which for ARM will raise SyncExternal. Perform the load
142
+ * into scratch memory to preserve register state until the end.
143
+ */
144
+ ARMVectorReg scratch;
145
146
- start:
147
- if (split - mem_off >= (1 << msz)) {
148
- /* At least one whole element on this page. */
149
- host = tlb_vaddr_to_host(env, addr + mem_off,
150
- MMU_DATA_LOAD, mmu_idx);
151
- if (host) {
152
- host -= mem_off;
153
- do {
154
- host_fn(&scratch, reg_off, host + mem_off);
155
- reg_off += 1 << esz;
156
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
157
- mem_off = reg_off >> diffsz;
158
- } while (split - mem_off >= (1 << msz));
159
- continue;
160
+ memset(&scratch, 0, reg_max);
161
+ mem_off = info.mem_off_first[0];
162
+ reg_off = info.reg_off_first[0];
163
+ reg_last = info.reg_off_last[1];
164
+ if (reg_last < 0) {
165
+ reg_last = info.reg_off_split;
166
+ if (reg_last < 0) {
167
+ reg_last = info.reg_off_last[0];
168
}
169
}
170
171
- /*
172
- * Perform one normal read. This may fault, longjmping out to the
173
- * main loop in order to raise an exception. It may succeed, and
174
- * as a side-effect load the TLB entry for the next round. Finally,
175
- * in the extremely unlikely case we're performing this operation
176
- * on I/O memory, it may succeed but not bring in the TLB entry.
177
- * But even then we have still made forward progress.
178
- */
179
- tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
180
- reg_off += 1 << esz;
181
- }
182
-#endif
183
+ do {
184
+ uint64_t pg = vg[reg_off >> 6];
185
+ do {
186
+ if ((pg >> (reg_off & 63)) & 1) {
187
+ tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
188
+ }
189
+ reg_off += 1 << esz;
190
+ mem_off += 1 << msz;
191
+ } while (reg_off & 63);
192
+ } while (reg_off <= reg_last);
193
194
- memcpy(vd, &scratch, reg_max);
195
+ memcpy(vd, &scratch, reg_max);
196
+ return;
197
+#endif
198
+ }
199
+
200
+ /* The entire operation is in RAM, on valid pages. */
201
+
202
+ memset(vd, 0, reg_max);
203
+ mem_off = info.mem_off_first[0];
204
+ reg_off = info.reg_off_first[0];
205
+ reg_last = info.reg_off_last[0];
206
+ host = info.page[0].host;
207
+
208
+ while (reg_off <= reg_last) {
209
+ uint64_t pg = vg[reg_off >> 6];
210
+ do {
211
+ if ((pg >> (reg_off & 63)) & 1) {
212
+ host_fn(vd, reg_off, host + mem_off);
213
+ }
214
+ reg_off += 1 << esz;
215
+ mem_off += 1 << msz;
216
+ } while (reg_off <= reg_last && (reg_off & 63));
217
+ }
188
+ }
218
+
189
+
219
+ /*
190
+ /*
220
+ * Use the slow path to manage the cross-page misalignment.
191
+ * When we handle a right shift insn using a left-shift helper
221
+ * But we know this is RAM and cannot trap.
192
+ * which permits a negative shift count to indicate a right-shift,
193
+ * we must negate the shift count.
222
+ */
194
+ */
223
+ mem_off = info.mem_off_split;
195
+ if (negateshift) {
224
+ if (unlikely(mem_off >= 0)) {
196
+ shift = -shift;
225
+ tlb_fn(env, vd, info.reg_off_split, addr + mem_off, retaddr);
197
+ }
226
+ }
198
+
227
+
199
+ qd = mve_qreg_ptr(a->qd);
228
+ mem_off = info.mem_off_first[1];
200
+ qm = mve_qreg_ptr(a->qm);
229
+ if (unlikely(mem_off >= 0)) {
201
+ fn(cpu_env, qd, qm, tcg_constant_i32(shift));
230
+ reg_off = info.reg_off_first[1];
202
+ tcg_temp_free_ptr(qd);
231
+ reg_last = info.reg_off_last[1];
203
+ tcg_temp_free_ptr(qm);
232
+ host = info.page[1].host;
204
+ mve_update_eci(s);
233
+
205
+ return true;
234
+ do {
206
+}
235
+ uint64_t pg = vg[reg_off >> 6];
207
+
236
+ do {
208
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \
237
+ if ((pg >> (reg_off & 63)) & 1) {
209
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
238
+ host_fn(vd, reg_off, host + mem_off);
210
+ { \
239
+ }
211
+ static MVEGenTwoOpShiftFn * const fns[] = { \
240
+ reg_off += 1 << esz;
212
+ gen_helper_mve_##FN##b, \
241
+ mem_off += 1 << msz;
213
+ gen_helper_mve_##FN##h, \
242
+ } while (reg_off & 63);
214
+ gen_helper_mve_##FN##w, \
243
+ } while (reg_off <= reg_last);
215
+ NULL, \
244
+ }
216
+ }; \
245
}
217
+ return do_2shift(s, a, fns[a->size], NEGATESHIFT); \
246
218
+ }
247
#define DO_LD1_1(NAME, ESZ) \
219
+
220
+DO_2SHIFT(VSHLI, vshli_u, false)
221
+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
222
+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
223
+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
248
--
224
--
249
2.20.1
225
2.20.1
250
226
251
227
diff view generated by jsdifflib
[PULL 28/34] target/arm: Make set_feature() available for other files
[PULL 14/24] target/arm: Implement MVE vector shift right by immediate insns
1
From: Thomas Huth <thuth@redhat.com>
1
Implement the MVE vector shift right by immediate insns VSHRI and
2
VRSHRI. As with Neon, we implement these by using helper functions
3
which perform left shifts but allow negative shift counts to indicate
4
right shifts.
2
5
3
Move the common set_feature() and unset_feature() functions
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
from cpu.c and cpu64.c to cpu.h.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
9
---
10
target/arm/helper-mve.h | 12 ++++++++++++
11
target/arm/translate.h | 20 ++++++++++++++++++++
12
target/arm/mve.decode | 28 ++++++++++++++++++++++++++++
13
target/arm/mve_helper.c | 7 +++++++
14
target/arm/translate-mve.c | 5 +++++
15
target/arm/translate-neon.c | 18 ------------------
16
6 files changed, 72 insertions(+), 18 deletions(-)
5
17
6
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
7
Signed-off-by: Thomas Huth <thuth@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20200504172448.9402-3-philmd@redhat.com
12
Message-ID: <20190921150420.30743-2-thuth@redhat.com>
13
[PMD: Split Thomas's patch in two: set_feature, cpu_register]
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/cpu.h | 10 ++++++++++
18
target/arm/cpu.c | 10 ----------
19
target/arm/cpu64.c | 10 ----------
20
3 files changed, 10 insertions(+), 20 deletions(-)
21
22
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
23
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/cpu.h
20
--- a/target/arm/helper-mve.h
25
+++ b/target/arm/cpu.h
21
+++ b/target/arm/helper-mve.h
26
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
27
void *gicv3state;
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
28
} CPUARMState;
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
29
25
30
+static inline void set_feature(CPUARMState *env, int feature)
26
+DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+
30
DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+
42
+DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
45
diff --git a/target/arm/translate.h b/target/arm/translate.h
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/translate.h
48
+++ b/target/arm/translate.h
49
@@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x)
50
return x * 2 + 1;
51
}
52
53
+static inline int rsub_64(DisasContext *s, int x)
31
+{
54
+{
32
+ env->features |= 1ULL << feature;
55
+ return 64 - x;
33
+}
56
+}
34
+
57
+
35
+static inline void unset_feature(CPUARMState *env, int feature)
58
+static inline int rsub_32(DisasContext *s, int x)
36
+{
59
+{
37
+ env->features &= ~(1ULL << feature);
60
+ return 32 - x;
38
+}
61
+}
39
+
62
+
40
/**
63
+static inline int rsub_16(DisasContext *s, int x)
41
* ARMELChangeHookFn:
64
+{
42
* type of a function which can be registered via arm_register_el_change_hook()
65
+ return 16 - x;
43
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
66
+}
67
+
68
+static inline int rsub_8(DisasContext *s, int x)
69
+{
70
+ return 8 - x;
71
+}
72
+
73
static inline int arm_dc_feature(DisasContext *dc, int feature)
74
{
75
return (dc->features & (1ULL << feature)) != 0;
76
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
44
index XXXXXXX..XXXXXXX 100644
77
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/cpu.c
78
--- a/target/arm/mve.decode
46
+++ b/target/arm/cpu.c
79
+++ b/target/arm/mve.decode
47
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
80
@@ -XXX,XX +XXX,XX @@
48
81
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
49
#endif
82
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
50
83
51
-static inline void set_feature(CPUARMState *env, int feature)
84
+# Right shifts are encoded as N - shift, where N is the element size in bits.
85
+%rshift_i5 16:5 !function=rsub_32
86
+%rshift_i4 16:4 !function=rsub_16
87
+%rshift_i3 16:3 !function=rsub_8
88
+
89
+@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \
90
+ size=0 shift=%rshift_i3
91
+@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \
92
+ size=1 shift=%rshift_i4
93
+@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
94
+ size=2 shift=%rshift_i5
95
+
96
# Vector loads and stores
97
98
# Widening loads and narrowing stores:
99
@@ -XXX,XX +XXX,XX @@ VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
100
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
101
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
102
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
103
+
104
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
105
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
106
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
107
+
108
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
109
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
110
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
111
+
112
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
113
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
114
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
115
+
116
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
117
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
118
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
119
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/target/arm/mve_helper.c
122
+++ b/target/arm/mve_helper.c
123
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
124
DO_2SHIFT(OP##b, 1, uint8_t, FN) \
125
DO_2SHIFT(OP##h, 2, uint16_t, FN) \
126
DO_2SHIFT(OP##w, 4, uint32_t, FN)
127
+#define DO_2SHIFT_S(OP, FN) \
128
+ DO_2SHIFT(OP##b, 1, int8_t, FN) \
129
+ DO_2SHIFT(OP##h, 2, int16_t, FN) \
130
+ DO_2SHIFT(OP##w, 4, int32_t, FN)
131
132
#define DO_2SHIFT_SAT_U(OP, FN) \
133
DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
134
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
135
DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
136
137
DO_2SHIFT_U(vshli_u, DO_VSHLU)
138
+DO_2SHIFT_S(vshli_s, DO_VSHLS)
139
DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
140
DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
141
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
142
+DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
143
+DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
144
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
145
index XXXXXXX..XXXXXXX 100644
146
--- a/target/arm/translate-mve.c
147
+++ b/target/arm/translate-mve.c
148
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false)
149
DO_2SHIFT(VQSHLI_S, vqshli_s, false)
150
DO_2SHIFT(VQSHLI_U, vqshli_u, false)
151
DO_2SHIFT(VQSHLUI, vqshlui_s, false)
152
+/* These right shifts use a left-shift helper with negated shift count */
153
+DO_2SHIFT(VSHRI_S, vshli_s, true)
154
+DO_2SHIFT(VSHRI_U, vshli_u, true)
155
+DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
+DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
158
index XXXXXXX..XXXXXXX 100644
159
--- a/target/arm/translate-neon.c
160
+++ b/target/arm/translate-neon.c
161
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
162
return x + 1;
163
}
164
165
-static inline int rsub_64(DisasContext *s, int x)
52
-{
166
-{
53
- env->features |= 1ULL << feature;
167
- return 64 - x;
54
-}
168
-}
55
-
169
-
56
-static inline void unset_feature(CPUARMState *env, int feature)
170
-static inline int rsub_32(DisasContext *s, int x)
57
-{
171
-{
58
- env->features &= ~(1ULL << feature);
172
- return 32 - x;
173
-}
174
-static inline int rsub_16(DisasContext *s, int x)
175
-{
176
- return 16 - x;
177
-}
178
-static inline int rsub_8(DisasContext *s, int x)
179
-{
180
- return 8 - x;
59
-}
181
-}
60
-
182
-
61
static int
183
static inline int neon_3same_fp_size(DisasContext *s, int x)
62
print_insn_thumb1(bfd_vma pc, disassemble_info *info)
63
{
184
{
64
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
185
/* Convert 0==fp32, 1==fp16 into a MO_* value */
65
index XXXXXXX..XXXXXXX 100644
66
--- a/target/arm/cpu64.c
67
+++ b/target/arm/cpu64.c
68
@@ -XXX,XX +XXX,XX @@
69
#include "kvm_arm.h"
70
#include "qapi/visitor.h"
71
72
-static inline void set_feature(CPUARMState *env, int feature)
73
-{
74
- env->features |= 1ULL << feature;
75
-}
76
-
77
-static inline void unset_feature(CPUARMState *env, int feature)
78
-{
79
- env->features &= ~(1ULL << feature);
80
-}
81
-
82
#ifndef CONFIG_USER_ONLY
83
static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
84
{
85
--
186
--
86
2.20.1
187
2.20.1
87
188
88
189
diff view generated by jsdifflib
[PULL 13/34] accel/tcg: Add endian-specific cpu_{ld, st}* operations
[PULL 15/24] target/arm: Implement MVE VSHLL
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the MVE VHLL (vector shift left long) insn. This has two
2
encodings: the T1 encoding is the usual shift-by-immediate format,
3
and the T2 encoding is a special case where the shift count is always
4
equal to the element size.
2
5
3
We currently have target-endian versions of these operations,
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
but no easy way to force a specific endianness. This can be
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
helpful if the target has endian-specific operations, or a mode
8
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
6
that swaps endianness.
9
---
10
target/arm/helper-mve.h | 9 +++++++
11
target/arm/mve.decode | 53 +++++++++++++++++++++++++++++++++++---
12
target/arm/mve_helper.c | 32 +++++++++++++++++++++++
13
target/arm/translate-mve.c | 15 +++++++++++
14
4 files changed, 105 insertions(+), 4 deletions(-)
7
15
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-7-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
docs/devel/loads-stores.rst | 39 +++--
14
include/exec/cpu_ldst.h | 283 +++++++++++++++++++++++++++---------
15
accel/tcg/cputlb.c | 236 ++++++++++++++++++++++--------
16
accel/tcg/user-exec.c | 211 ++++++++++++++++++++++-----
17
4 files changed, 587 insertions(+), 182 deletions(-)
18
19
diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst
20
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
21
--- a/docs/devel/loads-stores.rst
18
--- a/target/arm/helper-mve.h
22
+++ b/docs/devel/loads-stores.rst
19
+++ b/target/arm/helper-mve.h
23
@@ -XXX,XX +XXX,XX @@ function, which is a return address into the generated code.
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
21
DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
Function names follow the pattern:
22
DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
23
DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
-load: ``cpu_ld{sign}{size}_mmuidx_ra(env, ptr, mmuidx, retaddr)``
28
+load: ``cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmuidx, retaddr)``
29
30
-store: ``cpu_st{size}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
31
+store: ``cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
32
33
``sign``
34
- (empty) : for 32 or 64 bit sizes
35
@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
36
- ``l`` : 32 bits
37
- ``q`` : 64 bits
38
39
+``end``
40
+ - (empty) : for target endian, or 8 bit sizes
41
+ - ``_be`` : big endian
42
+ - ``_le`` : little endian
43
+
24
+
44
Regexes for git grep:
25
+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
45
- - ``\<cpu_ld[us]\?[bwlq]_mmuidx_ra\>``
26
+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
46
- - ``\<cpu_st[bwlq]_mmuidx_ra\>``
27
+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
47
+ - ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_mmuidx_ra\>``
28
+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
48
+ - ``\<cpu_st[bwlq](_[bl]e)\?_mmuidx_ra\>``
29
+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
49
30
+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
50
``cpu_{ld,st}*_data_ra``
31
+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
51
~~~~~~~~~~~~~~~~~~~~~~~~
32
+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
52
@@ -XXX,XX +XXX,XX @@ be performed with a context other than the default.
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
53
34
index XXXXXXX..XXXXXXX 100644
54
Function names follow the pattern:
35
--- a/target/arm/mve.decode
55
36
+++ b/target/arm/mve.decode
56
-load: ``cpu_ld{sign}{size}_data_ra(env, ptr, ra)``
37
@@ -XXX,XX +XXX,XX @@
57
+load: ``cpu_ld{sign}{size}{end}_data_ra(env, ptr, ra)``
38
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
58
39
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
59
-store: ``cpu_st{size}_data_ra(env, ptr, val, ra)``
40
60
+store: ``cpu_st{size}{end}_data_ra(env, ptr, val, ra)``
41
+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
61
42
+@2_shll_h .... .... ... 1 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
62
``sign``
43
+# VSHLL encoding T2 where shift == esize
63
- (empty) : for 32 or 64 bit sizes
44
+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
64
@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}_data_ra(env, ptr, val, ra)``
45
+ qd=%qd qm=%qm size=0 shift=8
65
- ``l`` : 32 bits
46
+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
66
- ``q`` : 64 bits
47
+ qd=%qd qm=%qm size=1 shift=16
67
68
+``end``
69
+ - (empty) : for target endian, or 8 bit sizes
70
+ - ``_be`` : big endian
71
+ - ``_le`` : little endian
72
+
48
+
73
Regexes for git grep:
49
# Right shifts are encoded as N - shift, where N is the element size in bits.
74
- - ``\<cpu_ld[us]\?[bwlq]_data_ra\>``
50
%rshift_i5 16:5 !function=rsub_32
75
- - ``\<cpu_st[bwlq]_data_ra\>``
51
%rshift_i4 16:4 !function=rsub_16
76
+ - ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_data_ra\>``
52
@@ -XXX,XX +XXX,XX @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
77
+ - ``\<cpu_st[bwlq](_[bl]e)\?_data_ra\>``
53
VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
78
54
VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
79
``cpu_{ld,st}*_data``
55
80
~~~~~~~~~~~~~~~~~~~~~
56
-VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
81
@@ -XXX,XX +XXX,XX @@ the CPU state anyway.
57
-VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
82
58
+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
83
Function names follow the pattern:
59
+# overlaps what would be size=0b11 VMULH/VRMULH
84
60
+{
85
-load: ``cpu_ld{sign}{size}_data(env, ptr)``
61
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
86
+load: ``cpu_ld{sign}{size}{end}_data(env, ptr)``
62
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
87
63
88
-store: ``cpu_st{size}_data(env, ptr, val)``
64
-VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
89
+store: ``cpu_st{size}{end}_data(env, ptr, val)``
65
-VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
90
66
+ VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
91
``sign``
92
- (empty) : for 32 or 64 bit sizes
93
@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}_data(env, ptr, val)``
94
- ``l`` : 32 bits
95
- ``q`` : 64 bits
96
97
+``end``
98
+ - (empty) : for target endian, or 8 bit sizes
99
+ - ``_be`` : big endian
100
+ - ``_le`` : little endian
101
+
102
Regexes for git grep
103
- - ``\<cpu_ld[us]\?[bwlq]_data\>``
104
- - ``\<cpu_st[bwlq]_data\+\>``
105
+ - ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_data\>``
106
+ - ``\<cpu_st[bwlq](_[bl]e)\?_data\+\>``
107
108
``cpu_ld*_code``
109
~~~~~~~~~~~~~~~~
110
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
111
index XXXXXXX..XXXXXXX 100644
112
--- a/include/exec/cpu_ldst.h
113
+++ b/include/exec/cpu_ldst.h
114
@@ -XXX,XX +XXX,XX @@
115
*
116
* The syntax for the accessors is:
117
*
118
- * load: cpu_ld{sign}{size}_{mmusuffix}(env, ptr)
119
- * cpu_ld{sign}{size}_{mmusuffix}_ra(env, ptr, retaddr)
120
- * cpu_ld{sign}{size}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
121
+ * load: cpu_ld{sign}{size}{end}_{mmusuffix}(env, ptr)
122
+ * cpu_ld{sign}{size}{end}_{mmusuffix}_ra(env, ptr, retaddr)
123
+ * cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
124
*
125
- * store: cpu_st{size}_{mmusuffix}(env, ptr, val)
126
- * cpu_st{size}_{mmusuffix}_ra(env, ptr, val, retaddr)
127
- * cpu_st{size}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
128
+ * store: cpu_st{size}{end}_{mmusuffix}(env, ptr, val)
129
+ * cpu_st{size}{end}_{mmusuffix}_ra(env, ptr, val, retaddr)
130
+ * cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
131
*
132
* sign is:
133
* (empty): for 32 and 64 bit sizes
134
@@ -XXX,XX +XXX,XX @@
135
* l: 32 bits
136
* q: 64 bits
137
*
138
+ * end is:
139
+ * (empty): for target native endian, or for 8 bit access
140
+ * _be: for forced big endian
141
+ * _le: for forced little endian
142
+ *
143
* mmusuffix is one of the generic suffixes "data" or "code", or "mmuidx".
144
* The "mmuidx" suffix carries an extra mmu_idx argument that specifies
145
* the index to use; the "data" and "code" suffixes take the index from
146
@@ -XXX,XX +XXX,XX @@ typedef target_ulong abi_ptr;
147
#endif
148
149
uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
150
-uint32_t cpu_lduw_data(CPUArchState *env, abi_ptr ptr);
151
-uint32_t cpu_ldl_data(CPUArchState *env, abi_ptr ptr);
152
-uint64_t cpu_ldq_data(CPUArchState *env, abi_ptr ptr);
153
int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr);
154
-int cpu_ldsw_data(CPUArchState *env, abi_ptr ptr);
155
156
-uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
157
-uint32_t cpu_lduw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
158
-uint32_t cpu_ldl_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
159
-uint64_t cpu_ldq_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
160
-int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
161
-int cpu_ldsw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
162
+uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr);
163
+int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr);
164
+uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr);
165
+uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr);
166
+
167
+uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr);
168
+int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr);
169
+uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr);
170
+uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr);
171
+
172
+uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
173
+int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
174
+
175
+uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
176
+int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
177
+uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
178
+uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
179
+
180
+uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
181
+int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
182
+uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
183
+uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
184
185
void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
186
-void cpu_stw_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
187
-void cpu_stl_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
188
-void cpu_stq_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
189
+
190
+void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
191
+void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
192
+void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
193
+
194
+void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
195
+void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
196
+void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
197
198
void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
199
- uint32_t val, uintptr_t retaddr);
200
-void cpu_stw_data_ra(CPUArchState *env, abi_ptr ptr,
201
- uint32_t val, uintptr_t retaddr);
202
-void cpu_stl_data_ra(CPUArchState *env, abi_ptr ptr,
203
- uint32_t val, uintptr_t retaddr);
204
-void cpu_stq_data_ra(CPUArchState *env, abi_ptr ptr,
205
- uint64_t val, uintptr_t retaddr);
206
+ uint32_t val, uintptr_t ra);
207
+
208
+void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
209
+ uint32_t val, uintptr_t ra);
210
+void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
211
+ uint32_t val, uintptr_t ra);
212
+void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
213
+ uint64_t val, uintptr_t ra);
214
+
215
+void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
216
+ uint32_t val, uintptr_t ra);
217
+void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
218
+ uint32_t val, uintptr_t ra);
219
+void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
220
+ uint64_t val, uintptr_t ra);
221
222
#if defined(CONFIG_USER_ONLY)
223
224
@@ -XXX,XX +XXX,XX @@ static inline uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
225
return cpu_ldub_data_ra(env, addr, ra);
226
}
227
228
-static inline uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
229
- int mmu_idx, uintptr_t ra)
230
-{
231
- return cpu_lduw_data_ra(env, addr, ra);
232
-}
233
-
234
-static inline uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
235
- int mmu_idx, uintptr_t ra)
236
-{
237
- return cpu_ldl_data_ra(env, addr, ra);
238
-}
239
-
240
-static inline uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
241
- int mmu_idx, uintptr_t ra)
242
-{
243
- return cpu_ldq_data_ra(env, addr, ra);
244
-}
245
-
246
static inline int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
247
int mmu_idx, uintptr_t ra)
248
{
249
return cpu_ldsb_data_ra(env, addr, ra);
250
}
251
252
-static inline int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
253
- int mmu_idx, uintptr_t ra)
254
+static inline uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
255
+ int mmu_idx, uintptr_t ra)
256
{
257
- return cpu_ldsw_data_ra(env, addr, ra);
258
+ return cpu_lduw_be_data_ra(env, addr, ra);
259
+}
67
+}
260
+
68
+
261
+static inline int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
262
+ int mmu_idx, uintptr_t ra)
263
+{
69
+{
264
+ return cpu_ldsw_be_data_ra(env, addr, ra);
70
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
71
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
72
+
73
+ VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
265
+}
74
+}
266
+
75
+
267
+static inline uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
268
+ int mmu_idx, uintptr_t ra)
269
+{
76
+{
270
+ return cpu_ldl_be_data_ra(env, addr, ra);
77
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
78
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
79
+
80
+ VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
271
+}
81
+}
272
+
82
+
273
+static inline uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
274
+ int mmu_idx, uintptr_t ra)
275
+{
83
+{
276
+ return cpu_ldq_be_data_ra(env, addr, ra);
84
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
85
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
86
+
87
+ VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
277
+}
88
+}
89
90
VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
91
VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
92
@@ -XXX,XX +XXX,XX @@ VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
93
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
94
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
95
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
278
+
96
+
279
+static inline uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
97
+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
280
+ int mmu_idx, uintptr_t ra)
98
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
281
+{
99
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
282
+ return cpu_lduw_le_data_ra(env, addr, ra);
283
+}
284
+
100
+
285
+static inline int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
101
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
286
+ int mmu_idx, uintptr_t ra)
102
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
287
+{
288
+ return cpu_ldsw_le_data_ra(env, addr, ra);
289
+}
290
+
103
+
291
+static inline uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
104
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
292
+ int mmu_idx, uintptr_t ra)
105
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
293
+{
294
+ return cpu_ldl_le_data_ra(env, addr, ra);
295
+}
296
+
106
+
297
+static inline uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
107
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
298
+ int mmu_idx, uintptr_t ra)
108
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
299
+{
109
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
300
+ return cpu_ldq_le_data_ra(env, addr, ra);
110
index XXXXXXX..XXXXXXX 100644
301
}
111
--- a/target/arm/mve_helper.c
302
112
+++ b/target/arm/mve_helper.c
303
static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
113
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
304
@@ -XXX,XX +XXX,XX @@ static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
114
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
305
cpu_stb_data_ra(env, addr, val, ra);
115
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
306
}
116
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
307
308
-static inline void cpu_stw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
309
- uint32_t val, int mmu_idx, uintptr_t ra)
310
+static inline void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
311
+ uint32_t val, int mmu_idx,
312
+ uintptr_t ra)
313
{
314
- cpu_stw_data_ra(env, addr, val, ra);
315
+ cpu_stw_be_data_ra(env, addr, val, ra);
316
}
317
318
-static inline void cpu_stl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
319
- uint32_t val, int mmu_idx, uintptr_t ra)
320
+static inline void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
321
+ uint32_t val, int mmu_idx,
322
+ uintptr_t ra)
323
{
324
- cpu_stl_data_ra(env, addr, val, ra);
325
+ cpu_stl_be_data_ra(env, addr, val, ra);
326
}
327
328
-static inline void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
329
- uint64_t val, int mmu_idx, uintptr_t ra)
330
+static inline void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
331
+ uint64_t val, int mmu_idx,
332
+ uintptr_t ra)
333
{
334
- cpu_stq_data_ra(env, addr, val, ra);
335
+ cpu_stq_be_data_ra(env, addr, val, ra);
336
+}
337
+
117
+
338
+static inline void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
118
+/*
339
+ uint32_t val, int mmu_idx,
119
+ * Long shifts taking half-sized inputs from top or bottom of the input
340
+ uintptr_t ra)
120
+ * vector and producing a double-width result. ESIZE, TYPE are for
341
+{
121
+ * the input, and LESIZE, LTYPE for the output.
342
+ cpu_stw_le_data_ra(env, addr, val, ra);
122
+ * Unlike the normal shift helpers, we do not handle negative shift counts,
343
+}
123
+ * because the long shift is strictly left-only.
124
+ */
125
+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \
126
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
127
+ void *vm, uint32_t shift) \
128
+ { \
129
+ LTYPE *d = vd; \
130
+ TYPE *m = vm; \
131
+ uint16_t mask = mve_element_mask(env); \
132
+ unsigned le; \
133
+ assert(shift <= 16); \
134
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
135
+ LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \
136
+ mergemask(&d[H##LESIZE(le)], r, mask); \
137
+ } \
138
+ mve_advance_vpt(env); \
139
+ }
344
+
140
+
345
+static inline void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
141
+#define DO_VSHLL_ALL(OP, TOP) \
346
+ uint32_t val, int mmu_idx,
142
+ DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \
347
+ uintptr_t ra)
143
+ DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \
348
+{
144
+ DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \
349
+ cpu_stl_le_data_ra(env, addr, val, ra);
145
+ DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \
350
+}
351
+
146
+
352
+static inline void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
147
+DO_VSHLL_ALL(vshllb, false)
353
+ uint64_t val, int mmu_idx,
148
+DO_VSHLL_ALL(vshllt, true)
354
+ uintptr_t ra)
149
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
355
+{
150
index XXXXXXX..XXXXXXX 100644
356
+ cpu_stq_le_data_ra(env, addr, val, ra);
151
--- a/target/arm/translate-mve.c
357
}
152
+++ b/target/arm/translate-mve.c
358
153
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
359
#else
154
DO_2SHIFT(VSHRI_U, vshli_u, true)
360
@@ -XXX,XX +XXX,XX @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
155
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
361
156
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
362
uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
363
int mmu_idx, uintptr_t ra);
364
-uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
365
- int mmu_idx, uintptr_t ra);
366
-uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
367
- int mmu_idx, uintptr_t ra);
368
-uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
369
- int mmu_idx, uintptr_t ra);
370
-
371
int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
372
int mmu_idx, uintptr_t ra);
373
-int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
374
- int mmu_idx, uintptr_t ra);
375
+
157
+
376
+uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
158
+#define DO_VSHLL(INSN, FN) \
377
+ int mmu_idx, uintptr_t ra);
159
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
378
+int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
160
+ { \
379
+ int mmu_idx, uintptr_t ra);
161
+ static MVEGenTwoOpShiftFn * const fns[] = { \
380
+uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
162
+ gen_helper_mve_##FN##b, \
381
+ int mmu_idx, uintptr_t ra);
163
+ gen_helper_mve_##FN##h, \
382
+uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
164
+ }; \
383
+ int mmu_idx, uintptr_t ra);
165
+ return do_2shift(s, a, fns[a->size], false); \
166
+ }
384
+
167
+
385
+uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
168
+DO_VSHLL(VSHLL_BS, vshllbs)
386
+ int mmu_idx, uintptr_t ra);
169
+DO_VSHLL(VSHLL_BU, vshllbu)
387
+int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
170
+DO_VSHLL(VSHLL_TS, vshllts)
388
+ int mmu_idx, uintptr_t ra);
171
+DO_VSHLL(VSHLL_TU, vshlltu)
389
+uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
390
+ int mmu_idx, uintptr_t ra);
391
+uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
392
+ int mmu_idx, uintptr_t ra);
393
394
void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
395
int mmu_idx, uintptr_t retaddr);
396
-void cpu_stw_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
397
- int mmu_idx, uintptr_t retaddr);
398
-void cpu_stl_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
399
- int mmu_idx, uintptr_t retaddr);
400
-void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
401
- int mmu_idx, uintptr_t retaddr);
402
+
403
+void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
404
+ int mmu_idx, uintptr_t retaddr);
405
+void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
406
+ int mmu_idx, uintptr_t retaddr);
407
+void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
408
+ int mmu_idx, uintptr_t retaddr);
409
+
410
+void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
411
+ int mmu_idx, uintptr_t retaddr);
412
+void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
413
+ int mmu_idx, uintptr_t retaddr);
414
+void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
415
+ int mmu_idx, uintptr_t retaddr);
416
417
#endif /* defined(CONFIG_USER_ONLY) */
418
419
+#ifdef TARGET_WORDS_BIGENDIAN
420
+# define cpu_lduw_data cpu_lduw_be_data
421
+# define cpu_ldsw_data cpu_ldsw_be_data
422
+# define cpu_ldl_data cpu_ldl_be_data
423
+# define cpu_ldq_data cpu_ldq_be_data
424
+# define cpu_lduw_data_ra cpu_lduw_be_data_ra
425
+# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra
426
+# define cpu_ldl_data_ra cpu_ldl_be_data_ra
427
+# define cpu_ldq_data_ra cpu_ldq_be_data_ra
428
+# define cpu_lduw_mmuidx_ra cpu_lduw_be_mmuidx_ra
429
+# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra
430
+# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra
431
+# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra
432
+# define cpu_stw_data cpu_stw_be_data
433
+# define cpu_stl_data cpu_stl_be_data
434
+# define cpu_stq_data cpu_stq_be_data
435
+# define cpu_stw_data_ra cpu_stw_be_data_ra
436
+# define cpu_stl_data_ra cpu_stl_be_data_ra
437
+# define cpu_stq_data_ra cpu_stq_be_data_ra
438
+# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra
439
+# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra
440
+# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra
441
+#else
442
+# define cpu_lduw_data cpu_lduw_le_data
443
+# define cpu_ldsw_data cpu_ldsw_le_data
444
+# define cpu_ldl_data cpu_ldl_le_data
445
+# define cpu_ldq_data cpu_ldq_le_data
446
+# define cpu_lduw_data_ra cpu_lduw_le_data_ra
447
+# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra
448
+# define cpu_ldl_data_ra cpu_ldl_le_data_ra
449
+# define cpu_ldq_data_ra cpu_ldq_le_data_ra
450
+# define cpu_lduw_mmuidx_ra cpu_lduw_le_mmuidx_ra
451
+# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra
452
+# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra
453
+# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra
454
+# define cpu_stw_data cpu_stw_le_data
455
+# define cpu_stl_data cpu_stl_le_data
456
+# define cpu_stq_data cpu_stq_le_data
457
+# define cpu_stw_data_ra cpu_stw_le_data_ra
458
+# define cpu_stl_data_ra cpu_stl_le_data_ra
459
+# define cpu_stq_data_ra cpu_stq_le_data_ra
460
+# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra
461
+# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra
462
+# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra
463
+#endif
464
+
465
uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
466
uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr);
467
uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr);
468
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
469
index XXXXXXX..XXXXXXX 100644
470
--- a/accel/tcg/cputlb.c
471
+++ b/accel/tcg/cputlb.c
472
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
473
full_ldub_mmu);
474
}
475
476
-uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
477
- int mmu_idx, uintptr_t ra)
478
+uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
479
+ int mmu_idx, uintptr_t ra)
480
{
481
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_TEUW,
482
- MO_TE == MO_LE
483
- ? full_le_lduw_mmu : full_be_lduw_mmu);
484
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUW, full_be_lduw_mmu);
485
}
486
487
-int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
488
- int mmu_idx, uintptr_t ra)
489
+int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
490
+ int mmu_idx, uintptr_t ra)
491
{
492
- return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_TESW,
493
- MO_TE == MO_LE
494
- ? full_le_lduw_mmu : full_be_lduw_mmu);
495
+ return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_BESW,
496
+ full_be_lduw_mmu);
497
}
498
499
-uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
500
- int mmu_idx, uintptr_t ra)
501
+uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
502
+ int mmu_idx, uintptr_t ra)
503
{
504
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_TEUL,
505
- MO_TE == MO_LE
506
- ? full_le_ldul_mmu : full_be_ldul_mmu);
507
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUL, full_be_ldul_mmu);
508
}
509
510
-uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
511
- int mmu_idx, uintptr_t ra)
512
+uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
513
+ int mmu_idx, uintptr_t ra)
514
{
515
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_TEQ,
516
- MO_TE == MO_LE
517
- ? helper_le_ldq_mmu : helper_be_ldq_mmu);
518
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEQ, helper_be_ldq_mmu);
519
+}
520
+
521
+uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
522
+ int mmu_idx, uintptr_t ra)
523
+{
524
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUW, full_le_lduw_mmu);
525
+}
526
+
527
+int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
528
+ int mmu_idx, uintptr_t ra)
529
+{
530
+ return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_LESW,
531
+ full_le_lduw_mmu);
532
+}
533
+
534
+uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
535
+ int mmu_idx, uintptr_t ra)
536
+{
537
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUL, full_le_ldul_mmu);
538
+}
539
+
540
+uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
541
+ int mmu_idx, uintptr_t ra)
542
+{
543
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEQ, helper_le_ldq_mmu);
544
}
545
546
uint32_t cpu_ldub_data_ra(CPUArchState *env, target_ulong ptr,
547
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
548
return cpu_ldsb_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
549
}
550
551
-uint32_t cpu_lduw_data_ra(CPUArchState *env, target_ulong ptr,
552
- uintptr_t retaddr)
553
+uint32_t cpu_lduw_be_data_ra(CPUArchState *env, target_ulong ptr,
554
+ uintptr_t retaddr)
555
{
556
- return cpu_lduw_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
557
+ return cpu_lduw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
558
}
559
560
-int cpu_ldsw_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
561
+int cpu_ldsw_be_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
562
{
563
- return cpu_ldsw_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
564
+ return cpu_ldsw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
565
}
566
567
-uint32_t cpu_ldl_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
568
+uint32_t cpu_ldl_be_data_ra(CPUArchState *env, target_ulong ptr,
569
+ uintptr_t retaddr)
570
{
571
- return cpu_ldl_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
572
+ return cpu_ldl_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
573
}
574
575
-uint64_t cpu_ldq_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
576
+uint64_t cpu_ldq_be_data_ra(CPUArchState *env, target_ulong ptr,
577
+ uintptr_t retaddr)
578
{
579
- return cpu_ldq_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
580
+ return cpu_ldq_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
581
+}
582
+
583
+uint32_t cpu_lduw_le_data_ra(CPUArchState *env, target_ulong ptr,
584
+ uintptr_t retaddr)
585
+{
586
+ return cpu_lduw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
587
+}
588
+
589
+int cpu_ldsw_le_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
590
+{
591
+ return cpu_ldsw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
592
+}
593
+
594
+uint32_t cpu_ldl_le_data_ra(CPUArchState *env, target_ulong ptr,
595
+ uintptr_t retaddr)
596
+{
597
+ return cpu_ldl_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
598
+}
599
+
600
+uint64_t cpu_ldq_le_data_ra(CPUArchState *env, target_ulong ptr,
601
+ uintptr_t retaddr)
602
+{
603
+ return cpu_ldq_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
604
}
605
606
uint32_t cpu_ldub_data(CPUArchState *env, target_ulong ptr)
607
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data(CPUArchState *env, target_ulong ptr)
608
return cpu_ldsb_data_ra(env, ptr, 0);
609
}
610
611
-uint32_t cpu_lduw_data(CPUArchState *env, target_ulong ptr)
612
+uint32_t cpu_lduw_be_data(CPUArchState *env, target_ulong ptr)
613
{
614
- return cpu_lduw_data_ra(env, ptr, 0);
615
+ return cpu_lduw_be_data_ra(env, ptr, 0);
616
}
617
618
-int cpu_ldsw_data(CPUArchState *env, target_ulong ptr)
619
+int cpu_ldsw_be_data(CPUArchState *env, target_ulong ptr)
620
{
621
- return cpu_ldsw_data_ra(env, ptr, 0);
622
+ return cpu_ldsw_be_data_ra(env, ptr, 0);
623
}
624
625
-uint32_t cpu_ldl_data(CPUArchState *env, target_ulong ptr)
626
+uint32_t cpu_ldl_be_data(CPUArchState *env, target_ulong ptr)
627
{
628
- return cpu_ldl_data_ra(env, ptr, 0);
629
+ return cpu_ldl_be_data_ra(env, ptr, 0);
630
}
631
632
-uint64_t cpu_ldq_data(CPUArchState *env, target_ulong ptr)
633
+uint64_t cpu_ldq_be_data(CPUArchState *env, target_ulong ptr)
634
{
635
- return cpu_ldq_data_ra(env, ptr, 0);
636
+ return cpu_ldq_be_data_ra(env, ptr, 0);
637
+}
638
+
639
+uint32_t cpu_lduw_le_data(CPUArchState *env, target_ulong ptr)
640
+{
641
+ return cpu_lduw_le_data_ra(env, ptr, 0);
642
+}
643
+
644
+int cpu_ldsw_le_data(CPUArchState *env, target_ulong ptr)
645
+{
646
+ return cpu_ldsw_le_data_ra(env, ptr, 0);
647
+}
648
+
649
+uint32_t cpu_ldl_le_data(CPUArchState *env, target_ulong ptr)
650
+{
651
+ return cpu_ldl_le_data_ra(env, ptr, 0);
652
+}
653
+
654
+uint64_t cpu_ldq_le_data(CPUArchState *env, target_ulong ptr)
655
+{
656
+ return cpu_ldq_le_data_ra(env, ptr, 0);
657
}
658
659
/*
660
@@ -XXX,XX +XXX,XX @@ void cpu_stb_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
661
cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_UB);
662
}
663
664
-void cpu_stw_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
665
- int mmu_idx, uintptr_t retaddr)
666
+void cpu_stw_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
667
+ int mmu_idx, uintptr_t retaddr)
668
{
669
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEUW);
670
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUW);
671
}
672
673
-void cpu_stl_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
674
- int mmu_idx, uintptr_t retaddr)
675
+void cpu_stl_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
676
+ int mmu_idx, uintptr_t retaddr)
677
{
678
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEUL);
679
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUL);
680
}
681
682
-void cpu_stq_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
683
- int mmu_idx, uintptr_t retaddr)
684
+void cpu_stq_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
685
+ int mmu_idx, uintptr_t retaddr)
686
{
687
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEQ);
688
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEQ);
689
+}
690
+
691
+void cpu_stw_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
692
+ int mmu_idx, uintptr_t retaddr)
693
+{
694
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUW);
695
+}
696
+
697
+void cpu_stl_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
698
+ int mmu_idx, uintptr_t retaddr)
699
+{
700
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUL);
701
+}
702
+
703
+void cpu_stq_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
704
+ int mmu_idx, uintptr_t retaddr)
705
+{
706
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEQ);
707
}
708
709
void cpu_stb_data_ra(CPUArchState *env, target_ulong ptr,
710
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data_ra(CPUArchState *env, target_ulong ptr,
711
cpu_stb_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
712
}
713
714
-void cpu_stw_data_ra(CPUArchState *env, target_ulong ptr,
715
- uint32_t val, uintptr_t retaddr)
716
+void cpu_stw_be_data_ra(CPUArchState *env, target_ulong ptr,
717
+ uint32_t val, uintptr_t retaddr)
718
{
719
- cpu_stw_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
720
+ cpu_stw_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
721
}
722
723
-void cpu_stl_data_ra(CPUArchState *env, target_ulong ptr,
724
- uint32_t val, uintptr_t retaddr)
725
+void cpu_stl_be_data_ra(CPUArchState *env, target_ulong ptr,
726
+ uint32_t val, uintptr_t retaddr)
727
{
728
- cpu_stl_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
729
+ cpu_stl_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
730
}
731
732
-void cpu_stq_data_ra(CPUArchState *env, target_ulong ptr,
733
- uint64_t val, uintptr_t retaddr)
734
+void cpu_stq_be_data_ra(CPUArchState *env, target_ulong ptr,
735
+ uint64_t val, uintptr_t retaddr)
736
{
737
- cpu_stq_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
738
+ cpu_stq_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
739
+}
740
+
741
+void cpu_stw_le_data_ra(CPUArchState *env, target_ulong ptr,
742
+ uint32_t val, uintptr_t retaddr)
743
+{
744
+ cpu_stw_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
745
+}
746
+
747
+void cpu_stl_le_data_ra(CPUArchState *env, target_ulong ptr,
748
+ uint32_t val, uintptr_t retaddr)
749
+{
750
+ cpu_stl_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
751
+}
752
+
753
+void cpu_stq_le_data_ra(CPUArchState *env, target_ulong ptr,
754
+ uint64_t val, uintptr_t retaddr)
755
+{
756
+ cpu_stq_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
757
}
758
759
void cpu_stb_data(CPUArchState *env, target_ulong ptr, uint32_t val)
760
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data(CPUArchState *env, target_ulong ptr, uint32_t val)
761
cpu_stb_data_ra(env, ptr, val, 0);
762
}
763
764
-void cpu_stw_data(CPUArchState *env, target_ulong ptr, uint32_t val)
765
+void cpu_stw_be_data(CPUArchState *env, target_ulong ptr, uint32_t val)
766
{
767
- cpu_stw_data_ra(env, ptr, val, 0);
768
+ cpu_stw_be_data_ra(env, ptr, val, 0);
769
}
770
771
-void cpu_stl_data(CPUArchState *env, target_ulong ptr, uint32_t val)
772
+void cpu_stl_be_data(CPUArchState *env, target_ulong ptr, uint32_t val)
773
{
774
- cpu_stl_data_ra(env, ptr, val, 0);
775
+ cpu_stl_be_data_ra(env, ptr, val, 0);
776
}
777
778
-void cpu_stq_data(CPUArchState *env, target_ulong ptr, uint64_t val)
779
+void cpu_stq_be_data(CPUArchState *env, target_ulong ptr, uint64_t val)
780
{
781
- cpu_stq_data_ra(env, ptr, val, 0);
782
+ cpu_stq_be_data_ra(env, ptr, val, 0);
783
+}
784
+
785
+void cpu_stw_le_data(CPUArchState *env, target_ulong ptr, uint32_t val)
786
+{
787
+ cpu_stw_le_data_ra(env, ptr, val, 0);
788
+}
789
+
790
+void cpu_stl_le_data(CPUArchState *env, target_ulong ptr, uint32_t val)
791
+{
792
+ cpu_stl_le_data_ra(env, ptr, val, 0);
793
+}
794
+
795
+void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val)
796
+{
797
+ cpu_stq_le_data_ra(env, ptr, val, 0);
798
}
799
800
/* First set of helpers allows passing in of OI and RETADDR. This makes
801
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
802
index XXXXXXX..XXXXXXX 100644
803
--- a/accel/tcg/user-exec.c
804
+++ b/accel/tcg/user-exec.c
805
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr)
806
return ret;
807
}
808
809
-uint32_t cpu_lduw_data(CPUArchState *env, abi_ptr ptr)
810
+uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr)
811
{
812
uint32_t ret;
813
- uint16_t meminfo = trace_mem_get_info(MO_TEUW, MMU_USER_IDX, false);
814
+ uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, false);
815
816
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
817
- ret = lduw_p(g2h(ptr));
818
+ ret = lduw_be_p(g2h(ptr));
819
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
820
return ret;
821
}
822
823
-int cpu_ldsw_data(CPUArchState *env, abi_ptr ptr)
824
+int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr)
825
{
826
int ret;
827
- uint16_t meminfo = trace_mem_get_info(MO_TESW, MMU_USER_IDX, false);
828
+ uint16_t meminfo = trace_mem_get_info(MO_BESW, MMU_USER_IDX, false);
829
830
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
831
- ret = ldsw_p(g2h(ptr));
832
+ ret = ldsw_be_p(g2h(ptr));
833
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
834
return ret;
835
}
836
837
-uint32_t cpu_ldl_data(CPUArchState *env, abi_ptr ptr)
838
+uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
839
{
840
uint32_t ret;
841
- uint16_t meminfo = trace_mem_get_info(MO_TEUL, MMU_USER_IDX, false);
842
+ uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, false);
843
844
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
845
- ret = ldl_p(g2h(ptr));
846
+ ret = ldl_be_p(g2h(ptr));
847
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
848
return ret;
849
}
850
851
-uint64_t cpu_ldq_data(CPUArchState *env, abi_ptr ptr)
852
+uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr)
853
{
854
uint64_t ret;
855
- uint16_t meminfo = trace_mem_get_info(MO_TEQ, MMU_USER_IDX, false);
856
+ uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, false);
857
858
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
859
- ret = ldq_p(g2h(ptr));
860
+ ret = ldq_be_p(g2h(ptr));
861
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
862
+ return ret;
863
+}
864
+
865
+uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr)
866
+{
867
+ uint32_t ret;
868
+ uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, false);
869
+
870
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
871
+ ret = lduw_le_p(g2h(ptr));
872
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
873
+ return ret;
874
+}
875
+
876
+int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr)
877
+{
878
+ int ret;
879
+ uint16_t meminfo = trace_mem_get_info(MO_LESW, MMU_USER_IDX, false);
880
+
881
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
882
+ ret = ldsw_le_p(g2h(ptr));
883
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
884
+ return ret;
885
+}
886
+
887
+uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
888
+{
889
+ uint32_t ret;
890
+ uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, false);
891
+
892
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
893
+ ret = ldl_le_p(g2h(ptr));
894
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
895
+ return ret;
896
+}
897
+
898
+uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr)
899
+{
900
+ uint64_t ret;
901
+ uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, false);
902
+
903
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
904
+ ret = ldq_le_p(g2h(ptr));
905
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
906
return ret;
907
}
908
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
909
return ret;
910
}
911
912
-uint32_t cpu_lduw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
913
+uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
914
{
915
uint32_t ret;
916
917
set_helper_retaddr(retaddr);
918
- ret = cpu_lduw_data(env, ptr);
919
+ ret = cpu_lduw_be_data(env, ptr);
920
clear_helper_retaddr();
921
return ret;
922
}
923
924
-int cpu_ldsw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
925
+int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
926
{
927
int ret;
928
929
set_helper_retaddr(retaddr);
930
- ret = cpu_ldsw_data(env, ptr);
931
+ ret = cpu_ldsw_be_data(env, ptr);
932
clear_helper_retaddr();
933
return ret;
934
}
935
936
-uint32_t cpu_ldl_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
937
+uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
938
{
939
uint32_t ret;
940
941
set_helper_retaddr(retaddr);
942
- ret = cpu_ldl_data(env, ptr);
943
+ ret = cpu_ldl_be_data(env, ptr);
944
clear_helper_retaddr();
945
return ret;
946
}
947
948
-uint64_t cpu_ldq_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
949
+uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
950
{
951
uint64_t ret;
952
953
set_helper_retaddr(retaddr);
954
- ret = cpu_ldq_data(env, ptr);
955
+ ret = cpu_ldq_be_data(env, ptr);
956
+ clear_helper_retaddr();
957
+ return ret;
958
+}
959
+
960
+uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
961
+{
962
+ uint32_t ret;
963
+
964
+ set_helper_retaddr(retaddr);
965
+ ret = cpu_lduw_le_data(env, ptr);
966
+ clear_helper_retaddr();
967
+ return ret;
968
+}
969
+
970
+int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
971
+{
972
+ int ret;
973
+
974
+ set_helper_retaddr(retaddr);
975
+ ret = cpu_ldsw_le_data(env, ptr);
976
+ clear_helper_retaddr();
977
+ return ret;
978
+}
979
+
980
+uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
981
+{
982
+ uint32_t ret;
983
+
984
+ set_helper_retaddr(retaddr);
985
+ ret = cpu_ldl_le_data(env, ptr);
986
+ clear_helper_retaddr();
987
+ return ret;
988
+}
989
+
990
+uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
991
+{
992
+ uint64_t ret;
993
+
994
+ set_helper_retaddr(retaddr);
995
+ ret = cpu_ldq_le_data(env, ptr);
996
clear_helper_retaddr();
997
return ret;
998
}
999
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1000
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1001
}
1002
1003
-void cpu_stw_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1004
+void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1005
{
1006
- uint16_t meminfo = trace_mem_get_info(MO_TEUW, MMU_USER_IDX, true);
1007
+ uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, true);
1008
1009
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1010
- stw_p(g2h(ptr), val);
1011
+ stw_be_p(g2h(ptr), val);
1012
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1013
}
1014
1015
-void cpu_stl_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1016
+void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1017
{
1018
- uint16_t meminfo = trace_mem_get_info(MO_TEUL, MMU_USER_IDX, true);
1019
+ uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, true);
1020
1021
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1022
- stl_p(g2h(ptr), val);
1023
+ stl_be_p(g2h(ptr), val);
1024
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1025
}
1026
1027
-void cpu_stq_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
1028
+void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
1029
{
1030
- uint16_t meminfo = trace_mem_get_info(MO_TEQ, MMU_USER_IDX, true);
1031
+ uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, true);
1032
1033
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1034
- stq_p(g2h(ptr), val);
1035
+ stq_be_p(g2h(ptr), val);
1036
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1037
+}
1038
+
1039
+void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1040
+{
1041
+ uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, true);
1042
+
1043
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1044
+ stw_le_p(g2h(ptr), val);
1045
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1046
+}
1047
+
1048
+void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1049
+{
1050
+ uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, true);
1051
+
1052
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1053
+ stl_le_p(g2h(ptr), val);
1054
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1055
+}
1056
+
1057
+void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
1058
+{
1059
+ uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, true);
1060
+
1061
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1062
+ stq_le_p(g2h(ptr), val);
1063
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1064
}
1065
1066
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
1067
clear_helper_retaddr();
1068
}
1069
1070
-void cpu_stw_data_ra(CPUArchState *env, abi_ptr ptr,
1071
- uint32_t val, uintptr_t retaddr)
1072
+void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
1073
+ uint32_t val, uintptr_t retaddr)
1074
{
1075
set_helper_retaddr(retaddr);
1076
- cpu_stw_data(env, ptr, val);
1077
+ cpu_stw_be_data(env, ptr, val);
1078
clear_helper_retaddr();
1079
}
1080
1081
-void cpu_stl_data_ra(CPUArchState *env, abi_ptr ptr,
1082
- uint32_t val, uintptr_t retaddr)
1083
+void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
1084
+ uint32_t val, uintptr_t retaddr)
1085
{
1086
set_helper_retaddr(retaddr);
1087
- cpu_stl_data(env, ptr, val);
1088
+ cpu_stl_be_data(env, ptr, val);
1089
clear_helper_retaddr();
1090
}
1091
1092
-void cpu_stq_data_ra(CPUArchState *env, abi_ptr ptr,
1093
- uint64_t val, uintptr_t retaddr)
1094
+void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
1095
+ uint64_t val, uintptr_t retaddr)
1096
{
1097
set_helper_retaddr(retaddr);
1098
- cpu_stq_data(env, ptr, val);
1099
+ cpu_stq_be_data(env, ptr, val);
1100
+ clear_helper_retaddr();
1101
+}
1102
+
1103
+void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
1104
+ uint32_t val, uintptr_t retaddr)
1105
+{
1106
+ set_helper_retaddr(retaddr);
1107
+ cpu_stw_le_data(env, ptr, val);
1108
+ clear_helper_retaddr();
1109
+}
1110
+
1111
+void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
1112
+ uint32_t val, uintptr_t retaddr)
1113
+{
1114
+ set_helper_retaddr(retaddr);
1115
+ cpu_stl_le_data(env, ptr, val);
1116
+ clear_helper_retaddr();
1117
+}
1118
+
1119
+void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
1120
+ uint64_t val, uintptr_t retaddr)
1121
+{
1122
+ set_helper_retaddr(retaddr);
1123
+ cpu_stq_le_data(env, ptr, val);
1124
clear_helper_retaddr();
1125
}
1126
1127
--
172
--
1128
2.20.1
173
2.20.1
1129
174
1130
175
diff view generated by jsdifflib
[PULL 30/34] target/arm/cpu: Restrict v8M IDAU interface to Aarch32 CPUs
[PULL 16/24] target/arm: Implement MVE VSRI, VSLI
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Implement the MVE VSRI and VSLI insns, which perform a
2
shift-and-insert operation.
2
3
3
As IDAU is a v8M feature, restrict it to the Aarch32 CPUs.
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
7
---
8
target/arm/helper-mve.h | 8 ++++++++
9
target/arm/mve.decode | 9 ++++++++
10
target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++
11
target/arm/translate-mve.c | 3 +++
12
4 files changed, 62 insertions(+)
4
13
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200504172448.9402-5-philmd@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/cpu.c | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
12
13
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.c
16
--- a/target/arm/helper-mve.h
16
+++ b/target/arm/cpu.c
17
+++ b/target/arm/helper-mve.h
17
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void)
18
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
18
const size_t cpu_count = ARRAY_SIZE(arm_cpus);
19
DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
19
20
DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
type_register_static(&arm_cpu_type_info);
21
DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
- type_register_static(&idau_interface_type_info);
22
+
22
23
+DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
#ifdef CONFIG_KVM
24
+DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
type_register_static(&host_arm_cpu_type_info);
25
+DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void)
26
+
26
if (cpu_count) {
27
+DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
size_t i;
28
+DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
29
+DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+ type_register_static(&idau_interface_type_info);
30
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
30
for (i = 0; i < cpu_count; ++i) {
31
index XXXXXXX..XXXXXXX 100644
31
arm_cpu_register(&arm_cpus[i]);
32
--- a/target/arm/mve.decode
32
}
33
+++ b/target/arm/mve.decode
34
@@ -XXX,XX +XXX,XX @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
35
36
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
37
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
38
+
39
+# Shift-and-insert
40
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
41
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
42
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
43
+
44
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
45
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
46
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
47
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/mve_helper.c
50
+++ b/target/arm/mve_helper.c
51
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
52
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
53
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
54
55
+/* Shift-and-insert; we always work with 64 bits at a time */
56
+#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \
57
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
58
+ void *vm, uint32_t shift) \
59
+ { \
60
+ uint64_t *d = vd, *m = vm; \
61
+ uint16_t mask; \
62
+ uint64_t shiftmask; \
63
+ unsigned e; \
64
+ if (shift == 0 || shift == ESIZE * 8) { \
65
+ /* \
66
+ * Only VSLI can shift by 0; only VSRI can shift by <dt>. \
67
+ * The generic logic would give the right answer for 0 but \
68
+ * fails for <dt>. \
69
+ */ \
70
+ goto done; \
71
+ } \
72
+ assert(shift < ESIZE * 8); \
73
+ mask = mve_element_mask(env); \
74
+ /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \
75
+ shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \
76
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
77
+ uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \
78
+ (d[H8(e)] & ~shiftmask); \
79
+ mergemask(&d[H8(e)], r, mask); \
80
+ } \
81
+done: \
82
+ mve_advance_vpt(env); \
83
+ }
84
+
85
+#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
86
+#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
87
+#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
88
+#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
89
+
90
+DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
91
+DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
92
+DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
93
+DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
94
+DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
95
+DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
96
+
97
/*
98
* Long shifts taking half-sized inputs from top or bottom of the input
99
* vector and producing a double-width result. ESIZE, TYPE are for
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/arm/translate-mve.c
103
+++ b/target/arm/translate-mve.c
104
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
105
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
106
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
107
108
+DO_2SHIFT(VSRI, vsri, false)
109
+DO_2SHIFT(VSLI, vsli, false)
110
+
111
#define DO_VSHLL(INSN, FN) \
112
static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
113
{ \
33
--
114
--
34
2.20.1
115
2.20.1
35
116
36
117
diff view generated by jsdifflib
[PULL 01/34] aspeed: Add boot stub for smp booting
[PULL 17/24] target/arm: Implement MVE VSHRN, VRSHRN
1
From: Joel Stanley <joel@jms.id.au>
1
Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
2
2
3
This is a boot stub that is similar to the code u-boot runs, allowing
3
do_urshr() is borrowed from sve_helper.c.
4
the kernel to boot the secondary CPU.
5
4
6
u-boot works as follows:
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
8
---
9
target/arm/helper-mve.h | 10 ++++++++++
10
target/arm/mve.decode | 11 +++++++++++
11
target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate-mve.c | 15 ++++++++++++++
13
4 files changed, 76 insertions(+)
7
14
8
1. Initialises the SMP mailbox area in the SCU at 0x1e6e2180 with default values
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
9
10
2. Copies a stub named 'mailbox_insn' from flash to the SCU, just above the
11
mailbox area
12
13
3. Sets AST_SMP_MBOX_FIELD_READY to a magic value to indicate the
14
secondary can begin execution from the stub
15
16
4. The stub waits until the AST_SMP_MBOX_FIELD_GOSIGN register is set to
17
a magic value
18
19
5. Jumps to the address in AST_SMP_MBOX_FIELD_ENTRY, starting Linux
20
21
Linux indicates it is ready by writing the address of its entrypoint
22
function to AST_SMP_MBOX_FIELD_ENTRY and the 'go' magic number to
23
AST_SMP_MBOX_FIELD_GOSIGN. The secondary CPU sees this at step 4 and
24
breaks out of it's loop.
25
26
To be compatible, a fixed qemu stub is loaded into the mailbox area. As
27
qemu can ensure the stub is loaded before execution starts, we do not
28
need to emulate the AST_SMP_MBOX_FIELD_READY behaviour of u-boot. The
29
secondary CPU's program counter points to the beginning of the stub,
30
allowing qemu to start secondaries at step four.
31
32
Reboot behaviour is preserved by resetting AST_SMP_MBOX_FIELD_GOSIGN
33
when the secondaries are reset.
34
35
This is only configured when the system is booted with -kernel and qemu
36
does not execute u-boot first.
37
38
Reviewed-by: Cédric Le Goater <clg@kaod.org>
39
Tested-by: Cédric Le Goater <clg@kaod.org>
40
Signed-off-by: Joel Stanley <joel@jms.id.au>
41
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
42
---
43
hw/arm/aspeed.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++++
44
1 file changed, 65 insertions(+)
45
46
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
47
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/aspeed.c
17
--- a/target/arm/helper-mve.h
49
+++ b/hw/arm/aspeed.c
18
+++ b/target/arm/helper-mve.h
50
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps max_ram_ops = {
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
51
.endianness = DEVICE_NATIVE_ENDIAN,
20
DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
52
};
21
DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
53
22
DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
54
+#define AST_SMP_MAILBOX_BASE 0x1e6e2180
55
+#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
56
+#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
57
+#define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
58
+#define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
59
+#define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
60
+#define AST_SMP_MBOX_GOSIGN 0xabbaab00
61
+
23
+
62
+static void aspeed_write_smpboot(ARMCPU *cpu,
24
+DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
63
+ const struct arm_boot_info *info)
25
+DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+
29
+DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/mve.decode
36
+++ b/target/arm/mve.decode
37
@@ -XXX,XX +XXX,XX @@ VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
38
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
39
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
40
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
41
+
42
+# Narrowing shifts (which only support b and h sizes)
43
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
44
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
45
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
46
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
47
+
48
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
49
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
50
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
51
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
52
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/mve_helper.c
55
+++ b/target/arm/mve_helper.c
56
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
57
58
DO_VSHLL_ALL(vshllb, false)
59
DO_VSHLL_ALL(vshllt, true)
60
+
61
+/*
62
+ * Narrowing right shifts, taking a double sized input, shifting it
63
+ * and putting the result in either the top or bottom half of the output.
64
+ * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
65
+ */
66
+#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
67
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
68
+ void *vm, uint32_t shift) \
69
+ { \
70
+ LTYPE *m = vm; \
71
+ TYPE *d = vd; \
72
+ uint16_t mask = mve_element_mask(env); \
73
+ unsigned le; \
74
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
75
+ TYPE r = FN(m[H##LESIZE(le)], shift); \
76
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
77
+ } \
78
+ mve_advance_vpt(env); \
79
+ }
80
+
81
+#define DO_VSHRN_ALL(OP, FN) \
82
+ DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \
83
+ DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \
84
+ DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \
85
+ DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
86
+
87
+static inline uint64_t do_urshr(uint64_t x, unsigned sh)
64
+{
88
+{
65
+ static const uint32_t poll_mailbox_ready[] = {
89
+ if (likely(sh < 64)) {
66
+ /*
90
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
67
+ * r2 = per-cpu go sign value
91
+ } else if (sh == 64) {
68
+ * r1 = AST_SMP_MBOX_FIELD_ENTRY
92
+ return x >> 63;
69
+ * r0 = AST_SMP_MBOX_FIELD_GOSIGN
93
+ } else {
70
+ */
94
+ return 0;
71
+ 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
95
+ }
72
+ 0xe21000ff, /* ands r0, r0, #255 */
73
+ 0xe59f201c, /* ldr r2, [pc, #28] */
74
+ 0xe1822000, /* orr r2, r2, r0 */
75
+
76
+ 0xe59f1018, /* ldr r1, [pc, #24] */
77
+ 0xe59f0018, /* ldr r0, [pc, #24] */
78
+
79
+ 0xe320f002, /* wfe */
80
+ 0xe5904000, /* ldr r4, [r0] */
81
+ 0xe1520004, /* cmp r2, r4 */
82
+ 0x1afffffb, /* bne <wfe> */
83
+ 0xe591f000, /* ldr pc, [r1] */
84
+ AST_SMP_MBOX_GOSIGN,
85
+ AST_SMP_MBOX_FIELD_ENTRY,
86
+ AST_SMP_MBOX_FIELD_GOSIGN,
87
+ };
88
+
89
+ rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
90
+ sizeof(poll_mailbox_ready),
91
+ info->smp_loader_start);
92
+}
96
+}
93
+
97
+
94
+static void aspeed_reset_secondary(ARMCPU *cpu,
98
+DO_VSHRN_ALL(vshrn, DO_SHR)
95
+ const struct arm_boot_info *info)
99
+DO_VSHRN_ALL(vrshrn, do_urshr)
96
+{
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
97
+ AddressSpace *as = arm_boot_address_space(cpu, info);
101
index XXXXXXX..XXXXXXX 100644
98
+ CPUState *cs = CPU(cpu);
102
--- a/target/arm/translate-mve.c
103
+++ b/target/arm/translate-mve.c
104
@@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs)
105
DO_VSHLL(VSHLL_BU, vshllbu)
106
DO_VSHLL(VSHLL_TS, vshllts)
107
DO_VSHLL(VSHLL_TU, vshlltu)
99
+
108
+
100
+ /* info->smp_bootreg_addr */
109
+#define DO_2SHIFT_N(INSN, FN) \
101
+ address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
110
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
102
+ MEMTXATTRS_UNSPECIFIED, NULL);
111
+ { \
103
+ cpu_set_pc(cs, info->smp_loader_start);
112
+ static MVEGenTwoOpShiftFn * const fns[] = { \
104
+}
113
+ gen_helper_mve_##FN##b, \
105
+
114
+ gen_helper_mve_##FN##h, \
106
#define FIRMWARE_ADDR 0x0
115
+ }; \
107
116
+ return do_2shift(s, a, fns[a->size], false); \
108
static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
109
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
110
}
111
}
112
113
+ if (machine->kernel_filename && bmc->soc.num_cpus > 1) {
114
+ /* With no u-boot we must set up a boot stub for the secondary CPU */
115
+ MemoryRegion *smpboot = g_new(MemoryRegion, 1);
116
+ memory_region_init_ram(smpboot, OBJECT(bmc), "aspeed.smpboot",
117
+ 0x80, &error_abort);
118
+ memory_region_add_subregion(get_system_memory(),
119
+ AST_SMP_MAILBOX_BASE, smpboot);
120
+
121
+ aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
122
+ aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
123
+ aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
124
+ }
117
+ }
125
+
118
+
126
aspeed_board_binfo.ram_size = ram_size;
119
+DO_2SHIFT_N(VSHRNB, vshrnb)
127
aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM];
120
+DO_2SHIFT_N(VSHRNT, vshrnt)
128
aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus;
121
+DO_2SHIFT_N(VRSHRNB, vrshrnb)
122
+DO_2SHIFT_N(VRSHRNT, vrshrnt)
129
--
123
--
130
2.20.1
124
2.20.1
131
125
132
126
diff view generated by jsdifflib
[PULL 02/34] target/arm: Drop access_el3_aa32ns_aa64any()
Deleted patch
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
2
1
3
Calling access_el3_aa32ns() works for AArch32 only cores
4
but it does not handle 32-bit EL2 on top of 64-bit EL3
5
for mixed 32/64-bit cores.
6
7
Merge access_el3_aa32ns_aa64any() into access_el3_aa32ns()
8
and only use the latter.
9
10
Fixes: 68e9c2fe65 ("target-arm: Add VTCR_EL2")
11
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
12
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
13
Message-id: 20200505141729.31930-2-edgar.iglesias@gmail.com
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/helper.c | 30 +++++++-----------------------
18
1 file changed, 7 insertions(+), 23 deletions(-)
19
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper.c
23
+++ b/target/arm/helper.c
24
@@ -XXX,XX +XXX,XX @@ void init_cpreg_list(ARMCPU *cpu)
25
}
26
27
/*
28
- * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
29
- * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
30
- *
31
- * access_el3_aa32ns: Used to check AArch32 register views.
32
- * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
33
+ * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
34
*/
35
static CPAccessResult access_el3_aa32ns(CPUARMState *env,
36
const ARMCPRegInfo *ri,
37
bool isread)
38
{
39
- bool secure = arm_is_secure_below_el3(env);
40
-
41
- assert(!arm_el_is_aa64(env, 3));
42
- if (secure) {
43
+ if (!is_a64(env) && arm_current_el(env) == 3 &&
44
+ arm_is_secure_below_el3(env)) {
45
return CP_ACCESS_TRAP_UNCATEGORIZED;
46
}
47
return CP_ACCESS_OK;
48
}
49
50
-static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
51
- const ARMCPRegInfo *ri,
52
- bool isread)
53
-{
54
- if (!arm_el_is_aa64(env, 3)) {
55
- return access_el3_aa32ns(env, ri, isread);
56
- }
57
- return CP_ACCESS_OK;
58
-}
59
-
60
/* Some secure-only AArch32 registers trap to EL3 if used from
61
* Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
62
* Note that an access from Secure EL1 can only happen if EL3 is AArch64.
63
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
64
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
65
{ .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
66
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
67
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
68
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
69
.type = ARM_CP_CONST, .resetvalue = 0 },
70
{ .name = "VTTBR", .state = ARM_CP_STATE_AA32,
71
.cp = 15, .opc1 = 6, .crm = 2,
72
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
73
.type = ARM_CP_CONST, .resetvalue = 0 },
74
{ .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
75
.opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
76
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
77
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
78
.type = ARM_CP_CONST, .resetvalue = 0 },
79
{ .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
80
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
81
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
82
ARMCPRegInfo vpidr_regs[] = {
83
{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
84
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
85
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
86
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
87
.type = ARM_CP_CONST, .resetvalue = cpu->midr,
88
.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
89
{ .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
90
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
91
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
92
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
93
.type = ARM_CP_NO_RAW,
94
.writefn = arm_cp_write_ignore, .readfn = mpidr_read },
95
REGINFO_SENTINEL
96
--
97
2.20.1
98
99
diff view generated by jsdifflib
[PULL 03/34] aspeed: Support AST2600A1 silicon revision
Deleted patch
1
From: Joel Stanley <joel@jms.id.au>
2
1
3
There are minimal differences from Qemu's point of view between the A0
4
and A1 silicon revisions.
5
6
As the A1 exercises different code paths in u-boot it is desirable to
7
emulate that instead.
8
9
Signed-off-by: Joel Stanley <joel@jms.id.au>
10
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
11
Reviewed-by: Cédric Le Goater <clg@kaod.org>
12
Message-id: 20200504093703.261135-1-joel@jms.id.au
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
include/hw/misc/aspeed_scu.h | 1 +
16
hw/arm/aspeed.c | 8 ++++----
17
hw/arm/aspeed_ast2600.c | 6 +++---
18
hw/misc/aspeed_scu.c | 11 +++++------
19
4 files changed, 13 insertions(+), 13 deletions(-)
20
21
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/misc/aspeed_scu.h
24
+++ b/include/hw/misc/aspeed_scu.h
25
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSCUState {
26
#define AST2500_A0_SILICON_REV 0x04000303U
27
#define AST2500_A1_SILICON_REV 0x04010303U
28
#define AST2600_A0_SILICON_REV 0x05000303U
29
+#define AST2600_A1_SILICON_REV 0x05010303U
30
31
#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
32
33
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/arm/aspeed.c
36
+++ b/hw/arm/aspeed.c
37
@@ -XXX,XX +XXX,XX @@ struct AspeedBoardState {
38
39
/* Tacoma hardware value */
40
#define TACOMA_BMC_HW_STRAP1 0x00000000
41
-#define TACOMA_BMC_HW_STRAP2 0x00000000
42
+#define TACOMA_BMC_HW_STRAP2 0x00000040
43
44
/*
45
* The max ram region is for firmwares that scan the address space
46
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
47
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
48
49
mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
50
- amc->soc_name = "ast2600-a0";
51
+ amc->soc_name = "ast2600-a1";
52
amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
53
amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
54
amc->fmc_model = "w25q512jv";
55
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
56
MachineClass *mc = MACHINE_CLASS(oc);
57
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
58
59
- mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
60
- amc->soc_name = "ast2600-a0";
61
+ mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)";
62
+ amc->soc_name = "ast2600-a1";
63
amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
64
amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
65
amc->fmc_model = "mx66l1g45g";
66
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/hw/arm/aspeed_ast2600.c
69
+++ b/hw/arm/aspeed_ast2600.c
70
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
71
72
dc->realize = aspeed_soc_ast2600_realize;
73
74
- sc->name = "ast2600-a0";
75
+ sc->name = "ast2600-a1";
76
sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
77
- sc->silicon_rev = AST2600_A0_SILICON_REV;
78
+ sc->silicon_rev = AST2600_A1_SILICON_REV;
79
sc->sram_size = 0x10000;
80
sc->spis_num = 2;
81
sc->ehcis_num = 2;
82
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
83
}
84
85
static const TypeInfo aspeed_soc_ast2600_type_info = {
86
- .name = "ast2600-a0",
87
+ .name = "ast2600-a1",
88
.parent = TYPE_ASPEED_SOC,
89
.instance_size = sizeof(AspeedSoCState),
90
.instance_init = aspeed_soc_ast2600_init,
91
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/hw/misc/aspeed_scu.c
94
+++ b/hw/misc/aspeed_scu.c
95
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_silicon_revs[] = {
96
AST2500_A0_SILICON_REV,
97
AST2500_A1_SILICON_REV,
98
AST2600_A0_SILICON_REV,
99
+ AST2600_A1_SILICON_REV,
100
};
101
102
bool is_supported_silicon_rev(uint32_t silicon_rev)
103
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = {
104
.valid.unaligned = false,
105
};
106
107
-static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = {
108
- [AST2600_SILICON_REV] = AST2600_SILICON_REV,
109
- [AST2600_SILICON_REV2] = AST2600_SILICON_REV,
110
- [AST2600_SYS_RST_CTRL] = 0xF7CFFEDC | 0x100,
111
+static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = {
112
+ [AST2600_SYS_RST_CTRL] = 0xF7C3FED8,
113
[AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC,
114
- [AST2600_CLK_STOP_CTRL] = 0xEFF43E8B,
115
+ [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A,
116
[AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0,
117
[AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */
118
[AST2600_HPLL_PARAM] = 0x1000405F,
119
@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data)
120
121
dc->desc = "ASPEED 2600 System Control Unit";
122
dc->reset = aspeed_ast2600_scu_reset;
123
- asc->resets = ast2600_a0_resets;
124
+ asc->resets = ast2600_a1_resets;
125
asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */
126
asc->apb_divider = 4;
127
asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
128
--
129
2.20.1
130
131
diff view generated by jsdifflib
[PULL 05/34] hw/arm/nrf51: Add NRF51_PERIPHERAL_SIZE definition
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
On the NRF51 series, all peripherals have a fixed I/O size
4
of 4KiB. Define NRF51_PERIPHERAL_SIZE and use it.
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200504072822.18799-2-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/nrf51.h | 3 +--
12
include/hw/i2c/microbit_i2c.h | 2 +-
13
hw/arm/nrf51_soc.c | 4 ++--
14
hw/i2c/microbit_i2c.c | 2 +-
15
hw/timer/nrf51_timer.c | 2 +-
16
5 files changed, 6 insertions(+), 7 deletions(-)
17
18
diff --git a/include/hw/arm/nrf51.h b/include/hw/arm/nrf51.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/nrf51.h
21
+++ b/include/hw/arm/nrf51.h
22
@@ -XXX,XX +XXX,XX @@
23
#define NRF51_IOMEM_BASE 0x40000000
24
#define NRF51_IOMEM_SIZE 0x20000000
25
26
+#define NRF51_PERIPHERAL_SIZE 0x00001000
27
#define NRF51_UART_BASE 0x40002000
28
#define NRF51_TWI_BASE 0x40003000
29
-#define NRF51_TWI_SIZE 0x00001000
30
#define NRF51_TIMER_BASE 0x40008000
31
-#define NRF51_TIMER_SIZE 0x00001000
32
#define NRF51_RNG_BASE 0x4000D000
33
#define NRF51_NVMC_BASE 0x4001E000
34
#define NRF51_GPIO_BASE 0x50000000
35
diff --git a/include/hw/i2c/microbit_i2c.h b/include/hw/i2c/microbit_i2c.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/include/hw/i2c/microbit_i2c.h
38
+++ b/include/hw/i2c/microbit_i2c.h
39
@@ -XXX,XX +XXX,XX @@
40
#define MICROBIT_I2C(obj) \
41
OBJECT_CHECK(MicrobitI2CState, (obj), TYPE_MICROBIT_I2C)
42
43
-#define MICROBIT_I2C_NREGS (NRF51_TWI_SIZE / sizeof(uint32_t))
44
+#define MICROBIT_I2C_NREGS (NRF51_PERIPHERAL_SIZE / sizeof(uint32_t))
45
46
typedef struct {
47
SysBusDevice parent_obj;
48
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/arm/nrf51_soc.c
51
+++ b/hw/arm/nrf51_soc.c
52
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
53
return;
54
}
55
56
- base_addr = NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE;
57
+ base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE;
58
59
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
60
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
61
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
62
63
/* STUB Peripherals */
64
memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL,
65
- "nrf51_soc.clock", 0x1000);
66
+ "nrf51_soc.clock", NRF51_PERIPHERAL_SIZE);
67
memory_region_add_subregion_overlap(&s->container,
68
NRF51_IOMEM_BASE, &s->clock, -1);
69
70
diff --git a/hw/i2c/microbit_i2c.c b/hw/i2c/microbit_i2c.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/i2c/microbit_i2c.c
73
+++ b/hw/i2c/microbit_i2c.c
74
@@ -XXX,XX +XXX,XX @@ static void microbit_i2c_realize(DeviceState *dev, Error **errp)
75
MicrobitI2CState *s = MICROBIT_I2C(dev);
76
77
memory_region_init_io(&s->iomem, OBJECT(s), &microbit_i2c_ops, s,
78
- "microbit.twi", NRF51_TWI_SIZE);
79
+ "microbit.twi", NRF51_PERIPHERAL_SIZE);
80
sysbus_init_mmio(sbd, &s->iomem);
81
}
82
83
diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c
84
index XXXXXXX..XXXXXXX 100644
85
--- a/hw/timer/nrf51_timer.c
86
+++ b/hw/timer/nrf51_timer.c
87
@@ -XXX,XX +XXX,XX @@ static void nrf51_timer_init(Object *obj)
88
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
89
90
memory_region_init_io(&s->iomem, obj, &rng_ops, s,
91
- TYPE_NRF51_TIMER, NRF51_TIMER_SIZE);
92
+ TYPE_NRF51_TIMER, NRF51_PERIPHERAL_SIZE);
93
sysbus_init_mmio(sbd, &s->iomem);
94
sysbus_init_irq(sbd, &s->irq);
95
96
--
97
2.20.1
98
99
diff view generated by jsdifflib
[PULL 31/34] target/arm: Restrict TCG cpus to TCG accel
[PULL 18/24] target/arm: Implement MVE saturating narrowing shifts
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Implement the MVE saturating shift-right-and-narrow insns
2
2
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
3
A KVM-only build won't be able to run TCG cpus.
3
4
4
do_srshr() is borrowed from sve_helper.c.
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
7
Message-id: 20200504172448.9402-6-philmd@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
9
---
10
target/arm/cpu.c | 634 -------------------------------------
10
target/arm/helper-mve.h | 30 +++++++++++
11
target/arm/cpu_tcg.c | 664 +++++++++++++++++++++++++++++++++++++++
11
target/arm/mve.decode | 28 ++++++++++
12
target/arm/Makefile.objs | 1 +
12
target/arm/mve_helper.c | 104 +++++++++++++++++++++++++++++++++++++
13
3 files changed, 665 insertions(+), 634 deletions(-)
13
target/arm/translate-mve.c | 12 +++++
14
create mode 100644 target/arm/cpu_tcg.c
14
4 files changed, 174 insertions(+)
15
15
16
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.c
18
--- a/target/arm/helper-mve.h
19
+++ b/target/arm/cpu.c
19
+++ b/target/arm/helper-mve.h
20
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
return true;
21
DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
+
25
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+
30
+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
+
35
+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
+DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+
40
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+
45
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
46
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
47
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
48
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
49
+
50
+DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
51
+DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
52
+DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
53
+DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
54
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
55
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/mve.decode
57
+++ b/target/arm/mve.decode
58
@@ -XXX,XX +XXX,XX @@ VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
59
VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
60
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
61
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
62
+
63
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
64
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
65
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
66
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
67
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
68
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
69
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
70
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
71
+
72
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
73
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
74
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
75
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
76
+
77
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
78
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
79
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
80
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
81
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
82
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
83
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
84
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
85
+
86
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
87
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
88
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
89
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
90
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/arm/mve_helper.c
93
+++ b/target/arm/mve_helper.c
94
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
95
}
22
}
96
}
23
97
24
-#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
98
+static inline int64_t do_srshr(int64_t x, unsigned sh)
25
-static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
26
-{
27
- CPUClass *cc = CPU_GET_CLASS(cs);
28
- ARMCPU *cpu = ARM_CPU(cs);
29
- CPUARMState *env = &cpu->env;
30
- bool ret = false;
31
-
32
- /*
33
- * ARMv7-M interrupt masking works differently than -A or -R.
34
- * There is no FIQ/IRQ distinction. Instead of I and F bits
35
- * masking FIQ and IRQ interrupts, an exception is taken only
36
- * if it is higher priority than the current execution priority
37
- * (which depends on state like BASEPRI, FAULTMASK and the
38
- * currently active exception).
39
- */
40
- if (interrupt_request & CPU_INTERRUPT_HARD
41
- && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
42
- cs->exception_index = EXCP_IRQ;
43
- cc->do_interrupt(cs);
44
- ret = true;
45
- }
46
- return ret;
47
-}
48
-#endif
49
-
50
void arm_cpu_update_virq(ARMCPU *cpu)
51
{
52
/*
53
@@ -XXX,XX +XXX,XX @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
54
/* CPU models. These are not needed for the AArch64 linux-user build. */
55
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
56
57
-static void arm926_initfn(Object *obj)
58
-{
59
- ARMCPU *cpu = ARM_CPU(obj);
60
-
61
- cpu->dtb_compatible = "arm,arm926";
62
- set_feature(&cpu->env, ARM_FEATURE_V5);
63
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
64
- set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
65
- cpu->midr = 0x41069265;
66
- cpu->reset_fpsid = 0x41011090;
67
- cpu->ctr = 0x1dd20d2;
68
- cpu->reset_sctlr = 0x00090078;
69
-
70
- /*
71
- * ARMv5 does not have the ID_ISAR registers, but we can still
72
- * set the field to indicate Jazelle support within QEMU.
73
- */
74
- cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
75
- /*
76
- * Similarly, we need to set MVFR0 fields to enable vfp and short vector
77
- * support even though ARMv5 doesn't have this register.
78
- */
79
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
80
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
81
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
82
-}
83
-
84
-static void arm946_initfn(Object *obj)
85
-{
86
- ARMCPU *cpu = ARM_CPU(obj);
87
-
88
- cpu->dtb_compatible = "arm,arm946";
89
- set_feature(&cpu->env, ARM_FEATURE_V5);
90
- set_feature(&cpu->env, ARM_FEATURE_PMSA);
91
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
92
- cpu->midr = 0x41059461;
93
- cpu->ctr = 0x0f004006;
94
- cpu->reset_sctlr = 0x00000078;
95
-}
96
-
97
-static void arm1026_initfn(Object *obj)
98
-{
99
- ARMCPU *cpu = ARM_CPU(obj);
100
-
101
- cpu->dtb_compatible = "arm,arm1026";
102
- set_feature(&cpu->env, ARM_FEATURE_V5);
103
- set_feature(&cpu->env, ARM_FEATURE_AUXCR);
104
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
105
- set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
106
- cpu->midr = 0x4106a262;
107
- cpu->reset_fpsid = 0x410110a0;
108
- cpu->ctr = 0x1dd20d2;
109
- cpu->reset_sctlr = 0x00090078;
110
- cpu->reset_auxcr = 1;
111
-
112
- /*
113
- * ARMv5 does not have the ID_ISAR registers, but we can still
114
- * set the field to indicate Jazelle support within QEMU.
115
- */
116
- cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
117
- /*
118
- * Similarly, we need to set MVFR0 fields to enable vfp and short vector
119
- * support even though ARMv5 doesn't have this register.
120
- */
121
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
122
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
123
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
124
-
125
- {
126
- /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
127
- ARMCPRegInfo ifar = {
128
- .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
129
- .access = PL1_RW,
130
- .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
131
- .resetvalue = 0
132
- };
133
- define_one_arm_cp_reg(cpu, &ifar);
134
- }
135
-}
136
-
137
-static void arm1136_r2_initfn(Object *obj)
138
-{
139
- ARMCPU *cpu = ARM_CPU(obj);
140
- /*
141
- * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
142
- * older core than plain "arm1136". In particular this does not
143
- * have the v6K features.
144
- * These ID register values are correct for 1136 but may be wrong
145
- * for 1136_r2 (in particular r0p2 does not actually implement most
146
- * of the ID registers).
147
- */
148
-
149
- cpu->dtb_compatible = "arm,arm1136";
150
- set_feature(&cpu->env, ARM_FEATURE_V6);
151
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
152
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
153
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
154
- cpu->midr = 0x4107b362;
155
- cpu->reset_fpsid = 0x410120b4;
156
- cpu->isar.mvfr0 = 0x11111111;
157
- cpu->isar.mvfr1 = 0x00000000;
158
- cpu->ctr = 0x1dd20d2;
159
- cpu->reset_sctlr = 0x00050078;
160
- cpu->id_pfr0 = 0x111;
161
- cpu->id_pfr1 = 0x1;
162
- cpu->isar.id_dfr0 = 0x2;
163
- cpu->id_afr0 = 0x3;
164
- cpu->isar.id_mmfr0 = 0x01130003;
165
- cpu->isar.id_mmfr1 = 0x10030302;
166
- cpu->isar.id_mmfr2 = 0x01222110;
167
- cpu->isar.id_isar0 = 0x00140011;
168
- cpu->isar.id_isar1 = 0x12002111;
169
- cpu->isar.id_isar2 = 0x11231111;
170
- cpu->isar.id_isar3 = 0x01102131;
171
- cpu->isar.id_isar4 = 0x141;
172
- cpu->reset_auxcr = 7;
173
-}
174
-
175
-static void arm1136_initfn(Object *obj)
176
-{
177
- ARMCPU *cpu = ARM_CPU(obj);
178
-
179
- cpu->dtb_compatible = "arm,arm1136";
180
- set_feature(&cpu->env, ARM_FEATURE_V6K);
181
- set_feature(&cpu->env, ARM_FEATURE_V6);
182
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
183
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
184
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
185
- cpu->midr = 0x4117b363;
186
- cpu->reset_fpsid = 0x410120b4;
187
- cpu->isar.mvfr0 = 0x11111111;
188
- cpu->isar.mvfr1 = 0x00000000;
189
- cpu->ctr = 0x1dd20d2;
190
- cpu->reset_sctlr = 0x00050078;
191
- cpu->id_pfr0 = 0x111;
192
- cpu->id_pfr1 = 0x1;
193
- cpu->isar.id_dfr0 = 0x2;
194
- cpu->id_afr0 = 0x3;
195
- cpu->isar.id_mmfr0 = 0x01130003;
196
- cpu->isar.id_mmfr1 = 0x10030302;
197
- cpu->isar.id_mmfr2 = 0x01222110;
198
- cpu->isar.id_isar0 = 0x00140011;
199
- cpu->isar.id_isar1 = 0x12002111;
200
- cpu->isar.id_isar2 = 0x11231111;
201
- cpu->isar.id_isar3 = 0x01102131;
202
- cpu->isar.id_isar4 = 0x141;
203
- cpu->reset_auxcr = 7;
204
-}
205
-
206
-static void arm1176_initfn(Object *obj)
207
-{
208
- ARMCPU *cpu = ARM_CPU(obj);
209
-
210
- cpu->dtb_compatible = "arm,arm1176";
211
- set_feature(&cpu->env, ARM_FEATURE_V6K);
212
- set_feature(&cpu->env, ARM_FEATURE_VAPA);
213
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
214
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
215
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
216
- set_feature(&cpu->env, ARM_FEATURE_EL3);
217
- cpu->midr = 0x410fb767;
218
- cpu->reset_fpsid = 0x410120b5;
219
- cpu->isar.mvfr0 = 0x11111111;
220
- cpu->isar.mvfr1 = 0x00000000;
221
- cpu->ctr = 0x1dd20d2;
222
- cpu->reset_sctlr = 0x00050078;
223
- cpu->id_pfr0 = 0x111;
224
- cpu->id_pfr1 = 0x11;
225
- cpu->isar.id_dfr0 = 0x33;
226
- cpu->id_afr0 = 0;
227
- cpu->isar.id_mmfr0 = 0x01130003;
228
- cpu->isar.id_mmfr1 = 0x10030302;
229
- cpu->isar.id_mmfr2 = 0x01222100;
230
- cpu->isar.id_isar0 = 0x0140011;
231
- cpu->isar.id_isar1 = 0x12002111;
232
- cpu->isar.id_isar2 = 0x11231121;
233
- cpu->isar.id_isar3 = 0x01102131;
234
- cpu->isar.id_isar4 = 0x01141;
235
- cpu->reset_auxcr = 7;
236
-}
237
-
238
-static void arm11mpcore_initfn(Object *obj)
239
-{
240
- ARMCPU *cpu = ARM_CPU(obj);
241
-
242
- cpu->dtb_compatible = "arm,arm11mpcore";
243
- set_feature(&cpu->env, ARM_FEATURE_V6K);
244
- set_feature(&cpu->env, ARM_FEATURE_VAPA);
245
- set_feature(&cpu->env, ARM_FEATURE_MPIDR);
246
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
247
- cpu->midr = 0x410fb022;
248
- cpu->reset_fpsid = 0x410120b4;
249
- cpu->isar.mvfr0 = 0x11111111;
250
- cpu->isar.mvfr1 = 0x00000000;
251
- cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
252
- cpu->id_pfr0 = 0x111;
253
- cpu->id_pfr1 = 0x1;
254
- cpu->isar.id_dfr0 = 0;
255
- cpu->id_afr0 = 0x2;
256
- cpu->isar.id_mmfr0 = 0x01100103;
257
- cpu->isar.id_mmfr1 = 0x10020302;
258
- cpu->isar.id_mmfr2 = 0x01222000;
259
- cpu->isar.id_isar0 = 0x00100011;
260
- cpu->isar.id_isar1 = 0x12002111;
261
- cpu->isar.id_isar2 = 0x11221011;
262
- cpu->isar.id_isar3 = 0x01102131;
263
- cpu->isar.id_isar4 = 0x141;
264
- cpu->reset_auxcr = 1;
265
-}
266
-
267
-static void cortex_m0_initfn(Object *obj)
268
-{
269
- ARMCPU *cpu = ARM_CPU(obj);
270
- set_feature(&cpu->env, ARM_FEATURE_V6);
271
- set_feature(&cpu->env, ARM_FEATURE_M);
272
-
273
- cpu->midr = 0x410cc200;
274
-}
275
-
276
-static void cortex_m3_initfn(Object *obj)
277
-{
278
- ARMCPU *cpu = ARM_CPU(obj);
279
- set_feature(&cpu->env, ARM_FEATURE_V7);
280
- set_feature(&cpu->env, ARM_FEATURE_M);
281
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
282
- cpu->midr = 0x410fc231;
283
- cpu->pmsav7_dregion = 8;
284
- cpu->id_pfr0 = 0x00000030;
285
- cpu->id_pfr1 = 0x00000200;
286
- cpu->isar.id_dfr0 = 0x00100000;
287
- cpu->id_afr0 = 0x00000000;
288
- cpu->isar.id_mmfr0 = 0x00000030;
289
- cpu->isar.id_mmfr1 = 0x00000000;
290
- cpu->isar.id_mmfr2 = 0x00000000;
291
- cpu->isar.id_mmfr3 = 0x00000000;
292
- cpu->isar.id_isar0 = 0x01141110;
293
- cpu->isar.id_isar1 = 0x02111000;
294
- cpu->isar.id_isar2 = 0x21112231;
295
- cpu->isar.id_isar3 = 0x01111110;
296
- cpu->isar.id_isar4 = 0x01310102;
297
- cpu->isar.id_isar5 = 0x00000000;
298
- cpu->isar.id_isar6 = 0x00000000;
299
-}
300
-
301
-static void cortex_m4_initfn(Object *obj)
302
-{
303
- ARMCPU *cpu = ARM_CPU(obj);
304
-
305
- set_feature(&cpu->env, ARM_FEATURE_V7);
306
- set_feature(&cpu->env, ARM_FEATURE_M);
307
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
308
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
309
- cpu->midr = 0x410fc240; /* r0p0 */
310
- cpu->pmsav7_dregion = 8;
311
- cpu->isar.mvfr0 = 0x10110021;
312
- cpu->isar.mvfr1 = 0x11000011;
313
- cpu->isar.mvfr2 = 0x00000000;
314
- cpu->id_pfr0 = 0x00000030;
315
- cpu->id_pfr1 = 0x00000200;
316
- cpu->isar.id_dfr0 = 0x00100000;
317
- cpu->id_afr0 = 0x00000000;
318
- cpu->isar.id_mmfr0 = 0x00000030;
319
- cpu->isar.id_mmfr1 = 0x00000000;
320
- cpu->isar.id_mmfr2 = 0x00000000;
321
- cpu->isar.id_mmfr3 = 0x00000000;
322
- cpu->isar.id_isar0 = 0x01141110;
323
- cpu->isar.id_isar1 = 0x02111000;
324
- cpu->isar.id_isar2 = 0x21112231;
325
- cpu->isar.id_isar3 = 0x01111110;
326
- cpu->isar.id_isar4 = 0x01310102;
327
- cpu->isar.id_isar5 = 0x00000000;
328
- cpu->isar.id_isar6 = 0x00000000;
329
-}
330
-
331
-static void cortex_m7_initfn(Object *obj)
332
-{
333
- ARMCPU *cpu = ARM_CPU(obj);
334
-
335
- set_feature(&cpu->env, ARM_FEATURE_V7);
336
- set_feature(&cpu->env, ARM_FEATURE_M);
337
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
338
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
339
- cpu->midr = 0x411fc272; /* r1p2 */
340
- cpu->pmsav7_dregion = 8;
341
- cpu->isar.mvfr0 = 0x10110221;
342
- cpu->isar.mvfr1 = 0x12000011;
343
- cpu->isar.mvfr2 = 0x00000040;
344
- cpu->id_pfr0 = 0x00000030;
345
- cpu->id_pfr1 = 0x00000200;
346
- cpu->isar.id_dfr0 = 0x00100000;
347
- cpu->id_afr0 = 0x00000000;
348
- cpu->isar.id_mmfr0 = 0x00100030;
349
- cpu->isar.id_mmfr1 = 0x00000000;
350
- cpu->isar.id_mmfr2 = 0x01000000;
351
- cpu->isar.id_mmfr3 = 0x00000000;
352
- cpu->isar.id_isar0 = 0x01101110;
353
- cpu->isar.id_isar1 = 0x02112000;
354
- cpu->isar.id_isar2 = 0x20232231;
355
- cpu->isar.id_isar3 = 0x01111131;
356
- cpu->isar.id_isar4 = 0x01310132;
357
- cpu->isar.id_isar5 = 0x00000000;
358
- cpu->isar.id_isar6 = 0x00000000;
359
-}
360
-
361
-static void cortex_m33_initfn(Object *obj)
362
-{
363
- ARMCPU *cpu = ARM_CPU(obj);
364
-
365
- set_feature(&cpu->env, ARM_FEATURE_V8);
366
- set_feature(&cpu->env, ARM_FEATURE_M);
367
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
368
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
369
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
370
- cpu->midr = 0x410fd213; /* r0p3 */
371
- cpu->pmsav7_dregion = 16;
372
- cpu->sau_sregion = 8;
373
- cpu->isar.mvfr0 = 0x10110021;
374
- cpu->isar.mvfr1 = 0x11000011;
375
- cpu->isar.mvfr2 = 0x00000040;
376
- cpu->id_pfr0 = 0x00000030;
377
- cpu->id_pfr1 = 0x00000210;
378
- cpu->isar.id_dfr0 = 0x00200000;
379
- cpu->id_afr0 = 0x00000000;
380
- cpu->isar.id_mmfr0 = 0x00101F40;
381
- cpu->isar.id_mmfr1 = 0x00000000;
382
- cpu->isar.id_mmfr2 = 0x01000000;
383
- cpu->isar.id_mmfr3 = 0x00000000;
384
- cpu->isar.id_isar0 = 0x01101110;
385
- cpu->isar.id_isar1 = 0x02212000;
386
- cpu->isar.id_isar2 = 0x20232232;
387
- cpu->isar.id_isar3 = 0x01111131;
388
- cpu->isar.id_isar4 = 0x01310132;
389
- cpu->isar.id_isar5 = 0x00000000;
390
- cpu->isar.id_isar6 = 0x00000000;
391
- cpu->clidr = 0x00000000;
392
- cpu->ctr = 0x8000c000;
393
-}
394
-
395
-static void arm_v7m_class_init(ObjectClass *oc, void *data)
396
-{
397
- ARMCPUClass *acc = ARM_CPU_CLASS(oc);
398
- CPUClass *cc = CPU_CLASS(oc);
399
-
400
- acc->info = data;
401
-#ifndef CONFIG_USER_ONLY
402
- cc->do_interrupt = arm_v7m_cpu_do_interrupt;
403
-#endif
404
-
405
- cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
406
-}
407
-
408
-static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
409
- /* Dummy the TCM region regs for the moment */
410
- { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
411
- .access = PL1_RW, .type = ARM_CP_CONST },
412
- { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
413
- .access = PL1_RW, .type = ARM_CP_CONST },
414
- { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
415
- .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
416
- REGINFO_SENTINEL
417
-};
418
-
419
-static void cortex_r5_initfn(Object *obj)
420
-{
421
- ARMCPU *cpu = ARM_CPU(obj);
422
-
423
- set_feature(&cpu->env, ARM_FEATURE_V7);
424
- set_feature(&cpu->env, ARM_FEATURE_V7MP);
425
- set_feature(&cpu->env, ARM_FEATURE_PMSA);
426
- set_feature(&cpu->env, ARM_FEATURE_PMU);
427
- cpu->midr = 0x411fc153; /* r1p3 */
428
- cpu->id_pfr0 = 0x0131;
429
- cpu->id_pfr1 = 0x001;
430
- cpu->isar.id_dfr0 = 0x010400;
431
- cpu->id_afr0 = 0x0;
432
- cpu->isar.id_mmfr0 = 0x0210030;
433
- cpu->isar.id_mmfr1 = 0x00000000;
434
- cpu->isar.id_mmfr2 = 0x01200000;
435
- cpu->isar.id_mmfr3 = 0x0211;
436
- cpu->isar.id_isar0 = 0x02101111;
437
- cpu->isar.id_isar1 = 0x13112111;
438
- cpu->isar.id_isar2 = 0x21232141;
439
- cpu->isar.id_isar3 = 0x01112131;
440
- cpu->isar.id_isar4 = 0x0010142;
441
- cpu->isar.id_isar5 = 0x0;
442
- cpu->isar.id_isar6 = 0x0;
443
- cpu->mp_is_up = true;
444
- cpu->pmsav7_dregion = 16;
445
- define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
446
-}
447
-
448
-static void cortex_r5f_initfn(Object *obj)
449
-{
450
- ARMCPU *cpu = ARM_CPU(obj);
451
-
452
- cortex_r5_initfn(obj);
453
- cpu->isar.mvfr0 = 0x10110221;
454
- cpu->isar.mvfr1 = 0x00000011;
455
-}
456
-
457
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
458
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
459
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
460
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
461
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
462
}
463
464
-static void ti925t_initfn(Object *obj)
465
-{
466
- ARMCPU *cpu = ARM_CPU(obj);
467
- set_feature(&cpu->env, ARM_FEATURE_V4T);
468
- set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
469
- cpu->midr = ARM_CPUID_TI925T;
470
- cpu->ctr = 0x5109149;
471
- cpu->reset_sctlr = 0x00000070;
472
-}
473
-
474
-static void sa1100_initfn(Object *obj)
475
-{
476
- ARMCPU *cpu = ARM_CPU(obj);
477
-
478
- cpu->dtb_compatible = "intel,sa1100";
479
- set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
480
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
481
- cpu->midr = 0x4401A11B;
482
- cpu->reset_sctlr = 0x00000070;
483
-}
484
-
485
-static void sa1110_initfn(Object *obj)
486
-{
487
- ARMCPU *cpu = ARM_CPU(obj);
488
- set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
489
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
490
- cpu->midr = 0x6901B119;
491
- cpu->reset_sctlr = 0x00000070;
492
-}
493
-
494
-static void pxa250_initfn(Object *obj)
495
-{
496
- ARMCPU *cpu = ARM_CPU(obj);
497
-
498
- cpu->dtb_compatible = "marvell,xscale";
499
- set_feature(&cpu->env, ARM_FEATURE_V5);
500
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
501
- cpu->midr = 0x69052100;
502
- cpu->ctr = 0xd172172;
503
- cpu->reset_sctlr = 0x00000078;
504
-}
505
-
506
-static void pxa255_initfn(Object *obj)
507
-{
508
- ARMCPU *cpu = ARM_CPU(obj);
509
-
510
- cpu->dtb_compatible = "marvell,xscale";
511
- set_feature(&cpu->env, ARM_FEATURE_V5);
512
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
513
- cpu->midr = 0x69052d00;
514
- cpu->ctr = 0xd172172;
515
- cpu->reset_sctlr = 0x00000078;
516
-}
517
-
518
-static void pxa260_initfn(Object *obj)
519
-{
520
- ARMCPU *cpu = ARM_CPU(obj);
521
-
522
- cpu->dtb_compatible = "marvell,xscale";
523
- set_feature(&cpu->env, ARM_FEATURE_V5);
524
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
525
- cpu->midr = 0x69052903;
526
- cpu->ctr = 0xd172172;
527
- cpu->reset_sctlr = 0x00000078;
528
-}
529
-
530
-static void pxa261_initfn(Object *obj)
531
-{
532
- ARMCPU *cpu = ARM_CPU(obj);
533
-
534
- cpu->dtb_compatible = "marvell,xscale";
535
- set_feature(&cpu->env, ARM_FEATURE_V5);
536
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
537
- cpu->midr = 0x69052d05;
538
- cpu->ctr = 0xd172172;
539
- cpu->reset_sctlr = 0x00000078;
540
-}
541
-
542
-static void pxa262_initfn(Object *obj)
543
-{
544
- ARMCPU *cpu = ARM_CPU(obj);
545
-
546
- cpu->dtb_compatible = "marvell,xscale";
547
- set_feature(&cpu->env, ARM_FEATURE_V5);
548
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
549
- cpu->midr = 0x69052d06;
550
- cpu->ctr = 0xd172172;
551
- cpu->reset_sctlr = 0x00000078;
552
-}
553
-
554
-static void pxa270a0_initfn(Object *obj)
555
-{
556
- ARMCPU *cpu = ARM_CPU(obj);
557
-
558
- cpu->dtb_compatible = "marvell,xscale";
559
- set_feature(&cpu->env, ARM_FEATURE_V5);
560
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
561
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
562
- cpu->midr = 0x69054110;
563
- cpu->ctr = 0xd172172;
564
- cpu->reset_sctlr = 0x00000078;
565
-}
566
-
567
-static void pxa270a1_initfn(Object *obj)
568
-{
569
- ARMCPU *cpu = ARM_CPU(obj);
570
-
571
- cpu->dtb_compatible = "marvell,xscale";
572
- set_feature(&cpu->env, ARM_FEATURE_V5);
573
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
574
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
575
- cpu->midr = 0x69054111;
576
- cpu->ctr = 0xd172172;
577
- cpu->reset_sctlr = 0x00000078;
578
-}
579
-
580
-static void pxa270b0_initfn(Object *obj)
581
-{
582
- ARMCPU *cpu = ARM_CPU(obj);
583
-
584
- cpu->dtb_compatible = "marvell,xscale";
585
- set_feature(&cpu->env, ARM_FEATURE_V5);
586
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
587
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
588
- cpu->midr = 0x69054112;
589
- cpu->ctr = 0xd172172;
590
- cpu->reset_sctlr = 0x00000078;
591
-}
592
-
593
-static void pxa270b1_initfn(Object *obj)
594
-{
595
- ARMCPU *cpu = ARM_CPU(obj);
596
-
597
- cpu->dtb_compatible = "marvell,xscale";
598
- set_feature(&cpu->env, ARM_FEATURE_V5);
599
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
600
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
601
- cpu->midr = 0x69054113;
602
- cpu->ctr = 0xd172172;
603
- cpu->reset_sctlr = 0x00000078;
604
-}
605
-
606
-static void pxa270c0_initfn(Object *obj)
607
-{
608
- ARMCPU *cpu = ARM_CPU(obj);
609
-
610
- cpu->dtb_compatible = "marvell,xscale";
611
- set_feature(&cpu->env, ARM_FEATURE_V5);
612
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
613
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
614
- cpu->midr = 0x69054114;
615
- cpu->ctr = 0xd172172;
616
- cpu->reset_sctlr = 0x00000078;
617
-}
618
-
619
-static void pxa270c5_initfn(Object *obj)
620
-{
621
- ARMCPU *cpu = ARM_CPU(obj);
622
-
623
- cpu->dtb_compatible = "marvell,xscale";
624
- set_feature(&cpu->env, ARM_FEATURE_V5);
625
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
626
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
627
- cpu->midr = 0x69054117;
628
- cpu->ctr = 0xd172172;
629
- cpu->reset_sctlr = 0x00000078;
630
-}
631
-
632
#ifndef TARGET_AARCH64
633
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
634
* otherwise, a CPU with as many features enabled as our emulation supports.
635
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
636
637
static const ARMCPUInfo arm_cpus[] = {
638
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
639
- { .name = "arm926", .initfn = arm926_initfn },
640
- { .name = "arm946", .initfn = arm946_initfn },
641
- { .name = "arm1026", .initfn = arm1026_initfn },
642
- /*
643
- * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
644
- * older core than plain "arm1136". In particular this does not
645
- * have the v6K features.
646
- */
647
- { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
648
- { .name = "arm1136", .initfn = arm1136_initfn },
649
- { .name = "arm1176", .initfn = arm1176_initfn },
650
- { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
651
- { .name = "cortex-m0", .initfn = cortex_m0_initfn,
652
- .class_init = arm_v7m_class_init },
653
- { .name = "cortex-m3", .initfn = cortex_m3_initfn,
654
- .class_init = arm_v7m_class_init },
655
- { .name = "cortex-m4", .initfn = cortex_m4_initfn,
656
- .class_init = arm_v7m_class_init },
657
- { .name = "cortex-m7", .initfn = cortex_m7_initfn,
658
- .class_init = arm_v7m_class_init },
659
- { .name = "cortex-m33", .initfn = cortex_m33_initfn,
660
- .class_init = arm_v7m_class_init },
661
- { .name = "cortex-r5", .initfn = cortex_r5_initfn },
662
- { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
663
{ .name = "cortex-a7", .initfn = cortex_a7_initfn },
664
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
665
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
666
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
667
- { .name = "ti925t", .initfn = ti925t_initfn },
668
- { .name = "sa1100", .initfn = sa1100_initfn },
669
- { .name = "sa1110", .initfn = sa1110_initfn },
670
- { .name = "pxa250", .initfn = pxa250_initfn },
671
- { .name = "pxa255", .initfn = pxa255_initfn },
672
- { .name = "pxa260", .initfn = pxa260_initfn },
673
- { .name = "pxa261", .initfn = pxa261_initfn },
674
- { .name = "pxa262", .initfn = pxa262_initfn },
675
- /* "pxa270" is an alias for "pxa270-a0" */
676
- { .name = "pxa270", .initfn = pxa270a0_initfn },
677
- { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
678
- { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
679
- { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
680
- { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
681
- { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
682
- { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
683
#ifndef TARGET_AARCH64
684
{ .name = "max", .initfn = arm_max_initfn },
685
#endif
686
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
687
new file mode 100644
688
index XXXXXXX..XXXXXXX
689
--- /dev/null
690
+++ b/target/arm/cpu_tcg.c
691
@@ -XXX,XX +XXX,XX @@
692
+/*
693
+ * QEMU ARM TCG CPUs.
694
+ *
695
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
696
+ *
697
+ * This code is licensed under the GNU GPL v2 or later.
698
+ *
699
+ * SPDX-License-Identifier: GPL-2.0-or-later
700
+ */
701
+
702
+#include "qemu/osdep.h"
703
+#include "cpu.h"
704
+#include "internals.h"
705
+
706
+/* CPU models. These are not needed for the AArch64 linux-user build. */
707
+#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
708
+
709
+static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
710
+{
99
+{
711
+ CPUClass *cc = CPU_GET_CLASS(cs);
100
+ if (likely(sh < 64)) {
712
+ ARMCPU *cpu = ARM_CPU(cs);
101
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
713
+ CPUARMState *env = &cpu->env;
102
+ } else {
714
+ bool ret = false;
103
+ /* Rounding the sign bit always produces 0. */
715
+
104
+ return 0;
716
+ /*
717
+ * ARMv7-M interrupt masking works differently than -A or -R.
718
+ * There is no FIQ/IRQ distinction. Instead of I and F bits
719
+ * masking FIQ and IRQ interrupts, an exception is taken only
720
+ * if it is higher priority than the current execution priority
721
+ * (which depends on state like BASEPRI, FAULTMASK and the
722
+ * currently active exception).
723
+ */
724
+ if (interrupt_request & CPU_INTERRUPT_HARD
725
+ && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
726
+ cs->exception_index = EXCP_IRQ;
727
+ cc->do_interrupt(cs);
728
+ ret = true;
729
+ }
730
+ return ret;
731
+}
732
+
733
+static void arm926_initfn(Object *obj)
734
+{
735
+ ARMCPU *cpu = ARM_CPU(obj);
736
+
737
+ cpu->dtb_compatible = "arm,arm926";
738
+ set_feature(&cpu->env, ARM_FEATURE_V5);
739
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
740
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
741
+ cpu->midr = 0x41069265;
742
+ cpu->reset_fpsid = 0x41011090;
743
+ cpu->ctr = 0x1dd20d2;
744
+ cpu->reset_sctlr = 0x00090078;
745
+
746
+ /*
747
+ * ARMv5 does not have the ID_ISAR registers, but we can still
748
+ * set the field to indicate Jazelle support within QEMU.
749
+ */
750
+ cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
751
+ /*
752
+ * Similarly, we need to set MVFR0 fields to enable vfp and short vector
753
+ * support even though ARMv5 doesn't have this register.
754
+ */
755
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
756
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
757
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
758
+}
759
+
760
+static void arm946_initfn(Object *obj)
761
+{
762
+ ARMCPU *cpu = ARM_CPU(obj);
763
+
764
+ cpu->dtb_compatible = "arm,arm946";
765
+ set_feature(&cpu->env, ARM_FEATURE_V5);
766
+ set_feature(&cpu->env, ARM_FEATURE_PMSA);
767
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
768
+ cpu->midr = 0x41059461;
769
+ cpu->ctr = 0x0f004006;
770
+ cpu->reset_sctlr = 0x00000078;
771
+}
772
+
773
+static void arm1026_initfn(Object *obj)
774
+{
775
+ ARMCPU *cpu = ARM_CPU(obj);
776
+
777
+ cpu->dtb_compatible = "arm,arm1026";
778
+ set_feature(&cpu->env, ARM_FEATURE_V5);
779
+ set_feature(&cpu->env, ARM_FEATURE_AUXCR);
780
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
781
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
782
+ cpu->midr = 0x4106a262;
783
+ cpu->reset_fpsid = 0x410110a0;
784
+ cpu->ctr = 0x1dd20d2;
785
+ cpu->reset_sctlr = 0x00090078;
786
+ cpu->reset_auxcr = 1;
787
+
788
+ /*
789
+ * ARMv5 does not have the ID_ISAR registers, but we can still
790
+ * set the field to indicate Jazelle support within QEMU.
791
+ */
792
+ cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
793
+ /*
794
+ * Similarly, we need to set MVFR0 fields to enable vfp and short vector
795
+ * support even though ARMv5 doesn't have this register.
796
+ */
797
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
798
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
799
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
800
+
801
+ {
802
+ /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
803
+ ARMCPRegInfo ifar = {
804
+ .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
805
+ .access = PL1_RW,
806
+ .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
807
+ .resetvalue = 0
808
+ };
809
+ define_one_arm_cp_reg(cpu, &ifar);
810
+ }
105
+ }
811
+}
106
+}
812
+
107
+
813
+static void arm1136_r2_initfn(Object *obj)
108
DO_VSHRN_ALL(vshrn, DO_SHR)
109
DO_VSHRN_ALL(vrshrn, do_urshr)
110
+
111
+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
112
+ bool *satp)
814
+{
113
+{
815
+ ARMCPU *cpu = ARM_CPU(obj);
114
+ if (val > max) {
816
+ /*
115
+ *satp = true;
817
+ * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
116
+ return max;
818
+ * older core than plain "arm1136". In particular this does not
117
+ } else if (val < min) {
819
+ * have the v6K features.
118
+ *satp = true;
820
+ * These ID register values are correct for 1136 but may be wrong
119
+ return min;
821
+ * for 1136_r2 (in particular r0p2 does not actually implement most
120
+ } else {
822
+ * of the ID registers).
121
+ return val;
823
+ */
824
+
825
+ cpu->dtb_compatible = "arm,arm1136";
826
+ set_feature(&cpu->env, ARM_FEATURE_V6);
827
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
828
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
829
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
830
+ cpu->midr = 0x4107b362;
831
+ cpu->reset_fpsid = 0x410120b4;
832
+ cpu->isar.mvfr0 = 0x11111111;
833
+ cpu->isar.mvfr1 = 0x00000000;
834
+ cpu->ctr = 0x1dd20d2;
835
+ cpu->reset_sctlr = 0x00050078;
836
+ cpu->id_pfr0 = 0x111;
837
+ cpu->id_pfr1 = 0x1;
838
+ cpu->isar.id_dfr0 = 0x2;
839
+ cpu->id_afr0 = 0x3;
840
+ cpu->isar.id_mmfr0 = 0x01130003;
841
+ cpu->isar.id_mmfr1 = 0x10030302;
842
+ cpu->isar.id_mmfr2 = 0x01222110;
843
+ cpu->isar.id_isar0 = 0x00140011;
844
+ cpu->isar.id_isar1 = 0x12002111;
845
+ cpu->isar.id_isar2 = 0x11231111;
846
+ cpu->isar.id_isar3 = 0x01102131;
847
+ cpu->isar.id_isar4 = 0x141;
848
+ cpu->reset_auxcr = 7;
849
+}
850
+
851
+static void arm1136_initfn(Object *obj)
852
+{
853
+ ARMCPU *cpu = ARM_CPU(obj);
854
+
855
+ cpu->dtb_compatible = "arm,arm1136";
856
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
857
+ set_feature(&cpu->env, ARM_FEATURE_V6);
858
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
859
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
860
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
861
+ cpu->midr = 0x4117b363;
862
+ cpu->reset_fpsid = 0x410120b4;
863
+ cpu->isar.mvfr0 = 0x11111111;
864
+ cpu->isar.mvfr1 = 0x00000000;
865
+ cpu->ctr = 0x1dd20d2;
866
+ cpu->reset_sctlr = 0x00050078;
867
+ cpu->id_pfr0 = 0x111;
868
+ cpu->id_pfr1 = 0x1;
869
+ cpu->isar.id_dfr0 = 0x2;
870
+ cpu->id_afr0 = 0x3;
871
+ cpu->isar.id_mmfr0 = 0x01130003;
872
+ cpu->isar.id_mmfr1 = 0x10030302;
873
+ cpu->isar.id_mmfr2 = 0x01222110;
874
+ cpu->isar.id_isar0 = 0x00140011;
875
+ cpu->isar.id_isar1 = 0x12002111;
876
+ cpu->isar.id_isar2 = 0x11231111;
877
+ cpu->isar.id_isar3 = 0x01102131;
878
+ cpu->isar.id_isar4 = 0x141;
879
+ cpu->reset_auxcr = 7;
880
+}
881
+
882
+static void arm1176_initfn(Object *obj)
883
+{
884
+ ARMCPU *cpu = ARM_CPU(obj);
885
+
886
+ cpu->dtb_compatible = "arm,arm1176";
887
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
888
+ set_feature(&cpu->env, ARM_FEATURE_VAPA);
889
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
890
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
891
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
892
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
893
+ cpu->midr = 0x410fb767;
894
+ cpu->reset_fpsid = 0x410120b5;
895
+ cpu->isar.mvfr0 = 0x11111111;
896
+ cpu->isar.mvfr1 = 0x00000000;
897
+ cpu->ctr = 0x1dd20d2;
898
+ cpu->reset_sctlr = 0x00050078;
899
+ cpu->id_pfr0 = 0x111;
900
+ cpu->id_pfr1 = 0x11;
901
+ cpu->isar.id_dfr0 = 0x33;
902
+ cpu->id_afr0 = 0;
903
+ cpu->isar.id_mmfr0 = 0x01130003;
904
+ cpu->isar.id_mmfr1 = 0x10030302;
905
+ cpu->isar.id_mmfr2 = 0x01222100;
906
+ cpu->isar.id_isar0 = 0x0140011;
907
+ cpu->isar.id_isar1 = 0x12002111;
908
+ cpu->isar.id_isar2 = 0x11231121;
909
+ cpu->isar.id_isar3 = 0x01102131;
910
+ cpu->isar.id_isar4 = 0x01141;
911
+ cpu->reset_auxcr = 7;
912
+}
913
+
914
+static void arm11mpcore_initfn(Object *obj)
915
+{
916
+ ARMCPU *cpu = ARM_CPU(obj);
917
+
918
+ cpu->dtb_compatible = "arm,arm11mpcore";
919
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
920
+ set_feature(&cpu->env, ARM_FEATURE_VAPA);
921
+ set_feature(&cpu->env, ARM_FEATURE_MPIDR);
922
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
923
+ cpu->midr = 0x410fb022;
924
+ cpu->reset_fpsid = 0x410120b4;
925
+ cpu->isar.mvfr0 = 0x11111111;
926
+ cpu->isar.mvfr1 = 0x00000000;
927
+ cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
928
+ cpu->id_pfr0 = 0x111;
929
+ cpu->id_pfr1 = 0x1;
930
+ cpu->isar.id_dfr0 = 0;
931
+ cpu->id_afr0 = 0x2;
932
+ cpu->isar.id_mmfr0 = 0x01100103;
933
+ cpu->isar.id_mmfr1 = 0x10020302;
934
+ cpu->isar.id_mmfr2 = 0x01222000;
935
+ cpu->isar.id_isar0 = 0x00100011;
936
+ cpu->isar.id_isar1 = 0x12002111;
937
+ cpu->isar.id_isar2 = 0x11221011;
938
+ cpu->isar.id_isar3 = 0x01102131;
939
+ cpu->isar.id_isar4 = 0x141;
940
+ cpu->reset_auxcr = 1;
941
+}
942
+
943
+static void cortex_m0_initfn(Object *obj)
944
+{
945
+ ARMCPU *cpu = ARM_CPU(obj);
946
+ set_feature(&cpu->env, ARM_FEATURE_V6);
947
+ set_feature(&cpu->env, ARM_FEATURE_M);
948
+
949
+ cpu->midr = 0x410cc200;
950
+}
951
+
952
+static void cortex_m3_initfn(Object *obj)
953
+{
954
+ ARMCPU *cpu = ARM_CPU(obj);
955
+ set_feature(&cpu->env, ARM_FEATURE_V7);
956
+ set_feature(&cpu->env, ARM_FEATURE_M);
957
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
958
+ cpu->midr = 0x410fc231;
959
+ cpu->pmsav7_dregion = 8;
960
+ cpu->id_pfr0 = 0x00000030;
961
+ cpu->id_pfr1 = 0x00000200;
962
+ cpu->isar.id_dfr0 = 0x00100000;
963
+ cpu->id_afr0 = 0x00000000;
964
+ cpu->isar.id_mmfr0 = 0x00000030;
965
+ cpu->isar.id_mmfr1 = 0x00000000;
966
+ cpu->isar.id_mmfr2 = 0x00000000;
967
+ cpu->isar.id_mmfr3 = 0x00000000;
968
+ cpu->isar.id_isar0 = 0x01141110;
969
+ cpu->isar.id_isar1 = 0x02111000;
970
+ cpu->isar.id_isar2 = 0x21112231;
971
+ cpu->isar.id_isar3 = 0x01111110;
972
+ cpu->isar.id_isar4 = 0x01310102;
973
+ cpu->isar.id_isar5 = 0x00000000;
974
+ cpu->isar.id_isar6 = 0x00000000;
975
+}
976
+
977
+static void cortex_m4_initfn(Object *obj)
978
+{
979
+ ARMCPU *cpu = ARM_CPU(obj);
980
+
981
+ set_feature(&cpu->env, ARM_FEATURE_V7);
982
+ set_feature(&cpu->env, ARM_FEATURE_M);
983
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
984
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
985
+ cpu->midr = 0x410fc240; /* r0p0 */
986
+ cpu->pmsav7_dregion = 8;
987
+ cpu->isar.mvfr0 = 0x10110021;
988
+ cpu->isar.mvfr1 = 0x11000011;
989
+ cpu->isar.mvfr2 = 0x00000000;
990
+ cpu->id_pfr0 = 0x00000030;
991
+ cpu->id_pfr1 = 0x00000200;
992
+ cpu->isar.id_dfr0 = 0x00100000;
993
+ cpu->id_afr0 = 0x00000000;
994
+ cpu->isar.id_mmfr0 = 0x00000030;
995
+ cpu->isar.id_mmfr1 = 0x00000000;
996
+ cpu->isar.id_mmfr2 = 0x00000000;
997
+ cpu->isar.id_mmfr3 = 0x00000000;
998
+ cpu->isar.id_isar0 = 0x01141110;
999
+ cpu->isar.id_isar1 = 0x02111000;
1000
+ cpu->isar.id_isar2 = 0x21112231;
1001
+ cpu->isar.id_isar3 = 0x01111110;
1002
+ cpu->isar.id_isar4 = 0x01310102;
1003
+ cpu->isar.id_isar5 = 0x00000000;
1004
+ cpu->isar.id_isar6 = 0x00000000;
1005
+}
1006
+
1007
+static void cortex_m7_initfn(Object *obj)
1008
+{
1009
+ ARMCPU *cpu = ARM_CPU(obj);
1010
+
1011
+ set_feature(&cpu->env, ARM_FEATURE_V7);
1012
+ set_feature(&cpu->env, ARM_FEATURE_M);
1013
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1014
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1015
+ cpu->midr = 0x411fc272; /* r1p2 */
1016
+ cpu->pmsav7_dregion = 8;
1017
+ cpu->isar.mvfr0 = 0x10110221;
1018
+ cpu->isar.mvfr1 = 0x12000011;
1019
+ cpu->isar.mvfr2 = 0x00000040;
1020
+ cpu->id_pfr0 = 0x00000030;
1021
+ cpu->id_pfr1 = 0x00000200;
1022
+ cpu->isar.id_dfr0 = 0x00100000;
1023
+ cpu->id_afr0 = 0x00000000;
1024
+ cpu->isar.id_mmfr0 = 0x00100030;
1025
+ cpu->isar.id_mmfr1 = 0x00000000;
1026
+ cpu->isar.id_mmfr2 = 0x01000000;
1027
+ cpu->isar.id_mmfr3 = 0x00000000;
1028
+ cpu->isar.id_isar0 = 0x01101110;
1029
+ cpu->isar.id_isar1 = 0x02112000;
1030
+ cpu->isar.id_isar2 = 0x20232231;
1031
+ cpu->isar.id_isar3 = 0x01111131;
1032
+ cpu->isar.id_isar4 = 0x01310132;
1033
+ cpu->isar.id_isar5 = 0x00000000;
1034
+ cpu->isar.id_isar6 = 0x00000000;
1035
+}
1036
+
1037
+static void cortex_m33_initfn(Object *obj)
1038
+{
1039
+ ARMCPU *cpu = ARM_CPU(obj);
1040
+
1041
+ set_feature(&cpu->env, ARM_FEATURE_V8);
1042
+ set_feature(&cpu->env, ARM_FEATURE_M);
1043
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1044
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
1045
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1046
+ cpu->midr = 0x410fd213; /* r0p3 */
1047
+ cpu->pmsav7_dregion = 16;
1048
+ cpu->sau_sregion = 8;
1049
+ cpu->isar.mvfr0 = 0x10110021;
1050
+ cpu->isar.mvfr1 = 0x11000011;
1051
+ cpu->isar.mvfr2 = 0x00000040;
1052
+ cpu->id_pfr0 = 0x00000030;
1053
+ cpu->id_pfr1 = 0x00000210;
1054
+ cpu->isar.id_dfr0 = 0x00200000;
1055
+ cpu->id_afr0 = 0x00000000;
1056
+ cpu->isar.id_mmfr0 = 0x00101F40;
1057
+ cpu->isar.id_mmfr1 = 0x00000000;
1058
+ cpu->isar.id_mmfr2 = 0x01000000;
1059
+ cpu->isar.id_mmfr3 = 0x00000000;
1060
+ cpu->isar.id_isar0 = 0x01101110;
1061
+ cpu->isar.id_isar1 = 0x02212000;
1062
+ cpu->isar.id_isar2 = 0x20232232;
1063
+ cpu->isar.id_isar3 = 0x01111131;
1064
+ cpu->isar.id_isar4 = 0x01310132;
1065
+ cpu->isar.id_isar5 = 0x00000000;
1066
+ cpu->isar.id_isar6 = 0x00000000;
1067
+ cpu->clidr = 0x00000000;
1068
+ cpu->ctr = 0x8000c000;
1069
+}
1070
+
1071
+static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
1072
+ /* Dummy the TCM region regs for the moment */
1073
+ { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1074
+ .access = PL1_RW, .type = ARM_CP_CONST },
1075
+ { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1076
+ .access = PL1_RW, .type = ARM_CP_CONST },
1077
+ { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
1078
+ .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
1079
+ REGINFO_SENTINEL
1080
+};
1081
+
1082
+static void cortex_r5_initfn(Object *obj)
1083
+{
1084
+ ARMCPU *cpu = ARM_CPU(obj);
1085
+
1086
+ set_feature(&cpu->env, ARM_FEATURE_V7);
1087
+ set_feature(&cpu->env, ARM_FEATURE_V7MP);
1088
+ set_feature(&cpu->env, ARM_FEATURE_PMSA);
1089
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
1090
+ cpu->midr = 0x411fc153; /* r1p3 */
1091
+ cpu->id_pfr0 = 0x0131;
1092
+ cpu->id_pfr1 = 0x001;
1093
+ cpu->isar.id_dfr0 = 0x010400;
1094
+ cpu->id_afr0 = 0x0;
1095
+ cpu->isar.id_mmfr0 = 0x0210030;
1096
+ cpu->isar.id_mmfr1 = 0x00000000;
1097
+ cpu->isar.id_mmfr2 = 0x01200000;
1098
+ cpu->isar.id_mmfr3 = 0x0211;
1099
+ cpu->isar.id_isar0 = 0x02101111;
1100
+ cpu->isar.id_isar1 = 0x13112111;
1101
+ cpu->isar.id_isar2 = 0x21232141;
1102
+ cpu->isar.id_isar3 = 0x01112131;
1103
+ cpu->isar.id_isar4 = 0x0010142;
1104
+ cpu->isar.id_isar5 = 0x0;
1105
+ cpu->isar.id_isar6 = 0x0;
1106
+ cpu->mp_is_up = true;
1107
+ cpu->pmsav7_dregion = 16;
1108
+ define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
1109
+}
1110
+
1111
+static void cortex_r5f_initfn(Object *obj)
1112
+{
1113
+ ARMCPU *cpu = ARM_CPU(obj);
1114
+
1115
+ cortex_r5_initfn(obj);
1116
+ cpu->isar.mvfr0 = 0x10110221;
1117
+ cpu->isar.mvfr1 = 0x00000011;
1118
+}
1119
+
1120
+static void ti925t_initfn(Object *obj)
1121
+{
1122
+ ARMCPU *cpu = ARM_CPU(obj);
1123
+ set_feature(&cpu->env, ARM_FEATURE_V4T);
1124
+ set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1125
+ cpu->midr = ARM_CPUID_TI925T;
1126
+ cpu->ctr = 0x5109149;
1127
+ cpu->reset_sctlr = 0x00000070;
1128
+}
1129
+
1130
+static void sa1100_initfn(Object *obj)
1131
+{
1132
+ ARMCPU *cpu = ARM_CPU(obj);
1133
+
1134
+ cpu->dtb_compatible = "intel,sa1100";
1135
+ set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1136
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1137
+ cpu->midr = 0x4401A11B;
1138
+ cpu->reset_sctlr = 0x00000070;
1139
+}
1140
+
1141
+static void sa1110_initfn(Object *obj)
1142
+{
1143
+ ARMCPU *cpu = ARM_CPU(obj);
1144
+ set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1145
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1146
+ cpu->midr = 0x6901B119;
1147
+ cpu->reset_sctlr = 0x00000070;
1148
+}
1149
+
1150
+static void pxa250_initfn(Object *obj)
1151
+{
1152
+ ARMCPU *cpu = ARM_CPU(obj);
1153
+
1154
+ cpu->dtb_compatible = "marvell,xscale";
1155
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1156
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1157
+ cpu->midr = 0x69052100;
1158
+ cpu->ctr = 0xd172172;
1159
+ cpu->reset_sctlr = 0x00000078;
1160
+}
1161
+
1162
+static void pxa255_initfn(Object *obj)
1163
+{
1164
+ ARMCPU *cpu = ARM_CPU(obj);
1165
+
1166
+ cpu->dtb_compatible = "marvell,xscale";
1167
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1168
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1169
+ cpu->midr = 0x69052d00;
1170
+ cpu->ctr = 0xd172172;
1171
+ cpu->reset_sctlr = 0x00000078;
1172
+}
1173
+
1174
+static void pxa260_initfn(Object *obj)
1175
+{
1176
+ ARMCPU *cpu = ARM_CPU(obj);
1177
+
1178
+ cpu->dtb_compatible = "marvell,xscale";
1179
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1180
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1181
+ cpu->midr = 0x69052903;
1182
+ cpu->ctr = 0xd172172;
1183
+ cpu->reset_sctlr = 0x00000078;
1184
+}
1185
+
1186
+static void pxa261_initfn(Object *obj)
1187
+{
1188
+ ARMCPU *cpu = ARM_CPU(obj);
1189
+
1190
+ cpu->dtb_compatible = "marvell,xscale";
1191
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1192
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1193
+ cpu->midr = 0x69052d05;
1194
+ cpu->ctr = 0xd172172;
1195
+ cpu->reset_sctlr = 0x00000078;
1196
+}
1197
+
1198
+static void pxa262_initfn(Object *obj)
1199
+{
1200
+ ARMCPU *cpu = ARM_CPU(obj);
1201
+
1202
+ cpu->dtb_compatible = "marvell,xscale";
1203
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1204
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1205
+ cpu->midr = 0x69052d06;
1206
+ cpu->ctr = 0xd172172;
1207
+ cpu->reset_sctlr = 0x00000078;
1208
+}
1209
+
1210
+static void pxa270a0_initfn(Object *obj)
1211
+{
1212
+ ARMCPU *cpu = ARM_CPU(obj);
1213
+
1214
+ cpu->dtb_compatible = "marvell,xscale";
1215
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1216
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1217
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1218
+ cpu->midr = 0x69054110;
1219
+ cpu->ctr = 0xd172172;
1220
+ cpu->reset_sctlr = 0x00000078;
1221
+}
1222
+
1223
+static void pxa270a1_initfn(Object *obj)
1224
+{
1225
+ ARMCPU *cpu = ARM_CPU(obj);
1226
+
1227
+ cpu->dtb_compatible = "marvell,xscale";
1228
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1229
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1230
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1231
+ cpu->midr = 0x69054111;
1232
+ cpu->ctr = 0xd172172;
1233
+ cpu->reset_sctlr = 0x00000078;
1234
+}
1235
+
1236
+static void pxa270b0_initfn(Object *obj)
1237
+{
1238
+ ARMCPU *cpu = ARM_CPU(obj);
1239
+
1240
+ cpu->dtb_compatible = "marvell,xscale";
1241
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1242
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1243
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1244
+ cpu->midr = 0x69054112;
1245
+ cpu->ctr = 0xd172172;
1246
+ cpu->reset_sctlr = 0x00000078;
1247
+}
1248
+
1249
+static void pxa270b1_initfn(Object *obj)
1250
+{
1251
+ ARMCPU *cpu = ARM_CPU(obj);
1252
+
1253
+ cpu->dtb_compatible = "marvell,xscale";
1254
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1255
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1256
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1257
+ cpu->midr = 0x69054113;
1258
+ cpu->ctr = 0xd172172;
1259
+ cpu->reset_sctlr = 0x00000078;
1260
+}
1261
+
1262
+static void pxa270c0_initfn(Object *obj)
1263
+{
1264
+ ARMCPU *cpu = ARM_CPU(obj);
1265
+
1266
+ cpu->dtb_compatible = "marvell,xscale";
1267
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1268
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1269
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1270
+ cpu->midr = 0x69054114;
1271
+ cpu->ctr = 0xd172172;
1272
+ cpu->reset_sctlr = 0x00000078;
1273
+}
1274
+
1275
+static void pxa270c5_initfn(Object *obj)
1276
+{
1277
+ ARMCPU *cpu = ARM_CPU(obj);
1278
+
1279
+ cpu->dtb_compatible = "marvell,xscale";
1280
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1281
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1282
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1283
+ cpu->midr = 0x69054117;
1284
+ cpu->ctr = 0xd172172;
1285
+ cpu->reset_sctlr = 0x00000078;
1286
+}
1287
+
1288
+static void arm_v7m_class_init(ObjectClass *oc, void *data)
1289
+{
1290
+ ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1291
+ CPUClass *cc = CPU_CLASS(oc);
1292
+
1293
+ acc->info = data;
1294
+#ifndef CONFIG_USER_ONLY
1295
+ cc->do_interrupt = arm_v7m_cpu_do_interrupt;
1296
+#endif
1297
+
1298
+ cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
1299
+}
1300
+
1301
+static const ARMCPUInfo arm_tcg_cpus[] = {
1302
+ { .name = "arm926", .initfn = arm926_initfn },
1303
+ { .name = "arm946", .initfn = arm946_initfn },
1304
+ { .name = "arm1026", .initfn = arm1026_initfn },
1305
+ /*
1306
+ * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1307
+ * older core than plain "arm1136". In particular this does not
1308
+ * have the v6K features.
1309
+ */
1310
+ { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1311
+ { .name = "arm1136", .initfn = arm1136_initfn },
1312
+ { .name = "arm1176", .initfn = arm1176_initfn },
1313
+ { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1314
+ { .name = "cortex-m0", .initfn = cortex_m0_initfn,
1315
+ .class_init = arm_v7m_class_init },
1316
+ { .name = "cortex-m3", .initfn = cortex_m3_initfn,
1317
+ .class_init = arm_v7m_class_init },
1318
+ { .name = "cortex-m4", .initfn = cortex_m4_initfn,
1319
+ .class_init = arm_v7m_class_init },
1320
+ { .name = "cortex-m7", .initfn = cortex_m7_initfn,
1321
+ .class_init = arm_v7m_class_init },
1322
+ { .name = "cortex-m33", .initfn = cortex_m33_initfn,
1323
+ .class_init = arm_v7m_class_init },
1324
+ { .name = "cortex-r5", .initfn = cortex_r5_initfn },
1325
+ { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
1326
+ { .name = "ti925t", .initfn = ti925t_initfn },
1327
+ { .name = "sa1100", .initfn = sa1100_initfn },
1328
+ { .name = "sa1110", .initfn = sa1110_initfn },
1329
+ { .name = "pxa250", .initfn = pxa250_initfn },
1330
+ { .name = "pxa255", .initfn = pxa255_initfn },
1331
+ { .name = "pxa260", .initfn = pxa260_initfn },
1332
+ { .name = "pxa261", .initfn = pxa261_initfn },
1333
+ { .name = "pxa262", .initfn = pxa262_initfn },
1334
+ /* "pxa270" is an alias for "pxa270-a0" */
1335
+ { .name = "pxa270", .initfn = pxa270a0_initfn },
1336
+ { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1337
+ { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1338
+ { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1339
+ { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1340
+ { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1341
+ { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
1342
+};
1343
+
1344
+static void arm_tcg_cpu_register_types(void)
1345
+{
1346
+ size_t i;
1347
+
1348
+ for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
1349
+ arm_cpu_register(&arm_tcg_cpus[i]);
1350
+ }
122
+ }
1351
+}
123
+}
1352
+
124
+
1353
+type_init(arm_tcg_cpu_register_types)
125
+/* Saturating narrowing right shifts */
1354
+
126
+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
1355
+#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
127
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
1356
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
128
+ void *vm, uint32_t shift) \
1357
index XXXXXXX..XXXXXXX 100644
129
+ { \
1358
--- a/target/arm/Makefile.objs
130
+ LTYPE *m = vm; \
1359
+++ b/target/arm/Makefile.objs
131
+ TYPE *d = vd; \
1360
@@ -XXX,XX +XXX,XX @@ obj-y += translate.o op_helper.o
132
+ uint16_t mask = mve_element_mask(env); \
1361
obj-y += crypto_helper.o
133
+ bool qc = false; \
1362
obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
134
+ unsigned le; \
1363
obj-y += m_helper.o
135
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
1364
+obj-y += cpu_tcg.o
136
+ bool sat = false; \
1365
137
+ TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \
1366
obj-$(CONFIG_SOFTMMU) += psci.o
138
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
1367
139
+ qc |= sat && (mask & 1 << (TOP * ESIZE)); \
140
+ } \
141
+ if (qc) { \
142
+ env->vfp.qc[0] = qc; \
143
+ } \
144
+ mve_advance_vpt(env); \
145
+ }
146
+
147
+#define DO_VSHRN_SAT_UB(BOP, TOP, FN) \
148
+ DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \
149
+ DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
150
+
151
+#define DO_VSHRN_SAT_UH(BOP, TOP, FN) \
152
+ DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \
153
+ DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
154
+
155
+#define DO_VSHRN_SAT_SB(BOP, TOP, FN) \
156
+ DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \
157
+ DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
158
+
159
+#define DO_VSHRN_SAT_SH(BOP, TOP, FN) \
160
+ DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \
161
+ DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
162
+
163
+#define DO_SHRN_SB(N, M, SATP) \
164
+ do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
165
+#define DO_SHRN_UB(N, M, SATP) \
166
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
167
+#define DO_SHRUN_B(N, M, SATP) \
168
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
169
+
170
+#define DO_SHRN_SH(N, M, SATP) \
171
+ do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
172
+#define DO_SHRN_UH(N, M, SATP) \
173
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
174
+#define DO_SHRUN_H(N, M, SATP) \
175
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
176
+
177
+#define DO_RSHRN_SB(N, M, SATP) \
178
+ do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
179
+#define DO_RSHRN_UB(N, M, SATP) \
180
+ do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
181
+#define DO_RSHRUN_B(N, M, SATP) \
182
+ do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
183
+
184
+#define DO_RSHRN_SH(N, M, SATP) \
185
+ do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
186
+#define DO_RSHRN_UH(N, M, SATP) \
187
+ do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
188
+#define DO_RSHRUN_H(N, M, SATP) \
189
+ do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
190
+
191
+DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
192
+DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
193
+DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
194
+DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
195
+DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
196
+DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
197
+
198
+DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
199
+DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
200
+DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
201
+DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
202
+DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
203
+DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
204
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
205
index XXXXXXX..XXXXXXX 100644
206
--- a/target/arm/translate-mve.c
207
+++ b/target/arm/translate-mve.c
208
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
209
DO_2SHIFT_N(VSHRNT, vshrnt)
210
DO_2SHIFT_N(VRSHRNB, vrshrnb)
211
DO_2SHIFT_N(VRSHRNT, vrshrnt)
212
+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
213
+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
214
+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
215
+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
216
+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
217
+DO_2SHIFT_N(VQSHRUNT, vqshrunt)
218
+DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
219
+DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
220
+DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
221
+DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
222
+DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
223
+DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
1368
--
224
--
1369
2.20.1
225
2.20.1
1370
226
1371
227
diff view generated by jsdifflib
[PULL 29/34] target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]
[PULL 19/24] target/arm: Implement MVE VSHLC
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Implement the MVE VSHLC insn, which performs a shift left of the
2
entire vector with carry in bits provided from a general purpose
3
register and carry out bits written back to that register.
2
4
3
Use ARRAY_SIZE() to iterate over ARMCPUInfo[].
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
8
---
9
target/arm/helper-mve.h | 2 ++
10
target/arm/mve.decode | 2 ++
11
target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
13
4 files changed, 72 insertions(+)
4
14
5
Since on the aarch64-linux-user build, arm_cpus[] is empty, add
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
6
the cpu_count variable and only iterate when it is non-zero.
7
8
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20200504172448.9402-4-philmd@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/cpu.c | 16 +++++++++-------
15
target/arm/cpu64.c | 8 +++-----
16
2 files changed, 12 insertions(+), 12 deletions(-)
17
18
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.c
17
--- a/target/arm/helper-mve.h
21
+++ b/target/arm/cpu.c
18
+++ b/target/arm/helper-mve.h
22
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
{ .name = "any", .initfn = arm_max_initfn },
20
DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
#endif
21
DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
#endif
22
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
- { .name = NULL }
27
};
28
29
static Property arm_cpu_properties[] = {
30
@@ -XXX,XX +XXX,XX @@ static const TypeInfo idau_interface_type_info = {
31
32
static void arm_cpu_register_types(void)
33
{
34
- const ARMCPUInfo *info = arm_cpus;
35
+ const size_t cpu_count = ARRAY_SIZE(arm_cpus);
36
37
type_register_static(&arm_cpu_type_info);
38
type_register_static(&idau_interface_type_info);
39
40
- while (info->name) {
41
- arm_cpu_register(info);
42
- info++;
43
- }
44
-
45
#ifdef CONFIG_KVM
46
type_register_static(&host_arm_cpu_type_info);
47
#endif
48
+
23
+
49
+ if (cpu_count) {
24
+DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
50
+ size_t i;
25
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/mve.decode
28
+++ b/target/arm/mve.decode
29
@@ -XXX,XX +XXX,XX @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
30
VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
31
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
32
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
51
+
33
+
52
+ for (i = 0; i < cpu_count; ++i) {
34
+VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
53
+ arm_cpu_register(&arm_cpus[i]);
35
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/mve_helper.c
38
+++ b/target/arm/mve_helper.c
39
@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
40
DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
41
DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
42
DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
43
+
44
+uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
45
+ uint32_t shift)
46
+{
47
+ uint32_t *d = vd;
48
+ uint16_t mask = mve_element_mask(env);
49
+ unsigned e;
50
+ uint32_t r;
51
+
52
+ /*
53
+ * For each 32-bit element, we shift it left, bringing in the
54
+ * low 'shift' bits of rdm at the bottom. Bits shifted out at
55
+ * the top become the new rdm, if the predicate mask permits.
56
+ * The final rdm value is returned to update the register.
57
+ * shift == 0 here means "shift by 32 bits".
58
+ */
59
+ if (shift == 0) {
60
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
61
+ r = rdm;
62
+ if (mask & 1) {
63
+ rdm = d[H4(e)];
64
+ }
65
+ mergemask(&d[H4(e)], r, mask);
66
+ }
67
+ } else {
68
+ uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
69
+
70
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
71
+ r = (d[H4(e)] << shift) | (rdm & shiftmask);
72
+ if (mask & 1) {
73
+ rdm = d[H4(e)] >> (32 - shift);
74
+ }
75
+ mergemask(&d[H4(e)], r, mask);
54
+ }
76
+ }
55
+ }
77
+ }
56
}
78
+ mve_advance_vpt(env);
57
79
+ return rdm;
58
type_init(arm_cpu_register_types)
80
+}
59
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
81
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
60
index XXXXXXX..XXXXXXX 100644
82
index XXXXXXX..XXXXXXX 100644
61
--- a/target/arm/cpu64.c
83
--- a/target/arm/translate-mve.c
62
+++ b/target/arm/cpu64.c
84
+++ b/target/arm/translate-mve.c
63
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
85
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
64
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
86
DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
65
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
87
DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
66
{ .name = "max", .initfn = aarch64_max_initfn },
88
DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
67
- { .name = NULL }
89
+
68
};
90
+static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
69
91
+{
70
static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
92
+ /*
71
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aarch64_cpu_type_info = {
93
+ * Whole Vector Left Shift with Carry. The carry is taken
72
94
+ * from a general purpose register and written back there.
73
static void aarch64_cpu_register_types(void)
95
+ * An imm of 0 means "shift by 32".
74
{
96
+ */
75
- const ARMCPUInfo *info = aarch64_cpus;
97
+ TCGv_ptr qd;
76
+ size_t i;
98
+ TCGv_i32 rdm;
77
99
+
78
type_register_static(&aarch64_cpu_type_info);
100
+ if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
79
101
+ return false;
80
- while (info->name) {
102
+ }
81
- aarch64_cpu_register(info);
103
+ if (a->rdm == 13 || a->rdm == 15) {
82
- info++;
104
+ /* CONSTRAINED UNPREDICTABLE: we UNDEF */
83
+ for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
105
+ return false;
84
+ aarch64_cpu_register(&aarch64_cpus[i]);
106
+ }
85
}
107
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
86
}
108
+ return true;
87
109
+ }
110
+
111
+ qd = mve_qreg_ptr(a->qd);
112
+ rdm = load_reg(s, a->rdm);
113
+ gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
114
+ store_reg(s, a->rdm, rdm);
115
+ tcg_temp_free_ptr(qd);
116
+ mve_update_eci(s);
117
+ return true;
118
+}
88
--
119
--
89
2.20.1
120
2.20.1
90
121
91
122
diff view generated by jsdifflib
[PULL 16/34] target/arm: Add sve infrastructure for page lookup
[PULL 20/24] target/arm: Implement MVE VADDLV
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the MVE VADDLV insn; this is similar to VADDV, except
2
that it accumulates 32-bit elements into a 64-bit accumulator
3
stored in a pair of general-purpose registers.
2
4
3
For contiguous predicated memory operations, we want to
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
minimize the number of tlb lookups performed. We have
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
open-coded this for sve_ld1_r, but for correctness with
7
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
6
MTE we will need this for all of the memory operations.
8
---
9
target/arm/helper-mve.h | 3 ++
10
target/arm/mve.decode | 6 +++-
11
target/arm/mve_helper.c | 19 ++++++++++++
12
target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
13
4 files changed, 90 insertions(+), 1 deletion(-)
7
14
8
Create a structure that holds the bounds of active elements,
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
9
and metadata for two pages. Add routines to find those
10
active elements, lookup the pages, and run watchpoints
11
for those pages.
12
13
Temporarily mark the functions unused to avoid Werror.
14
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20200508154359.7494-10-richard.henderson@linaro.org
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
target/arm/sve_helper.c | 263 +++++++++++++++++++++++++++++++++++++++-
21
1 file changed, 261 insertions(+), 2 deletions(-)
22
23
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
24
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/sve_helper.c
17
--- a/target/arm/helper-mve.h
26
+++ b/target/arm/sve_helper.c
18
+++ b/target/arm/helper-mve.h
27
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_cpy_z_d)(void *vd, void *vg, uint64_t val, uint32_t desc)
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
28
}
20
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
21
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
23
+DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
24
+DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
25
+
26
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
27
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
28
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
29
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/mve.decode
32
+++ b/target/arm/mve.decode
33
@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
34
VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
35
36
# Vector add across vector
37
-VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
38
+{
39
+ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
40
+ VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \
41
+ rdahi=%rdahi rdalo=%rdalo
42
+}
43
44
# Predicate operations
45
%mask_22_13 22:1 13:3
46
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/mve_helper.c
49
+++ b/target/arm/mve_helper.c
50
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)
51
DO_VADDV(vaddvuh, 2, uint16_t)
52
DO_VADDV(vaddvuw, 4, uint32_t)
53
54
+#define DO_VADDLV(OP, TYPE, LTYPE) \
55
+ uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
56
+ uint64_t ra) \
57
+ { \
58
+ uint16_t mask = mve_element_mask(env); \
59
+ unsigned e; \
60
+ TYPE *m = vm; \
61
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
62
+ if (mask & 1) { \
63
+ ra += (LTYPE)m[H4(e)]; \
64
+ } \
65
+ } \
66
+ mve_advance_vpt(env); \
67
+ return ra; \
68
+ } \
69
+
70
+DO_VADDLV(vaddlv_s, int32_t, int64_t)
71
+DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
72
+
73
/* Shifts by immediate */
74
#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
75
void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
76
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/translate-mve.c
79
+++ b/target/arm/translate-mve.c
80
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
81
return true;
29
}
82
}
30
83
31
-/* Big-endian hosts need to frob the byte indicies. If the copy
84
+static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
32
+/* Big-endian hosts need to frob the byte indices. If the copy
85
+{
33
* happens to be 8-byte aligned, then no frobbing necessary.
86
+ /*
34
*/
87
+ * Vector Add Long Across Vector: accumulate the 32-bit
35
static void swap_memmove(void *vd, void *vs, size_t n)
88
+ * elements of the vector into a 64-bit result stored in
36
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
89
+ * a pair of general-purpose registers.
37
/*
90
+ * No need to check Qm's bank: it is only 3 bits in decode.
38
* Load elements into @vd, controlled by @vg, from @host + @mem_ofs.
91
+ */
39
* Memory is valid through @host + @mem_max. The register element
92
+ TCGv_ptr qm;
40
- * indicies are inferred from @mem_ofs, as modified by the types for
93
+ TCGv_i64 rda;
41
+ * indices are inferred from @mem_ofs, as modified by the types for
94
+ TCGv_i32 rdalo, rdahi;
42
* which the helper is built. Return the @mem_ofs of the first element
43
* not loaded (which is @mem_max if they are all loaded).
44
*
45
@@ -XXX,XX +XXX,XX @@ static intptr_t max_for_page(target_ulong base, intptr_t mem_off,
46
return MIN(split, mem_max - mem_off) + mem_off;
47
}
48
49
+/*
50
+ * Resolve the guest virtual address to info->host and info->flags.
51
+ * If @nofault, return false if the page is invalid, otherwise
52
+ * exit via page fault exception.
53
+ */
54
+
95
+
55
+typedef struct {
96
+ if (!dc_isar_feature(aa32_mve, s)) {
56
+ void *host;
57
+ int flags;
58
+ MemTxAttrs attrs;
59
+} SVEHostPage;
60
+
61
+static bool sve_probe_page(SVEHostPage *info, bool nofault,
62
+ CPUARMState *env, target_ulong addr,
63
+ int mem_off, MMUAccessType access_type,
64
+ int mmu_idx, uintptr_t retaddr)
65
+{
66
+ int flags;
67
+
68
+ addr += mem_off;
69
+ flags = probe_access_flags(env, addr, access_type, mmu_idx, nofault,
70
+ &info->host, retaddr);
71
+ info->flags = flags;
72
+
73
+ if (flags & TLB_INVALID_MASK) {
74
+ g_assert(nofault);
75
+ return false;
97
+ return false;
76
+ }
98
+ }
77
+
78
+ /* Ensure that info->host[] is relative to addr, not addr + mem_off. */
79
+ info->host -= mem_off;
80
+
81
+#ifdef CONFIG_USER_ONLY
82
+ memset(&info->attrs, 0, sizeof(info->attrs));
83
+#else
84
+ /*
99
+ /*
85
+ * Find the iotlbentry for addr and return the transaction attributes.
100
+ * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
86
+ * This *must* be present in the TLB because we just found the mapping.
101
+ * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
87
+ */
102
+ */
88
+ {
103
+ if (a->rdahi == 13 || a->rdahi == 15) {
89
+ uintptr_t index = tlb_index(env, mmu_idx, addr);
90
+
91
+# ifdef CONFIG_DEBUG_TCG
92
+ CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
93
+ target_ulong comparator = (access_type == MMU_DATA_LOAD
94
+ ? entry->addr_read
95
+ : tlb_addr_write(entry));
96
+ g_assert(tlb_hit(comparator, addr));
97
+# endif
98
+
99
+ CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
100
+ info->attrs = iotlbentry->attrs;
101
+ }
102
+#endif
103
+
104
+ return true;
105
+}
106
+
107
+
108
+/*
109
+ * Analyse contiguous data, protected by a governing predicate.
110
+ */
111
+
112
+typedef enum {
113
+ FAULT_NO,
114
+ FAULT_FIRST,
115
+ FAULT_ALL,
116
+} SVEContFault;
117
+
118
+typedef struct {
119
+ /*
120
+ * First and last element wholly contained within the two pages.
121
+ * mem_off_first[0] and reg_off_first[0] are always set >= 0.
122
+ * reg_off_last[0] may be < 0 if the first element crosses pages.
123
+ * All of mem_off_first[1], reg_off_first[1] and reg_off_last[1]
124
+ * are set >= 0 only if there are complete elements on a second page.
125
+ *
126
+ * The reg_off_* offsets are relative to the internal vector register.
127
+ * The mem_off_first offset is relative to the memory address; the
128
+ * two offsets are different when a load operation extends, a store
129
+ * operation truncates, or for multi-register operations.
130
+ */
131
+ int16_t mem_off_first[2];
132
+ int16_t reg_off_first[2];
133
+ int16_t reg_off_last[2];
134
+
135
+ /*
136
+ * One element that is misaligned and spans both pages,
137
+ * or -1 if there is no such active element.
138
+ */
139
+ int16_t mem_off_split;
140
+ int16_t reg_off_split;
141
+
142
+ /*
143
+ * The byte offset at which the entire operation crosses a page boundary.
144
+ * Set >= 0 if and only if the entire operation spans two pages.
145
+ */
146
+ int16_t page_split;
147
+
148
+ /* TLB data for the two pages. */
149
+ SVEHostPage page[2];
150
+} SVEContLdSt;
151
+
152
+/*
153
+ * Find first active element on each page, and a loose bound for the
154
+ * final element on each page. Identify any single element that spans
155
+ * the page boundary. Return true if there are any active elements.
156
+ */
157
+static bool __attribute__((unused))
158
+sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg,
159
+ intptr_t reg_max, int esz, int msize)
160
+{
161
+ const int esize = 1 << esz;
162
+ const uint64_t pg_mask = pred_esz_masks[esz];
163
+ intptr_t reg_off_first = -1, reg_off_last = -1, reg_off_split;
164
+ intptr_t mem_off_last, mem_off_split;
165
+ intptr_t page_split, elt_split;
166
+ intptr_t i;
167
+
168
+ /* Set all of the element indices to -1, and the TLB data to 0. */
169
+ memset(info, -1, offsetof(SVEContLdSt, page));
170
+ memset(info->page, 0, sizeof(info->page));
171
+
172
+ /* Gross scan over the entire predicate to find bounds. */
173
+ i = 0;
174
+ do {
175
+ uint64_t pg = vg[i] & pg_mask;
176
+ if (pg) {
177
+ reg_off_last = i * 64 + 63 - clz64(pg);
178
+ if (reg_off_first < 0) {
179
+ reg_off_first = i * 64 + ctz64(pg);
180
+ }
181
+ }
182
+ } while (++i * 64 < reg_max);
183
+
184
+ if (unlikely(reg_off_first < 0)) {
185
+ /* No active elements, no pages touched. */
186
+ return false;
104
+ return false;
187
+ }
105
+ }
188
+ tcg_debug_assert(reg_off_last >= 0 && reg_off_last < reg_max);
106
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
189
+
190
+ info->reg_off_first[0] = reg_off_first;
191
+ info->mem_off_first[0] = (reg_off_first >> esz) * msize;
192
+ mem_off_last = (reg_off_last >> esz) * msize;
193
+
194
+ page_split = -(addr | TARGET_PAGE_MASK);
195
+ if (likely(mem_off_last + msize <= page_split)) {
196
+ /* The entire operation fits within a single page. */
197
+ info->reg_off_last[0] = reg_off_last;
198
+ return true;
199
+ }
200
+
201
+ info->page_split = page_split;
202
+ elt_split = page_split / msize;
203
+ reg_off_split = elt_split << esz;
204
+ mem_off_split = elt_split * msize;
205
+
206
+ /*
207
+ * This is the last full element on the first page, but it is not
208
+ * necessarily active. If there is no full element, i.e. the first
209
+ * active element is the one that's split, this value remains -1.
210
+ * It is useful as iteration bounds.
211
+ */
212
+ if (elt_split != 0) {
213
+ info->reg_off_last[0] = reg_off_split - esize;
214
+ }
215
+
216
+ /* Determine if an unaligned element spans the pages. */
217
+ if (page_split % msize != 0) {
218
+ /* It is helpful to know if the split element is active. */
219
+ if ((vg[reg_off_split >> 6] >> (reg_off_split & 63)) & 1) {
220
+ info->reg_off_split = reg_off_split;
221
+ info->mem_off_split = mem_off_split;
222
+
223
+ if (reg_off_split == reg_off_last) {
224
+ /* The page crossing element is last. */
225
+ return true;
226
+ }
227
+ }
228
+ reg_off_split += esize;
229
+ mem_off_split += msize;
230
+ }
231
+
232
+ /*
233
+ * We do want the first active element on the second page, because
234
+ * this may affect the address reported in an exception.
235
+ */
236
+ reg_off_split = find_next_active(vg, reg_off_split, reg_max, esz);
237
+ tcg_debug_assert(reg_off_split <= reg_off_last);
238
+ info->reg_off_first[1] = reg_off_split;
239
+ info->mem_off_first[1] = (reg_off_split >> esz) * msize;
240
+ info->reg_off_last[1] = reg_off_last;
241
+ return true;
242
+}
243
+
244
+/*
245
+ * Resolve the guest virtual addresses to info->page[].
246
+ * Control the generation of page faults with @fault. Return false if
247
+ * there is no work to do, which can only happen with @fault == FAULT_NO.
248
+ */
249
+static bool __attribute__((unused))
250
+sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, CPUARMState *env,
251
+ target_ulong addr, MMUAccessType access_type,
252
+ uintptr_t retaddr)
253
+{
254
+ int mmu_idx = cpu_mmu_index(env, false);
255
+ int mem_off = info->mem_off_first[0];
256
+ bool nofault = fault == FAULT_NO;
257
+ bool have_work = true;
258
+
259
+ if (!sve_probe_page(&info->page[0], nofault, env, addr, mem_off,
260
+ access_type, mmu_idx, retaddr)) {
261
+ /* No work to be done. */
262
+ return false;
263
+ }
264
+
265
+ if (likely(info->page_split < 0)) {
266
+ /* The entire operation was on the one page. */
267
+ return true;
107
+ return true;
268
+ }
108
+ }
269
+
109
+
270
+ /*
110
+ /*
271
+ * If the second page is invalid, then we want the fault address to be
111
+ * This insn is subject to beat-wise execution. Partial execution
272
+ * the first byte on that page which is accessed.
112
+ * of an A=0 (no-accumulate) insn which does not execute the first
113
+ * beat must start with the current value of RdaHi:RdaLo, not zero.
273
+ */
114
+ */
274
+ if (info->mem_off_split >= 0) {
115
+ if (a->a || mve_skip_first_beat(s)) {
275
+ /*
116
+ /* Accumulate input from RdaHi:RdaLo */
276
+ * There is an element split across the pages. The fault address
117
+ rda = tcg_temp_new_i64();
277
+ * should be the first byte of the second page.
118
+ rdalo = load_reg(s, a->rdalo);
278
+ */
119
+ rdahi = load_reg(s, a->rdahi);
279
+ mem_off = info->page_split;
120
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
280
+ /*
121
+ tcg_temp_free_i32(rdalo);
281
+ * If the split element is also the first active element
122
+ tcg_temp_free_i32(rdahi);
282
+ * of the vector, then: For first-fault we should continue
283
+ * to generate faults for the second page. For no-fault,
284
+ * we have work only if the second page is valid.
285
+ */
286
+ if (info->mem_off_first[0] < info->mem_off_split) {
287
+ nofault = FAULT_FIRST;
288
+ have_work = false;
289
+ }
290
+ } else {
123
+ } else {
291
+ /*
124
+ /* Accumulate starting at zero */
292
+ * There is no element split across the pages. The fault address
125
+ rda = tcg_const_i64(0);
293
+ * should be the first active element on the second page.
294
+ */
295
+ mem_off = info->mem_off_first[1];
296
+ /*
297
+ * There must have been one active element on the first page,
298
+ * so we're out of first-fault territory.
299
+ */
300
+ nofault = fault != FAULT_ALL;
301
+ }
126
+ }
302
+
127
+
303
+ have_work |= sve_probe_page(&info->page[1], nofault, env, addr, mem_off,
128
+ qm = mve_qreg_ptr(a->qm);
304
+ access_type, mmu_idx, retaddr);
129
+ if (a->u) {
305
+ return have_work;
130
+ gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
131
+ } else {
132
+ gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
133
+ }
134
+ tcg_temp_free_ptr(qm);
135
+
136
+ rdalo = tcg_temp_new_i32();
137
+ rdahi = tcg_temp_new_i32();
138
+ tcg_gen_extrl_i64_i32(rdalo, rda);
139
+ tcg_gen_extrh_i64_i32(rdahi, rda);
140
+ store_reg(s, a->rdalo, rdalo);
141
+ store_reg(s, a->rdahi, rdahi);
142
+ tcg_temp_free_i64(rda);
143
+ mve_update_eci(s);
144
+ return true;
306
+}
145
+}
307
+
146
+
308
/*
147
static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
309
* The result of tlb_vaddr_to_host for user-only is just g2h(x),
148
{
310
* which is always non-null. Elide the useless test.
149
TCGv_ptr qd;
311
--
150
--
312
2.20.1
151
2.20.1
313
152
314
153
diff view generated by jsdifflib
[PULL 26/34] target/arm: Remove sve_memopidx
[PULL 21/24] target/arm: Implement MVE long shifts by immediate
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The MVE extension to v8.1M includes some new shift instructions which
2
2
sit entirely within the non-coprocessor part of the encoding space
3
None of the sve helpers use TCGMemOpIdx any longer, so we can
3
and which operate only on general-purpose registers. They take up
4
stop passing it.
4
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
5
5
with Rm == 13 or 15.
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Implement the long shifts by immediate, which perform shifts on a
8
Message-id: 20200508154359.7494-20-richard.henderson@linaro.org
8
pair of general-purpose registers treated as a 64-bit quantity, with
9
an immediate shift count between 1 and 32.
10
11
Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
12
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
13
cases where v8.1M now requires that. (Trying to change MOVS and ORRS
14
is too difficult, because the functions that generate the code are
15
shared between a dozen different kinds of arithmetic or logical
16
instruction for all A32, T16 and T32 encodings, and for some insns
17
and some encodings Rm==13,15 are valid.)
18
19
We make the helper functions we need for UQSHLL and SQSHLL take
20
a 32-bit value which the helper casts to int8_t because we'll need
21
these helpers also for the shift-by-register insns, where the shift
22
count might be < 0 or > 32.
23
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
10
---
27
---
11
target/arm/internals.h | 5 -----
28
target/arm/helper-mve.h | 3 ++
12
target/arm/sve_helper.c | 14 +++++++-------
29
target/arm/translate.h | 1 +
13
target/arm/translate-sve.c | 17 +++--------------
30
target/arm/t32.decode | 28 +++++++++++++
14
3 files changed, 10 insertions(+), 26 deletions(-)
31
target/arm/mve_helper.c | 10 +++++
15
32
target/arm/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
33
5 files changed, 132 insertions(+)
17
index XXXXXXX..XXXXXXX 100644
34
18
--- a/target/arm/internals.h
35
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
19
+++ b/target/arm/internals.h
36
index XXXXXXX..XXXXXXX 100644
20
@@ -XXX,XX +XXX,XX @@ static inline int arm_num_ctx_cmps(ARMCPU *cpu)
37
--- a/target/arm/helper-mve.h
21
}
38
+++ b/target/arm/helper-mve.h
22
}
39
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
40
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
-/* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3.
41
25
- * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits.
42
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
26
- */
43
+
27
-#define MEMOPIDX_SHIFT 8
44
+DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
28
-
45
+DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
46
diff --git a/target/arm/translate.h b/target/arm/translate.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/translate.h
49
+++ b/target/arm/translate.h
50
@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
51
typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
52
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
53
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
54
+typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
55
29
/**
56
/**
30
* v7m_using_psp: Return true if using process stack pointer
57
* arm_tbflags_from_tb:
31
* Return true if the CPU is currently using the process stack
58
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
32
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
59
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/t32.decode
34
--- a/target/arm/sve_helper.c
61
+++ b/target/arm/t32.decode
35
+++ b/target/arm/sve_helper.c
62
@@ -XXX,XX +XXX,XX @@
36
@@ -XXX,XX +XXX,XX @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
63
&mcr !extern cp opc1 crn crm opc2 rt
37
sve_ldst1_host_fn *host_fn,
64
&mcrr !extern cp opc1 crm rt rt2
38
sve_ldst1_tlb_fn *tlb_fn)
65
66
+&mve_shl_ri rdalo rdahi shim
67
+
68
+# rdahi: bits [3:1] from insn, bit 0 is 1
69
+# rdalo: bits [3:1] from insn, bit 0 is 0
70
+%rdahi_9 9:3 !function=times_2_plus_1
71
+%rdalo_17 17:3 !function=times_2
72
+
73
# Data-processing (register)
74
75
%imm5_12_6 12:3 6:2
76
@@ -XXX,XX +XXX,XX @@
77
@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
78
&s_rrr_shi shim=%imm5_12_6 s=1 rd=0
79
80
+@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
81
+ &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
82
+
39
{
83
{
40
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
84
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
41
+ const unsigned rd = simd_data(desc);
85
AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi
42
const intptr_t reg_max = simd_oprsz(desc);
86
}
43
intptr_t reg_off, reg_last, mem_off;
87
BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
44
SVEContLdSt info;
45
@@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
46
sve_ldst1_host_fn *host_fn,
47
sve_ldst1_tlb_fn *tlb_fn)
48
{
88
{
49
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
89
+ # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
50
+ const unsigned rd = simd_data(desc);
90
+ # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
51
void *vd = &env->vfp.zregs[rd];
91
+ # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that
52
const intptr_t reg_max = simd_oprsz(desc);
92
+ # they explicitly call unallocated_encoding() for cases that must UNDEF
53
intptr_t reg_off, mem_off, reg_last;
93
+ # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
54
@@ -XXX,XX +XXX,XX @@ void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, uint32_t desc,
94
+ # the rest fall through (where ORR_rrri and MOV_rxri will end up
55
sve_ldst1_host_fn *host_fn,
95
+ # handling them as r13 and r15 accesses with the same semantics as A32).
56
sve_ldst1_tlb_fn *tlb_fn)
96
+ [
57
{
97
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
58
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
98
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
59
+ const unsigned rd = simd_data(desc);
99
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
60
const intptr_t reg_max = simd_oprsz(desc);
100
+
61
intptr_t reg_off, reg_last, mem_off;
101
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
62
SVEContLdSt info;
102
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
63
@@ -XXX,XX +XXX,XX @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
103
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
64
sve_ldst1_host_fn *host_fn,
104
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
65
sve_ldst1_tlb_fn *tlb_fn)
105
+ ]
66
{
106
+
67
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
107
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
68
const int mmu_idx = cpu_mmu_index(env, false);
108
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
69
const intptr_t reg_max = simd_oprsz(desc);
109
}
70
+ const int scale = simd_data(desc);
110
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
71
ARMVectorReg scratch;
111
index XXXXXXX..XXXXXXX 100644
72
intptr_t reg_off;
112
--- a/target/arm/mve_helper.c
73
SVEHostPage info, info2;
113
+++ b/target/arm/mve_helper.c
74
@@ -XXX,XX +XXX,XX @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
114
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
75
sve_ldst1_tlb_fn *tlb_fn)
115
mve_advance_vpt(env);
76
{
116
return rdm;
77
const int mmu_idx = cpu_mmu_index(env, false);
117
}
78
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
118
+
79
+ const intptr_t reg_max = simd_oprsz(desc);
119
+uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
80
+ const int scale = simd_data(desc);
120
+{
81
const int esize = 1 << esz;
121
+ return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
82
const int msize = 1 << msz;
122
+}
83
- const intptr_t reg_max = simd_oprsz(desc);
123
+
84
intptr_t reg_off;
124
+uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
85
SVEHostPage info;
125
+{
86
target_ulong addr, in_page;
126
+ return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
87
@@ -XXX,XX +XXX,XX @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
127
+}
88
sve_ldst1_host_fn *host_fn,
128
diff --git a/target/arm/translate.c b/target/arm/translate.c
89
sve_ldst1_tlb_fn *tlb_fn)
129
index XXXXXXX..XXXXXXX 100644
90
{
130
--- a/target/arm/translate.c
91
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
131
+++ b/target/arm/translate.c
92
const int mmu_idx = cpu_mmu_index(env, false);
132
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
93
const intptr_t reg_max = simd_oprsz(desc);
133
return true;
94
+ const int scale = simd_data(desc);
134
}
95
void *host[ARM_MAX_VQ * 4];
135
96
intptr_t reg_off, i;
136
+/*
97
SVEHostPage info, info2;
137
+ * v8.1M MVE wide-shifts
98
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
138
+ */
99
index XXXXXXX..XXXXXXX 100644
139
+static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,
100
--- a/target/arm/translate-sve.c
140
+ WideShiftImmFn *fn)
101
+++ b/target/arm/translate-sve.c
141
+{
102
@@ -XXX,XX +XXX,XX @@ static const uint8_t dtype_esz[16] = {
142
+ TCGv_i64 rda;
103
3, 2, 1, 3
143
+ TCGv_i32 rdalo, rdahi;
104
};
144
+
105
145
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
106
-static TCGMemOpIdx sve_memopidx(DisasContext *s, int dtype)
146
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
107
-{
147
+ return false;
108
- return make_memop_idx(s->be_data | dtype_mop[dtype], get_mem_index(s));
148
+ }
109
-}
149
+ if (a->rdahi == 15) {
110
-
150
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
111
static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
151
+ return false;
112
int dtype, gen_helper_gvec_mem *fn)
152
+ }
113
{
153
+ if (!dc_isar_feature(aa32_mve, s) ||
114
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
154
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
115
* registers as pointers, so encode the regno into the data field.
155
+ a->rdahi == 13) {
116
* For consistency, do this even for LD1.
156
+ /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */
117
*/
157
+ unallocated_encoding(s);
118
- desc = sve_memopidx(s, dtype);
158
+ return true;
119
- desc |= zt << MEMOPIDX_SHIFT;
159
+ }
120
- desc = simd_desc(vsz, vsz, desc);
160
+
121
+ desc = simd_desc(vsz, vsz, zt);
161
+ if (a->shim == 0) {
122
t_desc = tcg_const_i32(desc);
162
+ a->shim = 32;
123
t_pg = tcg_temp_new_ptr();
163
+ }
124
164
+
125
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int msz)
165
+ rda = tcg_temp_new_i64();
126
int desc, poff;
166
+ rdalo = load_reg(s, a->rdalo);
127
167
+ rdahi = load_reg(s, a->rdahi);
128
/* Load the first quadword using the normal predicated load helpers. */
168
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
129
- desc = sve_memopidx(s, msz_dtype(s, msz));
169
+
130
- desc |= zt << MEMOPIDX_SHIFT;
170
+ fn(rda, rda, a->shim);
131
- desc = simd_desc(16, 16, desc);
171
+
132
+ desc = simd_desc(16, 16, zt);
172
+ tcg_gen_extrl_i64_i32(rdalo, rda);
133
t_desc = tcg_const_i32(desc);
173
+ tcg_gen_extrh_i64_i32(rdahi, rda);
134
174
+ store_reg(s, a->rdalo, rdalo);
135
poff = pred_full_reg_offset(s, pg);
175
+ store_reg(s, a->rdahi, rdahi);
136
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
176
+ tcg_temp_free_i64(rda);
137
TCGv_i32 t_desc;
177
+
138
int desc;
178
+ return true;
139
179
+}
140
- desc = sve_memopidx(s, msz_dtype(s, msz));
180
+
141
- desc |= scale << MEMOPIDX_SHIFT;
181
+static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)
142
- desc = simd_desc(vsz, vsz, desc);
182
+{
143
+ desc = simd_desc(vsz, vsz, scale);
183
+ return do_mve_shl_ri(s, a, tcg_gen_sari_i64);
144
t_desc = tcg_const_i32(desc);
184
+}
145
185
+
146
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
186
+static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)
187
+{
188
+ return do_mve_shl_ri(s, a, tcg_gen_shli_i64);
189
+}
190
+
191
+static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
192
+{
193
+ return do_mve_shl_ri(s, a, tcg_gen_shri_i64);
194
+}
195
+
196
+static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
197
+{
198
+ gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
199
+}
200
+
201
+static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
202
+{
203
+ return do_mve_shl_ri(s, a, gen_mve_sqshll);
204
+}
205
+
206
+static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
207
+{
208
+ gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
209
+}
210
+
211
+static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
212
+{
213
+ return do_mve_shl_ri(s, a, gen_mve_uqshll);
214
+}
215
+
216
+static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
217
+{
218
+ return do_mve_shl_ri(s, a, gen_srshr64_i64);
219
+}
220
+
221
+static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
222
+{
223
+ return do_mve_shl_ri(s, a, gen_urshr64_i64);
224
+}
225
+
226
/*
227
* Multiply and multiply accumulate
228
*/
147
--
229
--
148
2.20.1
230
2.20.1
149
231
150
232
diff view generated by jsdifflib
[PULL 19/34] target/arm: Handle watchpoints in sve_ld1_r
[PULL 22/24] target/arm: Implement MVE long shifts by register
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the MVE long shifts by register, which perform shifts on a
2
2
pair of general-purpose registers treated as a 64-bit quantity, with
3
Handle all of the watchpoints for active elements all at once,
3
the shift count in another general-purpose register, which might be
4
before we've modified the vector register. This removes the
4
either positive or negative.
5
TLB_WATCHPOINT bit from page[].flags, which means that we can
5
6
use the normal fast path via RAM.
6
Like the long-shifts-by-immediate, these encodings sit in the space
7
7
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
10
Message-id: 20200508154359.7494-13-richard.henderson@linaro.org
10
we have to move the CSEL pattern into the same decodetree group.
11
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
12
---
15
---
13
target/arm/sve_helper.c | 72 ++++++++++++++++++++++++++++++++++++++++-
16
target/arm/helper-mve.h | 6 +++
14
1 file changed, 71 insertions(+), 1 deletion(-)
17
target/arm/translate.h | 1 +
15
18
target/arm/t32.decode | 16 +++++--
16
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
19
target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
17
index XXXXXXX..XXXXXXX 100644
20
target/arm/translate.c | 69 ++++++++++++++++++++++++++++++
18
--- a/target/arm/sve_helper.c
21
5 files changed, 182 insertions(+), 3 deletions(-)
19
+++ b/target/arm/sve_helper.c
22
20
@@ -XXX,XX +XXX,XX @@ static bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault,
23
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
21
return have_work;
24
index XXXXXXX..XXXXXXX 100644
22
}
25
--- a/target/arm/helper-mve.h
23
26
+++ b/target/arm/helper-mve.h
24
+static void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env,
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
+ uint64_t *vg, target_ulong addr,
28
26
+ int esize, int msize, int wp_access,
29
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
27
+ uintptr_t retaddr)
30
28
+{
31
+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
29
+#ifndef CONFIG_USER_ONLY
32
+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
30
+ intptr_t mem_off, reg_off, reg_last;
33
DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
31
+ int flags0 = info->page[0].flags;
34
DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
32
+ int flags1 = info->page[1].flags;
35
+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
33
+
36
+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
34
+ if (likely(!((flags0 | flags1) & TLB_WATCHPOINT))) {
37
+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
35
+ return;
38
+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
36
+ }
39
diff --git a/target/arm/translate.h b/target/arm/translate.h
37
+
40
index XXXXXXX..XXXXXXX 100644
38
+ /* Indicate that watchpoints are handled. */
41
--- a/target/arm/translate.h
39
+ info->page[0].flags = flags0 & ~TLB_WATCHPOINT;
42
+++ b/target/arm/translate.h
40
+ info->page[1].flags = flags1 & ~TLB_WATCHPOINT;
43
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
41
+
44
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
42
+ if (flags0 & TLB_WATCHPOINT) {
45
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
43
+ mem_off = info->mem_off_first[0];
46
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
44
+ reg_off = info->reg_off_first[0];
47
+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
45
+ reg_last = info->reg_off_last[0];
48
46
+
49
/**
47
+ while (reg_off <= reg_last) {
50
* arm_tbflags_from_tb:
48
+ uint64_t pg = vg[reg_off >> 6];
51
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
49
+ do {
52
index XXXXXXX..XXXXXXX 100644
50
+ if ((pg >> (reg_off & 63)) & 1) {
53
--- a/target/arm/t32.decode
51
+ cpu_check_watchpoint(env_cpu(env), addr + mem_off,
54
+++ b/target/arm/t32.decode
52
+ msize, info->page[0].attrs,
55
@@ -XXX,XX +XXX,XX @@
53
+ wp_access, retaddr);
56
&mcrr !extern cp opc1 crm rt rt2
54
+ }
57
55
+ reg_off += esize;
58
&mve_shl_ri rdalo rdahi shim
56
+ mem_off += msize;
59
+&mve_shl_rr rdalo rdahi rm
57
+ } while (reg_off <= reg_last && (reg_off & 63));
60
58
+ }
61
# rdahi: bits [3:1] from insn, bit 0 is 1
59
+ }
62
# rdalo: bits [3:1] from insn, bit 0 is 0
60
+
63
@@ -XXX,XX +XXX,XX @@
61
+ mem_off = info->mem_off_split;
64
62
+ if (mem_off >= 0) {
65
@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
63
+ cpu_check_watchpoint(env_cpu(env), addr + mem_off, msize,
66
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
64
+ info->page[0].attrs, wp_access, retaddr);
67
+@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
65
+ }
68
+ &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
66
+
69
67
+ mem_off = info->mem_off_first[1];
70
{
68
+ if ((flags1 & TLB_WATCHPOINT) && mem_off >= 0) {
71
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
69
+ reg_off = info->reg_off_first[1];
72
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
70
+ reg_last = info->reg_off_last[1];
73
URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
71
+
74
SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
72
+ do {
75
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
73
+ uint64_t pg = vg[reg_off >> 6];
76
+
74
+ do {
77
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
75
+ if ((pg >> (reg_off & 63)) & 1) {
78
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
76
+ cpu_check_watchpoint(env_cpu(env), addr + mem_off,
79
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
77
+ msize, info->page[1].attrs,
80
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
78
+ wp_access, retaddr);
81
+ UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
79
+ }
82
+ SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
80
+ reg_off += esize;
83
]
81
+ mem_off += msize;
84
82
+ } while (reg_off & 63);
85
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
83
+ } while (reg_off <= reg_last);
86
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
84
+ }
87
+
85
+#endif
88
+ # v8.1M CSEL and friends
89
+ CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
90
}
91
{
92
MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi
93
@@ -XXX,XX +XXX,XX @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi
94
}
95
RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi
96
97
-# v8.1M CSEL and friends
98
-CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
99
-
100
# Data-processing (register-shifted register)
101
102
MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
103
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/target/arm/mve_helper.c
106
+++ b/target/arm/mve_helper.c
107
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
108
return rdm;
109
}
110
111
+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
112
+{
113
+ return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
114
+}
115
+
116
+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
117
+{
118
+ return do_uqrshl_d(n, (int8_t)shift, false, NULL);
119
+}
120
+
121
uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
122
{
123
return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
124
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
{
126
return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
}
128
+
129
+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
130
+{
131
+ return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
132
+}
133
+
134
+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
135
+{
136
+ return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
137
+}
138
+
139
+/* Operate on 64-bit values, but saturate at 48 bits */
140
+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
141
+ bool round, uint32_t *sat)
142
+{
143
+ if (shift <= -48) {
144
+ /* Rounding the sign bit always produces 0. */
145
+ if (round) {
146
+ return 0;
147
+ }
148
+ return src >> 63;
149
+ } else if (shift < 0) {
150
+ if (round) {
151
+ src >>= -shift - 1;
152
+ return (src >> 1) + (src & 1);
153
+ }
154
+ return src >> -shift;
155
+ } else if (shift < 48) {
156
+ int64_t val = src << shift;
157
+ int64_t extval = sextract64(val, 0, 48);
158
+ if (!sat || val == extval) {
159
+ return extval;
160
+ }
161
+ } else if (!sat || src == 0) {
162
+ return 0;
163
+ }
164
+
165
+ *sat = 1;
166
+ return (1ULL << 47) - (src >= 0);
167
+}
168
+
169
+/* Operate on 64-bit values, but saturate at 48 bits */
170
+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
171
+ bool round, uint32_t *sat)
172
+{
173
+ uint64_t val, extval;
174
+
175
+ if (shift <= -(48 + round)) {
176
+ return 0;
177
+ } else if (shift < 0) {
178
+ if (round) {
179
+ val = src >> (-shift - 1);
180
+ val = (val >> 1) + (val & 1);
181
+ } else {
182
+ val = src >> -shift;
183
+ }
184
+ extval = extract64(val, 0, 48);
185
+ if (!sat || val == extval) {
186
+ return extval;
187
+ }
188
+ } else if (shift < 48) {
189
+ uint64_t val = src << shift;
190
+ uint64_t extval = extract64(val, 0, 48);
191
+ if (!sat || val == extval) {
192
+ return extval;
193
+ }
194
+ } else if (!sat || src == 0) {
195
+ return 0;
196
+ }
197
+
198
+ *sat = 1;
199
+ return MAKE_64BIT_MASK(0, 48);
200
+}
201
+
202
+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
203
+{
204
+ return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
205
+}
206
+
207
+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
208
+{
209
+ return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
210
+}
211
diff --git a/target/arm/translate.c b/target/arm/translate.c
212
index XXXXXXX..XXXXXXX 100644
213
--- a/target/arm/translate.c
214
+++ b/target/arm/translate.c
215
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
216
return do_mve_shl_ri(s, a, gen_urshr64_i64);
217
}
218
219
+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
220
+{
221
+ TCGv_i64 rda;
222
+ TCGv_i32 rdalo, rdahi;
223
+
224
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
225
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
226
+ return false;
227
+ }
228
+ if (a->rdahi == 15) {
229
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
230
+ return false;
231
+ }
232
+ if (!dc_isar_feature(aa32_mve, s) ||
233
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
234
+ a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
235
+ a->rm == a->rdahi || a->rm == a->rdalo) {
236
+ /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
237
+ unallocated_encoding(s);
238
+ return true;
239
+ }
240
+
241
+ rda = tcg_temp_new_i64();
242
+ rdalo = load_reg(s, a->rdalo);
243
+ rdahi = load_reg(s, a->rdahi);
244
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
245
+
246
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
247
+ fn(rda, cpu_env, rda, cpu_R[a->rm]);
248
+
249
+ tcg_gen_extrl_i64_i32(rdalo, rda);
250
+ tcg_gen_extrh_i64_i32(rdahi, rda);
251
+ store_reg(s, a->rdalo, rdalo);
252
+ store_reg(s, a->rdahi, rdahi);
253
+ tcg_temp_free_i64(rda);
254
+
255
+ return true;
256
+}
257
+
258
+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
259
+{
260
+ return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
261
+}
262
+
263
+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
264
+{
265
+ return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
266
+}
267
+
268
+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
269
+{
270
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
271
+}
272
+
273
+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
274
+{
275
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
276
+}
277
+
278
+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
279
+{
280
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
281
+}
282
+
283
+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
284
+{
285
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
86
+}
286
+}
87
+
287
+
88
/*
288
/*
89
* The result of tlb_vaddr_to_host for user-only is just g2h(x),
289
* Multiply and multiply accumulate
90
* which is always non-null. Elide the useless test.
290
*/
91
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
92
/* Probe the page(s). Exit with exception for any invalid page. */
93
sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, retaddr);
94
95
+ /* Handle watchpoints for all active elements. */
96
+ sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, 1 << msz,
97
+ BP_MEM_READ, retaddr);
98
+
99
+ /* TODO: MTE check. */
100
+
101
flags = info.page[0].flags | info.page[1].flags;
102
if (unlikely(flags != 0)) {
103
#ifdef CONFIG_USER_ONLY
104
g_assert_not_reached();
105
#else
106
/*
107
- * At least one page includes MMIO (or watchpoints).
108
+ * At least one page includes MMIO.
109
* Any bus operation can fail with cpu_transaction_failed,
110
* which for ARM will raise SyncExternal. Perform the load
111
* into scratch memory to preserve register state until the end.
112
--
291
--
113
2.20.1
292
2.20.1
114
293
115
294
diff view generated by jsdifflib
[PULL 06/34] hw/timer/nrf51_timer: Display timer ID in trace events
[PULL 23/24] target/arm: Implement MVE shifts by immediate
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Implement the MVE shifts by immediate, which perform shifts
2
2
on a single general-purpose register.
3
The NRF51 series SoC have 3 timer peripherals, each having
3
4
4 counters. To help differentiate which peripheral is accessed,
4
These patterns overlap with the long-shift-by-immediates,
5
display the timer ID in the trace events.
5
so we have to rearrange the grouping a little here.
6
6
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200504072822.18799-4-f4bug@amsat.org
9
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
include/hw/timer/nrf51_timer.h | 1 +
11
target/arm/helper-mve.h | 3 ++
13
hw/arm/nrf51_soc.c | 5 +++++
12
target/arm/translate.h | 1 +
14
hw/timer/nrf51_timer.c | 11 +++++++++--
13
target/arm/t32.decode | 31 ++++++++++++++-----
15
hw/timer/trace-events | 4 ++--
14
target/arm/mve_helper.c | 10 ++++++
16
4 files changed, 17 insertions(+), 4 deletions(-)
15
target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++--
17
16
5 files changed, 104 insertions(+), 9 deletions(-)
18
diff --git a/include/hw/timer/nrf51_timer.h b/include/hw/timer/nrf51_timer.h
17
19
index XXXXXXX..XXXXXXX 100644
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
20
--- a/include/hw/timer/nrf51_timer.h
19
index XXXXXXX..XXXXXXX 100644
21
+++ b/include/hw/timer/nrf51_timer.h
20
--- a/target/arm/helper-mve.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct NRF51TimerState {
21
+++ b/target/arm/helper-mve.h
23
MemoryRegion iomem;
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
24
qemu_irq irq;
23
DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
25
24
DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
26
+ uint8_t id;
25
DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
27
QEMUTimer timer;
26
+
28
int64_t timer_start_ns;
27
+DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
29
int64_t update_counter_ns;
28
+DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
30
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
29
diff --git a/target/arm/translate.h b/target/arm/translate.h
31
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/arm/nrf51_soc.c
31
--- a/target/arm/translate.h
33
+++ b/hw/arm/nrf51_soc.c
32
+++ b/target/arm/translate.h
34
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
33
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
35
34
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
36
/* TIMER */
35
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
37
for (i = 0; i < NRF51_NUM_TIMERS; i++) {
36
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
38
+ object_property_set_uint(OBJECT(&s->timer[i]), i, "id", &err);
37
+typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
39
+ if (err) {
38
40
+ error_propagate(errp, err);
39
/**
41
+ return;
40
* arm_tbflags_from_tb:
42
+ }
41
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
43
object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
42
index XXXXXXX..XXXXXXX 100644
44
if (err) {
43
--- a/target/arm/t32.decode
45
error_propagate(errp, err);
44
+++ b/target/arm/t32.decode
46
diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/timer/nrf51_timer.c
49
+++ b/hw/timer/nrf51_timer.c
50
@@ -XXX,XX +XXX,XX @@
45
@@ -XXX,XX +XXX,XX @@
51
#include "hw/arm/nrf51.h"
46
52
#include "hw/irq.h"
47
&mve_shl_ri rdalo rdahi shim
53
#include "hw/timer/nrf51_timer.h"
48
&mve_shl_rr rdalo rdahi rm
54
+#include "hw/qdev-properties.h"
49
+&mve_sh_ri rda shim
55
#include "migration/vmstate.h"
50
56
#include "trace.h"
51
# rdahi: bits [3:1] from insn, bit 0 is 1
57
52
# rdalo: bits [3:1] from insn, bit 0 is 0
58
@@ -XXX,XX +XXX,XX @@ static uint64_t nrf51_timer_read(void *opaque, hwaddr offset, unsigned int size)
53
@@ -XXX,XX +XXX,XX @@
59
__func__, offset);
54
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
60
}
55
@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
61
56
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
62
- trace_nrf51_timer_read(offset, r, size);
57
+@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
63
+ trace_nrf51_timer_read(s->id, offset, r, size);
58
+ &mve_sh_ri shim=%imm5_12_6
64
59
65
return r;
60
{
61
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
62
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
63
# the rest fall through (where ORR_rrri and MOV_rxri will end up
64
# handling them as r13 and r15 accesses with the same semantics as A32).
65
[
66
- LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
67
- LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
68
- ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
69
+ {
70
+ UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri
71
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
72
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
73
+ }
74
75
- UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
76
- URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
77
- SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
78
- SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
79
+ {
80
+ URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri
81
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
82
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
83
+ }
84
+
85
+ {
86
+ SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri
87
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
88
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
89
+ }
90
+
91
+ {
92
+ SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri
93
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
94
+ }
95
96
LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
97
ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
98
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/mve_helper.c
101
+++ b/target/arm/mve_helper.c
102
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
103
{
104
return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
66
}
105
}
67
@@ -XXX,XX +XXX,XX @@ static void nrf51_timer_write(void *opaque, hwaddr offset,
106
+
68
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
107
+uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
69
size_t idx;
108
+{
70
109
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
71
- trace_nrf51_timer_write(offset, value, size);
110
+}
72
+ trace_nrf51_timer_write(s->id, offset, value, size);
111
+
73
112
+uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
74
switch (offset) {
113
+{
75
case NRF51_TIMER_TASK_START:
114
+ return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
76
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nrf51_timer = {
115
+}
77
}
116
diff --git a/target/arm/translate.c b/target/arm/translate.c
78
};
117
index XXXXXXX..XXXXXXX 100644
79
118
--- a/target/arm/translate.c
80
+static Property nrf51_timer_properties[] = {
119
+++ b/target/arm/translate.c
81
+ DEFINE_PROP_UINT8("id", NRF51TimerState, id, 0),
120
@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
82
+ DEFINE_PROP_END_OF_LIST(),
121
83
+};
122
static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
84
+
123
{
85
static void nrf51_timer_class_init(ObjectClass *klass, void *data)
124
- TCGv_i32 t = tcg_temp_new_i32();
86
{
125
+ TCGv_i32 t;
87
DeviceClass *dc = DEVICE_CLASS(klass);
126
88
127
+ /* Handle shift by the input size for the benefit of trans_SRSHR_ri */
89
dc->reset = nrf51_timer_reset;
128
+ if (sh == 32) {
90
dc->vmsd = &vmstate_nrf51_timer;
129
+ tcg_gen_movi_i32(d, 0);
91
+ device_class_set_props(dc, nrf51_timer_properties);
130
+ return;
131
+ }
132
+ t = tcg_temp_new_i32();
133
tcg_gen_extract_i32(t, a, sh - 1, 1);
134
tcg_gen_sari_i32(d, a, sh);
135
tcg_gen_add_i32(d, d, t);
136
@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
137
138
static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
139
{
140
- TCGv_i32 t = tcg_temp_new_i32();
141
+ TCGv_i32 t;
142
143
+ /* Handle shift by the input size for the benefit of trans_URSHR_ri */
144
+ if (sh == 32) {
145
+ tcg_gen_extract_i32(d, a, sh - 1, 1);
146
+ return;
147
+ }
148
+ t = tcg_temp_new_i32();
149
tcg_gen_extract_i32(t, a, sh - 1, 1);
150
tcg_gen_shri_i32(d, a, sh);
151
tcg_gen_add_i32(d, d, t);
152
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
153
return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
92
}
154
}
93
155
94
static const TypeInfo nrf51_timer_info = {
156
+static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)
95
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
157
+{
96
index XXXXXXX..XXXXXXX 100644
158
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
97
--- a/hw/timer/trace-events
159
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
98
+++ b/hw/timer/trace-events
160
+ return false;
99
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK
161
+ }
100
cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
162
+ if (!dc_isar_feature(aa32_mve, s) ||
101
163
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
102
# nrf51_timer.c
164
+ a->rda == 13 || a->rda == 15) {
103
-nrf51_timer_read(uint64_t addr, uint32_t value, unsigned size) "read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
165
+ /* These rda cases are UNPREDICTABLE; we choose to UNDEF */
104
-nrf51_timer_write(uint64_t addr, uint32_t value, unsigned size) "write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
166
+ unallocated_encoding(s);
105
+nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
167
+ return true;
106
+nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
168
+ }
107
169
+
108
# bcm2835_systmr.c
170
+ if (a->shim == 0) {
109
bcm2835_systmr_irq(bool enable) "timer irq state %u"
171
+ a->shim = 32;
172
+ }
173
+ fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);
174
+
175
+ return true;
176
+}
177
+
178
+static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
179
+{
180
+ return do_mve_sh_ri(s, a, gen_urshr32_i32);
181
+}
182
+
183
+static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
184
+{
185
+ return do_mve_sh_ri(s, a, gen_srshr32_i32);
186
+}
187
+
188
+static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
189
+{
190
+ gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
191
+}
192
+
193
+static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
194
+{
195
+ return do_mve_sh_ri(s, a, gen_mve_sqshl);
196
+}
197
+
198
+static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
199
+{
200
+ gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
201
+}
202
+
203
+static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
204
+{
205
+ return do_mve_sh_ri(s, a, gen_mve_uqshl);
206
+}
207
+
208
/*
209
* Multiply and multiply accumulate
210
*/
110
--
211
--
111
2.20.1
212
2.20.1
112
213
113
214
diff view generated by jsdifflib
[PULL 07/34] hw/timer/nrf51_timer: Add trace event of counter value update
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Add trace event to display timer's counter value updates.
4
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200504072822.18799-5-f4bug@amsat.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/timer/nrf51_timer.c | 1 +
11
hw/timer/trace-events | 1 +
12
2 files changed, 2 insertions(+)
13
14
diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/timer/nrf51_timer.c
17
+++ b/hw/timer/nrf51_timer.c
18
@@ -XXX,XX +XXX,XX @@ static void nrf51_timer_write(void *opaque, hwaddr offset,
19
20
idx = (offset - NRF51_TIMER_TASK_CAPTURE_0) / 4;
21
s->cc[idx] = s->counter;
22
+ trace_nrf51_timer_set_count(s->id, idx, s->counter);
23
}
24
break;
25
case NRF51_TIMER_EVENT_COMPARE_0 ... NRF51_TIMER_EVENT_COMPARE_3:
26
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/timer/trace-events
29
+++ b/hw/timer/trace-events
30
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
31
# nrf51_timer.c
32
nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
33
nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
34
+nrf51_timer_set_count(uint8_t timer_id, uint8_t counter_id, uint32_t value) "timer %u counter %u count 0x%" PRIx32
35
36
# bcm2835_systmr.c
37
bcm2835_systmr_irq(bool enable) "timer irq state %u"
38
--
39
2.20.1
40
41
diff view generated by jsdifflib
[PULL 08/34] exec: Add block comments for watchpoint routines
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200508154359.7494-2-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
include/hw/core/cpu.h | 23 +++++++++++++++++++++++
9
1 file changed, 23 insertions(+)
10
11
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/core/cpu.h
14
+++ b/include/hw/core/cpu.h
15
@@ -XXX,XX +XXX,XX @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
16
vaddr len, int flags);
17
void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
18
void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
19
+
20
+/**
21
+ * cpu_check_watchpoint:
22
+ * @cpu: cpu context
23
+ * @addr: guest virtual address
24
+ * @len: access length
25
+ * @attrs: memory access attributes
26
+ * @flags: watchpoint access type
27
+ * @ra: unwind return address
28
+ *
29
+ * Check for a watchpoint hit in [addr, addr+len) of the type
30
+ * specified by @flags. Exit via exception with a hit.
31
+ */
32
void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
33
MemTxAttrs attrs, int flags, uintptr_t ra);
34
+
35
+/**
36
+ * cpu_watchpoint_address_matches:
37
+ * @cpu: cpu context
38
+ * @addr: guest virtual address
39
+ * @len: access length
40
+ *
41
+ * Return the watchpoint flags that apply to [addr, addr+len).
42
+ * If no watchpoint is registered for the range, the result is 0.
43
+ */
44
int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len);
45
#endif
46
47
--
48
2.20.1
49
50
diff view generated by jsdifflib
[PULL 10/34] accel/tcg: Add block comment for probe_access
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200508154359.7494-4-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
include/exec/exec-all.h | 17 +++++++++++++++++
9
1 file changed, 17 insertions(+)
10
11
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/exec/exec-all.h
14
+++ b/include/exec/exec-all.h
15
@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
16
{
17
}
18
#endif
19
+/**
20
+ * probe_access:
21
+ * @env: CPUArchState
22
+ * @addr: guest virtual address to look up
23
+ * @size: size of the access
24
+ * @access_type: read, write or execute permission
25
+ * @mmu_idx: MMU index to use for lookup
26
+ * @retaddr: return address for unwinding
27
+ *
28
+ * Look up the guest virtual address @addr. Raise an exception if the
29
+ * page does not satisfy @access_type. Raise an exception if the
30
+ * access (@addr, @size) hits a watchpoint. For writes, mark a clean
31
+ * page as dirty.
32
+ *
33
+ * Finally, return the host address for a page that is backed by RAM,
34
+ * or NULL if the page requires I/O.
35
+ */
36
void *probe_access(CPUArchState *env, target_ulong addr, int size,
37
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
38
39
--
40
2.20.1
41
42
diff view generated by jsdifflib
[PULL 12/34] accel/tcg: Add probe_access_flags
[PULL 24/24] target/arm: Implement MVE shifts by register
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the MVE shifts by register, which perform
2
shifts on a single general-purpose register.
2
3
3
This new interface will allow targets to probe for a page
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
and then handle watchpoints themselves. This will be most
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
useful for vector predicated memory operations, where one
6
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
6
page lookup can be used for many operations, and one test
7
---
7
can avoid many watchpoint checks.
8
target/arm/helper-mve.h | 2 ++
9
target/arm/translate.h | 1 +
10
target/arm/t32.decode | 18 ++++++++++++++----
11
target/arm/mve_helper.c | 10 ++++++++++
12
target/arm/translate.c | 30 ++++++++++++++++++++++++++++++
13
5 files changed, 57 insertions(+), 4 deletions(-)
8
14
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
10
Message-id: 20200508154359.7494-6-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
include/exec/cpu-all.h | 13 ++-
15
include/exec/exec-all.h | 22 +++++
16
accel/tcg/cputlb.c | 177 ++++++++++++++++++++--------------------
17
accel/tcg/user-exec.c | 43 ++++++++--
18
4 files changed, 158 insertions(+), 97 deletions(-)
19
20
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
21
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
22
--- a/include/exec/cpu-all.h
17
--- a/target/arm/helper-mve.h
23
+++ b/include/exec/cpu-all.h
18
+++ b/target/arm/helper-mve.h
24
@@ -XXX,XX +XXX,XX @@ CPUArchState *cpu_copy(CPUArchState *env);
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
25
| CPU_INTERRUPT_TGT_EXT_3 \
20
26
| CPU_INTERRUPT_TGT_EXT_4)
21
DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
27
22
DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
28
-#if !defined(CONFIG_USER_ONLY)
23
+DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
29
+#ifdef CONFIG_USER_ONLY
24
+DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
30
+
25
diff --git a/target/arm/translate.h b/target/arm/translate.h
31
+/*
32
+ * Allow some level of source compatibility with softmmu. We do not
33
+ * support any of the more exotic features, so only invalid pages may
34
+ * be signaled by probe_access_flags().
35
+ */
36
+#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
37
+#define TLB_MMIO 0
38
+#define TLB_WATCHPOINT 0
39
+
40
+#else
41
42
/*
43
* Flags stored in the low bits of the TLB virtual address.
44
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
45
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
46
--- a/include/exec/exec-all.h
27
--- a/target/arm/translate.h
47
+++ b/include/exec/exec-all.h
28
+++ b/target/arm/translate.h
48
@@ -XXX,XX +XXX,XX @@ static inline void *probe_read(CPUArchState *env, target_ulong addr, int size,
29
@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
49
return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
30
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
50
}
31
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
51
32
typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
52
+/**
33
+typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
53
+ * probe_access_flags:
34
54
+ * @env: CPUArchState
35
/**
55
+ * @addr: guest virtual address to look up
36
* arm_tbflags_from_tb:
56
+ * @access_type: read, write or execute permission
37
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
57
+ * @mmu_idx: MMU index to use for lookup
58
+ * @nonfault: suppress the fault
59
+ * @phost: return value for host address
60
+ * @retaddr: return address for unwinding
61
+ *
62
+ * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for
63
+ * the page, and storing the host address for RAM in @phost.
64
+ *
65
+ * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK.
66
+ * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags.
67
+ * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags.
68
+ * For simplicity, all "mmio-like" flags are folded to TLB_MMIO.
69
+ */
70
+int probe_access_flags(CPUArchState *env, target_ulong addr,
71
+ MMUAccessType access_type, int mmu_idx,
72
+ bool nonfault, void **phost, uintptr_t retaddr);
73
+
74
#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
75
76
/* Estimated block size for TB allocation. */
77
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
78
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
79
--- a/accel/tcg/cputlb.c
39
--- a/target/arm/t32.decode
80
+++ b/accel/tcg/cputlb.c
40
+++ b/target/arm/t32.decode
81
@@ -XXX,XX +XXX,XX @@ static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size,
41
@@ -XXX,XX +XXX,XX @@
42
&mve_shl_ri rdalo rdahi shim
43
&mve_shl_rr rdalo rdahi rm
44
&mve_sh_ri rda shim
45
+&mve_sh_rr rda rm
46
47
# rdahi: bits [3:1] from insn, bit 0 is 1
48
# rdalo: bits [3:1] from insn, bit 0 is 0
49
@@ -XXX,XX +XXX,XX @@
50
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
51
@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
52
&mve_sh_ri shim=%imm5_12_6
53
+@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
54
55
{
56
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
57
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
58
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
82
}
59
}
83
}
60
84
61
- LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
85
-/*
62
- ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
86
- * Probe for whether the specified guest access is permitted. If it is not
63
- UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
87
- * permitted then an exception will be taken in the same way as if this
64
- SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
88
- * were a real access (and we will not return).
65
+ {
89
- * If the size is 0 or the page requires I/O access, returns NULL; otherwise,
66
+ UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr
90
- * returns the address of the host page similar to tlb_vaddr_to_host().
67
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
91
- */
68
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
92
-void *probe_access(CPUArchState *env, target_ulong addr, int size,
93
- MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
94
+static int probe_access_internal(CPUArchState *env, target_ulong addr,
95
+ int fault_size, MMUAccessType access_type,
96
+ int mmu_idx, bool nonfault,
97
+ void **phost, uintptr_t retaddr)
98
{
99
uintptr_t index = tlb_index(env, mmu_idx, addr);
100
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
101
- target_ulong tlb_addr;
102
- size_t elt_ofs;
103
- int wp_access;
104
-
105
- g_assert(-(addr | TARGET_PAGE_MASK) >= size);
106
-
107
- switch (access_type) {
108
- case MMU_DATA_LOAD:
109
- elt_ofs = offsetof(CPUTLBEntry, addr_read);
110
- wp_access = BP_MEM_READ;
111
- break;
112
- case MMU_DATA_STORE:
113
- elt_ofs = offsetof(CPUTLBEntry, addr_write);
114
- wp_access = BP_MEM_WRITE;
115
- break;
116
- case MMU_INST_FETCH:
117
- elt_ofs = offsetof(CPUTLBEntry, addr_code);
118
- wp_access = BP_MEM_READ;
119
- break;
120
- default:
121
- g_assert_not_reached();
122
- }
123
- tlb_addr = tlb_read_ofs(entry, elt_ofs);
124
-
125
- if (unlikely(!tlb_hit(tlb_addr, addr))) {
126
- if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs,
127
- addr & TARGET_PAGE_MASK)) {
128
- tlb_fill(env_cpu(env), addr, size, access_type, mmu_idx, retaddr);
129
- /* TLB resize via tlb_fill may have moved the entry. */
130
- index = tlb_index(env, mmu_idx, addr);
131
- entry = tlb_entry(env, mmu_idx, addr);
132
- }
133
- tlb_addr = tlb_read_ofs(entry, elt_ofs);
134
- }
135
-
136
- if (!size) {
137
- return NULL;
138
- }
139
-
140
- if (unlikely(tlb_addr & TLB_FLAGS_MASK)) {
141
- CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
142
-
143
- /* Reject I/O access, or other required slow-path. */
144
- if (tlb_addr & (TLB_MMIO | TLB_BSWAP | TLB_DISCARD_WRITE)) {
145
- return NULL;
146
- }
147
-
148
- /* Handle watchpoints. */
149
- if (tlb_addr & TLB_WATCHPOINT) {
150
- cpu_check_watchpoint(env_cpu(env), addr, size,
151
- iotlbentry->attrs, wp_access, retaddr);
152
- }
153
-
154
- /* Handle clean RAM pages. */
155
- if (tlb_addr & TLB_NOTDIRTY) {
156
- notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr);
157
- }
158
- }
159
-
160
- return (void *)((uintptr_t)addr + entry->addend);
161
-}
162
-
163
-void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
164
- MMUAccessType access_type, int mmu_idx)
165
-{
166
- CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
167
- target_ulong tlb_addr, page;
168
+ target_ulong tlb_addr, page_addr;
169
size_t elt_ofs;
170
+ int flags;
171
172
switch (access_type) {
173
case MMU_DATA_LOAD:
174
@@ -XXX,XX +XXX,XX @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
175
default:
176
g_assert_not_reached();
177
}
178
-
179
- page = addr & TARGET_PAGE_MASK;
180
tlb_addr = tlb_read_ofs(entry, elt_ofs);
181
182
- if (!tlb_hit_page(tlb_addr, page)) {
183
- uintptr_t index = tlb_index(env, mmu_idx, addr);
184
-
185
- if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page)) {
186
+ page_addr = addr & TARGET_PAGE_MASK;
187
+ if (!tlb_hit_page(tlb_addr, page_addr)) {
188
+ if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) {
189
CPUState *cs = env_cpu(env);
190
CPUClass *cc = CPU_GET_CLASS(cs);
191
192
- if (!cc->tlb_fill(cs, addr, 0, access_type, mmu_idx, true, 0)) {
193
+ if (!cc->tlb_fill(cs, addr, fault_size, access_type,
194
+ mmu_idx, nonfault, retaddr)) {
195
/* Non-faulting page table read failed. */
196
- return NULL;
197
+ *phost = NULL;
198
+ return TLB_INVALID_MASK;
199
}
200
201
/* TLB resize via tlb_fill may have moved the entry. */
202
@@ -XXX,XX +XXX,XX @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
203
}
204
tlb_addr = tlb_read_ofs(entry, elt_ofs);
205
}
206
+ flags = tlb_addr & TLB_FLAGS_MASK;
207
208
- if (tlb_addr & ~TARGET_PAGE_MASK) {
209
- /* IO access */
210
+ /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */
211
+ if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) {
212
+ *phost = NULL;
213
+ return TLB_MMIO;
214
+ }
69
+ }
215
+
70
+
216
+ /* Everything else is RAM. */
71
+ {
217
+ *phost = (void *)((uintptr_t)addr + entry->addend);
72
+ SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr
218
+ return flags;
73
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
74
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
75
+ }
76
+
77
UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
78
SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
79
]
80
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/mve_helper.c
83
+++ b/target/arm/mve_helper.c
84
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
85
{
86
return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
87
}
88
+
89
+uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
90
+{
91
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
219
+}
92
+}
220
+
93
+
221
+int probe_access_flags(CPUArchState *env, target_ulong addr,
94
+uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
222
+ MMUAccessType access_type, int mmu_idx,
223
+ bool nonfault, void **phost, uintptr_t retaddr)
224
+{
95
+{
225
+ int flags;
96
+ return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
226
+
97
+}
227
+ flags = probe_access_internal(env, addr, 0, access_type, mmu_idx,
98
diff --git a/target/arm/translate.c b/target/arm/translate.c
228
+ nonfault, phost, retaddr);
99
index XXXXXXX..XXXXXXX 100644
229
+
100
--- a/target/arm/translate.c
230
+ /* Handle clean RAM pages. */
101
+++ b/target/arm/translate.c
231
+ if (unlikely(flags & TLB_NOTDIRTY)) {
102
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
232
+ uintptr_t index = tlb_index(env, mmu_idx, addr);
103
return do_mve_sh_ri(s, a, gen_mve_uqshl);
233
+ CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
104
}
234
+
105
235
+ notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr);
106
+static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
236
+ flags &= ~TLB_NOTDIRTY;
107
+{
108
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
109
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
110
+ return false;
111
+ }
112
+ if (!dc_isar_feature(aa32_mve, s) ||
113
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
114
+ a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||
115
+ a->rm == a->rda) {
116
+ /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */
117
+ unallocated_encoding(s);
118
+ return true;
237
+ }
119
+ }
238
+
120
+
239
+ return flags;
121
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
122
+ fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
123
+ return true;
240
+}
124
+}
241
+
125
+
242
+void *probe_access(CPUArchState *env, target_ulong addr, int size,
126
+static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)
243
+ MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
244
+{
127
+{
245
+ void *host;
128
+ return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);
246
+ int flags;
247
+
248
+ g_assert(-(addr | TARGET_PAGE_MASK) >= size);
249
+
250
+ flags = probe_access_internal(env, addr, size, access_type, mmu_idx,
251
+ false, &host, retaddr);
252
+
253
+ /* Per the interface, size == 0 merely faults the access. */
254
+ if (size == 0) {
255
return NULL;
256
}
257
258
- return (void *)((uintptr_t)addr + entry->addend);
259
+ if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) {
260
+ uintptr_t index = tlb_index(env, mmu_idx, addr);
261
+ CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
262
+
263
+ /* Handle watchpoints. */
264
+ if (flags & TLB_WATCHPOINT) {
265
+ int wp_access = (access_type == MMU_DATA_STORE
266
+ ? BP_MEM_WRITE : BP_MEM_READ);
267
+ cpu_check_watchpoint(env_cpu(env), addr, size,
268
+ iotlbentry->attrs, wp_access, retaddr);
269
+ }
270
+
271
+ /* Handle clean RAM pages. */
272
+ if (flags & TLB_NOTDIRTY) {
273
+ notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr);
274
+ }
275
+ }
276
+
277
+ return host;
278
}
279
280
+void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
281
+ MMUAccessType access_type, int mmu_idx)
282
+{
283
+ void *host;
284
+ int flags;
285
+
286
+ flags = probe_access_internal(env, addr, 0, access_type,
287
+ mmu_idx, true, &host, 0);
288
+
289
+ /* No combination of flags are expected by the caller. */
290
+ return flags ? NULL : host;
291
+}
292
293
#ifdef CONFIG_PLUGIN
294
/*
295
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
296
index XXXXXXX..XXXXXXX 100644
297
--- a/accel/tcg/user-exec.c
298
+++ b/accel/tcg/user-exec.c
299
@@ -XXX,XX +XXX,XX @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
300
g_assert_not_reached();
301
}
302
303
-void *probe_access(CPUArchState *env, target_ulong addr, int size,
304
- MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
305
+static int probe_access_internal(CPUArchState *env, target_ulong addr,
306
+ int fault_size, MMUAccessType access_type,
307
+ bool nonfault, uintptr_t ra)
308
{
309
int flags;
310
311
- g_assert(-(addr | TARGET_PAGE_MASK) >= size);
312
-
313
switch (access_type) {
314
case MMU_DATA_STORE:
315
flags = PAGE_WRITE;
316
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
317
}
318
319
if (!guest_addr_valid(addr) || page_check_range(addr, 1, flags) < 0) {
320
- CPUState *cpu = env_cpu(env);
321
- CPUClass *cc = CPU_GET_CLASS(cpu);
322
- cc->tlb_fill(cpu, addr, size, access_type, MMU_USER_IDX, false,
323
- retaddr);
324
- g_assert_not_reached();
325
+ if (nonfault) {
326
+ return TLB_INVALID_MASK;
327
+ } else {
328
+ CPUState *cpu = env_cpu(env);
329
+ CPUClass *cc = CPU_GET_CLASS(cpu);
330
+ cc->tlb_fill(cpu, addr, fault_size, access_type,
331
+ MMU_USER_IDX, false, ra);
332
+ g_assert_not_reached();
333
+ }
334
}
335
+ return 0;
336
+}
129
+}
337
+
130
+
338
+int probe_access_flags(CPUArchState *env, target_ulong addr,
131
+static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)
339
+ MMUAccessType access_type, int mmu_idx,
340
+ bool nonfault, void **phost, uintptr_t ra)
341
+{
132
+{
342
+ int flags;
133
+ return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);
343
+
344
+ flags = probe_access_internal(env, addr, 0, access_type, nonfault, ra);
345
+ *phost = flags ? NULL : g2h(addr);
346
+ return flags;
347
+}
134
+}
348
+
135
+
349
+void *probe_access(CPUArchState *env, target_ulong addr, int size,
136
/*
350
+ MMUAccessType access_type, int mmu_idx, uintptr_t ra)
137
* Multiply and multiply accumulate
351
+{
138
*/
352
+ int flags;
353
+
354
+ g_assert(-(addr | TARGET_PAGE_MASK) >= size);
355
+ flags = probe_access_internal(env, addr, size, access_type, false, ra);
356
+ g_assert(flags == 0);
357
358
return size ? g2h(addr) : NULL;
359
}
360
--
139
--
361
2.20.1
140
2.20.1
362
141
363
142
diff view generated by jsdifflib
[PULL 14/34] target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Use the "normal" memory access functions, rather than the
4
softmmu internal helper functions directly.
5
6
Since fb901c905dc3, cpu_mem_index is now a simple extract
7
from env->hflags and not a large computation. Which means
8
that it's now more work to pass around this value than it
9
is to recompute it.
10
11
This only adjusts the primitives, and does not clean up
12
all of the uses within sve_helper.c.
13
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 20200508154359.7494-8-richard.henderson@linaro.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
target/arm/sve_helper.c | 221 ++++++++++++++++------------------------
20
1 file changed, 86 insertions(+), 135 deletions(-)
21
22
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/sve_helper.c
25
+++ b/target/arm/sve_helper.c
26
@@ -XXX,XX +XXX,XX @@ typedef intptr_t sve_ld1_host_fn(void *vd, void *vg, void *host,
27
* Load one element into @vd + @reg_off from (@env, @vaddr, @ra).
28
* The controlling predicate is known to be true.
29
*/
30
-typedef void sve_ld1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
31
- target_ulong vaddr, TCGMemOpIdx oi, uintptr_t ra);
32
-typedef sve_ld1_tlb_fn sve_st1_tlb_fn;
33
+typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
34
+ target_ulong vaddr, uintptr_t retaddr);
35
36
/*
37
* Generate the above primitives.
38
@@ -XXX,XX +XXX,XX @@ static intptr_t sve_##NAME##_host(void *vd, void *vg, void *host, \
39
return mem_off; \
40
}
41
42
-#ifdef CONFIG_SOFTMMU
43
-#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, HOST, MOEND, TLB) \
44
+#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \
45
static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
46
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
47
+ target_ulong addr, uintptr_t ra) \
48
{ \
49
- TYPEM val = TLB(env, addr, oi, ra); \
50
- *(TYPEE *)(vd + H(reg_off)) = val; \
51
+ *(TYPEE *)(vd + H(reg_off)) = (TYPEM)TLB(env, addr, ra); \
52
}
53
-#else
54
-#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, HOST, MOEND, TLB) \
55
+
56
+#define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \
57
static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
58
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
59
+ target_ulong addr, uintptr_t ra) \
60
{ \
61
- TYPEM val = HOST(g2h(addr)); \
62
- *(TYPEE *)(vd + H(reg_off)) = val; \
63
+ TLB(env, addr, (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); \
64
}
65
-#endif
66
67
#define DO_LD_PRIM_1(NAME, H, TE, TM) \
68
DO_LD_HOST(NAME, H, TE, TM, ldub_p) \
69
- DO_LD_TLB(NAME, H, TE, TM, ldub_p, 0, helper_ret_ldub_mmu)
70
+ DO_LD_TLB(NAME, H, TE, TM, cpu_ldub_data_ra)
71
72
DO_LD_PRIM_1(ld1bb, H1, uint8_t, uint8_t)
73
DO_LD_PRIM_1(ld1bhu, H1_2, uint16_t, uint8_t)
74
@@ -XXX,XX +XXX,XX @@ DO_LD_PRIM_1(ld1bss, H1_4, uint32_t, int8_t)
75
DO_LD_PRIM_1(ld1bdu, , uint64_t, uint8_t)
76
DO_LD_PRIM_1(ld1bds, , uint64_t, int8_t)
77
78
-#define DO_LD_PRIM_2(NAME, end, MOEND, H, TE, TM, PH, PT) \
79
- DO_LD_HOST(NAME##_##end, H, TE, TM, PH##_##end##_p) \
80
- DO_LD_TLB(NAME##_##end, H, TE, TM, PH##_##end##_p, \
81
- MOEND, helper_##end##_##PT##_mmu)
82
+#define DO_ST_PRIM_1(NAME, H, TE, TM) \
83
+ DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra)
84
85
-DO_LD_PRIM_2(ld1hh, le, MO_LE, H1_2, uint16_t, uint16_t, lduw, lduw)
86
-DO_LD_PRIM_2(ld1hsu, le, MO_LE, H1_4, uint32_t, uint16_t, lduw, lduw)
87
-DO_LD_PRIM_2(ld1hss, le, MO_LE, H1_4, uint32_t, int16_t, lduw, lduw)
88
-DO_LD_PRIM_2(ld1hdu, le, MO_LE, , uint64_t, uint16_t, lduw, lduw)
89
-DO_LD_PRIM_2(ld1hds, le, MO_LE, , uint64_t, int16_t, lduw, lduw)
90
+DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t)
91
+DO_ST_PRIM_1(bh, H1_2, uint16_t, uint8_t)
92
+DO_ST_PRIM_1(bs, H1_4, uint32_t, uint8_t)
93
+DO_ST_PRIM_1(bd, , uint64_t, uint8_t)
94
95
-DO_LD_PRIM_2(ld1ss, le, MO_LE, H1_4, uint32_t, uint32_t, ldl, ldul)
96
-DO_LD_PRIM_2(ld1sdu, le, MO_LE, , uint64_t, uint32_t, ldl, ldul)
97
-DO_LD_PRIM_2(ld1sds, le, MO_LE, , uint64_t, int32_t, ldl, ldul)
98
+#define DO_LD_PRIM_2(NAME, H, TE, TM, LD) \
99
+ DO_LD_HOST(ld1##NAME##_be, H, TE, TM, LD##_be_p) \
100
+ DO_LD_HOST(ld1##NAME##_le, H, TE, TM, LD##_le_p) \
101
+ DO_LD_TLB(ld1##NAME##_be, H, TE, TM, cpu_##LD##_be_data_ra) \
102
+ DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra)
103
104
-DO_LD_PRIM_2(ld1dd, le, MO_LE, , uint64_t, uint64_t, ldq, ldq)
105
+#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \
106
+ DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \
107
+ DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra)
108
109
-DO_LD_PRIM_2(ld1hh, be, MO_BE, H1_2, uint16_t, uint16_t, lduw, lduw)
110
-DO_LD_PRIM_2(ld1hsu, be, MO_BE, H1_4, uint32_t, uint16_t, lduw, lduw)
111
-DO_LD_PRIM_2(ld1hss, be, MO_BE, H1_4, uint32_t, int16_t, lduw, lduw)
112
-DO_LD_PRIM_2(ld1hdu, be, MO_BE, , uint64_t, uint16_t, lduw, lduw)
113
-DO_LD_PRIM_2(ld1hds, be, MO_BE, , uint64_t, int16_t, lduw, lduw)
114
+DO_LD_PRIM_2(hh, H1_2, uint16_t, uint16_t, lduw)
115
+DO_LD_PRIM_2(hsu, H1_4, uint32_t, uint16_t, lduw)
116
+DO_LD_PRIM_2(hss, H1_4, uint32_t, int16_t, lduw)
117
+DO_LD_PRIM_2(hdu, , uint64_t, uint16_t, lduw)
118
+DO_LD_PRIM_2(hds, , uint64_t, int16_t, lduw)
119
120
-DO_LD_PRIM_2(ld1ss, be, MO_BE, H1_4, uint32_t, uint32_t, ldl, ldul)
121
-DO_LD_PRIM_2(ld1sdu, be, MO_BE, , uint64_t, uint32_t, ldl, ldul)
122
-DO_LD_PRIM_2(ld1sds, be, MO_BE, , uint64_t, int32_t, ldl, ldul)
123
+DO_ST_PRIM_2(hh, H1_2, uint16_t, uint16_t, stw)
124
+DO_ST_PRIM_2(hs, H1_4, uint32_t, uint16_t, stw)
125
+DO_ST_PRIM_2(hd, , uint64_t, uint16_t, stw)
126
127
-DO_LD_PRIM_2(ld1dd, be, MO_BE, , uint64_t, uint64_t, ldq, ldq)
128
+DO_LD_PRIM_2(ss, H1_4, uint32_t, uint32_t, ldl)
129
+DO_LD_PRIM_2(sdu, , uint64_t, uint32_t, ldl)
130
+DO_LD_PRIM_2(sds, , uint64_t, int32_t, ldl)
131
+
132
+DO_ST_PRIM_2(ss, H1_4, uint32_t, uint32_t, stl)
133
+DO_ST_PRIM_2(sd, , uint64_t, uint32_t, stl)
134
+
135
+DO_LD_PRIM_2(dd, , uint64_t, uint64_t, ldq)
136
+DO_ST_PRIM_2(dd, , uint64_t, uint64_t, stq)
137
138
#undef DO_LD_TLB
139
+#undef DO_ST_TLB
140
#undef DO_LD_HOST
141
#undef DO_LD_PRIM_1
142
+#undef DO_ST_PRIM_1
143
#undef DO_LD_PRIM_2
144
+#undef DO_ST_PRIM_2
145
146
/*
147
* Skip through a sequence of inactive elements in the guarding predicate @vg,
148
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
149
uint32_t desc, const uintptr_t retaddr,
150
const int esz, const int msz,
151
sve_ld1_host_fn *host_fn,
152
- sve_ld1_tlb_fn *tlb_fn)
153
+ sve_ldst1_tlb_fn *tlb_fn)
154
{
155
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
156
const int mmu_idx = get_mmuidx(oi);
157
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
158
* on I/O memory, it may succeed but not bring in the TLB entry.
159
* But even then we have still made forward progress.
160
*/
161
- tlb_fn(env, &scratch, reg_off, addr + mem_off, oi, retaddr);
162
+ tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
163
reg_off += 1 << esz;
164
}
165
#endif
166
@@ -XXX,XX +XXX,XX @@ DO_LD1_2(ld1dd, 3, 3)
167
*/
168
static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
169
uint32_t desc, int size, uintptr_t ra,
170
- sve_ld1_tlb_fn *tlb_fn)
171
+ sve_ldst1_tlb_fn *tlb_fn)
172
{
173
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
174
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
175
intptr_t i, oprsz = simd_oprsz(desc);
176
ARMVectorReg scratch[2] = { };
177
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
178
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
179
do {
180
if (pg & 1) {
181
- tlb_fn(env, &scratch[0], i, addr, oi, ra);
182
- tlb_fn(env, &scratch[1], i, addr + size, oi, ra);
183
+ tlb_fn(env, &scratch[0], i, addr, ra);
184
+ tlb_fn(env, &scratch[1], i, addr + size, ra);
185
}
186
i += size, pg >>= size;
187
addr += 2 * size;
188
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
189
190
static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
191
uint32_t desc, int size, uintptr_t ra,
192
- sve_ld1_tlb_fn *tlb_fn)
193
+ sve_ldst1_tlb_fn *tlb_fn)
194
{
195
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
196
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
197
intptr_t i, oprsz = simd_oprsz(desc);
198
ARMVectorReg scratch[3] = { };
199
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
200
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
201
do {
202
if (pg & 1) {
203
- tlb_fn(env, &scratch[0], i, addr, oi, ra);
204
- tlb_fn(env, &scratch[1], i, addr + size, oi, ra);
205
- tlb_fn(env, &scratch[2], i, addr + 2 * size, oi, ra);
206
+ tlb_fn(env, &scratch[0], i, addr, ra);
207
+ tlb_fn(env, &scratch[1], i, addr + size, ra);
208
+ tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
209
}
210
i += size, pg >>= size;
211
addr += 3 * size;
212
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
213
214
static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
215
uint32_t desc, int size, uintptr_t ra,
216
- sve_ld1_tlb_fn *tlb_fn)
217
+ sve_ldst1_tlb_fn *tlb_fn)
218
{
219
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
220
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
221
intptr_t i, oprsz = simd_oprsz(desc);
222
ARMVectorReg scratch[4] = { };
223
@@ -XXX,XX +XXX,XX @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
224
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
225
do {
226
if (pg & 1) {
227
- tlb_fn(env, &scratch[0], i, addr, oi, ra);
228
- tlb_fn(env, &scratch[1], i, addr + size, oi, ra);
229
- tlb_fn(env, &scratch[2], i, addr + 2 * size, oi, ra);
230
- tlb_fn(env, &scratch[3], i, addr + 3 * size, oi, ra);
231
+ tlb_fn(env, &scratch[0], i, addr, ra);
232
+ tlb_fn(env, &scratch[1], i, addr + size, ra);
233
+ tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
234
+ tlb_fn(env, &scratch[3], i, addr + 3 * size, ra);
235
}
236
i += size, pg >>= size;
237
addr += 4 * size;
238
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
239
uint32_t desc, const uintptr_t retaddr,
240
const int esz, const int msz,
241
sve_ld1_host_fn *host_fn,
242
- sve_ld1_tlb_fn *tlb_fn)
243
+ sve_ldst1_tlb_fn *tlb_fn)
244
{
245
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
246
const int mmu_idx = get_mmuidx(oi);
247
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
248
* Perform one normal read, which will fault or not.
249
* But it is likely to bring the page into the tlb.
250
*/
251
- tlb_fn(env, vd, reg_off, addr + mem_off, oi, retaddr);
252
+ tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
253
254
/* After any fault, zero any leading predicated false elts. */
255
swap_memzero(vd, reg_off);
256
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_LDNF1_2(dd, 3, 3)
257
#undef DO_LDFF1_LDNF1_1
258
#undef DO_LDFF1_LDNF1_2
259
260
-/*
261
- * Store contiguous data, protected by a governing predicate.
262
- */
263
-
264
-#ifdef CONFIG_SOFTMMU
265
-#define DO_ST_TLB(NAME, H, TYPEM, HOST, MOEND, TLB) \
266
-static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
267
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
268
-{ \
269
- TLB(env, addr, *(TYPEM *)(vd + H(reg_off)), oi, ra); \
270
-}
271
-#else
272
-#define DO_ST_TLB(NAME, H, TYPEM, HOST, MOEND, TLB) \
273
-static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
274
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
275
-{ \
276
- HOST(g2h(addr), *(TYPEM *)(vd + H(reg_off))); \
277
-}
278
-#endif
279
-
280
-DO_ST_TLB(st1bb, H1, uint8_t, stb_p, 0, helper_ret_stb_mmu)
281
-DO_ST_TLB(st1bh, H1_2, uint16_t, stb_p, 0, helper_ret_stb_mmu)
282
-DO_ST_TLB(st1bs, H1_4, uint32_t, stb_p, 0, helper_ret_stb_mmu)
283
-DO_ST_TLB(st1bd, , uint64_t, stb_p, 0, helper_ret_stb_mmu)
284
-
285
-DO_ST_TLB(st1hh_le, H1_2, uint16_t, stw_le_p, MO_LE, helper_le_stw_mmu)
286
-DO_ST_TLB(st1hs_le, H1_4, uint32_t, stw_le_p, MO_LE, helper_le_stw_mmu)
287
-DO_ST_TLB(st1hd_le, , uint64_t, stw_le_p, MO_LE, helper_le_stw_mmu)
288
-
289
-DO_ST_TLB(st1ss_le, H1_4, uint32_t, stl_le_p, MO_LE, helper_le_stl_mmu)
290
-DO_ST_TLB(st1sd_le, , uint64_t, stl_le_p, MO_LE, helper_le_stl_mmu)
291
-
292
-DO_ST_TLB(st1dd_le, , uint64_t, stq_le_p, MO_LE, helper_le_stq_mmu)
293
-
294
-DO_ST_TLB(st1hh_be, H1_2, uint16_t, stw_be_p, MO_BE, helper_be_stw_mmu)
295
-DO_ST_TLB(st1hs_be, H1_4, uint32_t, stw_be_p, MO_BE, helper_be_stw_mmu)
296
-DO_ST_TLB(st1hd_be, , uint64_t, stw_be_p, MO_BE, helper_be_stw_mmu)
297
-
298
-DO_ST_TLB(st1ss_be, H1_4, uint32_t, stl_be_p, MO_BE, helper_be_stl_mmu)
299
-DO_ST_TLB(st1sd_be, , uint64_t, stl_be_p, MO_BE, helper_be_stl_mmu)
300
-
301
-DO_ST_TLB(st1dd_be, , uint64_t, stq_be_p, MO_BE, helper_be_stq_mmu)
302
-
303
-#undef DO_ST_TLB
304
-
305
/*
306
* Common helpers for all contiguous 1,2,3,4-register predicated stores.
307
*/
308
static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
309
uint32_t desc, const uintptr_t ra,
310
const int esize, const int msize,
311
- sve_st1_tlb_fn *tlb_fn)
312
+ sve_ldst1_tlb_fn *tlb_fn)
313
{
314
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
315
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
316
intptr_t i, oprsz = simd_oprsz(desc);
317
void *vd = &env->vfp.zregs[rd];
318
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
319
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
320
do {
321
if (pg & 1) {
322
- tlb_fn(env, vd, i, addr, oi, ra);
323
+ tlb_fn(env, vd, i, addr, ra);
324
}
325
i += esize, pg >>= esize;
326
addr += msize;
327
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
328
static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
329
uint32_t desc, const uintptr_t ra,
330
const int esize, const int msize,
331
- sve_st1_tlb_fn *tlb_fn)
332
+ sve_ldst1_tlb_fn *tlb_fn)
333
{
334
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
335
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
336
intptr_t i, oprsz = simd_oprsz(desc);
337
void *d1 = &env->vfp.zregs[rd];
338
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
339
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
340
do {
341
if (pg & 1) {
342
- tlb_fn(env, d1, i, addr, oi, ra);
343
- tlb_fn(env, d2, i, addr + msize, oi, ra);
344
+ tlb_fn(env, d1, i, addr, ra);
345
+ tlb_fn(env, d2, i, addr + msize, ra);
346
}
347
i += esize, pg >>= esize;
348
addr += 2 * msize;
349
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
350
static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
351
uint32_t desc, const uintptr_t ra,
352
const int esize, const int msize,
353
- sve_st1_tlb_fn *tlb_fn)
354
+ sve_ldst1_tlb_fn *tlb_fn)
355
{
356
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
357
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
358
intptr_t i, oprsz = simd_oprsz(desc);
359
void *d1 = &env->vfp.zregs[rd];
360
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
361
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
362
do {
363
if (pg & 1) {
364
- tlb_fn(env, d1, i, addr, oi, ra);
365
- tlb_fn(env, d2, i, addr + msize, oi, ra);
366
- tlb_fn(env, d3, i, addr + 2 * msize, oi, ra);
367
+ tlb_fn(env, d1, i, addr, ra);
368
+ tlb_fn(env, d2, i, addr + msize, ra);
369
+ tlb_fn(env, d3, i, addr + 2 * msize, ra);
370
}
371
i += esize, pg >>= esize;
372
addr += 3 * msize;
373
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
374
static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
375
uint32_t desc, const uintptr_t ra,
376
const int esize, const int msize,
377
- sve_st1_tlb_fn *tlb_fn)
378
+ sve_ldst1_tlb_fn *tlb_fn)
379
{
380
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
381
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
382
intptr_t i, oprsz = simd_oprsz(desc);
383
void *d1 = &env->vfp.zregs[rd];
384
@@ -XXX,XX +XXX,XX @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
385
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
386
do {
387
if (pg & 1) {
388
- tlb_fn(env, d1, i, addr, oi, ra);
389
- tlb_fn(env, d2, i, addr + msize, oi, ra);
390
- tlb_fn(env, d3, i, addr + 2 * msize, oi, ra);
391
- tlb_fn(env, d4, i, addr + 3 * msize, oi, ra);
392
+ tlb_fn(env, d1, i, addr, ra);
393
+ tlb_fn(env, d2, i, addr + msize, ra);
394
+ tlb_fn(env, d3, i, addr + 2 * msize, ra);
395
+ tlb_fn(env, d4, i, addr + 3 * msize, ra);
396
}
397
i += esize, pg >>= esize;
398
addr += 4 * msize;
399
@@ -XXX,XX +XXX,XX @@ static target_ulong off_zd_d(void *reg, intptr_t reg_ofs)
400
401
static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
402
target_ulong base, uint32_t desc, uintptr_t ra,
403
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
404
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
405
{
406
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
407
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
408
intptr_t i, oprsz = simd_oprsz(desc);
409
ARMVectorReg scratch = { };
410
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
411
do {
412
if (likely(pg & 1)) {
413
target_ulong off = off_fn(vm, i);
414
- tlb_fn(env, &scratch, i, base + (off << scale), oi, ra);
415
+ tlb_fn(env, &scratch, i, base + (off << scale), ra);
416
}
417
i += 4, pg >>= 4;
418
} while (i & 15);
419
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
420
421
static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
422
target_ulong base, uint32_t desc, uintptr_t ra,
423
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
424
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
425
{
426
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
427
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
428
intptr_t i, oprsz = simd_oprsz(desc) / 8;
429
ARMVectorReg scratch = { };
430
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
431
uint8_t pg = *(uint8_t *)(vg + H1(i));
432
if (likely(pg & 1)) {
433
target_ulong off = off_fn(vm, i * 8);
434
- tlb_fn(env, &scratch, i * 8, base + (off << scale), oi, ra);
435
+ tlb_fn(env, &scratch, i * 8, base + (off << scale), ra);
436
}
437
}
438
clear_helper_retaddr();
439
@@ -XXX,XX +XXX,XX @@ DO_LD_NF(dd_be, , uint64_t, uint64_t, ldq_be_p)
440
*/
441
static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
442
target_ulong base, uint32_t desc, uintptr_t ra,
443
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn,
444
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
445
sve_ld1_nf_fn *nonfault_fn)
446
{
447
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
448
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
449
set_helper_retaddr(ra);
450
addr = off_fn(vm, reg_off);
451
addr = base + (addr << scale);
452
- tlb_fn(env, vd, reg_off, addr, oi, ra);
453
+ tlb_fn(env, vd, reg_off, addr, ra);
454
455
/* The rest of the reads will be non-faulting. */
456
clear_helper_retaddr();
457
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
458
459
static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
460
target_ulong base, uint32_t desc, uintptr_t ra,
461
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn,
462
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
463
sve_ld1_nf_fn *nonfault_fn)
464
{
465
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
466
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
467
set_helper_retaddr(ra);
468
addr = off_fn(vm, reg_off);
469
addr = base + (addr << scale);
470
- tlb_fn(env, vd, reg_off, addr, oi, ra);
471
+ tlb_fn(env, vd, reg_off, addr, ra);
472
473
/* The rest of the reads will be non-faulting. */
474
clear_helper_retaddr();
475
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_ZPZ_D(dd_be, zd)
476
477
static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
478
target_ulong base, uint32_t desc, uintptr_t ra,
479
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
480
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
481
{
482
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
483
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
484
intptr_t i, oprsz = simd_oprsz(desc);
485
486
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
487
do {
488
if (likely(pg & 1)) {
489
target_ulong off = off_fn(vm, i);
490
- tlb_fn(env, vd, i, base + (off << scale), oi, ra);
491
+ tlb_fn(env, vd, i, base + (off << scale), ra);
492
}
493
i += 4, pg >>= 4;
494
} while (i & 15);
495
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
496
497
static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
498
target_ulong base, uint32_t desc, uintptr_t ra,
499
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
500
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
501
{
502
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
503
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
504
intptr_t i, oprsz = simd_oprsz(desc) / 8;
505
506
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
507
uint8_t pg = *(uint8_t *)(vg + H1(i));
508
if (likely(pg & 1)) {
509
target_ulong off = off_fn(vm, i * 8);
510
- tlb_fn(env, vd, i * 8, base + (off << scale), oi, ra);
511
+ tlb_fn(env, vd, i * 8, base + (off << scale), ra);
512
}
513
}
514
clear_helper_retaddr();
515
--
516
2.20.1
517
518
diff view generated by jsdifflib
[PULL 15/34] target/arm: Drop manual handling of set/clear_helper_retaddr
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Since we converted back to cpu_*_data_ra, we do not need to
4
do this ourselves.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200508154359.7494-9-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/sve_helper.c | 38 --------------------------------------
12
1 file changed, 38 deletions(-)
13
14
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/sve_helper.c
17
+++ b/target/arm/sve_helper.c
18
@@ -XXX,XX +XXX,XX @@ static intptr_t max_for_page(target_ulong base, intptr_t mem_off,
19
return MIN(split, mem_max - mem_off) + mem_off;
20
}
21
22
-#ifndef CONFIG_USER_ONLY
23
-/* These are normally defined only for CONFIG_USER_ONLY in <exec/cpu_ldst.h> */
24
-static inline void set_helper_retaddr(uintptr_t ra) { }
25
-static inline void clear_helper_retaddr(void) { }
26
-#endif
27
-
28
/*
29
* The result of tlb_vaddr_to_host for user-only is just g2h(x),
30
* which is always non-null. Elide the useless test.
31
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
32
return;
33
}
34
mem_off = reg_off >> diffsz;
35
- set_helper_retaddr(retaddr);
36
37
/*
38
* If the (remaining) load is entirely within a single page, then:
39
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
40
if (test_host_page(host)) {
41
mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
42
tcg_debug_assert(mem_off == mem_max);
43
- clear_helper_retaddr();
44
/* After having taken any fault, zero leading inactive elements. */
45
swap_memzero(vd, reg_off);
46
return;
47
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
48
}
49
#endif
50
51
- clear_helper_retaddr();
52
memcpy(vd, &scratch, reg_max);
53
}
54
55
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
56
intptr_t i, oprsz = simd_oprsz(desc);
57
ARMVectorReg scratch[2] = { };
58
59
- set_helper_retaddr(ra);
60
for (i = 0; i < oprsz; ) {
61
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
62
do {
63
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
64
addr += 2 * size;
65
} while (i & 15);
66
}
67
- clear_helper_retaddr();
68
69
/* Wait until all exceptions have been raised to write back. */
70
memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
71
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
72
intptr_t i, oprsz = simd_oprsz(desc);
73
ARMVectorReg scratch[3] = { };
74
75
- set_helper_retaddr(ra);
76
for (i = 0; i < oprsz; ) {
77
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
78
do {
79
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
80
addr += 3 * size;
81
} while (i & 15);
82
}
83
- clear_helper_retaddr();
84
85
/* Wait until all exceptions have been raised to write back. */
86
memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
87
@@ -XXX,XX +XXX,XX @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
88
intptr_t i, oprsz = simd_oprsz(desc);
89
ARMVectorReg scratch[4] = { };
90
91
- set_helper_retaddr(ra);
92
for (i = 0; i < oprsz; ) {
93
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
94
do {
95
@@ -XXX,XX +XXX,XX @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
96
addr += 4 * size;
97
} while (i & 15);
98
}
99
- clear_helper_retaddr();
100
101
/* Wait until all exceptions have been raised to write back. */
102
memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
103
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
104
return;
105
}
106
mem_off = reg_off >> diffsz;
107
- set_helper_retaddr(retaddr);
108
109
/*
110
* If the (remaining) load is entirely within a single page, then:
111
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
112
if (test_host_page(host)) {
113
mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
114
tcg_debug_assert(mem_off == mem_max);
115
- clear_helper_retaddr();
116
/* After any fault, zero any leading inactive elements. */
117
swap_memzero(vd, reg_off);
118
return;
119
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
120
}
121
#endif
122
123
- clear_helper_retaddr();
124
record_fault(env, reg_off, reg_max);
125
}
126
127
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
128
intptr_t i, oprsz = simd_oprsz(desc);
129
void *vd = &env->vfp.zregs[rd];
130
131
- set_helper_retaddr(ra);
132
for (i = 0; i < oprsz; ) {
133
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
134
do {
135
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
136
addr += msize;
137
} while (i & 15);
138
}
139
- clear_helper_retaddr();
140
}
141
142
static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
143
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
144
void *d1 = &env->vfp.zregs[rd];
145
void *d2 = &env->vfp.zregs[(rd + 1) & 31];
146
147
- set_helper_retaddr(ra);
148
for (i = 0; i < oprsz; ) {
149
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
150
do {
151
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
152
addr += 2 * msize;
153
} while (i & 15);
154
}
155
- clear_helper_retaddr();
156
}
157
158
static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
159
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
160
void *d2 = &env->vfp.zregs[(rd + 1) & 31];
161
void *d3 = &env->vfp.zregs[(rd + 2) & 31];
162
163
- set_helper_retaddr(ra);
164
for (i = 0; i < oprsz; ) {
165
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
166
do {
167
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
168
addr += 3 * msize;
169
} while (i & 15);
170
}
171
- clear_helper_retaddr();
172
}
173
174
static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
175
@@ -XXX,XX +XXX,XX @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
176
void *d3 = &env->vfp.zregs[(rd + 2) & 31];
177
void *d4 = &env->vfp.zregs[(rd + 3) & 31];
178
179
- set_helper_retaddr(ra);
180
for (i = 0; i < oprsz; ) {
181
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
182
do {
183
@@ -XXX,XX +XXX,XX @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
184
addr += 4 * msize;
185
} while (i & 15);
186
}
187
- clear_helper_retaddr();
188
}
189
190
#define DO_STN_1(N, NAME, ESIZE) \
191
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
192
intptr_t i, oprsz = simd_oprsz(desc);
193
ARMVectorReg scratch = { };
194
195
- set_helper_retaddr(ra);
196
for (i = 0; i < oprsz; ) {
197
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
198
do {
199
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
200
i += 4, pg >>= 4;
201
} while (i & 15);
202
}
203
- clear_helper_retaddr();
204
205
/* Wait until all exceptions have been raised to write back. */
206
memcpy(vd, &scratch, oprsz);
207
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
208
intptr_t i, oprsz = simd_oprsz(desc) / 8;
209
ARMVectorReg scratch = { };
210
211
- set_helper_retaddr(ra);
212
for (i = 0; i < oprsz; i++) {
213
uint8_t pg = *(uint8_t *)(vg + H1(i));
214
if (likely(pg & 1)) {
215
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
216
tlb_fn(env, &scratch, i * 8, base + (off << scale), ra);
217
}
218
}
219
- clear_helper_retaddr();
220
221
/* Wait until all exceptions have been raised to write back. */
222
memcpy(vd, &scratch, oprsz * 8);
223
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
224
reg_off = find_next_active(vg, 0, reg_max, MO_32);
225
if (likely(reg_off < reg_max)) {
226
/* Perform one normal read, which will fault or not. */
227
- set_helper_retaddr(ra);
228
addr = off_fn(vm, reg_off);
229
addr = base + (addr << scale);
230
tlb_fn(env, vd, reg_off, addr, ra);
231
232
/* The rest of the reads will be non-faulting. */
233
- clear_helper_retaddr();
234
}
235
236
/* After any fault, zero the leading predicated false elements. */
237
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
238
reg_off = find_next_active(vg, 0, reg_max, MO_64);
239
if (likely(reg_off < reg_max)) {
240
/* Perform one normal read, which will fault or not. */
241
- set_helper_retaddr(ra);
242
addr = off_fn(vm, reg_off);
243
addr = base + (addr << scale);
244
tlb_fn(env, vd, reg_off, addr, ra);
245
246
/* The rest of the reads will be non-faulting. */
247
- clear_helper_retaddr();
248
}
249
250
/* After any fault, zero the leading predicated false elements. */
251
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
252
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
253
intptr_t i, oprsz = simd_oprsz(desc);
254
255
- set_helper_retaddr(ra);
256
for (i = 0; i < oprsz; ) {
257
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
258
do {
259
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
260
i += 4, pg >>= 4;
261
} while (i & 15);
262
}
263
- clear_helper_retaddr();
264
}
265
266
static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
267
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
268
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
269
intptr_t i, oprsz = simd_oprsz(desc) / 8;
270
271
- set_helper_retaddr(ra);
272
for (i = 0; i < oprsz; i++) {
273
uint8_t pg = *(uint8_t *)(vg + H1(i));
274
if (likely(pg & 1)) {
275
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
276
tlb_fn(env, vd, i * 8, base + (off << scale), ra);
277
}
278
}
279
- clear_helper_retaddr();
280
}
281
282
#define DO_ST1_ZPZ_S(MEM, OFS) \
283
--
284
2.20.1
285
286
diff view generated by jsdifflib
[PULL 24/34] target/arm: Reuse sve_probe_page for scatter stores
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200508154359.7494-18-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/sve_helper.c | 182 ++++++++++++++++++++++++----------------
9
1 file changed, 111 insertions(+), 71 deletions(-)
10
11
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/sve_helper.c
14
+++ b/target/arm/sve_helper.c
15
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_ZPZ_D(dd_be, zd, MO_64)
16
17
/* Stores with a vector index. */
18
19
-static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
20
- target_ulong base, uint32_t desc, uintptr_t ra,
21
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
22
+static inline QEMU_ALWAYS_INLINE
23
+void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
24
+ target_ulong base, uint32_t desc, uintptr_t retaddr,
25
+ int esize, int msize, zreg_off_fn *off_fn,
26
+ sve_ldst1_host_fn *host_fn,
27
+ sve_ldst1_tlb_fn *tlb_fn)
28
{
29
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
30
- intptr_t i, oprsz = simd_oprsz(desc);
31
+ const int mmu_idx = cpu_mmu_index(env, false);
32
+ const intptr_t reg_max = simd_oprsz(desc);
33
+ void *host[ARM_MAX_VQ * 4];
34
+ intptr_t reg_off, i;
35
+ SVEHostPage info, info2;
36
37
- for (i = 0; i < oprsz; ) {
38
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
39
+ /*
40
+ * Probe all of the elements for host addresses and flags.
41
+ */
42
+ i = reg_off = 0;
43
+ do {
44
+ uint64_t pg = vg[reg_off >> 6];
45
do {
46
- if (likely(pg & 1)) {
47
- target_ulong off = off_fn(vm, i);
48
- tlb_fn(env, vd, i, base + (off << scale), ra);
49
+ target_ulong addr = base + (off_fn(vm, reg_off) << scale);
50
+ target_ulong in_page = -(addr | TARGET_PAGE_MASK);
51
+
52
+ host[i] = NULL;
53
+ if (likely((pg >> (reg_off & 63)) & 1)) {
54
+ if (likely(in_page >= msize)) {
55
+ sve_probe_page(&info, false, env, addr, 0, MMU_DATA_STORE,
56
+ mmu_idx, retaddr);
57
+ host[i] = info.host;
58
+ } else {
59
+ /*
60
+ * Element crosses the page boundary.
61
+ * Probe both pages, but do not record the host address,
62
+ * so that we use the slow path.
63
+ */
64
+ sve_probe_page(&info, false, env, addr, 0,
65
+ MMU_DATA_STORE, mmu_idx, retaddr);
66
+ sve_probe_page(&info2, false, env, addr + in_page, 0,
67
+ MMU_DATA_STORE, mmu_idx, retaddr);
68
+ info.flags |= info2.flags;
69
+ }
70
+
71
+ if (unlikely(info.flags & TLB_WATCHPOINT)) {
72
+ cpu_check_watchpoint(env_cpu(env), addr, msize,
73
+ info.attrs, BP_MEM_WRITE, retaddr);
74
+ }
75
+ /* TODO: MTE check. */
76
}
77
- i += 4, pg >>= 4;
78
- } while (i & 15);
79
- }
80
-}
81
+ i += 1;
82
+ reg_off += esize;
83
+ } while (reg_off & 63);
84
+ } while (reg_off < reg_max);
85
86
-static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
87
- target_ulong base, uint32_t desc, uintptr_t ra,
88
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
89
-{
90
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
91
- intptr_t i, oprsz = simd_oprsz(desc) / 8;
92
-
93
- for (i = 0; i < oprsz; i++) {
94
- uint8_t pg = *(uint8_t *)(vg + H1(i));
95
- if (likely(pg & 1)) {
96
- target_ulong off = off_fn(vm, i * 8);
97
- tlb_fn(env, vd, i * 8, base + (off << scale), ra);
98
+ /*
99
+ * Now that we have recognized all exceptions except SyncExternal
100
+ * (from TLB_MMIO), which we cannot avoid, perform all of the stores.
101
+ *
102
+ * Note for the common case of an element in RAM, not crossing a page
103
+ * boundary, we have stored the host address in host[]. This doubles
104
+ * as a first-level check against the predicate, since only enabled
105
+ * elements have non-null host addresses.
106
+ */
107
+ i = reg_off = 0;
108
+ do {
109
+ void *h = host[i];
110
+ if (likely(h != NULL)) {
111
+ host_fn(vd, reg_off, h);
112
+ } else if ((vg[reg_off >> 6] >> (reg_off & 63)) & 1) {
113
+ target_ulong addr = base + (off_fn(vm, reg_off) << scale);
114
+ tlb_fn(env, vd, reg_off, addr, retaddr);
115
}
116
- }
117
+ i += 1;
118
+ reg_off += esize;
119
+ } while (reg_off < reg_max);
120
}
121
122
-#define DO_ST1_ZPZ_S(MEM, OFS) \
123
-void QEMU_FLATTEN HELPER(sve_st##MEM##_##OFS) \
124
- (CPUARMState *env, void *vd, void *vg, void *vm, \
125
- target_ulong base, uint32_t desc) \
126
-{ \
127
- sve_st1_zs(env, vd, vg, vm, base, desc, GETPC(), \
128
- off_##OFS##_s, sve_st1##MEM##_tlb); \
129
+#define DO_ST1_ZPZ_S(MEM, OFS, MSZ) \
130
+void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
131
+ void *vm, target_ulong base, uint32_t desc) \
132
+{ \
133
+ sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, \
134
+ off_##OFS##_s, sve_st1##MEM##_host, sve_st1##MEM##_tlb); \
135
}
136
137
-#define DO_ST1_ZPZ_D(MEM, OFS) \
138
-void QEMU_FLATTEN HELPER(sve_st##MEM##_##OFS) \
139
- (CPUARMState *env, void *vd, void *vg, void *vm, \
140
- target_ulong base, uint32_t desc) \
141
-{ \
142
- sve_st1_zd(env, vd, vg, vm, base, desc, GETPC(), \
143
- off_##OFS##_d, sve_st1##MEM##_tlb); \
144
+#define DO_ST1_ZPZ_D(MEM, OFS, MSZ) \
145
+void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
146
+ void *vm, target_ulong base, uint32_t desc) \
147
+{ \
148
+ sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, \
149
+ off_##OFS##_d, sve_st1##MEM##_host, sve_st1##MEM##_tlb); \
150
}
151
152
-DO_ST1_ZPZ_S(bs, zsu)
153
-DO_ST1_ZPZ_S(hs_le, zsu)
154
-DO_ST1_ZPZ_S(hs_be, zsu)
155
-DO_ST1_ZPZ_S(ss_le, zsu)
156
-DO_ST1_ZPZ_S(ss_be, zsu)
157
+DO_ST1_ZPZ_S(bs, zsu, MO_8)
158
+DO_ST1_ZPZ_S(hs_le, zsu, MO_16)
159
+DO_ST1_ZPZ_S(hs_be, zsu, MO_16)
160
+DO_ST1_ZPZ_S(ss_le, zsu, MO_32)
161
+DO_ST1_ZPZ_S(ss_be, zsu, MO_32)
162
163
-DO_ST1_ZPZ_S(bs, zss)
164
-DO_ST1_ZPZ_S(hs_le, zss)
165
-DO_ST1_ZPZ_S(hs_be, zss)
166
-DO_ST1_ZPZ_S(ss_le, zss)
167
-DO_ST1_ZPZ_S(ss_be, zss)
168
+DO_ST1_ZPZ_S(bs, zss, MO_8)
169
+DO_ST1_ZPZ_S(hs_le, zss, MO_16)
170
+DO_ST1_ZPZ_S(hs_be, zss, MO_16)
171
+DO_ST1_ZPZ_S(ss_le, zss, MO_32)
172
+DO_ST1_ZPZ_S(ss_be, zss, MO_32)
173
174
-DO_ST1_ZPZ_D(bd, zsu)
175
-DO_ST1_ZPZ_D(hd_le, zsu)
176
-DO_ST1_ZPZ_D(hd_be, zsu)
177
-DO_ST1_ZPZ_D(sd_le, zsu)
178
-DO_ST1_ZPZ_D(sd_be, zsu)
179
-DO_ST1_ZPZ_D(dd_le, zsu)
180
-DO_ST1_ZPZ_D(dd_be, zsu)
181
+DO_ST1_ZPZ_D(bd, zsu, MO_8)
182
+DO_ST1_ZPZ_D(hd_le, zsu, MO_16)
183
+DO_ST1_ZPZ_D(hd_be, zsu, MO_16)
184
+DO_ST1_ZPZ_D(sd_le, zsu, MO_32)
185
+DO_ST1_ZPZ_D(sd_be, zsu, MO_32)
186
+DO_ST1_ZPZ_D(dd_le, zsu, MO_64)
187
+DO_ST1_ZPZ_D(dd_be, zsu, MO_64)
188
189
-DO_ST1_ZPZ_D(bd, zss)
190
-DO_ST1_ZPZ_D(hd_le, zss)
191
-DO_ST1_ZPZ_D(hd_be, zss)
192
-DO_ST1_ZPZ_D(sd_le, zss)
193
-DO_ST1_ZPZ_D(sd_be, zss)
194
-DO_ST1_ZPZ_D(dd_le, zss)
195
-DO_ST1_ZPZ_D(dd_be, zss)
196
+DO_ST1_ZPZ_D(bd, zss, MO_8)
197
+DO_ST1_ZPZ_D(hd_le, zss, MO_16)
198
+DO_ST1_ZPZ_D(hd_be, zss, MO_16)
199
+DO_ST1_ZPZ_D(sd_le, zss, MO_32)
200
+DO_ST1_ZPZ_D(sd_be, zss, MO_32)
201
+DO_ST1_ZPZ_D(dd_le, zss, MO_64)
202
+DO_ST1_ZPZ_D(dd_be, zss, MO_64)
203
204
-DO_ST1_ZPZ_D(bd, zd)
205
-DO_ST1_ZPZ_D(hd_le, zd)
206
-DO_ST1_ZPZ_D(hd_be, zd)
207
-DO_ST1_ZPZ_D(sd_le, zd)
208
-DO_ST1_ZPZ_D(sd_be, zd)
209
-DO_ST1_ZPZ_D(dd_le, zd)
210
-DO_ST1_ZPZ_D(dd_be, zd)
211
+DO_ST1_ZPZ_D(bd, zd, MO_8)
212
+DO_ST1_ZPZ_D(hd_le, zd, MO_16)
213
+DO_ST1_ZPZ_D(hd_be, zd, MO_16)
214
+DO_ST1_ZPZ_D(sd_le, zd, MO_32)
215
+DO_ST1_ZPZ_D(sd_be, zd, MO_32)
216
+DO_ST1_ZPZ_D(dd_le, zd, MO_64)
217
+DO_ST1_ZPZ_D(dd_be, zd, MO_64)
218
219
#undef DO_ST1_ZPZ_S
220
#undef DO_ST1_ZPZ_D
221
--
222
2.20.1
223
224
diff view generated by jsdifflib
[PULL 25/34] target/arm: Reuse sve_probe_page for gather loads
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200508154359.7494-19-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/sve_helper.c | 208 +++++++++++++++++++++-------------------
9
1 file changed, 109 insertions(+), 99 deletions(-)
10
11
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/sve_helper.c
14
+++ b/target/arm/sve_helper.c
15
@@ -XXX,XX +XXX,XX @@ static target_ulong off_zd_d(void *reg, intptr_t reg_ofs)
16
return *(uint64_t *)(reg + reg_ofs);
17
}
18
19
-static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
20
- target_ulong base, uint32_t desc, uintptr_t ra,
21
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
22
+static inline QEMU_ALWAYS_INLINE
23
+void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
24
+ target_ulong base, uint32_t desc, uintptr_t retaddr,
25
+ int esize, int msize, zreg_off_fn *off_fn,
26
+ sve_ldst1_host_fn *host_fn,
27
+ sve_ldst1_tlb_fn *tlb_fn)
28
{
29
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
30
- intptr_t i, oprsz = simd_oprsz(desc);
31
- ARMVectorReg scratch = { };
32
+ const int mmu_idx = cpu_mmu_index(env, false);
33
+ const intptr_t reg_max = simd_oprsz(desc);
34
+ ARMVectorReg scratch;
35
+ intptr_t reg_off;
36
+ SVEHostPage info, info2;
37
38
- for (i = 0; i < oprsz; ) {
39
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
40
+ memset(&scratch, 0, reg_max);
41
+ reg_off = 0;
42
+ do {
43
+ uint64_t pg = vg[reg_off >> 6];
44
do {
45
if (likely(pg & 1)) {
46
- target_ulong off = off_fn(vm, i);
47
- tlb_fn(env, &scratch, i, base + (off << scale), ra);
48
+ target_ulong addr = base + (off_fn(vm, reg_off) << scale);
49
+ target_ulong in_page = -(addr | TARGET_PAGE_MASK);
50
+
51
+ sve_probe_page(&info, false, env, addr, 0, MMU_DATA_LOAD,
52
+ mmu_idx, retaddr);
53
+
54
+ if (likely(in_page >= msize)) {
55
+ if (unlikely(info.flags & TLB_WATCHPOINT)) {
56
+ cpu_check_watchpoint(env_cpu(env), addr, msize,
57
+ info.attrs, BP_MEM_READ, retaddr);
58
+ }
59
+ /* TODO: MTE check */
60
+ host_fn(&scratch, reg_off, info.host);
61
+ } else {
62
+ /* Element crosses the page boundary. */
63
+ sve_probe_page(&info2, false, env, addr + in_page, 0,
64
+ MMU_DATA_LOAD, mmu_idx, retaddr);
65
+ if (unlikely((info.flags | info2.flags) & TLB_WATCHPOINT)) {
66
+ cpu_check_watchpoint(env_cpu(env), addr,
67
+ msize, info.attrs,
68
+ BP_MEM_READ, retaddr);
69
+ }
70
+ /* TODO: MTE check */
71
+ tlb_fn(env, &scratch, reg_off, addr, retaddr);
72
+ }
73
}
74
- i += 4, pg >>= 4;
75
- } while (i & 15);
76
- }
77
+ reg_off += esize;
78
+ pg >>= esize;
79
+ } while (reg_off & 63);
80
+ } while (reg_off < reg_max);
81
82
/* Wait until all exceptions have been raised to write back. */
83
- memcpy(vd, &scratch, oprsz);
84
+ memcpy(vd, &scratch, reg_max);
85
}
86
87
-static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
88
- target_ulong base, uint32_t desc, uintptr_t ra,
89
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
90
-{
91
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
92
- intptr_t i, oprsz = simd_oprsz(desc) / 8;
93
- ARMVectorReg scratch = { };
94
-
95
- for (i = 0; i < oprsz; i++) {
96
- uint8_t pg = *(uint8_t *)(vg + H1(i));
97
- if (likely(pg & 1)) {
98
- target_ulong off = off_fn(vm, i * 8);
99
- tlb_fn(env, &scratch, i * 8, base + (off << scale), ra);
100
- }
101
- }
102
-
103
- /* Wait until all exceptions have been raised to write back. */
104
- memcpy(vd, &scratch, oprsz * 8);
105
+#define DO_LD1_ZPZ_S(MEM, OFS, MSZ) \
106
+void HELPER(sve_ld##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
107
+ void *vm, target_ulong base, uint32_t desc) \
108
+{ \
109
+ sve_ld1_z(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, \
110
+ off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
111
}
112
113
-#define DO_LD1_ZPZ_S(MEM, OFS) \
114
-void QEMU_FLATTEN HELPER(sve_ld##MEM##_##OFS) \
115
- (CPUARMState *env, void *vd, void *vg, void *vm, \
116
- target_ulong base, uint32_t desc) \
117
-{ \
118
- sve_ld1_zs(env, vd, vg, vm, base, desc, GETPC(), \
119
- off_##OFS##_s, sve_ld1##MEM##_tlb); \
120
+#define DO_LD1_ZPZ_D(MEM, OFS, MSZ) \
121
+void HELPER(sve_ld##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
122
+ void *vm, target_ulong base, uint32_t desc) \
123
+{ \
124
+ sve_ld1_z(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, \
125
+ off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
126
}
127
128
-#define DO_LD1_ZPZ_D(MEM, OFS) \
129
-void QEMU_FLATTEN HELPER(sve_ld##MEM##_##OFS) \
130
- (CPUARMState *env, void *vd, void *vg, void *vm, \
131
- target_ulong base, uint32_t desc) \
132
-{ \
133
- sve_ld1_zd(env, vd, vg, vm, base, desc, GETPC(), \
134
- off_##OFS##_d, sve_ld1##MEM##_tlb); \
135
-}
136
+DO_LD1_ZPZ_S(bsu, zsu, MO_8)
137
+DO_LD1_ZPZ_S(bsu, zss, MO_8)
138
+DO_LD1_ZPZ_D(bdu, zsu, MO_8)
139
+DO_LD1_ZPZ_D(bdu, zss, MO_8)
140
+DO_LD1_ZPZ_D(bdu, zd, MO_8)
141
142
-DO_LD1_ZPZ_S(bsu, zsu)
143
-DO_LD1_ZPZ_S(bsu, zss)
144
-DO_LD1_ZPZ_D(bdu, zsu)
145
-DO_LD1_ZPZ_D(bdu, zss)
146
-DO_LD1_ZPZ_D(bdu, zd)
147
+DO_LD1_ZPZ_S(bss, zsu, MO_8)
148
+DO_LD1_ZPZ_S(bss, zss, MO_8)
149
+DO_LD1_ZPZ_D(bds, zsu, MO_8)
150
+DO_LD1_ZPZ_D(bds, zss, MO_8)
151
+DO_LD1_ZPZ_D(bds, zd, MO_8)
152
153
-DO_LD1_ZPZ_S(bss, zsu)
154
-DO_LD1_ZPZ_S(bss, zss)
155
-DO_LD1_ZPZ_D(bds, zsu)
156
-DO_LD1_ZPZ_D(bds, zss)
157
-DO_LD1_ZPZ_D(bds, zd)
158
+DO_LD1_ZPZ_S(hsu_le, zsu, MO_16)
159
+DO_LD1_ZPZ_S(hsu_le, zss, MO_16)
160
+DO_LD1_ZPZ_D(hdu_le, zsu, MO_16)
161
+DO_LD1_ZPZ_D(hdu_le, zss, MO_16)
162
+DO_LD1_ZPZ_D(hdu_le, zd, MO_16)
163
164
-DO_LD1_ZPZ_S(hsu_le, zsu)
165
-DO_LD1_ZPZ_S(hsu_le, zss)
166
-DO_LD1_ZPZ_D(hdu_le, zsu)
167
-DO_LD1_ZPZ_D(hdu_le, zss)
168
-DO_LD1_ZPZ_D(hdu_le, zd)
169
+DO_LD1_ZPZ_S(hsu_be, zsu, MO_16)
170
+DO_LD1_ZPZ_S(hsu_be, zss, MO_16)
171
+DO_LD1_ZPZ_D(hdu_be, zsu, MO_16)
172
+DO_LD1_ZPZ_D(hdu_be, zss, MO_16)
173
+DO_LD1_ZPZ_D(hdu_be, zd, MO_16)
174
175
-DO_LD1_ZPZ_S(hsu_be, zsu)
176
-DO_LD1_ZPZ_S(hsu_be, zss)
177
-DO_LD1_ZPZ_D(hdu_be, zsu)
178
-DO_LD1_ZPZ_D(hdu_be, zss)
179
-DO_LD1_ZPZ_D(hdu_be, zd)
180
+DO_LD1_ZPZ_S(hss_le, zsu, MO_16)
181
+DO_LD1_ZPZ_S(hss_le, zss, MO_16)
182
+DO_LD1_ZPZ_D(hds_le, zsu, MO_16)
183
+DO_LD1_ZPZ_D(hds_le, zss, MO_16)
184
+DO_LD1_ZPZ_D(hds_le, zd, MO_16)
185
186
-DO_LD1_ZPZ_S(hss_le, zsu)
187
-DO_LD1_ZPZ_S(hss_le, zss)
188
-DO_LD1_ZPZ_D(hds_le, zsu)
189
-DO_LD1_ZPZ_D(hds_le, zss)
190
-DO_LD1_ZPZ_D(hds_le, zd)
191
+DO_LD1_ZPZ_S(hss_be, zsu, MO_16)
192
+DO_LD1_ZPZ_S(hss_be, zss, MO_16)
193
+DO_LD1_ZPZ_D(hds_be, zsu, MO_16)
194
+DO_LD1_ZPZ_D(hds_be, zss, MO_16)
195
+DO_LD1_ZPZ_D(hds_be, zd, MO_16)
196
197
-DO_LD1_ZPZ_S(hss_be, zsu)
198
-DO_LD1_ZPZ_S(hss_be, zss)
199
-DO_LD1_ZPZ_D(hds_be, zsu)
200
-DO_LD1_ZPZ_D(hds_be, zss)
201
-DO_LD1_ZPZ_D(hds_be, zd)
202
+DO_LD1_ZPZ_S(ss_le, zsu, MO_32)
203
+DO_LD1_ZPZ_S(ss_le, zss, MO_32)
204
+DO_LD1_ZPZ_D(sdu_le, zsu, MO_32)
205
+DO_LD1_ZPZ_D(sdu_le, zss, MO_32)
206
+DO_LD1_ZPZ_D(sdu_le, zd, MO_32)
207
208
-DO_LD1_ZPZ_S(ss_le, zsu)
209
-DO_LD1_ZPZ_S(ss_le, zss)
210
-DO_LD1_ZPZ_D(sdu_le, zsu)
211
-DO_LD1_ZPZ_D(sdu_le, zss)
212
-DO_LD1_ZPZ_D(sdu_le, zd)
213
+DO_LD1_ZPZ_S(ss_be, zsu, MO_32)
214
+DO_LD1_ZPZ_S(ss_be, zss, MO_32)
215
+DO_LD1_ZPZ_D(sdu_be, zsu, MO_32)
216
+DO_LD1_ZPZ_D(sdu_be, zss, MO_32)
217
+DO_LD1_ZPZ_D(sdu_be, zd, MO_32)
218
219
-DO_LD1_ZPZ_S(ss_be, zsu)
220
-DO_LD1_ZPZ_S(ss_be, zss)
221
-DO_LD1_ZPZ_D(sdu_be, zsu)
222
-DO_LD1_ZPZ_D(sdu_be, zss)
223
-DO_LD1_ZPZ_D(sdu_be, zd)
224
+DO_LD1_ZPZ_D(sds_le, zsu, MO_32)
225
+DO_LD1_ZPZ_D(sds_le, zss, MO_32)
226
+DO_LD1_ZPZ_D(sds_le, zd, MO_32)
227
228
-DO_LD1_ZPZ_D(sds_le, zsu)
229
-DO_LD1_ZPZ_D(sds_le, zss)
230
-DO_LD1_ZPZ_D(sds_le, zd)
231
+DO_LD1_ZPZ_D(sds_be, zsu, MO_32)
232
+DO_LD1_ZPZ_D(sds_be, zss, MO_32)
233
+DO_LD1_ZPZ_D(sds_be, zd, MO_32)
234
235
-DO_LD1_ZPZ_D(sds_be, zsu)
236
-DO_LD1_ZPZ_D(sds_be, zss)
237
-DO_LD1_ZPZ_D(sds_be, zd)
238
+DO_LD1_ZPZ_D(dd_le, zsu, MO_64)
239
+DO_LD1_ZPZ_D(dd_le, zss, MO_64)
240
+DO_LD1_ZPZ_D(dd_le, zd, MO_64)
241
242
-DO_LD1_ZPZ_D(dd_le, zsu)
243
-DO_LD1_ZPZ_D(dd_le, zss)
244
-DO_LD1_ZPZ_D(dd_le, zd)
245
-
246
-DO_LD1_ZPZ_D(dd_be, zsu)
247
-DO_LD1_ZPZ_D(dd_be, zss)
248
-DO_LD1_ZPZ_D(dd_be, zd)
249
+DO_LD1_ZPZ_D(dd_be, zsu, MO_64)
250
+DO_LD1_ZPZ_D(dd_be, zss, MO_64)
251
+DO_LD1_ZPZ_D(dd_be, zd, MO_64)
252
253
#undef DO_LD1_ZPZ_S
254
#undef DO_LD1_ZPZ_D
255
--
256
2.20.1
257
258
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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