1
The following changes since commit c88f1ffc19e38008a1c33ae039482a860aa7418c:
1
Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx
2
ethernet device failed 'make check' on big-endian hosts.
2
3
3
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2020-05-08 14:29:18 +0100)
4
-- PMM
5
6
The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:
7
8
Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000)
4
9
5
are available in the Git repository at:
10
are available in the Git repository at:
6
11
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200511
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1
8
13
9
for you to fetch changes up to 7e17d50ebd359ee5fa3d65d7fdc0fe0336d60694:
14
for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621:
10
15
11
target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed) (2020-05-11 14:22:54 +0100)
16
target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000)
12
17
13
----------------------------------------------------------------
18
----------------------------------------------------------------
14
target-arm queue:
19
target-arm queue:
15
aspeed: Add boot stub for smp booting
20
* Correctly initialize MDCR_EL2.HPMN
16
target/arm: Drop access_el3_aa32ns_aa64any()
21
* versal: Use nr_apu_cpus in favor of hard coding 2
17
aspeed: Support AST2600A1 silicon revision
22
* accel/tcg: Add URL of clang bug to comment about our workaround
18
aspeed: sdmc: Implement AST2600 locking behaviour
23
* Add support for FEAT_DIT, Data Independent Timing
19
nrf51: Tracing cleanups
24
* Remove GPIO from unimplemented NPCM7XX
20
target/arm: Improve handling of SVE loads and stores
25
* Fix SCR RES1 handling
21
target/arm: Don't show TCG-only CPUs in KVM-only QEMU builds
26
* Don't migrate CPUARMState.features
22
hw/arm/musicpal: Map the UART devices unconditionally
23
target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)
24
target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
25
27
26
----------------------------------------------------------------
28
----------------------------------------------------------------
29
Aaron Lindsay (1):
30
target/arm: Don't migrate CPUARMState.features
31
32
Daniel Müller (1):
33
target/arm: Correctly initialize MDCR_EL2.HPMN
34
27
Edgar E. Iglesias (1):
35
Edgar E. Iglesias (1):
28
target/arm: Drop access_el3_aa32ns_aa64any()
36
hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
29
37
30
Joel Stanley (3):
38
Hao Wu (1):
31
aspeed: Add boot stub for smp booting
39
hw/arm: Remove GPIO from unimplemented NPCM7XX
32
aspeed: Support AST2600A1 silicon revision
33
aspeed: sdmc: Implement AST2600 locking behaviour
34
40
35
Philippe Mathieu-Daudé (8):
41
Mike Nawrocki (1):
36
hw/arm/nrf51: Add NRF51_PERIPHERAL_SIZE definition
42
target/arm: Fix SCR RES1 handling
37
hw/timer/nrf51_timer: Display timer ID in trace events
38
hw/timer/nrf51_timer: Add trace event of counter value update
39
target/arm/kvm: Inline set_feature() calls
40
target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]
41
target/arm/cpu: Restrict v8M IDAU interface to Aarch32 CPUs
42
target/arm: Restrict TCG cpus to TCG accel
43
hw/arm/musicpal: Map the UART devices unconditionally
44
43
45
Richard Henderson (21):
44
Peter Maydell (2):
46
exec: Add block comments for watchpoint routines
45
arm: Update infocenter.arm.com URLs
47
exec: Fix cpu_watchpoint_address_matches address length
46
accel/tcg: Add URL of clang bug to comment about our workaround
48
accel/tcg: Add block comment for probe_access
49
accel/tcg: Adjust probe_access call to page_check_range
50
accel/tcg: Add probe_access_flags
51
accel/tcg: Add endian-specific cpu_{ld, st}* operations
52
target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn
53
target/arm: Drop manual handling of set/clear_helper_retaddr
54
target/arm: Add sve infrastructure for page lookup
55
target/arm: Adjust interface of sve_ld1_host_fn
56
target/arm: Use SVEContLdSt in sve_ld1_r
57
target/arm: Handle watchpoints in sve_ld1_r
58
target/arm: Use SVEContLdSt for multi-register contiguous loads
59
target/arm: Update contiguous first-fault and no-fault loads
60
target/arm: Use SVEContLdSt for contiguous stores
61
target/arm: Reuse sve_probe_page for gather first-fault loads
62
target/arm: Reuse sve_probe_page for scatter stores
63
target/arm: Reuse sve_probe_page for gather loads
64
target/arm: Remove sve_memopidx
65
target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
66
target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)
67
47
68
Thomas Huth (1):
48
Rebecca Cran (4):
69
target/arm: Make set_feature() available for other files
49
target/arm: Add support for FEAT_DIT, Data Independent Timing
50
target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
51
target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
52
target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
70
53
71
docs/devel/loads-stores.rst | 39 +-
54
include/hw/dma/pl080.h | 7 ++--
72
include/exec/cpu-all.h | 13 +-
55
include/hw/misc/arm_integrator_debug.h | 2 +-
73
include/exec/cpu_ldst.h | 283 +++--
56
include/hw/ssi/pl022.h | 5 ++-
74
include/exec/exec-all.h | 39 +
57
target/arm/cpu.h | 17 ++++++++
75
include/hw/arm/nrf51.h | 3 +-
58
target/arm/internals.h | 6 +++
76
include/hw/core/cpu.h | 23 +
59
accel/tcg/cpu-exec.c | 25 +++++++++---
77
include/hw/i2c/microbit_i2c.h | 2 +-
60
hw/arm/aspeed_ast2600.c | 2 +-
78
include/hw/misc/aspeed_scu.h | 1 +
61
hw/arm/musca.c | 4 +-
79
include/hw/timer/nrf51_timer.h | 1 +
62
hw/arm/npcm7xx.c | 8 ----
80
target/arm/cpu.h | 10 +
63
hw/arm/xlnx-versal.c | 4 +-
81
target/arm/helper-sve.h | 45 +-
64
hw/misc/arm_integrator_debug.c | 2 +-
82
target/arm/internals.h | 5 -
65
hw/timer/arm_timer.c | 7 ++--
83
accel/tcg/cputlb.c | 413 ++++---
66
target/arm/cpu.c | 4 ++
84
accel/tcg/user-exec.c | 256 ++++-
67
target/arm/cpu64.c | 5 +++
85
exec.c | 2 +-
68
target/arm/helper-a64.c | 27 +++++++++++--
86
hw/arm/aspeed.c | 73 +-
69
target/arm/helper.c | 71 +++++++++++++++++++++++++++-------
87
hw/arm/aspeed_ast2600.c | 6 +-
70
target/arm/machine.c | 2 +-
88
hw/arm/musicpal.c | 12 +-
71
target/arm/op_helper.c | 9 +----
89
hw/arm/nrf51_soc.c | 9 +-
72
target/arm/translate-a64.c | 12 ++++++
90
hw/i2c/microbit_i2c.c | 2 +-
73
19 files changed, 164 insertions(+), 55 deletions(-)
91
hw/misc/aspeed_scu.c | 11 +-
92
hw/misc/aspeed_sdmc.c | 55 +-
93
hw/timer/nrf51_timer.c | 14 +-
94
target/arm/cpu.c | 662 +----------
95
target/arm/cpu64.c | 18 +-
96
target/arm/cpu_tcg.c | 664 +++++++++++
97
target/arm/helper.c | 30 +-
98
target/arm/kvm32.c | 13 +-
99
target/arm/kvm64.c | 22 +-
100
target/arm/sve_helper.c | 2398 +++++++++++++++++++++-------------------
101
target/arm/translate-sve.c | 93 +-
102
hw/timer/trace-events | 5 +-
103
target/arm/Makefile.objs | 1 +
104
33 files changed, 2975 insertions(+), 2248 deletions(-)
105
create mode 100644 target/arm/cpu_tcg.c
106
74
diff view generated by jsdifflib
Deleted patch
1
From: Joel Stanley <joel@jms.id.au>
2
1
3
This is a boot stub that is similar to the code u-boot runs, allowing
4
the kernel to boot the secondary CPU.
5
6
u-boot works as follows:
7
8
1. Initialises the SMP mailbox area in the SCU at 0x1e6e2180 with default values
9
10
2. Copies a stub named 'mailbox_insn' from flash to the SCU, just above the
11
mailbox area
12
13
3. Sets AST_SMP_MBOX_FIELD_READY to a magic value to indicate the
14
secondary can begin execution from the stub
15
16
4. The stub waits until the AST_SMP_MBOX_FIELD_GOSIGN register is set to
17
a magic value
18
19
5. Jumps to the address in AST_SMP_MBOX_FIELD_ENTRY, starting Linux
20
21
Linux indicates it is ready by writing the address of its entrypoint
22
function to AST_SMP_MBOX_FIELD_ENTRY and the 'go' magic number to
23
AST_SMP_MBOX_FIELD_GOSIGN. The secondary CPU sees this at step 4 and
24
breaks out of it's loop.
25
26
To be compatible, a fixed qemu stub is loaded into the mailbox area. As
27
qemu can ensure the stub is loaded before execution starts, we do not
28
need to emulate the AST_SMP_MBOX_FIELD_READY behaviour of u-boot. The
29
secondary CPU's program counter points to the beginning of the stub,
30
allowing qemu to start secondaries at step four.
31
32
Reboot behaviour is preserved by resetting AST_SMP_MBOX_FIELD_GOSIGN
33
when the secondaries are reset.
34
35
This is only configured when the system is booted with -kernel and qemu
36
does not execute u-boot first.
37
38
Reviewed-by: Cédric Le Goater <clg@kaod.org>
39
Tested-by: Cédric Le Goater <clg@kaod.org>
40
Signed-off-by: Joel Stanley <joel@jms.id.au>
41
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
42
---
43
hw/arm/aspeed.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++++
44
1 file changed, 65 insertions(+)
45
46
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/aspeed.c
49
+++ b/hw/arm/aspeed.c
50
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps max_ram_ops = {
51
.endianness = DEVICE_NATIVE_ENDIAN,
52
};
53
54
+#define AST_SMP_MAILBOX_BASE 0x1e6e2180
55
+#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
56
+#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
57
+#define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
58
+#define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
59
+#define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
60
+#define AST_SMP_MBOX_GOSIGN 0xabbaab00
61
+
62
+static void aspeed_write_smpboot(ARMCPU *cpu,
63
+ const struct arm_boot_info *info)
64
+{
65
+ static const uint32_t poll_mailbox_ready[] = {
66
+ /*
67
+ * r2 = per-cpu go sign value
68
+ * r1 = AST_SMP_MBOX_FIELD_ENTRY
69
+ * r0 = AST_SMP_MBOX_FIELD_GOSIGN
70
+ */
71
+ 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
72
+ 0xe21000ff, /* ands r0, r0, #255 */
73
+ 0xe59f201c, /* ldr r2, [pc, #28] */
74
+ 0xe1822000, /* orr r2, r2, r0 */
75
+
76
+ 0xe59f1018, /* ldr r1, [pc, #24] */
77
+ 0xe59f0018, /* ldr r0, [pc, #24] */
78
+
79
+ 0xe320f002, /* wfe */
80
+ 0xe5904000, /* ldr r4, [r0] */
81
+ 0xe1520004, /* cmp r2, r4 */
82
+ 0x1afffffb, /* bne <wfe> */
83
+ 0xe591f000, /* ldr pc, [r1] */
84
+ AST_SMP_MBOX_GOSIGN,
85
+ AST_SMP_MBOX_FIELD_ENTRY,
86
+ AST_SMP_MBOX_FIELD_GOSIGN,
87
+ };
88
+
89
+ rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
90
+ sizeof(poll_mailbox_ready),
91
+ info->smp_loader_start);
92
+}
93
+
94
+static void aspeed_reset_secondary(ARMCPU *cpu,
95
+ const struct arm_boot_info *info)
96
+{
97
+ AddressSpace *as = arm_boot_address_space(cpu, info);
98
+ CPUState *cs = CPU(cpu);
99
+
100
+ /* info->smp_bootreg_addr */
101
+ address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
102
+ MEMTXATTRS_UNSPECIFIED, NULL);
103
+ cpu_set_pc(cs, info->smp_loader_start);
104
+}
105
+
106
#define FIRMWARE_ADDR 0x0
107
108
static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
109
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
110
}
111
}
112
113
+ if (machine->kernel_filename && bmc->soc.num_cpus > 1) {
114
+ /* With no u-boot we must set up a boot stub for the secondary CPU */
115
+ MemoryRegion *smpboot = g_new(MemoryRegion, 1);
116
+ memory_region_init_ram(smpboot, OBJECT(bmc), "aspeed.smpboot",
117
+ 0x80, &error_abort);
118
+ memory_region_add_subregion(get_system_memory(),
119
+ AST_SMP_MAILBOX_BASE, smpboot);
120
+
121
+ aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
122
+ aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
123
+ aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
124
+ }
125
+
126
aspeed_board_binfo.ram_size = ram_size;
127
aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM];
128
aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus;
129
--
130
2.20.1
131
132
diff view generated by jsdifflib
Deleted patch
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
2
1
3
Calling access_el3_aa32ns() works for AArch32 only cores
4
but it does not handle 32-bit EL2 on top of 64-bit EL3
5
for mixed 32/64-bit cores.
6
7
Merge access_el3_aa32ns_aa64any() into access_el3_aa32ns()
8
and only use the latter.
9
10
Fixes: 68e9c2fe65 ("target-arm: Add VTCR_EL2")
11
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
12
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
13
Message-id: 20200505141729.31930-2-edgar.iglesias@gmail.com
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/helper.c | 30 +++++++-----------------------
18
1 file changed, 7 insertions(+), 23 deletions(-)
19
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper.c
23
+++ b/target/arm/helper.c
24
@@ -XXX,XX +XXX,XX @@ void init_cpreg_list(ARMCPU *cpu)
25
}
26
27
/*
28
- * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
29
- * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
30
- *
31
- * access_el3_aa32ns: Used to check AArch32 register views.
32
- * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
33
+ * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
34
*/
35
static CPAccessResult access_el3_aa32ns(CPUARMState *env,
36
const ARMCPRegInfo *ri,
37
bool isread)
38
{
39
- bool secure = arm_is_secure_below_el3(env);
40
-
41
- assert(!arm_el_is_aa64(env, 3));
42
- if (secure) {
43
+ if (!is_a64(env) && arm_current_el(env) == 3 &&
44
+ arm_is_secure_below_el3(env)) {
45
return CP_ACCESS_TRAP_UNCATEGORIZED;
46
}
47
return CP_ACCESS_OK;
48
}
49
50
-static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
51
- const ARMCPRegInfo *ri,
52
- bool isread)
53
-{
54
- if (!arm_el_is_aa64(env, 3)) {
55
- return access_el3_aa32ns(env, ri, isread);
56
- }
57
- return CP_ACCESS_OK;
58
-}
59
-
60
/* Some secure-only AArch32 registers trap to EL3 if used from
61
* Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
62
* Note that an access from Secure EL1 can only happen if EL3 is AArch64.
63
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
64
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
65
{ .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
66
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
67
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
68
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
69
.type = ARM_CP_CONST, .resetvalue = 0 },
70
{ .name = "VTTBR", .state = ARM_CP_STATE_AA32,
71
.cp = 15, .opc1 = 6, .crm = 2,
72
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
73
.type = ARM_CP_CONST, .resetvalue = 0 },
74
{ .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
75
.opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
76
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
77
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
78
.type = ARM_CP_CONST, .resetvalue = 0 },
79
{ .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
80
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
81
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
82
ARMCPRegInfo vpidr_regs[] = {
83
{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
84
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
85
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
86
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
87
.type = ARM_CP_CONST, .resetvalue = cpu->midr,
88
.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
89
{ .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
90
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
91
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
92
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
93
.type = ARM_CP_NO_RAW,
94
.writefn = arm_cp_write_ignore, .readfn = mpidr_read },
95
REGINFO_SENTINEL
96
--
97
2.20.1
98
99
diff view generated by jsdifflib
Deleted patch
1
From: Joel Stanley <joel@jms.id.au>
2
1
3
There are minimal differences from Qemu's point of view between the A0
4
and A1 silicon revisions.
5
6
As the A1 exercises different code paths in u-boot it is desirable to
7
emulate that instead.
8
9
Signed-off-by: Joel Stanley <joel@jms.id.au>
10
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
11
Reviewed-by: Cédric Le Goater <clg@kaod.org>
12
Message-id: 20200504093703.261135-1-joel@jms.id.au
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
include/hw/misc/aspeed_scu.h | 1 +
16
hw/arm/aspeed.c | 8 ++++----
17
hw/arm/aspeed_ast2600.c | 6 +++---
18
hw/misc/aspeed_scu.c | 11 +++++------
19
4 files changed, 13 insertions(+), 13 deletions(-)
20
21
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/misc/aspeed_scu.h
24
+++ b/include/hw/misc/aspeed_scu.h
25
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSCUState {
26
#define AST2500_A0_SILICON_REV 0x04000303U
27
#define AST2500_A1_SILICON_REV 0x04010303U
28
#define AST2600_A0_SILICON_REV 0x05000303U
29
+#define AST2600_A1_SILICON_REV 0x05010303U
30
31
#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
32
33
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/arm/aspeed.c
36
+++ b/hw/arm/aspeed.c
37
@@ -XXX,XX +XXX,XX @@ struct AspeedBoardState {
38
39
/* Tacoma hardware value */
40
#define TACOMA_BMC_HW_STRAP1 0x00000000
41
-#define TACOMA_BMC_HW_STRAP2 0x00000000
42
+#define TACOMA_BMC_HW_STRAP2 0x00000040
43
44
/*
45
* The max ram region is for firmwares that scan the address space
46
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
47
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
48
49
mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
50
- amc->soc_name = "ast2600-a0";
51
+ amc->soc_name = "ast2600-a1";
52
amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
53
amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
54
amc->fmc_model = "w25q512jv";
55
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
56
MachineClass *mc = MACHINE_CLASS(oc);
57
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
58
59
- mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
60
- amc->soc_name = "ast2600-a0";
61
+ mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)";
62
+ amc->soc_name = "ast2600-a1";
63
amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
64
amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
65
amc->fmc_model = "mx66l1g45g";
66
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/hw/arm/aspeed_ast2600.c
69
+++ b/hw/arm/aspeed_ast2600.c
70
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
71
72
dc->realize = aspeed_soc_ast2600_realize;
73
74
- sc->name = "ast2600-a0";
75
+ sc->name = "ast2600-a1";
76
sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
77
- sc->silicon_rev = AST2600_A0_SILICON_REV;
78
+ sc->silicon_rev = AST2600_A1_SILICON_REV;
79
sc->sram_size = 0x10000;
80
sc->spis_num = 2;
81
sc->ehcis_num = 2;
82
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
83
}
84
85
static const TypeInfo aspeed_soc_ast2600_type_info = {
86
- .name = "ast2600-a0",
87
+ .name = "ast2600-a1",
88
.parent = TYPE_ASPEED_SOC,
89
.instance_size = sizeof(AspeedSoCState),
90
.instance_init = aspeed_soc_ast2600_init,
91
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/hw/misc/aspeed_scu.c
94
+++ b/hw/misc/aspeed_scu.c
95
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_silicon_revs[] = {
96
AST2500_A0_SILICON_REV,
97
AST2500_A1_SILICON_REV,
98
AST2600_A0_SILICON_REV,
99
+ AST2600_A1_SILICON_REV,
100
};
101
102
bool is_supported_silicon_rev(uint32_t silicon_rev)
103
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = {
104
.valid.unaligned = false,
105
};
106
107
-static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = {
108
- [AST2600_SILICON_REV] = AST2600_SILICON_REV,
109
- [AST2600_SILICON_REV2] = AST2600_SILICON_REV,
110
- [AST2600_SYS_RST_CTRL] = 0xF7CFFEDC | 0x100,
111
+static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = {
112
+ [AST2600_SYS_RST_CTRL] = 0xF7C3FED8,
113
[AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC,
114
- [AST2600_CLK_STOP_CTRL] = 0xEFF43E8B,
115
+ [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A,
116
[AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0,
117
[AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */
118
[AST2600_HPLL_PARAM] = 0x1000405F,
119
@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data)
120
121
dc->desc = "ASPEED 2600 System Control Unit";
122
dc->reset = aspeed_ast2600_scu_reset;
123
- asc->resets = ast2600_a0_resets;
124
+ asc->resets = ast2600_a1_resets;
125
asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */
126
asc->apb_divider = 4;
127
asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
128
--
129
2.20.1
130
131
diff view generated by jsdifflib
Deleted patch
1
From: Joel Stanley <joel@jms.id.au>
2
1
3
The AST2600 handles this differently with the extra 'hardlock' state, so
4
move the testing to the soc specific class' write callback.
5
6
Signed-off-by: Joel Stanley <joel@jms.id.au>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 20200505090136.341426-1-joel@jms.id.au
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/misc/aspeed_sdmc.c | 55 +++++++++++++++++++++++++++++++++++--------
12
1 file changed, 45 insertions(+), 10 deletions(-)
13
14
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/misc/aspeed_sdmc.c
17
+++ b/hw/misc/aspeed_sdmc.c
18
@@ -XXX,XX +XXX,XX @@
19
20
/* Protection Key Register */
21
#define R_PROT (0x00 / 4)
22
+#define PROT_UNLOCKED 0x01
23
+#define PROT_HARDLOCKED 0x10 /* AST2600 */
24
+#define PROT_SOFTLOCKED 0x00
25
+
26
#define PROT_KEY_UNLOCK 0xFC600309
27
+#define PROT_KEY_HARDLOCK 0xDEADDEAD /* AST2600 */
28
29
/* Configuration Register */
30
#define R_CONF (0x04 / 4)
31
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
32
return;
33
}
34
35
- if (addr == R_PROT) {
36
- s->regs[addr] = (data == PROT_KEY_UNLOCK) ? 1 : 0;
37
- return;
38
- }
39
-
40
- if (!s->regs[R_PROT]) {
41
- qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
42
- return;
43
- }
44
-
45
asc->write(s, addr, data);
46
}
47
48
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
49
static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg,
50
uint32_t data)
51
{
52
+ if (reg == R_PROT) {
53
+ s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
54
+ return;
55
+ }
56
+
57
+ if (!s->regs[R_PROT]) {
58
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
59
+ return;
60
+ }
61
+
62
switch (reg) {
63
case R_CONF:
64
data = aspeed_2400_sdmc_compute_conf(s, data);
65
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
66
static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg,
67
uint32_t data)
68
{
69
+ if (reg == R_PROT) {
70
+ s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
71
+ return;
72
+ }
73
+
74
+ if (!s->regs[R_PROT]) {
75
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
76
+ return;
77
+ }
78
+
79
switch (reg) {
80
case R_CONF:
81
data = aspeed_2500_sdmc_compute_conf(s, data);
82
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
83
static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,
84
uint32_t data)
85
{
86
+ if (s->regs[R_PROT] == PROT_HARDLOCKED) {
87
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n",
88
+ __func__);
89
+ return;
90
+ }
91
+
92
+ if (reg != R_PROT && s->regs[R_PROT] == PROT_SOFTLOCKED) {
93
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
94
+ return;
95
+ }
96
+
97
switch (reg) {
98
+ case R_PROT:
99
+ if (data == PROT_KEY_UNLOCK) {
100
+ data = PROT_UNLOCKED;
101
+ } else if (data == PROT_KEY_HARDLOCK) {
102
+ data = PROT_HARDLOCKED;
103
+ } else {
104
+ data = PROT_SOFTLOCKED;
105
+ }
106
+ break;
107
case R_CONF:
108
data = aspeed_2600_sdmc_compute_conf(s, data);
109
break;
110
--
111
2.20.1
112
113
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
On the NRF51 series, all peripherals have a fixed I/O size
4
of 4KiB. Define NRF51_PERIPHERAL_SIZE and use it.
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200504072822.18799-2-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/nrf51.h | 3 +--
12
include/hw/i2c/microbit_i2c.h | 2 +-
13
hw/arm/nrf51_soc.c | 4 ++--
14
hw/i2c/microbit_i2c.c | 2 +-
15
hw/timer/nrf51_timer.c | 2 +-
16
5 files changed, 6 insertions(+), 7 deletions(-)
17
18
diff --git a/include/hw/arm/nrf51.h b/include/hw/arm/nrf51.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/nrf51.h
21
+++ b/include/hw/arm/nrf51.h
22
@@ -XXX,XX +XXX,XX @@
23
#define NRF51_IOMEM_BASE 0x40000000
24
#define NRF51_IOMEM_SIZE 0x20000000
25
26
+#define NRF51_PERIPHERAL_SIZE 0x00001000
27
#define NRF51_UART_BASE 0x40002000
28
#define NRF51_TWI_BASE 0x40003000
29
-#define NRF51_TWI_SIZE 0x00001000
30
#define NRF51_TIMER_BASE 0x40008000
31
-#define NRF51_TIMER_SIZE 0x00001000
32
#define NRF51_RNG_BASE 0x4000D000
33
#define NRF51_NVMC_BASE 0x4001E000
34
#define NRF51_GPIO_BASE 0x50000000
35
diff --git a/include/hw/i2c/microbit_i2c.h b/include/hw/i2c/microbit_i2c.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/include/hw/i2c/microbit_i2c.h
38
+++ b/include/hw/i2c/microbit_i2c.h
39
@@ -XXX,XX +XXX,XX @@
40
#define MICROBIT_I2C(obj) \
41
OBJECT_CHECK(MicrobitI2CState, (obj), TYPE_MICROBIT_I2C)
42
43
-#define MICROBIT_I2C_NREGS (NRF51_TWI_SIZE / sizeof(uint32_t))
44
+#define MICROBIT_I2C_NREGS (NRF51_PERIPHERAL_SIZE / sizeof(uint32_t))
45
46
typedef struct {
47
SysBusDevice parent_obj;
48
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/arm/nrf51_soc.c
51
+++ b/hw/arm/nrf51_soc.c
52
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
53
return;
54
}
55
56
- base_addr = NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE;
57
+ base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE;
58
59
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
60
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
61
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
62
63
/* STUB Peripherals */
64
memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL,
65
- "nrf51_soc.clock", 0x1000);
66
+ "nrf51_soc.clock", NRF51_PERIPHERAL_SIZE);
67
memory_region_add_subregion_overlap(&s->container,
68
NRF51_IOMEM_BASE, &s->clock, -1);
69
70
diff --git a/hw/i2c/microbit_i2c.c b/hw/i2c/microbit_i2c.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/i2c/microbit_i2c.c
73
+++ b/hw/i2c/microbit_i2c.c
74
@@ -XXX,XX +XXX,XX @@ static void microbit_i2c_realize(DeviceState *dev, Error **errp)
75
MicrobitI2CState *s = MICROBIT_I2C(dev);
76
77
memory_region_init_io(&s->iomem, OBJECT(s), &microbit_i2c_ops, s,
78
- "microbit.twi", NRF51_TWI_SIZE);
79
+ "microbit.twi", NRF51_PERIPHERAL_SIZE);
80
sysbus_init_mmio(sbd, &s->iomem);
81
}
82
83
diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c
84
index XXXXXXX..XXXXXXX 100644
85
--- a/hw/timer/nrf51_timer.c
86
+++ b/hw/timer/nrf51_timer.c
87
@@ -XXX,XX +XXX,XX @@ static void nrf51_timer_init(Object *obj)
88
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
89
90
memory_region_init_io(&s->iomem, obj, &rng_ops, s,
91
- TYPE_NRF51_TIMER, NRF51_TIMER_SIZE);
92
+ TYPE_NRF51_TIMER, NRF51_PERIPHERAL_SIZE);
93
sysbus_init_mmio(sbd, &s->iomem);
94
sysbus_init_irq(sbd, &s->irq);
95
96
--
97
2.20.1
98
99
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
The NRF51 series SoC have 3 timer peripherals, each having
4
4 counters. To help differentiate which peripheral is accessed,
5
display the timer ID in the trace events.
6
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200504072822.18799-4-f4bug@amsat.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/timer/nrf51_timer.h | 1 +
13
hw/arm/nrf51_soc.c | 5 +++++
14
hw/timer/nrf51_timer.c | 11 +++++++++--
15
hw/timer/trace-events | 4 ++--
16
4 files changed, 17 insertions(+), 4 deletions(-)
17
18
diff --git a/include/hw/timer/nrf51_timer.h b/include/hw/timer/nrf51_timer.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/timer/nrf51_timer.h
21
+++ b/include/hw/timer/nrf51_timer.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct NRF51TimerState {
23
MemoryRegion iomem;
24
qemu_irq irq;
25
26
+ uint8_t id;
27
QEMUTimer timer;
28
int64_t timer_start_ns;
29
int64_t update_counter_ns;
30
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/arm/nrf51_soc.c
33
+++ b/hw/arm/nrf51_soc.c
34
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
35
36
/* TIMER */
37
for (i = 0; i < NRF51_NUM_TIMERS; i++) {
38
+ object_property_set_uint(OBJECT(&s->timer[i]), i, "id", &err);
39
+ if (err) {
40
+ error_propagate(errp, err);
41
+ return;
42
+ }
43
object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
44
if (err) {
45
error_propagate(errp, err);
46
diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/timer/nrf51_timer.c
49
+++ b/hw/timer/nrf51_timer.c
50
@@ -XXX,XX +XXX,XX @@
51
#include "hw/arm/nrf51.h"
52
#include "hw/irq.h"
53
#include "hw/timer/nrf51_timer.h"
54
+#include "hw/qdev-properties.h"
55
#include "migration/vmstate.h"
56
#include "trace.h"
57
58
@@ -XXX,XX +XXX,XX @@ static uint64_t nrf51_timer_read(void *opaque, hwaddr offset, unsigned int size)
59
__func__, offset);
60
}
61
62
- trace_nrf51_timer_read(offset, r, size);
63
+ trace_nrf51_timer_read(s->id, offset, r, size);
64
65
return r;
66
}
67
@@ -XXX,XX +XXX,XX @@ static void nrf51_timer_write(void *opaque, hwaddr offset,
68
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
69
size_t idx;
70
71
- trace_nrf51_timer_write(offset, value, size);
72
+ trace_nrf51_timer_write(s->id, offset, value, size);
73
74
switch (offset) {
75
case NRF51_TIMER_TASK_START:
76
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nrf51_timer = {
77
}
78
};
79
80
+static Property nrf51_timer_properties[] = {
81
+ DEFINE_PROP_UINT8("id", NRF51TimerState, id, 0),
82
+ DEFINE_PROP_END_OF_LIST(),
83
+};
84
+
85
static void nrf51_timer_class_init(ObjectClass *klass, void *data)
86
{
87
DeviceClass *dc = DEVICE_CLASS(klass);
88
89
dc->reset = nrf51_timer_reset;
90
dc->vmsd = &vmstate_nrf51_timer;
91
+ device_class_set_props(dc, nrf51_timer_properties);
92
}
93
94
static const TypeInfo nrf51_timer_info = {
95
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
96
index XXXXXXX..XXXXXXX 100644
97
--- a/hw/timer/trace-events
98
+++ b/hw/timer/trace-events
99
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK
100
cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
101
102
# nrf51_timer.c
103
-nrf51_timer_read(uint64_t addr, uint32_t value, unsigned size) "read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
104
-nrf51_timer_write(uint64_t addr, uint32_t value, unsigned size) "write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
105
+nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
106
+nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
107
108
# bcm2835_systmr.c
109
bcm2835_systmr_irq(bool enable) "timer irq state %u"
110
--
111
2.20.1
112
113
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Add trace event to display timer's counter value updates.
4
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200504072822.18799-5-f4bug@amsat.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/timer/nrf51_timer.c | 1 +
11
hw/timer/trace-events | 1 +
12
2 files changed, 2 insertions(+)
13
14
diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/timer/nrf51_timer.c
17
+++ b/hw/timer/nrf51_timer.c
18
@@ -XXX,XX +XXX,XX @@ static void nrf51_timer_write(void *opaque, hwaddr offset,
19
20
idx = (offset - NRF51_TIMER_TASK_CAPTURE_0) / 4;
21
s->cc[idx] = s->counter;
22
+ trace_nrf51_timer_set_count(s->id, idx, s->counter);
23
}
24
break;
25
case NRF51_TIMER_EVENT_COMPARE_0 ... NRF51_TIMER_EVENT_COMPARE_3:
26
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/timer/trace-events
29
+++ b/hw/timer/trace-events
30
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
31
# nrf51_timer.c
32
nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
33
nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
34
+nrf51_timer_set_count(uint8_t timer_id, uint8_t counter_id, uint32_t value) "timer %u counter %u count 0x%" PRIx32
35
36
# bcm2835_systmr.c
37
bcm2835_systmr_irq(bool enable) "timer irq state %u"
38
--
39
2.20.1
40
41
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200508154359.7494-2-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
include/hw/core/cpu.h | 23 +++++++++++++++++++++++
9
1 file changed, 23 insertions(+)
10
11
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/core/cpu.h
14
+++ b/include/hw/core/cpu.h
15
@@ -XXX,XX +XXX,XX @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
16
vaddr len, int flags);
17
void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
18
void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
19
+
20
+/**
21
+ * cpu_check_watchpoint:
22
+ * @cpu: cpu context
23
+ * @addr: guest virtual address
24
+ * @len: access length
25
+ * @attrs: memory access attributes
26
+ * @flags: watchpoint access type
27
+ * @ra: unwind return address
28
+ *
29
+ * Check for a watchpoint hit in [addr, addr+len) of the type
30
+ * specified by @flags. Exit via exception with a hit.
31
+ */
32
void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
33
MemTxAttrs attrs, int flags, uintptr_t ra);
34
+
35
+/**
36
+ * cpu_watchpoint_address_matches:
37
+ * @cpu: cpu context
38
+ * @addr: guest virtual address
39
+ * @len: access length
40
+ *
41
+ * Return the watchpoint flags that apply to [addr, addr+len).
42
+ * If no watchpoint is registered for the range, the result is 0.
43
+ */
44
int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len);
45
#endif
46
47
--
48
2.20.1
49
50
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
The only caller of cpu_watchpoint_address_matches passes
4
TARGET_PAGE_SIZE, so the bug is not currently visible.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20200508154359.7494-3-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
exec.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/exec.c b/exec.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/exec.c
18
+++ b/exec.c
19
@@ -XXX,XX +XXX,XX @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
20
int ret = 0;
21
22
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
23
- if (watchpoint_address_matches(wp, addr, TARGET_PAGE_SIZE)) {
24
+ if (watchpoint_address_matches(wp, addr, len)) {
25
ret |= wp->flags;
26
}
27
}
28
--
29
2.20.1
30
31
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200508154359.7494-4-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
include/exec/exec-all.h | 17 +++++++++++++++++
9
1 file changed, 17 insertions(+)
10
11
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/exec/exec-all.h
14
+++ b/include/exec/exec-all.h
15
@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
16
{
17
}
18
#endif
19
+/**
20
+ * probe_access:
21
+ * @env: CPUArchState
22
+ * @addr: guest virtual address to look up
23
+ * @size: size of the access
24
+ * @access_type: read, write or execute permission
25
+ * @mmu_idx: MMU index to use for lookup
26
+ * @retaddr: return address for unwinding
27
+ *
28
+ * Look up the guest virtual address @addr. Raise an exception if the
29
+ * page does not satisfy @access_type. Raise an exception if the
30
+ * access (@addr, @size) hits a watchpoint. For writes, mark a clean
31
+ * page as dirty.
32
+ *
33
+ * Finally, return the host address for a page that is backed by RAM,
34
+ * or NULL if the page requires I/O.
35
+ */
36
void *probe_access(CPUArchState *env, target_ulong addr, int size,
37
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
38
39
--
40
2.20.1
41
42
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
We have validated that addr+size does not cross a page boundary.
4
Therefore we need to validate exactly one page. We can achieve
5
that passing any value 1 <= x <= size to page_check_range.
6
7
Passing 1 will simplify the next patch.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-5-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
accel/tcg/user-exec.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/accel/tcg/user-exec.c
20
+++ b/accel/tcg/user-exec.c
21
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
22
g_assert_not_reached();
23
}
24
25
- if (!guest_addr_valid(addr) || page_check_range(addr, size, flags) < 0) {
26
+ if (!guest_addr_valid(addr) || page_check_range(addr, 1, flags) < 0) {
27
CPUState *cpu = env_cpu(env);
28
CPUClass *cc = CPU_GET_CLASS(cpu);
29
cc->tlb_fill(cpu, addr, size, access_type, MMU_USER_IDX, false,
30
--
31
2.20.1
32
33
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
This new interface will allow targets to probe for a page
4
and then handle watchpoints themselves. This will be most
5
useful for vector predicated memory operations, where one
6
page lookup can be used for many operations, and one test
7
can avoid many watchpoint checks.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-6-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
include/exec/cpu-all.h | 13 ++-
15
include/exec/exec-all.h | 22 +++++
16
accel/tcg/cputlb.c | 177 ++++++++++++++++++++--------------------
17
accel/tcg/user-exec.c | 43 ++++++++--
18
4 files changed, 158 insertions(+), 97 deletions(-)
19
20
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/exec/cpu-all.h
23
+++ b/include/exec/cpu-all.h
24
@@ -XXX,XX +XXX,XX @@ CPUArchState *cpu_copy(CPUArchState *env);
25
| CPU_INTERRUPT_TGT_EXT_3 \
26
| CPU_INTERRUPT_TGT_EXT_4)
27
28
-#if !defined(CONFIG_USER_ONLY)
29
+#ifdef CONFIG_USER_ONLY
30
+
31
+/*
32
+ * Allow some level of source compatibility with softmmu. We do not
33
+ * support any of the more exotic features, so only invalid pages may
34
+ * be signaled by probe_access_flags().
35
+ */
36
+#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
37
+#define TLB_MMIO 0
38
+#define TLB_WATCHPOINT 0
39
+
40
+#else
41
42
/*
43
* Flags stored in the low bits of the TLB virtual address.
44
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/include/exec/exec-all.h
47
+++ b/include/exec/exec-all.h
48
@@ -XXX,XX +XXX,XX @@ static inline void *probe_read(CPUArchState *env, target_ulong addr, int size,
49
return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
50
}
51
52
+/**
53
+ * probe_access_flags:
54
+ * @env: CPUArchState
55
+ * @addr: guest virtual address to look up
56
+ * @access_type: read, write or execute permission
57
+ * @mmu_idx: MMU index to use for lookup
58
+ * @nonfault: suppress the fault
59
+ * @phost: return value for host address
60
+ * @retaddr: return address for unwinding
61
+ *
62
+ * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for
63
+ * the page, and storing the host address for RAM in @phost.
64
+ *
65
+ * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK.
66
+ * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags.
67
+ * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags.
68
+ * For simplicity, all "mmio-like" flags are folded to TLB_MMIO.
69
+ */
70
+int probe_access_flags(CPUArchState *env, target_ulong addr,
71
+ MMUAccessType access_type, int mmu_idx,
72
+ bool nonfault, void **phost, uintptr_t retaddr);
73
+
74
#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
75
76
/* Estimated block size for TB allocation. */
77
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/accel/tcg/cputlb.c
80
+++ b/accel/tcg/cputlb.c
81
@@ -XXX,XX +XXX,XX @@ static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size,
82
}
83
}
84
85
-/*
86
- * Probe for whether the specified guest access is permitted. If it is not
87
- * permitted then an exception will be taken in the same way as if this
88
- * were a real access (and we will not return).
89
- * If the size is 0 or the page requires I/O access, returns NULL; otherwise,
90
- * returns the address of the host page similar to tlb_vaddr_to_host().
91
- */
92
-void *probe_access(CPUArchState *env, target_ulong addr, int size,
93
- MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
94
+static int probe_access_internal(CPUArchState *env, target_ulong addr,
95
+ int fault_size, MMUAccessType access_type,
96
+ int mmu_idx, bool nonfault,
97
+ void **phost, uintptr_t retaddr)
98
{
99
uintptr_t index = tlb_index(env, mmu_idx, addr);
100
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
101
- target_ulong tlb_addr;
102
- size_t elt_ofs;
103
- int wp_access;
104
-
105
- g_assert(-(addr | TARGET_PAGE_MASK) >= size);
106
-
107
- switch (access_type) {
108
- case MMU_DATA_LOAD:
109
- elt_ofs = offsetof(CPUTLBEntry, addr_read);
110
- wp_access = BP_MEM_READ;
111
- break;
112
- case MMU_DATA_STORE:
113
- elt_ofs = offsetof(CPUTLBEntry, addr_write);
114
- wp_access = BP_MEM_WRITE;
115
- break;
116
- case MMU_INST_FETCH:
117
- elt_ofs = offsetof(CPUTLBEntry, addr_code);
118
- wp_access = BP_MEM_READ;
119
- break;
120
- default:
121
- g_assert_not_reached();
122
- }
123
- tlb_addr = tlb_read_ofs(entry, elt_ofs);
124
-
125
- if (unlikely(!tlb_hit(tlb_addr, addr))) {
126
- if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs,
127
- addr & TARGET_PAGE_MASK)) {
128
- tlb_fill(env_cpu(env), addr, size, access_type, mmu_idx, retaddr);
129
- /* TLB resize via tlb_fill may have moved the entry. */
130
- index = tlb_index(env, mmu_idx, addr);
131
- entry = tlb_entry(env, mmu_idx, addr);
132
- }
133
- tlb_addr = tlb_read_ofs(entry, elt_ofs);
134
- }
135
-
136
- if (!size) {
137
- return NULL;
138
- }
139
-
140
- if (unlikely(tlb_addr & TLB_FLAGS_MASK)) {
141
- CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
142
-
143
- /* Reject I/O access, or other required slow-path. */
144
- if (tlb_addr & (TLB_MMIO | TLB_BSWAP | TLB_DISCARD_WRITE)) {
145
- return NULL;
146
- }
147
-
148
- /* Handle watchpoints. */
149
- if (tlb_addr & TLB_WATCHPOINT) {
150
- cpu_check_watchpoint(env_cpu(env), addr, size,
151
- iotlbentry->attrs, wp_access, retaddr);
152
- }
153
-
154
- /* Handle clean RAM pages. */
155
- if (tlb_addr & TLB_NOTDIRTY) {
156
- notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr);
157
- }
158
- }
159
-
160
- return (void *)((uintptr_t)addr + entry->addend);
161
-}
162
-
163
-void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
164
- MMUAccessType access_type, int mmu_idx)
165
-{
166
- CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
167
- target_ulong tlb_addr, page;
168
+ target_ulong tlb_addr, page_addr;
169
size_t elt_ofs;
170
+ int flags;
171
172
switch (access_type) {
173
case MMU_DATA_LOAD:
174
@@ -XXX,XX +XXX,XX @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
175
default:
176
g_assert_not_reached();
177
}
178
-
179
- page = addr & TARGET_PAGE_MASK;
180
tlb_addr = tlb_read_ofs(entry, elt_ofs);
181
182
- if (!tlb_hit_page(tlb_addr, page)) {
183
- uintptr_t index = tlb_index(env, mmu_idx, addr);
184
-
185
- if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page)) {
186
+ page_addr = addr & TARGET_PAGE_MASK;
187
+ if (!tlb_hit_page(tlb_addr, page_addr)) {
188
+ if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) {
189
CPUState *cs = env_cpu(env);
190
CPUClass *cc = CPU_GET_CLASS(cs);
191
192
- if (!cc->tlb_fill(cs, addr, 0, access_type, mmu_idx, true, 0)) {
193
+ if (!cc->tlb_fill(cs, addr, fault_size, access_type,
194
+ mmu_idx, nonfault, retaddr)) {
195
/* Non-faulting page table read failed. */
196
- return NULL;
197
+ *phost = NULL;
198
+ return TLB_INVALID_MASK;
199
}
200
201
/* TLB resize via tlb_fill may have moved the entry. */
202
@@ -XXX,XX +XXX,XX @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
203
}
204
tlb_addr = tlb_read_ofs(entry, elt_ofs);
205
}
206
+ flags = tlb_addr & TLB_FLAGS_MASK;
207
208
- if (tlb_addr & ~TARGET_PAGE_MASK) {
209
- /* IO access */
210
+ /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */
211
+ if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) {
212
+ *phost = NULL;
213
+ return TLB_MMIO;
214
+ }
215
+
216
+ /* Everything else is RAM. */
217
+ *phost = (void *)((uintptr_t)addr + entry->addend);
218
+ return flags;
219
+}
220
+
221
+int probe_access_flags(CPUArchState *env, target_ulong addr,
222
+ MMUAccessType access_type, int mmu_idx,
223
+ bool nonfault, void **phost, uintptr_t retaddr)
224
+{
225
+ int flags;
226
+
227
+ flags = probe_access_internal(env, addr, 0, access_type, mmu_idx,
228
+ nonfault, phost, retaddr);
229
+
230
+ /* Handle clean RAM pages. */
231
+ if (unlikely(flags & TLB_NOTDIRTY)) {
232
+ uintptr_t index = tlb_index(env, mmu_idx, addr);
233
+ CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
234
+
235
+ notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr);
236
+ flags &= ~TLB_NOTDIRTY;
237
+ }
238
+
239
+ return flags;
240
+}
241
+
242
+void *probe_access(CPUArchState *env, target_ulong addr, int size,
243
+ MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
244
+{
245
+ void *host;
246
+ int flags;
247
+
248
+ g_assert(-(addr | TARGET_PAGE_MASK) >= size);
249
+
250
+ flags = probe_access_internal(env, addr, size, access_type, mmu_idx,
251
+ false, &host, retaddr);
252
+
253
+ /* Per the interface, size == 0 merely faults the access. */
254
+ if (size == 0) {
255
return NULL;
256
}
257
258
- return (void *)((uintptr_t)addr + entry->addend);
259
+ if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) {
260
+ uintptr_t index = tlb_index(env, mmu_idx, addr);
261
+ CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
262
+
263
+ /* Handle watchpoints. */
264
+ if (flags & TLB_WATCHPOINT) {
265
+ int wp_access = (access_type == MMU_DATA_STORE
266
+ ? BP_MEM_WRITE : BP_MEM_READ);
267
+ cpu_check_watchpoint(env_cpu(env), addr, size,
268
+ iotlbentry->attrs, wp_access, retaddr);
269
+ }
270
+
271
+ /* Handle clean RAM pages. */
272
+ if (flags & TLB_NOTDIRTY) {
273
+ notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr);
274
+ }
275
+ }
276
+
277
+ return host;
278
}
279
280
+void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
281
+ MMUAccessType access_type, int mmu_idx)
282
+{
283
+ void *host;
284
+ int flags;
285
+
286
+ flags = probe_access_internal(env, addr, 0, access_type,
287
+ mmu_idx, true, &host, 0);
288
+
289
+ /* No combination of flags are expected by the caller. */
290
+ return flags ? NULL : host;
291
+}
292
293
#ifdef CONFIG_PLUGIN
294
/*
295
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
296
index XXXXXXX..XXXXXXX 100644
297
--- a/accel/tcg/user-exec.c
298
+++ b/accel/tcg/user-exec.c
299
@@ -XXX,XX +XXX,XX @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
300
g_assert_not_reached();
301
}
302
303
-void *probe_access(CPUArchState *env, target_ulong addr, int size,
304
- MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
305
+static int probe_access_internal(CPUArchState *env, target_ulong addr,
306
+ int fault_size, MMUAccessType access_type,
307
+ bool nonfault, uintptr_t ra)
308
{
309
int flags;
310
311
- g_assert(-(addr | TARGET_PAGE_MASK) >= size);
312
-
313
switch (access_type) {
314
case MMU_DATA_STORE:
315
flags = PAGE_WRITE;
316
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
317
}
318
319
if (!guest_addr_valid(addr) || page_check_range(addr, 1, flags) < 0) {
320
- CPUState *cpu = env_cpu(env);
321
- CPUClass *cc = CPU_GET_CLASS(cpu);
322
- cc->tlb_fill(cpu, addr, size, access_type, MMU_USER_IDX, false,
323
- retaddr);
324
- g_assert_not_reached();
325
+ if (nonfault) {
326
+ return TLB_INVALID_MASK;
327
+ } else {
328
+ CPUState *cpu = env_cpu(env);
329
+ CPUClass *cc = CPU_GET_CLASS(cpu);
330
+ cc->tlb_fill(cpu, addr, fault_size, access_type,
331
+ MMU_USER_IDX, false, ra);
332
+ g_assert_not_reached();
333
+ }
334
}
335
+ return 0;
336
+}
337
+
338
+int probe_access_flags(CPUArchState *env, target_ulong addr,
339
+ MMUAccessType access_type, int mmu_idx,
340
+ bool nonfault, void **phost, uintptr_t ra)
341
+{
342
+ int flags;
343
+
344
+ flags = probe_access_internal(env, addr, 0, access_type, nonfault, ra);
345
+ *phost = flags ? NULL : g2h(addr);
346
+ return flags;
347
+}
348
+
349
+void *probe_access(CPUArchState *env, target_ulong addr, int size,
350
+ MMUAccessType access_type, int mmu_idx, uintptr_t ra)
351
+{
352
+ int flags;
353
+
354
+ g_assert(-(addr | TARGET_PAGE_MASK) >= size);
355
+ flags = probe_access_internal(env, addr, size, access_type, false, ra);
356
+ g_assert(flags == 0);
357
358
return size ? g2h(addr) : NULL;
359
}
360
--
361
2.20.1
362
363
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
We currently have target-endian versions of these operations,
4
but no easy way to force a specific endianness. This can be
5
helpful if the target has endian-specific operations, or a mode
6
that swaps endianness.
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-7-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
docs/devel/loads-stores.rst | 39 +++--
14
include/exec/cpu_ldst.h | 283 +++++++++++++++++++++++++++---------
15
accel/tcg/cputlb.c | 236 ++++++++++++++++++++++--------
16
accel/tcg/user-exec.c | 211 ++++++++++++++++++++++-----
17
4 files changed, 587 insertions(+), 182 deletions(-)
18
19
diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst
20
index XXXXXXX..XXXXXXX 100644
21
--- a/docs/devel/loads-stores.rst
22
+++ b/docs/devel/loads-stores.rst
23
@@ -XXX,XX +XXX,XX @@ function, which is a return address into the generated code.
24
25
Function names follow the pattern:
26
27
-load: ``cpu_ld{sign}{size}_mmuidx_ra(env, ptr, mmuidx, retaddr)``
28
+load: ``cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmuidx, retaddr)``
29
30
-store: ``cpu_st{size}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
31
+store: ``cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
32
33
``sign``
34
- (empty) : for 32 or 64 bit sizes
35
@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
36
- ``l`` : 32 bits
37
- ``q`` : 64 bits
38
39
+``end``
40
+ - (empty) : for target endian, or 8 bit sizes
41
+ - ``_be`` : big endian
42
+ - ``_le`` : little endian
43
+
44
Regexes for git grep:
45
- - ``\<cpu_ld[us]\?[bwlq]_mmuidx_ra\>``
46
- - ``\<cpu_st[bwlq]_mmuidx_ra\>``
47
+ - ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_mmuidx_ra\>``
48
+ - ``\<cpu_st[bwlq](_[bl]e)\?_mmuidx_ra\>``
49
50
``cpu_{ld,st}*_data_ra``
51
~~~~~~~~~~~~~~~~~~~~~~~~
52
@@ -XXX,XX +XXX,XX @@ be performed with a context other than the default.
53
54
Function names follow the pattern:
55
56
-load: ``cpu_ld{sign}{size}_data_ra(env, ptr, ra)``
57
+load: ``cpu_ld{sign}{size}{end}_data_ra(env, ptr, ra)``
58
59
-store: ``cpu_st{size}_data_ra(env, ptr, val, ra)``
60
+store: ``cpu_st{size}{end}_data_ra(env, ptr, val, ra)``
61
62
``sign``
63
- (empty) : for 32 or 64 bit sizes
64
@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}_data_ra(env, ptr, val, ra)``
65
- ``l`` : 32 bits
66
- ``q`` : 64 bits
67
68
+``end``
69
+ - (empty) : for target endian, or 8 bit sizes
70
+ - ``_be`` : big endian
71
+ - ``_le`` : little endian
72
+
73
Regexes for git grep:
74
- - ``\<cpu_ld[us]\?[bwlq]_data_ra\>``
75
- - ``\<cpu_st[bwlq]_data_ra\>``
76
+ - ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_data_ra\>``
77
+ - ``\<cpu_st[bwlq](_[bl]e)\?_data_ra\>``
78
79
``cpu_{ld,st}*_data``
80
~~~~~~~~~~~~~~~~~~~~~
81
@@ -XXX,XX +XXX,XX @@ the CPU state anyway.
82
83
Function names follow the pattern:
84
85
-load: ``cpu_ld{sign}{size}_data(env, ptr)``
86
+load: ``cpu_ld{sign}{size}{end}_data(env, ptr)``
87
88
-store: ``cpu_st{size}_data(env, ptr, val)``
89
+store: ``cpu_st{size}{end}_data(env, ptr, val)``
90
91
``sign``
92
- (empty) : for 32 or 64 bit sizes
93
@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}_data(env, ptr, val)``
94
- ``l`` : 32 bits
95
- ``q`` : 64 bits
96
97
+``end``
98
+ - (empty) : for target endian, or 8 bit sizes
99
+ - ``_be`` : big endian
100
+ - ``_le`` : little endian
101
+
102
Regexes for git grep
103
- - ``\<cpu_ld[us]\?[bwlq]_data\>``
104
- - ``\<cpu_st[bwlq]_data\+\>``
105
+ - ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_data\>``
106
+ - ``\<cpu_st[bwlq](_[bl]e)\?_data\+\>``
107
108
``cpu_ld*_code``
109
~~~~~~~~~~~~~~~~
110
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
111
index XXXXXXX..XXXXXXX 100644
112
--- a/include/exec/cpu_ldst.h
113
+++ b/include/exec/cpu_ldst.h
114
@@ -XXX,XX +XXX,XX @@
115
*
116
* The syntax for the accessors is:
117
*
118
- * load: cpu_ld{sign}{size}_{mmusuffix}(env, ptr)
119
- * cpu_ld{sign}{size}_{mmusuffix}_ra(env, ptr, retaddr)
120
- * cpu_ld{sign}{size}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
121
+ * load: cpu_ld{sign}{size}{end}_{mmusuffix}(env, ptr)
122
+ * cpu_ld{sign}{size}{end}_{mmusuffix}_ra(env, ptr, retaddr)
123
+ * cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
124
*
125
- * store: cpu_st{size}_{mmusuffix}(env, ptr, val)
126
- * cpu_st{size}_{mmusuffix}_ra(env, ptr, val, retaddr)
127
- * cpu_st{size}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
128
+ * store: cpu_st{size}{end}_{mmusuffix}(env, ptr, val)
129
+ * cpu_st{size}{end}_{mmusuffix}_ra(env, ptr, val, retaddr)
130
+ * cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
131
*
132
* sign is:
133
* (empty): for 32 and 64 bit sizes
134
@@ -XXX,XX +XXX,XX @@
135
* l: 32 bits
136
* q: 64 bits
137
*
138
+ * end is:
139
+ * (empty): for target native endian, or for 8 bit access
140
+ * _be: for forced big endian
141
+ * _le: for forced little endian
142
+ *
143
* mmusuffix is one of the generic suffixes "data" or "code", or "mmuidx".
144
* The "mmuidx" suffix carries an extra mmu_idx argument that specifies
145
* the index to use; the "data" and "code" suffixes take the index from
146
@@ -XXX,XX +XXX,XX @@ typedef target_ulong abi_ptr;
147
#endif
148
149
uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
150
-uint32_t cpu_lduw_data(CPUArchState *env, abi_ptr ptr);
151
-uint32_t cpu_ldl_data(CPUArchState *env, abi_ptr ptr);
152
-uint64_t cpu_ldq_data(CPUArchState *env, abi_ptr ptr);
153
int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr);
154
-int cpu_ldsw_data(CPUArchState *env, abi_ptr ptr);
155
156
-uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
157
-uint32_t cpu_lduw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
158
-uint32_t cpu_ldl_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
159
-uint64_t cpu_ldq_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
160
-int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
161
-int cpu_ldsw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
162
+uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr);
163
+int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr);
164
+uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr);
165
+uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr);
166
+
167
+uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr);
168
+int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr);
169
+uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr);
170
+uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr);
171
+
172
+uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
173
+int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
174
+
175
+uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
176
+int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
177
+uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
178
+uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
179
+
180
+uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
181
+int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
182
+uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
183
+uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
184
185
void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
186
-void cpu_stw_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
187
-void cpu_stl_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
188
-void cpu_stq_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
189
+
190
+void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
191
+void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
192
+void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
193
+
194
+void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
195
+void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
196
+void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
197
198
void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
199
- uint32_t val, uintptr_t retaddr);
200
-void cpu_stw_data_ra(CPUArchState *env, abi_ptr ptr,
201
- uint32_t val, uintptr_t retaddr);
202
-void cpu_stl_data_ra(CPUArchState *env, abi_ptr ptr,
203
- uint32_t val, uintptr_t retaddr);
204
-void cpu_stq_data_ra(CPUArchState *env, abi_ptr ptr,
205
- uint64_t val, uintptr_t retaddr);
206
+ uint32_t val, uintptr_t ra);
207
+
208
+void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
209
+ uint32_t val, uintptr_t ra);
210
+void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
211
+ uint32_t val, uintptr_t ra);
212
+void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
213
+ uint64_t val, uintptr_t ra);
214
+
215
+void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
216
+ uint32_t val, uintptr_t ra);
217
+void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
218
+ uint32_t val, uintptr_t ra);
219
+void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
220
+ uint64_t val, uintptr_t ra);
221
222
#if defined(CONFIG_USER_ONLY)
223
224
@@ -XXX,XX +XXX,XX @@ static inline uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
225
return cpu_ldub_data_ra(env, addr, ra);
226
}
227
228
-static inline uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
229
- int mmu_idx, uintptr_t ra)
230
-{
231
- return cpu_lduw_data_ra(env, addr, ra);
232
-}
233
-
234
-static inline uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
235
- int mmu_idx, uintptr_t ra)
236
-{
237
- return cpu_ldl_data_ra(env, addr, ra);
238
-}
239
-
240
-static inline uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
241
- int mmu_idx, uintptr_t ra)
242
-{
243
- return cpu_ldq_data_ra(env, addr, ra);
244
-}
245
-
246
static inline int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
247
int mmu_idx, uintptr_t ra)
248
{
249
return cpu_ldsb_data_ra(env, addr, ra);
250
}
251
252
-static inline int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
253
- int mmu_idx, uintptr_t ra)
254
+static inline uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
255
+ int mmu_idx, uintptr_t ra)
256
{
257
- return cpu_ldsw_data_ra(env, addr, ra);
258
+ return cpu_lduw_be_data_ra(env, addr, ra);
259
+}
260
+
261
+static inline int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
262
+ int mmu_idx, uintptr_t ra)
263
+{
264
+ return cpu_ldsw_be_data_ra(env, addr, ra);
265
+}
266
+
267
+static inline uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
268
+ int mmu_idx, uintptr_t ra)
269
+{
270
+ return cpu_ldl_be_data_ra(env, addr, ra);
271
+}
272
+
273
+static inline uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
274
+ int mmu_idx, uintptr_t ra)
275
+{
276
+ return cpu_ldq_be_data_ra(env, addr, ra);
277
+}
278
+
279
+static inline uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
280
+ int mmu_idx, uintptr_t ra)
281
+{
282
+ return cpu_lduw_le_data_ra(env, addr, ra);
283
+}
284
+
285
+static inline int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
286
+ int mmu_idx, uintptr_t ra)
287
+{
288
+ return cpu_ldsw_le_data_ra(env, addr, ra);
289
+}
290
+
291
+static inline uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
292
+ int mmu_idx, uintptr_t ra)
293
+{
294
+ return cpu_ldl_le_data_ra(env, addr, ra);
295
+}
296
+
297
+static inline uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
298
+ int mmu_idx, uintptr_t ra)
299
+{
300
+ return cpu_ldq_le_data_ra(env, addr, ra);
301
}
302
303
static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
304
@@ -XXX,XX +XXX,XX @@ static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
305
cpu_stb_data_ra(env, addr, val, ra);
306
}
307
308
-static inline void cpu_stw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
309
- uint32_t val, int mmu_idx, uintptr_t ra)
310
+static inline void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
311
+ uint32_t val, int mmu_idx,
312
+ uintptr_t ra)
313
{
314
- cpu_stw_data_ra(env, addr, val, ra);
315
+ cpu_stw_be_data_ra(env, addr, val, ra);
316
}
317
318
-static inline void cpu_stl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
319
- uint32_t val, int mmu_idx, uintptr_t ra)
320
+static inline void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
321
+ uint32_t val, int mmu_idx,
322
+ uintptr_t ra)
323
{
324
- cpu_stl_data_ra(env, addr, val, ra);
325
+ cpu_stl_be_data_ra(env, addr, val, ra);
326
}
327
328
-static inline void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
329
- uint64_t val, int mmu_idx, uintptr_t ra)
330
+static inline void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
331
+ uint64_t val, int mmu_idx,
332
+ uintptr_t ra)
333
{
334
- cpu_stq_data_ra(env, addr, val, ra);
335
+ cpu_stq_be_data_ra(env, addr, val, ra);
336
+}
337
+
338
+static inline void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
339
+ uint32_t val, int mmu_idx,
340
+ uintptr_t ra)
341
+{
342
+ cpu_stw_le_data_ra(env, addr, val, ra);
343
+}
344
+
345
+static inline void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
346
+ uint32_t val, int mmu_idx,
347
+ uintptr_t ra)
348
+{
349
+ cpu_stl_le_data_ra(env, addr, val, ra);
350
+}
351
+
352
+static inline void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
353
+ uint64_t val, int mmu_idx,
354
+ uintptr_t ra)
355
+{
356
+ cpu_stq_le_data_ra(env, addr, val, ra);
357
}
358
359
#else
360
@@ -XXX,XX +XXX,XX @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
361
362
uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
363
int mmu_idx, uintptr_t ra);
364
-uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
365
- int mmu_idx, uintptr_t ra);
366
-uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
367
- int mmu_idx, uintptr_t ra);
368
-uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
369
- int mmu_idx, uintptr_t ra);
370
-
371
int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
372
int mmu_idx, uintptr_t ra);
373
-int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
374
- int mmu_idx, uintptr_t ra);
375
+
376
+uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
377
+ int mmu_idx, uintptr_t ra);
378
+int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
379
+ int mmu_idx, uintptr_t ra);
380
+uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
381
+ int mmu_idx, uintptr_t ra);
382
+uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
383
+ int mmu_idx, uintptr_t ra);
384
+
385
+uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
386
+ int mmu_idx, uintptr_t ra);
387
+int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
388
+ int mmu_idx, uintptr_t ra);
389
+uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
390
+ int mmu_idx, uintptr_t ra);
391
+uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
392
+ int mmu_idx, uintptr_t ra);
393
394
void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
395
int mmu_idx, uintptr_t retaddr);
396
-void cpu_stw_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
397
- int mmu_idx, uintptr_t retaddr);
398
-void cpu_stl_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
399
- int mmu_idx, uintptr_t retaddr);
400
-void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
401
- int mmu_idx, uintptr_t retaddr);
402
+
403
+void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
404
+ int mmu_idx, uintptr_t retaddr);
405
+void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
406
+ int mmu_idx, uintptr_t retaddr);
407
+void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
408
+ int mmu_idx, uintptr_t retaddr);
409
+
410
+void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
411
+ int mmu_idx, uintptr_t retaddr);
412
+void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
413
+ int mmu_idx, uintptr_t retaddr);
414
+void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
415
+ int mmu_idx, uintptr_t retaddr);
416
417
#endif /* defined(CONFIG_USER_ONLY) */
418
419
+#ifdef TARGET_WORDS_BIGENDIAN
420
+# define cpu_lduw_data cpu_lduw_be_data
421
+# define cpu_ldsw_data cpu_ldsw_be_data
422
+# define cpu_ldl_data cpu_ldl_be_data
423
+# define cpu_ldq_data cpu_ldq_be_data
424
+# define cpu_lduw_data_ra cpu_lduw_be_data_ra
425
+# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra
426
+# define cpu_ldl_data_ra cpu_ldl_be_data_ra
427
+# define cpu_ldq_data_ra cpu_ldq_be_data_ra
428
+# define cpu_lduw_mmuidx_ra cpu_lduw_be_mmuidx_ra
429
+# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra
430
+# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra
431
+# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra
432
+# define cpu_stw_data cpu_stw_be_data
433
+# define cpu_stl_data cpu_stl_be_data
434
+# define cpu_stq_data cpu_stq_be_data
435
+# define cpu_stw_data_ra cpu_stw_be_data_ra
436
+# define cpu_stl_data_ra cpu_stl_be_data_ra
437
+# define cpu_stq_data_ra cpu_stq_be_data_ra
438
+# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra
439
+# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra
440
+# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra
441
+#else
442
+# define cpu_lduw_data cpu_lduw_le_data
443
+# define cpu_ldsw_data cpu_ldsw_le_data
444
+# define cpu_ldl_data cpu_ldl_le_data
445
+# define cpu_ldq_data cpu_ldq_le_data
446
+# define cpu_lduw_data_ra cpu_lduw_le_data_ra
447
+# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra
448
+# define cpu_ldl_data_ra cpu_ldl_le_data_ra
449
+# define cpu_ldq_data_ra cpu_ldq_le_data_ra
450
+# define cpu_lduw_mmuidx_ra cpu_lduw_le_mmuidx_ra
451
+# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra
452
+# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra
453
+# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra
454
+# define cpu_stw_data cpu_stw_le_data
455
+# define cpu_stl_data cpu_stl_le_data
456
+# define cpu_stq_data cpu_stq_le_data
457
+# define cpu_stw_data_ra cpu_stw_le_data_ra
458
+# define cpu_stl_data_ra cpu_stl_le_data_ra
459
+# define cpu_stq_data_ra cpu_stq_le_data_ra
460
+# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra
461
+# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra
462
+# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra
463
+#endif
464
+
465
uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
466
uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr);
467
uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr);
468
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
469
index XXXXXXX..XXXXXXX 100644
470
--- a/accel/tcg/cputlb.c
471
+++ b/accel/tcg/cputlb.c
472
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
473
full_ldub_mmu);
474
}
475
476
-uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
477
- int mmu_idx, uintptr_t ra)
478
+uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
479
+ int mmu_idx, uintptr_t ra)
480
{
481
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_TEUW,
482
- MO_TE == MO_LE
483
- ? full_le_lduw_mmu : full_be_lduw_mmu);
484
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUW, full_be_lduw_mmu);
485
}
486
487
-int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
488
- int mmu_idx, uintptr_t ra)
489
+int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
490
+ int mmu_idx, uintptr_t ra)
491
{
492
- return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_TESW,
493
- MO_TE == MO_LE
494
- ? full_le_lduw_mmu : full_be_lduw_mmu);
495
+ return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_BESW,
496
+ full_be_lduw_mmu);
497
}
498
499
-uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
500
- int mmu_idx, uintptr_t ra)
501
+uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
502
+ int mmu_idx, uintptr_t ra)
503
{
504
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_TEUL,
505
- MO_TE == MO_LE
506
- ? full_le_ldul_mmu : full_be_ldul_mmu);
507
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUL, full_be_ldul_mmu);
508
}
509
510
-uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
511
- int mmu_idx, uintptr_t ra)
512
+uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
513
+ int mmu_idx, uintptr_t ra)
514
{
515
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_TEQ,
516
- MO_TE == MO_LE
517
- ? helper_le_ldq_mmu : helper_be_ldq_mmu);
518
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEQ, helper_be_ldq_mmu);
519
+}
520
+
521
+uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
522
+ int mmu_idx, uintptr_t ra)
523
+{
524
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUW, full_le_lduw_mmu);
525
+}
526
+
527
+int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
528
+ int mmu_idx, uintptr_t ra)
529
+{
530
+ return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_LESW,
531
+ full_le_lduw_mmu);
532
+}
533
+
534
+uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
535
+ int mmu_idx, uintptr_t ra)
536
+{
537
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUL, full_le_ldul_mmu);
538
+}
539
+
540
+uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
541
+ int mmu_idx, uintptr_t ra)
542
+{
543
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEQ, helper_le_ldq_mmu);
544
}
545
546
uint32_t cpu_ldub_data_ra(CPUArchState *env, target_ulong ptr,
547
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
548
return cpu_ldsb_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
549
}
550
551
-uint32_t cpu_lduw_data_ra(CPUArchState *env, target_ulong ptr,
552
- uintptr_t retaddr)
553
+uint32_t cpu_lduw_be_data_ra(CPUArchState *env, target_ulong ptr,
554
+ uintptr_t retaddr)
555
{
556
- return cpu_lduw_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
557
+ return cpu_lduw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
558
}
559
560
-int cpu_ldsw_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
561
+int cpu_ldsw_be_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
562
{
563
- return cpu_ldsw_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
564
+ return cpu_ldsw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
565
}
566
567
-uint32_t cpu_ldl_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
568
+uint32_t cpu_ldl_be_data_ra(CPUArchState *env, target_ulong ptr,
569
+ uintptr_t retaddr)
570
{
571
- return cpu_ldl_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
572
+ return cpu_ldl_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
573
}
574
575
-uint64_t cpu_ldq_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
576
+uint64_t cpu_ldq_be_data_ra(CPUArchState *env, target_ulong ptr,
577
+ uintptr_t retaddr)
578
{
579
- return cpu_ldq_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
580
+ return cpu_ldq_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
581
+}
582
+
583
+uint32_t cpu_lduw_le_data_ra(CPUArchState *env, target_ulong ptr,
584
+ uintptr_t retaddr)
585
+{
586
+ return cpu_lduw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
587
+}
588
+
589
+int cpu_ldsw_le_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
590
+{
591
+ return cpu_ldsw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
592
+}
593
+
594
+uint32_t cpu_ldl_le_data_ra(CPUArchState *env, target_ulong ptr,
595
+ uintptr_t retaddr)
596
+{
597
+ return cpu_ldl_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
598
+}
599
+
600
+uint64_t cpu_ldq_le_data_ra(CPUArchState *env, target_ulong ptr,
601
+ uintptr_t retaddr)
602
+{
603
+ return cpu_ldq_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
604
}
605
606
uint32_t cpu_ldub_data(CPUArchState *env, target_ulong ptr)
607
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data(CPUArchState *env, target_ulong ptr)
608
return cpu_ldsb_data_ra(env, ptr, 0);
609
}
610
611
-uint32_t cpu_lduw_data(CPUArchState *env, target_ulong ptr)
612
+uint32_t cpu_lduw_be_data(CPUArchState *env, target_ulong ptr)
613
{
614
- return cpu_lduw_data_ra(env, ptr, 0);
615
+ return cpu_lduw_be_data_ra(env, ptr, 0);
616
}
617
618
-int cpu_ldsw_data(CPUArchState *env, target_ulong ptr)
619
+int cpu_ldsw_be_data(CPUArchState *env, target_ulong ptr)
620
{
621
- return cpu_ldsw_data_ra(env, ptr, 0);
622
+ return cpu_ldsw_be_data_ra(env, ptr, 0);
623
}
624
625
-uint32_t cpu_ldl_data(CPUArchState *env, target_ulong ptr)
626
+uint32_t cpu_ldl_be_data(CPUArchState *env, target_ulong ptr)
627
{
628
- return cpu_ldl_data_ra(env, ptr, 0);
629
+ return cpu_ldl_be_data_ra(env, ptr, 0);
630
}
631
632
-uint64_t cpu_ldq_data(CPUArchState *env, target_ulong ptr)
633
+uint64_t cpu_ldq_be_data(CPUArchState *env, target_ulong ptr)
634
{
635
- return cpu_ldq_data_ra(env, ptr, 0);
636
+ return cpu_ldq_be_data_ra(env, ptr, 0);
637
+}
638
+
639
+uint32_t cpu_lduw_le_data(CPUArchState *env, target_ulong ptr)
640
+{
641
+ return cpu_lduw_le_data_ra(env, ptr, 0);
642
+}
643
+
644
+int cpu_ldsw_le_data(CPUArchState *env, target_ulong ptr)
645
+{
646
+ return cpu_ldsw_le_data_ra(env, ptr, 0);
647
+}
648
+
649
+uint32_t cpu_ldl_le_data(CPUArchState *env, target_ulong ptr)
650
+{
651
+ return cpu_ldl_le_data_ra(env, ptr, 0);
652
+}
653
+
654
+uint64_t cpu_ldq_le_data(CPUArchState *env, target_ulong ptr)
655
+{
656
+ return cpu_ldq_le_data_ra(env, ptr, 0);
657
}
658
659
/*
660
@@ -XXX,XX +XXX,XX @@ void cpu_stb_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
661
cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_UB);
662
}
663
664
-void cpu_stw_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
665
- int mmu_idx, uintptr_t retaddr)
666
+void cpu_stw_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
667
+ int mmu_idx, uintptr_t retaddr)
668
{
669
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEUW);
670
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUW);
671
}
672
673
-void cpu_stl_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
674
- int mmu_idx, uintptr_t retaddr)
675
+void cpu_stl_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
676
+ int mmu_idx, uintptr_t retaddr)
677
{
678
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEUL);
679
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUL);
680
}
681
682
-void cpu_stq_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
683
- int mmu_idx, uintptr_t retaddr)
684
+void cpu_stq_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
685
+ int mmu_idx, uintptr_t retaddr)
686
{
687
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEQ);
688
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEQ);
689
+}
690
+
691
+void cpu_stw_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
692
+ int mmu_idx, uintptr_t retaddr)
693
+{
694
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUW);
695
+}
696
+
697
+void cpu_stl_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
698
+ int mmu_idx, uintptr_t retaddr)
699
+{
700
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUL);
701
+}
702
+
703
+void cpu_stq_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
704
+ int mmu_idx, uintptr_t retaddr)
705
+{
706
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEQ);
707
}
708
709
void cpu_stb_data_ra(CPUArchState *env, target_ulong ptr,
710
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data_ra(CPUArchState *env, target_ulong ptr,
711
cpu_stb_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
712
}
713
714
-void cpu_stw_data_ra(CPUArchState *env, target_ulong ptr,
715
- uint32_t val, uintptr_t retaddr)
716
+void cpu_stw_be_data_ra(CPUArchState *env, target_ulong ptr,
717
+ uint32_t val, uintptr_t retaddr)
718
{
719
- cpu_stw_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
720
+ cpu_stw_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
721
}
722
723
-void cpu_stl_data_ra(CPUArchState *env, target_ulong ptr,
724
- uint32_t val, uintptr_t retaddr)
725
+void cpu_stl_be_data_ra(CPUArchState *env, target_ulong ptr,
726
+ uint32_t val, uintptr_t retaddr)
727
{
728
- cpu_stl_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
729
+ cpu_stl_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
730
}
731
732
-void cpu_stq_data_ra(CPUArchState *env, target_ulong ptr,
733
- uint64_t val, uintptr_t retaddr)
734
+void cpu_stq_be_data_ra(CPUArchState *env, target_ulong ptr,
735
+ uint64_t val, uintptr_t retaddr)
736
{
737
- cpu_stq_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
738
+ cpu_stq_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
739
+}
740
+
741
+void cpu_stw_le_data_ra(CPUArchState *env, target_ulong ptr,
742
+ uint32_t val, uintptr_t retaddr)
743
+{
744
+ cpu_stw_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
745
+}
746
+
747
+void cpu_stl_le_data_ra(CPUArchState *env, target_ulong ptr,
748
+ uint32_t val, uintptr_t retaddr)
749
+{
750
+ cpu_stl_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
751
+}
752
+
753
+void cpu_stq_le_data_ra(CPUArchState *env, target_ulong ptr,
754
+ uint64_t val, uintptr_t retaddr)
755
+{
756
+ cpu_stq_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
757
}
758
759
void cpu_stb_data(CPUArchState *env, target_ulong ptr, uint32_t val)
760
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data(CPUArchState *env, target_ulong ptr, uint32_t val)
761
cpu_stb_data_ra(env, ptr, val, 0);
762
}
763
764
-void cpu_stw_data(CPUArchState *env, target_ulong ptr, uint32_t val)
765
+void cpu_stw_be_data(CPUArchState *env, target_ulong ptr, uint32_t val)
766
{
767
- cpu_stw_data_ra(env, ptr, val, 0);
768
+ cpu_stw_be_data_ra(env, ptr, val, 0);
769
}
770
771
-void cpu_stl_data(CPUArchState *env, target_ulong ptr, uint32_t val)
772
+void cpu_stl_be_data(CPUArchState *env, target_ulong ptr, uint32_t val)
773
{
774
- cpu_stl_data_ra(env, ptr, val, 0);
775
+ cpu_stl_be_data_ra(env, ptr, val, 0);
776
}
777
778
-void cpu_stq_data(CPUArchState *env, target_ulong ptr, uint64_t val)
779
+void cpu_stq_be_data(CPUArchState *env, target_ulong ptr, uint64_t val)
780
{
781
- cpu_stq_data_ra(env, ptr, val, 0);
782
+ cpu_stq_be_data_ra(env, ptr, val, 0);
783
+}
784
+
785
+void cpu_stw_le_data(CPUArchState *env, target_ulong ptr, uint32_t val)
786
+{
787
+ cpu_stw_le_data_ra(env, ptr, val, 0);
788
+}
789
+
790
+void cpu_stl_le_data(CPUArchState *env, target_ulong ptr, uint32_t val)
791
+{
792
+ cpu_stl_le_data_ra(env, ptr, val, 0);
793
+}
794
+
795
+void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val)
796
+{
797
+ cpu_stq_le_data_ra(env, ptr, val, 0);
798
}
799
800
/* First set of helpers allows passing in of OI and RETADDR. This makes
801
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
802
index XXXXXXX..XXXXXXX 100644
803
--- a/accel/tcg/user-exec.c
804
+++ b/accel/tcg/user-exec.c
805
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr)
806
return ret;
807
}
808
809
-uint32_t cpu_lduw_data(CPUArchState *env, abi_ptr ptr)
810
+uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr)
811
{
812
uint32_t ret;
813
- uint16_t meminfo = trace_mem_get_info(MO_TEUW, MMU_USER_IDX, false);
814
+ uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, false);
815
816
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
817
- ret = lduw_p(g2h(ptr));
818
+ ret = lduw_be_p(g2h(ptr));
819
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
820
return ret;
821
}
822
823
-int cpu_ldsw_data(CPUArchState *env, abi_ptr ptr)
824
+int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr)
825
{
826
int ret;
827
- uint16_t meminfo = trace_mem_get_info(MO_TESW, MMU_USER_IDX, false);
828
+ uint16_t meminfo = trace_mem_get_info(MO_BESW, MMU_USER_IDX, false);
829
830
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
831
- ret = ldsw_p(g2h(ptr));
832
+ ret = ldsw_be_p(g2h(ptr));
833
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
834
return ret;
835
}
836
837
-uint32_t cpu_ldl_data(CPUArchState *env, abi_ptr ptr)
838
+uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
839
{
840
uint32_t ret;
841
- uint16_t meminfo = trace_mem_get_info(MO_TEUL, MMU_USER_IDX, false);
842
+ uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, false);
843
844
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
845
- ret = ldl_p(g2h(ptr));
846
+ ret = ldl_be_p(g2h(ptr));
847
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
848
return ret;
849
}
850
851
-uint64_t cpu_ldq_data(CPUArchState *env, abi_ptr ptr)
852
+uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr)
853
{
854
uint64_t ret;
855
- uint16_t meminfo = trace_mem_get_info(MO_TEQ, MMU_USER_IDX, false);
856
+ uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, false);
857
858
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
859
- ret = ldq_p(g2h(ptr));
860
+ ret = ldq_be_p(g2h(ptr));
861
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
862
+ return ret;
863
+}
864
+
865
+uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr)
866
+{
867
+ uint32_t ret;
868
+ uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, false);
869
+
870
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
871
+ ret = lduw_le_p(g2h(ptr));
872
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
873
+ return ret;
874
+}
875
+
876
+int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr)
877
+{
878
+ int ret;
879
+ uint16_t meminfo = trace_mem_get_info(MO_LESW, MMU_USER_IDX, false);
880
+
881
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
882
+ ret = ldsw_le_p(g2h(ptr));
883
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
884
+ return ret;
885
+}
886
+
887
+uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
888
+{
889
+ uint32_t ret;
890
+ uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, false);
891
+
892
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
893
+ ret = ldl_le_p(g2h(ptr));
894
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
895
+ return ret;
896
+}
897
+
898
+uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr)
899
+{
900
+ uint64_t ret;
901
+ uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, false);
902
+
903
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
904
+ ret = ldq_le_p(g2h(ptr));
905
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
906
return ret;
907
}
908
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
909
return ret;
910
}
911
912
-uint32_t cpu_lduw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
913
+uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
914
{
915
uint32_t ret;
916
917
set_helper_retaddr(retaddr);
918
- ret = cpu_lduw_data(env, ptr);
919
+ ret = cpu_lduw_be_data(env, ptr);
920
clear_helper_retaddr();
921
return ret;
922
}
923
924
-int cpu_ldsw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
925
+int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
926
{
927
int ret;
928
929
set_helper_retaddr(retaddr);
930
- ret = cpu_ldsw_data(env, ptr);
931
+ ret = cpu_ldsw_be_data(env, ptr);
932
clear_helper_retaddr();
933
return ret;
934
}
935
936
-uint32_t cpu_ldl_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
937
+uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
938
{
939
uint32_t ret;
940
941
set_helper_retaddr(retaddr);
942
- ret = cpu_ldl_data(env, ptr);
943
+ ret = cpu_ldl_be_data(env, ptr);
944
clear_helper_retaddr();
945
return ret;
946
}
947
948
-uint64_t cpu_ldq_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
949
+uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
950
{
951
uint64_t ret;
952
953
set_helper_retaddr(retaddr);
954
- ret = cpu_ldq_data(env, ptr);
955
+ ret = cpu_ldq_be_data(env, ptr);
956
+ clear_helper_retaddr();
957
+ return ret;
958
+}
959
+
960
+uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
961
+{
962
+ uint32_t ret;
963
+
964
+ set_helper_retaddr(retaddr);
965
+ ret = cpu_lduw_le_data(env, ptr);
966
+ clear_helper_retaddr();
967
+ return ret;
968
+}
969
+
970
+int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
971
+{
972
+ int ret;
973
+
974
+ set_helper_retaddr(retaddr);
975
+ ret = cpu_ldsw_le_data(env, ptr);
976
+ clear_helper_retaddr();
977
+ return ret;
978
+}
979
+
980
+uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
981
+{
982
+ uint32_t ret;
983
+
984
+ set_helper_retaddr(retaddr);
985
+ ret = cpu_ldl_le_data(env, ptr);
986
+ clear_helper_retaddr();
987
+ return ret;
988
+}
989
+
990
+uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
991
+{
992
+ uint64_t ret;
993
+
994
+ set_helper_retaddr(retaddr);
995
+ ret = cpu_ldq_le_data(env, ptr);
996
clear_helper_retaddr();
997
return ret;
998
}
999
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1000
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1001
}
1002
1003
-void cpu_stw_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1004
+void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1005
{
1006
- uint16_t meminfo = trace_mem_get_info(MO_TEUW, MMU_USER_IDX, true);
1007
+ uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, true);
1008
1009
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1010
- stw_p(g2h(ptr), val);
1011
+ stw_be_p(g2h(ptr), val);
1012
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1013
}
1014
1015
-void cpu_stl_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1016
+void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1017
{
1018
- uint16_t meminfo = trace_mem_get_info(MO_TEUL, MMU_USER_IDX, true);
1019
+ uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, true);
1020
1021
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1022
- stl_p(g2h(ptr), val);
1023
+ stl_be_p(g2h(ptr), val);
1024
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1025
}
1026
1027
-void cpu_stq_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
1028
+void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
1029
{
1030
- uint16_t meminfo = trace_mem_get_info(MO_TEQ, MMU_USER_IDX, true);
1031
+ uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, true);
1032
1033
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1034
- stq_p(g2h(ptr), val);
1035
+ stq_be_p(g2h(ptr), val);
1036
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1037
+}
1038
+
1039
+void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1040
+{
1041
+ uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, true);
1042
+
1043
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1044
+ stw_le_p(g2h(ptr), val);
1045
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1046
+}
1047
+
1048
+void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1049
+{
1050
+ uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, true);
1051
+
1052
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1053
+ stl_le_p(g2h(ptr), val);
1054
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1055
+}
1056
+
1057
+void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
1058
+{
1059
+ uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, true);
1060
+
1061
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1062
+ stq_le_p(g2h(ptr), val);
1063
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1064
}
1065
1066
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
1067
clear_helper_retaddr();
1068
}
1069
1070
-void cpu_stw_data_ra(CPUArchState *env, abi_ptr ptr,
1071
- uint32_t val, uintptr_t retaddr)
1072
+void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
1073
+ uint32_t val, uintptr_t retaddr)
1074
{
1075
set_helper_retaddr(retaddr);
1076
- cpu_stw_data(env, ptr, val);
1077
+ cpu_stw_be_data(env, ptr, val);
1078
clear_helper_retaddr();
1079
}
1080
1081
-void cpu_stl_data_ra(CPUArchState *env, abi_ptr ptr,
1082
- uint32_t val, uintptr_t retaddr)
1083
+void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
1084
+ uint32_t val, uintptr_t retaddr)
1085
{
1086
set_helper_retaddr(retaddr);
1087
- cpu_stl_data(env, ptr, val);
1088
+ cpu_stl_be_data(env, ptr, val);
1089
clear_helper_retaddr();
1090
}
1091
1092
-void cpu_stq_data_ra(CPUArchState *env, abi_ptr ptr,
1093
- uint64_t val, uintptr_t retaddr)
1094
+void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
1095
+ uint64_t val, uintptr_t retaddr)
1096
{
1097
set_helper_retaddr(retaddr);
1098
- cpu_stq_data(env, ptr, val);
1099
+ cpu_stq_be_data(env, ptr, val);
1100
+ clear_helper_retaddr();
1101
+}
1102
+
1103
+void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
1104
+ uint32_t val, uintptr_t retaddr)
1105
+{
1106
+ set_helper_retaddr(retaddr);
1107
+ cpu_stw_le_data(env, ptr, val);
1108
+ clear_helper_retaddr();
1109
+}
1110
+
1111
+void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
1112
+ uint32_t val, uintptr_t retaddr)
1113
+{
1114
+ set_helper_retaddr(retaddr);
1115
+ cpu_stl_le_data(env, ptr, val);
1116
+ clear_helper_retaddr();
1117
+}
1118
+
1119
+void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
1120
+ uint64_t val, uintptr_t retaddr)
1121
+{
1122
+ set_helper_retaddr(retaddr);
1123
+ cpu_stq_le_data(env, ptr, val);
1124
clear_helper_retaddr();
1125
}
1126
1127
--
1128
2.20.1
1129
1130
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Use the "normal" memory access functions, rather than the
4
softmmu internal helper functions directly.
5
6
Since fb901c905dc3, cpu_mem_index is now a simple extract
7
from env->hflags and not a large computation. Which means
8
that it's now more work to pass around this value than it
9
is to recompute it.
10
11
This only adjusts the primitives, and does not clean up
12
all of the uses within sve_helper.c.
13
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 20200508154359.7494-8-richard.henderson@linaro.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
target/arm/sve_helper.c | 221 ++++++++++++++++------------------------
20
1 file changed, 86 insertions(+), 135 deletions(-)
21
22
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/sve_helper.c
25
+++ b/target/arm/sve_helper.c
26
@@ -XXX,XX +XXX,XX @@ typedef intptr_t sve_ld1_host_fn(void *vd, void *vg, void *host,
27
* Load one element into @vd + @reg_off from (@env, @vaddr, @ra).
28
* The controlling predicate is known to be true.
29
*/
30
-typedef void sve_ld1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
31
- target_ulong vaddr, TCGMemOpIdx oi, uintptr_t ra);
32
-typedef sve_ld1_tlb_fn sve_st1_tlb_fn;
33
+typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
34
+ target_ulong vaddr, uintptr_t retaddr);
35
36
/*
37
* Generate the above primitives.
38
@@ -XXX,XX +XXX,XX @@ static intptr_t sve_##NAME##_host(void *vd, void *vg, void *host, \
39
return mem_off; \
40
}
41
42
-#ifdef CONFIG_SOFTMMU
43
-#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, HOST, MOEND, TLB) \
44
+#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \
45
static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
46
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
47
+ target_ulong addr, uintptr_t ra) \
48
{ \
49
- TYPEM val = TLB(env, addr, oi, ra); \
50
- *(TYPEE *)(vd + H(reg_off)) = val; \
51
+ *(TYPEE *)(vd + H(reg_off)) = (TYPEM)TLB(env, addr, ra); \
52
}
53
-#else
54
-#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, HOST, MOEND, TLB) \
55
+
56
+#define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \
57
static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
58
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
59
+ target_ulong addr, uintptr_t ra) \
60
{ \
61
- TYPEM val = HOST(g2h(addr)); \
62
- *(TYPEE *)(vd + H(reg_off)) = val; \
63
+ TLB(env, addr, (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); \
64
}
65
-#endif
66
67
#define DO_LD_PRIM_1(NAME, H, TE, TM) \
68
DO_LD_HOST(NAME, H, TE, TM, ldub_p) \
69
- DO_LD_TLB(NAME, H, TE, TM, ldub_p, 0, helper_ret_ldub_mmu)
70
+ DO_LD_TLB(NAME, H, TE, TM, cpu_ldub_data_ra)
71
72
DO_LD_PRIM_1(ld1bb, H1, uint8_t, uint8_t)
73
DO_LD_PRIM_1(ld1bhu, H1_2, uint16_t, uint8_t)
74
@@ -XXX,XX +XXX,XX @@ DO_LD_PRIM_1(ld1bss, H1_4, uint32_t, int8_t)
75
DO_LD_PRIM_1(ld1bdu, , uint64_t, uint8_t)
76
DO_LD_PRIM_1(ld1bds, , uint64_t, int8_t)
77
78
-#define DO_LD_PRIM_2(NAME, end, MOEND, H, TE, TM, PH, PT) \
79
- DO_LD_HOST(NAME##_##end, H, TE, TM, PH##_##end##_p) \
80
- DO_LD_TLB(NAME##_##end, H, TE, TM, PH##_##end##_p, \
81
- MOEND, helper_##end##_##PT##_mmu)
82
+#define DO_ST_PRIM_1(NAME, H, TE, TM) \
83
+ DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra)
84
85
-DO_LD_PRIM_2(ld1hh, le, MO_LE, H1_2, uint16_t, uint16_t, lduw, lduw)
86
-DO_LD_PRIM_2(ld1hsu, le, MO_LE, H1_4, uint32_t, uint16_t, lduw, lduw)
87
-DO_LD_PRIM_2(ld1hss, le, MO_LE, H1_4, uint32_t, int16_t, lduw, lduw)
88
-DO_LD_PRIM_2(ld1hdu, le, MO_LE, , uint64_t, uint16_t, lduw, lduw)
89
-DO_LD_PRIM_2(ld1hds, le, MO_LE, , uint64_t, int16_t, lduw, lduw)
90
+DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t)
91
+DO_ST_PRIM_1(bh, H1_2, uint16_t, uint8_t)
92
+DO_ST_PRIM_1(bs, H1_4, uint32_t, uint8_t)
93
+DO_ST_PRIM_1(bd, , uint64_t, uint8_t)
94
95
-DO_LD_PRIM_2(ld1ss, le, MO_LE, H1_4, uint32_t, uint32_t, ldl, ldul)
96
-DO_LD_PRIM_2(ld1sdu, le, MO_LE, , uint64_t, uint32_t, ldl, ldul)
97
-DO_LD_PRIM_2(ld1sds, le, MO_LE, , uint64_t, int32_t, ldl, ldul)
98
+#define DO_LD_PRIM_2(NAME, H, TE, TM, LD) \
99
+ DO_LD_HOST(ld1##NAME##_be, H, TE, TM, LD##_be_p) \
100
+ DO_LD_HOST(ld1##NAME##_le, H, TE, TM, LD##_le_p) \
101
+ DO_LD_TLB(ld1##NAME##_be, H, TE, TM, cpu_##LD##_be_data_ra) \
102
+ DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra)
103
104
-DO_LD_PRIM_2(ld1dd, le, MO_LE, , uint64_t, uint64_t, ldq, ldq)
105
+#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \
106
+ DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \
107
+ DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra)
108
109
-DO_LD_PRIM_2(ld1hh, be, MO_BE, H1_2, uint16_t, uint16_t, lduw, lduw)
110
-DO_LD_PRIM_2(ld1hsu, be, MO_BE, H1_4, uint32_t, uint16_t, lduw, lduw)
111
-DO_LD_PRIM_2(ld1hss, be, MO_BE, H1_4, uint32_t, int16_t, lduw, lduw)
112
-DO_LD_PRIM_2(ld1hdu, be, MO_BE, , uint64_t, uint16_t, lduw, lduw)
113
-DO_LD_PRIM_2(ld1hds, be, MO_BE, , uint64_t, int16_t, lduw, lduw)
114
+DO_LD_PRIM_2(hh, H1_2, uint16_t, uint16_t, lduw)
115
+DO_LD_PRIM_2(hsu, H1_4, uint32_t, uint16_t, lduw)
116
+DO_LD_PRIM_2(hss, H1_4, uint32_t, int16_t, lduw)
117
+DO_LD_PRIM_2(hdu, , uint64_t, uint16_t, lduw)
118
+DO_LD_PRIM_2(hds, , uint64_t, int16_t, lduw)
119
120
-DO_LD_PRIM_2(ld1ss, be, MO_BE, H1_4, uint32_t, uint32_t, ldl, ldul)
121
-DO_LD_PRIM_2(ld1sdu, be, MO_BE, , uint64_t, uint32_t, ldl, ldul)
122
-DO_LD_PRIM_2(ld1sds, be, MO_BE, , uint64_t, int32_t, ldl, ldul)
123
+DO_ST_PRIM_2(hh, H1_2, uint16_t, uint16_t, stw)
124
+DO_ST_PRIM_2(hs, H1_4, uint32_t, uint16_t, stw)
125
+DO_ST_PRIM_2(hd, , uint64_t, uint16_t, stw)
126
127
-DO_LD_PRIM_2(ld1dd, be, MO_BE, , uint64_t, uint64_t, ldq, ldq)
128
+DO_LD_PRIM_2(ss, H1_4, uint32_t, uint32_t, ldl)
129
+DO_LD_PRIM_2(sdu, , uint64_t, uint32_t, ldl)
130
+DO_LD_PRIM_2(sds, , uint64_t, int32_t, ldl)
131
+
132
+DO_ST_PRIM_2(ss, H1_4, uint32_t, uint32_t, stl)
133
+DO_ST_PRIM_2(sd, , uint64_t, uint32_t, stl)
134
+
135
+DO_LD_PRIM_2(dd, , uint64_t, uint64_t, ldq)
136
+DO_ST_PRIM_2(dd, , uint64_t, uint64_t, stq)
137
138
#undef DO_LD_TLB
139
+#undef DO_ST_TLB
140
#undef DO_LD_HOST
141
#undef DO_LD_PRIM_1
142
+#undef DO_ST_PRIM_1
143
#undef DO_LD_PRIM_2
144
+#undef DO_ST_PRIM_2
145
146
/*
147
* Skip through a sequence of inactive elements in the guarding predicate @vg,
148
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
149
uint32_t desc, const uintptr_t retaddr,
150
const int esz, const int msz,
151
sve_ld1_host_fn *host_fn,
152
- sve_ld1_tlb_fn *tlb_fn)
153
+ sve_ldst1_tlb_fn *tlb_fn)
154
{
155
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
156
const int mmu_idx = get_mmuidx(oi);
157
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
158
* on I/O memory, it may succeed but not bring in the TLB entry.
159
* But even then we have still made forward progress.
160
*/
161
- tlb_fn(env, &scratch, reg_off, addr + mem_off, oi, retaddr);
162
+ tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
163
reg_off += 1 << esz;
164
}
165
#endif
166
@@ -XXX,XX +XXX,XX @@ DO_LD1_2(ld1dd, 3, 3)
167
*/
168
static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
169
uint32_t desc, int size, uintptr_t ra,
170
- sve_ld1_tlb_fn *tlb_fn)
171
+ sve_ldst1_tlb_fn *tlb_fn)
172
{
173
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
174
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
175
intptr_t i, oprsz = simd_oprsz(desc);
176
ARMVectorReg scratch[2] = { };
177
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
178
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
179
do {
180
if (pg & 1) {
181
- tlb_fn(env, &scratch[0], i, addr, oi, ra);
182
- tlb_fn(env, &scratch[1], i, addr + size, oi, ra);
183
+ tlb_fn(env, &scratch[0], i, addr, ra);
184
+ tlb_fn(env, &scratch[1], i, addr + size, ra);
185
}
186
i += size, pg >>= size;
187
addr += 2 * size;
188
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
189
190
static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
191
uint32_t desc, int size, uintptr_t ra,
192
- sve_ld1_tlb_fn *tlb_fn)
193
+ sve_ldst1_tlb_fn *tlb_fn)
194
{
195
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
196
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
197
intptr_t i, oprsz = simd_oprsz(desc);
198
ARMVectorReg scratch[3] = { };
199
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
200
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
201
do {
202
if (pg & 1) {
203
- tlb_fn(env, &scratch[0], i, addr, oi, ra);
204
- tlb_fn(env, &scratch[1], i, addr + size, oi, ra);
205
- tlb_fn(env, &scratch[2], i, addr + 2 * size, oi, ra);
206
+ tlb_fn(env, &scratch[0], i, addr, ra);
207
+ tlb_fn(env, &scratch[1], i, addr + size, ra);
208
+ tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
209
}
210
i += size, pg >>= size;
211
addr += 3 * size;
212
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
213
214
static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
215
uint32_t desc, int size, uintptr_t ra,
216
- sve_ld1_tlb_fn *tlb_fn)
217
+ sve_ldst1_tlb_fn *tlb_fn)
218
{
219
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
220
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
221
intptr_t i, oprsz = simd_oprsz(desc);
222
ARMVectorReg scratch[4] = { };
223
@@ -XXX,XX +XXX,XX @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
224
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
225
do {
226
if (pg & 1) {
227
- tlb_fn(env, &scratch[0], i, addr, oi, ra);
228
- tlb_fn(env, &scratch[1], i, addr + size, oi, ra);
229
- tlb_fn(env, &scratch[2], i, addr + 2 * size, oi, ra);
230
- tlb_fn(env, &scratch[3], i, addr + 3 * size, oi, ra);
231
+ tlb_fn(env, &scratch[0], i, addr, ra);
232
+ tlb_fn(env, &scratch[1], i, addr + size, ra);
233
+ tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
234
+ tlb_fn(env, &scratch[3], i, addr + 3 * size, ra);
235
}
236
i += size, pg >>= size;
237
addr += 4 * size;
238
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
239
uint32_t desc, const uintptr_t retaddr,
240
const int esz, const int msz,
241
sve_ld1_host_fn *host_fn,
242
- sve_ld1_tlb_fn *tlb_fn)
243
+ sve_ldst1_tlb_fn *tlb_fn)
244
{
245
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
246
const int mmu_idx = get_mmuidx(oi);
247
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
248
* Perform one normal read, which will fault or not.
249
* But it is likely to bring the page into the tlb.
250
*/
251
- tlb_fn(env, vd, reg_off, addr + mem_off, oi, retaddr);
252
+ tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
253
254
/* After any fault, zero any leading predicated false elts. */
255
swap_memzero(vd, reg_off);
256
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_LDNF1_2(dd, 3, 3)
257
#undef DO_LDFF1_LDNF1_1
258
#undef DO_LDFF1_LDNF1_2
259
260
-/*
261
- * Store contiguous data, protected by a governing predicate.
262
- */
263
-
264
-#ifdef CONFIG_SOFTMMU
265
-#define DO_ST_TLB(NAME, H, TYPEM, HOST, MOEND, TLB) \
266
-static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
267
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
268
-{ \
269
- TLB(env, addr, *(TYPEM *)(vd + H(reg_off)), oi, ra); \
270
-}
271
-#else
272
-#define DO_ST_TLB(NAME, H, TYPEM, HOST, MOEND, TLB) \
273
-static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
274
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
275
-{ \
276
- HOST(g2h(addr), *(TYPEM *)(vd + H(reg_off))); \
277
-}
278
-#endif
279
-
280
-DO_ST_TLB(st1bb, H1, uint8_t, stb_p, 0, helper_ret_stb_mmu)
281
-DO_ST_TLB(st1bh, H1_2, uint16_t, stb_p, 0, helper_ret_stb_mmu)
282
-DO_ST_TLB(st1bs, H1_4, uint32_t, stb_p, 0, helper_ret_stb_mmu)
283
-DO_ST_TLB(st1bd, , uint64_t, stb_p, 0, helper_ret_stb_mmu)
284
-
285
-DO_ST_TLB(st1hh_le, H1_2, uint16_t, stw_le_p, MO_LE, helper_le_stw_mmu)
286
-DO_ST_TLB(st1hs_le, H1_4, uint32_t, stw_le_p, MO_LE, helper_le_stw_mmu)
287
-DO_ST_TLB(st1hd_le, , uint64_t, stw_le_p, MO_LE, helper_le_stw_mmu)
288
-
289
-DO_ST_TLB(st1ss_le, H1_4, uint32_t, stl_le_p, MO_LE, helper_le_stl_mmu)
290
-DO_ST_TLB(st1sd_le, , uint64_t, stl_le_p, MO_LE, helper_le_stl_mmu)
291
-
292
-DO_ST_TLB(st1dd_le, , uint64_t, stq_le_p, MO_LE, helper_le_stq_mmu)
293
-
294
-DO_ST_TLB(st1hh_be, H1_2, uint16_t, stw_be_p, MO_BE, helper_be_stw_mmu)
295
-DO_ST_TLB(st1hs_be, H1_4, uint32_t, stw_be_p, MO_BE, helper_be_stw_mmu)
296
-DO_ST_TLB(st1hd_be, , uint64_t, stw_be_p, MO_BE, helper_be_stw_mmu)
297
-
298
-DO_ST_TLB(st1ss_be, H1_4, uint32_t, stl_be_p, MO_BE, helper_be_stl_mmu)
299
-DO_ST_TLB(st1sd_be, , uint64_t, stl_be_p, MO_BE, helper_be_stl_mmu)
300
-
301
-DO_ST_TLB(st1dd_be, , uint64_t, stq_be_p, MO_BE, helper_be_stq_mmu)
302
-
303
-#undef DO_ST_TLB
304
-
305
/*
306
* Common helpers for all contiguous 1,2,3,4-register predicated stores.
307
*/
308
static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
309
uint32_t desc, const uintptr_t ra,
310
const int esize, const int msize,
311
- sve_st1_tlb_fn *tlb_fn)
312
+ sve_ldst1_tlb_fn *tlb_fn)
313
{
314
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
315
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
316
intptr_t i, oprsz = simd_oprsz(desc);
317
void *vd = &env->vfp.zregs[rd];
318
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
319
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
320
do {
321
if (pg & 1) {
322
- tlb_fn(env, vd, i, addr, oi, ra);
323
+ tlb_fn(env, vd, i, addr, ra);
324
}
325
i += esize, pg >>= esize;
326
addr += msize;
327
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
328
static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
329
uint32_t desc, const uintptr_t ra,
330
const int esize, const int msize,
331
- sve_st1_tlb_fn *tlb_fn)
332
+ sve_ldst1_tlb_fn *tlb_fn)
333
{
334
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
335
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
336
intptr_t i, oprsz = simd_oprsz(desc);
337
void *d1 = &env->vfp.zregs[rd];
338
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
339
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
340
do {
341
if (pg & 1) {
342
- tlb_fn(env, d1, i, addr, oi, ra);
343
- tlb_fn(env, d2, i, addr + msize, oi, ra);
344
+ tlb_fn(env, d1, i, addr, ra);
345
+ tlb_fn(env, d2, i, addr + msize, ra);
346
}
347
i += esize, pg >>= esize;
348
addr += 2 * msize;
349
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
350
static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
351
uint32_t desc, const uintptr_t ra,
352
const int esize, const int msize,
353
- sve_st1_tlb_fn *tlb_fn)
354
+ sve_ldst1_tlb_fn *tlb_fn)
355
{
356
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
357
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
358
intptr_t i, oprsz = simd_oprsz(desc);
359
void *d1 = &env->vfp.zregs[rd];
360
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
361
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
362
do {
363
if (pg & 1) {
364
- tlb_fn(env, d1, i, addr, oi, ra);
365
- tlb_fn(env, d2, i, addr + msize, oi, ra);
366
- tlb_fn(env, d3, i, addr + 2 * msize, oi, ra);
367
+ tlb_fn(env, d1, i, addr, ra);
368
+ tlb_fn(env, d2, i, addr + msize, ra);
369
+ tlb_fn(env, d3, i, addr + 2 * msize, ra);
370
}
371
i += esize, pg >>= esize;
372
addr += 3 * msize;
373
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
374
static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
375
uint32_t desc, const uintptr_t ra,
376
const int esize, const int msize,
377
- sve_st1_tlb_fn *tlb_fn)
378
+ sve_ldst1_tlb_fn *tlb_fn)
379
{
380
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
381
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
382
intptr_t i, oprsz = simd_oprsz(desc);
383
void *d1 = &env->vfp.zregs[rd];
384
@@ -XXX,XX +XXX,XX @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
385
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
386
do {
387
if (pg & 1) {
388
- tlb_fn(env, d1, i, addr, oi, ra);
389
- tlb_fn(env, d2, i, addr + msize, oi, ra);
390
- tlb_fn(env, d3, i, addr + 2 * msize, oi, ra);
391
- tlb_fn(env, d4, i, addr + 3 * msize, oi, ra);
392
+ tlb_fn(env, d1, i, addr, ra);
393
+ tlb_fn(env, d2, i, addr + msize, ra);
394
+ tlb_fn(env, d3, i, addr + 2 * msize, ra);
395
+ tlb_fn(env, d4, i, addr + 3 * msize, ra);
396
}
397
i += esize, pg >>= esize;
398
addr += 4 * msize;
399
@@ -XXX,XX +XXX,XX @@ static target_ulong off_zd_d(void *reg, intptr_t reg_ofs)
400
401
static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
402
target_ulong base, uint32_t desc, uintptr_t ra,
403
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
404
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
405
{
406
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
407
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
408
intptr_t i, oprsz = simd_oprsz(desc);
409
ARMVectorReg scratch = { };
410
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
411
do {
412
if (likely(pg & 1)) {
413
target_ulong off = off_fn(vm, i);
414
- tlb_fn(env, &scratch, i, base + (off << scale), oi, ra);
415
+ tlb_fn(env, &scratch, i, base + (off << scale), ra);
416
}
417
i += 4, pg >>= 4;
418
} while (i & 15);
419
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
420
421
static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
422
target_ulong base, uint32_t desc, uintptr_t ra,
423
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
424
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
425
{
426
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
427
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
428
intptr_t i, oprsz = simd_oprsz(desc) / 8;
429
ARMVectorReg scratch = { };
430
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
431
uint8_t pg = *(uint8_t *)(vg + H1(i));
432
if (likely(pg & 1)) {
433
target_ulong off = off_fn(vm, i * 8);
434
- tlb_fn(env, &scratch, i * 8, base + (off << scale), oi, ra);
435
+ tlb_fn(env, &scratch, i * 8, base + (off << scale), ra);
436
}
437
}
438
clear_helper_retaddr();
439
@@ -XXX,XX +XXX,XX @@ DO_LD_NF(dd_be, , uint64_t, uint64_t, ldq_be_p)
440
*/
441
static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
442
target_ulong base, uint32_t desc, uintptr_t ra,
443
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn,
444
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
445
sve_ld1_nf_fn *nonfault_fn)
446
{
447
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
448
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
449
set_helper_retaddr(ra);
450
addr = off_fn(vm, reg_off);
451
addr = base + (addr << scale);
452
- tlb_fn(env, vd, reg_off, addr, oi, ra);
453
+ tlb_fn(env, vd, reg_off, addr, ra);
454
455
/* The rest of the reads will be non-faulting. */
456
clear_helper_retaddr();
457
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
458
459
static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
460
target_ulong base, uint32_t desc, uintptr_t ra,
461
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn,
462
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
463
sve_ld1_nf_fn *nonfault_fn)
464
{
465
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
466
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
467
set_helper_retaddr(ra);
468
addr = off_fn(vm, reg_off);
469
addr = base + (addr << scale);
470
- tlb_fn(env, vd, reg_off, addr, oi, ra);
471
+ tlb_fn(env, vd, reg_off, addr, ra);
472
473
/* The rest of the reads will be non-faulting. */
474
clear_helper_retaddr();
475
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_ZPZ_D(dd_be, zd)
476
477
static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
478
target_ulong base, uint32_t desc, uintptr_t ra,
479
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
480
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
481
{
482
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
483
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
484
intptr_t i, oprsz = simd_oprsz(desc);
485
486
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
487
do {
488
if (likely(pg & 1)) {
489
target_ulong off = off_fn(vm, i);
490
- tlb_fn(env, vd, i, base + (off << scale), oi, ra);
491
+ tlb_fn(env, vd, i, base + (off << scale), ra);
492
}
493
i += 4, pg >>= 4;
494
} while (i & 15);
495
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
496
497
static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
498
target_ulong base, uint32_t desc, uintptr_t ra,
499
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
500
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
501
{
502
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
503
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
504
intptr_t i, oprsz = simd_oprsz(desc) / 8;
505
506
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
507
uint8_t pg = *(uint8_t *)(vg + H1(i));
508
if (likely(pg & 1)) {
509
target_ulong off = off_fn(vm, i * 8);
510
- tlb_fn(env, vd, i * 8, base + (off << scale), oi, ra);
511
+ tlb_fn(env, vd, i * 8, base + (off << scale), ra);
512
}
513
}
514
clear_helper_retaddr();
515
--
516
2.20.1
517
518
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Since we converted back to cpu_*_data_ra, we do not need to
4
do this ourselves.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200508154359.7494-9-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/sve_helper.c | 38 --------------------------------------
12
1 file changed, 38 deletions(-)
13
14
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/sve_helper.c
17
+++ b/target/arm/sve_helper.c
18
@@ -XXX,XX +XXX,XX @@ static intptr_t max_for_page(target_ulong base, intptr_t mem_off,
19
return MIN(split, mem_max - mem_off) + mem_off;
20
}
21
22
-#ifndef CONFIG_USER_ONLY
23
-/* These are normally defined only for CONFIG_USER_ONLY in <exec/cpu_ldst.h> */
24
-static inline void set_helper_retaddr(uintptr_t ra) { }
25
-static inline void clear_helper_retaddr(void) { }
26
-#endif
27
-
28
/*
29
* The result of tlb_vaddr_to_host for user-only is just g2h(x),
30
* which is always non-null. Elide the useless test.
31
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
32
return;
33
}
34
mem_off = reg_off >> diffsz;
35
- set_helper_retaddr(retaddr);
36
37
/*
38
* If the (remaining) load is entirely within a single page, then:
39
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
40
if (test_host_page(host)) {
41
mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
42
tcg_debug_assert(mem_off == mem_max);
43
- clear_helper_retaddr();
44
/* After having taken any fault, zero leading inactive elements. */
45
swap_memzero(vd, reg_off);
46
return;
47
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
48
}
49
#endif
50
51
- clear_helper_retaddr();
52
memcpy(vd, &scratch, reg_max);
53
}
54
55
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
56
intptr_t i, oprsz = simd_oprsz(desc);
57
ARMVectorReg scratch[2] = { };
58
59
- set_helper_retaddr(ra);
60
for (i = 0; i < oprsz; ) {
61
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
62
do {
63
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
64
addr += 2 * size;
65
} while (i & 15);
66
}
67
- clear_helper_retaddr();
68
69
/* Wait until all exceptions have been raised to write back. */
70
memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
71
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
72
intptr_t i, oprsz = simd_oprsz(desc);
73
ARMVectorReg scratch[3] = { };
74
75
- set_helper_retaddr(ra);
76
for (i = 0; i < oprsz; ) {
77
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
78
do {
79
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
80
addr += 3 * size;
81
} while (i & 15);
82
}
83
- clear_helper_retaddr();
84
85
/* Wait until all exceptions have been raised to write back. */
86
memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
87
@@ -XXX,XX +XXX,XX @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
88
intptr_t i, oprsz = simd_oprsz(desc);
89
ARMVectorReg scratch[4] = { };
90
91
- set_helper_retaddr(ra);
92
for (i = 0; i < oprsz; ) {
93
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
94
do {
95
@@ -XXX,XX +XXX,XX @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
96
addr += 4 * size;
97
} while (i & 15);
98
}
99
- clear_helper_retaddr();
100
101
/* Wait until all exceptions have been raised to write back. */
102
memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
103
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
104
return;
105
}
106
mem_off = reg_off >> diffsz;
107
- set_helper_retaddr(retaddr);
108
109
/*
110
* If the (remaining) load is entirely within a single page, then:
111
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
112
if (test_host_page(host)) {
113
mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
114
tcg_debug_assert(mem_off == mem_max);
115
- clear_helper_retaddr();
116
/* After any fault, zero any leading inactive elements. */
117
swap_memzero(vd, reg_off);
118
return;
119
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
120
}
121
#endif
122
123
- clear_helper_retaddr();
124
record_fault(env, reg_off, reg_max);
125
}
126
127
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
128
intptr_t i, oprsz = simd_oprsz(desc);
129
void *vd = &env->vfp.zregs[rd];
130
131
- set_helper_retaddr(ra);
132
for (i = 0; i < oprsz; ) {
133
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
134
do {
135
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
136
addr += msize;
137
} while (i & 15);
138
}
139
- clear_helper_retaddr();
140
}
141
142
static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
143
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
144
void *d1 = &env->vfp.zregs[rd];
145
void *d2 = &env->vfp.zregs[(rd + 1) & 31];
146
147
- set_helper_retaddr(ra);
148
for (i = 0; i < oprsz; ) {
149
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
150
do {
151
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
152
addr += 2 * msize;
153
} while (i & 15);
154
}
155
- clear_helper_retaddr();
156
}
157
158
static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
159
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
160
void *d2 = &env->vfp.zregs[(rd + 1) & 31];
161
void *d3 = &env->vfp.zregs[(rd + 2) & 31];
162
163
- set_helper_retaddr(ra);
164
for (i = 0; i < oprsz; ) {
165
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
166
do {
167
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
168
addr += 3 * msize;
169
} while (i & 15);
170
}
171
- clear_helper_retaddr();
172
}
173
174
static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
175
@@ -XXX,XX +XXX,XX @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
176
void *d3 = &env->vfp.zregs[(rd + 2) & 31];
177
void *d4 = &env->vfp.zregs[(rd + 3) & 31];
178
179
- set_helper_retaddr(ra);
180
for (i = 0; i < oprsz; ) {
181
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
182
do {
183
@@ -XXX,XX +XXX,XX @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
184
addr += 4 * msize;
185
} while (i & 15);
186
}
187
- clear_helper_retaddr();
188
}
189
190
#define DO_STN_1(N, NAME, ESIZE) \
191
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
192
intptr_t i, oprsz = simd_oprsz(desc);
193
ARMVectorReg scratch = { };
194
195
- set_helper_retaddr(ra);
196
for (i = 0; i < oprsz; ) {
197
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
198
do {
199
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
200
i += 4, pg >>= 4;
201
} while (i & 15);
202
}
203
- clear_helper_retaddr();
204
205
/* Wait until all exceptions have been raised to write back. */
206
memcpy(vd, &scratch, oprsz);
207
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
208
intptr_t i, oprsz = simd_oprsz(desc) / 8;
209
ARMVectorReg scratch = { };
210
211
- set_helper_retaddr(ra);
212
for (i = 0; i < oprsz; i++) {
213
uint8_t pg = *(uint8_t *)(vg + H1(i));
214
if (likely(pg & 1)) {
215
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
216
tlb_fn(env, &scratch, i * 8, base + (off << scale), ra);
217
}
218
}
219
- clear_helper_retaddr();
220
221
/* Wait until all exceptions have been raised to write back. */
222
memcpy(vd, &scratch, oprsz * 8);
223
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
224
reg_off = find_next_active(vg, 0, reg_max, MO_32);
225
if (likely(reg_off < reg_max)) {
226
/* Perform one normal read, which will fault or not. */
227
- set_helper_retaddr(ra);
228
addr = off_fn(vm, reg_off);
229
addr = base + (addr << scale);
230
tlb_fn(env, vd, reg_off, addr, ra);
231
232
/* The rest of the reads will be non-faulting. */
233
- clear_helper_retaddr();
234
}
235
236
/* After any fault, zero the leading predicated false elements. */
237
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
238
reg_off = find_next_active(vg, 0, reg_max, MO_64);
239
if (likely(reg_off < reg_max)) {
240
/* Perform one normal read, which will fault or not. */
241
- set_helper_retaddr(ra);
242
addr = off_fn(vm, reg_off);
243
addr = base + (addr << scale);
244
tlb_fn(env, vd, reg_off, addr, ra);
245
246
/* The rest of the reads will be non-faulting. */
247
- clear_helper_retaddr();
248
}
249
250
/* After any fault, zero the leading predicated false elements. */
251
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
252
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
253
intptr_t i, oprsz = simd_oprsz(desc);
254
255
- set_helper_retaddr(ra);
256
for (i = 0; i < oprsz; ) {
257
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
258
do {
259
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
260
i += 4, pg >>= 4;
261
} while (i & 15);
262
}
263
- clear_helper_retaddr();
264
}
265
266
static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
267
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
268
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
269
intptr_t i, oprsz = simd_oprsz(desc) / 8;
270
271
- set_helper_retaddr(ra);
272
for (i = 0; i < oprsz; i++) {
273
uint8_t pg = *(uint8_t *)(vg + H1(i));
274
if (likely(pg & 1)) {
275
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
276
tlb_fn(env, vd, i * 8, base + (off << scale), ra);
277
}
278
}
279
- clear_helper_retaddr();
280
}
281
282
#define DO_ST1_ZPZ_S(MEM, OFS) \
283
--
284
2.20.1
285
286
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
For contiguous predicated memory operations, we want to
4
minimize the number of tlb lookups performed. We have
5
open-coded this for sve_ld1_r, but for correctness with
6
MTE we will need this for all of the memory operations.
7
8
Create a structure that holds the bounds of active elements,
9
and metadata for two pages. Add routines to find those
10
active elements, lookup the pages, and run watchpoints
11
for those pages.
12
13
Temporarily mark the functions unused to avoid Werror.
14
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20200508154359.7494-10-richard.henderson@linaro.org
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
target/arm/sve_helper.c | 263 +++++++++++++++++++++++++++++++++++++++-
21
1 file changed, 261 insertions(+), 2 deletions(-)
22
23
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/sve_helper.c
26
+++ b/target/arm/sve_helper.c
27
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_cpy_z_d)(void *vd, void *vg, uint64_t val, uint32_t desc)
28
}
29
}
30
31
-/* Big-endian hosts need to frob the byte indicies. If the copy
32
+/* Big-endian hosts need to frob the byte indices. If the copy
33
* happens to be 8-byte aligned, then no frobbing necessary.
34
*/
35
static void swap_memmove(void *vd, void *vs, size_t n)
36
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
37
/*
38
* Load elements into @vd, controlled by @vg, from @host + @mem_ofs.
39
* Memory is valid through @host + @mem_max. The register element
40
- * indicies are inferred from @mem_ofs, as modified by the types for
41
+ * indices are inferred from @mem_ofs, as modified by the types for
42
* which the helper is built. Return the @mem_ofs of the first element
43
* not loaded (which is @mem_max if they are all loaded).
44
*
45
@@ -XXX,XX +XXX,XX @@ static intptr_t max_for_page(target_ulong base, intptr_t mem_off,
46
return MIN(split, mem_max - mem_off) + mem_off;
47
}
48
49
+/*
50
+ * Resolve the guest virtual address to info->host and info->flags.
51
+ * If @nofault, return false if the page is invalid, otherwise
52
+ * exit via page fault exception.
53
+ */
54
+
55
+typedef struct {
56
+ void *host;
57
+ int flags;
58
+ MemTxAttrs attrs;
59
+} SVEHostPage;
60
+
61
+static bool sve_probe_page(SVEHostPage *info, bool nofault,
62
+ CPUARMState *env, target_ulong addr,
63
+ int mem_off, MMUAccessType access_type,
64
+ int mmu_idx, uintptr_t retaddr)
65
+{
66
+ int flags;
67
+
68
+ addr += mem_off;
69
+ flags = probe_access_flags(env, addr, access_type, mmu_idx, nofault,
70
+ &info->host, retaddr);
71
+ info->flags = flags;
72
+
73
+ if (flags & TLB_INVALID_MASK) {
74
+ g_assert(nofault);
75
+ return false;
76
+ }
77
+
78
+ /* Ensure that info->host[] is relative to addr, not addr + mem_off. */
79
+ info->host -= mem_off;
80
+
81
+#ifdef CONFIG_USER_ONLY
82
+ memset(&info->attrs, 0, sizeof(info->attrs));
83
+#else
84
+ /*
85
+ * Find the iotlbentry for addr and return the transaction attributes.
86
+ * This *must* be present in the TLB because we just found the mapping.
87
+ */
88
+ {
89
+ uintptr_t index = tlb_index(env, mmu_idx, addr);
90
+
91
+# ifdef CONFIG_DEBUG_TCG
92
+ CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
93
+ target_ulong comparator = (access_type == MMU_DATA_LOAD
94
+ ? entry->addr_read
95
+ : tlb_addr_write(entry));
96
+ g_assert(tlb_hit(comparator, addr));
97
+# endif
98
+
99
+ CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
100
+ info->attrs = iotlbentry->attrs;
101
+ }
102
+#endif
103
+
104
+ return true;
105
+}
106
+
107
+
108
+/*
109
+ * Analyse contiguous data, protected by a governing predicate.
110
+ */
111
+
112
+typedef enum {
113
+ FAULT_NO,
114
+ FAULT_FIRST,
115
+ FAULT_ALL,
116
+} SVEContFault;
117
+
118
+typedef struct {
119
+ /*
120
+ * First and last element wholly contained within the two pages.
121
+ * mem_off_first[0] and reg_off_first[0] are always set >= 0.
122
+ * reg_off_last[0] may be < 0 if the first element crosses pages.
123
+ * All of mem_off_first[1], reg_off_first[1] and reg_off_last[1]
124
+ * are set >= 0 only if there are complete elements on a second page.
125
+ *
126
+ * The reg_off_* offsets are relative to the internal vector register.
127
+ * The mem_off_first offset is relative to the memory address; the
128
+ * two offsets are different when a load operation extends, a store
129
+ * operation truncates, or for multi-register operations.
130
+ */
131
+ int16_t mem_off_first[2];
132
+ int16_t reg_off_first[2];
133
+ int16_t reg_off_last[2];
134
+
135
+ /*
136
+ * One element that is misaligned and spans both pages,
137
+ * or -1 if there is no such active element.
138
+ */
139
+ int16_t mem_off_split;
140
+ int16_t reg_off_split;
141
+
142
+ /*
143
+ * The byte offset at which the entire operation crosses a page boundary.
144
+ * Set >= 0 if and only if the entire operation spans two pages.
145
+ */
146
+ int16_t page_split;
147
+
148
+ /* TLB data for the two pages. */
149
+ SVEHostPage page[2];
150
+} SVEContLdSt;
151
+
152
+/*
153
+ * Find first active element on each page, and a loose bound for the
154
+ * final element on each page. Identify any single element that spans
155
+ * the page boundary. Return true if there are any active elements.
156
+ */
157
+static bool __attribute__((unused))
158
+sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg,
159
+ intptr_t reg_max, int esz, int msize)
160
+{
161
+ const int esize = 1 << esz;
162
+ const uint64_t pg_mask = pred_esz_masks[esz];
163
+ intptr_t reg_off_first = -1, reg_off_last = -1, reg_off_split;
164
+ intptr_t mem_off_last, mem_off_split;
165
+ intptr_t page_split, elt_split;
166
+ intptr_t i;
167
+
168
+ /* Set all of the element indices to -1, and the TLB data to 0. */
169
+ memset(info, -1, offsetof(SVEContLdSt, page));
170
+ memset(info->page, 0, sizeof(info->page));
171
+
172
+ /* Gross scan over the entire predicate to find bounds. */
173
+ i = 0;
174
+ do {
175
+ uint64_t pg = vg[i] & pg_mask;
176
+ if (pg) {
177
+ reg_off_last = i * 64 + 63 - clz64(pg);
178
+ if (reg_off_first < 0) {
179
+ reg_off_first = i * 64 + ctz64(pg);
180
+ }
181
+ }
182
+ } while (++i * 64 < reg_max);
183
+
184
+ if (unlikely(reg_off_first < 0)) {
185
+ /* No active elements, no pages touched. */
186
+ return false;
187
+ }
188
+ tcg_debug_assert(reg_off_last >= 0 && reg_off_last < reg_max);
189
+
190
+ info->reg_off_first[0] = reg_off_first;
191
+ info->mem_off_first[0] = (reg_off_first >> esz) * msize;
192
+ mem_off_last = (reg_off_last >> esz) * msize;
193
+
194
+ page_split = -(addr | TARGET_PAGE_MASK);
195
+ if (likely(mem_off_last + msize <= page_split)) {
196
+ /* The entire operation fits within a single page. */
197
+ info->reg_off_last[0] = reg_off_last;
198
+ return true;
199
+ }
200
+
201
+ info->page_split = page_split;
202
+ elt_split = page_split / msize;
203
+ reg_off_split = elt_split << esz;
204
+ mem_off_split = elt_split * msize;
205
+
206
+ /*
207
+ * This is the last full element on the first page, but it is not
208
+ * necessarily active. If there is no full element, i.e. the first
209
+ * active element is the one that's split, this value remains -1.
210
+ * It is useful as iteration bounds.
211
+ */
212
+ if (elt_split != 0) {
213
+ info->reg_off_last[0] = reg_off_split - esize;
214
+ }
215
+
216
+ /* Determine if an unaligned element spans the pages. */
217
+ if (page_split % msize != 0) {
218
+ /* It is helpful to know if the split element is active. */
219
+ if ((vg[reg_off_split >> 6] >> (reg_off_split & 63)) & 1) {
220
+ info->reg_off_split = reg_off_split;
221
+ info->mem_off_split = mem_off_split;
222
+
223
+ if (reg_off_split == reg_off_last) {
224
+ /* The page crossing element is last. */
225
+ return true;
226
+ }
227
+ }
228
+ reg_off_split += esize;
229
+ mem_off_split += msize;
230
+ }
231
+
232
+ /*
233
+ * We do want the first active element on the second page, because
234
+ * this may affect the address reported in an exception.
235
+ */
236
+ reg_off_split = find_next_active(vg, reg_off_split, reg_max, esz);
237
+ tcg_debug_assert(reg_off_split <= reg_off_last);
238
+ info->reg_off_first[1] = reg_off_split;
239
+ info->mem_off_first[1] = (reg_off_split >> esz) * msize;
240
+ info->reg_off_last[1] = reg_off_last;
241
+ return true;
242
+}
243
+
244
+/*
245
+ * Resolve the guest virtual addresses to info->page[].
246
+ * Control the generation of page faults with @fault. Return false if
247
+ * there is no work to do, which can only happen with @fault == FAULT_NO.
248
+ */
249
+static bool __attribute__((unused))
250
+sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, CPUARMState *env,
251
+ target_ulong addr, MMUAccessType access_type,
252
+ uintptr_t retaddr)
253
+{
254
+ int mmu_idx = cpu_mmu_index(env, false);
255
+ int mem_off = info->mem_off_first[0];
256
+ bool nofault = fault == FAULT_NO;
257
+ bool have_work = true;
258
+
259
+ if (!sve_probe_page(&info->page[0], nofault, env, addr, mem_off,
260
+ access_type, mmu_idx, retaddr)) {
261
+ /* No work to be done. */
262
+ return false;
263
+ }
264
+
265
+ if (likely(info->page_split < 0)) {
266
+ /* The entire operation was on the one page. */
267
+ return true;
268
+ }
269
+
270
+ /*
271
+ * If the second page is invalid, then we want the fault address to be
272
+ * the first byte on that page which is accessed.
273
+ */
274
+ if (info->mem_off_split >= 0) {
275
+ /*
276
+ * There is an element split across the pages. The fault address
277
+ * should be the first byte of the second page.
278
+ */
279
+ mem_off = info->page_split;
280
+ /*
281
+ * If the split element is also the first active element
282
+ * of the vector, then: For first-fault we should continue
283
+ * to generate faults for the second page. For no-fault,
284
+ * we have work only if the second page is valid.
285
+ */
286
+ if (info->mem_off_first[0] < info->mem_off_split) {
287
+ nofault = FAULT_FIRST;
288
+ have_work = false;
289
+ }
290
+ } else {
291
+ /*
292
+ * There is no element split across the pages. The fault address
293
+ * should be the first active element on the second page.
294
+ */
295
+ mem_off = info->mem_off_first[1];
296
+ /*
297
+ * There must have been one active element on the first page,
298
+ * so we're out of first-fault territory.
299
+ */
300
+ nofault = fault != FAULT_ALL;
301
+ }
302
+
303
+ have_work |= sve_probe_page(&info->page[1], nofault, env, addr, mem_off,
304
+ access_type, mmu_idx, retaddr);
305
+ return have_work;
306
+}
307
+
308
/*
309
* The result of tlb_vaddr_to_host for user-only is just g2h(x),
310
* which is always non-null. Elide the useless test.
311
--
312
2.20.1
313
314
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
The current interface includes a loop; change it to load a
4
single element. We will then be able to use the function
5
for ld{2,3,4} where individual vector elements are not adjacent.
6
7
Replace each call with the simplest possible loop over active
8
elements.
9
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200508154359.7494-11-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/sve_helper.c | 124 ++++++++++++++++++++--------------------
16
1 file changed, 63 insertions(+), 61 deletions(-)
17
18
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/sve_helper.c
21
+++ b/target/arm/sve_helper.c
22
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
23
*/
24
25
/*
26
- * Load elements into @vd, controlled by @vg, from @host + @mem_ofs.
27
- * Memory is valid through @host + @mem_max. The register element
28
- * indices are inferred from @mem_ofs, as modified by the types for
29
- * which the helper is built. Return the @mem_ofs of the first element
30
- * not loaded (which is @mem_max if they are all loaded).
31
- *
32
- * For softmmu, we have fully validated the guest page. For user-only,
33
- * we cannot fully validate without taking the mmap lock, but since we
34
- * know the access is within one host page, if any access is valid they
35
- * all must be valid. However, when @vg is all false, it may be that
36
- * no access is valid.
37
+ * Load one element into @vd + @reg_off from @host.
38
+ * The controlling predicate is known to be true.
39
*/
40
-typedef intptr_t sve_ld1_host_fn(void *vd, void *vg, void *host,
41
- intptr_t mem_ofs, intptr_t mem_max);
42
+typedef void sve_ldst1_host_fn(void *vd, intptr_t reg_off, void *host);
43
44
/*
45
* Load one element into @vd + @reg_off from (@env, @vaddr, @ra).
46
@@ -XXX,XX +XXX,XX @@ typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
47
*/
48
49
#define DO_LD_HOST(NAME, H, TYPEE, TYPEM, HOST) \
50
-static intptr_t sve_##NAME##_host(void *vd, void *vg, void *host, \
51
- intptr_t mem_off, const intptr_t mem_max) \
52
-{ \
53
- intptr_t reg_off = mem_off * (sizeof(TYPEE) / sizeof(TYPEM)); \
54
- uint64_t *pg = vg; \
55
- while (mem_off + sizeof(TYPEM) <= mem_max) { \
56
- TYPEM val = 0; \
57
- if (likely((pg[reg_off >> 6] >> (reg_off & 63)) & 1)) { \
58
- val = HOST(host + mem_off); \
59
- } \
60
- *(TYPEE *)(vd + H(reg_off)) = val; \
61
- mem_off += sizeof(TYPEM), reg_off += sizeof(TYPEE); \
62
- } \
63
- return mem_off; \
64
+static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
65
+{ \
66
+ TYPEM val = HOST(host); \
67
+ *(TYPEE *)(vd + H(reg_off)) = val; \
68
}
69
70
#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \
71
@@ -XXX,XX +XXX,XX @@ static inline bool test_host_page(void *host)
72
static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
73
uint32_t desc, const uintptr_t retaddr,
74
const int esz, const int msz,
75
- sve_ld1_host_fn *host_fn,
76
+ sve_ldst1_host_fn *host_fn,
77
sve_ldst1_tlb_fn *tlb_fn)
78
{
79
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
80
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
81
if (likely(split == mem_max)) {
82
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
83
if (test_host_page(host)) {
84
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
85
- tcg_debug_assert(mem_off == mem_max);
86
+ intptr_t i = reg_off;
87
+ host -= mem_off;
88
+ do {
89
+ host_fn(vd, i, host + (i >> diffsz));
90
+ i = find_next_active(vg, i + (1 << esz), reg_max, esz);
91
+ } while (i < reg_max);
92
/* After having taken any fault, zero leading inactive elements. */
93
swap_memzero(vd, reg_off);
94
return;
95
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
96
*/
97
#ifdef CONFIG_USER_ONLY
98
swap_memzero(&scratch, reg_off);
99
- host_fn(&scratch, vg, g2h(addr), mem_off, mem_max);
100
+ host = g2h(addr);
101
+ do {
102
+ host_fn(&scratch, reg_off, host + (reg_off >> diffsz));
103
+ reg_off += 1 << esz;
104
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
105
+ } while (reg_off < reg_max);
106
#else
107
memset(&scratch, 0, reg_max);
108
goto start;
109
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
110
host = tlb_vaddr_to_host(env, addr + mem_off,
111
MMU_DATA_LOAD, mmu_idx);
112
if (host) {
113
- mem_off = host_fn(&scratch, vg, host - mem_off,
114
- mem_off, split);
115
- reg_off = mem_off << diffsz;
116
+ host -= mem_off;
117
+ do {
118
+ host_fn(&scratch, reg_off, host + mem_off);
119
+ reg_off += 1 << esz;
120
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
121
+ mem_off = reg_off >> diffsz;
122
+ } while (split - mem_off >= (1 << msz));
123
continue;
124
}
125
}
126
@@ -XXX,XX +XXX,XX @@ static void record_fault(CPUARMState *env, uintptr_t i, uintptr_t oprsz)
127
static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
128
uint32_t desc, const uintptr_t retaddr,
129
const int esz, const int msz,
130
- sve_ld1_host_fn *host_fn,
131
+ sve_ldst1_host_fn *host_fn,
132
sve_ldst1_tlb_fn *tlb_fn)
133
{
134
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
135
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
136
const int diffsz = esz - msz;
137
const intptr_t reg_max = simd_oprsz(desc);
138
const intptr_t mem_max = reg_max >> diffsz;
139
- intptr_t split, reg_off, mem_off;
140
+ intptr_t split, reg_off, mem_off, i;
141
void *host;
142
143
/* Skip to the first active element. */
144
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
145
if (likely(split == mem_max)) {
146
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
147
if (test_host_page(host)) {
148
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
149
- tcg_debug_assert(mem_off == mem_max);
150
+ i = reg_off;
151
+ host -= mem_off;
152
+ do {
153
+ host_fn(vd, i, host + (i >> diffsz));
154
+ i = find_next_active(vg, i + (1 << esz), reg_max, esz);
155
+ } while (i < reg_max);
156
/* After any fault, zero any leading inactive elements. */
157
swap_memzero(vd, reg_off);
158
return;
159
}
160
}
161
162
-#ifdef CONFIG_USER_ONLY
163
- /*
164
- * The page(s) containing this first element at ADDR+MEM_OFF must
165
- * be valid. Considering that this first element may be misaligned
166
- * and cross a page boundary itself, take the rest of the page from
167
- * the last byte of the element.
168
- */
169
- split = max_for_page(addr, mem_off + (1 << msz) - 1, mem_max);
170
- mem_off = host_fn(vd, vg, g2h(addr), mem_off, split);
171
-
172
- /* After any fault, zero any leading inactive elements. */
173
- swap_memzero(vd, reg_off);
174
- reg_off = mem_off << diffsz;
175
-#else
176
/*
177
* Perform one normal read, which will fault or not.
178
* But it is likely to bring the page into the tlb.
179
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
180
if (split >= (1 << msz)) {
181
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
182
if (host) {
183
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, split);
184
- reg_off = mem_off << diffsz;
185
+ host -= mem_off;
186
+ do {
187
+ host_fn(vd, reg_off, host + mem_off);
188
+ reg_off += 1 << esz;
189
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
190
+ mem_off = reg_off >> diffsz;
191
+ } while (split - mem_off >= (1 << msz));
192
}
193
}
194
-#endif
195
196
record_fault(env, reg_off, reg_max);
197
}
198
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
199
*/
200
static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
201
uint32_t desc, const int esz, const int msz,
202
- sve_ld1_host_fn *host_fn)
203
+ sve_ldst1_host_fn *host_fn)
204
{
205
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
206
void *vd = &env->vfp.zregs[rd];
207
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
208
host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_idx);
209
if (likely(page_check_range(addr, mem_max, PAGE_READ) == 0)) {
210
/* The entire operation is valid and will not fault. */
211
- host_fn(vd, vg, host, 0, mem_max);
212
+ reg_off = 0;
213
+ do {
214
+ mem_off = reg_off >> diffsz;
215
+ host_fn(vd, reg_off, host + mem_off);
216
+ reg_off += 1 << esz;
217
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
218
+ } while (reg_off < reg_max);
219
return;
220
}
221
#endif
222
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
223
if (page_check_range(addr + mem_off, 1 << msz, PAGE_READ) == 0) {
224
/* At least one load is valid; take the rest of the page. */
225
split = max_for_page(addr, mem_off + (1 << msz) - 1, mem_max);
226
- mem_off = host_fn(vd, vg, host, mem_off, split);
227
- reg_off = mem_off << diffsz;
228
+ do {
229
+ host_fn(vd, reg_off, host + mem_off);
230
+ reg_off += 1 << esz;
231
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
232
+ mem_off = reg_off >> diffsz;
233
+ } while (split - mem_off >= (1 << msz));
234
}
235
#else
236
/*
237
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
238
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
239
split = max_for_page(addr, mem_off, mem_max);
240
if (host && split >= (1 << msz)) {
241
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, split);
242
- reg_off = mem_off << diffsz;
243
+ host -= mem_off;
244
+ do {
245
+ host_fn(vd, reg_off, host + mem_off);
246
+ reg_off += 1 << esz;
247
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
248
+ mem_off = reg_off >> diffsz;
249
+ } while (split - mem_off >= (1 << msz));
250
}
251
#endif
252
253
--
254
2.20.1
255
256
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
First use of the new helper functions, so we can remove the
4
unused markup. No longer need a scratch for user-only, as
5
we completely probe the page set before reading; system mode
6
still requires a scratch for MMIO.
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-12-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/sve_helper.c | 188 +++++++++++++++++++++-------------------
14
1 file changed, 97 insertions(+), 91 deletions(-)
15
16
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sve_helper.c
19
+++ b/target/arm/sve_helper.c
20
@@ -XXX,XX +XXX,XX @@ typedef struct {
21
* final element on each page. Identify any single element that spans
22
* the page boundary. Return true if there are any active elements.
23
*/
24
-static bool __attribute__((unused))
25
-sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg,
26
- intptr_t reg_max, int esz, int msize)
27
+static bool sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr,
28
+ uint64_t *vg, intptr_t reg_max,
29
+ int esz, int msize)
30
{
31
const int esize = 1 << esz;
32
const uint64_t pg_mask = pred_esz_masks[esz];
33
@@ -XXX,XX +XXX,XX @@ sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg,
34
* Control the generation of page faults with @fault. Return false if
35
* there is no work to do, which can only happen with @fault == FAULT_NO.
36
*/
37
-static bool __attribute__((unused))
38
-sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, CPUARMState *env,
39
- target_ulong addr, MMUAccessType access_type,
40
- uintptr_t retaddr)
41
+static bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault,
42
+ CPUARMState *env, target_ulong addr,
43
+ MMUAccessType access_type, uintptr_t retaddr)
44
{
45
int mmu_idx = cpu_mmu_index(env, false);
46
int mem_off = info->mem_off_first[0];
47
@@ -XXX,XX +XXX,XX @@ static inline bool test_host_page(void *host)
48
/*
49
* Common helper for all contiguous one-register predicated loads.
50
*/
51
-static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
52
- uint32_t desc, const uintptr_t retaddr,
53
- const int esz, const int msz,
54
- sve_ldst1_host_fn *host_fn,
55
- sve_ldst1_tlb_fn *tlb_fn)
56
+static inline QEMU_ALWAYS_INLINE
57
+void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
58
+ uint32_t desc, const uintptr_t retaddr,
59
+ const int esz, const int msz,
60
+ sve_ldst1_host_fn *host_fn,
61
+ sve_ldst1_tlb_fn *tlb_fn)
62
{
63
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
64
- const int mmu_idx = get_mmuidx(oi);
65
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
66
void *vd = &env->vfp.zregs[rd];
67
- const int diffsz = esz - msz;
68
const intptr_t reg_max = simd_oprsz(desc);
69
- const intptr_t mem_max = reg_max >> diffsz;
70
- ARMVectorReg scratch;
71
+ intptr_t reg_off, reg_last, mem_off;
72
+ SVEContLdSt info;
73
void *host;
74
- intptr_t split, reg_off, mem_off;
75
+ int flags;
76
77
- /* Find the first active element. */
78
- reg_off = find_next_active(vg, 0, reg_max, esz);
79
- if (unlikely(reg_off == reg_max)) {
80
+ /* Find the active elements. */
81
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, 1 << msz)) {
82
/* The entire predicate was false; no load occurs. */
83
memset(vd, 0, reg_max);
84
return;
85
}
86
- mem_off = reg_off >> diffsz;
87
88
- /*
89
- * If the (remaining) load is entirely within a single page, then:
90
- * For softmmu, and the tlb hits, then no faults will occur;
91
- * For user-only, either the first load will fault or none will.
92
- * We can thus perform the load directly to the destination and
93
- * Vd will be unmodified on any exception path.
94
- */
95
- split = max_for_page(addr, mem_off, mem_max);
96
- if (likely(split == mem_max)) {
97
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
98
- if (test_host_page(host)) {
99
- intptr_t i = reg_off;
100
- host -= mem_off;
101
- do {
102
- host_fn(vd, i, host + (i >> diffsz));
103
- i = find_next_active(vg, i + (1 << esz), reg_max, esz);
104
- } while (i < reg_max);
105
- /* After having taken any fault, zero leading inactive elements. */
106
- swap_memzero(vd, reg_off);
107
- return;
108
- }
109
- }
110
+ /* Probe the page(s). Exit with exception for any invalid page. */
111
+ sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, retaddr);
112
113
- /*
114
- * Perform the predicated read into a temporary, thus ensuring
115
- * if the load of the last element faults, Vd is not modified.
116
- */
117
+ flags = info.page[0].flags | info.page[1].flags;
118
+ if (unlikely(flags != 0)) {
119
#ifdef CONFIG_USER_ONLY
120
- swap_memzero(&scratch, reg_off);
121
- host = g2h(addr);
122
- do {
123
- host_fn(&scratch, reg_off, host + (reg_off >> diffsz));
124
- reg_off += 1 << esz;
125
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
126
- } while (reg_off < reg_max);
127
+ g_assert_not_reached();
128
#else
129
- memset(&scratch, 0, reg_max);
130
- goto start;
131
- while (1) {
132
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
133
- if (reg_off >= reg_max) {
134
- break;
135
- }
136
- mem_off = reg_off >> diffsz;
137
- split = max_for_page(addr, mem_off, mem_max);
138
+ /*
139
+ * At least one page includes MMIO (or watchpoints).
140
+ * Any bus operation can fail with cpu_transaction_failed,
141
+ * which for ARM will raise SyncExternal. Perform the load
142
+ * into scratch memory to preserve register state until the end.
143
+ */
144
+ ARMVectorReg scratch;
145
146
- start:
147
- if (split - mem_off >= (1 << msz)) {
148
- /* At least one whole element on this page. */
149
- host = tlb_vaddr_to_host(env, addr + mem_off,
150
- MMU_DATA_LOAD, mmu_idx);
151
- if (host) {
152
- host -= mem_off;
153
- do {
154
- host_fn(&scratch, reg_off, host + mem_off);
155
- reg_off += 1 << esz;
156
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
157
- mem_off = reg_off >> diffsz;
158
- } while (split - mem_off >= (1 << msz));
159
- continue;
160
+ memset(&scratch, 0, reg_max);
161
+ mem_off = info.mem_off_first[0];
162
+ reg_off = info.reg_off_first[0];
163
+ reg_last = info.reg_off_last[1];
164
+ if (reg_last < 0) {
165
+ reg_last = info.reg_off_split;
166
+ if (reg_last < 0) {
167
+ reg_last = info.reg_off_last[0];
168
}
169
}
170
171
- /*
172
- * Perform one normal read. This may fault, longjmping out to the
173
- * main loop in order to raise an exception. It may succeed, and
174
- * as a side-effect load the TLB entry for the next round. Finally,
175
- * in the extremely unlikely case we're performing this operation
176
- * on I/O memory, it may succeed but not bring in the TLB entry.
177
- * But even then we have still made forward progress.
178
- */
179
- tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
180
- reg_off += 1 << esz;
181
- }
182
-#endif
183
+ do {
184
+ uint64_t pg = vg[reg_off >> 6];
185
+ do {
186
+ if ((pg >> (reg_off & 63)) & 1) {
187
+ tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
188
+ }
189
+ reg_off += 1 << esz;
190
+ mem_off += 1 << msz;
191
+ } while (reg_off & 63);
192
+ } while (reg_off <= reg_last);
193
194
- memcpy(vd, &scratch, reg_max);
195
+ memcpy(vd, &scratch, reg_max);
196
+ return;
197
+#endif
198
+ }
199
+
200
+ /* The entire operation is in RAM, on valid pages. */
201
+
202
+ memset(vd, 0, reg_max);
203
+ mem_off = info.mem_off_first[0];
204
+ reg_off = info.reg_off_first[0];
205
+ reg_last = info.reg_off_last[0];
206
+ host = info.page[0].host;
207
+
208
+ while (reg_off <= reg_last) {
209
+ uint64_t pg = vg[reg_off >> 6];
210
+ do {
211
+ if ((pg >> (reg_off & 63)) & 1) {
212
+ host_fn(vd, reg_off, host + mem_off);
213
+ }
214
+ reg_off += 1 << esz;
215
+ mem_off += 1 << msz;
216
+ } while (reg_off <= reg_last && (reg_off & 63));
217
+ }
218
+
219
+ /*
220
+ * Use the slow path to manage the cross-page misalignment.
221
+ * But we know this is RAM and cannot trap.
222
+ */
223
+ mem_off = info.mem_off_split;
224
+ if (unlikely(mem_off >= 0)) {
225
+ tlb_fn(env, vd, info.reg_off_split, addr + mem_off, retaddr);
226
+ }
227
+
228
+ mem_off = info.mem_off_first[1];
229
+ if (unlikely(mem_off >= 0)) {
230
+ reg_off = info.reg_off_first[1];
231
+ reg_last = info.reg_off_last[1];
232
+ host = info.page[1].host;
233
+
234
+ do {
235
+ uint64_t pg = vg[reg_off >> 6];
236
+ do {
237
+ if ((pg >> (reg_off & 63)) & 1) {
238
+ host_fn(vd, reg_off, host + mem_off);
239
+ }
240
+ reg_off += 1 << esz;
241
+ mem_off += 1 << msz;
242
+ } while (reg_off & 63);
243
+ } while (reg_off <= reg_last);
244
+ }
245
}
246
247
#define DO_LD1_1(NAME, ESZ) \
248
--
249
2.20.1
250
251
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Handle all of the watchpoints for active elements all at once,
4
before we've modified the vector register. This removes the
5
TLB_WATCHPOINT bit from page[].flags, which means that we can
6
use the normal fast path via RAM.
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-13-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/sve_helper.c | 72 ++++++++++++++++++++++++++++++++++++++++-
14
1 file changed, 71 insertions(+), 1 deletion(-)
15
16
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sve_helper.c
19
+++ b/target/arm/sve_helper.c
20
@@ -XXX,XX +XXX,XX @@ static bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault,
21
return have_work;
22
}
23
24
+static void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env,
25
+ uint64_t *vg, target_ulong addr,
26
+ int esize, int msize, int wp_access,
27
+ uintptr_t retaddr)
28
+{
29
+#ifndef CONFIG_USER_ONLY
30
+ intptr_t mem_off, reg_off, reg_last;
31
+ int flags0 = info->page[0].flags;
32
+ int flags1 = info->page[1].flags;
33
+
34
+ if (likely(!((flags0 | flags1) & TLB_WATCHPOINT))) {
35
+ return;
36
+ }
37
+
38
+ /* Indicate that watchpoints are handled. */
39
+ info->page[0].flags = flags0 & ~TLB_WATCHPOINT;
40
+ info->page[1].flags = flags1 & ~TLB_WATCHPOINT;
41
+
42
+ if (flags0 & TLB_WATCHPOINT) {
43
+ mem_off = info->mem_off_first[0];
44
+ reg_off = info->reg_off_first[0];
45
+ reg_last = info->reg_off_last[0];
46
+
47
+ while (reg_off <= reg_last) {
48
+ uint64_t pg = vg[reg_off >> 6];
49
+ do {
50
+ if ((pg >> (reg_off & 63)) & 1) {
51
+ cpu_check_watchpoint(env_cpu(env), addr + mem_off,
52
+ msize, info->page[0].attrs,
53
+ wp_access, retaddr);
54
+ }
55
+ reg_off += esize;
56
+ mem_off += msize;
57
+ } while (reg_off <= reg_last && (reg_off & 63));
58
+ }
59
+ }
60
+
61
+ mem_off = info->mem_off_split;
62
+ if (mem_off >= 0) {
63
+ cpu_check_watchpoint(env_cpu(env), addr + mem_off, msize,
64
+ info->page[0].attrs, wp_access, retaddr);
65
+ }
66
+
67
+ mem_off = info->mem_off_first[1];
68
+ if ((flags1 & TLB_WATCHPOINT) && mem_off >= 0) {
69
+ reg_off = info->reg_off_first[1];
70
+ reg_last = info->reg_off_last[1];
71
+
72
+ do {
73
+ uint64_t pg = vg[reg_off >> 6];
74
+ do {
75
+ if ((pg >> (reg_off & 63)) & 1) {
76
+ cpu_check_watchpoint(env_cpu(env), addr + mem_off,
77
+ msize, info->page[1].attrs,
78
+ wp_access, retaddr);
79
+ }
80
+ reg_off += esize;
81
+ mem_off += msize;
82
+ } while (reg_off & 63);
83
+ } while (reg_off <= reg_last);
84
+ }
85
+#endif
86
+}
87
+
88
/*
89
* The result of tlb_vaddr_to_host for user-only is just g2h(x),
90
* which is always non-null. Elide the useless test.
91
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
92
/* Probe the page(s). Exit with exception for any invalid page. */
93
sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, retaddr);
94
95
+ /* Handle watchpoints for all active elements. */
96
+ sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, 1 << msz,
97
+ BP_MEM_READ, retaddr);
98
+
99
+ /* TODO: MTE check. */
100
+
101
flags = info.page[0].flags | info.page[1].flags;
102
if (unlikely(flags != 0)) {
103
#ifdef CONFIG_USER_ONLY
104
g_assert_not_reached();
105
#else
106
/*
107
- * At least one page includes MMIO (or watchpoints).
108
+ * At least one page includes MMIO.
109
* Any bus operation can fail with cpu_transaction_failed,
110
* which for ARM will raise SyncExternal. Perform the load
111
* into scratch memory to preserve register state until the end.
112
--
113
2.20.1
114
115
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200508154359.7494-14-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/sve_helper.c | 223 ++++++++++++++--------------------------
9
1 file changed, 79 insertions(+), 144 deletions(-)
10
11
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/sve_helper.c
14
+++ b/target/arm/sve_helper.c
15
@@ -XXX,XX +XXX,XX @@ static inline bool test_host_page(void *host)
16
}
17
18
/*
19
- * Common helper for all contiguous one-register predicated loads.
20
+ * Common helper for all contiguous 1,2,3,4-register predicated stores.
21
*/
22
static inline QEMU_ALWAYS_INLINE
23
-void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
24
+void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
25
uint32_t desc, const uintptr_t retaddr,
26
- const int esz, const int msz,
27
+ const int esz, const int msz, const int N,
28
sve_ldst1_host_fn *host_fn,
29
sve_ldst1_tlb_fn *tlb_fn)
30
{
31
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
32
- void *vd = &env->vfp.zregs[rd];
33
const intptr_t reg_max = simd_oprsz(desc);
34
intptr_t reg_off, reg_last, mem_off;
35
SVEContLdSt info;
36
void *host;
37
- int flags;
38
+ int flags, i;
39
40
/* Find the active elements. */
41
- if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, 1 << msz)) {
42
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, N << msz)) {
43
/* The entire predicate was false; no load occurs. */
44
- memset(vd, 0, reg_max);
45
+ for (i = 0; i < N; ++i) {
46
+ memset(&env->vfp.zregs[(rd + i) & 31], 0, reg_max);
47
+ }
48
return;
49
}
50
51
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
52
sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, retaddr);
53
54
/* Handle watchpoints for all active elements. */
55
- sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, 1 << msz,
56
+ sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, N << msz,
57
BP_MEM_READ, retaddr);
58
59
/* TODO: MTE check. */
60
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
61
* which for ARM will raise SyncExternal. Perform the load
62
* into scratch memory to preserve register state until the end.
63
*/
64
- ARMVectorReg scratch;
65
+ ARMVectorReg scratch[4] = { };
66
67
- memset(&scratch, 0, reg_max);
68
mem_off = info.mem_off_first[0];
69
reg_off = info.reg_off_first[0];
70
reg_last = info.reg_off_last[1];
71
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
72
uint64_t pg = vg[reg_off >> 6];
73
do {
74
if ((pg >> (reg_off & 63)) & 1) {
75
- tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
76
+ for (i = 0; i < N; ++i) {
77
+ tlb_fn(env, &scratch[i], reg_off,
78
+ addr + mem_off + (i << msz), retaddr);
79
+ }
80
}
81
reg_off += 1 << esz;
82
- mem_off += 1 << msz;
83
+ mem_off += N << msz;
84
} while (reg_off & 63);
85
} while (reg_off <= reg_last);
86
87
- memcpy(vd, &scratch, reg_max);
88
+ for (i = 0; i < N; ++i) {
89
+ memcpy(&env->vfp.zregs[(rd + i) & 31], &scratch[i], reg_max);
90
+ }
91
return;
92
#endif
93
}
94
95
/* The entire operation is in RAM, on valid pages. */
96
97
- memset(vd, 0, reg_max);
98
+ for (i = 0; i < N; ++i) {
99
+ memset(&env->vfp.zregs[(rd + i) & 31], 0, reg_max);
100
+ }
101
+
102
mem_off = info.mem_off_first[0];
103
reg_off = info.reg_off_first[0];
104
reg_last = info.reg_off_last[0];
105
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
106
uint64_t pg = vg[reg_off >> 6];
107
do {
108
if ((pg >> (reg_off & 63)) & 1) {
109
- host_fn(vd, reg_off, host + mem_off);
110
+ for (i = 0; i < N; ++i) {
111
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
112
+ host + mem_off + (i << msz));
113
+ }
114
}
115
reg_off += 1 << esz;
116
- mem_off += 1 << msz;
117
+ mem_off += N << msz;
118
} while (reg_off <= reg_last && (reg_off & 63));
119
}
120
121
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
122
*/
123
mem_off = info.mem_off_split;
124
if (unlikely(mem_off >= 0)) {
125
- tlb_fn(env, vd, info.reg_off_split, addr + mem_off, retaddr);
126
+ reg_off = info.reg_off_split;
127
+ for (i = 0; i < N; ++i) {
128
+ tlb_fn(env, &env->vfp.zregs[(rd + i) & 31], reg_off,
129
+ addr + mem_off + (i << msz), retaddr);
130
+ }
131
}
132
133
mem_off = info.mem_off_first[1];
134
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
135
uint64_t pg = vg[reg_off >> 6];
136
do {
137
if ((pg >> (reg_off & 63)) & 1) {
138
- host_fn(vd, reg_off, host + mem_off);
139
+ for (i = 0; i < N; ++i) {
140
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
141
+ host + mem_off + (i << msz));
142
+ }
143
}
144
reg_off += 1 << esz;
145
- mem_off += 1 << msz;
146
+ mem_off += N << msz;
147
} while (reg_off & 63);
148
} while (reg_off <= reg_last);
149
}
150
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
151
void HELPER(sve_##NAME##_r)(CPUARMState *env, void *vg, \
152
target_ulong addr, uint32_t desc) \
153
{ \
154
- sve_ld1_r(env, vg, addr, desc, GETPC(), ESZ, 0, \
155
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, 1, \
156
sve_##NAME##_host, sve_##NAME##_tlb); \
157
}
158
159
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_##NAME##_r)(CPUARMState *env, void *vg, \
160
void HELPER(sve_##NAME##_le_r)(CPUARMState *env, void *vg, \
161
target_ulong addr, uint32_t desc) \
162
{ \
163
- sve_ld1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
164
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \
165
sve_##NAME##_le_host, sve_##NAME##_le_tlb); \
166
} \
167
void HELPER(sve_##NAME##_be_r)(CPUARMState *env, void *vg, \
168
target_ulong addr, uint32_t desc) \
169
{ \
170
- sve_ld1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
171
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \
172
sve_##NAME##_be_host, sve_##NAME##_be_tlb); \
173
}
174
175
-DO_LD1_1(ld1bb, 0)
176
-DO_LD1_1(ld1bhu, 1)
177
-DO_LD1_1(ld1bhs, 1)
178
-DO_LD1_1(ld1bsu, 2)
179
-DO_LD1_1(ld1bss, 2)
180
-DO_LD1_1(ld1bdu, 3)
181
-DO_LD1_1(ld1bds, 3)
182
+DO_LD1_1(ld1bb, MO_8)
183
+DO_LD1_1(ld1bhu, MO_16)
184
+DO_LD1_1(ld1bhs, MO_16)
185
+DO_LD1_1(ld1bsu, MO_32)
186
+DO_LD1_1(ld1bss, MO_32)
187
+DO_LD1_1(ld1bdu, MO_64)
188
+DO_LD1_1(ld1bds, MO_64)
189
190
-DO_LD1_2(ld1hh, 1, 1)
191
-DO_LD1_2(ld1hsu, 2, 1)
192
-DO_LD1_2(ld1hss, 2, 1)
193
-DO_LD1_2(ld1hdu, 3, 1)
194
-DO_LD1_2(ld1hds, 3, 1)
195
+DO_LD1_2(ld1hh, MO_16, MO_16)
196
+DO_LD1_2(ld1hsu, MO_32, MO_16)
197
+DO_LD1_2(ld1hss, MO_32, MO_16)
198
+DO_LD1_2(ld1hdu, MO_64, MO_16)
199
+DO_LD1_2(ld1hds, MO_64, MO_16)
200
201
-DO_LD1_2(ld1ss, 2, 2)
202
-DO_LD1_2(ld1sdu, 3, 2)
203
-DO_LD1_2(ld1sds, 3, 2)
204
+DO_LD1_2(ld1ss, MO_32, MO_32)
205
+DO_LD1_2(ld1sdu, MO_64, MO_32)
206
+DO_LD1_2(ld1sds, MO_64, MO_32)
207
208
-DO_LD1_2(ld1dd, 3, 3)
209
+DO_LD1_2(ld1dd, MO_64, MO_64)
210
211
#undef DO_LD1_1
212
#undef DO_LD1_2
213
214
-/*
215
- * Common helpers for all contiguous 2,3,4-register predicated loads.
216
- */
217
-static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
218
- uint32_t desc, int size, uintptr_t ra,
219
- sve_ldst1_tlb_fn *tlb_fn)
220
-{
221
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
222
- intptr_t i, oprsz = simd_oprsz(desc);
223
- ARMVectorReg scratch[2] = { };
224
-
225
- for (i = 0; i < oprsz; ) {
226
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
227
- do {
228
- if (pg & 1) {
229
- tlb_fn(env, &scratch[0], i, addr, ra);
230
- tlb_fn(env, &scratch[1], i, addr + size, ra);
231
- }
232
- i += size, pg >>= size;
233
- addr += 2 * size;
234
- } while (i & 15);
235
- }
236
-
237
- /* Wait until all exceptions have been raised to write back. */
238
- memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
239
- memcpy(&env->vfp.zregs[(rd + 1) & 31], &scratch[1], oprsz);
240
-}
241
-
242
-static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
243
- uint32_t desc, int size, uintptr_t ra,
244
- sve_ldst1_tlb_fn *tlb_fn)
245
-{
246
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
247
- intptr_t i, oprsz = simd_oprsz(desc);
248
- ARMVectorReg scratch[3] = { };
249
-
250
- for (i = 0; i < oprsz; ) {
251
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
252
- do {
253
- if (pg & 1) {
254
- tlb_fn(env, &scratch[0], i, addr, ra);
255
- tlb_fn(env, &scratch[1], i, addr + size, ra);
256
- tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
257
- }
258
- i += size, pg >>= size;
259
- addr += 3 * size;
260
- } while (i & 15);
261
- }
262
-
263
- /* Wait until all exceptions have been raised to write back. */
264
- memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
265
- memcpy(&env->vfp.zregs[(rd + 1) & 31], &scratch[1], oprsz);
266
- memcpy(&env->vfp.zregs[(rd + 2) & 31], &scratch[2], oprsz);
267
-}
268
-
269
-static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
270
- uint32_t desc, int size, uintptr_t ra,
271
- sve_ldst1_tlb_fn *tlb_fn)
272
-{
273
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
274
- intptr_t i, oprsz = simd_oprsz(desc);
275
- ARMVectorReg scratch[4] = { };
276
-
277
- for (i = 0; i < oprsz; ) {
278
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
279
- do {
280
- if (pg & 1) {
281
- tlb_fn(env, &scratch[0], i, addr, ra);
282
- tlb_fn(env, &scratch[1], i, addr + size, ra);
283
- tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
284
- tlb_fn(env, &scratch[3], i, addr + 3 * size, ra);
285
- }
286
- i += size, pg >>= size;
287
- addr += 4 * size;
288
- } while (i & 15);
289
- }
290
-
291
- /* Wait until all exceptions have been raised to write back. */
292
- memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
293
- memcpy(&env->vfp.zregs[(rd + 1) & 31], &scratch[1], oprsz);
294
- memcpy(&env->vfp.zregs[(rd + 2) & 31], &scratch[2], oprsz);
295
- memcpy(&env->vfp.zregs[(rd + 3) & 31], &scratch[3], oprsz);
296
-}
297
-
298
#define DO_LDN_1(N) \
299
-void QEMU_FLATTEN HELPER(sve_ld##N##bb_r) \
300
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
301
-{ \
302
- sve_ld##N##_r(env, vg, addr, desc, 1, GETPC(), sve_ld1bb_tlb); \
303
+void HELPER(sve_ld##N##bb_r)(CPUARMState *env, void *vg, \
304
+ target_ulong addr, uint32_t desc) \
305
+{ \
306
+ sve_ldN_r(env, vg, addr, desc, GETPC(), MO_8, MO_8, N, \
307
+ sve_ld1bb_host, sve_ld1bb_tlb); \
308
}
309
310
-#define DO_LDN_2(N, SUFF, SIZE) \
311
-void QEMU_FLATTEN HELPER(sve_ld##N##SUFF##_le_r) \
312
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
313
+#define DO_LDN_2(N, SUFF, ESZ) \
314
+void HELPER(sve_ld##N##SUFF##_le_r)(CPUARMState *env, void *vg, \
315
+ target_ulong addr, uint32_t desc) \
316
{ \
317
- sve_ld##N##_r(env, vg, addr, desc, SIZE, GETPC(), \
318
- sve_ld1##SUFF##_le_tlb); \
319
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \
320
+ sve_ld1##SUFF##_le_host, sve_ld1##SUFF##_le_tlb); \
321
} \
322
-void QEMU_FLATTEN HELPER(sve_ld##N##SUFF##_be_r) \
323
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
324
+void HELPER(sve_ld##N##SUFF##_be_r)(CPUARMState *env, void *vg, \
325
+ target_ulong addr, uint32_t desc) \
326
{ \
327
- sve_ld##N##_r(env, vg, addr, desc, SIZE, GETPC(), \
328
- sve_ld1##SUFF##_be_tlb); \
329
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \
330
+ sve_ld1##SUFF##_be_host, sve_ld1##SUFF##_be_tlb); \
331
}
332
333
DO_LDN_1(2)
334
DO_LDN_1(3)
335
DO_LDN_1(4)
336
337
-DO_LDN_2(2, hh, 2)
338
-DO_LDN_2(3, hh, 2)
339
-DO_LDN_2(4, hh, 2)
340
+DO_LDN_2(2, hh, MO_16)
341
+DO_LDN_2(3, hh, MO_16)
342
+DO_LDN_2(4, hh, MO_16)
343
344
-DO_LDN_2(2, ss, 4)
345
-DO_LDN_2(3, ss, 4)
346
-DO_LDN_2(4, ss, 4)
347
+DO_LDN_2(2, ss, MO_32)
348
+DO_LDN_2(3, ss, MO_32)
349
+DO_LDN_2(4, ss, MO_32)
350
351
-DO_LDN_2(2, dd, 8)
352
-DO_LDN_2(3, dd, 8)
353
-DO_LDN_2(4, dd, 8)
354
+DO_LDN_2(2, dd, MO_64)
355
+DO_LDN_2(3, dd, MO_64)
356
+DO_LDN_2(4, dd, MO_64)
357
358
#undef DO_LDN_1
359
#undef DO_LDN_2
360
--
361
2.20.1
362
363
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
With sve_cont_ldst_pages, the differences between first-fault and no-fault
4
are minimal, so unify the routines. With cpu_probe_watchpoint, we are able
5
to make progress through pages with TLB_WATCHPOINT set when the watchpoint
6
does not actually fire.
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-15-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/sve_helper.c | 346 +++++++++++++++++++---------------------
14
1 file changed, 162 insertions(+), 184 deletions(-)
15
16
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sve_helper.c
19
+++ b/target/arm/sve_helper.c
20
@@ -XXX,XX +XXX,XX @@ static intptr_t find_next_active(uint64_t *vg, intptr_t reg_off,
21
return reg_off;
22
}
23
24
-/*
25
- * Return the maximum offset <= @mem_max which is still within the page
26
- * referenced by @base + @mem_off.
27
- */
28
-static intptr_t max_for_page(target_ulong base, intptr_t mem_off,
29
- intptr_t mem_max)
30
-{
31
- target_ulong addr = base + mem_off;
32
- intptr_t split = -(intptr_t)(addr | TARGET_PAGE_MASK);
33
- return MIN(split, mem_max - mem_off) + mem_off;
34
-}
35
-
36
/*
37
* Resolve the guest virtual address to info->host and info->flags.
38
* If @nofault, return false if the page is invalid, otherwise
39
@@ -XXX,XX +XXX,XX @@ static void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env,
40
#endif
41
}
42
43
-/*
44
- * The result of tlb_vaddr_to_host for user-only is just g2h(x),
45
- * which is always non-null. Elide the useless test.
46
- */
47
-static inline bool test_host_page(void *host)
48
-{
49
-#ifdef CONFIG_USER_ONLY
50
- return true;
51
-#else
52
- return likely(host != NULL);
53
-#endif
54
-}
55
-
56
/*
57
* Common helper for all contiguous 1,2,3,4-register predicated stores.
58
*/
59
@@ -XXX,XX +XXX,XX @@ static void record_fault(CPUARMState *env, uintptr_t i, uintptr_t oprsz)
60
}
61
62
/*
63
- * Common helper for all contiguous first-fault loads.
64
+ * Common helper for all contiguous no-fault and first-fault loads.
65
*/
66
-static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
67
- uint32_t desc, const uintptr_t retaddr,
68
- const int esz, const int msz,
69
- sve_ldst1_host_fn *host_fn,
70
- sve_ldst1_tlb_fn *tlb_fn)
71
+static inline QEMU_ALWAYS_INLINE
72
+void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
73
+ uint32_t desc, const uintptr_t retaddr,
74
+ const int esz, const int msz, const SVEContFault fault,
75
+ sve_ldst1_host_fn *host_fn,
76
+ sve_ldst1_tlb_fn *tlb_fn)
77
{
78
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
79
- const int mmu_idx = get_mmuidx(oi);
80
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
81
void *vd = &env->vfp.zregs[rd];
82
- const int diffsz = esz - msz;
83
const intptr_t reg_max = simd_oprsz(desc);
84
- const intptr_t mem_max = reg_max >> diffsz;
85
- intptr_t split, reg_off, mem_off, i;
86
+ intptr_t reg_off, mem_off, reg_last;
87
+ SVEContLdSt info;
88
+ int flags;
89
void *host;
90
91
- /* Skip to the first active element. */
92
- reg_off = find_next_active(vg, 0, reg_max, esz);
93
- if (unlikely(reg_off == reg_max)) {
94
+ /* Find the active elements. */
95
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, 1 << msz)) {
96
/* The entire predicate was false; no load occurs. */
97
memset(vd, 0, reg_max);
98
return;
99
}
100
- mem_off = reg_off >> diffsz;
101
+ reg_off = info.reg_off_first[0];
102
103
- /*
104
- * If the (remaining) load is entirely within a single page, then:
105
- * For softmmu, and the tlb hits, then no faults will occur;
106
- * For user-only, either the first load will fault or none will.
107
- * We can thus perform the load directly to the destination and
108
- * Vd will be unmodified on any exception path.
109
- */
110
- split = max_for_page(addr, mem_off, mem_max);
111
- if (likely(split == mem_max)) {
112
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
113
- if (test_host_page(host)) {
114
- i = reg_off;
115
- host -= mem_off;
116
- do {
117
- host_fn(vd, i, host + (i >> diffsz));
118
- i = find_next_active(vg, i + (1 << esz), reg_max, esz);
119
- } while (i < reg_max);
120
- /* After any fault, zero any leading inactive elements. */
121
+ /* Probe the page(s). */
122
+ if (!sve_cont_ldst_pages(&info, fault, env, addr, MMU_DATA_LOAD, retaddr)) {
123
+ /* Fault on first element. */
124
+ tcg_debug_assert(fault == FAULT_NO);
125
+ memset(vd, 0, reg_max);
126
+ goto do_fault;
127
+ }
128
+
129
+ mem_off = info.mem_off_first[0];
130
+ flags = info.page[0].flags;
131
+
132
+ if (fault == FAULT_FIRST) {
133
+ /*
134
+ * Special handling of the first active element,
135
+ * if it crosses a page boundary or is MMIO.
136
+ */
137
+ bool is_split = mem_off == info.mem_off_split;
138
+ /* TODO: MTE check. */
139
+ if (unlikely(flags != 0) || unlikely(is_split)) {
140
+ /*
141
+ * Use the slow path for cross-page handling.
142
+ * Might trap for MMIO or watchpoints.
143
+ */
144
+ tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
145
+
146
+ /* After any fault, zero the other elements. */
147
swap_memzero(vd, reg_off);
148
- return;
149
+ reg_off += 1 << esz;
150
+ mem_off += 1 << msz;
151
+ swap_memzero(vd + reg_off, reg_max - reg_off);
152
+
153
+ if (is_split) {
154
+ goto second_page;
155
+ }
156
+ } else {
157
+ memset(vd, 0, reg_max);
158
+ }
159
+ } else {
160
+ memset(vd, 0, reg_max);
161
+ if (unlikely(mem_off == info.mem_off_split)) {
162
+ /* The first active element crosses a page boundary. */
163
+ flags |= info.page[1].flags;
164
+ if (unlikely(flags & TLB_MMIO)) {
165
+ /* Some page is MMIO, see below. */
166
+ goto do_fault;
167
+ }
168
+ if (unlikely(flags & TLB_WATCHPOINT) &&
169
+ (cpu_watchpoint_address_matches
170
+ (env_cpu(env), addr + mem_off, 1 << msz)
171
+ & BP_MEM_READ)) {
172
+ /* Watchpoint hit, see below. */
173
+ goto do_fault;
174
+ }
175
+ /* TODO: MTE check. */
176
+ /*
177
+ * Use the slow path for cross-page handling.
178
+ * This is RAM, without a watchpoint, and will not trap.
179
+ */
180
+ tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
181
+ goto second_page;
182
}
183
}
184
185
/*
186
- * Perform one normal read, which will fault or not.
187
- * But it is likely to bring the page into the tlb.
188
+ * From this point on, all memory operations are MemSingleNF.
189
+ *
190
+ * Per the MemSingleNF pseudocode, a no-fault load from Device memory
191
+ * must not actually hit the bus -- it returns (UNKNOWN, FAULT) instead.
192
+ *
193
+ * Unfortuately we do not have access to the memory attributes from the
194
+ * PTE to tell Device memory from Normal memory. So we make a mostly
195
+ * correct check, and indicate (UNKNOWN, FAULT) for any MMIO.
196
+ * This gives the right answer for the common cases of "Normal memory,
197
+ * backed by host RAM" and "Device memory, backed by MMIO".
198
+ * The architecture allows us to suppress an NF load and return
199
+ * (UNKNOWN, FAULT) for any reason, so our behaviour for the corner
200
+ * case of "Normal memory, backed by MMIO" is permitted. The case we
201
+ * get wrong is "Device memory, backed by host RAM", for which we
202
+ * should return (UNKNOWN, FAULT) for but do not.
203
+ *
204
+ * Similarly, CPU_BP breakpoints would raise exceptions, and so
205
+ * return (UNKNOWN, FAULT). For simplicity, we consider gdb and
206
+ * architectural breakpoints the same.
207
*/
208
- tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
209
+ if (unlikely(flags & TLB_MMIO)) {
210
+ goto do_fault;
211
+ }
212
213
- /* After any fault, zero any leading predicated false elts. */
214
- swap_memzero(vd, reg_off);
215
- mem_off += 1 << msz;
216
- reg_off += 1 << esz;
217
+ reg_last = info.reg_off_last[0];
218
+ host = info.page[0].host;
219
220
- /* Try again to read the balance of the page. */
221
- split = max_for_page(addr, mem_off - 1, mem_max);
222
- if (split >= (1 << msz)) {
223
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
224
- if (host) {
225
- host -= mem_off;
226
- do {
227
+ do {
228
+ uint64_t pg = *(uint64_t *)(vg + (reg_off >> 3));
229
+ do {
230
+ if ((pg >> (reg_off & 63)) & 1) {
231
+ if (unlikely(flags & TLB_WATCHPOINT) &&
232
+ (cpu_watchpoint_address_matches
233
+ (env_cpu(env), addr + mem_off, 1 << msz)
234
+ & BP_MEM_READ)) {
235
+ goto do_fault;
236
+ }
237
+ /* TODO: MTE check. */
238
host_fn(vd, reg_off, host + mem_off);
239
- reg_off += 1 << esz;
240
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
241
- mem_off = reg_off >> diffsz;
242
- } while (split - mem_off >= (1 << msz));
243
- }
244
- }
245
-
246
- record_fault(env, reg_off, reg_max);
247
-}
248
-
249
-/*
250
- * Common helper for all contiguous no-fault loads.
251
- */
252
-static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
253
- uint32_t desc, const int esz, const int msz,
254
- sve_ldst1_host_fn *host_fn)
255
-{
256
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
257
- void *vd = &env->vfp.zregs[rd];
258
- const int diffsz = esz - msz;
259
- const intptr_t reg_max = simd_oprsz(desc);
260
- const intptr_t mem_max = reg_max >> diffsz;
261
- const int mmu_idx = cpu_mmu_index(env, false);
262
- intptr_t split, reg_off, mem_off;
263
- void *host;
264
-
265
-#ifdef CONFIG_USER_ONLY
266
- host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_idx);
267
- if (likely(page_check_range(addr, mem_max, PAGE_READ) == 0)) {
268
- /* The entire operation is valid and will not fault. */
269
- reg_off = 0;
270
- do {
271
- mem_off = reg_off >> diffsz;
272
- host_fn(vd, reg_off, host + mem_off);
273
+ }
274
reg_off += 1 << esz;
275
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
276
- } while (reg_off < reg_max);
277
- return;
278
- }
279
-#endif
280
+ mem_off += 1 << msz;
281
+ } while (reg_off <= reg_last && (reg_off & 63));
282
+ } while (reg_off <= reg_last);
283
284
- /* There will be no fault, so we may modify in advance. */
285
- memset(vd, 0, reg_max);
286
-
287
- /* Skip to the first active element. */
288
- reg_off = find_next_active(vg, 0, reg_max, esz);
289
- if (unlikely(reg_off == reg_max)) {
290
- /* The entire predicate was false; no load occurs. */
291
- return;
292
- }
293
- mem_off = reg_off >> diffsz;
294
-
295
-#ifdef CONFIG_USER_ONLY
296
- if (page_check_range(addr + mem_off, 1 << msz, PAGE_READ) == 0) {
297
- /* At least one load is valid; take the rest of the page. */
298
- split = max_for_page(addr, mem_off + (1 << msz) - 1, mem_max);
299
- do {
300
- host_fn(vd, reg_off, host + mem_off);
301
- reg_off += 1 << esz;
302
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
303
- mem_off = reg_off >> diffsz;
304
- } while (split - mem_off >= (1 << msz));
305
- }
306
-#else
307
/*
308
- * If the address is not in the TLB, we have no way to bring the
309
- * entry into the TLB without also risking a fault. Note that
310
- * the corollary is that we never load from an address not in RAM.
311
- *
312
- * This last is out of spec, in a weird corner case.
313
- * Per the MemNF/MemSingleNF pseudocode, a NF load from Device memory
314
- * must not actually hit the bus -- it returns UNKNOWN data instead.
315
- * But if you map non-RAM with Normal memory attributes and do a NF
316
- * load then it should access the bus. (Nobody ought actually do this
317
- * in the real world, obviously.)
318
- *
319
- * Then there are the annoying special cases with watchpoints...
320
- * TODO: Add a form of non-faulting loads using cc->tlb_fill(probe=true).
321
+ * MemSingleNF is allowed to fail for any reason. We have special
322
+ * code above to handle the first element crossing a page boundary.
323
+ * As an implementation choice, decline to handle a cross-page element
324
+ * in any other position.
325
*/
326
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
327
- split = max_for_page(addr, mem_off, mem_max);
328
- if (host && split >= (1 << msz)) {
329
- host -= mem_off;
330
- do {
331
- host_fn(vd, reg_off, host + mem_off);
332
- reg_off += 1 << esz;
333
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
334
- mem_off = reg_off >> diffsz;
335
- } while (split - mem_off >= (1 << msz));
336
+ reg_off = info.reg_off_split;
337
+ if (reg_off >= 0) {
338
+ goto do_fault;
339
}
340
-#endif
341
342
+ second_page:
343
+ reg_off = info.reg_off_first[1];
344
+ if (likely(reg_off < 0)) {
345
+ /* No active elements on the second page. All done. */
346
+ return;
347
+ }
348
+
349
+ /*
350
+ * MemSingleNF is allowed to fail for any reason. As an implementation
351
+ * choice, decline to handle elements on the second page. This should
352
+ * be low frequency as the guest walks through memory -- the next
353
+ * iteration of the guest's loop should be aligned on the page boundary,
354
+ * and then all following iterations will stay aligned.
355
+ */
356
+
357
+ do_fault:
358
record_fault(env, reg_off, reg_max);
359
}
360
361
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
362
void HELPER(sve_ldff1##PART##_r)(CPUARMState *env, void *vg, \
363
target_ulong addr, uint32_t desc) \
364
{ \
365
- sve_ldff1_r(env, vg, addr, desc, GETPC(), ESZ, 0, \
366
- sve_ld1##PART##_host, sve_ld1##PART##_tlb); \
367
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, FAULT_FIRST, \
368
+ sve_ld1##PART##_host, sve_ld1##PART##_tlb); \
369
} \
370
void HELPER(sve_ldnf1##PART##_r)(CPUARMState *env, void *vg, \
371
target_ulong addr, uint32_t desc) \
372
{ \
373
- sve_ldnf1_r(env, vg, addr, desc, ESZ, 0, sve_ld1##PART##_host); \
374
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, FAULT_NO, \
375
+ sve_ld1##PART##_host, sve_ld1##PART##_tlb); \
376
}
377
378
#define DO_LDFF1_LDNF1_2(PART, ESZ, MSZ) \
379
void HELPER(sve_ldff1##PART##_le_r)(CPUARMState *env, void *vg, \
380
target_ulong addr, uint32_t desc) \
381
{ \
382
- sve_ldff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
383
- sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \
384
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_FIRST, \
385
+ sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \
386
} \
387
void HELPER(sve_ldnf1##PART##_le_r)(CPUARMState *env, void *vg, \
388
target_ulong addr, uint32_t desc) \
389
{ \
390
- sve_ldnf1_r(env, vg, addr, desc, ESZ, MSZ, sve_ld1##PART##_le_host); \
391
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_NO, \
392
+ sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \
393
} \
394
void HELPER(sve_ldff1##PART##_be_r)(CPUARMState *env, void *vg, \
395
target_ulong addr, uint32_t desc) \
396
{ \
397
- sve_ldff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
398
- sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \
399
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_FIRST, \
400
+ sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \
401
} \
402
void HELPER(sve_ldnf1##PART##_be_r)(CPUARMState *env, void *vg, \
403
target_ulong addr, uint32_t desc) \
404
{ \
405
- sve_ldnf1_r(env, vg, addr, desc, ESZ, MSZ, sve_ld1##PART##_be_host); \
406
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_NO, \
407
+ sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \
408
}
409
410
-DO_LDFF1_LDNF1_1(bb, 0)
411
-DO_LDFF1_LDNF1_1(bhu, 1)
412
-DO_LDFF1_LDNF1_1(bhs, 1)
413
-DO_LDFF1_LDNF1_1(bsu, 2)
414
-DO_LDFF1_LDNF1_1(bss, 2)
415
-DO_LDFF1_LDNF1_1(bdu, 3)
416
-DO_LDFF1_LDNF1_1(bds, 3)
417
+DO_LDFF1_LDNF1_1(bb, MO_8)
418
+DO_LDFF1_LDNF1_1(bhu, MO_16)
419
+DO_LDFF1_LDNF1_1(bhs, MO_16)
420
+DO_LDFF1_LDNF1_1(bsu, MO_32)
421
+DO_LDFF1_LDNF1_1(bss, MO_32)
422
+DO_LDFF1_LDNF1_1(bdu, MO_64)
423
+DO_LDFF1_LDNF1_1(bds, MO_64)
424
425
-DO_LDFF1_LDNF1_2(hh, 1, 1)
426
-DO_LDFF1_LDNF1_2(hsu, 2, 1)
427
-DO_LDFF1_LDNF1_2(hss, 2, 1)
428
-DO_LDFF1_LDNF1_2(hdu, 3, 1)
429
-DO_LDFF1_LDNF1_2(hds, 3, 1)
430
+DO_LDFF1_LDNF1_2(hh, MO_16, MO_16)
431
+DO_LDFF1_LDNF1_2(hsu, MO_32, MO_16)
432
+DO_LDFF1_LDNF1_2(hss, MO_32, MO_16)
433
+DO_LDFF1_LDNF1_2(hdu, MO_64, MO_16)
434
+DO_LDFF1_LDNF1_2(hds, MO_64, MO_16)
435
436
-DO_LDFF1_LDNF1_2(ss, 2, 2)
437
-DO_LDFF1_LDNF1_2(sdu, 3, 2)
438
-DO_LDFF1_LDNF1_2(sds, 3, 2)
439
+DO_LDFF1_LDNF1_2(ss, MO_32, MO_32)
440
+DO_LDFF1_LDNF1_2(sdu, MO_64, MO_32)
441
+DO_LDFF1_LDNF1_2(sds, MO_64, MO_32)
442
443
-DO_LDFF1_LDNF1_2(dd, 3, 3)
444
+DO_LDFF1_LDNF1_2(dd, MO_64, MO_64)
445
446
#undef DO_LDFF1_LDNF1_1
447
#undef DO_LDFF1_LDNF1_2
448
--
449
2.20.1
450
451
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Follow the model set up for contiguous loads. This handles
4
watchpoints correctly for contiguous stores, recognizing the
5
exception before any changes to memory.
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200508154359.7494-16-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/sve_helper.c | 285 ++++++++++++++++++++++------------------
13
1 file changed, 159 insertions(+), 126 deletions(-)
14
15
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/sve_helper.c
18
+++ b/target/arm/sve_helper.c
19
@@ -XXX,XX +XXX,XX @@ static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
20
*(TYPEE *)(vd + H(reg_off)) = val; \
21
}
22
23
+#define DO_ST_HOST(NAME, H, TYPEE, TYPEM, HOST) \
24
+static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
25
+{ HOST(host, (TYPEM)*(TYPEE *)(vd + H(reg_off))); }
26
+
27
#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \
28
static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
29
target_ulong addr, uintptr_t ra) \
30
@@ -XXX,XX +XXX,XX @@ DO_LD_PRIM_1(ld1bdu, , uint64_t, uint8_t)
31
DO_LD_PRIM_1(ld1bds, , uint64_t, int8_t)
32
33
#define DO_ST_PRIM_1(NAME, H, TE, TM) \
34
+ DO_ST_HOST(st1##NAME, H, TE, TM, stb_p) \
35
DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra)
36
37
DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t)
38
@@ -XXX,XX +XXX,XX @@ DO_ST_PRIM_1(bd, , uint64_t, uint8_t)
39
DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra)
40
41
#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \
42
+ DO_ST_HOST(st1##NAME##_be, H, TE, TM, ST##_be_p) \
43
+ DO_ST_HOST(st1##NAME##_le, H, TE, TM, ST##_le_p) \
44
DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \
45
DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra)
46
47
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_LDNF1_2(dd, MO_64, MO_64)
48
#undef DO_LDFF1_LDNF1_2
49
50
/*
51
- * Common helpers for all contiguous 1,2,3,4-register predicated stores.
52
+ * Common helper for all contiguous 1,2,3,4-register predicated stores.
53
*/
54
-static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
55
- uint32_t desc, const uintptr_t ra,
56
- const int esize, const int msize,
57
- sve_ldst1_tlb_fn *tlb_fn)
58
+
59
+static inline QEMU_ALWAYS_INLINE
60
+void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, uint32_t desc,
61
+ const uintptr_t retaddr, const int esz,
62
+ const int msz, const int N,
63
+ sve_ldst1_host_fn *host_fn,
64
+ sve_ldst1_tlb_fn *tlb_fn)
65
{
66
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
67
- intptr_t i, oprsz = simd_oprsz(desc);
68
- void *vd = &env->vfp.zregs[rd];
69
+ const intptr_t reg_max = simd_oprsz(desc);
70
+ intptr_t reg_off, reg_last, mem_off;
71
+ SVEContLdSt info;
72
+ void *host;
73
+ int i, flags;
74
75
- for (i = 0; i < oprsz; ) {
76
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
77
- do {
78
- if (pg & 1) {
79
- tlb_fn(env, vd, i, addr, ra);
80
+ /* Find the active elements. */
81
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, N << msz)) {
82
+ /* The entire predicate was false; no store occurs. */
83
+ return;
84
+ }
85
+
86
+ /* Probe the page(s). Exit with exception for any invalid page. */
87
+ sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_STORE, retaddr);
88
+
89
+ /* Handle watchpoints for all active elements. */
90
+ sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, N << msz,
91
+ BP_MEM_WRITE, retaddr);
92
+
93
+ /* TODO: MTE check. */
94
+
95
+ flags = info.page[0].flags | info.page[1].flags;
96
+ if (unlikely(flags != 0)) {
97
+#ifdef CONFIG_USER_ONLY
98
+ g_assert_not_reached();
99
+#else
100
+ /*
101
+ * At least one page includes MMIO.
102
+ * Any bus operation can fail with cpu_transaction_failed,
103
+ * which for ARM will raise SyncExternal. We cannot avoid
104
+ * this fault and will leave with the store incomplete.
105
+ */
106
+ mem_off = info.mem_off_first[0];
107
+ reg_off = info.reg_off_first[0];
108
+ reg_last = info.reg_off_last[1];
109
+ if (reg_last < 0) {
110
+ reg_last = info.reg_off_split;
111
+ if (reg_last < 0) {
112
+ reg_last = info.reg_off_last[0];
113
}
114
- i += esize, pg >>= esize;
115
- addr += msize;
116
- } while (i & 15);
117
+ }
118
+
119
+ do {
120
+ uint64_t pg = vg[reg_off >> 6];
121
+ do {
122
+ if ((pg >> (reg_off & 63)) & 1) {
123
+ for (i = 0; i < N; ++i) {
124
+ tlb_fn(env, &env->vfp.zregs[(rd + i) & 31], reg_off,
125
+ addr + mem_off + (i << msz), retaddr);
126
+ }
127
+ }
128
+ reg_off += 1 << esz;
129
+ mem_off += N << msz;
130
+ } while (reg_off & 63);
131
+ } while (reg_off <= reg_last);
132
+ return;
133
+#endif
134
+ }
135
+
136
+ mem_off = info.mem_off_first[0];
137
+ reg_off = info.reg_off_first[0];
138
+ reg_last = info.reg_off_last[0];
139
+ host = info.page[0].host;
140
+
141
+ while (reg_off <= reg_last) {
142
+ uint64_t pg = vg[reg_off >> 6];
143
+ do {
144
+ if ((pg >> (reg_off & 63)) & 1) {
145
+ for (i = 0; i < N; ++i) {
146
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
147
+ host + mem_off + (i << msz));
148
+ }
149
+ }
150
+ reg_off += 1 << esz;
151
+ mem_off += N << msz;
152
+ } while (reg_off <= reg_last && (reg_off & 63));
153
+ }
154
+
155
+ /*
156
+ * Use the slow path to manage the cross-page misalignment.
157
+ * But we know this is RAM and cannot trap.
158
+ */
159
+ mem_off = info.mem_off_split;
160
+ if (unlikely(mem_off >= 0)) {
161
+ reg_off = info.reg_off_split;
162
+ for (i = 0; i < N; ++i) {
163
+ tlb_fn(env, &env->vfp.zregs[(rd + i) & 31], reg_off,
164
+ addr + mem_off + (i << msz), retaddr);
165
+ }
166
+ }
167
+
168
+ mem_off = info.mem_off_first[1];
169
+ if (unlikely(mem_off >= 0)) {
170
+ reg_off = info.reg_off_first[1];
171
+ reg_last = info.reg_off_last[1];
172
+ host = info.page[1].host;
173
+
174
+ do {
175
+ uint64_t pg = vg[reg_off >> 6];
176
+ do {
177
+ if ((pg >> (reg_off & 63)) & 1) {
178
+ for (i = 0; i < N; ++i) {
179
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
180
+ host + mem_off + (i << msz));
181
+ }
182
+ }
183
+ reg_off += 1 << esz;
184
+ mem_off += N << msz;
185
+ } while (reg_off & 63);
186
+ } while (reg_off <= reg_last);
187
}
188
}
189
190
-static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
191
- uint32_t desc, const uintptr_t ra,
192
- const int esize, const int msize,
193
- sve_ldst1_tlb_fn *tlb_fn)
194
-{
195
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
196
- intptr_t i, oprsz = simd_oprsz(desc);
197
- void *d1 = &env->vfp.zregs[rd];
198
- void *d2 = &env->vfp.zregs[(rd + 1) & 31];
199
-
200
- for (i = 0; i < oprsz; ) {
201
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
202
- do {
203
- if (pg & 1) {
204
- tlb_fn(env, d1, i, addr, ra);
205
- tlb_fn(env, d2, i, addr + msize, ra);
206
- }
207
- i += esize, pg >>= esize;
208
- addr += 2 * msize;
209
- } while (i & 15);
210
- }
211
-}
212
-
213
-static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
214
- uint32_t desc, const uintptr_t ra,
215
- const int esize, const int msize,
216
- sve_ldst1_tlb_fn *tlb_fn)
217
-{
218
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
219
- intptr_t i, oprsz = simd_oprsz(desc);
220
- void *d1 = &env->vfp.zregs[rd];
221
- void *d2 = &env->vfp.zregs[(rd + 1) & 31];
222
- void *d3 = &env->vfp.zregs[(rd + 2) & 31];
223
-
224
- for (i = 0; i < oprsz; ) {
225
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
226
- do {
227
- if (pg & 1) {
228
- tlb_fn(env, d1, i, addr, ra);
229
- tlb_fn(env, d2, i, addr + msize, ra);
230
- tlb_fn(env, d3, i, addr + 2 * msize, ra);
231
- }
232
- i += esize, pg >>= esize;
233
- addr += 3 * msize;
234
- } while (i & 15);
235
- }
236
-}
237
-
238
-static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
239
- uint32_t desc, const uintptr_t ra,
240
- const int esize, const int msize,
241
- sve_ldst1_tlb_fn *tlb_fn)
242
-{
243
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
244
- intptr_t i, oprsz = simd_oprsz(desc);
245
- void *d1 = &env->vfp.zregs[rd];
246
- void *d2 = &env->vfp.zregs[(rd + 1) & 31];
247
- void *d3 = &env->vfp.zregs[(rd + 2) & 31];
248
- void *d4 = &env->vfp.zregs[(rd + 3) & 31];
249
-
250
- for (i = 0; i < oprsz; ) {
251
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
252
- do {
253
- if (pg & 1) {
254
- tlb_fn(env, d1, i, addr, ra);
255
- tlb_fn(env, d2, i, addr + msize, ra);
256
- tlb_fn(env, d3, i, addr + 2 * msize, ra);
257
- tlb_fn(env, d4, i, addr + 3 * msize, ra);
258
- }
259
- i += esize, pg >>= esize;
260
- addr += 4 * msize;
261
- } while (i & 15);
262
- }
263
-}
264
-
265
-#define DO_STN_1(N, NAME, ESIZE) \
266
-void QEMU_FLATTEN HELPER(sve_st##N##NAME##_r) \
267
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
268
+#define DO_STN_1(N, NAME, ESZ) \
269
+void HELPER(sve_st##N##NAME##_r)(CPUARMState *env, void *vg, \
270
+ target_ulong addr, uint32_t desc) \
271
{ \
272
- sve_st##N##_r(env, vg, addr, desc, GETPC(), ESIZE, 1, \
273
- sve_st1##NAME##_tlb); \
274
+ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, N, \
275
+ sve_st1##NAME##_host, sve_st1##NAME##_tlb); \
276
}
277
278
-#define DO_STN_2(N, NAME, ESIZE, MSIZE) \
279
-void QEMU_FLATTEN HELPER(sve_st##N##NAME##_le_r) \
280
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
281
+#define DO_STN_2(N, NAME, ESZ, MSZ) \
282
+void HELPER(sve_st##N##NAME##_le_r)(CPUARMState *env, void *vg, \
283
+ target_ulong addr, uint32_t desc) \
284
{ \
285
- sve_st##N##_r(env, vg, addr, desc, GETPC(), ESIZE, MSIZE, \
286
- sve_st1##NAME##_le_tlb); \
287
+ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, \
288
+ sve_st1##NAME##_le_host, sve_st1##NAME##_le_tlb); \
289
} \
290
-void QEMU_FLATTEN HELPER(sve_st##N##NAME##_be_r) \
291
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
292
+void HELPER(sve_st##N##NAME##_be_r)(CPUARMState *env, void *vg, \
293
+ target_ulong addr, uint32_t desc) \
294
{ \
295
- sve_st##N##_r(env, vg, addr, desc, GETPC(), ESIZE, MSIZE, \
296
- sve_st1##NAME##_be_tlb); \
297
+ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, \
298
+ sve_st1##NAME##_be_host, sve_st1##NAME##_be_tlb); \
299
}
300
301
-DO_STN_1(1, bb, 1)
302
-DO_STN_1(1, bh, 2)
303
-DO_STN_1(1, bs, 4)
304
-DO_STN_1(1, bd, 8)
305
-DO_STN_1(2, bb, 1)
306
-DO_STN_1(3, bb, 1)
307
-DO_STN_1(4, bb, 1)
308
+DO_STN_1(1, bb, MO_8)
309
+DO_STN_1(1, bh, MO_16)
310
+DO_STN_1(1, bs, MO_32)
311
+DO_STN_1(1, bd, MO_64)
312
+DO_STN_1(2, bb, MO_8)
313
+DO_STN_1(3, bb, MO_8)
314
+DO_STN_1(4, bb, MO_8)
315
316
-DO_STN_2(1, hh, 2, 2)
317
-DO_STN_2(1, hs, 4, 2)
318
-DO_STN_2(1, hd, 8, 2)
319
-DO_STN_2(2, hh, 2, 2)
320
-DO_STN_2(3, hh, 2, 2)
321
-DO_STN_2(4, hh, 2, 2)
322
+DO_STN_2(1, hh, MO_16, MO_16)
323
+DO_STN_2(1, hs, MO_32, MO_16)
324
+DO_STN_2(1, hd, MO_64, MO_16)
325
+DO_STN_2(2, hh, MO_16, MO_16)
326
+DO_STN_2(3, hh, MO_16, MO_16)
327
+DO_STN_2(4, hh, MO_16, MO_16)
328
329
-DO_STN_2(1, ss, 4, 4)
330
-DO_STN_2(1, sd, 8, 4)
331
-DO_STN_2(2, ss, 4, 4)
332
-DO_STN_2(3, ss, 4, 4)
333
-DO_STN_2(4, ss, 4, 4)
334
+DO_STN_2(1, ss, MO_32, MO_32)
335
+DO_STN_2(1, sd, MO_64, MO_32)
336
+DO_STN_2(2, ss, MO_32, MO_32)
337
+DO_STN_2(3, ss, MO_32, MO_32)
338
+DO_STN_2(4, ss, MO_32, MO_32)
339
340
-DO_STN_2(1, dd, 8, 8)
341
-DO_STN_2(2, dd, 8, 8)
342
-DO_STN_2(3, dd, 8, 8)
343
-DO_STN_2(4, dd, 8, 8)
344
+DO_STN_2(1, dd, MO_64, MO_64)
345
+DO_STN_2(2, dd, MO_64, MO_64)
346
+DO_STN_2(3, dd, MO_64, MO_64)
347
+DO_STN_2(4, dd, MO_64, MO_64)
348
349
#undef DO_STN_1
350
#undef DO_STN_2
351
--
352
2.20.1
353
354
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
This avoids the need for a separate set of helpers to implement
4
no-fault semantics, and will enable MTE in the future.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200508154359.7494-17-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/sve_helper.c | 323 ++++++++++++++++------------------------
12
1 file changed, 127 insertions(+), 196 deletions(-)
13
14
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/sve_helper.c
17
+++ b/target/arm/sve_helper.c
18
@@ -XXX,XX +XXX,XX @@ DO_LD1_ZPZ_D(dd_be, zd)
19
20
/* First fault loads with a vector index. */
21
22
-/* Load one element into VD+REG_OFF from (ENV,VADDR) without faulting.
23
- * The controlling predicate is known to be true. Return true if the
24
- * load was successful.
25
- */
26
-typedef bool sve_ld1_nf_fn(CPUARMState *env, void *vd, intptr_t reg_off,
27
- target_ulong vaddr, int mmu_idx);
28
-
29
-#ifdef CONFIG_SOFTMMU
30
-#define DO_LD_NF(NAME, H, TYPEE, TYPEM, HOST) \
31
-static bool sve_ld##NAME##_nf(CPUARMState *env, void *vd, intptr_t reg_off, \
32
- target_ulong addr, int mmu_idx) \
33
-{ \
34
- target_ulong next_page = -(addr | TARGET_PAGE_MASK); \
35
- if (likely(next_page - addr >= sizeof(TYPEM))) { \
36
- void *host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_idx); \
37
- if (likely(host)) { \
38
- TYPEM val = HOST(host); \
39
- *(TYPEE *)(vd + H(reg_off)) = val; \
40
- return true; \
41
- } \
42
- } \
43
- return false; \
44
-}
45
-#else
46
-#define DO_LD_NF(NAME, H, TYPEE, TYPEM, HOST) \
47
-static bool sve_ld##NAME##_nf(CPUARMState *env, void *vd, intptr_t reg_off, \
48
- target_ulong addr, int mmu_idx) \
49
-{ \
50
- if (likely(page_check_range(addr, sizeof(TYPEM), PAGE_READ))) { \
51
- TYPEM val = HOST(g2h(addr)); \
52
- *(TYPEE *)(vd + H(reg_off)) = val; \
53
- return true; \
54
- } \
55
- return false; \
56
-}
57
-#endif
58
-
59
-DO_LD_NF(bsu, H1_4, uint32_t, uint8_t, ldub_p)
60
-DO_LD_NF(bss, H1_4, uint32_t, int8_t, ldsb_p)
61
-DO_LD_NF(bdu, , uint64_t, uint8_t, ldub_p)
62
-DO_LD_NF(bds, , uint64_t, int8_t, ldsb_p)
63
-
64
-DO_LD_NF(hsu_le, H1_4, uint32_t, uint16_t, lduw_le_p)
65
-DO_LD_NF(hss_le, H1_4, uint32_t, int16_t, ldsw_le_p)
66
-DO_LD_NF(hsu_be, H1_4, uint32_t, uint16_t, lduw_be_p)
67
-DO_LD_NF(hss_be, H1_4, uint32_t, int16_t, ldsw_be_p)
68
-DO_LD_NF(hdu_le, , uint64_t, uint16_t, lduw_le_p)
69
-DO_LD_NF(hds_le, , uint64_t, int16_t, ldsw_le_p)
70
-DO_LD_NF(hdu_be, , uint64_t, uint16_t, lduw_be_p)
71
-DO_LD_NF(hds_be, , uint64_t, int16_t, ldsw_be_p)
72
-
73
-DO_LD_NF(ss_le, H1_4, uint32_t, uint32_t, ldl_le_p)
74
-DO_LD_NF(ss_be, H1_4, uint32_t, uint32_t, ldl_be_p)
75
-DO_LD_NF(sdu_le, , uint64_t, uint32_t, ldl_le_p)
76
-DO_LD_NF(sds_le, , uint64_t, int32_t, ldl_le_p)
77
-DO_LD_NF(sdu_be, , uint64_t, uint32_t, ldl_be_p)
78
-DO_LD_NF(sds_be, , uint64_t, int32_t, ldl_be_p)
79
-
80
-DO_LD_NF(dd_le, , uint64_t, uint64_t, ldq_le_p)
81
-DO_LD_NF(dd_be, , uint64_t, uint64_t, ldq_be_p)
82
-
83
/*
84
- * Common helper for all gather first-faulting loads.
85
+ * Common helpers for all gather first-faulting loads.
86
*/
87
-static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
88
- target_ulong base, uint32_t desc, uintptr_t ra,
89
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
90
- sve_ld1_nf_fn *nonfault_fn)
91
+
92
+static inline QEMU_ALWAYS_INLINE
93
+void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
94
+ target_ulong base, uint32_t desc, uintptr_t retaddr,
95
+ const int esz, const int msz, zreg_off_fn *off_fn,
96
+ sve_ldst1_host_fn *host_fn,
97
+ sve_ldst1_tlb_fn *tlb_fn)
98
{
99
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
100
- const int mmu_idx = get_mmuidx(oi);
101
+ const int mmu_idx = cpu_mmu_index(env, false);
102
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
103
- intptr_t reg_off, reg_max = simd_oprsz(desc);
104
- target_ulong addr;
105
+ const int esize = 1 << esz;
106
+ const int msize = 1 << msz;
107
+ const intptr_t reg_max = simd_oprsz(desc);
108
+ intptr_t reg_off;
109
+ SVEHostPage info;
110
+ target_ulong addr, in_page;
111
112
/* Skip to the first true predicate. */
113
- reg_off = find_next_active(vg, 0, reg_max, MO_32);
114
- if (likely(reg_off < reg_max)) {
115
- /* Perform one normal read, which will fault or not. */
116
- addr = off_fn(vm, reg_off);
117
- addr = base + (addr << scale);
118
- tlb_fn(env, vd, reg_off, addr, ra);
119
-
120
- /* The rest of the reads will be non-faulting. */
121
+ reg_off = find_next_active(vg, 0, reg_max, esz);
122
+ if (unlikely(reg_off >= reg_max)) {
123
+ /* The entire predicate was false; no load occurs. */
124
+ memset(vd, 0, reg_max);
125
+ return;
126
}
127
128
- /* After any fault, zero the leading predicated false elements. */
129
+ /*
130
+ * Probe the first element, allowing faults.
131
+ */
132
+ addr = base + (off_fn(vm, reg_off) << scale);
133
+ tlb_fn(env, vd, reg_off, addr, retaddr);
134
+
135
+ /* After any fault, zero the other elements. */
136
swap_memzero(vd, reg_off);
137
+ reg_off += esize;
138
+ swap_memzero(vd + reg_off, reg_max - reg_off);
139
140
- while (likely((reg_off += 4) < reg_max)) {
141
- uint64_t pg = *(uint64_t *)(vg + (reg_off >> 6) * 8);
142
- if (likely((pg >> (reg_off & 63)) & 1)) {
143
- addr = off_fn(vm, reg_off);
144
- addr = base + (addr << scale);
145
- if (!nonfault_fn(env, vd, reg_off, addr, mmu_idx)) {
146
- record_fault(env, reg_off, reg_max);
147
- break;
148
+ /*
149
+ * Probe the remaining elements, not allowing faults.
150
+ */
151
+ while (reg_off < reg_max) {
152
+ uint64_t pg = vg[reg_off >> 6];
153
+ do {
154
+ if (likely((pg >> (reg_off & 63)) & 1)) {
155
+ addr = base + (off_fn(vm, reg_off) << scale);
156
+ in_page = -(addr | TARGET_PAGE_MASK);
157
+
158
+ if (unlikely(in_page < msize)) {
159
+ /* Stop if the element crosses a page boundary. */
160
+ goto fault;
161
+ }
162
+
163
+ sve_probe_page(&info, true, env, addr, 0, MMU_DATA_LOAD,
164
+ mmu_idx, retaddr);
165
+ if (unlikely(info.flags & (TLB_INVALID_MASK | TLB_MMIO))) {
166
+ goto fault;
167
+ }
168
+ if (unlikely(info.flags & TLB_WATCHPOINT) &&
169
+ (cpu_watchpoint_address_matches
170
+ (env_cpu(env), addr, msize) & BP_MEM_READ)) {
171
+ goto fault;
172
+ }
173
+ /* TODO: MTE check. */
174
+
175
+ host_fn(vd, reg_off, info.host);
176
}
177
- } else {
178
- *(uint32_t *)(vd + H1_4(reg_off)) = 0;
179
- }
180
+ reg_off += esize;
181
+ } while (reg_off & 63);
182
}
183
+ return;
184
+
185
+ fault:
186
+ record_fault(env, reg_off, reg_max);
187
}
188
189
-static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
190
- target_ulong base, uint32_t desc, uintptr_t ra,
191
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
192
- sve_ld1_nf_fn *nonfault_fn)
193
-{
194
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
195
- const int mmu_idx = get_mmuidx(oi);
196
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
197
- intptr_t reg_off, reg_max = simd_oprsz(desc);
198
- target_ulong addr;
199
-
200
- /* Skip to the first true predicate. */
201
- reg_off = find_next_active(vg, 0, reg_max, MO_64);
202
- if (likely(reg_off < reg_max)) {
203
- /* Perform one normal read, which will fault or not. */
204
- addr = off_fn(vm, reg_off);
205
- addr = base + (addr << scale);
206
- tlb_fn(env, vd, reg_off, addr, ra);
207
-
208
- /* The rest of the reads will be non-faulting. */
209
- }
210
-
211
- /* After any fault, zero the leading predicated false elements. */
212
- swap_memzero(vd, reg_off);
213
-
214
- while (likely((reg_off += 8) < reg_max)) {
215
- uint8_t pg = *(uint8_t *)(vg + H1(reg_off >> 3));
216
- if (likely(pg & 1)) {
217
- addr = off_fn(vm, reg_off);
218
- addr = base + (addr << scale);
219
- if (!nonfault_fn(env, vd, reg_off, addr, mmu_idx)) {
220
- record_fault(env, reg_off, reg_max);
221
- break;
222
- }
223
- } else {
224
- *(uint64_t *)(vd + reg_off) = 0;
225
- }
226
- }
227
+#define DO_LDFF1_ZPZ_S(MEM, OFS, MSZ) \
228
+void HELPER(sve_ldff##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
229
+ void *vm, target_ulong base, uint32_t desc) \
230
+{ \
231
+ sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), MO_32, MSZ, \
232
+ off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
233
}
234
235
-#define DO_LDFF1_ZPZ_S(MEM, OFS) \
236
-void HELPER(sve_ldff##MEM##_##OFS) \
237
- (CPUARMState *env, void *vd, void *vg, void *vm, \
238
- target_ulong base, uint32_t desc) \
239
-{ \
240
- sve_ldff1_zs(env, vd, vg, vm, base, desc, GETPC(), \
241
- off_##OFS##_s, sve_ld1##MEM##_tlb, sve_ld##MEM##_nf); \
242
+#define DO_LDFF1_ZPZ_D(MEM, OFS, MSZ) \
243
+void HELPER(sve_ldff##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
244
+ void *vm, target_ulong base, uint32_t desc) \
245
+{ \
246
+ sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), MO_64, MSZ, \
247
+ off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
248
}
249
250
-#define DO_LDFF1_ZPZ_D(MEM, OFS) \
251
-void HELPER(sve_ldff##MEM##_##OFS) \
252
- (CPUARMState *env, void *vd, void *vg, void *vm, \
253
- target_ulong base, uint32_t desc) \
254
-{ \
255
- sve_ldff1_zd(env, vd, vg, vm, base, desc, GETPC(), \
256
- off_##OFS##_d, sve_ld1##MEM##_tlb, sve_ld##MEM##_nf); \
257
-}
258
+DO_LDFF1_ZPZ_S(bsu, zsu, MO_8)
259
+DO_LDFF1_ZPZ_S(bsu, zss, MO_8)
260
+DO_LDFF1_ZPZ_D(bdu, zsu, MO_8)
261
+DO_LDFF1_ZPZ_D(bdu, zss, MO_8)
262
+DO_LDFF1_ZPZ_D(bdu, zd, MO_8)
263
264
-DO_LDFF1_ZPZ_S(bsu, zsu)
265
-DO_LDFF1_ZPZ_S(bsu, zss)
266
-DO_LDFF1_ZPZ_D(bdu, zsu)
267
-DO_LDFF1_ZPZ_D(bdu, zss)
268
-DO_LDFF1_ZPZ_D(bdu, zd)
269
+DO_LDFF1_ZPZ_S(bss, zsu, MO_8)
270
+DO_LDFF1_ZPZ_S(bss, zss, MO_8)
271
+DO_LDFF1_ZPZ_D(bds, zsu, MO_8)
272
+DO_LDFF1_ZPZ_D(bds, zss, MO_8)
273
+DO_LDFF1_ZPZ_D(bds, zd, MO_8)
274
275
-DO_LDFF1_ZPZ_S(bss, zsu)
276
-DO_LDFF1_ZPZ_S(bss, zss)
277
-DO_LDFF1_ZPZ_D(bds, zsu)
278
-DO_LDFF1_ZPZ_D(bds, zss)
279
-DO_LDFF1_ZPZ_D(bds, zd)
280
+DO_LDFF1_ZPZ_S(hsu_le, zsu, MO_16)
281
+DO_LDFF1_ZPZ_S(hsu_le, zss, MO_16)
282
+DO_LDFF1_ZPZ_D(hdu_le, zsu, MO_16)
283
+DO_LDFF1_ZPZ_D(hdu_le, zss, MO_16)
284
+DO_LDFF1_ZPZ_D(hdu_le, zd, MO_16)
285
286
-DO_LDFF1_ZPZ_S(hsu_le, zsu)
287
-DO_LDFF1_ZPZ_S(hsu_le, zss)
288
-DO_LDFF1_ZPZ_D(hdu_le, zsu)
289
-DO_LDFF1_ZPZ_D(hdu_le, zss)
290
-DO_LDFF1_ZPZ_D(hdu_le, zd)
291
+DO_LDFF1_ZPZ_S(hsu_be, zsu, MO_16)
292
+DO_LDFF1_ZPZ_S(hsu_be, zss, MO_16)
293
+DO_LDFF1_ZPZ_D(hdu_be, zsu, MO_16)
294
+DO_LDFF1_ZPZ_D(hdu_be, zss, MO_16)
295
+DO_LDFF1_ZPZ_D(hdu_be, zd, MO_16)
296
297
-DO_LDFF1_ZPZ_S(hsu_be, zsu)
298
-DO_LDFF1_ZPZ_S(hsu_be, zss)
299
-DO_LDFF1_ZPZ_D(hdu_be, zsu)
300
-DO_LDFF1_ZPZ_D(hdu_be, zss)
301
-DO_LDFF1_ZPZ_D(hdu_be, zd)
302
+DO_LDFF1_ZPZ_S(hss_le, zsu, MO_16)
303
+DO_LDFF1_ZPZ_S(hss_le, zss, MO_16)
304
+DO_LDFF1_ZPZ_D(hds_le, zsu, MO_16)
305
+DO_LDFF1_ZPZ_D(hds_le, zss, MO_16)
306
+DO_LDFF1_ZPZ_D(hds_le, zd, MO_16)
307
308
-DO_LDFF1_ZPZ_S(hss_le, zsu)
309
-DO_LDFF1_ZPZ_S(hss_le, zss)
310
-DO_LDFF1_ZPZ_D(hds_le, zsu)
311
-DO_LDFF1_ZPZ_D(hds_le, zss)
312
-DO_LDFF1_ZPZ_D(hds_le, zd)
313
+DO_LDFF1_ZPZ_S(hss_be, zsu, MO_16)
314
+DO_LDFF1_ZPZ_S(hss_be, zss, MO_16)
315
+DO_LDFF1_ZPZ_D(hds_be, zsu, MO_16)
316
+DO_LDFF1_ZPZ_D(hds_be, zss, MO_16)
317
+DO_LDFF1_ZPZ_D(hds_be, zd, MO_16)
318
319
-DO_LDFF1_ZPZ_S(hss_be, zsu)
320
-DO_LDFF1_ZPZ_S(hss_be, zss)
321
-DO_LDFF1_ZPZ_D(hds_be, zsu)
322
-DO_LDFF1_ZPZ_D(hds_be, zss)
323
-DO_LDFF1_ZPZ_D(hds_be, zd)
324
+DO_LDFF1_ZPZ_S(ss_le, zsu, MO_32)
325
+DO_LDFF1_ZPZ_S(ss_le, zss, MO_32)
326
+DO_LDFF1_ZPZ_D(sdu_le, zsu, MO_32)
327
+DO_LDFF1_ZPZ_D(sdu_le, zss, MO_32)
328
+DO_LDFF1_ZPZ_D(sdu_le, zd, MO_32)
329
330
-DO_LDFF1_ZPZ_S(ss_le, zsu)
331
-DO_LDFF1_ZPZ_S(ss_le, zss)
332
-DO_LDFF1_ZPZ_D(sdu_le, zsu)
333
-DO_LDFF1_ZPZ_D(sdu_le, zss)
334
-DO_LDFF1_ZPZ_D(sdu_le, zd)
335
+DO_LDFF1_ZPZ_S(ss_be, zsu, MO_32)
336
+DO_LDFF1_ZPZ_S(ss_be, zss, MO_32)
337
+DO_LDFF1_ZPZ_D(sdu_be, zsu, MO_32)
338
+DO_LDFF1_ZPZ_D(sdu_be, zss, MO_32)
339
+DO_LDFF1_ZPZ_D(sdu_be, zd, MO_32)
340
341
-DO_LDFF1_ZPZ_S(ss_be, zsu)
342
-DO_LDFF1_ZPZ_S(ss_be, zss)
343
-DO_LDFF1_ZPZ_D(sdu_be, zsu)
344
-DO_LDFF1_ZPZ_D(sdu_be, zss)
345
-DO_LDFF1_ZPZ_D(sdu_be, zd)
346
+DO_LDFF1_ZPZ_D(sds_le, zsu, MO_32)
347
+DO_LDFF1_ZPZ_D(sds_le, zss, MO_32)
348
+DO_LDFF1_ZPZ_D(sds_le, zd, MO_32)
349
350
-DO_LDFF1_ZPZ_D(sds_le, zsu)
351
-DO_LDFF1_ZPZ_D(sds_le, zss)
352
-DO_LDFF1_ZPZ_D(sds_le, zd)
353
+DO_LDFF1_ZPZ_D(sds_be, zsu, MO_32)
354
+DO_LDFF1_ZPZ_D(sds_be, zss, MO_32)
355
+DO_LDFF1_ZPZ_D(sds_be, zd, MO_32)
356
357
-DO_LDFF1_ZPZ_D(sds_be, zsu)
358
-DO_LDFF1_ZPZ_D(sds_be, zss)
359
-DO_LDFF1_ZPZ_D(sds_be, zd)
360
+DO_LDFF1_ZPZ_D(dd_le, zsu, MO_64)
361
+DO_LDFF1_ZPZ_D(dd_le, zss, MO_64)
362
+DO_LDFF1_ZPZ_D(dd_le, zd, MO_64)
363
364
-DO_LDFF1_ZPZ_D(dd_le, zsu)
365
-DO_LDFF1_ZPZ_D(dd_le, zss)
366
-DO_LDFF1_ZPZ_D(dd_le, zd)
367
-
368
-DO_LDFF1_ZPZ_D(dd_be, zsu)
369
-DO_LDFF1_ZPZ_D(dd_be, zss)
370
-DO_LDFF1_ZPZ_D(dd_be, zd)
371
+DO_LDFF1_ZPZ_D(dd_be, zsu, MO_64)
372
+DO_LDFF1_ZPZ_D(dd_be, zss, MO_64)
373
+DO_LDFF1_ZPZ_D(dd_be, zd, MO_64)
374
375
/* Stores with a vector index. */
376
377
--
378
2.20.1
379
380
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200508154359.7494-18-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/sve_helper.c | 182 ++++++++++++++++++++++++----------------
9
1 file changed, 111 insertions(+), 71 deletions(-)
10
11
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/sve_helper.c
14
+++ b/target/arm/sve_helper.c
15
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_ZPZ_D(dd_be, zd, MO_64)
16
17
/* Stores with a vector index. */
18
19
-static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
20
- target_ulong base, uint32_t desc, uintptr_t ra,
21
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
22
+static inline QEMU_ALWAYS_INLINE
23
+void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
24
+ target_ulong base, uint32_t desc, uintptr_t retaddr,
25
+ int esize, int msize, zreg_off_fn *off_fn,
26
+ sve_ldst1_host_fn *host_fn,
27
+ sve_ldst1_tlb_fn *tlb_fn)
28
{
29
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
30
- intptr_t i, oprsz = simd_oprsz(desc);
31
+ const int mmu_idx = cpu_mmu_index(env, false);
32
+ const intptr_t reg_max = simd_oprsz(desc);
33
+ void *host[ARM_MAX_VQ * 4];
34
+ intptr_t reg_off, i;
35
+ SVEHostPage info, info2;
36
37
- for (i = 0; i < oprsz; ) {
38
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
39
+ /*
40
+ * Probe all of the elements for host addresses and flags.
41
+ */
42
+ i = reg_off = 0;
43
+ do {
44
+ uint64_t pg = vg[reg_off >> 6];
45
do {
46
- if (likely(pg & 1)) {
47
- target_ulong off = off_fn(vm, i);
48
- tlb_fn(env, vd, i, base + (off << scale), ra);
49
+ target_ulong addr = base + (off_fn(vm, reg_off) << scale);
50
+ target_ulong in_page = -(addr | TARGET_PAGE_MASK);
51
+
52
+ host[i] = NULL;
53
+ if (likely((pg >> (reg_off & 63)) & 1)) {
54
+ if (likely(in_page >= msize)) {
55
+ sve_probe_page(&info, false, env, addr, 0, MMU_DATA_STORE,
56
+ mmu_idx, retaddr);
57
+ host[i] = info.host;
58
+ } else {
59
+ /*
60
+ * Element crosses the page boundary.
61
+ * Probe both pages, but do not record the host address,
62
+ * so that we use the slow path.
63
+ */
64
+ sve_probe_page(&info, false, env, addr, 0,
65
+ MMU_DATA_STORE, mmu_idx, retaddr);
66
+ sve_probe_page(&info2, false, env, addr + in_page, 0,
67
+ MMU_DATA_STORE, mmu_idx, retaddr);
68
+ info.flags |= info2.flags;
69
+ }
70
+
71
+ if (unlikely(info.flags & TLB_WATCHPOINT)) {
72
+ cpu_check_watchpoint(env_cpu(env), addr, msize,
73
+ info.attrs, BP_MEM_WRITE, retaddr);
74
+ }
75
+ /* TODO: MTE check. */
76
}
77
- i += 4, pg >>= 4;
78
- } while (i & 15);
79
- }
80
-}
81
+ i += 1;
82
+ reg_off += esize;
83
+ } while (reg_off & 63);
84
+ } while (reg_off < reg_max);
85
86
-static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
87
- target_ulong base, uint32_t desc, uintptr_t ra,
88
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
89
-{
90
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
91
- intptr_t i, oprsz = simd_oprsz(desc) / 8;
92
-
93
- for (i = 0; i < oprsz; i++) {
94
- uint8_t pg = *(uint8_t *)(vg + H1(i));
95
- if (likely(pg & 1)) {
96
- target_ulong off = off_fn(vm, i * 8);
97
- tlb_fn(env, vd, i * 8, base + (off << scale), ra);
98
+ /*
99
+ * Now that we have recognized all exceptions except SyncExternal
100
+ * (from TLB_MMIO), which we cannot avoid, perform all of the stores.
101
+ *
102
+ * Note for the common case of an element in RAM, not crossing a page
103
+ * boundary, we have stored the host address in host[]. This doubles
104
+ * as a first-level check against the predicate, since only enabled
105
+ * elements have non-null host addresses.
106
+ */
107
+ i = reg_off = 0;
108
+ do {
109
+ void *h = host[i];
110
+ if (likely(h != NULL)) {
111
+ host_fn(vd, reg_off, h);
112
+ } else if ((vg[reg_off >> 6] >> (reg_off & 63)) & 1) {
113
+ target_ulong addr = base + (off_fn(vm, reg_off) << scale);
114
+ tlb_fn(env, vd, reg_off, addr, retaddr);
115
}
116
- }
117
+ i += 1;
118
+ reg_off += esize;
119
+ } while (reg_off < reg_max);
120
}
121
122
-#define DO_ST1_ZPZ_S(MEM, OFS) \
123
-void QEMU_FLATTEN HELPER(sve_st##MEM##_##OFS) \
124
- (CPUARMState *env, void *vd, void *vg, void *vm, \
125
- target_ulong base, uint32_t desc) \
126
-{ \
127
- sve_st1_zs(env, vd, vg, vm, base, desc, GETPC(), \
128
- off_##OFS##_s, sve_st1##MEM##_tlb); \
129
+#define DO_ST1_ZPZ_S(MEM, OFS, MSZ) \
130
+void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
131
+ void *vm, target_ulong base, uint32_t desc) \
132
+{ \
133
+ sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, \
134
+ off_##OFS##_s, sve_st1##MEM##_host, sve_st1##MEM##_tlb); \
135
}
136
137
-#define DO_ST1_ZPZ_D(MEM, OFS) \
138
-void QEMU_FLATTEN HELPER(sve_st##MEM##_##OFS) \
139
- (CPUARMState *env, void *vd, void *vg, void *vm, \
140
- target_ulong base, uint32_t desc) \
141
-{ \
142
- sve_st1_zd(env, vd, vg, vm, base, desc, GETPC(), \
143
- off_##OFS##_d, sve_st1##MEM##_tlb); \
144
+#define DO_ST1_ZPZ_D(MEM, OFS, MSZ) \
145
+void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
146
+ void *vm, target_ulong base, uint32_t desc) \
147
+{ \
148
+ sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, \
149
+ off_##OFS##_d, sve_st1##MEM##_host, sve_st1##MEM##_tlb); \
150
}
151
152
-DO_ST1_ZPZ_S(bs, zsu)
153
-DO_ST1_ZPZ_S(hs_le, zsu)
154
-DO_ST1_ZPZ_S(hs_be, zsu)
155
-DO_ST1_ZPZ_S(ss_le, zsu)
156
-DO_ST1_ZPZ_S(ss_be, zsu)
157
+DO_ST1_ZPZ_S(bs, zsu, MO_8)
158
+DO_ST1_ZPZ_S(hs_le, zsu, MO_16)
159
+DO_ST1_ZPZ_S(hs_be, zsu, MO_16)
160
+DO_ST1_ZPZ_S(ss_le, zsu, MO_32)
161
+DO_ST1_ZPZ_S(ss_be, zsu, MO_32)
162
163
-DO_ST1_ZPZ_S(bs, zss)
164
-DO_ST1_ZPZ_S(hs_le, zss)
165
-DO_ST1_ZPZ_S(hs_be, zss)
166
-DO_ST1_ZPZ_S(ss_le, zss)
167
-DO_ST1_ZPZ_S(ss_be, zss)
168
+DO_ST1_ZPZ_S(bs, zss, MO_8)
169
+DO_ST1_ZPZ_S(hs_le, zss, MO_16)
170
+DO_ST1_ZPZ_S(hs_be, zss, MO_16)
171
+DO_ST1_ZPZ_S(ss_le, zss, MO_32)
172
+DO_ST1_ZPZ_S(ss_be, zss, MO_32)
173
174
-DO_ST1_ZPZ_D(bd, zsu)
175
-DO_ST1_ZPZ_D(hd_le, zsu)
176
-DO_ST1_ZPZ_D(hd_be, zsu)
177
-DO_ST1_ZPZ_D(sd_le, zsu)
178
-DO_ST1_ZPZ_D(sd_be, zsu)
179
-DO_ST1_ZPZ_D(dd_le, zsu)
180
-DO_ST1_ZPZ_D(dd_be, zsu)
181
+DO_ST1_ZPZ_D(bd, zsu, MO_8)
182
+DO_ST1_ZPZ_D(hd_le, zsu, MO_16)
183
+DO_ST1_ZPZ_D(hd_be, zsu, MO_16)
184
+DO_ST1_ZPZ_D(sd_le, zsu, MO_32)
185
+DO_ST1_ZPZ_D(sd_be, zsu, MO_32)
186
+DO_ST1_ZPZ_D(dd_le, zsu, MO_64)
187
+DO_ST1_ZPZ_D(dd_be, zsu, MO_64)
188
189
-DO_ST1_ZPZ_D(bd, zss)
190
-DO_ST1_ZPZ_D(hd_le, zss)
191
-DO_ST1_ZPZ_D(hd_be, zss)
192
-DO_ST1_ZPZ_D(sd_le, zss)
193
-DO_ST1_ZPZ_D(sd_be, zss)
194
-DO_ST1_ZPZ_D(dd_le, zss)
195
-DO_ST1_ZPZ_D(dd_be, zss)
196
+DO_ST1_ZPZ_D(bd, zss, MO_8)
197
+DO_ST1_ZPZ_D(hd_le, zss, MO_16)
198
+DO_ST1_ZPZ_D(hd_be, zss, MO_16)
199
+DO_ST1_ZPZ_D(sd_le, zss, MO_32)
200
+DO_ST1_ZPZ_D(sd_be, zss, MO_32)
201
+DO_ST1_ZPZ_D(dd_le, zss, MO_64)
202
+DO_ST1_ZPZ_D(dd_be, zss, MO_64)
203
204
-DO_ST1_ZPZ_D(bd, zd)
205
-DO_ST1_ZPZ_D(hd_le, zd)
206
-DO_ST1_ZPZ_D(hd_be, zd)
207
-DO_ST1_ZPZ_D(sd_le, zd)
208
-DO_ST1_ZPZ_D(sd_be, zd)
209
-DO_ST1_ZPZ_D(dd_le, zd)
210
-DO_ST1_ZPZ_D(dd_be, zd)
211
+DO_ST1_ZPZ_D(bd, zd, MO_8)
212
+DO_ST1_ZPZ_D(hd_le, zd, MO_16)
213
+DO_ST1_ZPZ_D(hd_be, zd, MO_16)
214
+DO_ST1_ZPZ_D(sd_le, zd, MO_32)
215
+DO_ST1_ZPZ_D(sd_be, zd, MO_32)
216
+DO_ST1_ZPZ_D(dd_le, zd, MO_64)
217
+DO_ST1_ZPZ_D(dd_be, zd, MO_64)
218
219
#undef DO_ST1_ZPZ_S
220
#undef DO_ST1_ZPZ_D
221
--
222
2.20.1
223
224
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200508154359.7494-19-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/sve_helper.c | 208 +++++++++++++++++++++-------------------
9
1 file changed, 109 insertions(+), 99 deletions(-)
10
11
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/sve_helper.c
14
+++ b/target/arm/sve_helper.c
15
@@ -XXX,XX +XXX,XX @@ static target_ulong off_zd_d(void *reg, intptr_t reg_ofs)
16
return *(uint64_t *)(reg + reg_ofs);
17
}
18
19
-static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
20
- target_ulong base, uint32_t desc, uintptr_t ra,
21
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
22
+static inline QEMU_ALWAYS_INLINE
23
+void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
24
+ target_ulong base, uint32_t desc, uintptr_t retaddr,
25
+ int esize, int msize, zreg_off_fn *off_fn,
26
+ sve_ldst1_host_fn *host_fn,
27
+ sve_ldst1_tlb_fn *tlb_fn)
28
{
29
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
30
- intptr_t i, oprsz = simd_oprsz(desc);
31
- ARMVectorReg scratch = { };
32
+ const int mmu_idx = cpu_mmu_index(env, false);
33
+ const intptr_t reg_max = simd_oprsz(desc);
34
+ ARMVectorReg scratch;
35
+ intptr_t reg_off;
36
+ SVEHostPage info, info2;
37
38
- for (i = 0; i < oprsz; ) {
39
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
40
+ memset(&scratch, 0, reg_max);
41
+ reg_off = 0;
42
+ do {
43
+ uint64_t pg = vg[reg_off >> 6];
44
do {
45
if (likely(pg & 1)) {
46
- target_ulong off = off_fn(vm, i);
47
- tlb_fn(env, &scratch, i, base + (off << scale), ra);
48
+ target_ulong addr = base + (off_fn(vm, reg_off) << scale);
49
+ target_ulong in_page = -(addr | TARGET_PAGE_MASK);
50
+
51
+ sve_probe_page(&info, false, env, addr, 0, MMU_DATA_LOAD,
52
+ mmu_idx, retaddr);
53
+
54
+ if (likely(in_page >= msize)) {
55
+ if (unlikely(info.flags & TLB_WATCHPOINT)) {
56
+ cpu_check_watchpoint(env_cpu(env), addr, msize,
57
+ info.attrs, BP_MEM_READ, retaddr);
58
+ }
59
+ /* TODO: MTE check */
60
+ host_fn(&scratch, reg_off, info.host);
61
+ } else {
62
+ /* Element crosses the page boundary. */
63
+ sve_probe_page(&info2, false, env, addr + in_page, 0,
64
+ MMU_DATA_LOAD, mmu_idx, retaddr);
65
+ if (unlikely((info.flags | info2.flags) & TLB_WATCHPOINT)) {
66
+ cpu_check_watchpoint(env_cpu(env), addr,
67
+ msize, info.attrs,
68
+ BP_MEM_READ, retaddr);
69
+ }
70
+ /* TODO: MTE check */
71
+ tlb_fn(env, &scratch, reg_off, addr, retaddr);
72
+ }
73
}
74
- i += 4, pg >>= 4;
75
- } while (i & 15);
76
- }
77
+ reg_off += esize;
78
+ pg >>= esize;
79
+ } while (reg_off & 63);
80
+ } while (reg_off < reg_max);
81
82
/* Wait until all exceptions have been raised to write back. */
83
- memcpy(vd, &scratch, oprsz);
84
+ memcpy(vd, &scratch, reg_max);
85
}
86
87
-static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
88
- target_ulong base, uint32_t desc, uintptr_t ra,
89
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
90
-{
91
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
92
- intptr_t i, oprsz = simd_oprsz(desc) / 8;
93
- ARMVectorReg scratch = { };
94
-
95
- for (i = 0; i < oprsz; i++) {
96
- uint8_t pg = *(uint8_t *)(vg + H1(i));
97
- if (likely(pg & 1)) {
98
- target_ulong off = off_fn(vm, i * 8);
99
- tlb_fn(env, &scratch, i * 8, base + (off << scale), ra);
100
- }
101
- }
102
-
103
- /* Wait until all exceptions have been raised to write back. */
104
- memcpy(vd, &scratch, oprsz * 8);
105
+#define DO_LD1_ZPZ_S(MEM, OFS, MSZ) \
106
+void HELPER(sve_ld##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
107
+ void *vm, target_ulong base, uint32_t desc) \
108
+{ \
109
+ sve_ld1_z(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, \
110
+ off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
111
}
112
113
-#define DO_LD1_ZPZ_S(MEM, OFS) \
114
-void QEMU_FLATTEN HELPER(sve_ld##MEM##_##OFS) \
115
- (CPUARMState *env, void *vd, void *vg, void *vm, \
116
- target_ulong base, uint32_t desc) \
117
-{ \
118
- sve_ld1_zs(env, vd, vg, vm, base, desc, GETPC(), \
119
- off_##OFS##_s, sve_ld1##MEM##_tlb); \
120
+#define DO_LD1_ZPZ_D(MEM, OFS, MSZ) \
121
+void HELPER(sve_ld##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
122
+ void *vm, target_ulong base, uint32_t desc) \
123
+{ \
124
+ sve_ld1_z(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, \
125
+ off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
126
}
127
128
-#define DO_LD1_ZPZ_D(MEM, OFS) \
129
-void QEMU_FLATTEN HELPER(sve_ld##MEM##_##OFS) \
130
- (CPUARMState *env, void *vd, void *vg, void *vm, \
131
- target_ulong base, uint32_t desc) \
132
-{ \
133
- sve_ld1_zd(env, vd, vg, vm, base, desc, GETPC(), \
134
- off_##OFS##_d, sve_ld1##MEM##_tlb); \
135
-}
136
+DO_LD1_ZPZ_S(bsu, zsu, MO_8)
137
+DO_LD1_ZPZ_S(bsu, zss, MO_8)
138
+DO_LD1_ZPZ_D(bdu, zsu, MO_8)
139
+DO_LD1_ZPZ_D(bdu, zss, MO_8)
140
+DO_LD1_ZPZ_D(bdu, zd, MO_8)
141
142
-DO_LD1_ZPZ_S(bsu, zsu)
143
-DO_LD1_ZPZ_S(bsu, zss)
144
-DO_LD1_ZPZ_D(bdu, zsu)
145
-DO_LD1_ZPZ_D(bdu, zss)
146
-DO_LD1_ZPZ_D(bdu, zd)
147
+DO_LD1_ZPZ_S(bss, zsu, MO_8)
148
+DO_LD1_ZPZ_S(bss, zss, MO_8)
149
+DO_LD1_ZPZ_D(bds, zsu, MO_8)
150
+DO_LD1_ZPZ_D(bds, zss, MO_8)
151
+DO_LD1_ZPZ_D(bds, zd, MO_8)
152
153
-DO_LD1_ZPZ_S(bss, zsu)
154
-DO_LD1_ZPZ_S(bss, zss)
155
-DO_LD1_ZPZ_D(bds, zsu)
156
-DO_LD1_ZPZ_D(bds, zss)
157
-DO_LD1_ZPZ_D(bds, zd)
158
+DO_LD1_ZPZ_S(hsu_le, zsu, MO_16)
159
+DO_LD1_ZPZ_S(hsu_le, zss, MO_16)
160
+DO_LD1_ZPZ_D(hdu_le, zsu, MO_16)
161
+DO_LD1_ZPZ_D(hdu_le, zss, MO_16)
162
+DO_LD1_ZPZ_D(hdu_le, zd, MO_16)
163
164
-DO_LD1_ZPZ_S(hsu_le, zsu)
165
-DO_LD1_ZPZ_S(hsu_le, zss)
166
-DO_LD1_ZPZ_D(hdu_le, zsu)
167
-DO_LD1_ZPZ_D(hdu_le, zss)
168
-DO_LD1_ZPZ_D(hdu_le, zd)
169
+DO_LD1_ZPZ_S(hsu_be, zsu, MO_16)
170
+DO_LD1_ZPZ_S(hsu_be, zss, MO_16)
171
+DO_LD1_ZPZ_D(hdu_be, zsu, MO_16)
172
+DO_LD1_ZPZ_D(hdu_be, zss, MO_16)
173
+DO_LD1_ZPZ_D(hdu_be, zd, MO_16)
174
175
-DO_LD1_ZPZ_S(hsu_be, zsu)
176
-DO_LD1_ZPZ_S(hsu_be, zss)
177
-DO_LD1_ZPZ_D(hdu_be, zsu)
178
-DO_LD1_ZPZ_D(hdu_be, zss)
179
-DO_LD1_ZPZ_D(hdu_be, zd)
180
+DO_LD1_ZPZ_S(hss_le, zsu, MO_16)
181
+DO_LD1_ZPZ_S(hss_le, zss, MO_16)
182
+DO_LD1_ZPZ_D(hds_le, zsu, MO_16)
183
+DO_LD1_ZPZ_D(hds_le, zss, MO_16)
184
+DO_LD1_ZPZ_D(hds_le, zd, MO_16)
185
186
-DO_LD1_ZPZ_S(hss_le, zsu)
187
-DO_LD1_ZPZ_S(hss_le, zss)
188
-DO_LD1_ZPZ_D(hds_le, zsu)
189
-DO_LD1_ZPZ_D(hds_le, zss)
190
-DO_LD1_ZPZ_D(hds_le, zd)
191
+DO_LD1_ZPZ_S(hss_be, zsu, MO_16)
192
+DO_LD1_ZPZ_S(hss_be, zss, MO_16)
193
+DO_LD1_ZPZ_D(hds_be, zsu, MO_16)
194
+DO_LD1_ZPZ_D(hds_be, zss, MO_16)
195
+DO_LD1_ZPZ_D(hds_be, zd, MO_16)
196
197
-DO_LD1_ZPZ_S(hss_be, zsu)
198
-DO_LD1_ZPZ_S(hss_be, zss)
199
-DO_LD1_ZPZ_D(hds_be, zsu)
200
-DO_LD1_ZPZ_D(hds_be, zss)
201
-DO_LD1_ZPZ_D(hds_be, zd)
202
+DO_LD1_ZPZ_S(ss_le, zsu, MO_32)
203
+DO_LD1_ZPZ_S(ss_le, zss, MO_32)
204
+DO_LD1_ZPZ_D(sdu_le, zsu, MO_32)
205
+DO_LD1_ZPZ_D(sdu_le, zss, MO_32)
206
+DO_LD1_ZPZ_D(sdu_le, zd, MO_32)
207
208
-DO_LD1_ZPZ_S(ss_le, zsu)
209
-DO_LD1_ZPZ_S(ss_le, zss)
210
-DO_LD1_ZPZ_D(sdu_le, zsu)
211
-DO_LD1_ZPZ_D(sdu_le, zss)
212
-DO_LD1_ZPZ_D(sdu_le, zd)
213
+DO_LD1_ZPZ_S(ss_be, zsu, MO_32)
214
+DO_LD1_ZPZ_S(ss_be, zss, MO_32)
215
+DO_LD1_ZPZ_D(sdu_be, zsu, MO_32)
216
+DO_LD1_ZPZ_D(sdu_be, zss, MO_32)
217
+DO_LD1_ZPZ_D(sdu_be, zd, MO_32)
218
219
-DO_LD1_ZPZ_S(ss_be, zsu)
220
-DO_LD1_ZPZ_S(ss_be, zss)
221
-DO_LD1_ZPZ_D(sdu_be, zsu)
222
-DO_LD1_ZPZ_D(sdu_be, zss)
223
-DO_LD1_ZPZ_D(sdu_be, zd)
224
+DO_LD1_ZPZ_D(sds_le, zsu, MO_32)
225
+DO_LD1_ZPZ_D(sds_le, zss, MO_32)
226
+DO_LD1_ZPZ_D(sds_le, zd, MO_32)
227
228
-DO_LD1_ZPZ_D(sds_le, zsu)
229
-DO_LD1_ZPZ_D(sds_le, zss)
230
-DO_LD1_ZPZ_D(sds_le, zd)
231
+DO_LD1_ZPZ_D(sds_be, zsu, MO_32)
232
+DO_LD1_ZPZ_D(sds_be, zss, MO_32)
233
+DO_LD1_ZPZ_D(sds_be, zd, MO_32)
234
235
-DO_LD1_ZPZ_D(sds_be, zsu)
236
-DO_LD1_ZPZ_D(sds_be, zss)
237
-DO_LD1_ZPZ_D(sds_be, zd)
238
+DO_LD1_ZPZ_D(dd_le, zsu, MO_64)
239
+DO_LD1_ZPZ_D(dd_le, zss, MO_64)
240
+DO_LD1_ZPZ_D(dd_le, zd, MO_64)
241
242
-DO_LD1_ZPZ_D(dd_le, zsu)
243
-DO_LD1_ZPZ_D(dd_le, zss)
244
-DO_LD1_ZPZ_D(dd_le, zd)
245
-
246
-DO_LD1_ZPZ_D(dd_be, zsu)
247
-DO_LD1_ZPZ_D(dd_be, zss)
248
-DO_LD1_ZPZ_D(dd_be, zd)
249
+DO_LD1_ZPZ_D(dd_be, zsu, MO_64)
250
+DO_LD1_ZPZ_D(dd_be, zss, MO_64)
251
+DO_LD1_ZPZ_D(dd_be, zd, MO_64)
252
253
#undef DO_LD1_ZPZ_S
254
#undef DO_LD1_ZPZ_D
255
--
256
2.20.1
257
258
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
None of the sve helpers use TCGMemOpIdx any longer, so we can
4
stop passing it.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200508154359.7494-20-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/internals.h | 5 -----
12
target/arm/sve_helper.c | 14 +++++++-------
13
target/arm/translate-sve.c | 17 +++--------------
14
3 files changed, 10 insertions(+), 26 deletions(-)
15
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/internals.h
19
+++ b/target/arm/internals.h
20
@@ -XXX,XX +XXX,XX @@ static inline int arm_num_ctx_cmps(ARMCPU *cpu)
21
}
22
}
23
24
-/* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3.
25
- * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits.
26
- */
27
-#define MEMOPIDX_SHIFT 8
28
-
29
/**
30
* v7m_using_psp: Return true if using process stack pointer
31
* Return true if the CPU is currently using the process stack
32
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/sve_helper.c
35
+++ b/target/arm/sve_helper.c
36
@@ -XXX,XX +XXX,XX @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
37
sve_ldst1_host_fn *host_fn,
38
sve_ldst1_tlb_fn *tlb_fn)
39
{
40
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
41
+ const unsigned rd = simd_data(desc);
42
const intptr_t reg_max = simd_oprsz(desc);
43
intptr_t reg_off, reg_last, mem_off;
44
SVEContLdSt info;
45
@@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
46
sve_ldst1_host_fn *host_fn,
47
sve_ldst1_tlb_fn *tlb_fn)
48
{
49
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
50
+ const unsigned rd = simd_data(desc);
51
void *vd = &env->vfp.zregs[rd];
52
const intptr_t reg_max = simd_oprsz(desc);
53
intptr_t reg_off, mem_off, reg_last;
54
@@ -XXX,XX +XXX,XX @@ void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, uint32_t desc,
55
sve_ldst1_host_fn *host_fn,
56
sve_ldst1_tlb_fn *tlb_fn)
57
{
58
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
59
+ const unsigned rd = simd_data(desc);
60
const intptr_t reg_max = simd_oprsz(desc);
61
intptr_t reg_off, reg_last, mem_off;
62
SVEContLdSt info;
63
@@ -XXX,XX +XXX,XX @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
64
sve_ldst1_host_fn *host_fn,
65
sve_ldst1_tlb_fn *tlb_fn)
66
{
67
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
68
const int mmu_idx = cpu_mmu_index(env, false);
69
const intptr_t reg_max = simd_oprsz(desc);
70
+ const int scale = simd_data(desc);
71
ARMVectorReg scratch;
72
intptr_t reg_off;
73
SVEHostPage info, info2;
74
@@ -XXX,XX +XXX,XX @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
75
sve_ldst1_tlb_fn *tlb_fn)
76
{
77
const int mmu_idx = cpu_mmu_index(env, false);
78
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
79
+ const intptr_t reg_max = simd_oprsz(desc);
80
+ const int scale = simd_data(desc);
81
const int esize = 1 << esz;
82
const int msize = 1 << msz;
83
- const intptr_t reg_max = simd_oprsz(desc);
84
intptr_t reg_off;
85
SVEHostPage info;
86
target_ulong addr, in_page;
87
@@ -XXX,XX +XXX,XX @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
88
sve_ldst1_host_fn *host_fn,
89
sve_ldst1_tlb_fn *tlb_fn)
90
{
91
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
92
const int mmu_idx = cpu_mmu_index(env, false);
93
const intptr_t reg_max = simd_oprsz(desc);
94
+ const int scale = simd_data(desc);
95
void *host[ARM_MAX_VQ * 4];
96
intptr_t reg_off, i;
97
SVEHostPage info, info2;
98
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/translate-sve.c
101
+++ b/target/arm/translate-sve.c
102
@@ -XXX,XX +XXX,XX @@ static const uint8_t dtype_esz[16] = {
103
3, 2, 1, 3
104
};
105
106
-static TCGMemOpIdx sve_memopidx(DisasContext *s, int dtype)
107
-{
108
- return make_memop_idx(s->be_data | dtype_mop[dtype], get_mem_index(s));
109
-}
110
-
111
static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
112
int dtype, gen_helper_gvec_mem *fn)
113
{
114
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
115
* registers as pointers, so encode the regno into the data field.
116
* For consistency, do this even for LD1.
117
*/
118
- desc = sve_memopidx(s, dtype);
119
- desc |= zt << MEMOPIDX_SHIFT;
120
- desc = simd_desc(vsz, vsz, desc);
121
+ desc = simd_desc(vsz, vsz, zt);
122
t_desc = tcg_const_i32(desc);
123
t_pg = tcg_temp_new_ptr();
124
125
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int msz)
126
int desc, poff;
127
128
/* Load the first quadword using the normal predicated load helpers. */
129
- desc = sve_memopidx(s, msz_dtype(s, msz));
130
- desc |= zt << MEMOPIDX_SHIFT;
131
- desc = simd_desc(16, 16, desc);
132
+ desc = simd_desc(16, 16, zt);
133
t_desc = tcg_const_i32(desc);
134
135
poff = pred_full_reg_offset(s, pg);
136
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
137
TCGv_i32 t_desc;
138
int desc;
139
140
- desc = sve_memopidx(s, msz_dtype(s, msz));
141
- desc |= scale << MEMOPIDX_SHIFT;
142
- desc = simd_desc(vsz, vsz, desc);
143
+ desc = simd_desc(vsz, vsz, scale);
144
t_desc = tcg_const_i32(desc);
145
146
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
147
--
148
2.20.1
149
150
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
We want to move the inlined declarations of set_feature()
4
from cpu*.c to cpu.h. To avoid clashing with the KVM
5
declarations, inline the few KVM calls.
6
7
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20200504172448.9402-2-philmd@redhat.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/kvm32.c | 13 ++++---------
13
target/arm/kvm64.c | 22 ++++++----------------
14
2 files changed, 10 insertions(+), 25 deletions(-)
15
16
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/kvm32.c
19
+++ b/target/arm/kvm32.c
20
@@ -XXX,XX +XXX,XX @@
21
#include "internals.h"
22
#include "qemu/log.h"
23
24
-static inline void set_feature(uint64_t *features, int feature)
25
-{
26
- *features |= 1ULL << feature;
27
-}
28
-
29
static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
30
{
31
struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
32
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
33
* timers; this in turn implies most of the other feature
34
* bits, but a few must be tested.
35
*/
36
- set_feature(&features, ARM_FEATURE_V7VE);
37
- set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
38
+ features |= 1ULL << ARM_FEATURE_V7VE;
39
+ features |= 1ULL << ARM_FEATURE_GENERIC_TIMER;
40
41
if (extract32(id_pfr0, 12, 4) == 1) {
42
- set_feature(&features, ARM_FEATURE_THUMB2EE);
43
+ features |= 1ULL << ARM_FEATURE_THUMB2EE;
44
}
45
if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
46
- set_feature(&features, ARM_FEATURE_NEON);
47
+ features |= 1ULL << ARM_FEATURE_NEON;
48
}
49
50
ahcf->features = features;
51
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/kvm64.c
54
+++ b/target/arm/kvm64.c
55
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
56
}
57
}
58
59
-static inline void set_feature(uint64_t *features, int feature)
60
-{
61
- *features |= 1ULL << feature;
62
-}
63
-
64
-static inline void unset_feature(uint64_t *features, int feature)
65
-{
66
- *features &= ~(1ULL << feature);
67
-}
68
-
69
static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
70
{
71
uint64_t ret;
72
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
73
* with VFPv4+Neon; this in turn implies most of the other
74
* feature bits.
75
*/
76
- set_feature(&features, ARM_FEATURE_V8);
77
- set_feature(&features, ARM_FEATURE_NEON);
78
- set_feature(&features, ARM_FEATURE_AARCH64);
79
- set_feature(&features, ARM_FEATURE_PMU);
80
- set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
81
+ features |= 1ULL << ARM_FEATURE_V8;
82
+ features |= 1ULL << ARM_FEATURE_NEON;
83
+ features |= 1ULL << ARM_FEATURE_AARCH64;
84
+ features |= 1ULL << ARM_FEATURE_PMU;
85
+ features |= 1ULL << ARM_FEATURE_GENERIC_TIMER;
86
87
ahcf->features = features;
88
89
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
90
if (cpu->has_pmu) {
91
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
92
} else {
93
- unset_feature(&env->features, ARM_FEATURE_PMU);
94
+ env->features &= ~(1ULL << ARM_FEATURE_PMU);
95
}
96
if (cpu_isar_feature(aa64_sve, cpu)) {
97
assert(kvm_arm_sve_supported(cs));
98
--
99
2.20.1
100
101
diff view generated by jsdifflib
Deleted patch
1
From: Thomas Huth <thuth@redhat.com>
2
1
3
Move the common set_feature() and unset_feature() functions
4
from cpu.c and cpu64.c to cpu.h.
5
6
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Thomas Huth <thuth@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20200504172448.9402-3-philmd@redhat.com
12
Message-ID: <20190921150420.30743-2-thuth@redhat.com>
13
[PMD: Split Thomas's patch in two: set_feature, cpu_register]
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/cpu.h | 10 ++++++++++
18
target/arm/cpu.c | 10 ----------
19
target/arm/cpu64.c | 10 ----------
20
3 files changed, 10 insertions(+), 20 deletions(-)
21
22
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/cpu.h
25
+++ b/target/arm/cpu.h
26
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
27
void *gicv3state;
28
} CPUARMState;
29
30
+static inline void set_feature(CPUARMState *env, int feature)
31
+{
32
+ env->features |= 1ULL << feature;
33
+}
34
+
35
+static inline void unset_feature(CPUARMState *env, int feature)
36
+{
37
+ env->features &= ~(1ULL << feature);
38
+}
39
+
40
/**
41
* ARMELChangeHookFn:
42
* type of a function which can be registered via arm_register_el_change_hook()
43
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/cpu.c
46
+++ b/target/arm/cpu.c
47
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
48
49
#endif
50
51
-static inline void set_feature(CPUARMState *env, int feature)
52
-{
53
- env->features |= 1ULL << feature;
54
-}
55
-
56
-static inline void unset_feature(CPUARMState *env, int feature)
57
-{
58
- env->features &= ~(1ULL << feature);
59
-}
60
-
61
static int
62
print_insn_thumb1(bfd_vma pc, disassemble_info *info)
63
{
64
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
65
index XXXXXXX..XXXXXXX 100644
66
--- a/target/arm/cpu64.c
67
+++ b/target/arm/cpu64.c
68
@@ -XXX,XX +XXX,XX @@
69
#include "kvm_arm.h"
70
#include "qapi/visitor.h"
71
72
-static inline void set_feature(CPUARMState *env, int feature)
73
-{
74
- env->features |= 1ULL << feature;
75
-}
76
-
77
-static inline void unset_feature(CPUARMState *env, int feature)
78
-{
79
- env->features &= ~(1ULL << feature);
80
-}
81
-
82
#ifndef CONFIG_USER_ONLY
83
static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
84
{
85
--
86
2.20.1
87
88
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Use ARRAY_SIZE() to iterate over ARMCPUInfo[].
4
5
Since on the aarch64-linux-user build, arm_cpus[] is empty, add
6
the cpu_count variable and only iterate when it is non-zero.
7
8
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20200504172448.9402-4-philmd@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/cpu.c | 16 +++++++++-------
15
target/arm/cpu64.c | 8 +++-----
16
2 files changed, 12 insertions(+), 12 deletions(-)
17
18
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.c
21
+++ b/target/arm/cpu.c
22
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {
23
{ .name = "any", .initfn = arm_max_initfn },
24
#endif
25
#endif
26
- { .name = NULL }
27
};
28
29
static Property arm_cpu_properties[] = {
30
@@ -XXX,XX +XXX,XX @@ static const TypeInfo idau_interface_type_info = {
31
32
static void arm_cpu_register_types(void)
33
{
34
- const ARMCPUInfo *info = arm_cpus;
35
+ const size_t cpu_count = ARRAY_SIZE(arm_cpus);
36
37
type_register_static(&arm_cpu_type_info);
38
type_register_static(&idau_interface_type_info);
39
40
- while (info->name) {
41
- arm_cpu_register(info);
42
- info++;
43
- }
44
-
45
#ifdef CONFIG_KVM
46
type_register_static(&host_arm_cpu_type_info);
47
#endif
48
+
49
+ if (cpu_count) {
50
+ size_t i;
51
+
52
+ for (i = 0; i < cpu_count; ++i) {
53
+ arm_cpu_register(&arm_cpus[i]);
54
+ }
55
+ }
56
}
57
58
type_init(arm_cpu_register_types)
59
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/target/arm/cpu64.c
62
+++ b/target/arm/cpu64.c
63
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
64
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
65
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
66
{ .name = "max", .initfn = aarch64_max_initfn },
67
- { .name = NULL }
68
};
69
70
static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
71
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aarch64_cpu_type_info = {
72
73
static void aarch64_cpu_register_types(void)
74
{
75
- const ARMCPUInfo *info = aarch64_cpus;
76
+ size_t i;
77
78
type_register_static(&aarch64_cpu_type_info);
79
80
- while (info->name) {
81
- aarch64_cpu_register(info);
82
- info++;
83
+ for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
84
+ aarch64_cpu_register(&aarch64_cpus[i]);
85
}
86
}
87
88
--
89
2.20.1
90
91
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
As IDAU is a v8M feature, restrict it to the Aarch32 CPUs.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200504172448.9402-5-philmd@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/cpu.c | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
12
13
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.c
16
+++ b/target/arm/cpu.c
17
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void)
18
const size_t cpu_count = ARRAY_SIZE(arm_cpus);
19
20
type_register_static(&arm_cpu_type_info);
21
- type_register_static(&idau_interface_type_info);
22
23
#ifdef CONFIG_KVM
24
type_register_static(&host_arm_cpu_type_info);
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void)
26
if (cpu_count) {
27
size_t i;
28
29
+ type_register_static(&idau_interface_type_info);
30
for (i = 0; i < cpu_count; ++i) {
31
arm_cpu_register(&arm_cpus[i]);
32
}
33
--
34
2.20.1
35
36
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
A KVM-only build won't be able to run TCG cpus.
4
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-id: 20200504172448.9402-6-philmd@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/cpu.c | 634 -------------------------------------
11
target/arm/cpu_tcg.c | 664 +++++++++++++++++++++++++++++++++++++++
12
target/arm/Makefile.objs | 1 +
13
3 files changed, 665 insertions(+), 634 deletions(-)
14
create mode 100644 target/arm/cpu_tcg.c
15
16
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.c
19
+++ b/target/arm/cpu.c
20
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
21
return true;
22
}
23
24
-#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
25
-static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
26
-{
27
- CPUClass *cc = CPU_GET_CLASS(cs);
28
- ARMCPU *cpu = ARM_CPU(cs);
29
- CPUARMState *env = &cpu->env;
30
- bool ret = false;
31
-
32
- /*
33
- * ARMv7-M interrupt masking works differently than -A or -R.
34
- * There is no FIQ/IRQ distinction. Instead of I and F bits
35
- * masking FIQ and IRQ interrupts, an exception is taken only
36
- * if it is higher priority than the current execution priority
37
- * (which depends on state like BASEPRI, FAULTMASK and the
38
- * currently active exception).
39
- */
40
- if (interrupt_request & CPU_INTERRUPT_HARD
41
- && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
42
- cs->exception_index = EXCP_IRQ;
43
- cc->do_interrupt(cs);
44
- ret = true;
45
- }
46
- return ret;
47
-}
48
-#endif
49
-
50
void arm_cpu_update_virq(ARMCPU *cpu)
51
{
52
/*
53
@@ -XXX,XX +XXX,XX @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
54
/* CPU models. These are not needed for the AArch64 linux-user build. */
55
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
56
57
-static void arm926_initfn(Object *obj)
58
-{
59
- ARMCPU *cpu = ARM_CPU(obj);
60
-
61
- cpu->dtb_compatible = "arm,arm926";
62
- set_feature(&cpu->env, ARM_FEATURE_V5);
63
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
64
- set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
65
- cpu->midr = 0x41069265;
66
- cpu->reset_fpsid = 0x41011090;
67
- cpu->ctr = 0x1dd20d2;
68
- cpu->reset_sctlr = 0x00090078;
69
-
70
- /*
71
- * ARMv5 does not have the ID_ISAR registers, but we can still
72
- * set the field to indicate Jazelle support within QEMU.
73
- */
74
- cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
75
- /*
76
- * Similarly, we need to set MVFR0 fields to enable vfp and short vector
77
- * support even though ARMv5 doesn't have this register.
78
- */
79
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
80
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
81
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
82
-}
83
-
84
-static void arm946_initfn(Object *obj)
85
-{
86
- ARMCPU *cpu = ARM_CPU(obj);
87
-
88
- cpu->dtb_compatible = "arm,arm946";
89
- set_feature(&cpu->env, ARM_FEATURE_V5);
90
- set_feature(&cpu->env, ARM_FEATURE_PMSA);
91
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
92
- cpu->midr = 0x41059461;
93
- cpu->ctr = 0x0f004006;
94
- cpu->reset_sctlr = 0x00000078;
95
-}
96
-
97
-static void arm1026_initfn(Object *obj)
98
-{
99
- ARMCPU *cpu = ARM_CPU(obj);
100
-
101
- cpu->dtb_compatible = "arm,arm1026";
102
- set_feature(&cpu->env, ARM_FEATURE_V5);
103
- set_feature(&cpu->env, ARM_FEATURE_AUXCR);
104
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
105
- set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
106
- cpu->midr = 0x4106a262;
107
- cpu->reset_fpsid = 0x410110a0;
108
- cpu->ctr = 0x1dd20d2;
109
- cpu->reset_sctlr = 0x00090078;
110
- cpu->reset_auxcr = 1;
111
-
112
- /*
113
- * ARMv5 does not have the ID_ISAR registers, but we can still
114
- * set the field to indicate Jazelle support within QEMU.
115
- */
116
- cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
117
- /*
118
- * Similarly, we need to set MVFR0 fields to enable vfp and short vector
119
- * support even though ARMv5 doesn't have this register.
120
- */
121
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
122
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
123
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
124
-
125
- {
126
- /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
127
- ARMCPRegInfo ifar = {
128
- .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
129
- .access = PL1_RW,
130
- .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
131
- .resetvalue = 0
132
- };
133
- define_one_arm_cp_reg(cpu, &ifar);
134
- }
135
-}
136
-
137
-static void arm1136_r2_initfn(Object *obj)
138
-{
139
- ARMCPU *cpu = ARM_CPU(obj);
140
- /*
141
- * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
142
- * older core than plain "arm1136". In particular this does not
143
- * have the v6K features.
144
- * These ID register values are correct for 1136 but may be wrong
145
- * for 1136_r2 (in particular r0p2 does not actually implement most
146
- * of the ID registers).
147
- */
148
-
149
- cpu->dtb_compatible = "arm,arm1136";
150
- set_feature(&cpu->env, ARM_FEATURE_V6);
151
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
152
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
153
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
154
- cpu->midr = 0x4107b362;
155
- cpu->reset_fpsid = 0x410120b4;
156
- cpu->isar.mvfr0 = 0x11111111;
157
- cpu->isar.mvfr1 = 0x00000000;
158
- cpu->ctr = 0x1dd20d2;
159
- cpu->reset_sctlr = 0x00050078;
160
- cpu->id_pfr0 = 0x111;
161
- cpu->id_pfr1 = 0x1;
162
- cpu->isar.id_dfr0 = 0x2;
163
- cpu->id_afr0 = 0x3;
164
- cpu->isar.id_mmfr0 = 0x01130003;
165
- cpu->isar.id_mmfr1 = 0x10030302;
166
- cpu->isar.id_mmfr2 = 0x01222110;
167
- cpu->isar.id_isar0 = 0x00140011;
168
- cpu->isar.id_isar1 = 0x12002111;
169
- cpu->isar.id_isar2 = 0x11231111;
170
- cpu->isar.id_isar3 = 0x01102131;
171
- cpu->isar.id_isar4 = 0x141;
172
- cpu->reset_auxcr = 7;
173
-}
174
-
175
-static void arm1136_initfn(Object *obj)
176
-{
177
- ARMCPU *cpu = ARM_CPU(obj);
178
-
179
- cpu->dtb_compatible = "arm,arm1136";
180
- set_feature(&cpu->env, ARM_FEATURE_V6K);
181
- set_feature(&cpu->env, ARM_FEATURE_V6);
182
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
183
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
184
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
185
- cpu->midr = 0x4117b363;
186
- cpu->reset_fpsid = 0x410120b4;
187
- cpu->isar.mvfr0 = 0x11111111;
188
- cpu->isar.mvfr1 = 0x00000000;
189
- cpu->ctr = 0x1dd20d2;
190
- cpu->reset_sctlr = 0x00050078;
191
- cpu->id_pfr0 = 0x111;
192
- cpu->id_pfr1 = 0x1;
193
- cpu->isar.id_dfr0 = 0x2;
194
- cpu->id_afr0 = 0x3;
195
- cpu->isar.id_mmfr0 = 0x01130003;
196
- cpu->isar.id_mmfr1 = 0x10030302;
197
- cpu->isar.id_mmfr2 = 0x01222110;
198
- cpu->isar.id_isar0 = 0x00140011;
199
- cpu->isar.id_isar1 = 0x12002111;
200
- cpu->isar.id_isar2 = 0x11231111;
201
- cpu->isar.id_isar3 = 0x01102131;
202
- cpu->isar.id_isar4 = 0x141;
203
- cpu->reset_auxcr = 7;
204
-}
205
-
206
-static void arm1176_initfn(Object *obj)
207
-{
208
- ARMCPU *cpu = ARM_CPU(obj);
209
-
210
- cpu->dtb_compatible = "arm,arm1176";
211
- set_feature(&cpu->env, ARM_FEATURE_V6K);
212
- set_feature(&cpu->env, ARM_FEATURE_VAPA);
213
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
214
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
215
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
216
- set_feature(&cpu->env, ARM_FEATURE_EL3);
217
- cpu->midr = 0x410fb767;
218
- cpu->reset_fpsid = 0x410120b5;
219
- cpu->isar.mvfr0 = 0x11111111;
220
- cpu->isar.mvfr1 = 0x00000000;
221
- cpu->ctr = 0x1dd20d2;
222
- cpu->reset_sctlr = 0x00050078;
223
- cpu->id_pfr0 = 0x111;
224
- cpu->id_pfr1 = 0x11;
225
- cpu->isar.id_dfr0 = 0x33;
226
- cpu->id_afr0 = 0;
227
- cpu->isar.id_mmfr0 = 0x01130003;
228
- cpu->isar.id_mmfr1 = 0x10030302;
229
- cpu->isar.id_mmfr2 = 0x01222100;
230
- cpu->isar.id_isar0 = 0x0140011;
231
- cpu->isar.id_isar1 = 0x12002111;
232
- cpu->isar.id_isar2 = 0x11231121;
233
- cpu->isar.id_isar3 = 0x01102131;
234
- cpu->isar.id_isar4 = 0x01141;
235
- cpu->reset_auxcr = 7;
236
-}
237
-
238
-static void arm11mpcore_initfn(Object *obj)
239
-{
240
- ARMCPU *cpu = ARM_CPU(obj);
241
-
242
- cpu->dtb_compatible = "arm,arm11mpcore";
243
- set_feature(&cpu->env, ARM_FEATURE_V6K);
244
- set_feature(&cpu->env, ARM_FEATURE_VAPA);
245
- set_feature(&cpu->env, ARM_FEATURE_MPIDR);
246
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
247
- cpu->midr = 0x410fb022;
248
- cpu->reset_fpsid = 0x410120b4;
249
- cpu->isar.mvfr0 = 0x11111111;
250
- cpu->isar.mvfr1 = 0x00000000;
251
- cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
252
- cpu->id_pfr0 = 0x111;
253
- cpu->id_pfr1 = 0x1;
254
- cpu->isar.id_dfr0 = 0;
255
- cpu->id_afr0 = 0x2;
256
- cpu->isar.id_mmfr0 = 0x01100103;
257
- cpu->isar.id_mmfr1 = 0x10020302;
258
- cpu->isar.id_mmfr2 = 0x01222000;
259
- cpu->isar.id_isar0 = 0x00100011;
260
- cpu->isar.id_isar1 = 0x12002111;
261
- cpu->isar.id_isar2 = 0x11221011;
262
- cpu->isar.id_isar3 = 0x01102131;
263
- cpu->isar.id_isar4 = 0x141;
264
- cpu->reset_auxcr = 1;
265
-}
266
-
267
-static void cortex_m0_initfn(Object *obj)
268
-{
269
- ARMCPU *cpu = ARM_CPU(obj);
270
- set_feature(&cpu->env, ARM_FEATURE_V6);
271
- set_feature(&cpu->env, ARM_FEATURE_M);
272
-
273
- cpu->midr = 0x410cc200;
274
-}
275
-
276
-static void cortex_m3_initfn(Object *obj)
277
-{
278
- ARMCPU *cpu = ARM_CPU(obj);
279
- set_feature(&cpu->env, ARM_FEATURE_V7);
280
- set_feature(&cpu->env, ARM_FEATURE_M);
281
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
282
- cpu->midr = 0x410fc231;
283
- cpu->pmsav7_dregion = 8;
284
- cpu->id_pfr0 = 0x00000030;
285
- cpu->id_pfr1 = 0x00000200;
286
- cpu->isar.id_dfr0 = 0x00100000;
287
- cpu->id_afr0 = 0x00000000;
288
- cpu->isar.id_mmfr0 = 0x00000030;
289
- cpu->isar.id_mmfr1 = 0x00000000;
290
- cpu->isar.id_mmfr2 = 0x00000000;
291
- cpu->isar.id_mmfr3 = 0x00000000;
292
- cpu->isar.id_isar0 = 0x01141110;
293
- cpu->isar.id_isar1 = 0x02111000;
294
- cpu->isar.id_isar2 = 0x21112231;
295
- cpu->isar.id_isar3 = 0x01111110;
296
- cpu->isar.id_isar4 = 0x01310102;
297
- cpu->isar.id_isar5 = 0x00000000;
298
- cpu->isar.id_isar6 = 0x00000000;
299
-}
300
-
301
-static void cortex_m4_initfn(Object *obj)
302
-{
303
- ARMCPU *cpu = ARM_CPU(obj);
304
-
305
- set_feature(&cpu->env, ARM_FEATURE_V7);
306
- set_feature(&cpu->env, ARM_FEATURE_M);
307
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
308
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
309
- cpu->midr = 0x410fc240; /* r0p0 */
310
- cpu->pmsav7_dregion = 8;
311
- cpu->isar.mvfr0 = 0x10110021;
312
- cpu->isar.mvfr1 = 0x11000011;
313
- cpu->isar.mvfr2 = 0x00000000;
314
- cpu->id_pfr0 = 0x00000030;
315
- cpu->id_pfr1 = 0x00000200;
316
- cpu->isar.id_dfr0 = 0x00100000;
317
- cpu->id_afr0 = 0x00000000;
318
- cpu->isar.id_mmfr0 = 0x00000030;
319
- cpu->isar.id_mmfr1 = 0x00000000;
320
- cpu->isar.id_mmfr2 = 0x00000000;
321
- cpu->isar.id_mmfr3 = 0x00000000;
322
- cpu->isar.id_isar0 = 0x01141110;
323
- cpu->isar.id_isar1 = 0x02111000;
324
- cpu->isar.id_isar2 = 0x21112231;
325
- cpu->isar.id_isar3 = 0x01111110;
326
- cpu->isar.id_isar4 = 0x01310102;
327
- cpu->isar.id_isar5 = 0x00000000;
328
- cpu->isar.id_isar6 = 0x00000000;
329
-}
330
-
331
-static void cortex_m7_initfn(Object *obj)
332
-{
333
- ARMCPU *cpu = ARM_CPU(obj);
334
-
335
- set_feature(&cpu->env, ARM_FEATURE_V7);
336
- set_feature(&cpu->env, ARM_FEATURE_M);
337
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
338
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
339
- cpu->midr = 0x411fc272; /* r1p2 */
340
- cpu->pmsav7_dregion = 8;
341
- cpu->isar.mvfr0 = 0x10110221;
342
- cpu->isar.mvfr1 = 0x12000011;
343
- cpu->isar.mvfr2 = 0x00000040;
344
- cpu->id_pfr0 = 0x00000030;
345
- cpu->id_pfr1 = 0x00000200;
346
- cpu->isar.id_dfr0 = 0x00100000;
347
- cpu->id_afr0 = 0x00000000;
348
- cpu->isar.id_mmfr0 = 0x00100030;
349
- cpu->isar.id_mmfr1 = 0x00000000;
350
- cpu->isar.id_mmfr2 = 0x01000000;
351
- cpu->isar.id_mmfr3 = 0x00000000;
352
- cpu->isar.id_isar0 = 0x01101110;
353
- cpu->isar.id_isar1 = 0x02112000;
354
- cpu->isar.id_isar2 = 0x20232231;
355
- cpu->isar.id_isar3 = 0x01111131;
356
- cpu->isar.id_isar4 = 0x01310132;
357
- cpu->isar.id_isar5 = 0x00000000;
358
- cpu->isar.id_isar6 = 0x00000000;
359
-}
360
-
361
-static void cortex_m33_initfn(Object *obj)
362
-{
363
- ARMCPU *cpu = ARM_CPU(obj);
364
-
365
- set_feature(&cpu->env, ARM_FEATURE_V8);
366
- set_feature(&cpu->env, ARM_FEATURE_M);
367
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
368
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
369
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
370
- cpu->midr = 0x410fd213; /* r0p3 */
371
- cpu->pmsav7_dregion = 16;
372
- cpu->sau_sregion = 8;
373
- cpu->isar.mvfr0 = 0x10110021;
374
- cpu->isar.mvfr1 = 0x11000011;
375
- cpu->isar.mvfr2 = 0x00000040;
376
- cpu->id_pfr0 = 0x00000030;
377
- cpu->id_pfr1 = 0x00000210;
378
- cpu->isar.id_dfr0 = 0x00200000;
379
- cpu->id_afr0 = 0x00000000;
380
- cpu->isar.id_mmfr0 = 0x00101F40;
381
- cpu->isar.id_mmfr1 = 0x00000000;
382
- cpu->isar.id_mmfr2 = 0x01000000;
383
- cpu->isar.id_mmfr3 = 0x00000000;
384
- cpu->isar.id_isar0 = 0x01101110;
385
- cpu->isar.id_isar1 = 0x02212000;
386
- cpu->isar.id_isar2 = 0x20232232;
387
- cpu->isar.id_isar3 = 0x01111131;
388
- cpu->isar.id_isar4 = 0x01310132;
389
- cpu->isar.id_isar5 = 0x00000000;
390
- cpu->isar.id_isar6 = 0x00000000;
391
- cpu->clidr = 0x00000000;
392
- cpu->ctr = 0x8000c000;
393
-}
394
-
395
-static void arm_v7m_class_init(ObjectClass *oc, void *data)
396
-{
397
- ARMCPUClass *acc = ARM_CPU_CLASS(oc);
398
- CPUClass *cc = CPU_CLASS(oc);
399
-
400
- acc->info = data;
401
-#ifndef CONFIG_USER_ONLY
402
- cc->do_interrupt = arm_v7m_cpu_do_interrupt;
403
-#endif
404
-
405
- cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
406
-}
407
-
408
-static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
409
- /* Dummy the TCM region regs for the moment */
410
- { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
411
- .access = PL1_RW, .type = ARM_CP_CONST },
412
- { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
413
- .access = PL1_RW, .type = ARM_CP_CONST },
414
- { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
415
- .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
416
- REGINFO_SENTINEL
417
-};
418
-
419
-static void cortex_r5_initfn(Object *obj)
420
-{
421
- ARMCPU *cpu = ARM_CPU(obj);
422
-
423
- set_feature(&cpu->env, ARM_FEATURE_V7);
424
- set_feature(&cpu->env, ARM_FEATURE_V7MP);
425
- set_feature(&cpu->env, ARM_FEATURE_PMSA);
426
- set_feature(&cpu->env, ARM_FEATURE_PMU);
427
- cpu->midr = 0x411fc153; /* r1p3 */
428
- cpu->id_pfr0 = 0x0131;
429
- cpu->id_pfr1 = 0x001;
430
- cpu->isar.id_dfr0 = 0x010400;
431
- cpu->id_afr0 = 0x0;
432
- cpu->isar.id_mmfr0 = 0x0210030;
433
- cpu->isar.id_mmfr1 = 0x00000000;
434
- cpu->isar.id_mmfr2 = 0x01200000;
435
- cpu->isar.id_mmfr3 = 0x0211;
436
- cpu->isar.id_isar0 = 0x02101111;
437
- cpu->isar.id_isar1 = 0x13112111;
438
- cpu->isar.id_isar2 = 0x21232141;
439
- cpu->isar.id_isar3 = 0x01112131;
440
- cpu->isar.id_isar4 = 0x0010142;
441
- cpu->isar.id_isar5 = 0x0;
442
- cpu->isar.id_isar6 = 0x0;
443
- cpu->mp_is_up = true;
444
- cpu->pmsav7_dregion = 16;
445
- define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
446
-}
447
-
448
-static void cortex_r5f_initfn(Object *obj)
449
-{
450
- ARMCPU *cpu = ARM_CPU(obj);
451
-
452
- cortex_r5_initfn(obj);
453
- cpu->isar.mvfr0 = 0x10110221;
454
- cpu->isar.mvfr1 = 0x00000011;
455
-}
456
-
457
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
458
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
459
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
460
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
461
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
462
}
463
464
-static void ti925t_initfn(Object *obj)
465
-{
466
- ARMCPU *cpu = ARM_CPU(obj);
467
- set_feature(&cpu->env, ARM_FEATURE_V4T);
468
- set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
469
- cpu->midr = ARM_CPUID_TI925T;
470
- cpu->ctr = 0x5109149;
471
- cpu->reset_sctlr = 0x00000070;
472
-}
473
-
474
-static void sa1100_initfn(Object *obj)
475
-{
476
- ARMCPU *cpu = ARM_CPU(obj);
477
-
478
- cpu->dtb_compatible = "intel,sa1100";
479
- set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
480
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
481
- cpu->midr = 0x4401A11B;
482
- cpu->reset_sctlr = 0x00000070;
483
-}
484
-
485
-static void sa1110_initfn(Object *obj)
486
-{
487
- ARMCPU *cpu = ARM_CPU(obj);
488
- set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
489
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
490
- cpu->midr = 0x6901B119;
491
- cpu->reset_sctlr = 0x00000070;
492
-}
493
-
494
-static void pxa250_initfn(Object *obj)
495
-{
496
- ARMCPU *cpu = ARM_CPU(obj);
497
-
498
- cpu->dtb_compatible = "marvell,xscale";
499
- set_feature(&cpu->env, ARM_FEATURE_V5);
500
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
501
- cpu->midr = 0x69052100;
502
- cpu->ctr = 0xd172172;
503
- cpu->reset_sctlr = 0x00000078;
504
-}
505
-
506
-static void pxa255_initfn(Object *obj)
507
-{
508
- ARMCPU *cpu = ARM_CPU(obj);
509
-
510
- cpu->dtb_compatible = "marvell,xscale";
511
- set_feature(&cpu->env, ARM_FEATURE_V5);
512
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
513
- cpu->midr = 0x69052d00;
514
- cpu->ctr = 0xd172172;
515
- cpu->reset_sctlr = 0x00000078;
516
-}
517
-
518
-static void pxa260_initfn(Object *obj)
519
-{
520
- ARMCPU *cpu = ARM_CPU(obj);
521
-
522
- cpu->dtb_compatible = "marvell,xscale";
523
- set_feature(&cpu->env, ARM_FEATURE_V5);
524
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
525
- cpu->midr = 0x69052903;
526
- cpu->ctr = 0xd172172;
527
- cpu->reset_sctlr = 0x00000078;
528
-}
529
-
530
-static void pxa261_initfn(Object *obj)
531
-{
532
- ARMCPU *cpu = ARM_CPU(obj);
533
-
534
- cpu->dtb_compatible = "marvell,xscale";
535
- set_feature(&cpu->env, ARM_FEATURE_V5);
536
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
537
- cpu->midr = 0x69052d05;
538
- cpu->ctr = 0xd172172;
539
- cpu->reset_sctlr = 0x00000078;
540
-}
541
-
542
-static void pxa262_initfn(Object *obj)
543
-{
544
- ARMCPU *cpu = ARM_CPU(obj);
545
-
546
- cpu->dtb_compatible = "marvell,xscale";
547
- set_feature(&cpu->env, ARM_FEATURE_V5);
548
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
549
- cpu->midr = 0x69052d06;
550
- cpu->ctr = 0xd172172;
551
- cpu->reset_sctlr = 0x00000078;
552
-}
553
-
554
-static void pxa270a0_initfn(Object *obj)
555
-{
556
- ARMCPU *cpu = ARM_CPU(obj);
557
-
558
- cpu->dtb_compatible = "marvell,xscale";
559
- set_feature(&cpu->env, ARM_FEATURE_V5);
560
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
561
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
562
- cpu->midr = 0x69054110;
563
- cpu->ctr = 0xd172172;
564
- cpu->reset_sctlr = 0x00000078;
565
-}
566
-
567
-static void pxa270a1_initfn(Object *obj)
568
-{
569
- ARMCPU *cpu = ARM_CPU(obj);
570
-
571
- cpu->dtb_compatible = "marvell,xscale";
572
- set_feature(&cpu->env, ARM_FEATURE_V5);
573
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
574
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
575
- cpu->midr = 0x69054111;
576
- cpu->ctr = 0xd172172;
577
- cpu->reset_sctlr = 0x00000078;
578
-}
579
-
580
-static void pxa270b0_initfn(Object *obj)
581
-{
582
- ARMCPU *cpu = ARM_CPU(obj);
583
-
584
- cpu->dtb_compatible = "marvell,xscale";
585
- set_feature(&cpu->env, ARM_FEATURE_V5);
586
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
587
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
588
- cpu->midr = 0x69054112;
589
- cpu->ctr = 0xd172172;
590
- cpu->reset_sctlr = 0x00000078;
591
-}
592
-
593
-static void pxa270b1_initfn(Object *obj)
594
-{
595
- ARMCPU *cpu = ARM_CPU(obj);
596
-
597
- cpu->dtb_compatible = "marvell,xscale";
598
- set_feature(&cpu->env, ARM_FEATURE_V5);
599
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
600
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
601
- cpu->midr = 0x69054113;
602
- cpu->ctr = 0xd172172;
603
- cpu->reset_sctlr = 0x00000078;
604
-}
605
-
606
-static void pxa270c0_initfn(Object *obj)
607
-{
608
- ARMCPU *cpu = ARM_CPU(obj);
609
-
610
- cpu->dtb_compatible = "marvell,xscale";
611
- set_feature(&cpu->env, ARM_FEATURE_V5);
612
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
613
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
614
- cpu->midr = 0x69054114;
615
- cpu->ctr = 0xd172172;
616
- cpu->reset_sctlr = 0x00000078;
617
-}
618
-
619
-static void pxa270c5_initfn(Object *obj)
620
-{
621
- ARMCPU *cpu = ARM_CPU(obj);
622
-
623
- cpu->dtb_compatible = "marvell,xscale";
624
- set_feature(&cpu->env, ARM_FEATURE_V5);
625
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
626
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
627
- cpu->midr = 0x69054117;
628
- cpu->ctr = 0xd172172;
629
- cpu->reset_sctlr = 0x00000078;
630
-}
631
-
632
#ifndef TARGET_AARCH64
633
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
634
* otherwise, a CPU with as many features enabled as our emulation supports.
635
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
636
637
static const ARMCPUInfo arm_cpus[] = {
638
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
639
- { .name = "arm926", .initfn = arm926_initfn },
640
- { .name = "arm946", .initfn = arm946_initfn },
641
- { .name = "arm1026", .initfn = arm1026_initfn },
642
- /*
643
- * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
644
- * older core than plain "arm1136". In particular this does not
645
- * have the v6K features.
646
- */
647
- { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
648
- { .name = "arm1136", .initfn = arm1136_initfn },
649
- { .name = "arm1176", .initfn = arm1176_initfn },
650
- { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
651
- { .name = "cortex-m0", .initfn = cortex_m0_initfn,
652
- .class_init = arm_v7m_class_init },
653
- { .name = "cortex-m3", .initfn = cortex_m3_initfn,
654
- .class_init = arm_v7m_class_init },
655
- { .name = "cortex-m4", .initfn = cortex_m4_initfn,
656
- .class_init = arm_v7m_class_init },
657
- { .name = "cortex-m7", .initfn = cortex_m7_initfn,
658
- .class_init = arm_v7m_class_init },
659
- { .name = "cortex-m33", .initfn = cortex_m33_initfn,
660
- .class_init = arm_v7m_class_init },
661
- { .name = "cortex-r5", .initfn = cortex_r5_initfn },
662
- { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
663
{ .name = "cortex-a7", .initfn = cortex_a7_initfn },
664
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
665
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
666
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
667
- { .name = "ti925t", .initfn = ti925t_initfn },
668
- { .name = "sa1100", .initfn = sa1100_initfn },
669
- { .name = "sa1110", .initfn = sa1110_initfn },
670
- { .name = "pxa250", .initfn = pxa250_initfn },
671
- { .name = "pxa255", .initfn = pxa255_initfn },
672
- { .name = "pxa260", .initfn = pxa260_initfn },
673
- { .name = "pxa261", .initfn = pxa261_initfn },
674
- { .name = "pxa262", .initfn = pxa262_initfn },
675
- /* "pxa270" is an alias for "pxa270-a0" */
676
- { .name = "pxa270", .initfn = pxa270a0_initfn },
677
- { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
678
- { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
679
- { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
680
- { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
681
- { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
682
- { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
683
#ifndef TARGET_AARCH64
684
{ .name = "max", .initfn = arm_max_initfn },
685
#endif
686
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
687
new file mode 100644
688
index XXXXXXX..XXXXXXX
689
--- /dev/null
690
+++ b/target/arm/cpu_tcg.c
691
@@ -XXX,XX +XXX,XX @@
692
+/*
693
+ * QEMU ARM TCG CPUs.
694
+ *
695
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
696
+ *
697
+ * This code is licensed under the GNU GPL v2 or later.
698
+ *
699
+ * SPDX-License-Identifier: GPL-2.0-or-later
700
+ */
701
+
702
+#include "qemu/osdep.h"
703
+#include "cpu.h"
704
+#include "internals.h"
705
+
706
+/* CPU models. These are not needed for the AArch64 linux-user build. */
707
+#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
708
+
709
+static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
710
+{
711
+ CPUClass *cc = CPU_GET_CLASS(cs);
712
+ ARMCPU *cpu = ARM_CPU(cs);
713
+ CPUARMState *env = &cpu->env;
714
+ bool ret = false;
715
+
716
+ /*
717
+ * ARMv7-M interrupt masking works differently than -A or -R.
718
+ * There is no FIQ/IRQ distinction. Instead of I and F bits
719
+ * masking FIQ and IRQ interrupts, an exception is taken only
720
+ * if it is higher priority than the current execution priority
721
+ * (which depends on state like BASEPRI, FAULTMASK and the
722
+ * currently active exception).
723
+ */
724
+ if (interrupt_request & CPU_INTERRUPT_HARD
725
+ && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
726
+ cs->exception_index = EXCP_IRQ;
727
+ cc->do_interrupt(cs);
728
+ ret = true;
729
+ }
730
+ return ret;
731
+}
732
+
733
+static void arm926_initfn(Object *obj)
734
+{
735
+ ARMCPU *cpu = ARM_CPU(obj);
736
+
737
+ cpu->dtb_compatible = "arm,arm926";
738
+ set_feature(&cpu->env, ARM_FEATURE_V5);
739
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
740
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
741
+ cpu->midr = 0x41069265;
742
+ cpu->reset_fpsid = 0x41011090;
743
+ cpu->ctr = 0x1dd20d2;
744
+ cpu->reset_sctlr = 0x00090078;
745
+
746
+ /*
747
+ * ARMv5 does not have the ID_ISAR registers, but we can still
748
+ * set the field to indicate Jazelle support within QEMU.
749
+ */
750
+ cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
751
+ /*
752
+ * Similarly, we need to set MVFR0 fields to enable vfp and short vector
753
+ * support even though ARMv5 doesn't have this register.
754
+ */
755
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
756
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
757
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
758
+}
759
+
760
+static void arm946_initfn(Object *obj)
761
+{
762
+ ARMCPU *cpu = ARM_CPU(obj);
763
+
764
+ cpu->dtb_compatible = "arm,arm946";
765
+ set_feature(&cpu->env, ARM_FEATURE_V5);
766
+ set_feature(&cpu->env, ARM_FEATURE_PMSA);
767
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
768
+ cpu->midr = 0x41059461;
769
+ cpu->ctr = 0x0f004006;
770
+ cpu->reset_sctlr = 0x00000078;
771
+}
772
+
773
+static void arm1026_initfn(Object *obj)
774
+{
775
+ ARMCPU *cpu = ARM_CPU(obj);
776
+
777
+ cpu->dtb_compatible = "arm,arm1026";
778
+ set_feature(&cpu->env, ARM_FEATURE_V5);
779
+ set_feature(&cpu->env, ARM_FEATURE_AUXCR);
780
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
781
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
782
+ cpu->midr = 0x4106a262;
783
+ cpu->reset_fpsid = 0x410110a0;
784
+ cpu->ctr = 0x1dd20d2;
785
+ cpu->reset_sctlr = 0x00090078;
786
+ cpu->reset_auxcr = 1;
787
+
788
+ /*
789
+ * ARMv5 does not have the ID_ISAR registers, but we can still
790
+ * set the field to indicate Jazelle support within QEMU.
791
+ */
792
+ cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
793
+ /*
794
+ * Similarly, we need to set MVFR0 fields to enable vfp and short vector
795
+ * support even though ARMv5 doesn't have this register.
796
+ */
797
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
798
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
799
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
800
+
801
+ {
802
+ /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
803
+ ARMCPRegInfo ifar = {
804
+ .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
805
+ .access = PL1_RW,
806
+ .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
807
+ .resetvalue = 0
808
+ };
809
+ define_one_arm_cp_reg(cpu, &ifar);
810
+ }
811
+}
812
+
813
+static void arm1136_r2_initfn(Object *obj)
814
+{
815
+ ARMCPU *cpu = ARM_CPU(obj);
816
+ /*
817
+ * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
818
+ * older core than plain "arm1136". In particular this does not
819
+ * have the v6K features.
820
+ * These ID register values are correct for 1136 but may be wrong
821
+ * for 1136_r2 (in particular r0p2 does not actually implement most
822
+ * of the ID registers).
823
+ */
824
+
825
+ cpu->dtb_compatible = "arm,arm1136";
826
+ set_feature(&cpu->env, ARM_FEATURE_V6);
827
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
828
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
829
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
830
+ cpu->midr = 0x4107b362;
831
+ cpu->reset_fpsid = 0x410120b4;
832
+ cpu->isar.mvfr0 = 0x11111111;
833
+ cpu->isar.mvfr1 = 0x00000000;
834
+ cpu->ctr = 0x1dd20d2;
835
+ cpu->reset_sctlr = 0x00050078;
836
+ cpu->id_pfr0 = 0x111;
837
+ cpu->id_pfr1 = 0x1;
838
+ cpu->isar.id_dfr0 = 0x2;
839
+ cpu->id_afr0 = 0x3;
840
+ cpu->isar.id_mmfr0 = 0x01130003;
841
+ cpu->isar.id_mmfr1 = 0x10030302;
842
+ cpu->isar.id_mmfr2 = 0x01222110;
843
+ cpu->isar.id_isar0 = 0x00140011;
844
+ cpu->isar.id_isar1 = 0x12002111;
845
+ cpu->isar.id_isar2 = 0x11231111;
846
+ cpu->isar.id_isar3 = 0x01102131;
847
+ cpu->isar.id_isar4 = 0x141;
848
+ cpu->reset_auxcr = 7;
849
+}
850
+
851
+static void arm1136_initfn(Object *obj)
852
+{
853
+ ARMCPU *cpu = ARM_CPU(obj);
854
+
855
+ cpu->dtb_compatible = "arm,arm1136";
856
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
857
+ set_feature(&cpu->env, ARM_FEATURE_V6);
858
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
859
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
860
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
861
+ cpu->midr = 0x4117b363;
862
+ cpu->reset_fpsid = 0x410120b4;
863
+ cpu->isar.mvfr0 = 0x11111111;
864
+ cpu->isar.mvfr1 = 0x00000000;
865
+ cpu->ctr = 0x1dd20d2;
866
+ cpu->reset_sctlr = 0x00050078;
867
+ cpu->id_pfr0 = 0x111;
868
+ cpu->id_pfr1 = 0x1;
869
+ cpu->isar.id_dfr0 = 0x2;
870
+ cpu->id_afr0 = 0x3;
871
+ cpu->isar.id_mmfr0 = 0x01130003;
872
+ cpu->isar.id_mmfr1 = 0x10030302;
873
+ cpu->isar.id_mmfr2 = 0x01222110;
874
+ cpu->isar.id_isar0 = 0x00140011;
875
+ cpu->isar.id_isar1 = 0x12002111;
876
+ cpu->isar.id_isar2 = 0x11231111;
877
+ cpu->isar.id_isar3 = 0x01102131;
878
+ cpu->isar.id_isar4 = 0x141;
879
+ cpu->reset_auxcr = 7;
880
+}
881
+
882
+static void arm1176_initfn(Object *obj)
883
+{
884
+ ARMCPU *cpu = ARM_CPU(obj);
885
+
886
+ cpu->dtb_compatible = "arm,arm1176";
887
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
888
+ set_feature(&cpu->env, ARM_FEATURE_VAPA);
889
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
890
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
891
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
892
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
893
+ cpu->midr = 0x410fb767;
894
+ cpu->reset_fpsid = 0x410120b5;
895
+ cpu->isar.mvfr0 = 0x11111111;
896
+ cpu->isar.mvfr1 = 0x00000000;
897
+ cpu->ctr = 0x1dd20d2;
898
+ cpu->reset_sctlr = 0x00050078;
899
+ cpu->id_pfr0 = 0x111;
900
+ cpu->id_pfr1 = 0x11;
901
+ cpu->isar.id_dfr0 = 0x33;
902
+ cpu->id_afr0 = 0;
903
+ cpu->isar.id_mmfr0 = 0x01130003;
904
+ cpu->isar.id_mmfr1 = 0x10030302;
905
+ cpu->isar.id_mmfr2 = 0x01222100;
906
+ cpu->isar.id_isar0 = 0x0140011;
907
+ cpu->isar.id_isar1 = 0x12002111;
908
+ cpu->isar.id_isar2 = 0x11231121;
909
+ cpu->isar.id_isar3 = 0x01102131;
910
+ cpu->isar.id_isar4 = 0x01141;
911
+ cpu->reset_auxcr = 7;
912
+}
913
+
914
+static void arm11mpcore_initfn(Object *obj)
915
+{
916
+ ARMCPU *cpu = ARM_CPU(obj);
917
+
918
+ cpu->dtb_compatible = "arm,arm11mpcore";
919
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
920
+ set_feature(&cpu->env, ARM_FEATURE_VAPA);
921
+ set_feature(&cpu->env, ARM_FEATURE_MPIDR);
922
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
923
+ cpu->midr = 0x410fb022;
924
+ cpu->reset_fpsid = 0x410120b4;
925
+ cpu->isar.mvfr0 = 0x11111111;
926
+ cpu->isar.mvfr1 = 0x00000000;
927
+ cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
928
+ cpu->id_pfr0 = 0x111;
929
+ cpu->id_pfr1 = 0x1;
930
+ cpu->isar.id_dfr0 = 0;
931
+ cpu->id_afr0 = 0x2;
932
+ cpu->isar.id_mmfr0 = 0x01100103;
933
+ cpu->isar.id_mmfr1 = 0x10020302;
934
+ cpu->isar.id_mmfr2 = 0x01222000;
935
+ cpu->isar.id_isar0 = 0x00100011;
936
+ cpu->isar.id_isar1 = 0x12002111;
937
+ cpu->isar.id_isar2 = 0x11221011;
938
+ cpu->isar.id_isar3 = 0x01102131;
939
+ cpu->isar.id_isar4 = 0x141;
940
+ cpu->reset_auxcr = 1;
941
+}
942
+
943
+static void cortex_m0_initfn(Object *obj)
944
+{
945
+ ARMCPU *cpu = ARM_CPU(obj);
946
+ set_feature(&cpu->env, ARM_FEATURE_V6);
947
+ set_feature(&cpu->env, ARM_FEATURE_M);
948
+
949
+ cpu->midr = 0x410cc200;
950
+}
951
+
952
+static void cortex_m3_initfn(Object *obj)
953
+{
954
+ ARMCPU *cpu = ARM_CPU(obj);
955
+ set_feature(&cpu->env, ARM_FEATURE_V7);
956
+ set_feature(&cpu->env, ARM_FEATURE_M);
957
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
958
+ cpu->midr = 0x410fc231;
959
+ cpu->pmsav7_dregion = 8;
960
+ cpu->id_pfr0 = 0x00000030;
961
+ cpu->id_pfr1 = 0x00000200;
962
+ cpu->isar.id_dfr0 = 0x00100000;
963
+ cpu->id_afr0 = 0x00000000;
964
+ cpu->isar.id_mmfr0 = 0x00000030;
965
+ cpu->isar.id_mmfr1 = 0x00000000;
966
+ cpu->isar.id_mmfr2 = 0x00000000;
967
+ cpu->isar.id_mmfr3 = 0x00000000;
968
+ cpu->isar.id_isar0 = 0x01141110;
969
+ cpu->isar.id_isar1 = 0x02111000;
970
+ cpu->isar.id_isar2 = 0x21112231;
971
+ cpu->isar.id_isar3 = 0x01111110;
972
+ cpu->isar.id_isar4 = 0x01310102;
973
+ cpu->isar.id_isar5 = 0x00000000;
974
+ cpu->isar.id_isar6 = 0x00000000;
975
+}
976
+
977
+static void cortex_m4_initfn(Object *obj)
978
+{
979
+ ARMCPU *cpu = ARM_CPU(obj);
980
+
981
+ set_feature(&cpu->env, ARM_FEATURE_V7);
982
+ set_feature(&cpu->env, ARM_FEATURE_M);
983
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
984
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
985
+ cpu->midr = 0x410fc240; /* r0p0 */
986
+ cpu->pmsav7_dregion = 8;
987
+ cpu->isar.mvfr0 = 0x10110021;
988
+ cpu->isar.mvfr1 = 0x11000011;
989
+ cpu->isar.mvfr2 = 0x00000000;
990
+ cpu->id_pfr0 = 0x00000030;
991
+ cpu->id_pfr1 = 0x00000200;
992
+ cpu->isar.id_dfr0 = 0x00100000;
993
+ cpu->id_afr0 = 0x00000000;
994
+ cpu->isar.id_mmfr0 = 0x00000030;
995
+ cpu->isar.id_mmfr1 = 0x00000000;
996
+ cpu->isar.id_mmfr2 = 0x00000000;
997
+ cpu->isar.id_mmfr3 = 0x00000000;
998
+ cpu->isar.id_isar0 = 0x01141110;
999
+ cpu->isar.id_isar1 = 0x02111000;
1000
+ cpu->isar.id_isar2 = 0x21112231;
1001
+ cpu->isar.id_isar3 = 0x01111110;
1002
+ cpu->isar.id_isar4 = 0x01310102;
1003
+ cpu->isar.id_isar5 = 0x00000000;
1004
+ cpu->isar.id_isar6 = 0x00000000;
1005
+}
1006
+
1007
+static void cortex_m7_initfn(Object *obj)
1008
+{
1009
+ ARMCPU *cpu = ARM_CPU(obj);
1010
+
1011
+ set_feature(&cpu->env, ARM_FEATURE_V7);
1012
+ set_feature(&cpu->env, ARM_FEATURE_M);
1013
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1014
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1015
+ cpu->midr = 0x411fc272; /* r1p2 */
1016
+ cpu->pmsav7_dregion = 8;
1017
+ cpu->isar.mvfr0 = 0x10110221;
1018
+ cpu->isar.mvfr1 = 0x12000011;
1019
+ cpu->isar.mvfr2 = 0x00000040;
1020
+ cpu->id_pfr0 = 0x00000030;
1021
+ cpu->id_pfr1 = 0x00000200;
1022
+ cpu->isar.id_dfr0 = 0x00100000;
1023
+ cpu->id_afr0 = 0x00000000;
1024
+ cpu->isar.id_mmfr0 = 0x00100030;
1025
+ cpu->isar.id_mmfr1 = 0x00000000;
1026
+ cpu->isar.id_mmfr2 = 0x01000000;
1027
+ cpu->isar.id_mmfr3 = 0x00000000;
1028
+ cpu->isar.id_isar0 = 0x01101110;
1029
+ cpu->isar.id_isar1 = 0x02112000;
1030
+ cpu->isar.id_isar2 = 0x20232231;
1031
+ cpu->isar.id_isar3 = 0x01111131;
1032
+ cpu->isar.id_isar4 = 0x01310132;
1033
+ cpu->isar.id_isar5 = 0x00000000;
1034
+ cpu->isar.id_isar6 = 0x00000000;
1035
+}
1036
+
1037
+static void cortex_m33_initfn(Object *obj)
1038
+{
1039
+ ARMCPU *cpu = ARM_CPU(obj);
1040
+
1041
+ set_feature(&cpu->env, ARM_FEATURE_V8);
1042
+ set_feature(&cpu->env, ARM_FEATURE_M);
1043
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1044
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
1045
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1046
+ cpu->midr = 0x410fd213; /* r0p3 */
1047
+ cpu->pmsav7_dregion = 16;
1048
+ cpu->sau_sregion = 8;
1049
+ cpu->isar.mvfr0 = 0x10110021;
1050
+ cpu->isar.mvfr1 = 0x11000011;
1051
+ cpu->isar.mvfr2 = 0x00000040;
1052
+ cpu->id_pfr0 = 0x00000030;
1053
+ cpu->id_pfr1 = 0x00000210;
1054
+ cpu->isar.id_dfr0 = 0x00200000;
1055
+ cpu->id_afr0 = 0x00000000;
1056
+ cpu->isar.id_mmfr0 = 0x00101F40;
1057
+ cpu->isar.id_mmfr1 = 0x00000000;
1058
+ cpu->isar.id_mmfr2 = 0x01000000;
1059
+ cpu->isar.id_mmfr3 = 0x00000000;
1060
+ cpu->isar.id_isar0 = 0x01101110;
1061
+ cpu->isar.id_isar1 = 0x02212000;
1062
+ cpu->isar.id_isar2 = 0x20232232;
1063
+ cpu->isar.id_isar3 = 0x01111131;
1064
+ cpu->isar.id_isar4 = 0x01310132;
1065
+ cpu->isar.id_isar5 = 0x00000000;
1066
+ cpu->isar.id_isar6 = 0x00000000;
1067
+ cpu->clidr = 0x00000000;
1068
+ cpu->ctr = 0x8000c000;
1069
+}
1070
+
1071
+static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
1072
+ /* Dummy the TCM region regs for the moment */
1073
+ { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1074
+ .access = PL1_RW, .type = ARM_CP_CONST },
1075
+ { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1076
+ .access = PL1_RW, .type = ARM_CP_CONST },
1077
+ { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
1078
+ .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
1079
+ REGINFO_SENTINEL
1080
+};
1081
+
1082
+static void cortex_r5_initfn(Object *obj)
1083
+{
1084
+ ARMCPU *cpu = ARM_CPU(obj);
1085
+
1086
+ set_feature(&cpu->env, ARM_FEATURE_V7);
1087
+ set_feature(&cpu->env, ARM_FEATURE_V7MP);
1088
+ set_feature(&cpu->env, ARM_FEATURE_PMSA);
1089
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
1090
+ cpu->midr = 0x411fc153; /* r1p3 */
1091
+ cpu->id_pfr0 = 0x0131;
1092
+ cpu->id_pfr1 = 0x001;
1093
+ cpu->isar.id_dfr0 = 0x010400;
1094
+ cpu->id_afr0 = 0x0;
1095
+ cpu->isar.id_mmfr0 = 0x0210030;
1096
+ cpu->isar.id_mmfr1 = 0x00000000;
1097
+ cpu->isar.id_mmfr2 = 0x01200000;
1098
+ cpu->isar.id_mmfr3 = 0x0211;
1099
+ cpu->isar.id_isar0 = 0x02101111;
1100
+ cpu->isar.id_isar1 = 0x13112111;
1101
+ cpu->isar.id_isar2 = 0x21232141;
1102
+ cpu->isar.id_isar3 = 0x01112131;
1103
+ cpu->isar.id_isar4 = 0x0010142;
1104
+ cpu->isar.id_isar5 = 0x0;
1105
+ cpu->isar.id_isar6 = 0x0;
1106
+ cpu->mp_is_up = true;
1107
+ cpu->pmsav7_dregion = 16;
1108
+ define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
1109
+}
1110
+
1111
+static void cortex_r5f_initfn(Object *obj)
1112
+{
1113
+ ARMCPU *cpu = ARM_CPU(obj);
1114
+
1115
+ cortex_r5_initfn(obj);
1116
+ cpu->isar.mvfr0 = 0x10110221;
1117
+ cpu->isar.mvfr1 = 0x00000011;
1118
+}
1119
+
1120
+static void ti925t_initfn(Object *obj)
1121
+{
1122
+ ARMCPU *cpu = ARM_CPU(obj);
1123
+ set_feature(&cpu->env, ARM_FEATURE_V4T);
1124
+ set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1125
+ cpu->midr = ARM_CPUID_TI925T;
1126
+ cpu->ctr = 0x5109149;
1127
+ cpu->reset_sctlr = 0x00000070;
1128
+}
1129
+
1130
+static void sa1100_initfn(Object *obj)
1131
+{
1132
+ ARMCPU *cpu = ARM_CPU(obj);
1133
+
1134
+ cpu->dtb_compatible = "intel,sa1100";
1135
+ set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1136
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1137
+ cpu->midr = 0x4401A11B;
1138
+ cpu->reset_sctlr = 0x00000070;
1139
+}
1140
+
1141
+static void sa1110_initfn(Object *obj)
1142
+{
1143
+ ARMCPU *cpu = ARM_CPU(obj);
1144
+ set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1145
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1146
+ cpu->midr = 0x6901B119;
1147
+ cpu->reset_sctlr = 0x00000070;
1148
+}
1149
+
1150
+static void pxa250_initfn(Object *obj)
1151
+{
1152
+ ARMCPU *cpu = ARM_CPU(obj);
1153
+
1154
+ cpu->dtb_compatible = "marvell,xscale";
1155
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1156
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1157
+ cpu->midr = 0x69052100;
1158
+ cpu->ctr = 0xd172172;
1159
+ cpu->reset_sctlr = 0x00000078;
1160
+}
1161
+
1162
+static void pxa255_initfn(Object *obj)
1163
+{
1164
+ ARMCPU *cpu = ARM_CPU(obj);
1165
+
1166
+ cpu->dtb_compatible = "marvell,xscale";
1167
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1168
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1169
+ cpu->midr = 0x69052d00;
1170
+ cpu->ctr = 0xd172172;
1171
+ cpu->reset_sctlr = 0x00000078;
1172
+}
1173
+
1174
+static void pxa260_initfn(Object *obj)
1175
+{
1176
+ ARMCPU *cpu = ARM_CPU(obj);
1177
+
1178
+ cpu->dtb_compatible = "marvell,xscale";
1179
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1180
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1181
+ cpu->midr = 0x69052903;
1182
+ cpu->ctr = 0xd172172;
1183
+ cpu->reset_sctlr = 0x00000078;
1184
+}
1185
+
1186
+static void pxa261_initfn(Object *obj)
1187
+{
1188
+ ARMCPU *cpu = ARM_CPU(obj);
1189
+
1190
+ cpu->dtb_compatible = "marvell,xscale";
1191
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1192
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1193
+ cpu->midr = 0x69052d05;
1194
+ cpu->ctr = 0xd172172;
1195
+ cpu->reset_sctlr = 0x00000078;
1196
+}
1197
+
1198
+static void pxa262_initfn(Object *obj)
1199
+{
1200
+ ARMCPU *cpu = ARM_CPU(obj);
1201
+
1202
+ cpu->dtb_compatible = "marvell,xscale";
1203
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1204
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1205
+ cpu->midr = 0x69052d06;
1206
+ cpu->ctr = 0xd172172;
1207
+ cpu->reset_sctlr = 0x00000078;
1208
+}
1209
+
1210
+static void pxa270a0_initfn(Object *obj)
1211
+{
1212
+ ARMCPU *cpu = ARM_CPU(obj);
1213
+
1214
+ cpu->dtb_compatible = "marvell,xscale";
1215
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1216
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1217
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1218
+ cpu->midr = 0x69054110;
1219
+ cpu->ctr = 0xd172172;
1220
+ cpu->reset_sctlr = 0x00000078;
1221
+}
1222
+
1223
+static void pxa270a1_initfn(Object *obj)
1224
+{
1225
+ ARMCPU *cpu = ARM_CPU(obj);
1226
+
1227
+ cpu->dtb_compatible = "marvell,xscale";
1228
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1229
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1230
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1231
+ cpu->midr = 0x69054111;
1232
+ cpu->ctr = 0xd172172;
1233
+ cpu->reset_sctlr = 0x00000078;
1234
+}
1235
+
1236
+static void pxa270b0_initfn(Object *obj)
1237
+{
1238
+ ARMCPU *cpu = ARM_CPU(obj);
1239
+
1240
+ cpu->dtb_compatible = "marvell,xscale";
1241
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1242
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1243
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1244
+ cpu->midr = 0x69054112;
1245
+ cpu->ctr = 0xd172172;
1246
+ cpu->reset_sctlr = 0x00000078;
1247
+}
1248
+
1249
+static void pxa270b1_initfn(Object *obj)
1250
+{
1251
+ ARMCPU *cpu = ARM_CPU(obj);
1252
+
1253
+ cpu->dtb_compatible = "marvell,xscale";
1254
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1255
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1256
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1257
+ cpu->midr = 0x69054113;
1258
+ cpu->ctr = 0xd172172;
1259
+ cpu->reset_sctlr = 0x00000078;
1260
+}
1261
+
1262
+static void pxa270c0_initfn(Object *obj)
1263
+{
1264
+ ARMCPU *cpu = ARM_CPU(obj);
1265
+
1266
+ cpu->dtb_compatible = "marvell,xscale";
1267
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1268
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1269
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1270
+ cpu->midr = 0x69054114;
1271
+ cpu->ctr = 0xd172172;
1272
+ cpu->reset_sctlr = 0x00000078;
1273
+}
1274
+
1275
+static void pxa270c5_initfn(Object *obj)
1276
+{
1277
+ ARMCPU *cpu = ARM_CPU(obj);
1278
+
1279
+ cpu->dtb_compatible = "marvell,xscale";
1280
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1281
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1282
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1283
+ cpu->midr = 0x69054117;
1284
+ cpu->ctr = 0xd172172;
1285
+ cpu->reset_sctlr = 0x00000078;
1286
+}
1287
+
1288
+static void arm_v7m_class_init(ObjectClass *oc, void *data)
1289
+{
1290
+ ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1291
+ CPUClass *cc = CPU_CLASS(oc);
1292
+
1293
+ acc->info = data;
1294
+#ifndef CONFIG_USER_ONLY
1295
+ cc->do_interrupt = arm_v7m_cpu_do_interrupt;
1296
+#endif
1297
+
1298
+ cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
1299
+}
1300
+
1301
+static const ARMCPUInfo arm_tcg_cpus[] = {
1302
+ { .name = "arm926", .initfn = arm926_initfn },
1303
+ { .name = "arm946", .initfn = arm946_initfn },
1304
+ { .name = "arm1026", .initfn = arm1026_initfn },
1305
+ /*
1306
+ * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1307
+ * older core than plain "arm1136". In particular this does not
1308
+ * have the v6K features.
1309
+ */
1310
+ { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1311
+ { .name = "arm1136", .initfn = arm1136_initfn },
1312
+ { .name = "arm1176", .initfn = arm1176_initfn },
1313
+ { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1314
+ { .name = "cortex-m0", .initfn = cortex_m0_initfn,
1315
+ .class_init = arm_v7m_class_init },
1316
+ { .name = "cortex-m3", .initfn = cortex_m3_initfn,
1317
+ .class_init = arm_v7m_class_init },
1318
+ { .name = "cortex-m4", .initfn = cortex_m4_initfn,
1319
+ .class_init = arm_v7m_class_init },
1320
+ { .name = "cortex-m7", .initfn = cortex_m7_initfn,
1321
+ .class_init = arm_v7m_class_init },
1322
+ { .name = "cortex-m33", .initfn = cortex_m33_initfn,
1323
+ .class_init = arm_v7m_class_init },
1324
+ { .name = "cortex-r5", .initfn = cortex_r5_initfn },
1325
+ { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
1326
+ { .name = "ti925t", .initfn = ti925t_initfn },
1327
+ { .name = "sa1100", .initfn = sa1100_initfn },
1328
+ { .name = "sa1110", .initfn = sa1110_initfn },
1329
+ { .name = "pxa250", .initfn = pxa250_initfn },
1330
+ { .name = "pxa255", .initfn = pxa255_initfn },
1331
+ { .name = "pxa260", .initfn = pxa260_initfn },
1332
+ { .name = "pxa261", .initfn = pxa261_initfn },
1333
+ { .name = "pxa262", .initfn = pxa262_initfn },
1334
+ /* "pxa270" is an alias for "pxa270-a0" */
1335
+ { .name = "pxa270", .initfn = pxa270a0_initfn },
1336
+ { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1337
+ { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1338
+ { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1339
+ { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1340
+ { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1341
+ { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
1342
+};
1343
+
1344
+static void arm_tcg_cpu_register_types(void)
1345
+{
1346
+ size_t i;
1347
+
1348
+ for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
1349
+ arm_cpu_register(&arm_tcg_cpus[i]);
1350
+ }
1351
+}
1352
+
1353
+type_init(arm_tcg_cpu_register_types)
1354
+
1355
+#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
1356
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
1357
index XXXXXXX..XXXXXXX 100644
1358
--- a/target/arm/Makefile.objs
1359
+++ b/target/arm/Makefile.objs
1360
@@ -XXX,XX +XXX,XX @@ obj-y += translate.o op_helper.o
1361
obj-y += crypto_helper.o
1362
obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
1363
obj-y += m_helper.o
1364
+obj-y += cpu_tcg.o
1365
1366
obj-$(CONFIG_SOFTMMU) += psci.o
1367
1368
--
1369
2.20.1
1370
1371
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
I can't find proper documentation or datasheet, but it is likely
4
a MMIO mapped serial device mapped in the 0x80000000..0x8000ffff
5
range belongs to the SoC address space, thus is always mapped in
6
the memory bus.
7
Map the devices on the bus regardless a chardev is attached to it.
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Jan Kiszka <jan.kiszka@web.de>
11
Message-id: 20200505095945.23146-1-f4bug@amsat.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/musicpal.c | 12 ++++--------
15
1 file changed, 4 insertions(+), 8 deletions(-)
16
17
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/musicpal.c
20
+++ b/hw/arm/musicpal.c
21
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
22
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
23
pic[MP_TIMER4_IRQ], NULL);
24
25
- if (serial_hd(0)) {
26
- serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
27
- 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
28
- }
29
- if (serial_hd(1)) {
30
- serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
31
- 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
32
- }
33
+ serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
34
+ 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
35
+ serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
36
+ 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
37
38
/* Register flash */
39
dinfo = drive_get(IF_PFLASH, 0, 0);
40
--
41
2.20.1
42
43
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Now that we can pass 7 parameters, do not encode register
4
operands within simd_data.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200507172352.15418-2-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/helper-sve.h | 45 +++++++----
13
target/arm/sve_helper.c | 157 ++++++++++++++-----------------------
14
target/arm/translate-sve.c | 70 ++++++-----------
15
3 files changed, 114 insertions(+), 158 deletions(-)
16
17
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper-sve.h
20
+++ b/target/arm/helper-sve.h
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_6(sve_fcadd_s, TCG_CALL_NO_RWG,
22
DEF_HELPER_FLAGS_6(sve_fcadd_d, TCG_CALL_NO_RWG,
23
void, ptr, ptr, ptr, ptr, ptr, i32)
24
25
-DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
26
-DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
27
-DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
28
+DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG,
29
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG,
31
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG,
33
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
34
35
-DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
36
-DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
37
-DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
38
+DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG,
39
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG,
41
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
42
+DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG,
43
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
44
45
-DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
46
-DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
47
-DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
48
+DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG,
49
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
50
+DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG,
51
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
52
+DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG,
53
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
54
55
-DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
56
-DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
57
-DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
58
+DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG,
59
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
60
+DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG,
61
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
62
+DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG,
63
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
64
65
-DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
66
-DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
67
-DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
68
+DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG,
69
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
70
+DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG,
71
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
72
+DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG,
73
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
74
75
DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
76
DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
77
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/target/arm/sve_helper.c
80
+++ b/target/arm/sve_helper.c
81
@@ -XXX,XX +XXX,XX @@ DO_ZPZ_FP(sve_ucvt_dd, uint64_t, , uint64_to_float64)
82
83
#undef DO_ZPZ_FP
84
85
-/* 4-operand predicated multiply-add. This requires 7 operands to pass
86
- * "properly", so we need to encode some of the registers into DESC.
87
- */
88
-QEMU_BUILD_BUG_ON(SIMD_DATA_SHIFT + 20 > 32);
89
-
90
-static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
91
+static void do_fmla_zpzzz_h(void *vd, void *vn, void *vm, void *va, void *vg,
92
+ float_status *status, uint32_t desc,
93
uint16_t neg1, uint16_t neg3)
94
{
95
intptr_t i = simd_oprsz(desc);
96
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
97
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
98
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
99
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
100
- void *vd = &env->vfp.zregs[rd];
101
- void *vn = &env->vfp.zregs[rn];
102
- void *vm = &env->vfp.zregs[rm];
103
- void *va = &env->vfp.zregs[ra];
104
uint64_t *g = vg;
105
106
do {
107
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
108
e1 = *(uint16_t *)(vn + H1_2(i)) ^ neg1;
109
e2 = *(uint16_t *)(vm + H1_2(i));
110
e3 = *(uint16_t *)(va + H1_2(i)) ^ neg3;
111
- r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status_f16);
112
+ r = float16_muladd(e1, e2, e3, 0, status);
113
*(uint16_t *)(vd + H1_2(i)) = r;
114
}
115
} while (i & 63);
116
} while (i != 0);
117
}
118
119
-void HELPER(sve_fmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
120
+void HELPER(sve_fmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
121
+ void *vg, void *status, uint32_t desc)
122
{
123
- do_fmla_zpzzz_h(env, vg, desc, 0, 0);
124
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0);
125
}
126
127
-void HELPER(sve_fmls_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
128
+void HELPER(sve_fmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
129
+ void *vg, void *status, uint32_t desc)
130
{
131
- do_fmla_zpzzz_h(env, vg, desc, 0x8000, 0);
132
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0);
133
}
134
135
-void HELPER(sve_fnmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
136
+void HELPER(sve_fnmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
137
+ void *vg, void *status, uint32_t desc)
138
{
139
- do_fmla_zpzzz_h(env, vg, desc, 0x8000, 0x8000);
140
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0x8000);
141
}
142
143
-void HELPER(sve_fnmls_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
144
+void HELPER(sve_fnmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
145
+ void *vg, void *status, uint32_t desc)
146
{
147
- do_fmla_zpzzz_h(env, vg, desc, 0, 0x8000);
148
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0x8000);
149
}
150
151
-static void do_fmla_zpzzz_s(CPUARMState *env, void *vg, uint32_t desc,
152
+static void do_fmla_zpzzz_s(void *vd, void *vn, void *vm, void *va, void *vg,
153
+ float_status *status, uint32_t desc,
154
uint32_t neg1, uint32_t neg3)
155
{
156
intptr_t i = simd_oprsz(desc);
157
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
158
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
159
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
160
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
161
- void *vd = &env->vfp.zregs[rd];
162
- void *vn = &env->vfp.zregs[rn];
163
- void *vm = &env->vfp.zregs[rm];
164
- void *va = &env->vfp.zregs[ra];
165
uint64_t *g = vg;
166
167
do {
168
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_s(CPUARMState *env, void *vg, uint32_t desc,
169
e1 = *(uint32_t *)(vn + H1_4(i)) ^ neg1;
170
e2 = *(uint32_t *)(vm + H1_4(i));
171
e3 = *(uint32_t *)(va + H1_4(i)) ^ neg3;
172
- r = float32_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
173
+ r = float32_muladd(e1, e2, e3, 0, status);
174
*(uint32_t *)(vd + H1_4(i)) = r;
175
}
176
} while (i & 63);
177
} while (i != 0);
178
}
179
180
-void HELPER(sve_fmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
181
+void HELPER(sve_fmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
182
+ void *vg, void *status, uint32_t desc)
183
{
184
- do_fmla_zpzzz_s(env, vg, desc, 0, 0);
185
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0);
186
}
187
188
-void HELPER(sve_fmls_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
189
+void HELPER(sve_fmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
190
+ void *vg, void *status, uint32_t desc)
191
{
192
- do_fmla_zpzzz_s(env, vg, desc, 0x80000000, 0);
193
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0);
194
}
195
196
-void HELPER(sve_fnmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
197
+void HELPER(sve_fnmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
198
+ void *vg, void *status, uint32_t desc)
199
{
200
- do_fmla_zpzzz_s(env, vg, desc, 0x80000000, 0x80000000);
201
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0x80000000);
202
}
203
204
-void HELPER(sve_fnmls_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
205
+void HELPER(sve_fnmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
206
+ void *vg, void *status, uint32_t desc)
207
{
208
- do_fmla_zpzzz_s(env, vg, desc, 0, 0x80000000);
209
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0x80000000);
210
}
211
212
-static void do_fmla_zpzzz_d(CPUARMState *env, void *vg, uint32_t desc,
213
+static void do_fmla_zpzzz_d(void *vd, void *vn, void *vm, void *va, void *vg,
214
+ float_status *status, uint32_t desc,
215
uint64_t neg1, uint64_t neg3)
216
{
217
intptr_t i = simd_oprsz(desc);
218
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
219
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
220
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
221
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
222
- void *vd = &env->vfp.zregs[rd];
223
- void *vn = &env->vfp.zregs[rn];
224
- void *vm = &env->vfp.zregs[rm];
225
- void *va = &env->vfp.zregs[ra];
226
uint64_t *g = vg;
227
228
do {
229
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_d(CPUARMState *env, void *vg, uint32_t desc,
230
e1 = *(uint64_t *)(vn + i) ^ neg1;
231
e2 = *(uint64_t *)(vm + i);
232
e3 = *(uint64_t *)(va + i) ^ neg3;
233
- r = float64_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
234
+ r = float64_muladd(e1, e2, e3, 0, status);
235
*(uint64_t *)(vd + i) = r;
236
}
237
} while (i & 63);
238
} while (i != 0);
239
}
240
241
-void HELPER(sve_fmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
242
+void HELPER(sve_fmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
243
+ void *vg, void *status, uint32_t desc)
244
{
245
- do_fmla_zpzzz_d(env, vg, desc, 0, 0);
246
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, 0);
247
}
248
249
-void HELPER(sve_fmls_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
250
+void HELPER(sve_fmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
251
+ void *vg, void *status, uint32_t desc)
252
{
253
- do_fmla_zpzzz_d(env, vg, desc, INT64_MIN, 0);
254
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, 0);
255
}
256
257
-void HELPER(sve_fnmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
258
+void HELPER(sve_fnmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
259
+ void *vg, void *status, uint32_t desc)
260
{
261
- do_fmla_zpzzz_d(env, vg, desc, INT64_MIN, INT64_MIN);
262
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, INT64_MIN);
263
}
264
265
-void HELPER(sve_fnmls_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
266
+void HELPER(sve_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
267
+ void *vg, void *status, uint32_t desc)
268
{
269
- do_fmla_zpzzz_d(env, vg, desc, 0, INT64_MIN);
270
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, INT64_MIN);
271
}
272
273
/* Two operand floating-point comparison controlled by a predicate.
274
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
275
* FP Complex Multiply
276
*/
277
278
-QEMU_BUILD_BUG_ON(SIMD_DATA_SHIFT + 22 > 32);
279
-
280
-void HELPER(sve_fcmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
281
+void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
282
+ void *vg, void *status, uint32_t desc)
283
{
284
intptr_t j, i = simd_oprsz(desc);
285
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
286
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
287
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
288
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
289
- unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
290
+ unsigned rot = simd_data(desc);
291
bool flip = rot & 1;
292
float16 neg_imag, neg_real;
293
- void *vd = &env->vfp.zregs[rd];
294
- void *vn = &env->vfp.zregs[rn];
295
- void *vm = &env->vfp.zregs[rm];
296
- void *va = &env->vfp.zregs[ra];
297
uint64_t *g = vg;
298
299
neg_imag = float16_set_sign(0, (rot & 2) != 0);
300
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
301
302
if (likely((pg >> (i & 63)) & 1)) {
303
d = *(float16 *)(va + H1_2(i));
304
- d = float16_muladd(e2, e1, d, 0, &env->vfp.fp_status_f16);
305
+ d = float16_muladd(e2, e1, d, 0, status);
306
*(float16 *)(vd + H1_2(i)) = d;
307
}
308
if (likely((pg >> (j & 63)) & 1)) {
309
d = *(float16 *)(va + H1_2(j));
310
- d = float16_muladd(e4, e3, d, 0, &env->vfp.fp_status_f16);
311
+ d = float16_muladd(e4, e3, d, 0, status);
312
*(float16 *)(vd + H1_2(j)) = d;
313
}
314
} while (i & 63);
315
} while (i != 0);
316
}
317
318
-void HELPER(sve_fcmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
319
+void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
320
+ void *vg, void *status, uint32_t desc)
321
{
322
intptr_t j, i = simd_oprsz(desc);
323
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
324
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
325
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
326
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
327
- unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
328
+ unsigned rot = simd_data(desc);
329
bool flip = rot & 1;
330
float32 neg_imag, neg_real;
331
- void *vd = &env->vfp.zregs[rd];
332
- void *vn = &env->vfp.zregs[rn];
333
- void *vm = &env->vfp.zregs[rm];
334
- void *va = &env->vfp.zregs[ra];
335
uint64_t *g = vg;
336
337
neg_imag = float32_set_sign(0, (rot & 2) != 0);
338
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
339
340
if (likely((pg >> (i & 63)) & 1)) {
341
d = *(float32 *)(va + H1_2(i));
342
- d = float32_muladd(e2, e1, d, 0, &env->vfp.fp_status);
343
+ d = float32_muladd(e2, e1, d, 0, status);
344
*(float32 *)(vd + H1_2(i)) = d;
345
}
346
if (likely((pg >> (j & 63)) & 1)) {
347
d = *(float32 *)(va + H1_2(j));
348
- d = float32_muladd(e4, e3, d, 0, &env->vfp.fp_status);
349
+ d = float32_muladd(e4, e3, d, 0, status);
350
*(float32 *)(vd + H1_2(j)) = d;
351
}
352
} while (i & 63);
353
} while (i != 0);
354
}
355
356
-void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
357
+void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
358
+ void *vg, void *status, uint32_t desc)
359
{
360
intptr_t j, i = simd_oprsz(desc);
361
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
362
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
363
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
364
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
365
- unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
366
+ unsigned rot = simd_data(desc);
367
bool flip = rot & 1;
368
float64 neg_imag, neg_real;
369
- void *vd = &env->vfp.zregs[rd];
370
- void *vn = &env->vfp.zregs[rn];
371
- void *vm = &env->vfp.zregs[rm];
372
- void *va = &env->vfp.zregs[ra];
373
uint64_t *g = vg;
374
375
neg_imag = float64_set_sign(0, (rot & 2) != 0);
376
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
377
378
if (likely((pg >> (i & 63)) & 1)) {
379
d = *(float64 *)(va + H1_2(i));
380
- d = float64_muladd(e2, e1, d, 0, &env->vfp.fp_status);
381
+ d = float64_muladd(e2, e1, d, 0, status);
382
*(float64 *)(vd + H1_2(i)) = d;
383
}
384
if (likely((pg >> (j & 63)) & 1)) {
385
d = *(float64 *)(va + H1_2(j));
386
- d = float64_muladd(e4, e3, d, 0, &env->vfp.fp_status);
387
+ d = float64_muladd(e4, e3, d, 0, status);
388
*(float64 *)(vd + H1_2(j)) = d;
389
}
390
} while (i & 63);
391
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
392
index XXXXXXX..XXXXXXX 100644
393
--- a/target/arm/translate-sve.c
394
+++ b/target/arm/translate-sve.c
395
@@ -XXX,XX +XXX,XX @@ static bool trans_FCADD(DisasContext *s, arg_FCADD *a)
396
return true;
397
}
398
399
-typedef void gen_helper_sve_fmla(TCGv_env, TCGv_ptr, TCGv_i32);
400
-
401
-static bool do_fmla(DisasContext *s, arg_rprrr_esz *a, gen_helper_sve_fmla *fn)
402
+static bool do_fmla(DisasContext *s, arg_rprrr_esz *a,
403
+ gen_helper_gvec_5_ptr *fn)
404
{
405
- if (fn == NULL) {
406
+ if (a->esz == 0) {
407
return false;
408
}
409
- if (!sve_access_check(s)) {
410
- return true;
411
+ if (sve_access_check(s)) {
412
+ unsigned vsz = vec_full_reg_size(s);
413
+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
414
+ tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd),
415
+ vec_full_reg_offset(s, a->rn),
416
+ vec_full_reg_offset(s, a->rm),
417
+ vec_full_reg_offset(s, a->ra),
418
+ pred_full_reg_offset(s, a->pg),
419
+ status, vsz, vsz, 0, fn);
420
+ tcg_temp_free_ptr(status);
421
}
422
-
423
- unsigned vsz = vec_full_reg_size(s);
424
- unsigned desc;
425
- TCGv_i32 t_desc;
426
- TCGv_ptr pg = tcg_temp_new_ptr();
427
-
428
- /* We would need 7 operands to pass these arguments "properly".
429
- * So we encode all the register numbers into the descriptor.
430
- */
431
- desc = deposit32(a->rd, 5, 5, a->rn);
432
- desc = deposit32(desc, 10, 5, a->rm);
433
- desc = deposit32(desc, 15, 5, a->ra);
434
- desc = simd_desc(vsz, vsz, desc);
435
-
436
- t_desc = tcg_const_i32(desc);
437
- tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
438
- fn(cpu_env, pg, t_desc);
439
- tcg_temp_free_i32(t_desc);
440
- tcg_temp_free_ptr(pg);
441
return true;
442
}
443
444
#define DO_FMLA(NAME, name) \
445
static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a) \
446
{ \
447
- static gen_helper_sve_fmla * const fns[4] = { \
448
+ static gen_helper_gvec_5_ptr * const fns[4] = { \
449
NULL, gen_helper_sve_##name##_h, \
450
gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \
451
}; \
452
@@ -XXX,XX +XXX,XX @@ DO_FMLA(FNMLS_zpzzz, fnmls_zpzzz)
453
454
static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
455
{
456
- static gen_helper_sve_fmla * const fns[3] = {
457
+ static gen_helper_gvec_5_ptr * const fns[4] = {
458
+ NULL,
459
gen_helper_sve_fcmla_zpzzz_h,
460
gen_helper_sve_fcmla_zpzzz_s,
461
gen_helper_sve_fcmla_zpzzz_d,
462
@@ -XXX,XX +XXX,XX @@ static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
463
}
464
if (sve_access_check(s)) {
465
unsigned vsz = vec_full_reg_size(s);
466
- unsigned desc;
467
- TCGv_i32 t_desc;
468
- TCGv_ptr pg = tcg_temp_new_ptr();
469
-
470
- /* We would need 7 operands to pass these arguments "properly".
471
- * So we encode all the register numbers into the descriptor.
472
- */
473
- desc = deposit32(a->rd, 5, 5, a->rn);
474
- desc = deposit32(desc, 10, 5, a->rm);
475
- desc = deposit32(desc, 15, 5, a->ra);
476
- desc = deposit32(desc, 20, 2, a->rot);
477
- desc = sextract32(desc, 0, 22);
478
- desc = simd_desc(vsz, vsz, desc);
479
-
480
- t_desc = tcg_const_i32(desc);
481
- tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
482
- fns[a->esz - 1](cpu_env, pg, t_desc);
483
- tcg_temp_free_i32(t_desc);
484
- tcg_temp_free_ptr(pg);
485
+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
486
+ tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd),
487
+ vec_full_reg_offset(s, a->rn),
488
+ vec_full_reg_offset(s, a->rm),
489
+ vec_full_reg_offset(s, a->ra),
490
+ pred_full_reg_offset(s, a->pg),
491
+ status, vsz, vsz, a->rot, fns[a->esz]);
492
+ tcg_temp_free_ptr(status);
493
}
494
return true;
495
}
496
--
497
2.20.1
498
499
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
DUP (indexed) can duplicate 128-bit elements, so using esz
4
unconditionally can assert in tcg_gen_gvec_dup_imm.
5
6
Fixes: 8711e71f9cbb
7
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Message-id: 20200507172352.15418-5-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/translate-sve.c | 6 +++++-
15
1 file changed, 5 insertions(+), 1 deletion(-)
16
17
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate-sve.c
20
+++ b/target/arm/translate-sve.c
21
@@ -XXX,XX +XXX,XX @@ static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a)
22
unsigned nofs = vec_reg_offset(s, a->rn, index, esz);
23
tcg_gen_gvec_dup_mem(esz, dofs, nofs, vsz, vsz);
24
} else {
25
- tcg_gen_gvec_dup_imm(esz, dofs, vsz, vsz, 0);
26
+ /*
27
+ * While dup_mem handles 128-bit elements, dup_imm does not.
28
+ * Thankfully element size doesn't matter for splatting zero.
29
+ */
30
+ tcg_gen_gvec_dup_imm(MO_64, dofs, vsz, vsz, 0);
31
}
32
}
33
return true;
34
--
35
2.20.1
36
37
diff view generated by jsdifflib