target/ppc/cpu.h | 21 +++++++++++++++++++++ hw/ppc/pnv.c | 8 ++++---- target/ppc/excp_helper.c | 16 ++++++++-------- 3 files changed, 33 insertions(+), 12 deletions(-)
If an interrupt occurred when the thread was in power-saving mode,
bits [42:45] of SRR1 indicate the exception that caused exit from
power-saving mode.
bits [46:47] of SRR1 indicate the power-saving mode in which the
thread was when the interrupt occured.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 21 +++++++++++++++++++++
hw/ppc/pnv.c | 8 ++++----
target/ppc/excp_helper.c | 16 ++++++++--------
3 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index df5c30160da8..9648623677d2 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -476,6 +476,27 @@ typedef struct ppc_v3_pate_t {
#define SRR1_PROTFAULT DSISR_PROTFAULT
#define SRR1_IAMR DSISR_AMR
+/* SRR1[42:45] wakeup fields for System Reset Interrupt */
+
+#define SRR1_WAKEMASK 0x003c0000 /* reason for wakeup */
+
+#define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */
+#define SRR1_WAKEHVI 0x00240000 /* Hypervisor Virt. Interrupt (P9) */
+#define SRR1_WAKEEE 0x00200000 /* External interrupt */
+#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
+#define SRR1_WAKEDBELL 0x00140000 /* Privileged doorbell */
+#define SRR1_WAKERESET 0x00100000 /* System reset */
+#define SRR1_WAKEHDBELL 0x000c0000 /* Hypervisor doorbell */
+#define SRR1_WAKESCOM 0x00080000 /* SCOM not in power-saving mode */
+
+/* SRR1[46:47] power-saving exit mode */
+
+#define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask */
+
+#define SRR1_WS_HVLOSS 0x00030000 /* HV resources not maintained */
+#define SRR1_WS_GPRLOSS 0x00020000 /* GPRs not maintained */
+#define SRR1_WS_NOLOSS 0x00010000 /* All resources maintained */
+
/* Facility Status and Control (FSCR) bits */
#define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
#define FSCR_TAR (63 - 55) /* Target Address Register */
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 1b4748ce6dc3..182b62565022 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1986,15 +1986,15 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
cpu_synchronize_state(cs);
ppc_cpu_do_system_reset(cs);
- if (env->spr[SPR_SRR1] & PPC_BITMASK(46, 47)) {
+ if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) {
/*
* Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
* wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
* (PPC_BIT(43)).
*/
- if (!(env->spr[SPR_SRR1] & PPC_BIT(43))) {
+ if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) {
warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
- env->spr[SPR_SRR1] |= PPC_BIT(43);
+ env->spr[SPR_SRR1] |= SRR1_WAKERESET;
}
} else {
/*
@@ -2004,7 +2004,7 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
* another CPU requesting a NMI IPI) system reset exception should be
* 0b0010 (PPC_BIT(44)).
*/
- env->spr[SPR_SRR1] |= PPC_BIT(44);
+ env->spr[SPR_SRR1] |= SRR1_WAKESCOM;
}
}
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 14d39029825a..a988ba15f4f7 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -101,7 +101,7 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp,
env->resume_as_sreset = false;
/* Pretend to be returning from doze always as we don't lose state */
- *msr |= (0x1ull << (63 - 47));
+ *msr |= SRR1_WS_NOLOSS;
/* Machine checks are sent normally */
if (excp == POWERPC_EXCP_MCHECK) {
@@ -109,25 +109,25 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp,
}
switch (excp) {
case POWERPC_EXCP_RESET:
- *msr |= 0x4ull << (63 - 45);
+ *msr |= SRR1_WAKERESET;
break;
case POWERPC_EXCP_EXTERNAL:
- *msr |= 0x8ull << (63 - 45);
+ *msr |= SRR1_WAKEEE;
break;
case POWERPC_EXCP_DECR:
- *msr |= 0x6ull << (63 - 45);
+ *msr |= SRR1_WAKEDEC;
break;
case POWERPC_EXCP_SDOOR:
- *msr |= 0x5ull << (63 - 45);
+ *msr |= SRR1_WAKEDBELL;
break;
case POWERPC_EXCP_SDOOR_HV:
- *msr |= 0x3ull << (63 - 45);
+ *msr |= SRR1_WAKEHDBELL;
break;
case POWERPC_EXCP_HV_MAINT:
- *msr |= 0xaull << (63 - 45);
+ *msr |= SRR1_WAKEHMI;
break;
case POWERPC_EXCP_HVIRT:
- *msr |= 0x9ull << (63 - 45);
+ *msr |= SRR1_WAKEHVI;
break;
default:
cpu_abort(cs, "Unsupported exception %d in Power Save mode\n",
--
2.25.4
On Mon, May 11, 2020 at 10:58:22AM +0200, Cédric Le Goater wrote: > If an interrupt occurred when the thread was in power-saving mode, > bits [42:45] of SRR1 indicate the exception that caused exit from > power-saving mode. > > bits [46:47] of SRR1 indicate the power-saving mode in which the > thread was when the interrupt occured. > > Signed-off-by: Cédric Le Goater <clg@kaod.org> Applied to ppc-for-5.1. > --- > target/ppc/cpu.h | 21 +++++++++++++++++++++ > hw/ppc/pnv.c | 8 ++++---- > target/ppc/excp_helper.c | 16 ++++++++-------- > 3 files changed, 33 insertions(+), 12 deletions(-) > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index df5c30160da8..9648623677d2 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -476,6 +476,27 @@ typedef struct ppc_v3_pate_t { > #define SRR1_PROTFAULT DSISR_PROTFAULT > #define SRR1_IAMR DSISR_AMR > > +/* SRR1[42:45] wakeup fields for System Reset Interrupt */ > + > +#define SRR1_WAKEMASK 0x003c0000 /* reason for wakeup */ > + > +#define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */ > +#define SRR1_WAKEHVI 0x00240000 /* Hypervisor Virt. Interrupt (P9) */ > +#define SRR1_WAKEEE 0x00200000 /* External interrupt */ > +#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */ > +#define SRR1_WAKEDBELL 0x00140000 /* Privileged doorbell */ > +#define SRR1_WAKERESET 0x00100000 /* System reset */ > +#define SRR1_WAKEHDBELL 0x000c0000 /* Hypervisor doorbell */ > +#define SRR1_WAKESCOM 0x00080000 /* SCOM not in power-saving mode */ > + > +/* SRR1[46:47] power-saving exit mode */ > + > +#define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask */ > + > +#define SRR1_WS_HVLOSS 0x00030000 /* HV resources not maintained */ > +#define SRR1_WS_GPRLOSS 0x00020000 /* GPRs not maintained */ > +#define SRR1_WS_NOLOSS 0x00010000 /* All resources maintained */ > + > /* Facility Status and Control (FSCR) bits */ > #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */ > #define FSCR_TAR (63 - 55) /* Target Address Register */ > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 1b4748ce6dc3..182b62565022 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -1986,15 +1986,15 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) > > cpu_synchronize_state(cs); > ppc_cpu_do_system_reset(cs); > - if (env->spr[SPR_SRR1] & PPC_BITMASK(46, 47)) { > + if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { > /* > * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the > * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 > * (PPC_BIT(43)). > */ > - if (!(env->spr[SPR_SRR1] & PPC_BIT(43))) { > + if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { > warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); > - env->spr[SPR_SRR1] |= PPC_BIT(43); > + env->spr[SPR_SRR1] |= SRR1_WAKERESET; > } > } else { > /* > @@ -2004,7 +2004,7 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) > * another CPU requesting a NMI IPI) system reset exception should be > * 0b0010 (PPC_BIT(44)). > */ > - env->spr[SPR_SRR1] |= PPC_BIT(44); > + env->spr[SPR_SRR1] |= SRR1_WAKESCOM; > } > } > > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c > index 14d39029825a..a988ba15f4f7 100644 > --- a/target/ppc/excp_helper.c > +++ b/target/ppc/excp_helper.c > @@ -101,7 +101,7 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp, > env->resume_as_sreset = false; > > /* Pretend to be returning from doze always as we don't lose state */ > - *msr |= (0x1ull << (63 - 47)); > + *msr |= SRR1_WS_NOLOSS; > > /* Machine checks are sent normally */ > if (excp == POWERPC_EXCP_MCHECK) { > @@ -109,25 +109,25 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp, > } > switch (excp) { > case POWERPC_EXCP_RESET: > - *msr |= 0x4ull << (63 - 45); > + *msr |= SRR1_WAKERESET; > break; > case POWERPC_EXCP_EXTERNAL: > - *msr |= 0x8ull << (63 - 45); > + *msr |= SRR1_WAKEEE; > break; > case POWERPC_EXCP_DECR: > - *msr |= 0x6ull << (63 - 45); > + *msr |= SRR1_WAKEDEC; > break; > case POWERPC_EXCP_SDOOR: > - *msr |= 0x5ull << (63 - 45); > + *msr |= SRR1_WAKEDBELL; > break; > case POWERPC_EXCP_SDOOR_HV: > - *msr |= 0x3ull << (63 - 45); > + *msr |= SRR1_WAKEHDBELL; > break; > case POWERPC_EXCP_HV_MAINT: > - *msr |= 0xaull << (63 - 45); > + *msr |= SRR1_WAKEHMI; > break; > case POWERPC_EXCP_HVIRT: > - *msr |= 0x9ull << (63 - 45); > + *msr |= SRR1_WAKEHVI; > break; > default: > cpu_abort(cs, "Unsupported exception %d in Power Save mode\n", -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
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