The following changes since commit a36d64f43325fa503075cc9408ddabb69b32f829:

Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-gdbstub-060520-1' into staging (2020-05-06 14:06:00 +0100)

https://github.com/rth7680/qemu.git tags/pull-tcg-20200506

for you to fetch changes up to 07dada0336a83002dfa8673a9220a88e13d9a45c:

tcg: Fix integral argument type to tcg_gen_rot[rl]i_i{32,64} (2020-05-06 09:25:10 -0700)

Add tcg_gen_gvec_dup_imm

Misc tcg patches

Richard Henderson (10):

tcg: Add tcg_gen_gvec_dup_imm

target/s390x: Use tcg_gen_gvec_dup_imm

target/ppc: Use tcg_gen_gvec_dup_imm

target/arm: Use tcg_gen_gvec_dup_imm

tcg: Use tcg_gen_gvec_dup_imm in logical simplifications

tcg: Remove tcg_gen_gvec_dup{8,16,32,64}i

tcg: Add tcg_gen_gvec_dup_tl

tcg: Improve vector tail clearing

tcg: Add load_dest parameter to GVecGen2

tcg: Fix integral argument type to tcg_gen_rot[rl]i_i{32,64}

include/tcg/tcg-op-gvec.h | 13 ++-

include/tcg/tcg-op.h | 8 +-

target/arm/translate-a64.c | 10 +--

target/arm/translate-sve.c | 12 ++-

target/arm/translate.c | 9 +-

target/ppc/translate/vmx-impl.inc.c | 32 +++----

target/ppc/translate/vsx-impl.inc.c | 2 +-

target/s390x/translate_vx.inc.c | 41 ++-------

tcg/tcg-op-gvec.c | 162 +++++++++++++++++++++++-------------

tcg/tcg-op.c | 16 ++--

10 files changed, 166 insertions(+), 139 deletions(-)

Add a version of tcg_gen_dup_* that takes both immediate and

a vector element size operand. This will replace the set of

tcg_gen_gvec_dup{8,16,32,64}i functions that encode the element

size within the function name.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>

Reviewed-by: David Hildenbrand <david@redhat.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

include/tcg/tcg-op-gvec.h | 2 ++

tcg/tcg-op-gvec.c | 7 +++++++

2 files changed, 9 insertions(+)

diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h

--- a/include/tcg/tcg-op-gvec.h

+++ b/include/tcg/tcg-op-gvec.h

@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs,

void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,

uint32_t s, uint32_t m);

+void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t s,

+ uint32_t m, uint64_t imm);

void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,

uint32_t m, TCGv_i32);

void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s,

diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c

index XXXXXXX..XXXXXXX 100644

--- a/tcg/tcg-op-gvec.c

+++ b/tcg/tcg-op-gvec.c

@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz,

do_dup(MO_8, dofs, oprsz, maxsz, NULL, NULL, x);

}

+void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t oprsz,

+ uint32_t maxsz, uint64_t x)

+ check_size_align(oprsz, maxsz, dofs);

+ do_dup(vece, dofs, oprsz, maxsz, NULL, NULL, x);

void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs,

uint32_t oprsz, uint32_t maxsz)

{

2.20.1

For the benefit of compatibility of function pointer types,

we have standardized on int32_t and int64_t as the integral

argument to tcg expanders.

We converted most of them in 474b2e8f0f7, but missed the rotates.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

include/tcg/tcg-op.h | 8 ++++----

tcg/tcg-op.c | 16 ++++++++--------

2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h

--- a/include/tcg/tcg-op.h

+++ b/include/tcg/tcg-op.h

@@ -XXX,XX +XXX,XX @@ void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);

void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg);

void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2);

void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);

-void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);

+void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);

void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);

-void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);

+void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);

void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,

unsigned int ofs, unsigned int len);

void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg,

@@ -XXX,XX +XXX,XX @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);

void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg);

void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2);

void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);

-void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);

+void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);

void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);

-void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);

+void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);

void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,

unsigned int ofs, unsigned int len);

void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg,

diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c

index XXXXXXX..XXXXXXX 100644

--- a/tcg/tcg-op.c

+++ b/tcg/tcg-op.c

@@ -XXX,XX +XXX,XX @@ void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)

2.20.1

We have this same parameter for GVecGen2i, GVecGen3,

and GVecGen3i. This will make some SVE2 insns easier

to parameterize.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

include/tcg/tcg-op-gvec.h | 2 ++

tcg/tcg-op-gvec.c | 45 ++++++++++++++++++++++++++++-----------

2 files changed, 34 insertions(+), 13 deletions(-)

diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h

--- a/include/tcg/tcg-op-gvec.h

+++ b/include/tcg/tcg-op-gvec.h

@@ -XXX,XX +XXX,XX @@ typedef struct {

uint8_t vece;

/* Prefer i64 to v64. */

bool prefer_i64;

+ /* Load dest as a 2nd source operand. */

+ bool load_dest;

} GVecGen2;

typedef struct {

diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c

index XXXXXXX..XXXXXXX 100644

--- a/tcg/tcg-op-gvec.c

+++ b/tcg/tcg-op-gvec.c

@@ -XXX,XX +XXX,XX @@ static void expand_clr(uint32_t dofs, uint32_t maxsz)

/* Expand OPSZ bytes worth of two-operand operations using i32 elements. */

static void expand_2_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,

- void (*fni)(TCGv_i32, TCGv_i32))

+ bool load_dest, void (*fni)(TCGv_i32, TCGv_i32))

{

TCGv_i32 t0 = tcg_temp_new_i32();

+ TCGv_i32 t1 = tcg_temp_new_i32();

uint32_t i;

for (i = 0; i < oprsz; i += 4) {

tcg_gen_ld_i32(t0, cpu_env, aofs + i);

- fni(t0, t0);

- tcg_gen_st_i32(t0, cpu_env, dofs + i);

+ if (load_dest) {

+ tcg_gen_ld_i32(t1, cpu_env, dofs + i);

+ }

+ fni(t1, t0);

+ tcg_gen_st_i32(t1, cpu_env, dofs + i);

}

tcg_temp_free_i32(t0);

+ tcg_temp_free_i32(t1);

}

static void expand_2i_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,

@@ -XXX,XX +XXX,XX @@ static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,

/* Expand OPSZ bytes worth of two-operand operations using i64 elements. */

static void expand_2_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,

- void (*fni)(TCGv_i64, TCGv_i64))

+ bool load_dest, void (*fni)(TCGv_i64, TCGv_i64))

{

TCGv_i64 t0 = tcg_temp_new_i64();

+ TCGv_i64 t1 = tcg_temp_new_i64();

uint32_t i;

for (i = 0; i < oprsz; i += 8) {

tcg_gen_ld_i64(t0, cpu_env, aofs + i);

- fni(t0, t0);

- tcg_gen_st_i64(t0, cpu_env, dofs + i);

+ if (load_dest) {

+ tcg_gen_ld_i64(t1, cpu_env, dofs + i);

+ }

+ fni(t1, t0);

+ tcg_gen_st_i64(t1, cpu_env, dofs + i);

}

tcg_temp_free_i64(t0);

+ tcg_temp_free_i64(t1);

}

static void expand_2i_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,

@@ -XXX,XX +XXX,XX @@ static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,

/* Expand OPSZ bytes worth of two-operand operations using host vectors. */

static void expand_2_vec(unsigned vece, uint32_t dofs, uint32_t aofs,

uint32_t oprsz, uint32_t tysz, TCGType type,

+ bool load_dest,

void (*fni)(unsigned, TCGv_vec, TCGv_vec))

{

TCGv_vec t0 = tcg_temp_new_vec(type);

+ TCGv_vec t1 = tcg_temp_new_vec(type);

uint32_t i;

for (i = 0; i < oprsz; i += tysz) {

tcg_gen_ld_vec(t0, cpu_env, aofs + i);

- fni(vece, t0, t0);

- tcg_gen_st_vec(t0, cpu_env, dofs + i);

+ if (load_dest) {

+ tcg_gen_ld_vec(t1, cpu_env, dofs + i);

+ }

+ fni(vece, t1, t0);

+ tcg_gen_st_vec(t1, cpu_env, dofs + i);

}

tcg_temp_free_vec(t0);

+ tcg_temp_free_vec(t1);

}

/* Expand OPSZ bytes worth of two-vector operands and an immediate operand

@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,

* that e.g. size == 80 would be expanded with 2x32 + 1x16.

*/

some = QEMU_ALIGN_DOWN(oprsz, 32);

- expand_2_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, g->fniv);

+ expand_2_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256,

+ g->load_dest, g->fniv);

if (some == oprsz) {

break;

}

@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,

maxsz -= some;

/* fallthru */

case TCG_TYPE_V128:

- expand_2_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, g->fniv);

+ expand_2_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128,

+ g->load_dest, g->fniv);

break;

case TCG_TYPE_V64:

- expand_2_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, g->fniv);

+ expand_2_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64,

+ g->load_dest, g->fniv);

break;

case 0:

if (g->fni8 && check_size_impl(oprsz, 8)) {

- expand_2_i64(dofs, aofs, oprsz, g->fni8);

+ expand_2_i64(dofs, aofs, oprsz, g->load_dest, g->fni8);

} else if (g->fni4 && check_size_impl(oprsz, 4)) {

- expand_2_i32(dofs, aofs, oprsz, g->fni4);

+ expand_2_i32(dofs, aofs, oprsz, g->load_dest, g->fni4);

} else {

assert(g->fno != NULL);

tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, g->data, g->fno);

2.20.1

In a few cases, we're able to remove some manual replication.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

target/arm/translate-a64.c | 10 +++++-----

target/arm/translate-sve.c | 12 +++++-------

target/arm/translate.c | 9 ++++++---

3 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void clear_vec_high(DisasContext *s, bool is_q, int rd)

tcg_temp_free_i64(tcg_zero);

if (vsz > 16) {

- tcg_gen_gvec_dup8i(ofs + 16, vsz - 16, vsz - 16, 0);

+ tcg_gen_gvec_dup_imm(MO_64, ofs + 16, vsz - 16, vsz - 16, 0);

@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)

if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {

/* MOVI or MVNI, with MVNI negation handled above. */

- tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), is_q ? 16 : 8,

- vec_full_reg_size(s), imm);

+ tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), is_q ? 16 : 8,

+ vec_full_reg_size(s), imm);

/* ORR or BIC, with BIC negation to AND handled above. */

if (is_neg) {

@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,

if (is_u) {

if (shift == 8 << size) {

/* Shift count the same size as element size produces zero. */

- tcg_gen_gvec_dup8i(vec_full_reg_offset(s, rd),

- is_q ? 16 : 8, vec_full_reg_size(s), 0);

+ tcg_gen_gvec_dup_imm(size, vec_full_reg_offset(s, rd),

+ is_q ? 16 : 8, vec_full_reg_size(s), 0);

} else {

gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shri, size);

}

diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-sve.c

+++ b/target/arm/translate-sve.c

@@ -XXX,XX +XXX,XX @@ static bool do_mov_z(DisasContext *s, int rd, int rn)

static void do_dupi_z(DisasContext *s, int rd, uint64_t word)

{

unsigned vsz = vec_full_reg_size(s);

- tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), vsz, vsz, word);

+ tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), vsz, vsz, word);

}

/* Invoke a vector expander on two Pregs. */

@@ -XXX,XX +XXX,XX @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)

unsigned oprsz = size_for_gvec(setsz / 8);

if (oprsz * 8 == setsz) {

- tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);

+ tcg_gen_gvec_dup_imm(MO_64, ofs, oprsz, maxsz, word);

goto done;

}

2.20.1