[PULL v2 00/30] target-arm queue
[PULL v2 00/57] target-arm queue
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v2:
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Squashed in a trivial fix for 32-bit hosts:
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* dropped target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]
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* renamed CLOCK_SECOND to CLOCK_PERIOD_1SEC
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2
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--- a/target/arm/mve_helper.c
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+++ b/target/arm/mve_helper.c
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@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
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acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
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m[H##ESIZE(e)])); \
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} \
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- acc = int128_add(acc, 1 << 7); \
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+ acc = int128_add(acc, int128_make64(1 << 7)); \
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} \
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} \
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mve_advance_vpt(env); \
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14
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The following changes since commit 648db19685b7030aa558a4ddbd3a8e53d8c9a062:
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-- PMM
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Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-04-29' into staging (2020-04-29 15:07:33 +0100)
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The following changes since commit 53f306f316549d20c76886903181413d20842423:
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Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
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20
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200430-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
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24
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for you to fetch changes up to 6f7b6947a6639fff15c6a0956adf0f5ec004b789:
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for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
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26
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hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes (2020-04-30 15:35:41 +0100)
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docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
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28
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* xlnx-zdma: Fix endianness handling of descriptor loading
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* Don't require 'virt' board to be compiled in for ACPI GHES code
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* nrf51: Fix last GPIO CNF address
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* docs: Document which architecture extensions we emulate
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* gicv3: Use gicr_typer in arm_gicv3_icc_reset
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* Fix bugs in M-profile FPCXT_NS accesses
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* msf2: Add EMAC block to SmartFusion2 SoC
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* First slice of MVE patches
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* New clock modelling framework
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* Implement MTE3
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* hw/arm: versal: Setup the ADMA with 128bit bus-width
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* docs/system: arm: Add nRF boards description
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* Cadence: gem: fix wraparound in 64bit descriptors
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* cadence_gem: clear RX control descriptor
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* target/arm: Vectorize integer comparison vs zero
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* hw/arm/virt: dt: add kaslr-seed property
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* hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes
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37
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----------------------------------------------------------------
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----------------------------------------------------------------
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Cameron Esfahani (1):
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Alexandre Iooss (1):
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nrf51: Fix last GPIO CNF address
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docs/system: arm: Add nRF boards description
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41
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Damien Hedde (7):
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Peter Collingbourne (1):
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hw/core/clock-vmstate: define a vmstate entry for clock state
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target/arm: Implement MTE3
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qdev: add clock input&output support to devices.
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qdev-clock: introduce an init array to ease the device construction
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hw/misc/zynq_slcr: add clock generation for uarts
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hw/char/cadence_uart: add clock support
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hw/arm/xilinx_zynq: connect uart clocks to slcr
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qdev-monitor: print the device's clock with info qtree
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Edgar E. Iglesias (7):
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Peter Maydell (55):
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dma/xlnx-zdma: Fix descriptor loading (MEM) wrt endianness
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hw/acpi: Provide stub version of acpi_ghes_record_errors()
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dma/xlnx-zdma: Fix descriptor loading (REG) wrt endianness
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hw/acpi: Provide function acpi_ghes_present()
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hw/arm: versal: Setup the ADMA with 128bit bus-width
48
target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
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device_tree: Allow name wildcards in qemu_fdt_node_path()
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docs/system/arm: Document which architecture extensions we emulate
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device_tree: Constify compat in qemu_fdt_node_path()
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target/arm/translate-vfp.c: Whitespace fixes
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hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102
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target/arm: Handle FPU being disabled in FPCXT_NS accesses
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hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes
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target/arm: Don't NOCP fault for FPCXT_NS accesses
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target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
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target/arm: Factor FP context update code out into helper function
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target/arm: Split vfp_access_check() into A and M versions
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target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
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target/arm: Implement MVE VLDR/VSTR (non-widening forms)
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target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
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target/arm: Implement MVE VCLZ
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target/arm: Implement MVE VCLS
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target/arm: Implement MVE VREV16, VREV32, VREV64
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target/arm: Implement MVE VMVN (register)
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target/arm: Implement MVE VABS
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target/arm: Implement MVE VNEG
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tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
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target/arm: Implement MVE VDUP
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target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
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target/arm: Implement MVE VADD, VSUB, VMUL
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target/arm: Implement MVE VMULH
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target/arm: Implement MVE VRMULH
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target/arm: Implement MVE VMAX, VMIN
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target/arm: Implement MVE VABD
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target/arm: Implement MVE VHADD, VHSUB
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target/arm: Implement MVE VMULL
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target/arm: Implement MVE VMLALDAV
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target/arm: Implement MVE VMLSLDAV
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target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
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target/arm: Implement MVE VADD (scalar)
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target/arm: Implement MVE VSUB, VMUL (scalar)
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target/arm: Implement MVE VHADD, VHSUB (scalar)
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target/arm: Implement MVE VBRSR
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target/arm: Implement MVE VPST
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target/arm: Implement MVE VQADD and VQSUB
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target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
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target/arm: Implement MVE VQDMULL scalar
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target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
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target/arm: Implement MVE VQADD, VQSUB (vector)
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target/arm: Implement MVE VQSHL (vector)
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target/arm: Implement MVE VQRSHL
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target/arm: Implement MVE VSHL insn
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target/arm: Implement MVE VRSHL
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target/arm: Implement MVE VQDMLADH and VQRDMLADH
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target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
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target/arm: Implement MVE VQDMULL (vector)
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target/arm: Implement MVE VRHADD
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target/arm: Implement MVE VADC, VSBC
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target/arm: Implement MVE VCADD
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target/arm: Implement MVE VHCADD
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target/arm: Implement MVE VADDV
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target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
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101
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Jerome Forissier (2):
102
docs/system/arm/emulation.rst | 103 ++++
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hw/arm/virt: dt: move creation of /secure-chosen to create_fdt()
103
docs/system/arm/nrf.rst | 51 ++
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hw/arm/virt: dt: add kaslr-seed property
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docs/system/target-arm.rst | 7 +
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include/hw/acpi/ghes.h | 9 +
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include/tcg/tcg-op.h | 8 +
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include/tcg/tcg.h | 1 -
108
target/arm/helper-mve.h | 357 +++++++++++++
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target/arm/helper.h | 2 +
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target/arm/internals.h | 11 +
111
target/arm/translate-a32.h | 3 +
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target/arm/translate.h | 10 +
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target/arm/m-nocp.decode | 24 +
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target/arm/mve.decode | 240 +++++++++
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target/arm/vfp.decode | 14 -
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hw/acpi/ghes-stub.c | 22 +
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hw/acpi/ghes.c | 17 +
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target/arm/cpu64.c | 2 +-
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target/arm/kvm64.c | 6 +-
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target/arm/mte_helper.c | 82 +--
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target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
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target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
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target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
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target/arm/translate-vfp.c | 741 +++++++-------------------
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tcg/tcg-op-gvec.c | 20 +-
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MAINTAINERS | 1 +
127
hw/acpi/meson.build | 6 +-
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target/arm/meson.build | 1 +
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27 files changed, 3578 insertions(+), 629 deletions(-)
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create mode 100644 docs/system/arm/emulation.rst
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create mode 100644 docs/system/arm/nrf.rst
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create mode 100644 target/arm/helper-mve.h
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create mode 100644 hw/acpi/ghes-stub.c
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create mode 100644 target/arm/mve_helper.c
57
135
58
Keqian Zhu (2):
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bugfix: Use gicr_typer in arm_gicv3_icc_reset
60
Typo: Correct the name of CPU hotplug memory region
61
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Peter Maydell (2):
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hw/core/clock: introduce clock object
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docs/clocks: add device's clock documentation
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Philippe Mathieu-Daudé (2):
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target/arm: Restrict the Address Translate write operation to TCG accel
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target/arm/cpu: Update coding style to make checkpatch.pl happy
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Ramon Fried (2):
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Cadence: gem: fix wraparound in 64bit descriptors
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net: cadence_gem: clear RX control descriptor
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Richard Henderson (1):
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target/arm: Vectorize integer comparison vs zero
76
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Subbaraya Sundeep (3):
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hw/net: Add Smartfusion2 emac block
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msf2: Add EMAC block to SmartFusion2 SoC
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tests/boot_linux_console: Add ethernet test to SmartFusion2
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Thomas Huth (1):
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target/arm: Make cpu_register() available for other files
84
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hw/core/Makefile.objs | 2 +
86
hw/net/Makefile.objs | 1 +
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tests/Makefile.include | 1 +
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include/hw/arm/msf2-soc.h | 2 +
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include/hw/char/cadence_uart.h | 1 +
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include/hw/clock.h | 225 +++++++++++++
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include/hw/gpio/nrf51_gpio.h | 2 +-
92
include/hw/net/msf2-emac.h | 53 +++
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include/hw/qdev-clock.h | 159 +++++++++
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include/hw/qdev-core.h | 12 +
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include/sysemu/device_tree.h | 5 +-
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target/arm/cpu-qom.h | 9 +-
97
target/arm/helper.h | 27 +-
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target/arm/translate.h | 5 +
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device_tree.c | 4 +-
100
hw/acpi/cpu.c | 2 +-
101
hw/arm/msf2-soc.c | 26 +-
102
hw/arm/virt.c | 20 +-
103
hw/arm/xilinx_zynq.c | 57 +++-
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hw/arm/xlnx-versal.c | 2 +
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hw/arm/xlnx-zcu102.c | 39 ++-
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hw/char/cadence_uart.c | 73 +++-
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hw/core/clock-vmstate.c | 25 ++
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hw/core/clock.c | 130 ++++++++
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hw/core/qdev-clock.c | 185 +++++++++++
110
hw/core/qdev.c | 12 +
111
hw/dma/xlnx-zdma.c | 25 +-
112
hw/intc/arm_gicv3_kvm.c | 4 +-
113
hw/misc/zynq_slcr.c | 172 +++++++++-
114
hw/net/cadence_gem.c | 16 +-
115
hw/net/msf2-emac.c | 589 +++++++++++++++++++++++++++++++++
116
qdev-monitor.c | 9 +
117
target/arm/cpu.c | 19 +-
118
target/arm/cpu64.c | 8 +-
119
target/arm/helper.c | 17 +
120
target/arm/neon_helper.c | 24 --
121
target/arm/translate-a64.c | 64 +---
122
target/arm/translate.c | 256 ++++++++++++--
123
target/arm/vec_helper.c | 25 ++
124
MAINTAINERS | 2 +
125
docs/devel/clocks.rst | 391 ++++++++++++++++++++++
126
docs/devel/index.rst | 1 +
127
hw/char/trace-events | 3 +
128
hw/core/trace-events | 7 +
129
tests/acceptance/boot_linux_console.py | 15 +-
130
45 files changed, 2533 insertions(+), 193 deletions(-)
131
create mode 100644 include/hw/clock.h
132
create mode 100644 include/hw/net/msf2-emac.h
133
create mode 100644 include/hw/qdev-clock.h
134
create mode 100644 hw/core/clock-vmstate.c
135
create mode 100644 hw/core/clock.c
136
create mode 100644 hw/core/qdev-clock.c
137
create mode 100644 hw/net/msf2-emac.c
138
create mode 100644 docs/devel/clocks.rst
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