[PULL 00/31] target-arm queue
[PULL 00/72] target-arm queue
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First arm pullreq of the 5.1 cycle; mostly bugfixes and some
1
First arm pullreq of the cycle; this is mostly my softfloat NaN
2
cleanup patches. The new clock modelling framework is the big
2
handling series. (Lots more in my to-review queue, but I don't
3
thing here.
3
like pullreqs growing too close to a hundred patches at a time :-))
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4
5
thanks
5
-- PMM
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-- PMM
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The following changes since commit 648db19685b7030aa558a4ddbd3a8e53d8c9a062:
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The following changes since commit 97f2796a3736ed37a1b85dc1c76a6c45b829dd17:
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Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-04-29' into staging (2020-04-29 15:07:33 +0100)
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Open 10.0 development tree (2024-12-10 17:41:17 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200430
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241211
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15
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for you to fetch changes up to 1267437e593e85498f9105b3bdab796630d2e83f:
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for you to fetch changes up to 1abe28d519239eea5cf9620bb13149423e5665f8:
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hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes (2020-04-30 11:52:29 +0100)
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MAINTAINERS: Add correct email address for Vikram Garhwal (2024-12-11 15:31:09 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
21
target-arm queue:
21
* xlnx-zdma: Fix endianness handling of descriptor loading
22
* hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs
22
* nrf51: Fix last GPIO CNF address
23
* fpu: Make muladd NaN handling runtime-selected, not compile-time
23
* gicv3: Use gicr_typer in arm_gicv3_icc_reset
24
* fpu: Make default NaN pattern runtime-selected, not compile-time
24
* msf2: Add EMAC block to SmartFusion2 SoC
25
* fpu: Minor NaN-related cleanups
25
* New clock modelling framework
26
* MAINTAINERS: email address updates
26
* hw/arm: versal: Setup the ADMA with 128bit bus-width
27
* Cadence: gem: fix wraparound in 64bit descriptors
28
* cadence_gem: clear RX control descriptor
29
* target/arm: Vectorize integer comparison vs zero
30
* hw/arm/virt: dt: add kaslr-seed property
31
* hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes
32
27
33
----------------------------------------------------------------
28
----------------------------------------------------------------
34
Cameron Esfahani (1):
29
Bernhard Beschow (5):
35
nrf51: Fix last GPIO CNF address
30
hw/net/lan9118: Extract lan9118_phy
31
hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
32
hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
33
hw/net/lan9118_phy: Reuse MII constants
34
hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
36
35
37
Damien Hedde (7):
36
Leif Lindholm (1):
38
hw/core/clock-vmstate: define a vmstate entry for clock state
37
MAINTAINERS: update email address for Leif Lindholm
39
qdev: add clock input&output support to devices.
40
qdev-clock: introduce an init array to ease the device construction
41
hw/misc/zynq_slcr: add clock generation for uarts
42
hw/char/cadence_uart: add clock support
43
hw/arm/xilinx_zynq: connect uart clocks to slcr
44
qdev-monitor: print the device's clock with info qtree
45
38
46
Edgar E. Iglesias (7):
39
Peter Maydell (54):
47
dma/xlnx-zdma: Fix descriptor loading (MEM) wrt endianness
40
fpu: handle raising Invalid for infzero in pick_nan_muladd
48
dma/xlnx-zdma: Fix descriptor loading (REG) wrt endianness
41
fpu: Check for default_nan_mode before calling pickNaNMulAdd
49
hw/arm: versal: Setup the ADMA with 128bit bus-width
42
softfloat: Allow runtime choice of inf * 0 + NaN result
50
device_tree: Allow name wildcards in qemu_fdt_node_path()
43
tests/fp: Explicitly set inf-zero-nan rule
51
device_tree: Constify compat in qemu_fdt_node_path()
44
target/arm: Set FloatInfZeroNaNRule explicitly
52
hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102
45
target/s390: Set FloatInfZeroNaNRule explicitly
53
hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes
46
target/ppc: Set FloatInfZeroNaNRule explicitly
47
target/mips: Set FloatInfZeroNaNRule explicitly
48
target/sparc: Set FloatInfZeroNaNRule explicitly
49
target/xtensa: Set FloatInfZeroNaNRule explicitly
50
target/x86: Set FloatInfZeroNaNRule explicitly
51
target/loongarch: Set FloatInfZeroNaNRule explicitly
52
target/hppa: Set FloatInfZeroNaNRule explicitly
53
softfloat: Pass have_snan to pickNaNMulAdd
54
softfloat: Allow runtime choice of NaN propagation for muladd
55
tests/fp: Explicitly set 3-NaN propagation rule
56
target/arm: Set Float3NaNPropRule explicitly
57
target/loongarch: Set Float3NaNPropRule explicitly
58
target/ppc: Set Float3NaNPropRule explicitly
59
target/s390x: Set Float3NaNPropRule explicitly
60
target/sparc: Set Float3NaNPropRule explicitly
61
target/mips: Set Float3NaNPropRule explicitly
62
target/xtensa: Set Float3NaNPropRule explicitly
63
target/i386: Set Float3NaNPropRule explicitly
64
target/hppa: Set Float3NaNPropRule explicitly
65
fpu: Remove use_first_nan field from float_status
66
target/m68k: Don't pass NULL float_status to floatx80_default_nan()
67
softfloat: Create floatx80 default NaN from parts64_default_nan
68
target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
69
target/m68k: In frem helper, initialize local float_status from env->fp_status
70
target/m68k: Init local float_status from env fp_status in gdb get/set reg
71
target/sparc: Initialize local scratch float_status from env->fp_status
72
target/ppc: Use env->fp_status in helper_compute_fprf functions
73
fpu: Allow runtime choice of default NaN value
74
tests/fp: Set default NaN pattern explicitly
75
target/microblaze: Set default NaN pattern explicitly
76
target/i386: Set default NaN pattern explicitly
77
target/hppa: Set default NaN pattern explicitly
78
target/alpha: Set default NaN pattern explicitly
79
target/arm: Set default NaN pattern explicitly
80
target/loongarch: Set default NaN pattern explicitly
81
target/m68k: Set default NaN pattern explicitly
82
target/mips: Set default NaN pattern explicitly
83
target/openrisc: Set default NaN pattern explicitly
84
target/ppc: Set default NaN pattern explicitly
85
target/sh4: Set default NaN pattern explicitly
86
target/rx: Set default NaN pattern explicitly
87
target/s390x: Set default NaN pattern explicitly
88
target/sparc: Set default NaN pattern explicitly
89
target/xtensa: Set default NaN pattern explicitly
90
target/hexagon: Set default NaN pattern explicitly
91
target/riscv: Set default NaN pattern explicitly
92
target/tricore: Set default NaN pattern explicitly
93
fpu: Remove default handling for dnan_pattern
54
94
55
Jerome Forissier (2):
95
Richard Henderson (11):
56
hw/arm/virt: dt: move creation of /secure-chosen to create_fdt()
96
target/arm: Copy entire float_status in is_ebf
57
hw/arm/virt: dt: add kaslr-seed property
97
softfloat: Inline pickNaNMulAdd
98
softfloat: Use goto for default nan case in pick_nan_muladd
99
softfloat: Remove which from parts_pick_nan_muladd
100
softfloat: Pad array size in pick_nan_muladd
101
softfloat: Move propagateFloatx80NaN to softfloat.c
102
softfloat: Use parts_pick_nan in propagateFloatx80NaN
103
softfloat: Inline pickNaN
104
softfloat: Share code between parts_pick_nan cases
105
softfloat: Sink frac_cmp in parts_pick_nan until needed
106
softfloat: Replace WHICH with RET in parts_pick_nan
58
107
59
Keqian Zhu (2):
108
Vikram Garhwal (1):
60
bugfix: Use gicr_typer in arm_gicv3_icc_reset
109
MAINTAINERS: Add correct email address for Vikram Garhwal
61
Typo: Correct the name of CPU hotplug memory region
62
110
63
Peter Maydell (2):
111
MAINTAINERS | 4 +-
64
hw/core/clock: introduce clock object
112
include/fpu/softfloat-helpers.h | 38 +++-
65
docs/clocks: add device's clock documentation
113
include/fpu/softfloat-types.h | 89 +++++++-
66
114
include/hw/net/imx_fec.h | 9 +-
67
Philippe Mathieu-Daudé (3):
115
include/hw/net/lan9118_phy.h | 37 ++++
68
target/arm: Restrict the Address Translate write operation to TCG accel
116
include/hw/net/mii.h | 6 +
69
target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]
117
target/mips/fpu_helper.h | 20 ++
70
target/arm/cpu: Update coding style to make checkpatch.pl happy
118
target/sparc/helper.h | 4 +-
71
119
fpu/softfloat.c | 19 ++
72
Ramon Fried (2):
120
hw/net/imx_fec.c | 146 ++------------
73
Cadence: gem: fix wraparound in 64bit descriptors
121
hw/net/lan9118.c | 137 ++-----------
74
net: cadence_gem: clear RX control descriptor
122
hw/net/lan9118_phy.c | 222 ++++++++++++++++++++
75
123
linux-user/arm/nwfpe/fpa11.c | 5 +
76
Richard Henderson (1):
124
target/alpha/cpu.c | 2 +
77
target/arm: Vectorize integer comparison vs zero
125
target/arm/cpu.c | 10 +
78
126
target/arm/tcg/vec_helper.c | 20 +-
79
Subbaraya Sundeep (3):
127
target/hexagon/cpu.c | 2 +
80
hw/net: Add Smartfusion2 emac block
128
target/hppa/fpu_helper.c | 12 ++
81
msf2: Add EMAC block to SmartFusion2 SoC
129
target/i386/tcg/fpu_helper.c | 12 ++
82
tests/boot_linux_console: Add ethernet test to SmartFusion2
130
target/loongarch/tcg/fpu_helper.c | 14 +-
83
131
target/m68k/cpu.c | 14 +-
84
Thomas Huth (1):
132
target/m68k/fpu_helper.c | 6 +-
85
target/arm: Make cpu_register() available for other files
133
target/m68k/helper.c | 6 +-
86
134
target/microblaze/cpu.c | 2 +
87
hw/core/Makefile.objs | 2 +
135
target/mips/msa.c | 10 +
88
hw/net/Makefile.objs | 1 +
136
target/openrisc/cpu.c | 2 +
89
tests/Makefile.include | 1 +
137
target/ppc/cpu_init.c | 19 ++
90
include/hw/arm/msf2-soc.h | 2 +
138
target/ppc/fpu_helper.c | 3 +-
91
include/hw/char/cadence_uart.h | 1 +
139
target/riscv/cpu.c | 2 +
92
include/hw/clock.h | 225 +++++++++++++
140
target/rx/cpu.c | 2 +
93
include/hw/gpio/nrf51_gpio.h | 2 +-
141
target/s390x/cpu.c | 5 +
94
include/hw/net/msf2-emac.h | 53 +++
142
target/sh4/cpu.c | 2 +
95
include/hw/qdev-clock.h | 159 +++++++++
143
target/sparc/cpu.c | 6 +
96
include/hw/qdev-core.h | 12 +
144
target/sparc/fop_helper.c | 8 +-
97
include/sysemu/device_tree.h | 5 +-
145
target/sparc/translate.c | 4 +-
98
target/arm/cpu-qom.h | 9 +-
146
target/tricore/helper.c | 2 +
99
target/arm/helper.h | 27 +-
147
target/xtensa/cpu.c | 4 +
100
target/arm/translate.h | 5 +
148
target/xtensa/fpu_helper.c | 3 +-
101
device_tree.c | 4 +-
149
tests/fp/fp-bench.c | 7 +
102
hw/acpi/cpu.c | 2 +-
150
tests/fp/fp-test-log2.c | 1 +
103
hw/arm/msf2-soc.c | 26 +-
151
tests/fp/fp-test.c | 7 +
104
hw/arm/virt.c | 20 +-
152
fpu/softfloat-parts.c.inc | 152 +++++++++++---
105
hw/arm/xilinx_zynq.c | 57 +++-
153
fpu/softfloat-specialize.c.inc | 412 ++------------------------------------
106
hw/arm/xlnx-versal.c | 2 +
154
.mailmap | 5 +-
107
hw/arm/xlnx-zcu102.c | 39 ++-
155
hw/net/Kconfig | 5 +
108
hw/char/cadence_uart.c | 73 +++-
156
hw/net/meson.build | 1 +
109
hw/core/clock-vmstate.c | 25 ++
157
hw/net/trace-events | 10 +-
110
hw/core/clock.c | 130 ++++++++
158
47 files changed, 778 insertions(+), 730 deletions(-)
111
hw/core/qdev-clock.c | 185 +++++++++++
159
create mode 100644 include/hw/net/lan9118_phy.h
112
hw/core/qdev.c | 12 +
160
create mode 100644 hw/net/lan9118_phy.c
113
hw/dma/xlnx-zdma.c | 25 +-
114
hw/intc/arm_gicv3_kvm.c | 4 +-
115
hw/misc/zynq_slcr.c | 172 +++++++++-
116
hw/net/cadence_gem.c | 16 +-
117
hw/net/msf2-emac.c | 589 +++++++++++++++++++++++++++++++++
118
qdev-monitor.c | 9 +
119
target/arm/cpu.c | 25 +-
120
target/arm/cpu64.c | 16 +-
121
target/arm/helper.c | 17 +
122
target/arm/neon_helper.c | 24 --
123
target/arm/translate-a64.c | 64 +---
124
target/arm/translate.c | 256 ++++++++++++--
125
target/arm/vec_helper.c | 25 ++
126
MAINTAINERS | 2 +
127
docs/devel/clocks.rst | 391 ++++++++++++++++++++++
128
docs/devel/index.rst | 1 +
129
hw/char/trace-events | 3 +
130
hw/core/trace-events | 7 +
131
tests/acceptance/boot_linux_console.py | 15 +-
132
45 files changed, 2538 insertions(+), 202 deletions(-)
133
create mode 100644 include/hw/clock.h
134
create mode 100644 include/hw/net/msf2-emac.h
135
create mode 100644 include/hw/qdev-clock.h
136
create mode 100644 hw/core/clock-vmstate.c
137
create mode 100644 hw/core/clock.c
138
create mode 100644 hw/core/qdev-clock.c
139
create mode 100644 hw/net/msf2-emac.c
140
create mode 100644 docs/devel/clocks.rst
141
diff view generated by jsdifflib
[PULL 09/31] hw/core/clock: introduce clock object
[PULL 01/72] hw/net/lan9118: Extract lan9118_phy
1
This object may be used to represent a clock inside a clock tree.
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
A clock may be connected to another clock so that it receives update,
3
A very similar implementation of the same device exists in imx_fec. Prepare for
4
through a callback, whenever the source/parent clock is updated.
4
a common implementation by extracting a device model into its own files.
5
5
6
Although only the root clock of a clock tree controls the values
6
Some migration state has been moved into the new device model which breaks
7
(represented as periods) of all clocks in tree, each clock holds
7
migration compatibility for the following machines:
8
a local state containing the current value so that it can be fetched
8
* smdkc210
9
independently. It will allows us to fullfill migration requirements
9
* realview-*
10
by migrating each clock independently of others.
10
* vexpress-*
11
* kzm
12
* mps2-*
11
13
12
This is based on the original work of Frederic Konrad.
14
While breaking migration ABI, fix the size of the MII registers to be 16 bit,
15
as defined by IEEE 802.3u.
13
16
14
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
17
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
18
Tested-by: Guenter Roeck <linux@roeck-us.net>
16
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 20200406135251.157596-2-damien.hedde@greensocs.com
20
Message-id: 20241102125724.532843-2-shentey@gmail.com
18
[PMM: Use uint64_t rather than unsigned long long in trace events;
19
the dtrace backend can't handle the latter]
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
22
---
22
hw/core/Makefile.objs | 1 +
23
include/hw/net/lan9118_phy.h | 37 ++++++++
23
include/hw/clock.h | 216 ++++++++++++++++++++++++++++++++++++++++++
24
hw/net/lan9118.c | 137 +++++-----------------------
24
hw/core/clock.c | 130 +++++++++++++++++++++++++
25
hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++
25
hw/core/trace-events | 7 ++
26
hw/net/Kconfig | 4 +
26
4 files changed, 354 insertions(+)
27
hw/net/meson.build | 1 +
27
create mode 100644 include/hw/clock.h
28
5 files changed, 233 insertions(+), 115 deletions(-)
28
create mode 100644 hw/core/clock.c
29
create mode 100644 include/hw/net/lan9118_phy.h
30
create mode 100644 hw/net/lan9118_phy.c
29
31
30
diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
32
diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/core/Makefile.objs
33
+++ b/hw/core/Makefile.objs
34
@@ -XXX,XX +XXX,XX @@ common-obj-y += hotplug.o
35
common-obj-y += vmstate-if.o
36
# irq.o needed for qdev GPIO handling:
37
common-obj-y += irq.o
38
+common-obj-y += clock.o
39
40
common-obj-$(CONFIG_SOFTMMU) += reset.o
41
common-obj-$(CONFIG_SOFTMMU) += qdev-fw.o
42
diff --git a/include/hw/clock.h b/include/hw/clock.h
43
new file mode 100644
33
new file mode 100644
44
index XXXXXXX..XXXXXXX
34
index XXXXXXX..XXXXXXX
45
--- /dev/null
35
--- /dev/null
46
+++ b/include/hw/clock.h
36
+++ b/include/hw/net/lan9118_phy.h
47
@@ -XXX,XX +XXX,XX @@
37
@@ -XXX,XX +XXX,XX @@
48
+/*
38
+/*
49
+ * Hardware Clocks
39
+ * SMSC LAN9118 PHY emulation
50
+ *
40
+ *
51
+ * Copyright GreenSocs 2016-2020
41
+ * Copyright (c) 2009 CodeSourcery, LLC.
52
+ *
42
+ * Written by Paul Brook
53
+ * Authors:
54
+ * Frederic Konrad
55
+ * Damien Hedde
56
+ *
43
+ *
57
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
44
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
58
+ * See the COPYING file in the top-level directory.
45
+ * See the COPYING file in the top-level directory.
59
+ */
46
+ */
60
+
47
+
61
+#ifndef QEMU_HW_CLOCK_H
48
+#ifndef HW_NET_LAN9118_PHY_H
62
+#define QEMU_HW_CLOCK_H
49
+#define HW_NET_LAN9118_PHY_H
63
+
50
+
64
+#include "qom/object.h"
51
+#include "qom/object.h"
65
+#include "qemu/queue.h"
52
+#include "hw/sysbus.h"
66
+
53
+
67
+#define TYPE_CLOCK "clock"
54
+#define TYPE_LAN9118_PHY "lan9118-phy"
68
+#define CLOCK(obj) OBJECT_CHECK(Clock, (obj), TYPE_CLOCK)
55
+OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY)
69
+
56
+
70
+typedef void ClockCallback(void *opaque);
57
+typedef struct Lan9118PhyState {
71
+
58
+ SysBusDevice parent_obj;
72
+/*
59
+
73
+ * clock store a value representing the clock's period in 2^-32ns unit.
60
+ uint16_t status;
74
+ * It can represent:
61
+ uint16_t control;
75
+ * + periods from 2^-32ns up to 4seconds
62
+ uint16_t advertise;
76
+ * + frequency from ~0.25Hz 2e10Ghz
63
+ uint16_t ints;
77
+ * Resolution of frequency representation decreases with frequency:
64
+ uint16_t int_mask;
78
+ * + at 100MHz, resolution is ~2mHz
65
+ qemu_irq irq;
79
+ * + at 1Ghz, resolution is ~0.2Hz
66
+ bool link_down;
80
+ * + at 10Ghz, resolution is ~20Hz
67
+} Lan9118PhyState;
81
+ */
68
+
82
+#define CLOCK_SECOND (1000000000llu << 32)
69
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down);
83
+
70
+void lan9118_phy_reset(Lan9118PhyState *s);
84
+/*
71
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg);
85
+ * macro helpers to convert to hertz / nanosecond
72
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val);
86
+ */
73
+
87
+#define CLOCK_PERIOD_FROM_NS(ns) ((ns) * (CLOCK_SECOND / 1000000000llu))
74
+#endif
88
+#define CLOCK_PERIOD_TO_NS(per) ((per) / (CLOCK_SECOND / 1000000000llu))
75
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
89
+#define CLOCK_PERIOD_FROM_HZ(hz) (((hz) != 0) ? CLOCK_SECOND / (hz) : 0u)
76
index XXXXXXX..XXXXXXX 100644
90
+#define CLOCK_PERIOD_TO_HZ(per) (((per) != 0) ? CLOCK_SECOND / (per) : 0u)
77
--- a/hw/net/lan9118.c
91
+
78
+++ b/hw/net/lan9118.c
92
+/**
79
@@ -XXX,XX +XXX,XX @@
93
+ * Clock:
80
#include "net/net.h"
94
+ * @parent_obj: parent class
81
#include "net/eth.h"
95
+ * @period: unsigned integer representing the period of the clock
82
#include "hw/irq.h"
96
+ * @canonical_path: clock path string cache (used for trace purpose)
83
+#include "hw/net/lan9118_phy.h"
97
+ * @callback: called when clock changes
84
#include "hw/net/lan9118.h"
98
+ * @callback_opaque: argument for @callback
85
#include "hw/ptimer.h"
99
+ * @source: source (or parent in clock tree) of the clock
86
#include "hw/qdev-properties.h"
100
+ * @children: list of clocks connected to this one (it is their source)
87
@@ -XXX,XX +XXX,XX @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
101
+ * @sibling: structure used to form a clock list
88
#define MAC_CR_RXEN 0x00000004
102
+ */
89
#define MAC_CR_RESERVED 0x7f404213
103
+
90
104
+typedef struct Clock Clock;
91
-#define PHY_INT_ENERGYON 0x80
105
+
92
-#define PHY_INT_AUTONEG_COMPLETE 0x40
106
+struct Clock {
93
-#define PHY_INT_FAULT 0x20
107
+ /*< private >*/
94
-#define PHY_INT_DOWN 0x10
108
+ Object parent_obj;
95
-#define PHY_INT_AUTONEG_LP 0x08
109
+
96
-#define PHY_INT_PARFAULT 0x04
110
+ /* all fields are private and should not be modified directly */
97
-#define PHY_INT_AUTONEG_PAGE 0x02
111
+
98
-
112
+ /* fields */
99
#define GPT_TIMER_EN 0x20000000
113
+ uint64_t period;
100
114
+ char *canonical_path;
101
/*
115
+ ClockCallback *callback;
102
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
116
+ void *callback_opaque;
103
uint32_t mac_mii_data;
117
+
104
uint32_t mac_flow;
118
+ /* Clocks are organized in a clock tree */
105
119
+ Clock *source;
106
- uint32_t phy_status;
120
+ QLIST_HEAD(, Clock) children;
107
- uint32_t phy_control;
121
+ QLIST_ENTRY(Clock) sibling;
108
- uint32_t phy_advertise;
122
+};
109
- uint32_t phy_int;
123
+
110
- uint32_t phy_int_mask;
124
+/**
111
+ Lan9118PhyState mii;
125
+ * clock_setup_canonical_path:
112
+ IRQState mii_irq;
126
+ * @clk: clock
113
127
+ *
114
int32_t eeprom_writable;
128
+ * compute the canonical path of the clock (used by log messages)
115
uint8_t eeprom[128];
129
+ */
116
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
130
+void clock_setup_canonical_path(Clock *clk);
117
131
+
118
static const VMStateDescription vmstate_lan9118 = {
132
+/**
119
.name = "lan9118",
133
+ * clock_set_callback:
120
- .version_id = 2,
134
+ * @clk: the clock to register the callback into
121
- .minimum_version_id = 1,
135
+ * @cb: the callback function
122
+ .version_id = 3,
136
+ * @opaque: the argument to the callback
123
+ .minimum_version_id = 3,
137
+ *
124
.fields = (const VMStateField[]) {
138
+ * Register a callback called on every clock update.
125
VMSTATE_PTIMER(timer, lan9118_state),
139
+ */
126
VMSTATE_UINT32(irq_cfg, lan9118_state),
140
+void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque);
127
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118 = {
141
+
128
VMSTATE_UINT32(mac_mii_acc, lan9118_state),
142
+/**
129
VMSTATE_UINT32(mac_mii_data, lan9118_state),
143
+ * clock_clear_callback:
130
VMSTATE_UINT32(mac_flow, lan9118_state),
144
+ * @clk: the clock to delete the callback from
131
- VMSTATE_UINT32(phy_status, lan9118_state),
145
+ *
132
- VMSTATE_UINT32(phy_control, lan9118_state),
146
+ * Unregister the callback registered with clock_set_callback.
133
- VMSTATE_UINT32(phy_advertise, lan9118_state),
147
+ */
134
- VMSTATE_UINT32(phy_int, lan9118_state),
148
+void clock_clear_callback(Clock *clk);
135
- VMSTATE_UINT32(phy_int_mask, lan9118_state),
149
+
136
VMSTATE_INT32(eeprom_writable, lan9118_state),
150
+/**
137
VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
151
+ * clock_set_source:
138
VMSTATE_INT32(tx_fifo_size, lan9118_state),
152
+ * @clk: the clock.
139
@@ -XXX,XX +XXX,XX @@ static void lan9118_reload_eeprom(lan9118_state *s)
153
+ * @src: the source clock
140
lan9118_mac_changed(s);
154
+ *
141
}
155
+ * Setup @src as the clock source of @clk. The current @src period
142
156
+ * value is also copied to @clk and its subtree but no callback is
143
-static void phy_update_irq(lan9118_state *s)
157
+ * called.
144
+static void lan9118_update_irq(void *opaque, int n, int level)
158
+ * Further @src update will be propagated to @clk and its subtree.
145
{
159
+ */
146
- if (s->phy_int & s->phy_int_mask) {
160
+void clock_set_source(Clock *clk, Clock *src);
147
+ lan9118_state *s = opaque;
161
+
148
+
162
+/**
149
+ if (level) {
163
+ * clock_set:
150
s->int_sts |= PHY_INT;
164
+ * @clk: the clock to initialize.
151
} else {
165
+ * @value: the clock's value, 0 means unclocked
152
s->int_sts &= ~PHY_INT;
166
+ *
153
@@ -XXX,XX +XXX,XX @@ static void phy_update_irq(lan9118_state *s)
167
+ * Set the local cached period value of @clk to @value.
154
lan9118_update(s);
168
+ */
155
}
169
+void clock_set(Clock *clk, uint64_t value);
156
170
+
157
-static void phy_update_link(lan9118_state *s)
171
+static inline void clock_set_hz(Clock *clk, unsigned hz)
158
-{
172
+{
159
- /* Autonegotiation status mirrors link status. */
173
+ clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz));
160
- if (qemu_get_queue(s->nic)->link_down) {
174
+}
161
- s->phy_status &= ~0x0024;
175
+
162
- s->phy_int |= PHY_INT_DOWN;
176
+static inline void clock_set_ns(Clock *clk, unsigned ns)
163
- } else {
177
+{
164
- s->phy_status |= 0x0024;
178
+ clock_set(clk, CLOCK_PERIOD_FROM_NS(ns));
165
- s->phy_int |= PHY_INT_ENERGYON;
179
+}
166
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
180
+
167
- }
181
+/**
168
- phy_update_irq(s);
182
+ * clock_propagate:
169
-}
183
+ * @clk: the clock
170
-
184
+ *
171
static void lan9118_set_link(NetClientState *nc)
185
+ * Propagate the clock period that has been previously configured using
172
{
186
+ * @clock_set(). This will update recursively all connected clocks.
173
- phy_update_link(qemu_get_nic_opaque(nc));
187
+ * It is an error to call this function on a clock which has a source.
174
-}
188
+ * Note: this function must not be called during device inititialization
175
-
189
+ * or migration.
176
-static void phy_reset(lan9118_state *s)
190
+ */
177
-{
191
+void clock_propagate(Clock *clk);
178
- s->phy_status = 0x7809;
192
+
179
- s->phy_control = 0x3000;
193
+/**
180
- s->phy_advertise = 0x01e1;
194
+ * clock_update:
181
- s->phy_int_mask = 0;
195
+ * @clk: the clock to update.
182
- s->phy_int = 0;
196
+ * @value: the new clock's value, 0 means unclocked
183
- phy_update_link(s);
197
+ *
184
+ lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii,
198
+ * Update the @clk to the new @value. All connected clocks will be informed
185
+ nc->link_down);
199
+ * of this update. This is equivalent to call @clock_set() then
186
}
200
+ * @clock_propagate().
187
201
+ */
188
static void lan9118_reset(DeviceState *d)
202
+static inline void clock_update(Clock *clk, uint64_t value)
189
@@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d)
203
+{
190
s->read_word_n = 0;
204
+ clock_set(clk, value);
191
s->write_word_n = 0;
205
+ clock_propagate(clk);
192
206
+}
193
- phy_reset(s);
207
+
194
-
208
+static inline void clock_update_hz(Clock *clk, unsigned hz)
195
s->eeprom_writable = 0;
209
+{
196
lan9118_reload_eeprom(s);
210
+ clock_update(clk, CLOCK_PERIOD_FROM_HZ(hz));
197
}
211
+}
198
@@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s)
212
+
199
uint32_t status;
213
+static inline void clock_update_ns(Clock *clk, unsigned ns)
200
214
+{
201
/* FIXME: Honor TX disable, and allow queueing of packets. */
215
+ clock_update(clk, CLOCK_PERIOD_FROM_NS(ns));
202
- if (s->phy_control & 0x4000) {
216
+}
203
+ if (s->mii.control & 0x4000) {
217
+
204
/* This assumes the receive routine doesn't touch the VLANClient. */
218
+/**
205
qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
219
+ * clock_get:
206
} else {
220
+ * @clk: the clk to fetch the clock
207
@@ -XXX,XX +XXX,XX @@ static void tx_fifo_push(lan9118_state *s, uint32_t val)
221
+ *
208
}
222
+ * @return: the current period.
209
}
223
+ */
210
224
+static inline uint64_t clock_get(const Clock *clk)
211
-static uint32_t do_phy_read(lan9118_state *s, int reg)
225
+{
212
-{
226
+ return clk->period;
213
- uint32_t val;
227
+}
214
-
228
+
215
- switch (reg) {
229
+static inline unsigned clock_get_hz(Clock *clk)
216
- case 0: /* Basic Control */
230
+{
217
- return s->phy_control;
231
+ return CLOCK_PERIOD_TO_HZ(clock_get(clk));
218
- case 1: /* Basic Status */
232
+}
219
- return s->phy_status;
233
+
220
- case 2: /* ID1 */
234
+static inline unsigned clock_get_ns(Clock *clk)
221
- return 0x0007;
235
+{
222
- case 3: /* ID2 */
236
+ return CLOCK_PERIOD_TO_NS(clock_get(clk));
223
- return 0xc0d1;
237
+}
224
- case 4: /* Auto-neg advertisement */
238
+
225
- return s->phy_advertise;
239
+/**
226
- case 5: /* Auto-neg Link Partner Ability */
240
+ * clock_is_enabled:
227
- return 0x0f71;
241
+ * @clk: a clock
228
- case 6: /* Auto-neg Expansion */
242
+ *
229
- return 1;
243
+ * @return: true if the clock is running.
230
- /* TODO 17, 18, 27, 29, 30, 31 */
244
+ */
231
- case 29: /* Interrupt source. */
245
+static inline bool clock_is_enabled(const Clock *clk)
232
- val = s->phy_int;
246
+{
233
- s->phy_int = 0;
247
+ return clock_get(clk) != 0;
234
- phy_update_irq(s);
248
+}
235
- return val;
249
+
236
- case 30: /* Interrupt mask */
250
+static inline void clock_init(Clock *clk, uint64_t value)
237
- return s->phy_int_mask;
251
+{
238
- default:
252
+ clock_set(clk, value);
239
- qemu_log_mask(LOG_GUEST_ERROR,
253
+}
240
- "do_phy_read: PHY read reg %d\n", reg);
254
+static inline void clock_init_hz(Clock *clk, uint64_t value)
241
- return 0;
255
+{
242
- }
256
+ clock_set_hz(clk, value);
243
-}
257
+}
244
-
258
+static inline void clock_init_ns(Clock *clk, uint64_t value)
245
-static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
259
+{
246
-{
260
+ clock_set_ns(clk, value);
247
- switch (reg) {
261
+}
248
- case 0: /* Basic Control */
262
+
249
- if (val & 0x8000) {
263
+#endif /* QEMU_HW_CLOCK_H */
250
- phy_reset(s);
264
diff --git a/hw/core/clock.c b/hw/core/clock.c
251
- break;
252
- }
253
- s->phy_control = val & 0x7980;
254
- /* Complete autonegotiation immediately. */
255
- if (val & 0x1000) {
256
- s->phy_status |= 0x0020;
257
- }
258
- break;
259
- case 4: /* Auto-neg advertisement */
260
- s->phy_advertise = (val & 0x2d7f) | 0x80;
261
- break;
262
- /* TODO 17, 18, 27, 31 */
263
- case 30: /* Interrupt mask */
264
- s->phy_int_mask = val & 0xff;
265
- phy_update_irq(s);
266
- break;
267
- default:
268
- qemu_log_mask(LOG_GUEST_ERROR,
269
- "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
270
- }
271
-}
272
-
273
static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
274
{
275
switch (reg) {
276
@@ -XXX,XX +XXX,XX @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
277
if (val & 2) {
278
DPRINTF("PHY write %d = 0x%04x\n",
279
(val >> 6) & 0x1f, s->mac_mii_data);
280
- do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
281
+ lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data);
282
} else {
283
- s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
284
+ s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f);
285
DPRINTF("PHY read %d = 0x%04x\n",
286
(val >> 6) & 0x1f, s->mac_mii_data);
287
}
288
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
289
break;
290
case CSR_PMT_CTRL:
291
if (val & 0x400) {
292
- phy_reset(s);
293
+ lan9118_phy_reset(&s->mii);
294
}
295
s->pmt_ctrl &= ~0x34e;
296
s->pmt_ctrl |= (val & 0x34e);
297
@@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp)
298
const MemoryRegionOps *mem_ops =
299
s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops;
300
301
+ qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0);
302
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
303
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
304
+ return;
305
+ }
306
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
307
+
308
memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s,
309
"lan9118-mmio", 0x100);
310
sysbus_init_mmio(sbd, &s->mmio);
311
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
265
new file mode 100644
312
new file mode 100644
266
index XXXXXXX..XXXXXXX
313
index XXXXXXX..XXXXXXX
267
--- /dev/null
314
--- /dev/null
268
+++ b/hw/core/clock.c
315
+++ b/hw/net/lan9118_phy.c
269
@@ -XXX,XX +XXX,XX @@
316
@@ -XXX,XX +XXX,XX @@
270
+/*
317
+/*
271
+ * Hardware Clocks
318
+ * SMSC LAN9118 PHY emulation
272
+ *
319
+ *
273
+ * Copyright GreenSocs 2016-2020
320
+ * Copyright (c) 2009 CodeSourcery, LLC.
321
+ * Written by Paul Brook
274
+ *
322
+ *
275
+ * Authors:
323
+ * This code is licensed under the GNU GPL v2
276
+ * Frederic Konrad
277
+ * Damien Hedde
278
+ *
324
+ *
279
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
325
+ * Contributions after 2012-01-13 are licensed under the terms of the
280
+ * See the COPYING file in the top-level directory.
326
+ * GNU GPL, version 2 or (at your option) any later version.
281
+ */
327
+ */
282
+
328
+
283
+#include "qemu/osdep.h"
329
+#include "qemu/osdep.h"
284
+#include "hw/clock.h"
330
+#include "hw/net/lan9118_phy.h"
285
+#include "trace.h"
331
+#include "hw/irq.h"
286
+
332
+#include "hw/resettable.h"
287
+#define CLOCK_PATH(_clk) (_clk->canonical_path)
333
+#include "migration/vmstate.h"
288
+
334
+#include "qemu/log.h"
289
+void clock_setup_canonical_path(Clock *clk)
335
+
290
+{
336
+#define PHY_INT_ENERGYON (1 << 7)
291
+ g_free(clk->canonical_path);
337
+#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
292
+ clk->canonical_path = object_get_canonical_path(OBJECT(clk));
338
+#define PHY_INT_FAULT (1 << 5)
293
+}
339
+#define PHY_INT_DOWN (1 << 4)
294
+
340
+#define PHY_INT_AUTONEG_LP (1 << 3)
295
+void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque)
341
+#define PHY_INT_PARFAULT (1 << 2)
296
+{
342
+#define PHY_INT_AUTONEG_PAGE (1 << 1)
297
+ clk->callback = cb;
343
+
298
+ clk->callback_opaque = opaque;
344
+static void lan9118_phy_update_irq(Lan9118PhyState *s)
299
+}
345
+{
300
+
346
+ qemu_set_irq(s->irq, !!(s->ints & s->int_mask));
301
+void clock_clear_callback(Clock *clk)
347
+}
302
+{
348
+
303
+ clock_set_callback(clk, NULL, NULL);
349
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
304
+}
350
+{
305
+
351
+ uint16_t val;
306
+void clock_set(Clock *clk, uint64_t period)
352
+
307
+{
353
+ switch (reg) {
308
+ trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_NS(clk->period),
354
+ case 0: /* Basic Control */
309
+ CLOCK_PERIOD_TO_NS(period));
355
+ return s->control;
310
+ clk->period = period;
356
+ case 1: /* Basic Status */
311
+}
357
+ return s->status;
312
+
358
+ case 2: /* ID1 */
313
+static void clock_propagate_period(Clock *clk, bool call_callbacks)
359
+ return 0x0007;
314
+{
360
+ case 3: /* ID2 */
315
+ Clock *child;
361
+ return 0xc0d1;
316
+
362
+ case 4: /* Auto-neg advertisement */
317
+ QLIST_FOREACH(child, &clk->children, sibling) {
363
+ return s->advertise;
318
+ if (child->period != clk->period) {
364
+ case 5: /* Auto-neg Link Partner Ability */
319
+ child->period = clk->period;
365
+ return 0x0f71;
320
+ trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk),
366
+ case 6: /* Auto-neg Expansion */
321
+ CLOCK_PERIOD_TO_NS(clk->period),
367
+ return 1;
322
+ call_callbacks);
368
+ /* TODO 17, 18, 27, 29, 30, 31 */
323
+ if (call_callbacks && child->callback) {
369
+ case 29: /* Interrupt source. */
324
+ child->callback(child->callback_opaque);
370
+ val = s->ints;
325
+ }
371
+ s->ints = 0;
326
+ clock_propagate_period(child, call_callbacks);
372
+ lan9118_phy_update_irq(s);
373
+ return val;
374
+ case 30: /* Interrupt mask */
375
+ return s->int_mask;
376
+ default:
377
+ qemu_log_mask(LOG_GUEST_ERROR,
378
+ "lan9118_phy_read: PHY read reg %d\n", reg);
379
+ return 0;
380
+ }
381
+}
382
+
383
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
384
+{
385
+ switch (reg) {
386
+ case 0: /* Basic Control */
387
+ if (val & 0x8000) {
388
+ lan9118_phy_reset(s);
389
+ break;
327
+ }
390
+ }
391
+ s->control = val & 0x7980;
392
+ /* Complete autonegotiation immediately. */
393
+ if (val & 0x1000) {
394
+ s->status |= 0x0020;
395
+ }
396
+ break;
397
+ case 4: /* Auto-neg advertisement */
398
+ s->advertise = (val & 0x2d7f) | 0x80;
399
+ break;
400
+ /* TODO 17, 18, 27, 31 */
401
+ case 30: /* Interrupt mask */
402
+ s->int_mask = val & 0xff;
403
+ lan9118_phy_update_irq(s);
404
+ break;
405
+ default:
406
+ qemu_log_mask(LOG_GUEST_ERROR,
407
+ "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
328
+ }
408
+ }
329
+}
409
+}
330
+
410
+
331
+void clock_propagate(Clock *clk)
411
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
332
+{
412
+{
333
+ assert(clk->source == NULL);
413
+ s->link_down = link_down;
334
+ trace_clock_propagate(CLOCK_PATH(clk));
414
+
335
+ clock_propagate_period(clk, true);
415
+ /* Autonegotiation status mirrors link status. */
336
+}
416
+ if (link_down) {
337
+
417
+ s->status &= ~0x0024;
338
+void clock_set_source(Clock *clk, Clock *src)
418
+ s->ints |= PHY_INT_DOWN;
339
+{
419
+ } else {
340
+ /* changing clock source is not supported */
420
+ s->status |= 0x0024;
341
+ assert(!clk->source);
421
+ s->ints |= PHY_INT_ENERGYON;
342
+
422
+ s->ints |= PHY_INT_AUTONEG_COMPLETE;
343
+ trace_clock_set_source(CLOCK_PATH(clk), CLOCK_PATH(src));
344
+
345
+ clk->period = src->period;
346
+ QLIST_INSERT_HEAD(&src->children, clk, sibling);
347
+ clk->source = src;
348
+ clock_propagate_period(clk, false);
349
+}
350
+
351
+static void clock_disconnect(Clock *clk)
352
+{
353
+ if (clk->source == NULL) {
354
+ return;
355
+ }
423
+ }
356
+
424
+ lan9118_phy_update_irq(s);
357
+ trace_clock_disconnect(CLOCK_PATH(clk));
425
+}
358
+
426
+
359
+ clk->source = NULL;
427
+void lan9118_phy_reset(Lan9118PhyState *s)
360
+ QLIST_REMOVE(clk, sibling);
428
+{
361
+}
429
+ s->control = 0x3000;
362
+
430
+ s->status = 0x7809;
363
+static void clock_initfn(Object *obj)
431
+ s->advertise = 0x01e1;
364
+{
432
+ s->int_mask = 0;
365
+ Clock *clk = CLOCK(obj);
433
+ s->ints = 0;
366
+
434
+ lan9118_phy_update_link(s, s->link_down);
367
+ QLIST_INIT(&clk->children);
435
+}
368
+}
436
+
369
+
437
+static void lan9118_phy_reset_hold(Object *obj, ResetType type)
370
+static void clock_finalizefn(Object *obj)
438
+{
371
+{
439
+ Lan9118PhyState *s = LAN9118_PHY(obj);
372
+ Clock *clk = CLOCK(obj);
440
+
373
+ Clock *child, *next;
441
+ lan9118_phy_reset(s);
374
+
442
+}
375
+ /* clear our list of children */
443
+
376
+ QLIST_FOREACH_SAFE(child, &clk->children, sibling, next) {
444
+static void lan9118_phy_init(Object *obj)
377
+ clock_disconnect(child);
445
+{
446
+ Lan9118PhyState *s = LAN9118_PHY(obj);
447
+
448
+ qdev_init_gpio_out(DEVICE(s), &s->irq, 1);
449
+}
450
+
451
+static const VMStateDescription vmstate_lan9118_phy = {
452
+ .name = "lan9118-phy",
453
+ .version_id = 1,
454
+ .minimum_version_id = 1,
455
+ .fields = (const VMStateField[]) {
456
+ VMSTATE_UINT16(control, Lan9118PhyState),
457
+ VMSTATE_UINT16(status, Lan9118PhyState),
458
+ VMSTATE_UINT16(advertise, Lan9118PhyState),
459
+ VMSTATE_UINT16(ints, Lan9118PhyState),
460
+ VMSTATE_UINT16(int_mask, Lan9118PhyState),
461
+ VMSTATE_BOOL(link_down, Lan9118PhyState),
462
+ VMSTATE_END_OF_LIST()
378
+ }
463
+ }
379
+
380
+ /* remove us from source's children list */
381
+ clock_disconnect(clk);
382
+
383
+ g_free(clk->canonical_path);
384
+}
385
+
386
+static const TypeInfo clock_info = {
387
+ .name = TYPE_CLOCK,
388
+ .parent = TYPE_OBJECT,
389
+ .instance_size = sizeof(Clock),
390
+ .instance_init = clock_initfn,
391
+ .instance_finalize = clock_finalizefn,
392
+};
464
+};
393
+
465
+
394
+static void clock_register_types(void)
466
+static void lan9118_phy_class_init(ObjectClass *klass, void *data)
395
+{
467
+{
396
+ type_register_static(&clock_info);
468
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
397
+}
469
+ DeviceClass *dc = DEVICE_CLASS(klass);
398
+
470
+
399
+type_init(clock_register_types)
471
+ rc->phases.hold = lan9118_phy_reset_hold;
400
diff --git a/hw/core/trace-events b/hw/core/trace-events
472
+ dc->vmsd = &vmstate_lan9118_phy;
473
+}
474
+
475
+static const TypeInfo types[] = {
476
+ {
477
+ .name = TYPE_LAN9118_PHY,
478
+ .parent = TYPE_SYS_BUS_DEVICE,
479
+ .instance_size = sizeof(Lan9118PhyState),
480
+ .instance_init = lan9118_phy_init,
481
+ .class_init = lan9118_phy_class_init,
482
+ }
483
+};
484
+
485
+DEFINE_TYPES(types)
486
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
401
index XXXXXXX..XXXXXXX 100644
487
index XXXXXXX..XXXXXXX 100644
402
--- a/hw/core/trace-events
488
--- a/hw/net/Kconfig
403
+++ b/hw/core/trace-events
489
+++ b/hw/net/Kconfig
404
@@ -XXX,XX +XXX,XX @@ resettable_phase_exit_begin(void *obj, const char *objtype, unsigned count, int
490
@@ -XXX,XX +XXX,XX @@ config VMXNET3_PCI
405
resettable_phase_exit_exec(void *obj, const char *objtype, int has_method) "obj=%p(%s) method=%d"
491
config SMC91C111
406
resettable_phase_exit_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d"
492
bool
407
resettable_transitional_function(void *obj, const char *objtype) "obj=%p(%s)"
493
408
+
494
+config LAN9118_PHY
409
+# clock.c
495
+ bool
410
+clock_set_source(const char *clk, const char *src) "'%s', src='%s'"
496
+
411
+clock_disconnect(const char *clk) "'%s'"
497
config LAN9118
412
+clock_set(const char *clk, uint64_t old, uint64_t new) "'%s', ns=%"PRIu64"->%"PRIu64
498
bool
413
+clock_propagate(const char *clk) "'%s'"
499
+ select LAN9118_PHY
414
+clock_update(const char *clk, const char *src, uint64_t val, int cb) "'%s', src='%s', ns=%"PRIu64", cb=%d"
500
select PTIMER
501
502
config NE2000_ISA
503
diff --git a/hw/net/meson.build b/hw/net/meson.build
504
index XXXXXXX..XXXXXXX 100644
505
--- a/hw/net/meson.build
506
+++ b/hw/net/meson.build
507
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c'))
508
509
system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c'))
510
system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c'))
511
+system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c'))
512
system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c'))
513
system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c'))
514
system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c'))
415
--
515
--
416
2.20.1
516
2.34.1
417
418
diff view generated by jsdifflib
[PULL 14/31] hw/misc/zynq_slcr: add clock generation for uarts
[PULL 02/72] hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
1
From: Damien Hedde <damien.hedde@greensocs.com>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Add some clocks to zynq_slcr
3
imx_fec models the same PHY as lan9118_phy. The code is almost the same with
4
+ the main input clock (ps_clk)
4
imx_fec having more logging and tracing. Merge these improvements into
5
+ the reference clock outputs for each uart (uart0 & 1)
5
lan9118_phy and reuse in imx_fec to fix the code duplication.
6
6
7
This commit also transitional the slcr to multi-phase reset as it is
7
Some migration state how resides in the new device model which breaks migration
8
required to initialize the clocks correctly.
8
compatibility for the following machines:
9
* imx25-pdk
10
* sabrelite
11
* mcimx7d-sabre
12
* mcimx6ul-evk
9
13
10
The clock frequencies are computed using the internal pll & uart configuration
14
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
11
registers and the input ps_clk frequency.
15
Tested-by: Guenter Roeck <linux@roeck-us.net>
12
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
17
Message-id: 20241102125724.532843-3-shentey@gmail.com
14
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
15
Acked-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 20200406135251.157596-7-damien.hedde@greensocs.com
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
---
19
hw/misc/zynq_slcr.c | 172 ++++++++++++++++++++++++++++++++++++++++++--
20
include/hw/net/imx_fec.h | 9 ++-
20
1 file changed, 168 insertions(+), 4 deletions(-)
21
hw/net/imx_fec.c | 146 ++++-----------------------------------
22
hw/net/lan9118_phy.c | 82 ++++++++++++++++------
23
hw/net/Kconfig | 1 +
24
hw/net/trace-events | 10 +--
25
5 files changed, 85 insertions(+), 163 deletions(-)
21
26
22
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
27
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
23
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/misc/zynq_slcr.c
29
--- a/include/hw/net/imx_fec.h
25
+++ b/hw/misc/zynq_slcr.c
30
+++ b/include/hw/net/imx_fec.h
31
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC)
32
#define TYPE_IMX_ENET "imx.enet"
33
34
#include "hw/sysbus.h"
35
+#include "hw/net/lan9118_phy.h"
36
+#include "hw/irq.h"
37
#include "net/net.h"
38
39
#define ENET_EIR 1
40
@@ -XXX,XX +XXX,XX @@ struct IMXFECState {
41
uint32_t tx_descriptor[ENET_TX_RING_NUM];
42
uint32_t tx_ring_num;
43
44
- uint32_t phy_status;
45
- uint32_t phy_control;
46
- uint32_t phy_advertise;
47
- uint32_t phy_int;
48
- uint32_t phy_int_mask;
49
+ Lan9118PhyState mii;
50
+ IRQState mii_irq;
51
uint32_t phy_num;
52
bool phy_connected;
53
struct IMXFECState *phy_consumer;
54
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/net/imx_fec.c
57
+++ b/hw/net/imx_fec.c
58
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth_txdescs = {
59
60
static const VMStateDescription vmstate_imx_eth = {
61
.name = TYPE_IMX_FEC,
62
- .version_id = 2,
63
- .minimum_version_id = 2,
64
+ .version_id = 3,
65
+ .minimum_version_id = 3,
66
.fields = (const VMStateField[]) {
67
VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX),
68
VMSTATE_UINT32(rx_descriptor, IMXFECState),
69
VMSTATE_UINT32(tx_descriptor[0], IMXFECState),
70
- VMSTATE_UINT32(phy_status, IMXFECState),
71
- VMSTATE_UINT32(phy_control, IMXFECState),
72
- VMSTATE_UINT32(phy_advertise, IMXFECState),
73
- VMSTATE_UINT32(phy_int, IMXFECState),
74
- VMSTATE_UINT32(phy_int_mask, IMXFECState),
75
VMSTATE_END_OF_LIST()
76
},
77
.subsections = (const VMStateDescription * const []) {
78
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth = {
79
},
80
};
81
82
-#define PHY_INT_ENERGYON (1 << 7)
83
-#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
84
-#define PHY_INT_FAULT (1 << 5)
85
-#define PHY_INT_DOWN (1 << 4)
86
-#define PHY_INT_AUTONEG_LP (1 << 3)
87
-#define PHY_INT_PARFAULT (1 << 2)
88
-#define PHY_INT_AUTONEG_PAGE (1 << 1)
89
-
90
static void imx_eth_update(IMXFECState *s);
91
92
/*
93
@@ -XXX,XX +XXX,XX @@ static void imx_eth_update(IMXFECState *s);
94
* For now we don't handle any GPIO/interrupt line, so the OS will
95
* have to poll for the PHY status.
96
*/
97
-static void imx_phy_update_irq(IMXFECState *s)
98
+static void imx_phy_update_irq(void *opaque, int n, int level)
99
{
100
- imx_eth_update(s);
101
-}
102
-
103
-static void imx_phy_update_link(IMXFECState *s)
104
-{
105
- /* Autonegotiation status mirrors link status. */
106
- if (qemu_get_queue(s->nic)->link_down) {
107
- trace_imx_phy_update_link("down");
108
- s->phy_status &= ~0x0024;
109
- s->phy_int |= PHY_INT_DOWN;
110
- } else {
111
- trace_imx_phy_update_link("up");
112
- s->phy_status |= 0x0024;
113
- s->phy_int |= PHY_INT_ENERGYON;
114
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
115
- }
116
- imx_phy_update_irq(s);
117
+ imx_eth_update(opaque);
118
}
119
120
static void imx_eth_set_link(NetClientState *nc)
121
{
122
- imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc)));
123
-}
124
-
125
-static void imx_phy_reset(IMXFECState *s)
126
-{
127
- trace_imx_phy_reset();
128
-
129
- s->phy_status = 0x7809;
130
- s->phy_control = 0x3000;
131
- s->phy_advertise = 0x01e1;
132
- s->phy_int_mask = 0;
133
- s->phy_int = 0;
134
- imx_phy_update_link(s);
135
+ lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii,
136
+ nc->link_down);
137
}
138
139
static uint32_t imx_phy_read(IMXFECState *s, int reg)
140
{
141
- uint32_t val;
142
uint32_t phy = reg / 32;
143
144
if (!s->phy_connected) {
145
@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
146
147
reg %= 32;
148
149
- switch (reg) {
150
- case 0: /* Basic Control */
151
- val = s->phy_control;
152
- break;
153
- case 1: /* Basic Status */
154
- val = s->phy_status;
155
- break;
156
- case 2: /* ID1 */
157
- val = 0x0007;
158
- break;
159
- case 3: /* ID2 */
160
- val = 0xc0d1;
161
- break;
162
- case 4: /* Auto-neg advertisement */
163
- val = s->phy_advertise;
164
- break;
165
- case 5: /* Auto-neg Link Partner Ability */
166
- val = 0x0f71;
167
- break;
168
- case 6: /* Auto-neg Expansion */
169
- val = 1;
170
- break;
171
- case 29: /* Interrupt source. */
172
- val = s->phy_int;
173
- s->phy_int = 0;
174
- imx_phy_update_irq(s);
175
- break;
176
- case 30: /* Interrupt mask */
177
- val = s->phy_int_mask;
178
- break;
179
- case 17:
180
- case 18:
181
- case 27:
182
- case 31:
183
- qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n",
184
- TYPE_IMX_FEC, __func__, reg);
185
- val = 0;
186
- break;
187
- default:
188
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
189
- TYPE_IMX_FEC, __func__, reg);
190
- val = 0;
191
- break;
192
- }
193
-
194
- trace_imx_phy_read(val, phy, reg);
195
-
196
- return val;
197
+ return lan9118_phy_read(&s->mii, reg);
198
}
199
200
static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
201
@@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
202
203
reg %= 32;
204
205
- trace_imx_phy_write(val, phy, reg);
206
-
207
- switch (reg) {
208
- case 0: /* Basic Control */
209
- if (val & 0x8000) {
210
- imx_phy_reset(s);
211
- } else {
212
- s->phy_control = val & 0x7980;
213
- /* Complete autonegotiation immediately. */
214
- if (val & 0x1000) {
215
- s->phy_status |= 0x0020;
216
- }
217
- }
218
- break;
219
- case 4: /* Auto-neg advertisement */
220
- s->phy_advertise = (val & 0x2d7f) | 0x80;
221
- break;
222
- case 30: /* Interrupt mask */
223
- s->phy_int_mask = val & 0xff;
224
- imx_phy_update_irq(s);
225
- break;
226
- case 17:
227
- case 18:
228
- case 27:
229
- case 31:
230
- qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n",
231
- TYPE_IMX_FEC, __func__, reg);
232
- break;
233
- default:
234
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
235
- TYPE_IMX_FEC, __func__, reg);
236
- break;
237
- }
238
+ lan9118_phy_write(&s->mii, reg, val);
239
}
240
241
static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr)
242
@@ -XXX,XX +XXX,XX @@ static void imx_eth_reset(DeviceState *d)
243
244
s->rx_descriptor = 0;
245
memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor));
246
-
247
- /* We also reset the PHY */
248
- imx_phy_reset(s);
249
}
250
251
static uint32_t imx_default_read(IMXFECState *s, uint32_t index)
252
@@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
253
sysbus_init_irq(sbd, &s->irq[0]);
254
sysbus_init_irq(sbd, &s->irq[1]);
255
256
+ qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0);
257
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
258
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
259
+ return;
260
+ }
261
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
262
+
263
qemu_macaddr_default_if_unset(&s->conf.macaddr);
264
265
s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf,
266
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
267
index XXXXXXX..XXXXXXX 100644
268
--- a/hw/net/lan9118_phy.c
269
+++ b/hw/net/lan9118_phy.c
26
@@ -XXX,XX +XXX,XX @@
270
@@ -XXX,XX +XXX,XX @@
271
* Copyright (c) 2009 CodeSourcery, LLC.
272
* Written by Paul Brook
273
*
274
+ * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
275
+ *
276
* This code is licensed under the GNU GPL v2
277
*
278
* Contributions after 2012-01-13 are licensed under the terms of the
279
@@ -XXX,XX +XXX,XX @@
280
#include "hw/resettable.h"
281
#include "migration/vmstate.h"
27
#include "qemu/log.h"
282
#include "qemu/log.h"
28
#include "qemu/module.h"
283
+#include "trace.h"
29
#include "hw/registerfields.h"
284
30
+#include "hw/qdev-clock.h"
285
#define PHY_INT_ENERGYON (1 << 7)
31
286
#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
32
#ifndef ZYNQ_SLCR_ERR_DEBUG
287
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
33
#define ZYNQ_SLCR_ERR_DEBUG 0
288
34
@@ -XXX,XX +XXX,XX @@ REG32(LOCKSTA, 0x00c)
289
switch (reg) {
35
REG32(ARM_PLL_CTRL, 0x100)
290
case 0: /* Basic Control */
36
REG32(DDR_PLL_CTRL, 0x104)
291
- return s->control;
37
REG32(IO_PLL_CTRL, 0x108)
292
+ val = s->control;
38
+/* fields for [ARM|DDR|IO]_PLL_CTRL registers */
293
+ break;
39
+ FIELD(xxx_PLL_CTRL, PLL_RESET, 0, 1)
294
case 1: /* Basic Status */
40
+ FIELD(xxx_PLL_CTRL, PLL_PWRDWN, 1, 1)
295
- return s->status;
41
+ FIELD(xxx_PLL_CTRL, PLL_BYPASS_QUAL, 3, 1)
296
+ val = s->status;
42
+ FIELD(xxx_PLL_CTRL, PLL_BYPASS_FORCE, 4, 1)
297
+ break;
43
+ FIELD(xxx_PLL_CTRL, PLL_FPDIV, 12, 7)
298
case 2: /* ID1 */
44
REG32(PLL_STATUS, 0x10c)
299
- return 0x0007;
45
REG32(ARM_PLL_CFG, 0x110)
300
+ val = 0x0007;
46
REG32(DDR_PLL_CFG, 0x114)
301
+ break;
47
@@ -XXX,XX +XXX,XX @@ REG32(SMC_CLK_CTRL, 0x148)
302
case 3: /* ID2 */
48
REG32(LQSPI_CLK_CTRL, 0x14c)
303
- return 0xc0d1;
49
REG32(SDIO_CLK_CTRL, 0x150)
304
+ val = 0xc0d1;
50
REG32(UART_CLK_CTRL, 0x154)
305
+ break;
51
+ FIELD(UART_CLK_CTRL, CLKACT0, 0, 1)
306
case 4: /* Auto-neg advertisement */
52
+ FIELD(UART_CLK_CTRL, CLKACT1, 1, 1)
307
- return s->advertise;
53
+ FIELD(UART_CLK_CTRL, SRCSEL, 4, 2)
308
+ val = s->advertise;
54
+ FIELD(UART_CLK_CTRL, DIVISOR, 8, 6)
309
+ break;
55
REG32(SPI_CLK_CTRL, 0x158)
310
case 5: /* Auto-neg Link Partner Ability */
56
REG32(CAN_CLK_CTRL, 0x15c)
311
- return 0x0f71;
57
REG32(CAN_MIOCLK_CTRL, 0x160)
312
+ val = 0x0f71;
58
@@ -XXX,XX +XXX,XX @@ typedef struct ZynqSLCRState {
313
+ break;
59
MemoryRegion iomem;
314
case 6: /* Auto-neg Expansion */
60
315
- return 1;
61
uint32_t regs[ZYNQ_SLCR_NUM_REGS];
316
- /* TODO 17, 18, 27, 29, 30, 31 */
62
+
317
+ val = 1;
63
+ Clock *ps_clk;
318
+ break;
64
+ Clock *uart0_ref_clk;
319
case 29: /* Interrupt source. */
65
+ Clock *uart1_ref_clk;
320
val = s->ints;
66
} ZynqSLCRState;
321
s->ints = 0;
67
322
lan9118_phy_update_irq(s);
68
-static void zynq_slcr_reset(DeviceState *d)
323
- return val;
69
+/*
324
+ break;
70
+ * return the output frequency of ARM/DDR/IO pll
325
case 30: /* Interrupt mask */
71
+ * using input frequency and PLL_CTRL register
326
- return s->int_mask;
72
+ */
327
+ val = s->int_mask;
73
+static uint64_t zynq_slcr_compute_pll(uint64_t input, uint32_t ctrl_reg)
328
+ break;
329
+ case 17:
330
+ case 18:
331
+ case 27:
332
+ case 31:
333
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
334
+ __func__, reg);
335
+ val = 0;
336
+ break;
337
default:
338
- qemu_log_mask(LOG_GUEST_ERROR,
339
- "lan9118_phy_read: PHY read reg %d\n", reg);
340
- return 0;
341
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
342
+ __func__, reg);
343
+ val = 0;
344
+ break;
345
}
346
+
347
+ trace_lan9118_phy_read(val, reg);
348
+
349
+ return val;
350
}
351
352
void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
74
{
353
{
75
- ZynqSLCRState *s = ZYNQ_SLCR(d);
354
+ trace_lan9118_phy_write(val, reg);
76
+ uint32_t mult = ((ctrl_reg & R_xxx_PLL_CTRL_PLL_FPDIV_MASK) >>
355
+
77
+ R_xxx_PLL_CTRL_PLL_FPDIV_SHIFT);
356
switch (reg) {
78
+
357
case 0: /* Basic Control */
79
+ /* first, check if pll is bypassed */
358
if (val & 0x8000) {
80
+ if (ctrl_reg & R_xxx_PLL_CTRL_PLL_BYPASS_FORCE_MASK) {
359
lan9118_phy_reset(s);
81
+ return input;
360
- break;
82
+ }
361
- }
83
+
362
- s->control = val & 0x7980;
84
+ /* is pll disabled ? */
363
- /* Complete autonegotiation immediately. */
85
+ if (ctrl_reg & (R_xxx_PLL_CTRL_PLL_RESET_MASK |
364
- if (val & 0x1000) {
86
+ R_xxx_PLL_CTRL_PLL_PWRDWN_MASK)) {
365
- s->status |= 0x0020;
87
+ return 0;
366
+ } else {
88
+ }
367
+ s->control = val & 0x7980;
89
+
368
+ /* Complete autonegotiation immediately. */
90
+ /* frequency multiplier -> period division */
369
+ if (val & 0x1000) {
91
+ return input / mult;
370
+ s->status |= 0x0020;
92
+}
371
+ }
93
+
94
+/*
95
+ * return the output period of a clock given:
96
+ * + the periods in an array corresponding to input mux selector
97
+ * + the register xxx_CLK_CTRL value
98
+ * + enable bit index in ctrl register
99
+ *
100
+ * This function makes the assumption that the ctrl_reg value is organized as
101
+ * follows:
102
+ * + bits[13:8] clock frequency divisor
103
+ * + bits[5:4] clock mux selector (index in array)
104
+ * + bits[index] clock enable
105
+ */
106
+static uint64_t zynq_slcr_compute_clock(const uint64_t periods[],
107
+ uint32_t ctrl_reg,
108
+ unsigned index)
109
+{
110
+ uint32_t srcsel = extract32(ctrl_reg, 4, 2); /* bits [5:4] */
111
+ uint32_t divisor = extract32(ctrl_reg, 8, 6); /* bits [13:8] */
112
+
113
+ /* first, check if clock is disabled */
114
+ if (((ctrl_reg >> index) & 1u) == 0) {
115
+ return 0;
116
+ }
117
+
118
+ /*
119
+ * according to the Zynq technical ref. manual UG585 v1.12.2 in
120
+ * Clocks chapter, section 25.10.1 page 705:
121
+ * "The 6-bit divider provides a divide range of 1 to 63"
122
+ * We follow here what is implemented in linux kernel and consider
123
+ * the 0 value as a bypass (no division).
124
+ */
125
+ /* frequency divisor -> period multiplication */
126
+ return periods[srcsel] * (divisor ? divisor : 1u);
127
+}
128
+
129
+/*
130
+ * macro helper around zynq_slcr_compute_clock to avoid repeating
131
+ * the register name.
132
+ */
133
+#define ZYNQ_COMPUTE_CLK(state, plls, reg, enable_field) \
134
+ zynq_slcr_compute_clock((plls), (state)->regs[reg], \
135
+ reg ## _ ## enable_field ## _SHIFT)
136
+
137
+/**
138
+ * Compute and set the ouputs clocks periods.
139
+ * But do not propagate them further. Connected clocks
140
+ * will not receive any updates (See zynq_slcr_compute_clocks())
141
+ */
142
+static void zynq_slcr_compute_clocks(ZynqSLCRState *s)
143
+{
144
+ uint64_t ps_clk = clock_get(s->ps_clk);
145
+
146
+ /* consider outputs clocks are disabled while in reset */
147
+ if (device_is_in_reset(DEVICE(s))) {
148
+ ps_clk = 0;
149
+ }
150
+
151
+ uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]);
152
+ uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]);
153
+ uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]);
154
+
155
+ uint64_t uart_mux[4] = {io_pll, io_pll, arm_pll, ddr_pll};
156
+
157
+ /* compute uartX reference clocks */
158
+ clock_set(s->uart0_ref_clk,
159
+ ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0));
160
+ clock_set(s->uart1_ref_clk,
161
+ ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1));
162
+}
163
+
164
+/**
165
+ * Propagate the outputs clocks.
166
+ * zynq_slcr_compute_clocks() should have been called before
167
+ * to configure them.
168
+ */
169
+static void zynq_slcr_propagate_clocks(ZynqSLCRState *s)
170
+{
171
+ clock_propagate(s->uart0_ref_clk);
172
+ clock_propagate(s->uart1_ref_clk);
173
+}
174
+
175
+static void zynq_slcr_ps_clk_callback(void *opaque)
176
+{
177
+ ZynqSLCRState *s = (ZynqSLCRState *) opaque;
178
+ zynq_slcr_compute_clocks(s);
179
+ zynq_slcr_propagate_clocks(s);
180
+}
181
+
182
+static void zynq_slcr_reset_init(Object *obj, ResetType type)
183
+{
184
+ ZynqSLCRState *s = ZYNQ_SLCR(obj);
185
int i;
186
187
DB_PRINT("RESET\n");
188
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_reset(DeviceState *d)
189
s->regs[R_DDRIOB + 12] = 0x00000021;
190
}
191
192
+static void zynq_slcr_reset_hold(Object *obj)
193
+{
194
+ ZynqSLCRState *s = ZYNQ_SLCR(obj);
195
+
196
+ /* will disable all output clocks */
197
+ zynq_slcr_compute_clocks(s);
198
+ zynq_slcr_propagate_clocks(s);
199
+}
200
+
201
+static void zynq_slcr_reset_exit(Object *obj)
202
+{
203
+ ZynqSLCRState *s = ZYNQ_SLCR(obj);
204
+
205
+ /* will compute output clocks according to ps_clk and registers */
206
+ zynq_slcr_compute_clocks(s);
207
+ zynq_slcr_propagate_clocks(s);
208
+}
209
210
static bool zynq_slcr_check_offset(hwaddr offset, bool rnw)
211
{
212
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
213
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
214
}
372
}
215
break;
373
break;
216
+ case R_IO_PLL_CTRL:
374
case 4: /* Auto-neg advertisement */
217
+ case R_ARM_PLL_CTRL:
375
s->advertise = (val & 0x2d7f) | 0x80;
218
+ case R_DDR_PLL_CTRL:
376
break;
219
+ case R_UART_CLK_CTRL:
377
- /* TODO 17, 18, 27, 31 */
220
+ zynq_slcr_compute_clocks(s);
378
case 30: /* Interrupt mask */
221
+ zynq_slcr_propagate_clocks(s);
379
s->int_mask = val & 0xff;
380
lan9118_phy_update_irq(s);
381
break;
382
+ case 17:
383
+ case 18:
384
+ case 27:
385
+ case 31:
386
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
387
+ __func__, reg);
388
+ break;
389
default:
390
- qemu_log_mask(LOG_GUEST_ERROR,
391
- "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
392
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
393
+ __func__, reg);
222
+ break;
394
+ break;
223
}
395
}
224
}
396
}
225
397
226
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps slcr_ops = {
398
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
227
.endianness = DEVICE_NATIVE_ENDIAN,
399
228
};
400
/* Autonegotiation status mirrors link status. */
229
401
if (link_down) {
230
+static const ClockPortInitArray zynq_slcr_clocks = {
402
+ trace_lan9118_phy_update_link("down");
231
+ QDEV_CLOCK_IN(ZynqSLCRState, ps_clk, zynq_slcr_ps_clk_callback),
403
s->status &= ~0x0024;
232
+ QDEV_CLOCK_OUT(ZynqSLCRState, uart0_ref_clk),
404
s->ints |= PHY_INT_DOWN;
233
+ QDEV_CLOCK_OUT(ZynqSLCRState, uart1_ref_clk),
405
} else {
234
+ QDEV_CLOCK_END
406
+ trace_lan9118_phy_update_link("up");
235
+};
407
s->status |= 0x0024;
236
+
408
s->ints |= PHY_INT_ENERGYON;
237
static void zynq_slcr_init(Object *obj)
409
s->ints |= PHY_INT_AUTONEG_COMPLETE;
410
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
411
412
void lan9118_phy_reset(Lan9118PhyState *s)
238
{
413
{
239
ZynqSLCRState *s = ZYNQ_SLCR(obj);
414
+ trace_lan9118_phy_reset();
240
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_init(Object *obj)
415
+
241
memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr",
416
s->control = 0x3000;
242
ZYNQ_SLCR_MMIO_SIZE);
417
s->status = 0x7809;
243
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
418
s->advertise = 0x01e1;
244
+
419
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118_phy = {
245
+ qdev_init_clocks(DEVICE(obj), zynq_slcr_clocks);
420
.version_id = 1,
246
}
421
.minimum_version_id = 1,
247
422
.fields = (const VMStateField[]) {
248
static const VMStateDescription vmstate_zynq_slcr = {
423
- VMSTATE_UINT16(control, Lan9118PhyState),
249
.name = "zynq_slcr",
424
VMSTATE_UINT16(status, Lan9118PhyState),
250
- .version_id = 2,
425
+ VMSTATE_UINT16(control, Lan9118PhyState),
251
+ .version_id = 3,
426
VMSTATE_UINT16(advertise, Lan9118PhyState),
252
.minimum_version_id = 2,
427
VMSTATE_UINT16(ints, Lan9118PhyState),
253
.fields = (VMStateField[]) {
428
VMSTATE_UINT16(int_mask, Lan9118PhyState),
254
VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS),
429
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
255
+ VMSTATE_CLOCK_V(ps_clk, ZynqSLCRState, 3),
430
index XXXXXXX..XXXXXXX 100644
256
VMSTATE_END_OF_LIST()
431
--- a/hw/net/Kconfig
257
}
432
+++ b/hw/net/Kconfig
258
};
433
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_SUN8I_EMAC
259
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_zynq_slcr = {
434
260
static void zynq_slcr_class_init(ObjectClass *klass, void *data)
435
config IMX_FEC
261
{
436
bool
262
DeviceClass *dc = DEVICE_CLASS(klass);
437
+ select LAN9118_PHY
263
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
438
264
439
config CADENCE
265
dc->vmsd = &vmstate_zynq_slcr;
440
bool
266
- dc->reset = zynq_slcr_reset;
441
diff --git a/hw/net/trace-events b/hw/net/trace-events
267
+ rc->phases.enter = zynq_slcr_reset_init;
442
index XXXXXXX..XXXXXXX 100644
268
+ rc->phases.hold = zynq_slcr_reset_hold;
443
--- a/hw/net/trace-events
269
+ rc->phases.exit = zynq_slcr_reset_exit;
444
+++ b/hw/net/trace-events
270
}
445
@@ -XXX,XX +XXX,XX @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
271
446
allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
272
static const TypeInfo zynq_slcr_info = {
447
allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
448
449
+# lan9118_phy.c
450
+lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16
451
+lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16
452
+lan9118_phy_update_link(const char *s) "%s"
453
+lan9118_phy_reset(void) ""
454
+
455
# lance.c
456
lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x"
457
lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x"
458
@@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
459
i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
460
461
# imx_fec.c
462
-imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
463
imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)"
464
-imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
465
imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)"
466
-imx_phy_update_link(const char *s) "%s"
467
-imx_phy_reset(void) ""
468
imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
469
imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x"
470
imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit"
273
--
471
--
274
2.20.1
472
2.34.1
275
276
diff view generated by jsdifflib
New patch
[PULL 03/72] hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
1
From: Bernhard Beschow <shentey@gmail.com>
1
2
3
Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and
4
fixes the MSB of selector field to be zero, as specified in the datasheet.
5
6
Fixes: 2a424990170b "LAN9118 emulation"
7
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
8
Tested-by: Guenter Roeck <linux@roeck-us.net>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20241102125724.532843-4-shentey@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/net/lan9118_phy.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/net/lan9118_phy.c
19
+++ b/hw/net/lan9118_phy.c
20
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
21
val = s->advertise;
22
break;
23
case 5: /* Auto-neg Link Partner Ability */
24
- val = 0x0f71;
25
+ val = 0x0fe1;
26
break;
27
case 6: /* Auto-neg Expansion */
28
val = 1;
29
--
30
2.34.1
diff view generated by jsdifflib
[PULL 19/31] Cadence: gem: fix wraparound in 64bit descriptors
[PULL 04/72] hw/net/lan9118_phy: Reuse MII constants
1
From: Ramon Fried <rfried.dev@gmail.com>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Wraparound of TX descriptor cyclic buffer only updated
3
Prefer named constants over magic values for better readability.
4
the low 32 bits of the descriptor.
5
Fix that by checking if we're working with 64bit descriptors.
6
4
7
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
9
Message-id: 20200417171736.441607-1-rfried.dev@gmail.com
7
Tested-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20241102125724.532843-5-shentey@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
hw/net/cadence_gem.c | 9 ++++++++-
11
include/hw/net/mii.h | 6 +++++
13
1 file changed, 8 insertions(+), 1 deletion(-)
12
hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++----------------
13
2 files changed, 46 insertions(+), 23 deletions(-)
14
14
15
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
15
diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/net/cadence_gem.c
17
--- a/include/hw/net/mii.h
18
+++ b/hw/net/cadence_gem.c
18
+++ b/include/hw/net/mii.h
19
@@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s)
19
@@ -XXX,XX +XXX,XX @@
20
/* read next descriptor */
20
#define MII_BMSR_JABBER (1 << 1) /* Jabber detected */
21
if (tx_desc_get_wrap(desc)) {
21
#define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */
22
tx_desc_set_last(desc);
22
23
- packet_desc_addr = s->regs[GEM_TXQBASE];
23
+#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */
24
#define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */
25
#define MII_ANAR_PAUSE (1 << 10) /* Try for pause */
26
#define MII_ANAR_TXFD (1 << 8)
27
@@ -XXX,XX +XXX,XX @@
28
#define MII_ANAR_10FD (1 << 6)
29
#define MII_ANAR_10 (1 << 5)
30
#define MII_ANAR_CSMACD (1 << 0)
31
+#define MII_ANAR_SELECT (0x001f) /* Selector bits */
32
33
#define MII_ANLPAR_ACK (1 << 14)
34
#define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */
35
@@ -XXX,XX +XXX,XX @@
36
#define RTL8201CP_PHYID1 0x0000
37
#define RTL8201CP_PHYID2 0x8201
38
39
+/* SMSC LAN9118 */
40
+#define SMSCLAN9118_PHYID1 0x0007
41
+#define SMSCLAN9118_PHYID2 0xc0d1
24
+
42
+
25
+ if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
43
/* RealTek 8211E */
26
+ packet_desc_addr = s->regs[GEM_TBQPH];
44
#define RTL8211E_PHYID1 0x001c
27
+ packet_desc_addr <<= 32;
45
#define RTL8211E_PHYID2 0xc915
28
+ } else {
46
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
29
+ packet_desc_addr = 0;
47
index XXXXXXX..XXXXXXX 100644
30
+ }
48
--- a/hw/net/lan9118_phy.c
31
+ packet_desc_addr |= s->regs[GEM_TXQBASE];
49
+++ b/hw/net/lan9118_phy.c
32
} else {
50
@@ -XXX,XX +XXX,XX @@
33
packet_desc_addr += 4 * gem_get_desc_len(s, false);
51
52
#include "qemu/osdep.h"
53
#include "hw/net/lan9118_phy.h"
54
+#include "hw/net/mii.h"
55
#include "hw/irq.h"
56
#include "hw/resettable.h"
57
#include "migration/vmstate.h"
58
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
59
uint16_t val;
60
61
switch (reg) {
62
- case 0: /* Basic Control */
63
+ case MII_BMCR:
64
val = s->control;
65
break;
66
- case 1: /* Basic Status */
67
+ case MII_BMSR:
68
val = s->status;
69
break;
70
- case 2: /* ID1 */
71
- val = 0x0007;
72
+ case MII_PHYID1:
73
+ val = SMSCLAN9118_PHYID1;
74
break;
75
- case 3: /* ID2 */
76
- val = 0xc0d1;
77
+ case MII_PHYID2:
78
+ val = SMSCLAN9118_PHYID2;
79
break;
80
- case 4: /* Auto-neg advertisement */
81
+ case MII_ANAR:
82
val = s->advertise;
83
break;
84
- case 5: /* Auto-neg Link Partner Ability */
85
- val = 0x0fe1;
86
+ case MII_ANLPAR:
87
+ val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 |
88
+ MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD |
89
+ MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
90
break;
91
- case 6: /* Auto-neg Expansion */
92
- val = 1;
93
+ case MII_ANER:
94
+ val = MII_ANER_NWAY;
95
break;
96
case 29: /* Interrupt source. */
97
val = s->ints;
98
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
99
trace_lan9118_phy_write(val, reg);
100
101
switch (reg) {
102
- case 0: /* Basic Control */
103
- if (val & 0x8000) {
104
+ case MII_BMCR:
105
+ if (val & MII_BMCR_RESET) {
106
lan9118_phy_reset(s);
107
} else {
108
- s->control = val & 0x7980;
109
+ s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 |
110
+ MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD |
111
+ MII_BMCR_CTST);
112
/* Complete autonegotiation immediately. */
113
- if (val & 0x1000) {
114
- s->status |= 0x0020;
115
+ if (val & MII_BMCR_AUTOEN) {
116
+ s->status |= MII_BMSR_AN_COMP;
34
}
117
}
118
}
119
break;
120
- case 4: /* Auto-neg advertisement */
121
- s->advertise = (val & 0x2d7f) | 0x80;
122
+ case MII_ANAR:
123
+ s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
124
+ MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
125
+ MII_ANAR_SELECT))
126
+ | MII_ANAR_TX;
127
break;
128
case 30: /* Interrupt mask */
129
s->int_mask = val & 0xff;
130
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
131
/* Autonegotiation status mirrors link status. */
132
if (link_down) {
133
trace_lan9118_phy_update_link("down");
134
- s->status &= ~0x0024;
135
+ s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST);
136
s->ints |= PHY_INT_DOWN;
137
} else {
138
trace_lan9118_phy_update_link("up");
139
- s->status |= 0x0024;
140
+ s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST;
141
s->ints |= PHY_INT_ENERGYON;
142
s->ints |= PHY_INT_AUTONEG_COMPLETE;
143
}
144
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_reset(Lan9118PhyState *s)
145
{
146
trace_lan9118_phy_reset();
147
148
- s->control = 0x3000;
149
- s->status = 0x7809;
150
- s->advertise = 0x01e1;
151
+ s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100;
152
+ s->status = MII_BMSR_100TX_FD
153
+ | MII_BMSR_100TX_HD
154
+ | MII_BMSR_10T_FD
155
+ | MII_BMSR_10T_HD
156
+ | MII_BMSR_AUTONEG
157
+ | MII_BMSR_EXTCAP;
158
+ s->advertise = MII_ANAR_TXFD
159
+ | MII_ANAR_TX
160
+ | MII_ANAR_10FD
161
+ | MII_ANAR_10
162
+ | MII_ANAR_CSMACD;
163
s->int_mask = 0;
164
s->ints = 0;
165
lan9118_phy_update_link(s, s->link_down);
35
--
166
--
36
2.20.1
167
2.34.1
37
38
diff view generated by jsdifflib
[PULL 10/31] hw/core/clock-vmstate: define a vmstate entry for clock state
[PULL 05/72] hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
1
From: Damien Hedde <damien.hedde@greensocs.com>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
3
The real device advertises this mode and the device model already advertises
4
100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to
5
make the model more realistic.
6
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Tested-by: Guenter Roeck <linux@roeck-us.net>
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
Message-id: 20241102125724.532843-6-shentey@gmail.com
8
Message-id: 20200406135251.157596-3-damien.hedde@greensocs.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
hw/core/Makefile.objs | 1 +
13
hw/net/lan9118_phy.c | 4 ++--
12
include/hw/clock.h | 9 +++++++++
14
1 file changed, 2 insertions(+), 2 deletions(-)
13
hw/core/clock-vmstate.c | 25 +++++++++++++++++++++++++
14
3 files changed, 35 insertions(+)
15
create mode 100644 hw/core/clock-vmstate.c
16
15
17
diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
18
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/core/Makefile.objs
18
--- a/hw/net/lan9118_phy.c
20
+++ b/hw/core/Makefile.objs
19
+++ b/hw/net/lan9118_phy.c
21
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SOFTMMU) += null-machine.o
20
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
22
common-obj-$(CONFIG_SOFTMMU) += loader.o
21
break;
23
common-obj-$(CONFIG_SOFTMMU) += machine-hmp-cmds.o
22
case MII_ANAR:
24
common-obj-$(CONFIG_SOFTMMU) += numa.o
23
s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
25
+common-obj-$(CONFIG_SOFTMMU) += clock-vmstate.o
24
- MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
26
obj-$(CONFIG_SOFTMMU) += machine-qmp-cmds.o
25
- MII_ANAR_SELECT))
27
26
+ MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD |
28
common-obj-$(CONFIG_EMPTY_SLOT) += empty_slot.o
27
+ MII_ANAR_10 | MII_ANAR_SELECT))
29
diff --git a/include/hw/clock.h b/include/hw/clock.h
28
| MII_ANAR_TX;
30
index XXXXXXX..XXXXXXX 100644
29
break;
31
--- a/include/hw/clock.h
30
case 30: /* Interrupt mask */
32
+++ b/include/hw/clock.h
33
@@ -XXX,XX +XXX,XX @@ struct Clock {
34
QLIST_ENTRY(Clock) sibling;
35
};
36
37
+/*
38
+ * vmstate description entry to be added in device vmsd.
39
+ */
40
+extern const VMStateDescription vmstate_clock;
41
+#define VMSTATE_CLOCK(field, state) \
42
+ VMSTATE_CLOCK_V(field, state, 0)
43
+#define VMSTATE_CLOCK_V(field, state, version) \
44
+ VMSTATE_STRUCT_POINTER_V(field, state, version, vmstate_clock, Clock)
45
+
46
/**
47
* clock_setup_canonical_path:
48
* @clk: clock
49
diff --git a/hw/core/clock-vmstate.c b/hw/core/clock-vmstate.c
50
new file mode 100644
51
index XXXXXXX..XXXXXXX
52
--- /dev/null
53
+++ b/hw/core/clock-vmstate.c
54
@@ -XXX,XX +XXX,XX @@
55
+/*
56
+ * Clock migration structure
57
+ *
58
+ * Copyright GreenSocs 2019-2020
59
+ *
60
+ * Authors:
61
+ * Damien Hedde
62
+ *
63
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
64
+ * See the COPYING file in the top-level directory.
65
+ */
66
+
67
+#include "qemu/osdep.h"
68
+#include "migration/vmstate.h"
69
+#include "hw/clock.h"
70
+
71
+const VMStateDescription vmstate_clock = {
72
+ .name = "clock",
73
+ .version_id = 0,
74
+ .minimum_version_id = 0,
75
+ .fields = (VMStateField[]) {
76
+ VMSTATE_UINT64(period, Clock),
77
+ VMSTATE_END_OF_LIST()
78
+ }
79
+};
80
--
31
--
81
2.20.1
32
2.34.1
82
83
diff view generated by jsdifflib
[PULL 13/31] docs/clocks: add device's clock documentation
[PULL 06/72] fpu: handle raising Invalid for infzero in pick_nan_muladd
1
Add the documentation about the clock inputs and outputs in devices.
1
For IEEE fused multiply-add, the (0 * inf) + NaN case should raise
2
Invalid for the multiplication of 0 by infinity. Currently we handle
3
this in the per-architecture ifdef ladder in pickNaNMulAdd().
4
However, since this isn't really architecture specific we can hoist
5
it up to the generic code.
2
6
3
This is based on the original work of Frederic Konrad.
7
For the cases where the infzero test in pickNaNMulAdd was
8
returning 2, we can delete the check entirely and allow the
9
code to fall into the normal pick-a-NaN handling, because this
10
will return 2 anyway (input 'c' being the only NaN in this case).
11
For the cases where infzero was returning 3 to indicate "return
12
the default NaN", we must retain that "return 3".
4
13
5
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
14
For Arm, this looks like it might be a behaviour change because we
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
used to set float_flag_invalid | float_flag_invalid_imz only if C is
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
16
a quiet NaN. However, it is not, because Arm target code never looks
8
Message-id: 20200406135251.157596-6-damien.hedde@greensocs.com
17
at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we
9
[PMM: Editing pass for minor grammar, style and Sphinx
18
already raised float_flag_invalid via the "abc_mask &
10
formatting fixes]
19
float_cmask_snan" check in pick_nan_muladd.
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
21
For any target architecture using the "default implementation" at the
22
bottom of the ifdef, this is a behaviour change but will be fixing a
23
bug (where we failed to raise the Invalid exception for (0 * inf +
24
QNaN). The architectures using the default case are:
25
* hppa
26
* i386
27
* sh4
28
* tricore
29
30
The x86, Tricore and SH4 CPU architecture manuals are clear that this
31
should have raised Invalid; HPPA is a bit vaguer but still seems
32
clear enough.
33
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
36
Message-id: 20241202131347.498124-2-peter.maydell@linaro.org
13
---
37
---
14
docs/devel/clocks.rst | 391 ++++++++++++++++++++++++++++++++++++++++++
38
fpu/softfloat-parts.c.inc | 13 +++++++------
15
docs/devel/index.rst | 1 +
39
fpu/softfloat-specialize.c.inc | 29 +----------------------------
16
2 files changed, 392 insertions(+)
40
2 files changed, 8 insertions(+), 34 deletions(-)
17
create mode 100644 docs/devel/clocks.rst
18
41
19
diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst
42
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
20
new file mode 100644
43
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX
44
--- a/fpu/softfloat-parts.c.inc
22
--- /dev/null
45
+++ b/fpu/softfloat-parts.c.inc
23
+++ b/docs/devel/clocks.rst
46
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
24
@@ -XXX,XX +XXX,XX @@
47
int ab_mask, int abc_mask)
25
+Modelling a clock tree in QEMU
48
{
26
+==============================
49
int which;
27
+
50
+ bool infzero = (ab_mask == float_cmask_infzero);
28
+What are clocks?
51
29
+----------------
52
if (unlikely(abc_mask & float_cmask_snan)) {
30
+
53
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
31
+Clocks are QOM objects developed for the purpose of modelling the
54
}
32
+distribution of clocks in QEMU.
55
33
+
56
- which = pickNaNMulAdd(a->cls, b->cls, c->cls,
34
+They allow us to model the clock distribution of a platform and detect
57
- ab_mask == float_cmask_infzero, s);
35
+configuration errors in the clock tree such as badly configured PLL, clock
58
+ if (infzero) {
36
+source selection or disabled clock.
59
+ /* This is (0 * inf) + NaN or (inf * 0) + NaN */
37
+
60
+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
38
+The object is *Clock* and its QOM name is ``clock`` (in C code, the macro
39
+``TYPE_CLOCK``).
40
+
41
+Clocks are typically used with devices where they are used to model inputs
42
+and outputs. They are created in a similar way to GPIOs. Inputs and outputs
43
+of different devices can be connected together.
44
+
45
+In these cases a Clock object is a child of a Device object, but this
46
+is not a requirement. Clocks can be independent of devices. For
47
+example it is possible to create a clock outside of any device to
48
+model the main clock source of a machine.
49
+
50
+Here is an example of clocks::
51
+
52
+ +---------+ +----------------------+ +--------------+
53
+ | Clock 1 | | Device B | | Device C |
54
+ | | | +-------+ +-------+ | | +-------+ |
55
+ | |>>-+-->>|Clock 2| |Clock 3|>>--->>|Clock 6| |
56
+ +---------+ | | | (in) | | (out) | | | | (in) | |
57
+ | | +-------+ +-------+ | | +-------+ |
58
+ | | +-------+ | +--------------+
59
+ | | |Clock 4|>>
60
+ | | | (out) | | +--------------+
61
+ | | +-------+ | | Device D |
62
+ | | +-------+ | | +-------+ |
63
+ | | |Clock 5|>>--->>|Clock 7| |
64
+ | | | (out) | | | | (in) | |
65
+ | | +-------+ | | +-------+ |
66
+ | +----------------------+ | |
67
+ | | +-------+ |
68
+ +----------------------------->>|Clock 8| |
69
+ | | (in) | |
70
+ | +-------+ |
71
+ +--------------+
72
+
73
+Clocks are defined in the ``include/hw/clock.h`` header and device
74
+related functions are defined in the ``include/hw/qdev-clock.h``
75
+header.
76
+
77
+The clock state
78
+---------------
79
+
80
+The state of a clock is its period; it is stored as an integer
81
+representing it in units of 2 :sup:`-32` ns. The special value of 0 is used to
82
+represent the clock being inactive or gated. The clocks do not model
83
+the signal itself (pin toggling) or other properties such as the duty
84
+cycle.
85
+
86
+All clocks contain this state: outputs as well as inputs. This allows
87
+the current period of a clock to be fetched at any time. When a clock
88
+is updated, the value is immediately propagated to all connected
89
+clocks in the tree.
90
+
91
+To ease interaction with clocks, helpers with a unit suffix are defined for
92
+every clock state setter or getter. The suffixes are:
93
+
94
+- ``_ns`` for handling periods in nanoseconds
95
+- ``_hz`` for handling frequencies in hertz
96
+
97
+The 0 period value is converted to 0 in hertz and vice versa. 0 always means
98
+that the clock is disabled.
99
+
100
+Adding a new clock
101
+------------------
102
+
103
+Adding clocks to a device must be done during the init method of the Device
104
+instance.
105
+
106
+To add an input clock to a device, the function ``qdev_init_clock_in()``
107
+must be used. It takes the name, a callback and an opaque parameter
108
+for the callback (this will be explained in a following section).
109
+Output is simpler; only the name is required. Typically::
110
+
111
+ qdev_init_clock_in(DEVICE(dev), "clk_in", clk_in_callback, dev);
112
+ qdev_init_clock_out(DEVICE(dev), "clk_out");
113
+
114
+Both functions return the created Clock pointer, which should be saved in the
115
+device's state structure for further use.
116
+
117
+These objects will be automatically deleted by the QOM reference mechanism.
118
+
119
+Note that it is possible to create a static array describing clock inputs and
120
+outputs. The function ``qdev_init_clocks()`` must be called with the array as
121
+parameter to initialize the clocks: it has the same behaviour as calling the
122
+``qdev_init_clock_in/out()`` for each clock in the array. To ease the array
123
+construction, some macros are defined in ``include/hw/qdev-clock.h``.
124
+As an example, the following creates 2 clocks to a device: one input and one
125
+output.
126
+
127
+.. code-block:: c
128
+
129
+ /* device structure containing pointers to the clock objects */
130
+ typedef struct MyDeviceState {
131
+ DeviceState parent_obj;
132
+ Clock *clk_in;
133
+ Clock *clk_out;
134
+ } MyDeviceState;
135
+
136
+ /*
137
+ * callback for the input clock (see "Callback on input clock
138
+ * change" section below for more information).
139
+ */
140
+ static void clk_in_callback(void *opaque);
141
+
142
+ /*
143
+ * static array describing clocks:
144
+ * + a clock input named "clk_in", whose pointer is stored in
145
+ * the clk_in field of a MyDeviceState structure with callback
146
+ * clk_in_callback.
147
+ * + a clock output named "clk_out" whose pointer is stored in
148
+ * the clk_out field of a MyDeviceState structure.
149
+ */
150
+ static const ClockPortInitArray mydev_clocks = {
151
+ QDEV_CLOCK_IN(MyDeviceState, clk_in, clk_in_callback),
152
+ QDEV_CLOCK_OUT(MyDeviceState, clk_out),
153
+ QDEV_CLOCK_END
154
+ };
155
+
156
+ /* device initialization function */
157
+ static void mydev_init(Object *obj)
158
+ {
159
+ /* cast to MyDeviceState */
160
+ MyDeviceState *mydev = MYDEVICE(obj);
161
+ /* create and fill the pointer fields in the MyDeviceState */
162
+ qdev_init_clocks(mydev, mydev_clocks);
163
+ [...]
164
+ }
61
+ }
165
+
62
+
166
+An alternative way to create a clock is to simply call
63
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
167
+``object_new(TYPE_CLOCK)``. In that case the clock will neither be an
64
168
+input nor an output of a device. After the whole QOM hierarchy of the
65
if (s->default_nan_mode || which == 3) {
169
+clock has been set ``clock_setup_canonical_path()`` should be called.
66
- /*
67
- * Note that this check is after pickNaNMulAdd so that function
68
- * has an opportunity to set the Invalid flag for infzero.
69
- */
70
parts_default_nan(a, s);
71
return a;
72
}
73
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
74
index XXXXXXX..XXXXXXX 100644
75
--- a/fpu/softfloat-specialize.c.inc
76
+++ b/fpu/softfloat-specialize.c.inc
77
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
78
* the default NaN
79
*/
80
if (infzero && is_qnan(c_cls)) {
81
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
82
return 3;
83
}
84
85
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
86
* case sets InvalidOp and returns the default NaN
87
*/
88
if (infzero) {
89
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
90
return 3;
91
}
92
/* Prefer sNaN over qNaN, in the a, b, c order. */
93
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
94
* For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
95
* case sets InvalidOp and returns the input value 'c'
96
*/
97
- if (infzero) {
98
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
99
- return 2;
100
- }
101
/* Prefer sNaN over qNaN, in the c, a, b order. */
102
if (is_snan(c_cls)) {
103
return 2;
104
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
105
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
106
* case sets InvalidOp and returns the input value 'c'
107
*/
108
- if (infzero) {
109
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
110
- return 2;
111
- }
170
+
112
+
171
+At creation, the period of the clock is 0: the clock is disabled. You can
113
/* Prefer sNaN over qNaN, in the c, a, b order. */
172
+change it using ``clock_set_ns()`` or ``clock_set_hz()``.
114
if (is_snan(c_cls)) {
173
+
115
return 2;
174
+Note that if you are creating a clock with a fixed period which will never
116
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
175
+change (for example the main clock source of a board), then you'll have
117
* to return an input NaN if we have one (ie c) rather than generating
176
+nothing else to do. This value will be propagated to other clocks when
118
* a default NaN
177
+connecting the clocks together and devices will fetch the right value during
119
*/
178
+the first reset.
120
- if (infzero) {
179
+
121
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
180
+Retrieving clocks from a device
122
- return 2;
181
+-------------------------------
123
- }
182
+
124
183
+``qdev_get_clock_in()`` and ``dev_get_clock_out()`` are available to
125
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
184
+get the clock inputs or outputs of a device. For example:
126
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
185
+
127
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
186
+.. code-block:: c
128
return 1;
187
+
129
}
188
+ Clock *clk = qdev_get_clock_in(DEVICE(mydev), "clk_in");
130
#elif defined(TARGET_RISCV)
189
+
131
- /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
190
+or:
132
- if (infzero) {
191
+
133
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
192
+.. code-block:: c
134
- }
193
+
135
return 3; /* default NaN */
194
+ Clock *clk = qdev_get_clock_out(DEVICE(mydev), "clk_out");
136
#elif defined(TARGET_S390X)
195
+
137
if (infzero) {
196
+Connecting two clocks together
138
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
197
+------------------------------
139
return 3;
198
+
140
}
199
+To connect two clocks together, use the ``clock_set_source()`` function.
141
200
+Given two clocks ``clk1``, and ``clk2``, ``clock_set_source(clk2, clk1);``
142
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
201
+configures ``clk2`` to follow the ``clk1`` period changes. Every time ``clk1``
143
return 2;
202
+is updated, ``clk2`` will be updated too.
144
}
203
+
145
#elif defined(TARGET_SPARC)
204
+When connecting clock between devices, prefer using the
146
- /* For (inf,0,nan) return c. */
205
+``qdev_connect_clock_in()`` function to set the source of an input
147
- if (infzero) {
206
+device clock. For example, to connect the input clock ``clk2`` of
148
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
207
+``devB`` to the output clock ``clk1`` of ``devA``, do:
149
- return 2;
208
+
150
- }
209
+.. code-block:: c
151
/* Prefer SNaN over QNaN, order C, B, A. */
210
+
152
if (is_snan(c_cls)) {
211
+ qdev_connect_clock_in(devB, "clk2", qdev_get_clock_out(devA, "clk1"))
153
return 2;
212
+
154
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
213
+We used ``qdev_get_clock_out()`` above, but any clock can drive an
155
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
214
+input clock, even another input clock. The following diagram shows
156
* an input NaN if we have one (ie c).
215
+some examples of connections. Note also that a clock can drive several
157
*/
216
+other clocks.
158
- if (infzero) {
217
+
159
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
218
+::
160
- return 2;
219
+
161
- }
220
+ +------------+ +--------------------------------------------------+
162
if (status->use_first_nan) {
221
+ | Device A | | Device B |
163
if (is_nan(a_cls)) {
222
+ | | | +---------------------+ |
164
return 0;
223
+ | | | | Device C | |
224
+ | +-------+ | | +-------+ | +-------+ +-------+ | +-------+ |
225
+ | |Clock 1|>>-->>|Clock 2|>>+-->>|Clock 3| |Clock 5|>>>>|Clock 6|>>
226
+ | | (out) | | | | (in) | | | | (in) | | (out) | | | (out) | |
227
+ | +-------+ | | +-------+ | | +-------+ +-------+ | +-------+ |
228
+ +------------+ | | +---------------------+ |
229
+ | | |
230
+ | | +--------------+ |
231
+ | | | Device D | |
232
+ | | | +-------+ | |
233
+ | +-->>|Clock 4| | |
234
+ | | | (in) | | |
235
+ | | +-------+ | |
236
+ | +--------------+ |
237
+ +--------------------------------------------------+
238
+
239
+In the above example, when *Clock 1* is updated by *Device A*, three
240
+clocks get the new clock period value: *Clock 2*, *Clock 3* and *Clock 4*.
241
+
242
+It is not possible to disconnect a clock or to change the clock connection
243
+after it is connected.
244
+
245
+Unconnected input clocks
246
+------------------------
247
+
248
+A newly created input clock is disabled (period of 0). This means the
249
+clock will be considered as disabled until the period is updated. If
250
+the clock remains unconnected it will always keep its initial value
251
+of 0. If this is not the desired behaviour, ``clock_set()``,
252
+``clock_set_ns()`` or ``clock_set_hz()`` should be called on the Clock
253
+object during device instance init. For example:
254
+
255
+.. code-block:: c
256
+
257
+ clk = qdev_init_clock_in(DEVICE(dev), "clk-in", clk_in_callback,
258
+ dev);
259
+ /* set initial value to 10ns / 100MHz */
260
+ clock_set_ns(clk, 10);
261
+
262
+Fetching clock frequency/period
263
+-------------------------------
264
+
265
+To get the current state of a clock, use the functions ``clock_get()``,
266
+``clock_get_ns()`` or ``clock_get_hz()``.
267
+
268
+It is also possible to register a callback on clock frequency changes.
269
+Here is an example:
270
+
271
+.. code-block:: c
272
+
273
+ void clock_callback(void *opaque) {
274
+ MyDeviceState *s = (MyDeviceState *) opaque;
275
+ /*
276
+ * 'opaque' is the argument passed to qdev_init_clock_in();
277
+ * usually this will be the device state pointer.
278
+ */
279
+
280
+ /* do something with the new period */
281
+ fprintf(stdout, "device new period is %" PRIu64 "ns\n",
282
+ clock_get_ns(dev->my_clk_input));
283
+ }
284
+
285
+Changing a clock period
286
+-----------------------
287
+
288
+A device can change its outputs using the ``clock_update()``,
289
+``clock_update_ns()`` or ``clock_update_hz()`` function. It will trigger
290
+updates on every connected input.
291
+
292
+For example, let's say that we have an output clock *clkout* and we
293
+have a pointer to it in the device state because we did the following
294
+in init phase:
295
+
296
+.. code-block:: c
297
+
298
+ dev->clkout = qdev_init_clock_out(DEVICE(dev), "clkout");
299
+
300
+Then at any time (apart from the cases listed below), it is possible to
301
+change the clock value by doing:
302
+
303
+.. code-block:: c
304
+
305
+ clock_update_hz(dev->clkout, 1000 * 1000 * 1000); /* 1GHz */
306
+
307
+Because updating a clock may trigger any side effects through
308
+connected clocks and their callbacks, this operation must be done
309
+while holding the qemu io lock.
310
+
311
+For the same reason, one can update clocks only when it is allowed to have
312
+side effects on other objects. In consequence, it is forbidden:
313
+
314
+* during migration,
315
+* and in the enter phase of reset.
316
+
317
+Note that calling ``clock_update[_ns|_hz]()`` is equivalent to calling
318
+``clock_set[_ns|_hz]()`` (with the same arguments) then
319
+``clock_propagate()`` on the clock. Thus, setting the clock value can
320
+be separated from triggering the side-effects. This is often required
321
+to factorize code to handle reset and migration in devices.
322
+
323
+Aliasing clocks
324
+---------------
325
+
326
+Sometimes, one needs to forward, or inherit, a clock from another
327
+device. Typically, when doing device composition, a device might
328
+expose a sub-device's clock without interfering with it. The function
329
+``qdev_alias_clock()`` can be used to achieve this behaviour. Note
330
+that it is possible to expose the clock under a different name.
331
+``qdev_alias_clock()`` works for both input and output clocks.
332
+
333
+For example, if device B is a child of device A,
334
+``device_a_instance_init()`` may do something like this:
335
+
336
+.. code-block:: c
337
+
338
+ void device_a_instance_init(Object *obj)
339
+ {
340
+ AState *A = DEVICE_A(obj);
341
+ BState *B;
342
+ /* create object B as child of A */
343
+ [...]
344
+ qdev_alias_clock(B, "clk", A, "b_clk");
345
+ /*
346
+ * Now A has a clock "b_clk" which is an alias to
347
+ * the clock "clk" of its child B.
348
+ */
349
+ }
350
+
351
+This function does not return any clock object. The new clock has the
352
+same direction (input or output) as the original one. This function
353
+only adds a link to the existing clock. In the above example, object B
354
+remains the only object allowed to use the clock and device A must not
355
+try to change the clock period or set a callback to the clock. This
356
+diagram describes the example with an input clock::
357
+
358
+ +--------------------------+
359
+ | Device A |
360
+ | +--------------+ |
361
+ | | Device B | |
362
+ | | +-------+ | |
363
+ >>"b_clk">>>| "clk" | | |
364
+ | (in) | | (in) | | |
365
+ | | +-------+ | |
366
+ | +--------------+ |
367
+ +--------------------------+
368
+
369
+Migration
370
+---------
371
+
372
+Clock state is not migrated automatically. Every device must handle its
373
+clock migration. Alias clocks must not be migrated.
374
+
375
+To ensure clock states are restored correctly during migration, there
376
+are two solutions.
377
+
378
+Clock states can be migrated by adding an entry into the device
379
+vmstate description. You should use the ``VMSTATE_CLOCK`` macro for this.
380
+This is typically used to migrate an input clock state. For example:
381
+
382
+.. code-block:: c
383
+
384
+ MyDeviceState {
385
+ DeviceState parent_obj;
386
+ [...] /* some fields */
387
+ Clock *clk;
388
+ };
389
+
390
+ VMStateDescription my_device_vmstate = {
391
+ .name = "my_device",
392
+ .fields = (VMStateField[]) {
393
+ [...], /* other migrated fields */
394
+ VMSTATE_CLOCK(clk, MyDeviceState),
395
+ VMSTATE_END_OF_LIST()
396
+ }
397
+ };
398
+
399
+The second solution is to restore the clock state using information already
400
+at our disposal. This can be used to restore output clock states using the
401
+device state. The functions ``clock_set[_ns|_hz]()`` can be used during the
402
+``post_load()`` migration callback.
403
+
404
+When adding clock support to an existing device, if you care about
405
+migration compatibility you will need to be careful, as simply adding
406
+a ``VMSTATE_CLOCK()`` line will break compatibility. Instead, you can
407
+put the ``VMSTATE_CLOCK()`` line into a vmstate subsection with a
408
+suitable ``needed`` function, and use ``clock_set()`` in a
409
+``pre_load()`` function to set the default value that will be used if
410
+the source virtual machine in the migration does not send the clock
411
+state.
412
+
413
+Care should be taken not to use ``clock_update[_ns|_hz]()`` or
414
+``clock_propagate()`` during the whole migration procedure because it
415
+will trigger side effects to other devices in an unknown state.
416
diff --git a/docs/devel/index.rst b/docs/devel/index.rst
417
index XXXXXXX..XXXXXXX 100644
418
--- a/docs/devel/index.rst
419
+++ b/docs/devel/index.rst
420
@@ -XXX,XX +XXX,XX @@ Contents:
421
bitops
422
reset
423
s390-dasd-ipl
424
+ clocks
425
--
165
--
426
2.20.1
166
2.34.1
427
428
diff view generated by jsdifflib
New patch
[PULL 07/72] fpu: Check for default_nan_mode before calling pickNaNMulAdd
1
If the target sets default_nan_mode then we're always going to return
2
the default NaN, and pickNaNMulAdd() no longer has any side effects.
3
For consistency with pickNaN(), check for default_nan_mode before
4
calling pickNaNMulAdd().
1
5
6
When we convert pickNaNMulAdd() to allow runtime selection of the NaN
7
propagation rule, this means we won't have to make the targets which
8
use default_nan_mode also set a propagation rule.
9
10
Since RiscV always uses default_nan_mode, this allows us to remove
11
its ifdef case from pickNaNMulAdd().
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-3-peter.maydell@linaro.org
16
---
17
fpu/softfloat-parts.c.inc | 8 ++++++--
18
fpu/softfloat-specialize.c.inc | 9 +++++++--
19
2 files changed, 13 insertions(+), 4 deletions(-)
20
21
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
22
index XXXXXXX..XXXXXXX 100644
23
--- a/fpu/softfloat-parts.c.inc
24
+++ b/fpu/softfloat-parts.c.inc
25
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
26
float_raise(float_flag_invalid | float_flag_invalid_imz, s);
27
}
28
29
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
30
+ if (s->default_nan_mode) {
31
+ which = 3;
32
+ } else {
33
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ }
35
36
- if (s->default_nan_mode || which == 3) {
37
+ if (which == 3) {
38
parts_default_nan(a, s);
39
return a;
40
}
41
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
42
index XXXXXXX..XXXXXXX 100644
43
--- a/fpu/softfloat-specialize.c.inc
44
+++ b/fpu/softfloat-specialize.c.inc
45
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
46
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
47
bool infzero, float_status *status)
48
{
49
+ /*
50
+ * We guarantee not to require the target to tell us how to
51
+ * pick a NaN if we're always returning the default NaN.
52
+ * But if we're not in default-NaN mode then the target must
53
+ * specify.
54
+ */
55
+ assert(!status->default_nan_mode);
56
#if defined(TARGET_ARM)
57
/* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
58
* the default NaN
59
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
60
} else {
61
return 1;
62
}
63
-#elif defined(TARGET_RISCV)
64
- return 3; /* default NaN */
65
#elif defined(TARGET_S390X)
66
if (infzero) {
67
return 3;
68
--
69
2.34.1
diff view generated by jsdifflib
[PULL 20/31] net: cadence_gem: clear RX control descriptor
[PULL 08/72] softfloat: Allow runtime choice of inf * 0 + NaN result
1
From: Ramon Fried <rfried.dev@gmail.com>
1
IEEE 758 does not define a fixed rule for what NaN to return in
2
2
the case of a fused multiply-add of inf * 0 + NaN. Different
3
The RX ring descriptors control field is used for setting
3
architectures thus do different things:
4
SOF and EOF (start of frame and end of frame).
4
* some return the default NaN
5
The SOF and EOF weren't cleared from the previous descriptors,
5
* some return the input NaN
6
causing inconsistencies in ring buffer.
6
* Arm returns the default NaN if the input NaN is quiet,
7
Fix that by clearing the control field of every descriptors we're
7
and the input NaN if it is signalling
8
processing.
8
9
9
We want to make this logic be runtime selected rather than
10
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
10
hardcoded into the binary, because:
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
* this will let us have multiple targets in one QEMU binary
12
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
12
* the Arm FEAT_AFP architectural feature includes letting
13
Message-id: 20200418085145.489726-1-rfried.dev@gmail.com
13
the guest select a NaN propagation rule at runtime
14
15
In this commit we add an enum for the propagation rule, the field in
16
float_status, and the corresponding getters and setters. We change
17
pickNaNMulAdd to honour this, but because all targets still leave
18
this field at its default 0 value, the fallback logic will pick the
19
rule type with the old ifdef ladder.
20
21
Note that four architectures both use the muladd softfloat functions
22
and did not have a branch of the ifdef ladder to specify their
23
behaviour (and so were ending up with the "default" case, probably
24
wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set
25
default_nan_mode, and so will never get into pickNaNMulAdd(). For
26
HPPA and i386 we retain the same behaviour as the old default-case,
27
which is to not ever return the default NaN. This might not be
28
correct but it is not a behaviour change.
29
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
32
Message-id: 20241202131347.498124-4-peter.maydell@linaro.org
15
---
33
---
16
hw/net/cadence_gem.c | 7 +++++++
34
include/fpu/softfloat-helpers.h | 11 ++++
17
1 file changed, 7 insertions(+)
35
include/fpu/softfloat-types.h | 23 +++++++++
18
36
fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++-----------
19
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
37
3 files changed, 95 insertions(+), 30 deletions(-)
38
39
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
20
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/net/cadence_gem.c
41
--- a/include/fpu/softfloat-helpers.h
22
+++ b/hw/net/cadence_gem.c
42
+++ b/include/fpu/softfloat-helpers.h
23
@@ -XXX,XX +XXX,XX @@ static inline void rx_desc_set_sof(uint32_t *desc)
43
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
24
desc[1] |= DESC_1_RX_SOF;
44
status->float_2nan_prop_rule = rule;
25
}
45
}
26
46
27
+static inline void rx_desc_clear_control(uint32_t *desc)
47
+static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
48
+ float_status *status)
28
+{
49
+{
29
+ desc[1] = 0;
50
+ status->float_infzeronan_rule = rule;
30
+}
51
+}
31
+
52
+
32
static inline void rx_desc_set_eof(uint32_t *desc)
53
static inline void set_flush_to_zero(bool val, float_status *status)
33
{
54
{
34
desc[1] |= DESC_1_RX_EOF;
55
status->flush_to_zero = val;
35
@@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
56
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
36
rxbuf_ptr += MIN(bytes_to_copy, rxbufsize);
57
return status->float_2nan_prop_rule;
37
bytes_to_copy -= MIN(bytes_to_copy, rxbufsize);
58
}
38
59
39
+ rx_desc_clear_control(s->rx_desc[q]);
60
+static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
40
+
61
+{
41
/* Update the descriptor. */
62
+ return status->float_infzeronan_rule;
42
if (first_desc) {
63
+}
43
rx_desc_set_sof(s->rx_desc[q]);
64
+
65
static inline bool get_flush_to_zero(float_status *status)
66
{
67
return status->flush_to_zero;
68
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
69
index XXXXXXX..XXXXXXX 100644
70
--- a/include/fpu/softfloat-types.h
71
+++ b/include/fpu/softfloat-types.h
72
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
73
float_2nan_prop_x87,
74
} Float2NaNPropRule;
75
76
+/*
77
+ * Rule for result of fused multiply-add 0 * Inf + NaN.
78
+ * This must be a NaN, but implementations differ on whether this
79
+ * is the input NaN or the default NaN.
80
+ *
81
+ * You don't need to set this if default_nan_mode is enabled.
82
+ * When not in default-NaN mode, it is an error for the target
83
+ * not to set the rule in float_status if it uses muladd, and we
84
+ * will assert if we need to handle an input NaN and no rule was
85
+ * selected.
86
+ */
87
+typedef enum __attribute__((__packed__)) {
88
+ /* No propagation rule specified */
89
+ float_infzeronan_none = 0,
90
+ /* Result is never the default NaN (so always the input NaN) */
91
+ float_infzeronan_dnan_never,
92
+ /* Result is always the default NaN */
93
+ float_infzeronan_dnan_always,
94
+ /* Result is the default NaN if the input NaN is quiet */
95
+ float_infzeronan_dnan_if_qnan,
96
+} FloatInfZeroNaNRule;
97
+
98
/*
99
* Floating Point Status. Individual architectures may maintain
100
* several versions of float_status for different functions. The
101
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
102
FloatRoundMode float_rounding_mode;
103
FloatX80RoundPrec floatx80_rounding_precision;
104
Float2NaNPropRule float_2nan_prop_rule;
105
+ FloatInfZeroNaNRule float_infzeronan_rule;
106
bool tininess_before_rounding;
107
/* should denormalised results go to zero and set the inexact flag? */
108
bool flush_to_zero;
109
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
110
index XXXXXXX..XXXXXXX 100644
111
--- a/fpu/softfloat-specialize.c.inc
112
+++ b/fpu/softfloat-specialize.c.inc
113
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
114
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
115
bool infzero, float_status *status)
116
{
117
+ FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
118
+
119
/*
120
* We guarantee not to require the target to tell us how to
121
* pick a NaN if we're always returning the default NaN.
122
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
123
* specify.
124
*/
125
assert(!status->default_nan_mode);
126
+
127
+ if (rule == float_infzeronan_none) {
128
+ /*
129
+ * Temporarily fall back to ifdef ladder
130
+ */
131
#if defined(TARGET_ARM)
132
- /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
133
- * the default NaN
134
- */
135
- if (infzero && is_qnan(c_cls)) {
136
- return 3;
137
+ /*
138
+ * For ARM, the (inf,zero,qnan) case returns the default NaN,
139
+ * but (inf,zero,snan) returns the input NaN.
140
+ */
141
+ rule = float_infzeronan_dnan_if_qnan;
142
+#elif defined(TARGET_MIPS)
143
+ if (snan_bit_is_one(status)) {
144
+ /*
145
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
146
+ * case sets InvalidOp and returns the default NaN
147
+ */
148
+ rule = float_infzeronan_dnan_always;
149
+ } else {
150
+ /*
151
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
152
+ * case sets InvalidOp and returns the input value 'c'
153
+ */
154
+ rule = float_infzeronan_dnan_never;
155
+ }
156
+#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
157
+ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
158
+ defined(TARGET_I386) || defined(TARGET_LOONGARCH)
159
+ /*
160
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
161
+ * case sets InvalidOp and returns the input value 'c'
162
+ */
163
+ /*
164
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
165
+ * to return an input NaN if we have one (ie c) rather than generating
166
+ * a default NaN
167
+ */
168
+ rule = float_infzeronan_dnan_never;
169
+#elif defined(TARGET_S390X)
170
+ rule = float_infzeronan_dnan_always;
171
+#endif
172
}
173
174
+ if (infzero) {
175
+ /*
176
+ * Inf * 0 + NaN -- some implementations return the default NaN here,
177
+ * and some return the input NaN.
178
+ */
179
+ switch (rule) {
180
+ case float_infzeronan_dnan_never:
181
+ return 2;
182
+ case float_infzeronan_dnan_always:
183
+ return 3;
184
+ case float_infzeronan_dnan_if_qnan:
185
+ return is_qnan(c_cls) ? 3 : 2;
186
+ default:
187
+ g_assert_not_reached();
188
+ }
189
+ }
190
+
191
+#if defined(TARGET_ARM)
192
+
193
/* This looks different from the ARM ARM pseudocode, because the ARM ARM
194
* puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
195
*/
196
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
197
}
198
#elif defined(TARGET_MIPS)
199
if (snan_bit_is_one(status)) {
200
- /*
201
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
202
- * case sets InvalidOp and returns the default NaN
203
- */
204
- if (infzero) {
205
- return 3;
206
- }
207
/* Prefer sNaN over qNaN, in the a, b, c order. */
208
if (is_snan(a_cls)) {
209
return 0;
210
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
211
return 2;
212
}
213
} else {
214
- /*
215
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
216
- * case sets InvalidOp and returns the input value 'c'
217
- */
218
/* Prefer sNaN over qNaN, in the c, a, b order. */
219
if (is_snan(c_cls)) {
220
return 2;
221
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
222
}
223
}
224
#elif defined(TARGET_LOONGARCH64)
225
- /*
226
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
227
- * case sets InvalidOp and returns the input value 'c'
228
- */
229
-
230
/* Prefer sNaN over qNaN, in the c, a, b order. */
231
if (is_snan(c_cls)) {
232
return 2;
233
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
234
return 1;
235
}
236
#elif defined(TARGET_PPC)
237
- /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
238
- * to return an input NaN if we have one (ie c) rather than generating
239
- * a default NaN
240
- */
241
-
242
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
243
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
244
*/
245
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
246
return 1;
247
}
248
#elif defined(TARGET_S390X)
249
- if (infzero) {
250
- return 3;
251
- }
252
-
253
if (is_snan(a_cls)) {
254
return 0;
255
} else if (is_snan(b_cls)) {
44
--
256
--
45
2.20.1
257
2.34.1
46
47
diff view generated by jsdifflib
New patch
[PULL 09/72] tests/fp: Explicitly set inf-zero-nan rule
1
Explicitly set a rule in the softfloat tests for the inf-zero-nan
2
muladd special case. In meson.build we put -DTARGET_ARM in fpcflags,
3
and so we should select here the Arm rule of
4
float_infzeronan_dnan_if_qnan.
1
5
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241202131347.498124-5-peter.maydell@linaro.org
9
---
10
tests/fp/fp-bench.c | 5 +++++
11
tests/fp/fp-test.c | 5 +++++
12
2 files changed, 10 insertions(+)
13
14
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tests/fp/fp-bench.c
17
+++ b/tests/fp/fp-bench.c
18
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
19
{
20
bench_func_t f;
21
22
+ /*
23
+ * These implementation-defined choices for various things IEEE
24
+ * doesn't specify match those used by the Arm architecture.
25
+ */
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
28
29
f = bench_funcs[operation][precision];
30
g_assert(f);
31
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/tests/fp/fp-test.c
34
+++ b/tests/fp/fp-test.c
35
@@ -XXX,XX +XXX,XX @@ void run_test(void)
36
{
37
unsigned int i;
38
39
+ /*
40
+ * These implementation-defined choices for various things IEEE
41
+ * doesn't specify match those used by the Arm architecture.
42
+ */
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
44
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
45
46
genCases_setLevel(test_level);
47
verCases_maxErrorCount = n_max_errors;
48
--
49
2.34.1
diff view generated by jsdifflib
[PULL 27/31] target/arm/cpu: Update coding style to make checkpatch.pl happy
[PULL 10/72] target/arm: Set FloatInfZeroNaNRule explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the FloatInfZeroNaNRule explicitly for the Arm target,
2
so we can remove the ifdef from pickNaNMulAdd().
2
3
3
We will move this code in the next commit. Clean it up
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
first to avoid checkpatch.pl errors.
5
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Message-id: 20241202131347.498124-6-peter.maydell@linaro.org
8
Message-id: 20200423073358.27155-5-philmd@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
7
---
11
target/arm/cpu.c | 9 ++++++---
8
target/arm/cpu.c | 3 +++
12
1 file changed, 6 insertions(+), 3 deletions(-)
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 4 insertions(+), 7 deletions(-)
13
11
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
14
--- a/target/arm/cpu.c
17
+++ b/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
18
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
19
CPUARMState *env = &cpu->env;
17
* * tininess-before-rounding
20
bool ret = false;
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
21
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
22
- /* ARMv7-M interrupt masking works differently than -A or -R.
20
+ * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
23
+ /*
21
+ * and the input NaN if it is signalling
24
+ * ARMv7-M interrupt masking works differently than -A or -R.
22
*/
25
* There is no FIQ/IRQ distinction. Instead of I and F bits
23
static void arm_set_default_fp_behaviours(float_status *s)
26
* masking FIQ and IRQ interrupts, an exception is taken only
27
* if it is higher priority than the current execution priority
28
@@ -XXX,XX +XXX,XX @@ static void arm1026_initfn(Object *obj)
29
static void arm1136_r2_initfn(Object *obj)
30
{
24
{
31
ARMCPU *cpu = ARM_CPU(obj);
25
set_float_detect_tininess(float_tininess_before_rounding, s);
32
- /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
33
+ /*
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
34
+ * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
28
}
35
* older core than plain "arm1136". In particular this does not
29
36
* have the v6K features.
30
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
37
* These ID register values are correct for 1136 but may be wrong
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
38
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {
32
index XXXXXXX..XXXXXXX 100644
39
{ .name = "arm926", .initfn = arm926_initfn },
33
--- a/fpu/softfloat-specialize.c.inc
40
{ .name = "arm946", .initfn = arm946_initfn },
34
+++ b/fpu/softfloat-specialize.c.inc
41
{ .name = "arm1026", .initfn = arm1026_initfn },
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
42
- /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
36
/*
43
+ /*
37
* Temporarily fall back to ifdef ladder
44
+ * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
38
*/
45
* older core than plain "arm1136". In particular this does not
39
-#if defined(TARGET_ARM)
46
* have the v6K features.
40
- /*
47
*/
41
- * For ARM, the (inf,zero,qnan) case returns the default NaN,
42
- * but (inf,zero,snan) returns the input NaN.
43
- */
44
- rule = float_infzeronan_dnan_if_qnan;
45
-#elif defined(TARGET_MIPS)
46
+#if defined(TARGET_MIPS)
47
if (snan_bit_is_one(status)) {
48
/*
49
* For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
48
--
50
--
49
2.20.1
51
2.34.1
50
51
diff view generated by jsdifflib
New patch
[PULL 11/72] target/s390: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for s390, so we
2
can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-7-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_infzeronan_rule(float_infzeronan_dnan_always,
21
+ &env->fpu_status);
22
/* fall through */
23
case RESET_TYPE_S390_CPU_NORMAL:
24
env->psw.mask &= ~PSW_MASK_RI;
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
* a default NaN
31
*/
32
rule = float_infzeronan_dnan_never;
33
-#elif defined(TARGET_S390X)
34
- rule = float_infzeronan_dnan_always;
35
#endif
36
}
37
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/72] target/ppc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the PPC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-8-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 7 +++++++
9
fpu/softfloat-specialize.c.inc | 7 +------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
22
+ * to return an input NaN if we have one (ie c) rather than generating
23
+ * a default NaN
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
27
28
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
29
ppc_spr_t *spr = &env->spr_cb[i];
30
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
31
index XXXXXXX..XXXXXXX 100644
32
--- a/fpu/softfloat-specialize.c.inc
33
+++ b/fpu/softfloat-specialize.c.inc
34
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
*/
36
rule = float_infzeronan_dnan_never;
37
}
38
-#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
39
+#elif defined(TARGET_SPARC) || \
40
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
41
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
42
/*
43
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
44
* case sets InvalidOp and returns the input value 'c'
45
*/
46
- /*
47
- * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
48
- * to return an input NaN if we have one (ie c) rather than generating
49
- * a default NaN
50
- */
51
rule = float_infzeronan_dnan_never;
52
#endif
53
}
54
--
55
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/72] target/mips: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the MIPS target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-9-peter.maydell@linaro.org
7
---
8
target/mips/fpu_helper.h | 9 +++++++++
9
target/mips/msa.c | 4 ++++
10
fpu/softfloat-specialize.c.inc | 16 +---------------
11
3 files changed, 14 insertions(+), 15 deletions(-)
12
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/mips/fpu_helper.h
16
+++ b/target/mips/fpu_helper.h
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_flush_mode(CPUMIPSState *env)
18
static inline void restore_snan_bit_mode(CPUMIPSState *env)
19
{
20
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
21
+ FloatInfZeroNaNRule izn_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status);
28
set_default_nan_mode(!nan2008, &env->active_fpu.fp_status);
29
+ /*
30
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
31
+ * case sets InvalidOp and returns the default NaN.
32
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
33
+ * case sets InvalidOp and returns the input value 'c'.
34
+ */
35
+ izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
36
+ set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
37
}
38
39
static inline void restore_fp_status(CPUMIPSState *env)
40
diff --git a/target/mips/msa.c b/target/mips/msa.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/mips/msa.c
43
+++ b/target/mips/msa.c
44
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
45
46
/* set proper signanling bit meaning ("1" means "quiet") */
47
set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
48
+
49
+ /* Inf * 0 + NaN returns the input NaN */
50
+ set_float_infzeronan_rule(float_infzeronan_dnan_never,
51
+ &env->active_tc.msa_fp_status);
52
}
53
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
54
index XXXXXXX..XXXXXXX 100644
55
--- a/fpu/softfloat-specialize.c.inc
56
+++ b/fpu/softfloat-specialize.c.inc
57
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
58
/*
59
* Temporarily fall back to ifdef ladder
60
*/
61
-#if defined(TARGET_MIPS)
62
- if (snan_bit_is_one(status)) {
63
- /*
64
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
65
- * case sets InvalidOp and returns the default NaN
66
- */
67
- rule = float_infzeronan_dnan_always;
68
- } else {
69
- /*
70
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
71
- * case sets InvalidOp and returns the input value 'c'
72
- */
73
- rule = float_infzeronan_dnan_never;
74
- }
75
-#elif defined(TARGET_SPARC) || \
76
+#if defined(TARGET_SPARC) || \
77
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
78
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
79
/*
80
--
81
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/72] target/sparc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the SPARC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-10-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_SPARC) || \
34
- defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
35
+#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
36
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
37
/*
38
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/72] target/xtensa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the xtensa target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-11-peter.maydell@linaro.org
7
---
8
target/xtensa/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 +-
10
2 files changed, 3 insertions(+), 1 deletion(-)
11
12
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/xtensa/cpu.c
15
+++ b/target/xtensa/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
17
reset_mmu(env);
18
cs->halted = env->runstall;
19
#endif
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
set_no_signaling_nans(!dfpu, &env->fp_status);
23
xtensa_use_first_nan(env, !dfpu);
24
}
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
34
+#if defined(TARGET_HPPA) || \
35
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
36
/*
37
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 16/72] target/x86: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the x86 target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-12-peter.maydell@linaro.org
6
---
7
target/i386/tcg/fpu_helper.c | 7 +++++++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 8 insertions(+), 1 deletion(-)
10
11
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/i386/tcg/fpu_helper.c
14
+++ b/target/i386/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status);
18
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status);
19
+ /*
20
+ * Only SSE has multiply-add instructions. In the SDM Section 14.5.2
21
+ * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is
22
+ * specified -- for 0 * inf + NaN the input NaN is selected, and if
23
+ * there are multiple input NaNs they are selected in the order a, b, c.
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
26
}
27
28
static inline uint8_t save_exception_flags(CPUX86State *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
34
* Temporarily fall back to ifdef ladder
35
*/
36
#if defined(TARGET_HPPA) || \
37
- defined(TARGET_I386) || defined(TARGET_LOONGARCH)
38
+ defined(TARGET_LOONGARCH)
39
/*
40
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
41
* case sets InvalidOp and returns the input value 'c'
42
--
43
2.34.1
diff view generated by jsdifflib
New patch
[PULL 17/72] target/loongarch: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the loongarch target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-13-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 5 +++++
8
fpu/softfloat-specialize.c.inc | 7 +------
9
2 files changed, 6 insertions(+), 6 deletions(-)
10
11
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/loongarch/tcg/fpu_helper.c
14
+++ b/target/loongarch/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
16
&env->fp_status);
17
set_flush_to_zero(0, &env->fp_status);
18
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
19
+ /*
20
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
21
+ * case sets InvalidOp and returns the input value 'c'
22
+ */
23
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
}
25
26
int ieee_ex_to_loongarch(int xcpt)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
32
/*
33
* Temporarily fall back to ifdef ladder
34
*/
35
-#if defined(TARGET_HPPA) || \
36
- defined(TARGET_LOONGARCH)
37
- /*
38
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
- * case sets InvalidOp and returns the input value 'c'
40
- */
41
+#if defined(TARGET_HPPA)
42
rule = float_infzeronan_dnan_never;
43
#endif
44
}
45
--
46
2.34.1
diff view generated by jsdifflib
New patch
[PULL 18/72] target/hppa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the HPPA target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
As this is the last target to be converted to explicitly setting
5
the rule, we can remove the fallback code in pickNaNMulAdd()
6
entirely.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20241202131347.498124-14-peter.maydell@linaro.org
11
---
12
target/hppa/fpu_helper.c | 2 ++
13
fpu/softfloat-specialize.c.inc | 13 +------------
14
2 files changed, 3 insertions(+), 12 deletions(-)
15
16
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/hppa/fpu_helper.c
19
+++ b/target/hppa/fpu_helper.c
20
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
21
* HPPA does note implement a CPU reset method at all...
22
*/
23
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
24
+ /* For inf * 0 + NaN, return the input NaN */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
}
27
28
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
34
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
bool infzero, float_status *status)
36
{
37
- FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
38
-
39
/*
40
* We guarantee not to require the target to tell us how to
41
* pick a NaN if we're always returning the default NaN.
42
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
43
*/
44
assert(!status->default_nan_mode);
45
46
- if (rule == float_infzeronan_none) {
47
- /*
48
- * Temporarily fall back to ifdef ladder
49
- */
50
-#if defined(TARGET_HPPA)
51
- rule = float_infzeronan_dnan_never;
52
-#endif
53
- }
54
-
55
if (infzero) {
56
/*
57
* Inf * 0 + NaN -- some implementations return the default NaN here,
58
* and some return the input NaN.
59
*/
60
- switch (rule) {
61
+ switch (status->float_infzeronan_rule) {
62
case float_infzeronan_dnan_never:
63
return 2;
64
case float_infzeronan_dnan_always:
65
--
66
2.34.1
diff view generated by jsdifflib
New patch
[PULL 19/72] softfloat: Pass have_snan to pickNaNMulAdd
1
The new implementation of pickNaNMulAdd() will find it convenient
2
to know whether at least one of the three arguments to the muladd
3
was a signaling NaN. We already calculate that in the caller,
4
so pass it in as a new bool have_snan.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-15-peter.maydell@linaro.org
9
---
10
fpu/softfloat-parts.c.inc | 5 +++--
11
fpu/softfloat-specialize.c.inc | 2 +-
12
2 files changed, 4 insertions(+), 3 deletions(-)
13
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
16
--- a/fpu/softfloat-parts.c.inc
17
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
{
20
int which;
21
bool infzero = (ab_mask == float_cmask_infzero);
22
+ bool have_snan = (abc_mask & float_cmask_snan);
23
24
- if (unlikely(abc_mask & float_cmask_snan)) {
25
+ if (unlikely(have_snan)) {
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
27
}
28
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
30
if (s->default_nan_mode) {
31
which = 3;
32
} else {
33
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
35
}
36
37
if (which == 3) {
38
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
39
index XXXXXXX..XXXXXXX 100644
40
--- a/fpu/softfloat-specialize.c.inc
41
+++ b/fpu/softfloat-specialize.c.inc
42
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
43
| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
44
*----------------------------------------------------------------------------*/
45
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
46
- bool infzero, float_status *status)
47
+ bool infzero, bool have_snan, float_status *status)
48
{
49
/*
50
* We guarantee not to require the target to tell us how to
51
--
52
2.34.1
diff view generated by jsdifflib
[PULL 02/31] dma/xlnx-zdma: Fix descriptor loading (REG) wrt endianness
[PULL 20/72] softfloat: Allow runtime choice of NaN propagation for muladd
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
IEEE 758 does not define a fixed rule for which NaN to pick as the
2
2
result if both operands of a 3-operand fused multiply-add operation
3
Fix descriptor loading from registers wrt host endianness.
3
are NaNs. As a result different architectures have ended up with
4
4
different rules for propagating NaNs.
5
Reported-by: Peter Maydell <peter.maydell@linaro.org>
5
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
QEMU currently hardcodes the NaN propagation logic into the binary
7
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
7
because pickNaNMulAdd() has an ifdef ladder for different targets.
8
Message-id: 20200404122718.25111-3-edgar.iglesias@gmail.com
8
We want to make the propagation rule instead be selectable at
9
runtime, because:
10
* this will let us have multiple targets in one QEMU binary
11
* the Arm FEAT_AFP architectural feature includes letting
12
the guest select a NaN propagation rule at runtime
13
14
In this commit we add an enum for the propagation rule, the field in
15
float_status, and the corresponding getters and setters. We change
16
pickNaNMulAdd to honour this, but because all targets still leave
17
this field at its default 0 value, the fallback logic will pick the
18
rule type with the old ifdef ladder.
19
20
It's valid not to set a propagation rule if default_nan_mode is
21
enabled, because in that case there's no need to pick a NaN; all the
22
callers of pickNaNMulAdd() catch this case and skip calling it.
23
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20241202131347.498124-16-peter.maydell@linaro.org
10
---
27
---
11
hw/dma/xlnx-zdma.c | 14 ++++++++++----
28
include/fpu/softfloat-helpers.h | 11 +++
12
1 file changed, 10 insertions(+), 4 deletions(-)
29
include/fpu/softfloat-types.h | 55 +++++++++++
13
30
fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------
14
diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
31
3 files changed, 107 insertions(+), 126 deletions(-)
32
33
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
15
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/dma/xlnx-zdma.c
35
--- a/include/fpu/softfloat-helpers.h
17
+++ b/hw/dma/xlnx-zdma.c
36
+++ b/include/fpu/softfloat-helpers.h
18
@@ -XXX,XX +XXX,XX @@ static void zdma_put_regaddr64(XlnxZDMA *s, unsigned int basereg, uint64_t addr)
37
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
19
s->regs[basereg + 1] = addr >> 32;
38
status->float_2nan_prop_rule = rule;
20
}
39
}
21
40
22
+static void zdma_load_descriptor_reg(XlnxZDMA *s, unsigned int reg,
41
+static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule,
23
+ XlnxZDMADescr *descr)
42
+ float_status *status)
24
+{
43
+{
25
+ descr->addr = zdma_get_regaddr64(s, reg);
44
+ status->float_3nan_prop_rule = rule;
26
+ descr->size = s->regs[reg + 2];
27
+ descr->attr = s->regs[reg + 3];
28
+}
45
+}
29
+
46
+
30
static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr,
47
static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
31
XlnxZDMADescr *descr)
48
float_status *status)
32
{
49
{
33
@@ -XXX,XX +XXX,XX @@ static void zdma_load_src_descriptor(XlnxZDMA *s)
50
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
34
unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE);
51
return status->float_2nan_prop_rule;
35
52
}
36
if (ptype == PT_REG) {
53
37
- memcpy(&s->dsc_src, &s->regs[R_ZDMA_CH_SRC_DSCR_WORD0],
54
+static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status)
38
- sizeof(s->dsc_src));
55
+{
39
+ zdma_load_descriptor_reg(s, R_ZDMA_CH_SRC_DSCR_WORD0, &s->dsc_src);
56
+ return status->float_3nan_prop_rule;
40
return;
57
+}
58
+
59
static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
60
{
61
return status->float_infzeronan_rule;
62
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/include/fpu/softfloat-types.h
65
+++ b/include/fpu/softfloat-types.h
66
@@ -XXX,XX +XXX,XX @@ this code that are retained.
67
#ifndef SOFTFLOAT_TYPES_H
68
#define SOFTFLOAT_TYPES_H
69
70
+#include "hw/registerfields.h"
71
+
72
/*
73
* Software IEC/IEEE floating-point types.
74
*/
75
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
76
float_2nan_prop_x87,
77
} Float2NaNPropRule;
78
79
+/*
80
+ * 3-input NaN propagation rule, for fused multiply-add. Individual
81
+ * architectures have different rules for which input NaN is
82
+ * propagated to the output when there is more than one NaN on the
83
+ * input.
84
+ *
85
+ * If default_nan_mode is enabled then it is valid not to set a NaN
86
+ * propagation rule, because the softfloat code guarantees not to try
87
+ * to pick a NaN to propagate in default NaN mode. When not in
88
+ * default-NaN mode, it is an error for the target not to set the rule
89
+ * in float_status if it uses a muladd, and we will assert if we need
90
+ * to handle an input NaN and no rule was selected.
91
+ *
92
+ * The naming scheme for Float3NaNPropRule values is:
93
+ * float_3nan_prop_s_abc:
94
+ * = "Prefer SNaN over QNaN, then operand A over B over C"
95
+ * float_3nan_prop_abc:
96
+ * = "Prefer A over B over C regardless of SNaN vs QNAN"
97
+ *
98
+ * For QEMU, the multiply-add operation is A * B + C.
99
+ */
100
+
101
+/*
102
+ * We set the Float3NaNPropRule enum values up so we can select the
103
+ * right value in pickNaNMulAdd in a data driven way.
104
+ */
105
+FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */
106
+FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */
107
+FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */
108
+FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */
109
+
110
+#define PROPRULE(X, Y, Z) \
111
+ ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT))
112
+
113
+typedef enum __attribute__((__packed__)) {
114
+ float_3nan_prop_none = 0, /* No propagation rule specified */
115
+ float_3nan_prop_abc = PROPRULE(0, 1, 2),
116
+ float_3nan_prop_acb = PROPRULE(0, 2, 1),
117
+ float_3nan_prop_bac = PROPRULE(1, 0, 2),
118
+ float_3nan_prop_bca = PROPRULE(1, 2, 0),
119
+ float_3nan_prop_cab = PROPRULE(2, 0, 1),
120
+ float_3nan_prop_cba = PROPRULE(2, 1, 0),
121
+ float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK,
122
+ float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK,
123
+ float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK,
124
+ float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK,
125
+ float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK,
126
+ float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK,
127
+} Float3NaNPropRule;
128
+
129
+#undef PROPRULE
130
+
131
/*
132
* Rule for result of fused multiply-add 0 * Inf + NaN.
133
* This must be a NaN, but implementations differ on whether this
134
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
135
FloatRoundMode float_rounding_mode;
136
FloatX80RoundPrec floatx80_rounding_precision;
137
Float2NaNPropRule float_2nan_prop_rule;
138
+ Float3NaNPropRule float_3nan_prop_rule;
139
FloatInfZeroNaNRule float_infzeronan_rule;
140
bool tininess_before_rounding;
141
/* should denormalised results go to zero and set the inexact flag? */
142
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
143
index XXXXXXX..XXXXXXX 100644
144
--- a/fpu/softfloat-specialize.c.inc
145
+++ b/fpu/softfloat-specialize.c.inc
146
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
147
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
148
bool infzero, bool have_snan, float_status *status)
149
{
150
+ FloatClass cls[3] = { a_cls, b_cls, c_cls };
151
+ Float3NaNPropRule rule = status->float_3nan_prop_rule;
152
+ int which;
153
+
154
/*
155
* We guarantee not to require the target to tell us how to
156
* pick a NaN if we're always returning the default NaN.
157
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
158
}
41
}
159
}
42
160
43
@@ -XXX,XX +XXX,XX @@ static void zdma_load_dst_descriptor(XlnxZDMA *s)
161
+ if (rule == float_3nan_prop_none) {
44
bool dst_type;
162
#if defined(TARGET_ARM)
45
163
-
46
if (ptype == PT_REG) {
164
- /* This looks different from the ARM ARM pseudocode, because the ARM ARM
47
- memcpy(&s->dsc_dst, &s->regs[R_ZDMA_CH_DST_DSCR_WORD0],
165
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
48
- sizeof(s->dsc_dst));
166
- */
49
+ zdma_load_descriptor_reg(s, R_ZDMA_CH_DST_DSCR_WORD0, &s->dsc_dst);
167
- if (is_snan(c_cls)) {
50
return;
168
- return 2;
51
}
169
- } else if (is_snan(a_cls)) {
52
170
- return 0;
171
- } else if (is_snan(b_cls)) {
172
- return 1;
173
- } else if (is_qnan(c_cls)) {
174
- return 2;
175
- } else if (is_qnan(a_cls)) {
176
- return 0;
177
- } else {
178
- return 1;
179
- }
180
+ /*
181
+ * This looks different from the ARM ARM pseudocode, because the ARM ARM
182
+ * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
183
+ */
184
+ rule = float_3nan_prop_s_cab;
185
#elif defined(TARGET_MIPS)
186
- if (snan_bit_is_one(status)) {
187
- /* Prefer sNaN over qNaN, in the a, b, c order. */
188
- if (is_snan(a_cls)) {
189
- return 0;
190
- } else if (is_snan(b_cls)) {
191
- return 1;
192
- } else if (is_snan(c_cls)) {
193
- return 2;
194
- } else if (is_qnan(a_cls)) {
195
- return 0;
196
- } else if (is_qnan(b_cls)) {
197
- return 1;
198
+ if (snan_bit_is_one(status)) {
199
+ rule = float_3nan_prop_s_abc;
200
} else {
201
- return 2;
202
+ rule = float_3nan_prop_s_cab;
203
}
204
- } else {
205
- /* Prefer sNaN over qNaN, in the c, a, b order. */
206
- if (is_snan(c_cls)) {
207
- return 2;
208
- } else if (is_snan(a_cls)) {
209
- return 0;
210
- } else if (is_snan(b_cls)) {
211
- return 1;
212
- } else if (is_qnan(c_cls)) {
213
- return 2;
214
- } else if (is_qnan(a_cls)) {
215
- return 0;
216
- } else {
217
- return 1;
218
- }
219
- }
220
#elif defined(TARGET_LOONGARCH64)
221
- /* Prefer sNaN over qNaN, in the c, a, b order. */
222
- if (is_snan(c_cls)) {
223
- return 2;
224
- } else if (is_snan(a_cls)) {
225
- return 0;
226
- } else if (is_snan(b_cls)) {
227
- return 1;
228
- } else if (is_qnan(c_cls)) {
229
- return 2;
230
- } else if (is_qnan(a_cls)) {
231
- return 0;
232
- } else {
233
- return 1;
234
- }
235
+ rule = float_3nan_prop_s_cab;
236
#elif defined(TARGET_PPC)
237
- /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
238
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
239
- */
240
- if (is_nan(a_cls)) {
241
- return 0;
242
- } else if (is_nan(c_cls)) {
243
- return 2;
244
- } else {
245
- return 1;
246
- }
247
+ /*
248
+ * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
249
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
250
+ */
251
+ rule = float_3nan_prop_acb;
252
#elif defined(TARGET_S390X)
253
- if (is_snan(a_cls)) {
254
- return 0;
255
- } else if (is_snan(b_cls)) {
256
- return 1;
257
- } else if (is_snan(c_cls)) {
258
- return 2;
259
- } else if (is_qnan(a_cls)) {
260
- return 0;
261
- } else if (is_qnan(b_cls)) {
262
- return 1;
263
- } else {
264
- return 2;
265
- }
266
+ rule = float_3nan_prop_s_abc;
267
#elif defined(TARGET_SPARC)
268
- /* Prefer SNaN over QNaN, order C, B, A. */
269
- if (is_snan(c_cls)) {
270
- return 2;
271
- } else if (is_snan(b_cls)) {
272
- return 1;
273
- } else if (is_snan(a_cls)) {
274
- return 0;
275
- } else if (is_qnan(c_cls)) {
276
- return 2;
277
- } else if (is_qnan(b_cls)) {
278
- return 1;
279
- } else {
280
- return 0;
281
- }
282
+ rule = float_3nan_prop_s_cba;
283
#elif defined(TARGET_XTENSA)
284
- /*
285
- * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
286
- * an input NaN if we have one (ie c).
287
- */
288
- if (status->use_first_nan) {
289
- if (is_nan(a_cls)) {
290
- return 0;
291
- } else if (is_nan(b_cls)) {
292
- return 1;
293
+ if (status->use_first_nan) {
294
+ rule = float_3nan_prop_abc;
295
} else {
296
- return 2;
297
+ rule = float_3nan_prop_cba;
298
}
299
- } else {
300
- if (is_nan(c_cls)) {
301
- return 2;
302
- } else if (is_nan(b_cls)) {
303
- return 1;
304
- } else {
305
- return 0;
306
- }
307
- }
308
#else
309
- /* A default implementation: prefer a to b to c.
310
- * This is unlikely to actually match any real implementation.
311
- */
312
- if (is_nan(a_cls)) {
313
- return 0;
314
- } else if (is_nan(b_cls)) {
315
- return 1;
316
- } else {
317
- return 2;
318
- }
319
+ rule = float_3nan_prop_abc;
320
#endif
321
+ }
322
+
323
+ assert(rule != float_3nan_prop_none);
324
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
325
+ /* We have at least one SNaN input and should prefer it */
326
+ do {
327
+ which = rule & R_3NAN_1ST_MASK;
328
+ rule >>= R_3NAN_1ST_LENGTH;
329
+ } while (!is_snan(cls[which]));
330
+ } else {
331
+ do {
332
+ which = rule & R_3NAN_1ST_MASK;
333
+ rule >>= R_3NAN_1ST_LENGTH;
334
+ } while (!is_nan(cls[which]));
335
+ }
336
+ return which;
337
}
338
339
/*----------------------------------------------------------------------------
53
--
340
--
54
2.20.1
341
2.34.1
55
56
diff view generated by jsdifflib
New patch
[PULL 21/72] tests/fp: Explicitly set 3-NaN propagation rule
1
Explicitly set a rule in the softfloat tests for propagating NaNs in
2
the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and
3
so we should select here the Arm rule of float_3nan_prop_s_cab.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-17-peter.maydell@linaro.org
8
---
9
tests/fp/fp-bench.c | 1 +
10
tests/fp/fp-test.c | 1 +
11
2 files changed, 2 insertions(+)
12
13
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/tests/fp/fp-bench.c
16
+++ b/tests/fp/fp-bench.c
17
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
18
* doesn't specify match those used by the Arm architecture.
19
*/
20
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
22
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
23
24
f = bench_funcs[operation][precision];
25
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/tests/fp/fp-test.c
28
+++ b/tests/fp/fp-test.c
29
@@ -XXX,XX +XXX,XX @@ void run_test(void)
30
* doesn't specify match those used by the Arm architecture.
31
*/
32
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
33
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
34
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
35
36
genCases_setLevel(test_level);
37
--
38
2.34.1
diff view generated by jsdifflib
[PULL 26/31] target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]
[PULL 22/72] target/arm: Set Float3NaNPropRule explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Message-id: 20241202131347.498124-18-peter.maydell@linaro.org
6
Message-id: 20200423073358.27155-4-philmd@redhat.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
7
---
9
target/arm/cpu.c | 8 +++-----
8
target/arm/cpu.c | 5 +++++
10
target/arm/cpu64.c | 8 +++-----
9
fpu/softfloat-specialize.c.inc | 8 +-------
11
2 files changed, 6 insertions(+), 10 deletions(-)
10
2 files changed, 6 insertions(+), 7 deletions(-)
12
11
13
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
14
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.c
14
--- a/target/arm/cpu.c
16
+++ b/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
17
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
18
{ .name = "any", .initfn = arm_max_initfn },
17
* * tininess-before-rounding
19
#endif
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
20
#endif
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
21
- { .name = NULL }
20
+ * * 3-input NaN propagation prefers SNaN over QNaN, and then
22
};
21
+ * operand C over A over B (see FPProcessNaNs3() pseudocode,
23
22
+ * but note that for QEMU muladd is a * b + c, whereas for
24
static Property arm_cpu_properties[] = {
23
+ * the pseudocode function the arguments are in the order c, a, b.
25
@@ -XXX,XX +XXX,XX @@ static const TypeInfo idau_interface_type_info = {
24
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
26
25
* and the input NaN if it is signalling
27
static void arm_cpu_register_types(void)
26
*/
27
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
28
{
28
{
29
- const ARMCPUInfo *info = arm_cpus;
29
set_float_detect_tininess(float_tininess_before_rounding, s);
30
+ size_t i;
30
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
31
31
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
32
type_register_static(&arm_cpu_type_info);
32
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
33
type_register_static(&idau_interface_type_info);
33
}
34
34
35
- while (info->name) {
35
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
36
- arm_cpu_register(info);
36
index XXXXXXX..XXXXXXX 100644
37
- info++;
37
--- a/fpu/softfloat-specialize.c.inc
38
+ for (i = 0; i < ARRAY_SIZE(arm_cpus); ++i) {
38
+++ b/fpu/softfloat-specialize.c.inc
39
+ arm_cpu_register(&arm_cpus[i]);
39
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
40
}
40
}
41
41
42
#ifdef CONFIG_KVM
42
if (rule == float_3nan_prop_none) {
43
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
43
-#if defined(TARGET_ARM)
44
index XXXXXXX..XXXXXXX 100644
44
- /*
45
--- a/target/arm/cpu64.c
45
- * This looks different from the ARM ARM pseudocode, because the ARM ARM
46
+++ b/target/arm/cpu64.c
46
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
47
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
47
- */
48
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
48
- rule = float_3nan_prop_s_cab;
49
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
49
-#elif defined(TARGET_MIPS)
50
{ .name = "max", .initfn = aarch64_max_initfn },
50
+#if defined(TARGET_MIPS)
51
- { .name = NULL }
51
if (snan_bit_is_one(status)) {
52
};
52
rule = float_3nan_prop_s_abc;
53
53
} else {
54
static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
55
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aarch64_cpu_type_info = {
56
57
static void aarch64_cpu_register_types(void)
58
{
59
- const ARMCPUInfo *info = aarch64_cpus;
60
+ size_t i;
61
62
type_register_static(&aarch64_cpu_type_info);
63
64
- while (info->name) {
65
- aarch64_cpu_register(info);
66
- info++;
67
+ for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
68
+ aarch64_cpu_register(&aarch64_cpus[i]);
69
}
70
}
71
72
--
54
--
73
2.20.1
55
2.34.1
74
75
diff view generated by jsdifflib
New patch
[PULL 23/72] target/loongarch: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for loongarch, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-19-peter.maydell@linaro.org
7
---
8
target/loongarch/tcg/fpu_helper.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/loongarch/tcg/fpu_helper.c
15
+++ b/target/loongarch/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
17
* case sets InvalidOp and returns the input value 'c'
18
*/
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
21
}
22
23
int ieee_ex_to_loongarch(int xcpt)
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_LOONGARCH64)
33
- rule = float_3nan_prop_s_cab;
34
#elif defined(TARGET_PPC)
35
/*
36
* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 24/72] target/ppc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for PPC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-20-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 8 ++++++++
9
fpu/softfloat-specialize.c.inc | 6 ------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * NaN propagation for fused multiply-add:
22
+ * if fRA is a NaN return it; otherwise if fRB is a NaN return it;
23
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
24
+ * whereas QEMU labels the operands as (a * b) + c.
25
+ */
26
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status);
27
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status);
28
/*
29
* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
30
* to return an input NaN if we have one (ie c) rather than generating
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
32
index XXXXXXX..XXXXXXX 100644
33
--- a/fpu/softfloat-specialize.c.inc
34
+++ b/fpu/softfloat-specialize.c.inc
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
36
} else {
37
rule = float_3nan_prop_s_cab;
38
}
39
-#elif defined(TARGET_PPC)
40
- /*
41
- * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
42
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
43
- */
44
- rule = float_3nan_prop_acb;
45
#elif defined(TARGET_S390X)
46
rule = float_3nan_prop_s_abc;
47
#elif defined(TARGET_SPARC)
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 25/72] target/s390x: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for s390x, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-21-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
21
set_float_infzeronan_rule(float_infzeronan_dnan_always,
22
&env->fpu_status);
23
/* fall through */
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_S390X)
33
- rule = float_3nan_prop_s_abc;
34
#elif defined(TARGET_SPARC)
35
rule = float_3nan_prop_s_cba;
36
#elif defined(TARGET_XTENSA)
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 26/72] target/sparc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for SPARC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-22-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
22
/* For inf * 0 + NaN, return the input NaN */
23
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
} else {
31
rule = float_3nan_prop_s_cab;
32
}
33
-#elif defined(TARGET_SPARC)
34
- rule = float_3nan_prop_s_cba;
35
#elif defined(TARGET_XTENSA)
36
if (status->use_first_nan) {
37
rule = float_3nan_prop_abc;
38
--
39
2.34.1
diff view generated by jsdifflib
[PULL 23/31] hw/arm/virt: dt: add kaslr-seed property
[PULL 27/72] target/mips: Set Float3NaNPropRule explicitly
1
From: Jerome Forissier <jerome@forissier.org>
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Generate random seeds to be used by the non-secure and/or secure OSes
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
for ASLR. The seeds are 64-bit random values exported via the DT
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
properties /chosen/kaslr-seed [1] and /secure-chosen/kaslr-seed, the
6
Message-id: 20241202131347.498124-23-peter.maydell@linaro.org
6
latter being used by OP-TEE [2].
7
---
8
target/mips/fpu_helper.h | 4 ++++
9
target/mips/msa.c | 3 +++
10
fpu/softfloat-specialize.c.inc | 8 +-------
11
3 files changed, 8 insertions(+), 7 deletions(-)
7
12
8
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e5bc0c37c97e1
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
9
[2] https://github.com/OP-TEE/optee_os/commit/ef262691fe0e
10
11
Signed-off-by: Jerome Forissier <jerome@forissier.org>
12
Message-id: 20200420121807.8204-3-jerome@forissier.org
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/arm/virt.c | 15 +++++++++++++++
17
1 file changed, 15 insertions(+)
18
19
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
20
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/virt.c
15
--- a/target/mips/fpu_helper.h
22
+++ b/hw/arm/virt.c
16
+++ b/target/mips/fpu_helper.h
23
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
24
#include "hw/acpi/generic_event_device.h"
18
{
25
#include "hw/virtio/virtio-iommu.h"
19
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
26
#include "hw/char/pl011.h"
20
FloatInfZeroNaNRule izn_rule;
27
+#include "qemu/guest-random.h"
21
+ Float3NaNPropRule nan3_rule;
28
22
29
#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
23
/*
30
static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
24
* With nan2008, SNaNs are silenced in the usual way.
31
@@ -XXX,XX +XXX,XX @@ static bool cpu_type_valid(const char *cpu)
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
32
return false;
26
*/
27
izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
28
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
29
+ nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
30
+ set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
31
+
33
}
32
}
34
33
35
+static void create_kaslr_seed(VirtMachineState *vms, const char *node)
34
static inline void restore_fp_status(CPUMIPSState *env)
36
+{
35
diff --git a/target/mips/msa.c b/target/mips/msa.c
37
+ Error *err = NULL;
36
index XXXXXXX..XXXXXXX 100644
38
+ uint64_t seed;
37
--- a/target/mips/msa.c
38
+++ b/target/mips/msa.c
39
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
40
set_float_2nan_prop_rule(float_2nan_prop_s_ab,
41
&env->active_tc.msa_fp_status);
42
43
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab,
44
+ &env->active_tc.msa_fp_status);
39
+
45
+
40
+ if (qemu_guest_getrandom(&seed, sizeof(seed), &err)) {
46
/* clear float_status exception flags */
41
+ error_free(err);
47
set_float_exception_flags(0, &env->active_tc.msa_fp_status);
42
+ return;
48
43
+ }
49
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
44
+ qemu_fdt_setprop_u64(vms->fdt, node, "kaslr-seed", seed);
50
index XXXXXXX..XXXXXXX 100644
45
+}
51
--- a/fpu/softfloat-specialize.c.inc
46
+
52
+++ b/fpu/softfloat-specialize.c.inc
47
static void create_fdt(VirtMachineState *vms)
53
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
48
{
49
MachineState *ms = MACHINE(vms);
50
@@ -XXX,XX +XXX,XX @@ static void create_fdt(VirtMachineState *vms)
51
52
/* /chosen must exist for load_dtb to fill in necessary properties later */
53
qemu_fdt_add_subnode(fdt, "/chosen");
54
+ create_kaslr_seed(vms, "/chosen");
55
56
if (vms->secure) {
57
qemu_fdt_add_subnode(fdt, "/secure-chosen");
58
+ create_kaslr_seed(vms, "/secure-chosen");
59
}
54
}
60
55
61
/* Clock node, for the benefit of the UART. The kernel device tree
56
if (rule == float_3nan_prop_none) {
57
-#if defined(TARGET_MIPS)
58
- if (snan_bit_is_one(status)) {
59
- rule = float_3nan_prop_s_abc;
60
- } else {
61
- rule = float_3nan_prop_s_cab;
62
- }
63
-#elif defined(TARGET_XTENSA)
64
+#if defined(TARGET_XTENSA)
65
if (status->use_first_nan) {
66
rule = float_3nan_prop_abc;
67
} else {
62
--
68
--
63
2.20.1
69
2.34.1
64
65
diff view generated by jsdifflib
[PULL 01/31] dma/xlnx-zdma: Fix descriptor loading (MEM) wrt endianness
[PULL 28/72] target/xtensa: Set Float3NaNPropRule explicitly
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
Set the Float3NaNPropRule explicitly for xtensa, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Fix descriptor loading from memory wrt host endianness.
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-24-peter.maydell@linaro.org
7
---
8
target/xtensa/fpu_helper.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 8 --------
10
2 files changed, 2 insertions(+), 8 deletions(-)
4
11
5
Reported-by: Peter Maydell <peter.maydell@linaro.org>
12
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20200404122718.25111-2-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/dma/xlnx-zdma.c | 11 +++++++----
13
1 file changed, 7 insertions(+), 4 deletions(-)
14
15
diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/dma/xlnx-zdma.c
14
--- a/target/xtensa/fpu_helper.c
18
+++ b/hw/dma/xlnx-zdma.c
15
+++ b/target/xtensa/fpu_helper.c
19
@@ -XXX,XX +XXX,XX @@ static void zdma_put_regaddr64(XlnxZDMA *s, unsigned int basereg, uint64_t addr)
16
@@ -XXX,XX +XXX,XX @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
20
s->regs[basereg + 1] = addr >> 32;
17
set_use_first_nan(use_first, &env->fp_status);
18
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
19
&env->fp_status);
20
+ set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
21
+ &env->fp_status);
21
}
22
}
22
23
23
-static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
24
void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v)
24
+static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr,
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
+ XlnxZDMADescr *descr)
26
index XXXXXXX..XXXXXXX 100644
26
{
27
--- a/fpu/softfloat-specialize.c.inc
27
/* ZDMA descriptors must be aligned to their own size. */
28
+++ b/fpu/softfloat-specialize.c.inc
28
if (addr % sizeof(XlnxZDMADescr)) {
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
qemu_log_mask(LOG_GUEST_ERROR,
30
"zdma: unaligned descriptor at %" PRIx64,
31
addr);
32
- memset(buf, 0x0, sizeof(XlnxZDMADescr));
33
+ memset(descr, 0x0, sizeof(XlnxZDMADescr));
34
s->error = true;
35
return false;
36
}
30
}
37
31
38
- address_space_read(s->dma_as, addr, s->attr, buf, sizeof(XlnxZDMADescr));
32
if (rule == float_3nan_prop_none) {
39
+ descr->addr = address_space_ldq_le(s->dma_as, addr, s->attr, NULL);
33
-#if defined(TARGET_XTENSA)
40
+ descr->size = address_space_ldl_le(s->dma_as, addr + 8, s->attr, NULL);
34
- if (status->use_first_nan) {
41
+ descr->attr = address_space_ldl_le(s->dma_as, addr + 12, s->attr, NULL);
35
- rule = float_3nan_prop_abc;
42
return true;
36
- } else {
43
}
37
- rule = float_3nan_prop_cba;
44
38
- }
45
@@ -XXX,XX +XXX,XX @@ static void zdma_update_descr_addr(XlnxZDMA *s, bool type,
39
-#else
46
} else {
40
rule = float_3nan_prop_abc;
47
addr = zdma_get_regaddr64(s, basereg);
41
-#endif
48
addr += sizeof(s->dsc_dst);
49
- address_space_read(s->dma_as, addr, s->attr, (void *) &next, 8);
50
+ next = address_space_ldq_le(s->dma_as, addr, s->attr, NULL);
51
}
42
}
52
43
53
zdma_put_regaddr64(s, basereg, next);
44
assert(rule != float_3nan_prop_none);
54
--
45
--
55
2.20.1
46
2.34.1
56
57
diff view generated by jsdifflib
New patch
[PULL 29/72] target/i386: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for i386. We had no
2
i386-specific behaviour in the old ifdef ladder, so we were using the
3
default "prefer a then b then c" fallback; this is actually the
4
correct per-the-spec handling for i386.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-25-peter.maydell@linaro.org
9
---
10
target/i386/tcg/fpu_helper.c | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/i386/tcg/fpu_helper.c
16
+++ b/target/i386/tcg/fpu_helper.c
17
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
18
* there are multiple input NaNs they are selected in the order a, b, c.
19
*/
20
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
22
}
23
24
static inline uint8_t save_exception_flags(CPUX86State *env)
25
--
26
2.34.1
diff view generated by jsdifflib
New patch
[PULL 30/72] target/hppa: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for HPPA, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
HPPA is the only target that was using the default branch of the
5
ifdef ladder (other targets either do not use muladd or set
6
default_nan_mode), so we can remove the ifdef fallback entirely now
7
(allowing the "rule not set" case to fall into the default of the
8
switch statement and assert).
9
10
We add a TODO note that the HPPA rule is probably wrong; this is
11
not a behavioural change for this refactoring.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-26-peter.maydell@linaro.org
16
---
17
target/hppa/fpu_helper.c | 8 ++++++++
18
fpu/softfloat-specialize.c.inc | 4 ----
19
2 files changed, 8 insertions(+), 4 deletions(-)
20
21
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/hppa/fpu_helper.c
24
+++ b/target/hppa/fpu_helper.c
25
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
26
* HPPA does note implement a CPU reset method at all...
27
*/
28
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
29
+ /*
30
+ * TODO: The HPPA architecture reference only documents its NaN
31
+ * propagation rule for 2-operand operations. Testing on real hardware
32
+ * might be necessary to confirm whether this order for muladd is correct.
33
+ * Not preferring the SNaN is almost certainly incorrect as it diverges
34
+ * from the documented rules for 2-operand operations.
35
+ */
36
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
37
/* For inf * 0 + NaN, return the input NaN */
38
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
39
}
40
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
41
index XXXXXXX..XXXXXXX 100644
42
--- a/fpu/softfloat-specialize.c.inc
43
+++ b/fpu/softfloat-specialize.c.inc
44
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
45
}
46
}
47
48
- if (rule == float_3nan_prop_none) {
49
- rule = float_3nan_prop_abc;
50
- }
51
-
52
assert(rule != float_3nan_prop_none);
53
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
54
/* We have at least one SNaN input and should prefer it */
55
--
56
2.34.1
diff view generated by jsdifflib
New patch
[PULL 31/72] fpu: Remove use_first_nan field from float_status
1
The use_first_nan field in float_status was an xtensa-specific way to
2
select at runtime from two different NaN propagation rules. Now that
3
xtensa is using the target-agnostic NaN propagation rule selection
4
that we've just added, we can remove use_first_nan, because there is
5
no longer any code that reads it.
1
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20241202131347.498124-27-peter.maydell@linaro.org
10
---
11
include/fpu/softfloat-helpers.h | 5 -----
12
include/fpu/softfloat-types.h | 1 -
13
target/xtensa/fpu_helper.c | 1 -
14
3 files changed, 7 deletions(-)
15
16
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/fpu/softfloat-helpers.h
19
+++ b/include/fpu/softfloat-helpers.h
20
@@ -XXX,XX +XXX,XX @@ static inline void set_snan_bit_is_one(bool val, float_status *status)
21
status->snan_bit_is_one = val;
22
}
23
24
-static inline void set_use_first_nan(bool val, float_status *status)
25
-{
26
- status->use_first_nan = val;
27
-}
28
-
29
static inline void set_no_signaling_nans(bool val, float_status *status)
30
{
31
status->no_signaling_nans = val;
32
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/include/fpu/softfloat-types.h
35
+++ b/include/fpu/softfloat-types.h
36
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
37
* softfloat-specialize.inc.c)
38
*/
39
bool snan_bit_is_one;
40
- bool use_first_nan;
41
bool no_signaling_nans;
42
/* should overflowed results subtract re_bias to its exponent? */
43
bool rebias_overflow;
44
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/xtensa/fpu_helper.c
47
+++ b/target/xtensa/fpu_helper.c
48
@@ -XXX,XX +XXX,XX @@ static const struct {
49
50
void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
51
{
52
- set_use_first_nan(use_first, &env->fp_status);
53
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
54
&env->fp_status);
55
set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
56
--
57
2.34.1
diff view generated by jsdifflib
New patch
[PULL 32/72] target/m68k: Don't pass NULL float_status to floatx80_default_nan()
1
Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL)
2
to get the NaN bit pattern to reset the FPU registers. This
3
works because it happens that our implementation of
4
floatx80_default_nan() doesn't actually look at the float_status
5
pointer except for TARGET_MIPS. However, this isn't guaranteed,
6
and to be able to remove the ifdef in floatx80_default_nan()
7
we're going to need a real float_status here.
1
8
9
Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status
10
earlier, and thus can pass it to floatx80_default_nan().
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20241202131347.498124-28-peter.maydell@linaro.org
15
---
16
target/m68k/cpu.c | 12 +++++++-----
17
1 file changed, 7 insertions(+), 5 deletions(-)
18
19
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/m68k/cpu.c
22
+++ b/target/m68k/cpu.c
23
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
24
CPUState *cs = CPU(obj);
25
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj);
26
CPUM68KState *env = cpu_env(cs);
27
- floatx80 nan = floatx80_default_nan(NULL);
28
+ floatx80 nan;
29
int i;
30
31
if (mcc->parent_phases.hold) {
32
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
33
#else
34
cpu_m68k_set_sr(env, SR_S | SR_I);
35
#endif
36
- for (i = 0; i < 8; i++) {
37
- env->fregs[i].d = nan;
38
- }
39
- cpu_m68k_set_fpcr(env, 0);
40
/*
41
* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
42
* 3.4 FLOATING-POINT INSTRUCTION DETAILS
43
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
44
* preceding paragraph for nonsignaling NaNs.
45
*/
46
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
47
+
48
+ nan = floatx80_default_nan(&env->fp_status);
49
+ for (i = 0; i < 8; i++) {
50
+ env->fregs[i].d = nan;
51
+ }
52
+ cpu_m68k_set_fpcr(env, 0);
53
env->fpsr = 0;
54
55
/* TODO: We should set PC from the interrupt vector. */
56
--
57
2.34.1
diff view generated by jsdifflib
New patch
[PULL 33/72] softfloat: Create floatx80 default NaN from parts64_default_nan
1
We create our 128-bit default NaN by calling parts64_default_nan()
2
and then adjusting the result. We can do the same trick for creating
3
the floatx80 default NaN, which lets us drop a target ifdef.
1
4
5
floatx80 is used only by:
6
i386
7
m68k
8
arm nwfpe old floating-point emulation emulation support
9
(which is essentially dead, especially the parts involving floatx80)
10
PPC (only in the xsrqpxp instruction, which just rounds an input
11
value by converting to floatx80 and back, so will never generate
12
the default NaN)
13
14
The floatx80 default NaN as currently implemented is:
15
m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1
16
i386: sign = 1, exp = 1...1, int = 1, frac = 10...0
17
18
These are the same as the parts64_default_nan for these architectures.
19
20
This is technically a possible behaviour change for arm linux-user
21
nwfpe emulation emulation, because the default NaN will now have the
22
sign bit clear. But we were already generating a different floatx80
23
default NaN from the real kernel emulation we are supposedly
24
following, which appears to use an all-bits-1 value:
25
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267
26
27
This won't affect the only "real" use of the nwfpe emulation, which
28
is ancient binaries that used it as part of the old floating point
29
calling convention; that only uses loads and stores of 32 and 64 bit
30
floats, not any of the floatx80 behaviour the original hardware had.
31
We also get the nwfpe float64 default NaN value wrong:
32
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166
33
so if we ever cared about this obscure corner the right fix would be
34
to correct that so nwfpe used its own default-NaN setting rather
35
than the Arm VFP one.
36
37
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
38
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
39
Message-id: 20241202131347.498124-29-peter.maydell@linaro.org
40
---
41
fpu/softfloat-specialize.c.inc | 20 ++++++++++----------
42
1 file changed, 10 insertions(+), 10 deletions(-)
43
44
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
45
index XXXXXXX..XXXXXXX 100644
46
--- a/fpu/softfloat-specialize.c.inc
47
+++ b/fpu/softfloat-specialize.c.inc
48
@@ -XXX,XX +XXX,XX @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status)
49
floatx80 floatx80_default_nan(float_status *status)
50
{
51
floatx80 r;
52
+ /*
53
+ * Extrapolate from the choices made by parts64_default_nan to fill
54
+ * in the floatx80 format. We assume that floatx80's explicit
55
+ * integer bit is always set (this is true for i386 and m68k,
56
+ * which are the only real users of this format).
57
+ */
58
+ FloatParts64 p64;
59
+ parts64_default_nan(&p64, status);
60
61
- /* None of the targets that have snan_bit_is_one use floatx80. */
62
- assert(!snan_bit_is_one(status));
63
-#if defined(TARGET_M68K)
64
- r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
65
- r.high = 0x7FFF;
66
-#else
67
- /* X86 */
68
- r.low = UINT64_C(0xC000000000000000);
69
- r.high = 0xFFFF;
70
-#endif
71
+ r.high = 0x7FFF | (p64.sign << 15);
72
+ r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac;
73
return r;
74
}
75
76
--
77
2.34.1
diff view generated by jsdifflib
New patch
[PULL 34/72] target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
1
In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass
2
a zero-initialized float_status struct to float32_is_quiet_nan() and
3
float64_is_quiet_nan(), with the cryptic comment "for
4
snan_bit_is_one".
1
5
6
This pattern appears to have been copied from target/riscv, where it
7
is used because the functions there do not have ready access to the
8
CPU state struct. The comment presumably refers to the fact that the
9
main reason the is_quiet_nan() functions want the float_state is
10
because they want to know about the snan_bit_is_one config.
11
12
In the loongarch helpers, though, we have the CPU state struct
13
to hand. Use the usual env->fp_status here. This avoids our needing
14
to track that we need to update the initializer of the local
15
float_status structs when the core softfloat code adds new
16
options for targets to configure their behaviour.
17
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20241202131347.498124-30-peter.maydell@linaro.org
21
---
22
target/loongarch/tcg/fpu_helper.c | 6 ++----
23
1 file changed, 2 insertions(+), 4 deletions(-)
24
25
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/loongarch/tcg/fpu_helper.c
28
+++ b/target/loongarch/tcg/fpu_helper.c
29
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj)
30
} else if (float32_is_zero_or_denormal(f)) {
31
return sign ? 1 << 4 : 1 << 8;
32
} else if (float32_is_any_nan(f)) {
33
- float_status s = { }; /* for snan_bit_is_one */
34
- return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
35
+ return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
36
} else {
37
return sign ? 1 << 3 : 1 << 7;
38
}
39
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj)
40
} else if (float64_is_zero_or_denormal(f)) {
41
return sign ? 1 << 4 : 1 << 8;
42
} else if (float64_is_any_nan(f)) {
43
- float_status s = { }; /* for snan_bit_is_one */
44
- return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
45
+ return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
46
} else {
47
return sign ? 1 << 3 : 1 << 7;
48
}
49
--
50
2.34.1
diff view generated by jsdifflib
New patch
[PULL 35/72] target/m68k: In frem helper, initialize local float_status from env->fp_status
1
In the frem helper, we have a local float_status because we want to
2
execute the floatx80_div() with a custom rounding mode. Instead of
3
zero-initializing the local float_status and then having to set it up
4
with the m68k standard behaviour (including the NaN propagation rule
5
and copying the rounding precision from env->fp_status), initialize
6
it as a complete copy of env->fp_status. This will avoid our having
7
to add new code in this function for every new config knob we add
8
to fp_status.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-31-peter.maydell@linaro.org
13
---
14
target/m68k/fpu_helper.c | 6 ++----
15
1 file changed, 2 insertions(+), 4 deletions(-)
16
17
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/m68k/fpu_helper.c
20
+++ b/target/m68k/fpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
22
23
fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status);
24
if (!floatx80_is_any_nan(fp_rem)) {
25
- float_status fp_status = { };
26
+ /* Use local temporary fp_status to set different rounding mode */
27
+ float_status fp_status = env->fp_status;
28
uint32_t quotient;
29
int sign;
30
31
/* Calculate quotient directly using round to nearest mode */
32
- set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status);
33
set_float_rounding_mode(float_round_nearest_even, &fp_status);
34
- set_floatx80_rounding_precision(
35
- get_floatx80_rounding_precision(&env->fp_status), &fp_status);
36
fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status);
37
38
sign = extractFloatx80Sign(fp_quot.d);
39
--
40
2.34.1
diff view generated by jsdifflib
[PULL 22/31] hw/arm/virt: dt: move creation of /secure-chosen to create_fdt()
[PULL 36/72] target/m68k: Init local float_status from env fp_status in gdb get/set reg
1
From: Jerome Forissier <jerome@forissier.org>
1
In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion
2
from float64 to floatx80 using a scratch float_status, because we
3
don't want the conversion to affect the CPU's floating point exception
4
status. Currently we use a zero-initialized float_status. This will
5
get steadily more awkward as we add config knobs to float_status
6
that the target must initialize. Avoid having to add any of that
7
configuration here by instead initializing our local float_status
8
from the env->fp_status.
2
9
3
The /secure-chosen node is currently used only by create_uart(), but
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
this will change. Therefore move the creation of this node to
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
create_fdt().
12
Message-id: 20241202131347.498124-32-peter.maydell@linaro.org
13
---
14
target/m68k/helper.c | 6 ++++--
15
1 file changed, 4 insertions(+), 2 deletions(-)
6
16
7
Signed-off-by: Jerome Forissier <jerome@forissier.org>
17
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
8
Message-id: 20200420121807.8204-2-jerome@forissier.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/virt.c | 5 ++++-
13
1 file changed, 4 insertions(+), 1 deletion(-)
14
15
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/virt.c
19
--- a/target/m68k/helper.c
18
+++ b/hw/arm/virt.c
20
+++ b/target/m68k/helper.c
19
@@ -XXX,XX +XXX,XX @@ static void create_fdt(VirtMachineState *vms)
21
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n)
20
/* /chosen must exist for load_dtb to fill in necessary properties later */
22
CPUM68KState *env = &cpu->env;
21
qemu_fdt_add_subnode(fdt, "/chosen");
23
22
24
if (n < 8) {
23
+ if (vms->secure) {
25
- float_status s = {};
24
+ qemu_fdt_add_subnode(fdt, "/secure-chosen");
26
+ /* Use scratch float_status so any exceptions don't change CPU state */
25
+ }
27
+ float_status s = env->fp_status;
26
+
28
return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s));
27
/* Clock node, for the benefit of the UART. The kernel device tree
29
}
28
* binding documentation claims the PL011 node clock properties are
30
switch (n) {
29
* optional but in practice if you omit them the kernel refuses to
31
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n)
30
@@ -XXX,XX +XXX,XX @@ static void create_uart(const VirtMachineState *vms, int uart,
32
CPUM68KState *env = &cpu->env;
31
qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
33
32
qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
34
if (n < 8) {
33
35
- float_status s = {};
34
- qemu_fdt_add_subnode(vms->fdt, "/secure-chosen");
36
+ /* Use scratch float_status so any exceptions don't change CPU state */
35
qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path",
37
+ float_status s = env->fp_status;
36
nodename);
38
env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s);
39
return 8;
37
}
40
}
38
--
41
--
39
2.20.1
42
2.34.1
40
41
diff view generated by jsdifflib
[PULL 24/31] target/arm: Restrict the Address Translate write operation to TCG accel
[PULL 37/72] target/sparc: Initialize local scratch float_status from env->fp_status
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
In the helper functions flcmps and flcmpd we use a scratch float_status
2
so that we don't change the CPU state if the comparison raises any
3
floating point exception flags. Instead of zero-initializing this
4
scratch float_status, initialize it as a copy of env->fp_status. This
5
avoids the need to explicitly initialize settings like the NaN
6
propagation rule or others we might add to softfloat in future.
2
7
3
Under KVM these registers are written by the hardware.
8
To do this we need to pass the CPU env pointer in to the helper.
4
Restrict the writefn handlers to TCG to avoid when building
5
without TCG:
6
9
7
LINK aarch64-softmmu/qemu-system-aarch64
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
target/arm/helper.o: In function `do_ats_write':
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
target/arm/helper.c:3524: undefined reference to `raise_exception'
12
Message-id: 20241202131347.498124-33-peter.maydell@linaro.org
13
---
14
target/sparc/helper.h | 4 ++--
15
target/sparc/fop_helper.c | 8 ++++----
16
target/sparc/translate.c | 4 ++--
17
3 files changed, 8 insertions(+), 8 deletions(-)
10
18
11
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
19
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Message-id: 20200423073358.27155-2-philmd@redhat.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/helper.c | 17 +++++++++++++++++
18
1 file changed, 17 insertions(+)
19
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
21
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper.c
21
--- a/target/sparc/helper.h
23
+++ b/target/arm/helper.c
22
+++ b/target/sparc/helper.h
24
@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64)
25
return CP_ACCESS_OK;
24
DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64)
25
DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128)
26
DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128)
27
-DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32)
28
-DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64)
29
+DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32)
30
+DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64)
31
DEF_HELPER_2(raise_exception, noreturn, env, int)
32
33
DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64)
34
diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/sparc/fop_helper.c
37
+++ b/target/sparc/fop_helper.c
38
@@ -XXX,XX +XXX,XX @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2)
39
return finish_fcmp(env, r, GETPC());
26
}
40
}
27
41
28
+#ifdef CONFIG_TCG
42
-uint32_t helper_flcmps(float32 src1, float32 src2)
29
static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
43
+uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2)
30
MMUAccessType access_type, ARMMMUIdx mmu_idx)
31
{
44
{
32
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
45
/*
33
}
46
* FLCMP never raises an exception nor modifies any FSR fields.
34
return par64;
47
* Perform the comparison with a dummy fp environment.
48
*/
49
- float_status discard = { };
50
+ float_status discard = env->fp_status;
51
FloatRelation r;
52
53
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
54
@@ -XXX,XX +XXX,XX @@ uint32_t helper_flcmps(float32 src1, float32 src2)
55
g_assert_not_reached();
35
}
56
}
36
+#endif /* CONFIG_TCG */
57
37
58
-uint32_t helper_flcmpd(float64 src1, float64 src2)
38
static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
59
+uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2)
39
{
60
{
40
+#ifdef CONFIG_TCG
61
- float_status discard = { };
41
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
62
+ float_status discard = env->fp_status;
42
uint64_t par64;
63
FloatRelation r;
43
ARMMMUIdx mmu_idx;
64
44
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
65
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
45
par64 = do_ats_write(env, value, access_type, mmu_idx);
66
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
46
67
index XXXXXXX..XXXXXXX 100644
47
A32_BANKED_CURRENT_REG_SET(env, par, par64);
68
--- a/target/sparc/translate.c
48
+#else
69
+++ b/target/sparc/translate.c
49
+ /* Handled by hardware accelerator. */
70
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a)
50
+ g_assert_not_reached();
71
51
+#endif /* CONFIG_TCG */
72
src1 = gen_load_fpr_F(dc, a->rs1);
73
src2 = gen_load_fpr_F(dc, a->rs2);
74
- gen_helper_flcmps(cpu_fcc[a->cc], src1, src2);
75
+ gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2);
76
return advance_pc(dc);
52
}
77
}
53
78
54
static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
79
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a)
55
uint64_t value)
80
56
{
81
src1 = gen_load_fpr_D(dc, a->rs1);
57
+#ifdef CONFIG_TCG
82
src2 = gen_load_fpr_D(dc, a->rs2);
58
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
83
- gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2);
59
uint64_t par64;
84
+ gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2);
60
85
return advance_pc(dc);
61
par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2);
62
63
A32_BANKED_CURRENT_REG_SET(env, par, par64);
64
+#else
65
+ /* Handled by hardware accelerator. */
66
+ g_assert_not_reached();
67
+#endif /* CONFIG_TCG */
68
}
86
}
69
87
70
static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
71
@@ -XXX,XX +XXX,XX @@ static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
72
static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
73
uint64_t value)
74
{
75
+#ifdef CONFIG_TCG
76
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
77
ARMMMUIdx mmu_idx;
78
int secure = arm_is_secure_below_el3(env);
79
@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
80
}
81
82
env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
83
+#else
84
+ /* Handled by hardware accelerator. */
85
+ g_assert_not_reached();
86
+#endif /* CONFIG_TCG */
87
}
88
#endif
89
90
--
88
--
91
2.20.1
89
2.34.1
92
93
diff view generated by jsdifflib
New patch
[PULL 38/72] target/ppc: Use env->fp_status in helper_compute_fprf functions
1
In the helper_compute_fprf functions, we pass a dummy float_status
2
in to the is_signaling_nan() function. This is unnecessary, because
3
we have convenient access to the CPU env pointer here and that
4
is already set up with the correct values for the snan_bit_is_one
5
and no_signaling_nans config settings. is_signaling_nan() doesn't
6
ever update the fp_status with any exception flags, so there is
7
no reason not to use env->fp_status here.
1
8
9
Use env->fp_status instead of the dummy fp_status.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20241202131347.498124-34-peter.maydell@linaro.org
14
---
15
target/ppc/fpu_helper.c | 3 +--
16
1 file changed, 1 insertion(+), 2 deletions(-)
17
18
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/ppc/fpu_helper.c
21
+++ b/target/ppc/fpu_helper.c
22
@@ -XXX,XX +XXX,XX @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
23
} else if (tp##_is_infinity(arg)) { \
24
fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \
25
} else { \
26
- float_status dummy = { }; /* snan_bit_is_one = 0 */ \
27
- if (tp##_is_signaling_nan(arg, &dummy)) { \
28
+ if (tp##_is_signaling_nan(arg, &env->fp_status)) { \
29
fprf = 0x00 << FPSCR_FPRF; \
30
} else { \
31
fprf = 0x11 << FPSCR_FPRF; \
32
--
33
2.34.1
diff view generated by jsdifflib
[PULL 05/31] Typo: Correct the name of CPU hotplug memory region
[PULL 39/72] target/arm: Copy entire float_status in is_ebf
1
From: Keqian Zhu <zhukeqian1@huawei.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Replace "acpi-mem-hotplug" with "acpi-cpu-hotplug"
3
Now that float_status has a bunch of fp parameters,
4
it is easier to copy an existing structure than create
5
one from scratch. Begin by copying the structure that
6
corresponds to the FPSR and make only the adjustments
7
required for BFloat16 semantics.
4
8
5
Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200413091552.62748-4-zhukeqian1@huawei.com
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20241203203949.483774-2-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
14
---
10
hw/acpi/cpu.c | 2 +-
15
target/arm/tcg/vec_helper.c | 20 +++++++-------------
11
1 file changed, 1 insertion(+), 1 deletion(-)
16
1 file changed, 7 insertions(+), 13 deletions(-)
12
17
13
diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
18
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
14
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/acpi/cpu.c
20
--- a/target/arm/tcg/vec_helper.c
16
+++ b/hw/acpi/cpu.c
21
+++ b/target/arm/tcg/vec_helper.c
17
@@ -XXX,XX +XXX,XX @@ void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner,
22
@@ -XXX,XX +XXX,XX @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp)
18
state->devs[i].arch_id = id_list->cpus[i].arch_id;
23
* no effect on AArch32 instructions.
24
*/
25
bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF;
26
- *statusp = (float_status){
27
- .tininess_before_rounding = float_tininess_before_rounding,
28
- .float_rounding_mode = float_round_to_odd_inf,
29
- .flush_to_zero = true,
30
- .flush_inputs_to_zero = true,
31
- .default_nan_mode = true,
32
- };
33
+
34
+ *statusp = env->vfp.fp_status;
35
+ set_default_nan_mode(true, statusp);
36
37
if (ebf) {
38
- float_status *fpst = &env->vfp.fp_status;
39
- set_flush_to_zero(get_flush_to_zero(fpst), statusp);
40
- set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp);
41
- set_float_rounding_mode(get_float_rounding_mode(fpst), statusp);
42
-
43
/* EBF=1 needs to do a step with round-to-odd semantics */
44
*oddstatusp = *statusp;
45
set_float_rounding_mode(float_round_to_odd, oddstatusp);
46
+ } else {
47
+ set_flush_to_zero(true, statusp);
48
+ set_flush_inputs_to_zero(true, statusp);
49
+ set_float_rounding_mode(float_round_to_odd_inf, statusp);
19
}
50
}
20
memory_region_init_io(&state->ctrl_reg, owner, &cpu_hotplug_ops, state,
51
-
21
- "acpi-mem-hotplug", ACPI_CPU_HOTPLUG_REG_LEN);
52
return ebf;
22
+ "acpi-cpu-hotplug", ACPI_CPU_HOTPLUG_REG_LEN);
23
memory_region_add_subregion(as, base_addr, &state->ctrl_reg);
24
}
53
}
25
54
26
--
55
--
27
2.20.1
56
2.34.1
28
57
29
58
diff view generated by jsdifflib
[PULL 12/31] qdev-clock: introduce an init array to ease the device construction
[PULL 40/72] fpu: Allow runtime choice of default NaN value
1
From: Damien Hedde <damien.hedde@greensocs.com>
1
Currently we hardcode the default NaN value in parts64_default_nan()
2
using a compile-time ifdef ladder. This is awkward for two cases:
3
* for single-QEMU-binary we can't hard-code target-specifics like this
4
* for Arm FEAT_AFP the default NaN value depends on FPCR.AH
5
(specifically the sign bit is different)
2
6
3
Introduce a function and macro helpers to setup several clocks
7
Add a field to float_status to specify the default NaN value; fall
4
in a device from a static array description.
8
back to the old ifdef behaviour if these are not set.
5
9
6
An element of the array describes the clock (name and direction) as
10
The default NaN value is specified by setting a uint8_t to a
7
well as the related callback and an optional offset to store the
11
pattern corresponding to the sign and upper fraction parts of
8
created object pointer in the device state structure.
12
the NaN; the lower bits of the fraction are set from bit 0 of
13
the pattern.
9
14
10
The array must be terminated by a special element QDEV_CLOCK_END.
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20241202131347.498124-35-peter.maydell@linaro.org
18
---
19
include/fpu/softfloat-helpers.h | 11 +++++++
20
include/fpu/softfloat-types.h | 10 ++++++
21
fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++-------------
22
3 files changed, 54 insertions(+), 22 deletions(-)
11
23
12
This is based on the original work of Frederic Konrad.
24
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
13
14
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
16
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
18
Message-id: 20200406135251.157596-5-damien.hedde@greensocs.com
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
include/hw/qdev-clock.h | 55 +++++++++++++++++++++++++++++++++++++++++
22
hw/core/qdev-clock.c | 17 +++++++++++++
23
2 files changed, 72 insertions(+)
24
25
diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h
26
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
27
--- a/include/hw/qdev-clock.h
26
--- a/include/fpu/softfloat-helpers.h
28
+++ b/include/hw/qdev-clock.h
27
+++ b/include/fpu/softfloat-helpers.h
29
@@ -XXX,XX +XXX,XX @@ Clock *qdev_alias_clock(DeviceState *dev, const char *name,
28
@@ -XXX,XX +XXX,XX @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
30
*/
29
status->float_infzeronan_rule = rule;
31
void qdev_finalize_clocklist(DeviceState *dev);
30
}
32
31
33
+/**
32
+static inline void set_float_default_nan_pattern(uint8_t dnan_pattern,
34
+ * ClockPortInitElem:
33
+ float_status *status)
35
+ * @name: name of the clock (can't be NULL)
34
+{
36
+ * @output: indicates whether the clock is input or output
35
+ status->default_nan_pattern = dnan_pattern;
37
+ * @callback: for inputs, optional callback to be called on clock's update
38
+ * with device as opaque
39
+ * @offset: optional offset to store the ClockIn or ClockOut pointer in device
40
+ * state structure (0 means unused)
41
+ */
42
+struct ClockPortInitElem {
43
+ const char *name;
44
+ bool is_output;
45
+ ClockCallback *callback;
46
+ size_t offset;
47
+};
48
+
49
+#define clock_offset_value(devstate, field) \
50
+ (offsetof(devstate, field) + \
51
+ type_check(Clock *, typeof_field(devstate, field)))
52
+
53
+#define QDEV_CLOCK(out_not_in, devstate, field, cb) { \
54
+ .name = (stringify(field)), \
55
+ .is_output = out_not_in, \
56
+ .callback = cb, \
57
+ .offset = clock_offset_value(devstate, field), \
58
+}
36
+}
59
+
37
+
60
+/**
38
static inline void set_flush_to_zero(bool val, float_status *status)
61
+ * QDEV_CLOCK_(IN|OUT):
39
{
62
+ * @devstate: structure type. @dev argument of qdev_init_clocks below must be
40
status->flush_to_zero = val;
63
+ * a pointer to that same type.
41
@@ -XXX,XX +XXX,XX @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status
64
+ * @field: a field in @_devstate (must be Clock*)
42
return status->float_infzeronan_rule;
65
+ * @callback: (for input only) callback (or NULL) to be called with the device
66
+ * state as argument
67
+ *
68
+ * The name of the clock will be derived from @field
69
+ */
70
+#define QDEV_CLOCK_IN(devstate, field, callback) \
71
+ QDEV_CLOCK(false, devstate, field, callback)
72
+
73
+#define QDEV_CLOCK_OUT(devstate, field) \
74
+ QDEV_CLOCK(true, devstate, field, NULL)
75
+
76
+#define QDEV_CLOCK_END { .name = NULL }
77
+
78
+typedef struct ClockPortInitElem ClockPortInitArray[];
79
+
80
+/**
81
+ * qdev_init_clocks:
82
+ * @dev: the device to add clocks to
83
+ * @clocks: a QDEV_CLOCK_END-terminated array which contains the
84
+ * clocks information.
85
+ */
86
+void qdev_init_clocks(DeviceState *dev, const ClockPortInitArray clocks);
87
+
88
#endif /* QDEV_CLOCK_H */
89
diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/hw/core/qdev-clock.c
92
+++ b/hw/core/qdev-clock.c
93
@@ -XXX,XX +XXX,XX @@ Clock *qdev_init_clock_in(DeviceState *dev, const char *name,
94
return ncl->clock;
95
}
43
}
96
44
97
+void qdev_init_clocks(DeviceState *dev, const ClockPortInitArray clocks)
45
+static inline uint8_t get_float_default_nan_pattern(float_status *status)
98
+{
46
+{
99
+ const struct ClockPortInitElem *elem;
47
+ return status->default_nan_pattern;
100
+
101
+ for (elem = &clocks[0]; elem->name != NULL; elem++) {
102
+ Clock **clkp;
103
+ /* offset cannot be inside the DeviceState part */
104
+ assert(elem->offset > sizeof(DeviceState));
105
+ clkp = (Clock **)(((void *) dev) + elem->offset);
106
+ if (elem->is_output) {
107
+ *clkp = qdev_init_clock_out(dev, elem->name);
108
+ } else {
109
+ *clkp = qdev_init_clock_in(dev, elem->name, elem->callback, dev);
110
+ }
111
+ }
112
+}
48
+}
113
+
49
+
114
static NamedClockList *qdev_get_clocklist(DeviceState *dev, const char *name)
50
static inline bool get_flush_to_zero(float_status *status)
115
{
51
{
116
NamedClockList *ncl;
52
return status->flush_to_zero;
53
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
54
index XXXXXXX..XXXXXXX 100644
55
--- a/include/fpu/softfloat-types.h
56
+++ b/include/fpu/softfloat-types.h
57
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
58
/* should denormalised inputs go to zero and set the input_denormal flag? */
59
bool flush_inputs_to_zero;
60
bool default_nan_mode;
61
+ /*
62
+ * The pattern to use for the default NaN. Here the high bit specifies
63
+ * the default NaN's sign bit, and bits 6..0 specify the high bits of the
64
+ * fractional part. The low bits of the fractional part are copies of bit 0.
65
+ * The exponent of the default NaN is (as for any NaN) always all 1s.
66
+ * Note that a value of 0 here is not a valid NaN. The target must set
67
+ * this to the correct non-zero value, or we will assert when trying to
68
+ * create a default NaN.
69
+ */
70
+ uint8_t default_nan_pattern;
71
/*
72
* The flags below are not used on all specializations and may
73
* constant fold away (see snan_bit_is_one()/no_signalling_nans() in
74
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
75
index XXXXXXX..XXXXXXX 100644
76
--- a/fpu/softfloat-specialize.c.inc
77
+++ b/fpu/softfloat-specialize.c.inc
78
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
79
{
80
bool sign = 0;
81
uint64_t frac;
82
+ uint8_t dnan_pattern = status->default_nan_pattern;
83
84
+ if (dnan_pattern == 0) {
85
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
86
- /* !snan_bit_is_one, set all bits */
87
- frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
88
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
89
+ /* Sign bit clear, all frac bits set */
90
+ dnan_pattern = 0b01111111;
91
+#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
92
|| defined(TARGET_MICROBLAZE)
93
- /* !snan_bit_is_one, set sign and msb */
94
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
95
- sign = 1;
96
+ /* Sign bit set, most significant frac bit set */
97
+ dnan_pattern = 0b11000000;
98
#elif defined(TARGET_HPPA)
99
- /* snan_bit_is_one, set msb-1. */
100
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
101
+ /* Sign bit clear, msb-1 frac bit set */
102
+ dnan_pattern = 0b00100000;
103
#elif defined(TARGET_HEXAGON)
104
- sign = 1;
105
- frac = ~0ULL;
106
+ /* Sign bit set, all frac bits set. */
107
+ dnan_pattern = 0b11111111;
108
#else
109
- /*
110
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
111
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
112
- * do not have floating-point.
113
- */
114
- if (snan_bit_is_one(status)) {
115
- /* set all bits other than msb */
116
- frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
117
- } else {
118
- /* set msb */
119
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
120
- }
121
+ /*
122
+ * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
123
+ * S390, SH4, TriCore, and Xtensa. Our other supported targets
124
+ * do not have floating-point.
125
+ */
126
+ if (snan_bit_is_one(status)) {
127
+ /* sign bit clear, set all frac bits other than msb */
128
+ dnan_pattern = 0b00111111;
129
+ } else {
130
+ /* sign bit clear, set frac msb */
131
+ dnan_pattern = 0b01000000;
132
+ }
133
#endif
134
+ }
135
+ assert(dnan_pattern != 0);
136
+
137
+ sign = dnan_pattern >> 7;
138
+ /*
139
+ * Place default_nan_pattern [6:0] into bits [62:56],
140
+ * and replecate bit [0] down into [55:0]
141
+ */
142
+ frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern);
143
+ frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1));
144
145
*p = (FloatParts64) {
146
.cls = float_class_qnan,
117
--
147
--
118
2.20.1
148
2.34.1
119
120
diff view generated by jsdifflib
New patch
[PULL 41/72] tests/fp: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the tests/fp code.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-36-peter.maydell@linaro.org
6
---
7
tests/fp/fp-bench.c | 1 +
8
tests/fp/fp-test-log2.c | 1 +
9
tests/fp/fp-test.c | 1 +
10
3 files changed, 3 insertions(+)
11
12
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tests/fp/fp-bench.c
15
+++ b/tests/fp/fp-bench.c
16
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
17
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
18
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
19
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
20
+ set_float_default_nan_pattern(0b01000000, &soft_status);
21
22
f = bench_funcs[operation][precision];
23
g_assert(f);
24
diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/tests/fp/fp-test-log2.c
27
+++ b/tests/fp/fp-test-log2.c
28
@@ -XXX,XX +XXX,XX @@ int main(int ac, char **av)
29
int i;
30
31
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
32
+ set_float_default_nan_pattern(0b01000000, &qsf);
33
set_float_rounding_mode(float_round_nearest_even, &qsf);
34
35
test.d = 0.0;
36
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/tests/fp/fp-test.c
39
+++ b/tests/fp/fp-test.c
40
@@ -XXX,XX +XXX,XX @@ void run_test(void)
41
*/
42
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
43
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
44
+ set_float_default_nan_pattern(0b01000000, &qsf);
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
46
47
genCases_setLevel(test_level);
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 42/72] target/microblaze: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-37-peter.maydell@linaro.org
7
---
8
target/microblaze/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/microblaze/cpu.c
15
+++ b/target/microblaze/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj, ResetType type)
17
* this architecture.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
23
#if defined(CONFIG_USER_ONLY)
24
/* start in user mode with interrupts enabled. */
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
34
- || defined(TARGET_MICROBLAZE)
35
+#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
/* Sign bit set, most significant frac bit set */
37
dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 43/72] target/i386: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-38-peter.maydell@linaro.org
7
---
8
target/i386/tcg/fpu_helper.c | 4 ++++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 4 insertions(+), 3 deletions(-)
11
12
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/i386/tcg/fpu_helper.c
15
+++ b/target/i386/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
17
*/
18
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
19
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
+ set_float_default_nan_pattern(0b11000000, &env->mmx_status);
23
+ set_float_default_nan_pattern(0b11000000, &env->sse_status);
24
}
25
26
static inline uint8_t save_exception_flags(CPUX86State *env)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
32
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
/* Sign bit clear, all frac bits set */
34
dnan_pattern = 0b01111111;
35
-#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
- /* Sign bit set, most significant frac bit set */
37
- dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
/* Sign bit clear, msb-1 frac bit set */
40
dnan_pattern = 0b00100000;
41
--
42
2.34.1
diff view generated by jsdifflib
New patch
[PULL 44/72] target/hppa: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-39-peter.maydell@linaro.org
7
---
8
target/hppa/fpu_helper.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 2 insertions(+), 3 deletions(-)
11
12
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/hppa/fpu_helper.c
15
+++ b/target/hppa/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
17
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN: sign bit clear, msb-1 frac bit set */
21
+ set_float_default_nan_pattern(0b00100000, &env->fp_status);
22
}
23
24
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_HPPA)
34
- /* Sign bit clear, msb-1 frac bit set */
35
- dnan_pattern = 0b00100000;
36
#elif defined(TARGET_HEXAGON)
37
/* Sign bit set, all frac bits set. */
38
dnan_pattern = 0b11111111;
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 45/72] target/alpha: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the alpha target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-40-peter.maydell@linaro.org
6
---
7
target/alpha/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/alpha/cpu.c
13
+++ b/target/alpha/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj)
15
* operand in Fa. That is float_2nan_prop_ba.
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
18
+ /* Default NaN: sign bit clear, msb frac bit set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
#if defined(CONFIG_USER_ONLY)
21
env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
22
cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD
23
--
24
2.34.1
diff view generated by jsdifflib
[PULL 25/31] target/arm: Make cpu_register() available for other files
[PULL 46/72] target/arm: Set default NaN pattern explicitly
1
From: Thomas Huth <thuth@redhat.com>
1
Set the default NaN pattern explicitly for the arm target.
2
This includes setting it for the old linux-user nwfpe emulation.
3
For nwfpe, our default doesn't match the real kernel, but we
4
avoid making a behaviour change in this commit.
2
5
3
Make cpu_register() (renamed to arm_cpu_register()) available
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
from internals.h so we can register CPUs also from other files
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
in the future.
8
Message-id: 20241202131347.498124-41-peter.maydell@linaro.org
9
---
10
linux-user/arm/nwfpe/fpa11.c | 5 +++++
11
target/arm/cpu.c | 2 ++
12
2 files changed, 7 insertions(+)
6
13
7
Signed-off-by: Thomas Huth <thuth@redhat.com>
14
diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20200423073358.27155-3-philmd@redhat.com
12
Message-ID: <20190921150420.30743-2-thuth@redhat.com>
13
[PMD: Only take cpu_register() from Thomas's patch]
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/cpu-qom.h | 9 ++++++++-
18
target/arm/cpu.c | 10 ++--------
19
target/arm/cpu64.c | 8 +-------
20
3 files changed, 11 insertions(+), 16 deletions(-)
21
22
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
23
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/cpu-qom.h
16
--- a/linux-user/arm/nwfpe/fpa11.c
25
+++ b/target/arm/cpu-qom.h
17
+++ b/linux-user/arm/nwfpe/fpa11.c
26
@@ -XXX,XX +XXX,XX @@ struct arm_boot_info;
18
@@ -XXX,XX +XXX,XX @@ void resetFPA11(void)
27
19
* this late date.
28
#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
20
*/
29
21
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status);
30
-typedef struct ARMCPUInfo ARMCPUInfo;
22
+ /*
31
+typedef struct ARMCPUInfo {
23
+ * Use the same default NaN value as Arm VFP. This doesn't match
32
+ const char *name;
24
+ * the Linux kernel's nwfpe emulation, which uses an all-1s value.
33
+ void (*initfn)(Object *obj);
25
+ */
34
+ void (*class_init)(ObjectClass *oc, void *data);
26
+ set_float_default_nan_pattern(0b01000000, &fpa11->fp_status);
35
+} ARMCPUInfo;
27
}
36
+
28
37
+void arm_cpu_register(const ARMCPUInfo *info);
29
void SetRoundingMode(const unsigned int opcode)
38
+void aarch64_cpu_register(const ARMCPUInfo *info);
39
40
/**
41
* ARMCPUClass:
42
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
30
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
43
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/cpu.c
32
--- a/target/arm/cpu.c
45
+++ b/target/arm/cpu.c
33
+++ b/target/arm/cpu.c
46
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
34
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
47
35
* the pseudocode function the arguments are in the order c, a, b.
48
#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
36
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
49
37
* and the input NaN if it is signalling
50
-struct ARMCPUInfo {
38
+ * * Default NaN has sign bit clear, msb frac bit set
51
- const char *name;
39
*/
52
- void (*initfn)(Object *obj);
40
static void arm_set_default_fp_behaviours(float_status *s)
53
- void (*class_init)(ObjectClass *oc, void *data);
41
{
54
-};
42
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
55
-
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
56
static const ARMCPUInfo arm_cpus[] = {
44
set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
57
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
58
{ .name = "arm926", .initfn = arm926_initfn },
46
+ set_float_default_nan_pattern(0b01000000, s);
59
@@ -XXX,XX +XXX,XX @@ static void cpu_register_class_init(ObjectClass *oc, void *data)
60
acc->info = data;
61
}
47
}
62
48
63
-static void cpu_register(const ARMCPUInfo *info)
49
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
64
+void arm_cpu_register(const ARMCPUInfo *info)
65
{
66
TypeInfo type_info = {
67
.parent = TYPE_ARM_CPU,
68
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void)
69
type_register_static(&idau_interface_type_info);
70
71
while (info->name) {
72
- cpu_register(info);
73
+ arm_cpu_register(info);
74
info++;
75
}
76
77
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/target/arm/cpu64.c
80
+++ b/target/arm/cpu64.c
81
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
82
cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
83
}
84
85
-struct ARMCPUInfo {
86
- const char *name;
87
- void (*initfn)(Object *obj);
88
- void (*class_init)(ObjectClass *oc, void *data);
89
-};
90
-
91
static const ARMCPUInfo aarch64_cpus[] = {
92
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
93
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
94
@@ -XXX,XX +XXX,XX @@ static void cpu_register_class_init(ObjectClass *oc, void *data)
95
acc->info = data;
96
}
97
98
-static void aarch64_cpu_register(const ARMCPUInfo *info)
99
+void aarch64_cpu_register(const ARMCPUInfo *info)
100
{
101
TypeInfo type_info = {
102
.parent = TYPE_AARCH64_CPU,
103
--
50
--
104
2.20.1
51
2.34.1
105
106
diff view generated by jsdifflib
New patch
[PULL 47/72] target/loongarch: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for loongarch.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-42-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/loongarch/tcg/fpu_helper.c
13
+++ b/target/loongarch/tcg/fpu_helper.c
14
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
15
*/
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
17
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
18
+ /* Default NaN: sign bit clear, msb frac bit set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
}
21
22
int ieee_ex_to_loongarch(int xcpt)
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 48/72] target/m68k: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for m68k.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-43-peter.maydell@linaro.org
6
---
7
target/m68k/cpu.c | 2 ++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 3 insertions(+), 1 deletion(-)
10
11
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/m68k/cpu.c
14
+++ b/target/m68k/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
16
* preceding paragraph for nonsignaling NaNs.
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
+ /* Default NaN: sign bit clear, all frac bits set */
20
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
21
22
nan = floatx80_default_nan(&env->fp_status);
23
for (i = 0; i < 8; i++) {
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
29
uint8_t dnan_pattern = status->default_nan_pattern;
30
31
if (dnan_pattern == 0) {
32
-#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
+#if defined(TARGET_SPARC)
34
/* Sign bit clear, all frac bits set */
35
dnan_pattern = 0b01111111;
36
#elif defined(TARGET_HEXAGON)
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 49/72] target/mips: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for MIPS. Note that this
2
is our only target which currently changes the default NaN
3
at runtime (which it was previously doing indirectly when it
4
changed the snan_bit_is_one setting).
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-44-peter.maydell@linaro.org
9
---
10
target/mips/fpu_helper.h | 7 +++++++
11
target/mips/msa.c | 3 +++
12
2 files changed, 10 insertions(+)
13
14
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/mips/fpu_helper.h
17
+++ b/target/mips/fpu_helper.h
18
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
19
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
20
nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
21
set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
22
+ /*
23
+ * With nan2008, the default NaN value has the sign bit clear and the
24
+ * frac msb set; with the older mode, the sign bit is clear, and all
25
+ * frac bits except the msb are set.
26
+ */
27
+ set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111,
28
+ &env->active_fpu.fp_status);
29
30
}
31
32
diff --git a/target/mips/msa.c b/target/mips/msa.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/mips/msa.c
35
+++ b/target/mips/msa.c
36
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
37
/* Inf * 0 + NaN returns the input NaN */
38
set_float_infzeronan_rule(float_infzeronan_dnan_never,
39
&env->active_tc.msa_fp_status);
40
+ /* Default NaN: sign bit clear, frac msb set */
41
+ set_float_default_nan_pattern(0b01000000,
42
+ &env->active_tc.msa_fp_status);
43
}
44
--
45
2.34.1
diff view generated by jsdifflib
New patch
[PULL 50/72] target/openrisc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for openrisc.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-45-peter.maydell@linaro.org
6
---
7
target/openrisc/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/openrisc/cpu.c
13
+++ b/target/openrisc/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type)
15
*/
16
set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status);
17
18
+ /* Default NaN: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status);
20
21
#ifndef CONFIG_USER_ONLY
22
cpu->env.picmr = 0x00000000;
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 51/72] target/ppc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for ppc.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-46-peter.maydell@linaro.org
6
---
7
target/ppc/cpu_init.c | 4 ++++
8
1 file changed, 4 insertions(+)
9
10
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/ppc/cpu_init.c
13
+++ b/target/ppc/cpu_init.c
14
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
15
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
17
18
+ /* Default NaN: sign bit clear, set frac msb */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
+ set_float_default_nan_pattern(0b01000000, &env->vec_status);
21
+
22
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
23
ppc_spr_t *spr = &env->spr_cb[i];
24
25
--
26
2.34.1
diff view generated by jsdifflib
New patch
[PULL 52/72] target/sh4: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for sh4. Note that sh4
2
is one of the only three targets (the others being HPPA and
3
sometimes MIPS) that has snan_bit_is_one set.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-47-peter.maydell@linaro.org
8
---
9
target/sh4/cpu.c | 2 ++
10
1 file changed, 2 insertions(+)
11
12
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sh4/cpu.c
15
+++ b/target/sh4/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
17
set_flush_to_zero(1, &env->fp_status);
18
#endif
19
set_default_nan_mode(1, &env->fp_status);
20
+ /* sign bit clear, set all frac bits other than msb */
21
+ set_float_default_nan_pattern(0b00111111, &env->fp_status);
22
}
23
24
static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
25
--
26
2.34.1
diff view generated by jsdifflib
New patch
[PULL 53/72] target/rx: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for rx.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-48-peter.maydell@linaro.org
6
---
7
target/rx/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/rx/cpu.c
13
+++ b/target/rx/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj, ResetType type)
15
* then prefer dest over source", which is float_2nan_prop_s_ab.
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
18
+ /* Default NaN value: sign bit clear, set frac msb */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
}
21
22
static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 54/72] target/s390x: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for s390x.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-49-peter.maydell@linaro.org
6
---
7
target/s390x/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/s390x/cpu.c
13
+++ b/target/s390x/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
15
set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
16
set_float_infzeronan_rule(float_infzeronan_dnan_always,
17
&env->fpu_status);
18
+ /* Default NaN value: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fpu_status);
20
/* fall through */
21
case RESET_TYPE_S390_CPU_NORMAL:
22
env->psw.mask &= ~PSW_MASK_RI;
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 55/72] target/sparc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for SPARC, and remove
2
the ifdef from parts64_default_nan.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-50-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 5 +----
10
2 files changed, 3 insertions(+), 4 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN value: sign bit clear, all frac bits set */
21
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
uint8_t dnan_pattern = status->default_nan_pattern;
31
32
if (dnan_pattern == 0) {
33
-#if defined(TARGET_SPARC)
34
- /* Sign bit clear, all frac bits set */
35
- dnan_pattern = 0b01111111;
36
-#elif defined(TARGET_HEXAGON)
37
+#if defined(TARGET_HEXAGON)
38
/* Sign bit set, all frac bits set. */
39
dnan_pattern = 0b11111111;
40
#else
41
--
42
2.34.1
diff view generated by jsdifflib
[PULL 18/31] hw/arm: versal: Setup the ADMA with 128bit bus-width
[PULL 56/72] target/xtensa: Set default NaN pattern explicitly
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
Set the default NaN pattern explicitly for xtensa.
2
2
3
Setup the ADMA with 128bit bus-width. This matters when
4
FIXED BURST mode is used.
5
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Message-id: 20200417153800.27399-2-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-51-peter.maydell@linaro.org
11
---
6
---
12
hw/arm/xlnx-versal.c | 2 ++
7
target/xtensa/cpu.c | 2 ++
13
1 file changed, 2 insertions(+)
8
1 file changed, 2 insertions(+)
14
9
15
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
10
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
16
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/xlnx-versal.c
12
--- a/target/xtensa/cpu.c
18
+++ b/hw/arm/xlnx-versal.c
13
+++ b/target/xtensa/cpu.c
19
@@ -XXX,XX +XXX,XX @@ static void versal_create_admas(Versal *s, qemu_irq *pic)
14
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
20
15
/* For inf * 0 + NaN, return the input NaN */
21
dev = qdev_create(NULL, "xlnx.zdma");
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
s->lpd.iou.adma[i] = SYS_BUS_DEVICE(dev);
17
set_no_signaling_nans(!dfpu, &env->fp_status);
23
+ object_property_set_int(OBJECT(s->lpd.iou.adma[i]), 128, "bus-width",
18
+ /* Default NaN value: sign bit clear, set frac msb */
24
+ &error_abort);
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
25
object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
20
xtensa_use_first_nan(env, !dfpu);
26
qdev_init_nofail(dev);
21
}
27
22
28
--
23
--
29
2.20.1
24
2.34.1
30
31
diff view generated by jsdifflib
[PULL 31/31] hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes
[PULL 57/72] target/hexagon: Set default NaN pattern explicitly
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
Set the default NaN pattern explicitly for hexagon.
2
Remove the ifdef from parts64_default_nan(); the only
3
remaining unconverted targets all use the default case.
2
4
3
Disable unsupported FDT firmware nodes if a user passes us
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
a DTB with nodes enabled that the machine cannot support
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
due to lack of EL3 or EL2 support.
7
Message-id: 20241202131347.498124-52-peter.maydell@linaro.org
8
---
9
target/hexagon/cpu.c | 2 ++
10
fpu/softfloat-specialize.c.inc | 5 -----
11
2 files changed, 2 insertions(+), 5 deletions(-)
6
12
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
8
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
9
Message-id: 20200423121114.4274-5-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/xlnx-zcu102.c | 30 ++++++++++++++++++++++++++++++
13
1 file changed, 30 insertions(+)
14
15
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/xlnx-zcu102.c
15
--- a/target/hexagon/cpu.c
18
+++ b/hw/arm/xlnx-zcu102.c
16
+++ b/target/hexagon/cpu.c
19
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
20
#include "qemu/error-report.h"
18
21
#include "qemu/log.h"
19
set_default_nan_mode(1, &env->fp_status);
22
#include "sysemu/qtest.h"
20
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
23
+#include "sysemu/device_tree.h"
21
+ /* Default NaN value: sign bit set, all frac bits set */
24
22
+ set_float_default_nan_pattern(0b11111111, &env->fp_status);
25
typedef struct XlnxZCU102 {
26
MachineState parent_obj;
27
@@ -XXX,XX +XXX,XX @@ static void zcu102_set_virt(Object *obj, bool value, Error **errp)
28
s->virt = value;
29
}
23
}
30
24
31
+static void zcu102_modify_dtb(const struct arm_boot_info *binfo, void *fdt)
25
static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
32
+{
26
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
33
+ XlnxZCU102 *s = container_of(binfo, XlnxZCU102, binfo);
27
index XXXXXXX..XXXXXXX 100644
34
+ bool method_is_hvc;
28
--- a/fpu/softfloat-specialize.c.inc
35
+ char **node_path;
29
+++ b/fpu/softfloat-specialize.c.inc
36
+ const char *r;
30
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
37
+ int prop_len;
31
uint8_t dnan_pattern = status->default_nan_pattern;
38
+ int i;
32
39
+
33
if (dnan_pattern == 0) {
40
+ /* If EL3 is enabled, we keep all firmware nodes active. */
34
-#if defined(TARGET_HEXAGON)
41
+ if (!s->secure) {
35
- /* Sign bit set, all frac bits set. */
42
+ node_path = qemu_fdt_node_path(fdt, NULL, "xlnx,zynqmp-firmware",
36
- dnan_pattern = 0b11111111;
43
+ &error_fatal);
37
-#else
44
+
38
/*
45
+ for (i = 0; node_path && node_path[i]; i++) {
39
* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
46
+ r = qemu_fdt_getprop(fdt, node_path[i], "method", &prop_len, NULL);
40
* S390, SH4, TriCore, and Xtensa. Our other supported targets
47
+ method_is_hvc = r && !strcmp("hvc", r);
41
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
48
+
42
/* sign bit clear, set frac msb */
49
+ /* Allow HVC based firmware if EL2 is enabled. */
43
dnan_pattern = 0b01000000;
50
+ if (method_is_hvc && s->virt) {
44
}
51
+ continue;
45
-#endif
52
+ }
46
}
53
+ qemu_fdt_setprop_string(fdt, node_path[i], "status", "disabled");
47
assert(dnan_pattern != 0);
54
+ }
55
+ g_strfreev(node_path);
56
+ }
57
+}
58
+
59
static void xlnx_zcu102_init(MachineState *machine)
60
{
61
XlnxZCU102 *s = ZCU102_MACHINE(machine);
62
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
63
64
s->binfo.ram_size = ram_size;
65
s->binfo.loader_start = 0;
66
+ s->binfo.modify_dtb = zcu102_modify_dtb;
67
arm_load_kernel(s->soc.boot_cpu_ptr, machine, &s->binfo);
68
}
69
48
70
--
49
--
71
2.20.1
50
2.34.1
72
73
diff view generated by jsdifflib
New patch
[PULL 58/72] target/riscv: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for riscv.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-53-peter.maydell@linaro.org
6
---
7
target/riscv/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/riscv/cpu.c
13
+++ b/target/riscv/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
15
cs->exception_index = RISCV_EXCP_NONE;
16
env->load_res = -1;
17
set_default_nan_mode(1, &env->fp_status);
18
+ /* Default NaN value: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
env->vill = true;
21
22
#ifndef CONFIG_USER_ONLY
23
--
24
2.34.1
diff view generated by jsdifflib
[PULL 30/31] hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102
[PULL 59/72] target/tricore: Set default NaN pattern explicitly
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
Set the default NaN pattern explicitly for tricore.
2
2
3
Move arm_boot_info into XlnxZCU102.
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-54-peter.maydell@linaro.org
6
---
7
target/tricore/helper.c | 2 ++
8
1 file changed, 2 insertions(+)
4
9
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Message-id: 20200423121114.4274-4-edgar.iglesias@gmail.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/arm/xlnx-zcu102.c | 9 +++++----
11
1 file changed, 5 insertions(+), 4 deletions(-)
12
13
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
14
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/xlnx-zcu102.c
12
--- a/target/tricore/helper.c
16
+++ b/hw/arm/xlnx-zcu102.c
13
+++ b/target/tricore/helper.c
17
@@ -XXX,XX +XXX,XX @@ typedef struct XlnxZCU102 {
14
@@ -XXX,XX +XXX,XX @@ void fpu_set_state(CPUTriCoreState *env)
18
15
set_flush_to_zero(1, &env->fp_status);
19
bool secure;
16
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
20
bool virt;
17
set_default_nan_mode(1, &env->fp_status);
21
+
18
+ /* Default NaN pattern: sign bit clear, frac msb set */
22
+ struct arm_boot_info binfo;
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
23
} XlnxZCU102;
24
25
#define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")
26
#define ZCU102_MACHINE(obj) \
27
OBJECT_CHECK(XlnxZCU102, (obj), TYPE_ZCU102_MACHINE)
28
29
-static struct arm_boot_info xlnx_zcu102_binfo;
30
31
static bool zcu102_get_secure(Object *obj, Error **errp)
32
{
33
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
34
35
/* TODO create and connect IDE devices for ide_drive_get() */
36
37
- xlnx_zcu102_binfo.ram_size = ram_size;
38
- xlnx_zcu102_binfo.loader_start = 0;
39
- arm_load_kernel(s->soc.boot_cpu_ptr, machine, &xlnx_zcu102_binfo);
40
+ s->binfo.ram_size = ram_size;
41
+ s->binfo.loader_start = 0;
42
+ arm_load_kernel(s->soc.boot_cpu_ptr, machine, &s->binfo);
43
}
20
}
44
21
45
static void xlnx_zcu102_machine_instance_init(Object *obj)
22
uint32_t psw_read(CPUTriCoreState *env)
46
--
23
--
47
2.20.1
24
2.34.1
48
49
diff view generated by jsdifflib
New patch
[PULL 60/72] fpu: Remove default handling for dnan_pattern
1
Now that all our targets have bene converted to explicitly specify
2
their pattern for the default NaN value we can remove the remaining
3
fallback code in parts64_default_nan().
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-55-peter.maydell@linaro.org
8
---
9
fpu/softfloat-specialize.c.inc | 14 --------------
10
1 file changed, 14 deletions(-)
11
12
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
13
index XXXXXXX..XXXXXXX 100644
14
--- a/fpu/softfloat-specialize.c.inc
15
+++ b/fpu/softfloat-specialize.c.inc
16
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
17
uint64_t frac;
18
uint8_t dnan_pattern = status->default_nan_pattern;
19
20
- if (dnan_pattern == 0) {
21
- /*
22
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
23
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
24
- * do not have floating-point.
25
- */
26
- if (snan_bit_is_one(status)) {
27
- /* sign bit clear, set all frac bits other than msb */
28
- dnan_pattern = 0b00111111;
29
- } else {
30
- /* sign bit clear, set frac msb */
31
- dnan_pattern = 0b01000000;
32
- }
33
- }
34
assert(dnan_pattern != 0);
35
36
sign = dnan_pattern >> 7;
37
--
38
2.34.1
diff view generated by jsdifflib
[PULL 29/31] device_tree: Constify compat in qemu_fdt_node_path()
[PULL 61/72] softfloat: Inline pickNaNMulAdd
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Make compat in qemu_fdt_node_path() const char *.
3
Inline pickNaNMulAdd into its only caller. This makes
4
one assert redundant with the immediately preceding IF.
4
5
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200423121114.4274-3-edgar.iglesias@gmail.com
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-3-richard.henderson@linaro.org
9
[PMM: keep comment from old code in new location]
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
include/sysemu/device_tree.h | 2 +-
12
fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++-
11
device_tree.c | 2 +-
13
fpu/softfloat-specialize.c.inc | 54 ----------------------------------
12
2 files changed, 2 insertions(+), 2 deletions(-)
14
2 files changed, 40 insertions(+), 55 deletions(-)
13
15
14
diff --git a/include/sysemu/device_tree.h b/include/sysemu/device_tree.h
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/include/sysemu/device_tree.h
18
--- a/fpu/softfloat-parts.c.inc
17
+++ b/include/sysemu/device_tree.h
19
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ void *load_device_tree_from_sysfs(void);
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
* @name may be NULL to wildcard names and only match compatibility
21
}
20
* strings.
22
21
*/
23
if (s->default_nan_mode) {
22
-char **qemu_fdt_node_path(void *fdt, const char *name, char *compat,
24
+ /*
23
+char **qemu_fdt_node_path(void *fdt, const char *name, const char *compat,
25
+ * We guarantee not to require the target to tell us how to
24
Error **errp);
26
+ * pick a NaN if we're always returning the default NaN.
25
27
+ * But if we're not in default-NaN mode then the target must
26
/**
28
+ * specify.
27
diff --git a/device_tree.c b/device_tree.c
29
+ */
30
which = 3;
31
+ } else if (infzero) {
32
+ /*
33
+ * Inf * 0 + NaN -- some implementations return the
34
+ * default NaN here, and some return the input NaN.
35
+ */
36
+ switch (s->float_infzeronan_rule) {
37
+ case float_infzeronan_dnan_never:
38
+ which = 2;
39
+ break;
40
+ case float_infzeronan_dnan_always:
41
+ which = 3;
42
+ break;
43
+ case float_infzeronan_dnan_if_qnan:
44
+ which = is_qnan(c->cls) ? 3 : 2;
45
+ break;
46
+ default:
47
+ g_assert_not_reached();
48
+ }
49
} else {
50
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
51
+ FloatClass cls[3] = { a->cls, b->cls, c->cls };
52
+ Float3NaNPropRule rule = s->float_3nan_prop_rule;
53
+
54
+ assert(rule != float_3nan_prop_none);
55
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
56
+ /* We have at least one SNaN input and should prefer it */
57
+ do {
58
+ which = rule & R_3NAN_1ST_MASK;
59
+ rule >>= R_3NAN_1ST_LENGTH;
60
+ } while (!is_snan(cls[which]));
61
+ } else {
62
+ do {
63
+ which = rule & R_3NAN_1ST_MASK;
64
+ rule >>= R_3NAN_1ST_LENGTH;
65
+ } while (!is_nan(cls[which]));
66
+ }
67
}
68
69
if (which == 3) {
70
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
71
index XXXXXXX..XXXXXXX 100644
29
--- a/device_tree.c
72
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/device_tree.c
73
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ char **qemu_fdt_node_unit_path(void *fdt, const char *name, Error **errp)
74
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
32
return path_array;
75
}
33
}
76
}
34
77
35
-char **qemu_fdt_node_path(void *fdt, const char *name, char *compat,
78
-/*----------------------------------------------------------------------------
36
+char **qemu_fdt_node_path(void *fdt, const char *name, const char *compat,
79
-| Select which NaN to propagate for a three-input operation.
37
Error **errp)
80
-| For the moment we assume that no CPU needs the 'larger significand'
38
{
81
-| information.
39
int offset, len, ret;
82
-| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
83
-*----------------------------------------------------------------------------*/
84
-static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
85
- bool infzero, bool have_snan, float_status *status)
86
-{
87
- FloatClass cls[3] = { a_cls, b_cls, c_cls };
88
- Float3NaNPropRule rule = status->float_3nan_prop_rule;
89
- int which;
90
-
91
- /*
92
- * We guarantee not to require the target to tell us how to
93
- * pick a NaN if we're always returning the default NaN.
94
- * But if we're not in default-NaN mode then the target must
95
- * specify.
96
- */
97
- assert(!status->default_nan_mode);
98
-
99
- if (infzero) {
100
- /*
101
- * Inf * 0 + NaN -- some implementations return the default NaN here,
102
- * and some return the input NaN.
103
- */
104
- switch (status->float_infzeronan_rule) {
105
- case float_infzeronan_dnan_never:
106
- return 2;
107
- case float_infzeronan_dnan_always:
108
- return 3;
109
- case float_infzeronan_dnan_if_qnan:
110
- return is_qnan(c_cls) ? 3 : 2;
111
- default:
112
- g_assert_not_reached();
113
- }
114
- }
115
-
116
- assert(rule != float_3nan_prop_none);
117
- if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
118
- /* We have at least one SNaN input and should prefer it */
119
- do {
120
- which = rule & R_3NAN_1ST_MASK;
121
- rule >>= R_3NAN_1ST_LENGTH;
122
- } while (!is_snan(cls[which]));
123
- } else {
124
- do {
125
- which = rule & R_3NAN_1ST_MASK;
126
- rule >>= R_3NAN_1ST_LENGTH;
127
- } while (!is_nan(cls[which]));
128
- }
129
- return which;
130
-}
131
-
132
/*----------------------------------------------------------------------------
133
| Returns 1 if the double-precision floating-point value `a' is a quiet
134
| NaN; otherwise returns 0.
40
--
135
--
41
2.20.1
136
2.34.1
42
137
43
138
diff view generated by jsdifflib
[PULL 16/31] hw/arm/xilinx_zynq: connect uart clocks to slcr
[PULL 62/72] softfloat: Use goto for default nan case in pick_nan_muladd
1
From: Damien Hedde <damien.hedde@greensocs.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add the connection between the slcr's output clocks and the uarts inputs.
3
Remove "3" as a special case for which and simply
4
branch to return the desired value.
4
5
5
Also add the main board clock 'ps_clk', which is hard-coded to 33.33MHz
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
(the default frequency). This clock is used to feed the slcr's input
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
clock.
8
Message-id: 20241203203949.483774-4-richard.henderson@linaro.org
8
9
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
12
Message-id: 20200406135251.157596-9-damien.hedde@greensocs.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
10
---
15
hw/arm/xilinx_zynq.c | 57 +++++++++++++++++++++++++++++++++++++-------
11
fpu/softfloat-parts.c.inc | 20 ++++++++++----------
16
1 file changed, 49 insertions(+), 8 deletions(-)
12
1 file changed, 10 insertions(+), 10 deletions(-)
17
13
18
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/xilinx_zynq.c
16
--- a/fpu/softfloat-parts.c.inc
21
+++ b/hw/arm/xilinx_zynq.c
17
+++ b/fpu/softfloat-parts.c.inc
22
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
23
#include "hw/char/cadence_uart.h"
19
* But if we're not in default-NaN mode then the target must
24
#include "hw/net/cadence_gem.h"
20
* specify.
25
#include "hw/cpu/a9mpcore.h"
21
*/
26
+#include "hw/qdev-clock.h"
22
- which = 3;
27
+#include "sysemu/reset.h"
23
+ goto default_nan;
24
} else if (infzero) {
25
/*
26
* Inf * 0 + NaN -- some implementations return the
27
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
28
*/
29
switch (s->float_infzeronan_rule) {
30
case float_infzeronan_dnan_never:
31
- which = 2;
32
break;
33
case float_infzeronan_dnan_always:
34
- which = 3;
35
- break;
36
+ goto default_nan;
37
case float_infzeronan_dnan_if_qnan:
38
- which = is_qnan(c->cls) ? 3 : 2;
39
+ if (is_qnan(c->cls)) {
40
+ goto default_nan;
41
+ }
42
break;
43
default:
44
g_assert_not_reached();
45
}
46
+ which = 2;
47
} else {
48
FloatClass cls[3] = { a->cls, b->cls, c->cls };
49
Float3NaNPropRule rule = s->float_3nan_prop_rule;
50
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
51
}
52
}
53
54
- if (which == 3) {
55
- parts_default_nan(a, s);
56
- return a;
57
- }
58
-
59
switch (which) {
60
case 0:
61
break;
62
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
63
parts_silence_nan(a, s);
64
}
65
return a;
28
+
66
+
29
+#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
67
+ default_nan:
30
+#define ZYNQ_MACHINE(obj) \
68
+ parts_default_nan(a, s);
31
+ OBJECT_CHECK(ZynqMachineState, (obj), TYPE_ZYNQ_MACHINE)
69
+ return a;
32
+
33
+/* board base frequency: 33.333333 MHz */
34
+#define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3)
35
36
#define NUM_SPI_FLASHES 4
37
#define NUM_QSPI_FLASHES 2
38
@@ -XXX,XX +XXX,XX @@ static const int dma_irqs[8] = {
39
0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
40
0xe5801000 + (addr)
41
42
+typedef struct ZynqMachineState {
43
+ MachineState parent;
44
+ Clock *ps_clk;
45
+} ZynqMachineState;
46
+
47
static void zynq_write_board_setup(ARMCPU *cpu,
48
const struct arm_boot_info *info)
49
{
50
@@ -XXX,XX +XXX,XX @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
51
52
static void zynq_init(MachineState *machine)
53
{
54
+ ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine);
55
ARMCPU *cpu;
56
MemoryRegion *address_space_mem = get_system_memory();
57
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
58
- DeviceState *dev;
59
+ DeviceState *dev, *slcr;
60
SysBusDevice *busdev;
61
qemu_irq pic[64];
62
int n;
63
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
64
1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
65
0);
66
67
- dev = qdev_create(NULL, "xilinx,zynq_slcr");
68
- qdev_init_nofail(dev);
69
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
70
+ /* Create slcr, keep a pointer to connect clocks */
71
+ slcr = qdev_create(NULL, "xilinx,zynq_slcr");
72
+ qdev_init_nofail(slcr);
73
+ sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
74
+
75
+ /* Create the main clock source, and feed slcr with it */
76
+ zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK));
77
+ object_property_add_child(OBJECT(zynq_machine), "ps_clk",
78
+ OBJECT(zynq_machine->ps_clk), &error_abort);
79
+ object_unref(OBJECT(zynq_machine->ps_clk));
80
+ clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
81
+ qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
82
83
dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
84
qdev_prop_set_uint32(dev, "num-cpu", 1);
85
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
86
sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
87
sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);
88
89
- cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
90
- cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));
91
+ dev = cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
92
+ qdev_connect_clock_in(dev, "refclk",
93
+ qdev_get_clock_out(slcr, "uart0_ref_clk"));
94
+ dev = cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));
95
+ qdev_connect_clock_in(dev, "refclk",
96
+ qdev_get_clock_out(slcr, "uart1_ref_clk"));
97
98
sysbus_create_varargs("cadence_ttc", 0xF8001000,
99
pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
100
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
101
arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo);
102
}
70
}
103
71
104
-static void zynq_machine_init(MachineClass *mc)
72
/*
105
+static void zynq_machine_class_init(ObjectClass *oc, void *data)
106
{
107
+ MachineClass *mc = MACHINE_CLASS(oc);
108
mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
109
mc->init = zynq_init;
110
mc->max_cpus = 1;
111
@@ -XXX,XX +XXX,XX @@ static void zynq_machine_init(MachineClass *mc)
112
mc->default_ram_id = "zynq.ext_ram";
113
}
114
115
-DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)
116
+static const TypeInfo zynq_machine_type = {
117
+ .name = TYPE_ZYNQ_MACHINE,
118
+ .parent = TYPE_MACHINE,
119
+ .class_init = zynq_machine_class_init,
120
+ .instance_size = sizeof(ZynqMachineState),
121
+};
122
+
123
+static void zynq_machine_register_types(void)
124
+{
125
+ type_register_static(&zynq_machine_type);
126
+}
127
+
128
+type_init(zynq_machine_register_types)
129
--
73
--
130
2.20.1
74
2.34.1
131
75
132
76
diff view generated by jsdifflib
[PULL 17/31] qdev-monitor: print the device's clock with info qtree
[PULL 63/72] softfloat: Remove which from parts_pick_nan_muladd
1
From: Damien Hedde <damien.hedde@greensocs.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This prints the clocks attached to a DeviceState when using
3
Assign the pointer return value to 'a' directly,
4
"info qtree" monitor command. For every clock, it displays the
4
rather than going through an intermediary index.
5
direction, the name and if the clock is forwarded. For input clock,
6
it displays also the frequency.
7
5
8
This is based on the original work of Frederic Konrad.
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Here follows a sample of `info qtree` output on xilinx_zynq machine
8
Message-id: 20241203203949.483774-5-richard.henderson@linaro.org
11
after linux boot with only one uart clocked:
12
> bus: main-system-bus
13
> type System
14
> [...]
15
> dev: cadence_uart, id ""
16
> gpio-out "sysbus-irq" 1
17
> clock-in "refclk" freq_hz=0.000000e+00
18
> chardev = ""
19
> mmio 00000000e0001000/0000000000001000
20
> dev: cadence_uart, id ""
21
> gpio-out "sysbus-irq" 1
22
> clock-in "refclk" freq_hz=1.375661e+07
23
> chardev = "serial0"
24
> mmio 00000000e0000000/0000000000001000
25
> [...]
26
> dev: xilinx,zynq_slcr, id ""
27
> clock-out "uart1_ref_clk" freq_hz=0.000000e+00
28
> clock-out "uart0_ref_clk" freq_hz=1.375661e+07
29
> clock-in "ps_clk" freq_hz=3.333333e+07
30
> mmio 00000000f8000000/0000000000001000
31
32
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
33
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
34
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
35
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
36
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
37
Message-id: 20200406135251.157596-10-damien.hedde@greensocs.com
38
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
39
---
10
---
40
qdev-monitor.c | 9 +++++++++
11
fpu/softfloat-parts.c.inc | 32 ++++++++++----------------------
41
1 file changed, 9 insertions(+)
12
1 file changed, 10 insertions(+), 22 deletions(-)
42
13
43
diff --git a/qdev-monitor.c b/qdev-monitor.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
44
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
45
--- a/qdev-monitor.c
16
--- a/fpu/softfloat-parts.c.inc
46
+++ b/qdev-monitor.c
17
+++ b/fpu/softfloat-parts.c.inc
47
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
48
#include "migration/misc.h"
19
FloatPartsN *c, float_status *s,
49
#include "migration/migration.h"
20
int ab_mask, int abc_mask)
50
#include "qemu/cutils.h"
21
{
51
+#include "hw/clock.h"
22
- int which;
52
23
bool infzero = (ab_mask == float_cmask_infzero);
53
/*
24
bool have_snan = (abc_mask & float_cmask_snan);
54
* Aliases were a bad idea from the start. Let's keep them
25
+ FloatPartsN *ret;
55
@@ -XXX,XX +XXX,XX @@ static void qdev_print(Monitor *mon, DeviceState *dev, int indent)
26
56
ObjectClass *class;
27
if (unlikely(have_snan)) {
57
BusState *child;
28
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
58
NamedGPIOList *ngl;
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
59
+ NamedClockList *ncl;
30
default:
60
31
g_assert_not_reached();
61
qdev_printf("dev: %s, id \"%s\"\n", object_get_typename(OBJECT(dev)),
32
}
62
dev->id ? dev->id : "");
33
- which = 2;
63
@@ -XXX,XX +XXX,XX @@ static void qdev_print(Monitor *mon, DeviceState *dev, int indent)
34
+ ret = c;
64
ngl->num_out);
35
} else {
36
- FloatClass cls[3] = { a->cls, b->cls, c->cls };
37
+ FloatPartsN *val[3] = { a, b, c };
38
Float3NaNPropRule rule = s->float_3nan_prop_rule;
39
40
assert(rule != float_3nan_prop_none);
41
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
42
/* We have at least one SNaN input and should prefer it */
43
do {
44
- which = rule & R_3NAN_1ST_MASK;
45
+ ret = val[rule & R_3NAN_1ST_MASK];
46
rule >>= R_3NAN_1ST_LENGTH;
47
- } while (!is_snan(cls[which]));
48
+ } while (!is_snan(ret->cls));
49
} else {
50
do {
51
- which = rule & R_3NAN_1ST_MASK;
52
+ ret = val[rule & R_3NAN_1ST_MASK];
53
rule >>= R_3NAN_1ST_LENGTH;
54
- } while (!is_nan(cls[which]));
55
+ } while (!is_nan(ret->cls));
65
}
56
}
66
}
57
}
67
+ QLIST_FOREACH(ncl, &dev->clocks, node) {
58
68
+ qdev_printf("clock-%s%s \"%s\" freq_hz=%e\n",
59
- switch (which) {
69
+ ncl->output ? "out" : "in",
60
- case 0:
70
+ ncl->alias ? " (alias)" : "",
61
- break;
71
+ ncl->name,
62
- case 1:
72
+ CLOCK_PERIOD_TO_HZ(1.0 * clock_get(ncl->clock)));
63
- a = b;
73
+ }
64
- break;
74
class = object_get_class(OBJECT(dev));
65
- case 2:
75
do {
66
- a = c;
76
qdev_print_props(mon, dev, DEVICE_CLASS(class)->props_, indent);
67
- break;
68
- default:
69
- g_assert_not_reached();
70
+ if (is_snan(ret->cls)) {
71
+ parts_silence_nan(ret, s);
72
}
73
- if (is_snan(a->cls)) {
74
- parts_silence_nan(a, s);
75
- }
76
- return a;
77
+ return ret;
78
79
default_nan:
80
parts_default_nan(a, s);
77
--
81
--
78
2.20.1
82
2.34.1
79
83
80
84
diff view generated by jsdifflib
[PULL 03/31] nrf51: Fix last GPIO CNF address
[PULL 64/72] softfloat: Pad array size in pick_nan_muladd
1
From: Cameron Esfahani <dirty@apple.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
NRF51_GPIO_REG_CNF_END doesn't actually refer to the start of the last
3
While all indices into val[] should be in [0-2], the mask
4
valid CNF register: it's referring to the last byte of the last valid
4
applied is two bits. To help static analysis see there is
5
CNF register.
5
no possibility of read beyond the end of the array, pad the
6
array to 4 entries, with the final being (implicitly) NULL.
6
7
7
This hasn't been a problem up to now, as current implementation in
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
memory.c turns an unaligned 4-byte read from 0x77f to a single byte read
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
and the qtest only looks at the least-significant byte of the register.
10
Message-id: 20241203203949.483774-6-richard.henderson@linaro.org
10
11
But when running with patches which fix unaligned accesses in memory.c,
12
the qtest breaks.
13
14
Considering NRF51 doesn't support unaligned accesses, the simplest fix
15
is to actually set NRF51_GPIO_REG_CNF_END to the start of the last valid
16
CNF register: 0x77c.
17
18
Now, qtests work with or without the unaligned access patches.
19
20
Reviewed-by: Cédric Le Goater <clg@kaod.org>
21
Tested-by: Cédric Le Goater <clg@kaod.org>
22
Reviewed-by: Joel Stanley <joel@jms.id.au>
23
Signed-off-by: Cameron Esfahani <dirty@apple.com>
24
Message-id: 51b427f06838622da783d38ba56e3630d6d85c60.1586925392.git.dirty@apple.com
25
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
---
12
---
28
include/hw/gpio/nrf51_gpio.h | 2 +-
13
fpu/softfloat-parts.c.inc | 2 +-
29
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
30
15
31
diff --git a/include/hw/gpio/nrf51_gpio.h b/include/hw/gpio/nrf51_gpio.h
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
32
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
33
--- a/include/hw/gpio/nrf51_gpio.h
18
--- a/fpu/softfloat-parts.c.inc
34
+++ b/include/hw/gpio/nrf51_gpio.h
19
+++ b/fpu/softfloat-parts.c.inc
35
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
36
#define NRF51_GPIO_REG_DIRSET 0x518
21
}
37
#define NRF51_GPIO_REG_DIRCLR 0x51C
22
ret = c;
38
#define NRF51_GPIO_REG_CNF_START 0x700
23
} else {
39
-#define NRF51_GPIO_REG_CNF_END 0x77F
24
- FloatPartsN *val[3] = { a, b, c };
40
+#define NRF51_GPIO_REG_CNF_END 0x77C
25
+ FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c };
41
26
Float3NaNPropRule rule = s->float_3nan_prop_rule;
42
#define NRF51_GPIO_PULLDOWN 1
27
43
#define NRF51_GPIO_PULLUP 3
28
assert(rule != float_3nan_prop_none);
44
--
29
--
45
2.20.1
30
2.34.1
46
31
47
32
diff view generated by jsdifflib
[PULL 11/31] qdev: add clock input&output support to devices.
[PULL 65/72] softfloat: Move propagateFloatx80NaN to softfloat.c
1
From: Damien Hedde <damien.hedde@greensocs.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add functions to easily handle clocks with devices.
3
This function is part of the public interface and
4
Clock inputs and outputs should be used to handle clock propagation
4
is not "specialized" to any target in any way.
5
between devices.
6
The API is very similar the GPIO API.
7
5
8
This is based on the original work of Frederic Konrad.
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
8
Message-id: 20241203203949.483774-7-richard.henderson@linaro.org
11
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-id: 20200406135251.157596-4-damien.hedde@greensocs.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
10
---
16
hw/core/Makefile.objs | 2 +-
11
fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++
17
tests/Makefile.include | 1 +
12
fpu/softfloat-specialize.c.inc | 52 ----------------------------------
18
include/hw/qdev-clock.h | 104 +++++++++++++++++++++++++
13
2 files changed, 52 insertions(+), 52 deletions(-)
19
include/hw/qdev-core.h | 12 +++
20
hw/core/qdev-clock.c | 168 ++++++++++++++++++++++++++++++++++++++++
21
hw/core/qdev.c | 12 +++
22
6 files changed, 298 insertions(+), 1 deletion(-)
23
create mode 100644 include/hw/qdev-clock.h
24
create mode 100644 hw/core/qdev-clock.c
25
14
26
diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
27
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/core/Makefile.objs
17
--- a/fpu/softfloat.c
29
+++ b/hw/core/Makefile.objs
18
+++ b/fpu/softfloat.c
30
@@ -XXX,XX +XXX,XX @@ common-obj-y += hotplug.o
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
31
common-obj-y += vmstate-if.o
20
*zExpPtr = 1 - shiftCount;
32
# irq.o needed for qdev GPIO handling:
21
}
33
common-obj-y += irq.o
22
34
-common-obj-y += clock.o
23
+/*----------------------------------------------------------------------------
35
+common-obj-y += clock.o qdev-clock.o
24
+| Takes two extended double-precision floating-point values `a' and `b', one
36
25
+| of which is a NaN, and returns the appropriate NaN result. If either `a' or
37
common-obj-$(CONFIG_SOFTMMU) += reset.o
26
+| `b' is a signaling NaN, the invalid exception is raised.
38
common-obj-$(CONFIG_SOFTMMU) += qdev-fw.o
27
+*----------------------------------------------------------------------------*/
39
diff --git a/tests/Makefile.include b/tests/Makefile.include
40
index XXXXXXX..XXXXXXX 100644
41
--- a/tests/Makefile.include
42
+++ b/tests/Makefile.include
43
@@ -XXX,XX +XXX,XX @@ tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \
44
    hw/core/fw-path-provider.o \
45
    hw/core/reset.o \
46
    hw/core/vmstate-if.o \
47
+    hw/core/clock.o hw/core/qdev-clock.o \
48
    $(test-qapi-obj-y)
49
tests/test-vmstate$(EXESUF): tests/test-vmstate.o \
50
    migration/vmstate.o migration/vmstate-types.o migration/qemu-file.o \
51
diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h
52
new file mode 100644
53
index XXXXXXX..XXXXXXX
54
--- /dev/null
55
+++ b/include/hw/qdev-clock.h
56
@@ -XXX,XX +XXX,XX @@
57
+/*
58
+ * Device's clock input and output
59
+ *
60
+ * Copyright GreenSocs 2016-2020
61
+ *
62
+ * Authors:
63
+ * Frederic Konrad
64
+ * Damien Hedde
65
+ *
66
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
67
+ * See the COPYING file in the top-level directory.
68
+ */
69
+
28
+
70
+#ifndef QDEV_CLOCK_H
29
+floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
71
+#define QDEV_CLOCK_H
30
+{
31
+ bool aIsLargerSignificand;
32
+ FloatClass a_cls, b_cls;
72
+
33
+
73
+#include "hw/clock.h"
34
+ /* This is not complete, but is good enough for pickNaN. */
35
+ a_cls = (!floatx80_is_any_nan(a)
36
+ ? float_class_normal
37
+ : floatx80_is_signaling_nan(a, status)
38
+ ? float_class_snan
39
+ : float_class_qnan);
40
+ b_cls = (!floatx80_is_any_nan(b)
41
+ ? float_class_normal
42
+ : floatx80_is_signaling_nan(b, status)
43
+ ? float_class_snan
44
+ : float_class_qnan);
74
+
45
+
75
+/**
46
+ if (is_snan(a_cls) || is_snan(b_cls)) {
76
+ * qdev_init_clock_in:
47
+ float_raise(float_flag_invalid, status);
77
+ * @dev: the device to add an input clock to
78
+ * @name: the name of the clock (can't be NULL).
79
+ * @callback: optional callback to be called on update or NULL.
80
+ * @opaque: argument for the callback
81
+ * @returns: a pointer to the newly added clock
82
+ *
83
+ * Add an input clock to device @dev as a clock named @name.
84
+ * This adds a child<> property.
85
+ * The callback will be called with @opaque as opaque parameter.
86
+ */
87
+Clock *qdev_init_clock_in(DeviceState *dev, const char *name,
88
+ ClockCallback *callback, void *opaque);
89
+
90
+/**
91
+ * qdev_init_clock_out:
92
+ * @dev: the device to add an output clock to
93
+ * @name: the name of the clock (can't be NULL).
94
+ * @returns: a pointer to the newly added clock
95
+ *
96
+ * Add an output clock to device @dev as a clock named @name.
97
+ * This adds a child<> property.
98
+ */
99
+Clock *qdev_init_clock_out(DeviceState *dev, const char *name);
100
+
101
+/**
102
+ * qdev_get_clock_in:
103
+ * @dev: the device which has the clock
104
+ * @name: the name of the clock (can't be NULL).
105
+ * @returns: a pointer to the clock
106
+ *
107
+ * Get the input clock @name from @dev or NULL if does not exist.
108
+ */
109
+Clock *qdev_get_clock_in(DeviceState *dev, const char *name);
110
+
111
+/**
112
+ * qdev_get_clock_out:
113
+ * @dev: the device which has the clock
114
+ * @name: the name of the clock (can't be NULL).
115
+ * @returns: a pointer to the clock
116
+ *
117
+ * Get the output clock @name from @dev or NULL if does not exist.
118
+ */
119
+Clock *qdev_get_clock_out(DeviceState *dev, const char *name);
120
+
121
+/**
122
+ * qdev_connect_clock_in:
123
+ * @dev: a device
124
+ * @name: the name of an input clock in @dev
125
+ * @source: the source clock (an output clock of another device for example)
126
+ *
127
+ * Set the source clock of input clock @name of device @dev to @source.
128
+ * @source period update will be propagated to @name clock.
129
+ */
130
+static inline void qdev_connect_clock_in(DeviceState *dev, const char *name,
131
+ Clock *source)
132
+{
133
+ clock_set_source(qdev_get_clock_in(dev, name), source);
134
+}
135
+
136
+/**
137
+ * qdev_alias_clock:
138
+ * @dev: the device which has the clock
139
+ * @name: the name of the clock in @dev (can't be NULL)
140
+ * @alias_dev: the device to add the clock
141
+ * @alias_name: the name of the clock in @container
142
+ * @returns: a pointer to the clock
143
+ *
144
+ * Add a clock @alias_name in @alias_dev which is an alias of the clock @name
145
+ * in @dev. The direction _in_ or _out_ will the same as the original.
146
+ * An alias clock must not be modified or used by @alias_dev and should
147
+ * typically be only only for device composition purpose.
148
+ */
149
+Clock *qdev_alias_clock(DeviceState *dev, const char *name,
150
+ DeviceState *alias_dev, const char *alias_name);
151
+
152
+/**
153
+ * qdev_finalize_clocklist:
154
+ * @dev: the device being finalized
155
+ *
156
+ * Clear the clocklist from @dev. Only used internally in qdev.
157
+ */
158
+void qdev_finalize_clocklist(DeviceState *dev);
159
+
160
+#endif /* QDEV_CLOCK_H */
161
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
162
index XXXXXXX..XXXXXXX 100644
163
--- a/include/hw/qdev-core.h
164
+++ b/include/hw/qdev-core.h
165
@@ -XXX,XX +XXX,XX @@ struct NamedGPIOList {
166
QLIST_ENTRY(NamedGPIOList) node;
167
};
168
169
+typedef struct Clock Clock;
170
+typedef struct NamedClockList NamedClockList;
171
+
172
+struct NamedClockList {
173
+ char *name;
174
+ Clock *clock;
175
+ bool output;
176
+ bool alias;
177
+ QLIST_ENTRY(NamedClockList) node;
178
+};
179
+
180
/**
181
* DeviceState:
182
* @realized: Indicates whether the device has been fully constructed.
183
@@ -XXX,XX +XXX,XX @@ struct DeviceState {
184
bool allow_unplug_during_migration;
185
BusState *parent_bus;
186
QLIST_HEAD(, NamedGPIOList) gpios;
187
+ QLIST_HEAD(, NamedClockList) clocks;
188
QLIST_HEAD(, BusState) child_bus;
189
int num_child_bus;
190
int instance_id_alias;
191
diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c
192
new file mode 100644
193
index XXXXXXX..XXXXXXX
194
--- /dev/null
195
+++ b/hw/core/qdev-clock.c
196
@@ -XXX,XX +XXX,XX @@
197
+/*
198
+ * Device's clock input and output
199
+ *
200
+ * Copyright GreenSocs 2016-2020
201
+ *
202
+ * Authors:
203
+ * Frederic Konrad
204
+ * Damien Hedde
205
+ *
206
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
207
+ * See the COPYING file in the top-level directory.
208
+ */
209
+
210
+#include "qemu/osdep.h"
211
+#include "hw/qdev-clock.h"
212
+#include "hw/qdev-core.h"
213
+#include "qapi/error.h"
214
+
215
+/*
216
+ * qdev_init_clocklist:
217
+ * Add a new clock in a device
218
+ */
219
+static NamedClockList *qdev_init_clocklist(DeviceState *dev, const char *name,
220
+ bool output, Clock *clk)
221
+{
222
+ NamedClockList *ncl;
223
+
224
+ /*
225
+ * Clock must be added before realize() so that we can compute the
226
+ * clock's canonical path during device_realize().
227
+ */
228
+ assert(!dev->realized);
229
+
230
+ /*
231
+ * The ncl structure is freed by qdev_finalize_clocklist() which will
232
+ * be called during @dev's device_finalize().
233
+ */
234
+ ncl = g_new0(NamedClockList, 1);
235
+ ncl->name = g_strdup(name);
236
+ ncl->output = output;
237
+ ncl->alias = (clk != NULL);
238
+
239
+ /*
240
+ * Trying to create a clock whose name clashes with some other
241
+ * clock or property is a bug in the caller and we will abort().
242
+ */
243
+ if (clk == NULL) {
244
+ clk = CLOCK(object_new(TYPE_CLOCK));
245
+ object_property_add_child(OBJECT(dev), name, OBJECT(clk), &error_abort);
246
+ if (output) {
247
+ /*
248
+ * Remove object_new()'s initial reference.
249
+ * Note that for inputs, the reference created by object_new()
250
+ * will be deleted in qdev_finalize_clocklist().
251
+ */
252
+ object_unref(OBJECT(clk));
253
+ }
254
+ } else {
255
+ object_property_add_link(OBJECT(dev), name,
256
+ object_get_typename(OBJECT(clk)),
257
+ (Object **) &ncl->clock,
258
+ NULL, OBJ_PROP_LINK_STRONG, &error_abort);
259
+ }
48
+ }
260
+
49
+
261
+ ncl->clock = clk;
50
+ if (status->default_nan_mode) {
51
+ return floatx80_default_nan(status);
52
+ }
262
+
53
+
263
+ QLIST_INSERT_HEAD(&dev->clocks, ncl, node);
54
+ if (a.low < b.low) {
264
+ return ncl;
55
+ aIsLargerSignificand = 0;
265
+}
56
+ } else if (b.low < a.low) {
57
+ aIsLargerSignificand = 1;
58
+ } else {
59
+ aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
60
+ }
266
+
61
+
267
+void qdev_finalize_clocklist(DeviceState *dev)
62
+ if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
268
+{
63
+ if (is_snan(b_cls)) {
269
+ /* called by @dev's device_finalize() */
64
+ return floatx80_silence_nan(b, status);
270
+ NamedClockList *ncl, *ncl_next;
271
+
272
+ QLIST_FOREACH_SAFE(ncl, &dev->clocks, node, ncl_next) {
273
+ QLIST_REMOVE(ncl, node);
274
+ if (!ncl->output && !ncl->alias) {
275
+ /*
276
+ * We kept a reference on the input clock to ensure it lives up to
277
+ * this point so we can safely remove the callback.
278
+ * It avoids having a callback to a deleted object if ncl->clock
279
+ * is still referenced somewhere else (eg: by a clock output).
280
+ */
281
+ clock_clear_callback(ncl->clock);
282
+ object_unref(OBJECT(ncl->clock));
283
+ }
65
+ }
284
+ g_free(ncl->name);
66
+ return b;
285
+ g_free(ncl);
67
+ } else {
68
+ if (is_snan(a_cls)) {
69
+ return floatx80_silence_nan(a, status);
70
+ }
71
+ return a;
286
+ }
72
+ }
287
+}
73
+}
288
+
74
+
289
+Clock *qdev_init_clock_out(DeviceState *dev, const char *name)
75
/*----------------------------------------------------------------------------
290
+{
76
| Takes an abstract floating-point value having sign `zSign', exponent `zExp',
291
+ NamedClockList *ncl;
77
| and extended significand formed by the concatenation of `zSig0' and `zSig1',
292
+
78
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
293
+ assert(name);
294
+
295
+ ncl = qdev_init_clocklist(dev, name, true, NULL);
296
+
297
+ return ncl->clock;
298
+}
299
+
300
+Clock *qdev_init_clock_in(DeviceState *dev, const char *name,
301
+ ClockCallback *callback, void *opaque)
302
+{
303
+ NamedClockList *ncl;
304
+
305
+ assert(name);
306
+
307
+ ncl = qdev_init_clocklist(dev, name, false, NULL);
308
+
309
+ if (callback) {
310
+ clock_set_callback(ncl->clock, callback, opaque);
311
+ }
312
+ return ncl->clock;
313
+}
314
+
315
+static NamedClockList *qdev_get_clocklist(DeviceState *dev, const char *name)
316
+{
317
+ NamedClockList *ncl;
318
+
319
+ QLIST_FOREACH(ncl, &dev->clocks, node) {
320
+ if (strcmp(name, ncl->name) == 0) {
321
+ return ncl;
322
+ }
323
+ }
324
+
325
+ return NULL;
326
+}
327
+
328
+Clock *qdev_get_clock_in(DeviceState *dev, const char *name)
329
+{
330
+ NamedClockList *ncl;
331
+
332
+ assert(name);
333
+
334
+ ncl = qdev_get_clocklist(dev, name);
335
+ assert(!ncl->output);
336
+
337
+ return ncl->clock;
338
+}
339
+
340
+Clock *qdev_get_clock_out(DeviceState *dev, const char *name)
341
+{
342
+ NamedClockList *ncl;
343
+
344
+ assert(name);
345
+
346
+ ncl = qdev_get_clocklist(dev, name);
347
+ assert(ncl->output);
348
+
349
+ return ncl->clock;
350
+}
351
+
352
+Clock *qdev_alias_clock(DeviceState *dev, const char *name,
353
+ DeviceState *alias_dev, const char *alias_name)
354
+{
355
+ NamedClockList *ncl;
356
+
357
+ assert(name && alias_name);
358
+
359
+ ncl = qdev_get_clocklist(dev, name);
360
+
361
+ qdev_init_clocklist(alias_dev, alias_name, ncl->output, ncl->clock);
362
+
363
+ return ncl->clock;
364
+}
365
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
366
index XXXXXXX..XXXXXXX 100644
79
index XXXXXXX..XXXXXXX 100644
367
--- a/hw/core/qdev.c
80
--- a/fpu/softfloat-specialize.c.inc
368
+++ b/hw/core/qdev.c
81
+++ b/fpu/softfloat-specialize.c.inc
369
@@ -XXX,XX +XXX,XX @@
82
@@ -XXX,XX +XXX,XX @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
370
#include "hw/qdev-properties.h"
83
return a;
371
#include "hw/boards.h"
372
#include "hw/sysbus.h"
373
+#include "hw/qdev-clock.h"
374
#include "migration/vmstate.h"
375
#include "trace.h"
376
377
@@ -XXX,XX +XXX,XX @@ static void device_set_realized(Object *obj, bool value, Error **errp)
378
DeviceClass *dc = DEVICE_GET_CLASS(dev);
379
HotplugHandler *hotplug_ctrl;
380
BusState *bus;
381
+ NamedClockList *ncl;
382
Error *local_err = NULL;
383
bool unattached_parent = false;
384
static int unattached_count;
385
@@ -XXX,XX +XXX,XX @@ static void device_set_realized(Object *obj, bool value, Error **errp)
386
*/
387
g_free(dev->canonical_path);
388
dev->canonical_path = object_get_canonical_path(OBJECT(dev));
389
+ QLIST_FOREACH(ncl, &dev->clocks, node) {
390
+ if (ncl->alias) {
391
+ continue;
392
+ } else {
393
+ clock_setup_canonical_path(ncl->clock);
394
+ }
395
+ }
396
397
if (qdev_get_vmsd(dev)) {
398
if (vmstate_register_with_alias_id(VMSTATE_IF(dev),
399
@@ -XXX,XX +XXX,XX @@ static void device_initfn(Object *obj)
400
dev->allow_unplug_during_migration = false;
401
402
QLIST_INIT(&dev->gpios);
403
+ QLIST_INIT(&dev->clocks);
404
}
84
}
405
85
406
static void device_post_init(Object *obj)
86
-/*----------------------------------------------------------------------------
407
@@ -XXX,XX +XXX,XX @@ static void device_finalize(Object *obj)
87
-| Takes two extended double-precision floating-point values `a' and `b', one
408
*/
88
-| of which is a NaN, and returns the appropriate NaN result. If either `a' or
409
}
89
-| `b' is a signaling NaN, the invalid exception is raised.
410
90
-*----------------------------------------------------------------------------*/
411
+ qdev_finalize_clocklist(dev);
91
-
412
+
92
-floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
413
/* Only send event if the device had been completely realized */
93
-{
414
if (dev->pending_deleted_event) {
94
- bool aIsLargerSignificand;
415
g_assert(dev->canonical_path);
95
- FloatClass a_cls, b_cls;
96
-
97
- /* This is not complete, but is good enough for pickNaN. */
98
- a_cls = (!floatx80_is_any_nan(a)
99
- ? float_class_normal
100
- : floatx80_is_signaling_nan(a, status)
101
- ? float_class_snan
102
- : float_class_qnan);
103
- b_cls = (!floatx80_is_any_nan(b)
104
- ? float_class_normal
105
- : floatx80_is_signaling_nan(b, status)
106
- ? float_class_snan
107
- : float_class_qnan);
108
-
109
- if (is_snan(a_cls) || is_snan(b_cls)) {
110
- float_raise(float_flag_invalid, status);
111
- }
112
-
113
- if (status->default_nan_mode) {
114
- return floatx80_default_nan(status);
115
- }
116
-
117
- if (a.low < b.low) {
118
- aIsLargerSignificand = 0;
119
- } else if (b.low < a.low) {
120
- aIsLargerSignificand = 1;
121
- } else {
122
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
123
- }
124
-
125
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
126
- if (is_snan(b_cls)) {
127
- return floatx80_silence_nan(b, status);
128
- }
129
- return b;
130
- } else {
131
- if (is_snan(a_cls)) {
132
- return floatx80_silence_nan(a, status);
133
- }
134
- return a;
135
- }
136
-}
137
-
138
/*----------------------------------------------------------------------------
139
| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
140
| NaN; otherwise returns 0.
416
--
141
--
417
2.20.1
142
2.34.1
418
419
diff view generated by jsdifflib
[PULL 21/31] target/arm: Vectorize integer comparison vs zero
[PULL 66/72] softfloat: Use parts_pick_nan in propagateFloatx80NaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
These instructions are often used in glibc's string routines.
3
Unpacking and repacking the parts may be slightly more work
4
They were the final uses of the 32-bit at a time neon helpers.
4
than we did before, but we get to reuse more code. For a
5
code path handling exceptional values, this is an improvement.
5
6
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200418162808.4680-1-richard.henderson@linaro.org
8
Message-id: 20241203203949.483774-8-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
target/arm/helper.h | 27 ++--
12
fpu/softfloat.c | 43 +++++--------------------------------------
12
target/arm/translate.h | 5 +
13
1 file changed, 5 insertions(+), 38 deletions(-)
13
target/arm/neon_helper.c | 24 ----
14
target/arm/translate-a64.c | 64 +++-------
15
target/arm/translate.c | 256 +++++++++++++++++++++++++++++++------
16
target/arm/vec_helper.c | 25 ++++
17
6 files changed, 278 insertions(+), 123 deletions(-)
18
14
19
diff --git a/target/arm/helper.h b/target/arm/helper.h
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
20
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper.h
17
--- a/fpu/softfloat.c
22
+++ b/target/arm/helper.h
18
+++ b/fpu/softfloat.c
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(neon_hsub_u16, i32, i32, i32)
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
24
DEF_HELPER_2(neon_hsub_s32, s32, s32, s32)
20
25
DEF_HELPER_2(neon_hsub_u32, i32, i32, i32)
21
floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
26
22
{
27
-DEF_HELPER_2(neon_cgt_u8, i32, i32, i32)
23
- bool aIsLargerSignificand;
28
-DEF_HELPER_2(neon_cgt_s8, i32, i32, i32)
24
- FloatClass a_cls, b_cls;
29
-DEF_HELPER_2(neon_cgt_u16, i32, i32, i32)
25
+ FloatParts128 pa, pb, *pr;
30
-DEF_HELPER_2(neon_cgt_s16, i32, i32, i32)
26
31
-DEF_HELPER_2(neon_cgt_u32, i32, i32, i32)
27
- /* This is not complete, but is good enough for pickNaN. */
32
-DEF_HELPER_2(neon_cgt_s32, i32, i32, i32)
28
- a_cls = (!floatx80_is_any_nan(a)
33
-DEF_HELPER_2(neon_cge_u8, i32, i32, i32)
29
- ? float_class_normal
34
-DEF_HELPER_2(neon_cge_s8, i32, i32, i32)
30
- : floatx80_is_signaling_nan(a, status)
35
-DEF_HELPER_2(neon_cge_u16, i32, i32, i32)
31
- ? float_class_snan
36
-DEF_HELPER_2(neon_cge_s16, i32, i32, i32)
32
- : float_class_qnan);
37
-DEF_HELPER_2(neon_cge_u32, i32, i32, i32)
33
- b_cls = (!floatx80_is_any_nan(b)
38
-DEF_HELPER_2(neon_cge_s32, i32, i32, i32)
34
- ? float_class_normal
35
- : floatx80_is_signaling_nan(b, status)
36
- ? float_class_snan
37
- : float_class_qnan);
39
-
38
-
40
DEF_HELPER_2(neon_pmin_u8, i32, i32, i32)
39
- if (is_snan(a_cls) || is_snan(b_cls)) {
41
DEF_HELPER_2(neon_pmin_s8, i32, i32, i32)
40
- float_raise(float_flag_invalid, status);
42
DEF_HELPER_2(neon_pmin_u16, i32, i32, i32)
41
- }
43
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(neon_mul_u16, i32, i32, i32)
42
-
44
DEF_HELPER_2(neon_tst_u8, i32, i32, i32)
43
- if (status->default_nan_mode) {
45
DEF_HELPER_2(neon_tst_u16, i32, i32, i32)
44
+ if (!floatx80_unpack_canonical(&pa, a, status) ||
46
DEF_HELPER_2(neon_tst_u32, i32, i32, i32)
45
+ !floatx80_unpack_canonical(&pb, b, status)) {
47
-DEF_HELPER_2(neon_ceq_u8, i32, i32, i32)
46
return floatx80_default_nan(status);
48
-DEF_HELPER_2(neon_ceq_u16, i32, i32, i32)
47
}
49
-DEF_HELPER_2(neon_ceq_u32, i32, i32, i32)
48
50
49
- if (a.low < b.low) {
51
DEF_HELPER_1(neon_clz_u8, i32, i32)
50
- aIsLargerSignificand = 0;
52
DEF_HELPER_1(neon_clz_u16, i32, i32)
51
- } else if (b.low < a.low) {
53
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, ptr)
52
- aIsLargerSignificand = 1;
54
DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr)
53
- } else {
55
DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr)
54
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
56
55
- }
57
+DEF_HELPER_FLAGS_3(gvec_ceq0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
56
-
58
+DEF_HELPER_FLAGS_3(gvec_ceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
57
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
59
+DEF_HELPER_FLAGS_3(gvec_clt0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
58
- if (is_snan(b_cls)) {
60
+DEF_HELPER_FLAGS_3(gvec_clt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
59
- return floatx80_silence_nan(b, status);
61
+DEF_HELPER_FLAGS_3(gvec_cle0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
60
- }
62
+DEF_HELPER_FLAGS_3(gvec_cle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
61
- return b;
63
+DEF_HELPER_FLAGS_3(gvec_cgt0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
62
- } else {
64
+DEF_HELPER_FLAGS_3(gvec_cgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
63
- if (is_snan(a_cls)) {
65
+DEF_HELPER_FLAGS_3(gvec_cge0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
64
- return floatx80_silence_nan(a, status);
66
+DEF_HELPER_FLAGS_3(gvec_cge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
65
- }
67
+
66
- return a;
68
DEF_HELPER_FLAGS_4(gvec_sshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
67
- }
69
DEF_HELPER_FLAGS_4(gvec_sshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
68
+ pr = parts_pick_nan(&pa, &pb, status);
70
DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
69
+ return floatx80_round_pack_canonical(pr, status);
71
diff --git a/target/arm/translate.h b/target/arm/translate.h
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/translate.h
74
+++ b/target/arm/translate.h
75
@@ -XXX,XX +XXX,XX @@ static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
76
uint64_t vfp_expand_imm(int size, uint8_t imm8);
77
78
/* Vector operations shared between ARM and AArch64. */
79
+extern const GVecGen2 ceq0_op[4];
80
+extern const GVecGen2 clt0_op[4];
81
+extern const GVecGen2 cgt0_op[4];
82
+extern const GVecGen2 cle0_op[4];
83
+extern const GVecGen2 cge0_op[4];
84
extern const GVecGen3 mla_op[4];
85
extern const GVecGen3 mls_op[4];
86
extern const GVecGen3 cmtst_op[4];
87
diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/target/arm/neon_helper.c
90
+++ b/target/arm/neon_helper.c
91
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_hsub_u32)(uint32_t src1, uint32_t src2)
92
return dest;
93
}
70
}
94
71
95
-#define NEON_FN(dest, src1, src2) dest = (src1 > src2) ? ~0 : 0
72
/*----------------------------------------------------------------------------
96
-NEON_VOP(cgt_s8, neon_s8, 4)
97
-NEON_VOP(cgt_u8, neon_u8, 4)
98
-NEON_VOP(cgt_s16, neon_s16, 2)
99
-NEON_VOP(cgt_u16, neon_u16, 2)
100
-NEON_VOP(cgt_s32, neon_s32, 1)
101
-NEON_VOP(cgt_u32, neon_u32, 1)
102
-#undef NEON_FN
103
-
104
-#define NEON_FN(dest, src1, src2) dest = (src1 >= src2) ? ~0 : 0
105
-NEON_VOP(cge_s8, neon_s8, 4)
106
-NEON_VOP(cge_u8, neon_u8, 4)
107
-NEON_VOP(cge_s16, neon_s16, 2)
108
-NEON_VOP(cge_u16, neon_u16, 2)
109
-NEON_VOP(cge_s32, neon_s32, 1)
110
-NEON_VOP(cge_u32, neon_u32, 1)
111
-#undef NEON_FN
112
-
113
#define NEON_FN(dest, src1, src2) dest = (src1 < src2) ? src1 : src2
114
NEON_POP(pmin_s8, neon_s8, 4)
115
NEON_POP(pmin_u8, neon_u8, 4)
116
@@ -XXX,XX +XXX,XX @@ NEON_VOP(tst_u16, neon_u16, 2)
117
NEON_VOP(tst_u32, neon_u32, 1)
118
#undef NEON_FN
119
120
-#define NEON_FN(dest, src1, src2) dest = (src1 == src2) ? -1 : 0
121
-NEON_VOP(ceq_u8, neon_u8, 4)
122
-NEON_VOP(ceq_u16, neon_u16, 2)
123
-NEON_VOP(ceq_u32, neon_u32, 1)
124
-#undef NEON_FN
125
-
126
/* Count Leading Sign/Zero Bits. */
127
static inline int do_clz8(uint8_t x)
128
{
129
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
130
index XXXXXXX..XXXXXXX 100644
131
--- a/target/arm/translate-a64.c
132
+++ b/target/arm/translate-a64.c
133
@@ -XXX,XX +XXX,XX @@ static void gen_gvec_fn4(DisasContext *s, bool is_q, int rd, int rn, int rm,
134
is_q ? 16 : 8, vec_full_reg_size(s));
135
}
136
137
+/* Expand a 2-operand AdvSIMD vector operation using an op descriptor. */
138
+static void gen_gvec_op2(DisasContext *s, bool is_q, int rd,
139
+ int rn, const GVecGen2 *gvec_op)
140
+{
141
+ tcg_gen_gvec_2(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn),
142
+ is_q ? 16 : 8, vec_full_reg_size(s), gvec_op);
143
+}
144
+
145
/* Expand a 2-operand + immediate AdvSIMD vector operation using
146
* an op descriptor.
147
*/
148
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
149
return;
150
}
151
break;
152
+ case 0x8: /* CMGT, CMGE */
153
+ gen_gvec_op2(s, is_q, rd, rn, u ? &cge0_op[size] : &cgt0_op[size]);
154
+ return;
155
+ case 0x9: /* CMEQ, CMLE */
156
+ gen_gvec_op2(s, is_q, rd, rn, u ? &cle0_op[size] : &ceq0_op[size]);
157
+ return;
158
+ case 0xa: /* CMLT */
159
+ gen_gvec_op2(s, is_q, rd, rn, &clt0_op[size]);
160
+ return;
161
case 0xb:
162
if (u) { /* ABS, NEG */
163
gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size);
164
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
165
for (pass = 0; pass < (is_q ? 4 : 2); pass++) {
166
TCGv_i32 tcg_op = tcg_temp_new_i32();
167
TCGv_i32 tcg_res = tcg_temp_new_i32();
168
- TCGCond cond;
169
170
read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
171
172
if (size == 2) {
173
/* Special cases for 32 bit elements */
174
switch (opcode) {
175
- case 0xa: /* CMLT */
176
- /* 32 bit integer comparison against zero, result is
177
- * test ? (2^32 - 1) : 0. We implement via setcond(test)
178
- * and inverting.
179
- */
180
- cond = TCG_COND_LT;
181
- do_cmop:
182
- tcg_gen_setcondi_i32(cond, tcg_res, tcg_op, 0);
183
- tcg_gen_neg_i32(tcg_res, tcg_res);
184
- break;
185
- case 0x8: /* CMGT, CMGE */
186
- cond = u ? TCG_COND_GE : TCG_COND_GT;
187
- goto do_cmop;
188
- case 0x9: /* CMEQ, CMLE */
189
- cond = u ? TCG_COND_LE : TCG_COND_EQ;
190
- goto do_cmop;
191
case 0x4: /* CLS */
192
if (u) {
193
tcg_gen_clzi_i32(tcg_res, tcg_op, 32);
194
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
195
genfn(tcg_res, cpu_env, tcg_op);
196
break;
197
}
198
- case 0x8: /* CMGT, CMGE */
199
- case 0x9: /* CMEQ, CMLE */
200
- case 0xa: /* CMLT */
201
- {
202
- static NeonGenTwoOpFn * const fns[3][2] = {
203
- { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_s16 },
204
- { gen_helper_neon_cge_s8, gen_helper_neon_cge_s16 },
205
- { gen_helper_neon_ceq_u8, gen_helper_neon_ceq_u16 },
206
- };
207
- NeonGenTwoOpFn *genfn;
208
- int comp;
209
- bool reverse;
210
- TCGv_i32 tcg_zero = tcg_const_i32(0);
211
-
212
- /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
213
- comp = (opcode - 0x8) * 2 + u;
214
- /* ...but LE, LT are implemented as reverse GE, GT */
215
- reverse = (comp > 2);
216
- if (reverse) {
217
- comp = 4 - comp;
218
- }
219
- genfn = fns[comp][size];
220
- if (reverse) {
221
- genfn(tcg_res, tcg_zero, tcg_op);
222
- } else {
223
- genfn(tcg_res, tcg_op, tcg_zero);
224
- }
225
- tcg_temp_free_i32(tcg_zero);
226
- break;
227
- }
228
case 0x4: /* CLS, CLZ */
229
if (u) {
230
if (size == 0) {
231
diff --git a/target/arm/translate.c b/target/arm/translate.c
232
index XXXXXXX..XXXXXXX 100644
233
--- a/target/arm/translate.c
234
+++ b/target/arm/translate.c
235
@@ -XXX,XX +XXX,XX @@ static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn,
236
return 1;
237
}
238
239
+static void gen_ceq0_i32(TCGv_i32 d, TCGv_i32 a)
240
+{
241
+ tcg_gen_setcondi_i32(TCG_COND_EQ, d, a, 0);
242
+ tcg_gen_neg_i32(d, d);
243
+}
244
+
245
+static void gen_ceq0_i64(TCGv_i64 d, TCGv_i64 a)
246
+{
247
+ tcg_gen_setcondi_i64(TCG_COND_EQ, d, a, 0);
248
+ tcg_gen_neg_i64(d, d);
249
+}
250
+
251
+static void gen_ceq0_vec(unsigned vece, TCGv_vec d, TCGv_vec a)
252
+{
253
+ TCGv_vec zero = tcg_const_zeros_vec_matching(d);
254
+ tcg_gen_cmp_vec(TCG_COND_EQ, vece, d, a, zero);
255
+ tcg_temp_free_vec(zero);
256
+}
257
+
258
+static const TCGOpcode vecop_list_cmp[] = {
259
+ INDEX_op_cmp_vec, 0
260
+};
261
+
262
+const GVecGen2 ceq0_op[4] = {
263
+ { .fno = gen_helper_gvec_ceq0_b,
264
+ .fniv = gen_ceq0_vec,
265
+ .opt_opc = vecop_list_cmp,
266
+ .vece = MO_8 },
267
+ { .fno = gen_helper_gvec_ceq0_h,
268
+ .fniv = gen_ceq0_vec,
269
+ .opt_opc = vecop_list_cmp,
270
+ .vece = MO_16 },
271
+ { .fni4 = gen_ceq0_i32,
272
+ .fniv = gen_ceq0_vec,
273
+ .opt_opc = vecop_list_cmp,
274
+ .vece = MO_32 },
275
+ { .fni8 = gen_ceq0_i64,
276
+ .fniv = gen_ceq0_vec,
277
+ .opt_opc = vecop_list_cmp,
278
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
279
+ .vece = MO_64 },
280
+};
281
+
282
+static void gen_cle0_i32(TCGv_i32 d, TCGv_i32 a)
283
+{
284
+ tcg_gen_setcondi_i32(TCG_COND_LE, d, a, 0);
285
+ tcg_gen_neg_i32(d, d);
286
+}
287
+
288
+static void gen_cle0_i64(TCGv_i64 d, TCGv_i64 a)
289
+{
290
+ tcg_gen_setcondi_i64(TCG_COND_LE, d, a, 0);
291
+ tcg_gen_neg_i64(d, d);
292
+}
293
+
294
+static void gen_cle0_vec(unsigned vece, TCGv_vec d, TCGv_vec a)
295
+{
296
+ TCGv_vec zero = tcg_const_zeros_vec_matching(d);
297
+ tcg_gen_cmp_vec(TCG_COND_LE, vece, d, a, zero);
298
+ tcg_temp_free_vec(zero);
299
+}
300
+
301
+const GVecGen2 cle0_op[4] = {
302
+ { .fno = gen_helper_gvec_cle0_b,
303
+ .fniv = gen_cle0_vec,
304
+ .opt_opc = vecop_list_cmp,
305
+ .vece = MO_8 },
306
+ { .fno = gen_helper_gvec_cle0_h,
307
+ .fniv = gen_cle0_vec,
308
+ .opt_opc = vecop_list_cmp,
309
+ .vece = MO_16 },
310
+ { .fni4 = gen_cle0_i32,
311
+ .fniv = gen_cle0_vec,
312
+ .opt_opc = vecop_list_cmp,
313
+ .vece = MO_32 },
314
+ { .fni8 = gen_cle0_i64,
315
+ .fniv = gen_cle0_vec,
316
+ .opt_opc = vecop_list_cmp,
317
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
318
+ .vece = MO_64 },
319
+};
320
+
321
+static void gen_cge0_i32(TCGv_i32 d, TCGv_i32 a)
322
+{
323
+ tcg_gen_setcondi_i32(TCG_COND_GE, d, a, 0);
324
+ tcg_gen_neg_i32(d, d);
325
+}
326
+
327
+static void gen_cge0_i64(TCGv_i64 d, TCGv_i64 a)
328
+{
329
+ tcg_gen_setcondi_i64(TCG_COND_GE, d, a, 0);
330
+ tcg_gen_neg_i64(d, d);
331
+}
332
+
333
+static void gen_cge0_vec(unsigned vece, TCGv_vec d, TCGv_vec a)
334
+{
335
+ TCGv_vec zero = tcg_const_zeros_vec_matching(d);
336
+ tcg_gen_cmp_vec(TCG_COND_GE, vece, d, a, zero);
337
+ tcg_temp_free_vec(zero);
338
+}
339
+
340
+const GVecGen2 cge0_op[4] = {
341
+ { .fno = gen_helper_gvec_cge0_b,
342
+ .fniv = gen_cge0_vec,
343
+ .opt_opc = vecop_list_cmp,
344
+ .vece = MO_8 },
345
+ { .fno = gen_helper_gvec_cge0_h,
346
+ .fniv = gen_cge0_vec,
347
+ .opt_opc = vecop_list_cmp,
348
+ .vece = MO_16 },
349
+ { .fni4 = gen_cge0_i32,
350
+ .fniv = gen_cge0_vec,
351
+ .opt_opc = vecop_list_cmp,
352
+ .vece = MO_32 },
353
+ { .fni8 = gen_cge0_i64,
354
+ .fniv = gen_cge0_vec,
355
+ .opt_opc = vecop_list_cmp,
356
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
357
+ .vece = MO_64 },
358
+};
359
+
360
+static void gen_clt0_i32(TCGv_i32 d, TCGv_i32 a)
361
+{
362
+ tcg_gen_setcondi_i32(TCG_COND_LT, d, a, 0);
363
+ tcg_gen_neg_i32(d, d);
364
+}
365
+
366
+static void gen_clt0_i64(TCGv_i64 d, TCGv_i64 a)
367
+{
368
+ tcg_gen_setcondi_i64(TCG_COND_LT, d, a, 0);
369
+ tcg_gen_neg_i64(d, d);
370
+}
371
+
372
+static void gen_clt0_vec(unsigned vece, TCGv_vec d, TCGv_vec a)
373
+{
374
+ TCGv_vec zero = tcg_const_zeros_vec_matching(d);
375
+ tcg_gen_cmp_vec(TCG_COND_LT, vece, d, a, zero);
376
+ tcg_temp_free_vec(zero);
377
+}
378
+
379
+const GVecGen2 clt0_op[4] = {
380
+ { .fno = gen_helper_gvec_clt0_b,
381
+ .fniv = gen_clt0_vec,
382
+ .opt_opc = vecop_list_cmp,
383
+ .vece = MO_8 },
384
+ { .fno = gen_helper_gvec_clt0_h,
385
+ .fniv = gen_clt0_vec,
386
+ .opt_opc = vecop_list_cmp,
387
+ .vece = MO_16 },
388
+ { .fni4 = gen_clt0_i32,
389
+ .fniv = gen_clt0_vec,
390
+ .opt_opc = vecop_list_cmp,
391
+ .vece = MO_32 },
392
+ { .fni8 = gen_clt0_i64,
393
+ .fniv = gen_clt0_vec,
394
+ .opt_opc = vecop_list_cmp,
395
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
396
+ .vece = MO_64 },
397
+};
398
+
399
+static void gen_cgt0_i32(TCGv_i32 d, TCGv_i32 a)
400
+{
401
+ tcg_gen_setcondi_i32(TCG_COND_GT, d, a, 0);
402
+ tcg_gen_neg_i32(d, d);
403
+}
404
+
405
+static void gen_cgt0_i64(TCGv_i64 d, TCGv_i64 a)
406
+{
407
+ tcg_gen_setcondi_i64(TCG_COND_GT, d, a, 0);
408
+ tcg_gen_neg_i64(d, d);
409
+}
410
+
411
+static void gen_cgt0_vec(unsigned vece, TCGv_vec d, TCGv_vec a)
412
+{
413
+ TCGv_vec zero = tcg_const_zeros_vec_matching(d);
414
+ tcg_gen_cmp_vec(TCG_COND_GT, vece, d, a, zero);
415
+ tcg_temp_free_vec(zero);
416
+}
417
+
418
+const GVecGen2 cgt0_op[4] = {
419
+ { .fno = gen_helper_gvec_cgt0_b,
420
+ .fniv = gen_cgt0_vec,
421
+ .opt_opc = vecop_list_cmp,
422
+ .vece = MO_8 },
423
+ { .fno = gen_helper_gvec_cgt0_h,
424
+ .fniv = gen_cgt0_vec,
425
+ .opt_opc = vecop_list_cmp,
426
+ .vece = MO_16 },
427
+ { .fni4 = gen_cgt0_i32,
428
+ .fniv = gen_cgt0_vec,
429
+ .opt_opc = vecop_list_cmp,
430
+ .vece = MO_32 },
431
+ { .fni8 = gen_cgt0_i64,
432
+ .fniv = gen_cgt0_vec,
433
+ .opt_opc = vecop_list_cmp,
434
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
435
+ .vece = MO_64 },
436
+};
437
+
438
static void gen_ssra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
439
{
440
tcg_gen_vec_sar8i_i64(a, a, shift);
441
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
442
tcg_gen_gvec_abs(size, rd_ofs, rm_ofs, vec_size, vec_size);
443
break;
444
445
+ case NEON_2RM_VCEQ0:
446
+ tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size,
447
+ vec_size, &ceq0_op[size]);
448
+ break;
449
+ case NEON_2RM_VCGT0:
450
+ tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size,
451
+ vec_size, &cgt0_op[size]);
452
+ break;
453
+ case NEON_2RM_VCLE0:
454
+ tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size,
455
+ vec_size, &cle0_op[size]);
456
+ break;
457
+ case NEON_2RM_VCGE0:
458
+ tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size,
459
+ vec_size, &cge0_op[size]);
460
+ break;
461
+ case NEON_2RM_VCLT0:
462
+ tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size,
463
+ vec_size, &clt0_op[size]);
464
+ break;
465
+
466
default:
467
elementwise:
468
for (pass = 0; pass < (q ? 4 : 2); pass++) {
469
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
470
default: abort();
471
}
472
break;
473
- case NEON_2RM_VCGT0: case NEON_2RM_VCLE0:
474
- tmp2 = tcg_const_i32(0);
475
- switch(size) {
476
- case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break;
477
- case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break;
478
- case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break;
479
- default: abort();
480
- }
481
- tcg_temp_free_i32(tmp2);
482
- if (op == NEON_2RM_VCLE0) {
483
- tcg_gen_not_i32(tmp, tmp);
484
- }
485
- break;
486
- case NEON_2RM_VCGE0: case NEON_2RM_VCLT0:
487
- tmp2 = tcg_const_i32(0);
488
- switch(size) {
489
- case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break;
490
- case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break;
491
- case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break;
492
- default: abort();
493
- }
494
- tcg_temp_free_i32(tmp2);
495
- if (op == NEON_2RM_VCLT0) {
496
- tcg_gen_not_i32(tmp, tmp);
497
- }
498
- break;
499
- case NEON_2RM_VCEQ0:
500
- tmp2 = tcg_const_i32(0);
501
- switch(size) {
502
- case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
503
- case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
504
- case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
505
- default: abort();
506
- }
507
- tcg_temp_free_i32(tmp2);
508
- break;
509
case NEON_2RM_VCGT0_F:
510
{
511
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
512
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
513
index XXXXXXX..XXXXXXX 100644
514
--- a/target/arm/vec_helper.c
515
+++ b/target/arm/vec_helper.c
516
@@ -XXX,XX +XXX,XX @@ void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc)
517
}
518
}
519
#endif
520
+
521
+#define DO_CMP0(NAME, TYPE, OP) \
522
+void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
523
+{ \
524
+ intptr_t i, opr_sz = simd_oprsz(desc); \
525
+ for (i = 0; i < opr_sz; i += sizeof(TYPE)) { \
526
+ TYPE nn = *(TYPE *)(vn + i); \
527
+ *(TYPE *)(vd + i) = -(nn OP 0); \
528
+ } \
529
+ clear_tail(vd, opr_sz, simd_maxsz(desc)); \
530
+}
531
+
532
+DO_CMP0(gvec_ceq0_b, int8_t, ==)
533
+DO_CMP0(gvec_clt0_b, int8_t, <)
534
+DO_CMP0(gvec_cle0_b, int8_t, <=)
535
+DO_CMP0(gvec_cgt0_b, int8_t, >)
536
+DO_CMP0(gvec_cge0_b, int8_t, >=)
537
+
538
+DO_CMP0(gvec_ceq0_h, int16_t, ==)
539
+DO_CMP0(gvec_clt0_h, int16_t, <)
540
+DO_CMP0(gvec_cle0_h, int16_t, <=)
541
+DO_CMP0(gvec_cgt0_h, int16_t, >)
542
+DO_CMP0(gvec_cge0_h, int16_t, >=)
543
+
544
+#undef DO_CMP0
545
--
73
--
546
2.20.1
74
2.34.1
547
548
diff view generated by jsdifflib
[PULL 07/31] msf2: Add EMAC block to SmartFusion2 SoC
[PULL 67/72] softfloat: Inline pickNaN
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
With SmartFusion2 Ethernet MAC model in
3
Inline pickNaN into its only caller. This makes one assert
4
place this patch adds the same to SoC.
4
redundant with the immediately preceding IF.
5
5
6
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20241203203949.483774-9-richard.henderson@linaro.org
9
Message-id: 1587048891-30493-3-git-send-email-sundeep.lkml@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
include/hw/arm/msf2-soc.h | 2 ++
11
fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++----
13
hw/arm/msf2-soc.c | 26 ++++++++++++++++++++++++--
12
fpu/softfloat-specialize.c.inc | 96 ----------------------------------
14
2 files changed, 26 insertions(+), 2 deletions(-)
13
2 files changed, 73 insertions(+), 105 deletions(-)
15
14
16
diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
15
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/msf2-soc.h
17
--- a/fpu/softfloat-parts.c.inc
19
+++ b/include/hw/arm/msf2-soc.h
18
+++ b/fpu/softfloat-parts.c.inc
20
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
21
#include "hw/timer/mss-timer.h"
20
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
22
#include "hw/misc/msf2-sysreg.h"
21
float_status *s)
23
#include "hw/ssi/mss-spi.h"
22
{
24
+#include "hw/net/msf2-emac.h"
23
+ int cmp, which;
25
24
+
26
#define TYPE_MSF2_SOC "msf2-soc"
25
if (is_snan(a->cls) || is_snan(b->cls)) {
27
#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
28
@@ -XXX,XX +XXX,XX @@ typedef struct MSF2State {
27
}
29
MSF2SysregState sysreg;
28
30
MSSTimerState timer;
29
if (s->default_nan_mode) {
31
MSSSpiState spi[MSF2_NUM_SPIS];
30
parts_default_nan(a, s);
32
+ MSF2EmacState emac;
31
- } else {
33
} MSF2State;
32
- int cmp = frac_cmp(a, b);
34
33
- if (cmp == 0) {
35
#endif
34
- cmp = a->sign < b->sign;
36
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
35
- }
36
+ return a;
37
+ }
38
39
- if (pickNaN(a->cls, b->cls, cmp > 0, s)) {
40
- a = b;
41
- }
42
+ cmp = frac_cmp(a, b);
43
+ if (cmp == 0) {
44
+ cmp = a->sign < b->sign;
45
+ }
46
+
47
+ switch (s->float_2nan_prop_rule) {
48
+ case float_2nan_prop_s_ab:
49
if (is_snan(a->cls)) {
50
- parts_silence_nan(a, s);
51
+ which = 0;
52
+ } else if (is_snan(b->cls)) {
53
+ which = 1;
54
+ } else if (is_qnan(a->cls)) {
55
+ which = 0;
56
+ } else {
57
+ which = 1;
58
}
59
+ break;
60
+ case float_2nan_prop_s_ba:
61
+ if (is_snan(b->cls)) {
62
+ which = 1;
63
+ } else if (is_snan(a->cls)) {
64
+ which = 0;
65
+ } else if (is_qnan(b->cls)) {
66
+ which = 1;
67
+ } else {
68
+ which = 0;
69
+ }
70
+ break;
71
+ case float_2nan_prop_ab:
72
+ which = is_nan(a->cls) ? 0 : 1;
73
+ break;
74
+ case float_2nan_prop_ba:
75
+ which = is_nan(b->cls) ? 1 : 0;
76
+ break;
77
+ case float_2nan_prop_x87:
78
+ /*
79
+ * This implements x87 NaN propagation rules:
80
+ * SNaN + QNaN => return the QNaN
81
+ * two SNaNs => return the one with the larger significand, silenced
82
+ * two QNaNs => return the one with the larger significand
83
+ * SNaN and a non-NaN => return the SNaN, silenced
84
+ * QNaN and a non-NaN => return the QNaN
85
+ *
86
+ * If we get down to comparing significands and they are the same,
87
+ * return the NaN with the positive sign bit (if any).
88
+ */
89
+ if (is_snan(a->cls)) {
90
+ if (is_snan(b->cls)) {
91
+ which = cmp > 0 ? 0 : 1;
92
+ } else {
93
+ which = is_qnan(b->cls) ? 1 : 0;
94
+ }
95
+ } else if (is_qnan(a->cls)) {
96
+ if (is_snan(b->cls) || !is_qnan(b->cls)) {
97
+ which = 0;
98
+ } else {
99
+ which = cmp > 0 ? 0 : 1;
100
+ }
101
+ } else {
102
+ which = 1;
103
+ }
104
+ break;
105
+ default:
106
+ g_assert_not_reached();
107
+ }
108
+
109
+ if (which) {
110
+ a = b;
111
+ }
112
+ if (is_snan(a->cls)) {
113
+ parts_silence_nan(a, s);
114
}
115
return a;
116
}
117
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
37
index XXXXXXX..XXXXXXX 100644
118
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/arm/msf2-soc.c
119
--- a/fpu/softfloat-specialize.c.inc
39
+++ b/hw/arm/msf2-soc.c
120
+++ b/fpu/softfloat-specialize.c.inc
40
@@ -XXX,XX +XXX,XX @@
121
@@ -XXX,XX +XXX,XX @@ bool float32_is_signaling_nan(float32 a_, float_status *status)
41
/*
42
* SmartFusion2 SoC emulation.
43
*
44
- * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
45
+ * Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>
46
*
47
* Permission is hereby granted, free of charge, to any person obtaining a copy
48
* of this software and associated documentation files (the "Software"), to deal
49
@@ -XXX,XX +XXX,XX @@
50
51
#define MSF2_TIMER_BASE 0x40004000
52
#define MSF2_SYSREG_BASE 0x40038000
53
+#define MSF2_EMAC_BASE 0x40041000
54
55
#define ENVM_BASE_ADDRESS 0x60000000
56
57
#define SRAM_BASE_ADDRESS 0x20000000
58
59
+#define MSF2_EMAC_IRQ 12
60
+
61
#define MSF2_ENVM_MAX_SIZE (512 * KiB)
62
63
/*
64
@@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_initfn(Object *obj)
65
sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
66
TYPE_MSS_SPI);
67
}
122
}
68
+
69
+ sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
70
+ TYPE_MSS_EMAC);
71
+ if (nd_table[0].used) {
72
+ qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC);
73
+ qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
74
+ }
75
}
123
}
76
124
77
static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
125
-/*----------------------------------------------------------------------------
78
@@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
126
-| Select which NaN to propagate for a two-input operation.
79
g_free(bus_name);
127
-| IEEE754 doesn't specify all the details of this, so the
80
}
128
-| algorithm is target-specific.
81
129
-| The routine is passed various bits of information about the
82
+ dev = DEVICE(&s->emac);
130
-| two NaNs and should return 0 to select NaN a and 1 for NaN b.
83
+ object_property_set_link(OBJECT(&s->emac), OBJECT(get_system_memory()),
131
-| Note that signalling NaNs are always squashed to quiet NaNs
84
+ "ahb-bus", &error_abort);
132
-| by the caller, by calling floatXX_silence_nan() before
85
+ object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
133
-| returning them.
86
+ if (err != NULL) {
134
-|
87
+ error_propagate(errp, err);
135
-| aIsLargerSignificand is only valid if both a and b are NaNs
88
+ return;
136
-| of some kind, and is true if a has the larger significand,
89
+ }
137
-| or if both a and b have the same significand but a is
90
+ busdev = SYS_BUS_DEVICE(dev);
138
-| positive but b is negative. It is only needed for the x87
91
+ sysbus_mmio_map(busdev, 0, MSF2_EMAC_BASE);
139
-| tie-break rule.
92
+ sysbus_connect_irq(busdev, 0,
140
-*----------------------------------------------------------------------------*/
93
+ qdev_get_gpio_in(armv7m, MSF2_EMAC_IRQ));
141
-
94
+
142
-static int pickNaN(FloatClass a_cls, FloatClass b_cls,
95
/* Below devices are not modelled yet. */
143
- bool aIsLargerSignificand, float_status *status)
96
create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
144
-{
97
create_unimplemented_device("dma", 0x40003000, 0x1000);
145
- /*
98
@@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
146
- * We guarantee not to require the target to tell us how to
99
create_unimplemented_device("can", 0x40015000, 0x1000);
147
- * pick a NaN if we're always returning the default NaN.
100
create_unimplemented_device("rtc", 0x40017000, 0x1000);
148
- * But if we're not in default-NaN mode then the target must
101
create_unimplemented_device("apb_config", 0x40020000, 0x10000);
149
- * specify via set_float_2nan_prop_rule().
102
- create_unimplemented_device("emac", 0x40041000, 0x1000);
150
- */
103
create_unimplemented_device("usb", 0x40043000, 0x1000);
151
- assert(!status->default_nan_mode);
104
}
152
-
105
153
- switch (status->float_2nan_prop_rule) {
154
- case float_2nan_prop_s_ab:
155
- if (is_snan(a_cls)) {
156
- return 0;
157
- } else if (is_snan(b_cls)) {
158
- return 1;
159
- } else if (is_qnan(a_cls)) {
160
- return 0;
161
- } else {
162
- return 1;
163
- }
164
- break;
165
- case float_2nan_prop_s_ba:
166
- if (is_snan(b_cls)) {
167
- return 1;
168
- } else if (is_snan(a_cls)) {
169
- return 0;
170
- } else if (is_qnan(b_cls)) {
171
- return 1;
172
- } else {
173
- return 0;
174
- }
175
- break;
176
- case float_2nan_prop_ab:
177
- if (is_nan(a_cls)) {
178
- return 0;
179
- } else {
180
- return 1;
181
- }
182
- break;
183
- case float_2nan_prop_ba:
184
- if (is_nan(b_cls)) {
185
- return 1;
186
- } else {
187
- return 0;
188
- }
189
- break;
190
- case float_2nan_prop_x87:
191
- /*
192
- * This implements x87 NaN propagation rules:
193
- * SNaN + QNaN => return the QNaN
194
- * two SNaNs => return the one with the larger significand, silenced
195
- * two QNaNs => return the one with the larger significand
196
- * SNaN and a non-NaN => return the SNaN, silenced
197
- * QNaN and a non-NaN => return the QNaN
198
- *
199
- * If we get down to comparing significands and they are the same,
200
- * return the NaN with the positive sign bit (if any).
201
- */
202
- if (is_snan(a_cls)) {
203
- if (is_snan(b_cls)) {
204
- return aIsLargerSignificand ? 0 : 1;
205
- }
206
- return is_qnan(b_cls) ? 1 : 0;
207
- } else if (is_qnan(a_cls)) {
208
- if (is_snan(b_cls) || !is_qnan(b_cls)) {
209
- return 0;
210
- } else {
211
- return aIsLargerSignificand ? 0 : 1;
212
- }
213
- } else {
214
- return 1;
215
- }
216
- default:
217
- g_assert_not_reached();
218
- }
219
-}
220
-
221
/*----------------------------------------------------------------------------
222
| Returns 1 if the double-precision floating-point value `a' is a quiet
223
| NaN; otherwise returns 0.
106
--
224
--
107
2.20.1
225
2.34.1
108
226
109
227
diff view generated by jsdifflib
[PULL 08/31] tests/boot_linux_console: Add ethernet test to SmartFusion2
[PULL 68/72] softfloat: Share code between parts_pick_nan cases
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
In addition to simple serial test this patch uses ping
3
Remember if there was an SNaN, and use that to simplify
4
to test the ethernet block modelled in SmartFusion2 SoC.
4
float_2nan_prop_s_{ab,ba} to only the snan component.
5
Then, fall through to the corresponding
6
float_2nan_prop_{ab,ba} case to handle any remaining
7
nans, which must be quiet.
5
8
6
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20241203203949.483774-10-richard.henderson@linaro.org
9
Message-id: 1587048891-30493-4-git-send-email-sundeep.lkml@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
tests/acceptance/boot_linux_console.py | 15 ++++++++++-----
14
fpu/softfloat-parts.c.inc | 32 ++++++++++++--------------------
13
1 file changed, 10 insertions(+), 5 deletions(-)
15
1 file changed, 12 insertions(+), 20 deletions(-)
14
16
15
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/tests/acceptance/boot_linux_console.py
19
--- a/fpu/softfloat-parts.c.inc
18
+++ b/tests/acceptance/boot_linux_console.py
20
+++ b/fpu/softfloat-parts.c.inc
19
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
21
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
20
"""
22
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
21
uboot_url = ('https://raw.githubusercontent.com/'
23
float_status *s)
22
'Subbaraya-Sundeep/qemu-test-binaries/'
24
{
23
- 'fa030bd77a014a0b8e360d3b7011df89283a2f0b/u-boot')
25
+ bool have_snan = false;
24
- uboot_hash = 'abba5d9c24cdd2d49cdc2a8aa92976cf20737eff'
26
int cmp, which;
25
+ 'fe371d32e50ca682391e1e70ab98c2942aeffb01/u-boot')
27
26
+ uboot_hash = 'cbb8cbab970f594bf6523b9855be209c08374ae2'
28
if (is_snan(a->cls) || is_snan(b->cls)) {
27
uboot_path = self.fetch_asset(uboot_url, asset_hash=uboot_hash)
29
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
28
spi_url = ('https://raw.githubusercontent.com/'
30
+ have_snan = true;
29
'Subbaraya-Sundeep/qemu-test-binaries/'
31
}
30
- 'fa030bd77a014a0b8e360d3b7011df89283a2f0b/spi.bin')
32
31
- spi_hash = '85f698329d38de63aea6e884a86fbde70890a78a'
33
if (s->default_nan_mode) {
32
+ 'fe371d32e50ca682391e1e70ab98c2942aeffb01/spi.bin')
34
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
33
+ spi_hash = '65523a1835949b6f4553be96dec1b6a38fb05501'
35
34
spi_path = self.fetch_asset(spi_url, asset_hash=spi_hash)
36
switch (s->float_2nan_prop_rule) {
35
37
case float_2nan_prop_s_ab:
36
self.vm.set_console()
38
- if (is_snan(a->cls)) {
37
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
39
- which = 0;
38
'-drive', 'file=' + spi_path + ',if=mtd,format=raw',
40
- } else if (is_snan(b->cls)) {
39
'-no-reboot')
41
- which = 1;
40
self.vm.launch()
42
- } else if (is_qnan(a->cls)) {
41
- self.wait_for_console_pattern('init started: BusyBox')
43
- which = 0;
42
+ self.wait_for_console_pattern('Enter \'help\' for a list')
44
- } else {
43
+
45
- which = 1;
44
+ exec_command_and_wait_for_pattern(self, 'ifconfig eth0 10.0.2.15',
46
+ if (have_snan) {
45
+ 'eth0: link becomes ready')
47
+ which = is_snan(a->cls) ? 0 : 1;
46
+ exec_command_and_wait_for_pattern(self, 'ping -c 3 10.0.2.2',
48
+ break;
47
+ '3 packets transmitted, 3 packets received, 0% packet loss')
49
}
48
50
- break;
49
def do_test_arm_raspi2(self, uart_id):
51
- case float_2nan_prop_s_ba:
50
"""
52
- if (is_snan(b->cls)) {
53
- which = 1;
54
- } else if (is_snan(a->cls)) {
55
- which = 0;
56
- } else if (is_qnan(b->cls)) {
57
- which = 1;
58
- } else {
59
- which = 0;
60
- }
61
- break;
62
+ /* fall through */
63
case float_2nan_prop_ab:
64
which = is_nan(a->cls) ? 0 : 1;
65
break;
66
+ case float_2nan_prop_s_ba:
67
+ if (have_snan) {
68
+ which = is_snan(b->cls) ? 1 : 0;
69
+ break;
70
+ }
71
+ /* fall through */
72
case float_2nan_prop_ba:
73
which = is_nan(b->cls) ? 1 : 0;
74
break;
51
--
75
--
52
2.20.1
76
2.34.1
53
54
diff view generated by jsdifflib
[PULL 15/31] hw/char/cadence_uart: add clock support
[PULL 69/72] softfloat: Sink frac_cmp in parts_pick_nan until needed
1
From: Damien Hedde <damien.hedde@greensocs.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Switch the cadence uart to multi-phase reset and add the
3
Move the fractional comparison to the end of the
4
reference clock input.
4
float_2nan_prop_x87 case. This is not required for
5
any other 2nan propagation rule. Reorganize the
6
x87 case itself to break out of the switch when the
7
fractional comparison is not required.
5
8
6
The input clock frequency is added to the migration structure.
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
The reference clock controls the baudrate generation. If it disabled,
11
Message-id: 20241203203949.483774-11-richard.henderson@linaro.org
9
any input characters and events are ignored.
10
11
If this clock remains unconnected, the uart behaves as before
12
(it default to a 50MHz ref clock).
13
14
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
15
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
16
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Message-id: 20200406135251.157596-8-damien.hedde@greensocs.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
13
---
20
include/hw/char/cadence_uart.h | 1 +
14
fpu/softfloat-parts.c.inc | 19 +++++++++----------
21
hw/char/cadence_uart.c | 73 +++++++++++++++++++++++++++++-----
15
1 file changed, 9 insertions(+), 10 deletions(-)
22
hw/char/trace-events | 3 ++
23
3 files changed, 67 insertions(+), 10 deletions(-)
24
16
25
diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
26
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
27
--- a/include/hw/char/cadence_uart.h
19
--- a/fpu/softfloat-parts.c.inc
28
+++ b/include/hw/char/cadence_uart.h
20
+++ b/fpu/softfloat-parts.c.inc
29
@@ -XXX,XX +XXX,XX @@ typedef struct {
21
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
30
CharBackend chr;
22
return a;
31
qemu_irq irq;
32
QEMUTimer *fifo_trigger_handle;
33
+ Clock *refclk;
34
} CadenceUARTState;
35
36
static inline DeviceState *cadence_uart_create(hwaddr addr,
37
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/char/cadence_uart.c
40
+++ b/hw/char/cadence_uart.c
41
@@ -XXX,XX +XXX,XX @@
42
#include "qemu/module.h"
43
#include "hw/char/cadence_uart.h"
44
#include "hw/irq.h"
45
+#include "hw/qdev-clock.h"
46
+#include "trace.h"
47
48
#ifdef CADENCE_UART_ERR_DEBUG
49
#define DB_PRINT(...) do { \
50
@@ -XXX,XX +XXX,XX @@
51
#define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
52
#define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
53
54
-#define UART_INPUT_CLK 50000000
55
+#define UART_DEFAULT_REF_CLK (50 * 1000 * 1000)
56
57
#define R_CR (0x00/4)
58
#define R_MR (0x04/4)
59
@@ -XXX,XX +XXX,XX @@ static void uart_send_breaks(CadenceUARTState *s)
60
static void uart_parameters_setup(CadenceUARTState *s)
61
{
62
QEMUSerialSetParams ssp;
63
- unsigned int baud_rate, packet_size;
64
+ unsigned int baud_rate, packet_size, input_clk;
65
+ input_clk = clock_get_hz(s->refclk);
66
67
- baud_rate = (s->r[R_MR] & UART_MR_CLKS) ?
68
- UART_INPUT_CLK / 8 : UART_INPUT_CLK;
69
+ baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? input_clk / 8 : input_clk;
70
+ baud_rate /= (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
71
+ trace_cadence_uart_baudrate(baud_rate);
72
+
73
+ ssp.speed = baud_rate;
74
75
- ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
76
packet_size = 1;
77
78
switch (s->r[R_MR] & UART_MR_PAR) {
79
@@ -XXX,XX +XXX,XX @@ static void uart_parameters_setup(CadenceUARTState *s)
80
}
23
}
81
24
82
packet_size += ssp.data_bits + ssp.stop_bits;
25
- cmp = frac_cmp(a, b);
83
+ if (ssp.speed == 0) {
26
- if (cmp == 0) {
84
+ /*
27
- cmp = a->sign < b->sign;
85
+ * Avoid division-by-zero below.
86
+ * TODO: find something better
87
+ */
88
+ ssp.speed = 1;
89
+ }
90
s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size;
91
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
92
}
93
@@ -XXX,XX +XXX,XX @@ static void uart_receive(void *opaque, const uint8_t *buf, int size)
94
CadenceUARTState *s = opaque;
95
uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
96
97
+ /* ignore characters when unclocked or in reset */
98
+ if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
99
+ return;
100
+ }
101
+
102
if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
103
uart_write_rx_fifo(opaque, buf, size);
104
}
105
@@ -XXX,XX +XXX,XX @@ static void uart_event(void *opaque, QEMUChrEvent event)
106
CadenceUARTState *s = opaque;
107
uint8_t buf = '\0';
108
109
+ /* ignore characters when unclocked or in reset */
110
+ if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
111
+ return;
112
+ }
113
+
114
if (event == CHR_EVENT_BREAK) {
115
uart_write_rx_fifo(opaque, &buf, 1);
116
}
117
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps uart_ops = {
118
.endianness = DEVICE_NATIVE_ENDIAN,
119
};
120
121
-static void cadence_uart_reset(DeviceState *dev)
122
+static void cadence_uart_reset_init(Object *obj, ResetType type)
123
{
124
- CadenceUARTState *s = CADENCE_UART(dev);
125
+ CadenceUARTState *s = CADENCE_UART(obj);
126
127
s->r[R_CR] = 0x00000128;
128
s->r[R_IMR] = 0;
129
@@ -XXX,XX +XXX,XX @@ static void cadence_uart_reset(DeviceState *dev)
130
s->r[R_BRGR] = 0x0000028B;
131
s->r[R_BDIV] = 0x0000000F;
132
s->r[R_TTRIG] = 0x00000020;
133
+}
134
+
135
+static void cadence_uart_reset_hold(Object *obj)
136
+{
137
+ CadenceUARTState *s = CADENCE_UART(obj);
138
139
uart_rx_reset(s);
140
uart_tx_reset(s);
141
@@ -XXX,XX +XXX,XX @@ static void cadence_uart_realize(DeviceState *dev, Error **errp)
142
uart_event, NULL, s, NULL, true);
143
}
144
145
+static void cadence_uart_refclk_update(void *opaque)
146
+{
147
+ CadenceUARTState *s = opaque;
148
+
149
+ /* recompute uart's speed on clock change */
150
+ uart_parameters_setup(s);
151
+}
152
+
153
static void cadence_uart_init(Object *obj)
154
{
155
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
156
@@ -XXX,XX +XXX,XX @@ static void cadence_uart_init(Object *obj)
157
sysbus_init_mmio(sbd, &s->iomem);
158
sysbus_init_irq(sbd, &s->irq);
159
160
+ s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk",
161
+ cadence_uart_refclk_update, s);
162
+ /* initialize the frequency in case the clock remains unconnected */
163
+ clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK);
164
+
165
s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
166
}
167
168
+static int cadence_uart_pre_load(void *opaque)
169
+{
170
+ CadenceUARTState *s = opaque;
171
+
172
+ /* the frequency will be overriden if the refclk field is present */
173
+ clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK);
174
+ return 0;
175
+}
176
+
177
static int cadence_uart_post_load(void *opaque, int version_id)
178
{
179
CadenceUARTState *s = opaque;
180
@@ -XXX,XX +XXX,XX @@ static int cadence_uart_post_load(void *opaque, int version_id)
181
182
static const VMStateDescription vmstate_cadence_uart = {
183
.name = "cadence_uart",
184
- .version_id = 2,
185
+ .version_id = 3,
186
.minimum_version_id = 2,
187
+ .pre_load = cadence_uart_pre_load,
188
.post_load = cadence_uart_post_load,
189
.fields = (VMStateField[]) {
190
VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX),
191
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_cadence_uart = {
192
VMSTATE_UINT32(tx_count, CadenceUARTState),
193
VMSTATE_UINT32(rx_wpos, CadenceUARTState),
194
VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
195
+ VMSTATE_CLOCK_V(refclk, CadenceUARTState, 3),
196
VMSTATE_END_OF_LIST()
197
- }
28
- }
198
+ },
29
-
199
};
30
switch (s->float_2nan_prop_rule) {
200
31
case float_2nan_prop_s_ab:
201
static Property cadence_uart_properties[] = {
32
if (have_snan) {
202
@@ -XXX,XX +XXX,XX @@ static Property cadence_uart_properties[] = {
33
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
203
static void cadence_uart_class_init(ObjectClass *klass, void *data)
34
* return the NaN with the positive sign bit (if any).
204
{
35
*/
205
DeviceClass *dc = DEVICE_CLASS(klass);
36
if (is_snan(a->cls)) {
206
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
37
- if (is_snan(b->cls)) {
207
38
- which = cmp > 0 ? 0 : 1;
208
dc->realize = cadence_uart_realize;
39
- } else {
209
dc->vmsd = &vmstate_cadence_uart;
40
+ if (!is_snan(b->cls)) {
210
- dc->reset = cadence_uart_reset;
41
which = is_qnan(b->cls) ? 1 : 0;
211
+ rc->phases.enter = cadence_uart_reset_init;
42
+ break;
212
+ rc->phases.hold = cadence_uart_reset_hold;
43
}
213
device_class_set_props(dc, cadence_uart_properties);
44
} else if (is_qnan(a->cls)) {
214
}
45
if (is_snan(b->cls) || !is_qnan(b->cls)) {
215
46
which = 0;
216
diff --git a/hw/char/trace-events b/hw/char/trace-events
47
- } else {
217
index XXXXXXX..XXXXXXX 100644
48
- which = cmp > 0 ? 0 : 1;
218
--- a/hw/char/trace-events
49
+ break;
219
+++ b/hw/char/trace-events
50
}
220
@@ -XXX,XX +XXX,XX @@ exynos_uart_wo_read(uint32_t channel, const char *name, uint32_t reg) "UART%d: T
51
} else {
221
exynos_uart_rxsize(uint32_t channel, uint32_t size) "UART%d: Rx FIFO size: %d"
52
which = 1;
222
exynos_uart_channel_error(uint32_t channel) "Wrong UART channel number: %d"
53
+ break;
223
exynos_uart_rx_timeout(uint32_t channel, uint32_t stat, uint32_t intsp) "UART%d: Rx timeout stat=0x%x intsp=0x%x"
54
}
224
+
55
+ cmp = frac_cmp(a, b);
225
+# hw/char/cadence_uart.c
56
+ if (cmp == 0) {
226
+cadence_uart_baudrate(unsigned baudrate) "baudrate %u"
57
+ cmp = a->sign < b->sign;
58
+ }
59
+ which = cmp > 0 ? 0 : 1;
60
break;
61
default:
62
g_assert_not_reached();
227
--
63
--
228
2.20.1
64
2.34.1
229
230
diff view generated by jsdifflib
[PULL 28/31] device_tree: Allow name wildcards in qemu_fdt_node_path()
[PULL 70/72] softfloat: Replace WHICH with RET in parts_pick_nan
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Allow name wildcards in qemu_fdt_node_path(). This is useful
3
Replace the "index" selecting between A and B with a result variable
4
to find all nodes with a given compatibility string.
4
of the proper type. This improves clarity within the function.
5
5
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20200423121114.4274-2-edgar.iglesias@gmail.com
8
Message-id: 20241203203949.483774-12-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
include/sysemu/device_tree.h | 3 +++
11
fpu/softfloat-parts.c.inc | 28 +++++++++++++---------------
12
device_tree.c | 2 +-
12
1 file changed, 13 insertions(+), 15 deletions(-)
13
2 files changed, 4 insertions(+), 1 deletion(-)
14
13
15
diff --git a/include/sysemu/device_tree.h b/include/sysemu/device_tree.h
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/include/sysemu/device_tree.h
16
--- a/fpu/softfloat-parts.c.inc
18
+++ b/include/sysemu/device_tree.h
17
+++ b/fpu/softfloat-parts.c.inc
19
@@ -XXX,XX +XXX,XX @@ void *load_device_tree_from_sysfs(void);
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
20
* NULL. If there is no error but no matching node was found, the
19
float_status *s)
21
* returned array contains a single element equal to NULL. If an error
20
{
22
* was encountered when parsing the blob, the function returns NULL
21
bool have_snan = false;
23
+ *
22
- int cmp, which;
24
+ * @name may be NULL to wildcard names and only match compatibility
23
+ FloatPartsN *ret;
25
+ * strings.
24
+ int cmp;
26
*/
25
27
char **qemu_fdt_node_path(void *fdt, const char *name, char *compat,
26
if (is_snan(a->cls) || is_snan(b->cls)) {
28
Error **errp);
27
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
29
diff --git a/device_tree.c b/device_tree.c
28
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
30
index XXXXXXX..XXXXXXX 100644
29
switch (s->float_2nan_prop_rule) {
31
--- a/device_tree.c
30
case float_2nan_prop_s_ab:
32
+++ b/device_tree.c
31
if (have_snan) {
33
@@ -XXX,XX +XXX,XX @@ char **qemu_fdt_node_path(void *fdt, const char *name, char *compat,
32
- which = is_snan(a->cls) ? 0 : 1;
34
offset = len;
33
+ ret = is_snan(a->cls) ? a : b;
35
break;
34
break;
36
}
35
}
37
- if (!strcmp(iter_name, name)) {
36
/* fall through */
38
+ if (!name || !strcmp(iter_name, name)) {
37
case float_2nan_prop_ab:
39
char *path;
38
- which = is_nan(a->cls) ? 0 : 1;
40
39
+ ret = is_nan(a->cls) ? a : b;
41
path = g_malloc(path_len);
40
break;
41
case float_2nan_prop_s_ba:
42
if (have_snan) {
43
- which = is_snan(b->cls) ? 1 : 0;
44
+ ret = is_snan(b->cls) ? b : a;
45
break;
46
}
47
/* fall through */
48
case float_2nan_prop_ba:
49
- which = is_nan(b->cls) ? 1 : 0;
50
+ ret = is_nan(b->cls) ? b : a;
51
break;
52
case float_2nan_prop_x87:
53
/*
54
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
55
*/
56
if (is_snan(a->cls)) {
57
if (!is_snan(b->cls)) {
58
- which = is_qnan(b->cls) ? 1 : 0;
59
+ ret = is_qnan(b->cls) ? b : a;
60
break;
61
}
62
} else if (is_qnan(a->cls)) {
63
if (is_snan(b->cls) || !is_qnan(b->cls)) {
64
- which = 0;
65
+ ret = a;
66
break;
67
}
68
} else {
69
- which = 1;
70
+ ret = b;
71
break;
72
}
73
cmp = frac_cmp(a, b);
74
if (cmp == 0) {
75
cmp = a->sign < b->sign;
76
}
77
- which = cmp > 0 ? 0 : 1;
78
+ ret = cmp > 0 ? a : b;
79
break;
80
default:
81
g_assert_not_reached();
82
}
83
84
- if (which) {
85
- a = b;
86
+ if (is_snan(ret->cls)) {
87
+ parts_silence_nan(ret, s);
88
}
89
- if (is_snan(a->cls)) {
90
- parts_silence_nan(a, s);
91
- }
92
- return a;
93
+ return ret;
94
}
95
96
static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
42
--
97
--
43
2.20.1
98
2.34.1
44
99
45
100
diff view generated by jsdifflib
[PULL 04/31] bugfix: Use gicr_typer in arm_gicv3_icc_reset
[PULL 71/72] MAINTAINERS: update email address for Leif Lindholm
1
From: Keqian Zhu <zhukeqian1@huawei.com>
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
2
2
3
The KVM_VGIC_ATTR macro expect the second parameter as gicr_typer,
3
I'm migrating to Qualcomm's new open source email infrastructure, so
4
of which high 32bit is constructed by mp_affinity. For most case,
4
update my email address, and update the mailmap to match.
5
the high 32bit of mp_affinity is zero, so it will always access the
6
ICC_CTLR_EL1 of CPU0.
7
5
8
Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
6
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
9
Message-id: 20200413091552.62748-2-zhukeqian1@huawei.com
7
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
---
13
hw/intc/arm_gicv3_kvm.c | 4 +---
14
MAINTAINERS | 2 +-
14
1 file changed, 1 insertion(+), 3 deletions(-)
15
.mailmap | 5 +++--
16
2 files changed, 4 insertions(+), 3 deletions(-)
15
17
16
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
18
diff --git a/MAINTAINERS b/MAINTAINERS
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/arm_gicv3_kvm.c
20
--- a/MAINTAINERS
19
+++ b/hw/intc/arm_gicv3_kvm.c
21
+++ b/MAINTAINERS
20
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_get(GICv3State *s)
22
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
21
23
SBSA-REF
22
static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
24
M: Radoslaw Biernacki <rad@semihalf.com>
23
{
25
M: Peter Maydell <peter.maydell@linaro.org>
24
- ARMCPU *cpu;
26
-R: Leif Lindholm <quic_llindhol@quicinc.com>
25
GICv3State *s;
27
+R: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
26
GICv3CPUState *c;
28
R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
27
29
L: qemu-arm@nongnu.org
28
c = (GICv3CPUState *)env->gicv3state;
30
S: Maintained
29
s = c->gic;
31
diff --git a/.mailmap b/.mailmap
30
- cpu = ARM_CPU(c->cpu);
32
index XXXXXXX..XXXXXXX 100644
31
33
--- a/.mailmap
32
c->icc_pmr_el1 = 0;
34
+++ b/.mailmap
33
c->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
35
@@ -XXX,XX +XXX,XX @@ Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
34
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
36
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
35
37
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
36
/* Initialize to actual HW supported configuration */
38
Juan Quintela <quintela@trasno.org> <quintela@redhat.com>
37
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
39
-Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
38
- KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity),
40
-Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
39
+ KVM_VGIC_ATTR(ICC_CTLR_EL1, c->gicr_typer),
41
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <quic_llindhol@quicinc.com>
40
&c->icc_ctlr_el1[GICV3_NS], false, &error_abort);
42
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif.lindholm@linaro.org>
41
43
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif@nuviainc.com>
42
c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
44
Luc Michel <luc@lmichel.fr> <luc.michel@git.antfield.fr>
45
Luc Michel <luc@lmichel.fr> <luc.michel@greensocs.com>
46
Luc Michel <luc@lmichel.fr> <lmichel@kalray.eu>
43
--
47
--
44
2.20.1
48
2.34.1
45
49
46
50
diff view generated by jsdifflib
[PULL 06/31] hw/net: Add Smartfusion2 emac block
[PULL 72/72] MAINTAINERS: Add correct email address for Vikram Garhwal
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Vikram Garhwal <vikram.garhwal@bytedance.com>
2
2
3
Modelled Ethernet MAC of Smartfusion2 SoC.
3
Previously, maintainer role was paused due to inactive email id. Commit id:
4
Micrel KSZ8051 PHY is present on Emcraft's
4
c009d715721861984c4987bcc78b7ee183e86d75.
5
SOM kit hence same PHY is emulated.
6
5
7
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
6
Signed-off-by: Vikram Garhwal <vikram.garhwal@bytedance.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
9
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com
10
Message-id: 1587048891-30493-2-git-send-email-sundeep.lkml@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
hw/net/Makefile.objs | 1 +
11
MAINTAINERS | 2 ++
14
include/hw/net/msf2-emac.h | 53 ++++
12
1 file changed, 2 insertions(+)
15
hw/net/msf2-emac.c | 589 +++++++++++++++++++++++++++++++++++++
16
MAINTAINERS | 2 +
17
4 files changed, 645 insertions(+)
18
create mode 100644 include/hw/net/msf2-emac.h
19
create mode 100644 hw/net/msf2-emac.c
20
13
21
diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/net/Makefile.objs
24
+++ b/hw/net/Makefile.objs
25
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_ROCKER) += rocker/rocker.o rocker/rocker_fp.o \
26
obj-$(call lnot,$(CONFIG_ROCKER)) += rocker/qmp-norocker.o
27
28
common-obj-$(CONFIG_CAN_BUS) += can/
29
+common-obj-$(CONFIG_MSF2) += msf2-emac.o
30
diff --git a/include/hw/net/msf2-emac.h b/include/hw/net/msf2-emac.h
31
new file mode 100644
32
index XXXXXXX..XXXXXXX
33
--- /dev/null
34
+++ b/include/hw/net/msf2-emac.h
35
@@ -XXX,XX +XXX,XX @@
36
+/*
37
+ * QEMU model of the Smartfusion2 Ethernet MAC.
38
+ *
39
+ * Copyright (c) 2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
40
+ *
41
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
42
+ * of this software and associated documentation files (the "Software"), to deal
43
+ * in the Software without restriction, including without limitation the rights
44
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
45
+ * copies of the Software, and to permit persons to whom the Software is
46
+ * furnished to do so, subject to the following conditions:
47
+ *
48
+ * The above copyright notice and this permission notice shall be included in
49
+ * all copies or substantial portions of the Software.
50
+ *
51
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
52
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
53
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
54
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
55
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
56
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
57
+ * THE SOFTWARE.
58
+ */
59
+
60
+#include "hw/sysbus.h"
61
+#include "exec/memory.h"
62
+#include "net/net.h"
63
+#include "net/eth.h"
64
+
65
+#define TYPE_MSS_EMAC "msf2-emac"
66
+#define MSS_EMAC(obj) \
67
+ OBJECT_CHECK(MSF2EmacState, (obj), TYPE_MSS_EMAC)
68
+
69
+#define R_MAX (0x1a0 / 4)
70
+#define PHY_MAX_REGS 32
71
+
72
+typedef struct MSF2EmacState {
73
+ SysBusDevice parent;
74
+
75
+ MemoryRegion mmio;
76
+ MemoryRegion *dma_mr;
77
+ AddressSpace dma_as;
78
+
79
+ qemu_irq irq;
80
+ NICState *nic;
81
+ NICConf conf;
82
+
83
+ uint8_t mac_addr[ETH_ALEN];
84
+ uint32_t rx_desc;
85
+ uint16_t phy_regs[PHY_MAX_REGS];
86
+
87
+ uint32_t regs[R_MAX];
88
+} MSF2EmacState;
89
diff --git a/hw/net/msf2-emac.c b/hw/net/msf2-emac.c
90
new file mode 100644
91
index XXXXXXX..XXXXXXX
92
--- /dev/null
93
+++ b/hw/net/msf2-emac.c
94
@@ -XXX,XX +XXX,XX @@
95
+/*
96
+ * QEMU model of the Smartfusion2 Ethernet MAC.
97
+ *
98
+ * Copyright (c) 2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
99
+ *
100
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
101
+ * of this software and associated documentation files (the "Software"), to deal
102
+ * in the Software without restriction, including without limitation the rights
103
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
104
+ * copies of the Software, and to permit persons to whom the Software is
105
+ * furnished to do so, subject to the following conditions:
106
+ *
107
+ * The above copyright notice and this permission notice shall be included in
108
+ * all copies or substantial portions of the Software.
109
+ *
110
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
111
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
112
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
113
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
114
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
115
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
116
+ * THE SOFTWARE.
117
+ *
118
+ * Refer to section Ethernet MAC in the document:
119
+ * UG0331: SmartFusion2 Microcontroller Subsystem User Guide
120
+ * Datasheet URL:
121
+ * https://www.microsemi.com/document-portal/cat_view/56661-internal-documents/
122
+ * 56758-soc?lang=en&limit=20&limitstart=220
123
+ */
124
+
125
+#include "qemu/osdep.h"
126
+#include "qemu-common.h"
127
+#include "qemu/log.h"
128
+#include "qapi/error.h"
129
+#include "exec/address-spaces.h"
130
+#include "hw/registerfields.h"
131
+#include "hw/net/msf2-emac.h"
132
+#include "hw/net/mii.h"
133
+#include "hw/irq.h"
134
+#include "hw/qdev-properties.h"
135
+#include "migration/vmstate.h"
136
+
137
+REG32(CFG1, 0x0)
138
+ FIELD(CFG1, RESET, 31, 1)
139
+ FIELD(CFG1, RX_EN, 2, 1)
140
+ FIELD(CFG1, TX_EN, 0, 1)
141
+ FIELD(CFG1, LB_EN, 8, 1)
142
+REG32(CFG2, 0x4)
143
+REG32(IFG, 0x8)
144
+REG32(HALF_DUPLEX, 0xc)
145
+REG32(MAX_FRAME_LENGTH, 0x10)
146
+REG32(MII_CMD, 0x24)
147
+ FIELD(MII_CMD, READ, 0, 1)
148
+REG32(MII_ADDR, 0x28)
149
+ FIELD(MII_ADDR, REGADDR, 0, 5)
150
+ FIELD(MII_ADDR, PHYADDR, 8, 5)
151
+REG32(MII_CTL, 0x2c)
152
+REG32(MII_STS, 0x30)
153
+REG32(STA1, 0x40)
154
+REG32(STA2, 0x44)
155
+REG32(FIFO_CFG0, 0x48)
156
+REG32(FIFO_CFG4, 0x58)
157
+ FIELD(FIFO_CFG4, BCAST, 9, 1)
158
+ FIELD(FIFO_CFG4, MCAST, 8, 1)
159
+REG32(FIFO_CFG5, 0x5C)
160
+ FIELD(FIFO_CFG5, BCAST, 9, 1)
161
+ FIELD(FIFO_CFG5, MCAST, 8, 1)
162
+REG32(DMA_TX_CTL, 0x180)
163
+ FIELD(DMA_TX_CTL, EN, 0, 1)
164
+REG32(DMA_TX_DESC, 0x184)
165
+REG32(DMA_TX_STATUS, 0x188)
166
+ FIELD(DMA_TX_STATUS, PKTCNT, 16, 8)
167
+ FIELD(DMA_TX_STATUS, UNDERRUN, 1, 1)
168
+ FIELD(DMA_TX_STATUS, PKT_SENT, 0, 1)
169
+REG32(DMA_RX_CTL, 0x18c)
170
+ FIELD(DMA_RX_CTL, EN, 0, 1)
171
+REG32(DMA_RX_DESC, 0x190)
172
+REG32(DMA_RX_STATUS, 0x194)
173
+ FIELD(DMA_RX_STATUS, PKTCNT, 16, 8)
174
+ FIELD(DMA_RX_STATUS, OVERFLOW, 2, 1)
175
+ FIELD(DMA_RX_STATUS, PKT_RCVD, 0, 1)
176
+REG32(DMA_IRQ_MASK, 0x198)
177
+REG32(DMA_IRQ, 0x19c)
178
+
179
+#define EMPTY_MASK (1 << 31)
180
+#define PKT_SIZE 0x7FF
181
+#define PHYADDR 0x1
182
+#define MAX_PKT_SIZE 2048
183
+
184
+typedef struct {
185
+ uint32_t pktaddr;
186
+ uint32_t pktsize;
187
+ uint32_t next;
188
+} EmacDesc;
189
+
190
+static uint32_t emac_get_isr(MSF2EmacState *s)
191
+{
192
+ uint32_t ier = s->regs[R_DMA_IRQ_MASK];
193
+ uint32_t tx = s->regs[R_DMA_TX_STATUS] & 0xF;
194
+ uint32_t rx = s->regs[R_DMA_RX_STATUS] & 0xF;
195
+ uint32_t isr = (rx << 4) | tx;
196
+
197
+ s->regs[R_DMA_IRQ] = ier & isr;
198
+ return s->regs[R_DMA_IRQ];
199
+}
200
+
201
+static void emac_update_irq(MSF2EmacState *s)
202
+{
203
+ bool intr = emac_get_isr(s);
204
+
205
+ qemu_set_irq(s->irq, intr);
206
+}
207
+
208
+static void emac_load_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc)
209
+{
210
+ address_space_read(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeof *d);
211
+ /* Convert from LE into host endianness. */
212
+ d->pktaddr = le32_to_cpu(d->pktaddr);
213
+ d->pktsize = le32_to_cpu(d->pktsize);
214
+ d->next = le32_to_cpu(d->next);
215
+}
216
+
217
+static void emac_store_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc)
218
+{
219
+ /* Convert from host endianness into LE. */
220
+ d->pktaddr = cpu_to_le32(d->pktaddr);
221
+ d->pktsize = cpu_to_le32(d->pktsize);
222
+ d->next = cpu_to_le32(d->next);
223
+
224
+ address_space_write(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeof *d);
225
+}
226
+
227
+static void msf2_dma_tx(MSF2EmacState *s)
228
+{
229
+ NetClientState *nc = qemu_get_queue(s->nic);
230
+ hwaddr desc = s->regs[R_DMA_TX_DESC];
231
+ uint8_t buf[MAX_PKT_SIZE];
232
+ EmacDesc d;
233
+ int size;
234
+ uint8_t pktcnt;
235
+ uint32_t status;
236
+
237
+ if (!(s->regs[R_CFG1] & R_CFG1_TX_EN_MASK)) {
238
+ return;
239
+ }
240
+
241
+ while (1) {
242
+ emac_load_desc(s, &d, desc);
243
+ if (d.pktsize & EMPTY_MASK) {
244
+ break;
245
+ }
246
+ size = d.pktsize & PKT_SIZE;
247
+ address_space_read(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED,
248
+ buf, size);
249
+ /*
250
+ * This is very basic way to send packets. Ideally there should be
251
+ * a FIFO and packets should be sent out from FIFO only when
252
+ * R_CFG1 bit 0 is set.
253
+ */
254
+ if (s->regs[R_CFG1] & R_CFG1_LB_EN_MASK) {
255
+ nc->info->receive(nc, buf, size);
256
+ } else {
257
+ qemu_send_packet(nc, buf, size);
258
+ }
259
+ d.pktsize |= EMPTY_MASK;
260
+ emac_store_desc(s, &d, desc);
261
+ /* update sent packets count */
262
+ status = s->regs[R_DMA_TX_STATUS];
263
+ pktcnt = FIELD_EX32(status, DMA_TX_STATUS, PKTCNT);
264
+ pktcnt++;
265
+ s->regs[R_DMA_TX_STATUS] = FIELD_DP32(status, DMA_TX_STATUS,
266
+ PKTCNT, pktcnt);
267
+ s->regs[R_DMA_TX_STATUS] |= R_DMA_TX_STATUS_PKT_SENT_MASK;
268
+ desc = d.next;
269
+ }
270
+ s->regs[R_DMA_TX_STATUS] |= R_DMA_TX_STATUS_UNDERRUN_MASK;
271
+ s->regs[R_DMA_TX_CTL] &= ~R_DMA_TX_CTL_EN_MASK;
272
+}
273
+
274
+static void msf2_phy_update_link(MSF2EmacState *s)
275
+{
276
+ /* Autonegotiation status mirrors link status. */
277
+ if (qemu_get_queue(s->nic)->link_down) {
278
+ s->phy_regs[MII_BMSR] &= ~(MII_BMSR_AN_COMP |
279
+ MII_BMSR_LINK_ST);
280
+ } else {
281
+ s->phy_regs[MII_BMSR] |= (MII_BMSR_AN_COMP |
282
+ MII_BMSR_LINK_ST);
283
+ }
284
+}
285
+
286
+static void msf2_phy_reset(MSF2EmacState *s)
287
+{
288
+ memset(&s->phy_regs[0], 0, sizeof(s->phy_regs));
289
+ s->phy_regs[MII_BMCR] = 0x1140;
290
+ s->phy_regs[MII_BMSR] = 0x7968;
291
+ s->phy_regs[MII_PHYID1] = 0x0022;
292
+ s->phy_regs[MII_PHYID2] = 0x1550;
293
+ s->phy_regs[MII_ANAR] = 0x01E1;
294
+ s->phy_regs[MII_ANLPAR] = 0xCDE1;
295
+
296
+ msf2_phy_update_link(s);
297
+}
298
+
299
+static void write_to_phy(MSF2EmacState *s)
300
+{
301
+ uint8_t reg_addr = s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK;
302
+ uint8_t phy_addr = (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT) &
303
+ R_MII_ADDR_REGADDR_MASK;
304
+ uint16_t data = s->regs[R_MII_CTL] & 0xFFFF;
305
+
306
+ if (phy_addr != PHYADDR) {
307
+ return;
308
+ }
309
+
310
+ switch (reg_addr) {
311
+ case MII_BMCR:
312
+ if (data & MII_BMCR_RESET) {
313
+ /* Phy reset */
314
+ msf2_phy_reset(s);
315
+ data &= ~MII_BMCR_RESET;
316
+ }
317
+ if (data & MII_BMCR_AUTOEN) {
318
+ /* Complete autonegotiation immediately */
319
+ data &= ~MII_BMCR_AUTOEN;
320
+ s->phy_regs[MII_BMSR] |= MII_BMSR_AN_COMP;
321
+ }
322
+ break;
323
+ }
324
+
325
+ s->phy_regs[reg_addr] = data;
326
+}
327
+
328
+static uint16_t read_from_phy(MSF2EmacState *s)
329
+{
330
+ uint8_t reg_addr = s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK;
331
+ uint8_t phy_addr = (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT) &
332
+ R_MII_ADDR_REGADDR_MASK;
333
+
334
+ if (phy_addr == PHYADDR) {
335
+ return s->phy_regs[reg_addr];
336
+ } else {
337
+ return 0xFFFF;
338
+ }
339
+}
340
+
341
+static void msf2_emac_do_reset(MSF2EmacState *s)
342
+{
343
+ memset(&s->regs[0], 0, sizeof(s->regs));
344
+ s->regs[R_CFG1] = 0x80000000;
345
+ s->regs[R_CFG2] = 0x00007000;
346
+ s->regs[R_IFG] = 0x40605060;
347
+ s->regs[R_HALF_DUPLEX] = 0x00A1F037;
348
+ s->regs[R_MAX_FRAME_LENGTH] = 0x00000600;
349
+ s->regs[R_FIFO_CFG5] = 0X3FFFF;
350
+
351
+ msf2_phy_reset(s);
352
+}
353
+
354
+static uint64_t emac_read(void *opaque, hwaddr addr, unsigned int size)
355
+{
356
+ MSF2EmacState *s = opaque;
357
+ uint32_t r = 0;
358
+
359
+ addr >>= 2;
360
+
361
+ switch (addr) {
362
+ case R_DMA_IRQ:
363
+ r = emac_get_isr(s);
364
+ break;
365
+ default:
366
+ if (addr >= ARRAY_SIZE(s->regs)) {
367
+ qemu_log_mask(LOG_GUEST_ERROR,
368
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
369
+ addr * 4);
370
+ return r;
371
+ }
372
+ r = s->regs[addr];
373
+ break;
374
+ }
375
+ return r;
376
+}
377
+
378
+static void emac_write(void *opaque, hwaddr addr, uint64_t val64,
379
+ unsigned int size)
380
+{
381
+ MSF2EmacState *s = opaque;
382
+ uint32_t value = val64;
383
+ uint32_t enreqbits;
384
+ uint8_t pktcnt;
385
+
386
+ addr >>= 2;
387
+ switch (addr) {
388
+ case R_DMA_TX_CTL:
389
+ s->regs[addr] = value;
390
+ if (value & R_DMA_TX_CTL_EN_MASK) {
391
+ msf2_dma_tx(s);
392
+ }
393
+ break;
394
+ case R_DMA_RX_CTL:
395
+ s->regs[addr] = value;
396
+ if (value & R_DMA_RX_CTL_EN_MASK) {
397
+ s->rx_desc = s->regs[R_DMA_RX_DESC];
398
+ qemu_flush_queued_packets(qemu_get_queue(s->nic));
399
+ }
400
+ break;
401
+ case R_CFG1:
402
+ s->regs[addr] = value;
403
+ if (value & R_CFG1_RESET_MASK) {
404
+ msf2_emac_do_reset(s);
405
+ }
406
+ break;
407
+ case R_FIFO_CFG0:
408
+ /*
409
+ * For our implementation, turning on modules is instantaneous,
410
+ * so the states requested via the *ENREQ bits appear in the
411
+ * *ENRPLY bits immediately. Also the reset bits to reset PE-MCXMAC
412
+ * module are not emulated here since it deals with start of frames,
413
+ * inter-packet gap and control frames.
414
+ */
415
+ enreqbits = extract32(value, 8, 5);
416
+ s->regs[addr] = deposit32(value, 16, 5, enreqbits);
417
+ break;
418
+ case R_DMA_TX_DESC:
419
+ if (value & 0x3) {
420
+ qemu_log_mask(LOG_GUEST_ERROR, "Tx Descriptor address should be"
421
+ " 32 bit aligned\n");
422
+ }
423
+ /* Ignore [1:0] bits */
424
+ s->regs[addr] = value & ~3;
425
+ break;
426
+ case R_DMA_RX_DESC:
427
+ if (value & 0x3) {
428
+ qemu_log_mask(LOG_GUEST_ERROR, "Rx Descriptor address should be"
429
+ " 32 bit aligned\n");
430
+ }
431
+ /* Ignore [1:0] bits */
432
+ s->regs[addr] = value & ~3;
433
+ break;
434
+ case R_DMA_TX_STATUS:
435
+ if (value & R_DMA_TX_STATUS_UNDERRUN_MASK) {
436
+ s->regs[addr] &= ~R_DMA_TX_STATUS_UNDERRUN_MASK;
437
+ }
438
+ if (value & R_DMA_TX_STATUS_PKT_SENT_MASK) {
439
+ pktcnt = FIELD_EX32(s->regs[addr], DMA_TX_STATUS, PKTCNT);
440
+ pktcnt--;
441
+ s->regs[addr] = FIELD_DP32(s->regs[addr], DMA_TX_STATUS,
442
+ PKTCNT, pktcnt);
443
+ if (pktcnt == 0) {
444
+ s->regs[addr] &= ~R_DMA_TX_STATUS_PKT_SENT_MASK;
445
+ }
446
+ }
447
+ break;
448
+ case R_DMA_RX_STATUS:
449
+ if (value & R_DMA_RX_STATUS_OVERFLOW_MASK) {
450
+ s->regs[addr] &= ~R_DMA_RX_STATUS_OVERFLOW_MASK;
451
+ }
452
+ if (value & R_DMA_RX_STATUS_PKT_RCVD_MASK) {
453
+ pktcnt = FIELD_EX32(s->regs[addr], DMA_RX_STATUS, PKTCNT);
454
+ pktcnt--;
455
+ s->regs[addr] = FIELD_DP32(s->regs[addr], DMA_RX_STATUS,
456
+ PKTCNT, pktcnt);
457
+ if (pktcnt == 0) {
458
+ s->regs[addr] &= ~R_DMA_RX_STATUS_PKT_RCVD_MASK;
459
+ }
460
+ }
461
+ break;
462
+ case R_DMA_IRQ:
463
+ break;
464
+ case R_MII_CMD:
465
+ if (value & R_MII_CMD_READ_MASK) {
466
+ s->regs[R_MII_STS] = read_from_phy(s);
467
+ }
468
+ break;
469
+ case R_MII_CTL:
470
+ s->regs[addr] = value;
471
+ write_to_phy(s);
472
+ break;
473
+ case R_STA1:
474
+ s->regs[addr] = value;
475
+ /*
476
+ * R_STA1 [31:24] : octet 1 of mac address
477
+ * R_STA1 [23:16] : octet 2 of mac address
478
+ * R_STA1 [15:8] : octet 3 of mac address
479
+ * R_STA1 [7:0] : octet 4 of mac address
480
+ */
481
+ stl_be_p(s->mac_addr, value);
482
+ break;
483
+ case R_STA2:
484
+ s->regs[addr] = value;
485
+ /*
486
+ * R_STA2 [31:24] : octet 5 of mac address
487
+ * R_STA2 [23:16] : octet 6 of mac address
488
+ */
489
+ stw_be_p(s->mac_addr + 4, value >> 16);
490
+ break;
491
+ default:
492
+ if (addr >= ARRAY_SIZE(s->regs)) {
493
+ qemu_log_mask(LOG_GUEST_ERROR,
494
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
495
+ addr * 4);
496
+ return;
497
+ }
498
+ s->regs[addr] = value;
499
+ break;
500
+ }
501
+ emac_update_irq(s);
502
+}
503
+
504
+static const MemoryRegionOps emac_ops = {
505
+ .read = emac_read,
506
+ .write = emac_write,
507
+ .endianness = DEVICE_NATIVE_ENDIAN,
508
+ .impl = {
509
+ .min_access_size = 4,
510
+ .max_access_size = 4
511
+ }
512
+};
513
+
514
+static bool emac_can_rx(NetClientState *nc)
515
+{
516
+ MSF2EmacState *s = qemu_get_nic_opaque(nc);
517
+
518
+ return (s->regs[R_CFG1] & R_CFG1_RX_EN_MASK) &&
519
+ (s->regs[R_DMA_RX_CTL] & R_DMA_RX_CTL_EN_MASK);
520
+}
521
+
522
+static bool addr_filter_ok(MSF2EmacState *s, const uint8_t *buf)
523
+{
524
+ /* The broadcast MAC address: FF:FF:FF:FF:FF:FF */
525
+ const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF,
526
+ 0xFF, 0xFF };
527
+ bool bcast_en = true;
528
+ bool mcast_en = true;
529
+
530
+ if (s->regs[R_FIFO_CFG5] & R_FIFO_CFG5_BCAST_MASK) {
531
+ bcast_en = true; /* Broadcast dont care for drop circuitry */
532
+ } else if (s->regs[R_FIFO_CFG4] & R_FIFO_CFG4_BCAST_MASK) {
533
+ bcast_en = false;
534
+ }
535
+
536
+ if (s->regs[R_FIFO_CFG5] & R_FIFO_CFG5_MCAST_MASK) {
537
+ mcast_en = true; /* Multicast dont care for drop circuitry */
538
+ } else if (s->regs[R_FIFO_CFG4] & R_FIFO_CFG4_MCAST_MASK) {
539
+ mcast_en = false;
540
+ }
541
+
542
+ if (!memcmp(buf, broadcast_addr, sizeof(broadcast_addr))) {
543
+ return bcast_en;
544
+ }
545
+
546
+ if (buf[0] & 1) {
547
+ return mcast_en;
548
+ }
549
+
550
+ return !memcmp(buf, s->mac_addr, sizeof(s->mac_addr));
551
+}
552
+
553
+static ssize_t emac_rx(NetClientState *nc, const uint8_t *buf, size_t size)
554
+{
555
+ MSF2EmacState *s = qemu_get_nic_opaque(nc);
556
+ EmacDesc d;
557
+ uint8_t pktcnt;
558
+ uint32_t status;
559
+
560
+ if (size > (s->regs[R_MAX_FRAME_LENGTH] & 0xFFFF)) {
561
+ return size;
562
+ }
563
+ if (!addr_filter_ok(s, buf)) {
564
+ return size;
565
+ }
566
+
567
+ emac_load_desc(s, &d, s->rx_desc);
568
+
569
+ if (d.pktsize & EMPTY_MASK) {
570
+ address_space_write(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED,
571
+ buf, size & PKT_SIZE);
572
+ d.pktsize = size & PKT_SIZE;
573
+ emac_store_desc(s, &d, s->rx_desc);
574
+ /* update received packets count */
575
+ status = s->regs[R_DMA_RX_STATUS];
576
+ pktcnt = FIELD_EX32(status, DMA_RX_STATUS, PKTCNT);
577
+ pktcnt++;
578
+ s->regs[R_DMA_RX_STATUS] = FIELD_DP32(status, DMA_RX_STATUS,
579
+ PKTCNT, pktcnt);
580
+ s->regs[R_DMA_RX_STATUS] |= R_DMA_RX_STATUS_PKT_RCVD_MASK;
581
+ s->rx_desc = d.next;
582
+ } else {
583
+ s->regs[R_DMA_RX_CTL] &= ~R_DMA_RX_CTL_EN_MASK;
584
+ s->regs[R_DMA_RX_STATUS] |= R_DMA_RX_STATUS_OVERFLOW_MASK;
585
+ }
586
+ emac_update_irq(s);
587
+ return size;
588
+}
589
+
590
+static void msf2_emac_reset(DeviceState *dev)
591
+{
592
+ MSF2EmacState *s = MSS_EMAC(dev);
593
+
594
+ msf2_emac_do_reset(s);
595
+}
596
+
597
+static void emac_set_link(NetClientState *nc)
598
+{
599
+ MSF2EmacState *s = qemu_get_nic_opaque(nc);
600
+
601
+ msf2_phy_update_link(s);
602
+}
603
+
604
+static NetClientInfo net_msf2_emac_info = {
605
+ .type = NET_CLIENT_DRIVER_NIC,
606
+ .size = sizeof(NICState),
607
+ .can_receive = emac_can_rx,
608
+ .receive = emac_rx,
609
+ .link_status_changed = emac_set_link,
610
+};
611
+
612
+static void msf2_emac_realize(DeviceState *dev, Error **errp)
613
+{
614
+ MSF2EmacState *s = MSS_EMAC(dev);
615
+
616
+ if (!s->dma_mr) {
617
+ error_setg(errp, "MSS_EMAC 'ahb-bus' link not set");
618
+ return;
619
+ }
620
+
621
+ address_space_init(&s->dma_as, s->dma_mr, "emac-ahb");
622
+
623
+ qemu_macaddr_default_if_unset(&s->conf.macaddr);
624
+ s->nic = qemu_new_nic(&net_msf2_emac_info, &s->conf,
625
+ object_get_typename(OBJECT(dev)), dev->id, s);
626
+ qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
627
+}
628
+
629
+static void msf2_emac_init(Object *obj)
630
+{
631
+ MSF2EmacState *s = MSS_EMAC(obj);
632
+
633
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
634
+
635
+ memory_region_init_io(&s->mmio, obj, &emac_ops, s,
636
+ "msf2-emac", R_MAX * 4);
637
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
638
+}
639
+
640
+static Property msf2_emac_properties[] = {
641
+ DEFINE_PROP_LINK("ahb-bus", MSF2EmacState, dma_mr,
642
+ TYPE_MEMORY_REGION, MemoryRegion *),
643
+ DEFINE_NIC_PROPERTIES(MSF2EmacState, conf),
644
+ DEFINE_PROP_END_OF_LIST(),
645
+};
646
+
647
+static const VMStateDescription vmstate_msf2_emac = {
648
+ .name = TYPE_MSS_EMAC,
649
+ .version_id = 1,
650
+ .minimum_version_id = 1,
651
+ .fields = (VMStateField[]) {
652
+ VMSTATE_UINT8_ARRAY(mac_addr, MSF2EmacState, ETH_ALEN),
653
+ VMSTATE_UINT32(rx_desc, MSF2EmacState),
654
+ VMSTATE_UINT16_ARRAY(phy_regs, MSF2EmacState, PHY_MAX_REGS),
655
+ VMSTATE_UINT32_ARRAY(regs, MSF2EmacState, R_MAX),
656
+ VMSTATE_END_OF_LIST()
657
+ }
658
+};
659
+
660
+static void msf2_emac_class_init(ObjectClass *klass, void *data)
661
+{
662
+ DeviceClass *dc = DEVICE_CLASS(klass);
663
+
664
+ dc->realize = msf2_emac_realize;
665
+ dc->reset = msf2_emac_reset;
666
+ dc->vmsd = &vmstate_msf2_emac;
667
+ device_class_set_props(dc, msf2_emac_properties);
668
+}
669
+
670
+static const TypeInfo msf2_emac_info = {
671
+ .name = TYPE_MSS_EMAC,
672
+ .parent = TYPE_SYS_BUS_DEVICE,
673
+ .instance_size = sizeof(MSF2EmacState),
674
+ .instance_init = msf2_emac_init,
675
+ .class_init = msf2_emac_class_init,
676
+};
677
+
678
+static void msf2_emac_register_types(void)
679
+{
680
+ type_register_static(&msf2_emac_info);
681
+}
682
+
683
+type_init(msf2_emac_register_types)
684
diff --git a/MAINTAINERS b/MAINTAINERS
14
diff --git a/MAINTAINERS b/MAINTAINERS
685
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
686
--- a/MAINTAINERS
16
--- a/MAINTAINERS
687
+++ b/MAINTAINERS
17
+++ b/MAINTAINERS
688
@@ -XXX,XX +XXX,XX @@ F: include/hw/arm/msf2-soc.h
18
@@ -XXX,XX +XXX,XX @@ F: tests/qtest/fuzz-sb16-test.c
689
F: include/hw/misc/msf2-sysreg.h
19
690
F: include/hw/timer/mss-timer.h
20
Xilinx CAN
691
F: include/hw/ssi/mss-spi.h
21
M: Francisco Iglesias <francisco.iglesias@amd.com>
692
+F: hw/net/msf2-emac.c
22
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
693
+F: include/hw/net/msf2-emac.h
23
S: Maintained
694
24
F: hw/net/can/xlnx-*
695
Emcraft M2S-FG484
25
F: include/hw/net/xlnx-*
696
M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
26
@@ -XXX,XX +XXX,XX @@ F: include/hw/rx/
27
CAN bus subsystem and hardware
28
M: Pavel Pisa <pisa@cmp.felk.cvut.cz>
29
M: Francisco Iglesias <francisco.iglesias@amd.com>
30
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
31
S: Maintained
32
W: https://canbus.pages.fel.cvut.cz/
33
F: net/can/*
697
--
34
--
698
2.20.1
35
2.34.1
699
700
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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