1
First arm pullreq of the 5.1 cycle; mostly bugfixes and some
1
Arm queue; not huge but I figured I might as well send it out since
2
cleanup patches. The new clock modelling framework is the big
2
I've been doing code review today and there's no queue of unprocessed
3
thing here.
3
pullreqs...
4
4
5
thanks
5
-- PMM
6
-- PMM
6
7
7
The following changes since commit 648db19685b7030aa558a4ddbd3a8e53d8c9a062:
8
The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92:
8
9
9
Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-04-29' into staging (2020-04-29 15:07:33 +0100)
10
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000)
10
11
11
are available in the Git repository at:
12
are available in the Git repository at:
12
13
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200430
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112
14
15
15
for you to fetch changes up to 1267437e593e85498f9105b3bdab796630d2e83f:
16
for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de:
16
17
17
hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes (2020-04-30 11:52:29 +0100)
18
ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000)
18
19
19
----------------------------------------------------------------
20
----------------------------------------------------------------
20
target-arm queue:
21
target-arm queue:
21
* xlnx-zdma: Fix endianness handling of descriptor loading
22
* arm: Support emulation of ARMv8.4-TTST extension
22
* nrf51: Fix last GPIO CNF address
23
* arm: Update cpu.h ID register field definitions
23
* gicv3: Use gicr_typer in arm_gicv3_icc_reset
24
* arm: Fix breakage of XScale instruction emulation
24
* msf2: Add EMAC block to SmartFusion2 SoC
25
* hw/net/lan9118: Fix RX Status FIFO PEEK value
25
* New clock modelling framework
26
* npcm7xx: Add ADC and PWM emulation
26
* hw/arm: versal: Setup the ADMA with 128bit bus-width
27
* ui/cocoa: Make "open docs" help menu entry work again when binary
27
* Cadence: gem: fix wraparound in 64bit descriptors
28
is run from the build tree
28
* cadence_gem: clear RX control descriptor
29
* ui/cocoa: Fix openFile: deprecation on Big Sur
29
* target/arm: Vectorize integer comparison vs zero
30
* docs: Add qemu-storage-daemon(1) manpage to meson.build
30
* hw/arm/virt: dt: add kaslr-seed property
31
* docs: Build and install all the docs in a single manual
31
* hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes
32
32
33
----------------------------------------------------------------
33
----------------------------------------------------------------
34
Cameron Esfahani (1):
34
Hao Wu (6):
35
nrf51: Fix last GPIO CNF address
35
hw/misc: Add clock converter in NPCM7XX CLK module
36
hw/timer: Refactor NPCM7XX Timer to use CLK clock
37
hw/adc: Add an ADC module for NPCM7XX
38
hw/misc: Add a PWM module for NPCM7XX
39
hw/misc: Add QTest for NPCM7XX PWM Module
40
hw/*: Use type casting for SysBusDevice in NPCM7XX
36
41
37
Damien Hedde (7):
42
Leif Lindholm (6):
38
hw/core/clock-vmstate: define a vmstate entry for clock state
43
target/arm: fix typo in cpu.h ID_AA64PFR1 field name
39
qdev: add clock input&output support to devices.
44
target/arm: make ARMCPU.clidr 64-bit
40
qdev-clock: introduce an init array to ease the device construction
45
target/arm: make ARMCPU.ctr 64-bit
41
hw/misc/zynq_slcr: add clock generation for uarts
46
target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
42
hw/char/cadence_uart: add clock support
47
target/arm: add aarch64 ID register fields to cpu.h
43
hw/arm/xilinx_zynq: connect uart clocks to slcr
48
target/arm: add aarch32 ID register fields to cpu.h
44
qdev-monitor: print the device's clock with info qtree
45
49
46
Edgar E. Iglesias (7):
50
Peter Maydell (5):
47
dma/xlnx-zdma: Fix descriptor loading (MEM) wrt endianness
51
docs: Add qemu-storage-daemon(1) manpage to meson.build
48
dma/xlnx-zdma: Fix descriptor loading (REG) wrt endianness
52
docs: Build and install all the docs in a single manual
49
hw/arm: versal: Setup the ADMA with 128bit bus-width
53
target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
50
device_tree: Allow name wildcards in qemu_fdt_node_path()
54
hw/net/lan9118: Fix RX Status FIFO PEEK value
51
device_tree: Constify compat in qemu_fdt_node_path()
55
hw/net/lan9118: Add symbolic constants for register offsets
52
hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102
53
hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes
54
56
55
Jerome Forissier (2):
57
Roman Bolshakov (2):
56
hw/arm/virt: dt: move creation of /secure-chosen to create_fdt()
58
ui/cocoa: Update path to docs in build tree
57
hw/arm/virt: dt: add kaslr-seed property
59
ui/cocoa: Fix openFile: deprecation on Big Sur
58
60
59
Keqian Zhu (2):
61
Rémi Denis-Courmont (2):
60
bugfix: Use gicr_typer in arm_gicv3_icc_reset
62
target/arm: ARMv8.4-TTST extension
61
Typo: Correct the name of CPU hotplug memory region
63
target/arm: enable Small Translation tables in max CPU
62
64
63
Peter Maydell (2):
65
docs/conf.py | 46 ++-
64
hw/core/clock: introduce clock object
66
docs/devel/conf.py | 15 -
65
docs/clocks: add device's clock documentation
67
docs/index.html.in | 17 -
68
docs/interop/conf.py | 28 --
69
docs/meson.build | 65 ++--
70
docs/specs/conf.py | 16 -
71
docs/system/arm/nuvoton.rst | 4 +-
72
docs/system/conf.py | 28 --
73
docs/tools/conf.py | 37 --
74
docs/user/conf.py | 15 -
75
meson.build | 1 +
76
hw/adc/trace.h | 1 +
77
include/hw/adc/npcm7xx_adc.h | 69 ++++
78
include/hw/arm/npcm7xx.h | 4 +
79
include/hw/misc/npcm7xx_clk.h | 146 ++++++-
80
include/hw/misc/npcm7xx_pwm.h | 105 +++++
81
include/hw/timer/npcm7xx_timer.h | 1 +
82
target/arm/cpu.h | 85 ++++-
83
hw/adc/npcm7xx_adc.c | 301 +++++++++++++++
84
hw/arm/npcm7xx.c | 55 ++-
85
hw/arm/npcm7xx_boards.c | 2 +-
86
hw/mem/npcm7xx_mc.c | 2 +-
87
hw/misc/npcm7xx_clk.c | 807 ++++++++++++++++++++++++++++++++++++++-
88
hw/misc/npcm7xx_gcr.c | 2 +-
89
hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++
90
hw/misc/npcm7xx_rng.c | 2 +-
91
hw/net/lan9118.c | 26 +-
92
hw/nvram/npcm7xx_otp.c | 2 +-
93
hw/ssi/npcm7xx_fiu.c | 2 +-
94
hw/timer/npcm7xx_timer.c | 39 +-
95
target/arm/cpu64.c | 1 +
96
target/arm/helper.c | 15 +-
97
target/arm/translate.c | 7 +
98
tests/qtest/npcm7xx_adc-test.c | 377 ++++++++++++++++++
99
tests/qtest/npcm7xx_pwm-test.c | 490 ++++++++++++++++++++++++
100
hw/adc/meson.build | 1 +
101
hw/adc/trace-events | 5 +
102
hw/misc/meson.build | 1 +
103
hw/misc/trace-events | 6 +
104
tests/qtest/meson.build | 4 +-
105
ui/cocoa.m | 7 +-
106
41 files changed, 3124 insertions(+), 263 deletions(-)
107
delete mode 100644 docs/devel/conf.py
108
delete mode 100644 docs/index.html.in
109
delete mode 100644 docs/interop/conf.py
110
delete mode 100644 docs/specs/conf.py
111
delete mode 100644 docs/system/conf.py
112
delete mode 100644 docs/tools/conf.py
113
delete mode 100644 docs/user/conf.py
114
create mode 100644 hw/adc/trace.h
115
create mode 100644 include/hw/adc/npcm7xx_adc.h
116
create mode 100644 include/hw/misc/npcm7xx_pwm.h
117
create mode 100644 hw/adc/npcm7xx_adc.c
118
create mode 100644 hw/misc/npcm7xx_pwm.c
119
create mode 100644 tests/qtest/npcm7xx_adc-test.c
120
create mode 100644 tests/qtest/npcm7xx_pwm-test.c
121
create mode 100644 hw/adc/trace-events
66
122
67
Philippe Mathieu-Daudé (3):
68
target/arm: Restrict the Address Translate write operation to TCG accel
69
target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]
70
target/arm/cpu: Update coding style to make checkpatch.pl happy
71
72
Ramon Fried (2):
73
Cadence: gem: fix wraparound in 64bit descriptors
74
net: cadence_gem: clear RX control descriptor
75
76
Richard Henderson (1):
77
target/arm: Vectorize integer comparison vs zero
78
79
Subbaraya Sundeep (3):
80
hw/net: Add Smartfusion2 emac block
81
msf2: Add EMAC block to SmartFusion2 SoC
82
tests/boot_linux_console: Add ethernet test to SmartFusion2
83
84
Thomas Huth (1):
85
target/arm: Make cpu_register() available for other files
86
87
hw/core/Makefile.objs | 2 +
88
hw/net/Makefile.objs | 1 +
89
tests/Makefile.include | 1 +
90
include/hw/arm/msf2-soc.h | 2 +
91
include/hw/char/cadence_uart.h | 1 +
92
include/hw/clock.h | 225 +++++++++++++
93
include/hw/gpio/nrf51_gpio.h | 2 +-
94
include/hw/net/msf2-emac.h | 53 +++
95
include/hw/qdev-clock.h | 159 +++++++++
96
include/hw/qdev-core.h | 12 +
97
include/sysemu/device_tree.h | 5 +-
98
target/arm/cpu-qom.h | 9 +-
99
target/arm/helper.h | 27 +-
100
target/arm/translate.h | 5 +
101
device_tree.c | 4 +-
102
hw/acpi/cpu.c | 2 +-
103
hw/arm/msf2-soc.c | 26 +-
104
hw/arm/virt.c | 20 +-
105
hw/arm/xilinx_zynq.c | 57 +++-
106
hw/arm/xlnx-versal.c | 2 +
107
hw/arm/xlnx-zcu102.c | 39 ++-
108
hw/char/cadence_uart.c | 73 +++-
109
hw/core/clock-vmstate.c | 25 ++
110
hw/core/clock.c | 130 ++++++++
111
hw/core/qdev-clock.c | 185 +++++++++++
112
hw/core/qdev.c | 12 +
113
hw/dma/xlnx-zdma.c | 25 +-
114
hw/intc/arm_gicv3_kvm.c | 4 +-
115
hw/misc/zynq_slcr.c | 172 +++++++++-
116
hw/net/cadence_gem.c | 16 +-
117
hw/net/msf2-emac.c | 589 +++++++++++++++++++++++++++++++++
118
qdev-monitor.c | 9 +
119
target/arm/cpu.c | 25 +-
120
target/arm/cpu64.c | 16 +-
121
target/arm/helper.c | 17 +
122
target/arm/neon_helper.c | 24 --
123
target/arm/translate-a64.c | 64 +---
124
target/arm/translate.c | 256 ++++++++++++--
125
target/arm/vec_helper.c | 25 ++
126
MAINTAINERS | 2 +
127
docs/devel/clocks.rst | 391 ++++++++++++++++++++++
128
docs/devel/index.rst | 1 +
129
hw/char/trace-events | 3 +
130
hw/core/trace-events | 7 +
131
tests/acceptance/boot_linux_console.py | 15 +-
132
45 files changed, 2538 insertions(+), 202 deletions(-)
133
create mode 100644 include/hw/clock.h
134
create mode 100644 include/hw/net/msf2-emac.h
135
create mode 100644 include/hw/qdev-clock.h
136
create mode 100644 hw/core/clock-vmstate.c
137
create mode 100644 hw/core/clock.c
138
create mode 100644 hw/core/qdev-clock.c
139
create mode 100644 hw/net/msf2-emac.c
140
create mode 100644 docs/devel/clocks.rst
141
diff view generated by jsdifflib
Deleted patch
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
2
1
3
Fix descriptor loading from memory wrt host endianness.
4
5
Reported-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20200404122718.25111-2-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/dma/xlnx-zdma.c | 11 +++++++----
13
1 file changed, 7 insertions(+), 4 deletions(-)
14
15
diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/dma/xlnx-zdma.c
18
+++ b/hw/dma/xlnx-zdma.c
19
@@ -XXX,XX +XXX,XX @@ static void zdma_put_regaddr64(XlnxZDMA *s, unsigned int basereg, uint64_t addr)
20
s->regs[basereg + 1] = addr >> 32;
21
}
22
23
-static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
24
+static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr,
25
+ XlnxZDMADescr *descr)
26
{
27
/* ZDMA descriptors must be aligned to their own size. */
28
if (addr % sizeof(XlnxZDMADescr)) {
29
qemu_log_mask(LOG_GUEST_ERROR,
30
"zdma: unaligned descriptor at %" PRIx64,
31
addr);
32
- memset(buf, 0x0, sizeof(XlnxZDMADescr));
33
+ memset(descr, 0x0, sizeof(XlnxZDMADescr));
34
s->error = true;
35
return false;
36
}
37
38
- address_space_read(s->dma_as, addr, s->attr, buf, sizeof(XlnxZDMADescr));
39
+ descr->addr = address_space_ldq_le(s->dma_as, addr, s->attr, NULL);
40
+ descr->size = address_space_ldl_le(s->dma_as, addr + 8, s->attr, NULL);
41
+ descr->attr = address_space_ldl_le(s->dma_as, addr + 12, s->attr, NULL);
42
return true;
43
}
44
45
@@ -XXX,XX +XXX,XX @@ static void zdma_update_descr_addr(XlnxZDMA *s, bool type,
46
} else {
47
addr = zdma_get_regaddr64(s, basereg);
48
addr += sizeof(s->dsc_dst);
49
- address_space_read(s->dma_as, addr, s->attr, (void *) &next, 8);
50
+ next = address_space_ldq_le(s->dma_as, addr, s->attr, NULL);
51
}
52
53
zdma_put_regaddr64(s, basereg, next);
54
--
55
2.20.1
56
57
diff view generated by jsdifflib
Deleted patch
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
2
1
3
Fix descriptor loading from registers wrt host endianness.
4
5
Reported-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
8
Message-id: 20200404122718.25111-3-edgar.iglesias@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/dma/xlnx-zdma.c | 14 ++++++++++----
12
1 file changed, 10 insertions(+), 4 deletions(-)
13
14
diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/dma/xlnx-zdma.c
17
+++ b/hw/dma/xlnx-zdma.c
18
@@ -XXX,XX +XXX,XX @@ static void zdma_put_regaddr64(XlnxZDMA *s, unsigned int basereg, uint64_t addr)
19
s->regs[basereg + 1] = addr >> 32;
20
}
21
22
+static void zdma_load_descriptor_reg(XlnxZDMA *s, unsigned int reg,
23
+ XlnxZDMADescr *descr)
24
+{
25
+ descr->addr = zdma_get_regaddr64(s, reg);
26
+ descr->size = s->regs[reg + 2];
27
+ descr->attr = s->regs[reg + 3];
28
+}
29
+
30
static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr,
31
XlnxZDMADescr *descr)
32
{
33
@@ -XXX,XX +XXX,XX @@ static void zdma_load_src_descriptor(XlnxZDMA *s)
34
unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE);
35
36
if (ptype == PT_REG) {
37
- memcpy(&s->dsc_src, &s->regs[R_ZDMA_CH_SRC_DSCR_WORD0],
38
- sizeof(s->dsc_src));
39
+ zdma_load_descriptor_reg(s, R_ZDMA_CH_SRC_DSCR_WORD0, &s->dsc_src);
40
return;
41
}
42
43
@@ -XXX,XX +XXX,XX @@ static void zdma_load_dst_descriptor(XlnxZDMA *s)
44
bool dst_type;
45
46
if (ptype == PT_REG) {
47
- memcpy(&s->dsc_dst, &s->regs[R_ZDMA_CH_DST_DSCR_WORD0],
48
- sizeof(s->dsc_dst));
49
+ zdma_load_descriptor_reg(s, R_ZDMA_CH_DST_DSCR_WORD0, &s->dsc_dst);
50
return;
51
}
52
53
--
54
2.20.1
55
56
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
2
2
3
Disable unsupported FDT firmware nodes if a user passes us
3
This adds for the Small Translation tables extension in AArch64 state.
4
a DTB with nodes enabled that the machine cannot support
5
due to lack of EL3 or EL2 support.
6
4
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
8
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200423121114.4274-5-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
8
---
12
hw/arm/xlnx-zcu102.c | 30 ++++++++++++++++++++++++++++++
9
target/arm/cpu.h | 5 +++++
13
1 file changed, 30 insertions(+)
10
target/arm/helper.c | 15 +++++++++++++--
11
2 files changed, 18 insertions(+), 2 deletions(-)
14
12
15
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/xlnx-zcu102.c
15
--- a/target/arm/cpu.h
18
+++ b/hw/arm/xlnx-zcu102.c
16
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
20
#include "qemu/error-report.h"
18
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
21
#include "qemu/log.h"
22
#include "sysemu/qtest.h"
23
+#include "sysemu/device_tree.h"
24
25
typedef struct XlnxZCU102 {
26
MachineState parent_obj;
27
@@ -XXX,XX +XXX,XX @@ static void zcu102_set_virt(Object *obj, bool value, Error **errp)
28
s->virt = value;
29
}
19
}
30
20
31
+static void zcu102_modify_dtb(const struct arm_boot_info *binfo, void *fdt)
21
+static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
32
+{
22
+{
33
+ XlnxZCU102 *s = container_of(binfo, XlnxZCU102, binfo);
23
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
34
+ bool method_is_hvc;
35
+ char **node_path;
36
+ const char *r;
37
+ int prop_len;
38
+ int i;
39
+
40
+ /* If EL3 is enabled, we keep all firmware nodes active. */
41
+ if (!s->secure) {
42
+ node_path = qemu_fdt_node_path(fdt, NULL, "xlnx,zynqmp-firmware",
43
+ &error_fatal);
44
+
45
+ for (i = 0; node_path && node_path[i]; i++) {
46
+ r = qemu_fdt_getprop(fdt, node_path[i], "method", &prop_len, NULL);
47
+ method_is_hvc = r && !strcmp("hvc", r);
48
+
49
+ /* Allow HVC based firmware if EL2 is enabled. */
50
+ if (method_is_hvc && s->virt) {
51
+ continue;
52
+ }
53
+ qemu_fdt_setprop_string(fdt, node_path[i], "status", "disabled");
54
+ }
55
+ g_strfreev(node_path);
56
+ }
57
+}
24
+}
58
+
25
+
59
static void xlnx_zcu102_init(MachineState *machine)
26
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
60
{
27
{
61
XlnxZCU102 *s = ZCU102_MACHINE(machine);
28
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
62
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
29
diff --git a/target/arm/helper.c b/target/arm/helper.c
63
30
index XXXXXXX..XXXXXXX 100644
64
s->binfo.ram_size = ram_size;
31
--- a/target/arm/helper.c
65
s->binfo.loader_start = 0;
32
+++ b/target/arm/helper.c
66
+ s->binfo.modify_dtb = zcu102_modify_dtb;
33
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
67
arm_load_kernel(s->soc.boot_cpu_ptr, machine, &s->binfo);
34
{
68
}
35
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
69
36
bool epd, hpd, using16k, using64k;
37
- int select, tsz, tbi;
38
+ int select, tsz, tbi, max_tsz;
39
40
if (!regime_has_2_ranges(mmu_idx)) {
41
select = 0;
42
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
43
hpd = extract64(tcr, 42, 1);
44
}
45
}
46
- tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */
47
+
48
+ if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
49
+ max_tsz = 48 - using64k;
50
+ } else {
51
+ max_tsz = 39;
52
+ }
53
+
54
+ tsz = MIN(tsz, max_tsz);
55
tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
56
57
/* Present TBI as a composite with TBID. */
58
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
59
if (!aarch64 || stride == 9) {
60
/* AArch32 or 4KB pages */
61
startlevel = 2 - sl0;
62
+
63
+ if (cpu_isar_feature(aa64_st, cpu)) {
64
+ startlevel &= 3;
65
+ }
66
} else {
67
/* 16KB or 64KB pages */
68
startlevel = 3 - sl0;
70
--
69
--
71
2.20.1
70
2.20.1
72
71
73
72
diff view generated by jsdifflib
1
From: Thomas Huth <thuth@redhat.com>
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
2
2
3
Make cpu_register() (renamed to arm_cpu_register()) available
3
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
4
from internals.h so we can register CPUs also from other files
5
in the future.
6
7
Signed-off-by: Thomas Huth <thuth@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20200423073358.27155-3-philmd@redhat.com
12
Message-ID: <20190921150420.30743-2-thuth@redhat.com>
13
[PMD: Only take cpu_register() from Thomas's patch]
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
6
---
17
target/arm/cpu-qom.h | 9 ++++++++-
7
target/arm/cpu64.c | 1 +
18
target/arm/cpu.c | 10 ++--------
8
1 file changed, 1 insertion(+)
19
target/arm/cpu64.c | 8 +-------
20
3 files changed, 11 insertions(+), 16 deletions(-)
21
9
22
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/cpu-qom.h
25
+++ b/target/arm/cpu-qom.h
26
@@ -XXX,XX +XXX,XX @@ struct arm_boot_info;
27
28
#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
29
30
-typedef struct ARMCPUInfo ARMCPUInfo;
31
+typedef struct ARMCPUInfo {
32
+ const char *name;
33
+ void (*initfn)(Object *obj);
34
+ void (*class_init)(ObjectClass *oc, void *data);
35
+} ARMCPUInfo;
36
+
37
+void arm_cpu_register(const ARMCPUInfo *info);
38
+void aarch64_cpu_register(const ARMCPUInfo *info);
39
40
/**
41
* ARMCPUClass:
42
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/cpu.c
45
+++ b/target/arm/cpu.c
46
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
47
48
#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
49
50
-struct ARMCPUInfo {
51
- const char *name;
52
- void (*initfn)(Object *obj);
53
- void (*class_init)(ObjectClass *oc, void *data);
54
-};
55
-
56
static const ARMCPUInfo arm_cpus[] = {
57
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
58
{ .name = "arm926", .initfn = arm926_initfn },
59
@@ -XXX,XX +XXX,XX @@ static void cpu_register_class_init(ObjectClass *oc, void *data)
60
acc->info = data;
61
}
62
63
-static void cpu_register(const ARMCPUInfo *info)
64
+void arm_cpu_register(const ARMCPUInfo *info)
65
{
66
TypeInfo type_info = {
67
.parent = TYPE_ARM_CPU,
68
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void)
69
type_register_static(&idau_interface_type_info);
70
71
while (info->name) {
72
- cpu_register(info);
73
+ arm_cpu_register(info);
74
info++;
75
}
76
77
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
10
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
78
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
79
--- a/target/arm/cpu64.c
12
--- a/target/arm/cpu64.c
80
+++ b/target/arm/cpu64.c
13
+++ b/target/arm/cpu64.c
81
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
14
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
82
cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
15
t = cpu->isar.id_aa64mmfr2;
83
}
16
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
84
17
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
85
-struct ARMCPUInfo {
18
+ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
86
- const char *name;
19
cpu->isar.id_aa64mmfr2 = t;
87
- void (*initfn)(Object *obj);
20
88
- void (*class_init)(ObjectClass *oc, void *data);
21
/* Replicate the same data to the 32-bit id registers. */
89
-};
90
-
91
static const ARMCPUInfo aarch64_cpus[] = {
92
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
93
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
94
@@ -XXX,XX +XXX,XX @@ static void cpu_register_class_init(ObjectClass *oc, void *data)
95
acc->info = data;
96
}
97
98
-static void aarch64_cpu_register(const ARMCPUInfo *info)
99
+void aarch64_cpu_register(const ARMCPUInfo *info)
100
{
101
TypeInfo type_info = {
102
.parent = TYPE_AARCH64_CPU,
103
--
22
--
104
2.20.1
23
2.20.1
105
24
106
25
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
3
SBSS -> SSBS
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
6
Message-id: 20200423073358.27155-4-philmd@redhat.com
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
9
Message-id: 20210108185154.8108-2-leif@nuviainc.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
11
---
9
target/arm/cpu.c | 8 +++-----
12
target/arm/cpu.h | 2 +-
10
target/arm/cpu64.c | 8 +++-----
13
1 file changed, 1 insertion(+), 1 deletion(-)
11
2 files changed, 6 insertions(+), 10 deletions(-)
12
14
13
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.c
17
--- a/target/arm/cpu.h
16
+++ b/target/arm/cpu.c
18
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {
19
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, RAS, 28, 4)
18
{ .name = "any", .initfn = arm_max_initfn },
20
FIELD(ID_AA64PFR0, SVE, 32, 4)
19
#endif
21
20
#endif
22
FIELD(ID_AA64PFR1, BT, 0, 4)
21
- { .name = NULL }
23
-FIELD(ID_AA64PFR1, SBSS, 4, 4)
22
};
24
+FIELD(ID_AA64PFR1, SSBS, 4, 4)
23
25
FIELD(ID_AA64PFR1, MTE, 8, 4)
24
static Property arm_cpu_properties[] = {
26
FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
25
@@ -XXX,XX +XXX,XX @@ static const TypeInfo idau_interface_type_info = {
26
27
static void arm_cpu_register_types(void)
28
{
29
- const ARMCPUInfo *info = arm_cpus;
30
+ size_t i;
31
32
type_register_static(&arm_cpu_type_info);
33
type_register_static(&idau_interface_type_info);
34
35
- while (info->name) {
36
- arm_cpu_register(info);
37
- info++;
38
+ for (i = 0; i < ARRAY_SIZE(arm_cpus); ++i) {
39
+ arm_cpu_register(&arm_cpus[i]);
40
}
41
42
#ifdef CONFIG_KVM
43
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/cpu64.c
46
+++ b/target/arm/cpu64.c
47
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
48
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
49
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
50
{ .name = "max", .initfn = aarch64_max_initfn },
51
- { .name = NULL }
52
};
53
54
static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
55
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aarch64_cpu_type_info = {
56
57
static void aarch64_cpu_register_types(void)
58
{
59
- const ARMCPUInfo *info = aarch64_cpus;
60
+ size_t i;
61
62
type_register_static(&aarch64_cpu_type_info);
63
64
- while (info->name) {
65
- aarch64_cpu_register(info);
66
- info++;
67
+ for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
68
+ aarch64_cpu_register(&aarch64_cpus[i]);
69
}
70
}
71
27
72
--
28
--
73
2.20.1
29
2.20.1
74
30
75
31
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
Move arm_boot_info into XlnxZCU102.
3
The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
4
32, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
5
Extend the clidr field to be able to hold this context.
4
6
7
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20200423121114.4274-4-edgar.iglesias@gmail.com
10
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Message-id: 20210108185154.8108-3-leif@nuviainc.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
13
---
10
hw/arm/xlnx-zcu102.c | 9 +++++----
14
target/arm/cpu.h | 2 +-
11
1 file changed, 5 insertions(+), 4 deletions(-)
15
1 file changed, 1 insertion(+), 1 deletion(-)
12
16
13
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/xlnx-zcu102.c
19
--- a/target/arm/cpu.h
16
+++ b/hw/arm/xlnx-zcu102.c
20
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ typedef struct XlnxZCU102 {
21
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
18
22
uint32_t id_afr0;
19
bool secure;
23
uint64_t id_aa64afr0;
20
bool virt;
24
uint64_t id_aa64afr1;
21
+
25
- uint32_t clidr;
22
+ struct arm_boot_info binfo;
26
+ uint64_t clidr;
23
} XlnxZCU102;
27
uint64_t mp_affinity; /* MP ID without feature bits */
24
28
/* The elements of this array are the CCSIDR values for each cache,
25
#define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")
29
* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
26
#define ZCU102_MACHINE(obj) \
27
OBJECT_CHECK(XlnxZCU102, (obj), TYPE_ZCU102_MACHINE)
28
29
-static struct arm_boot_info xlnx_zcu102_binfo;
30
31
static bool zcu102_get_secure(Object *obj, Error **errp)
32
{
33
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
34
35
/* TODO create and connect IDE devices for ide_drive_get() */
36
37
- xlnx_zcu102_binfo.ram_size = ram_size;
38
- xlnx_zcu102_binfo.loader_start = 0;
39
- arm_load_kernel(s->soc.boot_cpu_ptr, machine, &xlnx_zcu102_binfo);
40
+ s->binfo.ram_size = ram_size;
41
+ s->binfo.loader_start = 0;
42
+ arm_load_kernel(s->soc.boot_cpu_ptr, machine, &s->binfo);
43
}
44
45
static void xlnx_zcu102_machine_instance_init(Object *obj)
46
--
30
--
47
2.20.1
31
2.20.1
48
32
49
33
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
Make compat in qemu_fdt_node_path() const char *.
3
When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the
4
TminLine field in bits [37:32].
5
Extend the ctr field to be able to hold this context.
4
6
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
6
Message-id: 20200423121114.4274-3-edgar.iglesias@gmail.com
8
Reviewed-by: Hao Wu <wuhaotsh@google.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Message-id: 20210108185154.8108-4-leif@nuviainc.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
13
---
10
include/sysemu/device_tree.h | 2 +-
14
target/arm/cpu.h | 2 +-
11
device_tree.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
12
2 files changed, 2 insertions(+), 2 deletions(-)
13
16
14
diff --git a/include/sysemu/device_tree.h b/include/sysemu/device_tree.h
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/include/sysemu/device_tree.h
19
--- a/target/arm/cpu.h
17
+++ b/include/sysemu/device_tree.h
20
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ void *load_device_tree_from_sysfs(void);
21
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
19
* @name may be NULL to wildcard names and only match compatibility
22
uint64_t midr;
20
* strings.
23
uint32_t revidr;
21
*/
24
uint32_t reset_fpsid;
22
-char **qemu_fdt_node_path(void *fdt, const char *name, char *compat,
25
- uint32_t ctr;
23
+char **qemu_fdt_node_path(void *fdt, const char *name, const char *compat,
26
+ uint64_t ctr;
24
Error **errp);
27
uint32_t reset_sctlr;
25
28
uint64_t pmceid0;
26
/**
29
uint64_t pmceid1;
27
diff --git a/device_tree.c b/device_tree.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/device_tree.c
30
+++ b/device_tree.c
31
@@ -XXX,XX +XXX,XX @@ char **qemu_fdt_node_unit_path(void *fdt, const char *name, Error **errp)
32
return path_array;
33
}
34
35
-char **qemu_fdt_node_path(void *fdt, const char *name, char *compat,
36
+char **qemu_fdt_node_path(void *fdt, const char *name, const char *compat,
37
Error **errp)
38
{
39
int offset, len, ret;
40
--
30
--
41
2.20.1
31
2.20.1
42
32
43
33
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
Allow name wildcards in qemu_fdt_node_path(). This is useful
3
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
4
to find all nodes with a given compatibility string.
4
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
5
5
Message-id: 20210108185154.8108-5-leif@nuviainc.com
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Message-id: 20200423121114.4274-2-edgar.iglesias@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
7
---
11
include/sysemu/device_tree.h | 3 +++
8
target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++
12
device_tree.c | 2 +-
9
1 file changed, 31 insertions(+)
13
2 files changed, 4 insertions(+), 1 deletion(-)
14
10
15
diff --git a/include/sysemu/device_tree.h b/include/sysemu/device_tree.h
11
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
17
--- a/include/sysemu/device_tree.h
13
--- a/target/arm/cpu.h
18
+++ b/include/sysemu/device_tree.h
14
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ void *load_device_tree_from_sysfs(void);
15
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
20
* NULL. If there is no error but no matching node was found, the
16
/*
21
* returned array contains a single element equal to NULL. If an error
17
* System register ID fields.
22
* was encountered when parsing the blob, the function returns NULL
23
+ *
24
+ * @name may be NULL to wildcard names and only match compatibility
25
+ * strings.
26
*/
18
*/
27
char **qemu_fdt_node_path(void *fdt, const char *name, char *compat,
19
+FIELD(CLIDR_EL1, CTYPE1, 0, 3)
28
Error **errp);
20
+FIELD(CLIDR_EL1, CTYPE2, 3, 3)
29
diff --git a/device_tree.c b/device_tree.c
21
+FIELD(CLIDR_EL1, CTYPE3, 6, 3)
30
index XXXXXXX..XXXXXXX 100644
22
+FIELD(CLIDR_EL1, CTYPE4, 9, 3)
31
--- a/device_tree.c
23
+FIELD(CLIDR_EL1, CTYPE5, 12, 3)
32
+++ b/device_tree.c
24
+FIELD(CLIDR_EL1, CTYPE6, 15, 3)
33
@@ -XXX,XX +XXX,XX @@ char **qemu_fdt_node_path(void *fdt, const char *name, char *compat,
25
+FIELD(CLIDR_EL1, CTYPE7, 18, 3)
34
offset = len;
26
+FIELD(CLIDR_EL1, LOUIS, 21, 3)
35
break;
27
+FIELD(CLIDR_EL1, LOC, 24, 3)
36
}
28
+FIELD(CLIDR_EL1, LOUU, 27, 3)
37
- if (!strcmp(iter_name, name)) {
29
+FIELD(CLIDR_EL1, ICB, 30, 3)
38
+ if (!name || !strcmp(iter_name, name)) {
30
+
39
char *path;
31
+/* When FEAT_CCIDX is implemented */
40
32
+FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
41
path = g_malloc(path_len);
33
+FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
34
+FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
35
+
36
+/* When FEAT_CCIDX is not implemented */
37
+FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
38
+FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
39
+FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
40
+
41
+FIELD(CTR_EL0, IMINLINE, 0, 4)
42
+FIELD(CTR_EL0, L1IP, 14, 2)
43
+FIELD(CTR_EL0, DMINLINE, 16, 4)
44
+FIELD(CTR_EL0, ERG, 20, 4)
45
+FIELD(CTR_EL0, CWG, 24, 4)
46
+FIELD(CTR_EL0, IDC, 28, 1)
47
+FIELD(CTR_EL0, DIC, 29, 1)
48
+FIELD(CTR_EL0, TMINLINE, 32, 6)
49
+
50
FIELD(MIDR_EL1, REVISION, 0, 4)
51
FIELD(MIDR_EL1, PARTNUM, 4, 12)
52
FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
42
--
53
--
43
2.20.1
54
2.20.1
44
55
45
56
diff view generated by jsdifflib
1
From: Jerome Forissier <jerome@forissier.org>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
Generate random seeds to be used by the non-secure and/or secure OSes
3
Add entries present in ARM DDI 0487F.c (August 2020).
4
for ASLR. The seeds are 64-bit random values exported via the DT
5
properties /chosen/kaslr-seed [1] and /secure-chosen/kaslr-seed, the
6
latter being used by OP-TEE [2].
7
4
8
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e5bc0c37c97e1
5
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
9
[2] https://github.com/OP-TEE/optee_os/commit/ef262691fe0e
10
11
Signed-off-by: Jerome Forissier <jerome@forissier.org>
12
Message-id: 20200420121807.8204-3-jerome@forissier.org
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
Message-id: 20210108185154.8108-6-leif@nuviainc.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
10
---
16
hw/arm/virt.c | 15 +++++++++++++++
11
target/arm/cpu.h | 15 +++++++++++++++
17
1 file changed, 15 insertions(+)
12
1 file changed, 15 insertions(+)
18
13
19
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
20
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/virt.c
16
--- a/target/arm/cpu.h
22
+++ b/hw/arm/virt.c
17
+++ b/target/arm/cpu.h
23
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR1, GPI, 28, 4)
24
#include "hw/acpi/generic_event_device.h"
19
FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
25
#include "hw/virtio/virtio-iommu.h"
20
FIELD(ID_AA64ISAR1, SB, 36, 4)
26
#include "hw/char/pl011.h"
21
FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
27
+#include "qemu/guest-random.h"
22
+FIELD(ID_AA64ISAR1, BF16, 44, 4)
28
23
+FIELD(ID_AA64ISAR1, DGH, 48, 4)
29
#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
24
+FIELD(ID_AA64ISAR1, I8MM, 52, 4)
30
static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
25
31
@@ -XXX,XX +XXX,XX @@ static bool cpu_type_valid(const char *cpu)
26
FIELD(ID_AA64PFR0, EL0, 0, 4)
32
return false;
27
FIELD(ID_AA64PFR0, EL1, 4, 4)
33
}
28
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
34
29
FIELD(ID_AA64PFR0, GIC, 24, 4)
35
+static void create_kaslr_seed(VirtMachineState *vms, const char *node)
30
FIELD(ID_AA64PFR0, RAS, 28, 4)
36
+{
31
FIELD(ID_AA64PFR0, SVE, 32, 4)
37
+ Error *err = NULL;
32
+FIELD(ID_AA64PFR0, SEL2, 36, 4)
38
+ uint64_t seed;
33
+FIELD(ID_AA64PFR0, MPAM, 40, 4)
39
+
34
+FIELD(ID_AA64PFR0, AMU, 44, 4)
40
+ if (qemu_guest_getrandom(&seed, sizeof(seed), &err)) {
35
+FIELD(ID_AA64PFR0, DIT, 48, 4)
41
+ error_free(err);
36
+FIELD(ID_AA64PFR0, CSV2, 56, 4)
42
+ return;
37
+FIELD(ID_AA64PFR0, CSV3, 60, 4)
43
+ }
38
44
+ qemu_fdt_setprop_u64(vms->fdt, node, "kaslr-seed", seed);
39
FIELD(ID_AA64PFR1, BT, 0, 4)
45
+}
40
FIELD(ID_AA64PFR1, SSBS, 4, 4)
46
+
41
FIELD(ID_AA64PFR1, MTE, 8, 4)
47
static void create_fdt(VirtMachineState *vms)
42
FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
48
{
43
+FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
49
MachineState *ms = MACHINE(vms);
44
50
@@ -XXX,XX +XXX,XX @@ static void create_fdt(VirtMachineState *vms)
45
FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
51
46
FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
52
/* /chosen must exist for load_dtb to fill in necessary properties later */
47
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
53
qemu_fdt_add_subnode(fdt, "/chosen");
48
FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
54
+ create_kaslr_seed(vms, "/chosen");
49
FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
55
50
FIELD(ID_AA64MMFR0, EXS, 44, 4)
56
if (vms->secure) {
51
+FIELD(ID_AA64MMFR0, FGT, 56, 4)
57
qemu_fdt_add_subnode(fdt, "/secure-chosen");
52
+FIELD(ID_AA64MMFR0, ECV, 60, 4)
58
+ create_kaslr_seed(vms, "/secure-chosen");
53
59
}
54
FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
60
55
FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
61
/* Clock node, for the benefit of the UART. The kernel device tree
56
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, LO, 16, 4)
57
FIELD(ID_AA64MMFR1, PAN, 20, 4)
58
FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
59
FIELD(ID_AA64MMFR1, XNX, 28, 4)
60
+FIELD(ID_AA64MMFR1, TWED, 32, 4)
61
+FIELD(ID_AA64MMFR1, ETS, 36, 4)
62
63
FIELD(ID_AA64MMFR2, CNP, 0, 4)
64
FIELD(ID_AA64MMFR2, UAO, 4, 4)
65
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
66
FIELD(ID_AA64DFR0, PMSVER, 32, 4)
67
FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
68
FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
69
+FIELD(ID_AA64DFR0, MTPMU, 48, 4)
70
71
FIELD(ID_DFR0, COPDBG, 0, 4)
72
FIELD(ID_DFR0, COPSDBG, 4, 4)
62
--
73
--
63
2.20.1
74
2.20.1
64
75
65
76
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
We will move this code in the next commit. Clean it up
3
Add entries present in ARM DDI 0487F.c (August 2020).
4
first to avoid checkpatch.pl errors.
5
4
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20200423073358.27155-5-philmd@redhat.com
7
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
Message-id: 20210108185154.8108-7-leif@nuviainc.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/cpu.c | 9 ++++++---
11
target/arm/cpu.h | 28 ++++++++++++++++++++++++++++
12
1 file changed, 6 insertions(+), 3 deletions(-)
12
1 file changed, 28 insertions(+)
13
13
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
16
--- a/target/arm/cpu.h
17
+++ b/target/arm/cpu.c
17
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
18
@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, DP, 4, 4)
19
CPUARMState *env = &cpu->env;
19
FIELD(ID_ISAR6, FHM, 8, 4)
20
bool ret = false;
20
FIELD(ID_ISAR6, SB, 12, 4)
21
21
FIELD(ID_ISAR6, SPECRES, 16, 4)
22
- /* ARMv7-M interrupt masking works differently than -A or -R.
22
+FIELD(ID_ISAR6, BF16, 20, 4)
23
+ /*
23
+FIELD(ID_ISAR6, I8MM, 24, 4)
24
+ * ARMv7-M interrupt masking works differently than -A or -R.
24
25
* There is no FIQ/IRQ distinction. Instead of I and F bits
25
FIELD(ID_MMFR0, VMSA, 0, 4)
26
* masking FIQ and IRQ interrupts, an exception is taken only
26
FIELD(ID_MMFR0, PMSA, 4, 4)
27
* if it is higher priority than the current execution priority
27
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR0, AUXREG, 20, 4)
28
@@ -XXX,XX +XXX,XX @@ static void arm1026_initfn(Object *obj)
28
FIELD(ID_MMFR0, FCSE, 24, 4)
29
static void arm1136_r2_initfn(Object *obj)
29
FIELD(ID_MMFR0, INNERSHR, 28, 4)
30
{
30
31
ARMCPU *cpu = ARM_CPU(obj);
31
+FIELD(ID_MMFR1, L1HVDVA, 0, 4)
32
- /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
32
+FIELD(ID_MMFR1, L1UNIVA, 4, 4)
33
+ /*
33
+FIELD(ID_MMFR1, L1HVDSW, 8, 4)
34
+ * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
34
+FIELD(ID_MMFR1, L1UNISW, 12, 4)
35
* older core than plain "arm1136". In particular this does not
35
+FIELD(ID_MMFR1, L1HVD, 16, 4)
36
* have the v6K features.
36
+FIELD(ID_MMFR1, L1UNI, 20, 4)
37
* These ID register values are correct for 1136 but may be wrong
37
+FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
38
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {
38
+FIELD(ID_MMFR1, BPRED, 28, 4)
39
{ .name = "arm926", .initfn = arm926_initfn },
39
+
40
{ .name = "arm946", .initfn = arm946_initfn },
40
+FIELD(ID_MMFR2, L1HVDFG, 0, 4)
41
{ .name = "arm1026", .initfn = arm1026_initfn },
41
+FIELD(ID_MMFR2, L1HVDBG, 4, 4)
42
- /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
42
+FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
43
+ /*
43
+FIELD(ID_MMFR2, HVDTLB, 12, 4)
44
+ * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
44
+FIELD(ID_MMFR2, UNITLB, 16, 4)
45
* older core than plain "arm1136". In particular this does not
45
+FIELD(ID_MMFR2, MEMBARR, 20, 4)
46
* have the v6K features.
46
+FIELD(ID_MMFR2, WFISTALL, 24, 4)
47
*/
47
+FIELD(ID_MMFR2, HWACCFLG, 28, 4)
48
+
49
FIELD(ID_MMFR3, CMAINTVA, 0, 4)
50
FIELD(ID_MMFR3, CMAINTSW, 4, 4)
51
FIELD(ID_MMFR3, BPMAINT, 8, 4)
52
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
53
FIELD(ID_MMFR4, CCIDX, 24, 4)
54
FIELD(ID_MMFR4, EVT, 28, 4)
55
56
+FIELD(ID_MMFR5, ETS, 0, 4)
57
+
58
FIELD(ID_PFR0, STATE0, 0, 4)
59
FIELD(ID_PFR0, STATE1, 4, 4)
60
FIELD(ID_PFR0, STATE2, 8, 4)
61
@@ -XXX,XX +XXX,XX @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4)
62
FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
63
FIELD(ID_PFR1, GIC, 28, 4)
64
65
+FIELD(ID_PFR2, CSV3, 0, 4)
66
+FIELD(ID_PFR2, SSBS, 4, 4)
67
+FIELD(ID_PFR2, RAS_FRAC, 8, 4)
68
+
69
FIELD(ID_AA64ISAR0, AES, 4, 4)
70
FIELD(ID_AA64ISAR0, SHA1, 8, 4)
71
FIELD(ID_AA64ISAR0, SHA2, 12, 4)
72
@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
73
FIELD(ID_DFR0, PERFMON, 24, 4)
74
FIELD(ID_DFR0, TRACEFILT, 28, 4)
75
76
+FIELD(ID_DFR1, MTPMU, 0, 4)
77
+
78
FIELD(DBGDIDR, SE_IMP, 12, 1)
79
FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
80
FIELD(DBGDIDR, VERSION, 16, 4)
48
--
81
--
49
2.20.1
82
2.20.1
50
83
51
84
diff view generated by jsdifflib
1
From: Keqian Zhu <zhukeqian1@huawei.com>
1
From: Roman Bolshakov <r.bolshakov@yadro.com>
2
2
3
Replace "acpi-mem-hotplug" with "acpi-cpu-hotplug"
3
QEMU documentation can't be opened if QEMU is run from build tree
4
because executables are placed in the top of build tree after conversion
5
to meson.
4
6
5
Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
7
Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
6
Message-id: 20200413091552.62748-4-zhukeqian1@huawei.com
8
Reported-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20210108213815.64678-1-r.bolshakov@yadro.com
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
hw/acpi/cpu.c | 2 +-
13
ui/cocoa.m | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
12
15
13
diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
16
diff --git a/ui/cocoa.m b/ui/cocoa.m
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/acpi/cpu.c
18
--- a/ui/cocoa.m
16
+++ b/hw/acpi/cpu.c
19
+++ b/ui/cocoa.m
17
@@ -XXX,XX +XXX,XX @@ void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner,
20
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
18
state->devs[i].arch_id = id_list->cpus[i].arch_id;
21
- (void) openDocumentation: (NSString *) filename
19
}
22
{
20
memory_region_init_io(&state->ctrl_reg, owner, &cpu_hotplug_ops, state,
23
/* Where to look for local files */
21
- "acpi-mem-hotplug", ACPI_CPU_HOTPLUG_REG_LEN);
24
- NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"../docs/"};
22
+ "acpi-cpu-hotplug", ACPI_CPU_HOTPLUG_REG_LEN);
25
+ NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
23
memory_region_add_subregion(as, base_addr, &state->ctrl_reg);
26
NSString *full_file_path;
24
}
27
25
28
/* iterate thru the possible paths until the file is found */
26
--
29
--
27
2.20.1
30
2.20.1
28
31
29
32
diff view generated by jsdifflib
1
From: Ramon Fried <rfried.dev@gmail.com>
1
In commit 1982e1602d15 we added a new qemu-storage-daemon(1) manpage.
2
At the moment new manpages have to be listed both in the conf.py for
3
Sphinx and also in docs/meson.build for Meson. We forgot the second
4
of those -- correct the omission.
2
5
3
The RX ring descriptors control field is used for setting
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
SOF and EOF (start of frame and end of frame).
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
The SOF and EOF weren't cleared from the previous descriptors,
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
causing inconsistencies in ring buffer.
9
Message-id: 20210108161416.21129-2-peter.maydell@linaro.org
7
Fix that by clearing the control field of every descriptors we're
10
---
8
processing.
11
docs/meson.build | 1 +
12
1 file changed, 1 insertion(+)
9
13
10
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
14
diff --git a/docs/meson.build b/docs/meson.build
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
13
Message-id: 20200418085145.489726-1-rfried.dev@gmail.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/net/cadence_gem.c | 7 +++++++
17
1 file changed, 7 insertions(+)
18
19
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
20
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/net/cadence_gem.c
16
--- a/docs/meson.build
22
+++ b/hw/net/cadence_gem.c
17
+++ b/docs/meson.build
23
@@ -XXX,XX +XXX,XX @@ static inline void rx_desc_set_sof(uint32_t *desc)
18
@@ -XXX,XX +XXX,XX @@ if build_docs
24
desc[1] |= DESC_1_RX_SOF;
19
'qemu-img.1': (have_tools ? 'man1' : ''),
25
}
20
'qemu-nbd.8': (have_tools ? 'man8' : ''),
26
21
'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
27
+static inline void rx_desc_clear_control(uint32_t *desc)
22
+ 'qemu-storage-daemon.1': (have_tools ? 'man1' : ''),
28
+{
23
'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
29
+ desc[1] = 0;
24
'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
30
+}
25
'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
31
+
32
static inline void rx_desc_set_eof(uint32_t *desc)
33
{
34
desc[1] |= DESC_1_RX_EOF;
35
@@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
36
rxbuf_ptr += MIN(bytes_to_copy, rxbufsize);
37
bytes_to_copy -= MIN(bytes_to_copy, rxbufsize);
38
39
+ rx_desc_clear_control(s->rx_desc[q]);
40
+
41
/* Update the descriptor. */
42
if (first_desc) {
43
rx_desc_set_sof(s->rx_desc[q]);
44
--
26
--
45
2.20.1
27
2.20.1
46
28
47
29
diff view generated by jsdifflib
1
From: Ramon Fried <rfried.dev@gmail.com>
1
When we first converted our documentation to Sphinx, we split it into
2
2
multiple manuals (system, interop, tools, etc), which are all built
3
Wraparound of TX descriptor cyclic buffer only updated
3
separately. The primary driver for this was wanting to be able to
4
the low 32 bits of the descriptor.
4
avoid shipping the 'devel' manual to end-users. However, this is
5
Fix that by checking if we're working with 64bit descriptors.
5
working against the grain of the way Sphinx wants to be used and
6
6
causes some annoyances:
7
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
7
* Cross-references between documents become much harder or
8
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
possibly impossible
9
Message-id: 20200417171736.441607-1-rfried.dev@gmail.com
9
* There is no single index to the whole documentation
10
* Within one manual there's no links or table-of-contents info
11
that lets you easily navigate to the others
12
* The devel manual doesn't get published on the QEMU website
13
(it would be nice to able to refer to it there)
14
15
Merely hiding our developer documentation from end users seems like
16
it's not enough benefit for these costs. Combine all the
17
documentation into a single manual (the same way that the readthedocs
18
site builds it) and install the whole thing. The previous manual
19
divisions remain as the new top level sections in the manual.
20
21
* The per-manual conf.py files are no longer needed
22
* The man_pages[] specifications previously in each per-manual
23
conf.py move to the top level conf.py
24
* docs/meson.build logic is simplified as we now only need to run
25
Sphinx once for the HTML and then once for the manpages5B
26
* The old index.html.in that produced the top-level page with
27
links to each manual is no longer needed
28
29
Unfortunately this means that we now have to build the HTML
30
documentation into docs/manual in the build tree rather than directly
31
into docs/; otherwise it is too awkward to ensure we install only the
32
built manual and not also the dependency info, stamp file, etc. The
33
manual still ends up in the same place in the final installed
34
directory, but anybody who was consulting documentation from within
35
the build tree will have to adjust where they're looking.
36
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
37
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
38
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
39
Message-id: 20210108161416.21129-3-peter.maydell@linaro.org
11
---
40
---
12
hw/net/cadence_gem.c | 9 ++++++++-
41
docs/conf.py | 46 ++++++++++++++++++++++++++++++-
13
1 file changed, 8 insertions(+), 1 deletion(-)
42
docs/devel/conf.py | 15 -----------
14
43
docs/index.html.in | 17 ------------
15
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
44
docs/interop/conf.py | 28 -------------------
45
docs/meson.build | 64 +++++++++++++++++---------------------------
46
docs/specs/conf.py | 16 -----------
47
docs/system/conf.py | 28 -------------------
48
docs/tools/conf.py | 37 -------------------------
49
docs/user/conf.py | 15 -----------
50
9 files changed, 70 insertions(+), 196 deletions(-)
51
delete mode 100644 docs/devel/conf.py
52
delete mode 100644 docs/index.html.in
53
delete mode 100644 docs/interop/conf.py
54
delete mode 100644 docs/specs/conf.py
55
delete mode 100644 docs/system/conf.py
56
delete mode 100644 docs/tools/conf.py
57
delete mode 100644 docs/user/conf.py
58
59
diff --git a/docs/conf.py b/docs/conf.py
16
index XXXXXXX..XXXXXXX 100644
60
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/net/cadence_gem.c
61
--- a/docs/conf.py
18
+++ b/hw/net/cadence_gem.c
62
+++ b/docs/conf.py
19
@@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s)
63
@@ -XXX,XX +XXX,XX @@ latex_documents = [
20
/* read next descriptor */
64
21
if (tx_desc_get_wrap(desc)) {
65
# -- Options for manual page output ---------------------------------------
22
tx_desc_set_last(desc);
66
# Individual manual/conf.py can override this to create man pages
23
- packet_desc_addr = s->regs[GEM_TXQBASE];
67
-man_pages = []
68
+man_pages = [
69
+ ('interop/qemu-ga', 'qemu-ga',
70
+ 'QEMU Guest Agent',
71
+ ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
72
+ ('interop/qemu-ga-ref', 'qemu-ga-ref',
73
+ 'QEMU Guest Agent Protocol Reference',
74
+ [], 7),
75
+ ('interop/qemu-qmp-ref', 'qemu-qmp-ref',
76
+ 'QEMU QMP Reference Manual',
77
+ [], 7),
78
+ ('interop/qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
79
+ 'QEMU Storage Daemon QMP Reference Manual',
80
+ [], 7),
81
+ ('system/qemu-manpage', 'qemu',
82
+ 'QEMU User Documentation',
83
+ ['Fabrice Bellard'], 1),
84
+ ('system/qemu-block-drivers', 'qemu-block-drivers',
85
+ 'QEMU block drivers reference',
86
+ ['Fabrice Bellard and the QEMU Project developers'], 7),
87
+ ('system/qemu-cpu-models', 'qemu-cpu-models',
88
+ 'QEMU CPU Models',
89
+ ['The QEMU Project developers'], 7),
90
+ ('tools/qemu-img', 'qemu-img',
91
+ 'QEMU disk image utility',
92
+ ['Fabrice Bellard'], 1),
93
+ ('tools/qemu-nbd', 'qemu-nbd',
94
+ 'QEMU Disk Network Block Device Server',
95
+ ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
96
+ ('tools/qemu-pr-helper', 'qemu-pr-helper',
97
+ 'QEMU persistent reservation helper',
98
+ [], 8),
99
+ ('tools/qemu-storage-daemon', 'qemu-storage-daemon',
100
+ 'QEMU storage daemon',
101
+ [], 1),
102
+ ('tools/qemu-trace-stap', 'qemu-trace-stap',
103
+ 'QEMU SystemTap trace tool',
104
+ [], 1),
105
+ ('tools/virtfs-proxy-helper', 'virtfs-proxy-helper',
106
+ 'QEMU 9p virtfs proxy filesystem helper',
107
+ ['M. Mohan Kumar'], 1),
108
+ ('tools/virtiofsd', 'virtiofsd',
109
+ 'QEMU virtio-fs shared file system daemon',
110
+ ['Stefan Hajnoczi <stefanha@redhat.com>',
111
+ 'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
112
+]
113
114
# -- Options for Texinfo output -------------------------------------------
115
116
diff --git a/docs/devel/conf.py b/docs/devel/conf.py
117
deleted file mode 100644
118
index XXXXXXX..XXXXXXX
119
--- a/docs/devel/conf.py
120
+++ /dev/null
121
@@ -XXX,XX +XXX,XX @@
122
-# -*- coding: utf-8 -*-
123
-#
124
-# QEMU documentation build configuration file for the 'devel' manual.
125
-#
126
-# This includes the top level conf file and then makes any necessary tweaks.
127
-import sys
128
-import os
129
-
130
-qemu_docdir = os.path.abspath("..")
131
-parent_config = os.path.join(qemu_docdir, "conf.py")
132
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
133
-
134
-# This slightly misuses the 'description', but is the best way to get
135
-# the manual title to appear in the sidebar.
136
-html_theme_options['description'] = u'Developer''s Guide'
137
diff --git a/docs/index.html.in b/docs/index.html.in
138
deleted file mode 100644
139
index XXXXXXX..XXXXXXX
140
--- a/docs/index.html.in
141
+++ /dev/null
142
@@ -XXX,XX +XXX,XX @@
143
-<!DOCTYPE html>
144
-<html lang="en">
145
- <head>
146
- <meta charset="UTF-8">
147
- <title>QEMU @VERSION@ Documentation</title>
148
- </head>
149
- <body>
150
- <h1>QEMU @VERSION@ Documentation</h1>
151
- <ul>
152
- <li><a href="system/index.html">System Emulation User's Guide</a></li>
153
- <li><a href="user/index.html">User Mode Emulation User's Guide</a></li>
154
- <li><a href="tools/index.html">Tools Guide</a></li>
155
- <li><a href="interop/index.html">System Emulation Management and Interoperability Guide</a></li>
156
- <li><a href="specs/index.html">System Emulation Guest Hardware Specifications</a></li>
157
- </ul>
158
- </body>
159
-</html>
160
diff --git a/docs/interop/conf.py b/docs/interop/conf.py
161
deleted file mode 100644
162
index XXXXXXX..XXXXXXX
163
--- a/docs/interop/conf.py
164
+++ /dev/null
165
@@ -XXX,XX +XXX,XX @@
166
-# -*- coding: utf-8 -*-
167
-#
168
-# QEMU documentation build configuration file for the 'interop' manual.
169
-#
170
-# This includes the top level conf file and then makes any necessary tweaks.
171
-import sys
172
-import os
173
-
174
-qemu_docdir = os.path.abspath("..")
175
-parent_config = os.path.join(qemu_docdir, "conf.py")
176
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
177
-
178
-# This slightly misuses the 'description', but is the best way to get
179
-# the manual title to appear in the sidebar.
180
-html_theme_options['description'] = u'System Emulation Management and Interoperability Guide'
181
-
182
-# One entry per manual page. List of tuples
183
-# (source start file, name, description, authors, manual section).
184
-man_pages = [
185
- ('qemu-ga', 'qemu-ga', u'QEMU Guest Agent',
186
- ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
187
- ('qemu-ga-ref', 'qemu-ga-ref', 'QEMU Guest Agent Protocol Reference',
188
- [], 7),
189
- ('qemu-qmp-ref', 'qemu-qmp-ref', 'QEMU QMP Reference Manual',
190
- [], 7),
191
- ('qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
192
- 'QEMU Storage Daemon QMP Reference Manual', [], 7),
193
-]
194
diff --git a/docs/meson.build b/docs/meson.build
195
index XXXXXXX..XXXXXXX 100644
196
--- a/docs/meson.build
197
+++ b/docs/meson.build
198
@@ -XXX,XX +XXX,XX @@ if build_docs
199
meson.source_root() / 'docs/sphinx/qmp_lexer.py',
200
qapi_gen_depends ]
201
202
- configure_file(output: 'index.html',
203
- input: files('index.html.in'),
204
- configuration: {'VERSION': meson.project_version()},
205
- install_dir: qemu_docdir)
206
- manuals = [ 'devel', 'interop', 'tools', 'specs', 'system', 'user' ]
207
man_pages = {
208
- 'interop' : {
209
'qemu-ga.8': (have_tools ? 'man8' : ''),
210
'qemu-ga-ref.7': 'man7',
211
'qemu-qmp-ref.7': 'man7',
212
'qemu-storage-daemon-qmp-ref.7': (have_tools ? 'man7' : ''),
213
- },
214
- 'tools': {
215
'qemu-img.1': (have_tools ? 'man1' : ''),
216
'qemu-nbd.8': (have_tools ? 'man8' : ''),
217
'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
218
@@ -XXX,XX +XXX,XX @@ if build_docs
219
'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
220
'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
221
'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
222
- },
223
- 'system': {
224
'qemu.1': 'man1',
225
'qemu-block-drivers.7': 'man7',
226
'qemu-cpu-models.7': 'man7'
227
- },
228
}
229
230
sphinxdocs = []
231
sphinxmans = []
232
- foreach manual : manuals
233
- private_dir = meson.current_build_dir() / (manual + '.p')
234
- output_dir = meson.current_build_dir() / manual
235
- input_dir = meson.current_source_dir() / manual
236
237
- this_manual = custom_target(manual + ' manual',
238
+ private_dir = meson.current_build_dir() / 'manual.p'
239
+ output_dir = meson.current_build_dir() / 'manual'
240
+ input_dir = meson.current_source_dir()
24
+
241
+
25
+ if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
242
+ this_manual = custom_target('QEMU manual',
26
+ packet_desc_addr = s->regs[GEM_TBQPH];
243
build_by_default: build_docs,
27
+ packet_desc_addr <<= 32;
244
- output: [manual + '.stamp'],
28
+ } else {
245
- input: [files('conf.py'), files(manual / 'conf.py')],
29
+ packet_desc_addr = 0;
246
- depfile: manual + '.d',
30
+ }
247
+ output: 'docs.stamp',
31
+ packet_desc_addr |= s->regs[GEM_TXQBASE];
248
+ input: files('conf.py'),
32
} else {
249
+ depfile: 'docs.d',
33
packet_desc_addr += 4 * gem_get_desc_len(s, false);
250
depend_files: sphinx_extn_depends,
34
}
251
command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@',
252
'-Ddepfile_stamp=@OUTPUT0@',
253
'-b', 'html', '-d', private_dir,
254
input_dir, output_dir])
255
- sphinxdocs += this_manual
256
- if build_docs and manual != 'devel'
257
- install_subdir(output_dir, install_dir: qemu_docdir)
258
- endif
259
+ sphinxdocs += this_manual
260
+ install_subdir(output_dir, install_dir: qemu_docdir, strip_directory: true)
261
262
- these_man_pages = []
263
- install_dirs = []
264
- foreach page, section : man_pages.get(manual, {})
265
- these_man_pages += page
266
- install_dirs += section == '' ? false : get_option('mandir') / section
267
- endforeach
268
- if these_man_pages.length() > 0
269
- sphinxmans += custom_target(manual + ' man pages',
270
- build_by_default: build_docs,
271
- output: these_man_pages,
272
- input: this_manual,
273
- install: build_docs,
274
- install_dir: install_dirs,
275
- command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
276
- input_dir, meson.current_build_dir()])
277
- endif
278
+ these_man_pages = []
279
+ install_dirs = []
280
+ foreach page, section : man_pages
281
+ these_man_pages += page
282
+ install_dirs += section == '' ? false : get_option('mandir') / section
283
endforeach
284
+
285
+ sphinxmans += custom_target('QEMU man pages',
286
+ build_by_default: build_docs,
287
+ output: these_man_pages,
288
+ input: this_manual,
289
+ install: build_docs,
290
+ install_dir: install_dirs,
291
+ command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
292
+ input_dir, meson.current_build_dir()])
293
+
294
alias_target('sphinxdocs', sphinxdocs)
295
alias_target('html', sphinxdocs)
296
alias_target('man', sphinxmans)
297
diff --git a/docs/specs/conf.py b/docs/specs/conf.py
298
deleted file mode 100644
299
index XXXXXXX..XXXXXXX
300
--- a/docs/specs/conf.py
301
+++ /dev/null
302
@@ -XXX,XX +XXX,XX @@
303
-# -*- coding: utf-8 -*-
304
-#
305
-# QEMU documentation build configuration file for the 'specs' manual.
306
-#
307
-# This includes the top level conf file and then makes any necessary tweaks.
308
-import sys
309
-import os
310
-
311
-qemu_docdir = os.path.abspath("..")
312
-parent_config = os.path.join(qemu_docdir, "conf.py")
313
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
314
-
315
-# This slightly misuses the 'description', but is the best way to get
316
-# the manual title to appear in the sidebar.
317
-html_theme_options['description'] = \
318
- u'System Emulation Guest Hardware Specifications'
319
diff --git a/docs/system/conf.py b/docs/system/conf.py
320
deleted file mode 100644
321
index XXXXXXX..XXXXXXX
322
--- a/docs/system/conf.py
323
+++ /dev/null
324
@@ -XXX,XX +XXX,XX @@
325
-# -*- coding: utf-8 -*-
326
-#
327
-# QEMU documentation build configuration file for the 'system' manual.
328
-#
329
-# This includes the top level conf file and then makes any necessary tweaks.
330
-import sys
331
-import os
332
-
333
-qemu_docdir = os.path.abspath("..")
334
-parent_config = os.path.join(qemu_docdir, "conf.py")
335
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
336
-
337
-# This slightly misuses the 'description', but is the best way to get
338
-# the manual title to appear in the sidebar.
339
-html_theme_options['description'] = u'System Emulation User''s Guide'
340
-
341
-# One entry per manual page. List of tuples
342
-# (source start file, name, description, authors, manual section).
343
-man_pages = [
344
- ('qemu-manpage', 'qemu', u'QEMU User Documentation',
345
- ['Fabrice Bellard'], 1),
346
- ('qemu-block-drivers', 'qemu-block-drivers',
347
- u'QEMU block drivers reference',
348
- ['Fabrice Bellard and the QEMU Project developers'], 7),
349
- ('qemu-cpu-models', 'qemu-cpu-models',
350
- u'QEMU CPU Models',
351
- ['The QEMU Project developers'], 7)
352
-]
353
diff --git a/docs/tools/conf.py b/docs/tools/conf.py
354
deleted file mode 100644
355
index XXXXXXX..XXXXXXX
356
--- a/docs/tools/conf.py
357
+++ /dev/null
358
@@ -XXX,XX +XXX,XX @@
359
-# -*- coding: utf-8 -*-
360
-#
361
-# QEMU documentation build configuration file for the 'tools' manual.
362
-#
363
-# This includes the top level conf file and then makes any necessary tweaks.
364
-import sys
365
-import os
366
-
367
-qemu_docdir = os.path.abspath("..")
368
-parent_config = os.path.join(qemu_docdir, "conf.py")
369
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
370
-
371
-# This slightly misuses the 'description', but is the best way to get
372
-# the manual title to appear in the sidebar.
373
-html_theme_options['description'] = \
374
- u'Tools Guide'
375
-
376
-# One entry per manual page. List of tuples
377
-# (source start file, name, description, authors, manual section).
378
-man_pages = [
379
- ('qemu-img', 'qemu-img', u'QEMU disk image utility',
380
- ['Fabrice Bellard'], 1),
381
- ('qemu-storage-daemon', 'qemu-storage-daemon', u'QEMU storage daemon',
382
- [], 1),
383
- ('qemu-nbd', 'qemu-nbd', u'QEMU Disk Network Block Device Server',
384
- ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
385
- ('qemu-pr-helper', 'qemu-pr-helper', 'QEMU persistent reservation helper',
386
- [], 8),
387
- ('qemu-trace-stap', 'qemu-trace-stap', u'QEMU SystemTap trace tool',
388
- [], 1),
389
- ('virtfs-proxy-helper', 'virtfs-proxy-helper',
390
- u'QEMU 9p virtfs proxy filesystem helper',
391
- ['M. Mohan Kumar'], 1),
392
- ('virtiofsd', 'virtiofsd', u'QEMU virtio-fs shared file system daemon',
393
- ['Stefan Hajnoczi <stefanha@redhat.com>',
394
- 'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
395
-]
396
diff --git a/docs/user/conf.py b/docs/user/conf.py
397
deleted file mode 100644
398
index XXXXXXX..XXXXXXX
399
--- a/docs/user/conf.py
400
+++ /dev/null
401
@@ -XXX,XX +XXX,XX @@
402
-# -*- coding: utf-8 -*-
403
-#
404
-# QEMU documentation build configuration file for the 'user' manual.
405
-#
406
-# This includes the top level conf file and then makes any necessary tweaks.
407
-import sys
408
-import os
409
-
410
-qemu_docdir = os.path.abspath("..")
411
-parent_config = os.path.join(qemu_docdir, "conf.py")
412
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
413
-
414
-# This slightly misuses the 'description', but is the best way to get
415
-# the manual title to appear in the sidebar.
416
-html_theme_options['description'] = u'User Mode Emulation User''s Guide'
35
--
417
--
36
2.20.1
418
2.20.1
37
419
38
420
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In commit cd8be50e58f63413c0 we converted the A32 coprocessor
2
insns to decodetree. This accidentally broke XScale/iWMMXt insns,
3
because it moved the handling of "cp insns which are handled
4
by looking up the cp register in the hashtable" from after the
5
call to the legacy disas_xscale_insn() decode to before it,
6
with the result that all XScale/iWMMXt insns now UNDEF.
2
7
3
These instructions are often used in glibc's string routines.
8
Update valid_cp() so that it knows that on XScale cp 0 and 1
4
They were the final uses of the 32-bit at a time neon helpers.
9
are not standard coprocessor instructions; this will cause
10
the decodetree trans_ functions to ignore them, so that
11
execution will correctly get through to the legacy decode again.
5
12
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Cc: qemu-stable@nongnu.org
7
Message-id: 20200418162808.4680-1-richard.henderson@linaro.org
14
Reported-by: Guenter Roeck <linux@roeck-us.net>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Tested-by: Guenter Roeck <linux@roeck-us.net>
18
Message-id: 20210108195157.32067-1-peter.maydell@linaro.org
10
---
19
---
11
target/arm/helper.h | 27 ++--
20
target/arm/translate.c | 7 +++++++
12
target/arm/translate.h | 5 +
21
1 file changed, 7 insertions(+)
13
target/arm/neon_helper.c | 24 ----
14
target/arm/translate-a64.c | 64 +++-------
15
target/arm/translate.c | 256 +++++++++++++++++++++++++++++++------
16
target/arm/vec_helper.c | 25 ++++
17
6 files changed, 278 insertions(+), 123 deletions(-)
18
22
19
diff --git a/target/arm/helper.h b/target/arm/helper.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper.h
22
+++ b/target/arm/helper.h
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(neon_hsub_u16, i32, i32, i32)
24
DEF_HELPER_2(neon_hsub_s32, s32, s32, s32)
25
DEF_HELPER_2(neon_hsub_u32, i32, i32, i32)
26
27
-DEF_HELPER_2(neon_cgt_u8, i32, i32, i32)
28
-DEF_HELPER_2(neon_cgt_s8, i32, i32, i32)
29
-DEF_HELPER_2(neon_cgt_u16, i32, i32, i32)
30
-DEF_HELPER_2(neon_cgt_s16, i32, i32, i32)
31
-DEF_HELPER_2(neon_cgt_u32, i32, i32, i32)
32
-DEF_HELPER_2(neon_cgt_s32, i32, i32, i32)
33
-DEF_HELPER_2(neon_cge_u8, i32, i32, i32)
34
-DEF_HELPER_2(neon_cge_s8, i32, i32, i32)
35
-DEF_HELPER_2(neon_cge_u16, i32, i32, i32)
36
-DEF_HELPER_2(neon_cge_s16, i32, i32, i32)
37
-DEF_HELPER_2(neon_cge_u32, i32, i32, i32)
38
-DEF_HELPER_2(neon_cge_s32, i32, i32, i32)
39
-
40
DEF_HELPER_2(neon_pmin_u8, i32, i32, i32)
41
DEF_HELPER_2(neon_pmin_s8, i32, i32, i32)
42
DEF_HELPER_2(neon_pmin_u16, i32, i32, i32)
43
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(neon_mul_u16, i32, i32, i32)
44
DEF_HELPER_2(neon_tst_u8, i32, i32, i32)
45
DEF_HELPER_2(neon_tst_u16, i32, i32, i32)
46
DEF_HELPER_2(neon_tst_u32, i32, i32, i32)
47
-DEF_HELPER_2(neon_ceq_u8, i32, i32, i32)
48
-DEF_HELPER_2(neon_ceq_u16, i32, i32, i32)
49
-DEF_HELPER_2(neon_ceq_u32, i32, i32, i32)
50
51
DEF_HELPER_1(neon_clz_u8, i32, i32)
52
DEF_HELPER_1(neon_clz_u16, i32, i32)
53
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, ptr)
54
DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr)
55
DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr)
56
57
+DEF_HELPER_FLAGS_3(gvec_ceq0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
58
+DEF_HELPER_FLAGS_3(gvec_ceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
59
+DEF_HELPER_FLAGS_3(gvec_clt0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
60
+DEF_HELPER_FLAGS_3(gvec_clt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
61
+DEF_HELPER_FLAGS_3(gvec_cle0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
62
+DEF_HELPER_FLAGS_3(gvec_cle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
63
+DEF_HELPER_FLAGS_3(gvec_cgt0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
64
+DEF_HELPER_FLAGS_3(gvec_cgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
65
+DEF_HELPER_FLAGS_3(gvec_cge0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
66
+DEF_HELPER_FLAGS_3(gvec_cge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
67
+
68
DEF_HELPER_FLAGS_4(gvec_sshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
69
DEF_HELPER_FLAGS_4(gvec_sshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
70
DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
71
diff --git a/target/arm/translate.h b/target/arm/translate.h
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/translate.h
74
+++ b/target/arm/translate.h
75
@@ -XXX,XX +XXX,XX @@ static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
76
uint64_t vfp_expand_imm(int size, uint8_t imm8);
77
78
/* Vector operations shared between ARM and AArch64. */
79
+extern const GVecGen2 ceq0_op[4];
80
+extern const GVecGen2 clt0_op[4];
81
+extern const GVecGen2 cgt0_op[4];
82
+extern const GVecGen2 cle0_op[4];
83
+extern const GVecGen2 cge0_op[4];
84
extern const GVecGen3 mla_op[4];
85
extern const GVecGen3 mls_op[4];
86
extern const GVecGen3 cmtst_op[4];
87
diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/target/arm/neon_helper.c
90
+++ b/target/arm/neon_helper.c
91
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_hsub_u32)(uint32_t src1, uint32_t src2)
92
return dest;
93
}
94
95
-#define NEON_FN(dest, src1, src2) dest = (src1 > src2) ? ~0 : 0
96
-NEON_VOP(cgt_s8, neon_s8, 4)
97
-NEON_VOP(cgt_u8, neon_u8, 4)
98
-NEON_VOP(cgt_s16, neon_s16, 2)
99
-NEON_VOP(cgt_u16, neon_u16, 2)
100
-NEON_VOP(cgt_s32, neon_s32, 1)
101
-NEON_VOP(cgt_u32, neon_u32, 1)
102
-#undef NEON_FN
103
-
104
-#define NEON_FN(dest, src1, src2) dest = (src1 >= src2) ? ~0 : 0
105
-NEON_VOP(cge_s8, neon_s8, 4)
106
-NEON_VOP(cge_u8, neon_u8, 4)
107
-NEON_VOP(cge_s16, neon_s16, 2)
108
-NEON_VOP(cge_u16, neon_u16, 2)
109
-NEON_VOP(cge_s32, neon_s32, 1)
110
-NEON_VOP(cge_u32, neon_u32, 1)
111
-#undef NEON_FN
112
-
113
#define NEON_FN(dest, src1, src2) dest = (src1 < src2) ? src1 : src2
114
NEON_POP(pmin_s8, neon_s8, 4)
115
NEON_POP(pmin_u8, neon_u8, 4)
116
@@ -XXX,XX +XXX,XX @@ NEON_VOP(tst_u16, neon_u16, 2)
117
NEON_VOP(tst_u32, neon_u32, 1)
118
#undef NEON_FN
119
120
-#define NEON_FN(dest, src1, src2) dest = (src1 == src2) ? -1 : 0
121
-NEON_VOP(ceq_u8, neon_u8, 4)
122
-NEON_VOP(ceq_u16, neon_u16, 2)
123
-NEON_VOP(ceq_u32, neon_u32, 1)
124
-#undef NEON_FN
125
-
126
/* Count Leading Sign/Zero Bits. */
127
static inline int do_clz8(uint8_t x)
128
{
129
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
130
index XXXXXXX..XXXXXXX 100644
131
--- a/target/arm/translate-a64.c
132
+++ b/target/arm/translate-a64.c
133
@@ -XXX,XX +XXX,XX @@ static void gen_gvec_fn4(DisasContext *s, bool is_q, int rd, int rn, int rm,
134
is_q ? 16 : 8, vec_full_reg_size(s));
135
}
136
137
+/* Expand a 2-operand AdvSIMD vector operation using an op descriptor. */
138
+static void gen_gvec_op2(DisasContext *s, bool is_q, int rd,
139
+ int rn, const GVecGen2 *gvec_op)
140
+{
141
+ tcg_gen_gvec_2(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn),
142
+ is_q ? 16 : 8, vec_full_reg_size(s), gvec_op);
143
+}
144
+
145
/* Expand a 2-operand + immediate AdvSIMD vector operation using
146
* an op descriptor.
147
*/
148
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
149
return;
150
}
151
break;
152
+ case 0x8: /* CMGT, CMGE */
153
+ gen_gvec_op2(s, is_q, rd, rn, u ? &cge0_op[size] : &cgt0_op[size]);
154
+ return;
155
+ case 0x9: /* CMEQ, CMLE */
156
+ gen_gvec_op2(s, is_q, rd, rn, u ? &cle0_op[size] : &ceq0_op[size]);
157
+ return;
158
+ case 0xa: /* CMLT */
159
+ gen_gvec_op2(s, is_q, rd, rn, &clt0_op[size]);
160
+ return;
161
case 0xb:
162
if (u) { /* ABS, NEG */
163
gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size);
164
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
165
for (pass = 0; pass < (is_q ? 4 : 2); pass++) {
166
TCGv_i32 tcg_op = tcg_temp_new_i32();
167
TCGv_i32 tcg_res = tcg_temp_new_i32();
168
- TCGCond cond;
169
170
read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
171
172
if (size == 2) {
173
/* Special cases for 32 bit elements */
174
switch (opcode) {
175
- case 0xa: /* CMLT */
176
- /* 32 bit integer comparison against zero, result is
177
- * test ? (2^32 - 1) : 0. We implement via setcond(test)
178
- * and inverting.
179
- */
180
- cond = TCG_COND_LT;
181
- do_cmop:
182
- tcg_gen_setcondi_i32(cond, tcg_res, tcg_op, 0);
183
- tcg_gen_neg_i32(tcg_res, tcg_res);
184
- break;
185
- case 0x8: /* CMGT, CMGE */
186
- cond = u ? TCG_COND_GE : TCG_COND_GT;
187
- goto do_cmop;
188
- case 0x9: /* CMEQ, CMLE */
189
- cond = u ? TCG_COND_LE : TCG_COND_EQ;
190
- goto do_cmop;
191
case 0x4: /* CLS */
192
if (u) {
193
tcg_gen_clzi_i32(tcg_res, tcg_op, 32);
194
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
195
genfn(tcg_res, cpu_env, tcg_op);
196
break;
197
}
198
- case 0x8: /* CMGT, CMGE */
199
- case 0x9: /* CMEQ, CMLE */
200
- case 0xa: /* CMLT */
201
- {
202
- static NeonGenTwoOpFn * const fns[3][2] = {
203
- { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_s16 },
204
- { gen_helper_neon_cge_s8, gen_helper_neon_cge_s16 },
205
- { gen_helper_neon_ceq_u8, gen_helper_neon_ceq_u16 },
206
- };
207
- NeonGenTwoOpFn *genfn;
208
- int comp;
209
- bool reverse;
210
- TCGv_i32 tcg_zero = tcg_const_i32(0);
211
-
212
- /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
213
- comp = (opcode - 0x8) * 2 + u;
214
- /* ...but LE, LT are implemented as reverse GE, GT */
215
- reverse = (comp > 2);
216
- if (reverse) {
217
- comp = 4 - comp;
218
- }
219
- genfn = fns[comp][size];
220
- if (reverse) {
221
- genfn(tcg_res, tcg_zero, tcg_op);
222
- } else {
223
- genfn(tcg_res, tcg_op, tcg_zero);
224
- }
225
- tcg_temp_free_i32(tcg_zero);
226
- break;
227
- }
228
case 0x4: /* CLS, CLZ */
229
if (u) {
230
if (size == 0) {
231
diff --git a/target/arm/translate.c b/target/arm/translate.c
23
diff --git a/target/arm/translate.c b/target/arm/translate.c
232
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
233
--- a/target/arm/translate.c
25
--- a/target/arm/translate.c
234
+++ b/target/arm/translate.c
26
+++ b/target/arm/translate.c
235
@@ -XXX,XX +XXX,XX @@ static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn,
27
@@ -XXX,XX +XXX,XX @@ static bool valid_cp(DisasContext *s, int cp)
236
return 1;
28
* only cp14 and cp15 are valid, and other values aren't considered
237
}
29
* to be in the coprocessor-instruction space at all. v8M still
238
30
* permits coprocessors 0..7.
239
+static void gen_ceq0_i32(TCGv_i32 d, TCGv_i32 a)
31
+ * For XScale, we must not decode the XScale cp0, cp1 space as
240
+{
32
+ * a standard coprocessor insn, because we want to fall through to
241
+ tcg_gen_setcondi_i32(TCG_COND_EQ, d, a, 0);
33
+ * the legacy disas_xscale_insn() decoder after decodetree is done.
242
+ tcg_gen_neg_i32(d, d);
34
*/
243
+}
35
+ if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) {
36
+ return false;
37
+ }
244
+
38
+
245
+static void gen_ceq0_i64(TCGv_i64 d, TCGv_i64 a)
39
if (arm_dc_feature(s, ARM_FEATURE_V8) &&
246
+{
40
!arm_dc_feature(s, ARM_FEATURE_M)) {
247
+ tcg_gen_setcondi_i64(TCG_COND_EQ, d, a, 0);
41
return cp >= 14;
248
+ tcg_gen_neg_i64(d, d);
249
+}
250
+
251
+static void gen_ceq0_vec(unsigned vece, TCGv_vec d, TCGv_vec a)
252
+{
253
+ TCGv_vec zero = tcg_const_zeros_vec_matching(d);
254
+ tcg_gen_cmp_vec(TCG_COND_EQ, vece, d, a, zero);
255
+ tcg_temp_free_vec(zero);
256
+}
257
+
258
+static const TCGOpcode vecop_list_cmp[] = {
259
+ INDEX_op_cmp_vec, 0
260
+};
261
+
262
+const GVecGen2 ceq0_op[4] = {
263
+ { .fno = gen_helper_gvec_ceq0_b,
264
+ .fniv = gen_ceq0_vec,
265
+ .opt_opc = vecop_list_cmp,
266
+ .vece = MO_8 },
267
+ { .fno = gen_helper_gvec_ceq0_h,
268
+ .fniv = gen_ceq0_vec,
269
+ .opt_opc = vecop_list_cmp,
270
+ .vece = MO_16 },
271
+ { .fni4 = gen_ceq0_i32,
272
+ .fniv = gen_ceq0_vec,
273
+ .opt_opc = vecop_list_cmp,
274
+ .vece = MO_32 },
275
+ { .fni8 = gen_ceq0_i64,
276
+ .fniv = gen_ceq0_vec,
277
+ .opt_opc = vecop_list_cmp,
278
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
279
+ .vece = MO_64 },
280
+};
281
+
282
+static void gen_cle0_i32(TCGv_i32 d, TCGv_i32 a)
283
+{
284
+ tcg_gen_setcondi_i32(TCG_COND_LE, d, a, 0);
285
+ tcg_gen_neg_i32(d, d);
286
+}
287
+
288
+static void gen_cle0_i64(TCGv_i64 d, TCGv_i64 a)
289
+{
290
+ tcg_gen_setcondi_i64(TCG_COND_LE, d, a, 0);
291
+ tcg_gen_neg_i64(d, d);
292
+}
293
+
294
+static void gen_cle0_vec(unsigned vece, TCGv_vec d, TCGv_vec a)
295
+{
296
+ TCGv_vec zero = tcg_const_zeros_vec_matching(d);
297
+ tcg_gen_cmp_vec(TCG_COND_LE, vece, d, a, zero);
298
+ tcg_temp_free_vec(zero);
299
+}
300
+
301
+const GVecGen2 cle0_op[4] = {
302
+ { .fno = gen_helper_gvec_cle0_b,
303
+ .fniv = gen_cle0_vec,
304
+ .opt_opc = vecop_list_cmp,
305
+ .vece = MO_8 },
306
+ { .fno = gen_helper_gvec_cle0_h,
307
+ .fniv = gen_cle0_vec,
308
+ .opt_opc = vecop_list_cmp,
309
+ .vece = MO_16 },
310
+ { .fni4 = gen_cle0_i32,
311
+ .fniv = gen_cle0_vec,
312
+ .opt_opc = vecop_list_cmp,
313
+ .vece = MO_32 },
314
+ { .fni8 = gen_cle0_i64,
315
+ .fniv = gen_cle0_vec,
316
+ .opt_opc = vecop_list_cmp,
317
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
318
+ .vece = MO_64 },
319
+};
320
+
321
+static void gen_cge0_i32(TCGv_i32 d, TCGv_i32 a)
322
+{
323
+ tcg_gen_setcondi_i32(TCG_COND_GE, d, a, 0);
324
+ tcg_gen_neg_i32(d, d);
325
+}
326
+
327
+static void gen_cge0_i64(TCGv_i64 d, TCGv_i64 a)
328
+{
329
+ tcg_gen_setcondi_i64(TCG_COND_GE, d, a, 0);
330
+ tcg_gen_neg_i64(d, d);
331
+}
332
+
333
+static void gen_cge0_vec(unsigned vece, TCGv_vec d, TCGv_vec a)
334
+{
335
+ TCGv_vec zero = tcg_const_zeros_vec_matching(d);
336
+ tcg_gen_cmp_vec(TCG_COND_GE, vece, d, a, zero);
337
+ tcg_temp_free_vec(zero);
338
+}
339
+
340
+const GVecGen2 cge0_op[4] = {
341
+ { .fno = gen_helper_gvec_cge0_b,
342
+ .fniv = gen_cge0_vec,
343
+ .opt_opc = vecop_list_cmp,
344
+ .vece = MO_8 },
345
+ { .fno = gen_helper_gvec_cge0_h,
346
+ .fniv = gen_cge0_vec,
347
+ .opt_opc = vecop_list_cmp,
348
+ .vece = MO_16 },
349
+ { .fni4 = gen_cge0_i32,
350
+ .fniv = gen_cge0_vec,
351
+ .opt_opc = vecop_list_cmp,
352
+ .vece = MO_32 },
353
+ { .fni8 = gen_cge0_i64,
354
+ .fniv = gen_cge0_vec,
355
+ .opt_opc = vecop_list_cmp,
356
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
357
+ .vece = MO_64 },
358
+};
359
+
360
+static void gen_clt0_i32(TCGv_i32 d, TCGv_i32 a)
361
+{
362
+ tcg_gen_setcondi_i32(TCG_COND_LT, d, a, 0);
363
+ tcg_gen_neg_i32(d, d);
364
+}
365
+
366
+static void gen_clt0_i64(TCGv_i64 d, TCGv_i64 a)
367
+{
368
+ tcg_gen_setcondi_i64(TCG_COND_LT, d, a, 0);
369
+ tcg_gen_neg_i64(d, d);
370
+}
371
+
372
+static void gen_clt0_vec(unsigned vece, TCGv_vec d, TCGv_vec a)
373
+{
374
+ TCGv_vec zero = tcg_const_zeros_vec_matching(d);
375
+ tcg_gen_cmp_vec(TCG_COND_LT, vece, d, a, zero);
376
+ tcg_temp_free_vec(zero);
377
+}
378
+
379
+const GVecGen2 clt0_op[4] = {
380
+ { .fno = gen_helper_gvec_clt0_b,
381
+ .fniv = gen_clt0_vec,
382
+ .opt_opc = vecop_list_cmp,
383
+ .vece = MO_8 },
384
+ { .fno = gen_helper_gvec_clt0_h,
385
+ .fniv = gen_clt0_vec,
386
+ .opt_opc = vecop_list_cmp,
387
+ .vece = MO_16 },
388
+ { .fni4 = gen_clt0_i32,
389
+ .fniv = gen_clt0_vec,
390
+ .opt_opc = vecop_list_cmp,
391
+ .vece = MO_32 },
392
+ { .fni8 = gen_clt0_i64,
393
+ .fniv = gen_clt0_vec,
394
+ .opt_opc = vecop_list_cmp,
395
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
396
+ .vece = MO_64 },
397
+};
398
+
399
+static void gen_cgt0_i32(TCGv_i32 d, TCGv_i32 a)
400
+{
401
+ tcg_gen_setcondi_i32(TCG_COND_GT, d, a, 0);
402
+ tcg_gen_neg_i32(d, d);
403
+}
404
+
405
+static void gen_cgt0_i64(TCGv_i64 d, TCGv_i64 a)
406
+{
407
+ tcg_gen_setcondi_i64(TCG_COND_GT, d, a, 0);
408
+ tcg_gen_neg_i64(d, d);
409
+}
410
+
411
+static void gen_cgt0_vec(unsigned vece, TCGv_vec d, TCGv_vec a)
412
+{
413
+ TCGv_vec zero = tcg_const_zeros_vec_matching(d);
414
+ tcg_gen_cmp_vec(TCG_COND_GT, vece, d, a, zero);
415
+ tcg_temp_free_vec(zero);
416
+}
417
+
418
+const GVecGen2 cgt0_op[4] = {
419
+ { .fno = gen_helper_gvec_cgt0_b,
420
+ .fniv = gen_cgt0_vec,
421
+ .opt_opc = vecop_list_cmp,
422
+ .vece = MO_8 },
423
+ { .fno = gen_helper_gvec_cgt0_h,
424
+ .fniv = gen_cgt0_vec,
425
+ .opt_opc = vecop_list_cmp,
426
+ .vece = MO_16 },
427
+ { .fni4 = gen_cgt0_i32,
428
+ .fniv = gen_cgt0_vec,
429
+ .opt_opc = vecop_list_cmp,
430
+ .vece = MO_32 },
431
+ { .fni8 = gen_cgt0_i64,
432
+ .fniv = gen_cgt0_vec,
433
+ .opt_opc = vecop_list_cmp,
434
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
435
+ .vece = MO_64 },
436
+};
437
+
438
static void gen_ssra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
439
{
440
tcg_gen_vec_sar8i_i64(a, a, shift);
441
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
442
tcg_gen_gvec_abs(size, rd_ofs, rm_ofs, vec_size, vec_size);
443
break;
444
445
+ case NEON_2RM_VCEQ0:
446
+ tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size,
447
+ vec_size, &ceq0_op[size]);
448
+ break;
449
+ case NEON_2RM_VCGT0:
450
+ tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size,
451
+ vec_size, &cgt0_op[size]);
452
+ break;
453
+ case NEON_2RM_VCLE0:
454
+ tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size,
455
+ vec_size, &cle0_op[size]);
456
+ break;
457
+ case NEON_2RM_VCGE0:
458
+ tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size,
459
+ vec_size, &cge0_op[size]);
460
+ break;
461
+ case NEON_2RM_VCLT0:
462
+ tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size,
463
+ vec_size, &clt0_op[size]);
464
+ break;
465
+
466
default:
467
elementwise:
468
for (pass = 0; pass < (q ? 4 : 2); pass++) {
469
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
470
default: abort();
471
}
472
break;
473
- case NEON_2RM_VCGT0: case NEON_2RM_VCLE0:
474
- tmp2 = tcg_const_i32(0);
475
- switch(size) {
476
- case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break;
477
- case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break;
478
- case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break;
479
- default: abort();
480
- }
481
- tcg_temp_free_i32(tmp2);
482
- if (op == NEON_2RM_VCLE0) {
483
- tcg_gen_not_i32(tmp, tmp);
484
- }
485
- break;
486
- case NEON_2RM_VCGE0: case NEON_2RM_VCLT0:
487
- tmp2 = tcg_const_i32(0);
488
- switch(size) {
489
- case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break;
490
- case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break;
491
- case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break;
492
- default: abort();
493
- }
494
- tcg_temp_free_i32(tmp2);
495
- if (op == NEON_2RM_VCLT0) {
496
- tcg_gen_not_i32(tmp, tmp);
497
- }
498
- break;
499
- case NEON_2RM_VCEQ0:
500
- tmp2 = tcg_const_i32(0);
501
- switch(size) {
502
- case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
503
- case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
504
- case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
505
- default: abort();
506
- }
507
- tcg_temp_free_i32(tmp2);
508
- break;
509
case NEON_2RM_VCGT0_F:
510
{
511
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
512
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
513
index XXXXXXX..XXXXXXX 100644
514
--- a/target/arm/vec_helper.c
515
+++ b/target/arm/vec_helper.c
516
@@ -XXX,XX +XXX,XX @@ void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc)
517
}
518
}
519
#endif
520
+
521
+#define DO_CMP0(NAME, TYPE, OP) \
522
+void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
523
+{ \
524
+ intptr_t i, opr_sz = simd_oprsz(desc); \
525
+ for (i = 0; i < opr_sz; i += sizeof(TYPE)) { \
526
+ TYPE nn = *(TYPE *)(vn + i); \
527
+ *(TYPE *)(vd + i) = -(nn OP 0); \
528
+ } \
529
+ clear_tail(vd, opr_sz, simd_maxsz(desc)); \
530
+}
531
+
532
+DO_CMP0(gvec_ceq0_b, int8_t, ==)
533
+DO_CMP0(gvec_clt0_b, int8_t, <)
534
+DO_CMP0(gvec_cle0_b, int8_t, <=)
535
+DO_CMP0(gvec_cgt0_b, int8_t, >)
536
+DO_CMP0(gvec_cge0_b, int8_t, >=)
537
+
538
+DO_CMP0(gvec_ceq0_h, int16_t, ==)
539
+DO_CMP0(gvec_clt0_h, int16_t, <)
540
+DO_CMP0(gvec_cle0_h, int16_t, <=)
541
+DO_CMP0(gvec_cgt0_h, int16_t, >)
542
+DO_CMP0(gvec_cge0_h, int16_t, >=)
543
+
544
+#undef DO_CMP0
545
--
42
--
546
2.20.1
43
2.20.1
547
44
548
45
diff view generated by jsdifflib
1
From: Cameron Esfahani <dirty@apple.com>
1
A copy-and-paste error meant that the return value for register offset 0x44
2
(the RX Status FIFO PEEK register) returned a byte from a bogus offset in
3
the rx status FIFO. Fix the typo.
2
4
3
NRF51_GPIO_REG_CNF_END doesn't actually refer to the start of the last
5
Cc: qemu-stable@nongnu.org
4
valid CNF register: it's referring to the last byte of the last valid
6
Fixes: https://bugs.launchpad.net/qemu/+bug/1904954
5
CNF register.
6
7
This hasn't been a problem up to now, as current implementation in
8
memory.c turns an unaligned 4-byte read from 0x77f to a single byte read
9
and the qtest only looks at the least-significant byte of the register.
10
11
But when running with patches which fix unaligned accesses in memory.c,
12
the qtest breaks.
13
14
Considering NRF51 doesn't support unaligned accesses, the simplest fix
15
is to actually set NRF51_GPIO_REG_CNF_END to the start of the last valid
16
CNF register: 0x77c.
17
18
Now, qtests work with or without the unaligned access patches.
19
20
Reviewed-by: Cédric Le Goater <clg@kaod.org>
21
Tested-by: Cédric Le Goater <clg@kaod.org>
22
Reviewed-by: Joel Stanley <joel@jms.id.au>
23
Signed-off-by: Cameron Esfahani <dirty@apple.com>
24
Message-id: 51b427f06838622da783d38ba56e3630d6d85c60.1586925392.git.dirty@apple.com
25
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20210108180401.2263-2-peter.maydell@linaro.org
27
---
10
---
28
include/hw/gpio/nrf51_gpio.h | 2 +-
11
hw/net/lan9118.c | 2 +-
29
1 file changed, 1 insertion(+), 1 deletion(-)
12
1 file changed, 1 insertion(+), 1 deletion(-)
30
13
31
diff --git a/include/hw/gpio/nrf51_gpio.h b/include/hw/gpio/nrf51_gpio.h
14
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
32
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
33
--- a/include/hw/gpio/nrf51_gpio.h
16
--- a/hw/net/lan9118.c
34
+++ b/include/hw/gpio/nrf51_gpio.h
17
+++ b/hw/net/lan9118.c
35
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
36
#define NRF51_GPIO_REG_DIRSET 0x518
19
case 0x40:
37
#define NRF51_GPIO_REG_DIRCLR 0x51C
20
return rx_status_fifo_pop(s);
38
#define NRF51_GPIO_REG_CNF_START 0x700
21
case 0x44:
39
-#define NRF51_GPIO_REG_CNF_END 0x77F
22
- return s->rx_status_fifo[s->tx_status_fifo_head];
40
+#define NRF51_GPIO_REG_CNF_END 0x77C
23
+ return s->rx_status_fifo[s->rx_status_fifo_head];
41
24
case 0x48:
42
#define NRF51_GPIO_PULLDOWN 1
25
return tx_status_fifo_pop(s);
43
#define NRF51_GPIO_PULLUP 3
26
case 0x4c:
44
--
27
--
45
2.20.1
28
2.20.1
46
29
47
30
diff view generated by jsdifflib
Deleted patch
1
From: Keqian Zhu <zhukeqian1@huawei.com>
2
1
3
The KVM_VGIC_ATTR macro expect the second parameter as gicr_typer,
4
of which high 32bit is constructed by mp_affinity. For most case,
5
the high 32bit of mp_affinity is zero, so it will always access the
6
ICC_CTLR_EL1 of CPU0.
7
8
Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
9
Message-id: 20200413091552.62748-2-zhukeqian1@huawei.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/intc/arm_gicv3_kvm.c | 4 +---
14
1 file changed, 1 insertion(+), 3 deletions(-)
15
16
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/arm_gicv3_kvm.c
19
+++ b/hw/intc/arm_gicv3_kvm.c
20
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_get(GICv3State *s)
21
22
static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
23
{
24
- ARMCPU *cpu;
25
GICv3State *s;
26
GICv3CPUState *c;
27
28
c = (GICv3CPUState *)env->gicv3state;
29
s = c->gic;
30
- cpu = ARM_CPU(c->cpu);
31
32
c->icc_pmr_el1 = 0;
33
c->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
34
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
35
36
/* Initialize to actual HW supported configuration */
37
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
38
- KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity),
39
+ KVM_VGIC_ATTR(ICC_CTLR_EL1, c->gicr_typer),
40
&c->icc_ctlr_el1[GICV3_NS], false, &error_abort);
41
42
c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
43
--
44
2.20.1
45
46
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
The lan9118 code mostly uses symbolic constants for register offsets;
2
the exceptions are those which the datasheet doesn't give an official
3
symbolic name to.
2
4
3
Setup the ADMA with 128bit bus-width. This matters when
5
Add some names for the registers which don't already have them, based
4
FIXED BURST mode is used.
6
on the longer names they are given in the memory map.
5
7
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Message-id: 20200417153800.27399-2-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20210108180401.2263-3-peter.maydell@linaro.org
11
---
11
---
12
hw/arm/xlnx-versal.c | 2 ++
12
hw/net/lan9118.c | 24 ++++++++++++++++++------
13
1 file changed, 2 insertions(+)
13
1 file changed, 18 insertions(+), 6 deletions(-)
14
14
15
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
15
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/xlnx-versal.c
17
--- a/hw/net/lan9118.c
18
+++ b/hw/arm/xlnx-versal.c
18
+++ b/hw/net/lan9118.c
19
@@ -XXX,XX +XXX,XX @@ static void versal_create_admas(Versal *s, qemu_irq *pic)
19
@@ -XXX,XX +XXX,XX @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
20
20
do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
21
dev = qdev_create(NULL, "xlnx.zdma");
21
#endif
22
s->lpd.iou.adma[i] = SYS_BUS_DEVICE(dev);
22
23
+ object_property_set_int(OBJECT(s->lpd.iou.adma[i]), 128, "bus-width",
23
+/* The tx and rx fifo ports are a range of aliased 32-bit registers */
24
+ &error_abort);
24
+#define RX_DATA_FIFO_PORT_FIRST 0x00
25
object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
25
+#define RX_DATA_FIFO_PORT_LAST 0x1f
26
qdev_init_nofail(dev);
26
+#define TX_DATA_FIFO_PORT_FIRST 0x20
27
27
+#define TX_DATA_FIFO_PORT_LAST 0x3f
28
+
29
+#define RX_STATUS_FIFO_PORT 0x40
30
+#define RX_STATUS_FIFO_PEEK 0x44
31
+#define TX_STATUS_FIFO_PORT 0x48
32
+#define TX_STATUS_FIFO_PEEK 0x4c
33
+
34
#define CSR_ID_REV 0x50
35
#define CSR_IRQ_CFG 0x54
36
#define CSR_INT_STS 0x58
37
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
38
offset &= 0xff;
39
40
//DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
41
- if (offset >= 0x20 && offset < 0x40) {
42
+ if (offset >= TX_DATA_FIFO_PORT_FIRST &&
43
+ offset <= TX_DATA_FIFO_PORT_LAST) {
44
/* TX FIFO */
45
tx_fifo_push(s, val);
46
return;
47
@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
48
lan9118_state *s = (lan9118_state *)opaque;
49
50
//DPRINTF("Read reg 0x%02x\n", (int)offset);
51
- if (offset < 0x20) {
52
+ if (offset <= RX_DATA_FIFO_PORT_LAST) {
53
/* RX FIFO */
54
return rx_fifo_pop(s);
55
}
56
switch (offset) {
57
- case 0x40:
58
+ case RX_STATUS_FIFO_PORT:
59
return rx_status_fifo_pop(s);
60
- case 0x44:
61
+ case RX_STATUS_FIFO_PEEK:
62
return s->rx_status_fifo[s->rx_status_fifo_head];
63
- case 0x48:
64
+ case TX_STATUS_FIFO_PORT:
65
return tx_status_fifo_pop(s);
66
- case 0x4c:
67
+ case TX_STATUS_FIFO_PEEK:
68
return s->tx_status_fifo[s->tx_status_fifo_head];
69
case CSR_ID_REV:
70
return 0x01180001;
28
--
71
--
29
2.20.1
72
2.20.1
30
73
31
74
diff view generated by jsdifflib
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
Modelled Ethernet MAC of Smartfusion2 SoC.
3
This patch allows NPCM7XX CLK module to compute clocks that are used by
4
Micrel KSZ8051 PHY is present on Emcraft's
4
other NPCM7XX modules.
5
SOM kit hence same PHY is emulated.
6
5
7
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
6
Add a new struct NPCM7xxClockConverterState which represents a
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
single converter. Each clock converter in CLK module represents one
9
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
10
Message-id: 1587048891-30493-2-git-send-email-sundeep.lkml@gmail.com
9
takes one or more input clocks and converts them into one output clock.
10
They form a clock hierarchy in the CLK module and are responsible for
11
outputing clocks for various other modules in an NPCM7XX SoC.
12
13
Each converter has a function pointer called "convert" which represents
14
the unique logic for that converter.
15
16
The clock contains two initialization information: ConverterInitInfo and
17
ConverterConnectionInfo. They represent the vertices and edges in the
18
clock diagram respectively.
19
20
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
21
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
22
Signed-off-by: Hao Wu <wuhaotsh@google.com>
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
Message-id: 20210108190945.949196-2-wuhaotsh@google.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
26
---
13
hw/net/Makefile.objs | 1 +
27
include/hw/misc/npcm7xx_clk.h | 140 +++++-
14
include/hw/net/msf2-emac.h | 53 ++++
28
hw/misc/npcm7xx_clk.c | 805 +++++++++++++++++++++++++++++++++-
15
hw/net/msf2-emac.c | 589 +++++++++++++++++++++++++++++++++++++
29
2 files changed, 932 insertions(+), 13 deletions(-)
16
MAINTAINERS | 2 +
17
4 files changed, 645 insertions(+)
18
create mode 100644 include/hw/net/msf2-emac.h
19
create mode 100644 hw/net/msf2-emac.c
20
30
21
diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs
31
diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
22
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/net/Makefile.objs
33
--- a/include/hw/misc/npcm7xx_clk.h
24
+++ b/hw/net/Makefile.objs
34
+++ b/include/hw/misc/npcm7xx_clk.h
25
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_ROCKER) += rocker/rocker.o rocker/rocker_fp.o \
26
obj-$(call lnot,$(CONFIG_ROCKER)) += rocker/qmp-norocker.o
27
28
common-obj-$(CONFIG_CAN_BUS) += can/
29
+common-obj-$(CONFIG_MSF2) += msf2-emac.o
30
diff --git a/include/hw/net/msf2-emac.h b/include/hw/net/msf2-emac.h
31
new file mode 100644
32
index XXXXXXX..XXXXXXX
33
--- /dev/null
34
+++ b/include/hw/net/msf2-emac.h
35
@@ -XXX,XX +XXX,XX @@
35
@@ -XXX,XX +XXX,XX @@
36
#define NPCM7XX_CLK_H
37
38
#include "exec/memory.h"
39
+#include "hw/clock.h"
40
#include "hw/sysbus.h"
41
42
/*
43
@@ -XXX,XX +XXX,XX @@
44
45
#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
46
47
-typedef struct NPCM7xxCLKState {
48
+/* Maximum amount of clock inputs in a SEL module. */
49
+#define NPCM7XX_CLK_SEL_MAX_INPUT 5
50
+
51
+/* PLLs in CLK module. */
52
+typedef enum NPCM7xxClockPLL {
53
+ NPCM7XX_CLOCK_PLL0,
54
+ NPCM7XX_CLOCK_PLL1,
55
+ NPCM7XX_CLOCK_PLL2,
56
+ NPCM7XX_CLOCK_PLLG,
57
+ NPCM7XX_CLOCK_NR_PLLS,
58
+} NPCM7xxClockPLL;
59
+
60
+/* SEL/MUX in CLK module. */
61
+typedef enum NPCM7xxClockSEL {
62
+ NPCM7XX_CLOCK_PIXCKSEL,
63
+ NPCM7XX_CLOCK_MCCKSEL,
64
+ NPCM7XX_CLOCK_CPUCKSEL,
65
+ NPCM7XX_CLOCK_CLKOUTSEL,
66
+ NPCM7XX_CLOCK_UARTCKSEL,
67
+ NPCM7XX_CLOCK_TIMCKSEL,
68
+ NPCM7XX_CLOCK_SDCKSEL,
69
+ NPCM7XX_CLOCK_GFXMSEL,
70
+ NPCM7XX_CLOCK_SUCKSEL,
71
+ NPCM7XX_CLOCK_NR_SELS,
72
+} NPCM7xxClockSEL;
73
+
74
+/* Dividers in CLK module. */
75
+typedef enum NPCM7xxClockDivider {
76
+ NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */
77
+ NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */
78
+ NPCM7XX_CLOCK_MC_DIVIDER,
79
+ NPCM7XX_CLOCK_AXI_DIVIDER,
80
+ NPCM7XX_CLOCK_AHB_DIVIDER,
81
+ NPCM7XX_CLOCK_AHB3_DIVIDER,
82
+ NPCM7XX_CLOCK_SPI0_DIVIDER,
83
+ NPCM7XX_CLOCK_SPIX_DIVIDER,
84
+ NPCM7XX_CLOCK_APB1_DIVIDER,
85
+ NPCM7XX_CLOCK_APB2_DIVIDER,
86
+ NPCM7XX_CLOCK_APB3_DIVIDER,
87
+ NPCM7XX_CLOCK_APB4_DIVIDER,
88
+ NPCM7XX_CLOCK_APB5_DIVIDER,
89
+ NPCM7XX_CLOCK_CLKOUT_DIVIDER,
90
+ NPCM7XX_CLOCK_UART_DIVIDER,
91
+ NPCM7XX_CLOCK_TIMER_DIVIDER,
92
+ NPCM7XX_CLOCK_ADC_DIVIDER,
93
+ NPCM7XX_CLOCK_MMC_DIVIDER,
94
+ NPCM7XX_CLOCK_SDHC_DIVIDER,
95
+ NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */
96
+ NPCM7XX_CLOCK_UTMI_DIVIDER,
97
+ NPCM7XX_CLOCK_NR_DIVIDERS,
98
+} NPCM7xxClockConverter;
99
+
100
+typedef struct NPCM7xxCLKState NPCM7xxCLKState;
101
+
102
+/**
103
+ * struct NPCM7xxClockPLLState - A PLL module in CLK module.
104
+ * @name: The name of the module.
105
+ * @clk: The CLK module that owns this module.
106
+ * @clock_in: The input clock of this module.
107
+ * @clock_out: The output clock of this module.
108
+ * @reg: The control registers for this PLL module.
109
+ */
110
+typedef struct NPCM7xxClockPLLState {
111
+ DeviceState parent;
112
+
113
+ const char *name;
114
+ NPCM7xxCLKState *clk;
115
+ Clock *clock_in;
116
+ Clock *clock_out;
117
+
118
+ int reg;
119
+} NPCM7xxClockPLLState;
120
+
121
+/**
122
+ * struct NPCM7xxClockSELState - A SEL module in CLK module.
123
+ * @name: The name of the module.
124
+ * @clk: The CLK module that owns this module.
125
+ * @input_size: The size of inputs of this module.
126
+ * @clock_in: The input clocks of this module.
127
+ * @clock_out: The output clocks of this module.
128
+ * @offset: The offset of this module in the control register.
129
+ * @len: The length of this module in the control register.
130
+ */
131
+typedef struct NPCM7xxClockSELState {
132
+ DeviceState parent;
133
+
134
+ const char *name;
135
+ NPCM7xxCLKState *clk;
136
+ uint8_t input_size;
137
+ Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];
138
+ Clock *clock_out;
139
+
140
+ int offset;
141
+ int len;
142
+} NPCM7xxClockSELState;
143
+
144
+/**
145
+ * struct NPCM7xxClockDividerState - A Divider module in CLK module.
146
+ * @name: The name of the module.
147
+ * @clk: The CLK module that owns this module.
148
+ * @clock_in: The input clock of this module.
149
+ * @clock_out: The output clock of this module.
150
+ * @divide: The function the divider uses to divide the input.
151
+ * @reg: The index of the control register that contains the divisor.
152
+ * @offset: The offset of the divisor in the control register.
153
+ * @len: The length of the divisor in the control register.
154
+ * @divisor: The divisor for a constant divisor
155
+ */
156
+typedef struct NPCM7xxClockDividerState {
157
+ DeviceState parent;
158
+
159
+ const char *name;
160
+ NPCM7xxCLKState *clk;
161
+ Clock *clock_in;
162
+ Clock *clock_out;
163
+
164
+ uint32_t (*divide)(struct NPCM7xxClockDividerState *s);
165
+ union {
166
+ struct {
167
+ int reg;
168
+ int offset;
169
+ int len;
170
+ };
171
+ int divisor;
172
+ };
173
+} NPCM7xxClockDividerState;
174
+
175
+struct NPCM7xxCLKState {
176
SysBusDevice parent;
177
178
MemoryRegion iomem;
179
180
+ /* Clock converters */
181
+ NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS];
182
+ NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
183
+ NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
184
+
185
uint32_t regs[NPCM7XX_CLK_NR_REGS];
186
187
/* Time reference for SECCNT and CNTR25M, initialized by power on reset */
188
int64_t ref_ns;
189
-} NPCM7xxCLKState;
190
+
191
+ /* The incoming reference clock. */
192
+ Clock *clkref;
193
+};
194
195
#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
196
#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
197
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
198
index XXXXXXX..XXXXXXX 100644
199
--- a/hw/misc/npcm7xx_clk.c
200
+++ b/hw/misc/npcm7xx_clk.c
201
@@ -XXX,XX +XXX,XX @@
202
203
#include "hw/misc/npcm7xx_clk.h"
204
#include "hw/timer/npcm7xx_timer.h"
205
+#include "hw/qdev-clock.h"
206
#include "migration/vmstate.h"
207
#include "qemu/error-report.h"
208
#include "qemu/log.h"
209
@@ -XXX,XX +XXX,XX @@
210
#include "trace.h"
211
#include "sysemu/watchdog.h"
212
36
+/*
213
+/*
37
+ * QEMU model of the Smartfusion2 Ethernet MAC.
214
+ * The reference clock hz, and the SECCNT and CNTR25M registers in this module,
38
+ *
215
+ * is always 25 MHz.
39
+ * Copyright (c) 2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
40
+ *
41
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
42
+ * of this software and associated documentation files (the "Software"), to deal
43
+ * in the Software without restriction, including without limitation the rights
44
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
45
+ * copies of the Software, and to permit persons to whom the Software is
46
+ * furnished to do so, subject to the following conditions:
47
+ *
48
+ * The above copyright notice and this permission notice shall be included in
49
+ * all copies or substantial portions of the Software.
50
+ *
51
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
52
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
53
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
54
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
55
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
56
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
57
+ * THE SOFTWARE.
58
+ */
216
+ */
59
+
217
+#define NPCM7XX_CLOCK_REF_HZ (25000000)
60
+#include "hw/sysbus.h"
218
+
61
+#include "exec/memory.h"
219
+/* Register Field Definitions */
62
+#include "net/net.h"
220
+#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */
63
+#include "net/eth.h"
221
+
64
+
222
#define PLLCON_LOKI BIT(31)
65
+#define TYPE_MSS_EMAC "msf2-emac"
223
#define PLLCON_LOKS BIT(30)
66
+#define MSS_EMAC(obj) \
224
#define PLLCON_PWDEN BIT(12)
67
+ OBJECT_CHECK(MSF2EmacState, (obj), TYPE_MSS_EMAC)
225
+#define PLLCON_FBDV(con) extract32((con), 16, 12)
68
+
226
+#define PLLCON_OTDV2(con) extract32((con), 13, 3)
69
+#define R_MAX (0x1a0 / 4)
227
+#define PLLCON_OTDV1(con) extract32((con), 8, 3)
70
+#define PHY_MAX_REGS 32
228
+#define PLLCON_INDV(con) extract32((con), 0, 6)
71
+
229
72
+typedef struct MSF2EmacState {
230
enum NPCM7xxCLKRegisters {
73
+ SysBusDevice parent;
231
NPCM7XX_CLK_CLKEN1,
74
+
232
@@ -XXX,XX +XXX,XX @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
75
+ MemoryRegion mmio;
233
[NPCM7XX_CLK_AHBCKFI] = 0x000000c8,
76
+ MemoryRegion *dma_mr;
234
};
77
+ AddressSpace dma_as;
235
78
+
236
-/* Register Field Definitions */
79
+ qemu_irq irq;
237
-#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */
80
+ NICState *nic;
238
-
81
+ NICConf conf;
239
/* The number of watchdogs that can trigger a reset. */
82
+
240
#define NPCM7XX_NR_WATCHDOGS (3)
83
+ uint8_t mac_addr[ETH_ALEN];
241
84
+ uint32_t rx_desc;
242
+/* Clock converter functions */
85
+ uint16_t phy_regs[PHY_MAX_REGS];
243
+
86
+
244
+#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
87
+ uint32_t regs[R_MAX];
245
+#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \
88
+} MSF2EmacState;
246
+ (obj), TYPE_NPCM7XX_CLOCK_PLL)
89
diff --git a/hw/net/msf2-emac.c b/hw/net/msf2-emac.c
247
+#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
90
new file mode 100644
248
+#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \
91
index XXXXXXX..XXXXXXX
249
+ (obj), TYPE_NPCM7XX_CLOCK_SEL)
92
--- /dev/null
250
+#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
93
+++ b/hw/net/msf2-emac.c
251
+#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \
94
@@ -XXX,XX +XXX,XX @@
252
+ (obj), TYPE_NPCM7XX_CLOCK_DIVIDER)
95
+/*
253
+
96
+ * QEMU model of the Smartfusion2 Ethernet MAC.
254
+static void npcm7xx_clk_update_pll(void *opaque)
97
+ *
255
+{
98
+ * Copyright (c) 2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
256
+ NPCM7xxClockPLLState *s = opaque;
99
+ *
257
+ uint32_t con = s->clk->regs[s->reg];
100
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
258
+ uint64_t freq;
101
+ * of this software and associated documentation files (the "Software"), to deal
259
+
102
+ * in the Software without restriction, including without limitation the rights
260
+ /* The PLL is grounded if it is not locked yet. */
103
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
261
+ if (con & PLLCON_LOKI) {
104
+ * copies of the Software, and to permit persons to whom the Software is
262
+ freq = clock_get_hz(s->clock_in);
105
+ * furnished to do so, subject to the following conditions:
263
+ freq *= PLLCON_FBDV(con);
106
+ *
264
+ freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con);
107
+ * The above copyright notice and this permission notice shall be included in
265
+ } else {
108
+ * all copies or substantial portions of the Software.
266
+ freq = 0;
109
+ *
267
+ }
110
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
268
+
111
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
269
+ clock_update_hz(s->clock_out, freq);
112
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
270
+}
113
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
271
+
114
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
272
+static void npcm7xx_clk_update_sel(void *opaque)
115
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
273
+{
116
+ * THE SOFTWARE.
274
+ NPCM7xxClockSELState *s = opaque;
117
+ *
275
+ uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset,
118
+ * Refer to section Ethernet MAC in the document:
276
+ s->len);
119
+ * UG0331: SmartFusion2 Microcontroller Subsystem User Guide
277
+
120
+ * Datasheet URL:
278
+ if (index >= s->input_size) {
121
+ * https://www.microsemi.com/document-portal/cat_view/56661-internal-documents/
279
+ qemu_log_mask(LOG_GUEST_ERROR,
122
+ * 56758-soc?lang=en&limit=20&limitstart=220
280
+ "%s: SEL index: %u out of range\n",
123
+ */
281
+ __func__, index);
124
+
282
+ index = 0;
125
+#include "qemu/osdep.h"
283
+ }
126
+#include "qemu-common.h"
284
+ clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index]));
127
+#include "qemu/log.h"
285
+}
128
+#include "qapi/error.h"
286
+
129
+#include "exec/address-spaces.h"
287
+static void npcm7xx_clk_update_divider(void *opaque)
130
+#include "hw/registerfields.h"
288
+{
131
+#include "hw/net/msf2-emac.h"
289
+ NPCM7xxClockDividerState *s = opaque;
132
+#include "hw/net/mii.h"
290
+ uint32_t freq;
133
+#include "hw/irq.h"
291
+
134
+#include "hw/qdev-properties.h"
292
+ freq = s->divide(s);
135
+#include "migration/vmstate.h"
293
+ clock_update_hz(s->clock_out, freq);
136
+
294
+}
137
+REG32(CFG1, 0x0)
295
+
138
+ FIELD(CFG1, RESET, 31, 1)
296
+static uint32_t divide_by_constant(NPCM7xxClockDividerState *s)
139
+ FIELD(CFG1, RX_EN, 2, 1)
297
+{
140
+ FIELD(CFG1, TX_EN, 0, 1)
298
+ return clock_get_hz(s->clock_in) / s->divisor;
141
+ FIELD(CFG1, LB_EN, 8, 1)
299
+}
142
+REG32(CFG2, 0x4)
300
+
143
+REG32(IFG, 0x8)
301
+static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s)
144
+REG32(HALF_DUPLEX, 0xc)
302
+{
145
+REG32(MAX_FRAME_LENGTH, 0x10)
303
+ return clock_get_hz(s->clock_in) /
146
+REG32(MII_CMD, 0x24)
304
+ (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1);
147
+ FIELD(MII_CMD, READ, 0, 1)
305
+}
148
+REG32(MII_ADDR, 0x28)
306
+
149
+ FIELD(MII_ADDR, REGADDR, 0, 5)
307
+static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s)
150
+ FIELD(MII_ADDR, PHYADDR, 8, 5)
308
+{
151
+REG32(MII_CTL, 0x2c)
309
+ return divide_by_reg_divisor(s) / 2;
152
+REG32(MII_STS, 0x30)
310
+}
153
+REG32(STA1, 0x40)
311
+
154
+REG32(STA2, 0x44)
312
+static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s)
155
+REG32(FIFO_CFG0, 0x48)
313
+{
156
+REG32(FIFO_CFG4, 0x58)
314
+ return clock_get_hz(s->clock_in) >>
157
+ FIELD(FIFO_CFG4, BCAST, 9, 1)
315
+ extract32(s->clk->regs[s->reg], s->offset, s->len);
158
+ FIELD(FIFO_CFG4, MCAST, 8, 1)
316
+}
159
+REG32(FIFO_CFG5, 0x5C)
317
+
160
+ FIELD(FIFO_CFG5, BCAST, 9, 1)
318
+static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg)
161
+ FIELD(FIFO_CFG5, MCAST, 8, 1)
319
+{
162
+REG32(DMA_TX_CTL, 0x180)
320
+ switch (reg) {
163
+ FIELD(DMA_TX_CTL, EN, 0, 1)
321
+ case NPCM7XX_CLK_PLLCON0:
164
+REG32(DMA_TX_DESC, 0x184)
322
+ return NPCM7XX_CLOCK_PLL0;
165
+REG32(DMA_TX_STATUS, 0x188)
323
+ case NPCM7XX_CLK_PLLCON1:
166
+ FIELD(DMA_TX_STATUS, PKTCNT, 16, 8)
324
+ return NPCM7XX_CLOCK_PLL1;
167
+ FIELD(DMA_TX_STATUS, UNDERRUN, 1, 1)
325
+ case NPCM7XX_CLK_PLLCON2:
168
+ FIELD(DMA_TX_STATUS, PKT_SENT, 0, 1)
326
+ return NPCM7XX_CLOCK_PLL2;
169
+REG32(DMA_RX_CTL, 0x18c)
327
+ case NPCM7XX_CLK_PLLCONG:
170
+ FIELD(DMA_RX_CTL, EN, 0, 1)
328
+ return NPCM7XX_CLOCK_PLLG;
171
+REG32(DMA_RX_DESC, 0x190)
329
+ default:
172
+REG32(DMA_RX_STATUS, 0x194)
330
+ g_assert_not_reached();
173
+ FIELD(DMA_RX_STATUS, PKTCNT, 16, 8)
331
+ }
174
+ FIELD(DMA_RX_STATUS, OVERFLOW, 2, 1)
332
+}
175
+ FIELD(DMA_RX_STATUS, PKT_RCVD, 0, 1)
333
+
176
+REG32(DMA_IRQ_MASK, 0x198)
334
+static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
177
+REG32(DMA_IRQ, 0x19c)
335
+{
178
+
336
+ int i;
179
+#define EMPTY_MASK (1 << 31)
337
+
180
+#define PKT_SIZE 0x7FF
338
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
181
+#define PHYADDR 0x1
339
+ npcm7xx_clk_update_pll(&clk->plls[i]);
182
+#define MAX_PKT_SIZE 2048
340
+ }
183
+
341
+}
184
+typedef struct {
342
+
185
+ uint32_t pktaddr;
343
+static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
186
+ uint32_t pktsize;
344
+{
187
+ uint32_t next;
345
+ int i;
188
+} EmacDesc;
346
+
189
+
347
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
190
+static uint32_t emac_get_isr(MSF2EmacState *s)
348
+ npcm7xx_clk_update_sel(&clk->sels[i]);
191
+{
349
+ }
192
+ uint32_t ier = s->regs[R_DMA_IRQ_MASK];
350
+}
193
+ uint32_t tx = s->regs[R_DMA_TX_STATUS] & 0xF;
351
+
194
+ uint32_t rx = s->regs[R_DMA_RX_STATUS] & 0xF;
352
+static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
195
+ uint32_t isr = (rx << 4) | tx;
353
+{
196
+
354
+ int i;
197
+ s->regs[R_DMA_IRQ] = ier & isr;
355
+
198
+ return s->regs[R_DMA_IRQ];
356
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
199
+}
357
+ npcm7xx_clk_update_divider(&clk->dividers[i]);
200
+
358
+ }
201
+static void emac_update_irq(MSF2EmacState *s)
359
+}
202
+{
360
+
203
+ bool intr = emac_get_isr(s);
361
+static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk)
204
+
362
+{
205
+ qemu_set_irq(s->irq, intr);
363
+ clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);
206
+}
364
+ npcm7xx_clk_update_all_plls(clk);
207
+
365
+ npcm7xx_clk_update_all_sels(clk);
208
+static void emac_load_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc)
366
+ npcm7xx_clk_update_all_dividers(clk);
209
+{
367
+}
210
+ address_space_read(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeof *d);
368
+
211
+ /* Convert from LE into host endianness. */
369
+/* Types of clock sources. */
212
+ d->pktaddr = le32_to_cpu(d->pktaddr);
370
+typedef enum ClockSrcType {
213
+ d->pktsize = le32_to_cpu(d->pktsize);
371
+ CLKSRC_REF,
214
+ d->next = le32_to_cpu(d->next);
372
+ CLKSRC_PLL,
215
+}
373
+ CLKSRC_SEL,
216
+
374
+ CLKSRC_DIV,
217
+static void emac_store_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc)
375
+} ClockSrcType;
218
+{
376
+
219
+ /* Convert from host endianness into LE. */
377
+typedef struct PLLInitInfo {
220
+ d->pktaddr = cpu_to_le32(d->pktaddr);
378
+ const char *name;
221
+ d->pktsize = cpu_to_le32(d->pktsize);
379
+ ClockSrcType src_type;
222
+ d->next = cpu_to_le32(d->next);
380
+ int src_index;
223
+
381
+ int reg;
224
+ address_space_write(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeof *d);
382
+ const char *public_name;
225
+}
383
+} PLLInitInfo;
226
+
384
+
227
+static void msf2_dma_tx(MSF2EmacState *s)
385
+typedef struct SELInitInfo {
228
+{
386
+ const char *name;
229
+ NetClientState *nc = qemu_get_queue(s->nic);
387
+ uint8_t input_size;
230
+ hwaddr desc = s->regs[R_DMA_TX_DESC];
388
+ ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT];
231
+ uint8_t buf[MAX_PKT_SIZE];
389
+ int src_index[NPCM7XX_CLK_SEL_MAX_INPUT];
232
+ EmacDesc d;
390
+ int offset;
233
+ int size;
391
+ int len;
234
+ uint8_t pktcnt;
392
+ const char *public_name;
235
+ uint32_t status;
393
+} SELInitInfo;
236
+
394
+
237
+ if (!(s->regs[R_CFG1] & R_CFG1_TX_EN_MASK)) {
395
+typedef struct DividerInitInfo {
238
+ return;
396
+ const char *name;
239
+ }
397
+ ClockSrcType src_type;
240
+
398
+ int src_index;
241
+ while (1) {
399
+ uint32_t (*divide)(NPCM7xxClockDividerState *s);
242
+ emac_load_desc(s, &d, desc);
400
+ int reg; /* not used when type == CONSTANT */
243
+ if (d.pktsize & EMPTY_MASK) {
401
+ int offset; /* not used when type == CONSTANT */
244
+ break;
402
+ int len; /* not used when type == CONSTANT */
403
+ int divisor; /* used only when type == CONSTANT */
404
+ const char *public_name;
405
+} DividerInitInfo;
406
+
407
+static const PLLInitInfo pll_init_info_list[] = {
408
+ [NPCM7XX_CLOCK_PLL0] = {
409
+ .name = "pll0",
410
+ .src_type = CLKSRC_REF,
411
+ .reg = NPCM7XX_CLK_PLLCON0,
412
+ },
413
+ [NPCM7XX_CLOCK_PLL1] = {
414
+ .name = "pll1",
415
+ .src_type = CLKSRC_REF,
416
+ .reg = NPCM7XX_CLK_PLLCON1,
417
+ },
418
+ [NPCM7XX_CLOCK_PLL2] = {
419
+ .name = "pll2",
420
+ .src_type = CLKSRC_REF,
421
+ .reg = NPCM7XX_CLK_PLLCON2,
422
+ },
423
+ [NPCM7XX_CLOCK_PLLG] = {
424
+ .name = "pllg",
425
+ .src_type = CLKSRC_REF,
426
+ .reg = NPCM7XX_CLK_PLLCONG,
427
+ },
428
+};
429
+
430
+static const SELInitInfo sel_init_info_list[] = {
431
+ [NPCM7XX_CLOCK_PIXCKSEL] = {
432
+ .name = "pixcksel",
433
+ .input_size = 2,
434
+ .src_type = {CLKSRC_PLL, CLKSRC_REF},
435
+ .src_index = {NPCM7XX_CLOCK_PLLG, 0},
436
+ .offset = 5,
437
+ .len = 1,
438
+ .public_name = "pixel-clock",
439
+ },
440
+ [NPCM7XX_CLOCK_MCCKSEL] = {
441
+ .name = "mccksel",
442
+ .input_size = 4,
443
+ .src_type = {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF,
444
+ /*MCBPCK, shouldn't be used in normal operation*/
445
+ CLKSRC_REF},
446
+ .src_index = {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0},
447
+ .offset = 12,
448
+ .len = 2,
449
+ .public_name = "mc-phy-clock",
450
+ },
451
+ [NPCM7XX_CLOCK_CPUCKSEL] = {
452
+ .name = "cpucksel",
453
+ .input_size = 4,
454
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
455
+ /*SYSBPCK, shouldn't be used in normal operation*/
456
+ CLKSRC_REF},
457
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0},
458
+ .offset = 0,
459
+ .len = 2,
460
+ .public_name = "system-clock",
461
+ },
462
+ [NPCM7XX_CLOCK_CLKOUTSEL] = {
463
+ .name = "clkoutsel",
464
+ .input_size = 5,
465
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
466
+ CLKSRC_PLL, CLKSRC_DIV},
467
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
468
+ NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2},
469
+ .offset = 18,
470
+ .len = 3,
471
+ .public_name = "tock",
472
+ },
473
+ [NPCM7XX_CLOCK_UARTCKSEL] = {
474
+ .name = "uartcksel",
475
+ .input_size = 4,
476
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
477
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
478
+ NPCM7XX_CLOCK_PLL2D2},
479
+ .offset = 8,
480
+ .len = 2,
481
+ },
482
+ [NPCM7XX_CLOCK_TIMCKSEL] = {
483
+ .name = "timcksel",
484
+ .input_size = 4,
485
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
486
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
487
+ NPCM7XX_CLOCK_PLL2D2},
488
+ .offset = 14,
489
+ .len = 2,
490
+ },
491
+ [NPCM7XX_CLOCK_SDCKSEL] = {
492
+ .name = "sdcksel",
493
+ .input_size = 4,
494
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
495
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
496
+ NPCM7XX_CLOCK_PLL2D2},
497
+ .offset = 6,
498
+ .len = 2,
499
+ },
500
+ [NPCM7XX_CLOCK_GFXMSEL] = {
501
+ .name = "gfxmksel",
502
+ .input_size = 2,
503
+ .src_type = {CLKSRC_REF, CLKSRC_PLL},
504
+ .src_index = {0, NPCM7XX_CLOCK_PLL2},
505
+ .offset = 21,
506
+ .len = 1,
507
+ },
508
+ [NPCM7XX_CLOCK_SUCKSEL] = {
509
+ .name = "sucksel",
510
+ .input_size = 4,
511
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
512
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
513
+ NPCM7XX_CLOCK_PLL2D2},
514
+ .offset = 10,
515
+ .len = 2,
516
+ },
517
+};
518
+
519
+static const DividerInitInfo divider_init_info_list[] = {
520
+ [NPCM7XX_CLOCK_PLL1D2] = {
521
+ .name = "pll1d2",
522
+ .src_type = CLKSRC_PLL,
523
+ .src_index = NPCM7XX_CLOCK_PLL1,
524
+ .divide = divide_by_constant,
525
+ .divisor = 2,
526
+ },
527
+ [NPCM7XX_CLOCK_PLL2D2] = {
528
+ .name = "pll2d2",
529
+ .src_type = CLKSRC_PLL,
530
+ .src_index = NPCM7XX_CLOCK_PLL2,
531
+ .divide = divide_by_constant,
532
+ .divisor = 2,
533
+ },
534
+ [NPCM7XX_CLOCK_MC_DIVIDER] = {
535
+ .name = "mc-divider",
536
+ .src_type = CLKSRC_SEL,
537
+ .src_index = NPCM7XX_CLOCK_MCCKSEL,
538
+ .divide = divide_by_constant,
539
+ .divisor = 2,
540
+ .public_name = "mc-clock"
541
+ },
542
+ [NPCM7XX_CLOCK_AXI_DIVIDER] = {
543
+ .name = "axi-divider",
544
+ .src_type = CLKSRC_SEL,
545
+ .src_index = NPCM7XX_CLOCK_CPUCKSEL,
546
+ .divide = shift_by_reg_divisor,
547
+ .reg = NPCM7XX_CLK_CLKDIV1,
548
+ .offset = 0,
549
+ .len = 1,
550
+ .public_name = "clk2"
551
+ },
552
+ [NPCM7XX_CLOCK_AHB_DIVIDER] = {
553
+ .name = "ahb-divider",
554
+ .src_type = CLKSRC_DIV,
555
+ .src_index = NPCM7XX_CLOCK_AXI_DIVIDER,
556
+ .divide = divide_by_reg_divisor,
557
+ .reg = NPCM7XX_CLK_CLKDIV1,
558
+ .offset = 26,
559
+ .len = 2,
560
+ .public_name = "clk4"
561
+ },
562
+ [NPCM7XX_CLOCK_AHB3_DIVIDER] = {
563
+ .name = "ahb3-divider",
564
+ .src_type = CLKSRC_DIV,
565
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
566
+ .divide = divide_by_reg_divisor,
567
+ .reg = NPCM7XX_CLK_CLKDIV1,
568
+ .offset = 6,
569
+ .len = 5,
570
+ .public_name = "ahb3-spi3-clock"
571
+ },
572
+ [NPCM7XX_CLOCK_SPI0_DIVIDER] = {
573
+ .name = "spi0-divider",
574
+ .src_type = CLKSRC_DIV,
575
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
576
+ .divide = divide_by_reg_divisor,
577
+ .reg = NPCM7XX_CLK_CLKDIV3,
578
+ .offset = 6,
579
+ .len = 5,
580
+ .public_name = "spi0-clock",
581
+ },
582
+ [NPCM7XX_CLOCK_SPIX_DIVIDER] = {
583
+ .name = "spix-divider",
584
+ .src_type = CLKSRC_DIV,
585
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
586
+ .divide = divide_by_reg_divisor,
587
+ .reg = NPCM7XX_CLK_CLKDIV3,
588
+ .offset = 1,
589
+ .len = 5,
590
+ .public_name = "spix-clock",
591
+ },
592
+ [NPCM7XX_CLOCK_APB1_DIVIDER] = {
593
+ .name = "apb1-divider",
594
+ .src_type = CLKSRC_DIV,
595
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
596
+ .divide = shift_by_reg_divisor,
597
+ .reg = NPCM7XX_CLK_CLKDIV2,
598
+ .offset = 24,
599
+ .len = 2,
600
+ .public_name = "apb1-clock",
601
+ },
602
+ [NPCM7XX_CLOCK_APB2_DIVIDER] = {
603
+ .name = "apb2-divider",
604
+ .src_type = CLKSRC_DIV,
605
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
606
+ .divide = shift_by_reg_divisor,
607
+ .reg = NPCM7XX_CLK_CLKDIV2,
608
+ .offset = 26,
609
+ .len = 2,
610
+ .public_name = "apb2-clock",
611
+ },
612
+ [NPCM7XX_CLOCK_APB3_DIVIDER] = {
613
+ .name = "apb3-divider",
614
+ .src_type = CLKSRC_DIV,
615
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
616
+ .divide = shift_by_reg_divisor,
617
+ .reg = NPCM7XX_CLK_CLKDIV2,
618
+ .offset = 28,
619
+ .len = 2,
620
+ .public_name = "apb3-clock",
621
+ },
622
+ [NPCM7XX_CLOCK_APB4_DIVIDER] = {
623
+ .name = "apb4-divider",
624
+ .src_type = CLKSRC_DIV,
625
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
626
+ .divide = shift_by_reg_divisor,
627
+ .reg = NPCM7XX_CLK_CLKDIV2,
628
+ .offset = 30,
629
+ .len = 2,
630
+ .public_name = "apb4-clock",
631
+ },
632
+ [NPCM7XX_CLOCK_APB5_DIVIDER] = {
633
+ .name = "apb5-divider",
634
+ .src_type = CLKSRC_DIV,
635
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
636
+ .divide = shift_by_reg_divisor,
637
+ .reg = NPCM7XX_CLK_CLKDIV2,
638
+ .offset = 22,
639
+ .len = 2,
640
+ .public_name = "apb5-clock",
641
+ },
642
+ [NPCM7XX_CLOCK_CLKOUT_DIVIDER] = {
643
+ .name = "clkout-divider",
644
+ .src_type = CLKSRC_SEL,
645
+ .src_index = NPCM7XX_CLOCK_CLKOUTSEL,
646
+ .divide = divide_by_reg_divisor,
647
+ .reg = NPCM7XX_CLK_CLKDIV2,
648
+ .offset = 16,
649
+ .len = 5,
650
+ .public_name = "clkout",
651
+ },
652
+ [NPCM7XX_CLOCK_UART_DIVIDER] = {
653
+ .name = "uart-divider",
654
+ .src_type = CLKSRC_SEL,
655
+ .src_index = NPCM7XX_CLOCK_UARTCKSEL,
656
+ .divide = divide_by_reg_divisor,
657
+ .reg = NPCM7XX_CLK_CLKDIV1,
658
+ .offset = 16,
659
+ .len = 5,
660
+ .public_name = "uart-clock",
661
+ },
662
+ [NPCM7XX_CLOCK_TIMER_DIVIDER] = {
663
+ .name = "timer-divider",
664
+ .src_type = CLKSRC_SEL,
665
+ .src_index = NPCM7XX_CLOCK_TIMCKSEL,
666
+ .divide = divide_by_reg_divisor,
667
+ .reg = NPCM7XX_CLK_CLKDIV1,
668
+ .offset = 21,
669
+ .len = 5,
670
+ .public_name = "timer-clock",
671
+ },
672
+ [NPCM7XX_CLOCK_ADC_DIVIDER] = {
673
+ .name = "adc-divider",
674
+ .src_type = CLKSRC_DIV,
675
+ .src_index = NPCM7XX_CLOCK_TIMER_DIVIDER,
676
+ .divide = shift_by_reg_divisor,
677
+ .reg = NPCM7XX_CLK_CLKDIV1,
678
+ .offset = 28,
679
+ .len = 3,
680
+ .public_name = "adc-clock",
681
+ },
682
+ [NPCM7XX_CLOCK_MMC_DIVIDER] = {
683
+ .name = "mmc-divider",
684
+ .src_type = CLKSRC_SEL,
685
+ .src_index = NPCM7XX_CLOCK_SDCKSEL,
686
+ .divide = divide_by_reg_divisor,
687
+ .reg = NPCM7XX_CLK_CLKDIV1,
688
+ .offset = 11,
689
+ .len = 5,
690
+ .public_name = "mmc-clock",
691
+ },
692
+ [NPCM7XX_CLOCK_SDHC_DIVIDER] = {
693
+ .name = "sdhc-divider",
694
+ .src_type = CLKSRC_SEL,
695
+ .src_index = NPCM7XX_CLOCK_SDCKSEL,
696
+ .divide = divide_by_reg_divisor_times_2,
697
+ .reg = NPCM7XX_CLK_CLKDIV2,
698
+ .offset = 0,
699
+ .len = 4,
700
+ .public_name = "sdhc-clock",
701
+ },
702
+ [NPCM7XX_CLOCK_GFXM_DIVIDER] = {
703
+ .name = "gfxm-divider",
704
+ .src_type = CLKSRC_SEL,
705
+ .src_index = NPCM7XX_CLOCK_GFXMSEL,
706
+ .divide = divide_by_constant,
707
+ .divisor = 3,
708
+ .public_name = "gfxm-clock",
709
+ },
710
+ [NPCM7XX_CLOCK_UTMI_DIVIDER] = {
711
+ .name = "utmi-divider",
712
+ .src_type = CLKSRC_SEL,
713
+ .src_index = NPCM7XX_CLOCK_SUCKSEL,
714
+ .divide = divide_by_reg_divisor,
715
+ .reg = NPCM7XX_CLK_CLKDIV2,
716
+ .offset = 8,
717
+ .len = 5,
718
+ .public_name = "utmi-clock",
719
+ },
720
+};
721
+
722
+static void npcm7xx_clk_pll_init(Object *obj)
723
+{
724
+ NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj);
725
+
726
+ pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in",
727
+ npcm7xx_clk_update_pll, pll);
728
+ pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out");
729
+}
730
+
731
+static void npcm7xx_clk_sel_init(Object *obj)
732
+{
733
+ int i;
734
+ NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj);
735
+
736
+ for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) {
737
+ sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel),
738
+ g_strdup_printf("clock-in[%d]", i),
739
+ npcm7xx_clk_update_sel, sel);
740
+ }
741
+ sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out");
742
+}
743
+static void npcm7xx_clk_divider_init(Object *obj)
744
+{
745
+ NPCM7xxClockDividerState *div = NPCM7XX_CLOCK_DIVIDER(obj);
746
+
747
+ div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in",
748
+ npcm7xx_clk_update_divider, div);
749
+ div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out");
750
+}
751
+
752
+static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
753
+ NPCM7xxCLKState *clk, const PLLInitInfo *init_info)
754
+{
755
+ pll->name = init_info->name;
756
+ pll->clk = clk;
757
+ pll->reg = init_info->reg;
758
+ if (init_info->public_name != NULL) {
759
+ qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk),
760
+ init_info->public_name);
761
+ }
762
+}
763
+
764
+static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
765
+ NPCM7xxCLKState *clk, const SELInitInfo *init_info)
766
+{
767
+ int input_size = init_info->input_size;
768
+
769
+ sel->name = init_info->name;
770
+ sel->clk = clk;
771
+ sel->input_size = init_info->input_size;
772
+ g_assert(input_size <= NPCM7XX_CLK_SEL_MAX_INPUT);
773
+ sel->offset = init_info->offset;
774
+ sel->len = init_info->len;
775
+ if (init_info->public_name != NULL) {
776
+ qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk),
777
+ init_info->public_name);
778
+ }
779
+}
780
+
781
+static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
782
+ NPCM7xxCLKState *clk, const DividerInitInfo *init_info)
783
+{
784
+ div->name = init_info->name;
785
+ div->clk = clk;
786
+
787
+ div->divide = init_info->divide;
788
+ if (div->divide == divide_by_constant) {
789
+ div->divisor = init_info->divisor;
790
+ } else {
791
+ div->reg = init_info->reg;
792
+ div->offset = init_info->offset;
793
+ div->len = init_info->len;
794
+ }
795
+ if (init_info->public_name != NULL) {
796
+ qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk),
797
+ init_info->public_name);
798
+ }
799
+}
800
+
801
+static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
802
+ int index)
803
+{
804
+ switch (type) {
805
+ case CLKSRC_REF:
806
+ return clk->clkref;
807
+ case CLKSRC_PLL:
808
+ return clk->plls[index].clock_out;
809
+ case CLKSRC_SEL:
810
+ return clk->sels[index].clock_out;
811
+ case CLKSRC_DIV:
812
+ return clk->dividers[index].clock_out;
813
+ default:
814
+ g_assert_not_reached();
815
+ }
816
+}
817
+
818
+static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
819
+{
820
+ int i, j;
821
+ Clock *src;
822
+
823
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
824
+ src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type,
825
+ pll_init_info_list[i].src_index);
826
+ clock_set_source(clk->plls[i].clock_in, src);
827
+ }
828
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
829
+ for (j = 0; j < sel_init_info_list[i].input_size; ++j) {
830
+ src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j],
831
+ sel_init_info_list[i].src_index[j]);
832
+ clock_set_source(clk->sels[i].clock_in[j], src);
245
+ }
833
+ }
246
+ size = d.pktsize & PKT_SIZE;
834
+ }
247
+ address_space_read(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED,
835
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
248
+ buf, size);
836
+ src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type,
249
+ /*
837
+ divider_init_info_list[i].src_index);
250
+ * This is very basic way to send packets. Ideally there should be
838
+ clock_set_source(clk->dividers[i].clock_in, src);
251
+ * a FIFO and packets should be sent out from FIFO only when
839
+ }
252
+ * R_CFG1 bit 0 is set.
840
+}
253
+ */
841
+
254
+ if (s->regs[R_CFG1] & R_CFG1_LB_EN_MASK) {
842
static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
255
+ nc->info->receive(nc, buf, size);
843
{
256
+ } else {
844
uint32_t reg = offset / sizeof(uint32_t);
257
+ qemu_send_packet(nc, buf, size);
845
@@ -XXX,XX +XXX,XX @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
258
+ }
846
*
259
+ d.pktsize |= EMPTY_MASK;
847
* The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000.
260
+ emac_store_desc(s, &d, desc);
848
*/
261
+ /* update sent packets count */
849
- value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ;
262
+ status = s->regs[R_DMA_TX_STATUS];
850
+ value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ;
263
+ pktcnt = FIELD_EX32(status, DMA_TX_STATUS, PKTCNT);
851
break;
264
+ pktcnt++;
852
265
+ s->regs[R_DMA_TX_STATUS] = FIELD_DP32(status, DMA_TX_STATUS,
853
default:
266
+ PKTCNT, pktcnt);
854
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
267
+ s->regs[R_DMA_TX_STATUS] |= R_DMA_TX_STATUS_PKT_SENT_MASK;
855
value |= (value & PLLCON_LOKS);
268
+ desc = d.next;
856
}
269
+ }
857
}
270
+ s->regs[R_DMA_TX_STATUS] |= R_DMA_TX_STATUS_UNDERRUN_MASK;
858
+ /* Only update PLL when it is locked. */
271
+ s->regs[R_DMA_TX_CTL] &= ~R_DMA_TX_CTL_EN_MASK;
859
+ if (value & PLLCON_LOKI) {
272
+}
860
+ npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]);
273
+
274
+static void msf2_phy_update_link(MSF2EmacState *s)
275
+{
276
+ /* Autonegotiation status mirrors link status. */
277
+ if (qemu_get_queue(s->nic)->link_down) {
278
+ s->phy_regs[MII_BMSR] &= ~(MII_BMSR_AN_COMP |
279
+ MII_BMSR_LINK_ST);
280
+ } else {
281
+ s->phy_regs[MII_BMSR] |= (MII_BMSR_AN_COMP |
282
+ MII_BMSR_LINK_ST);
283
+ }
284
+}
285
+
286
+static void msf2_phy_reset(MSF2EmacState *s)
287
+{
288
+ memset(&s->phy_regs[0], 0, sizeof(s->phy_regs));
289
+ s->phy_regs[MII_BMCR] = 0x1140;
290
+ s->phy_regs[MII_BMSR] = 0x7968;
291
+ s->phy_regs[MII_PHYID1] = 0x0022;
292
+ s->phy_regs[MII_PHYID2] = 0x1550;
293
+ s->phy_regs[MII_ANAR] = 0x01E1;
294
+ s->phy_regs[MII_ANLPAR] = 0xCDE1;
295
+
296
+ msf2_phy_update_link(s);
297
+}
298
+
299
+static void write_to_phy(MSF2EmacState *s)
300
+{
301
+ uint8_t reg_addr = s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK;
302
+ uint8_t phy_addr = (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT) &
303
+ R_MII_ADDR_REGADDR_MASK;
304
+ uint16_t data = s->regs[R_MII_CTL] & 0xFFFF;
305
+
306
+ if (phy_addr != PHYADDR) {
307
+ return;
308
+ }
309
+
310
+ switch (reg_addr) {
311
+ case MII_BMCR:
312
+ if (data & MII_BMCR_RESET) {
313
+ /* Phy reset */
314
+ msf2_phy_reset(s);
315
+ data &= ~MII_BMCR_RESET;
316
+ }
317
+ if (data & MII_BMCR_AUTOEN) {
318
+ /* Complete autonegotiation immediately */
319
+ data &= ~MII_BMCR_AUTOEN;
320
+ s->phy_regs[MII_BMSR] |= MII_BMSR_AN_COMP;
321
+ }
861
+ }
322
+ break;
862
+ break;
323
+ }
863
+
324
+
864
+ case NPCM7XX_CLK_CLKSEL:
325
+ s->phy_regs[reg_addr] = data;
865
+ npcm7xx_clk_update_all_sels(s);
326
+}
327
+
328
+static uint16_t read_from_phy(MSF2EmacState *s)
329
+{
330
+ uint8_t reg_addr = s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK;
331
+ uint8_t phy_addr = (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT) &
332
+ R_MII_ADDR_REGADDR_MASK;
333
+
334
+ if (phy_addr == PHYADDR) {
335
+ return s->phy_regs[reg_addr];
336
+ } else {
337
+ return 0xFFFF;
338
+ }
339
+}
340
+
341
+static void msf2_emac_do_reset(MSF2EmacState *s)
342
+{
343
+ memset(&s->regs[0], 0, sizeof(s->regs));
344
+ s->regs[R_CFG1] = 0x80000000;
345
+ s->regs[R_CFG2] = 0x00007000;
346
+ s->regs[R_IFG] = 0x40605060;
347
+ s->regs[R_HALF_DUPLEX] = 0x00A1F037;
348
+ s->regs[R_MAX_FRAME_LENGTH] = 0x00000600;
349
+ s->regs[R_FIFO_CFG5] = 0X3FFFF;
350
+
351
+ msf2_phy_reset(s);
352
+}
353
+
354
+static uint64_t emac_read(void *opaque, hwaddr addr, unsigned int size)
355
+{
356
+ MSF2EmacState *s = opaque;
357
+ uint32_t r = 0;
358
+
359
+ addr >>= 2;
360
+
361
+ switch (addr) {
362
+ case R_DMA_IRQ:
363
+ r = emac_get_isr(s);
364
+ break;
866
+ break;
365
+ default:
867
+
366
+ if (addr >= ARRAY_SIZE(s->regs)) {
868
+ case NPCM7XX_CLK_CLKDIV1:
367
+ qemu_log_mask(LOG_GUEST_ERROR,
869
+ case NPCM7XX_CLK_CLKDIV2:
368
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
870
+ case NPCM7XX_CLK_CLKDIV3:
369
+ addr * 4);
871
+ npcm7xx_clk_update_all_dividers(s);
370
+ return r;
872
break;
371
+ }
873
372
+ r = s->regs[addr];
874
case NPCM7XX_CLK_CNTR25M:
373
+ break;
875
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
374
+ }
876
case RESET_TYPE_COLD:
375
+ return r;
877
memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
376
+}
878
s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
377
+
879
+ npcm7xx_clk_update_all_clocks(s);
378
+static void emac_write(void *opaque, hwaddr addr, uint64_t val64,
880
return;
379
+ unsigned int size)
881
}
380
+{
882
381
+ MSF2EmacState *s = opaque;
883
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
382
+ uint32_t value = val64;
884
__func__, type);
383
+ uint32_t enreqbits;
885
}
384
+ uint8_t pktcnt;
886
385
+
887
+static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
386
+ addr >>= 2;
888
+{
387
+ switch (addr) {
889
+ int i;
388
+ case R_DMA_TX_CTL:
890
+
389
+ s->regs[addr] = value;
891
+ s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL);
390
+ if (value & R_DMA_TX_CTL_EN_MASK) {
892
+
391
+ msf2_dma_tx(s);
893
+ /* First pass: init all converter modules */
392
+ }
894
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) != NPCM7XX_CLOCK_NR_PLLS);
393
+ break;
895
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(sel_init_info_list) != NPCM7XX_CLOCK_NR_SELS);
394
+ case R_DMA_RX_CTL:
896
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(divider_init_info_list)
395
+ s->regs[addr] = value;
897
+ != NPCM7XX_CLOCK_NR_DIVIDERS);
396
+ if (value & R_DMA_RX_CTL_EN_MASK) {
898
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
397
+ s->rx_desc = s->regs[R_DMA_RX_DESC];
899
+ object_initialize_child(OBJECT(s), pll_init_info_list[i].name,
398
+ qemu_flush_queued_packets(qemu_get_queue(s->nic));
900
+ &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL);
399
+ }
901
+ npcm7xx_init_clock_pll(&s->plls[i], s,
400
+ break;
902
+ &pll_init_info_list[i]);
401
+ case R_CFG1:
903
+ }
402
+ s->regs[addr] = value;
904
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
403
+ if (value & R_CFG1_RESET_MASK) {
905
+ object_initialize_child(OBJECT(s), sel_init_info_list[i].name,
404
+ msf2_emac_do_reset(s);
906
+ &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL);
405
+ }
907
+ npcm7xx_init_clock_sel(&s->sels[i], s,
406
+ break;
908
+ &sel_init_info_list[i]);
407
+ case R_FIFO_CFG0:
909
+ }
408
+ /*
910
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
409
+ * For our implementation, turning on modules is instantaneous,
911
+ object_initialize_child(OBJECT(s), divider_init_info_list[i].name,
410
+ * so the states requested via the *ENREQ bits appear in the
912
+ &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER);
411
+ * *ENRPLY bits immediately. Also the reset bits to reset PE-MCXMAC
913
+ npcm7xx_init_clock_divider(&s->dividers[i], s,
412
+ * module are not emulated here since it deals with start of frames,
914
+ &divider_init_info_list[i]);
413
+ * inter-packet gap and control frames.
915
+ }
414
+ */
916
+
415
+ enreqbits = extract32(value, 8, 5);
917
+ /* Second pass: connect converter modules */
416
+ s->regs[addr] = deposit32(value, 16, 5, enreqbits);
918
+ npcm7xx_connect_clocks(s);
417
+ break;
919
+
418
+ case R_DMA_TX_DESC:
920
+ clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ);
419
+ if (value & 0x3) {
921
+}
420
+ qemu_log_mask(LOG_GUEST_ERROR, "Tx Descriptor address should be"
922
+
421
+ " 32 bit aligned\n");
923
static void npcm7xx_clk_init(Object *obj)
422
+ }
924
{
423
+ /* Ignore [1:0] bits */
925
NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
424
+ s->regs[addr] = value & ~3;
926
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
425
+ break;
927
memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
426
+ case R_DMA_RX_DESC:
928
TYPE_NPCM7XX_CLK, 4 * KiB);
427
+ if (value & 0x3) {
929
sysbus_init_mmio(&s->parent, &s->iomem);
428
+ qemu_log_mask(LOG_GUEST_ERROR, "Rx Descriptor address should be"
930
- qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
429
+ " 32 bit aligned\n");
931
- NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
430
+ }
932
}
431
+ /* Ignore [1:0] bits */
933
432
+ s->regs[addr] = value & ~3;
934
-static const VMStateDescription vmstate_npcm7xx_clk = {
433
+ break;
935
- .name = "npcm7xx-clk",
434
+ case R_DMA_TX_STATUS:
936
+static int npcm7xx_clk_post_load(void *opaque, int version_id)
435
+ if (value & R_DMA_TX_STATUS_UNDERRUN_MASK) {
937
+{
436
+ s->regs[addr] &= ~R_DMA_TX_STATUS_UNDERRUN_MASK;
938
+ if (version_id >= 1) {
437
+ }
939
+ NPCM7xxCLKState *clk = opaque;
438
+ if (value & R_DMA_TX_STATUS_PKT_SENT_MASK) {
940
+
439
+ pktcnt = FIELD_EX32(s->regs[addr], DMA_TX_STATUS, PKTCNT);
941
+ npcm7xx_clk_update_all_clocks(clk);
440
+ pktcnt--;
942
+ }
441
+ s->regs[addr] = FIELD_DP32(s->regs[addr], DMA_TX_STATUS,
943
+
442
+ PKTCNT, pktcnt);
944
+ return 0;
443
+ if (pktcnt == 0) {
945
+}
444
+ s->regs[addr] &= ~R_DMA_TX_STATUS_PKT_SENT_MASK;
946
+
445
+ }
947
+static void npcm7xx_clk_realize(DeviceState *dev, Error **errp)
446
+ }
948
+{
447
+ break;
949
+ int i;
448
+ case R_DMA_RX_STATUS:
950
+ NPCM7xxCLKState *s = NPCM7XX_CLK(dev);
449
+ if (value & R_DMA_RX_STATUS_OVERFLOW_MASK) {
951
+
450
+ s->regs[addr] &= ~R_DMA_RX_STATUS_OVERFLOW_MASK;
952
+ qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
451
+ }
953
+ NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
452
+ if (value & R_DMA_RX_STATUS_PKT_RCVD_MASK) {
954
+ npcm7xx_clk_init_clock_hierarchy(s);
453
+ pktcnt = FIELD_EX32(s->regs[addr], DMA_RX_STATUS, PKTCNT);
955
+
454
+ pktcnt--;
956
+ /* Realize child devices */
455
+ s->regs[addr] = FIELD_DP32(s->regs[addr], DMA_RX_STATUS,
957
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
456
+ PKTCNT, pktcnt);
958
+ if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) {
457
+ if (pktcnt == 0) {
458
+ s->regs[addr] &= ~R_DMA_RX_STATUS_PKT_RCVD_MASK;
459
+ }
460
+ }
461
+ break;
462
+ case R_DMA_IRQ:
463
+ break;
464
+ case R_MII_CMD:
465
+ if (value & R_MII_CMD_READ_MASK) {
466
+ s->regs[R_MII_STS] = read_from_phy(s);
467
+ }
468
+ break;
469
+ case R_MII_CTL:
470
+ s->regs[addr] = value;
471
+ write_to_phy(s);
472
+ break;
473
+ case R_STA1:
474
+ s->regs[addr] = value;
475
+ /*
476
+ * R_STA1 [31:24] : octet 1 of mac address
477
+ * R_STA1 [23:16] : octet 2 of mac address
478
+ * R_STA1 [15:8] : octet 3 of mac address
479
+ * R_STA1 [7:0] : octet 4 of mac address
480
+ */
481
+ stl_be_p(s->mac_addr, value);
482
+ break;
483
+ case R_STA2:
484
+ s->regs[addr] = value;
485
+ /*
486
+ * R_STA2 [31:24] : octet 5 of mac address
487
+ * R_STA2 [23:16] : octet 6 of mac address
488
+ */
489
+ stw_be_p(s->mac_addr + 4, value >> 16);
490
+ break;
491
+ default:
492
+ if (addr >= ARRAY_SIZE(s->regs)) {
493
+ qemu_log_mask(LOG_GUEST_ERROR,
494
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
495
+ addr * 4);
496
+ return;
959
+ return;
497
+ }
960
+ }
498
+ s->regs[addr] = value;
961
+ }
499
+ break;
962
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
500
+ }
963
+ if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) {
501
+ emac_update_irq(s);
964
+ return;
502
+}
965
+ }
503
+
966
+ }
504
+static const MemoryRegionOps emac_ops = {
967
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
505
+ .read = emac_read,
968
+ if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) {
506
+ .write = emac_write,
969
+ return;
507
+ .endianness = DEVICE_NATIVE_ENDIAN,
970
+ }
508
+ .impl = {
971
+ }
509
+ .min_access_size = 4,
972
+}
510
+ .max_access_size = 4
973
+
511
+ }
974
+static const VMStateDescription vmstate_npcm7xx_clk_pll = {
975
+ .name = "npcm7xx-clock-pll",
976
.version_id = 0,
977
.minimum_version_id = 0,
978
- .fields = (VMStateField[]) {
979
- VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
980
- VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
981
+ .fields = (VMStateField[]) {
982
+ VMSTATE_CLOCK(clock_in, NPCM7xxClockPLLState),
983
VMSTATE_END_OF_LIST(),
984
},
985
};
986
987
+static const VMStateDescription vmstate_npcm7xx_clk_sel = {
988
+ .name = "npcm7xx-clock-sel",
989
+ .version_id = 0,
990
+ .minimum_version_id = 0,
991
+ .fields = (VMStateField[]) {
992
+ VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(clock_in, NPCM7xxClockSELState,
993
+ NPCM7XX_CLK_SEL_MAX_INPUT, 0, vmstate_clock, Clock),
994
+ VMSTATE_END_OF_LIST(),
995
+ },
512
+};
996
+};
513
+
997
+
514
+static bool emac_can_rx(NetClientState *nc)
998
+static const VMStateDescription vmstate_npcm7xx_clk_divider = {
515
+{
999
+ .name = "npcm7xx-clock-divider",
516
+ MSF2EmacState *s = qemu_get_nic_opaque(nc);
1000
+ .version_id = 0,
517
+
1001
+ .minimum_version_id = 0,
518
+ return (s->regs[R_CFG1] & R_CFG1_RX_EN_MASK) &&
1002
+ .fields = (VMStateField[]) {
519
+ (s->regs[R_DMA_RX_CTL] & R_DMA_RX_CTL_EN_MASK);
1003
+ VMSTATE_CLOCK(clock_in, NPCM7xxClockDividerState),
520
+}
1004
+ VMSTATE_END_OF_LIST(),
521
+
1005
+ },
522
+static bool addr_filter_ok(MSF2EmacState *s, const uint8_t *buf)
523
+{
524
+ /* The broadcast MAC address: FF:FF:FF:FF:FF:FF */
525
+ const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF,
526
+ 0xFF, 0xFF };
527
+ bool bcast_en = true;
528
+ bool mcast_en = true;
529
+
530
+ if (s->regs[R_FIFO_CFG5] & R_FIFO_CFG5_BCAST_MASK) {
531
+ bcast_en = true; /* Broadcast dont care for drop circuitry */
532
+ } else if (s->regs[R_FIFO_CFG4] & R_FIFO_CFG4_BCAST_MASK) {
533
+ bcast_en = false;
534
+ }
535
+
536
+ if (s->regs[R_FIFO_CFG5] & R_FIFO_CFG5_MCAST_MASK) {
537
+ mcast_en = true; /* Multicast dont care for drop circuitry */
538
+ } else if (s->regs[R_FIFO_CFG4] & R_FIFO_CFG4_MCAST_MASK) {
539
+ mcast_en = false;
540
+ }
541
+
542
+ if (!memcmp(buf, broadcast_addr, sizeof(broadcast_addr))) {
543
+ return bcast_en;
544
+ }
545
+
546
+ if (buf[0] & 1) {
547
+ return mcast_en;
548
+ }
549
+
550
+ return !memcmp(buf, s->mac_addr, sizeof(s->mac_addr));
551
+}
552
+
553
+static ssize_t emac_rx(NetClientState *nc, const uint8_t *buf, size_t size)
554
+{
555
+ MSF2EmacState *s = qemu_get_nic_opaque(nc);
556
+ EmacDesc d;
557
+ uint8_t pktcnt;
558
+ uint32_t status;
559
+
560
+ if (size > (s->regs[R_MAX_FRAME_LENGTH] & 0xFFFF)) {
561
+ return size;
562
+ }
563
+ if (!addr_filter_ok(s, buf)) {
564
+ return size;
565
+ }
566
+
567
+ emac_load_desc(s, &d, s->rx_desc);
568
+
569
+ if (d.pktsize & EMPTY_MASK) {
570
+ address_space_write(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED,
571
+ buf, size & PKT_SIZE);
572
+ d.pktsize = size & PKT_SIZE;
573
+ emac_store_desc(s, &d, s->rx_desc);
574
+ /* update received packets count */
575
+ status = s->regs[R_DMA_RX_STATUS];
576
+ pktcnt = FIELD_EX32(status, DMA_RX_STATUS, PKTCNT);
577
+ pktcnt++;
578
+ s->regs[R_DMA_RX_STATUS] = FIELD_DP32(status, DMA_RX_STATUS,
579
+ PKTCNT, pktcnt);
580
+ s->regs[R_DMA_RX_STATUS] |= R_DMA_RX_STATUS_PKT_RCVD_MASK;
581
+ s->rx_desc = d.next;
582
+ } else {
583
+ s->regs[R_DMA_RX_CTL] &= ~R_DMA_RX_CTL_EN_MASK;
584
+ s->regs[R_DMA_RX_STATUS] |= R_DMA_RX_STATUS_OVERFLOW_MASK;
585
+ }
586
+ emac_update_irq(s);
587
+ return size;
588
+}
589
+
590
+static void msf2_emac_reset(DeviceState *dev)
591
+{
592
+ MSF2EmacState *s = MSS_EMAC(dev);
593
+
594
+ msf2_emac_do_reset(s);
595
+}
596
+
597
+static void emac_set_link(NetClientState *nc)
598
+{
599
+ MSF2EmacState *s = qemu_get_nic_opaque(nc);
600
+
601
+ msf2_phy_update_link(s);
602
+}
603
+
604
+static NetClientInfo net_msf2_emac_info = {
605
+ .type = NET_CLIENT_DRIVER_NIC,
606
+ .size = sizeof(NICState),
607
+ .can_receive = emac_can_rx,
608
+ .receive = emac_rx,
609
+ .link_status_changed = emac_set_link,
610
+};
1006
+};
611
+
1007
+
612
+static void msf2_emac_realize(DeviceState *dev, Error **errp)
1008
+static const VMStateDescription vmstate_npcm7xx_clk = {
613
+{
1009
+ .name = "npcm7xx-clk",
614
+ MSF2EmacState *s = MSS_EMAC(dev);
615
+
616
+ if (!s->dma_mr) {
617
+ error_setg(errp, "MSS_EMAC 'ahb-bus' link not set");
618
+ return;
619
+ }
620
+
621
+ address_space_init(&s->dma_as, s->dma_mr, "emac-ahb");
622
+
623
+ qemu_macaddr_default_if_unset(&s->conf.macaddr);
624
+ s->nic = qemu_new_nic(&net_msf2_emac_info, &s->conf,
625
+ object_get_typename(OBJECT(dev)), dev->id, s);
626
+ qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
627
+}
628
+
629
+static void msf2_emac_init(Object *obj)
630
+{
631
+ MSF2EmacState *s = MSS_EMAC(obj);
632
+
633
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
634
+
635
+ memory_region_init_io(&s->mmio, obj, &emac_ops, s,
636
+ "msf2-emac", R_MAX * 4);
637
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
638
+}
639
+
640
+static Property msf2_emac_properties[] = {
641
+ DEFINE_PROP_LINK("ahb-bus", MSF2EmacState, dma_mr,
642
+ TYPE_MEMORY_REGION, MemoryRegion *),
643
+ DEFINE_NIC_PROPERTIES(MSF2EmacState, conf),
644
+ DEFINE_PROP_END_OF_LIST(),
645
+};
646
+
647
+static const VMStateDescription vmstate_msf2_emac = {
648
+ .name = TYPE_MSS_EMAC,
649
+ .version_id = 1,
1010
+ .version_id = 1,
650
+ .minimum_version_id = 1,
1011
+ .minimum_version_id = 1,
1012
+ .post_load = npcm7xx_clk_post_load,
651
+ .fields = (VMStateField[]) {
1013
+ .fields = (VMStateField[]) {
652
+ VMSTATE_UINT8_ARRAY(mac_addr, MSF2EmacState, ETH_ALEN),
1014
+ VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
653
+ VMSTATE_UINT32(rx_desc, MSF2EmacState),
1015
+ VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
654
+ VMSTATE_UINT16_ARRAY(phy_regs, MSF2EmacState, PHY_MAX_REGS),
1016
+ VMSTATE_CLOCK(clkref, NPCM7xxCLKState),
655
+ VMSTATE_UINT32_ARRAY(regs, MSF2EmacState, R_MAX),
1017
+ VMSTATE_END_OF_LIST(),
656
+ VMSTATE_END_OF_LIST()
1018
+ },
657
+ }
658
+};
1019
+};
659
+
1020
+
660
+static void msf2_emac_class_init(ObjectClass *klass, void *data)
1021
+static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data)
661
+{
1022
+{
662
+ DeviceClass *dc = DEVICE_CLASS(klass);
1023
+ DeviceClass *dc = DEVICE_CLASS(klass);
663
+
1024
+
664
+ dc->realize = msf2_emac_realize;
1025
+ dc->desc = "NPCM7xx Clock PLL Module";
665
+ dc->reset = msf2_emac_reset;
1026
+ dc->vmsd = &vmstate_npcm7xx_clk_pll;
666
+ dc->vmsd = &vmstate_msf2_emac;
1027
+}
667
+ device_class_set_props(dc, msf2_emac_properties);
1028
+
668
+}
1029
+static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data)
669
+
1030
+{
670
+static const TypeInfo msf2_emac_info = {
1031
+ DeviceClass *dc = DEVICE_CLASS(klass);
671
+ .name = TYPE_MSS_EMAC,
1032
+
672
+ .parent = TYPE_SYS_BUS_DEVICE,
1033
+ dc->desc = "NPCM7xx Clock SEL Module";
673
+ .instance_size = sizeof(MSF2EmacState),
1034
+ dc->vmsd = &vmstate_npcm7xx_clk_sel;
674
+ .instance_init = msf2_emac_init,
1035
+}
675
+ .class_init = msf2_emac_class_init,
1036
+
1037
+static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
1038
+{
1039
+ DeviceClass *dc = DEVICE_CLASS(klass);
1040
+
1041
+ dc->desc = "NPCM7xx Clock Divider Module";
1042
+ dc->vmsd = &vmstate_npcm7xx_clk_divider;
1043
+}
1044
+
1045
static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
1046
{
1047
ResettableClass *rc = RESETTABLE_CLASS(klass);
1048
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
1049
1050
dc->desc = "NPCM7xx Clock Control Registers";
1051
dc->vmsd = &vmstate_npcm7xx_clk;
1052
+ dc->realize = npcm7xx_clk_realize;
1053
rc->phases.enter = npcm7xx_clk_enter_reset;
1054
}
1055
1056
+static const TypeInfo npcm7xx_clk_pll_info = {
1057
+ .name = TYPE_NPCM7XX_CLOCK_PLL,
1058
+ .parent = TYPE_DEVICE,
1059
+ .instance_size = sizeof(NPCM7xxClockPLLState),
1060
+ .instance_init = npcm7xx_clk_pll_init,
1061
+ .class_init = npcm7xx_clk_pll_class_init,
676
+};
1062
+};
677
+
1063
+
678
+static void msf2_emac_register_types(void)
1064
+static const TypeInfo npcm7xx_clk_sel_info = {
679
+{
1065
+ .name = TYPE_NPCM7XX_CLOCK_SEL,
680
+ type_register_static(&msf2_emac_info);
1066
+ .parent = TYPE_DEVICE,
681
+}
1067
+ .instance_size = sizeof(NPCM7xxClockSELState),
682
+
1068
+ .instance_init = npcm7xx_clk_sel_init,
683
+type_init(msf2_emac_register_types)
1069
+ .class_init = npcm7xx_clk_sel_class_init,
684
diff --git a/MAINTAINERS b/MAINTAINERS
1070
+};
685
index XXXXXXX..XXXXXXX 100644
1071
+
686
--- a/MAINTAINERS
1072
+static const TypeInfo npcm7xx_clk_divider_info = {
687
+++ b/MAINTAINERS
1073
+ .name = TYPE_NPCM7XX_CLOCK_DIVIDER,
688
@@ -XXX,XX +XXX,XX @@ F: include/hw/arm/msf2-soc.h
1074
+ .parent = TYPE_DEVICE,
689
F: include/hw/misc/msf2-sysreg.h
1075
+ .instance_size = sizeof(NPCM7xxClockDividerState),
690
F: include/hw/timer/mss-timer.h
1076
+ .instance_init = npcm7xx_clk_divider_init,
691
F: include/hw/ssi/mss-spi.h
1077
+ .class_init = npcm7xx_clk_divider_class_init,
692
+F: hw/net/msf2-emac.c
1078
+};
693
+F: include/hw/net/msf2-emac.h
1079
+
694
1080
static const TypeInfo npcm7xx_clk_info = {
695
Emcraft M2S-FG484
1081
.name = TYPE_NPCM7XX_CLK,
696
M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1082
.parent = TYPE_SYS_BUS_DEVICE,
1083
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_clk_info = {
1084
1085
static void npcm7xx_clk_register_type(void)
1086
{
1087
+ type_register_static(&npcm7xx_clk_pll_info);
1088
+ type_register_static(&npcm7xx_clk_sel_info);
1089
+ type_register_static(&npcm7xx_clk_divider_info);
1090
type_register_static(&npcm7xx_clk_info);
1091
}
1092
type_init(npcm7xx_clk_register_type);
697
--
1093
--
698
2.20.1
1094
2.20.1
699
1095
700
1096
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
Under KVM these registers are written by the hardware.
3
This patch makes NPCM7XX Timer to use a the timer clock generated by the
4
Restrict the writefn handlers to TCG to avoid when building
4
CLK module instead of the magic number TIMER_REF_HZ.
5
without TCG:
6
5
7
LINK aarch64-softmmu/qemu-system-aarch64
6
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
8
target/arm/helper.o: In function `do_ats_write':
7
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
9
target/arm/helper.c:3524: undefined reference to `raise_exception'
8
Signed-off-by: Hao Wu <wuhaotsh@google.com>
10
9
Message-id: 20210108190945.949196-3-wuhaotsh@google.com
11
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Message-id: 20200423073358.27155-2-philmd@redhat.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
12
---
17
target/arm/helper.c | 17 +++++++++++++++++
13
include/hw/misc/npcm7xx_clk.h | 6 -----
18
1 file changed, 17 insertions(+)
14
include/hw/timer/npcm7xx_timer.h | 1 +
15
hw/arm/npcm7xx.c | 5 ++++
16
hw/timer/npcm7xx_timer.c | 39 +++++++++++++++-----------------
17
4 files changed, 24 insertions(+), 27 deletions(-)
19
18
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
19
diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
21
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper.c
21
--- a/include/hw/misc/npcm7xx_clk.h
23
+++ b/target/arm/helper.c
22
+++ b/include/hw/misc/npcm7xx_clk.h
24
@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
23
@@ -XXX,XX +XXX,XX @@
25
return CP_ACCESS_OK;
24
#include "hw/clock.h"
25
#include "hw/sysbus.h"
26
27
-/*
28
- * The reference clock frequency for the timer modules, and the SECCNT and
29
- * CNTR25M registers in this module, is always 25 MHz.
30
- */
31
-#define NPCM7XX_TIMER_REF_HZ (25000000)
32
-
33
/*
34
* Number of registers in our device state structure. Don't change this without
35
* incrementing the version_id in the vmstate.
36
diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/timer/npcm7xx_timer.h
39
+++ b/include/hw/timer/npcm7xx_timer.h
40
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState {
41
42
uint32_t tisr;
43
44
+ Clock *clock;
45
NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
46
NPCM7xxWatchdogTimer watchdog_timer;
47
};
48
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/arm/npcm7xx.c
51
+++ b/hw/arm/npcm7xx.c
52
@@ -XXX,XX +XXX,XX @@
53
#include "hw/char/serial.h"
54
#include "hw/loader.h"
55
#include "hw/misc/unimp.h"
56
+#include "hw/qdev-clock.h"
57
#include "hw/qdev-properties.h"
58
#include "qapi/error.h"
59
#include "qemu/units.h"
60
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
61
int first_irq;
62
int j;
63
64
+ /* Connect the timer clock. */
65
+ qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(
66
+ DEVICE(&s->clk), "timer-clock"));
67
+
68
sysbus_realize(sbd, &error_abort);
69
sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
70
71
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/hw/timer/npcm7xx_timer.c
74
+++ b/hw/timer/npcm7xx_timer.c
75
@@ -XXX,XX +XXX,XX @@
76
#include "qemu/osdep.h"
77
78
#include "hw/irq.h"
79
+#include "hw/qdev-clock.h"
80
#include "hw/qdev-properties.h"
81
-#include "hw/misc/npcm7xx_clk.h"
82
#include "hw/timer/npcm7xx_timer.h"
83
#include "migration/vmstate.h"
84
#include "qemu/bitops.h"
85
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)
86
/* Convert a timer cycle count to a time interval in nanoseconds. */
87
static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
88
{
89
- int64_t ns = count;
90
+ int64_t ticks = count;
91
92
- ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
93
- ns *= npcm7xx_tcsr_prescaler(t->tcsr);
94
+ ticks *= npcm7xx_tcsr_prescaler(t->tcsr);
95
96
- return ns;
97
+ return clock_ticks_to_ns(t->ctrl->clock, ticks);
26
}
98
}
27
99
28
+#ifdef CONFIG_TCG
100
/* Convert a time interval in nanoseconds to a timer cycle count. */
29
static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
101
static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
30
MMUAccessType access_type, ARMMMUIdx mmu_idx)
31
{
102
{
32
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
103
- int64_t count;
33
}
104
-
34
return par64;
105
- count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
106
- count /= npcm7xx_tcsr_prescaler(t->tcsr);
107
-
108
- return count;
109
+ return ns / clock_ticks_to_ns(t->ctrl->clock,
110
+ npcm7xx_tcsr_prescaler(t->tcsr));
35
}
111
}
36
+#endif /* CONFIG_TCG */
112
37
113
static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
38
static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
114
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
115
static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
116
int64_t cycles)
39
{
117
{
40
+#ifdef CONFIG_TCG
118
- uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
41
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
119
- int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
42
uint64_t par64;
120
+ int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t);
43
ARMMMUIdx mmu_idx;
121
+ int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks);
44
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
122
45
par64 = do_ats_write(env, value, access_type, mmu_idx);
123
/*
46
124
* The reset function always clears the current timer. The caller of the
47
A32_BANKED_CURRENT_REG_SET(env, par, par64);
125
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
48
+#else
126
*/
49
+ /* Handled by hardware accelerator. */
127
npcm7xx_timer_clear(&t->base_timer);
50
+ g_assert_not_reached();
128
51
+#endif /* CONFIG_TCG */
129
- ns *= prescaler;
130
t->base_timer.remaining_ns = ns;
52
}
131
}
53
132
54
static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
133
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj)
55
uint64_t value)
134
qemu_irq_lower(s->watchdog_timer.irq);
135
}
136
137
-static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
138
+static void npcm7xx_timer_init(Object *obj)
56
{
139
{
57
+#ifdef CONFIG_TCG
140
- NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
58
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
141
- SysBusDevice *sbd = &s->parent;
59
uint64_t par64;
142
+ NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
60
143
+ DeviceState *dev = DEVICE(obj);
61
par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2);
144
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
62
145
int i;
63
A32_BANKED_CURRENT_REG_SET(env, par, par64);
146
NPCM7xxWatchdogTimer *w;
64
+#else
147
65
+ /* Handled by hardware accelerator. */
148
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
66
+ g_assert_not_reached();
149
npcm7xx_watchdog_timer_expired, w);
67
+#endif /* CONFIG_TCG */
150
sysbus_init_irq(sbd, &w->irq);
151
152
- memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
153
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s,
154
TYPE_NPCM7XX_TIMER, 4 * KiB);
155
sysbus_init_mmio(sbd, &s->iomem);
156
qdev_init_gpio_out_named(dev, &w->reset_signal,
157
NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
158
+ s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL);
68
}
159
}
69
160
70
static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
161
static const VMStateDescription vmstate_npcm7xx_base_timer = {
71
@@ -XXX,XX +XXX,XX @@ static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
162
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
72
static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
163
73
uint64_t value)
164
static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
74
{
165
.name = "npcm7xx-timer-ctrl",
75
+#ifdef CONFIG_TCG
166
- .version_id = 1,
76
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
167
- .minimum_version_id = 1,
77
ARMMMUIdx mmu_idx;
168
+ .version_id = 2,
78
int secure = arm_is_secure_below_el3(env);
169
+ .minimum_version_id = 2,
79
@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
170
.fields = (VMStateField[]) {
80
}
171
VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
81
172
+ VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),
82
env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
173
VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
83
+#else
174
NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
84
+ /* Handled by hardware accelerator. */
175
NPCM7xxTimer),
85
+ g_assert_not_reached();
176
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
86
+#endif /* CONFIG_TCG */
177
QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
87
}
178
88
#endif
179
dc->desc = "NPCM7xx Timer Controller";
89
180
- dc->realize = npcm7xx_timer_realize;
181
dc->vmsd = &vmstate_npcm7xx_timer_ctrl;
182
rc->phases.enter = npcm7xx_timer_enter_reset;
183
rc->phases.hold = npcm7xx_timer_hold_reset;
184
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_timer_info = {
185
.parent = TYPE_SYS_BUS_DEVICE,
186
.instance_size = sizeof(NPCM7xxTimerCtrlState),
187
.class_init = npcm7xx_timer_class_init,
188
+ .instance_init = npcm7xx_timer_init,
189
};
190
191
static void npcm7xx_timer_register_type(void)
90
--
192
--
91
2.20.1
193
2.20.1
92
194
93
195
diff view generated by jsdifflib
1
This object may be used to represent a clock inside a clock tree.
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
A clock may be connected to another clock so that it receives update,
3
The ADC is part of NPCM7XX Module. Its behavior is controled by the
4
through a callback, whenever the source/parent clock is updated.
4
ADC_CON register. It converts one of the eight analog inputs into a
5
digital input and stores it in the ADC_DATA register when enabled.
5
6
6
Although only the root clock of a clock tree controls the values
7
Users can alter input value by using qom-set QMP command.
7
(represented as periods) of all clocks in tree, each clock holds
8
a local state containing the current value so that it can be fetched
9
independently. It will allows us to fullfill migration requirements
10
by migrating each clock independently of others.
11
8
12
This is based on the original work of Frederic Konrad.
9
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
13
10
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
14
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
11
Signed-off-by: Hao Wu <wuhaotsh@google.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-id: 20210108190945.949196-4-wuhaotsh@google.com
16
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
13
[PMM: Added missing hw/adc/trace.h file]
17
Message-id: 20200406135251.157596-2-damien.hedde@greensocs.com
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
[PMM: Use uint64_t rather than unsigned long long in trace events;
19
the dtrace backend can't handle the latter]
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
16
---
22
hw/core/Makefile.objs | 1 +
17
docs/system/arm/nuvoton.rst | 2 +-
23
include/hw/clock.h | 216 ++++++++++++++++++++++++++++++++++++++++++
18
meson.build | 1 +
24
hw/core/clock.c | 130 +++++++++++++++++++++++++
19
hw/adc/trace.h | 1 +
25
hw/core/trace-events | 7 ++
20
include/hw/adc/npcm7xx_adc.h | 69 ++++++
26
4 files changed, 354 insertions(+)
21
include/hw/arm/npcm7xx.h | 2 +
27
create mode 100644 include/hw/clock.h
22
hw/adc/npcm7xx_adc.c | 301 ++++++++++++++++++++++++++
28
create mode 100644 hw/core/clock.c
23
hw/arm/npcm7xx.c | 24 ++-
24
tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++
25
hw/adc/meson.build | 1 +
26
hw/adc/trace-events | 5 +
27
tests/qtest/meson.build | 3 +-
28
11 files changed, 783 insertions(+), 3 deletions(-)
29
create mode 100644 hw/adc/trace.h
30
create mode 100644 include/hw/adc/npcm7xx_adc.h
31
create mode 100644 hw/adc/npcm7xx_adc.c
32
create mode 100644 tests/qtest/npcm7xx_adc-test.c
33
create mode 100644 hw/adc/trace-events
29
34
30
diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
35
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
31
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/core/Makefile.objs
37
--- a/docs/system/arm/nuvoton.rst
33
+++ b/hw/core/Makefile.objs
38
+++ b/docs/system/arm/nuvoton.rst
34
@@ -XXX,XX +XXX,XX @@ common-obj-y += hotplug.o
39
@@ -XXX,XX +XXX,XX @@ Supported devices
35
common-obj-y += vmstate-if.o
40
* Random Number Generator (RNG)
36
# irq.o needed for qdev GPIO handling:
41
* USB host (USBH)
37
common-obj-y += irq.o
42
* GPIO controller
38
+common-obj-y += clock.o
43
+ * Analog to Digital Converter (ADC)
39
44
40
common-obj-$(CONFIG_SOFTMMU) += reset.o
45
Missing devices
41
common-obj-$(CONFIG_SOFTMMU) += qdev-fw.o
46
---------------
42
diff --git a/include/hw/clock.h b/include/hw/clock.h
47
@@ -XXX,XX +XXX,XX @@ Missing devices
48
* USB device (USBD)
49
* SMBus controller (SMBF)
50
* Peripheral SPI controller (PSPI)
51
- * Analog to Digital Converter (ADC)
52
* SD/MMC host
53
* PECI interface
54
* Pulse Width Modulation (PWM)
55
diff --git a/meson.build b/meson.build
56
index XXXXXXX..XXXXXXX 100644
57
--- a/meson.build
58
+++ b/meson.build
59
@@ -XXX,XX +XXX,XX @@ if have_system
60
'chardev',
61
'hw/9pfs',
62
'hw/acpi',
63
+ 'hw/adc',
64
'hw/alpha',
65
'hw/arm',
66
'hw/audio',
67
diff --git a/hw/adc/trace.h b/hw/adc/trace.h
43
new file mode 100644
68
new file mode 100644
44
index XXXXXXX..XXXXXXX
69
index XXXXXXX..XXXXXXX
45
--- /dev/null
70
--- /dev/null
46
+++ b/include/hw/clock.h
71
+++ b/hw/adc/trace.h
47
@@ -XXX,XX +XXX,XX @@
72
@@ -0,0 +1 @@
48
+/*
73
+#include "trace/trace-hw_adc.h"
49
+ * Hardware Clocks
74
diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h
50
+ *
51
+ * Copyright GreenSocs 2016-2020
52
+ *
53
+ * Authors:
54
+ * Frederic Konrad
55
+ * Damien Hedde
56
+ *
57
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
58
+ * See the COPYING file in the top-level directory.
59
+ */
60
+
61
+#ifndef QEMU_HW_CLOCK_H
62
+#define QEMU_HW_CLOCK_H
63
+
64
+#include "qom/object.h"
65
+#include "qemu/queue.h"
66
+
67
+#define TYPE_CLOCK "clock"
68
+#define CLOCK(obj) OBJECT_CHECK(Clock, (obj), TYPE_CLOCK)
69
+
70
+typedef void ClockCallback(void *opaque);
71
+
72
+/*
73
+ * clock store a value representing the clock's period in 2^-32ns unit.
74
+ * It can represent:
75
+ * + periods from 2^-32ns up to 4seconds
76
+ * + frequency from ~0.25Hz 2e10Ghz
77
+ * Resolution of frequency representation decreases with frequency:
78
+ * + at 100MHz, resolution is ~2mHz
79
+ * + at 1Ghz, resolution is ~0.2Hz
80
+ * + at 10Ghz, resolution is ~20Hz
81
+ */
82
+#define CLOCK_SECOND (1000000000llu << 32)
83
+
84
+/*
85
+ * macro helpers to convert to hertz / nanosecond
86
+ */
87
+#define CLOCK_PERIOD_FROM_NS(ns) ((ns) * (CLOCK_SECOND / 1000000000llu))
88
+#define CLOCK_PERIOD_TO_NS(per) ((per) / (CLOCK_SECOND / 1000000000llu))
89
+#define CLOCK_PERIOD_FROM_HZ(hz) (((hz) != 0) ? CLOCK_SECOND / (hz) : 0u)
90
+#define CLOCK_PERIOD_TO_HZ(per) (((per) != 0) ? CLOCK_SECOND / (per) : 0u)
91
+
92
+/**
93
+ * Clock:
94
+ * @parent_obj: parent class
95
+ * @period: unsigned integer representing the period of the clock
96
+ * @canonical_path: clock path string cache (used for trace purpose)
97
+ * @callback: called when clock changes
98
+ * @callback_opaque: argument for @callback
99
+ * @source: source (or parent in clock tree) of the clock
100
+ * @children: list of clocks connected to this one (it is their source)
101
+ * @sibling: structure used to form a clock list
102
+ */
103
+
104
+typedef struct Clock Clock;
105
+
106
+struct Clock {
107
+ /*< private >*/
108
+ Object parent_obj;
109
+
110
+ /* all fields are private and should not be modified directly */
111
+
112
+ /* fields */
113
+ uint64_t period;
114
+ char *canonical_path;
115
+ ClockCallback *callback;
116
+ void *callback_opaque;
117
+
118
+ /* Clocks are organized in a clock tree */
119
+ Clock *source;
120
+ QLIST_HEAD(, Clock) children;
121
+ QLIST_ENTRY(Clock) sibling;
122
+};
123
+
124
+/**
125
+ * clock_setup_canonical_path:
126
+ * @clk: clock
127
+ *
128
+ * compute the canonical path of the clock (used by log messages)
129
+ */
130
+void clock_setup_canonical_path(Clock *clk);
131
+
132
+/**
133
+ * clock_set_callback:
134
+ * @clk: the clock to register the callback into
135
+ * @cb: the callback function
136
+ * @opaque: the argument to the callback
137
+ *
138
+ * Register a callback called on every clock update.
139
+ */
140
+void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque);
141
+
142
+/**
143
+ * clock_clear_callback:
144
+ * @clk: the clock to delete the callback from
145
+ *
146
+ * Unregister the callback registered with clock_set_callback.
147
+ */
148
+void clock_clear_callback(Clock *clk);
149
+
150
+/**
151
+ * clock_set_source:
152
+ * @clk: the clock.
153
+ * @src: the source clock
154
+ *
155
+ * Setup @src as the clock source of @clk. The current @src period
156
+ * value is also copied to @clk and its subtree but no callback is
157
+ * called.
158
+ * Further @src update will be propagated to @clk and its subtree.
159
+ */
160
+void clock_set_source(Clock *clk, Clock *src);
161
+
162
+/**
163
+ * clock_set:
164
+ * @clk: the clock to initialize.
165
+ * @value: the clock's value, 0 means unclocked
166
+ *
167
+ * Set the local cached period value of @clk to @value.
168
+ */
169
+void clock_set(Clock *clk, uint64_t value);
170
+
171
+static inline void clock_set_hz(Clock *clk, unsigned hz)
172
+{
173
+ clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz));
174
+}
175
+
176
+static inline void clock_set_ns(Clock *clk, unsigned ns)
177
+{
178
+ clock_set(clk, CLOCK_PERIOD_FROM_NS(ns));
179
+}
180
+
181
+/**
182
+ * clock_propagate:
183
+ * @clk: the clock
184
+ *
185
+ * Propagate the clock period that has been previously configured using
186
+ * @clock_set(). This will update recursively all connected clocks.
187
+ * It is an error to call this function on a clock which has a source.
188
+ * Note: this function must not be called during device inititialization
189
+ * or migration.
190
+ */
191
+void clock_propagate(Clock *clk);
192
+
193
+/**
194
+ * clock_update:
195
+ * @clk: the clock to update.
196
+ * @value: the new clock's value, 0 means unclocked
197
+ *
198
+ * Update the @clk to the new @value. All connected clocks will be informed
199
+ * of this update. This is equivalent to call @clock_set() then
200
+ * @clock_propagate().
201
+ */
202
+static inline void clock_update(Clock *clk, uint64_t value)
203
+{
204
+ clock_set(clk, value);
205
+ clock_propagate(clk);
206
+}
207
+
208
+static inline void clock_update_hz(Clock *clk, unsigned hz)
209
+{
210
+ clock_update(clk, CLOCK_PERIOD_FROM_HZ(hz));
211
+}
212
+
213
+static inline void clock_update_ns(Clock *clk, unsigned ns)
214
+{
215
+ clock_update(clk, CLOCK_PERIOD_FROM_NS(ns));
216
+}
217
+
218
+/**
219
+ * clock_get:
220
+ * @clk: the clk to fetch the clock
221
+ *
222
+ * @return: the current period.
223
+ */
224
+static inline uint64_t clock_get(const Clock *clk)
225
+{
226
+ return clk->period;
227
+}
228
+
229
+static inline unsigned clock_get_hz(Clock *clk)
230
+{
231
+ return CLOCK_PERIOD_TO_HZ(clock_get(clk));
232
+}
233
+
234
+static inline unsigned clock_get_ns(Clock *clk)
235
+{
236
+ return CLOCK_PERIOD_TO_NS(clock_get(clk));
237
+}
238
+
239
+/**
240
+ * clock_is_enabled:
241
+ * @clk: a clock
242
+ *
243
+ * @return: true if the clock is running.
244
+ */
245
+static inline bool clock_is_enabled(const Clock *clk)
246
+{
247
+ return clock_get(clk) != 0;
248
+}
249
+
250
+static inline void clock_init(Clock *clk, uint64_t value)
251
+{
252
+ clock_set(clk, value);
253
+}
254
+static inline void clock_init_hz(Clock *clk, uint64_t value)
255
+{
256
+ clock_set_hz(clk, value);
257
+}
258
+static inline void clock_init_ns(Clock *clk, uint64_t value)
259
+{
260
+ clock_set_ns(clk, value);
261
+}
262
+
263
+#endif /* QEMU_HW_CLOCK_H */
264
diff --git a/hw/core/clock.c b/hw/core/clock.c
265
new file mode 100644
75
new file mode 100644
266
index XXXXXXX..XXXXXXX
76
index XXXXXXX..XXXXXXX
267
--- /dev/null
77
--- /dev/null
268
+++ b/hw/core/clock.c
78
+++ b/include/hw/adc/npcm7xx_adc.h
269
@@ -XXX,XX +XXX,XX @@
79
@@ -XXX,XX +XXX,XX @@
270
+/*
80
+/*
271
+ * Hardware Clocks
81
+ * Nuvoton NPCM7xx ADC Module
272
+ *
82
+ *
273
+ * Copyright GreenSocs 2016-2020
83
+ * Copyright 2020 Google LLC
274
+ *
84
+ *
275
+ * Authors:
85
+ * This program is free software; you can redistribute it and/or modify it
276
+ * Frederic Konrad
86
+ * under the terms of the GNU General Public License as published by the
277
+ * Damien Hedde
87
+ * Free Software Foundation; either version 2 of the License, or
88
+ * (at your option) any later version.
278
+ *
89
+ *
279
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
90
+ * This program is distributed in the hope that it will be useful, but WITHOUT
280
+ * See the COPYING file in the top-level directory.
91
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
92
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
93
+ * for more details.
281
+ */
94
+ */
95
+#ifndef NPCM7XX_ADC_H
96
+#define NPCM7XX_ADC_H
97
+
98
+#include "hw/clock.h"
99
+#include "hw/irq.h"
100
+#include "hw/sysbus.h"
101
+#include "qemu/timer.h"
102
+
103
+#define NPCM7XX_ADC_NUM_INPUTS 8
104
+/**
105
+ * This value should not be changed unless write_adc_calibration function in
106
+ * hw/arm/npcm7xx.c is also changed.
107
+ */
108
+#define NPCM7XX_ADC_NUM_CALIB 2
109
+
110
+/**
111
+ * struct NPCM7xxADCState - Analog to Digital Converter Module device state.
112
+ * @parent: System bus device.
113
+ * @iomem: Memory region through which registers are accessed.
114
+ * @conv_timer: The timer counts down remaining cycles for the conversion.
115
+ * @irq: GIC interrupt line to fire on expiration (if enabled).
116
+ * @con: The Control Register.
117
+ * @data: The Data Buffer.
118
+ * @clock: The ADC Clock.
119
+ * @adci: The input voltage in units of uV. 1uv = 1e-6V.
120
+ * @vref: The external reference voltage.
121
+ * @iref: The internal reference voltage, initialized at launch time.
122
+ * @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
123
+ */
124
+typedef struct {
125
+ SysBusDevice parent;
126
+
127
+ MemoryRegion iomem;
128
+
129
+ QEMUTimer conv_timer;
130
+
131
+ qemu_irq irq;
132
+ uint32_t con;
133
+ uint32_t data;
134
+ Clock *clock;
135
+
136
+ /* Voltages are in unit of uV. 1V = 1000000uV. */
137
+ uint32_t adci[NPCM7XX_ADC_NUM_INPUTS];
138
+ uint32_t vref;
139
+ uint32_t iref;
140
+
141
+ uint16_t calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
142
+} NPCM7xxADCState;
143
+
144
+#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
145
+#define NPCM7XX_ADC(obj) \
146
+ OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
147
+
148
+#endif /* NPCM7XX_ADC_H */
149
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
150
index XXXXXXX..XXXXXXX 100644
151
--- a/include/hw/arm/npcm7xx.h
152
+++ b/include/hw/arm/npcm7xx.h
153
@@ -XXX,XX +XXX,XX @@
154
#define NPCM7XX_H
155
156
#include "hw/boards.h"
157
+#include "hw/adc/npcm7xx_adc.h"
158
#include "hw/cpu/a9mpcore.h"
159
#include "hw/gpio/npcm7xx_gpio.h"
160
#include "hw/mem/npcm7xx_mc.h"
161
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
162
NPCM7xxGCRState gcr;
163
NPCM7xxCLKState clk;
164
NPCM7xxTimerCtrlState tim[3];
165
+ NPCM7xxADCState adc;
166
NPCM7xxOTPState key_storage;
167
NPCM7xxOTPState fuse_array;
168
NPCM7xxMCState mc;
169
diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
170
new file mode 100644
171
index XXXXXXX..XXXXXXX
172
--- /dev/null
173
+++ b/hw/adc/npcm7xx_adc.c
174
@@ -XXX,XX +XXX,XX @@
175
+/*
176
+ * Nuvoton NPCM7xx ADC Module
177
+ *
178
+ * Copyright 2020 Google LLC
179
+ *
180
+ * This program is free software; you can redistribute it and/or modify it
181
+ * under the terms of the GNU General Public License as published by the
182
+ * Free Software Foundation; either version 2 of the License, or
183
+ * (at your option) any later version.
184
+ *
185
+ * This program is distributed in the hope that it will be useful, but WITHOUT
186
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
187
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
188
+ * for more details.
189
+ */
282
+
190
+
283
+#include "qemu/osdep.h"
191
+#include "qemu/osdep.h"
284
+#include "hw/clock.h"
192
+#include "hw/adc/npcm7xx_adc.h"
193
+#include "hw/qdev-clock.h"
194
+#include "hw/qdev-properties.h"
195
+#include "hw/registerfields.h"
196
+#include "migration/vmstate.h"
197
+#include "qemu/log.h"
198
+#include "qemu/module.h"
199
+#include "qemu/timer.h"
200
+#include "qemu/units.h"
285
+#include "trace.h"
201
+#include "trace.h"
286
+
202
+
287
+#define CLOCK_PATH(_clk) (_clk->canonical_path)
203
+REG32(NPCM7XX_ADC_CON, 0x0)
288
+
204
+REG32(NPCM7XX_ADC_DATA, 0x4)
289
+void clock_setup_canonical_path(Clock *clk)
205
+
290
+{
206
+/* Register field definitions. */
291
+ g_free(clk->canonical_path);
207
+#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
292
+ clk->canonical_path = object_get_canonical_path(OBJECT(clk));
208
+#define NPCM7XX_ADC_CON_INT_EN BIT(21)
293
+}
209
+#define NPCM7XX_ADC_CON_REFSEL BIT(19)
294
+
210
+#define NPCM7XX_ADC_CON_INT BIT(18)
295
+void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque)
211
+#define NPCM7XX_ADC_CON_EN BIT(17)
296
+{
212
+#define NPCM7XX_ADC_CON_RST BIT(16)
297
+ clk->callback = cb;
213
+#define NPCM7XX_ADC_CON_CONV BIT(14)
298
+ clk->callback_opaque = opaque;
214
+#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
299
+}
215
+
300
+
216
+#define NPCM7XX_ADC_MAX_RESULT 1023
301
+void clock_clear_callback(Clock *clk)
217
+#define NPCM7XX_ADC_DEFAULT_IREF 2000000
302
+{
218
+#define NPCM7XX_ADC_CONV_CYCLES 20
303
+ clock_set_callback(clk, NULL, NULL);
219
+#define NPCM7XX_ADC_RESET_CYCLES 10
304
+}
220
+#define NPCM7XX_ADC_R0_INPUT 500000
305
+
221
+#define NPCM7XX_ADC_R1_INPUT 1500000
306
+void clock_set(Clock *clk, uint64_t period)
222
+
307
+{
223
+static void npcm7xx_adc_reset(NPCM7xxADCState *s)
308
+ trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_NS(clk->period),
224
+{
309
+ CLOCK_PERIOD_TO_NS(period));
225
+ timer_del(&s->conv_timer);
310
+ clk->period = period;
226
+ s->con = 0x000c0001;
311
+}
227
+ s->data = 0x00000000;
312
+
228
+}
313
+static void clock_propagate_period(Clock *clk, bool call_callbacks)
229
+
314
+{
230
+static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref)
315
+ Clock *child;
231
+{
316
+
232
+ uint32_t result;
317
+ QLIST_FOREACH(child, &clk->children, sibling) {
233
+
318
+ if (child->period != clk->period) {
234
+ result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref;
319
+ child->period = clk->period;
235
+ if (result > NPCM7XX_ADC_MAX_RESULT) {
320
+ trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk),
236
+ result = NPCM7XX_ADC_MAX_RESULT;
321
+ CLOCK_PERIOD_TO_NS(clk->period),
237
+ }
322
+ call_callbacks);
238
+
323
+ if (call_callbacks && child->callback) {
239
+ return result;
324
+ child->callback(child->callback_opaque);
240
+}
241
+
242
+static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s)
243
+{
244
+ return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1);
245
+}
246
+
247
+static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer,
248
+ uint32_t cycles, uint32_t prescaler)
249
+{
250
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
251
+ int64_t ticks = cycles;
252
+ int64_t ns;
253
+
254
+ ticks *= prescaler;
255
+ ns = clock_ticks_to_ns(clk, ticks);
256
+ ns += now;
257
+ timer_mod(timer, ns);
258
+}
259
+
260
+static void npcm7xx_adc_start_convert(NPCM7xxADCState *s)
261
+{
262
+ uint32_t prescaler = npcm7xx_adc_prescaler(s);
263
+
264
+ npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES,
265
+ prescaler);
266
+}
267
+
268
+static void npcm7xx_adc_convert_done(void *opaque)
269
+{
270
+ NPCM7xxADCState *s = opaque;
271
+ uint32_t input = NPCM7XX_ADC_CON_MUX(s->con);
272
+ uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL)
273
+ ? s->iref : s->vref;
274
+
275
+ if (input >= NPCM7XX_ADC_NUM_INPUTS) {
276
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n",
277
+ __func__, input);
278
+ return;
279
+ }
280
+ s->data = npcm7xx_adc_convert(s->adci[input], ref);
281
+ if (s->con & NPCM7XX_ADC_CON_INT_EN) {
282
+ s->con |= NPCM7XX_ADC_CON_INT;
283
+ qemu_irq_raise(s->irq);
284
+ }
285
+ s->con &= ~NPCM7XX_ADC_CON_CONV;
286
+}
287
+
288
+static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc)
289
+{
290
+ adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT,
291
+ adc->iref);
292
+ adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT,
293
+ adc->iref);
294
+}
295
+
296
+static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con)
297
+{
298
+ uint32_t old_con = s->con;
299
+
300
+ /* Write ADC_INT to 1 to clear it */
301
+ if (new_con & NPCM7XX_ADC_CON_INT) {
302
+ new_con &= ~NPCM7XX_ADC_CON_INT;
303
+ qemu_irq_lower(s->irq);
304
+ } else if (old_con & NPCM7XX_ADC_CON_INT) {
305
+ new_con |= NPCM7XX_ADC_CON_INT;
306
+ }
307
+
308
+ s->con = new_con;
309
+
310
+ if (s->con & NPCM7XX_ADC_CON_RST) {
311
+ npcm7xx_adc_reset(s);
312
+ return;
313
+ }
314
+
315
+ if ((s->con & NPCM7XX_ADC_CON_EN)) {
316
+ if (s->con & NPCM7XX_ADC_CON_CONV) {
317
+ if (!(old_con & NPCM7XX_ADC_CON_CONV)) {
318
+ npcm7xx_adc_start_convert(s);
325
+ }
319
+ }
326
+ clock_propagate_period(child, call_callbacks);
320
+ } else {
321
+ timer_del(&s->conv_timer);
327
+ }
322
+ }
328
+ }
323
+ }
329
+}
324
+}
330
+
325
+
331
+void clock_propagate(Clock *clk)
326
+static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size)
332
+{
327
+{
333
+ assert(clk->source == NULL);
328
+ uint64_t value = 0;
334
+ trace_clock_propagate(CLOCK_PATH(clk));
329
+ NPCM7xxADCState *s = opaque;
335
+ clock_propagate_period(clk, true);
330
+
336
+}
331
+ switch (offset) {
337
+
332
+ case A_NPCM7XX_ADC_CON:
338
+void clock_set_source(Clock *clk, Clock *src)
333
+ value = s->con;
339
+{
334
+ break;
340
+ /* changing clock source is not supported */
335
+
341
+ assert(!clk->source);
336
+ case A_NPCM7XX_ADC_DATA:
342
+
337
+ value = s->data;
343
+ trace_clock_set_source(CLOCK_PATH(clk), CLOCK_PATH(src));
338
+ break;
344
+
339
+
345
+ clk->period = src->period;
340
+ default:
346
+ QLIST_INSERT_HEAD(&src->children, clk, sibling);
341
+ qemu_log_mask(LOG_GUEST_ERROR,
347
+ clk->source = src;
342
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
348
+ clock_propagate_period(clk, false);
343
+ __func__, offset);
349
+}
344
+ break;
350
+
345
+ }
351
+static void clock_disconnect(Clock *clk)
346
+
352
+{
347
+ trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value);
353
+ if (clk->source == NULL) {
348
+ return value;
354
+ return;
349
+}
355
+ }
350
+
356
+
351
+static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v,
357
+ trace_clock_disconnect(CLOCK_PATH(clk));
352
+ unsigned size)
358
+
353
+{
359
+ clk->source = NULL;
354
+ NPCM7xxADCState *s = opaque;
360
+ QLIST_REMOVE(clk, sibling);
355
+
361
+}
356
+ trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v);
362
+
357
+ switch (offset) {
363
+static void clock_initfn(Object *obj)
358
+ case A_NPCM7XX_ADC_CON:
364
+{
359
+ npcm7xx_adc_write_con(s, v);
365
+ Clock *clk = CLOCK(obj);
360
+ break;
366
+
361
+
367
+ QLIST_INIT(&clk->children);
362
+ case A_NPCM7XX_ADC_DATA:
368
+}
363
+ qemu_log_mask(LOG_GUEST_ERROR,
369
+
364
+ "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
370
+static void clock_finalizefn(Object *obj)
365
+ __func__, offset);
371
+{
366
+ break;
372
+ Clock *clk = CLOCK(obj);
367
+
373
+ Clock *child, *next;
368
+ default:
374
+
369
+ qemu_log_mask(LOG_GUEST_ERROR,
375
+ /* clear our list of children */
370
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
376
+ QLIST_FOREACH_SAFE(child, &clk->children, sibling, next) {
371
+ __func__, offset);
377
+ clock_disconnect(child);
372
+ break;
378
+ }
373
+ }
379
+
374
+
380
+ /* remove us from source's children list */
375
+}
381
+ clock_disconnect(clk);
376
+
382
+
377
+static const struct MemoryRegionOps npcm7xx_adc_ops = {
383
+ g_free(clk->canonical_path);
378
+ .read = npcm7xx_adc_read,
384
+}
379
+ .write = npcm7xx_adc_write,
385
+
380
+ .endianness = DEVICE_LITTLE_ENDIAN,
386
+static const TypeInfo clock_info = {
381
+ .valid = {
387
+ .name = TYPE_CLOCK,
382
+ .min_access_size = 4,
388
+ .parent = TYPE_OBJECT,
383
+ .max_access_size = 4,
389
+ .instance_size = sizeof(Clock),
384
+ .unaligned = false,
390
+ .instance_init = clock_initfn,
385
+ },
391
+ .instance_finalize = clock_finalizefn,
392
+};
386
+};
393
+
387
+
394
+static void clock_register_types(void)
388
+static void npcm7xx_adc_enter_reset(Object *obj, ResetType type)
395
+{
389
+{
396
+ type_register_static(&clock_info);
390
+ NPCM7xxADCState *s = NPCM7XX_ADC(obj);
397
+}
391
+
398
+
392
+ npcm7xx_adc_reset(s);
399
+type_init(clock_register_types)
393
+}
400
diff --git a/hw/core/trace-events b/hw/core/trace-events
394
+
395
+static void npcm7xx_adc_hold_reset(Object *obj)
396
+{
397
+ NPCM7xxADCState *s = NPCM7XX_ADC(obj);
398
+
399
+ qemu_irq_lower(s->irq);
400
+}
401
+
402
+static void npcm7xx_adc_init(Object *obj)
403
+{
404
+ NPCM7xxADCState *s = NPCM7XX_ADC(obj);
405
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
406
+ int i;
407
+
408
+ sysbus_init_irq(sbd, &s->irq);
409
+
410
+ timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL,
411
+ npcm7xx_adc_convert_done, s);
412
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s,
413
+ TYPE_NPCM7XX_ADC, 4 * KiB);
414
+ sysbus_init_mmio(sbd, &s->iomem);
415
+ s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
416
+
417
+ for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) {
418
+ object_property_add_uint32_ptr(obj, "adci[*]",
419
+ &s->adci[i], OBJ_PROP_FLAG_WRITE);
420
+ }
421
+ object_property_add_uint32_ptr(obj, "vref",
422
+ &s->vref, OBJ_PROP_FLAG_WRITE);
423
+ npcm7xx_adc_calibrate(s);
424
+}
425
+
426
+static const VMStateDescription vmstate_npcm7xx_adc = {
427
+ .name = "npcm7xx-adc",
428
+ .version_id = 0,
429
+ .minimum_version_id = 0,
430
+ .fields = (VMStateField[]) {
431
+ VMSTATE_TIMER(conv_timer, NPCM7xxADCState),
432
+ VMSTATE_UINT32(con, NPCM7xxADCState),
433
+ VMSTATE_UINT32(data, NPCM7xxADCState),
434
+ VMSTATE_CLOCK(clock, NPCM7xxADCState),
435
+ VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS),
436
+ VMSTATE_UINT32(vref, NPCM7xxADCState),
437
+ VMSTATE_UINT32(iref, NPCM7xxADCState),
438
+ VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState,
439
+ NPCM7XX_ADC_NUM_CALIB),
440
+ VMSTATE_END_OF_LIST(),
441
+ },
442
+};
443
+
444
+static Property npcm7xx_timer_properties[] = {
445
+ DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF),
446
+ DEFINE_PROP_END_OF_LIST(),
447
+};
448
+
449
+static void npcm7xx_adc_class_init(ObjectClass *klass, void *data)
450
+{
451
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
452
+ DeviceClass *dc = DEVICE_CLASS(klass);
453
+
454
+ dc->desc = "NPCM7xx ADC Module";
455
+ dc->vmsd = &vmstate_npcm7xx_adc;
456
+ rc->phases.enter = npcm7xx_adc_enter_reset;
457
+ rc->phases.hold = npcm7xx_adc_hold_reset;
458
+
459
+ device_class_set_props(dc, npcm7xx_timer_properties);
460
+}
461
+
462
+static const TypeInfo npcm7xx_adc_info = {
463
+ .name = TYPE_NPCM7XX_ADC,
464
+ .parent = TYPE_SYS_BUS_DEVICE,
465
+ .instance_size = sizeof(NPCM7xxADCState),
466
+ .class_init = npcm7xx_adc_class_init,
467
+ .instance_init = npcm7xx_adc_init,
468
+};
469
+
470
+static void npcm7xx_adc_register_types(void)
471
+{
472
+ type_register_static(&npcm7xx_adc_info);
473
+}
474
+
475
+type_init(npcm7xx_adc_register_types);
476
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
401
index XXXXXXX..XXXXXXX 100644
477
index XXXXXXX..XXXXXXX 100644
402
--- a/hw/core/trace-events
478
--- a/hw/arm/npcm7xx.c
403
+++ b/hw/core/trace-events
479
+++ b/hw/arm/npcm7xx.c
404
@@ -XXX,XX +XXX,XX @@ resettable_phase_exit_begin(void *obj, const char *objtype, unsigned count, int
480
@@ -XXX,XX +XXX,XX @@
405
resettable_phase_exit_exec(void *obj, const char *objtype, int has_method) "obj=%p(%s) method=%d"
481
#define NPCM7XX_EHCI_BA (0xf0806000)
406
resettable_phase_exit_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d"
482
#define NPCM7XX_OHCI_BA (0xf0807000)
407
resettable_transitional_function(void *obj, const char *objtype) "obj=%p(%s)"
483
408
+
484
+/* ADC Module */
409
+# clock.c
485
+#define NPCM7XX_ADC_BA (0xf000c000)
410
+clock_set_source(const char *clk, const char *src) "'%s', src='%s'"
486
+
411
+clock_disconnect(const char *clk) "'%s'"
487
/* Internal AHB SRAM */
412
+clock_set(const char *clk, uint64_t old, uint64_t new) "'%s', ns=%"PRIu64"->%"PRIu64
488
#define NPCM7XX_RAM3_BA (0xc0008000)
413
+clock_propagate(const char *clk) "'%s'"
489
#define NPCM7XX_RAM3_SZ (4 * KiB)
414
+clock_update(const char *clk, const char *src, uint64_t val, int cb) "'%s', src='%s', ns=%"PRIu64", cb=%d"
490
@@ -XXX,XX +XXX,XX @@
491
#define NPCM7XX_ROM_BA (0xffff0000)
492
#define NPCM7XX_ROM_SZ (64 * KiB)
493
494
+
495
/* Clock configuration values to be fixed up when bypassing bootloader */
496
497
/* Run PLL1 at 1600 MHz */
498
@@ -XXX,XX +XXX,XX @@
499
* interrupts.
500
*/
501
enum NPCM7xxInterrupt {
502
+ NPCM7XX_ADC_IRQ = 0,
503
NPCM7XX_UART0_IRQ = 2,
504
NPCM7XX_UART1_IRQ,
505
NPCM7XX_UART2_IRQ,
506
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
507
sizeof(value));
508
}
509
510
+static void npcm7xx_write_adc_calibration(NPCM7xxState *s)
511
+{
512
+ /* Both ADC and the fuse array must have realized. */
513
+ QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
514
+ npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
515
+ NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
516
+}
517
+
518
static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
519
{
520
return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
521
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
522
TYPE_NPCM7XX_FUSE_ARRAY);
523
object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
524
object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
525
+ object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
526
527
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
528
object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
529
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
530
sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
531
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
532
533
+ /* ADC Modules. Cannot fail. */
534
+ qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
535
+ DEVICE(&s->clk), "adc-clock"));
536
+ sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
537
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA);
538
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
539
+ npcm7xx_irq(s, NPCM7XX_ADC_IRQ));
540
+ npcm7xx_write_adc_calibration(s);
541
+
542
/* Timer Modules (TIM). Cannot fail. */
543
QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
544
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
545
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
546
create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB);
547
create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
548
create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);
549
- create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB);
550
create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB);
551
create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB);
552
create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB);
553
diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c
554
new file mode 100644
555
index XXXXXXX..XXXXXXX
556
--- /dev/null
557
+++ b/tests/qtest/npcm7xx_adc-test.c
558
@@ -XXX,XX +XXX,XX @@
559
+/*
560
+ * QTests for Nuvoton NPCM7xx ADCModules.
561
+ *
562
+ * Copyright 2020 Google LLC
563
+ *
564
+ * This program is free software; you can redistribute it and/or modify it
565
+ * under the terms of the GNU General Public License as published by the
566
+ * Free Software Foundation; either version 2 of the License, or
567
+ * (at your option) any later version.
568
+ *
569
+ * This program is distributed in the hope that it will be useful, but WITHOUT
570
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
571
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
572
+ * for more details.
573
+ */
574
+
575
+#include "qemu/osdep.h"
576
+#include "qemu/bitops.h"
577
+#include "qemu/timer.h"
578
+#include "libqos/libqtest.h"
579
+#include "qapi/qmp/qdict.h"
580
+
581
+#define REF_HZ (25000000)
582
+
583
+#define CON_OFFSET 0x0
584
+#define DATA_OFFSET 0x4
585
+
586
+#define NUM_INPUTS 8
587
+#define DEFAULT_IREF 2000000
588
+#define CONV_CYCLES 20
589
+#define RESET_CYCLES 10
590
+#define R0_INPUT 500000
591
+#define R1_INPUT 1500000
592
+#define MAX_RESULT 1023
593
+
594
+#define DEFAULT_CLKDIV 5
595
+
596
+#define FUSE_ARRAY_BA 0xf018a000
597
+#define FCTL_OFFSET 0x14
598
+#define FST_OFFSET 0x0
599
+#define FADDR_OFFSET 0x4
600
+#define FDATA_OFFSET 0x8
601
+#define ADC_CALIB_ADDR 24
602
+#define FUSE_READ 0x2
603
+
604
+/* Register field definitions. */
605
+#define CON_MUX(rv) ((rv) << 24)
606
+#define CON_INT_EN BIT(21)
607
+#define CON_REFSEL BIT(19)
608
+#define CON_INT BIT(18)
609
+#define CON_EN BIT(17)
610
+#define CON_RST BIT(16)
611
+#define CON_CONV BIT(14)
612
+#define CON_DIV(rv) extract32(rv, 1, 8)
613
+
614
+#define FST_RDST BIT(1)
615
+#define FDATA_MASK 0xff
616
+
617
+#define MAX_ERROR 10000
618
+#define MIN_CALIB_INPUT 100000
619
+#define MAX_CALIB_INPUT 1800000
620
+
621
+static const uint32_t input_list[] = {
622
+ 100000,
623
+ 500000,
624
+ 1000000,
625
+ 1500000,
626
+ 1800000,
627
+ 2000000,
628
+};
629
+
630
+static const uint32_t vref_list[] = {
631
+ 2000000,
632
+ 2200000,
633
+ 2500000,
634
+};
635
+
636
+static const uint32_t iref_list[] = {
637
+ 1800000,
638
+ 1900000,
639
+ 2000000,
640
+ 2100000,
641
+ 2200000,
642
+};
643
+
644
+static const uint32_t div_list[] = {0, 1, 3, 7, 15};
645
+
646
+typedef struct ADC {
647
+ int irq;
648
+ uint64_t base_addr;
649
+} ADC;
650
+
651
+ADC adc = {
652
+ .irq = 0,
653
+ .base_addr = 0xf000c000
654
+};
655
+
656
+static uint32_t adc_read_con(QTestState *qts, const ADC *adc)
657
+{
658
+ return qtest_readl(qts, adc->base_addr + CON_OFFSET);
659
+}
660
+
661
+static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value)
662
+{
663
+ qtest_writel(qts, adc->base_addr + CON_OFFSET, value);
664
+}
665
+
666
+static uint32_t adc_read_data(QTestState *qts, const ADC *adc)
667
+{
668
+ return qtest_readl(qts, adc->base_addr + DATA_OFFSET);
669
+}
670
+
671
+static uint32_t adc_calibrate(uint32_t measured, uint32_t *rv)
672
+{
673
+ return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0])
674
+ / (int32_t)(rv[1] - rv[0]);
675
+}
676
+
677
+static void adc_qom_set(QTestState *qts, const ADC *adc,
678
+ const char *name, uint32_t value)
679
+{
680
+ QDict *response;
681
+ const char *path = "/machine/soc/adc";
682
+
683
+ g_test_message("Setting properties %s of %s with value %u",
684
+ name, path, value);
685
+ response = qtest_qmp(qts, "{ 'execute': 'qom-set',"
686
+ " 'arguments': { 'path': %s, 'property': %s, 'value': %u}}",
687
+ path, name, value);
688
+ /* The qom set message returns successfully. */
689
+ g_assert_true(qdict_haskey(response, "return"));
690
+}
691
+
692
+static void adc_write_input(QTestState *qts, const ADC *adc,
693
+ uint32_t index, uint32_t value)
694
+{
695
+ char name[100];
696
+
697
+ sprintf(name, "adci[%u]", index);
698
+ adc_qom_set(qts, adc, name, value);
699
+}
700
+
701
+static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value)
702
+{
703
+ adc_qom_set(qts, adc, "vref", value);
704
+}
705
+
706
+static uint32_t adc_calculate_output(uint32_t input, uint32_t ref)
707
+{
708
+ uint32_t output;
709
+
710
+ g_assert_cmpuint(input, <=, ref);
711
+ output = (input * (MAX_RESULT + 1)) / ref;
712
+ if (output > MAX_RESULT) {
713
+ output = MAX_RESULT;
714
+ }
715
+
716
+ return output;
717
+}
718
+
719
+static uint32_t adc_prescaler(QTestState *qts, const ADC *adc)
720
+{
721
+ uint32_t div = extract32(adc_read_con(qts, adc), 1, 8);
722
+
723
+ return 2 * (div + 1);
724
+}
725
+
726
+static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale,
727
+ uint32_t clkdiv)
728
+{
729
+ return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale;
730
+}
731
+
732
+static void adc_wait_conv_finished(QTestState *qts, const ADC *adc,
733
+ uint32_t clkdiv)
734
+{
735
+ uint32_t prescaler = adc_prescaler(qts, adc);
736
+
737
+ /*
738
+ * ADC should takes roughly 20 cycles to convert one sample. So we assert it
739
+ * should take 10~30 cycles here.
740
+ */
741
+ qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES / 2, prescaler,
742
+ clkdiv));
743
+ /* ADC is still converting. */
744
+ g_assert_true(adc_read_con(qts, adc) & CON_CONV);
745
+ qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkdiv));
746
+ /* ADC has finished conversion. */
747
+ g_assert_false(adc_read_con(qts, adc) & CON_CONV);
748
+}
749
+
750
+/* Check ADC can be reset to default value. */
751
+static void test_init(gconstpointer adc_p)
752
+{
753
+ const ADC *adc = adc_p;
754
+
755
+ QTestState *qts = qtest_init("-machine quanta-gsj");
756
+ adc_write_con(qts, adc, CON_REFSEL | CON_INT);
757
+ g_assert_cmphex(adc_read_con(qts, adc), ==, CON_REFSEL);
758
+ qtest_quit(qts);
759
+}
760
+
761
+/* Check ADC can convert from an internal reference. */
762
+static void test_convert_internal(gconstpointer adc_p)
763
+{
764
+ const ADC *adc = adc_p;
765
+ uint32_t index, input, output, expected_output;
766
+ QTestState *qts = qtest_init("-machine quanta-gsj");
767
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
768
+
769
+ for (index = 0; index < NUM_INPUTS; ++index) {
770
+ for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
771
+ input = input_list[i];
772
+ expected_output = adc_calculate_output(input, DEFAULT_IREF);
773
+
774
+ adc_write_input(qts, adc, index, input);
775
+ adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
776
+ CON_EN | CON_CONV);
777
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
778
+ g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) |
779
+ CON_REFSEL | CON_EN);
780
+ g_assert_false(qtest_get_irq(qts, adc->irq));
781
+ output = adc_read_data(qts, adc);
782
+ g_assert_cmpuint(output, ==, expected_output);
783
+ }
784
+ }
785
+
786
+ qtest_quit(qts);
787
+}
788
+
789
+/* Check ADC can convert from an external reference. */
790
+static void test_convert_external(gconstpointer adc_p)
791
+{
792
+ const ADC *adc = adc_p;
793
+ uint32_t index, input, vref, output, expected_output;
794
+ QTestState *qts = qtest_init("-machine quanta-gsj");
795
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
796
+
797
+ for (index = 0; index < NUM_INPUTS; ++index) {
798
+ for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
799
+ for (size_t j = 0; j < ARRAY_SIZE(vref_list); ++j) {
800
+ input = input_list[i];
801
+ vref = vref_list[j];
802
+ expected_output = adc_calculate_output(input, vref);
803
+
804
+ adc_write_input(qts, adc, index, input);
805
+ adc_write_vref(qts, adc, vref);
806
+ adc_write_con(qts, adc, CON_MUX(index) | CON_INT | CON_EN |
807
+ CON_CONV);
808
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
809
+ g_assert_cmphex(adc_read_con(qts, adc), ==,
810
+ CON_MUX(index) | CON_EN);
811
+ g_assert_false(qtest_get_irq(qts, adc->irq));
812
+ output = adc_read_data(qts, adc);
813
+ g_assert_cmpuint(output, ==, expected_output);
814
+ }
815
+ }
816
+ }
817
+
818
+ qtest_quit(qts);
819
+}
820
+
821
+/* Check ADC interrupt files if and only if CON_INT_EN is set. */
822
+static void test_interrupt(gconstpointer adc_p)
823
+{
824
+ const ADC *adc = adc_p;
825
+ uint32_t index, input, output, expected_output;
826
+ QTestState *qts = qtest_init("-machine quanta-gsj");
827
+
828
+ index = 1;
829
+ input = input_list[1];
830
+ expected_output = adc_calculate_output(input, DEFAULT_IREF);
831
+
832
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
833
+ adc_write_input(qts, adc, index, input);
834
+ g_assert_false(qtest_get_irq(qts, adc->irq));
835
+ adc_write_con(qts, adc, CON_MUX(index) | CON_INT_EN | CON_REFSEL | CON_INT
836
+ | CON_EN | CON_CONV);
837
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
838
+ g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | CON_INT_EN
839
+ | CON_REFSEL | CON_INT | CON_EN);
840
+ g_assert_true(qtest_get_irq(qts, adc->irq));
841
+ output = adc_read_data(qts, adc);
842
+ g_assert_cmpuint(output, ==, expected_output);
843
+
844
+ qtest_quit(qts);
845
+}
846
+
847
+/* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */
848
+static void test_reset(gconstpointer adc_p)
849
+{
850
+ const ADC *adc = adc_p;
851
+ QTestState *qts = qtest_init("-machine quanta-gsj");
852
+
853
+ for (size_t i = 0; i < ARRAY_SIZE(div_list); ++i) {
854
+ uint32_t div = div_list[i];
855
+
856
+ adc_write_con(qts, adc, CON_INT | CON_EN | CON_RST | CON_DIV(div));
857
+ qtest_clock_step(qts, adc_calculate_steps(RESET_CYCLES,
858
+ adc_prescaler(qts, adc), DEFAULT_CLKDIV));
859
+ g_assert_false(adc_read_con(qts, adc) & CON_EN);
860
+ }
861
+ qtest_quit(qts);
862
+}
863
+
864
+/* Check ADC Calibration works as desired. */
865
+static void test_calibrate(gconstpointer adc_p)
866
+{
867
+ int i, j;
868
+ const ADC *adc = adc_p;
869
+
870
+ for (j = 0; j < ARRAY_SIZE(iref_list); ++j) {
871
+ uint32_t iref = iref_list[j];
872
+ uint32_t expected_rv[] = {
873
+ adc_calculate_output(R0_INPUT, iref),
874
+ adc_calculate_output(R1_INPUT, iref),
875
+ };
876
+ char buf[100];
877
+ QTestState *qts;
878
+
879
+ sprintf(buf, "-machine quanta-gsj -global npcm7xx-adc.iref=%u", iref);
880
+ qts = qtest_init(buf);
881
+
882
+ /* Check the converted value is correct using the calibration value. */
883
+ for (i = 0; i < ARRAY_SIZE(input_list); ++i) {
884
+ uint32_t input;
885
+ uint32_t output;
886
+ uint32_t expected_output;
887
+ uint32_t calibrated_voltage;
888
+ uint32_t index = 0;
889
+
890
+ input = input_list[i];
891
+ /* Calibration only works for input range 0.1V ~ 1.8V. */
892
+ if (input < MIN_CALIB_INPUT || input > MAX_CALIB_INPUT) {
893
+ continue;
894
+ }
895
+ expected_output = adc_calculate_output(input, iref);
896
+
897
+ adc_write_input(qts, adc, index, input);
898
+ adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
899
+ CON_EN | CON_CONV);
900
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
901
+ g_assert_cmphex(adc_read_con(qts, adc), ==,
902
+ CON_REFSEL | CON_MUX(index) | CON_EN);
903
+ output = adc_read_data(qts, adc);
904
+ g_assert_cmpuint(output, ==, expected_output);
905
+
906
+ calibrated_voltage = adc_calibrate(output, expected_rv);
907
+ g_assert_cmpuint(calibrated_voltage, >, input - MAX_ERROR);
908
+ g_assert_cmpuint(calibrated_voltage, <, input + MAX_ERROR);
909
+ }
910
+
911
+ qtest_quit(qts);
912
+ }
913
+}
914
+
915
+static void adc_add_test(const char *name, const ADC* wd,
916
+ GTestDataFunc fn)
917
+{
918
+ g_autofree char *full_name = g_strdup_printf("npcm7xx_adc/%s", name);
919
+ qtest_add_data_func(full_name, wd, fn);
920
+}
921
+#define add_test(name, td) adc_add_test(#name, td, test_##name)
922
+
923
+int main(int argc, char **argv)
924
+{
925
+ g_test_init(&argc, &argv, NULL);
926
+
927
+ add_test(init, &adc);
928
+ add_test(convert_internal, &adc);
929
+ add_test(convert_external, &adc);
930
+ add_test(interrupt, &adc);
931
+ add_test(reset, &adc);
932
+ add_test(calibrate, &adc);
933
+
934
+ return g_test_run();
935
+}
936
diff --git a/hw/adc/meson.build b/hw/adc/meson.build
937
index XXXXXXX..XXXXXXX 100644
938
--- a/hw/adc/meson.build
939
+++ b/hw/adc/meson.build
940
@@ -1 +1,2 @@
941
softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c'))
942
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c'))
943
diff --git a/hw/adc/trace-events b/hw/adc/trace-events
944
new file mode 100644
945
index XXXXXXX..XXXXXXX
946
--- /dev/null
947
+++ b/hw/adc/trace-events
948
@@ -XXX,XX +XXX,XX @@
949
+# See docs/devel/tracing.txt for syntax documentation.
950
+
951
+# npcm7xx_adc.c
952
+npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
953
+npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
954
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
955
index XXXXXXX..XXXXXXX 100644
956
--- a/tests/qtest/meson.build
957
+++ b/tests/qtest/meson.build
958
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
959
['prom-env-test', 'boot-serial-test']
960
961
qtests_npcm7xx = \
962
- ['npcm7xx_gpio-test',
963
+ ['npcm7xx_adc-test',
964
+ 'npcm7xx_gpio-test',
965
'npcm7xx_rng-test',
966
'npcm7xx_timer-test',
967
'npcm7xx_watchdog_timer-test']
415
--
968
--
416
2.20.1
969
2.20.1
417
970
418
971
diff view generated by jsdifflib
1
From: Damien Hedde <damien.hedde@greensocs.com>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
Add functions to easily handle clocks with devices.
3
The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
4
Clock inputs and outputs should be used to handle clock propagation
4
identical PWM modules. Each module contains 4 PWM entries. Each PWM has
5
between devices.
5
two outputs: frequency and duty_cycle. Both are computed using inputs
6
The API is very similar the GPIO API.
6
from software side.
7
7
8
This is based on the original work of Frederic Konrad.
8
This module does not model detail pulse signals since it is expensive.
9
It also does not model interrupts and watchdogs that are dependant on
10
the detail models. The interfaces for these are left in the module so
11
that anyone in need for these functionalities can implement on their
12
own.
9
13
10
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
14
The user can read the duty cycle and frequency using qom-get command.
11
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
15
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
13
Message-id: 20200406135251.157596-4-damien.hedde@greensocs.com
17
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
18
Signed-off-by: Hao Wu <wuhaotsh@google.com>
19
Message-id: 20210108190945.949196-5-wuhaotsh@google.com
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
22
---
16
hw/core/Makefile.objs | 2 +-
23
docs/system/arm/nuvoton.rst | 2 +-
17
tests/Makefile.include | 1 +
24
include/hw/arm/npcm7xx.h | 2 +
18
include/hw/qdev-clock.h | 104 +++++++++++++++++++++++++
25
include/hw/misc/npcm7xx_pwm.h | 105 +++++++
19
include/hw/qdev-core.h | 12 +++
26
hw/arm/npcm7xx.c | 26 +-
20
hw/core/qdev-clock.c | 168 ++++++++++++++++++++++++++++++++++++++++
27
hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++++++++++
21
hw/core/qdev.c | 12 +++
28
hw/misc/meson.build | 1 +
22
6 files changed, 298 insertions(+), 1 deletion(-)
29
hw/misc/trace-events | 6 +
23
create mode 100644 include/hw/qdev-clock.h
30
7 files changed, 689 insertions(+), 3 deletions(-)
24
create mode 100644 hw/core/qdev-clock.c
31
create mode 100644 include/hw/misc/npcm7xx_pwm.h
32
create mode 100644 hw/misc/npcm7xx_pwm.c
25
33
26
diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
34
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
27
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/core/Makefile.objs
36
--- a/docs/system/arm/nuvoton.rst
29
+++ b/hw/core/Makefile.objs
37
+++ b/docs/system/arm/nuvoton.rst
30
@@ -XXX,XX +XXX,XX @@ common-obj-y += hotplug.o
38
@@ -XXX,XX +XXX,XX @@ Supported devices
31
common-obj-y += vmstate-if.o
39
* USB host (USBH)
32
# irq.o needed for qdev GPIO handling:
40
* GPIO controller
33
common-obj-y += irq.o
41
* Analog to Digital Converter (ADC)
34
-common-obj-y += clock.o
42
+ * Pulse Width Modulation (PWM)
35
+common-obj-y += clock.o qdev-clock.o
43
36
44
Missing devices
37
common-obj-$(CONFIG_SOFTMMU) += reset.o
45
---------------
38
common-obj-$(CONFIG_SOFTMMU) += qdev-fw.o
46
@@ -XXX,XX +XXX,XX @@ Missing devices
39
diff --git a/tests/Makefile.include b/tests/Makefile.include
47
* Peripheral SPI controller (PSPI)
48
* SD/MMC host
49
* PECI interface
50
- * Pulse Width Modulation (PWM)
51
* Tachometer
52
* PCI and PCIe root complex and bridges
53
* VDM and MCTP support
54
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
40
index XXXXXXX..XXXXXXX 100644
55
index XXXXXXX..XXXXXXX 100644
41
--- a/tests/Makefile.include
56
--- a/include/hw/arm/npcm7xx.h
42
+++ b/tests/Makefile.include
57
+++ b/include/hw/arm/npcm7xx.h
43
@@ -XXX,XX +XXX,XX @@ tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \
58
@@ -XXX,XX +XXX,XX @@
44
    hw/core/fw-path-provider.o \
59
#include "hw/mem/npcm7xx_mc.h"
45
    hw/core/reset.o \
60
#include "hw/misc/npcm7xx_clk.h"
46
    hw/core/vmstate-if.o \
61
#include "hw/misc/npcm7xx_gcr.h"
47
+    hw/core/clock.o hw/core/qdev-clock.o \
62
+#include "hw/misc/npcm7xx_pwm.h"
48
    $(test-qapi-obj-y)
63
#include "hw/misc/npcm7xx_rng.h"
49
tests/test-vmstate$(EXESUF): tests/test-vmstate.o \
64
#include "hw/nvram/npcm7xx_otp.h"
50
    migration/vmstate.o migration/vmstate-types.o migration/qemu-file.o \
65
#include "hw/timer/npcm7xx_timer.h"
51
diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h
66
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
67
NPCM7xxCLKState clk;
68
NPCM7xxTimerCtrlState tim[3];
69
NPCM7xxADCState adc;
70
+ NPCM7xxPWMState pwm[2];
71
NPCM7xxOTPState key_storage;
72
NPCM7xxOTPState fuse_array;
73
NPCM7xxMCState mc;
74
diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h
52
new file mode 100644
75
new file mode 100644
53
index XXXXXXX..XXXXXXX
76
index XXXXXXX..XXXXXXX
54
--- /dev/null
77
--- /dev/null
55
+++ b/include/hw/qdev-clock.h
78
+++ b/include/hw/misc/npcm7xx_pwm.h
56
@@ -XXX,XX +XXX,XX @@
79
@@ -XXX,XX +XXX,XX @@
57
+/*
80
+/*
58
+ * Device's clock input and output
81
+ * Nuvoton NPCM7xx PWM Module
59
+ *
82
+ *
60
+ * Copyright GreenSocs 2016-2020
83
+ * Copyright 2020 Google LLC
61
+ *
84
+ *
62
+ * Authors:
85
+ * This program is free software; you can redistribute it and/or modify it
63
+ * Frederic Konrad
86
+ * under the terms of the GNU General Public License as published by the
64
+ * Damien Hedde
87
+ * Free Software Foundation; either version 2 of the License, or
88
+ * (at your option) any later version.
65
+ *
89
+ *
66
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
90
+ * This program is distributed in the hope that it will be useful, but WITHOUT
67
+ * See the COPYING file in the top-level directory.
91
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
92
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
93
+ * for more details.
68
+ */
94
+ */
69
+
95
+#ifndef NPCM7XX_PWM_H
70
+#ifndef QDEV_CLOCK_H
96
+#define NPCM7XX_PWM_H
71
+#define QDEV_CLOCK_H
72
+
97
+
73
+#include "hw/clock.h"
98
+#include "hw/clock.h"
99
+#include "hw/sysbus.h"
100
+#include "hw/irq.h"
101
+
102
+/* Each PWM module holds 4 PWM channels. */
103
+#define NPCM7XX_PWM_PER_MODULE 4
104
+
105
+/*
106
+ * Number of registers in one pwm module. Don't change this without increasing
107
+ * the version_id in vmstate.
108
+ */
109
+#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t))
110
+
111
+/*
112
+ * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY
113
+ * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty
114
+ * value of 100,000 the duty cycle for that PWM is 10%.
115
+ */
116
+#define NPCM7XX_PWM_MAX_DUTY 1000000
117
+
118
+typedef struct NPCM7xxPWMState NPCM7xxPWMState;
74
+
119
+
75
+/**
120
+/**
76
+ * qdev_init_clock_in:
121
+ * struct NPCM7xxPWM - The state of a single PWM channel.
77
+ * @dev: the device to add an input clock to
122
+ * @module: The PWM module that contains this channel.
78
+ * @name: the name of the clock (can't be NULL).
123
+ * @irq: GIC interrupt line to fire on expiration if enabled.
79
+ * @callback: optional callback to be called on update or NULL.
124
+ * @running: Whether this PWM channel is generating output.
80
+ * @opaque: argument for the callback
125
+ * @inverted: Whether this PWM channel is inverted.
81
+ * @returns: a pointer to the newly added clock
126
+ * @index: The index of this PWM channel.
82
+ *
127
+ * @cnr: The counter register.
83
+ * Add an input clock to device @dev as a clock named @name.
128
+ * @cmr: The comparator register.
84
+ * This adds a child<> property.
129
+ * @pdr: The data register.
85
+ * The callback will be called with @opaque as opaque parameter.
130
+ * @pwdr: The watchdog register.
131
+ * @freq: The frequency of this PWM channel.
132
+ * @duty: The duty cycle of this PWM channel. One unit represents
133
+ * 1/NPCM7XX_MAX_DUTY cycles.
86
+ */
134
+ */
87
+Clock *qdev_init_clock_in(DeviceState *dev, const char *name,
135
+typedef struct NPCM7xxPWM {
88
+ ClockCallback *callback, void *opaque);
136
+ NPCM7xxPWMState *module;
137
+
138
+ qemu_irq irq;
139
+
140
+ bool running;
141
+ bool inverted;
142
+
143
+ uint8_t index;
144
+ uint32_t cnr;
145
+ uint32_t cmr;
146
+ uint32_t pdr;
147
+ uint32_t pwdr;
148
+
149
+ uint32_t freq;
150
+ uint32_t duty;
151
+} NPCM7xxPWM;
89
+
152
+
90
+/**
153
+/**
91
+ * qdev_init_clock_out:
154
+ * struct NPCM7xxPWMState - Pulse Width Modulation device state.
92
+ * @dev: the device to add an output clock to
155
+ * @parent: System bus device.
93
+ * @name: the name of the clock (can't be NULL).
156
+ * @iomem: Memory region through which registers are accessed.
94
+ * @returns: a pointer to the newly added clock
157
+ * @clock: The PWM clock.
95
+ *
158
+ * @pwm: The PWM channels owned by this module.
96
+ * Add an output clock to device @dev as a clock named @name.
159
+ * @ppr: The prescaler register.
97
+ * This adds a child<> property.
160
+ * @csr: The clock selector register.
161
+ * @pcr: The control register.
162
+ * @pier: The interrupt enable register.
163
+ * @piir: The interrupt indication register.
98
+ */
164
+ */
99
+Clock *qdev_init_clock_out(DeviceState *dev, const char *name);
165
+struct NPCM7xxPWMState {
100
+
166
+ SysBusDevice parent;
101
+/**
167
+
102
+ * qdev_get_clock_in:
168
+ MemoryRegion iomem;
103
+ * @dev: the device which has the clock
169
+
104
+ * @name: the name of the clock (can't be NULL).
170
+ Clock *clock;
105
+ * @returns: a pointer to the clock
171
+ NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE];
106
+ *
172
+
107
+ * Get the input clock @name from @dev or NULL if does not exist.
173
+ uint32_t ppr;
108
+ */
174
+ uint32_t csr;
109
+Clock *qdev_get_clock_in(DeviceState *dev, const char *name);
175
+ uint32_t pcr;
110
+
176
+ uint32_t pier;
111
+/**
177
+ uint32_t piir;
112
+ * qdev_get_clock_out:
178
+};
113
+ * @dev: the device which has the clock
179
+
114
+ * @name: the name of the clock (can't be NULL).
180
+#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
115
+ * @returns: a pointer to the clock
181
+#define NPCM7XX_PWM(obj) \
116
+ *
182
+ OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
117
+ * Get the output clock @name from @dev or NULL if does not exist.
183
+
118
+ */
184
+#endif /* NPCM7XX_PWM_H */
119
+Clock *qdev_get_clock_out(DeviceState *dev, const char *name);
185
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
120
+
121
+/**
122
+ * qdev_connect_clock_in:
123
+ * @dev: a device
124
+ * @name: the name of an input clock in @dev
125
+ * @source: the source clock (an output clock of another device for example)
126
+ *
127
+ * Set the source clock of input clock @name of device @dev to @source.
128
+ * @source period update will be propagated to @name clock.
129
+ */
130
+static inline void qdev_connect_clock_in(DeviceState *dev, const char *name,
131
+ Clock *source)
132
+{
133
+ clock_set_source(qdev_get_clock_in(dev, name), source);
134
+}
135
+
136
+/**
137
+ * qdev_alias_clock:
138
+ * @dev: the device which has the clock
139
+ * @name: the name of the clock in @dev (can't be NULL)
140
+ * @alias_dev: the device to add the clock
141
+ * @alias_name: the name of the clock in @container
142
+ * @returns: a pointer to the clock
143
+ *
144
+ * Add a clock @alias_name in @alias_dev which is an alias of the clock @name
145
+ * in @dev. The direction _in_ or _out_ will the same as the original.
146
+ * An alias clock must not be modified or used by @alias_dev and should
147
+ * typically be only only for device composition purpose.
148
+ */
149
+Clock *qdev_alias_clock(DeviceState *dev, const char *name,
150
+ DeviceState *alias_dev, const char *alias_name);
151
+
152
+/**
153
+ * qdev_finalize_clocklist:
154
+ * @dev: the device being finalized
155
+ *
156
+ * Clear the clocklist from @dev. Only used internally in qdev.
157
+ */
158
+void qdev_finalize_clocklist(DeviceState *dev);
159
+
160
+#endif /* QDEV_CLOCK_H */
161
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
162
index XXXXXXX..XXXXXXX 100644
186
index XXXXXXX..XXXXXXX 100644
163
--- a/include/hw/qdev-core.h
187
--- a/hw/arm/npcm7xx.c
164
+++ b/include/hw/qdev-core.h
188
+++ b/hw/arm/npcm7xx.c
165
@@ -XXX,XX +XXX,XX @@ struct NamedGPIOList {
189
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
166
QLIST_ENTRY(NamedGPIOList) node;
190
NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
191
NPCM7XX_EHCI_IRQ = 61,
192
NPCM7XX_OHCI_IRQ = 62,
193
+ NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */
194
+ NPCM7XX_PWM1_IRQ, /* PWM module 1 */
195
NPCM7XX_GPIO0_IRQ = 116,
196
NPCM7XX_GPIO1_IRQ,
197
NPCM7XX_GPIO2_IRQ,
198
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {
199
0xb8000000, /* CS3 */
167
};
200
};
168
201
169
+typedef struct Clock Clock;
202
+/* Register base address for each PWM Module */
170
+typedef struct NamedClockList NamedClockList;
203
+static const hwaddr npcm7xx_pwm_addr[] = {
171
+
204
+ 0xf0103000,
172
+struct NamedClockList {
205
+ 0xf0104000,
173
+ char *name;
174
+ Clock *clock;
175
+ bool output;
176
+ bool alias;
177
+ QLIST_ENTRY(NamedClockList) node;
178
+};
206
+};
179
+
207
+
180
/**
208
static const struct {
181
* DeviceState:
209
hwaddr regs_addr;
182
* @realized: Indicates whether the device has been fully constructed.
210
uint32_t unconnected_pins;
183
@@ -XXX,XX +XXX,XX @@ struct DeviceState {
211
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
184
bool allow_unplug_during_migration;
212
object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
185
BusState *parent_bus;
213
TYPE_NPCM7XX_FIU);
186
QLIST_HEAD(, NamedGPIOList) gpios;
214
}
187
+ QLIST_HEAD(, NamedClockList) clocks;
215
+
188
QLIST_HEAD(, BusState) child_bus;
216
+ for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
189
int num_child_bus;
217
+ object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
190
int instance_id_alias;
218
+ }
191
diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c
219
}
220
221
static void npcm7xx_realize(DeviceState *dev, Error **errp)
222
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
223
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
224
npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
225
226
+ /* PWM Modules. Cannot fail. */
227
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
228
+ for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
229
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);
230
+
231
+ qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(
232
+ DEVICE(&s->clk), "apb3-clock"));
233
+ sysbus_realize(sbd, &error_abort);
234
+ sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
235
+ sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
236
+ }
237
+
238
/*
239
* Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
240
* specified, but this is a programming error.
241
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
242
create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB);
243
create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB);
244
create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB);
245
- create_unimplemented_device("npcm7xx.pwm[0]", 0xf0103000, 4 * KiB);
246
- create_unimplemented_device("npcm7xx.pwm[1]", 0xf0104000, 4 * KiB);
247
create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB);
248
create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB);
249
create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB);
250
diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c
192
new file mode 100644
251
new file mode 100644
193
index XXXXXXX..XXXXXXX
252
index XXXXXXX..XXXXXXX
194
--- /dev/null
253
--- /dev/null
195
+++ b/hw/core/qdev-clock.c
254
+++ b/hw/misc/npcm7xx_pwm.c
196
@@ -XXX,XX +XXX,XX @@
255
@@ -XXX,XX +XXX,XX @@
197
+/*
256
+/*
198
+ * Device's clock input and output
257
+ * Nuvoton NPCM7xx PWM Module
199
+ *
258
+ *
200
+ * Copyright GreenSocs 2016-2020
259
+ * Copyright 2020 Google LLC
201
+ *
260
+ *
202
+ * Authors:
261
+ * This program is free software; you can redistribute it and/or modify it
203
+ * Frederic Konrad
262
+ * under the terms of the GNU General Public License as published by the
204
+ * Damien Hedde
263
+ * Free Software Foundation; either version 2 of the License, or
264
+ * (at your option) any later version.
205
+ *
265
+ *
206
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
266
+ * This program is distributed in the hope that it will be useful, but WITHOUT
207
+ * See the COPYING file in the top-level directory.
267
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
268
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
269
+ * for more details.
208
+ */
270
+ */
209
+
271
+
210
+#include "qemu/osdep.h"
272
+#include "qemu/osdep.h"
273
+#include "hw/irq.h"
211
+#include "hw/qdev-clock.h"
274
+#include "hw/qdev-clock.h"
212
+#include "hw/qdev-core.h"
275
+#include "hw/qdev-properties.h"
213
+#include "qapi/error.h"
276
+#include "hw/misc/npcm7xx_pwm.h"
214
+
277
+#include "hw/registerfields.h"
215
+/*
278
+#include "migration/vmstate.h"
216
+ * qdev_init_clocklist:
279
+#include "qemu/bitops.h"
217
+ * Add a new clock in a device
280
+#include "qemu/error-report.h"
218
+ */
281
+#include "qemu/log.h"
219
+static NamedClockList *qdev_init_clocklist(DeviceState *dev, const char *name,
282
+#include "qemu/module.h"
220
+ bool output, Clock *clk)
283
+#include "qemu/units.h"
221
+{
284
+#include "trace.h"
222
+ NamedClockList *ncl;
285
+
223
+
286
+REG32(NPCM7XX_PWM_PPR, 0x00);
224
+ /*
287
+REG32(NPCM7XX_PWM_CSR, 0x04);
225
+ * Clock must be added before realize() so that we can compute the
288
+REG32(NPCM7XX_PWM_PCR, 0x08);
226
+ * clock's canonical path during device_realize().
289
+REG32(NPCM7XX_PWM_CNR0, 0x0c);
227
+ */
290
+REG32(NPCM7XX_PWM_CMR0, 0x10);
228
+ assert(!dev->realized);
291
+REG32(NPCM7XX_PWM_PDR0, 0x14);
229
+
292
+REG32(NPCM7XX_PWM_CNR1, 0x18);
230
+ /*
293
+REG32(NPCM7XX_PWM_CMR1, 0x1c);
231
+ * The ncl structure is freed by qdev_finalize_clocklist() which will
294
+REG32(NPCM7XX_PWM_PDR1, 0x20);
232
+ * be called during @dev's device_finalize().
295
+REG32(NPCM7XX_PWM_CNR2, 0x24);
233
+ */
296
+REG32(NPCM7XX_PWM_CMR2, 0x28);
234
+ ncl = g_new0(NamedClockList, 1);
297
+REG32(NPCM7XX_PWM_PDR2, 0x2c);
235
+ ncl->name = g_strdup(name);
298
+REG32(NPCM7XX_PWM_CNR3, 0x30);
236
+ ncl->output = output;
299
+REG32(NPCM7XX_PWM_CMR3, 0x34);
237
+ ncl->alias = (clk != NULL);
300
+REG32(NPCM7XX_PWM_PDR3, 0x38);
238
+
301
+REG32(NPCM7XX_PWM_PIER, 0x3c);
239
+ /*
302
+REG32(NPCM7XX_PWM_PIIR, 0x40);
240
+ * Trying to create a clock whose name clashes with some other
303
+REG32(NPCM7XX_PWM_PWDR0, 0x44);
241
+ * clock or property is a bug in the caller and we will abort().
304
+REG32(NPCM7XX_PWM_PWDR1, 0x48);
242
+ */
305
+REG32(NPCM7XX_PWM_PWDR2, 0x4c);
243
+ if (clk == NULL) {
306
+REG32(NPCM7XX_PWM_PWDR3, 0x50);
244
+ clk = CLOCK(object_new(TYPE_CLOCK));
307
+
245
+ object_property_add_child(OBJECT(dev), name, OBJECT(clk), &error_abort);
308
+/* Register field definitions. */
246
+ if (output) {
309
+#define NPCM7XX_PPR(rv, index) extract32((rv), npcm7xx_ppr_base[index], 8)
247
+ /*
310
+#define NPCM7XX_CSR(rv, index) extract32((rv), npcm7xx_csr_base[index], 3)
248
+ * Remove object_new()'s initial reference.
311
+#define NPCM7XX_CH(rv, index) extract32((rv), npcm7xx_ch_base[index], 4)
249
+ * Note that for inputs, the reference created by object_new()
312
+#define NPCM7XX_CH_EN BIT(0)
250
+ * will be deleted in qdev_finalize_clocklist().
313
+#define NPCM7XX_CH_INV BIT(2)
251
+ */
314
+#define NPCM7XX_CH_MOD BIT(3)
252
+ object_unref(OBJECT(clk));
315
+
316
+/* Offset of each PWM channel's prescaler in the PPR register. */
317
+static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 };
318
+/* Offset of each PWM channel's clock selector in the CSR register. */
319
+static const int npcm7xx_csr_base[] = { 0, 4, 8, 12 };
320
+/* Offset of each PWM channel's control variable in the PCR register. */
321
+static const int npcm7xx_ch_base[] = { 0, 8, 12, 16 };
322
+
323
+static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p)
324
+{
325
+ uint32_t ppr;
326
+ uint32_t csr;
327
+ uint32_t freq;
328
+
329
+ if (!p->running) {
330
+ return 0;
331
+ }
332
+
333
+ csr = NPCM7XX_CSR(p->module->csr, p->index);
334
+ ppr = NPCM7XX_PPR(p->module->ppr, p->index);
335
+ freq = clock_get_hz(p->module->clock);
336
+ freq /= ppr + 1;
337
+ /* csr can only be 0~4 */
338
+ if (csr > 4) {
339
+ qemu_log_mask(LOG_GUEST_ERROR,
340
+ "%s: invalid csr value %u\n",
341
+ __func__, csr);
342
+ csr = 4;
343
+ }
344
+ /* freq won't be changed if csr == 4. */
345
+ if (csr < 4) {
346
+ freq >>= csr + 1;
347
+ }
348
+
349
+ return freq / (p->cnr + 1);
350
+}
351
+
352
+static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)
353
+{
354
+ uint64_t duty;
355
+
356
+ if (p->running) {
357
+ if (p->cnr == 0) {
358
+ duty = 0;
359
+ } else if (p->cmr >= p->cnr) {
360
+ duty = NPCM7XX_PWM_MAX_DUTY;
361
+ } else {
362
+ duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1);
253
+ }
363
+ }
254
+ } else {
364
+ } else {
255
+ object_property_add_link(OBJECT(dev), name,
365
+ duty = 0;
256
+ object_get_typename(OBJECT(clk)),
366
+ }
257
+ (Object **) &ncl->clock,
367
+
258
+ NULL, OBJ_PROP_LINK_STRONG, &error_abort);
368
+ if (p->inverted) {
259
+ }
369
+ duty = NPCM7XX_PWM_MAX_DUTY - duty;
260
+
370
+ }
261
+ ncl->clock = clk;
371
+
262
+
372
+ return duty;
263
+ QLIST_INSERT_HEAD(&dev->clocks, ncl, node);
373
+}
264
+ return ncl;
374
+
265
+}
375
+static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p)
266
+
376
+{
267
+void qdev_finalize_clocklist(DeviceState *dev)
377
+ uint32_t freq = npcm7xx_pwm_calculate_freq(p);
268
+{
378
+
269
+ /* called by @dev's device_finalize() */
379
+ if (freq != p->freq) {
270
+ NamedClockList *ncl, *ncl_next;
380
+ trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path,
271
+
381
+ p->index, p->freq, freq);
272
+ QLIST_FOREACH_SAFE(ncl, &dev->clocks, node, ncl_next) {
382
+ p->freq = freq;
273
+ QLIST_REMOVE(ncl, node);
383
+ }
274
+ if (!ncl->output && !ncl->alias) {
384
+}
275
+ /*
385
+
276
+ * We kept a reference on the input clock to ensure it lives up to
386
+static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p)
277
+ * this point so we can safely remove the callback.
387
+{
278
+ * It avoids having a callback to a deleted object if ncl->clock
388
+ uint32_t duty = npcm7xx_pwm_calculate_duty(p);
279
+ * is still referenced somewhere else (eg: by a clock output).
389
+
280
+ */
390
+ if (duty != p->duty) {
281
+ clock_clear_callback(ncl->clock);
391
+ trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path,
282
+ object_unref(OBJECT(ncl->clock));
392
+ p->index, p->duty, duty);
393
+ p->duty = duty;
394
+ }
395
+}
396
+
397
+static void npcm7xx_pwm_update_output(NPCM7xxPWM *p)
398
+{
399
+ npcm7xx_pwm_update_freq(p);
400
+ npcm7xx_pwm_update_duty(p);
401
+}
402
+
403
+static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr)
404
+{
405
+ int i;
406
+ uint32_t old_ppr = s->ppr;
407
+
408
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) != NPCM7XX_PWM_PER_MODULE);
409
+ s->ppr = new_ppr;
410
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
411
+ if (NPCM7XX_PPR(old_ppr, i) != NPCM7XX_PPR(new_ppr, i)) {
412
+ npcm7xx_pwm_update_freq(&s->pwm[i]);
283
+ }
413
+ }
284
+ g_free(ncl->name);
414
+ }
285
+ g_free(ncl);
415
+}
286
+ }
416
+
287
+}
417
+static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr)
288
+
418
+{
289
+Clock *qdev_init_clock_out(DeviceState *dev, const char *name)
419
+ int i;
290
+{
420
+ uint32_t old_csr = s->csr;
291
+ NamedClockList *ncl;
421
+
292
+
422
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) != NPCM7XX_PWM_PER_MODULE);
293
+ assert(name);
423
+ s->csr = new_csr;
294
+
424
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
295
+ ncl = qdev_init_clocklist(dev, name, true, NULL);
425
+ if (NPCM7XX_CSR(old_csr, i) != NPCM7XX_CSR(new_csr, i)) {
296
+
426
+ npcm7xx_pwm_update_freq(&s->pwm[i]);
297
+ return ncl->clock;
298
+}
299
+
300
+Clock *qdev_init_clock_in(DeviceState *dev, const char *name,
301
+ ClockCallback *callback, void *opaque)
302
+{
303
+ NamedClockList *ncl;
304
+
305
+ assert(name);
306
+
307
+ ncl = qdev_init_clocklist(dev, name, false, NULL);
308
+
309
+ if (callback) {
310
+ clock_set_callback(ncl->clock, callback, opaque);
311
+ }
312
+ return ncl->clock;
313
+}
314
+
315
+static NamedClockList *qdev_get_clocklist(DeviceState *dev, const char *name)
316
+{
317
+ NamedClockList *ncl;
318
+
319
+ QLIST_FOREACH(ncl, &dev->clocks, node) {
320
+ if (strcmp(name, ncl->name) == 0) {
321
+ return ncl;
322
+ }
427
+ }
323
+ }
428
+ }
324
+
429
+}
325
+ return NULL;
430
+
326
+}
431
+static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr)
327
+
432
+{
328
+Clock *qdev_get_clock_in(DeviceState *dev, const char *name)
433
+ int i;
329
+{
434
+ bool inverted;
330
+ NamedClockList *ncl;
435
+ uint32_t pcr;
331
+
436
+ NPCM7xxPWM *p;
332
+ assert(name);
437
+
333
+
438
+ s->pcr = new_pcr;
334
+ ncl = qdev_get_clocklist(dev, name);
439
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) != NPCM7XX_PWM_PER_MODULE);
335
+ assert(!ncl->output);
440
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
336
+
441
+ p = &s->pwm[i];
337
+ return ncl->clock;
442
+ pcr = NPCM7XX_CH(new_pcr, i);
338
+}
443
+ inverted = pcr & NPCM7XX_CH_INV;
339
+
444
+
340
+Clock *qdev_get_clock_out(DeviceState *dev, const char *name)
445
+ /*
341
+{
446
+ * We only run a PWM channel with toggle mode. Single-shot mode does not
342
+ NamedClockList *ncl;
447
+ * generate frequency and duty-cycle values.
343
+
448
+ */
344
+ assert(name);
449
+ if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) {
345
+
450
+ if (p->running) {
346
+ ncl = qdev_get_clocklist(dev, name);
451
+ /* Re-run this PWM channel if inverted changed. */
347
+ assert(ncl->output);
452
+ if (p->inverted ^ inverted) {
348
+
453
+ p->inverted = inverted;
349
+ return ncl->clock;
454
+ npcm7xx_pwm_update_duty(p);
350
+}
455
+ }
351
+
456
+ } else {
352
+Clock *qdev_alias_clock(DeviceState *dev, const char *name,
457
+ /* Run this PWM channel. */
353
+ DeviceState *alias_dev, const char *alias_name)
458
+ p->running = true;
354
+{
459
+ p->inverted = inverted;
355
+ NamedClockList *ncl;
460
+ npcm7xx_pwm_update_output(p);
356
+
461
+ }
357
+ assert(name && alias_name);
462
+ } else {
358
+
463
+ /* Clear this PWM channel. */
359
+ ncl = qdev_get_clocklist(dev, name);
464
+ p->running = false;
360
+
465
+ p->inverted = inverted;
361
+ qdev_init_clocklist(alias_dev, alias_name, ncl->output, ncl->clock);
466
+ npcm7xx_pwm_update_output(p);
362
+
467
+ }
363
+ return ncl->clock;
468
+ }
364
+}
469
+
365
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
470
+}
471
+
472
+static hwaddr npcm7xx_cnr_index(hwaddr offset)
473
+{
474
+ switch (offset) {
475
+ case A_NPCM7XX_PWM_CNR0:
476
+ return 0;
477
+ case A_NPCM7XX_PWM_CNR1:
478
+ return 1;
479
+ case A_NPCM7XX_PWM_CNR2:
480
+ return 2;
481
+ case A_NPCM7XX_PWM_CNR3:
482
+ return 3;
483
+ default:
484
+ g_assert_not_reached();
485
+ }
486
+}
487
+
488
+static hwaddr npcm7xx_cmr_index(hwaddr offset)
489
+{
490
+ switch (offset) {
491
+ case A_NPCM7XX_PWM_CMR0:
492
+ return 0;
493
+ case A_NPCM7XX_PWM_CMR1:
494
+ return 1;
495
+ case A_NPCM7XX_PWM_CMR2:
496
+ return 2;
497
+ case A_NPCM7XX_PWM_CMR3:
498
+ return 3;
499
+ default:
500
+ g_assert_not_reached();
501
+ }
502
+}
503
+
504
+static hwaddr npcm7xx_pdr_index(hwaddr offset)
505
+{
506
+ switch (offset) {
507
+ case A_NPCM7XX_PWM_PDR0:
508
+ return 0;
509
+ case A_NPCM7XX_PWM_PDR1:
510
+ return 1;
511
+ case A_NPCM7XX_PWM_PDR2:
512
+ return 2;
513
+ case A_NPCM7XX_PWM_PDR3:
514
+ return 3;
515
+ default:
516
+ g_assert_not_reached();
517
+ }
518
+}
519
+
520
+static hwaddr npcm7xx_pwdr_index(hwaddr offset)
521
+{
522
+ switch (offset) {
523
+ case A_NPCM7XX_PWM_PWDR0:
524
+ return 0;
525
+ case A_NPCM7XX_PWM_PWDR1:
526
+ return 1;
527
+ case A_NPCM7XX_PWM_PWDR2:
528
+ return 2;
529
+ case A_NPCM7XX_PWM_PWDR3:
530
+ return 3;
531
+ default:
532
+ g_assert_not_reached();
533
+ }
534
+}
535
+
536
+static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned size)
537
+{
538
+ NPCM7xxPWMState *s = opaque;
539
+ uint64_t value = 0;
540
+
541
+ switch (offset) {
542
+ case A_NPCM7XX_PWM_CNR0:
543
+ case A_NPCM7XX_PWM_CNR1:
544
+ case A_NPCM7XX_PWM_CNR2:
545
+ case A_NPCM7XX_PWM_CNR3:
546
+ value = s->pwm[npcm7xx_cnr_index(offset)].cnr;
547
+ break;
548
+
549
+ case A_NPCM7XX_PWM_CMR0:
550
+ case A_NPCM7XX_PWM_CMR1:
551
+ case A_NPCM7XX_PWM_CMR2:
552
+ case A_NPCM7XX_PWM_CMR3:
553
+ value = s->pwm[npcm7xx_cmr_index(offset)].cmr;
554
+ break;
555
+
556
+ case A_NPCM7XX_PWM_PDR0:
557
+ case A_NPCM7XX_PWM_PDR1:
558
+ case A_NPCM7XX_PWM_PDR2:
559
+ case A_NPCM7XX_PWM_PDR3:
560
+ value = s->pwm[npcm7xx_pdr_index(offset)].pdr;
561
+ break;
562
+
563
+ case A_NPCM7XX_PWM_PWDR0:
564
+ case A_NPCM7XX_PWM_PWDR1:
565
+ case A_NPCM7XX_PWM_PWDR2:
566
+ case A_NPCM7XX_PWM_PWDR3:
567
+ value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr;
568
+ break;
569
+
570
+ case A_NPCM7XX_PWM_PPR:
571
+ value = s->ppr;
572
+ break;
573
+
574
+ case A_NPCM7XX_PWM_CSR:
575
+ value = s->csr;
576
+ break;
577
+
578
+ case A_NPCM7XX_PWM_PCR:
579
+ value = s->pcr;
580
+ break;
581
+
582
+ case A_NPCM7XX_PWM_PIER:
583
+ value = s->pier;
584
+ break;
585
+
586
+ case A_NPCM7XX_PWM_PIIR:
587
+ value = s->piir;
588
+ break;
589
+
590
+ default:
591
+ qemu_log_mask(LOG_GUEST_ERROR,
592
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
593
+ __func__, offset);
594
+ break;
595
+ }
596
+
597
+ trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value);
598
+ return value;
599
+}
600
+
601
+static void npcm7xx_pwm_write(void *opaque, hwaddr offset,
602
+ uint64_t v, unsigned size)
603
+{
604
+ NPCM7xxPWMState *s = opaque;
605
+ NPCM7xxPWM *p;
606
+ uint32_t value = v;
607
+
608
+ trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value);
609
+ switch (offset) {
610
+ case A_NPCM7XX_PWM_CNR0:
611
+ case A_NPCM7XX_PWM_CNR1:
612
+ case A_NPCM7XX_PWM_CNR2:
613
+ case A_NPCM7XX_PWM_CNR3:
614
+ p = &s->pwm[npcm7xx_cnr_index(offset)];
615
+ p->cnr = value;
616
+ npcm7xx_pwm_update_output(p);
617
+ break;
618
+
619
+ case A_NPCM7XX_PWM_CMR0:
620
+ case A_NPCM7XX_PWM_CMR1:
621
+ case A_NPCM7XX_PWM_CMR2:
622
+ case A_NPCM7XX_PWM_CMR3:
623
+ p = &s->pwm[npcm7xx_cmr_index(offset)];
624
+ p->cmr = value;
625
+ npcm7xx_pwm_update_output(p);
626
+ break;
627
+
628
+ case A_NPCM7XX_PWM_PDR0:
629
+ case A_NPCM7XX_PWM_PDR1:
630
+ case A_NPCM7XX_PWM_PDR2:
631
+ case A_NPCM7XX_PWM_PDR3:
632
+ qemu_log_mask(LOG_GUEST_ERROR,
633
+ "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
634
+ __func__, offset);
635
+ break;
636
+
637
+ case A_NPCM7XX_PWM_PWDR0:
638
+ case A_NPCM7XX_PWM_PWDR1:
639
+ case A_NPCM7XX_PWM_PWDR2:
640
+ case A_NPCM7XX_PWM_PWDR3:
641
+ qemu_log_mask(LOG_UNIMP,
642
+ "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
643
+ __func__, offset);
644
+ break;
645
+
646
+ case A_NPCM7XX_PWM_PPR:
647
+ npcm7xx_pwm_write_ppr(s, value);
648
+ break;
649
+
650
+ case A_NPCM7XX_PWM_CSR:
651
+ npcm7xx_pwm_write_csr(s, value);
652
+ break;
653
+
654
+ case A_NPCM7XX_PWM_PCR:
655
+ npcm7xx_pwm_write_pcr(s, value);
656
+ break;
657
+
658
+ case A_NPCM7XX_PWM_PIER:
659
+ qemu_log_mask(LOG_UNIMP,
660
+ "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
661
+ __func__, offset);
662
+ break;
663
+
664
+ case A_NPCM7XX_PWM_PIIR:
665
+ qemu_log_mask(LOG_UNIMP,
666
+ "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
667
+ __func__, offset);
668
+ break;
669
+
670
+ default:
671
+ qemu_log_mask(LOG_GUEST_ERROR,
672
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
673
+ __func__, offset);
674
+ break;
675
+ }
676
+}
677
+
678
+static const struct MemoryRegionOps npcm7xx_pwm_ops = {
679
+ .read = npcm7xx_pwm_read,
680
+ .write = npcm7xx_pwm_write,
681
+ .endianness = DEVICE_LITTLE_ENDIAN,
682
+ .valid = {
683
+ .min_access_size = 4,
684
+ .max_access_size = 4,
685
+ .unaligned = false,
686
+ },
687
+};
688
+
689
+static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type)
690
+{
691
+ NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
692
+ int i;
693
+
694
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
695
+ NPCM7xxPWM *p = &s->pwm[i];
696
+
697
+ p->cnr = 0x00000000;
698
+ p->cmr = 0x00000000;
699
+ p->pdr = 0x00000000;
700
+ p->pwdr = 0x00000000;
701
+ }
702
+
703
+ s->ppr = 0x00000000;
704
+ s->csr = 0x00000000;
705
+ s->pcr = 0x00000000;
706
+ s->pier = 0x00000000;
707
+ s->piir = 0x00000000;
708
+}
709
+
710
+static void npcm7xx_pwm_hold_reset(Object *obj)
711
+{
712
+ NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
713
+ int i;
714
+
715
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
716
+ qemu_irq_lower(s->pwm[i].irq);
717
+ }
718
+}
719
+
720
+static void npcm7xx_pwm_init(Object *obj)
721
+{
722
+ NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
723
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
724
+ int i;
725
+
726
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
727
+ NPCM7xxPWM *p = &s->pwm[i];
728
+ p->module = s;
729
+ p->index = i;
730
+ sysbus_init_irq(sbd, &p->irq);
731
+ }
732
+
733
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s,
734
+ TYPE_NPCM7XX_PWM, 4 * KiB);
735
+ sysbus_init_mmio(sbd, &s->iomem);
736
+ s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
737
+
738
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
739
+ object_property_add_uint32_ptr(obj, "freq[*]",
740
+ &s->pwm[i].freq, OBJ_PROP_FLAG_READ);
741
+ object_property_add_uint32_ptr(obj, "duty[*]",
742
+ &s->pwm[i].duty, OBJ_PROP_FLAG_READ);
743
+ }
744
+}
745
+
746
+static const VMStateDescription vmstate_npcm7xx_pwm = {
747
+ .name = "npcm7xx-pwm",
748
+ .version_id = 0,
749
+ .minimum_version_id = 0,
750
+ .fields = (VMStateField[]) {
751
+ VMSTATE_BOOL(running, NPCM7xxPWM),
752
+ VMSTATE_BOOL(inverted, NPCM7xxPWM),
753
+ VMSTATE_UINT8(index, NPCM7xxPWM),
754
+ VMSTATE_UINT32(cnr, NPCM7xxPWM),
755
+ VMSTATE_UINT32(cmr, NPCM7xxPWM),
756
+ VMSTATE_UINT32(pdr, NPCM7xxPWM),
757
+ VMSTATE_UINT32(pwdr, NPCM7xxPWM),
758
+ VMSTATE_UINT32(freq, NPCM7xxPWM),
759
+ VMSTATE_UINT32(duty, NPCM7xxPWM),
760
+ VMSTATE_END_OF_LIST(),
761
+ },
762
+};
763
+
764
+static const VMStateDescription vmstate_npcm7xx_pwm_module = {
765
+ .name = "npcm7xx-pwm-module",
766
+ .version_id = 0,
767
+ .minimum_version_id = 0,
768
+ .fields = (VMStateField[]) {
769
+ VMSTATE_CLOCK(clock, NPCM7xxPWMState),
770
+ VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState,
771
+ NPCM7XX_PWM_PER_MODULE, 0, vmstate_npcm7xx_pwm,
772
+ NPCM7xxPWM),
773
+ VMSTATE_UINT32(ppr, NPCM7xxPWMState),
774
+ VMSTATE_UINT32(csr, NPCM7xxPWMState),
775
+ VMSTATE_UINT32(pcr, NPCM7xxPWMState),
776
+ VMSTATE_UINT32(pier, NPCM7xxPWMState),
777
+ VMSTATE_UINT32(piir, NPCM7xxPWMState),
778
+ VMSTATE_END_OF_LIST(),
779
+ },
780
+};
781
+
782
+static void npcm7xx_pwm_class_init(ObjectClass *klass, void *data)
783
+{
784
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
785
+ DeviceClass *dc = DEVICE_CLASS(klass);
786
+
787
+ dc->desc = "NPCM7xx PWM Controller";
788
+ dc->vmsd = &vmstate_npcm7xx_pwm_module;
789
+ rc->phases.enter = npcm7xx_pwm_enter_reset;
790
+ rc->phases.hold = npcm7xx_pwm_hold_reset;
791
+}
792
+
793
+static const TypeInfo npcm7xx_pwm_info = {
794
+ .name = TYPE_NPCM7XX_PWM,
795
+ .parent = TYPE_SYS_BUS_DEVICE,
796
+ .instance_size = sizeof(NPCM7xxPWMState),
797
+ .class_init = npcm7xx_pwm_class_init,
798
+ .instance_init = npcm7xx_pwm_init,
799
+};
800
+
801
+static void npcm7xx_pwm_register_type(void)
802
+{
803
+ type_register_static(&npcm7xx_pwm_info);
804
+}
805
+type_init(npcm7xx_pwm_register_type);
806
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
366
index XXXXXXX..XXXXXXX 100644
807
index XXXXXXX..XXXXXXX 100644
367
--- a/hw/core/qdev.c
808
--- a/hw/misc/meson.build
368
+++ b/hw/core/qdev.c
809
+++ b/hw/misc/meson.build
369
@@ -XXX,XX +XXX,XX @@
810
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
370
#include "hw/qdev-properties.h"
811
softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
371
#include "hw/boards.h"
812
'npcm7xx_clk.c',
372
#include "hw/sysbus.h"
813
'npcm7xx_gcr.c',
373
+#include "hw/qdev-clock.h"
814
+ 'npcm7xx_pwm.c',
374
#include "migration/vmstate.h"
815
'npcm7xx_rng.c',
375
#include "trace.h"
816
))
376
817
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
377
@@ -XXX,XX +XXX,XX @@ static void device_set_realized(Object *obj, bool value, Error **errp)
818
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
378
DeviceClass *dc = DEVICE_GET_CLASS(dev);
819
index XXXXXXX..XXXXXXX 100644
379
HotplugHandler *hotplug_ctrl;
820
--- a/hw/misc/trace-events
380
BusState *bus;
821
+++ b/hw/misc/trace-events
381
+ NamedClockList *ncl;
822
@@ -XXX,XX +XXX,XX @@ npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu
382
Error *local_err = NULL;
823
npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
383
bool unattached_parent = false;
824
npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
384
static int unattached_count;
825
385
@@ -XXX,XX +XXX,XX @@ static void device_set_realized(Object *obj, bool value, Error **errp)
826
+# npcm7xx_pwm.c
386
*/
827
+npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
387
g_free(dev->canonical_path);
828
+npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
388
dev->canonical_path = object_get_canonical_path(OBJECT(dev));
829
+npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u"
389
+ QLIST_FOREACH(ncl, &dev->clocks, node) {
830
+npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u"
390
+ if (ncl->alias) {
831
+
391
+ continue;
832
# stm32f4xx_syscfg.c
392
+ } else {
833
stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
393
+ clock_setup_canonical_path(ncl->clock);
834
stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
394
+ }
395
+ }
396
397
if (qdev_get_vmsd(dev)) {
398
if (vmstate_register_with_alias_id(VMSTATE_IF(dev),
399
@@ -XXX,XX +XXX,XX @@ static void device_initfn(Object *obj)
400
dev->allow_unplug_during_migration = false;
401
402
QLIST_INIT(&dev->gpios);
403
+ QLIST_INIT(&dev->clocks);
404
}
405
406
static void device_post_init(Object *obj)
407
@@ -XXX,XX +XXX,XX @@ static void device_finalize(Object *obj)
408
*/
409
}
410
411
+ qdev_finalize_clocklist(dev);
412
+
413
/* Only send event if the device had been completely realized */
414
if (dev->pending_deleted_event) {
415
g_assert(dev->canonical_path);
416
--
835
--
417
2.20.1
836
2.20.1
418
837
419
838
diff view generated by jsdifflib
1
From: Damien Hedde <damien.hedde@greensocs.com>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
3
We add a qtest for the PWM in the previous patch. It proves it works as
4
expected.
5
6
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
7
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
8
Signed-off-by: Hao Wu <wuhaotsh@google.com>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20210108190945.949196-6-wuhaotsh@google.com
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Message-id: 20200406135251.157596-3-damien.hedde@greensocs.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
hw/core/Makefile.objs | 1 +
13
tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++++++++++++++++
12
include/hw/clock.h | 9 +++++++++
14
tests/qtest/meson.build | 1 +
13
hw/core/clock-vmstate.c | 25 +++++++++++++++++++++++++
15
2 files changed, 491 insertions(+)
14
3 files changed, 35 insertions(+)
16
create mode 100644 tests/qtest/npcm7xx_pwm-test.c
15
create mode 100644 hw/core/clock-vmstate.c
16
17
17
diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
18
diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/core/Makefile.objs
20
+++ b/hw/core/Makefile.objs
21
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SOFTMMU) += null-machine.o
22
common-obj-$(CONFIG_SOFTMMU) += loader.o
23
common-obj-$(CONFIG_SOFTMMU) += machine-hmp-cmds.o
24
common-obj-$(CONFIG_SOFTMMU) += numa.o
25
+common-obj-$(CONFIG_SOFTMMU) += clock-vmstate.o
26
obj-$(CONFIG_SOFTMMU) += machine-qmp-cmds.o
27
28
common-obj-$(CONFIG_EMPTY_SLOT) += empty_slot.o
29
diff --git a/include/hw/clock.h b/include/hw/clock.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/include/hw/clock.h
32
+++ b/include/hw/clock.h
33
@@ -XXX,XX +XXX,XX @@ struct Clock {
34
QLIST_ENTRY(Clock) sibling;
35
};
36
37
+/*
38
+ * vmstate description entry to be added in device vmsd.
39
+ */
40
+extern const VMStateDescription vmstate_clock;
41
+#define VMSTATE_CLOCK(field, state) \
42
+ VMSTATE_CLOCK_V(field, state, 0)
43
+#define VMSTATE_CLOCK_V(field, state, version) \
44
+ VMSTATE_STRUCT_POINTER_V(field, state, version, vmstate_clock, Clock)
45
+
46
/**
47
* clock_setup_canonical_path:
48
* @clk: clock
49
diff --git a/hw/core/clock-vmstate.c b/hw/core/clock-vmstate.c
50
new file mode 100644
19
new file mode 100644
51
index XXXXXXX..XXXXXXX
20
index XXXXXXX..XXXXXXX
52
--- /dev/null
21
--- /dev/null
53
+++ b/hw/core/clock-vmstate.c
22
+++ b/tests/qtest/npcm7xx_pwm-test.c
54
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@
55
+/*
24
+/*
56
+ * Clock migration structure
25
+ * QTests for Nuvoton NPCM7xx PWM Modules.
57
+ *
26
+ *
58
+ * Copyright GreenSocs 2019-2020
27
+ * Copyright 2020 Google LLC
59
+ *
28
+ *
60
+ * Authors:
29
+ * This program is free software; you can redistribute it and/or modify it
61
+ * Damien Hedde
30
+ * under the terms of the GNU General Public License as published by the
31
+ * Free Software Foundation; either version 2 of the License, or
32
+ * (at your option) any later version.
62
+ *
33
+ *
63
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
34
+ * This program is distributed in the hope that it will be useful, but WITHOUT
64
+ * See the COPYING file in the top-level directory.
35
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
36
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
37
+ * for more details.
65
+ */
38
+ */
66
+
39
+
67
+#include "qemu/osdep.h"
40
+#include "qemu/osdep.h"
68
+#include "migration/vmstate.h"
41
+#include "qemu/bitops.h"
69
+#include "hw/clock.h"
42
+#include "libqos/libqtest.h"
70
+
43
+#include "qapi/qmp/qdict.h"
71
+const VMStateDescription vmstate_clock = {
44
+#include "qapi/qmp/qnum.h"
72
+ .name = "clock",
45
+
73
+ .version_id = 0,
46
+#define REF_HZ 25000000
74
+ .minimum_version_id = 0,
47
+
75
+ .fields = (VMStateField[]) {
48
+/* Register field definitions. */
76
+ VMSTATE_UINT64(period, Clock),
49
+#define CH_EN BIT(0)
77
+ VMSTATE_END_OF_LIST()
50
+#define CH_INV BIT(2)
51
+#define CH_MOD BIT(3)
52
+
53
+/* Registers shared between all PWMs in a module */
54
+#define PPR 0x00
55
+#define CSR 0x04
56
+#define PCR 0x08
57
+#define PIER 0x3c
58
+#define PIIR 0x40
59
+
60
+/* CLK module related */
61
+#define CLK_BA 0xf0801000
62
+#define CLKSEL 0x04
63
+#define CLKDIV1 0x08
64
+#define CLKDIV2 0x2c
65
+#define PLLCON0 0x0c
66
+#define PLLCON1 0x10
67
+#define PLL_INDV(rv) extract32((rv), 0, 6)
68
+#define PLL_FBDV(rv) extract32((rv), 16, 12)
69
+#define PLL_OTDV1(rv) extract32((rv), 8, 3)
70
+#define PLL_OTDV2(rv) extract32((rv), 13, 3)
71
+#define APB3CKDIV(rv) extract32((rv), 28, 2)
72
+#define CLK2CKDIV(rv) extract32((rv), 0, 1)
73
+#define CLK4CKDIV(rv) extract32((rv), 26, 2)
74
+#define CPUCKSEL(rv) extract32((rv), 0, 2)
75
+
76
+#define MAX_DUTY 1000000
77
+
78
+typedef struct PWMModule {
79
+ int irq;
80
+ uint64_t base_addr;
81
+} PWMModule;
82
+
83
+typedef struct PWM {
84
+ uint32_t cnr_offset;
85
+ uint32_t cmr_offset;
86
+ uint32_t pdr_offset;
87
+ uint32_t pwdr_offset;
88
+} PWM;
89
+
90
+typedef struct TestData {
91
+ const PWMModule *module;
92
+ const PWM *pwm;
93
+} TestData;
94
+
95
+static const PWMModule pwm_module_list[] = {
96
+ {
97
+ .irq = 93,
98
+ .base_addr = 0xf0103000
99
+ },
100
+ {
101
+ .irq = 94,
102
+ .base_addr = 0xf0104000
78
+ }
103
+ }
79
+};
104
+};
105
+
106
+static const PWM pwm_list[] = {
107
+ {
108
+ .cnr_offset = 0x0c,
109
+ .cmr_offset = 0x10,
110
+ .pdr_offset = 0x14,
111
+ .pwdr_offset = 0x44,
112
+ },
113
+ {
114
+ .cnr_offset = 0x18,
115
+ .cmr_offset = 0x1c,
116
+ .pdr_offset = 0x20,
117
+ .pwdr_offset = 0x48,
118
+ },
119
+ {
120
+ .cnr_offset = 0x24,
121
+ .cmr_offset = 0x28,
122
+ .pdr_offset = 0x2c,
123
+ .pwdr_offset = 0x4c,
124
+ },
125
+ {
126
+ .cnr_offset = 0x30,
127
+ .cmr_offset = 0x34,
128
+ .pdr_offset = 0x38,
129
+ .pwdr_offset = 0x50,
130
+ },
131
+};
132
+
133
+static const int ppr_base[] = { 0, 0, 8, 8 };
134
+static const int csr_base[] = { 0, 4, 8, 12 };
135
+static const int pcr_base[] = { 0, 8, 12, 16 };
136
+
137
+static const uint32_t ppr_list[] = {
138
+ 0,
139
+ 1,
140
+ 10,
141
+ 100,
142
+ 255, /* Max possible value. */
143
+};
144
+
145
+static const uint32_t csr_list[] = {
146
+ 0,
147
+ 1,
148
+ 2,
149
+ 3,
150
+ 4, /* Max possible value. */
151
+};
152
+
153
+static const uint32_t cnr_list[] = {
154
+ 0,
155
+ 1,
156
+ 50,
157
+ 100,
158
+ 150,
159
+ 200,
160
+ 1000,
161
+ 10000,
162
+ 65535, /* Max possible value. */
163
+};
164
+
165
+static const uint32_t cmr_list[] = {
166
+ 0,
167
+ 1,
168
+ 10,
169
+ 50,
170
+ 100,
171
+ 150,
172
+ 200,
173
+ 1000,
174
+ 10000,
175
+ 65535, /* Max possible value. */
176
+};
177
+
178
+/* Returns the index of the PWM module. */
179
+static int pwm_module_index(const PWMModule *module)
180
+{
181
+ ptrdiff_t diff = module - pwm_module_list;
182
+
183
+ g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list));
184
+
185
+ return diff;
186
+}
187
+
188
+/* Returns the index of the PWM entry. */
189
+static int pwm_index(const PWM *pwm)
190
+{
191
+ ptrdiff_t diff = pwm - pwm_list;
192
+
193
+ g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list));
194
+
195
+ return diff;
196
+}
197
+
198
+static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name)
199
+{
200
+ QDict *response;
201
+
202
+ g_test_message("Getting properties %s from %s", name, path);
203
+ response = qtest_qmp(qts, "{ 'execute': 'qom-get',"
204
+ " 'arguments': { 'path': %s, 'property': %s}}",
205
+ path, name);
206
+ /* The qom set message returns successfully. */
207
+ g_assert_true(qdict_haskey(response, "return"));
208
+ return qnum_get_uint(qobject_to(QNum, qdict_get(response, "return")));
209
+}
210
+
211
+static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index)
212
+{
213
+ char path[100];
214
+ char name[100];
215
+
216
+ sprintf(path, "/machine/soc/pwm[%d]", module_index);
217
+ sprintf(name, "freq[%d]", pwm_index);
218
+
219
+ return pwm_qom_get(qts, path, name);
220
+}
221
+
222
+static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index)
223
+{
224
+ char path[100];
225
+ char name[100];
226
+
227
+ sprintf(path, "/machine/soc/pwm[%d]", module_index);
228
+ sprintf(name, "duty[%d]", pwm_index);
229
+
230
+ return pwm_qom_get(qts, path, name);
231
+}
232
+
233
+static uint32_t get_pll(uint32_t con)
234
+{
235
+ return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con)
236
+ * PLL_OTDV2(con));
237
+}
238
+
239
+static uint64_t read_pclk(QTestState *qts)
240
+{
241
+ uint64_t freq = REF_HZ;
242
+ uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL);
243
+ uint32_t pllcon;
244
+ uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1);
245
+ uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2);
246
+
247
+ switch (CPUCKSEL(clksel)) {
248
+ case 0:
249
+ pllcon = qtest_readl(qts, CLK_BA + PLLCON0);
250
+ freq = get_pll(pllcon);
251
+ break;
252
+ case 1:
253
+ pllcon = qtest_readl(qts, CLK_BA + PLLCON1);
254
+ freq = get_pll(pllcon);
255
+ break;
256
+ case 2:
257
+ break;
258
+ case 3:
259
+ break;
260
+ default:
261
+ g_assert_not_reached();
262
+ }
263
+
264
+ freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2));
265
+
266
+ return freq;
267
+}
268
+
269
+static uint32_t pwm_selector(uint32_t csr)
270
+{
271
+ switch (csr) {
272
+ case 0:
273
+ return 2;
274
+ case 1:
275
+ return 4;
276
+ case 2:
277
+ return 8;
278
+ case 3:
279
+ return 16;
280
+ case 4:
281
+ return 1;
282
+ default:
283
+ g_assert_not_reached();
284
+ }
285
+}
286
+
287
+static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr,
288
+ uint32_t cnr)
289
+{
290
+ return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1));
291
+}
292
+
293
+static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
294
+{
295
+ uint64_t duty;
296
+
297
+ if (cnr == 0) {
298
+ /* PWM is stopped. */
299
+ duty = 0;
300
+ } else if (cmr >= cnr) {
301
+ duty = MAX_DUTY;
302
+ } else {
303
+ duty = MAX_DUTY * (cmr + 1) / (cnr + 1);
304
+ }
305
+
306
+ if (inverted) {
307
+ duty = MAX_DUTY - duty;
308
+ }
309
+
310
+ return duty;
311
+}
312
+
313
+static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned offset)
314
+{
315
+ return qtest_readl(qts, td->module->base_addr + offset);
316
+}
317
+
318
+static void pwm_write(QTestState *qts, const TestData *td, unsigned offset,
319
+ uint32_t value)
320
+{
321
+ qtest_writel(qts, td->module->base_addr + offset, value);
322
+}
323
+
324
+static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td)
325
+{
326
+ return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8);
327
+}
328
+
329
+static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t value)
330
+{
331
+ pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]);
332
+}
333
+
334
+static uint32_t pwm_read_csr(QTestState *qts, const TestData *td)
335
+{
336
+ return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3);
337
+}
338
+
339
+static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t value)
340
+{
341
+ pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]);
342
+}
343
+
344
+static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td)
345
+{
346
+ return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)], 4);
347
+}
348
+
349
+static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t value)
350
+{
351
+ pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]);
352
+}
353
+
354
+static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td)
355
+{
356
+ return pwm_read(qts, td, td->pwm->cnr_offset);
357
+}
358
+
359
+static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t value)
360
+{
361
+ pwm_write(qts, td, td->pwm->cnr_offset, value);
362
+}
363
+
364
+static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td)
365
+{
366
+ return pwm_read(qts, td, td->pwm->cmr_offset);
367
+}
368
+
369
+static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value)
370
+{
371
+ pwm_write(qts, td, td->pwm->cmr_offset, value);
372
+}
373
+
374
+/* Check pwm registers can be reset to default value */
375
+static void test_init(gconstpointer test_data)
376
+{
377
+ const TestData *td = test_data;
378
+ QTestState *qts = qtest_init("-machine quanta-gsj");
379
+ int module = pwm_module_index(td->module);
380
+ int pwm = pwm_index(td->pwm);
381
+
382
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
383
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
384
+
385
+ qtest_quit(qts);
386
+}
387
+
388
+/* One-shot mode should not change frequency and duty cycle. */
389
+static void test_oneshot(gconstpointer test_data)
390
+{
391
+ const TestData *td = test_data;
392
+ QTestState *qts = qtest_init("-machine quanta-gsj");
393
+ int module = pwm_module_index(td->module);
394
+ int pwm = pwm_index(td->pwm);
395
+ uint32_t ppr, csr, pcr;
396
+ int i, j;
397
+
398
+ pcr = CH_EN;
399
+ for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
400
+ ppr = ppr_list[i];
401
+ pwm_write_ppr(qts, td, ppr);
402
+
403
+ for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
404
+ csr = csr_list[j];
405
+ pwm_write_csr(qts, td, csr);
406
+ pwm_write_pcr(qts, td, pcr);
407
+
408
+ g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
409
+ g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
410
+ g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
411
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
412
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
413
+ }
414
+ }
415
+
416
+ qtest_quit(qts);
417
+}
418
+
419
+/* In toggle mode, the PWM generates correct outputs. */
420
+static void test_toggle(gconstpointer test_data)
421
+{
422
+ const TestData *td = test_data;
423
+ QTestState *qts = qtest_init("-machine quanta-gsj");
424
+ int module = pwm_module_index(td->module);
425
+ int pwm = pwm_index(td->pwm);
426
+ uint32_t ppr, csr, pcr, cnr, cmr;
427
+ int i, j, k, l;
428
+ uint64_t expected_freq, expected_duty;
429
+
430
+ pcr = CH_EN | CH_MOD;
431
+ for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
432
+ ppr = ppr_list[i];
433
+ pwm_write_ppr(qts, td, ppr);
434
+
435
+ for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
436
+ csr = csr_list[j];
437
+ pwm_write_csr(qts, td, csr);
438
+
439
+ for (k = 0; k < ARRAY_SIZE(cnr_list); ++k) {
440
+ cnr = cnr_list[k];
441
+ pwm_write_cnr(qts, td, cnr);
442
+
443
+ for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) {
444
+ cmr = cmr_list[l];
445
+ pwm_write_cmr(qts, td, cmr);
446
+ expected_freq = pwm_compute_freq(qts, ppr, csr, cnr);
447
+ expected_duty = pwm_compute_duty(cnr, cmr, false);
448
+
449
+ pwm_write_pcr(qts, td, pcr);
450
+ g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
451
+ g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
452
+ g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
453
+ g_assert_cmpuint(pwm_read_cnr(qts, td), ==, cnr);
454
+ g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr);
455
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
456
+ ==, expected_duty);
457
+ if (expected_duty != 0 && expected_duty != 100) {
458
+ /* Duty cycle with 0 or 100 doesn't need frequency. */
459
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
460
+ ==, expected_freq);
461
+ }
462
+
463
+ /* Test inverted mode */
464
+ expected_duty = pwm_compute_duty(cnr, cmr, true);
465
+ pwm_write_pcr(qts, td, pcr | CH_INV);
466
+ g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr | CH_INV);
467
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
468
+ ==, expected_duty);
469
+ if (expected_duty != 0 && expected_duty != 100) {
470
+ /* Duty cycle with 0 or 100 doesn't need frequency. */
471
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
472
+ ==, expected_freq);
473
+ }
474
+
475
+ }
476
+ }
477
+ }
478
+ }
479
+
480
+ qtest_quit(qts);
481
+}
482
+
483
+static void pwm_add_test(const char *name, const TestData* td,
484
+ GTestDataFunc fn)
485
+{
486
+ g_autofree char *full_name = g_strdup_printf(
487
+ "npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->module),
488
+ pwm_index(td->pwm), name);
489
+ qtest_add_data_func(full_name, td, fn);
490
+}
491
+#define add_test(name, td) pwm_add_test(#name, td, test_##name)
492
+
493
+int main(int argc, char **argv)
494
+{
495
+ TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list)];
496
+
497
+ g_test_init(&argc, &argv, NULL);
498
+
499
+ for (int i = 0; i < ARRAY_SIZE(pwm_module_list); ++i) {
500
+ for (int j = 0; j < ARRAY_SIZE(pwm_list); ++j) {
501
+ TestData *td = &test_data_list[i * ARRAY_SIZE(pwm_list) + j];
502
+
503
+ td->module = &pwm_module_list[i];
504
+ td->pwm = &pwm_list[j];
505
+
506
+ add_test(init, td);
507
+ add_test(oneshot, td);
508
+ add_test(toggle, td);
509
+ }
510
+ }
511
+
512
+ return g_test_run();
513
+}
514
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
515
index XXXXXXX..XXXXXXX 100644
516
--- a/tests/qtest/meson.build
517
+++ b/tests/qtest/meson.build
518
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
519
qtests_npcm7xx = \
520
['npcm7xx_adc-test',
521
'npcm7xx_gpio-test',
522
+ 'npcm7xx_pwm-test',
523
'npcm7xx_rng-test',
524
'npcm7xx_timer-test',
525
'npcm7xx_watchdog_timer-test']
80
--
526
--
81
2.20.1
527
2.20.1
82
528
83
529
diff view generated by jsdifflib
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
With SmartFusion2 Ethernet MAC model in
3
A device shouldn't access its parent object which is QOM internal.
4
place this patch adds the same to SoC.
4
Instead it should use type cast for this purporse. This patch fixes this
5
issue for all NPCM7XX Devices.
5
6
6
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
7
Signed-off-by: Hao Wu <wuhaotsh@google.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20210108190945.949196-7-wuhaotsh@google.com
9
Message-id: 1587048891-30493-3-git-send-email-sundeep.lkml@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
include/hw/arm/msf2-soc.h | 2 ++
12
hw/arm/npcm7xx_boards.c | 2 +-
13
hw/arm/msf2-soc.c | 26 ++++++++++++++++++++++++--
13
hw/mem/npcm7xx_mc.c | 2 +-
14
2 files changed, 26 insertions(+), 2 deletions(-)
14
hw/misc/npcm7xx_clk.c | 2 +-
15
hw/misc/npcm7xx_gcr.c | 2 +-
16
hw/misc/npcm7xx_rng.c | 2 +-
17
hw/nvram/npcm7xx_otp.c | 2 +-
18
hw/ssi/npcm7xx_fiu.c | 2 +-
19
7 files changed, 7 insertions(+), 7 deletions(-)
15
20
16
diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
21
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
17
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/msf2-soc.h
23
--- a/hw/arm/npcm7xx_boards.c
19
+++ b/include/hw/arm/msf2-soc.h
24
+++ b/hw/arm/npcm7xx_boards.c
20
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
21
#include "hw/timer/mss-timer.h"
26
uint32_t hw_straps)
22
#include "hw/misc/msf2-sysreg.h"
27
{
23
#include "hw/ssi/mss-spi.h"
28
NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
24
+#include "hw/net/msf2-emac.h"
29
- MachineClass *mc = &nmc->parent;
25
30
+ MachineClass *mc = MACHINE_CLASS(nmc);
26
#define TYPE_MSF2_SOC "msf2-soc"
31
Object *obj;
27
#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
32
28
@@ -XXX,XX +XXX,XX @@ typedef struct MSF2State {
33
if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
29
MSF2SysregState sysreg;
34
diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c
30
MSSTimerState timer;
31
MSSSpiState spi[MSF2_NUM_SPIS];
32
+ MSF2EmacState emac;
33
} MSF2State;
34
35
#endif
36
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
37
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/arm/msf2-soc.c
36
--- a/hw/mem/npcm7xx_mc.c
39
+++ b/hw/arm/msf2-soc.c
37
+++ b/hw/mem/npcm7xx_mc.c
40
@@ -XXX,XX +XXX,XX @@
38
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_mc_realize(DeviceState *dev, Error **errp)
41
/*
39
42
* SmartFusion2 SoC emulation.
40
memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs",
43
*
41
NPCM7XX_MC_REGS_SIZE);
44
- * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
42
- sysbus_init_mmio(&s->parent, &s->mmio);
45
+ * Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>
43
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
46
*
47
* Permission is hereby granted, free of charge, to any person obtaining a copy
48
* of this software and associated documentation files (the "Software"), to deal
49
@@ -XXX,XX +XXX,XX @@
50
51
#define MSF2_TIMER_BASE 0x40004000
52
#define MSF2_SYSREG_BASE 0x40038000
53
+#define MSF2_EMAC_BASE 0x40041000
54
55
#define ENVM_BASE_ADDRESS 0x60000000
56
57
#define SRAM_BASE_ADDRESS 0x20000000
58
59
+#define MSF2_EMAC_IRQ 12
60
+
61
#define MSF2_ENVM_MAX_SIZE (512 * KiB)
62
63
/*
64
@@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_initfn(Object *obj)
65
sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
66
TYPE_MSS_SPI);
67
}
68
+
69
+ sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
70
+ TYPE_MSS_EMAC);
71
+ if (nd_table[0].used) {
72
+ qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC);
73
+ qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
74
+ }
75
}
44
}
76
45
77
static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
46
static void npcm7xx_mc_class_init(ObjectClass *klass, void *data)
78
@@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
47
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
79
g_free(bus_name);
48
index XXXXXXX..XXXXXXX 100644
80
}
49
--- a/hw/misc/npcm7xx_clk.c
81
50
+++ b/hw/misc/npcm7xx_clk.c
82
+ dev = DEVICE(&s->emac);
51
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
83
+ object_property_set_link(OBJECT(&s->emac), OBJECT(get_system_memory()),
52
84
+ "ahb-bus", &error_abort);
53
memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
85
+ object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
54
TYPE_NPCM7XX_CLK, 4 * KiB);
86
+ if (err != NULL) {
55
- sysbus_init_mmio(&s->parent, &s->iomem);
87
+ error_propagate(errp, err);
56
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
88
+ return;
89
+ }
90
+ busdev = SYS_BUS_DEVICE(dev);
91
+ sysbus_mmio_map(busdev, 0, MSF2_EMAC_BASE);
92
+ sysbus_connect_irq(busdev, 0,
93
+ qdev_get_gpio_in(armv7m, MSF2_EMAC_IRQ));
94
+
95
/* Below devices are not modelled yet. */
96
create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
97
create_unimplemented_device("dma", 0x40003000, 0x1000);
98
@@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
99
create_unimplemented_device("can", 0x40015000, 0x1000);
100
create_unimplemented_device("rtc", 0x40017000, 0x1000);
101
create_unimplemented_device("apb_config", 0x40020000, 0x10000);
102
- create_unimplemented_device("emac", 0x40041000, 0x1000);
103
create_unimplemented_device("usb", 0x40043000, 0x1000);
104
}
57
}
105
58
59
static int npcm7xx_clk_post_load(void *opaque, int version_id)
60
diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/hw/misc/npcm7xx_gcr.c
63
+++ b/hw/misc/npcm7xx_gcr.c
64
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gcr_init(Object *obj)
65
66
memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s,
67
TYPE_NPCM7XX_GCR, 4 * KiB);
68
- sysbus_init_mmio(&s->parent, &s->iomem);
69
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
70
}
71
72
static const VMStateDescription vmstate_npcm7xx_gcr = {
73
diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/hw/misc/npcm7xx_rng.c
76
+++ b/hw/misc/npcm7xx_rng.c
77
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_rng_init(Object *obj)
78
79
memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs",
80
NPCM7XX_RNG_REGS_SIZE);
81
- sysbus_init_mmio(&s->parent, &s->iomem);
82
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
83
}
84
85
static const VMStateDescription vmstate_npcm7xx_rng = {
86
diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/hw/nvram/npcm7xx_otp.c
89
+++ b/hw/nvram/npcm7xx_otp.c
90
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
91
{
92
NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
93
NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
94
- SysBusDevice *sbd = &s->parent;
95
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
96
97
memset(s->array, 0, sizeof(s->array));
98
99
diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/hw/ssi/npcm7xx_fiu.c
102
+++ b/hw/ssi/npcm7xx_fiu.c
103
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_hold_reset(Object *obj)
104
static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
105
{
106
NPCM7xxFIUState *s = NPCM7XX_FIU(dev);
107
- SysBusDevice *sbd = &s->parent;
108
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
109
int i;
110
111
if (s->cs_count <= 0) {
106
--
112
--
107
2.20.1
113
2.20.1
108
114
109
115
diff view generated by jsdifflib
Deleted patch
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
2
1
3
In addition to simple serial test this patch uses ping
4
to test the ethernet block modelled in SmartFusion2 SoC.
5
6
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 1587048891-30493-4-git-send-email-sundeep.lkml@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
tests/acceptance/boot_linux_console.py | 15 ++++++++++-----
13
1 file changed, 10 insertions(+), 5 deletions(-)
14
15
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
16
index XXXXXXX..XXXXXXX 100644
17
--- a/tests/acceptance/boot_linux_console.py
18
+++ b/tests/acceptance/boot_linux_console.py
19
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
20
"""
21
uboot_url = ('https://raw.githubusercontent.com/'
22
'Subbaraya-Sundeep/qemu-test-binaries/'
23
- 'fa030bd77a014a0b8e360d3b7011df89283a2f0b/u-boot')
24
- uboot_hash = 'abba5d9c24cdd2d49cdc2a8aa92976cf20737eff'
25
+ 'fe371d32e50ca682391e1e70ab98c2942aeffb01/u-boot')
26
+ uboot_hash = 'cbb8cbab970f594bf6523b9855be209c08374ae2'
27
uboot_path = self.fetch_asset(uboot_url, asset_hash=uboot_hash)
28
spi_url = ('https://raw.githubusercontent.com/'
29
'Subbaraya-Sundeep/qemu-test-binaries/'
30
- 'fa030bd77a014a0b8e360d3b7011df89283a2f0b/spi.bin')
31
- spi_hash = '85f698329d38de63aea6e884a86fbde70890a78a'
32
+ 'fe371d32e50ca682391e1e70ab98c2942aeffb01/spi.bin')
33
+ spi_hash = '65523a1835949b6f4553be96dec1b6a38fb05501'
34
spi_path = self.fetch_asset(spi_url, asset_hash=spi_hash)
35
36
self.vm.set_console()
37
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
38
'-drive', 'file=' + spi_path + ',if=mtd,format=raw',
39
'-no-reboot')
40
self.vm.launch()
41
- self.wait_for_console_pattern('init started: BusyBox')
42
+ self.wait_for_console_pattern('Enter \'help\' for a list')
43
+
44
+ exec_command_and_wait_for_pattern(self, 'ifconfig eth0 10.0.2.15',
45
+ 'eth0: link becomes ready')
46
+ exec_command_and_wait_for_pattern(self, 'ping -c 3 10.0.2.2',
47
+ '3 packets transmitted, 3 packets received, 0% packet loss')
48
49
def do_test_arm_raspi2(self, uart_id):
50
"""
51
--
52
2.20.1
53
54
diff view generated by jsdifflib
Deleted patch
1
From: Damien Hedde <damien.hedde@greensocs.com>
2
1
3
Introduce a function and macro helpers to setup several clocks
4
in a device from a static array description.
5
6
An element of the array describes the clock (name and direction) as
7
well as the related callback and an optional offset to store the
8
created object pointer in the device state structure.
9
10
The array must be terminated by a special element QDEV_CLOCK_END.
11
12
This is based on the original work of Frederic Konrad.
13
14
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
16
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
18
Message-id: 20200406135251.157596-5-damien.hedde@greensocs.com
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
include/hw/qdev-clock.h | 55 +++++++++++++++++++++++++++++++++++++++++
22
hw/core/qdev-clock.c | 17 +++++++++++++
23
2 files changed, 72 insertions(+)
24
25
diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h
26
index XXXXXXX..XXXXXXX 100644
27
--- a/include/hw/qdev-clock.h
28
+++ b/include/hw/qdev-clock.h
29
@@ -XXX,XX +XXX,XX @@ Clock *qdev_alias_clock(DeviceState *dev, const char *name,
30
*/
31
void qdev_finalize_clocklist(DeviceState *dev);
32
33
+/**
34
+ * ClockPortInitElem:
35
+ * @name: name of the clock (can't be NULL)
36
+ * @output: indicates whether the clock is input or output
37
+ * @callback: for inputs, optional callback to be called on clock's update
38
+ * with device as opaque
39
+ * @offset: optional offset to store the ClockIn or ClockOut pointer in device
40
+ * state structure (0 means unused)
41
+ */
42
+struct ClockPortInitElem {
43
+ const char *name;
44
+ bool is_output;
45
+ ClockCallback *callback;
46
+ size_t offset;
47
+};
48
+
49
+#define clock_offset_value(devstate, field) \
50
+ (offsetof(devstate, field) + \
51
+ type_check(Clock *, typeof_field(devstate, field)))
52
+
53
+#define QDEV_CLOCK(out_not_in, devstate, field, cb) { \
54
+ .name = (stringify(field)), \
55
+ .is_output = out_not_in, \
56
+ .callback = cb, \
57
+ .offset = clock_offset_value(devstate, field), \
58
+}
59
+
60
+/**
61
+ * QDEV_CLOCK_(IN|OUT):
62
+ * @devstate: structure type. @dev argument of qdev_init_clocks below must be
63
+ * a pointer to that same type.
64
+ * @field: a field in @_devstate (must be Clock*)
65
+ * @callback: (for input only) callback (or NULL) to be called with the device
66
+ * state as argument
67
+ *
68
+ * The name of the clock will be derived from @field
69
+ */
70
+#define QDEV_CLOCK_IN(devstate, field, callback) \
71
+ QDEV_CLOCK(false, devstate, field, callback)
72
+
73
+#define QDEV_CLOCK_OUT(devstate, field) \
74
+ QDEV_CLOCK(true, devstate, field, NULL)
75
+
76
+#define QDEV_CLOCK_END { .name = NULL }
77
+
78
+typedef struct ClockPortInitElem ClockPortInitArray[];
79
+
80
+/**
81
+ * qdev_init_clocks:
82
+ * @dev: the device to add clocks to
83
+ * @clocks: a QDEV_CLOCK_END-terminated array which contains the
84
+ * clocks information.
85
+ */
86
+void qdev_init_clocks(DeviceState *dev, const ClockPortInitArray clocks);
87
+
88
#endif /* QDEV_CLOCK_H */
89
diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/hw/core/qdev-clock.c
92
+++ b/hw/core/qdev-clock.c
93
@@ -XXX,XX +XXX,XX @@ Clock *qdev_init_clock_in(DeviceState *dev, const char *name,
94
return ncl->clock;
95
}
96
97
+void qdev_init_clocks(DeviceState *dev, const ClockPortInitArray clocks)
98
+{
99
+ const struct ClockPortInitElem *elem;
100
+
101
+ for (elem = &clocks[0]; elem->name != NULL; elem++) {
102
+ Clock **clkp;
103
+ /* offset cannot be inside the DeviceState part */
104
+ assert(elem->offset > sizeof(DeviceState));
105
+ clkp = (Clock **)(((void *) dev) + elem->offset);
106
+ if (elem->is_output) {
107
+ *clkp = qdev_init_clock_out(dev, elem->name);
108
+ } else {
109
+ *clkp = qdev_init_clock_in(dev, elem->name, elem->callback, dev);
110
+ }
111
+ }
112
+}
113
+
114
static NamedClockList *qdev_get_clocklist(DeviceState *dev, const char *name)
115
{
116
NamedClockList *ncl;
117
--
118
2.20.1
119
120
diff view generated by jsdifflib
Deleted patch
1
Add the documentation about the clock inputs and outputs in devices.
2
1
3
This is based on the original work of Frederic Konrad.
4
5
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Message-id: 20200406135251.157596-6-damien.hedde@greensocs.com
9
[PMM: Editing pass for minor grammar, style and Sphinx
10
formatting fixes]
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
docs/devel/clocks.rst | 391 ++++++++++++++++++++++++++++++++++++++++++
15
docs/devel/index.rst | 1 +
16
2 files changed, 392 insertions(+)
17
create mode 100644 docs/devel/clocks.rst
18
19
diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst
20
new file mode 100644
21
index XXXXXXX..XXXXXXX
22
--- /dev/null
23
+++ b/docs/devel/clocks.rst
24
@@ -XXX,XX +XXX,XX @@
25
+Modelling a clock tree in QEMU
26
+==============================
27
+
28
+What are clocks?
29
+----------------
30
+
31
+Clocks are QOM objects developed for the purpose of modelling the
32
+distribution of clocks in QEMU.
33
+
34
+They allow us to model the clock distribution of a platform and detect
35
+configuration errors in the clock tree such as badly configured PLL, clock
36
+source selection or disabled clock.
37
+
38
+The object is *Clock* and its QOM name is ``clock`` (in C code, the macro
39
+``TYPE_CLOCK``).
40
+
41
+Clocks are typically used with devices where they are used to model inputs
42
+and outputs. They are created in a similar way to GPIOs. Inputs and outputs
43
+of different devices can be connected together.
44
+
45
+In these cases a Clock object is a child of a Device object, but this
46
+is not a requirement. Clocks can be independent of devices. For
47
+example it is possible to create a clock outside of any device to
48
+model the main clock source of a machine.
49
+
50
+Here is an example of clocks::
51
+
52
+ +---------+ +----------------------+ +--------------+
53
+ | Clock 1 | | Device B | | Device C |
54
+ | | | +-------+ +-------+ | | +-------+ |
55
+ | |>>-+-->>|Clock 2| |Clock 3|>>--->>|Clock 6| |
56
+ +---------+ | | | (in) | | (out) | | | | (in) | |
57
+ | | +-------+ +-------+ | | +-------+ |
58
+ | | +-------+ | +--------------+
59
+ | | |Clock 4|>>
60
+ | | | (out) | | +--------------+
61
+ | | +-------+ | | Device D |
62
+ | | +-------+ | | +-------+ |
63
+ | | |Clock 5|>>--->>|Clock 7| |
64
+ | | | (out) | | | | (in) | |
65
+ | | +-------+ | | +-------+ |
66
+ | +----------------------+ | |
67
+ | | +-------+ |
68
+ +----------------------------->>|Clock 8| |
69
+ | | (in) | |
70
+ | +-------+ |
71
+ +--------------+
72
+
73
+Clocks are defined in the ``include/hw/clock.h`` header and device
74
+related functions are defined in the ``include/hw/qdev-clock.h``
75
+header.
76
+
77
+The clock state
78
+---------------
79
+
80
+The state of a clock is its period; it is stored as an integer
81
+representing it in units of 2 :sup:`-32` ns. The special value of 0 is used to
82
+represent the clock being inactive or gated. The clocks do not model
83
+the signal itself (pin toggling) or other properties such as the duty
84
+cycle.
85
+
86
+All clocks contain this state: outputs as well as inputs. This allows
87
+the current period of a clock to be fetched at any time. When a clock
88
+is updated, the value is immediately propagated to all connected
89
+clocks in the tree.
90
+
91
+To ease interaction with clocks, helpers with a unit suffix are defined for
92
+every clock state setter or getter. The suffixes are:
93
+
94
+- ``_ns`` for handling periods in nanoseconds
95
+- ``_hz`` for handling frequencies in hertz
96
+
97
+The 0 period value is converted to 0 in hertz and vice versa. 0 always means
98
+that the clock is disabled.
99
+
100
+Adding a new clock
101
+------------------
102
+
103
+Adding clocks to a device must be done during the init method of the Device
104
+instance.
105
+
106
+To add an input clock to a device, the function ``qdev_init_clock_in()``
107
+must be used. It takes the name, a callback and an opaque parameter
108
+for the callback (this will be explained in a following section).
109
+Output is simpler; only the name is required. Typically::
110
+
111
+ qdev_init_clock_in(DEVICE(dev), "clk_in", clk_in_callback, dev);
112
+ qdev_init_clock_out(DEVICE(dev), "clk_out");
113
+
114
+Both functions return the created Clock pointer, which should be saved in the
115
+device's state structure for further use.
116
+
117
+These objects will be automatically deleted by the QOM reference mechanism.
118
+
119
+Note that it is possible to create a static array describing clock inputs and
120
+outputs. The function ``qdev_init_clocks()`` must be called with the array as
121
+parameter to initialize the clocks: it has the same behaviour as calling the
122
+``qdev_init_clock_in/out()`` for each clock in the array. To ease the array
123
+construction, some macros are defined in ``include/hw/qdev-clock.h``.
124
+As an example, the following creates 2 clocks to a device: one input and one
125
+output.
126
+
127
+.. code-block:: c
128
+
129
+ /* device structure containing pointers to the clock objects */
130
+ typedef struct MyDeviceState {
131
+ DeviceState parent_obj;
132
+ Clock *clk_in;
133
+ Clock *clk_out;
134
+ } MyDeviceState;
135
+
136
+ /*
137
+ * callback for the input clock (see "Callback on input clock
138
+ * change" section below for more information).
139
+ */
140
+ static void clk_in_callback(void *opaque);
141
+
142
+ /*
143
+ * static array describing clocks:
144
+ * + a clock input named "clk_in", whose pointer is stored in
145
+ * the clk_in field of a MyDeviceState structure with callback
146
+ * clk_in_callback.
147
+ * + a clock output named "clk_out" whose pointer is stored in
148
+ * the clk_out field of a MyDeviceState structure.
149
+ */
150
+ static const ClockPortInitArray mydev_clocks = {
151
+ QDEV_CLOCK_IN(MyDeviceState, clk_in, clk_in_callback),
152
+ QDEV_CLOCK_OUT(MyDeviceState, clk_out),
153
+ QDEV_CLOCK_END
154
+ };
155
+
156
+ /* device initialization function */
157
+ static void mydev_init(Object *obj)
158
+ {
159
+ /* cast to MyDeviceState */
160
+ MyDeviceState *mydev = MYDEVICE(obj);
161
+ /* create and fill the pointer fields in the MyDeviceState */
162
+ qdev_init_clocks(mydev, mydev_clocks);
163
+ [...]
164
+ }
165
+
166
+An alternative way to create a clock is to simply call
167
+``object_new(TYPE_CLOCK)``. In that case the clock will neither be an
168
+input nor an output of a device. After the whole QOM hierarchy of the
169
+clock has been set ``clock_setup_canonical_path()`` should be called.
170
+
171
+At creation, the period of the clock is 0: the clock is disabled. You can
172
+change it using ``clock_set_ns()`` or ``clock_set_hz()``.
173
+
174
+Note that if you are creating a clock with a fixed period which will never
175
+change (for example the main clock source of a board), then you'll have
176
+nothing else to do. This value will be propagated to other clocks when
177
+connecting the clocks together and devices will fetch the right value during
178
+the first reset.
179
+
180
+Retrieving clocks from a device
181
+-------------------------------
182
+
183
+``qdev_get_clock_in()`` and ``dev_get_clock_out()`` are available to
184
+get the clock inputs or outputs of a device. For example:
185
+
186
+.. code-block:: c
187
+
188
+ Clock *clk = qdev_get_clock_in(DEVICE(mydev), "clk_in");
189
+
190
+or:
191
+
192
+.. code-block:: c
193
+
194
+ Clock *clk = qdev_get_clock_out(DEVICE(mydev), "clk_out");
195
+
196
+Connecting two clocks together
197
+------------------------------
198
+
199
+To connect two clocks together, use the ``clock_set_source()`` function.
200
+Given two clocks ``clk1``, and ``clk2``, ``clock_set_source(clk2, clk1);``
201
+configures ``clk2`` to follow the ``clk1`` period changes. Every time ``clk1``
202
+is updated, ``clk2`` will be updated too.
203
+
204
+When connecting clock between devices, prefer using the
205
+``qdev_connect_clock_in()`` function to set the source of an input
206
+device clock. For example, to connect the input clock ``clk2`` of
207
+``devB`` to the output clock ``clk1`` of ``devA``, do:
208
+
209
+.. code-block:: c
210
+
211
+ qdev_connect_clock_in(devB, "clk2", qdev_get_clock_out(devA, "clk1"))
212
+
213
+We used ``qdev_get_clock_out()`` above, but any clock can drive an
214
+input clock, even another input clock. The following diagram shows
215
+some examples of connections. Note also that a clock can drive several
216
+other clocks.
217
+
218
+::
219
+
220
+ +------------+ +--------------------------------------------------+
221
+ | Device A | | Device B |
222
+ | | | +---------------------+ |
223
+ | | | | Device C | |
224
+ | +-------+ | | +-------+ | +-------+ +-------+ | +-------+ |
225
+ | |Clock 1|>>-->>|Clock 2|>>+-->>|Clock 3| |Clock 5|>>>>|Clock 6|>>
226
+ | | (out) | | | | (in) | | | | (in) | | (out) | | | (out) | |
227
+ | +-------+ | | +-------+ | | +-------+ +-------+ | +-------+ |
228
+ +------------+ | | +---------------------+ |
229
+ | | |
230
+ | | +--------------+ |
231
+ | | | Device D | |
232
+ | | | +-------+ | |
233
+ | +-->>|Clock 4| | |
234
+ | | | (in) | | |
235
+ | | +-------+ | |
236
+ | +--------------+ |
237
+ +--------------------------------------------------+
238
+
239
+In the above example, when *Clock 1* is updated by *Device A*, three
240
+clocks get the new clock period value: *Clock 2*, *Clock 3* and *Clock 4*.
241
+
242
+It is not possible to disconnect a clock or to change the clock connection
243
+after it is connected.
244
+
245
+Unconnected input clocks
246
+------------------------
247
+
248
+A newly created input clock is disabled (period of 0). This means the
249
+clock will be considered as disabled until the period is updated. If
250
+the clock remains unconnected it will always keep its initial value
251
+of 0. If this is not the desired behaviour, ``clock_set()``,
252
+``clock_set_ns()`` or ``clock_set_hz()`` should be called on the Clock
253
+object during device instance init. For example:
254
+
255
+.. code-block:: c
256
+
257
+ clk = qdev_init_clock_in(DEVICE(dev), "clk-in", clk_in_callback,
258
+ dev);
259
+ /* set initial value to 10ns / 100MHz */
260
+ clock_set_ns(clk, 10);
261
+
262
+Fetching clock frequency/period
263
+-------------------------------
264
+
265
+To get the current state of a clock, use the functions ``clock_get()``,
266
+``clock_get_ns()`` or ``clock_get_hz()``.
267
+
268
+It is also possible to register a callback on clock frequency changes.
269
+Here is an example:
270
+
271
+.. code-block:: c
272
+
273
+ void clock_callback(void *opaque) {
274
+ MyDeviceState *s = (MyDeviceState *) opaque;
275
+ /*
276
+ * 'opaque' is the argument passed to qdev_init_clock_in();
277
+ * usually this will be the device state pointer.
278
+ */
279
+
280
+ /* do something with the new period */
281
+ fprintf(stdout, "device new period is %" PRIu64 "ns\n",
282
+ clock_get_ns(dev->my_clk_input));
283
+ }
284
+
285
+Changing a clock period
286
+-----------------------
287
+
288
+A device can change its outputs using the ``clock_update()``,
289
+``clock_update_ns()`` or ``clock_update_hz()`` function. It will trigger
290
+updates on every connected input.
291
+
292
+For example, let's say that we have an output clock *clkout* and we
293
+have a pointer to it in the device state because we did the following
294
+in init phase:
295
+
296
+.. code-block:: c
297
+
298
+ dev->clkout = qdev_init_clock_out(DEVICE(dev), "clkout");
299
+
300
+Then at any time (apart from the cases listed below), it is possible to
301
+change the clock value by doing:
302
+
303
+.. code-block:: c
304
+
305
+ clock_update_hz(dev->clkout, 1000 * 1000 * 1000); /* 1GHz */
306
+
307
+Because updating a clock may trigger any side effects through
308
+connected clocks and their callbacks, this operation must be done
309
+while holding the qemu io lock.
310
+
311
+For the same reason, one can update clocks only when it is allowed to have
312
+side effects on other objects. In consequence, it is forbidden:
313
+
314
+* during migration,
315
+* and in the enter phase of reset.
316
+
317
+Note that calling ``clock_update[_ns|_hz]()`` is equivalent to calling
318
+``clock_set[_ns|_hz]()`` (with the same arguments) then
319
+``clock_propagate()`` on the clock. Thus, setting the clock value can
320
+be separated from triggering the side-effects. This is often required
321
+to factorize code to handle reset and migration in devices.
322
+
323
+Aliasing clocks
324
+---------------
325
+
326
+Sometimes, one needs to forward, or inherit, a clock from another
327
+device. Typically, when doing device composition, a device might
328
+expose a sub-device's clock without interfering with it. The function
329
+``qdev_alias_clock()`` can be used to achieve this behaviour. Note
330
+that it is possible to expose the clock under a different name.
331
+``qdev_alias_clock()`` works for both input and output clocks.
332
+
333
+For example, if device B is a child of device A,
334
+``device_a_instance_init()`` may do something like this:
335
+
336
+.. code-block:: c
337
+
338
+ void device_a_instance_init(Object *obj)
339
+ {
340
+ AState *A = DEVICE_A(obj);
341
+ BState *B;
342
+ /* create object B as child of A */
343
+ [...]
344
+ qdev_alias_clock(B, "clk", A, "b_clk");
345
+ /*
346
+ * Now A has a clock "b_clk" which is an alias to
347
+ * the clock "clk" of its child B.
348
+ */
349
+ }
350
+
351
+This function does not return any clock object. The new clock has the
352
+same direction (input or output) as the original one. This function
353
+only adds a link to the existing clock. In the above example, object B
354
+remains the only object allowed to use the clock and device A must not
355
+try to change the clock period or set a callback to the clock. This
356
+diagram describes the example with an input clock::
357
+
358
+ +--------------------------+
359
+ | Device A |
360
+ | +--------------+ |
361
+ | | Device B | |
362
+ | | +-------+ | |
363
+ >>"b_clk">>>| "clk" | | |
364
+ | (in) | | (in) | | |
365
+ | | +-------+ | |
366
+ | +--------------+ |
367
+ +--------------------------+
368
+
369
+Migration
370
+---------
371
+
372
+Clock state is not migrated automatically. Every device must handle its
373
+clock migration. Alias clocks must not be migrated.
374
+
375
+To ensure clock states are restored correctly during migration, there
376
+are two solutions.
377
+
378
+Clock states can be migrated by adding an entry into the device
379
+vmstate description. You should use the ``VMSTATE_CLOCK`` macro for this.
380
+This is typically used to migrate an input clock state. For example:
381
+
382
+.. code-block:: c
383
+
384
+ MyDeviceState {
385
+ DeviceState parent_obj;
386
+ [...] /* some fields */
387
+ Clock *clk;
388
+ };
389
+
390
+ VMStateDescription my_device_vmstate = {
391
+ .name = "my_device",
392
+ .fields = (VMStateField[]) {
393
+ [...], /* other migrated fields */
394
+ VMSTATE_CLOCK(clk, MyDeviceState),
395
+ VMSTATE_END_OF_LIST()
396
+ }
397
+ };
398
+
399
+The second solution is to restore the clock state using information already
400
+at our disposal. This can be used to restore output clock states using the
401
+device state. The functions ``clock_set[_ns|_hz]()`` can be used during the
402
+``post_load()`` migration callback.
403
+
404
+When adding clock support to an existing device, if you care about
405
+migration compatibility you will need to be careful, as simply adding
406
+a ``VMSTATE_CLOCK()`` line will break compatibility. Instead, you can
407
+put the ``VMSTATE_CLOCK()`` line into a vmstate subsection with a
408
+suitable ``needed`` function, and use ``clock_set()`` in a
409
+``pre_load()`` function to set the default value that will be used if
410
+the source virtual machine in the migration does not send the clock
411
+state.
412
+
413
+Care should be taken not to use ``clock_update[_ns|_hz]()`` or
414
+``clock_propagate()`` during the whole migration procedure because it
415
+will trigger side effects to other devices in an unknown state.
416
diff --git a/docs/devel/index.rst b/docs/devel/index.rst
417
index XXXXXXX..XXXXXXX 100644
418
--- a/docs/devel/index.rst
419
+++ b/docs/devel/index.rst
420
@@ -XXX,XX +XXX,XX @@ Contents:
421
bitops
422
reset
423
s390-dasd-ipl
424
+ clocks
425
--
426
2.20.1
427
428
diff view generated by jsdifflib
Deleted patch
1
From: Damien Hedde <damien.hedde@greensocs.com>
2
1
3
Add some clocks to zynq_slcr
4
+ the main input clock (ps_clk)
5
+ the reference clock outputs for each uart (uart0 & 1)
6
7
This commit also transitional the slcr to multi-phase reset as it is
8
required to initialize the clocks correctly.
9
10
The clock frequencies are computed using the internal pll & uart configuration
11
registers and the input ps_clk frequency.
12
13
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
14
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
15
Acked-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 20200406135251.157596-7-damien.hedde@greensocs.com
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
hw/misc/zynq_slcr.c | 172 ++++++++++++++++++++++++++++++++++++++++++--
20
1 file changed, 168 insertions(+), 4 deletions(-)
21
22
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/misc/zynq_slcr.c
25
+++ b/hw/misc/zynq_slcr.c
26
@@ -XXX,XX +XXX,XX @@
27
#include "qemu/log.h"
28
#include "qemu/module.h"
29
#include "hw/registerfields.h"
30
+#include "hw/qdev-clock.h"
31
32
#ifndef ZYNQ_SLCR_ERR_DEBUG
33
#define ZYNQ_SLCR_ERR_DEBUG 0
34
@@ -XXX,XX +XXX,XX @@ REG32(LOCKSTA, 0x00c)
35
REG32(ARM_PLL_CTRL, 0x100)
36
REG32(DDR_PLL_CTRL, 0x104)
37
REG32(IO_PLL_CTRL, 0x108)
38
+/* fields for [ARM|DDR|IO]_PLL_CTRL registers */
39
+ FIELD(xxx_PLL_CTRL, PLL_RESET, 0, 1)
40
+ FIELD(xxx_PLL_CTRL, PLL_PWRDWN, 1, 1)
41
+ FIELD(xxx_PLL_CTRL, PLL_BYPASS_QUAL, 3, 1)
42
+ FIELD(xxx_PLL_CTRL, PLL_BYPASS_FORCE, 4, 1)
43
+ FIELD(xxx_PLL_CTRL, PLL_FPDIV, 12, 7)
44
REG32(PLL_STATUS, 0x10c)
45
REG32(ARM_PLL_CFG, 0x110)
46
REG32(DDR_PLL_CFG, 0x114)
47
@@ -XXX,XX +XXX,XX @@ REG32(SMC_CLK_CTRL, 0x148)
48
REG32(LQSPI_CLK_CTRL, 0x14c)
49
REG32(SDIO_CLK_CTRL, 0x150)
50
REG32(UART_CLK_CTRL, 0x154)
51
+ FIELD(UART_CLK_CTRL, CLKACT0, 0, 1)
52
+ FIELD(UART_CLK_CTRL, CLKACT1, 1, 1)
53
+ FIELD(UART_CLK_CTRL, SRCSEL, 4, 2)
54
+ FIELD(UART_CLK_CTRL, DIVISOR, 8, 6)
55
REG32(SPI_CLK_CTRL, 0x158)
56
REG32(CAN_CLK_CTRL, 0x15c)
57
REG32(CAN_MIOCLK_CTRL, 0x160)
58
@@ -XXX,XX +XXX,XX @@ typedef struct ZynqSLCRState {
59
MemoryRegion iomem;
60
61
uint32_t regs[ZYNQ_SLCR_NUM_REGS];
62
+
63
+ Clock *ps_clk;
64
+ Clock *uart0_ref_clk;
65
+ Clock *uart1_ref_clk;
66
} ZynqSLCRState;
67
68
-static void zynq_slcr_reset(DeviceState *d)
69
+/*
70
+ * return the output frequency of ARM/DDR/IO pll
71
+ * using input frequency and PLL_CTRL register
72
+ */
73
+static uint64_t zynq_slcr_compute_pll(uint64_t input, uint32_t ctrl_reg)
74
{
75
- ZynqSLCRState *s = ZYNQ_SLCR(d);
76
+ uint32_t mult = ((ctrl_reg & R_xxx_PLL_CTRL_PLL_FPDIV_MASK) >>
77
+ R_xxx_PLL_CTRL_PLL_FPDIV_SHIFT);
78
+
79
+ /* first, check if pll is bypassed */
80
+ if (ctrl_reg & R_xxx_PLL_CTRL_PLL_BYPASS_FORCE_MASK) {
81
+ return input;
82
+ }
83
+
84
+ /* is pll disabled ? */
85
+ if (ctrl_reg & (R_xxx_PLL_CTRL_PLL_RESET_MASK |
86
+ R_xxx_PLL_CTRL_PLL_PWRDWN_MASK)) {
87
+ return 0;
88
+ }
89
+
90
+ /* frequency multiplier -> period division */
91
+ return input / mult;
92
+}
93
+
94
+/*
95
+ * return the output period of a clock given:
96
+ * + the periods in an array corresponding to input mux selector
97
+ * + the register xxx_CLK_CTRL value
98
+ * + enable bit index in ctrl register
99
+ *
100
+ * This function makes the assumption that the ctrl_reg value is organized as
101
+ * follows:
102
+ * + bits[13:8] clock frequency divisor
103
+ * + bits[5:4] clock mux selector (index in array)
104
+ * + bits[index] clock enable
105
+ */
106
+static uint64_t zynq_slcr_compute_clock(const uint64_t periods[],
107
+ uint32_t ctrl_reg,
108
+ unsigned index)
109
+{
110
+ uint32_t srcsel = extract32(ctrl_reg, 4, 2); /* bits [5:4] */
111
+ uint32_t divisor = extract32(ctrl_reg, 8, 6); /* bits [13:8] */
112
+
113
+ /* first, check if clock is disabled */
114
+ if (((ctrl_reg >> index) & 1u) == 0) {
115
+ return 0;
116
+ }
117
+
118
+ /*
119
+ * according to the Zynq technical ref. manual UG585 v1.12.2 in
120
+ * Clocks chapter, section 25.10.1 page 705:
121
+ * "The 6-bit divider provides a divide range of 1 to 63"
122
+ * We follow here what is implemented in linux kernel and consider
123
+ * the 0 value as a bypass (no division).
124
+ */
125
+ /* frequency divisor -> period multiplication */
126
+ return periods[srcsel] * (divisor ? divisor : 1u);
127
+}
128
+
129
+/*
130
+ * macro helper around zynq_slcr_compute_clock to avoid repeating
131
+ * the register name.
132
+ */
133
+#define ZYNQ_COMPUTE_CLK(state, plls, reg, enable_field) \
134
+ zynq_slcr_compute_clock((plls), (state)->regs[reg], \
135
+ reg ## _ ## enable_field ## _SHIFT)
136
+
137
+/**
138
+ * Compute and set the ouputs clocks periods.
139
+ * But do not propagate them further. Connected clocks
140
+ * will not receive any updates (See zynq_slcr_compute_clocks())
141
+ */
142
+static void zynq_slcr_compute_clocks(ZynqSLCRState *s)
143
+{
144
+ uint64_t ps_clk = clock_get(s->ps_clk);
145
+
146
+ /* consider outputs clocks are disabled while in reset */
147
+ if (device_is_in_reset(DEVICE(s))) {
148
+ ps_clk = 0;
149
+ }
150
+
151
+ uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]);
152
+ uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]);
153
+ uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]);
154
+
155
+ uint64_t uart_mux[4] = {io_pll, io_pll, arm_pll, ddr_pll};
156
+
157
+ /* compute uartX reference clocks */
158
+ clock_set(s->uart0_ref_clk,
159
+ ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0));
160
+ clock_set(s->uart1_ref_clk,
161
+ ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1));
162
+}
163
+
164
+/**
165
+ * Propagate the outputs clocks.
166
+ * zynq_slcr_compute_clocks() should have been called before
167
+ * to configure them.
168
+ */
169
+static void zynq_slcr_propagate_clocks(ZynqSLCRState *s)
170
+{
171
+ clock_propagate(s->uart0_ref_clk);
172
+ clock_propagate(s->uart1_ref_clk);
173
+}
174
+
175
+static void zynq_slcr_ps_clk_callback(void *opaque)
176
+{
177
+ ZynqSLCRState *s = (ZynqSLCRState *) opaque;
178
+ zynq_slcr_compute_clocks(s);
179
+ zynq_slcr_propagate_clocks(s);
180
+}
181
+
182
+static void zynq_slcr_reset_init(Object *obj, ResetType type)
183
+{
184
+ ZynqSLCRState *s = ZYNQ_SLCR(obj);
185
int i;
186
187
DB_PRINT("RESET\n");
188
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_reset(DeviceState *d)
189
s->regs[R_DDRIOB + 12] = 0x00000021;
190
}
191
192
+static void zynq_slcr_reset_hold(Object *obj)
193
+{
194
+ ZynqSLCRState *s = ZYNQ_SLCR(obj);
195
+
196
+ /* will disable all output clocks */
197
+ zynq_slcr_compute_clocks(s);
198
+ zynq_slcr_propagate_clocks(s);
199
+}
200
+
201
+static void zynq_slcr_reset_exit(Object *obj)
202
+{
203
+ ZynqSLCRState *s = ZYNQ_SLCR(obj);
204
+
205
+ /* will compute output clocks according to ps_clk and registers */
206
+ zynq_slcr_compute_clocks(s);
207
+ zynq_slcr_propagate_clocks(s);
208
+}
209
210
static bool zynq_slcr_check_offset(hwaddr offset, bool rnw)
211
{
212
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
213
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
214
}
215
break;
216
+ case R_IO_PLL_CTRL:
217
+ case R_ARM_PLL_CTRL:
218
+ case R_DDR_PLL_CTRL:
219
+ case R_UART_CLK_CTRL:
220
+ zynq_slcr_compute_clocks(s);
221
+ zynq_slcr_propagate_clocks(s);
222
+ break;
223
}
224
}
225
226
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps slcr_ops = {
227
.endianness = DEVICE_NATIVE_ENDIAN,
228
};
229
230
+static const ClockPortInitArray zynq_slcr_clocks = {
231
+ QDEV_CLOCK_IN(ZynqSLCRState, ps_clk, zynq_slcr_ps_clk_callback),
232
+ QDEV_CLOCK_OUT(ZynqSLCRState, uart0_ref_clk),
233
+ QDEV_CLOCK_OUT(ZynqSLCRState, uart1_ref_clk),
234
+ QDEV_CLOCK_END
235
+};
236
+
237
static void zynq_slcr_init(Object *obj)
238
{
239
ZynqSLCRState *s = ZYNQ_SLCR(obj);
240
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_init(Object *obj)
241
memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr",
242
ZYNQ_SLCR_MMIO_SIZE);
243
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
244
+
245
+ qdev_init_clocks(DEVICE(obj), zynq_slcr_clocks);
246
}
247
248
static const VMStateDescription vmstate_zynq_slcr = {
249
.name = "zynq_slcr",
250
- .version_id = 2,
251
+ .version_id = 3,
252
.minimum_version_id = 2,
253
.fields = (VMStateField[]) {
254
VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS),
255
+ VMSTATE_CLOCK_V(ps_clk, ZynqSLCRState, 3),
256
VMSTATE_END_OF_LIST()
257
}
258
};
259
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_zynq_slcr = {
260
static void zynq_slcr_class_init(ObjectClass *klass, void *data)
261
{
262
DeviceClass *dc = DEVICE_CLASS(klass);
263
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
264
265
dc->vmsd = &vmstate_zynq_slcr;
266
- dc->reset = zynq_slcr_reset;
267
+ rc->phases.enter = zynq_slcr_reset_init;
268
+ rc->phases.hold = zynq_slcr_reset_hold;
269
+ rc->phases.exit = zynq_slcr_reset_exit;
270
}
271
272
static const TypeInfo zynq_slcr_info = {
273
--
274
2.20.1
275
276
diff view generated by jsdifflib
Deleted patch
1
From: Damien Hedde <damien.hedde@greensocs.com>
2
1
3
Switch the cadence uart to multi-phase reset and add the
4
reference clock input.
5
6
The input clock frequency is added to the migration structure.
7
8
The reference clock controls the baudrate generation. If it disabled,
9
any input characters and events are ignored.
10
11
If this clock remains unconnected, the uart behaves as before
12
(it default to a 50MHz ref clock).
13
14
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
15
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
16
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Message-id: 20200406135251.157596-8-damien.hedde@greensocs.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
include/hw/char/cadence_uart.h | 1 +
21
hw/char/cadence_uart.c | 73 +++++++++++++++++++++++++++++-----
22
hw/char/trace-events | 3 ++
23
3 files changed, 67 insertions(+), 10 deletions(-)
24
25
diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h
26
index XXXXXXX..XXXXXXX 100644
27
--- a/include/hw/char/cadence_uart.h
28
+++ b/include/hw/char/cadence_uart.h
29
@@ -XXX,XX +XXX,XX @@ typedef struct {
30
CharBackend chr;
31
qemu_irq irq;
32
QEMUTimer *fifo_trigger_handle;
33
+ Clock *refclk;
34
} CadenceUARTState;
35
36
static inline DeviceState *cadence_uart_create(hwaddr addr,
37
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/char/cadence_uart.c
40
+++ b/hw/char/cadence_uart.c
41
@@ -XXX,XX +XXX,XX @@
42
#include "qemu/module.h"
43
#include "hw/char/cadence_uart.h"
44
#include "hw/irq.h"
45
+#include "hw/qdev-clock.h"
46
+#include "trace.h"
47
48
#ifdef CADENCE_UART_ERR_DEBUG
49
#define DB_PRINT(...) do { \
50
@@ -XXX,XX +XXX,XX @@
51
#define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
52
#define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
53
54
-#define UART_INPUT_CLK 50000000
55
+#define UART_DEFAULT_REF_CLK (50 * 1000 * 1000)
56
57
#define R_CR (0x00/4)
58
#define R_MR (0x04/4)
59
@@ -XXX,XX +XXX,XX @@ static void uart_send_breaks(CadenceUARTState *s)
60
static void uart_parameters_setup(CadenceUARTState *s)
61
{
62
QEMUSerialSetParams ssp;
63
- unsigned int baud_rate, packet_size;
64
+ unsigned int baud_rate, packet_size, input_clk;
65
+ input_clk = clock_get_hz(s->refclk);
66
67
- baud_rate = (s->r[R_MR] & UART_MR_CLKS) ?
68
- UART_INPUT_CLK / 8 : UART_INPUT_CLK;
69
+ baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? input_clk / 8 : input_clk;
70
+ baud_rate /= (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
71
+ trace_cadence_uart_baudrate(baud_rate);
72
+
73
+ ssp.speed = baud_rate;
74
75
- ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
76
packet_size = 1;
77
78
switch (s->r[R_MR] & UART_MR_PAR) {
79
@@ -XXX,XX +XXX,XX @@ static void uart_parameters_setup(CadenceUARTState *s)
80
}
81
82
packet_size += ssp.data_bits + ssp.stop_bits;
83
+ if (ssp.speed == 0) {
84
+ /*
85
+ * Avoid division-by-zero below.
86
+ * TODO: find something better
87
+ */
88
+ ssp.speed = 1;
89
+ }
90
s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size;
91
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
92
}
93
@@ -XXX,XX +XXX,XX @@ static void uart_receive(void *opaque, const uint8_t *buf, int size)
94
CadenceUARTState *s = opaque;
95
uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
96
97
+ /* ignore characters when unclocked or in reset */
98
+ if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
99
+ return;
100
+ }
101
+
102
if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
103
uart_write_rx_fifo(opaque, buf, size);
104
}
105
@@ -XXX,XX +XXX,XX @@ static void uart_event(void *opaque, QEMUChrEvent event)
106
CadenceUARTState *s = opaque;
107
uint8_t buf = '\0';
108
109
+ /* ignore characters when unclocked or in reset */
110
+ if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
111
+ return;
112
+ }
113
+
114
if (event == CHR_EVENT_BREAK) {
115
uart_write_rx_fifo(opaque, &buf, 1);
116
}
117
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps uart_ops = {
118
.endianness = DEVICE_NATIVE_ENDIAN,
119
};
120
121
-static void cadence_uart_reset(DeviceState *dev)
122
+static void cadence_uart_reset_init(Object *obj, ResetType type)
123
{
124
- CadenceUARTState *s = CADENCE_UART(dev);
125
+ CadenceUARTState *s = CADENCE_UART(obj);
126
127
s->r[R_CR] = 0x00000128;
128
s->r[R_IMR] = 0;
129
@@ -XXX,XX +XXX,XX @@ static void cadence_uart_reset(DeviceState *dev)
130
s->r[R_BRGR] = 0x0000028B;
131
s->r[R_BDIV] = 0x0000000F;
132
s->r[R_TTRIG] = 0x00000020;
133
+}
134
+
135
+static void cadence_uart_reset_hold(Object *obj)
136
+{
137
+ CadenceUARTState *s = CADENCE_UART(obj);
138
139
uart_rx_reset(s);
140
uart_tx_reset(s);
141
@@ -XXX,XX +XXX,XX @@ static void cadence_uart_realize(DeviceState *dev, Error **errp)
142
uart_event, NULL, s, NULL, true);
143
}
144
145
+static void cadence_uart_refclk_update(void *opaque)
146
+{
147
+ CadenceUARTState *s = opaque;
148
+
149
+ /* recompute uart's speed on clock change */
150
+ uart_parameters_setup(s);
151
+}
152
+
153
static void cadence_uart_init(Object *obj)
154
{
155
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
156
@@ -XXX,XX +XXX,XX @@ static void cadence_uart_init(Object *obj)
157
sysbus_init_mmio(sbd, &s->iomem);
158
sysbus_init_irq(sbd, &s->irq);
159
160
+ s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk",
161
+ cadence_uart_refclk_update, s);
162
+ /* initialize the frequency in case the clock remains unconnected */
163
+ clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK);
164
+
165
s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
166
}
167
168
+static int cadence_uart_pre_load(void *opaque)
169
+{
170
+ CadenceUARTState *s = opaque;
171
+
172
+ /* the frequency will be overriden if the refclk field is present */
173
+ clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK);
174
+ return 0;
175
+}
176
+
177
static int cadence_uart_post_load(void *opaque, int version_id)
178
{
179
CadenceUARTState *s = opaque;
180
@@ -XXX,XX +XXX,XX @@ static int cadence_uart_post_load(void *opaque, int version_id)
181
182
static const VMStateDescription vmstate_cadence_uart = {
183
.name = "cadence_uart",
184
- .version_id = 2,
185
+ .version_id = 3,
186
.minimum_version_id = 2,
187
+ .pre_load = cadence_uart_pre_load,
188
.post_load = cadence_uart_post_load,
189
.fields = (VMStateField[]) {
190
VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX),
191
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_cadence_uart = {
192
VMSTATE_UINT32(tx_count, CadenceUARTState),
193
VMSTATE_UINT32(rx_wpos, CadenceUARTState),
194
VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
195
+ VMSTATE_CLOCK_V(refclk, CadenceUARTState, 3),
196
VMSTATE_END_OF_LIST()
197
- }
198
+ },
199
};
200
201
static Property cadence_uart_properties[] = {
202
@@ -XXX,XX +XXX,XX @@ static Property cadence_uart_properties[] = {
203
static void cadence_uart_class_init(ObjectClass *klass, void *data)
204
{
205
DeviceClass *dc = DEVICE_CLASS(klass);
206
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
207
208
dc->realize = cadence_uart_realize;
209
dc->vmsd = &vmstate_cadence_uart;
210
- dc->reset = cadence_uart_reset;
211
+ rc->phases.enter = cadence_uart_reset_init;
212
+ rc->phases.hold = cadence_uart_reset_hold;
213
device_class_set_props(dc, cadence_uart_properties);
214
}
215
216
diff --git a/hw/char/trace-events b/hw/char/trace-events
217
index XXXXXXX..XXXXXXX 100644
218
--- a/hw/char/trace-events
219
+++ b/hw/char/trace-events
220
@@ -XXX,XX +XXX,XX @@ exynos_uart_wo_read(uint32_t channel, const char *name, uint32_t reg) "UART%d: T
221
exynos_uart_rxsize(uint32_t channel, uint32_t size) "UART%d: Rx FIFO size: %d"
222
exynos_uart_channel_error(uint32_t channel) "Wrong UART channel number: %d"
223
exynos_uart_rx_timeout(uint32_t channel, uint32_t stat, uint32_t intsp) "UART%d: Rx timeout stat=0x%x intsp=0x%x"
224
+
225
+# hw/char/cadence_uart.c
226
+cadence_uart_baudrate(unsigned baudrate) "baudrate %u"
227
--
228
2.20.1
229
230
diff view generated by jsdifflib
Deleted patch
1
From: Damien Hedde <damien.hedde@greensocs.com>
2
1
3
Add the connection between the slcr's output clocks and the uarts inputs.
4
5
Also add the main board clock 'ps_clk', which is hard-coded to 33.33MHz
6
(the default frequency). This clock is used to feed the slcr's input
7
clock.
8
9
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
12
Message-id: 20200406135251.157596-9-damien.hedde@greensocs.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/arm/xilinx_zynq.c | 57 +++++++++++++++++++++++++++++++++++++-------
16
1 file changed, 49 insertions(+), 8 deletions(-)
17
18
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/xilinx_zynq.c
21
+++ b/hw/arm/xilinx_zynq.c
22
@@ -XXX,XX +XXX,XX @@
23
#include "hw/char/cadence_uart.h"
24
#include "hw/net/cadence_gem.h"
25
#include "hw/cpu/a9mpcore.h"
26
+#include "hw/qdev-clock.h"
27
+#include "sysemu/reset.h"
28
+
29
+#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
30
+#define ZYNQ_MACHINE(obj) \
31
+ OBJECT_CHECK(ZynqMachineState, (obj), TYPE_ZYNQ_MACHINE)
32
+
33
+/* board base frequency: 33.333333 MHz */
34
+#define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3)
35
36
#define NUM_SPI_FLASHES 4
37
#define NUM_QSPI_FLASHES 2
38
@@ -XXX,XX +XXX,XX @@ static const int dma_irqs[8] = {
39
0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
40
0xe5801000 + (addr)
41
42
+typedef struct ZynqMachineState {
43
+ MachineState parent;
44
+ Clock *ps_clk;
45
+} ZynqMachineState;
46
+
47
static void zynq_write_board_setup(ARMCPU *cpu,
48
const struct arm_boot_info *info)
49
{
50
@@ -XXX,XX +XXX,XX @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
51
52
static void zynq_init(MachineState *machine)
53
{
54
+ ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine);
55
ARMCPU *cpu;
56
MemoryRegion *address_space_mem = get_system_memory();
57
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
58
- DeviceState *dev;
59
+ DeviceState *dev, *slcr;
60
SysBusDevice *busdev;
61
qemu_irq pic[64];
62
int n;
63
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
64
1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
65
0);
66
67
- dev = qdev_create(NULL, "xilinx,zynq_slcr");
68
- qdev_init_nofail(dev);
69
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
70
+ /* Create slcr, keep a pointer to connect clocks */
71
+ slcr = qdev_create(NULL, "xilinx,zynq_slcr");
72
+ qdev_init_nofail(slcr);
73
+ sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
74
+
75
+ /* Create the main clock source, and feed slcr with it */
76
+ zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK));
77
+ object_property_add_child(OBJECT(zynq_machine), "ps_clk",
78
+ OBJECT(zynq_machine->ps_clk), &error_abort);
79
+ object_unref(OBJECT(zynq_machine->ps_clk));
80
+ clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
81
+ qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
82
83
dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
84
qdev_prop_set_uint32(dev, "num-cpu", 1);
85
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
86
sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
87
sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);
88
89
- cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
90
- cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));
91
+ dev = cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
92
+ qdev_connect_clock_in(dev, "refclk",
93
+ qdev_get_clock_out(slcr, "uart0_ref_clk"));
94
+ dev = cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));
95
+ qdev_connect_clock_in(dev, "refclk",
96
+ qdev_get_clock_out(slcr, "uart1_ref_clk"));
97
98
sysbus_create_varargs("cadence_ttc", 0xF8001000,
99
pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
100
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
101
arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo);
102
}
103
104
-static void zynq_machine_init(MachineClass *mc)
105
+static void zynq_machine_class_init(ObjectClass *oc, void *data)
106
{
107
+ MachineClass *mc = MACHINE_CLASS(oc);
108
mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
109
mc->init = zynq_init;
110
mc->max_cpus = 1;
111
@@ -XXX,XX +XXX,XX @@ static void zynq_machine_init(MachineClass *mc)
112
mc->default_ram_id = "zynq.ext_ram";
113
}
114
115
-DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)
116
+static const TypeInfo zynq_machine_type = {
117
+ .name = TYPE_ZYNQ_MACHINE,
118
+ .parent = TYPE_MACHINE,
119
+ .class_init = zynq_machine_class_init,
120
+ .instance_size = sizeof(ZynqMachineState),
121
+};
122
+
123
+static void zynq_machine_register_types(void)
124
+{
125
+ type_register_static(&zynq_machine_type);
126
+}
127
+
128
+type_init(zynq_machine_register_types)
129
--
130
2.20.1
131
132
diff view generated by jsdifflib
Deleted patch
1
From: Damien Hedde <damien.hedde@greensocs.com>
2
1
3
This prints the clocks attached to a DeviceState when using
4
"info qtree" monitor command. For every clock, it displays the
5
direction, the name and if the clock is forwarded. For input clock,
6
it displays also the frequency.
7
8
This is based on the original work of Frederic Konrad.
9
10
Here follows a sample of `info qtree` output on xilinx_zynq machine
11
after linux boot with only one uart clocked:
12
> bus: main-system-bus
13
> type System
14
> [...]
15
> dev: cadence_uart, id ""
16
> gpio-out "sysbus-irq" 1
17
> clock-in "refclk" freq_hz=0.000000e+00
18
> chardev = ""
19
> mmio 00000000e0001000/0000000000001000
20
> dev: cadence_uart, id ""
21
> gpio-out "sysbus-irq" 1
22
> clock-in "refclk" freq_hz=1.375661e+07
23
> chardev = "serial0"
24
> mmio 00000000e0000000/0000000000001000
25
> [...]
26
> dev: xilinx,zynq_slcr, id ""
27
> clock-out "uart1_ref_clk" freq_hz=0.000000e+00
28
> clock-out "uart0_ref_clk" freq_hz=1.375661e+07
29
> clock-in "ps_clk" freq_hz=3.333333e+07
30
> mmio 00000000f8000000/0000000000001000
31
32
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
33
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
34
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
35
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
36
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
37
Message-id: 20200406135251.157596-10-damien.hedde@greensocs.com
38
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
39
---
40
qdev-monitor.c | 9 +++++++++
41
1 file changed, 9 insertions(+)
42
43
diff --git a/qdev-monitor.c b/qdev-monitor.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/qdev-monitor.c
46
+++ b/qdev-monitor.c
47
@@ -XXX,XX +XXX,XX @@
48
#include "migration/misc.h"
49
#include "migration/migration.h"
50
#include "qemu/cutils.h"
51
+#include "hw/clock.h"
52
53
/*
54
* Aliases were a bad idea from the start. Let's keep them
55
@@ -XXX,XX +XXX,XX @@ static void qdev_print(Monitor *mon, DeviceState *dev, int indent)
56
ObjectClass *class;
57
BusState *child;
58
NamedGPIOList *ngl;
59
+ NamedClockList *ncl;
60
61
qdev_printf("dev: %s, id \"%s\"\n", object_get_typename(OBJECT(dev)),
62
dev->id ? dev->id : "");
63
@@ -XXX,XX +XXX,XX @@ static void qdev_print(Monitor *mon, DeviceState *dev, int indent)
64
ngl->num_out);
65
}
66
}
67
+ QLIST_FOREACH(ncl, &dev->clocks, node) {
68
+ qdev_printf("clock-%s%s \"%s\" freq_hz=%e\n",
69
+ ncl->output ? "out" : "in",
70
+ ncl->alias ? " (alias)" : "",
71
+ ncl->name,
72
+ CLOCK_PERIOD_TO_HZ(1.0 * clock_get(ncl->clock)));
73
+ }
74
class = object_get_class(OBJECT(dev));
75
do {
76
qdev_print_props(mon, dev, DEVICE_CLASS(class)->props_, indent);
77
--
78
2.20.1
79
80
diff view generated by jsdifflib
1
From: Jerome Forissier <jerome@forissier.org>
1
From: Roman Bolshakov <r.bolshakov@yadro.com>
2
2
3
The /secure-chosen node is currently used only by create_uart(), but
3
ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in macOS 11.0 - Use -[NSWorkspace openURL:] instead.
4
this will change. Therefore move the creation of this node to
4
[-Wdeprecated-declarations]
5
create_fdt().
5
if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
6
^
7
/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSWorkspace.h:350:1: note:
8
'openFile:' has been explicitly marked deprecated here
9
- (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace openURL:] instead.", macos(10.0, 11.0));
10
^
6
11
7
Signed-off-by: Jerome Forissier <jerome@forissier.org>
12
Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
8
Message-id: 20200420121807.8204-2-jerome@forissier.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-id: 20210102150718.47618-1-r.bolshakov@yadro.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
16
---
12
hw/arm/virt.c | 5 ++++-
17
ui/cocoa.m | 5 ++++-
13
1 file changed, 4 insertions(+), 1 deletion(-)
18
1 file changed, 4 insertions(+), 1 deletion(-)
14
19
15
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
20
diff --git a/ui/cocoa.m b/ui/cocoa.m
16
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/virt.c
22
--- a/ui/cocoa.m
18
+++ b/hw/arm/virt.c
23
+++ b/ui/cocoa.m
19
@@ -XXX,XX +XXX,XX @@ static void create_fdt(VirtMachineState *vms)
24
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
20
/* /chosen must exist for load_dtb to fill in necessary properties later */
25
/* Where to look for local files */
21
qemu_fdt_add_subnode(fdt, "/chosen");
26
NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
22
27
NSString *full_file_path;
23
+ if (vms->secure) {
28
+ NSURL *full_file_url;
24
+ qemu_fdt_add_subnode(fdt, "/secure-chosen");
29
25
+ }
30
/* iterate thru the possible paths until the file is found */
26
+
31
int index;
27
/* Clock node, for the benefit of the UART. The kernel device tree
32
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
28
* binding documentation claims the PL011 node clock properties are
33
full_file_path = [full_file_path stringByDeletingLastPathComponent];
29
* optional but in practice if you omit them the kernel refuses to
34
full_file_path = [NSString stringWithFormat: @"%@/%@%@", full_file_path,
30
@@ -XXX,XX +XXX,XX @@ static void create_uart(const VirtMachineState *vms, int uart,
35
path_array[index], filename];
31
qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
36
- if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
32
qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
37
+ full_file_url = [NSURL fileURLWithPath: full_file_path
33
38
+ isDirectory: false];
34
- qemu_fdt_add_subnode(vms->fdt, "/secure-chosen");
39
+ if ([[NSWorkspace sharedWorkspace] openURL: full_file_url] == YES) {
35
qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path",
40
return;
36
nodename);
41
}
37
}
42
}
38
--
43
--
39
2.20.1
44
2.20.1
40
45
41
46
diff view generated by jsdifflib