[v3] RISC-V Spike machine improvements

[PATCH v3 0/3] RISC-V Spike machine improvements

Anup Patel posted 3 patches 4 years ago

Diff against v1 v2
Download series mbox

Test docker-mingw@fedora passed

Test docker-quick@centos7 passed

Test checkpatch passed

Test FreeBSD passed

Test asan failed

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20200427080644.168461-1-anup.patel@wdc.com

Maintainers: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>

hw/riscv/boot.c         | 13 ++++++++-----
hw/riscv/sifive_u.c     |  2 +-
hw/riscv/spike.c        | 26 ++++++++++++++++++++++++--
hw/riscv/virt.c         |  2 +-
include/hw/riscv/boot.h |  6 ++++--
5 files changed, 38 insertions(+), 11 deletions(-)

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[PATCH v3 0/3] RISC-V Spike machine improvements

Posted by Anup Patel 4 years ago

This series improves QEMU Spike machine to:
1. Allow loading OpenBI firmware using -bios option
2. Allow more than one CPUs

Changes since v2:
 - Rebased on QEMU v5.0-rc4

Changes since v1:
 - Rebased on QEMU master (commit 2ac031d171ccd18c973014d9978b4a63f0ad5fb0)

Anup Patel (3):
  hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
  hw/riscv/spike: Allow loading firmware separately using -bios option
  hw/riscv/spike: Allow more than one CPUs

 hw/riscv/boot.c         | 13 ++++++++-----
 hw/riscv/sifive_u.c     |  2 +-
 hw/riscv/spike.c        | 26 ++++++++++++++++++++++++--
 hw/riscv/virt.c         |  2 +-
 include/hw/riscv/boot.h |  6 ++++--
 5 files changed, 38 insertions(+), 11 deletions(-)

-- 
2.25.1

Re: [PATCH v3 0/3] RISC-V Spike machine improvements

Posted by Alistair Francis 4 years ago

On Mon, Apr 27, 2020 at 1:07 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> This series improves QEMU Spike machine to:
> 1. Allow loading OpenBI firmware using -bios option
> 2. Allow more than one CPUs
>
> Changes since v2:
>  - Rebased on QEMU v5.0-rc4
>
> Changes since v1:
>  - Rebased on QEMU master (commit 2ac031d171ccd18c973014d9978b4a63f0ad5fb0)

Applied to the RISC-V tree for 5.1.

Alistair

>
> Anup Patel (3):
>   hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
>   hw/riscv/spike: Allow loading firmware separately using -bios option
>   hw/riscv/spike: Allow more than one CPUs
>
>  hw/riscv/boot.c         | 13 ++++++++-----
>  hw/riscv/sifive_u.c     |  2 +-
>  hw/riscv/spike.c        | 26 ++++++++++++++++++++++++--
>  hw/riscv/virt.c         |  2 +-
>  include/hw/riscv/boot.h |  6 ++++--
>  5 files changed, 38 insertions(+), 11 deletions(-)
>
> --
> 2.25.1
>
>