[v2] target-microblaze: Misc configurability #2

[PATCH v2 0/6] target-microblaze: Misc configurability #2

Edgar E. Iglesias posted 6 patches 4 years ago

Diff against v1
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git fetch https://github.com/patchew-project/qemu tags/patchew/20200420175250.25777-1-edgar.iglesias@gmail.com

Maintainers: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>

target/microblaze/cpu.c       | 24 ++++++++++++++++++++++--
target/microblaze/cpu.h       |  6 ++++++
target/microblaze/op_helper.c |  5 +++--
target/microblaze/translate.c |  8 ++++----
4 files changed, 35 insertions(+), 8 deletions(-)

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[PATCH v2 0/6] target-microblaze: Misc configurability #2

Posted by Edgar E. Iglesias 4 years ago

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

This is another round of conversion from hardcoded regs to
cpu properties.
The property names are taken from the device-tree bindings.

Cheers,
Edgar

ChangeLog:

v1 -> v2:
* Populate the pvr2 div-zero-exception bit

Edgar E. Iglesias (6):
  target/microblaze: Add the opcode-0x0-illegal CPU property
  target/microblaze: Add the ill-opcode-exception property
  target/microblaze: Add the div-zero-exception property
  target/microblaze: Add the unaligned-exceptions property
  target/microblaze: Add the pvr-user1 property
  target/microblaze: Add the pvr-user2 property

 target/microblaze/cpu.c       | 24 ++++++++++++++++++++++--
 target/microblaze/cpu.h       |  6 ++++++
 target/microblaze/op_helper.c |  5 +++--
 target/microblaze/translate.c |  8 ++++----
 4 files changed, 35 insertions(+), 8 deletions(-)

-- 
2.20.1