Wraparound of TX descriptor cyclic buffer only updated
the low 32 bits of the descriptor.
Fix that by checking if we're working with 64bit descriptors.
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
v2: Fix indention problem.
hw/net/cadence_gem.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 51ec5a072d..b7b7985bf2 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1238,7 +1238,14 @@ static void gem_transmit(CadenceGEMState *s)
/* read next descriptor */
if (tx_desc_get_wrap(desc)) {
tx_desc_set_last(desc);
- packet_desc_addr = s->regs[GEM_TXQBASE];
+
+ if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
+ packet_desc_addr = s->regs[GEM_TBQPH];
+ packet_desc_addr <<= 32;
+ } else {
+ packet_desc_addr = 0;
+ }
+ packet_desc_addr |= s->regs[GEM_TXQBASE];
} else {
packet_desc_addr += 4 * gem_get_desc_len(s, false);
}
--
2.26.0